diff --git a/.github/workflows/manual_trigger_scons_except_STM32_all.yml b/.github/workflows/manual_trigger_scons_except_STM32_all.yml index 7658f948c0..f3b4186b64 100644 --- a/.github/workflows/manual_trigger_scons_except_STM32_all.yml +++ b/.github/workflows/manual_trigger_scons_except_STM32_all.yml @@ -126,6 +126,8 @@ jobs: #- {RTT_BSP_NAME: "hk32_hk32f030c8-mini", RTT_TOOL_CHAIN: "sourcery-arm", RTT_BSP: "hk32/hk32f030c8-mini"} #scons dist有问题 - {RTT_BSP_NAME: "hpmicro_hpm6750evk", RTT_TOOL_CHAIN: "sourcery-arm", RTT_BSP: "hpmicro/hpm6750evk"} - {RTT_BSP_NAME: "hpmicro_hpm6750evkmini", RTT_TOOL_CHAIN: "sourcery-arm", RTT_BSP: "hpmicro/hpm6750evkmini"} + - {RTT_BSP_NAME: "ht32f12366", RTT_TOOL_CHAIN: "sourcery-arm", RTT_BSP: "ht32/ht32f12366"} + - {RTT_BSP_NAME: "ht32f52352", RTT_TOOL_CHAIN: "sourcery-arm", RTT_BSP: "ht32/ht32f52352"} #- {RTT_BSP_NAME: "imx_imx6ull-smart", RTT_TOOL_CHAIN: "sourcery-arm", RTT_BSP: "imx/imx6ull-smart"} # toolchain还没支持 - {RTT_BSP_NAME: "imx6sx_cortex-a9", RTT_TOOL_CHAIN: "sourcery-arm", RTT_BSP: "imx6sx/cortex-a9"} - {RTT_BSP_NAME: "imx6ul", RTT_TOOL_CHAIN: "sourcery-arm", RTT_BSP: "imx6ul"} diff --git a/bsp/ht32/ht32f12366/.config b/bsp/ht32/ht32f12366/.config new file mode 100644 index 0000000000..ca3e7e11bd --- /dev/null +++ b/bsp/ht32/ht32f12366/.config @@ -0,0 +1,1095 @@ +# +# Automatically generated file; DO NOT EDIT. +# RT-Thread Configuration +# + +# +# RT-Thread Kernel +# +CONFIG_RT_NAME_MAX=8 +# CONFIG_RT_USING_ARCH_DATA_TYPE is not set +# CONFIG_RT_USING_SMART is not set +# CONFIG_RT_USING_NANO is not set +# CONFIG_RT_USING_AMP is not set +# CONFIG_RT_USING_SMP is not set +CONFIG_RT_CPUS_NR=1 +CONFIG_RT_ALIGN_SIZE=4 +# CONFIG_RT_THREAD_PRIORITY_8 is not set +CONFIG_RT_THREAD_PRIORITY_32=y +# CONFIG_RT_THREAD_PRIORITY_256 is not set +CONFIG_RT_THREAD_PRIORITY_MAX=32 +CONFIG_RT_TICK_PER_SECOND=1000 +CONFIG_RT_USING_OVERFLOW_CHECK=y +CONFIG_RT_USING_HOOK=y +CONFIG_RT_HOOK_USING_FUNC_PTR=y +# CONFIG_RT_USING_HOOKLIST is not set +CONFIG_RT_USING_IDLE_HOOK=y +CONFIG_RT_IDLE_HOOK_LIST_SIZE=4 +CONFIG_IDLE_THREAD_STACK_SIZE=256 +# CONFIG_RT_USING_TIMER_SOFT is not set + +# +# kservice optimization +# +# CONFIG_RT_KSERVICE_USING_STDLIB is not set +# CONFIG_RT_KSERVICE_USING_TINY_SIZE is not set +# CONFIG_RT_USING_TINY_FFS is not set +# CONFIG_RT_KPRINTF_USING_LONGLONG is not set +CONFIG_RT_USING_DEBUG=y +CONFIG_RT_DEBUGING_COLOR=y +CONFIG_RT_DEBUGING_CONTEXT=y +# CONFIG_RT_DEBUGING_AUTO_INIT is not set + +# +# Inter-Thread communication +# +CONFIG_RT_USING_SEMAPHORE=y +CONFIG_RT_USING_MUTEX=y +CONFIG_RT_USING_EVENT=y +CONFIG_RT_USING_MAILBOX=y +CONFIG_RT_USING_MESSAGEQUEUE=y +# CONFIG_RT_USING_MESSAGEQUEUE_PRIORITY is not set +# CONFIG_RT_USING_SIGNALS is not set + +# +# Memory Management +# +CONFIG_RT_USING_MEMPOOL=y +CONFIG_RT_USING_SMALL_MEM=y +# CONFIG_RT_USING_SLAB is not set +CONFIG_RT_USING_MEMHEAP=y +CONFIG_RT_MEMHEAP_FAST_MODE=y +# CONFIG_RT_MEMHEAP_BEST_MODE is not set +CONFIG_RT_USING_SMALL_MEM_AS_HEAP=y +# CONFIG_RT_USING_MEMHEAP_AS_HEAP is not set +# CONFIG_RT_USING_SLAB_AS_HEAP is not set +# CONFIG_RT_USING_USERHEAP is not set +# CONFIG_RT_USING_NOHEAP is not set +# CONFIG_RT_USING_MEMTRACE is not set +# CONFIG_RT_USING_HEAP_ISR is not set +CONFIG_RT_USING_HEAP=y +CONFIG_RT_USING_DEVICE=y +# CONFIG_RT_USING_DEVICE_OPS is not set +# CONFIG_RT_USING_INTERRUPT_INFO is not set +# CONFIG_RT_USING_THREADSAFE_PRINTF is not set +# CONFIG_RT_USING_SCHED_THREAD_CTX is not set +CONFIG_RT_USING_CONSOLE=y +CONFIG_RT_CONSOLEBUF_SIZE=128 +CONFIG_RT_CONSOLE_DEVICE_NAME="usart0" +CONFIG_RT_VER_NUM=0x50100 +# CONFIG_RT_USING_STDC_ATOMIC is not set +CONFIG_RT_BACKTRACE_LEVEL_MAX_NR=32 +# CONFIG_RT_USING_CACHE is not set +CONFIG_RT_USING_HW_ATOMIC=y +# CONFIG_ARCH_ARM_BOOTWITH_FLUSH_CACHE is not set +# CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set +CONFIG_RT_USING_CPU_FFS=y +CONFIG_ARCH_ARM=y +CONFIG_ARCH_ARM_CORTEX_M=y +CONFIG_ARCH_ARM_CORTEX_M3=y + +# +# RT-Thread Components +# +CONFIG_RT_USING_COMPONENTS_INIT=y +CONFIG_RT_USING_USER_MAIN=y +CONFIG_RT_MAIN_THREAD_STACK_SIZE=2048 +CONFIG_RT_MAIN_THREAD_PRIORITY=10 +# CONFIG_RT_USING_LEGACY is not set +CONFIG_RT_USING_MSH=y +CONFIG_RT_USING_FINSH=y +CONFIG_FINSH_USING_MSH=y +CONFIG_FINSH_THREAD_NAME="tshell" +CONFIG_FINSH_THREAD_PRIORITY=20 +CONFIG_FINSH_THREAD_STACK_SIZE=4096 +CONFIG_FINSH_USING_HISTORY=y +CONFIG_FINSH_HISTORY_LINES=5 +CONFIG_FINSH_USING_SYMTAB=y +CONFIG_FINSH_CMD_SIZE=80 +CONFIG_MSH_USING_BUILT_IN_COMMANDS=y +CONFIG_FINSH_USING_DESCRIPTION=y +# CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set +# CONFIG_FINSH_USING_AUTH is not set +CONFIG_FINSH_ARG_MAX=10 +CONFIG_FINSH_USING_OPTION_COMPLETION=y + +# +# DFS: device virtual file system +# +# CONFIG_RT_USING_DFS is not set +# CONFIG_RT_USING_FAL is not set + +# +# Device Drivers +# +# CONFIG_RT_USING_DM is not set +CONFIG_RT_USING_DEVICE_IPC=y +CONFIG_RT_UNAMED_PIPE_NUMBER=64 +# CONFIG_RT_USING_SYSTEM_WORKQUEUE is not set +CONFIG_RT_USING_SERIAL=y +CONFIG_RT_USING_SERIAL_V1=y +# CONFIG_RT_USING_SERIAL_V2 is not set +CONFIG_RT_SERIAL_USING_DMA=y +CONFIG_RT_SERIAL_RB_BUFSZ=64 +# CONFIG_RT_USING_CAN is not set +# CONFIG_RT_USING_CPUTIME is not set +CONFIG_RT_USING_I2C=y +# CONFIG_RT_I2C_DEBUG is not set +CONFIG_RT_USING_I2C_BITOPS=y +# CONFIG_RT_I2C_BITOPS_DEBUG is not set +# CONFIG_RT_USING_SOFT_I2C is not set +# CONFIG_RT_USING_PHY is not set +# CONFIG_RT_USING_ADC is not set +# CONFIG_RT_USING_DAC is not set +# CONFIG_RT_USING_NULL is not set +# CONFIG_RT_USING_ZERO is not set +# CONFIG_RT_USING_RANDOM is not set +# CONFIG_RT_USING_PWM is not set +# CONFIG_RT_USING_MTD_NOR is not set +# CONFIG_RT_USING_MTD_NAND is not set +# CONFIG_RT_USING_PM is not set +# CONFIG_RT_USING_RTC is not set +# CONFIG_RT_USING_SDIO is not set +CONFIG_RT_USING_SPI=y +# CONFIG_RT_USING_SPI_BITOPS is not set +# CONFIG_RT_USING_QSPI is not set +# CONFIG_RT_USING_SPI_MSD is not set +# CONFIG_RT_USING_SFUD is not set +# CONFIG_RT_USING_ENC28J60 is not set +# CONFIG_RT_USING_SPI_WIFI is not set +# CONFIG_RT_USING_WDT is not set +# CONFIG_RT_USING_AUDIO is not set +# CONFIG_RT_USING_SENSOR is not set +# CONFIG_RT_USING_TOUCH is not set +# CONFIG_RT_USING_LCD is not set +# CONFIG_RT_USING_HWCRYPTO is not set +# CONFIG_RT_USING_PULSE_ENCODER is not set +# CONFIG_RT_USING_INPUT_CAPTURE is not set +# CONFIG_RT_USING_DEV_BUS is not set +# CONFIG_RT_USING_WIFI is not set +# CONFIG_RT_USING_VIRTIO is not set +CONFIG_RT_USING_PIN=y +# CONFIG_RT_USING_KTIME is not set +# CONFIG_RT_USING_HWTIMER is not set + +# +# Using USB +# +# CONFIG_RT_USING_USB is not set +# CONFIG_RT_USING_USB_HOST is not set +# CONFIG_RT_USING_USB_DEVICE is not set + +# +# C/C++ and POSIX layer +# + +# +# ISO-ANSI C layer +# + +# +# Timezone and Daylight Saving Time +# +# CONFIG_RT_LIBC_USING_FULL_TZ_DST is not set +CONFIG_RT_LIBC_USING_LIGHT_TZ_DST=y +CONFIG_RT_LIBC_TZ_DEFAULT_HOUR=8 +CONFIG_RT_LIBC_TZ_DEFAULT_MIN=0 +CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 + +# +# POSIX (Portable Operating System Interface) layer +# +# CONFIG_RT_USING_POSIX_FS is not set +# CONFIG_RT_USING_POSIX_DELAY is not set +# CONFIG_RT_USING_POSIX_CLOCK is not set +# CONFIG_RT_USING_POSIX_TIMER is not set +# CONFIG_RT_USING_PTHREADS is not set +# CONFIG_RT_USING_MODULE is not set + +# +# Interprocess Communication (IPC) +# +# CONFIG_RT_USING_POSIX_PIPE is not set +# CONFIG_RT_USING_POSIX_MESSAGE_QUEUE is not set +# CONFIG_RT_USING_POSIX_MESSAGE_SEMAPHORE is not set + +# +# Socket is in the 'Network' category +# +# CONFIG_RT_USING_CPLUSPLUS is not set + +# +# Network +# +# CONFIG_RT_USING_SAL is not set +# CONFIG_RT_USING_NETDEV is not set +# CONFIG_RT_USING_LWIP is not set +# CONFIG_RT_USING_AT is not set + +# +# Memory protection +# +# CONFIG_RT_USING_MEM_PROTECTION is not set +# CONFIG_RT_USING_HW_STACK_GUARD is not set + +# +# Utilities +# +# CONFIG_RT_USING_RYM is not set +# CONFIG_RT_USING_ULOG is not set +# CONFIG_RT_USING_UTEST is not set +# CONFIG_RT_USING_VAR_EXPORT is not set +# CONFIG_RT_USING_RESOURCE_ID is not set +# CONFIG_RT_USING_ADT is not set +# CONFIG_RT_USING_RT_LINK is not set +# CONFIG_RT_USING_VBUS is not set + +# +# RT-Thread Utestcases +# +# CONFIG_RT_USING_UTESTCASES is not set + +# +# RT-Thread online packages +# + +# +# IoT - internet of things +# +# CONFIG_PKG_USING_LWIP is not set +# CONFIG_PKG_USING_LORAWAN_DRIVER is not set +# CONFIG_PKG_USING_PAHOMQTT is not set +# CONFIG_PKG_USING_UMQTT is not set +# CONFIG_PKG_USING_WEBCLIENT is not set +# CONFIG_PKG_USING_WEBNET is not set +# CONFIG_PKG_USING_MONGOOSE is not set +# CONFIG_PKG_USING_MYMQTT is not set +# CONFIG_PKG_USING_KAWAII_MQTT is not set +# CONFIG_PKG_USING_BC28_MQTT is not set +# CONFIG_PKG_USING_WEBTERMINAL is not set +# CONFIG_PKG_USING_FREEMODBUS is not set +# CONFIG_PKG_USING_NANOPB is not set + +# +# Wi-Fi +# + +# +# Marvell WiFi +# +# CONFIG_PKG_USING_WLANMARVELL is not set + +# +# Wiced WiFi +# +# CONFIG_PKG_USING_WLAN_WICED is not set +# CONFIG_PKG_USING_RW007 is not set + +# +# CYW43012 WiFi +# +# CONFIG_PKG_USING_WLAN_CYW43012 is not set + +# +# BL808 WiFi +# +# CONFIG_PKG_USING_WLAN_BL808 is not set + +# +# CYW43439 WiFi +# +# CONFIG_PKG_USING_WLAN_CYW43439 is not set +# CONFIG_PKG_USING_COAP is not set +# CONFIG_PKG_USING_NOPOLL is not set +# CONFIG_PKG_USING_NETUTILS is not set +# CONFIG_PKG_USING_CMUX is not set +# CONFIG_PKG_USING_PPP_DEVICE is not set +# CONFIG_PKG_USING_AT_DEVICE is not set +# CONFIG_PKG_USING_ATSRV_SOCKET is not set +# CONFIG_PKG_USING_WIZNET is not set +# CONFIG_PKG_USING_ZB_COORDINATOR is not set + +# +# IoT Cloud +# +# CONFIG_PKG_USING_ONENET is not set +# CONFIG_PKG_USING_GAGENT_CLOUD is not set +# CONFIG_PKG_USING_ALI_IOTKIT is not set +# CONFIG_PKG_USING_AZURE is not set +# CONFIG_PKG_USING_TENCENT_IOT_EXPLORER is not set +# CONFIG_PKG_USING_JIOT-C-SDK is not set +# CONFIG_PKG_USING_UCLOUD_IOT_SDK is not set +# CONFIG_PKG_USING_JOYLINK is not set +# CONFIG_PKG_USING_IOTSHARP_SDK is not set +# CONFIG_PKG_USING_NIMBLE is not set +# CONFIG_PKG_USING_LLSYNC_SDK_ADAPTER is not set +# CONFIG_PKG_USING_OTA_DOWNLOADER is not set +# CONFIG_PKG_USING_IPMSG is not set +# CONFIG_PKG_USING_LSSDP is not set +# CONFIG_PKG_USING_AIRKISS_OPEN is not set +# CONFIG_PKG_USING_LIBRWS is not set +# CONFIG_PKG_USING_TCPSERVER is not set +# CONFIG_PKG_USING_PROTOBUF_C is not set +# CONFIG_PKG_USING_DLT645 is not set +# CONFIG_PKG_USING_QXWZ is not set +# CONFIG_PKG_USING_SMTP_CLIENT is not set +# CONFIG_PKG_USING_ABUP_FOTA is not set +# CONFIG_PKG_USING_LIBCURL2RTT is not set +# CONFIG_PKG_USING_CAPNP is not set +# CONFIG_PKG_USING_AGILE_TELNET is not set +# CONFIG_PKG_USING_NMEALIB is not set +# CONFIG_PKG_USING_PDULIB is not set +# CONFIG_PKG_USING_BTSTACK is not set +# CONFIG_PKG_USING_BT_CYW43012 is not set +# CONFIG_PKG_USING_CYW43XX is not set +# CONFIG_PKG_USING_LORAWAN_ED_STACK is not set +# CONFIG_PKG_USING_WAYZ_IOTKIT is not set +# CONFIG_PKG_USING_MAVLINK is not set +# CONFIG_PKG_USING_BSAL is not set +# CONFIG_PKG_USING_AGILE_MODBUS is not set +# CONFIG_PKG_USING_AGILE_FTP is not set +# CONFIG_PKG_USING_EMBEDDEDPROTO is not set +# CONFIG_PKG_USING_RT_LINK_HW is not set +# CONFIG_PKG_USING_RYANMQTT is not set +# CONFIG_PKG_USING_RYANW5500 is not set +# CONFIG_PKG_USING_LORA_PKT_FWD is not set +# CONFIG_PKG_USING_LORA_GW_DRIVER_LIB is not set +# CONFIG_PKG_USING_LORA_PKT_SNIFFER is not set +# CONFIG_PKG_USING_HM is not set +# CONFIG_PKG_USING_SMALL_MODBUS is not set +# CONFIG_PKG_USING_NET_SERVER is not set +# CONFIG_PKG_USING_ZFTP is not set +# CONFIG_PKG_USING_WOL is not set +# CONFIG_PKG_USING_ZEPHYR_POLLING is not set +# CONFIG_PKG_USING_MATTER_ADAPTATION_LAYER is not set +# CONFIG_PKG_USING_LHC_MODBUS is not set + +# +# security packages +# +# CONFIG_PKG_USING_MBEDTLS is not set +# CONFIG_PKG_USING_LIBSODIUM is not set +# CONFIG_PKG_USING_LIBHYDROGEN is not set +# CONFIG_PKG_USING_TINYCRYPT is not set +# CONFIG_PKG_USING_TFM is not set +# CONFIG_PKG_USING_YD_CRYPTO is not set + +# +# language packages +# + +# +# JSON: JavaScript Object Notation, a lightweight data-interchange format +# +# CONFIG_PKG_USING_CJSON is not set +# CONFIG_PKG_USING_LJSON is not set +# CONFIG_PKG_USING_RT_CJSON_TOOLS is not set +# CONFIG_PKG_USING_RAPIDJSON is not set +# CONFIG_PKG_USING_JSMN is not set +# CONFIG_PKG_USING_AGILE_JSMN is not set +# CONFIG_PKG_USING_PARSON is not set + +# +# XML: Extensible Markup Language +# +# CONFIG_PKG_USING_SIMPLE_XML is not set +# CONFIG_PKG_USING_EZXML is not set +# CONFIG_PKG_USING_LUATOS_SOC is not set +# CONFIG_PKG_USING_LUA is not set +# CONFIG_PKG_USING_JERRYSCRIPT is not set +# CONFIG_PKG_USING_MICROPYTHON is not set +# CONFIG_PKG_USING_PIKASCRIPT is not set +# CONFIG_PKG_USING_RTT_RUST is not set + +# +# multimedia packages +# + +# +# LVGL: powerful and easy-to-use embedded GUI library +# +# CONFIG_PKG_USING_LVGL is not set +# CONFIG_PKG_USING_LV_MUSIC_DEMO is not set +# CONFIG_PKG_USING_GUI_GUIDER_DEMO is not set + +# +# u8g2: a monochrome graphic library +# +# CONFIG_PKG_USING_U8G2_OFFICIAL is not set +# CONFIG_PKG_USING_U8G2 is not set +# CONFIG_PKG_USING_OPENMV is not set +# CONFIG_PKG_USING_MUPDF is not set +# CONFIG_PKG_USING_STEMWIN is not set +# CONFIG_PKG_USING_WAVPLAYER is not set +# CONFIG_PKG_USING_TJPGD is not set +# CONFIG_PKG_USING_PDFGEN is not set +# CONFIG_PKG_USING_HELIX is not set +# CONFIG_PKG_USING_AZUREGUIX is not set +# CONFIG_PKG_USING_TOUCHGFX2RTT is not set +# CONFIG_PKG_USING_NUEMWIN is not set +# CONFIG_PKG_USING_MP3PLAYER is not set +# CONFIG_PKG_USING_TINYJPEG is not set +# CONFIG_PKG_USING_UGUI is not set +# CONFIG_PKG_USING_MCURSES is not set +# CONFIG_PKG_USING_TERMBOX is not set +# CONFIG_PKG_USING_VT100 is not set +# CONFIG_PKG_USING_QRCODE is not set +# CONFIG_PKG_USING_GUIENGINE is not set +# CONFIG_PKG_USING_3GPP_AMRNB is not set + +# +# tools packages +# +# CONFIG_PKG_USING_CMBACKTRACE is not set +# CONFIG_PKG_USING_EASYFLASH is not set +# CONFIG_PKG_USING_EASYLOGGER is not set +# CONFIG_PKG_USING_SYSTEMVIEW is not set +# CONFIG_PKG_USING_SEGGER_RTT is not set +# CONFIG_PKG_USING_RTT_AUTO_EXE_CMD is not set +# CONFIG_PKG_USING_RDB is not set +# CONFIG_PKG_USING_ULOG_EASYFLASH is not set +# CONFIG_PKG_USING_LOGMGR is not set +# CONFIG_PKG_USING_ADBD is not set +# CONFIG_PKG_USING_COREMARK is not set +# CONFIG_PKG_USING_DHRYSTONE is not set +# CONFIG_PKG_USING_MEMORYPERF is not set +# CONFIG_PKG_USING_NR_MICRO_SHELL is not set +# CONFIG_PKG_USING_CHINESE_FONT_LIBRARY is not set +# CONFIG_PKG_USING_LUNAR_CALENDAR is not set +# CONFIG_PKG_USING_BS8116A is not set +# CONFIG_PKG_USING_GPS_RMC is not set +# CONFIG_PKG_USING_URLENCODE is not set +# CONFIG_PKG_USING_UMCN is not set +# CONFIG_PKG_USING_LWRB2RTT is not set +# CONFIG_PKG_USING_CPU_USAGE is not set +# CONFIG_PKG_USING_GBK2UTF8 is not set +# CONFIG_PKG_USING_VCONSOLE is not set +# CONFIG_PKG_USING_KDB is not set +# CONFIG_PKG_USING_WAMR is not set +# CONFIG_PKG_USING_MICRO_XRCE_DDS_CLIENT is not set +# CONFIG_PKG_USING_LWLOG is not set +# CONFIG_PKG_USING_ANV_TRACE is not set +# CONFIG_PKG_USING_ANV_MEMLEAK is not set +# CONFIG_PKG_USING_ANV_TESTSUIT is not set +# CONFIG_PKG_USING_ANV_BENCH is not set +# CONFIG_PKG_USING_DEVMEM is not set +# CONFIG_PKG_USING_REGEX is not set +# CONFIG_PKG_USING_MEM_SANDBOX is not set +# CONFIG_PKG_USING_SOLAR_TERMS is not set +# CONFIG_PKG_USING_GAN_ZHI is not set +# CONFIG_PKG_USING_FDT is not set +# CONFIG_PKG_USING_CBOX is not set +# CONFIG_PKG_USING_SNOWFLAKE is not set +# CONFIG_PKG_USING_HASH_MATCH is not set +# CONFIG_PKG_USING_ARMV7M_DWT_TOOL is not set +# CONFIG_PKG_USING_VOFA_PLUS is not set +# CONFIG_PKG_USING_RT_TRACE is not set +# CONFIG_PKG_USING_ZDEBUG is not set + +# +# system packages +# + +# +# enhanced kernel services +# +# CONFIG_PKG_USING_RT_MEMCPY_CM is not set +# CONFIG_PKG_USING_RT_KPRINTF_THREADSAFE is not set +# CONFIG_PKG_USING_RT_VSNPRINTF_FULL is not set + +# +# acceleration: Assembly language or algorithmic acceleration packages +# +# CONFIG_PKG_USING_QFPLIB_M0_FULL is not set +# CONFIG_PKG_USING_QFPLIB_M0_TINY is not set +# CONFIG_PKG_USING_QFPLIB_M3 is not set + +# +# CMSIS: ARM Cortex-M Microcontroller Software Interface Standard +# +# CONFIG_PKG_USING_CMSIS_5 is not set +# CONFIG_PKG_USING_CMSIS_CORE is not set +# CONFIG_PKG_USING_CMSIS_DSP is not set +# CONFIG_PKG_USING_CMSIS_NN is not set +# CONFIG_PKG_USING_CMSIS_RTOS1 is not set +# CONFIG_PKG_USING_CMSIS_RTOS2 is not set + +# +# Micrium: Micrium software products porting for RT-Thread +# +# CONFIG_PKG_USING_UCOSIII_WRAPPER is not set +# CONFIG_PKG_USING_UCOSII_WRAPPER is not set +# CONFIG_PKG_USING_UC_CRC is not set +# CONFIG_PKG_USING_UC_CLK is not set +# CONFIG_PKG_USING_UC_COMMON is not set +# CONFIG_PKG_USING_UC_MODBUS is not set +# CONFIG_PKG_USING_FREERTOS_WRAPPER is not set +# CONFIG_PKG_USING_LITEOS_SDK is not set +# CONFIG_PKG_USING_TZ_DATABASE is not set +# CONFIG_PKG_USING_CAIRO is not set +# CONFIG_PKG_USING_PIXMAN is not set +# CONFIG_PKG_USING_PARTITION is not set +# CONFIG_PKG_USING_PERF_COUNTER is not set +# CONFIG_PKG_USING_FILEX is not set +# CONFIG_PKG_USING_LEVELX is not set +# CONFIG_PKG_USING_FLASHDB is not set +# CONFIG_PKG_USING_SQLITE is not set +# CONFIG_PKG_USING_RTI is not set +# CONFIG_PKG_USING_DFS_YAFFS is not set +# CONFIG_PKG_USING_LITTLEFS is not set +# CONFIG_PKG_USING_DFS_JFFS2 is not set +# CONFIG_PKG_USING_DFS_UFFS is not set +# CONFIG_PKG_USING_LWEXT4 is not set +# CONFIG_PKG_USING_THREAD_POOL is not set +# CONFIG_PKG_USING_ROBOTS is not set +# CONFIG_PKG_USING_EV is not set +# CONFIG_PKG_USING_SYSWATCH is not set +# CONFIG_PKG_USING_SYS_LOAD_MONITOR is not set +# CONFIG_PKG_USING_PLCCORE is not set +# CONFIG_PKG_USING_RAMDISK is not set +# CONFIG_PKG_USING_MININI is not set +# CONFIG_PKG_USING_QBOOT is not set +# CONFIG_PKG_USING_PPOOL is not set +# CONFIG_PKG_USING_OPENAMP is not set +# CONFIG_PKG_USING_RPMSG_LITE is not set +# CONFIG_PKG_USING_LPM is not set +# CONFIG_PKG_USING_TLSF is not set +# CONFIG_PKG_USING_EVENT_RECORDER is not set +# CONFIG_PKG_USING_ARM_2D is not set +# CONFIG_PKG_USING_MCUBOOT is not set +# CONFIG_PKG_USING_TINYUSB is not set +# CONFIG_PKG_USING_CHERRYUSB is not set +# CONFIG_PKG_USING_KMULTI_RTIMER is not set +# CONFIG_PKG_USING_TFDB is not set +# CONFIG_PKG_USING_QPC is not set +# CONFIG_PKG_USING_AGILE_UPGRADE is not set +# CONFIG_PKG_USING_FLASH_BLOB is not set +# CONFIG_PKG_USING_MLIBC is not set +# CONFIG_PKG_USING_TASK_MSG_BUS is not set +# CONFIG_PKG_USING_SFDB is not set +# CONFIG_PKG_USING_RTP is not set +# CONFIG_PKG_USING_REB is not set +# CONFIG_PKG_USING_R_RHEALSTONE is not set + +# +# peripheral libraries and drivers +# + +# +# HAL & SDK Drivers +# + +# +# STM32 HAL & SDK Drivers +# +# CONFIG_PKG_USING_STM32L4XX_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32WB55_SDK is not set +# CONFIG_PKG_USING_STM32_SDIO is not set +# CONFIG_PKG_USING_BLUETRUM_SDK is not set +# CONFIG_PKG_USING_EMBARC_BSP is not set +# CONFIG_PKG_USING_ESP_IDF is not set + +# +# Kendryte SDK +# +# CONFIG_PKG_USING_K210_SDK is not set +# CONFIG_PKG_USING_KENDRYTE_SDK is not set +# CONFIG_PKG_USING_NRF5X_SDK is not set +# CONFIG_PKG_USING_NRFX is not set +# CONFIG_PKG_USING_RASPBERRYPI_PICO_SDK is not set + +# +# sensors drivers +# +# CONFIG_PKG_USING_LSM6DSM is not set +# CONFIG_PKG_USING_LSM6DSL is not set +# CONFIG_PKG_USING_LPS22HB is not set +# CONFIG_PKG_USING_HTS221 is not set +# CONFIG_PKG_USING_LSM303AGR is not set +# CONFIG_PKG_USING_BME280 is not set +# CONFIG_PKG_USING_BME680 is not set +# CONFIG_PKG_USING_BMA400 is not set +# CONFIG_PKG_USING_BMI160_BMX160 is not set +# CONFIG_PKG_USING_SPL0601 is not set +# CONFIG_PKG_USING_MS5805 is not set +# CONFIG_PKG_USING_DA270 is not set +# CONFIG_PKG_USING_DF220 is not set +# CONFIG_PKG_USING_HSHCAL001 is not set +# CONFIG_PKG_USING_BH1750 is not set +# CONFIG_PKG_USING_MPU6XXX is not set +# CONFIG_PKG_USING_AHT10 is not set +# CONFIG_PKG_USING_AP3216C is not set +# CONFIG_PKG_USING_TSL4531 is not set +# CONFIG_PKG_USING_DS18B20 is not set +# CONFIG_PKG_USING_DHT11 is not set +# CONFIG_PKG_USING_DHTXX is not set +# CONFIG_PKG_USING_GY271 is not set +# CONFIG_PKG_USING_GP2Y10 is not set +# CONFIG_PKG_USING_SGP30 is not set +# CONFIG_PKG_USING_HDC1000 is not set +# CONFIG_PKG_USING_BMP180 is not set +# CONFIG_PKG_USING_BMP280 is not set +# CONFIG_PKG_USING_SHTC1 is not set +# CONFIG_PKG_USING_BMI088 is not set +# CONFIG_PKG_USING_HMC5883 is not set +# CONFIG_PKG_USING_MAX6675 is not set +# CONFIG_PKG_USING_TMP1075 is not set +# CONFIG_PKG_USING_SR04 is not set +# CONFIG_PKG_USING_CCS811 is not set +# CONFIG_PKG_USING_PMSXX is not set +# CONFIG_PKG_USING_RT3020 is not set +# CONFIG_PKG_USING_MLX90632 is not set +# CONFIG_PKG_USING_MLX90393 is not set +# CONFIG_PKG_USING_MLX90392 is not set +# CONFIG_PKG_USING_MLX90397 is not set +# CONFIG_PKG_USING_MS5611 is not set +# CONFIG_PKG_USING_MAX31865 is not set +# CONFIG_PKG_USING_VL53L0X is not set +# CONFIG_PKG_USING_INA260 is not set +# CONFIG_PKG_USING_MAX30102 is not set +# CONFIG_PKG_USING_INA226 is not set +# CONFIG_PKG_USING_LIS2DH12 is not set +# CONFIG_PKG_USING_HS300X is not set +# CONFIG_PKG_USING_ZMOD4410 is not set +# CONFIG_PKG_USING_ISL29035 is not set +# CONFIG_PKG_USING_MMC3680KJ is not set +# CONFIG_PKG_USING_QMP6989 is not set +# CONFIG_PKG_USING_BALANCE is not set +# CONFIG_PKG_USING_SHT2X is not set +# CONFIG_PKG_USING_SHT3X is not set +# CONFIG_PKG_USING_SHT4X is not set +# CONFIG_PKG_USING_AD7746 is not set +# CONFIG_PKG_USING_ADT74XX is not set +# CONFIG_PKG_USING_MAX17048 is not set +# CONFIG_PKG_USING_AS7341 is not set +# CONFIG_PKG_USING_CW2015 is not set +# CONFIG_PKG_USING_ICM20608 is not set +# CONFIG_PKG_USING_PAJ7620 is not set +# CONFIG_PKG_USING_STHS34PF80 is not set + +# +# touch drivers +# +# CONFIG_PKG_USING_GT9147 is not set +# CONFIG_PKG_USING_GT1151 is not set +# CONFIG_PKG_USING_GT917S is not set +# CONFIG_PKG_USING_GT911 is not set +# CONFIG_PKG_USING_FT6206 is not set +# CONFIG_PKG_USING_FT5426 is not set +# CONFIG_PKG_USING_FT6236 is not set +# CONFIG_PKG_USING_XPT2046_TOUCH is not set +# CONFIG_PKG_USING_CST816X is not set +# CONFIG_PKG_USING_CST812T is not set +# CONFIG_PKG_USING_REALTEK_AMEBA is not set +# CONFIG_PKG_USING_BUTTON is not set +# CONFIG_PKG_USING_PCF8574 is not set +# CONFIG_PKG_USING_SX12XX is not set +# CONFIG_PKG_USING_SIGNAL_LED is not set +# CONFIG_PKG_USING_LEDBLINK is not set +# CONFIG_PKG_USING_LITTLED is not set +# CONFIG_PKG_USING_LKDGUI is not set +# CONFIG_PKG_USING_WM_LIBRARIES is not set +# CONFIG_PKG_USING_INFRARED is not set +# CONFIG_PKG_USING_MULTI_INFRARED is not set +# CONFIG_PKG_USING_AGILE_BUTTON is not set +# CONFIG_PKG_USING_AGILE_LED is not set +# CONFIG_PKG_USING_AT24CXX is not set +# CONFIG_PKG_USING_MOTIONDRIVER2RTT is not set +# CONFIG_PKG_USING_PCA9685 is not set +# CONFIG_PKG_USING_ILI9341 is not set +# CONFIG_PKG_USING_I2C_TOOLS is not set +# CONFIG_PKG_USING_NRF24L01 is not set +# CONFIG_PKG_USING_RPLIDAR is not set +# CONFIG_PKG_USING_AS608 is not set +# CONFIG_PKG_USING_RC522 is not set +# CONFIG_PKG_USING_WS2812B is not set +# CONFIG_PKG_USING_EXTERN_RTC_DRIVERS is not set +# CONFIG_PKG_USING_MULTI_RTIMER is not set +# CONFIG_PKG_USING_MAX7219 is not set +# CONFIG_PKG_USING_BEEP is not set +# CONFIG_PKG_USING_EASYBLINK is not set +# CONFIG_PKG_USING_PMS_SERIES is not set +# CONFIG_PKG_USING_CAN_YMODEM is not set +# CONFIG_PKG_USING_LORA_RADIO_DRIVER is not set +# CONFIG_PKG_USING_QLED is not set +# CONFIG_PKG_USING_AGILE_CONSOLE is not set +# CONFIG_PKG_USING_LD3320 is not set +# CONFIG_PKG_USING_WK2124 is not set +# CONFIG_PKG_USING_LY68L6400 is not set +# CONFIG_PKG_USING_DM9051 is not set +# CONFIG_PKG_USING_SSD1306 is not set +# CONFIG_PKG_USING_QKEY is not set +# CONFIG_PKG_USING_RS485 is not set +# CONFIG_PKG_USING_RS232 is not set +# CONFIG_PKG_USING_NES is not set +# CONFIG_PKG_USING_VIRTUAL_SENSOR is not set +# CONFIG_PKG_USING_VDEVICE is not set +# CONFIG_PKG_USING_SGM706 is not set +# CONFIG_PKG_USING_RDA58XX is not set +# CONFIG_PKG_USING_LIBNFC is not set +# CONFIG_PKG_USING_MFOC is not set +# CONFIG_PKG_USING_TMC51XX is not set +# CONFIG_PKG_USING_TCA9534 is not set +# CONFIG_PKG_USING_KOBUKI is not set +# CONFIG_PKG_USING_ROSSERIAL is not set +# CONFIG_PKG_USING_MICRO_ROS is not set +# CONFIG_PKG_USING_MCP23008 is not set +# CONFIG_PKG_USING_MISAKA_AT24CXX is not set +# CONFIG_PKG_USING_MISAKA_RGB_BLING is not set +# CONFIG_PKG_USING_LORA_MODEM_DRIVER is not set +# CONFIG_PKG_USING_SOFT_SERIAL is not set +# CONFIG_PKG_USING_MB85RS16 is not set +# CONFIG_PKG_USING_RFM300 is not set +# CONFIG_PKG_USING_IO_INPUT_FILTER is not set +# CONFIG_PKG_USING_LRF_NV7LIDAR is not set +# CONFIG_PKG_USING_AIP650 is not set +# CONFIG_PKG_USING_FINGERPRINT is not set +# CONFIG_PKG_USING_BT_ECB02C is not set +# CONFIG_PKG_USING_UAT is not set +# CONFIG_PKG_USING_ST7789 is not set +# CONFIG_PKG_USING_VS1003 is not set +# CONFIG_PKG_USING_X9555 is not set +# CONFIG_PKG_USING_SYSTEM_RUN_LED is not set +# CONFIG_PKG_USING_BT_MX01 is not set +# CONFIG_PKG_USING_RGPOWER is not set +# CONFIG_PKG_USING_SPI_TOOLS is not set + +# +# AI packages +# +# CONFIG_PKG_USING_LIBANN is not set +# CONFIG_PKG_USING_NNOM is not set +# CONFIG_PKG_USING_ONNX_BACKEND is not set +# CONFIG_PKG_USING_ONNX_PARSER is not set +# CONFIG_PKG_USING_TENSORFLOWLITEMICRO is not set +# CONFIG_PKG_USING_ELAPACK is not set +# CONFIG_PKG_USING_ULAPACK is not set +# CONFIG_PKG_USING_QUEST is not set +# CONFIG_PKG_USING_NAXOS is not set +# CONFIG_PKG_USING_R_TINYMAIX is not set + +# +# Signal Processing and Control Algorithm Packages +# +# CONFIG_PKG_USING_FIRE_PID_CURVE is not set +# CONFIG_PKG_USING_QPID is not set +# CONFIG_PKG_USING_UKAL is not set +# CONFIG_PKG_USING_DIGITALCTRL is not set +# CONFIG_PKG_USING_KISSFFT is not set + +# +# miscellaneous packages +# + +# +# project laboratory +# + +# +# samples: kernel and components samples +# +# CONFIG_PKG_USING_KERNEL_SAMPLES is not set +# CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set +# CONFIG_PKG_USING_NETWORK_SAMPLES is not set +# CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set + +# +# entertainment: terminal games and other interesting software packages +# +# CONFIG_PKG_USING_CMATRIX is not set +# CONFIG_PKG_USING_SL is not set +# CONFIG_PKG_USING_CAL is not set +# CONFIG_PKG_USING_ACLOCK is not set +# CONFIG_PKG_USING_THREES is not set +# CONFIG_PKG_USING_2048 is not set +# CONFIG_PKG_USING_SNAKE is not set +# CONFIG_PKG_USING_TETRIS is not set +# CONFIG_PKG_USING_DONUT is not set +# CONFIG_PKG_USING_COWSAY is not set +# CONFIG_PKG_USING_MORSE is not set +# CONFIG_PKG_USING_TINYSQUARE is not set +# CONFIG_PKG_USING_LIBCSV is not set +# CONFIG_PKG_USING_OPTPARSE is not set +# CONFIG_PKG_USING_FASTLZ is not set +# CONFIG_PKG_USING_MINILZO is not set +# CONFIG_PKG_USING_QUICKLZ is not set +# CONFIG_PKG_USING_LZMA is not set +# CONFIG_PKG_USING_RALARAM is not set +# CONFIG_PKG_USING_MULTIBUTTON is not set +# CONFIG_PKG_USING_FLEXIBLE_BUTTON is not set +# CONFIG_PKG_USING_CANFESTIVAL is not set +# CONFIG_PKG_USING_ZLIB is not set +# CONFIG_PKG_USING_MINIZIP is not set +# CONFIG_PKG_USING_HEATSHRINK is not set +# CONFIG_PKG_USING_DSTR is not set +# CONFIG_PKG_USING_TINYFRAME is not set +# CONFIG_PKG_USING_KENDRYTE_DEMO is not set +# CONFIG_PKG_USING_UPACKER is not set +# CONFIG_PKG_USING_UPARAM is not set +# CONFIG_PKG_USING_HELLO is not set +# CONFIG_PKG_USING_VI is not set +# CONFIG_PKG_USING_KI is not set +# CONFIG_PKG_USING_ARMv7M_DWT is not set +# CONFIG_PKG_USING_CRCLIB is not set +# CONFIG_PKG_USING_LWGPS is not set +# CONFIG_PKG_USING_STATE_MACHINE is not set +# CONFIG_PKG_USING_DESIGN_PATTERN is not set +# CONFIG_PKG_USING_CONTROLLER is not set +# CONFIG_PKG_USING_PHASE_LOCKED_LOOP is not set +# CONFIG_PKG_USING_MFBD is not set +# CONFIG_PKG_USING_SLCAN2RTT is not set +# CONFIG_PKG_USING_SOEM is not set +# CONFIG_PKG_USING_QPARAM is not set +# CONFIG_PKG_USING_CorevMCU_CLI is not set + +# +# Arduino libraries +# +# CONFIG_PKG_USING_RTDUINO is not set + +# +# Projects and Demos +# +# CONFIG_PKG_USING_ARDUINO_MSGQ_C_CPP_DEMO is not set +# CONFIG_PKG_USING_ARDUINO_SKETCH_LOADER_DEMO is not set +# CONFIG_PKG_USING_ARDUINO_ULTRASOUND_RADAR is not set +# CONFIG_PKG_USING_ARDUINO_NINEINONE_SENSOR_SHIELD is not set +# CONFIG_PKG_USING_ARDUINO_SENSOR_KIT is not set +# CONFIG_PKG_USING_ARDUINO_MATLAB_SUPPORT is not set + +# +# Sensors +# +# CONFIG_PKG_USING_ARDUINO_SENSOR_DEVICE_DRIVERS is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SENSOR is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SENSORLAB is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL375 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL53L0X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL53L1X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL6180X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX31855 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX31865 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX31856 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX6675 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90614 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM9DS1 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AHTX0 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM9DS0 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP280 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADT7410 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP085 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BME680 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP9808 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP4728 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_INA219 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LTR390 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL345 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DHT is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP9600 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM6DS is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO055 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX1704X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MMC56X3 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90393 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90395 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ICM20X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DPS310 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTS221 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SHT4X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SHT31 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL343 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BME280 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AS726X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AMG88XX is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AM2320 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AM2315 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LTR329_LTR303 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP085_UNIFIED is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP183 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP183_UNIFIED is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP3XX is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MS8607 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS3MDL is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90640 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MMA8451 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MSA301 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPL115A2 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO08X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO08X_RVC is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS2MDL is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM303DLH_MAG is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LC709203F is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_CAP1188 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_CCS811 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_NAU7802 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS331 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LPS2X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LPS35HW is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM303_ACCEL is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS3DH is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCF8591 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPL3115A2 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPR121 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPRLS is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPU6050 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCT2075 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PM25AQI is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_EMC2101 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_FXAS21002C is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SCD30 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_FXOS8700 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HMC5883_UNIFIED is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SGP30 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP006 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TLA202X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TCS34725 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI7021 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI1145 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SGP40 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SHTC3 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HDC1000 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTU21DF is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AS7341 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTU31D is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_INA260 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP007_LIBRARY is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_L3GD20 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP117 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TSC2007 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TSL2561 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TSL2591_LIBRARY is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VCNL4040 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML6070 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML6075 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML7700 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_LIS3DHTR is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_DHT is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_ADXL335 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_ADXL345 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_BME280 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_BMP280 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_H3LIS331DL is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_MMA7660 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_TSL2561 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_PAJ7620 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_VL53L0X is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_ITG3200 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_SHT31 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_HP20X is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_DRV2605L is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_BBM150 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_HMC5883L is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_LSM303DLH is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_TCS3414CS is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_MP503 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_BMP085 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_HIGHTEMP is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_VEML6070 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_SI1145 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_SHT35 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_AT42QT1070 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_LSM6DS3 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_HDC1000 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_HM3301 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_MCP9600 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_LTC2941 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_LDC1612 is not set +# CONFIG_PKG_USING_ARDUINO_CAPACITIVESENSOR is not set +# CONFIG_PKG_USING_ARDUINO_JARZEBSKI_MPU6050 is not set + +# +# Display +# +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_GFX_LIBRARY is not set +# CONFIG_PKG_USING_ARDUINO_U8G2 is not set +# CONFIG_PKG_USING_ARDUINO_TFT_ESPI is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ST7735 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SSD1306 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ILI9341 is not set +# CONFIG_PKG_USING_SEEED_TM1637 is not set + +# +# Timing +# +# CONFIG_PKG_USING_ARDUINO_RTCLIB is not set +# CONFIG_PKG_USING_ARDUINO_MSTIMER2 is not set +# CONFIG_PKG_USING_ARDUINO_TICKER is not set +# CONFIG_PKG_USING_ARDUINO_TASKSCHEDULER is not set + +# +# Data Processing +# +# CONFIG_PKG_USING_ARDUINO_KALMANFILTER is not set +# CONFIG_PKG_USING_ARDUINO_ARDUINOJSON is not set +# CONFIG_PKG_USING_ARDUINO_TENSORFLOW_LITE_MICRO is not set +# CONFIG_PKG_USING_ARDUINO_RUNNINGMEDIAN is not set + +# +# Data Storage +# + +# +# Communication +# +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PN532 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI4713 is not set + +# +# Device Control +# +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCF8574 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCA9685 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TPA2016 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DRV2605 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DS1841 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DS3502 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_PCF85063TP is not set + +# +# Other +# +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MFRC630 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI5351 is not set + +# +# Signal IO +# +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BUSIO is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TCA8418 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP23017 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADS1X15 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AW9523 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP3008 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP4725 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BD3491FS is not set + +# +# Uncategorized +# +CONFIG_SOC_FAMILY_HT32=y +CONFIG_SOC_SERIES_HT32F1=y + +# +# Hardware Drivers Config +# +CONFIG_SOC_HT32F12366=y + +# +# Onboard Peripheral Drivers +# + +# +# On-chip Peripheral Drivers +# +CONFIG_BSP_USING_GPIO=y +CONFIG_BSP_USING_UART=y +CONFIG_BSP_USING_USART0=y +# CONFIG_BSP_USING_USART1 is not set +# CONFIG_BSP_USING_UART0 is not set +# CONFIG_BSP_USING_UART1 is not set +# CONFIG_BSP_USING_SPI is not set +# CONFIG_BSP_USING_I2C is not set + +# +# Board extended module Drivers +# diff --git a/bsp/ht32/ht32f12366/Kconfig b/bsp/ht32/ht32f12366/Kconfig new file mode 100644 index 0000000000..7a400db91f --- /dev/null +++ b/bsp/ht32/ht32f12366/Kconfig @@ -0,0 +1,22 @@ +mainmenu "RT-Thread Configuration" + +config BSP_DIR + string + option env="BSP_ROOT" + default "." + +config RTT_DIR + string + option env="RTT_ROOT" + default "../../.." + +config PKGS_DIR + string + option env="PKGS_ROOT" + default "packages" + +source "$RTT_DIR/Kconfig" +source "$PKGS_DIR/Kconfig" +source "../libraries/Kconfig" +source "board/Kconfig" + diff --git a/bsp/ht32/ht32f12366/README.md b/bsp/ht32/ht32f12366/README.md new file mode 100644 index 0000000000..04de7527d7 --- /dev/null +++ b/bsp/ht32/ht32f12366/README.md @@ -0,0 +1,107 @@ +# HT32F12366 BSP 说明 + +## 简介 + +ESK32-30105是合泰基于HT32F12366芯片并针对Cortex®-M3入门而设计的评估板。本文档是为ESK32-30105开发板提供的BSP(板级支持包)说明。 + +主要内容如下： + +- 开发板资源介绍 +- BSP 快速上手 +- 进阶使用方法 + +通过阅读快速上手章节开发者可以快速地上手该 BSP，将 RT-Thread 运行在开发板上。 + +## 开发板介绍 + +ESK32-30105使用32位ARM® Cortex®-M3高性能、低功耗单片机HT32F12366，针对Cortex®-M3入门而设计。开发板外观如下图所示： + +![board.png](figures/board.png) + +该开发板常用 **板载资源** 如下： + +- MCU：HT32F12366，主频 96MHz，256KB FLASH ，128KB SRAM +- 常用外设 + - LED：2个，（绿色，PE0、PD15） +- 常用接口：USB 转串口 、USB SLAVE +- 调试接口：板载的 e-Link32 Lite SWD 下载 + +开发板更多详细信息请参考合泰官网的相关文档 [ESK32-30105](https://www.holtek.com.cn/page/detail/dev_kit/ESK32-30105)。 + +## 外设支持 + +本 BSP 目前对外设的支持情况如下： + +| **板载外设** | **支持情况** | **备注** | +| :--- | :---: | :--- | +| USB 转串口 | 支持 | 使用 USART0 | +| **片上外设** | **支持情况** | **备注** | +| GPIO | 支持 | PA0, PA1...PE15 ---> PIN: 0, 1...79 | +| USART | 支持 | USART0/1 | +| UART | 支持 | UART0/1 | +| SPI | 支持 | SPI0/1 | +| I2C | 支持 | 硬件 I2C0/1 | +| ADC | 暂不支持 | | +| WDT | 暂不支持 | | + +## 使用说明 + +使用说明分为如下两个章节： + +- 快速上手 + + 本章节是为刚接触 RT-Thread 的新手准备的使用说明，遵循简单的步骤即可将 RT-Thread 操作系统运行在该开发板上，看到实验效果 。 + +- 进阶使用 + + 本章节是为需要在 RT-Thread 操作系统上使用更多开发板资源的开发者准备的。通过使用 ENV 工具对 BSP 进行配置，可以开启更多片上资源，实现更多高级功能。 + +### 快速上手 + +本 BSP 为仅为开发者提供MDK5的工程。下面以 MDK5 开发环境为例，介绍如何将系统运行起来。 + +#### 硬件连接 + +使用数据线通过板载的 e-Link32 Lite将芯片连接到 PC。 + +#### 编译下载 + +双击 project.uvprojx 文件，打开 MDK5 工程，编译并下载程序到开发板。 + +> 注：工程默认配置使用CMSIS-DAP下载方式，在通过 e-Link32 Lite 连接开发板的基础上，点击下载按钮即可下载程序到开发板。 + +#### 运行结果 + +下载程序成功之后，系统会自动运行，观察开发板上 LED 的运行效果，LED1和LED2交替闪烁。 + +连接开发板对应串口到 PC（也可以通过e-Link32 Lite的模拟串口将开发板连接到PC）, 在终端工具里调整好串口配置（115200-8-1-N）并打开相应的串口，复位设备后，可以看到 RT-Thread 的输出信息: + +> 注：由于RT-Thread的finsh控制台使用的是命令行的输入形式，推荐使用串口调试工具如：Tabby terminal 或者 Tera Term。 + +```bash + \ | / +- RT - Thread Operating System + / | \ 5.1.0 build Apr 10 2024 14:39:43 + 2006 - 2024 Copyright by RT-Thread team +msh > +``` + +### 进阶使用 + +此 BSP 默认只开启了 GPIO 和 USART0 的功能，如果需使用更多的片上资源，需要利用 ENV 工具对BSP 进行配置，步骤如下： + +1. 在 bsp 下打开 env 工具。 + +2. 输入`menuconfig`命令配置工程，配置好之后保存退出。 + +3. 输入`scons --target=mdk5` 命令重新生成工程。 + +## 注意事项 + +开发板和芯片的相关资料可以在[合泰官网](https://www.holtek.com.cn/page/index)进行查找和下载，如芯片的数据手册和开发使用手册、开发板的原理图、Keil_v5的pack安装包等。 + +## 联系人信息 + +维护人: + +- [QT-one](https://github.com/QT-one) \ No newline at end of file diff --git a/bsp/ht32/ht32f12366/SConscript b/bsp/ht32/ht32f12366/SConscript new file mode 100644 index 0000000000..682f94215c --- /dev/null +++ b/bsp/ht32/ht32f12366/SConscript @@ -0,0 +1,15 @@ +# for module compiling +import os #包含os库 +Import('RTT_ROOT') #导入RTT_ROOT对象（RTT_ROOT代表的是RT-Thread源码包） +from building import * #把building模块的所有内容都导入到当前模块中 + +cwd = GetCurrentDir() #获取当前路径，并将该路径信息保存到变量cwd中 +objs = [] #创建一个list型变量objs +list = os.listdir(cwd) #得到当前目录下的所有子目录，并保存到变量list中 + +for d in list: #for循环用d记录循环的次数，直到寻遍所有路径 + path = os.path.join(cwd, d) #根据d获取到不同的路径 + if os.path.isfile(os.path.join(path, 'SConscript')): #如果该路径下存在名为SConscript的文件 + objs = objs + SConscript(os.path.join(d, 'SConscript')) #将路径中SConscript文件内的源码读取到objs中 + +Return('objs') #将objs返回出去 diff --git a/bsp/ht32/ht32f12366/SConstruct b/bsp/ht32/ht32f12366/SConstruct new file mode 100644 index 0000000000..5fcd0e3860 --- /dev/null +++ b/bsp/ht32/ht32f12366/SConstruct @@ -0,0 +1,60 @@ +import os +import sys +import rtconfig + +if os.getenv('RTT_ROOT'): + RTT_ROOT = os.getenv('RTT_ROOT') +else: + RTT_ROOT = os.path.normpath(os.getcwd() + '/../../..') + +sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')] +try: + from building import * +except: + print('Cannot found RT-Thread root directory, please check RTT_ROOT') + print(RTT_ROOT) + exit(-1) + +TARGET = 'rt-thread.' + rtconfig.TARGET_EXT + +DefaultEnvironment(tools=[]) +env = Environment(tools = ['mingw'], + AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS, + CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS, + AR = rtconfig.AR, ARFLAGS = '-rc', + CXX = rtconfig.CXX, CXXFLAGS = rtconfig.CXXFLAGS, + LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS) +env.PrependENVPath('PATH', rtconfig.EXEC_PATH) + +if rtconfig.PLATFORM == 'iar': + env.Replace(CCCOM = ['$CC $CCFLAGS $CPPFLAGS $_CPPDEFFLAGS $_CPPINCFLAGS -o $TARGET $SOURCES']) + env.Replace(ARFLAGS = ['']) + env.Replace(LINKCOM = env["LINKCOM"] + ' --map rt-thread.map') + +Export('RTT_ROOT') +Export('rtconfig') + +SDK_ROOT = os.path.abspath('./') + +if os.path.exists(SDK_ROOT + '/libraries'): + libraries_path_prefix = SDK_ROOT + '/libraries' +else: + libraries_path_prefix = os.path.dirname(SDK_ROOT) + '/libraries' + +SDK_LIB = libraries_path_prefix +Export('SDK_LIB') + +# prepare building environment +objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False) + +ht32_library = 'HT32_STD_1xxxx_FWLib' +rtconfig.BSP_LIBRARY_TYPE = ht32_library + +# include libraries +objs.extend(SConscript(os.path.join(libraries_path_prefix, ht32_library, 'SConscript'))) + +# include drivers +objs.extend(SConscript(os.path.join(libraries_path_prefix, 'ht32_drivers', 'SConscript'))) + +# make a building +DoBuilding(TARGET, objs) diff --git a/bsp/ht32/ht32f12366/applications/SConscript b/bsp/ht32/ht32f12366/applications/SConscript new file mode 100644 index 0000000000..9023be657a --- /dev/null +++ b/bsp/ht32/ht32f12366/applications/SConscript @@ -0,0 +1,21 @@ +#导入其他模块的变量 +Import('RTT_ROOT') +Import('rtconfig') + +#导入使用到的模块 +from building import * + +#获取当前目录的路径 +cwd = GetCurrentDir() + +#创建一个列表，用于保存需要使用到的C文件路径 +src = Glob('*c') + +#创建一个列表，用于保存需要包含的H文件路径 +path = [cwd] + +#创建一个组别 +group = DefineGroup('Applications', src, depend = [''], CPPPATH = path) + +#返回创建好的组别 +Return('group') \ No newline at end of file diff --git a/bsp/ht32/ht32f12366/applications/main.c b/bsp/ht32/ht32f12366/applications/main.c new file mode 100644 index 0000000000..6df261c71b --- /dev/null +++ b/bsp/ht32/ht32f12366/applications/main.c @@ -0,0 +1,37 @@ +/* + * Copyright (c) 2006-2024, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2024-04-08 QT-one first version + */ + +#include +#include +#include "board.h" + +/* defined the led2 pin: pd15 */ +#define LED1_PIN GET_PIN(D, 15) +/* defined the led3 pin: pe0 */ +#define LED2_PIN GET_PIN(E, 0) + +int main(void) +{ + rt_uint32_t speed = 200; + /* set led1 pin mode to output */ + rt_pin_mode(LED1_PIN, PIN_MODE_OUTPUT); + /* set led2 pin mode to output */ + rt_pin_mode(LED2_PIN, PIN_MODE_OUTPUT); + + while (1) + { + rt_pin_write(LED1_PIN, PIN_LOW); + rt_pin_write(LED2_PIN, PIN_HIGH); + rt_thread_mdelay(speed); + rt_pin_write(LED1_PIN, PIN_HIGH); + rt_pin_write(LED2_PIN, PIN_LOW); + rt_thread_mdelay(speed); + } +} diff --git a/bsp/ht32/ht32f12366/board/Kconfig b/bsp/ht32/ht32f12366/board/Kconfig new file mode 100644 index 0000000000..3ee604b7be --- /dev/null +++ b/bsp/ht32/ht32f12366/board/Kconfig @@ -0,0 +1,77 @@ +menu "Hardware Drivers Config" + +config SOC_HT32F12366 + bool + select SOC_SERIES_HT32F1 + select RT_USING_COMPONENTS_INIT + select RT_USING_USER_MAIN + default y + +menu "Onboard Peripheral Drivers" + +endmenu + +menu "On-chip Peripheral Drivers" + + config BSP_USING_GPIO + bool "Enable GPIO" + select RT_USING_PIN + default n + +    menuconfig BSP_USING_UART + bool "Enable UART" + default n + select RT_USING_SERIAL + if BSP_USING_UART + config BSP_USING_USART0 + bool "Enable USART0" + default n + + config BSP_USING_USART1 + bool "Enable USART1" + default n + + config BSP_USING_UART0 + bool "Enable UART0" + default n + + config BSP_USING_UART1 + bool "Enable UART1" + default n +        endif + + menuconfig BSP_USING_SPI + bool "Enable SPI Bus" + default n + select RT_USING_SPI + if BSP_USING_SPI + config BSP_USING_SPI0 + bool "Enable SPI0 Bus" + default n + + config BSP_USING_SPI1 + bool "Enable SPI1 Bus" + default n  + endif + + menuconfig BSP_USING_I2C + bool "Enable I2C Bus" + default n + select RT_USING_I2C + if BSP_USING_I2C + config BSP_USING_I2C0 + bool "Enable I2C0 Bus" + default n + + config BSP_USING_I2C1 + bool "Enable I2C1 Bus" + default n + endif + +endmenu + +menu "Board extended module Drivers" + +endmenu + +endmenu diff --git a/bsp/ht32/ht32f12366/board/SConscript b/bsp/ht32/ht32f12366/board/SConscript new file mode 100644 index 0000000000..ba173ea968 --- /dev/null +++ b/bsp/ht32/ht32f12366/board/SConscript @@ -0,0 +1,27 @@ + +import os +import rtconfig +from building import * + +Import('SDK_LIB') + +cwd = GetCurrentDir() + +src = Glob('src/*.c') + +startup_path_prefix = SDK_LIB +if rtconfig.CROSS_TOOL == 'gcc': + src += [startup_path_prefix + '/HT32_STD_1xxxx_FWLib/library/Device/Holtek/HT32F1xxxx/Source/GCC/startup_ht32f1xxxx_gcc_01.s'] +elif rtconfig.CROSS_TOOL == 'keil': + src += [startup_path_prefix + '/HT32_STD_1xxxx_FWLib/library/Device/Holtek/HT32F1xxxx/Source/ARM/startup_ht32f1xxxx_01.s'] +elif rtconfig.CROSS_TOOL == 'iar': + src += [startup_path_prefix + '/HT32_STD_1xxxx_FWLib/library/Device/Holtek/HT32F1xxxx/Source/IAR/startup_ht32f1xxxx_iar_01.s'] + +path = [cwd] +path = [cwd + '/inc'] + +CPPDEFINES = ['USE_HT32F12366_SK, USE_HT32F12365_66, USE_MEM_HT32F12366'] + +group = DefineGroup('Drivers', src, depend = [''], CPPPATH = path, CPPDEFINES = CPPDEFINES) + +Return('group') \ No newline at end of file diff --git a/bsp/ht32/ht32f12366/board/inc/board.h b/bsp/ht32/ht32f12366/board/inc/board.h new file mode 100644 index 0000000000..91d5c2d0a5 --- /dev/null +++ b/bsp/ht32/ht32f12366/board/inc/board.h @@ -0,0 +1,64 @@ +/* + * Copyright (c) 2006-2024, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2024-04-08 QT-one first version + */ + +#ifndef __BOARD_H__ +#define __BOARD_H__ + +#include +#include "ht32.h" +#include "ht32_msp.h" + +#ifdef BSP_USING_GPIO + #include "drv_gpio.h" +#endif + +#ifdef BSP_USING_UART + #include "drv_usart.h" +#endif + +#ifdef BSP_USING_SPI + #include "drv_spi.h" +#endif + +#ifdef BSP_USING_I2C + #include "drv_i2c.h" +#endif + +#ifdef __cplusplus +extern "C" { +#endif + +/* whether use board external SRAM memory */ +#define HT32_EXT_SRAM 0 +#define HT32_EXT_SRAM_BEGIN 0x68000000 +#define HT32_EXT_SRAM_END (HT32_EXT_SRAM_BEGIN + HT32_EXT_SRAM*1024) + +/* internal sram memory size */ +#define HT32_SRAM_END (0x20000000 + LIBCFG_RAM_SIZE) + +#ifdef __CC_ARM +extern int Image$$RW_IRAM1$$ZI$$Limit; +#define HEAP_BEGIN ((void *)&Image$$RW_IRAM1$$ZI$$Limit) +#elif __ICCARM__ +#pragma section="HEAP" +#define HEAP_BEGIN (__segment_end("HEAP")) +#else +extern int __bss_end; +#define HEAP_BEGIN ((void *)&__bss_end) +#endif +#define HEAP_END HT32_SRAM_END + +void rt_hw_board_clock_init(void); + +#ifdef __cplusplus +} +#endif + +#endif /* __BOARD_H__ */ diff --git a/bsp/ht32/ht32f12366/board/inc/ht32_msp.h b/bsp/ht32/ht32f12366/board/inc/ht32_msp.h new file mode 100644 index 0000000000..8d05995146 --- /dev/null +++ b/bsp/ht32/ht32f12366/board/inc/ht32_msp.h @@ -0,0 +1,211 @@ +/* + * Copyright (c) 2006-2024, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2024-04-08 QT-one first version + */ + +#ifndef __HT32_MSP_H__ +#define __HT32_MSP_H__ + +#include +#include "ht32.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* UART gpio */ +#ifdef BSP_USING_UART +#ifdef BSP_USING_USART0 + + #define HTCFG_USART0_IPN USART0 + + #define _HTCFG_USART0_TX_GPIOX A + #define _HTCFG_USART0_TX_GPION 8 + #define _HTCFG_USART0_RX_GPIOX A + #define _HTCFG_USART0_RX_GPION 10 + + #define HTCFG_USART0_TX_GPIO_ID STRCAT2(GPIO_P, _HTCFG_USART0_TX_GPIOX) + #define HTCFG_USART0_TX_GPIO_CLK STRCAT2(P, _HTCFG_USART0_TX_GPIOX) + #define HTCFG_USART0_TX_GPIO_PORT STRCAT2(HT_GPIO, _HTCFG_USART0_TX_GPIOX) + #define HTCFG_USART0_TX_GPIO_PIN STRCAT2(GPIO_PIN_, _HTCFG_USART0_TX_GPION) + + #define HTCFG_USART0_RX_GPIO_ID STRCAT2(GPIO_P, _HTCFG_USART0_RX_GPIOX) + #define HTCFG_USART0_RX_GPIO_CLK STRCAT2(P, _HTCFG_USART0_RX_GPIOX) + #define HTCFG_USART0_RX_GPIO_PORT STRCAT2(HT_GPIO, _HTCFG_USART0_RX_GPIOX) + #define HTCFG_USART0_RX_GPIO_PIN STRCAT2(GPIO_PIN_, _HTCFG_USART0_RX_GPION) + +#endif +#ifdef BSP_USING_USART1 + + #define HTCFG_USART1_IPN USART1 + + #define _HTCFG_USART1_TX_GPIOX A + #define _HTCFG_USART1_TX_GPION 4 + #define _HTCFG_USART1_RX_GPIOX A + #define _HTCFG_USART1_RX_GPION 5 + + #define HTCFG_USART1_TX_GPIO_ID STRCAT2(GPIO_P, _HTCFG_USART1_TX_GPIOX) + #define HTCFG_USART1_TX_GPIO_CLK STRCAT2(P, _HTCFG_USART1_TX_GPIOX) + #define HTCFG_USART1_TX_GPIO_PORT STRCAT2(HT_GPIO, _HTCFG_USART1_TX_GPIOX) + #define HTCFG_USART1_TX_GPIO_PIN STRCAT2(GPIO_PIN_, _HTCFG_USART1_TX_GPION) + + #define HTCFG_USART1_RX_GPIO_ID STRCAT2(GPIO_P, _HTCFG_USART1_RX_GPIOX) + #define HTCFG_USART1_RX_GPIO_CLK STRCAT2(P, _HTCFG_USART1_RX_GPIOX) + #define HTCFG_USART1_RX_GPIO_PORT STRCAT2(HT_GPIO, _HTCFG_USART1_RX_GPIOX) + #define HTCFG_USART1_RX_GPIO_PIN STRCAT2(GPIO_PIN_, _HTCFG_USART1_RX_GPION) + +#endif +#ifdef BSP_USING_UART0 + + #define HTCFG_UART0_IPN UART0 + + #define _HTCFG_UART0_TX_GPIOX C + #define _HTCFG_UART0_TX_GPION 9 + #define _HTCFG_UART0_RX_GPIOX C + #define _HTCFG_UART0_RX_GPION 10 + + #define HTCFG_UART0_TX_GPIO_ID STRCAT2(GPIO_P, _HTCFG_UART0_TX_GPIOX) + #define HTCFG_UART0_TX_GPIO_CLK STRCAT2(P, _HTCFG_UART0_TX_GPIOX) + #define HTCFG_UART0_TX_GPIO_PORT STRCAT2(HT_GPIO, _HTCFG_UART0_TX_GPIOX) + #define HTCFG_UART0_TX_GPIO_PIN STRCAT2(GPIO_PIN_, _HTCFG_UART0_TX_GPION) + + #define HTCFG_UART0_RX_GPIO_ID STRCAT2(GPIO_P, _HTCFG_UART0_RX_GPIOX) + #define HTCFG_UART0_RX_GPIO_CLK STRCAT2(P, _HTCFG_UART0_RX_GPIOX) + #define HTCFG_UART0_RX_GPIO_PORT STRCAT2(HT_GPIO, _HTCFG_UART0_RX_GPIOX) + #define HTCFG_UART0_RX_GPIO_PIN STRCAT2(GPIO_PIN_, _HTCFG_UART0_RX_GPION) + +#endif +#ifdef BSP_USING_UART1 + + #define HTCFG_UART1_IPN UART1 + + #define _HTCFG_UART1_TX_GPIOX C + #define _HTCFG_UART1_TX_GPION 2 + #define _HTCFG_UART1_RX_GPIOX C + #define _HTCFG_UART1_RX_GPION 3 + + #define HTCFG_UART1_TX_GPIO_ID STRCAT2(GPIO_P, _HTCFG_UART1_TX_GPIOX) + #define HTCFG_UART1_TX_GPIO_CLK STRCAT2(P, _HTCFG_UART1_TX_GPIOX) + #define HTCFG_UART1_TX_GPIO_PORT STRCAT2(HT_GPIO, _HTCFG_UART1_TX_GPIOX) + #define HTCFG_UART1_TX_GPIO_PIN STRCAT2(GPIO_PIN_, _HTCFG_UART1_TX_GPION) + + #define HTCFG_UART1_RX_GPIO_ID STRCAT2(GPIO_P, _HTCFG_UART1_RX_GPIOX) + #define HTCFG_UART1_RX_GPIO_CLK STRCAT2(P, _HTCFG_UART1_RX_GPIOX) + #define HTCFG_UART1_RX_GPIO_PORT STRCAT2(HT_GPIO, _HTCFG_UART1_RX_GPIOX) + #define HTCFG_UART1_RX_GPIO_PIN STRCAT2(GPIO_PIN_, _HTCFG_UART1_RX_GPION) + +#endif +#endif + +/* SPI gpio */ +#ifdef BSP_USING_SPI +#ifdef BSP_USING_SPI0 + + #define HTCFG_SPI0_IPN SPI0 + + #define _HTCFG_SPI0_SCK_GPIOX B + #define _HTCFG_SPI0_SCK_GPION 3 + + #define _HTCFG_SPI0_MISO_GPIOX B + #define _HTCFG_SPI0_MISO_GPION 5 + + #define _HTCFG_SPI0_MOSI_GPIOX B + #define _HTCFG_SPI0_MOSI_GPION 4 + + #define HTCFG_SPI0_SCK_GPIO_CLK STRCAT2(P, _HTCFG_SPI0_SCK_GPIOX) + #define HTCFG_SPI0_SCK_GPIO_ID STRCAT2(GPIO_P, _HTCFG_SPI0_SCK_GPIOX) + #define HTCFG_SPI0_SCK_GPIO_PIN STRCAT2(GPIO_PIN_, _HTCFG_SPI0_SCK_GPION) + + #define HTCFG_SPI0_MISO_GPIO_CLK STRCAT2(P, _HTCFG_SPI0_MISO_GPIOX) + #define HTCFG_SPI0_MISO_GPIO_ID STRCAT2(GPIO_P, _HTCFG_SPI0_MISO_GPIOX) + #define HTCFG_SPI0_MISO_GPIO_PIN STRCAT2(GPIO_PIN_, _HTCFG_SPI0_MISO_GPION) + + #define HTCFG_SPI0_MOSI_GPIO_CLK STRCAT2(P, _HTCFG_SPI0_MOSI_GPIOX) + #define HTCFG_SPI0_MOSI_GPIO_ID STRCAT2(GPIO_P, _HTCFG_SPI0_MOSI_GPIOX) + #define HTCFG_SPI0_MOSI_GPIO_PIN STRCAT2(GPIO_PIN_, _HTCFG_SPI0_MOSI_GPION) + +#endif +#ifdef BSP_USING_SPI1 + + #define HTCFG_SPI1_IPN SPI1 + + #define _HTCFG_SPI1_SCK_GPIOX B + #define _HTCFG_SPI1_SCK_GPION 7 + + #define _HTCFG_SPI1_MISO_GPIOX B + #define _HTCFG_SPI1_MISO_GPION 9 + + #define _HTCFG_SPI1_MOSI_GPIOX B + #define _HTCFG_SPI1_MOSI_GPION 8 + + #define HTCFG_SPI1_SCK_GPIO_CLK STRCAT2(P, _HTCFG_SPI1_SCK_GPIOX) + #define HTCFG_SPI1_SCK_GPIO_ID STRCAT2(GPIO_P, _HTCFG_SPI1_SCK_GPIOX) + #define HTCFG_SPI1_SCK_GPIO_PIN STRCAT2(GPIO_PIN_, _HTCFG_SPI1_SCK_GPION) + + #define HTCFG_SPI1_MISO_GPIO_CLK STRCAT2(P, _HTCFG_SPI1_MISO_GPIOX) + #define HTCFG_SPI1_MISO_GPIO_ID STRCAT2(GPIO_P, _HTCFG_SPI1_MISO_GPIOX) + #define HTCFG_SPI1_MISO_GPIO_PIN STRCAT2(GPIO_PIN_, _HTCFG_SPI1_MISO_GPION) + + #define HTCFG_SPI1_MOSI_GPIO_CLK STRCAT2(P, _HTCFG_SPI1_MOSI_GPIOX) + #define HTCFG_SPI1_MOSI_GPIO_ID STRCAT2(GPIO_P, _HTCFG_SPI1_MOSI_GPIOX) + #define HTCFG_SPI1_MOSI_GPIO_PIN STRCAT2(GPIO_PIN_, _HTCFG_SPI1_MOSI_GPION) + +#endif +#endif + +/* I2C gpio */ +#ifdef BSP_USING_I2C +#ifdef BSP_USING_I2C0 + + #define HTCFG_I2C0_IPN I2C0 + + #define _HTCFG_I2C0_SCL_GPIOX B + #define _HTCFG_I2C0_SCL_GPION 12 + + #define _HTCFG_I2C0_SDA_GPIOX B + #define _HTCFG_I2C0_SDA_GPION 13 + + #define HTCFG_I2C0_SCL_GPIO_CLK STRCAT2(P, _HTCFG_I2C0_SCL_GPIOX) + #define HTCFG_I2C0_SCL_GPIO_ID STRCAT2(GPIO_P, _HTCFG_I2C0_SCL_GPIOX) + #define HTCFG_I2C0_SCL_GPIO_PIN STRCAT2(GPIO_PIN_, _HTCFG_I2C0_SCL_GPION) + + #define HTCFG_I2C0_SDA_GPIO_CLK STRCAT2(P, _HTCFG_I2C0_SDA_GPIOX) + #define HTCFG_I2C0_SDA_GPIO_ID STRCAT2(GPIO_P, _HTCFG_I2C0_SDA_GPIOX) + #define HTCFG_I2C0_SDA_GPIO_PIN STRCAT2(GPIO_PIN_, _HTCFG_I2C0_SDA_GPION) + +#endif +#ifdef BSP_USING_I2C1 + + #define HTCFG_I2C1_IPN I2C1 + + #define _HTCFG_I2C1_SCL_GPIOX A + #define _HTCFG_I2C1_SCL_GPION 0 + + #define _HTCFG_I2C1_SDA_GPIOX A + #define _HTCFG_I2C1_SDA_GPION 1 + + #define HTCFG_I2C1_SCL_GPIO_CLK STRCAT2(P, _HTCFG_I2C1_SCL_GPIOX) + #define HTCFG_I2C1_SCL_GPIO_ID STRCAT2(GPIO_P, _HTCFG_I2C1_SCL_GPIOX) + #define HTCFG_I2C1_SCL_GPIO_PIN STRCAT2(GPIO_PIN_, _HTCFG_I2C1_SCL_GPION) + + #define HTCFG_I2C1_SDA_GPIO_CLK STRCAT2(P, _HTCFG_I2C1_SDA_GPIOX) + #define HTCFG_I2C1_SDA_GPIO_ID STRCAT2(GPIO_P, _HTCFG_I2C1_SDA_GPIOX) + #define HTCFG_I2C1_SDA_GPIO_PIN STRCAT2(GPIO_PIN_, _HTCFG_I2C1_SDA_GPION) + +#endif +#endif + +void ht32_usart_gpio_init(void *instance); +void ht32_spi_gpio_init(void *instance); +void ht32_i2c_gpio_init(void *instance); + +#ifdef __cplusplus +} +#endif + +#endif /* __HT32_MSP_H__ */ diff --git a/bsp/ht32/ht32f12366/board/inc/ht32f1xxxx_01_usbdconf.h b/bsp/ht32/ht32f12366/board/inc/ht32f1xxxx_01_usbdconf.h new file mode 100644 index 0000000000..432b323d7a --- /dev/null +++ b/bsp/ht32/ht32f12366/board/inc/ht32f1xxxx_01_usbdconf.h @@ -0,0 +1,453 @@ +/*********************************************************************************************************//** + * @file IP/Example/ht32f1xxxx_01_usbdconf.h + * @version $Rev:: 1090 $ + * @date $Date:: 2018-01-29 #$ + * @brief The configuration file of USB Device Driver. + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ +// <<< Use Configuration Wizard in Context Menu >>> + +/* Define to prevent recursive inclusion -------------------------------------------------------------------*/ +#ifndef __HT32F1XXXX_01_USBDCONF_H +#define __HT32F1XXXX_01_USBDCONF_H + +// Enter Low Power mode when Suspended +#define USBDCORE_ENABLE_LOW_POWER (0) +// + +#if (USBDCORE_ENABLE_LOW_POWER == 1) + #define USBDCore_LowPower() PWRCU_DeepSleep1(PWRCU_SLEEP_ENTRY_WFE) +#else + #define USBDCore_LowPower(...) +#endif + +/*----------------------------------------------------------------------------------------------------------*/ +/* USB Interrupt Enable */ +/*----------------------------------------------------------------------------------------------------------*/ +// USB Interrupt Setting (UIER) +// USB Global Interrupt Enable (UGIE) (Default) +// Start Of Frame Interrupt Enable (SOFIE) +// USB Reset Interrupt Enable (URSTIE) (Default) +// Resume Interrupt Enable (RSMIE) (Default) +// Suspend Interrupt Enable (SUSPIE) (Default) +// Expected Start of Frame Interrupt Enable (ESOFE) +// Control Endpoint Interrupt Enable (EP0IE) (Default) +// Endpoint1 Interrupt Enable (EP1IE) +// Endpoint2 Interrupt Enable (EP2IE) +// Endpoint3 Interrupt Enable (EP3IE) +// Endpoint4 Interrupt Enable (EP4IE) +// Endpoint5 Interrupt Enable (EP5IE) +// Endpoint6 Interrupt Enable (EP6IE) +// Endpoint7 Interrupt Enable (EP7IE) +#define _UIER (0x011D) +// + + +/*----------------------------------------------------------------------------------------------------------*/ +/* Endpoint0 Configuration Setting */ +/*----------------------------------------------------------------------------------------------------------*/ +// Control Endpoint0 Configuration +// Endpoint Buffer Length (EPLEN) +// <8=> 8 bytes +// <16=> 16 bytes +// <32=> 32 bytes +// <64=> 64 bytes + /* Maximum: 64 Bytes */ +#define _EP0LEN (64) + + +// Control Endpoint0 Interrupt Enable Settings (EP0IER) +// OUT Token Packet Received Interrupt Enable (OTRXIE) +// OUT Data Packet Received Interrupt Enable (ODRXIE) (Default) +// OUT Data Buffer Overrun Interrupt Enable (ODOVIE) +// IN Token Packet Received Interrupt Enable (ITRXIE) +// IN Data Packet Transmitted Interrupt Enable (IDTXIE) (Default) +// NAK Transmitted Interrupt Enable (NAKIE) +// STALL Transmitted Interrupt Enable (STLIE) +// USB Error Interrupt Enable (UERIE) +// SETUP Token Packet Received Interrupt Enable (STRXIE) +// SETUP Data Packet Received Interrupt Enable (SDRXIE) (Default) +// SETUP Data Error Interrupt Enable (SDERIE) +// Zero Length Data Packet Received Interrupt Enable (ZLRXIE) +#define _EP0_IER (0x212) +// +// + +/*----------------------------------------------------------------------------------------------------------*/ +/* Endpoint1 Configuration Setting */ +/*----------------------------------------------------------------------------------------------------------*/ +// Endpoint1 Configuration +#define _EP1_ENABLE (0) + +// Endpoint Address (EPADR) +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 +#define _EP1_CFG_EPADR (1) + +// Endpoint Enable (EPEN) +#define _EP1_CFG_EPEN_TMP (1) + +// Endpoint Transfer Type +// <2=> Bulk +// <3=> Interrupt +#define _EP1_TYPR (3) + +// Endpoint Direction (EPDIR) +// <1=> IN +// <0=> OUT +#define _EP1_CFG_EPDIR (1) + +// Endpoint Buffer Length (EPLEN) (in byte) <4-64:4> + /* Maximum: 64 Bytes */ +#define _EP1LEN_TMP (8) + +// Endpoint Interrupt Enable Settings (EPIER) +// Endpoint Interrupt Enable Settings (EPIER) <0x0-0xFF:1> +// OUT Token Packet Received Interrupt Enable (OTRXIE) +// OUT Data Packet Received Interrupt Enable (ODRXIE) +// OUT Data Buffer Overrun Interrupt Enable (ODOVIE) +// IN Token Packet Received Interrupt Enable (ITRXIE) +// IN Data Packet Transmitted Interrupt Enable (IDTXIE) +// NAK Transmitted Interrupt Enable (NAKIE) +// STALL Transmitted Interrupt Enable (STLIE) +// USB Error Interrupt Enable (UERIE) +#define _EP1_IER (0x10) +// +// + + +/*----------------------------------------------------------------------------------------------------------*/ +/* Endpoint2 Configuration Setting */ +/*----------------------------------------------------------------------------------------------------------*/ +// Endpoint2 Configuration +#define _EP2_ENABLE (0) + +// Endpoint Address (EPADR) +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 +#define _EP2_CFG_EPADR (2) + +// Endpoint Enable (EPEN) +#define _EP2_CFG_EPEN_TMP (1) + +// Endpoint Transfer Type +// <2=> Bulk +// <3=> Interrupt +#define _EP2_TYPR (3) + +// Endpoint Direction (EPDIR) +// <1=> IN +// <0=> OUT +#define _EP2_CFG_EPDIR (0) + +// Endpoint Buffer Length (EPLEN) (in byte) <4-64:4> + /* Maximum: 64 Bytes */ +#define _EP2LEN_TMP (8) + +// Endpoint Interrupt Enable Settings (EPIER) +// Endpoint Interrupt Enable Settings (EPIER) <0x0-0xFF:1> +// OUT Token Packet Received Interrupt Enable (OTRXIE) +// OUT Data Packet Received Interrupt Enable (ODRXIE) +// OUT Data Buffer Overrun Interrupt Enable (ODOVIE) +// IN Token Packet Received Interrupt Enable (ITRXIE) +// IN Data Packet Transmitted Interrupt Enable (IDTXIE) +// NAK Transmitted Interrupt Enable (NAKIE) +// STALL Transmitted Interrupt Enable (STLIE) +// USB Error Interrupt Enable (UERIE) +#define _EP2_IER (0x002) +// +// + +/*----------------------------------------------------------------------------------------------------------*/ +/* Endpoint3 Configuration Setting */ +/*----------------------------------------------------------------------------------------------------------*/ +// Endpoint3 Configuration +#define _EP3_ENABLE (0) + +// Endpoint Address (EPADR) +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 +#define _EP3_CFG_EPADR (3) + +// Endpoint Enable (EPEN) +#define _EP3_CFG_EPEN_TMP (1) + +// Endpoint Transfer Type +// <2=> Bulk +// <3=> Interrupt +#define _EP3_TYPR (3) + +// Endpoint Direction (EPDIR) +// <1=> IN +// <0=> OUT +#define _EP3_CFG_EPDIR (1) + +// Endpoint Buffer Length (EPLEN) (in byte) <4-64:4> + /* Maximum: 64 Bytes */ +#define _EP3LEN_TMP (8) + +// Endpoint Interrupt Enable Settings (EPIER) +// Endpoint Interrupt Enable Settings (EPIER) <0x0-0xFF:1> +// OUT Token Packet Received Interrupt Enable (OTRXIE) +// OUT Data Packet Received Interrupt Enable (ODRXIE) +// OUT Data Buffer Overrun Interrupt Enable (ODOVIE) +// IN Token Packet Received Interrupt Enable (ITRXIE) +// IN Data Packet Transmitted Interrupt Enable (IDTXIE) +// NAK Transmitted Interrupt Enable (NAKIE) +// STALL Transmitted Interrupt Enable (STLIE) +// USB Error Interrupt Enable (UERIE) +#define _EP3_IER (0x10) +// +// + +/*----------------------------------------------------------------------------------------------------------*/ +/* Endpoint4 Configuration Setting */ +/*----------------------------------------------------------------------------------------------------------*/ +// Endpoint4 Configuration +#define _EP4_ENABLE (0) + +// Endpoint Address (EPADR) +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 +#define _EP4_CFG_EPADR (4) + +// Endpoint Enable (EPEN) +#define _EP4_CFG_EPEN_TMP (1) + +// Endpoint Transfer Type +// <1=> Isochronous +// <2=> Bulk +// <3=> Interrupt +#define _EP4_TYPR (3) + +// Endpoint Direction (EPDIR) +// <1=> IN +// <0=> OUT +#define _EP4_CFG_EPDIR (0) + +// Endpoint Buffer Length (EPLEN) (in byte) <4-1000:4> + /* Maximum: 1000 Bytes */ +#define _EP4LEN_TMP (8) + +// Single/Double Buffer Selection (SDBS) +// <0=> Single Buffer +// <1=> Double Buffer +#define _EP4_CFG_SDBS (0) + +// Endpoint Interrupt Enable Settings (EPIER) +// Endpoint Interrupt Enable Settings (EPIER) <0x0-0xFF:1> +// OUT Token Packet Received Interrupt Enable (OTRXIE) +// OUT Data Packet Received Interrupt Enable (ODRXIE) +// OUT Data Buffer Overrun Interrupt Enable (ODOVIE) +// IN Token Packet Received Interrupt Enable (ITRXIE) +// IN Data Packet Transmitted Interrupt Enable (IDTXIE) +// NAK Transmitted Interrupt Enable (NAKIE) +// STALL Transmitted Interrupt Enable (STLIE) +// USB Error Interrupt Enable (UERIE) +#define _EP4_IER (0x02) +// +// + + +/*----------------------------------------------------------------------------------------------------------*/ +/* Endpoint5 Configuration Setting */ +/*----------------------------------------------------------------------------------------------------------*/ +// Endpoint5 Configuration +#define _EP5_ENABLE (0) + +// Endpoint Address (EPADR) +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 +#define _EP5_CFG_EPADR (5) + +// Endpoint Enable (EPEN) +#define _EP5_CFG_EPEN_TMP (1) + +// Endpoint Transfer Type +// <1=> Isochronous +// <2=> Bulk +// <3=> Interrupt +#define _EP5_TYPR (3) + +// Endpoint Direction (EPDIR) +// <1=> IN +// <0=> OUT +#define _EP5_CFG_EPDIR (1) + +// Endpoint Buffer Length (EPLEN) (in byte) <4-1000:4> + /* Maximum: 1000 Bytes */ +#define _EP5LEN_TMP (8) + + +// Single/Double Buffer Selection (SDBS) +// <0=> Single Buffer +// <1=> Double Buffer +#define _EP5_CFG_SDBS (0) + +// Endpoint Interrupt Enable Settings (EPIER) +// Endpoint Interrupt Enable Settings (EPIER) <0x0-0xFF:1> +// OUT Token Packet Received Interrupt Enable (OTRXIE) +// OUT Data Packet Received Interrupt Enable (ODRXIE) +// OUT Data Buffer Overrun Interrupt Enable (ODOVIE) +// IN Token Packet Received Interrupt Enable (ITRXIE) +// IN Data Packet Transmitted Interrupt Enable (IDTXIE) +// NAK Transmitted Interrupt Enable (NAKIE) +// STALL Transmitted Interrupt Enable (STLIE) +// USB Error Interrupt Enable (UERIE) +#define _EP5_IER (0x10) +// +// + + +/*----------------------------------------------------------------------------------------------------------*/ +/* Endpoint6 Configuration Setting */ +/*----------------------------------------------------------------------------------------------------------*/ +// Endpoint6 Configuration +#define _EP6_ENABLE (0) + +// Endpoint Address (EPADR) +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 +#define _EP6_CFG_EPADR (6) + +// Endpoint Enable (EPEN) +#define _EP6_CFG_EPEN_TMP (1) + +// Endpoint Transfer Type +// <1=> Isochronous +// <2=> Bulk +// <3=> Interrupt +#define _EP6_TYPR (3) + +// Endpoint Direction (EPDIR) +// <1=> IN +// <0=> OUT +#define _EP6_CFG_EPDIR (0) + +// Endpoint Buffer Length (EPLEN) (in byte) <4-1000:4> + /* Maximum: 1000 Bytes */ +#define _EP6LEN_TMP (8) + +// Single/Double Buffer Selection (SDBS) +// <0=> Single Buffer +// <1=> Double Buffer +#define _EP6_CFG_SDBS (0) + +// Endpoint Interrupt Enable Settings (EPIER) +// Endpoint Interrupt Enable Settings (EPIER) <0x0-0xFF:1> +// OUT Token Packet Received Interrupt Enable (OTRXIE) +// OUT Data Packet Received Interrupt Enable (ODRXIE) +// OUT Data Buffer Overrun Interrupt Enable (ODOVIE) +// IN Token Packet Received Interrupt Enable (ITRXIE) +// IN Data Packet Transmitted Interrupt Enable (IDTXIE) +// NAK Transmitted Interrupt Enable (NAKIE) +// STALL Transmitted Interrupt Enable (STLIE) +// USB Error Interrupt Enable (UERIE) +#define _EP6_IER (0x02) +// +// + + +/*----------------------------------------------------------------------------------------------------------*/ +/* Endpoint7 Configuration Setting */ +/*----------------------------------------------------------------------------------------------------------*/ +// Endpoint7 Configuration +#define _EP7_ENABLE (0) + +// Endpoint Address (EPADR) +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 +#define _EP7_CFG_EPADR (7) + +// Endpoint Enable (EPEN) +#define _EP7_CFG_EPEN_TMP (1) + +// Endpoint Transfer Type +// <1=> Isochronous +// <2=> Bulk +// <3=> Interrupt +#define _EP7_TYPR (3) + +// Endpoint Direction (EPDIR) +// <1=> IN +// <0=> OUT +#define _EP7_CFG_EPDIR (1) + +// Endpoint Buffer Length (EPLEN) (in byte) <4-1000:4> + /* Maximum: 1000 Bytes */ +#define _EP7LEN_TMP (8) + +// Single/Double Buffer Selection (SDBS) +// <0=> Single Buffer +// <1=> Double Buffer +#define _EP7_CFG_SDBS (0) + +// Endpoint Interrupt Enable Settings (EPIER) +// Endpoint Interrupt Enable Settings (EPIER) <0x0-0xFF:1> +// OUT Token Packet Received Interrupt Enable (OTRXIE) +// OUT Data Packet Received Interrupt Enable (ODRXIE) +// OUT Data Buffer Overrun Interrupt Enable (ODOVIE) +// IN Token Packet Received Interrupt Enable (ITRXIE) +// IN Data Packet Transmitted Interrupt Enable (IDTXIE) +// NAK Transmitted Interrupt Enable (NAKIE) +// STALL Transmitted Interrupt Enable (STLIE) +// USB Error Interrupt Enable (UERIE) +#define _EP7_IER (0x10) +// +// + +#endif diff --git a/bsp/ht32/ht32f12366/board/inc/ht32f1xxxx_conf.h b/bsp/ht32/ht32f12366/board/inc/ht32f1xxxx_conf.h new file mode 100644 index 0000000000..1128790b11 --- /dev/null +++ b/bsp/ht32/ht32f12366/board/inc/ht32f1xxxx_conf.h @@ -0,0 +1,490 @@ +/*********************************************************************************************************//** + * @file IP/Example/ht32f1xxxx_conf.h + * @version $Rev:: 2922 $ + * @date $Date:: 2023-06-07 #$ + * @brief Library configuration file. + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ +//-------- <<< Use Configuration Wizard in Context Menu >>> ----------------- + +/* Define to prevent recursive inclusion -------------------------------------------------------------------*/ +#ifndef __HT32F1XXXX_CONF_H +#define __HT32F1XXXX_CONF_H + +/* Exported constants --------------------------------------------------------------------------------------*/ + +#define RETARGET_ITM 0 +#define RETARGET_USB 1 +#define RETARGET_SYSLOG 2 +#define RETARGET_COM1 10 +#define RETARGET_COM2 11 +#define RETARGET_USART0 12 +#define RETARGET_USART1 13 +#define RETARGET_UART0 14 +#define RETARGET_UART1 15 + + +/* Retarget settings of the C standard I/O library functions (printf, scanf, getchar, ...etc.) */ +/* +// Enable Retarget +// Retarget Port +// <0=> ITM +// <1=> USB Virtual COM +// <2=> Syslog +// <10=> COM1 +// <11=> COM2 +// <12=> USART0 +// <13=> USART1 +// <14=> UART0 +// <15=> UART1 +// Enable Auto Return +// Auto Return function adds "\r" before "\n" automatically when print message by Retarget. +*/ +#define _RETARGET 1 +#define RETARGET_PORT 10 +#define _AUTO_RETURN 0 + +#ifndef AUTO_RETURN +#if (_AUTO_RETURN == 1) +#define AUTO_RETURN +#endif +#endif + +/* Enable Interrupt Mode for UxART Retarget +// Retarget COM/UxART Setting +// UxART Baudrate +// Enable Interrupt Mode for UxART Tx Retarget +// Define UxARTn_IRQHandler By Retarget (ht32_serial.c) +// Disable (RETARGET_DEFINE_HANDLER = 0) if application already have UxARTn_IRQHandler. +// RETARGET_UART_IRQHandler() shall be called by UxARTn_IRQHandler when disable. +// Tx Buffer Length (in byte) +// +*/ +#define RETARGET_UxART_BAUDRATE 115200 +#define RETARGET_INT_MODE 0 +#define RETARGET_DEFINE_HANDLER 1 +#define RETARGET_INT_BUFFER_SIZE 64 + +#if (_RETARGET == 1) +#if (RETARGET_PORT == RETARGET_ITM) +#elif (RETARGET_PORT == RETARGET_USB) + #define RETARGET_IS_USB +// Retarget USB Virtual COM Setting +// Communication (Interrupt IN) +// <1=> Endpoint 1 +// <2=> Endpoint 2 +// <3=> Endpoint 3 +// <4=> Endpoint 4 +// <5=> Endpoint 5 +// <6=> Endpoint 6 +// <7=> Endpoint 7 +// Data Rx (Bulk OUT) +// <1=> Endpoint 1 +// <2=> Endpoint 2 +// <3=> Endpoint 3 +// <4=> Endpoint 4 +// <5=> Endpoint 5 +// <6=> Endpoint 6 +// <7=> Endpoint 7 +// Data Tx (Bulk IN) +// <1=> Endpoint 1 +// <2=> Endpoint 2 +// <3=> Endpoint 3 +// <4=> Endpoint 4 +// <5=> Endpoint 5 +// <6=> Endpoint 6 +// <7=> Endpoint 7 +// Communication Endpoint Buffer Length (in byte) <4-64:4> +// Data Rx Endpoint Buffer Length (in byte) <4-64:4> +// Data Tx Endpoint Buffer Length (in byte) <4-64:4> +// Rx Buffer Length (in byte) <64-1024:4> +// Tx Buffer Length (in byte) <1-63:1> +// Please use "SERIAL_Flush()" to sent out the buffer data immediately when Tx Buffer Length > 1. +// USB Tx Mode (BULK IN) +// <0=> Block Mode (Wait until both USB and terminal software are ready) +// <1=> Non-Block Mode (Drop data if USB or terminal software is not ready) +// Enable HSI Auto Trim By USB Function +// Need turn on if the USB clock source is from HSI (PLL USBPLL clock Source). + #define RETARGET_CTRL_EPT (5) + #define RETARGET_RX_EPT (6) + #define RETARGET_TX_EPT (7) + #define RETARGET_CTRL_EPTLEN (8) + #define RETARGET_RX_EPTLEN (64) + #define RETARGET_TX_EPTLEN (64) + #define RETARGET_BUFFER_SIZE (64) + #define RETARGET_TXBUFFER_SIZE (1) // Use "SERIAL_Flush()" to sent out the buffer data immediately when Tx Buffer Length > 1. + #define RETARGET_USB_MODE (0) + #define RETARGET_HSI_ATM (1) +// +#elif (RETARGET_PORT == RETARGET_COM1) + #define RETARGET_COM_PORT COM1 + #define RETARGET_USART_PORT COM1_PORT + #define RETARGET_UART_IRQn COM1_IRQn + #define RETARGET_UART_IRQHandler COM1_IRQHandler + #define RETARGET_IS_UART +#elif (RETARGET_PORT == RETARGET_COM2) + #define RETARGET_COM_PORT COM2 + #define RETARGET_USART_PORT COM2_PORT + #define RETARGET_UART_IRQn COM2_IRQn + #define RETARGET_UART_IRQHandler COM2_IRQHandler + #define RETARGET_IS_UART +#elif (RETARGET_PORT == RETARGET_USART0) + #define RETARGET_UxART_IPN USART0 + #define RETARGET_USART_PORT STRCAT2(HT_, RETARGET_UxART_IPN) + #define RETARGET_UART_IRQn STRCAT2(RETARGET_UxART_IPN, _IRQn) + #define RETARGET_UART_IRQHandler STRCAT2(RETARGET_UxART_IPN, _IRQHandler) + #define RETARGET_IS_UART +#elif (RETARGET_PORT == RETARGET_USART1) + #define RETARGET_UxART_IPN USART1 + #define RETARGET_USART_PORT STRCAT2(HT_, RETARGET_UxART_IPN) + #define RETARGET_UART_IRQn STRCAT2(RETARGET_UxART_IPN, _IRQn) + #define RETARGET_UART_IRQHandler STRCAT2(RETARGET_UxART_IPN, _IRQHandler) + #define RETARGET_IS_UART +#elif (RETARGET_PORT == RETARGET_UART0) + #define RETARGET_UxART_IPN UART0 + #define RETARGET_USART_PORT STRCAT2(HT_, RETARGET_UxART_IPN) + #define RETARGET_UART_IRQn STRCAT2(RETARGET_UxART_IPN, _IRQn) + #define RETARGET_UART_IRQHandler STRCAT2(RETARGET_UxART_IPN, _IRQHandler) + #define RETARGET_IS_UART +#elif (RETARGET_PORT == RETARGET_UART1) + #define RETARGET_UxART_IPN UART1 + #define RETARGET_USART_PORT STRCAT2(HT_, RETARGET_UxART_IPN) + #define RETARGET_UART_IRQn STRCAT2(RETARGET_UxART_IPN, _IRQn) + #define RETARGET_UART_IRQHandler STRCAT2(RETARGET_UxART_IPN, _IRQHandler) + #define RETARGET_IS_UART +#endif + extern void RETARGET_Configuration(void); +#else + #define RETARGET_Configuration(...) + #undef printf + #undef getchar + #define printf(...) + #define getchar() (0) +#endif + +#if (RETARGET_DEFINE_HANDLER == 0) +#undef RETARGET_UART_IRQHandler +#endif + +/* +// Enable HT32 Time Function +// Provide "Time_GetTick()" and "Time_Dealy()" functions. + +// Timer Selection +// <0=> BFTM0 +// <1=> BFTM1 +// <2=> SCTM0 +// <3=> SCTM1 +// <4=> SCTM2 +// <5=> SCTM3 +// <6=> PWM0 +// <7=> PWM1 +// <8=> PWM2 +// <9=> GPTM0 +// <10=> GPTM1 +// <11=> MCTM0 + +// Timer Clock Setting +// +// Timer Clock = (Core Clock) / (APB Peripheral Clock Prescaler) +// HTCFG_TIME_CLKSRC = _HTCFG_TIME_CORECLK / (2^HTCFG_TIME_PCLK_DIV) +// _HTCFG_TIME_CORECLK = LIBCFG_MAX_SPEED or HTCFG_TIME_CLK_MANUAL (selected by HTCFG_TIME_CLKSEL) + +// -- Core Clock Setting (CK_AHB) +// HTCFG_TIME_CLKSEL +// 0 = Default Maximum (LIBCFG_MAX_SPEED) +// 1 = Manual Input (HTCFG_TIME_CLK_MANUAL) +// <0=> Default Maximum (LIBCFG_MAX_SPEED) +// <1=> Manual Input (HTCFG_TIME_CLK_MANUAL) + +// -- Core Clock Manual Input (Hz) +// HTCFG_TIME_CLK_MANUAL +// Only meaningful when Core Clock Setting (HTCFG_TIME_CLKSEL) = Manual Input (1) + +// -- APB Peripheral Clock Prescaler +// HTCFG_TIME_PCLK_DIV +// <0=> /1 +// <1=> /2 +// <2=> /4 +// <3=> /8 + +// Time Tick (Hz, not applicable for BFTM) <1-1000000:100> +// Not applicable for BFTM, fixed TICKHZ to HTCFG_TIME_CLKSRC for BFTM. +*/ +#if (0) // Enable HT32 Time Function +#define HTCFG_TIME_IPSEL (0) +#define HTCFG_TIME_CLKSEL (0) // 0 = Default Maximum (LIBCFG_MAX_SPEED), 1 = Manual Input (HTCFG_TIME_CLKSRC) +#define HTCFG_TIME_CLK_MANUAL (20000000) // Only meaningful when HTCFG_TIME_CLKSEL = 1 (Manual Input) +#define HTCFG_TIME_PCLK_DIV (0) // 0 ~ 3. (/1, /2, /4, /8) +#define HTCFG_TIME_TICKHZ (1000) // Hz, not applicable for BFTM, fixed TICKHZ to HTCFG_TIME_CLKSRC for BFTM +#define HTCFG_TIME_MULTIPLE (1) // MUST be 1, 2, 4, 8. TICK = COUNT / MULTIPLE. Not applicable for BFTM. +/* + + Timer Clock = (Core Clock) / (APB Peripheral Clock Prescaler) + HTCFG_TIME_CLKSRC = (_HTCFG_TIME_CORECLK) / (2^HTCFG_TIME_PCLK_DIV) + where _HTCFG_TIME_CORECLK can be LIBCFG_MAX_SPEED or HTCFG_TIME_CLK_MANUAL (selected by HTCFG_TIME_CLKSEL) + + Tick Range: 0 ~ 2^32 / HTCFG_TIME_TICKHZ (maximum tick time) + Interrupt Time: _HTCFG_TIME_OVERFLOW_VALUE / (HTCFG_TIME_TICKHZ * HTCFG_TIME_MULTIPLE) Second + (Interrupt Time is not applicable for BFTM) + + Example: 32-bit BFTM with 48 MHz Timer Clock + HTCFG_TIME_TICKHZ = HTCFG_TIME_CLKSRC = 48000000 + Tick Range: 0 ~ 2^32 / 48000000 = 0 ~ 89.478485 Second (maximum tick time, return to 0 every 89.478485 Second) + BFTM do not use interrupt + + Example: 16-bit GPTM with 1 ms tick + HTCFG_TIME_TICKHZ = 1000 (Hz) + HTCFG_TIME_MULTIPLE = 1 (1 Timer Count = 1 Tick) + Tick Range: 0 ~ 2^32 / 1000 = 0 ~ 4294967 Second = 0 ~ 49.7 Day (maximum tick time, return to 0 every 49.7 Day) + Interrupt Time: 65536 / (1000 * 1) = 65.536 Second (Trigger interrupt every 65.536 Second) +*/ +#endif +/* +// +*/ + +/* !!! NOTICE !!! + * How to adjust the value of High Speed External oscillator (HSE)? + The default value of HSE is define by "HSE_VALUE" in "ht32fxxxxx_nn.h". + If your board uses a different HSE speed, please add a new compiler preprocessor + C define, "HSE_VALUE=n000000" ("n" represents n MHz) in the toolchain/IDE, + or edit the "HSE_VALUE" in the "ht32f1xxxx_conf.h" file (this file). +*/ +/* +// Enable User Define HSE Value +// Enable user define HSE value to overwrite default "HSE_VALUE" define in "ht32fxxxxx_nn.h". +// HSE Value (Hz) +*/ +#if (0) +#define HSE_VALUE 16000000 +#endif +/* +// +*/ + +/* +// Enable CKOUT Function +*/ +#define ENABLE_CKOUT 0 + + +/* The DEBUG definition to enter debug mode for library */ +/* +// Library Debug Mode +*/ +#define HT32_LIB_DEBUG 0 + + +/* Enable/disable the specific peripheral inclusion */ + +// Library Inclusion Configuration +/* ADC -----------------------------------------------------------------------------------------------------*/ +/* +// ADC Library +*/ +#define _ADC 1 + +/* AES -----------------------------------------------------------------------------------------------------*/ +/* +// AES Library +*/ +#define _AES 1 + +/* BFTM ----------------------------------------------------------------------------------------------------*/ +/* +// BFTM Library +*/ +#define _BFTM 1 + +/* Clock Control -------------------------------------------------------------------------------------------*/ +/* +// Clock Control Library +*/ +#define _CKCU 1 + +/* Comparator/OPA ------------------------------------------------------------------------------------------*/ +/* +// Comparator/OPA Library +*/ +#define _CMP_OPA 1 + +/* Comparator ----------------------------------------------------------------------------------------------*/ +/* +// Comparator Library +*/ +#define _CMP 1 + +/* CRC -----------------------------------------------------------------------------------------------------*/ +/* +// CRC Library +*/ +#define _CRC 1 + +/* CSIF ----------------------------------------------------------------------------------------------------*/ +/* +// CSIF Library +*/ +#define _CSIF 1 + +/* EBI -----------------------------------------------------------------------------------------------------*/ +/* +// EBI Library +*/ +#define _EBI 1 + +/* EXTI ----------------------------------------------------------------------------------------------------*/ +/* +// EXTI Library +*/ +#define _EXTI 1 + +/* Flash ---------------------------------------------------------------------------------------------------*/ +/* +// Flash Library +*/ +#define _FLASH 1 + +/* GPIO ----------------------------------------------------------------------------------------------------*/ +/* +// GPIO Library +*/ +#define _GPIO 1 + +/* GPTM ----------------------------------------------------------------------------------------------------*/ +/* +// GPTM Library +*/ +#define _GPTM 1 + +/* I2C -----------------------------------------------------------------------------------------------------*/ +/* +// I2C Library +*/ +#define _I2C 1 + +/* I2S -----------------------------------------------------------------------------------------------------*/ +/* +// I2S Library +*/ +#define _I2S 1 + +/* MCTM ----------------------------------------------------------------------------------------------------*/ +/* +// MCTM Library +*/ +#define _MCTM 1 + +/* PDMA ----------------------------------------------------------------------------------------------------*/ +/* +// PDMA Library +*/ +#define _PDMA 1 + +/* PWM -----------------------------------------------------------------------------------------------------*/ +/* +// PWM Library +*/ +#define _PWM 1 + +/* PWRCU ---------------------------------------------------------------------------------------------------*/ +/* +// PWRCU Library +*/ +#define _PWRCU 1 + +/* RSTCU ---------------------------------------------------------------------------------------------------*/ +/* +// RSTCU Library +*/ +#define _RSTCU 1 + +/* RTC -----------------------------------------------------------------------------------------------------*/ +/* +// RTC Library +*/ +#define _RTC 1 + +/* SCI -----------------------------------------------------------------------------------------------------*/ +/* +// SCI Library +*/ +#define _SCI 1 + +/* SCTM ----------------------------------------------------------------------------------------------------*/ +/* +// SCTM Library +*/ +#define _SCTM 1 + +/* SDIO ----------------------------------------------------------------------------------------------------*/ +/* +// SDIO Library +*/ +#define _SDIO 1 + +/* SPI -----------------------------------------------------------------------------------------------------*/ +/* +// SPI Library +*/ +#define _SPI 1 + +/* USART ---------------------------------------------------------------------------------------------------*/ +/* +// USART/UART Library +*/ +#define _USART 1 + +/* USBD ----------------------------------------------------------------------------------------------------*/ +/* +// USB Library +*/ +#define _USB 1 + +/* WDT -----------------------------------------------------------------------------------------------------*/ +/* +// WDT Library +*/ +#define _WDT 1 + +/* Misc ----------------------------------------------------------------------------------------------------*/ +/* +// Misc Library +*/ +#define _MISC 1 + +/* Serial --------------------------------------------------------------------------------------------------*/ +/* +// Serial Library +*/ +#define _SERIAL 1 + +/* Software Random Number ----------------------------------------------------------------------------------*/ +/* +// Software Random Number Library +*/ +#define _SWRAND 1 + + +// + +#endif diff --git a/bsp/ht32/ht32f12366/board/linker_scripts/link.icf b/bsp/ht32/ht32f12366/board/linker_scripts/link.icf new file mode 100644 index 0000000000..65c2bfc8b7 --- /dev/null +++ b/bsp/ht32/ht32f12366/board/linker_scripts/link.icf @@ -0,0 +1,28 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x08000000; +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_ROM_start__ = 0x08000000; +define symbol __ICFEDIT_region_ROM_end__ = 0x080FFFFF; +define symbol __ICFEDIT_region_RAM_start__ = 0x20000000; +define symbol __ICFEDIT_region_RAM_end__ = 0x20017FFF; +/*-Sizes-*/ +define symbol __ICFEDIT_size_cstack__ = 0x0400; +define symbol __ICFEDIT_size_heap__ = 0x0000; +/**** End of ICF editor section. ###ICF###*/ + +define memory mem with size = 4G; +define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; +define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; + +initialize by copy { readwrite }; +do not initialize { section .noinit }; + +place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; + +place in ROM_region { readonly }; +place in RAM_region { readwrite, last block CSTACK}; \ No newline at end of file diff --git a/bsp/ht32/ht32f12366/board/linker_scripts/link.lds b/bsp/ht32/ht32f12366/board/linker_scripts/link.lds new file mode 100644 index 0000000000..27269dd77e --- /dev/null +++ b/bsp/ht32/ht32f12366/board/linker_scripts/link.lds @@ -0,0 +1,156 @@ +/* + * linker script for AT32 with GNU ld + */ + +/* Program Entry, set to mark it as "used" and avoid gc */ +MEMORY +{ + ROM (rx) : ORIGIN = 0x08000000, LENGTH = 1024k /* 1024KB flash */ + RAM (rw) : ORIGIN = 0x20000000, LENGTH = 96k /* 96K sram */ +} +ENTRY(Reset_Handler) +_system_stack_size = 0x200; + +SECTIONS +{ + .text : + { + . = ALIGN(4); + _stext = .; + KEEP(*(.isr_vector)) /* Startup code */ + + . = ALIGN(4); + *(.text) /* remaining code */ + *(.text.*) /* remaining code */ + *(.rodata) /* read-only data (constants) */ + *(.rodata*) + *(.glue_7) + *(.glue_7t) + *(.gnu.linkonce.t*) + + /* section information for finsh shell */ + . = ALIGN(4); + __fsymtab_start = .; + KEEP(*(FSymTab)) + __fsymtab_end = .; + + . = ALIGN(4); + __vsymtab_start = .; + KEEP(*(VSymTab)) + __vsymtab_end = .; + + /* section information for initial. */ + . = ALIGN(4); + __rt_init_start = .; + KEEP(*(SORT(.rti_fn*))) + __rt_init_end = .; + + . = ALIGN(4); + + PROVIDE(__ctors_start__ = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array)) + PROVIDE(__ctors_end__ = .); + + . = ALIGN(4); + + _etext = .; + } > ROM = 0 + + /* .ARM.exidx is sorted, so has to go in its own output section. */ + __exidx_start = .; + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + + /* This is used by the startup in order to initialize the .data secion */ + _sidata = .; + } > ROM + __exidx_end = .; + + /* .data section which is used for initialized data */ + + .data : AT (_sidata) + { + . = ALIGN(4); + /* This is used by the startup in order to initialize the .data secion */ + _sdata = . ; + + *(.data) + *(.data.*) + *(.gnu.linkonce.d*) + + PROVIDE(__dtors_start__ = .); + KEEP(*(SORT(.dtors.*))) + KEEP(*(.dtors)) + PROVIDE(__dtors_end__ = .); + + . = ALIGN(4); + /* This is used by the startup in order to initialize the .data secion */ + _edata = . ; + } >RAM + + .stack : + { + . = ALIGN(4); + _sstack = .; + . = . + _system_stack_size; + . = ALIGN(4); + _estack = .; + } >RAM + + __bss_start = .; + .bss : + { + . = ALIGN(4); + /* This is used by the startup in order to initialize the .bss secion */ + _sbss = .; + + *(.bss) + *(.bss.*) + *(COMMON) + + . = ALIGN(4); + /* This is used by the startup in order to initialize the .bss secion */ + _ebss = . ; + + *(.bss.init) + } > RAM + __bss_end = .; + + _end = .; + + /* Stabs debugging sections. */ + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + /* DWARF debug sections. + * Symbols in the DWARF debugging sections are relative to the beginning + * of the section so we begin them at 0. */ + /* DWARF 1 */ + .debug 0 : { *(.debug) } + .line 0 : { *(.line) } + /* GNU DWARF 1 extensions */ + .debug_srcinfo 0 : { *(.debug_srcinfo) } + .debug_sfnames 0 : { *(.debug_sfnames) } + /* DWARF 1.1 and DWARF 2 */ + .debug_aranges 0 : { *(.debug_aranges) } + .debug_pubnames 0 : { *(.debug_pubnames) } + /* DWARF 2 */ + .debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_line 0 : { *(.debug_line) } + .debug_frame 0 : { *(.debug_frame) } + .debug_str 0 : { *(.debug_str) } + .debug_loc 0 : { *(.debug_loc) } + .debug_macinfo 0 : { *(.debug_macinfo) } + /* SGI/MIPS DWARF 2 extensions */ + .debug_weaknames 0 : { *(.debug_weaknames) } + .debug_funcnames 0 : { *(.debug_funcnames) } + .debug_typenames 0 : { *(.debug_typenames) } + .debug_varnames 0 : { *(.debug_varnames) } +} diff --git a/bsp/ht32/ht32f12366/board/linker_scripts/link.sct b/bsp/ht32/ht32f12366/board/linker_scripts/link.sct new file mode 100644 index 0000000000..16cced4f77 --- /dev/null +++ b/bsp/ht32/ht32f12366/board/linker_scripts/link.sct @@ -0,0 +1,15 @@ +; ************************************************************* +; *** Scatter-Loading Description File generated by uVision *** +; ************************************************************* + +LR_IROM1 0x00000000 0x0003FC00 { ; load region size_region + ER_IROM1 0x00000000 0x0003FC00 { ; load address = execution address + *.o (RESET, +First) + *(InRoot$$Sections) + .ANY (+RO) + } + RW_IRAM1 0x20000000 0x00020000 { ; RW data + .ANY (+RW +ZI) + } +} + diff --git a/bsp/ht32/ht32f12366/board/src/board.c b/bsp/ht32/ht32f12366/board/src/board.c new file mode 100644 index 0000000000..e0160468e9 --- /dev/null +++ b/bsp/ht32/ht32f12366/board/src/board.c @@ -0,0 +1,17 @@ +/* + * Copyright (c) 2006-2024, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2024-04-08 QT-one first version + */ + +#include "board.h" + +/* This feature will initialize the HT32 chip clock */ +void rt_hw_board_clock_init(void) +{ + +} diff --git a/bsp/ht32/ht32f12366/board/src/ht32_msp.c b/bsp/ht32/ht32f12366/board/src/ht32_msp.c new file mode 100644 index 0000000000..4ef7b61b54 --- /dev/null +++ b/bsp/ht32/ht32f12366/board/src/ht32_msp.c @@ -0,0 +1,138 @@ +/* + * Copyright (c) 2006-2024, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2024-04-08 QT-one first version + */ + +#include "ht32_msp.h" + +/* GPIO configuration for UART */ +#ifdef BSP_USING_UART +void ht32_usart_gpio_init(void *instance) +{ + CKCU_PeripClockConfig_TypeDef CKCUClock = {{0}}; + HT_USART_TypeDef *usart_x = (HT_USART_TypeDef *)instance; +#ifdef BSP_USING_USART0 + if(HT_USART0 == usart_x) + { + CKCUClock.Bit.HTCFG_USART0_TX_GPIO_CLK = 1; + CKCUClock.Bit.HTCFG_USART0_RX_GPIO_CLK = 1; + CKCU_PeripClockConfig(CKCUClock,ENABLE); + /* Turn on UxART Rx internal pull up resistor to prevent unknow state */ + GPIO_PullResistorConfig(HTCFG_USART0_RX_GPIO_PORT,HTCFG_USART0_RX_GPIO_PIN,GPIO_PR_UP); + /* Config AFIO mode as UxART function */ + AFIO_GPxConfig(HTCFG_USART0_TX_GPIO_ID,HTCFG_USART0_TX_GPIO_PIN,AFIO_FUN_USART_UART); + AFIO_GPxConfig(HTCFG_USART0_RX_GPIO_ID,HTCFG_USART0_RX_GPIO_PIN,AFIO_FUN_USART_UART); + } +#endif +#ifdef BSP_USING_USART1 + if(HT_USART1 == usart_x) + { + CKCUClock.Bit.HTCFG_USART1_TX_GPIO_CLK = 1; + CKCUClock.Bit.HTCFG_USART1_RX_GPIO_CLK = 1; + CKCU_PeripClockConfig(CKCUClock,ENABLE); + /* Turn on UxART Rx internal pull up resistor to prevent unknow state */ + GPIO_PullResistorConfig(HTCFG_USART1_RX_GPIO_PORT,HTCFG_USART1_RX_GPIO_PIN,GPIO_PR_UP); + /* Config AFIO mode as UxART function */ + AFIO_GPxConfig(HTCFG_USART1_TX_GPIO_ID,HTCFG_USART1_TX_GPIO_PIN,AFIO_FUN_USART_UART); + AFIO_GPxConfig(HTCFG_USART1_RX_GPIO_ID,HTCFG_USART1_RX_GPIO_PIN,AFIO_FUN_USART_UART); + } +#endif +#ifdef BSP_USING_UART0 + if(HT_UART0 == usart_x) + { + CKCUClock.Bit.HTCFG_UART0_TX_GPIO_CLK = 1; + CKCUClock.Bit.HTCFG_UART0_RX_GPIO_CLK = 1; + CKCU_PeripClockConfig(CKCUClock,ENABLE); + /* Turn on UxART Rx internal pull up resistor to prevent unknow state */ + GPIO_PullResistorConfig(HTCFG_UART0_RX_GPIO_PORT,HTCFG_UART0_RX_GPIO_PIN,GPIO_PR_UP); + /* Config AFIO mode as UxART function */ + AFIO_GPxConfig(HTCFG_UART0_TX_GPIO_ID,HTCFG_UART0_TX_GPIO_PIN,AFIO_FUN_USART_UART); + AFIO_GPxConfig(HTCFG_UART0_RX_GPIO_ID,HTCFG_UART0_RX_GPIO_PIN,AFIO_FUN_USART_UART); + } +#endif +#ifdef BSP_USING_UART1 + if(HT_UART1 == usart_x) + { + CKCUClock.Bit.HTCFG_UART1_TX_GPIO_CLK = 1; + CKCUClock.Bit.HTCFG_UART1_RX_GPIO_CLK = 1; + CKCU_PeripClockConfig(CKCUClock,ENABLE); + /* Turn on UxART Rx internal pull up resistor to prevent unknow state */ + GPIO_PullResistorConfig(HTCFG_UART1_RX_GPIO_PORT,HTCFG_UART1_RX_GPIO_PIN,GPIO_PR_UP); + /* Config AFIO mode as UxART function */ + AFIO_GPxConfig(HTCFG_UART1_TX_GPIO_ID,HTCFG_UART1_TX_GPIO_PIN,AFIO_FUN_USART_UART); + AFIO_GPxConfig(HTCFG_UART1_RX_GPIO_ID,HTCFG_UART1_RX_GPIO_PIN,AFIO_FUN_USART_UART); + } +#endif +} +#endif + +/* GPIO configuration for SPI */ +#ifdef BSP_USING_SPI +void ht32_spi_gpio_init(void *instance) +{ + CKCU_PeripClockConfig_TypeDef CKCUClock = {{0}}; + HT_SPI_TypeDef *spi_x = (HT_SPI_TypeDef *)instance; +#ifdef BSP_USING_SPI0 + if(HT_SPI0 == spi_x) + { + CKCUClock.Bit.HTCFG_SPI0_SCK_GPIO_CLK = 1; + CKCUClock.Bit.HTCFG_SPI0_MISO_GPIO_CLK = 1; + CKCUClock.Bit.HTCFG_SPI0_MOSI_GPIO_CLK = 1; + CKCU_PeripClockConfig(CKCUClock,ENABLE); + + AFIO_GPxConfig(HTCFG_SPI0_SCK_GPIO_ID, HTCFG_SPI0_SCK_GPIO_PIN, AFIO_FUN_SPI); + AFIO_GPxConfig(HTCFG_SPI0_MISO_GPIO_ID, HTCFG_SPI0_MISO_GPIO_PIN, AFIO_FUN_SPI); + AFIO_GPxConfig(HTCFG_SPI0_MOSI_GPIO_ID, HTCFG_SPI0_MOSI_GPIO_PIN, AFIO_FUN_SPI); + } +#endif +#ifdef BSP_USING_SPI1 + if(HT_SPI1 == spi_x) + { + CKCUClock.Bit.HTCFG_SPI1_SCK_GPIO_CLK = 1; + CKCUClock.Bit.HTCFG_SPI1_MISO_GPIO_CLK = 1; + CKCUClock.Bit.HTCFG_SPI1_MOSI_GPIO_CLK = 1; + CKCU_PeripClockConfig(CKCUClock,ENABLE); + + AFIO_GPxConfig(HTCFG_SPI1_SCK_GPIO_ID, HTCFG_SPI1_SCK_GPIO_PIN, AFIO_FUN_SPI); + AFIO_GPxConfig(HTCFG_SPI1_MISO_GPIO_ID, HTCFG_SPI1_MISO_GPIO_PIN, AFIO_FUN_SPI); + AFIO_GPxConfig(HTCFG_SPI1_MOSI_GPIO_ID, HTCFG_SPI1_MOSI_GPIO_PIN, AFIO_FUN_SPI); + } +#endif +} +#endif + +/* GPIO configuration for I2C */ +#ifdef BSP_USING_I2C +void ht32_i2c_gpio_init(void *instance) +{ + CKCU_PeripClockConfig_TypeDef CKCUClock = {{0}}; + HT_I2C_TypeDef *i2c_x = (HT_I2C_TypeDef *)instance; +#ifdef BSP_USING_I2C0 + if(HT_I2C0 == i2c_x) + { + CKCUClock.Bit.HTCFG_I2C0_SCL_GPIO_CLK = 1; + CKCUClock.Bit.HTCFG_I2C0_SDA_GPIO_CLK = 1; + CKCU_PeripClockConfig(CKCUClock,ENABLE); + /* Configure GPIO to I2C mode */ + AFIO_GPxConfig(HTCFG_I2C0_SCL_GPIO_ID,HTCFG_I2C0_SCL_GPIO_PIN,AFIO_FUN_I2C); + AFIO_GPxConfig(HTCFG_I2C0_SDA_GPIO_ID,HTCFG_I2C0_SDA_GPIO_PIN,AFIO_FUN_I2C); + } +#endif +#ifdef BSP_USING_I2C1 + if(HT_I2C1 == i2c_x) + { + CKCUClock.Bit.HTCFG_I2C1_SCL_GPIO_CLK = 1; + CKCUClock.Bit.HTCFG_I2C1_SDA_GPIO_CLK = 1; + CKCU_PeripClockConfig(CKCUClock,ENABLE); + /* Configure GPIO to I2C mode */ + AFIO_GPxConfig(HTCFG_I2C1_SCL_GPIO_ID,HTCFG_I2C1_SCL_GPIO_PIN,AFIO_FUN_I2C); + AFIO_GPxConfig(HTCFG_I2C1_SDA_GPIO_ID,HTCFG_I2C1_SDA_GPIO_PIN,AFIO_FUN_I2C); + } +#endif +} +#endif diff --git a/bsp/ht32/ht32f12366/figures/board.png b/bsp/ht32/ht32f12366/figures/board.png new file mode 100644 index 0000000000..850221d1af Binary files /dev/null and b/bsp/ht32/ht32f12366/figures/board.png differ diff --git a/bsp/ht32/ht32f12366/project.uvoptx b/bsp/ht32/ht32f12366/project.uvoptx new file mode 100644 index 0000000000..b6ec60944b --- /dev/null +++ b/bsp/ht32/ht32f12366/project.uvoptx @@ -0,0 +1,1219 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
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0 + ..\libraries\HT32_STD_1xxxx_FWLib\library\HT32F1xxxx_Driver\src\ht32f1xxxx_exti.c + ht32f1xxxx_exti.c + 0 + 0 + + + 8 + 82 + 1 + 0 + 0 + 0 + ..\libraries\HT32_STD_1xxxx_FWLib\library\HT32F1xxxx_Driver\src\ht32f1xxxx_rtc.c + ht32f1xxxx_rtc.c + 0 + 0 + + + + diff --git a/bsp/ht32/ht32f12366/project.uvprojx b/bsp/ht32/ht32f12366/project.uvprojx new file mode 100644 index 0000000000..0e9ceaea2f --- /dev/null +++ b/bsp/ht32/ht32f12366/project.uvprojx @@ -0,0 +1,2439 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
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..\libraries\HT32_STD_1xxxx_FWLib\library\HT32F1xxxx_Driver\src\ht32f1xxxx_sdio.c + + + ht32f1xxxx_ebi.c + 1 + ..\libraries\HT32_STD_1xxxx_FWLib\library\HT32F1xxxx_Driver\src\ht32f1xxxx_ebi.c + + + ht32f1xxxx_cmp.c + 1 + ..\libraries\HT32_STD_1xxxx_FWLib\library\HT32F1xxxx_Driver\src\ht32f1xxxx_cmp.c + + + ht32f1xxxx_i2c.c + 1 + ..\libraries\HT32_STD_1xxxx_FWLib\library\HT32F1xxxx_Driver\src\ht32f1xxxx_i2c.c + + + ht32f1xxxx_adc.c + 1 + ..\libraries\HT32_STD_1xxxx_FWLib\library\HT32F1xxxx_Driver\src\ht32f1xxxx_adc.c + + + ht32f1xxxx_pwrcu.c + 1 + ..\libraries\HT32_STD_1xxxx_FWLib\library\HT32F1xxxx_Driver\src\ht32f1xxxx_pwrcu.c + + + ht32f1xxxx_pdma.c + 1 + ..\libraries\HT32_STD_1xxxx_FWLib\library\HT32F1xxxx_Driver\src\ht32f1xxxx_pdma.c + + + system_ht32f1xxxx_02.c + 1 + ..\libraries\HT32_STD_1xxxx_FWLib\library\Device\Holtek\HT32F1xxxx\Source\system_ht32f1xxxx_02.c + + + ht32f1xxxx_mctm.c + 1 + ..\libraries\HT32_STD_1xxxx_FWLib\library\HT32F1xxxx_Driver\src\ht32f1xxxx_mctm.c + + + ht32f1xxxx_spi.c + 1 + ..\libraries\HT32_STD_1xxxx_FWLib\library\HT32F1xxxx_Driver\src\ht32f1xxxx_spi.c + + + ht32f1xxxx_bftm.c + 1 + ..\libraries\HT32_STD_1xxxx_FWLib\library\HT32F1xxxx_Driver\src\ht32f1xxxx_bftm.c + + + ht32f1xxxx_i2s.c + 1 + ..\libraries\HT32_STD_1xxxx_FWLib\library\HT32F1xxxx_Driver\src\ht32f1xxxx_i2s.c + + + ht32f1xxxx_exti.c + 1 + ..\libraries\HT32_STD_1xxxx_FWLib\library\HT32F1xxxx_Driver\src\ht32f1xxxx_exti.c + + + ht32f1xxxx_rtc.c + 1 + ..\libraries\HT32_STD_1xxxx_FWLib\library\HT32F1xxxx_Driver\src\ht32f1xxxx_rtc.c + + + + + + + + + + + + + + diff --git a/bsp/ht32/ht32f12366/rtconfig.h b/bsp/ht32/ht32f12366/rtconfig.h new file mode 100644 index 0000000000..42fd7c23e0 --- /dev/null +++ b/bsp/ht32/ht32f12366/rtconfig.h @@ -0,0 +1,273 @@ +#ifndef RT_CONFIG_H__ +#define RT_CONFIG_H__ + +/* Automatically generated file; DO NOT EDIT. */ +/* RT-Thread Configuration */ + +/* RT-Thread Kernel */ + +#define RT_NAME_MAX 8 +#define RT_CPUS_NR 1 +#define RT_ALIGN_SIZE 4 +#define RT_THREAD_PRIORITY_32 +#define RT_THREAD_PRIORITY_MAX 32 +#define RT_TICK_PER_SECOND 1000 +#define RT_USING_OVERFLOW_CHECK +#define RT_USING_HOOK +#define RT_HOOK_USING_FUNC_PTR +#define RT_USING_IDLE_HOOK +#define RT_IDLE_HOOK_LIST_SIZE 4 +#define IDLE_THREAD_STACK_SIZE 256 + +/* kservice optimization */ + +#define RT_USING_DEBUG +#define RT_DEBUGING_COLOR +#define RT_DEBUGING_CONTEXT + +/* Inter-Thread communication */ + +#define RT_USING_SEMAPHORE +#define RT_USING_MUTEX +#define RT_USING_EVENT +#define RT_USING_MAILBOX +#define RT_USING_MESSAGEQUEUE + +/* Memory Management */ + +#define RT_USING_MEMPOOL +#define RT_USING_SMALL_MEM +#define RT_USING_MEMHEAP +#define RT_MEMHEAP_FAST_MODE +#define RT_USING_SMALL_MEM_AS_HEAP +#define RT_USING_HEAP +#define RT_USING_DEVICE +#define RT_USING_CONSOLE +#define RT_CONSOLEBUF_SIZE 128 +#define RT_CONSOLE_DEVICE_NAME "usart0" +#define RT_VER_NUM 0x50100 +#define RT_BACKTRACE_LEVEL_MAX_NR 32 +#define RT_USING_HW_ATOMIC +#define RT_USING_CPU_FFS +#define ARCH_ARM +#define ARCH_ARM_CORTEX_M +#define ARCH_ARM_CORTEX_M3 + +/* RT-Thread Components */ + +#define RT_USING_COMPONENTS_INIT +#define RT_USING_USER_MAIN +#define RT_MAIN_THREAD_STACK_SIZE 2048 +#define RT_MAIN_THREAD_PRIORITY 10 +#define RT_USING_MSH +#define RT_USING_FINSH +#define FINSH_USING_MSH +#define FINSH_THREAD_NAME "tshell" +#define FINSH_THREAD_PRIORITY 20 +#define FINSH_THREAD_STACK_SIZE 4096 +#define FINSH_USING_HISTORY +#define FINSH_HISTORY_LINES 5 +#define FINSH_USING_SYMTAB +#define FINSH_CMD_SIZE 80 +#define MSH_USING_BUILT_IN_COMMANDS +#define FINSH_USING_DESCRIPTION +#define FINSH_ARG_MAX 10 +#define FINSH_USING_OPTION_COMPLETION + +/* DFS: device virtual file system */ + + +/* Device Drivers */ + +#define RT_USING_DEVICE_IPC +#define RT_UNAMED_PIPE_NUMBER 64 +#define RT_USING_SERIAL +#define RT_USING_SERIAL_V1 +#define RT_SERIAL_USING_DMA +#define RT_SERIAL_RB_BUFSZ 64 +#define RT_USING_I2C +#define RT_USING_I2C_BITOPS +#define RT_USING_SPI +#define RT_USING_PIN + +/* Using USB */ + + +/* C/C++ and POSIX layer */ + +/* ISO-ANSI C layer */ + +/* Timezone and Daylight Saving Time */ + +#define RT_LIBC_USING_LIGHT_TZ_DST +#define RT_LIBC_TZ_DEFAULT_HOUR 8 +#define RT_LIBC_TZ_DEFAULT_MIN 0 +#define RT_LIBC_TZ_DEFAULT_SEC 0 + +/* POSIX (Portable Operating System Interface) layer */ + + +/* Interprocess Communication (IPC) */ + + +/* Socket is in the 'Network' category */ + + +/* Network */ + + +/* Memory protection */ + + +/* Utilities */ + + +/* RT-Thread Utestcases */ + + +/* RT-Thread online packages */ + +/* IoT - internet of things */ + + +/* Wi-Fi */ + +/* Marvell WiFi */ + + +/* Wiced WiFi */ + + +/* CYW43012 WiFi */ + + +/* BL808 WiFi */ + + +/* CYW43439 WiFi */ + + +/* IoT Cloud */ + + +/* security packages */ + + +/* language packages */ + +/* JSON: JavaScript Object Notation, a lightweight data-interchange format */ + + +/* XML: Extensible Markup Language */ + + +/* multimedia packages */ + +/* LVGL: powerful and easy-to-use embedded GUI library */ + + +/* u8g2: a monochrome graphic library */ + + +/* tools packages */ + + +/* system packages */ + +/* enhanced kernel services */ + + +/* acceleration: Assembly language or algorithmic acceleration packages */ + + +/* CMSIS: ARM Cortex-M Microcontroller Software Interface Standard */ + + +/* Micrium: Micrium software products porting for RT-Thread */ + + +/* peripheral libraries and drivers */ + +/* HAL & SDK Drivers */ + +/* STM32 HAL & SDK Drivers */ + + +/* Kendryte SDK */ + + +/* sensors drivers */ + + +/* touch drivers */ + + +/* AI packages */ + + +/* Signal Processing and Control Algorithm Packages */ + + +/* miscellaneous packages */ + +/* project laboratory */ + +/* samples: kernel and components samples */ + + +/* entertainment: terminal games and other interesting software packages */ + + +/* Arduino libraries */ + + +/* Projects and Demos */ + + +/* Sensors */ + + +/* Display */ + + +/* Timing */ + + +/* Data Processing */ + + +/* Data Storage */ + +/* Communication */ + + +/* Device Control */ + + +/* Other */ + + +/* Signal IO */ + + +/* Uncategorized */ + +#define SOC_FAMILY_HT32 +#define SOC_SERIES_HT32F1 + +/* Hardware Drivers Config */ + +#define SOC_HT32F12366 + +/* Onboard Peripheral Drivers */ + +/* On-chip Peripheral Drivers */ + +#define BSP_USING_GPIO +#define BSP_USING_UART +#define BSP_USING_USART0 + +/* Board extended module Drivers */ + + +#endif diff --git a/bsp/ht32/ht32f12366/rtconfig.py b/bsp/ht32/ht32f12366/rtconfig.py new file mode 100644 index 0000000000..1c3077b6cf --- /dev/null +++ b/bsp/ht32/ht32f12366/rtconfig.py @@ -0,0 +1,152 @@ +import os + +# toolchains options +ARCH='arm' +CPU='cortex-m3' +CROSS_TOOL='keil' + +# bsp lib config +BSP_LIBRARY_TYPE = None + +if os.getenv('RTT_CC'): + CROSS_TOOL = os.getenv('RTT_CC') +if os.getenv('RTT_ROOT'): + RTT_ROOT = os.getenv('RTT_ROOT') + +# cross_tool provides the cross compiler +# EXEC_PATH is the compiler execute path, for example, CodeSourcery, Keil MDK, IAR +if CROSS_TOOL == 'gcc': + PLATFORM = 'gcc' + EXEC_PATH = r'C:\Users\XXYYZZ' +elif CROSS_TOOL == 'keil': + PLATFORM = 'armcc' +# EXEC_PATH = r'D:\keil5\keil_v532\UV4' + EXEC_PATH = r'C:/Keil_v5' +elif CROSS_TOOL == 'iar': + PLATFORM = 'iar' + EXEC_PATH = r'C:/Program Files (x86)/IAR Systems/Embedded Workbench 8.0' + +if os.getenv('RTT_EXEC_PATH'): + EXEC_PATH = os.getenv('RTT_EXEC_PATH') + +BUILD = 'debug' + +if PLATFORM == 'gcc': + # toolchains + PREFIX = 'arm-none-eabi-' + CC = PREFIX + 'gcc' + AS = PREFIX + 'gcc' + AR = PREFIX + 'ar' + CXX = PREFIX + 'g++' + LINK = PREFIX + 'gcc' + TARGET_EXT = 'elf' + SIZE = PREFIX + 'size' + OBJDUMP = PREFIX + 'objdump' + OBJCPY = PREFIX + 'objcopy' + + DEVICE = ' -mcpu=cortex-m3 -mthumb -ffunction-sections -fdata-sections' + CFLAGS = DEVICE + ' -Dgcc' + AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp -Wa,-mimplicit-it=thumb ' + LFLAGS = DEVICE + ' -Wl,--gc-sections,-Map=rt-thread.map,-cref,-u,Reset_Handler -T board/linker_scripts/link.lds' + + CPATH = '' + LPATH = '' + + if BUILD == 'debug': + CFLAGS += ' -O0 -gdwarf-2 -g' + AFLAGS += ' -gdwarf-2' + else: + CFLAGS += ' -O2' + + CXXFLAGS = CFLAGS + + POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n' + +elif PLATFORM == 'armcc': + # toolchains + CC = 'armcc' + CXX = 'armcc' + AS = 'armasm' + AR = 'armar' + LINK = 'armlink' + TARGET_EXT = 'axf' + + DEVICE = ' --cpu Cortex-M3 ' + CFLAGS = '-c ' + DEVICE + ' --apcs=interwork --c99' + AFLAGS = DEVICE + ' --apcs=interwork ' + LFLAGS = DEVICE + ' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rt-thread.map --strict' + CFLAGS += ' -I' + EXEC_PATH + '/ARM/ARMCC/include' + LFLAGS += ' --libpath=' + EXEC_PATH + '/ARM/ARMCC/lib' + + CFLAGS += ' -D__MICROLIB ' + AFLAGS += ' --pd "__MICROLIB SETA 1" ' + LFLAGS += ' --library_type=microlib ' + EXEC_PATH += '/ARM/ARMCC/bin/' + + if BUILD == 'debug': + CFLAGS += ' -g -O0' + AFLAGS += ' -g' + else: + CFLAGS += ' -O2' + + CXXFLAGS = CFLAGS + CFLAGS += ' -std=c99' + + POST_ACTION = 'fromelf --bin $TARGET --output rtthread.bin \nfromelf -z $TARGET' + +elif PLATFORM == 'iar': + # toolchains + CC = 'iccarm' + CXX = 'iccarm' + AS = 'iasmarm' + AR = 'iarchive' + LINK = 'ilinkarm' + TARGET_EXT = 'out' + + DEVICE = '-Dewarm' + + CFLAGS = DEVICE + CFLAGS += ' --diag_suppress Pa050' + CFLAGS += ' --no_cse' + CFLAGS += ' --no_unroll' + CFLAGS += ' --no_inline' + CFLAGS += ' --no_code_motion' + CFLAGS += ' --no_tbaa' + CFLAGS += ' --no_clustering' + CFLAGS += ' --no_scheduling' + CFLAGS += ' --endian=little' + CFLAGS += ' --cpu=Cortex-M3' + CFLAGS += ' -e' + CFLAGS += ' --fpu=None' + CFLAGS += ' --dlib_config "' + EXEC_PATH + '/arm/INC/c/DLib_Config_Normal.h"' + CFLAGS += ' --silent' + + AFLAGS = DEVICE + AFLAGS += ' -s+' + AFLAGS += ' -w+' + AFLAGS += ' -r' + AFLAGS += ' --cpu Cortex-M3' + AFLAGS += ' --fpu None' + AFLAGS += ' -S' + + if BUILD == 'debug': + CFLAGS += ' --debug' + CFLAGS += ' -On' + else: + CFLAGS += ' -Oh' + + LFLAGS = ' --config "board/linker_scripts/link.icf"' + LFLAGS += ' --entry __iar_program_start' + + CXXFLAGS = CFLAGS + + EXEC_PATH = EXEC_PATH + '/arm/bin/' + POST_ACTION = 'ielftool --bin $TARGET rtthread.bin' + +def dist_handle(BSP_ROOT, dist_dir): + import sys + cwd_path = os.getcwd() + sys.path.append(os.path.join(os.path.dirname(BSP_ROOT), 'tools')) + from sdk_dist import dist_do_building + dist_do_building(BSP_ROOT, dist_dir) + diff --git a/bsp/ht32/ht32f12366/template.uvoptx b/bsp/ht32/ht32f12366/template.uvoptx new file mode 100644 index 0000000000..4c6655f9dd --- /dev/null +++ b/bsp/ht32/ht32f12366/template.uvoptx @@ -0,0 +1,179 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + rt-thread + 0x4 + ARM-ADS + + 12000000 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\build\keil\List\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 255 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 2 + + + + + + + + + + + BIN\CMSIS_AGDI.dll + + + + 0 + CMSIS_AGDI + -X"Any" -UAny -O206 -S0 -C0 -P00 -N00("ARM CoreSight SW-DP") -D00(2BA01477) -L00(0) -TO18 -TC10000000 -TP20 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO15 -FD20000000 -FC1000 -FN2 -FF0HT32F.FLM -FS00 -FL0100000 -FP0($$Device:HT32F12366$ARM\Flash\HT32F.FLM) -FF1HT32F_OPT.FLM -FS11FF00000 -FL11000 -FP1($$Device:HT32F12366$ARM\Flash\HT32F_OPT.FLM) + + + 0 + UL2CM3 + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN2 -FF0HT32F -FS00 -FL0100000 -FF1HT32F_OPT -FS11FF00000 -FL11000 -FP0($$Device:HT32F12366$ARM\Flash\HT32F.FLM) -FP1($$Device:HT32F12366$ARM\Flash\HT32F_OPT.FLM)) + + + + + 0 + + + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + Source Group 1 + 0 + 0 + 0 + 0 + + + diff --git a/bsp/ht32/ht32f12366/template.uvprojx b/bsp/ht32/ht32f12366/template.uvprojx new file mode 100644 index 0000000000..9b24487b53 --- /dev/null +++ b/bsp/ht32/ht32f12366/template.uvprojx @@ -0,0 +1,392 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + rt-thread + 0x4 + ARM-ADS + 5060422::V5.06 update 4 (build 422)::ARMCC + + + HT32F12366 + Holtek + Holtek.HT32_DFP.1.0.19 + http://mcu.holtek.com.tw/pack + IRAM(0x20000000,0x20000) IROM(0x00000000,0x3FC00) CPUTYPE("Cortex-M3") CLOCK(12000000) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN2 -FF0HT32F -FS00 -FL0100000 -FF1HT32F_OPT -FS11FF00000 -FL11000 -FP0($$Device:HT32F12366$ARM\Flash\HT32F.FLM) -FP1($$Device:HT32F12366$ARM\Flash\HT32F_OPT.FLM)) + 0 + $$Device:HT32F12366$ARM\INC\Holtek\HT32F1xxxx\ht32f1xxxx_01.h + + + + + + + + + + $$Device:HT32F12366$SVD\HT32F12365_66.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\build\keil\Obj\ + rt-thread + 1 + 0 + 0 + 1 + 1 + .\build\keil\List\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + + DCM.DLL + -pCM3 + SARMCM3.DLL + + TCM.DLL + -pCM3 + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M3" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 8 + 0 + 0 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x20000 + + + 1 + 0x0 + 0x3fc00 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x3fc00 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x20000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 0 + + + + + + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + USE_HT32_CHIP=2 + + + + + + 0 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + .\board\linker_scripts\link.sct + + + + + + + + + + + Source Group 1 + + + + + + + + + + + + diff --git a/bsp/ht32/ht32f52352/.config b/bsp/ht32/ht32f52352/.config new file mode 100644 index 0000000000..cb70b2f90b --- /dev/null +++ b/bsp/ht32/ht32f52352/.config @@ -0,0 +1,1094 @@ +# +# Automatically generated file; DO NOT EDIT. +# RT-Thread Configuration +# + +# +# RT-Thread Kernel +# +CONFIG_RT_NAME_MAX=8 +# CONFIG_RT_USING_ARCH_DATA_TYPE is not set +# CONFIG_RT_USING_SMART is not set +# CONFIG_RT_USING_NANO is not set +# CONFIG_RT_USING_AMP is not set +# CONFIG_RT_USING_SMP is not set +CONFIG_RT_CPUS_NR=1 +CONFIG_RT_ALIGN_SIZE=4 +# CONFIG_RT_THREAD_PRIORITY_8 is not set +CONFIG_RT_THREAD_PRIORITY_32=y +# CONFIG_RT_THREAD_PRIORITY_256 is not set +CONFIG_RT_THREAD_PRIORITY_MAX=32 +CONFIG_RT_TICK_PER_SECOND=1000 +CONFIG_RT_USING_OVERFLOW_CHECK=y +CONFIG_RT_USING_HOOK=y +CONFIG_RT_HOOK_USING_FUNC_PTR=y +# CONFIG_RT_USING_HOOKLIST is not set +CONFIG_RT_USING_IDLE_HOOK=y +CONFIG_RT_IDLE_HOOK_LIST_SIZE=4 +CONFIG_IDLE_THREAD_STACK_SIZE=256 +# CONFIG_RT_USING_TIMER_SOFT is not set + +# +# kservice optimization +# +# CONFIG_RT_KSERVICE_USING_STDLIB is not set +# CONFIG_RT_KSERVICE_USING_TINY_SIZE is not set +# CONFIG_RT_USING_TINY_FFS is not set +# CONFIG_RT_KPRINTF_USING_LONGLONG is not set +CONFIG_RT_USING_DEBUG=y +CONFIG_RT_DEBUGING_COLOR=y +CONFIG_RT_DEBUGING_CONTEXT=y +# CONFIG_RT_DEBUGING_AUTO_INIT is not set + +# +# Inter-Thread communication +# +CONFIG_RT_USING_SEMAPHORE=y +CONFIG_RT_USING_MUTEX=y +CONFIG_RT_USING_EVENT=y +CONFIG_RT_USING_MAILBOX=y +CONFIG_RT_USING_MESSAGEQUEUE=y +# CONFIG_RT_USING_MESSAGEQUEUE_PRIORITY is not set +# CONFIG_RT_USING_SIGNALS is not set + +# +# Memory Management +# +CONFIG_RT_USING_MEMPOOL=y +CONFIG_RT_USING_SMALL_MEM=y +# CONFIG_RT_USING_SLAB is not set +CONFIG_RT_USING_MEMHEAP=y +CONFIG_RT_MEMHEAP_FAST_MODE=y +# CONFIG_RT_MEMHEAP_BEST_MODE is not set +CONFIG_RT_USING_SMALL_MEM_AS_HEAP=y +# CONFIG_RT_USING_MEMHEAP_AS_HEAP is not set +# CONFIG_RT_USING_SLAB_AS_HEAP is not set +# CONFIG_RT_USING_USERHEAP is not set +# CONFIG_RT_USING_NOHEAP is not set +# CONFIG_RT_USING_MEMTRACE is not set +# CONFIG_RT_USING_HEAP_ISR is not set +CONFIG_RT_USING_HEAP=y +CONFIG_RT_USING_DEVICE=y +# CONFIG_RT_USING_DEVICE_OPS is not set +# CONFIG_RT_USING_INTERRUPT_INFO is not set +# CONFIG_RT_USING_THREADSAFE_PRINTF is not set +# CONFIG_RT_USING_SCHED_THREAD_CTX is not set +CONFIG_RT_USING_CONSOLE=y +CONFIG_RT_CONSOLEBUF_SIZE=128 +CONFIG_RT_CONSOLE_DEVICE_NAME="usart1" +CONFIG_RT_VER_NUM=0x50100 +# CONFIG_RT_USING_STDC_ATOMIC is not set +CONFIG_RT_BACKTRACE_LEVEL_MAX_NR=32 +# CONFIG_RT_USING_CACHE is not set +# CONFIG_RT_USING_HW_ATOMIC is not set +# CONFIG_ARCH_ARM_BOOTWITH_FLUSH_CACHE is not set +# CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set +# CONFIG_RT_USING_CPU_FFS is not set +CONFIG_ARCH_ARM=y +CONFIG_ARCH_ARM_CORTEX_M=y +CONFIG_ARCH_ARM_CORTEX_M0=y + +# +# RT-Thread Components +# +CONFIG_RT_USING_COMPONENTS_INIT=y +CONFIG_RT_USING_USER_MAIN=y +CONFIG_RT_MAIN_THREAD_STACK_SIZE=2048 +CONFIG_RT_MAIN_THREAD_PRIORITY=10 +# CONFIG_RT_USING_LEGACY is not set +CONFIG_RT_USING_MSH=y +CONFIG_RT_USING_FINSH=y +CONFIG_FINSH_USING_MSH=y +CONFIG_FINSH_THREAD_NAME="tshell" +CONFIG_FINSH_THREAD_PRIORITY=20 +CONFIG_FINSH_THREAD_STACK_SIZE=4096 +CONFIG_FINSH_USING_HISTORY=y +CONFIG_FINSH_HISTORY_LINES=5 +CONFIG_FINSH_USING_SYMTAB=y +CONFIG_FINSH_CMD_SIZE=80 +CONFIG_MSH_USING_BUILT_IN_COMMANDS=y +CONFIG_FINSH_USING_DESCRIPTION=y +# CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set +# CONFIG_FINSH_USING_AUTH is not set +CONFIG_FINSH_ARG_MAX=10 +CONFIG_FINSH_USING_OPTION_COMPLETION=y + +# +# DFS: device virtual file system +# +# CONFIG_RT_USING_DFS is not set +# CONFIG_RT_USING_FAL is not set + +# +# Device Drivers +# +# CONFIG_RT_USING_DM is not set +CONFIG_RT_USING_DEVICE_IPC=y +CONFIG_RT_UNAMED_PIPE_NUMBER=64 +# CONFIG_RT_USING_SYSTEM_WORKQUEUE is not set +CONFIG_RT_USING_SERIAL=y +CONFIG_RT_USING_SERIAL_V1=y +# CONFIG_RT_USING_SERIAL_V2 is not set +CONFIG_RT_SERIAL_USING_DMA=y +CONFIG_RT_SERIAL_RB_BUFSZ=64 +# CONFIG_RT_USING_CAN is not set +# CONFIG_RT_USING_CPUTIME is not set +CONFIG_RT_USING_I2C=y +# CONFIG_RT_I2C_DEBUG is not set +CONFIG_RT_USING_I2C_BITOPS=y +# CONFIG_RT_I2C_BITOPS_DEBUG is not set +# CONFIG_RT_USING_SOFT_I2C is not set +# CONFIG_RT_USING_PHY is not set +# CONFIG_RT_USING_ADC is not set +# CONFIG_RT_USING_DAC is not set +# CONFIG_RT_USING_NULL is not set +# CONFIG_RT_USING_ZERO is not set +# CONFIG_RT_USING_RANDOM is not set +# CONFIG_RT_USING_PWM is not set +# CONFIG_RT_USING_MTD_NOR is not set +# CONFIG_RT_USING_MTD_NAND is not set +# CONFIG_RT_USING_PM is not set +# CONFIG_RT_USING_RTC is not set +# CONFIG_RT_USING_SDIO is not set +CONFIG_RT_USING_SPI=y +# CONFIG_RT_USING_SPI_BITOPS is not set +# CONFIG_RT_USING_QSPI is not set +# CONFIG_RT_USING_SPI_MSD is not set +# CONFIG_RT_USING_SFUD is not set +# CONFIG_RT_USING_ENC28J60 is not set +# CONFIG_RT_USING_SPI_WIFI is not set +# CONFIG_RT_USING_WDT is not set +# CONFIG_RT_USING_AUDIO is not set +# CONFIG_RT_USING_SENSOR is not set +# CONFIG_RT_USING_TOUCH is not set +# CONFIG_RT_USING_LCD is not set +# CONFIG_RT_USING_HWCRYPTO is not set +# CONFIG_RT_USING_PULSE_ENCODER is not set +# CONFIG_RT_USING_INPUT_CAPTURE is not set +# CONFIG_RT_USING_DEV_BUS is not set +# CONFIG_RT_USING_WIFI is not set +# CONFIG_RT_USING_VIRTIO is not set +CONFIG_RT_USING_PIN=y +# CONFIG_RT_USING_KTIME is not set +# CONFIG_RT_USING_HWTIMER is not set + +# +# Using USB +# +# CONFIG_RT_USING_USB is not set +# CONFIG_RT_USING_USB_HOST is not set +# CONFIG_RT_USING_USB_DEVICE is not set + +# +# C/C++ and POSIX layer +# + +# +# ISO-ANSI C layer +# + +# +# Timezone and Daylight Saving Time +# +# CONFIG_RT_LIBC_USING_FULL_TZ_DST is not set +CONFIG_RT_LIBC_USING_LIGHT_TZ_DST=y +CONFIG_RT_LIBC_TZ_DEFAULT_HOUR=8 +CONFIG_RT_LIBC_TZ_DEFAULT_MIN=0 +CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 + +# +# POSIX (Portable Operating System Interface) layer +# +# CONFIG_RT_USING_POSIX_FS is not set +# CONFIG_RT_USING_POSIX_DELAY is not set +# CONFIG_RT_USING_POSIX_CLOCK is not set +# CONFIG_RT_USING_POSIX_TIMER is not set +# CONFIG_RT_USING_PTHREADS is not set +# CONFIG_RT_USING_MODULE is not set + +# +# Interprocess Communication (IPC) +# +# CONFIG_RT_USING_POSIX_PIPE is not set +# CONFIG_RT_USING_POSIX_MESSAGE_QUEUE is not set +# CONFIG_RT_USING_POSIX_MESSAGE_SEMAPHORE is not set + +# +# Socket is in the 'Network' category +# +# CONFIG_RT_USING_CPLUSPLUS is not set + +# +# Network +# +# CONFIG_RT_USING_SAL is not set +# CONFIG_RT_USING_NETDEV is not set +# CONFIG_RT_USING_LWIP is not set +# CONFIG_RT_USING_AT is not set + +# +# Memory protection +# +# CONFIG_RT_USING_MEM_PROTECTION is not set +# CONFIG_RT_USING_HW_STACK_GUARD is not set + +# +# Utilities +# +# CONFIG_RT_USING_RYM is not set +# CONFIG_RT_USING_ULOG is not set +# CONFIG_RT_USING_UTEST is not set +# CONFIG_RT_USING_VAR_EXPORT is not set +# CONFIG_RT_USING_RESOURCE_ID is not set +# CONFIG_RT_USING_ADT is not set +# CONFIG_RT_USING_RT_LINK is not set +# CONFIG_RT_USING_VBUS is not set + +# +# RT-Thread Utestcases +# +# CONFIG_RT_USING_UTESTCASES is not set + +# +# RT-Thread online packages +# + +# +# IoT - internet of things +# +# CONFIG_PKG_USING_LWIP is not set +# CONFIG_PKG_USING_LORAWAN_DRIVER is not set +# CONFIG_PKG_USING_PAHOMQTT is not set +# CONFIG_PKG_USING_UMQTT is not set +# CONFIG_PKG_USING_WEBCLIENT is not set +# CONFIG_PKG_USING_WEBNET is not set +# CONFIG_PKG_USING_MONGOOSE is not set +# CONFIG_PKG_USING_MYMQTT is not set +# CONFIG_PKG_USING_KAWAII_MQTT is not set +# CONFIG_PKG_USING_BC28_MQTT is not set +# CONFIG_PKG_USING_WEBTERMINAL is not set +# CONFIG_PKG_USING_FREEMODBUS is not set +# CONFIG_PKG_USING_NANOPB is not set + +# +# Wi-Fi +# + +# +# Marvell WiFi +# +# CONFIG_PKG_USING_WLANMARVELL is not set + +# +# Wiced WiFi +# +# CONFIG_PKG_USING_WLAN_WICED is not set +# CONFIG_PKG_USING_RW007 is not set + +# +# CYW43012 WiFi +# +# CONFIG_PKG_USING_WLAN_CYW43012 is not set + +# +# BL808 WiFi +# +# CONFIG_PKG_USING_WLAN_BL808 is not set + +# +# CYW43439 WiFi +# +# CONFIG_PKG_USING_WLAN_CYW43439 is not set +# CONFIG_PKG_USING_COAP is not set +# CONFIG_PKG_USING_NOPOLL is not set +# CONFIG_PKG_USING_NETUTILS is not set +# CONFIG_PKG_USING_CMUX is not set +# CONFIG_PKG_USING_PPP_DEVICE is not set +# CONFIG_PKG_USING_AT_DEVICE is not set +# CONFIG_PKG_USING_ATSRV_SOCKET is not set +# CONFIG_PKG_USING_WIZNET is not set +# CONFIG_PKG_USING_ZB_COORDINATOR is not set + +# +# IoT Cloud +# +# CONFIG_PKG_USING_ONENET is not set +# CONFIG_PKG_USING_GAGENT_CLOUD is not set +# CONFIG_PKG_USING_ALI_IOTKIT is not set +# CONFIG_PKG_USING_AZURE is not set +# CONFIG_PKG_USING_TENCENT_IOT_EXPLORER is not set +# CONFIG_PKG_USING_JIOT-C-SDK is not set +# CONFIG_PKG_USING_UCLOUD_IOT_SDK is not set +# CONFIG_PKG_USING_JOYLINK is not set +# CONFIG_PKG_USING_IOTSHARP_SDK is not set +# CONFIG_PKG_USING_NIMBLE is not set +# CONFIG_PKG_USING_LLSYNC_SDK_ADAPTER is not set +# CONFIG_PKG_USING_OTA_DOWNLOADER is not set +# CONFIG_PKG_USING_IPMSG is not set +# CONFIG_PKG_USING_LSSDP is not set +# CONFIG_PKG_USING_AIRKISS_OPEN is not set +# CONFIG_PKG_USING_LIBRWS is not set +# CONFIG_PKG_USING_TCPSERVER is not set +# CONFIG_PKG_USING_PROTOBUF_C is not set +# CONFIG_PKG_USING_DLT645 is not set +# CONFIG_PKG_USING_QXWZ is not set +# CONFIG_PKG_USING_SMTP_CLIENT is not set +# CONFIG_PKG_USING_ABUP_FOTA is not set +# CONFIG_PKG_USING_LIBCURL2RTT is not set +# CONFIG_PKG_USING_CAPNP is not set +# CONFIG_PKG_USING_AGILE_TELNET is not set +# CONFIG_PKG_USING_NMEALIB is not set +# CONFIG_PKG_USING_PDULIB is not set +# CONFIG_PKG_USING_BTSTACK is not set +# CONFIG_PKG_USING_BT_CYW43012 is not set +# CONFIG_PKG_USING_CYW43XX is not set +# CONFIG_PKG_USING_LORAWAN_ED_STACK is not set +# CONFIG_PKG_USING_WAYZ_IOTKIT is not set +# CONFIG_PKG_USING_MAVLINK is not set +# CONFIG_PKG_USING_BSAL is not set +# CONFIG_PKG_USING_AGILE_MODBUS is not set +# CONFIG_PKG_USING_AGILE_FTP is not set +# CONFIG_PKG_USING_EMBEDDEDPROTO is not set +# CONFIG_PKG_USING_RT_LINK_HW is not set +# CONFIG_PKG_USING_RYANMQTT is not set +# CONFIG_PKG_USING_RYANW5500 is not set +# CONFIG_PKG_USING_LORA_PKT_FWD is not set +# CONFIG_PKG_USING_LORA_GW_DRIVER_LIB is not set +# CONFIG_PKG_USING_LORA_PKT_SNIFFER is not set +# CONFIG_PKG_USING_HM is not set +# CONFIG_PKG_USING_SMALL_MODBUS is not set +# CONFIG_PKG_USING_NET_SERVER is not set +# CONFIG_PKG_USING_ZFTP is not set +# CONFIG_PKG_USING_WOL is not set +# CONFIG_PKG_USING_ZEPHYR_POLLING is not set +# CONFIG_PKG_USING_MATTER_ADAPTATION_LAYER is not set +# CONFIG_PKG_USING_LHC_MODBUS is not set + +# +# security packages +# +# CONFIG_PKG_USING_MBEDTLS is not set +# CONFIG_PKG_USING_LIBSODIUM is not set +# CONFIG_PKG_USING_LIBHYDROGEN is not set +# CONFIG_PKG_USING_TINYCRYPT is not set +# CONFIG_PKG_USING_TFM is not set +# CONFIG_PKG_USING_YD_CRYPTO is not set + +# +# language packages +# + +# +# JSON: JavaScript Object Notation, a lightweight data-interchange format +# +# CONFIG_PKG_USING_CJSON is not set +# CONFIG_PKG_USING_LJSON is not set +# CONFIG_PKG_USING_RT_CJSON_TOOLS is not set +# CONFIG_PKG_USING_RAPIDJSON is not set +# CONFIG_PKG_USING_JSMN is not set +# CONFIG_PKG_USING_AGILE_JSMN is not set +# CONFIG_PKG_USING_PARSON is not set + +# +# XML: Extensible Markup Language +# +# CONFIG_PKG_USING_SIMPLE_XML is not set +# CONFIG_PKG_USING_EZXML is not set +# CONFIG_PKG_USING_LUATOS_SOC is not set +# CONFIG_PKG_USING_LUA is not set +# CONFIG_PKG_USING_JERRYSCRIPT is not set +# CONFIG_PKG_USING_MICROPYTHON is not set +# CONFIG_PKG_USING_PIKASCRIPT is not set +# CONFIG_PKG_USING_RTT_RUST is not set + +# +# multimedia packages +# + +# +# LVGL: powerful and easy-to-use embedded GUI library +# +# CONFIG_PKG_USING_LVGL is not set +# CONFIG_PKG_USING_LV_MUSIC_DEMO is not set +# CONFIG_PKG_USING_GUI_GUIDER_DEMO is not set + +# +# u8g2: a monochrome graphic library +# +# CONFIG_PKG_USING_U8G2_OFFICIAL is not set +# CONFIG_PKG_USING_U8G2 is not set +# CONFIG_PKG_USING_OPENMV is not set +# CONFIG_PKG_USING_MUPDF is not set +# CONFIG_PKG_USING_STEMWIN is not set +# CONFIG_PKG_USING_WAVPLAYER is not set +# CONFIG_PKG_USING_TJPGD is not set +# CONFIG_PKG_USING_PDFGEN is not set +# CONFIG_PKG_USING_HELIX is not set +# CONFIG_PKG_USING_AZUREGUIX is not set +# CONFIG_PKG_USING_TOUCHGFX2RTT is not set +# CONFIG_PKG_USING_NUEMWIN is not set +# CONFIG_PKG_USING_MP3PLAYER is not set +# CONFIG_PKG_USING_TINYJPEG is not set +# CONFIG_PKG_USING_UGUI is not set +# CONFIG_PKG_USING_MCURSES is not set +# CONFIG_PKG_USING_TERMBOX is not set +# CONFIG_PKG_USING_VT100 is not set +# CONFIG_PKG_USING_QRCODE is not set +# CONFIG_PKG_USING_GUIENGINE is not set +# CONFIG_PKG_USING_3GPP_AMRNB is not set + +# +# tools packages +# +# CONFIG_PKG_USING_CMBACKTRACE is not set +# CONFIG_PKG_USING_EASYFLASH is not set +# CONFIG_PKG_USING_EASYLOGGER is not set +# CONFIG_PKG_USING_SYSTEMVIEW is not set +# CONFIG_PKG_USING_SEGGER_RTT is not set +# CONFIG_PKG_USING_RTT_AUTO_EXE_CMD is not set +# CONFIG_PKG_USING_RDB is not set +# CONFIG_PKG_USING_ULOG_EASYFLASH is not set +# CONFIG_PKG_USING_LOGMGR is not set +# CONFIG_PKG_USING_ADBD is not set +# CONFIG_PKG_USING_COREMARK is not set +# CONFIG_PKG_USING_DHRYSTONE is not set +# CONFIG_PKG_USING_MEMORYPERF is not set +# CONFIG_PKG_USING_NR_MICRO_SHELL is not set +# CONFIG_PKG_USING_CHINESE_FONT_LIBRARY is not set +# CONFIG_PKG_USING_LUNAR_CALENDAR is not set +# CONFIG_PKG_USING_BS8116A is not set +# CONFIG_PKG_USING_GPS_RMC is not set +# CONFIG_PKG_USING_URLENCODE is not set +# CONFIG_PKG_USING_UMCN is not set +# CONFIG_PKG_USING_LWRB2RTT is not set +# CONFIG_PKG_USING_CPU_USAGE is not set +# CONFIG_PKG_USING_GBK2UTF8 is not set +# CONFIG_PKG_USING_VCONSOLE is not set +# CONFIG_PKG_USING_KDB is not set +# CONFIG_PKG_USING_WAMR is not set +# CONFIG_PKG_USING_MICRO_XRCE_DDS_CLIENT is not set +# CONFIG_PKG_USING_LWLOG is not set +# CONFIG_PKG_USING_ANV_TRACE is not set +# CONFIG_PKG_USING_ANV_MEMLEAK is not set +# CONFIG_PKG_USING_ANV_TESTSUIT is not set +# CONFIG_PKG_USING_ANV_BENCH is not set +# CONFIG_PKG_USING_DEVMEM is not set +# CONFIG_PKG_USING_REGEX is not set +# CONFIG_PKG_USING_MEM_SANDBOX is not set +# CONFIG_PKG_USING_SOLAR_TERMS is not set +# CONFIG_PKG_USING_GAN_ZHI is not set +# CONFIG_PKG_USING_FDT is not set +# CONFIG_PKG_USING_CBOX is not set +# CONFIG_PKG_USING_SNOWFLAKE is not set +# CONFIG_PKG_USING_HASH_MATCH is not set +# CONFIG_PKG_USING_ARMV7M_DWT_TOOL is not set +# CONFIG_PKG_USING_VOFA_PLUS is not set +# CONFIG_PKG_USING_RT_TRACE is not set +# CONFIG_PKG_USING_ZDEBUG is not set + +# +# system packages +# + +# +# enhanced kernel services +# +# CONFIG_PKG_USING_RT_MEMCPY_CM is not set +# CONFIG_PKG_USING_RT_KPRINTF_THREADSAFE is not set +# CONFIG_PKG_USING_RT_VSNPRINTF_FULL is not set + +# +# acceleration: Assembly language or algorithmic acceleration packages +# +# CONFIG_PKG_USING_QFPLIB_M0_FULL is not set +# CONFIG_PKG_USING_QFPLIB_M0_TINY is not set +# CONFIG_PKG_USING_QFPLIB_M3 is not set + +# +# CMSIS: ARM Cortex-M Microcontroller Software Interface Standard +# +# CONFIG_PKG_USING_CMSIS_5 is not set +# CONFIG_PKG_USING_CMSIS_CORE is not set +# CONFIG_PKG_USING_CMSIS_DSP is not set +# CONFIG_PKG_USING_CMSIS_NN is not set +# CONFIG_PKG_USING_CMSIS_RTOS1 is not set +# CONFIG_PKG_USING_CMSIS_RTOS2 is not set + +# +# Micrium: Micrium software products porting for RT-Thread +# +# CONFIG_PKG_USING_UCOSIII_WRAPPER is not set +# CONFIG_PKG_USING_UCOSII_WRAPPER is not set +# CONFIG_PKG_USING_UC_CRC is not set +# CONFIG_PKG_USING_UC_CLK is not set +# CONFIG_PKG_USING_UC_COMMON is not set +# CONFIG_PKG_USING_UC_MODBUS is not set +# CONFIG_PKG_USING_FREERTOS_WRAPPER is not set +# CONFIG_PKG_USING_LITEOS_SDK is not set +# CONFIG_PKG_USING_TZ_DATABASE is not set +# CONFIG_PKG_USING_CAIRO is not set +# CONFIG_PKG_USING_PIXMAN is not set +# CONFIG_PKG_USING_PARTITION is not set +# CONFIG_PKG_USING_PERF_COUNTER is not set +# CONFIG_PKG_USING_FILEX is not set +# CONFIG_PKG_USING_LEVELX is not set +# CONFIG_PKG_USING_FLASHDB is not set +# CONFIG_PKG_USING_SQLITE is not set +# CONFIG_PKG_USING_RTI is not set +# CONFIG_PKG_USING_DFS_YAFFS is not set +# CONFIG_PKG_USING_LITTLEFS is not set +# CONFIG_PKG_USING_DFS_JFFS2 is not set +# CONFIG_PKG_USING_DFS_UFFS is not set +# CONFIG_PKG_USING_LWEXT4 is not set +# CONFIG_PKG_USING_THREAD_POOL is not set +# CONFIG_PKG_USING_ROBOTS is not set +# CONFIG_PKG_USING_EV is not set +# CONFIG_PKG_USING_SYSWATCH is not set +# CONFIG_PKG_USING_SYS_LOAD_MONITOR is not set +# CONFIG_PKG_USING_PLCCORE is not set +# CONFIG_PKG_USING_RAMDISK is not set +# CONFIG_PKG_USING_MININI is not set +# CONFIG_PKG_USING_QBOOT is not set +# CONFIG_PKG_USING_PPOOL is not set +# CONFIG_PKG_USING_OPENAMP is not set +# CONFIG_PKG_USING_RPMSG_LITE is not set +# CONFIG_PKG_USING_LPM is not set +# CONFIG_PKG_USING_TLSF is not set +# CONFIG_PKG_USING_EVENT_RECORDER is not set +# CONFIG_PKG_USING_ARM_2D is not set +# CONFIG_PKG_USING_MCUBOOT is not set +# CONFIG_PKG_USING_TINYUSB is not set +# CONFIG_PKG_USING_CHERRYUSB is not set +# CONFIG_PKG_USING_KMULTI_RTIMER is not set +# CONFIG_PKG_USING_TFDB is not set +# CONFIG_PKG_USING_QPC is not set +# CONFIG_PKG_USING_AGILE_UPGRADE is not set +# CONFIG_PKG_USING_FLASH_BLOB is not set +# CONFIG_PKG_USING_MLIBC is not set +# CONFIG_PKG_USING_TASK_MSG_BUS is not set +# CONFIG_PKG_USING_SFDB is not set +# CONFIG_PKG_USING_RTP is not set +# CONFIG_PKG_USING_REB is not set +# CONFIG_PKG_USING_R_RHEALSTONE is not set + +# +# peripheral libraries and drivers +# + +# +# HAL & SDK Drivers +# + +# +# STM32 HAL & SDK Drivers +# +# CONFIG_PKG_USING_STM32L4XX_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32WB55_SDK is not set +# CONFIG_PKG_USING_STM32_SDIO is not set +# CONFIG_PKG_USING_BLUETRUM_SDK is not set +# CONFIG_PKG_USING_EMBARC_BSP is not set +# CONFIG_PKG_USING_ESP_IDF is not set + +# +# Kendryte SDK +# +# CONFIG_PKG_USING_K210_SDK is not set +# CONFIG_PKG_USING_KENDRYTE_SDK is not set +# CONFIG_PKG_USING_NRF5X_SDK is not set +# CONFIG_PKG_USING_NRFX is not set +# CONFIG_PKG_USING_RASPBERRYPI_PICO_SDK is not set + +# +# sensors drivers +# +# CONFIG_PKG_USING_LSM6DSM is not set +# CONFIG_PKG_USING_LSM6DSL is not set +# CONFIG_PKG_USING_LPS22HB is not set +# CONFIG_PKG_USING_HTS221 is not set +# CONFIG_PKG_USING_LSM303AGR is not set +# CONFIG_PKG_USING_BME280 is not set +# CONFIG_PKG_USING_BME680 is not set +# CONFIG_PKG_USING_BMA400 is not set +# CONFIG_PKG_USING_BMI160_BMX160 is not set +# CONFIG_PKG_USING_SPL0601 is not set +# CONFIG_PKG_USING_MS5805 is not set +# CONFIG_PKG_USING_DA270 is not set +# CONFIG_PKG_USING_DF220 is not set +# CONFIG_PKG_USING_HSHCAL001 is not set +# CONFIG_PKG_USING_BH1750 is not set +# CONFIG_PKG_USING_MPU6XXX is not set +# CONFIG_PKG_USING_AHT10 is not set +# CONFIG_PKG_USING_AP3216C is not set +# CONFIG_PKG_USING_TSL4531 is not set +# CONFIG_PKG_USING_DS18B20 is not set +# CONFIG_PKG_USING_DHT11 is not set +# CONFIG_PKG_USING_DHTXX is not set +# CONFIG_PKG_USING_GY271 is not set +# CONFIG_PKG_USING_GP2Y10 is not set +# CONFIG_PKG_USING_SGP30 is not set +# CONFIG_PKG_USING_HDC1000 is not set +# CONFIG_PKG_USING_BMP180 is not set +# CONFIG_PKG_USING_BMP280 is not set +# CONFIG_PKG_USING_SHTC1 is not set +# CONFIG_PKG_USING_BMI088 is not set +# CONFIG_PKG_USING_HMC5883 is not set +# CONFIG_PKG_USING_MAX6675 is not set +# CONFIG_PKG_USING_TMP1075 is not set +# CONFIG_PKG_USING_SR04 is not set +# CONFIG_PKG_USING_CCS811 is not set +# CONFIG_PKG_USING_PMSXX is not set +# CONFIG_PKG_USING_RT3020 is not set +# CONFIG_PKG_USING_MLX90632 is not set +# CONFIG_PKG_USING_MLX90393 is not set +# CONFIG_PKG_USING_MLX90392 is not set +# CONFIG_PKG_USING_MLX90397 is not set +# CONFIG_PKG_USING_MS5611 is not set +# CONFIG_PKG_USING_MAX31865 is not set +# CONFIG_PKG_USING_VL53L0X is not set +# CONFIG_PKG_USING_INA260 is not set +# CONFIG_PKG_USING_MAX30102 is not set +# CONFIG_PKG_USING_INA226 is not set +# CONFIG_PKG_USING_LIS2DH12 is not set +# CONFIG_PKG_USING_HS300X is not set +# CONFIG_PKG_USING_ZMOD4410 is not set +# CONFIG_PKG_USING_ISL29035 is not set +# CONFIG_PKG_USING_MMC3680KJ is not set +# CONFIG_PKG_USING_QMP6989 is not set +# CONFIG_PKG_USING_BALANCE is not set +# CONFIG_PKG_USING_SHT2X is not set +# CONFIG_PKG_USING_SHT3X is not set +# CONFIG_PKG_USING_SHT4X is not set +# CONFIG_PKG_USING_AD7746 is not set +# CONFIG_PKG_USING_ADT74XX is not set +# CONFIG_PKG_USING_MAX17048 is not set +# CONFIG_PKG_USING_AS7341 is not set +# CONFIG_PKG_USING_CW2015 is not set +# CONFIG_PKG_USING_ICM20608 is not set +# CONFIG_PKG_USING_PAJ7620 is not set +# CONFIG_PKG_USING_STHS34PF80 is not set + +# +# touch drivers +# +# CONFIG_PKG_USING_GT9147 is not set +# CONFIG_PKG_USING_GT1151 is not set +# CONFIG_PKG_USING_GT917S is not set +# CONFIG_PKG_USING_GT911 is not set +# CONFIG_PKG_USING_FT6206 is not set +# CONFIG_PKG_USING_FT5426 is not set +# CONFIG_PKG_USING_FT6236 is not set +# CONFIG_PKG_USING_XPT2046_TOUCH is not set +# CONFIG_PKG_USING_CST816X is not set +# CONFIG_PKG_USING_CST812T is not set +# CONFIG_PKG_USING_REALTEK_AMEBA is not set +# CONFIG_PKG_USING_BUTTON is not set +# CONFIG_PKG_USING_PCF8574 is not set +# CONFIG_PKG_USING_SX12XX is not set +# CONFIG_PKG_USING_SIGNAL_LED is not set +# CONFIG_PKG_USING_LEDBLINK is not set +# CONFIG_PKG_USING_LITTLED is not set +# CONFIG_PKG_USING_LKDGUI is not set +# CONFIG_PKG_USING_INFRARED is not set +# CONFIG_PKG_USING_MULTI_INFRARED is not set +# CONFIG_PKG_USING_AGILE_BUTTON is not set +# CONFIG_PKG_USING_AGILE_LED is not set +# CONFIG_PKG_USING_AT24CXX is not set +# CONFIG_PKG_USING_MOTIONDRIVER2RTT is not set +# CONFIG_PKG_USING_PCA9685 is not set +# CONFIG_PKG_USING_ILI9341 is not set +# CONFIG_PKG_USING_I2C_TOOLS is not set +# CONFIG_PKG_USING_NRF24L01 is not set +# CONFIG_PKG_USING_RPLIDAR is not set +# CONFIG_PKG_USING_AS608 is not set +# CONFIG_PKG_USING_RC522 is not set +# CONFIG_PKG_USING_WS2812B is not set +# CONFIG_PKG_USING_EXTERN_RTC_DRIVERS is not set +# CONFIG_PKG_USING_MULTI_RTIMER is not set +# CONFIG_PKG_USING_MAX7219 is not set +# CONFIG_PKG_USING_BEEP is not set +# CONFIG_PKG_USING_EASYBLINK is not set +# CONFIG_PKG_USING_PMS_SERIES is not set +# CONFIG_PKG_USING_CAN_YMODEM is not set +# CONFIG_PKG_USING_LORA_RADIO_DRIVER is not set +# CONFIG_PKG_USING_QLED is not set +# CONFIG_PKG_USING_AGILE_CONSOLE is not set +# CONFIG_PKG_USING_LD3320 is not set +# CONFIG_PKG_USING_WK2124 is not set +# CONFIG_PKG_USING_LY68L6400 is not set +# CONFIG_PKG_USING_DM9051 is not set +# CONFIG_PKG_USING_SSD1306 is not set +# CONFIG_PKG_USING_QKEY is not set +# CONFIG_PKG_USING_RS485 is not set +# CONFIG_PKG_USING_RS232 is not set +# CONFIG_PKG_USING_NES is not set +# CONFIG_PKG_USING_VIRTUAL_SENSOR is not set +# CONFIG_PKG_USING_VDEVICE is not set +# CONFIG_PKG_USING_SGM706 is not set +# CONFIG_PKG_USING_RDA58XX is not set +# CONFIG_PKG_USING_LIBNFC is not set +# CONFIG_PKG_USING_MFOC is not set +# CONFIG_PKG_USING_TMC51XX is not set +# CONFIG_PKG_USING_TCA9534 is not set +# CONFIG_PKG_USING_KOBUKI is not set +# CONFIG_PKG_USING_ROSSERIAL is not set +# CONFIG_PKG_USING_MICRO_ROS is not set +# CONFIG_PKG_USING_MCP23008 is not set +# CONFIG_PKG_USING_MISAKA_AT24CXX is not set +# CONFIG_PKG_USING_MISAKA_RGB_BLING is not set +# CONFIG_PKG_USING_LORA_MODEM_DRIVER is not set +# CONFIG_PKG_USING_SOFT_SERIAL is not set +# CONFIG_PKG_USING_MB85RS16 is not set +# CONFIG_PKG_USING_RFM300 is not set +# CONFIG_PKG_USING_IO_INPUT_FILTER is not set +# CONFIG_PKG_USING_LRF_NV7LIDAR is not set +# CONFIG_PKG_USING_AIP650 is not set +# CONFIG_PKG_USING_FINGERPRINT is not set +# CONFIG_PKG_USING_BT_ECB02C is not set +# CONFIG_PKG_USING_UAT is not set +# CONFIG_PKG_USING_ST7789 is not set +# CONFIG_PKG_USING_VS1003 is not set +# CONFIG_PKG_USING_X9555 is not set +# CONFIG_PKG_USING_SYSTEM_RUN_LED is not set +# CONFIG_PKG_USING_BT_MX01 is not set +# CONFIG_PKG_USING_RGPOWER is not set +# CONFIG_PKG_USING_SPI_TOOLS is not set + +# +# AI packages +# +# CONFIG_PKG_USING_LIBANN is not set +# CONFIG_PKG_USING_NNOM is not set +# CONFIG_PKG_USING_ONNX_BACKEND is not set +# CONFIG_PKG_USING_ONNX_PARSER is not set +# CONFIG_PKG_USING_TENSORFLOWLITEMICRO is not set +# CONFIG_PKG_USING_ELAPACK is not set +# CONFIG_PKG_USING_ULAPACK is not set +# CONFIG_PKG_USING_QUEST is not set +# CONFIG_PKG_USING_NAXOS is not set +# CONFIG_PKG_USING_R_TINYMAIX is not set + +# +# Signal Processing and Control Algorithm Packages +# +# CONFIG_PKG_USING_FIRE_PID_CURVE is not set +# CONFIG_PKG_USING_QPID is not set +# CONFIG_PKG_USING_UKAL is not set +# CONFIG_PKG_USING_DIGITALCTRL is not set +# CONFIG_PKG_USING_KISSFFT is not set + +# +# miscellaneous packages +# + +# +# project laboratory +# + +# +# samples: kernel and components samples +# +# CONFIG_PKG_USING_KERNEL_SAMPLES is not set +# CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set +# CONFIG_PKG_USING_NETWORK_SAMPLES is not set +# CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set + +# +# entertainment: terminal games and other interesting software packages +# +# CONFIG_PKG_USING_CMATRIX is not set +# CONFIG_PKG_USING_SL is not set +# CONFIG_PKG_USING_CAL is not set +# CONFIG_PKG_USING_ACLOCK is not set +# CONFIG_PKG_USING_THREES is not set +# CONFIG_PKG_USING_2048 is not set +# CONFIG_PKG_USING_SNAKE is not set +# CONFIG_PKG_USING_TETRIS is not set +# CONFIG_PKG_USING_DONUT is not set +# CONFIG_PKG_USING_COWSAY is not set +# CONFIG_PKG_USING_MORSE is not set +# CONFIG_PKG_USING_TINYSQUARE is not set +# CONFIG_PKG_USING_LIBCSV is not set +# CONFIG_PKG_USING_OPTPARSE is not set +# CONFIG_PKG_USING_FASTLZ is not set +# CONFIG_PKG_USING_MINILZO is not set +# CONFIG_PKG_USING_QUICKLZ is not set +# CONFIG_PKG_USING_LZMA is not set +# CONFIG_PKG_USING_RALARAM is not set +# CONFIG_PKG_USING_MULTIBUTTON is not set +# CONFIG_PKG_USING_FLEXIBLE_BUTTON is not set +# CONFIG_PKG_USING_CANFESTIVAL is not set +# CONFIG_PKG_USING_ZLIB is not set +# CONFIG_PKG_USING_MINIZIP is not set +# CONFIG_PKG_USING_HEATSHRINK is not set +# CONFIG_PKG_USING_DSTR is not set +# CONFIG_PKG_USING_TINYFRAME is not set +# CONFIG_PKG_USING_KENDRYTE_DEMO is not set +# CONFIG_PKG_USING_UPACKER is not set +# CONFIG_PKG_USING_UPARAM is not set +# CONFIG_PKG_USING_HELLO is not set +# CONFIG_PKG_USING_VI is not set +# CONFIG_PKG_USING_KI is not set +# CONFIG_PKG_USING_ARMv7M_DWT is not set +# CONFIG_PKG_USING_CRCLIB is not set +# CONFIG_PKG_USING_LWGPS is not set +# CONFIG_PKG_USING_STATE_MACHINE is not set +# CONFIG_PKG_USING_DESIGN_PATTERN is not set +# CONFIG_PKG_USING_CONTROLLER is not set +# CONFIG_PKG_USING_PHASE_LOCKED_LOOP is not set +# CONFIG_PKG_USING_MFBD is not set +# CONFIG_PKG_USING_SLCAN2RTT is not set +# CONFIG_PKG_USING_SOEM is not set +# CONFIG_PKG_USING_QPARAM is not set +# CONFIG_PKG_USING_CorevMCU_CLI is not set + +# +# Arduino libraries +# +# CONFIG_PKG_USING_RTDUINO is not set + +# +# Projects and Demos +# +# CONFIG_PKG_USING_ARDUINO_MSGQ_C_CPP_DEMO is not set +# CONFIG_PKG_USING_ARDUINO_SKETCH_LOADER_DEMO is not set +# CONFIG_PKG_USING_ARDUINO_ULTRASOUND_RADAR is not set +# CONFIG_PKG_USING_ARDUINO_NINEINONE_SENSOR_SHIELD is not set +# CONFIG_PKG_USING_ARDUINO_SENSOR_KIT is not set +# CONFIG_PKG_USING_ARDUINO_MATLAB_SUPPORT is not set + +# +# Sensors +# +# CONFIG_PKG_USING_ARDUINO_SENSOR_DEVICE_DRIVERS is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SENSOR is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SENSORLAB is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL375 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL53L0X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL53L1X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL6180X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX31855 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX31865 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX31856 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX6675 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90614 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM9DS1 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AHTX0 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM9DS0 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP280 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADT7410 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP085 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BME680 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP9808 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP4728 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_INA219 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LTR390 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL345 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DHT is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP9600 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM6DS is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO055 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX1704X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MMC56X3 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90393 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90395 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ICM20X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DPS310 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTS221 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SHT4X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SHT31 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL343 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BME280 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AS726X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AMG88XX is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AM2320 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AM2315 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LTR329_LTR303 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP085_UNIFIED is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP183 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP183_UNIFIED is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP3XX is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MS8607 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS3MDL is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90640 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MMA8451 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MSA301 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPL115A2 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO08X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO08X_RVC is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS2MDL is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM303DLH_MAG is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LC709203F is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_CAP1188 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_CCS811 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_NAU7802 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS331 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LPS2X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LPS35HW is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM303_ACCEL is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS3DH is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCF8591 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPL3115A2 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPR121 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPRLS is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPU6050 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCT2075 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PM25AQI is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_EMC2101 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_FXAS21002C is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SCD30 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_FXOS8700 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HMC5883_UNIFIED is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SGP30 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP006 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TLA202X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TCS34725 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI7021 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI1145 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SGP40 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SHTC3 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HDC1000 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTU21DF is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AS7341 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTU31D is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_INA260 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP007_LIBRARY is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_L3GD20 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP117 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TSC2007 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TSL2561 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TSL2591_LIBRARY is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VCNL4040 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML6070 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML6075 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML7700 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_LIS3DHTR is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_DHT is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_ADXL335 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_ADXL345 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_BME280 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_BMP280 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_H3LIS331DL is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_MMA7660 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_TSL2561 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_PAJ7620 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_VL53L0X is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_ITG3200 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_SHT31 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_HP20X is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_DRV2605L is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_BBM150 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_HMC5883L is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_LSM303DLH is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_TCS3414CS is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_MP503 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_BMP085 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_HIGHTEMP is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_VEML6070 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_SI1145 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_SHT35 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_AT42QT1070 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_LSM6DS3 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_HDC1000 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_HM3301 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_MCP9600 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_LTC2941 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_LDC1612 is not set +# CONFIG_PKG_USING_ARDUINO_CAPACITIVESENSOR is not set +# CONFIG_PKG_USING_ARDUINO_JARZEBSKI_MPU6050 is not set + +# +# Display +# +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_GFX_LIBRARY is not set +# CONFIG_PKG_USING_ARDUINO_U8G2 is not set +# CONFIG_PKG_USING_ARDUINO_TFT_ESPI is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ST7735 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SSD1306 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ILI9341 is not set +# CONFIG_PKG_USING_SEEED_TM1637 is not set + +# +# Timing +# +# CONFIG_PKG_USING_ARDUINO_RTCLIB is not set +# CONFIG_PKG_USING_ARDUINO_MSTIMER2 is not set +# CONFIG_PKG_USING_ARDUINO_TICKER is not set +# CONFIG_PKG_USING_ARDUINO_TASKSCHEDULER is not set + +# +# Data Processing +# +# CONFIG_PKG_USING_ARDUINO_KALMANFILTER is not set +# CONFIG_PKG_USING_ARDUINO_ARDUINOJSON is not set +# CONFIG_PKG_USING_ARDUINO_TENSORFLOW_LITE_MICRO is not set +# CONFIG_PKG_USING_ARDUINO_RUNNINGMEDIAN is not set + +# +# Data Storage +# + +# +# Communication +# +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PN532 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI4713 is not set + +# +# Device Control +# +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCF8574 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCA9685 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TPA2016 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DRV2605 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DS1841 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DS3502 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_PCF85063TP is not set + +# +# Other +# +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MFRC630 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI5351 is not set + +# +# Signal IO +# +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BUSIO is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TCA8418 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP23017 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADS1X15 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AW9523 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP3008 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP4725 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BD3491FS is not set + +# +# Uncategorized +# +CONFIG_SOC_FAMILY_HT32=y +CONFIG_SOC_SERIES_HT32F5=y + +# +# Hardware Drivers Config +# +CONFIG_SOC_HT32F52352=y + +# +# Onboard Peripheral Drivers +# + +# +# On-chip Peripheral Drivers +# +CONFIG_BSP_USING_GPIO=y +CONFIG_BSP_USING_UART=y +# CONFIG_BSP_USING_USART0 is not set +CONFIG_BSP_USING_USART1=y +# CONFIG_BSP_USING_UART0 is not set +# CONFIG_BSP_USING_UART1 is not set +# CONFIG_BSP_USING_SPI is not set +# CONFIG_BSP_USING_I2C is not set + +# +# Board extended module Drivers +# diff --git a/bsp/ht32/ht32f52352/Kconfig b/bsp/ht32/ht32f52352/Kconfig new file mode 100644 index 0000000000..79b160b856 --- /dev/null +++ b/bsp/ht32/ht32f52352/Kconfig @@ -0,0 +1,21 @@ +mainmenu "RT-Thread Configuration" + +config BSP_DIR + string + option env="BSP_ROOT" + default "." + +config RTT_DIR + string + option env="RTT_ROOT" + default "../../.." + +config PKGS_DIR + string + option env="PKGS_ROOT" + default "packages" + +source "$RTT_DIR/Kconfig" +source "$PKGS_DIR/Kconfig" +source "../libraries/Kconfig" +source "board/Kconfig" diff --git a/bsp/ht32/ht32f52352/README.md b/bsp/ht32/ht32f52352/README.md new file mode 100644 index 0000000000..10644a76a4 --- /dev/null +++ b/bsp/ht32/ht32f52352/README.md @@ -0,0 +1,108 @@ +# HT32F52352 BSP 说明 + +## 简介 + +ESK32-30501是合泰基于HT32F52352芯片并针对Cortex®-M0+入门而设计的评估板。本文档是为ESK32-30501开发板提供的BSP(板级支持包)说明。 + +主要内容如下： + +- 开发板资源介绍 +- BSP 快速上手 +- 进阶使用方法 + +通过阅读快速上手章节开发者可以快速地上手该 BSP，将 RT-Thread 运行在开发板上。 + +## 开发板介绍 + +ESK32-30501使用32位Arm® Cortex®-M0+高性能、低功耗单片机HT32F52352，针对Cortex®-M0+入门而设计。开发板外观如下图所示： + +![board.png](figures/board.png) + +该开发板常用 **板载资源** 如下： + +- MCU：HT32F52352，主频 48MHz，128KB FLASH ，16KB SRAM +- 常用外设 + - LED：2个，（绿色，PC14、PC15） +- 常用接口：USB 转串口 、USB SLAVE +- 调试接口：板载的 e-Link32 Lite SWD 下载 + +开发板更多详细信息请参考合泰官网的相关文档[ESK32-30501](https://www.holtek.com.cn/page/detail/dev_kit/ESK32-30501)。 + +## 外设支持 + +本 BSP 目前对外设的支持情况如下： + +| **板载外设** | **支持情况** | **备注** | +| :--- | :---: | :--- | +| USB 转串口 | 支持 | 使用 USART1 | +| **片上外设** | **支持情况** | **备注** | +| GPIO | 支持 | PA0, PA1...PD3 ---> PIN: 0, 1...51 | +| USART | 支持 | USART0/1 | +| UART | 支持 | UART0/1 | +| SPI | 支持 | SPI0/1 | +| I2C | 支持 | 硬件 I2C0/1 | +| ADC | 暂不支持 | | +| WDT | 暂不支持 | | + +## 使用说明 + +使用说明分为如下两个章节： + +- 快速上手 + + 本章节是为刚接触 RT-Thread 的新手准备的使用说明，遵循简单的步骤即可将 RT-Thread 操作系统运行在该开发板上，看到实验效果 。 + +- 进阶使用 + + 本章节是为需要在 RT-Thread 操作系统上使用更多开发板资源的开发者准备的。通过使用 ENV 工具对 BSP 进行配置，可以开启更多片上资源，实现更多高级功能。 + + +### 快速上手 + +本 BSP 为仅为开发者提供MDK5的工程。下面以 MDK5 开发环境为例，介绍如何将系统运行起来。 + +#### 硬件连接 + +使用数据线通过板载的 e-Link32 Lite将芯片连接到 PC。 + +#### 编译下载 + +双击 project.uvprojx 文件，打开 MDK5 工程，编译并下载程序到开发板。 + +> 注：工程默认配置使用CMSIS-DAP下载方式，在通过 e-Link32 Lite 连接开发板的基础上，点击下载按钮即可下载程序到开发板。 + +#### 运行结果 + +下载程序成功之后，系统会自动运行，观察开发板上 LED 的运行效果，LED1和LED2交替闪烁。 + +连接开发板对应串口到 PC（也可以通过e-Link32 Lite的模拟串口将开发板连接到PC）, 在终端工具里调整好串口配置（115200-8-1-N）并打开相应的串口，复位设备后，可以看到 RT-Thread 的输出信息: + +> 注：由于RT-Thread的finsh控制台使用的是命令行的输入形式，推荐使用串口调试工具如：Tabby terminal 或者 Tera Term。 + +```bash + \ | / +- RT - Thread Operating System + / | \ 5.1.0 build Apr 10 2024 14:39:43 + 2006 - 2024 Copyright by RT-Thread team +msh > +``` + +### 进阶使用 + +此 BSP 默认只开启了 GPIO 和 USART1 的功能，如果需使用更多的片上资源，需要利用 ENV 工具对BSP 进行配置，步骤如下： + +1. 在 bsp 下打开 env 工具。 + +2. 输入`menuconfig`命令配置工程，配置好之后保存退出。 + +3. 输入`scons --target=mdk5` 命令重新生成工程。 + +## 注意事项 + +开发板和芯片的相关资料可以在[合泰官网](https://www.holtek.com.cn/page/index)进行查找和下载，如芯片的数据手册和开发使用手册、开发板的原理图、Keil_v5的pack安装包等。 + +## 联系人信息 + +维护人: + +- [QT-one](https://github.com/QT-one) \ No newline at end of file diff --git a/bsp/ht32/ht32f52352/SConscript b/bsp/ht32/ht32f52352/SConscript new file mode 100644 index 0000000000..682f94215c --- /dev/null +++ b/bsp/ht32/ht32f52352/SConscript @@ -0,0 +1,15 @@ +# for module compiling +import os #包含os库 +Import('RTT_ROOT') #导入RTT_ROOT对象（RTT_ROOT代表的是RT-Thread源码包） +from building import * #把building模块的所有内容都导入到当前模块中 + +cwd = GetCurrentDir() #获取当前路径，并将该路径信息保存到变量cwd中 +objs = [] #创建一个list型变量objs +list = os.listdir(cwd) #得到当前目录下的所有子目录，并保存到变量list中 + +for d in list: #for循环用d记录循环的次数，直到寻遍所有路径 + path = os.path.join(cwd, d) #根据d获取到不同的路径 + if os.path.isfile(os.path.join(path, 'SConscript')): #如果该路径下存在名为SConscript的文件 + objs = objs + SConscript(os.path.join(d, 'SConscript')) #将路径中SConscript文件内的源码读取到objs中 + +Return('objs') #将objs返回出去 diff --git a/bsp/ht32/ht32f52352/SConstruct b/bsp/ht32/ht32f52352/SConstruct new file mode 100644 index 0000000000..9f16ec63d2 --- /dev/null +++ b/bsp/ht32/ht32f52352/SConstruct @@ -0,0 +1,60 @@ +import os +import sys +import rtconfig + +if os.getenv('RTT_ROOT'): + RTT_ROOT = os.getenv('RTT_ROOT') +else: + RTT_ROOT = os.path.normpath(os.getcwd() + '/../../..') + +sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')] +try: + from building import * +except: + print('Cannot found RT-Thread root directory, please check RTT_ROOT') + print(RTT_ROOT) + exit(-1) + +TARGET = 'rt-thread.' + rtconfig.TARGET_EXT + +DefaultEnvironment(tools=[]) +env = Environment(tools = ['mingw'], + AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS, + CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS, + AR = rtconfig.AR, ARFLAGS = '-rc', + CXX = rtconfig.CXX, CXXFLAGS = rtconfig.CXXFLAGS, + LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS) +env.PrependENVPath('PATH', rtconfig.EXEC_PATH) + +if rtconfig.PLATFORM == 'iar': + env.Replace(CCCOM = ['$CC $CCFLAGS $CPPFLAGS $_CPPDEFFLAGS $_CPPINCFLAGS -o $TARGET $SOURCES']) + env.Replace(ARFLAGS = ['']) + env.Replace(LINKCOM = env["LINKCOM"] + ' --map rt-thread.map') + +Export('RTT_ROOT') +Export('rtconfig') + +SDK_ROOT = os.path.abspath('./') + +if os.path.exists(SDK_ROOT + '/libraries'): + libraries_path_prefix = SDK_ROOT + '/libraries' +else: + libraries_path_prefix = os.path.dirname(SDK_ROOT) + '/libraries' + +SDK_LIB = libraries_path_prefix +Export('SDK_LIB') + +# prepare building environment +objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False) + +ht32_library = 'HT32_STD_5xxxx_FWLib' +rtconfig.BSP_LIBRARY_TYPE = ht32_library + +# include libraries +objs.extend(SConscript(os.path.join(libraries_path_prefix, ht32_library, 'SConscript'))) + +# include drivers +objs.extend(SConscript(os.path.join(libraries_path_prefix, 'ht32_drivers', 'SConscript'))) + +# make a building +DoBuilding(TARGET, objs) diff --git a/bsp/ht32/ht32f52352/applications/SConscript b/bsp/ht32/ht32f52352/applications/SConscript new file mode 100644 index 0000000000..9023be657a --- /dev/null +++ b/bsp/ht32/ht32f52352/applications/SConscript @@ -0,0 +1,21 @@ +#导入其他模块的变量 +Import('RTT_ROOT') +Import('rtconfig') + +#导入使用到的模块 +from building import * + +#获取当前目录的路径 +cwd = GetCurrentDir() + +#创建一个列表，用于保存需要使用到的C文件路径 +src = Glob('*c') + +#创建一个列表，用于保存需要包含的H文件路径 +path = [cwd] + +#创建一个组别 +group = DefineGroup('Applications', src, depend = [''], CPPPATH = path) + +#返回创建好的组别 +Return('group') \ No newline at end of file diff --git a/bsp/ht32/ht32f52352/applications/main.c b/bsp/ht32/ht32f52352/applications/main.c new file mode 100644 index 0000000000..3bcf7a1215 --- /dev/null +++ b/bsp/ht32/ht32f52352/applications/main.c @@ -0,0 +1,37 @@ +/* + * Copyright (c) 2006-2024, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2024-04-08 QT-one first version + */ + +#include +#include +#include "board.h" + +/* defined the led2 pin: pc14 */ +#define LED1_PIN GET_PIN(C, 14) +/* defined the led3 pin: pc15 */ +#define LED2_PIN GET_PIN(C, 15) + +int main(void) +{ + rt_uint32_t speed = 200; + /* set led1 pin mode to output */ + rt_pin_mode(LED1_PIN, PIN_MODE_OUTPUT); + /* set led2 pin mode to output */ + rt_pin_mode(LED2_PIN, PIN_MODE_OUTPUT); + + while (1) + { + rt_pin_write(LED1_PIN, PIN_LOW); + rt_pin_write(LED2_PIN, PIN_HIGH); + rt_thread_mdelay(speed); + rt_pin_write(LED1_PIN, PIN_HIGH); + rt_pin_write(LED2_PIN, PIN_LOW); + rt_thread_mdelay(speed); + } +} diff --git a/bsp/ht32/ht32f52352/board/Kconfig b/bsp/ht32/ht32f52352/board/Kconfig new file mode 100644 index 0000000000..b12d8e5626 --- /dev/null +++ b/bsp/ht32/ht32f52352/board/Kconfig @@ -0,0 +1,77 @@ +menu "Hardware Drivers Config" + +config SOC_HT32F52352 + bool + select SOC_SERIES_HT32F5 + select RT_USING_COMPONENTS_INIT + select RT_USING_USER_MAIN + default y + +menu "Onboard Peripheral Drivers" + +endmenu + +menu "On-chip Peripheral Drivers" + + config BSP_USING_GPIO + bool "Enable GPIO" + select RT_USING_PIN + default n + +    menuconfig BSP_USING_UART + bool "Enable UART" + default n + select RT_USING_SERIAL + if BSP_USING_UART + config BSP_USING_USART0 + bool "Enable USART0" + default n + + config BSP_USING_USART1 + bool "Enable USART1" + default n + + config BSP_USING_UART0 + bool "Enable UART0" + default n + + config BSP_USING_UART1 + bool "Enable UART1" + default n +        endif + + menuconfig BSP_USING_SPI + bool "Enable SPI Bus" + default n + select RT_USING_SPI + if BSP_USING_SPI + config BSP_USING_SPI0 + bool "Enable SPI0 Bus" + default n + + config BSP_USING_SPI1 + bool "Enable SPI1 Bus" + default n + endif + + menuconfig BSP_USING_I2C + bool "Enable I2C Bus" + default n + select RT_USING_I2C + if BSP_USING_I2C + config BSP_USING_I2C0 + bool "Enable I2C0 Bus" + default n + + config BSP_USING_I2C1 + bool "Enable I2C1 Bus" + default n + endif + +endmenu + +menu "Board extended module Drivers" + +endmenu + +endmenu diff --git a/bsp/ht32/ht32f52352/board/SConscript b/bsp/ht32/ht32f52352/board/SConscript new file mode 100644 index 0000000000..79eab7eced --- /dev/null +++ b/bsp/ht32/ht32f52352/board/SConscript @@ -0,0 +1,27 @@ + +import os +import rtconfig +from building import * + +Import('SDK_LIB') + +cwd = GetCurrentDir() + +src = Glob('src/*.c') + +startup_path_prefix = SDK_LIB +if rtconfig.CROSS_TOOL == 'gcc': + src += [startup_path_prefix + '/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/GCC/startup_ht32f5xxxx_gcc_01.s'] +elif rtconfig.CROSS_TOOL == 'keil': + src += [startup_path_prefix + '/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f5xxxx_01.s'] +elif rtconfig.CROSS_TOOL == 'iar': + src += [startup_path_prefix + '/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/IAR/startup_ht32f5xxxx_iar_01.s'] + +path = [cwd] +path = [cwd + '/inc'] + +CPPDEFINES = ['USE_HT32F52352_SK, USE_HT32F52342_52, USE_MEM_HT32F52352'] + +group = DefineGroup('Drivers', src, depend = [''], CPPPATH = path, CPPDEFINES = CPPDEFINES) + +Return('group') \ No newline at end of file diff --git a/bsp/ht32/ht32f52352/board/inc/board.h b/bsp/ht32/ht32f52352/board/inc/board.h new file mode 100644 index 0000000000..91d5c2d0a5 --- /dev/null +++ b/bsp/ht32/ht32f52352/board/inc/board.h @@ -0,0 +1,64 @@ +/* + * Copyright (c) 2006-2024, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2024-04-08 QT-one first version + */ + +#ifndef __BOARD_H__ +#define __BOARD_H__ + +#include +#include "ht32.h" +#include "ht32_msp.h" + +#ifdef BSP_USING_GPIO + #include "drv_gpio.h" +#endif + +#ifdef BSP_USING_UART + #include "drv_usart.h" +#endif + +#ifdef BSP_USING_SPI + #include "drv_spi.h" +#endif + +#ifdef BSP_USING_I2C + #include "drv_i2c.h" +#endif + +#ifdef __cplusplus +extern "C" { +#endif + +/* whether use board external SRAM memory */ +#define HT32_EXT_SRAM 0 +#define HT32_EXT_SRAM_BEGIN 0x68000000 +#define HT32_EXT_SRAM_END (HT32_EXT_SRAM_BEGIN + HT32_EXT_SRAM*1024) + +/* internal sram memory size */ +#define HT32_SRAM_END (0x20000000 + LIBCFG_RAM_SIZE) + +#ifdef __CC_ARM +extern int Image$$RW_IRAM1$$ZI$$Limit; +#define HEAP_BEGIN ((void *)&Image$$RW_IRAM1$$ZI$$Limit) +#elif __ICCARM__ +#pragma section="HEAP" +#define HEAP_BEGIN (__segment_end("HEAP")) +#else +extern int __bss_end; +#define HEAP_BEGIN ((void *)&__bss_end) +#endif +#define HEAP_END HT32_SRAM_END + +void rt_hw_board_clock_init(void); + +#ifdef __cplusplus +} +#endif + +#endif /* __BOARD_H__ */ diff --git a/bsp/ht32/ht32f52352/board/inc/ht32_msp.h b/bsp/ht32/ht32f52352/board/inc/ht32_msp.h new file mode 100644 index 0000000000..066add8d56 --- /dev/null +++ b/bsp/ht32/ht32f52352/board/inc/ht32_msp.h @@ -0,0 +1,210 @@ +/* + * Copyright (c) 2006-2024, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2024-04-08 QT-one first version + */ + +#ifndef __HT32_MSP_H__ +#define __HT32_MSP_H__ + +#include +#include "ht32.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* UART gpio */ +#ifdef BSP_USING_UART +#ifdef BSP_USING_USART0 +#define HTCFG_USART0_IPN USART0 + +#define _HTCFG_USART0_TX_GPIOX A +#define _HTCFG_USART0_TX_GPION 2 +#define _HTCFG_USART0_RX_GPIOX A +#define _HTCFG_USART0_RX_GPION 3 + +#define HTCFG_USART0_TX_GPIO_ID STRCAT2(GPIO_P, _HTCFG_USART0_TX_GPIOX) +#define HTCFG_USART0_TX_GPIO_CLK STRCAT2(P, _HTCFG_USART0_TX_GPIOX) +#define HTCFG_USART0_TX_GPIO_PORT STRCAT2(HT_GPIO, _HTCFG_USART0_TX_GPIOX) +#define HTCFG_USART0_TX_GPIO_PIN STRCAT2(GPIO_PIN_, _HTCFG_USART0_TX_GPION) + +#define HTCFG_USART0_RX_GPIO_ID STRCAT2(GPIO_P, _HTCFG_USART0_RX_GPIOX) +#define HTCFG_USART0_RX_GPIO_CLK STRCAT2(P, _HTCFG_USART0_RX_GPIOX) +#define HTCFG_USART0_RX_GPIO_PORT STRCAT2(HT_GPIO, _HTCFG_USART0_RX_GPIOX) +#define HTCFG_USART0_RX_GPIO_PIN STRCAT2(GPIO_PIN_, _HTCFG_USART0_RX_GPION) + +#endif +#ifdef BSP_USING_USART1 + +#define HTCFG_USART1_IPN USART1 + +#define _HTCFG_USART1_TX_GPIOX A +#define _HTCFG_USART1_TX_GPION 4 +#define _HTCFG_USART1_RX_GPIOX A +#define _HTCFG_USART1_RX_GPION 5 + +#define HTCFG_USART1_TX_GPIO_ID STRCAT2(GPIO_P, _HTCFG_USART1_TX_GPIOX) +#define HTCFG_USART1_TX_GPIO_CLK STRCAT2(P, _HTCFG_USART1_TX_GPIOX) +#define HTCFG_USART1_TX_GPIO_PORT STRCAT2(HT_GPIO, _HTCFG_USART1_TX_GPIOX) +#define HTCFG_USART1_TX_GPIO_PIN STRCAT2(GPIO_PIN_, _HTCFG_USART1_TX_GPION) + +#define HTCFG_USART1_RX_GPIO_ID STRCAT2(GPIO_P, _HTCFG_USART1_RX_GPIOX) +#define HTCFG_USART1_RX_GPIO_CLK STRCAT2(P, _HTCFG_USART1_RX_GPIOX) +#define HTCFG_USART1_RX_GPIO_PORT STRCAT2(HT_GPIO, _HTCFG_USART1_RX_GPIOX) +#define HTCFG_USART1_RX_GPIO_PIN STRCAT2(GPIO_PIN_, _HTCFG_USART1_RX_GPION) + +#endif +#ifdef BSP_USING_UART0 + +#define HTCFG_UART0_IPN UART0 + +#define _HTCFG_UART0_TX_GPIOX B +#define _HTCFG_UART0_TX_GPION 2 +#define _HTCFG_UART0_RX_GPIOX B +#define _HTCFG_UART0_RX_GPION 3 + +#define HTCFG_UART0_TX_GPIO_ID STRCAT2(GPIO_P, _HTCFG_UART0_TX_GPIOX) +#define HTCFG_UART0_TX_GPIO_CLK STRCAT2(P, _HTCFG_UART0_TX_GPIOX) +#define HTCFG_UART0_TX_GPIO_PORT STRCAT2(HT_GPIO, _HTCFG_UART0_TX_GPIOX) +#define HTCFG_UART0_TX_GPIO_PIN STRCAT2(GPIO_PIN_, _HTCFG_UART0_TX_GPION) + +#define HTCFG_UART0_RX_GPIO_ID STRCAT2(GPIO_P, _HTCFG_UART0_RX_GPIOX) +#define HTCFG_UART0_RX_GPIO_CLK STRCAT2(P, _HTCFG_UART0_RX_GPIOX) +#define HTCFG_UART0_RX_GPIO_PORT STRCAT2(HT_GPIO, _HTCFG_UART0_RX_GPIOX) +#define HTCFG_UART0_RX_GPIO_PIN STRCAT2(GPIO_PIN_, _HTCFG_UART0_RX_GPION) + +#endif +#ifdef BSP_USING_UART1 + +#define HTCFG_UART1_IPN UART1 + +#define _HTCFG_UART1_TX_GPIOX B +#define _HTCFG_UART1_TX_GPION 4 +#define _HTCFG_UART1_RX_GPIOX B +#define _HTCFG_UART1_RX_GPION 5 + +#define HTCFG_UART1_TX_GPIO_ID STRCAT2(GPIO_P, _HTCFG_UART1_TX_GPIOX) +#define HTCFG_UART1_TX_GPIO_CLK STRCAT2(P, _HTCFG_UART1_TX_GPIOX) +#define HTCFG_UART1_TX_GPIO_PORT STRCAT2(HT_GPIO, _HTCFG_UART1_TX_GPIOX) +#define HTCFG_UART1_TX_GPIO_PIN STRCAT2(GPIO_PIN_, _HTCFG_UART1_TX_GPION) + +#define HTCFG_UART1_RX_GPIO_ID STRCAT2(GPIO_P, _HTCFG_UART1_RX_GPIOX) +#define HTCFG_UART1_RX_GPIO_CLK STRCAT2(P, _HTCFG_UART1_RX_GPIOX) +#define HTCFG_UART1_RX_GPIO_PORT STRCAT2(HT_GPIO, _HTCFG_UART1_RX_GPIOX) +#define HTCFG_UART1_RX_GPIO_PIN STRCAT2(GPIO_PIN_, _HTCFG_UART1_RX_GPION) + +#endif +#endif + +/* SPI gpio */ +#ifdef BSP_USING_SPI +#ifdef BSP_USING_SPI0 + +#define HTCFG_SPI0_IPN SPI0 + +#define _HTCFG_SPI0_SCK_GPIOX C +#define _HTCFG_SPI0_SCK_GPION 0 + +#define _HTCFG_SPI0_MISO_GPIOX A +#define _HTCFG_SPI0_MISO_GPION 11 + +#define _HTCFG_SPI0_MOSI_GPIOX A +#define _HTCFG_SPI0_MOSI_GPION 9 + +#define HTCFG_SPI0_SCK_GPIO_CLK STRCAT2(P, _HTCFG_SPI0_SCK_GPIOX) +#define HTCFG_SPI0_SCK_GPIO_ID STRCAT2(GPIO_P, _HTCFG_SPI0_SCK_GPIOX) +#define HTCFG_SPI0_SCK_GPIO_PIN STRCAT2(GPIO_PIN_, _HTCFG_SPI0_SCK_GPION) + +#define HTCFG_SPI0_MISO_GPIO_CLK STRCAT2(P, _HTCFG_SPI0_MISO_GPIOX) +#define HTCFG_SPI0_MISO_GPIO_ID STRCAT2(GPIO_P, _HTCFG_SPI0_MISO_GPIOX) +#define HTCFG_SPI0_MISO_GPIO_PIN STRCAT2(GPIO_PIN_, _HTCFG_SPI0_MISO_GPION) + +#define HTCFG_SPI0_MOSI_GPIO_CLK STRCAT2(P, _HTCFG_SPI0_MOSI_GPIOX) +#define HTCFG_SPI0_MOSI_GPIO_ID STRCAT2(GPIO_P, _HTCFG_SPI0_MOSI_GPIOX) +#define HTCFG_SPI0_MOSI_GPIO_PIN STRCAT2(GPIO_PIN_, _HTCFG_SPI0_MOSI_GPION) + +#endif +#ifdef BSP_USING_SPI1 + +#define HTCFG_SPI1_IPN SPI1 + +#define _HTCFG_SPI1_SCK_GPIOX A +#define _HTCFG_SPI1_SCK_GPION 15 + +#define _HTCFG_SPI1_MISO_GPIOX B +#define _HTCFG_SPI1_MISO_GPION 1 + +#define _HTCFG_SPI1_MOSI_GPIOX B +#define _HTCFG_SPI1_MOSI_GPION 0 + +#define HTCFG_SPI1_SCK_GPIO_CLK STRCAT2(P, _HTCFG_SPI1_SCK_GPIOX) +#define HTCFG_SPI1_SCK_GPIO_ID STRCAT2(GPIO_P, _HTCFG_SPI1_SCK_GPIOX) +#define HTCFG_SPI1_SCK_GPIO_PIN STRCAT2(GPIO_PIN_, _HTCFG_SPI1_SCK_GPION) + +#define HTCFG_SPI1_MISO_GPIO_CLK STRCAT2(P, _HTCFG_SPI1_MISO_GPIOX) +#define HTCFG_SPI1_MISO_GPIO_ID STRCAT2(GPIO_P, _HTCFG_SPI1_MISO_GPIOX) +#define HTCFG_SPI1_MISO_GPIO_PIN STRCAT2(GPIO_PIN_, _HTCFG_SPI1_MISO_GPION) + +#define HTCFG_SPI1_MOSI_GPIO_CLK STRCAT2(P, _HTCFG_SPI1_MOSI_GPIOX) +#define HTCFG_SPI1_MOSI_GPIO_ID STRCAT2(GPIO_P, _HTCFG_SPI1_MOSI_GPIOX) +#define HTCFG_SPI1_MOSI_GPIO_PIN STRCAT2(GPIO_PIN_, _HTCFG_SPI1_MOSI_GPION) + +#endif +#endif + +/* I2C gpio */ +#ifdef BSP_USING_I2C +#ifdef BSP_USING_I2C0 + +#define HTCFG_I2C0_IPN I2C0 + +#define _HTCFG_I2C0_SCL_GPIOX C +#define _HTCFG_I2C0_SCL_GPION 12 + +#define _HTCFG_I2C0_SDA_GPIOX C +#define _HTCFG_I2C0_SDA_GPION 13 + +#define HTCFG_I2C0_SCL_GPIO_CLK STRCAT2(P, _HTCFG_I2C0_SCL_GPIOX) +#define HTCFG_I2C0_SCL_GPIO_ID STRCAT2(GPIO_P, _HTCFG_I2C0_SCL_GPIOX) +#define HTCFG_I2C0_SCL_GPIO_PIN STRCAT2(GPIO_PIN_, _HTCFG_I2C0_SCL_GPION) + +#define HTCFG_I2C0_SDA_GPIO_CLK STRCAT2(P, _HTCFG_I2C0_SDA_GPIOX) +#define HTCFG_I2C0_SDA_GPIO_ID STRCAT2(GPIO_P, _HTCFG_I2C0_SDA_GPIOX) +#define HTCFG_I2C0_SDA_GPIO_PIN STRCAT2(GPIO_PIN_, _HTCFG_I2C0_SDA_GPION) + +#endif +#ifdef BSP_USING_I2C1 + +#define HTCFG_I2C1_IPN I2C1 + +#define _HTCFG_I2C1_SCL_GPIOX A +#define _HTCFG_I2C1_SCL_GPION 0 + +#define _HTCFG_I2C1_SDA_GPIOX A +#define _HTCFG_I2C1_SDA_GPION 1 + +#define HTCFG_I2C1_SCL_GPIO_CLK STRCAT2(P, _HTCFG_I2C1_SCL_GPIOX) +#define HTCFG_I2C1_SCL_GPIO_ID STRCAT2(GPIO_P, _HTCFG_I2C1_SCL_GPIOX) +#define HTCFG_I2C1_SCL_GPIO_PIN STRCAT2(GPIO_PIN_, _HTCFG_I2C1_SCL_GPION) + +#define HTCFG_I2C1_SDA_GPIO_CLK STRCAT2(P, _HTCFG_I2C1_SDA_GPIOX) +#define HTCFG_I2C1_SDA_GPIO_ID STRCAT2(GPIO_P, _HTCFG_I2C1_SDA_GPIOX) +#define HTCFG_I2C1_SDA_GPIO_PIN STRCAT2(GPIO_PIN_, _HTCFG_I2C1_SDA_GPION) + +#endif +#endif + +void ht32_usart_gpio_init(void *instance); +void ht32_spi_gpio_init(void *instance); +void ht32_i2c_gpio_init(void *instance); + +#ifdef __cplusplus +} +#endif + +#endif /* __HT32_MSP_H__ */ diff --git a/bsp/ht32/ht32f52352/board/inc/ht32f5xxxx_01_usbdconf.h b/bsp/ht32/ht32f52352/board/inc/ht32f5xxxx_01_usbdconf.h new file mode 100644 index 0000000000..a512579519 --- /dev/null +++ b/bsp/ht32/ht32f52352/board/inc/ht32f5xxxx_01_usbdconf.h @@ -0,0 +1,453 @@ +/*********************************************************************************************************//** + * @file IP/Example/ht32f5xxxx_01_usbdconf.h + * @version $Rev:: 2390 $ + * @date $Date:: 2017-12-21 #$ + * @brief The configuration file of USB Device Driver. + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ +// <<< Use Configuration Wizard in Context Menu >>> + +/* Define to prevent recursive inclusion -------------------------------------------------------------------*/ +#ifndef __HT32F5XXXX_01_USBDCONF_H +#define __HT32F5XXXX_01_USBDCONF_H + +// Enter Low Power mode when Suspended +#define USBDCORE_ENABLE_LOW_POWER (0) +// + +#if (USBDCORE_ENABLE_LOW_POWER == 1) + #define USBDCore_LowPower() PWRCU_DeepSleep1(PWRCU_SLEEP_ENTRY_WFE) +#else + #define USBDCore_LowPower(...) +#endif + +/*----------------------------------------------------------------------------------------------------------*/ +/* USB Interrupt Enable */ +/*----------------------------------------------------------------------------------------------------------*/ +// USB Interrupt Setting (UIER) +// USB Global Interrupt Enable (UGIE) (Default) +// Start Of Frame Interrupt Enable (SOFIE) +// USB Reset Interrupt Enable (URSTIE) (Default) +// Resume Interrupt Enable (RSMIE) (Default) +// Suspend Interrupt Enable (SUSPIE) (Default) +// Expected Start of Frame Interrupt Enable (ESOFE) +// Control Endpoint Interrupt Enable (EP0IE) (Default) +// Endpoint1 Interrupt Enable (EP1IE) +// Endpoint2 Interrupt Enable (EP2IE) +// Endpoint3 Interrupt Enable (EP3IE) +// Endpoint4 Interrupt Enable (EP4IE) +// Endpoint5 Interrupt Enable (EP5IE) +// Endpoint6 Interrupt Enable (EP6IE) +// Endpoint7 Interrupt Enable (EP7IE) +#define _UIER (0x011D) +// + + +/*----------------------------------------------------------------------------------------------------------*/ +/* Endpoint0 Configuration Setting */ +/*----------------------------------------------------------------------------------------------------------*/ +// Control Endpoint0 Configuration +// Endpoint Buffer Length (EPLEN) +// <8=> 8 bytes +// <16=> 16 bytes +// <32=> 32 bytes +// <64=> 64 bytes + /* Maximum: 64 Bytes */ +#define _EP0LEN (64) + + +// Control Endpoint0 Interrupt Enable Settings (EP0IER) +// OUT Token Packet Received Interrupt Enable (OTRXIE) +// OUT Data Packet Received Interrupt Enable (ODRXIE) (Default) +// OUT Data Buffer Overrun Interrupt Enable (ODOVIE) +// IN Token Packet Received Interrupt Enable (ITRXIE) +// IN Data Packet Transmitted Interrupt Enable (IDTXIE) (Default) +// NAK Transmitted Interrupt Enable (NAKIE) +// STALL Transmitted Interrupt Enable (STLIE) +// USB Error Interrupt Enable (UERIE) +// SETUP Token Packet Received Interrupt Enable (STRXIE) +// SETUP Data Packet Received Interrupt Enable (SDRXIE) (Default) +// SETUP Data Error Interrupt Enable (SDERIE) +// Zero Length Data Packet Received Interrupt Enable (ZLRXIE) +#define _EP0_IER (0x212) +// +// + +/*----------------------------------------------------------------------------------------------------------*/ +/* Endpoint1 Configuration Setting */ +/*----------------------------------------------------------------------------------------------------------*/ +// Endpoint1 Configuration +#define _EP1_ENABLE (0) + +// Endpoint Address (EPADR) +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 +#define _EP1_CFG_EPADR (1) + +// Endpoint Enable (EPEN) +#define _EP1_CFG_EPEN_TMP (1) + +// Endpoint Transfer Type +// <2=> Bulk +// <3=> Interrupt +#define _EP1_TYPR (3) + +// Endpoint Direction (EPDIR) +// <1=> IN +// <0=> OUT +#define _EP1_CFG_EPDIR (1) + +// Endpoint Buffer Length (EPLEN) (in byte) <4-64:4> + /* Maximum: 64 Bytes */ +#define _EP1LEN_TMP (8) + +// Endpoint Interrupt Enable Settings (EPIER) +// Endpoint Interrupt Enable Settings (EPIER) <0x0-0xFF:1> +// OUT Token Packet Received Interrupt Enable (OTRXIE) +// OUT Data Packet Received Interrupt Enable (ODRXIE) +// OUT Data Buffer Overrun Interrupt Enable (ODOVIE) +// IN Token Packet Received Interrupt Enable (ITRXIE) +// IN Data Packet Transmitted Interrupt Enable (IDTXIE) +// NAK Transmitted Interrupt Enable (NAKIE) +// STALL Transmitted Interrupt Enable (STLIE) +// USB Error Interrupt Enable (UERIE) +#define _EP1_IER (0x10) +// +// + + +/*----------------------------------------------------------------------------------------------------------*/ +/* Endpoint2 Configuration Setting */ +/*----------------------------------------------------------------------------------------------------------*/ +// Endpoint2 Configuration +#define _EP2_ENABLE (0) + +// Endpoint Address (EPADR) +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 +#define _EP2_CFG_EPADR (2) + +// Endpoint Enable (EPEN) +#define _EP2_CFG_EPEN_TMP (1) + +// Endpoint Transfer Type +// <2=> Bulk +// <3=> Interrupt +#define _EP2_TYPR (3) + +// Endpoint Direction (EPDIR) +// <1=> IN +// <0=> OUT +#define _EP2_CFG_EPDIR (0) + +// Endpoint Buffer Length (EPLEN) (in byte) <4-64:4> + /* Maximum: 64 Bytes */ +#define _EP2LEN_TMP (8) + +// Endpoint Interrupt Enable Settings (EPIER) +// Endpoint Interrupt Enable Settings (EPIER) <0x0-0xFF:1> +// OUT Token Packet Received Interrupt Enable (OTRXIE) +// OUT Data Packet Received Interrupt Enable (ODRXIE) +// OUT Data Buffer Overrun Interrupt Enable (ODOVIE) +// IN Token Packet Received Interrupt Enable (ITRXIE) +// IN Data Packet Transmitted Interrupt Enable (IDTXIE) +// NAK Transmitted Interrupt Enable (NAKIE) +// STALL Transmitted Interrupt Enable (STLIE) +// USB Error Interrupt Enable (UERIE) +#define _EP2_IER (0x002) +// +// + +/*----------------------------------------------------------------------------------------------------------*/ +/* Endpoint3 Configuration Setting */ +/*----------------------------------------------------------------------------------------------------------*/ +// Endpoint3 Configuration +#define _EP3_ENABLE (0) + +// Endpoint Address (EPADR) +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 +#define _EP3_CFG_EPADR (3) + +// Endpoint Enable (EPEN) +#define _EP3_CFG_EPEN_TMP (1) + +// Endpoint Transfer Type +// <2=> Bulk +// <3=> Interrupt +#define _EP3_TYPR (3) + +// Endpoint Direction (EPDIR) +// <1=> IN +// <0=> OUT +#define _EP3_CFG_EPDIR (1) + +// Endpoint Buffer Length (EPLEN) (in byte) <4-64:4> + /* Maximum: 64 Bytes */ +#define _EP3LEN_TMP (8) + +// Endpoint Interrupt Enable Settings (EPIER) +// Endpoint Interrupt Enable Settings (EPIER) <0x0-0xFF:1> +// OUT Token Packet Received Interrupt Enable (OTRXIE) +// OUT Data Packet Received Interrupt Enable (ODRXIE) +// OUT Data Buffer Overrun Interrupt Enable (ODOVIE) +// IN Token Packet Received Interrupt Enable (ITRXIE) +// IN Data Packet Transmitted Interrupt Enable (IDTXIE) +// NAK Transmitted Interrupt Enable (NAKIE) +// STALL Transmitted Interrupt Enable (STLIE) +// USB Error Interrupt Enable (UERIE) +#define _EP3_IER (0x10) +// +// + +/*----------------------------------------------------------------------------------------------------------*/ +/* Endpoint4 Configuration Setting */ +/*----------------------------------------------------------------------------------------------------------*/ +// Endpoint4 Configuration +#define _EP4_ENABLE (0) + +// Endpoint Address (EPADR) +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 +#define _EP4_CFG_EPADR (4) + +// Endpoint Enable (EPEN) +#define _EP4_CFG_EPEN_TMP (1) + +// Endpoint Transfer Type +// <1=> Isochronous +// <2=> Bulk +// <3=> Interrupt +#define _EP4_TYPR (3) + +// Endpoint Direction (EPDIR) +// <1=> IN +// <0=> OUT +#define _EP4_CFG_EPDIR (0) + +// Endpoint Buffer Length (EPLEN) (in byte) <4-1000:4> + /* Maximum: 1000 Bytes */ +#define _EP4LEN_TMP (8) + +// Single/Double Buffer Selection (SDBS) +// <0=> Single Buffer +// <1=> Double Buffer +#define _EP4_CFG_SDBS (0) + +// Endpoint Interrupt Enable Settings (EPIER) +// Endpoint Interrupt Enable Settings (EPIER) <0x0-0xFF:1> +// OUT Token Packet Received Interrupt Enable (OTRXIE) +// OUT Data Packet Received Interrupt Enable (ODRXIE) +// OUT Data Buffer Overrun Interrupt Enable (ODOVIE) +// IN Token Packet Received Interrupt Enable (ITRXIE) +// IN Data Packet Transmitted Interrupt Enable (IDTXIE) +// NAK Transmitted Interrupt Enable (NAKIE) +// STALL Transmitted Interrupt Enable (STLIE) +// USB Error Interrupt Enable (UERIE) +#define _EP4_IER (0x02) +// +// + + +/*----------------------------------------------------------------------------------------------------------*/ +/* Endpoint5 Configuration Setting */ +/*----------------------------------------------------------------------------------------------------------*/ +// Endpoint5 Configuration +#define _EP5_ENABLE (0) + +// Endpoint Address (EPADR) +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 +#define _EP5_CFG_EPADR (5) + +// Endpoint Enable (EPEN) +#define _EP5_CFG_EPEN_TMP (1) + +// Endpoint Transfer Type +// <1=> Isochronous +// <2=> Bulk +// <3=> Interrupt +#define _EP5_TYPR (3) + +// Endpoint Direction (EPDIR) +// <1=> IN +// <0=> OUT +#define _EP5_CFG_EPDIR (1) + +// Endpoint Buffer Length (EPLEN) (in byte) <4-1000:4> + /* Maximum: 1000 Bytes */ +#define _EP5LEN_TMP (8) + + +// Single/Double Buffer Selection (SDBS) +// <0=> Single Buffer +// <1=> Double Buffer +#define _EP5_CFG_SDBS (0) + +// Endpoint Interrupt Enable Settings (EPIER) +// Endpoint Interrupt Enable Settings (EPIER) <0x0-0xFF:1> +// OUT Token Packet Received Interrupt Enable (OTRXIE) +// OUT Data Packet Received Interrupt Enable (ODRXIE) +// OUT Data Buffer Overrun Interrupt Enable (ODOVIE) +// IN Token Packet Received Interrupt Enable (ITRXIE) +// IN Data Packet Transmitted Interrupt Enable (IDTXIE) +// NAK Transmitted Interrupt Enable (NAKIE) +// STALL Transmitted Interrupt Enable (STLIE) +// USB Error Interrupt Enable (UERIE) +#define _EP5_IER (0x10) +// +// + + +/*----------------------------------------------------------------------------------------------------------*/ +/* Endpoint6 Configuration Setting */ +/*----------------------------------------------------------------------------------------------------------*/ +// Endpoint6 Configuration +#define _EP6_ENABLE (0) + +// Endpoint Address (EPADR) +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 +#define _EP6_CFG_EPADR (6) + +// Endpoint Enable (EPEN) +#define _EP6_CFG_EPEN_TMP (1) + +// Endpoint Transfer Type +// <1=> Isochronous +// <2=> Bulk +// <3=> Interrupt +#define _EP6_TYPR (3) + +// Endpoint Direction (EPDIR) +// <1=> IN +// <0=> OUT +#define _EP6_CFG_EPDIR (0) + +// Endpoint Buffer Length (EPLEN) (in byte) <4-1000:4> + /* Maximum: 1000 Bytes */ +#define _EP6LEN_TMP (8) + +// Single/Double Buffer Selection (SDBS) +// <0=> Single Buffer +// <1=> Double Buffer +#define _EP6_CFG_SDBS (0) + +// Endpoint Interrupt Enable Settings (EPIER) +// Endpoint Interrupt Enable Settings (EPIER) <0x0-0xFF:1> +// OUT Token Packet Received Interrupt Enable (OTRXIE) +// OUT Data Packet Received Interrupt Enable (ODRXIE) +// OUT Data Buffer Overrun Interrupt Enable (ODOVIE) +// IN Token Packet Received Interrupt Enable (ITRXIE) +// IN Data Packet Transmitted Interrupt Enable (IDTXIE) +// NAK Transmitted Interrupt Enable (NAKIE) +// STALL Transmitted Interrupt Enable (STLIE) +// USB Error Interrupt Enable (UERIE) +#define _EP6_IER (0x02) +// +// + + +/*----------------------------------------------------------------------------------------------------------*/ +/* Endpoint7 Configuration Setting */ +/*----------------------------------------------------------------------------------------------------------*/ +// Endpoint7 Configuration +#define _EP7_ENABLE (0) + +// Endpoint Address (EPADR) +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 +#define _EP7_CFG_EPADR (7) + +// Endpoint Enable (EPEN) +#define _EP7_CFG_EPEN_TMP (1) + +// Endpoint Transfer Type +// <1=> Isochronous +// <2=> Bulk +// <3=> Interrupt +#define _EP7_TYPR (3) + +// Endpoint Direction (EPDIR) +// <1=> IN +// <0=> OUT +#define _EP7_CFG_EPDIR (1) + +// Endpoint Buffer Length (EPLEN) (in byte) <4-1000:4> + /* Maximum: 1000 Bytes */ +#define _EP7LEN_TMP (8) + +// Single/Double Buffer Selection (SDBS) +// <0=> Single Buffer +// <1=> Double Buffer +#define _EP7_CFG_SDBS (0) + +// Endpoint Interrupt Enable Settings (EPIER) +// Endpoint Interrupt Enable Settings (EPIER) <0x0-0xFF:1> +// OUT Token Packet Received Interrupt Enable (OTRXIE) +// OUT Data Packet Received Interrupt Enable (ODRXIE) +// OUT Data Buffer Overrun Interrupt Enable (ODOVIE) +// IN Token Packet Received Interrupt Enable (ITRXIE) +// IN Data Packet Transmitted Interrupt Enable (IDTXIE) +// NAK Transmitted Interrupt Enable (NAKIE) +// STALL Transmitted Interrupt Enable (STLIE) +// USB Error Interrupt Enable (UERIE) +#define _EP7_IER (0x10) +// +// + +#endif diff --git a/bsp/ht32/ht32f52352/board/inc/ht32f5xxxx_02_usbdconf.h b/bsp/ht32/ht32f52352/board/inc/ht32f5xxxx_02_usbdconf.h new file mode 100644 index 0000000000..272e8cd127 --- /dev/null +++ b/bsp/ht32/ht32f52352/board/inc/ht32f5xxxx_02_usbdconf.h @@ -0,0 +1,569 @@ +/*********************************************************************************************************//** + * @file IP/Example/ht32f5xxxx_02_usbdconf.h + * @version $Rev:: 5656 $ + * @date $Date:: 2021-11-24 #$ + * @brief The configuration file of USB Device Driver. + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ +// <<< Use Configuration Wizard in Context Menu >>> + +/* Define to prevent recursive inclusion -------------------------------------------------------------------*/ +#ifndef __HT32F5XXXX_02_USBDCONF_H +#define __HT32F5XXXX_02_USBDCONF_H + +// Enter Low Power mode when Suspended +#define USBDCORE_ENABLE_LOW_POWER (0) +// + +#if (USBDCORE_ENABLE_LOW_POWER == 1) + #define USBDCore_LowPower() PWRCU_DeepSleep1(PWRCU_SLEEP_ENTRY_WFE) +#else + #define USBDCore_LowPower(...) +#endif + +/*----------------------------------------------------------------------------------------------------------*/ +/* USB Interrupt Enable */ +/*----------------------------------------------------------------------------------------------------------*/ +// USB Interrupt Setting (UIER) +// USB Global Interrupt Enable (UGIE) (Default) +// Start Of Frame Interrupt Enable (SOFIE) +// USB Reset Interrupt Enable (URSTIE) (Default) +// Resume Interrupt Enable (RSMIE) (Default) +// Suspend Interrupt Enable (SUSPIE) (Default) +// Expected Start of Frame Interrupt Enable (ESOFE) +// Control Endpoint Interrupt Enable (EP0IE) (Default) +// Endpoint1 Interrupt Enable (EP1IE) +// Endpoint2 Interrupt Enable (EP2IE) +// Endpoint3 Interrupt Enable (EP3IE) +// Endpoint4 Interrupt Enable (EP4IE) +// Endpoint5 Interrupt Enable (EP5IE) +// Endpoint6 Interrupt Enable (EP6IE) +// Endpoint7 Interrupt Enable (EP7IE) +// Endpoint8 Interrupt Enable (EP8IE) +// Endpoint9 Interrupt Enable (EP9IE) +#define _UIER (0x011D) +// + + +/*----------------------------------------------------------------------------------------------------------*/ +/* Endpoint0 Configuration Setting */ +/*----------------------------------------------------------------------------------------------------------*/ +// Control Endpoint0 Configuration +// Endpoint Buffer Length (EPLEN) +// <8=> 8 bytes +// <16=> 16 bytes +// <32=> 32 bytes +// <64=> 64 bytes + /* Maximum: 64 Bytes */ +#define _EP0LEN (64) + + +// Control Endpoint0 Interrupt Enable Settings (EP0IER) +// OUT Token Packet Received Interrupt Enable (OTRXIE) +// OUT Data Packet Received Interrupt Enable (ODRXIE) (Default) +// OUT Data Buffer Overrun Interrupt Enable (ODOVIE) +// IN Token Packet Received Interrupt Enable (ITRXIE) +// IN Data Packet Transmitted Interrupt Enable (IDTXIE) (Default) +// NAK Transmitted Interrupt Enable (NAKIE) +// STALL Transmitted Interrupt Enable (STLIE) +// USB Error Interrupt Enable (UERIE) +// SETUP Token Packet Received Interrupt Enable (STRXIE) +// SETUP Data Packet Received Interrupt Enable (SDRXIE) (Default) +// SETUP Data Error Interrupt Enable (SDERIE) +// Zero Length Data Packet Received Interrupt Enable (ZLRXIE) +#define _EP0_IER (0x212) +// +// + +/*----------------------------------------------------------------------------------------------------------*/ +/* Endpoint1 Configuration Setting */ +/*----------------------------------------------------------------------------------------------------------*/ +// Endpoint1 Configuration +#define _EP1_ENABLE (0) + +// Endpoint Address (EPADR) +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 +// <8=> 8 +// <9=> 9 +#define _EP1_CFG_EPADR (1) + +// Endpoint Enable (EPEN) +#define _EP1_CFG_EPEN_TMP (1) + +// Endpoint Transfer Type +// <2=> Bulk +// <3=> Interrupt +#define _EP1_TYPR (3) + +// Endpoint Direction (EPDIR) +// <1=> IN +// <0=> OUT +#define _EP1_CFG_EPDIR (1) + +// Endpoint Buffer Length (EPLEN) (in byte) <4-64:4> + /* Maximum: 64 Bytes */ +#define _EP1LEN_TMP (8) + +// Endpoint Interrupt Enable Settings (EPIER) +// Endpoint Interrupt Enable Settings (EPIER) <0x0-0xFF:1> +// OUT Token Packet Received Interrupt Enable (OTRXIE) +// OUT Data Packet Received Interrupt Enable (ODRXIE) +// OUT Data Buffer Overrun Interrupt Enable (ODOVIE) +// IN Token Packet Received Interrupt Enable (ITRXIE) +// IN Data Packet Transmitted Interrupt Enable (IDTXIE) +// NAK Transmitted Interrupt Enable (NAKIE) +// STALL Transmitted Interrupt Enable (STLIE) +// USB Error Interrupt Enable (UERIE) +#define _EP1_IER (0x10) +// +// + + +/*----------------------------------------------------------------------------------------------------------*/ +/* Endpoint2 Configuration Setting */ +/*----------------------------------------------------------------------------------------------------------*/ +// Endpoint2 Configuration +#define _EP2_ENABLE (0) + +// Endpoint Address (EPADR) +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 +// <8=> 8 +// <9=> 9 +#define _EP2_CFG_EPADR (2) + +// Endpoint Enable (EPEN) +#define _EP2_CFG_EPEN_TMP (1) + +// Endpoint Transfer Type +// <2=> Bulk +// <3=> Interrupt +#define _EP2_TYPR (3) + +// Endpoint Direction (EPDIR) +// <1=> IN +// <0=> OUT +#define _EP2_CFG_EPDIR (0) + +// Endpoint Buffer Length (EPLEN) (in byte) <4-64:4> + /* Maximum: 64 Bytes */ +#define _EP2LEN_TMP (8) + +// Endpoint Interrupt Enable Settings (EPIER) +// Endpoint Interrupt Enable Settings (EPIER) <0x0-0xFF:1> +// OUT Token Packet Received Interrupt Enable (OTRXIE) +// OUT Data Packet Received Interrupt Enable (ODRXIE) +// OUT Data Buffer Overrun Interrupt Enable (ODOVIE) +// IN Token Packet Received Interrupt Enable (ITRXIE) +// IN Data Packet Transmitted Interrupt Enable (IDTXIE) +// NAK Transmitted Interrupt Enable (NAKIE) +// STALL Transmitted Interrupt Enable (STLIE) +// USB Error Interrupt Enable (UERIE) +#define _EP2_IER (0x002) +// +// + +/*----------------------------------------------------------------------------------------------------------*/ +/* Endpoint3 Configuration Setting */ +/*----------------------------------------------------------------------------------------------------------*/ +// Endpoint3 Configuration +#define _EP3_ENABLE (0) + +// Endpoint Address (EPADR) +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 +// <8=> 8 +// <9=> 9 +#define _EP3_CFG_EPADR (3) + +// Endpoint Enable (EPEN) +#define _EP3_CFG_EPEN_TMP (1) + +// Endpoint Transfer Type +// <2=> Bulk +// <3=> Interrupt +#define _EP3_TYPR (3) + +// Endpoint Direction (EPDIR) +// <1=> IN +// <0=> OUT +#define _EP3_CFG_EPDIR (1) + +// Endpoint Buffer Length (EPLEN) (in byte) <4-64:4> + /* Maximum: 64 Bytes */ +#define _EP3LEN_TMP (8) + +// Endpoint Interrupt Enable Settings (EPIER) +// Endpoint Interrupt Enable Settings (EPIER) <0x0-0xFF:1> +// OUT Token Packet Received Interrupt Enable (OTRXIE) +// OUT Data Packet Received Interrupt Enable (ODRXIE) +// OUT Data Buffer Overrun Interrupt Enable (ODOVIE) +// IN Token Packet Received Interrupt Enable (ITRXIE) +// IN Data Packet Transmitted Interrupt Enable (IDTXIE) +// NAK Transmitted Interrupt Enable (NAKIE) +// STALL Transmitted Interrupt Enable (STLIE) +// USB Error Interrupt Enable (UERIE) +#define _EP3_IER (0x10) +// +// + +/*----------------------------------------------------------------------------------------------------------*/ +/* Endpoint4 Configuration Setting */ +/*----------------------------------------------------------------------------------------------------------*/ +// Endpoint4 Configuration +#define _EP4_ENABLE (0) + +// Endpoint Address (EPADR) +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 +// <8=> 8 +// <9=> 9 +#define _EP4_CFG_EPADR (4) + +// Endpoint Enable (EPEN) +#define _EP4_CFG_EPEN_TMP (1) + +// Endpoint Transfer Type +// <1=> Isochronous +// <2=> Bulk +// <3=> Interrupt +#define _EP4_TYPR (3) + +// Endpoint Direction (EPDIR) +// <1=> IN +// <0=> OUT +#define _EP4_CFG_EPDIR (0) + +// Endpoint Buffer Length (EPLEN) (in byte) <4-1000:4> + /* Maximum: 1000 Bytes */ +#define _EP4LEN_TMP (8) + +// Single/Double Buffer Selection (SDBS) +// <0=> Single Buffer +// <1=> Double Buffer +#define _EP4_CFG_SDBS (0) + +// Endpoint Interrupt Enable Settings (EPIER) +// Endpoint Interrupt Enable Settings (EPIER) <0x0-0xFF:1> +// OUT Token Packet Received Interrupt Enable (OTRXIE) +// OUT Data Packet Received Interrupt Enable (ODRXIE) +// OUT Data Buffer Overrun Interrupt Enable (ODOVIE) +// IN Token Packet Received Interrupt Enable (ITRXIE) +// IN Data Packet Transmitted Interrupt Enable (IDTXIE) +// NAK Transmitted Interrupt Enable (NAKIE) +// STALL Transmitted Interrupt Enable (STLIE) +// USB Error Interrupt Enable (UERIE) +#define _EP4_IER (0x02) +// +// + + +/*----------------------------------------------------------------------------------------------------------*/ +/* Endpoint5 Configuration Setting */ +/*----------------------------------------------------------------------------------------------------------*/ +// Endpoint5 Configuration +#define _EP5_ENABLE (0) + +// Endpoint Address (EPADR) +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 +// <8=> 8 +// <9=> 9 +#define _EP5_CFG_EPADR (5) + +// Endpoint Enable (EPEN) +#define _EP5_CFG_EPEN_TMP (1) + +// Endpoint Transfer Type +// <1=> Isochronous +// <2=> Bulk +// <3=> Interrupt +#define _EP5_TYPR (3) + +// Endpoint Direction (EPDIR) +// <1=> IN +// <0=> OUT +#define _EP5_CFG_EPDIR (1) + +// Endpoint Buffer Length (EPLEN) (in byte) <4-1000:4> + /* Maximum: 1000 Bytes */ +#define _EP5LEN_TMP (8) + + +// Single/Double Buffer Selection (SDBS) +// <0=> Single Buffer +// <1=> Double Buffer +#define _EP5_CFG_SDBS (0) + +// Endpoint Interrupt Enable Settings (EPIER) +// Endpoint Interrupt Enable Settings (EPIER) <0x0-0xFF:1> +// OUT Token Packet Received Interrupt Enable (OTRXIE) +// OUT Data Packet Received Interrupt Enable (ODRXIE) +// OUT Data Buffer Overrun Interrupt Enable (ODOVIE) +// IN Token Packet Received Interrupt Enable (ITRXIE) +// IN Data Packet Transmitted Interrupt Enable (IDTXIE) +// NAK Transmitted Interrupt Enable (NAKIE) +// STALL Transmitted Interrupt Enable (STLIE) +// USB Error Interrupt Enable (UERIE) +#define _EP5_IER (0x10) +// +// + + +/*----------------------------------------------------------------------------------------------------------*/ +/* Endpoint6 Configuration Setting */ +/*----------------------------------------------------------------------------------------------------------*/ +// Endpoint6 Configuration +#define _EP6_ENABLE (0) + +// Endpoint Address (EPADR) +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 +// <8=> 8 +// <9=> 9 +#define _EP6_CFG_EPADR (6) + +// Endpoint Enable (EPEN) +#define _EP6_CFG_EPEN_TMP (1) + +// Endpoint Transfer Type +// <1=> Isochronous +// <2=> Bulk +// <3=> Interrupt +#define _EP6_TYPR (3) + +// Endpoint Direction (EPDIR) +// <1=> IN +// <0=> OUT +#define _EP6_CFG_EPDIR (0) + +// Endpoint Buffer Length (EPLEN) (in byte) <4-1000:4> + /* Maximum: 1000 Bytes */ +#define _EP6LEN_TMP (8) + +// Single/Double Buffer Selection (SDBS) +// <0=> Single Buffer +// <1=> Double Buffer +#define _EP6_CFG_SDBS (0) + +// Endpoint Interrupt Enable Settings (EPIER) +// Endpoint Interrupt Enable Settings (EPIER) <0x0-0xFF:1> +// OUT Token Packet Received Interrupt Enable (OTRXIE) +// OUT Data Packet Received Interrupt Enable (ODRXIE) +// OUT Data Buffer Overrun Interrupt Enable (ODOVIE) +// IN Token Packet Received Interrupt Enable (ITRXIE) +// IN Data Packet Transmitted Interrupt Enable (IDTXIE) +// NAK Transmitted Interrupt Enable (NAKIE) +// STALL Transmitted Interrupt Enable (STLIE) +// USB Error Interrupt Enable (UERIE) +#define _EP6_IER (0x02) +// +// + + +/*----------------------------------------------------------------------------------------------------------*/ +/* Endpoint7 Configuration Setting */ +/*----------------------------------------------------------------------------------------------------------*/ +// Endpoint7 Configuration +#define _EP7_ENABLE (0) + +// Endpoint Address (EPADR) +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 +// <8=> 8 +// <9=> 9 +#define _EP7_CFG_EPADR (7) + +// Endpoint Enable (EPEN) +#define _EP7_CFG_EPEN_TMP (1) + +// Endpoint Transfer Type +// <1=> Isochronous +// <2=> Bulk +// <3=> Interrupt +#define _EP7_TYPR (3) + +// Endpoint Direction (EPDIR) +// <1=> IN +// <0=> OUT +#define _EP7_CFG_EPDIR (1) + +// Endpoint Buffer Length (EPLEN) (in byte) <4-1000:4> + /* Maximum: 1000 Bytes */ +#define _EP7LEN_TMP (8) + +// Single/Double Buffer Selection (SDBS) +// <0=> Single Buffer +// <1=> Double Buffer +#define _EP7_CFG_SDBS (0) + +// Endpoint Interrupt Enable Settings (EPIER) +// Endpoint Interrupt Enable Settings (EPIER) <0x0-0xFF:1> +// OUT Token Packet Received Interrupt Enable (OTRXIE) +// OUT Data Packet Received Interrupt Enable (ODRXIE) +// OUT Data Buffer Overrun Interrupt Enable (ODOVIE) +// IN Token Packet Received Interrupt Enable (ITRXIE) +// IN Data Packet Transmitted Interrupt Enable (IDTXIE) +// NAK Transmitted Interrupt Enable (NAKIE) +// STALL Transmitted Interrupt Enable (STLIE) +// USB Error Interrupt Enable (UERIE) +#define _EP7_IER (0x10) +// +// + + +/*----------------------------------------------------------------------------------------------------------*/ +/* Endpoint8 Configuration Setting */ +/*----------------------------------------------------------------------------------------------------------*/ +// Endpoint8 Configuration +#define _EP8_ENABLE (0) + +// Endpoint Address (EPADR) +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 +// <8=> 8 +// <9=> 9 +#define _EP8_CFG_EPADR (8) + +// Endpoint Enable (EPEN) +#define _EP8_CFG_EPEN_TMP (1) + +// Endpoint Transfer Type +// <2=> Bulk +// <3=> Interrupt +#define _EP8_TYPR (3) + +// Endpoint Direction (EPDIR) +// <1=> IN +// <0=> OUT +#define _EP8_CFG_EPDIR (1) + +// Endpoint Buffer Length (EPLEN) (in byte) <4-64:4> + /* Maximum: 64 Bytes */ +#define _EP8LEN_TMP (8) + +// Endpoint Interrupt Enable Settings (EPIER) +// Endpoint Interrupt Enable Settings (EPIER) <0x0-0xFF:1> +// OUT Token Packet Received Interrupt Enable (OTRXIE) +// OUT Data Packet Received Interrupt Enable (ODRXIE) +// OUT Data Buffer Overrun Interrupt Enable (ODOVIE) +// IN Token Packet Received Interrupt Enable (ITRXIE) +// IN Data Packet Transmitted Interrupt Enable (IDTXIE) +// NAK Transmitted Interrupt Enable (NAKIE) +// STALL Transmitted Interrupt Enable (STLIE) +// USB Error Interrupt Enable (UERIE) +#define _EP8_IER (0x10) +// +// + + +/*----------------------------------------------------------------------------------------------------------*/ +/* Endpoint9 Configuration Setting */ +/*----------------------------------------------------------------------------------------------------------*/ +// Endpoint9 Configuration +#define _EP9_ENABLE (0) + +// Endpoint Address (EPADR) +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 +// <8=> 8 +// <9=> 9 +#define _EP9_CFG_EPADR (9) + +// Endpoint Enable (EPEN) +#define _EP9_CFG_EPEN_TMP (1) + +// Endpoint Transfer Type +// <2=> Bulk +// <3=> Interrupt +#define _EP9_TYPR (3) + +// Endpoint Direction (EPDIR) +// <1=> IN +// <0=> OUT +#define _EP9_CFG_EPDIR (1) + +// Endpoint Buffer Length (EPLEN) (in byte) <4-64:4> + /* Maximum: 64 Bytes */ +#define _EP9LEN_TMP (8) + +// Endpoint Interrupt Enable Settings (EPIER) +// Endpoint Interrupt Enable Settings (EPIER) <0x0-0xFF:1> +// OUT Token Packet Received Interrupt Enable (OTRXIE) +// OUT Data Packet Received Interrupt Enable (ODRXIE) +// OUT Data Buffer Overrun Interrupt Enable (ODOVIE) +// IN Token Packet Received Interrupt Enable (ITRXIE) +// IN Data Packet Transmitted Interrupt Enable (IDTXIE) +// NAK Transmitted Interrupt Enable (NAKIE) +// STALL Transmitted Interrupt Enable (STLIE) +// USB Error Interrupt Enable (UERIE) +#define _EP9_IER (0x10) +// +// + +#endif diff --git a/bsp/ht32/ht32f52352/board/inc/ht32f5xxxx_conf.h b/bsp/ht32/ht32f52352/board/inc/ht32f5xxxx_conf.h new file mode 100644 index 0000000000..c78b9bb75d --- /dev/null +++ b/bsp/ht32/ht32f52352/board/inc/ht32f5xxxx_conf.h @@ -0,0 +1,556 @@ +/*********************************************************************************************************//** + * @file IP/Example/ht32f5xxxx_conf.h + * @version $Rev:: 7109 $ + * @date $Date:: 2023-08-10 #$ + * @brief Library configuration file. + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ +//-------- <<< Use Configuration Wizard in Context Menu >>> ----------------- + +/* Define to prevent recursive inclusion -------------------------------------------------------------------*/ +#ifndef __HT32F5XXXX_CONF_H +#define __HT32F5XXXX_CONF_H + +/* Exported constants --------------------------------------------------------------------------------------*/ + +#define RETARGET_USB 1 +#define RETARGET_SYSLOG 2 +#define RETARGET_COM1 10 +#define RETARGET_COM2 11 +#define RETARGET_USART0 12 +#define RETARGET_USART1 13 +#define RETARGET_UART0 14 +#define RETARGET_UART1 15 +#define RETARGET_UART2 16 +#define RETARGET_UART3 17 + + +/* Retarget settings of the C standard I/O library functions (printf, scanf, getchar, ...etc.) */ +/* +// Enable Retarget +// Retarget Port +// <1=> USB Virtual COM +// <2=> Syslog +// <10=> COM1 +// <11=> COM2 +// <12=> USART0 +// <13=> USART1 +// <14=> UART0 +// <15=> UART1 +// <16=> UART2 +// <17=> UART3 +// Enable Auto Return +// Auto Return function adds "\r" before "\n" automatically when print message by Retarget. +*/ +#define _RETARGET 1 +#define RETARGET_PORT 10 +#define _AUTO_RETURN 0 + +#ifndef AUTO_RETURN +#if (_AUTO_RETURN == 1) +#define AUTO_RETURN +#endif +#endif + +/* Enable Interrupt Mode for UxART Retarget +// Retarget COM/UxART Setting +// UxART Baudrate +// Enable Interrupt Mode for UxART Tx Retarget +// Define UxARTn_IRQHandler By Retarget (ht32_serial.c) +// Disable (RETARGET_DEFINE_HANDLER = 0) if application already have UxARTn_IRQHandler. +// RETARGET_UART_IRQHandler() shall be called by UxARTn_IRQHandler when disable. +// Tx Buffer Length (in byte) +// +*/ +#define RETARGET_UxART_BAUDRATE 115200 +#define RETARGET_INT_MODE 0 +#define RETARGET_DEFINE_HANDLER 1 +#define RETARGET_INT_BUFFER_SIZE 64 + +#if (_RETARGET == 1) +#if (RETARGET_PORT == RETARGET_USB) + #define RETARGET_IS_USB +// Retarget USB Virtual COM Setting +// Communication (Interrupt IN) +// <1=> Endpoint 1 +// <2=> Endpoint 2 +// <3=> Endpoint 3 +// <4=> Endpoint 4 +// <5=> Endpoint 5 +// <6=> Endpoint 6 +// <7=> Endpoint 7 +// Data Rx (Bulk OUT) +// <1=> Endpoint 1 +// <2=> Endpoint 2 +// <3=> Endpoint 3 +// <4=> Endpoint 4 +// <5=> Endpoint 5 +// <6=> Endpoint 6 +// <7=> Endpoint 7 +// Data Tx (Bulk IN) +// <1=> Endpoint 1 +// <2=> Endpoint 2 +// <3=> Endpoint 3 +// <4=> Endpoint 4 +// <5=> Endpoint 5 +// <6=> Endpoint 6 +// <7=> Endpoint 7 +// Communication Endpoint Buffer Length (in byte) <4-64:4> +// Data Rx Endpoint Buffer Length (in byte) <4-64:4> +// Data Tx Endpoint Buffer Length (in byte) <4-64:4> +// Rx Buffer Length (in byte) <64-1024:4> +// Tx Buffer Length (in byte) <1-63:1> +// Please use "SERIAL_Flush()" to sent out the buffer data immediately when Tx Buffer Length > 1. +// USB Tx Mode (BULK IN) +// <0=> Block Mode (Wait until both USB and terminal software are ready) +// <1=> Non-Block Mode (Drop data if USB or terminal software is not ready) +// Enable HSI Auto Trim By USB Function +// Need turn on if the USB clock source is from HSI (PLL USBPLL clock Source). + #define RETARGET_CTRL_EPT (5) + #define RETARGET_RX_EPT (6) + #define RETARGET_TX_EPT (7) + #define RETARGET_CTRL_EPTLEN (8) + #define RETARGET_RX_EPTLEN (64) + #define RETARGET_TX_EPTLEN (64) + #define RETARGET_BUFFER_SIZE (64) + #define RETARGET_TXBUFFER_SIZE (1) // Use "SERIAL_Flush()" to sent out the buffer data immediately when Tx Buffer Length > 1. + #define RETARGET_USB_MODE (0) + #define RETARGET_HSI_ATM (1) +// +#elif (RETARGET_PORT == RETARGET_COM1) + #define RETARGET_COM_PORT COM1 + #define RETARGET_USART_PORT COM1_PORT + #define RETARGET_UART_IRQn COM1_IRQn + #define RETARGET_UART_IRQHandler COM1_IRQHandler + #define RETARGET_IS_UART +#elif (RETARGET_PORT == RETARGET_COM2) + #define RETARGET_COM_PORT COM2 + #define RETARGET_USART_PORT COM2_PORT + #define RETARGET_UART_IRQn COM2_IRQn + #define RETARGET_UART_IRQHandler COM2_IRQHandler + #define RETARGET_IS_UART +#elif (RETARGET_PORT == RETARGET_USART0) + #define RETARGET_UxART_IPN USART0 + #define RETARGET_USART_PORT STRCAT2(HT_, RETARGET_UxART_IPN) + #define RETARGET_UART_IRQn STRCAT2(RETARGET_UxART_IPN, _IRQn) + #define RETARGET_UART_IRQHandler STRCAT2(RETARGET_UxART_IPN, _IRQHandler) + #define RETARGET_IS_UART +#elif (RETARGET_PORT == RETARGET_USART1) + #define RETARGET_UxART_IPN USART1 + #define RETARGET_USART_PORT STRCAT2(HT_, RETARGET_UxART_IPN) + #define RETARGET_UART_IRQn STRCAT2(RETARGET_UxART_IPN, _IRQn) + #define RETARGET_UART_IRQHandler STRCAT2(RETARGET_UxART_IPN, _IRQHandler) + #define RETARGET_IS_UART +#elif (RETARGET_PORT == RETARGET_UART0) + #define RETARGET_UxART_IPN UART0 + #define RETARGET_USART_PORT STRCAT2(HT_, RETARGET_UxART_IPN) + #define RETARGET_UART_IRQn STRCAT2(RETARGET_UxART_IPN, _IRQn) + #define RETARGET_UART_IRQHandler STRCAT2(RETARGET_UxART_IPN, _IRQHandler) + #define RETARGET_IS_UART +#elif (RETARGET_PORT == RETARGET_UART1) + #define RETARGET_UxART_IPN UART1 + #define RETARGET_USART_PORT STRCAT2(HT_, RETARGET_UxART_IPN) + #define RETARGET_UART_IRQn STRCAT2(RETARGET_UxART_IPN, _IRQn) + #define RETARGET_UART_IRQHandler STRCAT2(RETARGET_UxART_IPN, _IRQHandler) + #define RETARGET_IS_UART +#elif (RETARGET_PORT == RETARGET_UART2) + #define RETARGET_UxART_IPN UART2 + #define RETARGET_USART_PORT STRCAT2(HT_, RETARGET_UxART_IPN) + #define RETARGET_UART_IRQn STRCAT2(RETARGET_UxART_IPN, _IRQn) + #define RETARGET_UART_IRQHandler STRCAT2(RETARGET_UxART_IPN, _IRQHandler) + #define RETARGET_IS_UART +#elif (RETARGET_PORT == RETARGET_UART3) + #define RETARGET_UxART_IPN UART3 + #define RETARGET_USART_PORT STRCAT2(HT_, RETARGET_UxART_IPN) + #define RETARGET_UART_IRQn STRCAT2(RETARGET_UxART_IPN, _IRQn) + #define RETARGET_UART_IRQHandler STRCAT2(RETARGET_UxART_IPN, _IRQHandler) + #define RETARGET_IS_UART +#endif + extern void RETARGET_Configuration(void); +#else + #define RETARGET_Configuration(...) + #undef printf + #undef getchar + #define printf(...) + #define getchar() (0) +#endif + +#if (RETARGET_DEFINE_HANDLER == 0) +#undef RETARGET_UART_IRQHandler +#endif + +/* +// Enable HT32 Time Function +// Provide "Time_GetTick()" and "Time_Dealy()" functions. + +// Timer Selection +// <0=> BFTM0 +// <1=> BFTM1 +// <2=> SCTM0 +// <3=> SCTM1 +// <4=> SCTM2 +// <5=> SCTM3 +// <6=> PWM0 +// <7=> PWM1 +// <8=> PWM2 +// <9=> GPTM0 +// <10=> GPTM1 +// <11=> MCTM0 + +// Timer Clock Setting +// +// Timer Clock = (Core Clock) / (APB Peripheral Clock Prescaler) +// HTCFG_TIME_CLKSRC = _HTCFG_TIME_CORECLK / (2^HTCFG_TIME_PCLK_DIV) +// _HTCFG_TIME_CORECLK = LIBCFG_MAX_SPEED or HTCFG_TIME_CLK_MANUAL (selected by HTCFG_TIME_CLKSEL) + +// -- Core Clock Setting (CK_AHB) +// HTCFG_TIME_CLKSEL +// 0 = Default Maximum (LIBCFG_MAX_SPEED) +// 1 = Manual Input (HTCFG_TIME_CLK_MANUAL) +// <0=> Default Maximum (LIBCFG_MAX_SPEED) +// <1=> Manual Input (HTCFG_TIME_CLK_MANUAL) + +// -- Core Clock Manual Input (Hz) +// HTCFG_TIME_CLK_MANUAL +// Only meaningful when Core Clock Setting (HTCFG_TIME_CLKSEL) = Manual Input (1) + +// -- APB Peripheral Clock Prescaler +// HTCFG_TIME_PCLK_DIV +// <0=> /1 +// <1=> /2 +// <2=> /4 +// <3=> /8 + +// Time Tick (Hz, not applicable for BFTM) <1-1000000:100> +// Not applicable for BFTM, fixed TICKHZ to HTCFG_TIME_CLKSRC for BFTM. +*/ +#if (0) // Enable HT32 Time Function +#define HTCFG_TIME_IPSEL (0) +#define HTCFG_TIME_CLKSEL (0) // 0 = Default Maximum (LIBCFG_MAX_SPEED), 1 = Manual Input (HTCFG_TIME_CLKSRC) +#define HTCFG_TIME_CLK_MANUAL (20000000) // Only meaningful when HTCFG_TIME_CLKSEL = 1 (Manual Input) +#define HTCFG_TIME_PCLK_DIV (0) // 0 ~ 3. (/1, /2, /4, /8) +#define HTCFG_TIME_TICKHZ (1000) // Hz, not applicable for BFTM, fixed TICKHZ to HTCFG_TIME_CLKSRC for BFTM +#define HTCFG_TIME_MULTIPLE (1) // MUST be 1, 2, 4, 8. TICK = COUNT / MULTIPLE. Not applicable for BFTM. +/* + + Timer Clock = (Core Clock) / (APB Peripheral Clock Prescaler) + HTCFG_TIME_CLKSRC = (_HTCFG_TIME_CORECLK) / (2^HTCFG_TIME_PCLK_DIV) + where _HTCFG_TIME_CORECLK can be LIBCFG_MAX_SPEED or HTCFG_TIME_CLK_MANUAL (selected by HTCFG_TIME_CLKSEL) + + Tick Range: 0 ~ 2^32 / HTCFG_TIME_TICKHZ (maximum tick time) + Interrupt Time: _HTCFG_TIME_OVERFLOW_VALUE / (HTCFG_TIME_TICKHZ * HTCFG_TIME_MULTIPLE) Second + (Interrupt Time is not applicable for BFTM) + + Example: 32-bit BFTM with 48 MHz Timer Clock + HTCFG_TIME_TICKHZ = HTCFG_TIME_CLKSRC = 48000000 + Tick Range: 0 ~ 2^32 / 48000000 = 0 ~ 89.478485 Second (maximum tick time, return to 0 every 89.478485 Second) + BFTM do not use interrupt + + Example: 16-bit GPTM with 1 ms tick + HTCFG_TIME_TICKHZ = 1000 (Hz) + HTCFG_TIME_MULTIPLE = 1 (1 Timer Count = 1 Tick) + Tick Range: 0 ~ 2^32 / 1000 = 0 ~ 4294967 Second = 0 ~ 49.7 Day (maximum tick time, return to 0 every 49.7 Day) + Interrupt Time: 65536 / (1000 * 1) = 65.536 Second (Trigger interrupt every 65.536 Second) +*/ +#endif +/* +// +*/ + +/* !!! NOTICE !!! + * How to adjust the value of High Speed External oscillator (HSE)? + The default value of HSE is define by "HSE_VALUE" in "ht32fxxxxx_nn.h". + If your board uses a different HSE speed, please add a new compiler preprocessor + C define, "HSE_VALUE=n000000" ("n" represents n MHz) in the toolchain/IDE, + or edit the "HSE_VALUE" in the "ht32f5xxxx_conf.h" file (this file). +*/ +/* +// Enable User Define HSE Value +// Enable user define HSE value to overwrite default "HSE_VALUE" define in "ht32fxxxxx_nn.h". +// HSE Value (Hz) +*/ +#if (0) +#define HSE_VALUE 16000000 +#endif +/* +// +*/ + +/* +// Enable CKOUT Function +*/ +#define ENABLE_CKOUT 0 + +/* +// Enable Get CK_ADC of "CKCU_GetClocksFrequency()" +// Enable ADC0_Freq and ADC1_Freq of the "CKCU_GetClocksFrequency()" function. It required the division calculation (by C Library) and increased the code size. +*/ +#define HT32_LIB_ENABLE_GET_CK_ADC 0 + +/* The DEBUG definition to enter debug mode for library */ +/* +// Library Debug Mode +*/ +#define HT32_LIB_DEBUG 0 + + +/* Enable/disable the specific peripheral inclusion */ + +// Library Inclusion Configuration +/* ADC -----------------------------------------------------------------------------------------------------*/ +/* +// ADC Library +*/ +#define _ADC 1 + +/* AES -----------------------------------------------------------------------------------------------------*/ +/* +// AES Library +*/ +#define _AES 1 + +/* BFTM ----------------------------------------------------------------------------------------------------*/ +/* +// BFTM Library +*/ +#define _BFTM 1 + +/* CAN -----------------------------------------------------------------------------------------------------*/ +/* +// CAN Library +*/ +#define _CAN 1 + +/* Clock Control -------------------------------------------------------------------------------------------*/ +/* +// Clock Control Library +*/ +#define _CKCU 1 + +/* Comparator ----------------------------------------------------------------------------------------------*/ +/* +// Comparator Library +*/ +#define _CMP 1 + +/* CRC -----------------------------------------------------------------------------------------------------*/ +/* +// CRC Library +*/ +#define _CRC 1 + +/* DAC -----------------------------------------------------------------------------------------------------*/ +/* +// DAC Library +*/ +#define _DAC 1 + +/* DAC Dual 16-bit -----------------------------------------------------------------------------------------*/ +/* +// DAC_Dual16 Library +*/ +#define _DAC_DUAL16 1 + +/* DIV -----------------------------------------------------------------------------------------------------*/ +/* +// DIV Library +*/ +#define _DIV 1 + +/* EBI -----------------------------------------------------------------------------------------------------*/ +/* +// EBI Library +*/ +#define _EBI 1 + +/* EXTI ----------------------------------------------------------------------------------------------------*/ +/* +// EXTI Library +*/ +#define _EXTI 1 + +/* Flash ---------------------------------------------------------------------------------------------------*/ +/* +// Flash Library +*/ +#define _FLASH 1 + +/* GPIO ----------------------------------------------------------------------------------------------------*/ +/* +// GPIO Library +*/ +#define _GPIO 1 + +/* GPTM ----------------------------------------------------------------------------------------------------*/ +/* +// GPTM Library +*/ +#define _GPTM 1 + +/* I2C -----------------------------------------------------------------------------------------------------*/ +/* +// I2C Library +*/ +#define _I2C 1 + +/* I2S -----------------------------------------------------------------------------------------------------*/ +/* +// I2S Library +*/ +#define _I2S 1 + +/* LCD -----------------------------------------------------------------------------------------------------*/ +/* +// LCD Library +*/ +#define _LCD 1 + +/* LEDC ----------------------------------------------------------------------------------------------------*/ +/* +// LEDC Library +*/ +#define _LEDC 1 + +/* MCTM ----------------------------------------------------------------------------------------------------*/ +/* +// MCTM Library +*/ +#define _MCTM 1 + +/* MIDI ----------------------------------------------------------------------------------------------------*/ +/* +// MIDI Library +*/ +#define _MIDI 1 + +/* OPA -----------------------------------------------------------------------------------------------------*/ +/* +// OPA +*/ +#define _OPA 1 + +/* PDMA ----------------------------------------------------------------------------------------------------*/ +/* +// PDMA Library +*/ +#define _PDMA 1 + +/* PWM -----------------------------------------------------------------------------------------------------*/ +/* +// PWM Library +*/ +#define _PWM 1 + +/* PWRCU ---------------------------------------------------------------------------------------------------*/ +/* +// PWRCU Library +*/ +#define _PWRCU 1 + +/* RSTCU ---------------------------------------------------------------------------------------------------*/ +/* +// RSTCU Library +*/ +#define _RSTCU 1 + +/* RTC -----------------------------------------------------------------------------------------------------*/ +/* +// RTC Library +*/ +#define _RTC 1 + +/* SCI -----------------------------------------------------------------------------------------------------*/ +/* +// SCI Library +*/ +#define _SCI 1 + +/* SCTM ----------------------------------------------------------------------------------------------------*/ +/* +// SCTM Library +*/ +#define _SCTM 1 + +/* SLED ----------------------------------------------------------------------------------------------------*/ +/* +// SLED Library +*/ +#define _SLED 1 + +/* SPI -----------------------------------------------------------------------------------------------------*/ +/* +// SPI Library +*/ +#define _SPI 1 + +/* TKEY ----------------------------------------------------------------------------------------------------*/ +/* +// TKEY Library +*/ +#define _TKEY 1 + +/* USART ---------------------------------------------------------------------------------------------------*/ +/* +// USART/UART Library +*/ +#define _USART 1 + +/* USBD ----------------------------------------------------------------------------------------------------*/ +/* +// USB Library +*/ +#define _USB 1 + +/* WDT -----------------------------------------------------------------------------------------------------*/ +/* +// WDT Library +*/ +#define _WDT 1 + +/* Misc ----------------------------------------------------------------------------------------------------*/ +/* +// Misc Library +*/ +#define _MISC 1 + +/* Serial --------------------------------------------------------------------------------------------------*/ +/* +// Serial Library +*/ +#define _SERIAL 1 + +/* Software DIV --------------------------------------------------------------------------------------------*/ +/* +// Software Divider Library +*/ +#define _SWDIV 1 + +/* Software Random Number ----------------------------------------------------------------------------------*/ +/* +// Software Random Number Library +*/ +#define _SWRAND 1 + + +// + +#endif diff --git a/bsp/ht32/ht32f52352/board/linker_scripts/link.icf b/bsp/ht32/ht32f52352/board/linker_scripts/link.icf new file mode 100644 index 0000000000..65c2bfc8b7 --- /dev/null +++ b/bsp/ht32/ht32f52352/board/linker_scripts/link.icf @@ -0,0 +1,28 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x08000000; +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_ROM_start__ = 0x08000000; +define symbol __ICFEDIT_region_ROM_end__ = 0x080FFFFF; +define symbol __ICFEDIT_region_RAM_start__ = 0x20000000; +define symbol __ICFEDIT_region_RAM_end__ = 0x20017FFF; +/*-Sizes-*/ +define symbol __ICFEDIT_size_cstack__ = 0x0400; +define symbol __ICFEDIT_size_heap__ = 0x0000; +/**** End of ICF editor section. ###ICF###*/ + +define memory mem with size = 4G; +define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; +define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; + +initialize by copy { readwrite }; +do not initialize { section .noinit }; + +place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; + +place in ROM_region { readonly }; +place in RAM_region { readwrite, last block CSTACK}; \ No newline at end of file diff --git a/bsp/ht32/ht32f52352/board/linker_scripts/link.lds b/bsp/ht32/ht32f52352/board/linker_scripts/link.lds new file mode 100644 index 0000000000..27269dd77e --- /dev/null +++ b/bsp/ht32/ht32f52352/board/linker_scripts/link.lds @@ -0,0 +1,156 @@ +/* + * linker script for AT32 with GNU ld + */ + +/* Program Entry, set to mark it as "used" and avoid gc */ +MEMORY +{ + ROM (rx) : ORIGIN = 0x08000000, LENGTH = 1024k /* 1024KB flash */ + RAM (rw) : ORIGIN = 0x20000000, LENGTH = 96k /* 96K sram */ +} +ENTRY(Reset_Handler) +_system_stack_size = 0x200; + +SECTIONS +{ + .text : + { + . = ALIGN(4); + _stext = .; + KEEP(*(.isr_vector)) /* Startup code */ + + . = ALIGN(4); + *(.text) /* remaining code */ + *(.text.*) /* remaining code */ + *(.rodata) /* read-only data (constants) */ + *(.rodata*) + *(.glue_7) + *(.glue_7t) + *(.gnu.linkonce.t*) + + /* section information for finsh shell */ + . = ALIGN(4); + __fsymtab_start = .; + KEEP(*(FSymTab)) + __fsymtab_end = .; + + . = ALIGN(4); + __vsymtab_start = .; + KEEP(*(VSymTab)) + __vsymtab_end = .; + + /* section information for initial. */ + . = ALIGN(4); + __rt_init_start = .; + KEEP(*(SORT(.rti_fn*))) + __rt_init_end = .; + + . = ALIGN(4); + + PROVIDE(__ctors_start__ = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array)) + PROVIDE(__ctors_end__ = .); + + . = ALIGN(4); + + _etext = .; + } > ROM = 0 + + /* .ARM.exidx is sorted, so has to go in its own output section. */ + __exidx_start = .; + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + + /* This is used by the startup in order to initialize the .data secion */ + _sidata = .; + } > ROM + __exidx_end = .; + + /* .data section which is used for initialized data */ + + .data : AT (_sidata) + { + . = ALIGN(4); + /* This is used by the startup in order to initialize the .data secion */ + _sdata = . ; + + *(.data) + *(.data.*) + *(.gnu.linkonce.d*) + + PROVIDE(__dtors_start__ = .); + KEEP(*(SORT(.dtors.*))) + KEEP(*(.dtors)) + PROVIDE(__dtors_end__ = .); + + . = ALIGN(4); + /* This is used by the startup in order to initialize the .data secion */ + _edata = . ; + } >RAM + + .stack : + { + . = ALIGN(4); + _sstack = .; + . = . + _system_stack_size; + . = ALIGN(4); + _estack = .; + } >RAM + + __bss_start = .; + .bss : + { + . = ALIGN(4); + /* This is used by the startup in order to initialize the .bss secion */ + _sbss = .; + + *(.bss) + *(.bss.*) + *(COMMON) + + . = ALIGN(4); + /* This is used by the startup in order to initialize the .bss secion */ + _ebss = . ; + + *(.bss.init) + } > RAM + __bss_end = .; + + _end = .; + + /* Stabs debugging sections. */ + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + /* DWARF debug sections. + * Symbols in the DWARF debugging sections are relative to the beginning + * of the section so we begin them at 0. */ + /* DWARF 1 */ + .debug 0 : { *(.debug) } + .line 0 : { *(.line) } + /* GNU DWARF 1 extensions */ + .debug_srcinfo 0 : { *(.debug_srcinfo) } + .debug_sfnames 0 : { *(.debug_sfnames) } + /* DWARF 1.1 and DWARF 2 */ + .debug_aranges 0 : { *(.debug_aranges) } + .debug_pubnames 0 : { *(.debug_pubnames) } + /* DWARF 2 */ + .debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_line 0 : { *(.debug_line) } + .debug_frame 0 : { *(.debug_frame) } + .debug_str 0 : { *(.debug_str) } + .debug_loc 0 : { *(.debug_loc) } + .debug_macinfo 0 : { *(.debug_macinfo) } + /* SGI/MIPS DWARF 2 extensions */ + .debug_weaknames 0 : { *(.debug_weaknames) } + .debug_funcnames 0 : { *(.debug_funcnames) } + .debug_typenames 0 : { *(.debug_typenames) } + .debug_varnames 0 : { *(.debug_varnames) } +} diff --git a/bsp/ht32/ht32f52352/board/linker_scripts/link.sct b/bsp/ht32/ht32f52352/board/linker_scripts/link.sct new file mode 100644 index 0000000000..ece577cb3e --- /dev/null +++ b/bsp/ht32/ht32f52352/board/linker_scripts/link.sct @@ -0,0 +1,15 @@ +; ************************************************************* +; *** Scatter-Loading Description File generated by uVision *** +; ************************************************************* + +LR_IROM1 0x00000000 0x0001FE00 { ; load region size_region + ER_IROM1 0x00000000 0x0001FE00 { ; load address = execution address + *.o (RESET, +First) + *(InRoot$$Sections) + .ANY (+RO) + } + RW_IRAM1 0x20000000 0x00004000 { ; RW data + .ANY (+RW +ZI) + } +} + diff --git a/bsp/ht32/ht32f52352/board/src/board.c b/bsp/ht32/ht32f52352/board/src/board.c new file mode 100644 index 0000000000..e0160468e9 --- /dev/null +++ b/bsp/ht32/ht32f52352/board/src/board.c @@ -0,0 +1,17 @@ +/* + * Copyright (c) 2006-2024, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2024-04-08 QT-one first version + */ + +#include "board.h" + +/* This feature will initialize the HT32 chip clock */ +void rt_hw_board_clock_init(void) +{ + +} diff --git a/bsp/ht32/ht32f52352/board/src/ht32_msp.c b/bsp/ht32/ht32f52352/board/src/ht32_msp.c new file mode 100644 index 0000000000..1315b9723f --- /dev/null +++ b/bsp/ht32/ht32f52352/board/src/ht32_msp.c @@ -0,0 +1,138 @@ +/* + * Copyright (c) 2006-2024, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2024-04-08 QT-one first version + */ + +#include "ht32_msp.h" + +/* GPIO configuration for UART */ +#ifdef BSP_USING_UART +void ht32_usart_gpio_init(void *instance) +{ + CKCU_PeripClockConfig_TypeDef CKCUClock = {{0}}; + HT_USART_TypeDef *usart_x = (HT_USART_TypeDef *)instance; +#ifdef BSP_USING_USART0 + if (HT_USART0 == usart_x) + { + CKCUClock.Bit.HTCFG_USART0_TX_GPIO_CLK = 1; + CKCUClock.Bit.HTCFG_USART0_RX_GPIO_CLK = 1; + CKCU_PeripClockConfig(CKCUClock, ENABLE); + /* Turn on UxART Rx internal pull up resistor to prevent unknow state */ + GPIO_PullResistorConfig(HTCFG_USART0_RX_GPIO_PORT, HTCFG_USART0_RX_GPIO_PIN, GPIO_PR_UP); + /* Config AFIO mode as UxART function */ + AFIO_GPxConfig(HTCFG_USART0_TX_GPIO_ID, HTCFG_USART0_TX_GPIO_PIN, AFIO_FUN_USART_UART); + AFIO_GPxConfig(HTCFG_USART0_RX_GPIO_ID, HTCFG_USART0_RX_GPIO_PIN, AFIO_FUN_USART_UART); + } +#endif +#ifdef BSP_USING_USART1 + if (HT_USART1 == usart_x) + { + CKCUClock.Bit.HTCFG_USART1_TX_GPIO_CLK = 1; + CKCUClock.Bit.HTCFG_USART1_RX_GPIO_CLK = 1; + CKCU_PeripClockConfig(CKCUClock, ENABLE); + /* Turn on UxART Rx internal pull up resistor to prevent unknow state */ + GPIO_PullResistorConfig(HTCFG_USART1_RX_GPIO_PORT, HTCFG_USART1_RX_GPIO_PIN, GPIO_PR_UP); + /* Config AFIO mode as UxART function */ + AFIO_GPxConfig(HTCFG_USART1_TX_GPIO_ID, HTCFG_USART1_TX_GPIO_PIN, AFIO_FUN_USART_UART); + AFIO_GPxConfig(HTCFG_USART1_RX_GPIO_ID, HTCFG_USART1_RX_GPIO_PIN, AFIO_FUN_USART_UART); + } +#endif +#ifdef BSP_USING_UART0 + if (HT_UART0 == usart_x) + { + CKCUClock.Bit.HTCFG_UART0_TX_GPIO_CLK = 1; + CKCUClock.Bit.HTCFG_UART0_RX_GPIO_CLK = 1; + CKCU_PeripClockConfig(CKCUClock, ENABLE); + /* Turn on UxART Rx internal pull up resistor to prevent unknow state */ + GPIO_PullResistorConfig(HTCFG_UART0_RX_GPIO_PORT, HTCFG_UART0_RX_GPIO_PIN, GPIO_PR_UP); + /* Config AFIO mode as UxART function */ + AFIO_GPxConfig(HTCFG_UART0_TX_GPIO_ID, HTCFG_UART0_TX_GPIO_PIN, AFIO_FUN_USART_UART); + AFIO_GPxConfig(HTCFG_UART0_RX_GPIO_ID, HTCFG_UART0_RX_GPIO_PIN, AFIO_FUN_USART_UART); + } +#endif +#ifdef BSP_USING_UART1 + if (HT_UART1 == usart_x) + { + CKCUClock.Bit.HTCFG_UART1_TX_GPIO_CLK = 1; + CKCUClock.Bit.HTCFG_UART1_RX_GPIO_CLK = 1; + CKCU_PeripClockConfig(CKCUClock, ENABLE); + /* Turn on UxART Rx internal pull up resistor to prevent unknow state */ + GPIO_PullResistorConfig(HTCFG_UART1_RX_GPIO_PORT, HTCFG_UART1_RX_GPIO_PIN, GPIO_PR_UP); + /* Config AFIO mode as UxART function */ + AFIO_GPxConfig(HTCFG_UART1_TX_GPIO_ID, HTCFG_UART1_TX_GPIO_PIN, AFIO_FUN_USART_UART); + AFIO_GPxConfig(HTCFG_UART1_RX_GPIO_ID, HTCFG_UART1_RX_GPIO_PIN, AFIO_FUN_USART_UART); + } +#endif +} +#endif + +/* GPIO configuration for SPI */ +#ifdef BSP_USING_SPI +void ht32_spi_gpio_init(void *instance) +{ + CKCU_PeripClockConfig_TypeDef CKCUClock = {{0}}; + HT_SPI_TypeDef *spi_x = (HT_SPI_TypeDef *)instance; +#ifdef BSP_USING_SPI0 + if (HT_SPI0 == spi_x) + { + CKCUClock.Bit.HTCFG_SPI0_SCK_GPIO_CLK = 1; + CKCUClock.Bit.HTCFG_SPI0_MISO_GPIO_CLK = 1; + CKCUClock.Bit.HTCFG_SPI0_MOSI_GPIO_CLK = 1; + CKCU_PeripClockConfig(CKCUClock, ENABLE); + + AFIO_GPxConfig(HTCFG_SPI0_SCK_GPIO_ID, HTCFG_SPI0_SCK_GPIO_PIN, AFIO_FUN_SPI); + AFIO_GPxConfig(HTCFG_SPI0_MISO_GPIO_ID, HTCFG_SPI0_MISO_GPIO_PIN, AFIO_FUN_SPI); + AFIO_GPxConfig(HTCFG_SPI0_MOSI_GPIO_ID, HTCFG_SPI0_MOSI_GPIO_PIN, AFIO_FUN_SPI); + } +#endif +#ifdef BSP_USING_SPI1 + if (HT_SPI1 == spi_x) + { + CKCUClock.Bit.HTCFG_SPI1_SCK_GPIO_CLK = 1; + CKCUClock.Bit.HTCFG_SPI1_MISO_GPIO_CLK = 1; + CKCUClock.Bit.HTCFG_SPI1_MOSI_GPIO_CLK = 1; + CKCU_PeripClockConfig(CKCUClock, ENABLE); + + AFIO_GPxConfig(HTCFG_SPI1_SCK_GPIO_ID, HTCFG_SPI1_SCK_GPIO_PIN, AFIO_FUN_SPI); + AFIO_GPxConfig(HTCFG_SPI1_MISO_GPIO_ID, HTCFG_SPI1_MISO_GPIO_PIN, AFIO_FUN_SPI); + AFIO_GPxConfig(HTCFG_SPI1_MOSI_GPIO_ID, HTCFG_SPI1_MOSI_GPIO_PIN, AFIO_FUN_SPI); + } +#endif +} +#endif + +/* GPIO configuration for I2C */ +#ifdef BSP_USING_I2C +void ht32_i2c_gpio_init(void *instance) +{ + CKCU_PeripClockConfig_TypeDef CKCUClock = {{0}}; + HT_I2C_TypeDef *i2c_x = (HT_I2C_TypeDef *)instance; +#ifdef BSP_USING_I2C0 + if (HT_I2C0 == i2c_x) + { + CKCUClock.Bit.HTCFG_I2C0_SCL_GPIO_CLK = 1; + CKCUClock.Bit.HTCFG_I2C0_SDA_GPIO_CLK = 1; + CKCU_PeripClockConfig(CKCUClock, ENABLE); + /* Configure GPIO to I2C mode */ + AFIO_GPxConfig(HTCFG_I2C0_SCL_GPIO_ID, HTCFG_I2C0_SCL_GPIO_PIN, AFIO_FUN_I2C); + AFIO_GPxConfig(HTCFG_I2C0_SDA_GPIO_ID, HTCFG_I2C0_SDA_GPIO_PIN, AFIO_FUN_I2C); + } +#endif +#ifdef BSP_USING_I2C1 + if (HT_I2C1 == i2c_x) + { + CKCUClock.Bit.HTCFG_I2C1_SCL_GPIO_CLK = 1; + CKCUClock.Bit.HTCFG_I2C1_SDA_GPIO_CLK = 1; + CKCU_PeripClockConfig(CKCUClock, ENABLE); + /* Configure GPIO to I2C mode */ + AFIO_GPxConfig(HTCFG_I2C1_SCL_GPIO_ID, HTCFG_I2C1_SCL_GPIO_PIN, AFIO_FUN_I2C); + AFIO_GPxConfig(HTCFG_I2C1_SDA_GPIO_ID, HTCFG_I2C1_SDA_GPIO_PIN, AFIO_FUN_I2C); + } +#endif +} +#endif diff --git a/bsp/ht32/ht32f52352/figures/board.png b/bsp/ht32/ht32f52352/figures/board.png new file mode 100644 index 0000000000..2e7fb71882 Binary files /dev/null and b/bsp/ht32/ht32f52352/figures/board.png differ diff --git a/bsp/ht32/ht32f52352/project.uvoptx b/bsp/ht32/ht32f52352/project.uvoptx new file mode 100644 index 0000000000..9668fa37f7 --- /dev/null +++ b/bsp/ht32/ht32f52352/project.uvoptx @@ -0,0 +1,1183 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + rt-thread + 0x4 + ARM-ADS + + 12000000 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\build\keil\List\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 255 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 2 + + + + + + + + + + + BIN\CMSIS_AGDI.dll + + + + 0 + CMSIS_AGDI + -X"Any" -UAny -O206 -S0 -C0 -P00 -N00("ARM CoreSight SW-DP") -D00(0BC11477) -L00(0) -TO18 -TC10000000 -TP20 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO15 -FD20000000 -FC1000 -FN2 -FF0HT32F.FLM -FS00 -FL0100000 -FP0($$Device:HT32F52352$ARM\Flash\HT32F.FLM) -FF1HT32F_OPT.FLM -FS11FF00000 -FL11000 -FP1($$Device:HT32F52352$ARM\Flash\HT32F_OPT.FLM) + + + 0 + UL2CM3 + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN2 -FF0HT32F -FS00 -FL0100000 -FF1HT32F_OPT -FS11FF00000 -FL11000 -FP0($$Device:HT32F52352$ARM\Flash\HT32F.FLM) -FP1($$Device:HT32F52352$ARM\Flash\HT32F_OPT.FLM)) + + + + + 0 + + + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + Applications + 0 + 0 + 0 + 0 + + 1 + 1 + 1 + 0 + 0 + 0 + applications\main.c + main.c + 0 + 0 + + + + + Compiler + 0 + 0 + 0 + 0 + + 2 + 2 + 1 + 0 + 0 + 0 + ..\..\..\components\libc\compilers\armlibc\syscall_mem.c + syscall_mem.c + 0 + 0 + + + 2 + 3 + 1 + 0 + 0 + 0 + ..\..\..\components\libc\compilers\armlibc\syscalls.c + syscalls.c + 0 + 0 + + + 2 + 4 + 1 + 0 + 0 + 0 + ..\..\..\components\libc\compilers\common\cctype.c + cctype.c + 0 + 0 + + + 2 + 5 + 1 + 0 + 0 + 0 + ..\..\..\components\libc\compilers\common\cstdlib.c + cstdlib.c + 0 + 0 + + + 2 + 6 + 1 + 0 + 0 + 0 + ..\..\..\components\libc\compilers\common\cstring.c + cstring.c + 0 + 0 + + + 2 + 7 + 1 + 0 + 0 + 0 + ..\..\..\components\libc\compilers\common\ctime.c + ctime.c + 0 + 0 + + + 2 + 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+ + + + + + idle.c + 1 + ..\..\..\src\idle.c + + + 2 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 + + + __RT_KERNEL_SOURCE__ + + + + + + + + + ipc.c + 1 + ..\..\..\src\ipc.c + + + 2 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 + + + __RT_KERNEL_SOURCE__ + + + + + + + + + irq.c + 1 + ..\..\..\src\irq.c + + + 2 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 + + + __RT_KERNEL_SOURCE__ + + + + + + + + + kstdio.c + 1 + ..\..\..\src\klibc\kstdio.c + + + 2 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 + + + __RT_KERNEL_SOURCE__ + + + + + + + + + kstring.c + 1 + ..\..\..\src\klibc\kstring.c + + + 2 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 + + + __RT_KERNEL_SOURCE__ + + + + + + + + + kservice.c + 1 + ..\..\..\src\kservice.c + + + 2 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 + + + __RT_KERNEL_SOURCE__ + + + + + + + + + mem.c + 1 + ..\..\..\src\mem.c + + + 2 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 + + + __RT_KERNEL_SOURCE__ + + + + + + + + + memheap.c + 1 + ..\..\..\src\memheap.c + + + 2 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 + + + __RT_KERNEL_SOURCE__ + + + + + + + + + mempool.c + 1 + ..\..\..\src\mempool.c + + + 2 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 + + + __RT_KERNEL_SOURCE__ + + + + + + + + + object.c + 1 + ..\..\..\src\object.c + + + 2 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 + + + __RT_KERNEL_SOURCE__ + + + + + + + + + scheduler_comm.c + 1 + ..\..\..\src\scheduler_comm.c + + + 2 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 + + + __RT_KERNEL_SOURCE__ + + + + + + + + + scheduler_up.c + 1 + ..\..\..\src\scheduler_up.c + + + 2 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 + + + __RT_KERNEL_SOURCE__ + + + + + + + + + thread.c + 1 + ..\..\..\src\thread.c + + + 2 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 + + + __RT_KERNEL_SOURCE__ + + + + + + + + + timer.c + 1 + ..\..\..\src\timer.c + + + 2 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 + + + __RT_KERNEL_SOURCE__ + + + + + + + + + + + libcpu + + + div0.c + 1 + ..\..\..\libcpu\arm\common\div0.c + + + showmem.c + 1 + ..\..\..\libcpu\arm\common\showmem.c + + + context_rvds.S + 2 + ..\..\..\libcpu\arm\cortex-m0\context_rvds.S + + + cpuport.c + 1 + ..\..\..\libcpu\arm\cortex-m0\cpuport.c + + + + + Libraries + + + ht32f5xxxx_sci.c + 1 + ..\libraries\HT32_STD_5xxxx_FWLib\library\HT32F5xxxx_Driver\src\ht32f5xxxx_sci.c + + + ht32f5xxxx_rstcu.c + 1 + ..\libraries\HT32_STD_5xxxx_FWLib\library\HT32F5xxxx_Driver\src\ht32f5xxxx_rstcu.c + + + ht32f5xxxx_adc.c + 1 + ..\libraries\HT32_STD_5xxxx_FWLib\library\HT32F5xxxx_Driver\src\ht32f5xxxx_adc.c + + + ht32f5xxxx_cmp.c + 1 + ..\libraries\HT32_STD_5xxxx_FWLib\library\HT32F5xxxx_Driver\src\ht32f5xxxx_cmp.c + + + ht32_cm0plus_misc.c + 1 + ..\libraries\HT32_STD_5xxxx_FWLib\library\HT32F5xxxx_Driver\src\ht32_cm0plus_misc.c + + + ht32f5xxxx_crc.c + 1 + ..\libraries\HT32_STD_5xxxx_FWLib\library\HT32F5xxxx_Driver\src\ht32f5xxxx_crc.c + + + ht32f5xxxx_spi.c + 1 + ..\libraries\HT32_STD_5xxxx_FWLib\library\HT32F5xxxx_Driver\src\ht32f5xxxx_spi.c + + + ht32f5xxxx_pwrcu.c + 1 + ..\libraries\HT32_STD_5xxxx_FWLib\library\HT32F5xxxx_Driver\src\ht32f5xxxx_pwrcu.c + + + ht32f5xxxx_pdma.c + 1 + ..\libraries\HT32_STD_5xxxx_FWLib\library\HT32F5xxxx_Driver\src\ht32f5xxxx_pdma.c + + + ht32f5xxxx_mctm.c + 1 + ..\libraries\HT32_STD_5xxxx_FWLib\library\HT32F5xxxx_Driver\src\ht32f5xxxx_mctm.c + + + ht32f5xxxx_rtc.c + 1 + ..\libraries\HT32_STD_5xxxx_FWLib\library\HT32F5xxxx_Driver\src\ht32f5xxxx_rtc.c + + + ht32f5xxxx_i2s.c + 1 + ..\libraries\HT32_STD_5xxxx_FWLib\library\HT32F5xxxx_Driver\src\ht32f5xxxx_i2s.c + + + ht32f5xxxx_usbd.c + 1 + ..\libraries\HT32_STD_5xxxx_FWLib\library\HT32F5xxxx_Driver\src\ht32f5xxxx_usbd.c + + + ht32f5xxxx_wdt.c + 1 + ..\libraries\HT32_STD_5xxxx_FWLib\library\HT32F5xxxx_Driver\src\ht32f5xxxx_wdt.c + + + ht32f5xxxx_ebi.c + 1 + ..\libraries\HT32_STD_5xxxx_FWLib\library\HT32F5xxxx_Driver\src\ht32f5xxxx_ebi.c + + + ht32f5xxxx_tm.c + 1 + ..\libraries\HT32_STD_5xxxx_FWLib\library\HT32F5xxxx_Driver\src\ht32f5xxxx_tm.c + + + ht32f5xxxx_ckcu.c + 1 + ..\libraries\HT32_STD_5xxxx_FWLib\library\HT32F5xxxx_Driver\src\ht32f5xxxx_ckcu.c + + + ht32f5xxxx_gpio.c + 1 + ..\libraries\HT32_STD_5xxxx_FWLib\library\HT32F5xxxx_Driver\src\ht32f5xxxx_gpio.c + + + ht32f5xxxx_exti.c + 1 + ..\libraries\HT32_STD_5xxxx_FWLib\library\HT32F5xxxx_Driver\src\ht32f5xxxx_exti.c + + + ht32f5xxxx_bftm.c + 1 + ..\libraries\HT32_STD_5xxxx_FWLib\library\HT32F5xxxx_Driver\src\ht32f5xxxx_bftm.c + + + ht32f5xxxx_usart.c + 1 + ..\libraries\HT32_STD_5xxxx_FWLib\library\HT32F5xxxx_Driver\src\ht32f5xxxx_usart.c + + + ht32f5xxxx_i2c.c + 1 + ..\libraries\HT32_STD_5xxxx_FWLib\library\HT32F5xxxx_Driver\src\ht32f5xxxx_i2c.c + + + ht32f5xxxx_flash.c + 1 + ..\libraries\HT32_STD_5xxxx_FWLib\library\HT32F5xxxx_Driver\src\ht32f5xxxx_flash.c + + + system_ht32f5xxxx_01.c + 1 + ..\libraries\HT32_STD_5xxxx_FWLib\library\Device\Holtek\HT32F5xxxx\Source\system_ht32f5xxxx_01.c + + + + + + + + + + + + + + diff --git a/bsp/ht32/ht32f52352/rtconfig.h b/bsp/ht32/ht32f52352/rtconfig.h new file mode 100644 index 0000000000..3caf5a5be0 --- /dev/null +++ b/bsp/ht32/ht32f52352/rtconfig.h @@ -0,0 +1,271 @@ +#ifndef RT_CONFIG_H__ +#define RT_CONFIG_H__ + +/* Automatically generated file; DO NOT EDIT. */ +/* RT-Thread Configuration */ + +/* RT-Thread Kernel */ + +#define RT_NAME_MAX 8 +#define RT_CPUS_NR 1 +#define RT_ALIGN_SIZE 4 +#define RT_THREAD_PRIORITY_32 +#define RT_THREAD_PRIORITY_MAX 32 +#define RT_TICK_PER_SECOND 1000 +#define RT_USING_OVERFLOW_CHECK +#define RT_USING_HOOK +#define RT_HOOK_USING_FUNC_PTR +#define RT_USING_IDLE_HOOK +#define RT_IDLE_HOOK_LIST_SIZE 4 +#define IDLE_THREAD_STACK_SIZE 256 + +/* kservice optimization */ + +#define RT_USING_DEBUG +#define RT_DEBUGING_COLOR +#define RT_DEBUGING_CONTEXT + +/* Inter-Thread communication */ + +#define RT_USING_SEMAPHORE +#define RT_USING_MUTEX +#define RT_USING_EVENT +#define RT_USING_MAILBOX +#define RT_USING_MESSAGEQUEUE + +/* Memory Management */ + +#define RT_USING_MEMPOOL +#define RT_USING_SMALL_MEM +#define RT_USING_MEMHEAP +#define RT_MEMHEAP_FAST_MODE +#define RT_USING_SMALL_MEM_AS_HEAP +#define RT_USING_HEAP +#define RT_USING_DEVICE +#define RT_USING_CONSOLE +#define RT_CONSOLEBUF_SIZE 128 +#define RT_CONSOLE_DEVICE_NAME "usart1" +#define RT_VER_NUM 0x50100 +#define RT_BACKTRACE_LEVEL_MAX_NR 32 +#define ARCH_ARM +#define ARCH_ARM_CORTEX_M +#define ARCH_ARM_CORTEX_M0 + +/* RT-Thread Components */ + +#define RT_USING_COMPONENTS_INIT +#define RT_USING_USER_MAIN +#define RT_MAIN_THREAD_STACK_SIZE 2048 +#define RT_MAIN_THREAD_PRIORITY 10 +#define RT_USING_MSH +#define RT_USING_FINSH +#define FINSH_USING_MSH +#define FINSH_THREAD_NAME "tshell" +#define FINSH_THREAD_PRIORITY 20 +#define FINSH_THREAD_STACK_SIZE 4096 +#define FINSH_USING_HISTORY +#define FINSH_HISTORY_LINES 5 +#define FINSH_USING_SYMTAB +#define FINSH_CMD_SIZE 80 +#define MSH_USING_BUILT_IN_COMMANDS +#define FINSH_USING_DESCRIPTION +#define FINSH_ARG_MAX 10 +#define FINSH_USING_OPTION_COMPLETION + +/* DFS: device virtual file system */ + + +/* Device Drivers */ + +#define RT_USING_DEVICE_IPC +#define RT_UNAMED_PIPE_NUMBER 64 +#define RT_USING_SERIAL +#define RT_USING_SERIAL_V1 +#define RT_SERIAL_USING_DMA +#define RT_SERIAL_RB_BUFSZ 64 +#define RT_USING_I2C +#define RT_USING_I2C_BITOPS +#define RT_USING_SPI +#define RT_USING_PIN + +/* Using USB */ + + +/* C/C++ and POSIX layer */ + +/* ISO-ANSI C layer */ + +/* Timezone and Daylight Saving Time */ + +#define RT_LIBC_USING_LIGHT_TZ_DST +#define RT_LIBC_TZ_DEFAULT_HOUR 8 +#define RT_LIBC_TZ_DEFAULT_MIN 0 +#define RT_LIBC_TZ_DEFAULT_SEC 0 + +/* POSIX (Portable Operating System Interface) layer */ + + +/* Interprocess Communication (IPC) */ + + +/* Socket is in the 'Network' category */ + + +/* Network */ + + +/* Memory protection */ + + +/* Utilities */ + + +/* RT-Thread Utestcases */ + + +/* RT-Thread online packages */ + +/* IoT - internet of things */ + + +/* Wi-Fi */ + +/* Marvell WiFi */ + + +/* Wiced WiFi */ + + +/* CYW43012 WiFi */ + + +/* BL808 WiFi */ + + +/* CYW43439 WiFi */ + + +/* IoT Cloud */ + + +/* security packages */ + + +/* language packages */ + +/* JSON: JavaScript Object Notation, a lightweight data-interchange format */ + + +/* XML: Extensible Markup Language */ + + +/* multimedia packages */ + +/* LVGL: powerful and easy-to-use embedded GUI library */ + + +/* u8g2: a monochrome graphic library */ + + +/* tools packages */ + + +/* system packages */ + +/* enhanced kernel services */ + + +/* acceleration: Assembly language or algorithmic acceleration packages */ + + +/* CMSIS: ARM Cortex-M Microcontroller Software Interface Standard */ + + +/* Micrium: Micrium software products porting for RT-Thread */ + + +/* peripheral libraries and drivers */ + +/* HAL & SDK Drivers */ + +/* STM32 HAL & SDK Drivers */ + + +/* Kendryte SDK */ + + +/* sensors drivers */ + + +/* touch drivers */ + + +/* AI packages */ + + +/* Signal Processing and Control Algorithm Packages */ + + +/* miscellaneous packages */ + +/* project laboratory */ + +/* samples: kernel and components samples */ + + +/* entertainment: terminal games and other interesting software packages */ + + +/* Arduino libraries */ + + +/* Projects and Demos */ + + +/* Sensors */ + + +/* Display */ + + +/* Timing */ + + +/* Data Processing */ + + +/* Data Storage */ + +/* Communication */ + + +/* Device Control */ + + +/* Other */ + + +/* Signal IO */ + + +/* Uncategorized */ + +#define SOC_FAMILY_HT32 +#define SOC_SERIES_HT32F5 + +/* Hardware Drivers Config */ + +#define SOC_HT32F52352 + +/* Onboard Peripheral Drivers */ + +/* On-chip Peripheral Drivers */ + +#define BSP_USING_GPIO +#define BSP_USING_UART +#define BSP_USING_USART1 + +/* Board extended module Drivers */ + + +#endif diff --git a/bsp/ht32/ht32f52352/rtconfig.py b/bsp/ht32/ht32f52352/rtconfig.py new file mode 100644 index 0000000000..964fa9313e --- /dev/null +++ b/bsp/ht32/ht32f52352/rtconfig.py @@ -0,0 +1,152 @@ +import os + +# toolchains options +ARCH='arm' +CPU='cortex-m0' +CROSS_TOOL='keil' + +# bsp lib config +BSP_LIBRARY_TYPE = None + +if os.getenv('RTT_CC'): + CROSS_TOOL = os.getenv('RTT_CC') +if os.getenv('RTT_ROOT'): + RTT_ROOT = os.getenv('RTT_ROOT') + +# cross_tool provides the cross compiler +# EXEC_PATH is the compiler execute path, for example, CodeSourcery, Keil MDK, IAR +if CROSS_TOOL == 'gcc': + PLATFORM = 'gcc' + EXEC_PATH = r'C:\Users\XXYYZZ' +elif CROSS_TOOL == 'keil': + PLATFORM = 'armcc' +# EXEC_PATH = r'D:\keil5\keil_v532\UV4' + EXEC_PATH = r'C:/Keil_v5' +elif CROSS_TOOL == 'iar': + PLATFORM = 'iar' + EXEC_PATH = r'C:/Program Files (x86)/IAR Systems/Embedded Workbench 8.0' + +if os.getenv('RTT_EXEC_PATH'): + EXEC_PATH = os.getenv('RTT_EXEC_PATH') + +BUILD = 'debug' + +if PLATFORM == 'gcc': + # toolchains + PREFIX = 'arm-none-eabi-' + CC = PREFIX + 'gcc' + AS = PREFIX + 'gcc' + AR = PREFIX + 'ar' + CXX = PREFIX + 'g++' + LINK = PREFIX + 'gcc' + TARGET_EXT = 'elf' + SIZE = PREFIX + 'size' + OBJDUMP = PREFIX + 'objdump' + OBJCPY = PREFIX + 'objcopy' + + DEVICE = ' -mcpu=cortex-m0 -mthumb -ffunction-sections -fdata-sections' + CFLAGS = DEVICE + ' -Dgcc' + AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp -Wa,-mimplicit-it=thumb ' + LFLAGS = DEVICE + ' -Wl,--gc-sections,-Map=rt-thread.map,-cref,-u,Reset_Handler -T board/linker_scripts/link.lds' + + CPATH = '' + LPATH = '' + + if BUILD == 'debug': + CFLAGS += ' -O0 -gdwarf-2 -g' + AFLAGS += ' -gdwarf-2' + else: + CFLAGS += ' -O2' + + CXXFLAGS = CFLAGS + + POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n' + +elif PLATFORM == 'armcc': + # toolchains + CC = 'armcc' + CXX = 'armcc' + AS = 'armasm' + AR = 'armar' + LINK = 'armlink' + TARGET_EXT = 'axf' + + DEVICE = ' --cpu Cortex-M0 ' + CFLAGS = '-c ' + DEVICE + ' --apcs=interwork --c99' + AFLAGS = DEVICE + ' --apcs=interwork ' + LFLAGS = DEVICE + ' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rt-thread.map --strict' + CFLAGS += ' -I' + EXEC_PATH + '/ARM/ARMCC/include' + LFLAGS += ' --libpath=' + EXEC_PATH + '/ARM/ARMCC/lib' + + CFLAGS += ' -D__MICROLIB ' + AFLAGS += ' --pd "__MICROLIB SETA 1" ' + LFLAGS += ' --library_type=microlib ' + EXEC_PATH += '/ARM/ARMCC/bin/' + + if BUILD == 'debug': + CFLAGS += ' -g -O0' + AFLAGS += ' -g' + else: + CFLAGS += ' -O2' + + CXXFLAGS = CFLAGS + CFLAGS += ' -std=c99' + + POST_ACTION = 'fromelf --bin $TARGET --output rtthread.bin \nfromelf -z $TARGET' + +elif PLATFORM == 'iar': + # toolchains + CC = 'iccarm' + CXX = 'iccarm' + AS = 'iasmarm' + AR = 'iarchive' + LINK = 'ilinkarm' + TARGET_EXT = 'out' + + DEVICE = '-Dewarm' + + CFLAGS = DEVICE + CFLAGS += ' --diag_suppress Pa050' + CFLAGS += ' --no_cse' + CFLAGS += ' --no_unroll' + CFLAGS += ' --no_inline' + CFLAGS += ' --no_code_motion' + CFLAGS += ' --no_tbaa' + CFLAGS += ' --no_clustering' + CFLAGS += ' --no_scheduling' + CFLAGS += ' --endian=little' + CFLAGS += ' --cpu=Cortex-M0' + CFLAGS += ' -e' + CFLAGS += ' --fpu=None' + CFLAGS += ' --dlib_config "' + EXEC_PATH + '/arm/INC/c/DLib_Config_Normal.h"' + CFLAGS += ' --silent' + + AFLAGS = DEVICE + AFLAGS += ' -s+' + AFLAGS += ' -w+' + AFLAGS += ' -r' + AFLAGS += ' --cpu Cortex-M0' + AFLAGS += ' --fpu None' + AFLAGS += ' -S' + + if BUILD == 'debug': + CFLAGS += ' --debug' + CFLAGS += ' -On' + else: + CFLAGS += ' -Oh' + + LFLAGS = ' --config "board/linker_scripts/link.icf"' + LFLAGS += ' --entry __iar_program_start' + + CXXFLAGS = CFLAGS + + EXEC_PATH = EXEC_PATH + '/arm/bin/' + POST_ACTION = 'ielftool --bin $TARGET rtthread.bin' + +def dist_handle(BSP_ROOT, dist_dir): + import sys + cwd_path = os.getcwd() + sys.path.append(os.path.join(os.path.dirname(BSP_ROOT), 'tools')) + from sdk_dist import dist_do_building + dist_do_building(BSP_ROOT, dist_dir) + diff --git a/bsp/ht32/ht32f52352/template.uvoptx b/bsp/ht32/ht32f52352/template.uvoptx new file mode 100644 index 0000000000..eaed3566ca --- /dev/null +++ b/bsp/ht32/ht32f52352/template.uvoptx @@ -0,0 +1,179 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + rt-thread + 0x4 + ARM-ADS + + 12000000 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\build\keil\List\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 255 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 2 + + + + + + + + + + + BIN\CMSIS_AGDI.dll + + + + 0 + CMSIS_AGDI + -X"Any" -UAny -O206 -S0 -C0 -P00 -N00("ARM CoreSight SW-DP") -D00(0BC11477) -L00(0) -TO18 -TC10000000 -TP20 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO15 -FD20000000 -FC1000 -FN2 -FF0HT32F.FLM -FS00 -FL0100000 -FP0($$Device:HT32F52352$ARM\Flash\HT32F.FLM) -FF1HT32F_OPT.FLM -FS11FF00000 -FL11000 -FP1($$Device:HT32F52352$ARM\Flash\HT32F_OPT.FLM) + + + 0 + UL2CM3 + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN2 -FF0HT32F -FS00 -FL0100000 -FF1HT32F_OPT -FS11FF00000 -FL11000 -FP0($$Device:HT32F52352$ARM\Flash\HT32F.FLM) -FP1($$Device:HT32F52352$ARM\Flash\HT32F_OPT.FLM)) + + + + + 0 + + + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + Source Group 1 + 0 + 0 + 0 + 0 + + + diff --git a/bsp/ht32/ht32f52352/template.uvprojx b/bsp/ht32/ht32f52352/template.uvprojx new file mode 100644 index 0000000000..2530ad2a7e --- /dev/null +++ b/bsp/ht32/ht32f52352/template.uvprojx @@ -0,0 +1,392 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + rt-thread + 0x4 + ARM-ADS + 5060422::V5.06 update 4 (build 422)::ARMCC + + + HT32F52352 + Holtek + Holtek.HT32_DFP.1.0.19 + http://mcu.holtek.com.tw/pack + IRAM(0x20000000,0x4000) IROM(0x00000000,0x1FE00) CPUTYPE("Cortex-M0+") CLOCK(12000000) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN2 -FF0HT32F -FS00 -FL0100000 -FF1HT32F_OPT -FS11FF00000 -FL11000 -FP0($$Device:HT32F52352$ARM\Flash\HT32F.FLM) -FP1($$Device:HT32F52352$ARM\Flash\HT32F_OPT.FLM)) + 0 + $$Device:HT32F52352$ARM\INC\Holtek\HT32F5xxxx\ht32f5xxxx_01.h + + + + + + + + + + $$Device:HT32F52352$SVD\HT32F52342_52.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\build\keil\Obj\ + rt-thread + 1 + 0 + 0 + 1 + 1 + .\build\keil\List\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + + DARMCM1.DLL + -pCM0+ + SARMCM3.DLL + + TARMCM1.DLL + -pCM0+ + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 0 + -1 + + 1 + BIN\UL2CM3.DLL + + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M0+" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 8 + 0 + 0 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x4000 + + + 1 + 0x0 + 0x1fe00 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x1fe00 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x4000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 0 + + + + + + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + USE_HT32_CHIP=4 + + + + + + 0 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + .\board\linker_scripts\link.sct + + + + + + + + + + + Source Group 1 + + + + + + + + + + + + diff --git a/bsp/ht32/libraries/.ignore_format.yml b/bsp/ht32/libraries/.ignore_format.yml new file mode 100644 index 0000000000..65b2f1a156 --- /dev/null +++ b/bsp/ht32/libraries/.ignore_format.yml @@ -0,0 +1,7 @@ +# files format check exclude path, please follow the instructions below to modify; +# If you need to exclude an entire folder, add the folder path in dir_path; +# If you need to exclude a file, add the path to the file in file_path. + +dir_path: +- HT32_STD_1xxxx_FWLib +- HT32_STD_5xxxx_FWLib diff --git a/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/Release_Notes.txt b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/Release_Notes.txt new file mode 100644 index 0000000000..20ad57f3fc --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/Release_Notes.txt @@ -0,0 +1,876 @@ +/*********************************************************************************************************//** + * @file Release_Notes.txt + * @version V1.4.1 + * @date 2023-10-31 + * @brief The Release notes of HT32 Firmware Library. + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ + +// Supported Device +// ======================================== +// HT32F1653, HT32F1654 +// HT32F1655, HT32F1656 +// HT32F12345 +// HT32F12364 +// HT32F12365, HT32F12366 +// HT32F22366 + +/*----------------------------------------------------------------------------------------------------------*/ +/* HT32_STD_1xxxx_FWLib_V1.4.1_2982 */ +/*----------------------------------------------------------------------------------------------------------*/ + Release Date: 2023-10-31 + + Main Changes + + Add new example. + - "GPIO/PinLock" + + Modify examples below, add volatile qualifiers on some variables (in the for loop usage) + to fix the Arm Compiler Version 6 optimization issue. + ("u32" to "vu32", unsigned int to volatile unsigned int). + - “PWRCU/PowerDown_WAKEUPPin” + - “PWRCU/PowerDown_RTC” + - “TM/PWM” + + Modify examples below, use separate "if" statements instead of "if-else" to avoid double-entry ISR. + - "PWRCU/DeepSleepMode1" + - "PWRCU/DeepSleepMode2" + + Modify "ht32_time.h", "ht32f1xxxx_conf.h" and "ht32_time_conf.h" for "LIBCFG_CKCU_NO_APB_PRESCALER" series. + - To ensure the correct configuration of the timer clock, the "HTCFG_TIME_PCLK_DIV" is redefined as 0. + + Add "Project or Target File Clearing" functions ("_ClearProject.bat" and "_ClearTarget.bat"). + + Modify "syscall.c" to prevent redundant initialization of the heap index. + + Modify "ht32f1xxxx_01.h" to add below definition. + - "sc64", "vs64", "vsc64", "uc64", "vu64", "vuc64" + + Modify PWRCU related define (The left side old one is still kept for backward compatible). + - PWRCU_FLAG_BAKPOR -> PWRCU_FLAG_PWRPOR + + Modify "RETARGET_Configuration()", add the operation of UxARTn peripheral clock enable. + + Update and sync "ht32f1xxxx_conf.h", modify related define of UxARTn retarget port. + + Update "ht32_op.c" and "ht32_op.s" to support new version of bootloader waiting time setting address. + (The setting address is changed from 0x1FF0002C to 0x1FF0004C) + + Add "ht32_op_V107.c" and "ht32_op_V107.s" to support the use of older versions of bootloader. + + Add "CKCU_ATCInit()" API for HSI Auto Trim initial function. + + Update "ht32f1xxxx_adc.c" and "ht32f1xxxx_adc_02.c", modify the ADC enable related flow. + + Add the below folder, For the BMduino shield/module Keil Driver. + - "BestModules" + + Others + + Update comment, format, typing error, and coding style. + + Adjust "LIBCFG_xxxxx" definition below. + - "LIBCFG_CKCU_APBCLKFIX" rename to "LIBCFG_CKCU_NO_APB_PRESCALER" + + Modify the Sourcery G++ Lite toolchain project. + - Set C99 mode to fix issues after updating CMSIS v5.9.0 ("for" loop initial declarations). + + Update e-Link32 Pro/Lite Command line tool as "V1.19" ("utilities/elink32pro/eLink32pro.exe"). + + Modify "_ProjectConfigScript.bat" to prevent the creation of project that copy unused system/startup files. + + Update "project_template/Script" for adding project C++ source files and setting the chip model mechanism. + - The updated files are as follows: + "Script/_ProjectSource.bat" + "Script/_ProjectSource.ini" + + Update "project_template/Script" for improving script mechanism. + - The updated files are as follows: + "Script/_CreateProjectConfScript.bat" + "Script/_CreateProjectScript.bat" + "Script/_ht32_ic_name.ini" + + Modify and check the example supportability of each IC. + + Add the below file, for the BMduino shield. + - "ht32_undef_IP.h" + +/*----------------------------------------------------------------------------------------------------------*/ +/* HT32_STD_1xxxx_FWLib_V1.3.2_2858 */ +/*----------------------------------------------------------------------------------------------------------*/ + Release Date: 2023-02-02 + + Main Changes + + Add new examples: + - "SRAM_Overwrite/Watchpoint_Heap" + - "SRAM_Overwrite/Watchpoint_Stack" + + Update "ht32f1xxxx_conf.h" for user layer HSE_VALUE setting. + + Others + + Update comment, format, typing error, and coding style. + + Modify "system_ht32fxxxxx_nn.c", add HSE_VALUE notice and update PLL Out formula. + + Update and sync system.c files. + + Update EEPROM Emulation middleware, improve efficacy and reduce resource usage. + "utilities/middleware/eeprom_emulation.c" + "utilities/middleware/ht32_eeprom_config_templet.h" + + Update I2C Master middleware, improve setting way and fix minor errors. + "utilities/middleware/i2c_master.c/.h" + "utilities/middleware/i2c_master_config_templet.h" + +/*----------------------------------------------------------------------------------------------------------*/ +/* HT32_STD_1xxxx_FWLib_V1.3.1_2808 */ +/*----------------------------------------------------------------------------------------------------------*/ + Release Date: 2022-12-01 + + Main Changes + + Update "ht32_time.h", fix a formula error of "TIME_TICK2US()" and "TIME_TICK2MS()" macro. + + Modify "ht32_retarget.c", fix retarget can't work when the MicroLIB is not used in Keil's V6 compiler. + + Modify "ht32_serial.c/.h" and "ht32_retarget.c", fix ITM setting issue. + + Update "ht32fxxxx_sk.h", add TRACESWO pin assignment for ITM. + + Update "SPI/PDMA" example, change the order of API execution (SPI_SELOutputCmd() execution before SPI_Cmd()). + + Update "CSIF/Init" example, modify the datatype form and add comments to explain the length of the Rx buffer. + + Update following I2C example. (sync. with M0+) + - I2C/7_bit_mode + - I2C/10_bit_mode + - I2C/EEPROM_Simulate + - I2C/Interrupt + - I2C/PDMA + + GPIO + - Add new define "GPIO_PIN_NUM_n" for GPIO pin number (n = 0 ~ 15). + + EXTI + - Add "gEXTIn_IRQn[]" and "EXTI_GetIRQn()" macro to map GPIO pin number (0 ~ 15) to "EXTIn_IRQn". + - Add "GPIO2EXTI()" macro to map GPIO pin to EXTI Channel. + - Change "AFIO_EXTISourceConfig()" API, remove "AFIO_EXTI_CH_Enum" and "AFIO_ESS_Enum". + Old: void AFIO_EXTISourceConfig(AFIO_EXTI_CH_Enum AFIO_EXTI_CH_n, AFIO_ESS_Enum AFIO_ESS_Px) + New: void AFIO_EXTISourceConfig(u32 GPIO_PIN_NUM_n, u32 GPIO_Px) + + Others + + Update comment, format, typing error, and coding style. + + Update "ht32_op.s/.c", allow "Bootloader Waiting Time" function for all series. + + Update "CKCU/HSI_AutoTrim_By_USB" example, add the following define to "ht32_board_config.h". + - "CKCU_PLL_CFG" + - "CKCU_SYSCLK_DIV_CFG" + + Upgrade CMSIS to v5.9.0. + + Modify API parameter check macro of Library Debug Mode, fix parameter check error. + + Modify variable declaration of "PDMACH_InitTypeDef" to reduce memory size. + +/*----------------------------------------------------------------------------------------------------------*/ +/* HT32_STD_1xxxx_FWLib_V1.2.1_2753 */ +/*----------------------------------------------------------------------------------------------------------*/ + Release Date: 2022-10-11 + + Main Changes + + Add new examples: + - "I2C/7_bit_mode_master" + - "I2C/7_bit_mode_slave" + + Add the following API for PDMA. + - "PDMA_DeInit()" + - "PDMA_AddrConfig()" + - "PDMA_SrcAddrConfig()" + - "PDMA_DstAddrConfig()" + - "PDMA_GetRemainBlkCnt()" + + Add the following API for ADC. + - "ADC_ChannelDataAlign()" + - "ADC_ChannelOffsetValue()" + - "ADC_ChannelOffsetCmd()" + + Update "ht32_retarget.c", modify the retarget related functions for SEGGER Embedded Studio. + + Update "FLASH_SetWaitState()" function, disable Pre-fetch and Branch Cache function before change + wait state. + + Update following middleware. + "utilities/middleware/i2c_master.c/h" + "utilities/middleware/uart_module.c" + + Others + + Update comment, format, typing error, and coding style. + + Update "BFTM/OneShot" example, fix the register access sequence and time calculation formula. + + Update "TM/PWM/main.c" + - Add "HTCFG_PWM_TM_RELOAD" check. + - Add PWM channel initial function. + - Remove "_ht32_project_source.h" (Use "_ProjectSource.ini" to add "pwm.c" into project compiling list). + + Fix the upper/lower case error of #include file name. + + Update e-Link32 Pro/Lite Command line tool as "V1.18" ("utilities/elink32pro/eLink32pro.exe"). + + Change the project recommended minimum version of SEGGER Embedded Studio from V4.12 to V6.20. + +/*----------------------------------------------------------------------------------------------------------*/ +/* HT32_STD_1xxxx_FWLib_V1.1.1_2647 */ +/*----------------------------------------------------------------------------------------------------------*/ + Release Date: 2022-06-10 + + Main Changes + + Add following middleware. + "utilities/middleware/spi_module.c" + "utilities/middleware/spi_module.h" + "utilities/middleware/spi_module_config_templet.h" + + Fixed FW library compatibility with ARM compiler version 6 of MDK-ARM V5.37. + - Add MDK-ARMv537 project template for MDK-ARM V5.37. + - Update "project_template/Script". Those MDK-ARMv537 project templates will be added for use if choose + the target IDE is "Keil MDK-ARMv5". The fixed files are as follows: + "Script/_CreateProjectScript.bat" + "Script/_ProjectConfig.bat" + "Script/_ProjectSource.bat" + - Update "core_cm3.h", fix compiler error. + - Update "FMC/FLASH_OperationNoHalt", fix the compiler issue of Arm Compiler Version V6.18 and the + compiler warning of linker script file. The fixed files are as follows: + "FLASH_OperationNoHalt/main.c" + "FLASH_OperationNoHalt/linker.lin" + - Update following middleware, remove STRCAT3 usage to fix compiler error. + "utilities/middleware/uart_module.c" + "utilities/middleware/i2c_master.c" + "utilities/middleware/spi_module.c" + + Update "ht32_retarget.c". Implement __write function to fix compiler error in IAR EWARM Version 9.20 + or later. + + Update GNU Arm makefile in the project_template, fix the compatibility issue that the makefile of GNU Arm + Version 11 cannot be compiled. + + Update EWARM in the project_template, fix the compiler error that header file path doesn't exist in + the file list of Workspace of IAR EWARM Version 7. + + Fix SPI initial PDMA parameter in the "utilities/common/spi_flash.c". + + Sync M0+ I2C/EEPROM to fix compiler warning of the GNU compiler. + + Sync M0+ library\HT32F1xxxx_Driver\inc\ht32_dependency.h. + + Others + + Update comment, format, typing error, and coding style. + + Update e-Link32 Pro/Lite Command line tool as "V1.16" ("utilities/elink32pro/eLink32pro.exe"). + + Update the following examples to remove compiler warning of the IAR EWARM. + "BFTM\TimeMeasure" + "TM\PWMInput\ht32f1xxxx_01_it.c" + "USBD\HID_Keyboard_Virtual_COM\ht32_usbd_class.c" + "USBD\Mass_Storage_SDIO\sd_disk.c" + "USBD\USB_UAC_Sound\ht32_usbd_class.c" + "USBD\Virtual_COM\ht32_usbd_class.c" + + Update and sync create project related files ("_ProjectConfig.bat"、"_ProjectConfig.ini"). + + Update content of "project_template/IP/Example/readme.txt", add MDK-ARM V5.37 related information. + +/*----------------------------------------------------------------------------------------------------------*/ +/* HT32_STD_1xxxx_FWLib_V1.0.10_2585 */ +/*----------------------------------------------------------------------------------------------------------*/ + Release Date: 2022-04-14 + + Main Changes + + Update EEPROM Basic and EEPROM Emulation middleware, fix the include and define sequence. + "utilities/middleware/eeprom_basic.h" + "utilities/middleware/eeprom_emulation.h" + + Update UART Module middleware, add the "UARTM_IsTxFinished()" API. + "utilities/middleware/uart_module.c" + "utilities/middleware/uart_module.h" + + Others + + Update e-Link32 Pro/Lite Command line tool as "V1.0.15" ("utilities/elink32pro/eLink32pro.exe"). + +/*----------------------------------------------------------------------------------------------------------*/ +/* HT32_STD_1xxxx_FWLib_V1.0.10_2585 */ +/*----------------------------------------------------------------------------------------------------------*/ + Release Date: 2022-04-14 + + Main Changes + + Update EEPROM Basic and EEPROM Emulation middleware, fix the include and define sequence. + "utilities/middleware/eeprom_basic.h" + "utilities/middleware/eeprom_emulation.h" + + Update UART Module middleware, add the "UARTM_IsTxFinished()" API. + "utilities/middleware/uart_module.c" + "utilities/middleware/uart_module.h" + + Others + + Update e-Link32 Pro/Lite Command line tool as "V1.0.15" ("utilities/elink32pro/eLink32pro.exe"). + +/*----------------------------------------------------------------------------------------------------------*/ +/* HT32_STD_1xxxx_FWLib_V1.0.9_2556 */ +/*----------------------------------------------------------------------------------------------------------*/ + Release Date: 2022-03-15 + + Main Changes + + Change to the new Holtek version format (Vm.n.r). + + Add new "FMC/FLASH_OperationNoHalt" example. + + Modify "utilities/common/ring_buffer.c", fix the thread-safe issue of "Buffer_GetLength()". + + Update "GNU_ARM/linker.ld", fix the heap/stack area overlap problem. + + Add "ADC_SamplingTimeConfig()" function for the "ht32f1xxxx_adc_02.c". + + Others + + Update comment, format, typing error, and coding style. + + Modify "bool, TRUE, FALSE" define way for C++/.cpp applications. + + Update "startup_ht32fxxxxx_nn.s", support "USE_HT32_CHIP" define exist at startup.s and project Asm + setting in the same time (project's Asm Define has the higher priority). + + Remove unuse global variable "DelayTime" of "ebi_lcd.c" and "spi_lcd.c". + + Update "spi_lcd.c/.h", fix the GPIO Chip SEL define mistake. + + Add following middleware. + "utilities/middleware/uart_module.c" + "utilities/middleware/uart_module.h" + + Update related middleware (eeprom_basic and eeprom_emulation). + + Update e-Link32 Pro/Lite Command line tool as "V1.0.14" ("utilities/elink32pro/eLink32pro.exe"). + +/*----------------------------------------------------------------------------------------------------------*/ +/* HT32_STD_1xxxx_FWLib_v008_2470 */ +/*----------------------------------------------------------------------------------------------------------*/ + Release Date: 2021-08-19 + + Main Changes + + Add "ht32_time.c/.h" to support following new functions for delay, time measure, and timeout. + "Time_Init()" + "Time_Delay()" + "Time_GetTick()" + + Add new examples: + - "ADC/OneShot_SWTrigger_ByTM" + - "GPIO/Input" + - "GPIO/Output" + - "Time/TimeFun" + - "Time/TimeFun_UserConf" + - "USART/RS485_NMM_Slave" + + Add new definition, "FLASH_WAITSTATE_MAX". + + Add "USART_PARITY_MARK" and "USART_PARITY_SPACE" for the UART parity mode. + + Update "ADC_RegularTrigConfig()" and "AC_TRIG_XXXX" define to support all the trigger source of ADC. + + Add "CKCU_ADCPRE_DIV1" parameter of "CKCU_SetADCnPrescaler()" for the HT32F12364. + + Modified "SDIO_ClearFlag()", disable Status Enable Register (SER) to clear SDIO_FLAG_BUF_OVERFLOW and + SDIO_FLAG_BUF_UNDERFLOW. + + Fix the result mistake of the marco below of HT32F12364 (LIBCFG_FLASH_2PAGE_PER_WPBIT is missing). + "#define FLASH_WP_PAGE_SET(OP, PAGE)" + "#define FLASH_WP_PAGE_CLEAR(OP, PAGE)" + "#define FLASH_IS_WP_PAGE(OP, PAGE)" + + Update following example, modify the default value of "gIsINEmpty" from TRUE to FALSE. The default value + TRUE may cause the F/W to not send CSW after the first Inquiry CBW Command in a specific condition. + "example/USBD/HID_Keyboard_Mass_Storage" + "example/USBD/Mass_Storage" + "example/USBD/Mass_Storage_IAP" + "example/USBD/Mass_Storage_SDIO" + + Others + + Update comment, format, typing error, and coding style. + + Fix compile error when turn on Library debug mode (HT32_LIB_DEBUG = 1). + + Update e-Link32 Pro Commander to V1.10. + +/*----------------------------------------------------------------------------------------------------------*/ +/* HT32_STD_1xxxx_FWLib_v007_2414 */ +/*----------------------------------------------------------------------------------------------------------*/ + Release Date: 2021-05-11 + + Main Changes + + Add new examples: + - "EXTI/GPIO_Interrupt" + - "CKCU/HSI_AutoTrim_By_LSE" + + Update the IAP example of HT32F12364 project: + - IAR EWARM v6/v7/v8: + 1. Modify "startup_ht32f1xxxx_03.s" to "startup_ht32f1xxxx_iar_03.s". + 2. Modify "ht32f1xxxx_adc.c" to "ht32f1xxxx_adc_02.c". + - Keil MDK-ARM v4/v5: Modify "ht32f1xxxx_adc.c" to "ht32f1xxxx_adc_02.c". + + Fix the system stuck in CKCU_HSIAutoTrimCmd() because of the misjudgment of CKCU_HSIAutoTrimIsReady(). + + Fix the CHIP ID error. Fixed "USE_HT32_CHIP=3" to "USE_HT32_CHIP=16". The fixed files are as follows: + - IAP/IAP_Text_RAM/EWARM/Project_12364_IAP.ewp + - IAP/IAP_UI/EWARM/Project_12364_IAP.ewp + + Fix the syntax error on the "IAP/IAP_Text_RAM/EWARM/startup_ht32f1xxxx_iar_03_iap.s". + + Others + + Update comment, format, typing error, and coding style. + + Update the version of eLink32pro.exe to 1.0.1.1. + + Update the following project setting: + - IAR EWARM v6/v7: Modify "_ht32_project_source.c" to "_ht32_project_source.h". + - SEGGER Embedded Studio: Add the new definition "arm_compiler_variant="SEGGER"". + +/*----------------------------------------------------------------------------------------------------------*/ +/* HT32_STD_1xxxx_FWLib_v006_2361 */ +/*----------------------------------------------------------------------------------------------------------*/ + Release Date: 2021-02-26 + + Main Changes + + Add "Create Project Configuration Menu" to choose the target IDE and Device when the first time to do the + create project operation of the example. The configuration file, "_CreateProjectConfig.bat" is saved to + the root path of the HT32 Firmware Library. You can reset the create project IDE/IC configuration anytime + by deleting the configuration file. + Target IDE/Compiler: + - Keil MDK-ARM v5 + - Keil MDK-ARM v4 + - IAR EWARM v8 + - IAR EWARM v6/v7 + - SEGGER Embedded Studio + - GNU [with Keil and GNU make] + - SourceryG++Lite [with Keil] + Target Device: + - xxxxx: Single Device + - xxx*: Series + + Add new examples: + - "NVIC/Disable_Interrupt" + - "TM/InternalTrigger" + - "TM/PWM_Buzzer" + - "WDT/Auto_Enable" + + Add Flash programming function of GNU Maker (via e-Link32 Pro/Lite Commander). + "make IC=xxxxx eraseall" + "make IC=xxxxx program" + "make IC=xxxxx run" + + Update "CKCU_HSIAutoTrimCmd()" and "CKCU_HSIAutoTrimIsReady()" function to improve clock stability. + + Fix the cache address problem of "SDDISK_Read()" function. + "USBD/Mass_Storage/sd_disk.c", "USBD/Mass_Storage_SDIO/sd_disk.c" + + Update GNU project (*.uvprojx), fix the compile error when use new GNU Arm version + ("gcc-arm-none-eabi-10-2020-q2-preview-win32" or above). + + Fix Keil compiling error when disable both retarget and MicroLib. + + Update "ht32f1xxxx_01.h", fix the compatibility issue when user include "stdbool.h". + + Modify GNU compiler settings, output text file (disassembly) after building the code. + + Add "HT32_FWLIB_VER" and "HT32_FWLIB_SVN" in "ht32f1xxxx_lib.h" for the version information of + HT32 Firmware Library. + Example: + "#define HT32_FWLIB_VER (006)" + "#define HT32_FWLIB_VER (2361)" + + Add new AFIO define in "ht32f1xxxx_gpio.h". + - "AFIO_FUN_MCTM1" + - "AFIO_FUN_PWM" + - "AFIO_FUN_PWM0", "AFIO_FUN_PWM1", "AFIO_FUN_PWM2", "AFIO_FUN_PWM3" + + Add following alias of MCTM IRQ handler + "#define MCTM0_IRQn MCTM0UP_IRQn" + "#define MCTM0_IRQHandler MCTM0UP_IRQHandler" + "#define MCTM1_IRQn MCTM1UP_IRQn" + "#define MCTM1_IRQHandler MCTM1UP_IRQHandler" + + Others + + Update comment, format, typing error, and coding style. + + Update "SPI/FIFO_SEL_Hardware" example, add Rx FIFO Timeout function and fix data loss issue. + + Update "USBD/Mass_Storage" example, add "HTCFG_SD_MAXSPEED" define for different board. + + Update "utilities/common/spi_lcd.c". + - Remove duplicate SPI parameter setting of "LCD_Init()". + - Update SPI chip select define and SPI configuration by "LCD_SPI_SEL_AFIO_MODE". + - Swap the "GPIO_DirectionConfig()" and "GPIO_SetOutBits()" function to prevent transient state + of SPI_SEL pin. + + Update "_ProjectConfig*.bat" files. + + Add "Project Source File Setting" functions ("_ProjectSource.ini" and "_ProjectSource.bat"). + + Rename "_CreateProjectUSB.bat" as "_CreateProject.bat". + + Add dummy xxTM C files, to notify the user that SCTM/PWM/GPTM/MCTM timer use the "ht32f1xxxx_tm.c" driver. + "ht32f1xxxx_gptm.c", "ht32f1xxxx_pwm.c", "ht32f1xxxx_sctm.c" + + Add "IS_IPN_MCTM()" and "IS_IPN_GPTM" macro, for use to confirm the xxTMn is GPTM or MCTM. + + Update comment and board/pin configuration of "ADC/OneShot_TMTrigger_PDMA" example. + + Update and sync startup.s/system.c files. + +/*----------------------------------------------------------------------------------------------------------*/ +/* HT32F1xxxx_FWLib_v005_2207 */ +/*----------------------------------------------------------------------------------------------------------*/ + Release Date: 2020-08-11 + + Main Changes + + Add the following files to use e-Link32 Pro with SEGGER Embedded Studio. Refer to the + "readme e-Link32 Pro.txt" for how to use it. + "emStudiov4/readme e-Link32 Pro.txt" + "emStudiov4/Project_xxxxx.bat" + "emStudiov4/_MassErase.bat" + + Fix the "I2S_FIFOTrigLevelConfig()" error which did not clear the field of I2S FCR correctly. + + Fix "RPRE_MASK" define error for "RTC_SetPrescaler()" function. + + Add "SPI_FLASH_WaitForWriteEnd()" function in the end of the write status operation + ("SPI_FLASH_WriteStatus()"). + + Modify "SPI_FLASH_WaitForWriteEnd()" function to return value of status register. + + Add below notice of examples to inform the user to check the local structure variable without a + default value. + "Notice that the local variable (structure) did not have an initial value. + Please confirm that there are no missing members in the parameter settings below this function." + + Add "LIBCFG_MAX_SPEED" in the file "ht32fxxxxx_libcfg.h" which indicate the maximum core speed. + + Add the following definition for convenience. + PDMACH0_IRQn ~ PDMACH5_IRQn + AFIO_FUN_MCTM0 + AFIO_FUN_GPTM0 ~ AFIO_FUN_GPTM3 + AFIO_FUN_PWM0 + AFIO_FUN_SCTM0 ~ AFIO_FUN_SCTM2 + + Add new examples. + "TM/PWM" + "TM/UpdateEvent" + + Add "s64/u64" definition. + + Others + + Update comment, format, typing error, and coding style. + + Add below notice in the "FMC/FLASH_Security" example. + "The Option Byte will be write protected (cannot be changed again) after the + Security Protection is enabled. Refer to the user manual for details." + + Remove HSI disable setting of Configuration Wizard and add notice in the "system_xxxxx_nn.c". + + Update the following examples to remove compiler warning of the GNU compiler. + "USBD/Mass_Storage" + "USART/PDMA" + "USART/Interrupt" + + Add "-Waddress-of-packed-member" #pragma of below examples to remove compiler warning of the + GNU compiler. + "USBD/Mass_Storage" + "USBD/Mass_Storage_IAP" + "USBD/Mass_Storage_SDIO" + "USBD/HID_Keyboard" + "USBD/HID_Keyboard_Joystick" + "USBD/HID_Keyboard_Mass_Storage" + "USBD/HID_Keyboard_Virtual_COM" + "USBD/HID_Mouse" + +/*----------------------------------------------------------------------------------------------------------*/ +/* HT32F1xxxx_FWLib_v004_2103 */ +/*----------------------------------------------------------------------------------------------------------*/ + Release Date: 2020-04-25 + + Main Changes + + Remove the "I2C_Cmd()" in the "I2C_Init()" function since it shall be called after the I2C related + settings. User shall call the "I2C_Cmd()" by themself after the "I2C_Init()". + + Update "system_ht32f1xxxx_02.c", modify the LDO related setting. + + Add "USART_GetIntStatus()" function to get the enabled interrupt source. + + Add "RETARGET_HSI_ATM" setting to turn on/off the auto-trim function of HSI ("ht32f1xxxx_conf.h"). + + Add "USBDClass_Reset()" into the "USBD/*" example to reset related flag for the self-power application. + + Modify "ht32f5xxxx_aes.c", fix "AES_SetKeyTable()" and "_AES_CryptData()" functions who did not clear + related fields before set it. + + Rename examples as below. + IP Old Name New Name + -------- -------- -------- + ADC EXTITrigger_DiscontinuousMode Discontinuous_EXTITrigger + ADC PDMA_ADCResult OneShot_TMTrigger_PDMA + ADC Potentiometer_ContinuousMode Continuous_Potentiometer + ADC TM_Trigger OneShot_PWMTrigger + ADC TM_Trigger_with_Delay OneShot_PWMTrigger_with_Delay + USART HyperTerminal_TxRx Retarget + USART HyperTerminal_TxRx_Interrupt Interrupt + USART HyperTerminal_TxRx_Interrupt_FIFO Interrupt_FIFO + + Update the following example to improve readability. + "ADC/AnalogWatchdog" + "ADC/Continuous_Potentiometer" + "ADC/Discontinuous_EXTITrigger" + "ADC/InternalReferenceVoltage" + "ADC/OneShot_PWMTrigger" + "ADC/OneShot_PWMTrigger_with_Delay" + "ADC/OneShot_TMTrigger_PDMA" + "ADC/Two_Group_MaxCH" + "USART/Interrupt" + "USART/Interrupt_FIFO" + "USART/PDMA" + "USART/Polling" + "USART/Retarget" + "USBD/HID_Demo" + "USBD/HID_DemoVendorReport" + + Update UxART related example, turn on internal pull up to prevent unknown state. + + Add new examples. + "BFTM/OneShot" + "BFTM/TimeMeasure" + + Remove unnecessary RTC compare match restart setting of the RTC example + (which cause the time not correct after entering the low power mode). + + ADC to ADC0 related modification (to compatible with M0+ and ADC1). + Modify "HT_ADC" and "ADC_IRQn" to "HT_ADC0" and "ADC0_IRQn". + Modify "AFIO_FUN_ADC" as "AFIO_FUN_ADC0". + Modify "CKCU_SetADCPrescaler()" to "CKCU_SetADCnPrescaler()". + Add "CKCU_ADCPRE_ADCn_TypeDef". + Modify "ADC_Freq" to "ADC0_Freq" of "CKCU_ClocksTypeDef". + Modify "ADC" to "ADC0" of "RSTCU_PeripReset_TypeDef". + Add "HT_ADC", "ADC_IRQn", "AFIO_FUN_ADC" define for backward compatibility. + + Fix "HT_GPIOF" define error of HT32F12364. + + Others + + Update "SPI/FIFO_SEL_Hardware" example, change the code location of the IP enable ("SPI_Cmd()"). + + Update "system_ht32fxxxxx_nn.c" (coding style). + + Update "ht32_series.c/h" and "ht32_retarget_usbdconf.h" to improve the compatibly of the + terminal software. + + Update comment, format, typing error, and coding style. + + Fix interrupt mode of UxART retarget, remove unnecessary FIFO/interrupt configuration of the + retarget function. + + Update format of "CKCU_PeripClockConfig_TypeDef" and "RSTCU_PeripReset_TypeDef". + + Update and modify naming rule of the "HTCFG_xxxx" configuration define in the "ht32_board_config.h". + + Update settings of project files. + +/*----------------------------------------------------------------------------------------------------------*/ +/* HT32F1xxxx_FWLib_v004_1946 */ +/*----------------------------------------------------------------------------------------------------------*/ + Release Date: 2019-11-28 + + Main Changes + + Move the "common/*.h" include from the begin to the end (after the pin define) in the file + "HT32_Board/ht32fxxxx_sk/dvb.h". The original include way leads to the pin define lost when you + use the EBI_LCD->EBI_LCD_RAM outside the "ebi_lcd.c". + + Fix error of "_CreateProjectScript.bat" which cause the stack size and RW base can not be set by the + "_ProjectConfig.bat" of the emStudiov4 project. + + Add "GPIO_GetID()" function to convert HT_GPIOx to GPIO_Px. + + Update "HID_Demo_UI.exe" to support HID Report ID. + + Add "USBD/HID_DemoVendorReport" example. + + Modify "SPI_Init()" function, fix SPIx Clock Prescaler setting of HT32F12364. + + Modify "system_ht32f1xxxx_03.c", fix PLLCFGR initiation error which cause the "PLL_CLK_SRC_DIV" setting + is not work. + + Add "RETARGET_UxART_BAUDRATE" setting to change the retarget UART baudrate in "ht32f1xxxx_conf.h". + + Add "RETARGET_HSI_ATM" setting to turn on/off the auto-trim function of HSI. + + Add "RETARGET_DEFINE_HANDLER" setting to remove the UxARTn_IRQHandler() define of the retarget. + This setting is used for the model who grouping two UART Interrupt into one vector. + + Add non-block mode of USB Virtual-COM retarget function ((Drop data if USB or terminal software is + not ready). + + Modify "PWRCU_SetLDOFTRM()" function, fix the error which cause the LDO output voltage fine trim is + not work. + + Update "PWRCU_DeepSleep2()" to restore the LDO output voltage fine trim after system wakeup. + + Add SWCLK toggle of "GPIO_DisableDebugPort()" function. + + Others + + Add "utilities/common/lcd.h" to put the lcd related register together. + + Update format and coding style. + + Add PLL Output frequency comment of "system_ht32f1xxxx_nn.c". + + Update project files. + .c and .h files order. + Project format. + Include path order. + + Add "USAGE_PAGE_L" define of "USB/HID_Demo" example. + + Fix typing error of "ht32f1xxxx_conf.h". + +/*----------------------------------------------------------------------------------------------------------*/ +/* HT32F1xxxx_FWLib_v004_1812 */ +/*----------------------------------------------------------------------------------------------------------*/ + Release Date: 2019-09-11 + + Main Changes + + Add new device support. + HT32F12364 + + Update "ebi_lcd.c/h", fix LCD_SPI_BL_GPIO_XXX define error (shall be LCD_EBI_BL_GPIO_XXX). + + Update USB example, use USB PLL by default (if USB PLL exist). + + Fix function name typing error + SPI_GUADTCmd() -> SPI_GUARDTCmd() + SPI_GUADTConfig -> SPI_GUARDTConfig() + + Update "ADC_RegularGroupConfig()" and "ADC_HPGroupConfig()", prevent to enable the ADC directly after + the above function call. User shall use the "ADC_Cmd(HT_ADC, ENABLE);" to enable the ADC. + + Rename following files. + "IAR/startup_ht32f1xxxx_01.s" to "IARstartup_ht32f1xxxx_iar_01.s" + "IAR/startup_ht32f1xxxx_03.s" to "IARstartup_ht32f1xxxx_iar_03.s" + + Others + + Update comment and coding style. + + Update "USART/HyperTerminal_TxRx_Interrupt" example, remove unnecessary configuration of LED. + + Update readme file of "EBI/LCD" example. + + Add "PWRCU/PowerDown_RTC" example. + + Add "PWRCU/PWRCU_PowerDown_WAKEUPPin" example. + + Add "RTC/Time" example. + + Update and sync "ht32f1xxxx_conf.h". + + Update and sync "HT32F1xxxx_01_DebugSupport.ini". + + Update "ht32f1xxxx_tm.c", remove unnecessary variable initialization. + + Update "ht32_op.c" and "ht32_op.s", edit comment of WDT Enable function. + +/*----------------------------------------------------------------------------------------------------------*/ +/* HT32F1xxxx_FWLib_v003_1679 */ +/*----------------------------------------------------------------------------------------------------------*/ + Release Date: 2019-04-19 + + Main Changes + + Fix error of "CKCU_HSIAutoTrimClkConfig()" function which cause the HSI auto-trim not work. + + Modify following define of ADC. + ADC_CH_GNDREF -> ADC_CH_GND_VREF + ADC_CH_VREF -> ADC_CH_VDD_VREF + + Others + + None. + +/*----------------------------------------------------------------------------------------------------------*/ +/* HT32F1xxxx_FWLib_v003_1673 */ +/*----------------------------------------------------------------------------------------------------------*/ + Release Date: 2019-04-09 + + Main Changes + + Add SEGGER Embedded Studio IDE support (beta version). + + Update "ht32f1xxxx_usbd.c" and "ht32_usbd_core.c", add Force USB Reset Control function (apply to specific + model only). + + Update Create Project script, add Script folder in project_template. + + Add "TM/TriggerCounter" example. + + Add "USBD/HID_Keyboard_Mass_Storage" example. + + Others + + Update comment of example code. + + Update define of "USBD/Mass_Storage" example. + + Update "EXTI/WakeUp_DeepSleepMode1" Example, add LED3 (for some SK have only LED2 and LED3 on board). + + Update/sync startup.s/system.c files. + + Update/sync "HT32F1xxxx_01_DebugSupport.ini". + + Update/sync "ht32_op.s" and "ht32_op.c". + + Update "BootProcess" function. + + Update/sync "FlashMacro.mac". + +/*----------------------------------------------------------------------------------------------------------*/ +/* HT32F1xxxx_FWLib_v002_1496 */ +/*----------------------------------------------------------------------------------------------------------*/ + Release Date: 2018-12-17 + + Main Changes + + Modify Control IN/OUT method of USB Core, to fix USB transfer problem when CPU in the lower speed or late + USB interrupt case. + + Add workaround for PDMA CH3 issue (Interrupt Enable bit of CH3 is not work). + + Others + + Add "USBD_DisableDefaultPull()" function to disable pull resistance when the USB is not use. + + Rename RTC example as below. + "Calendar" -> "Time_BackupDomain" + + Add new example. + "RTC/Calendar_BackupDomain" + "FMC/EnableProtectionByFW" + + Update "EXTI/WakeUp_DeepSleepMode1" example. + + Update coding style. + +/*----------------------------------------------------------------------------------------------------------*/ +/* HT32F1xxxx_FWLib_v002_1406 */ +/*----------------------------------------------------------------------------------------------------------*/ + Release Date: 2018-09-30 + + Main Changes + + Update HardFault_Handler of "ht32f1xxxx_01_it.c",add the debug instruction and system reset. + + Add "RAND/Random_Number" example and update "ht32_rand.c". + + Add "__HT_check_sp" and "__HT_check_heap" symbol into startup.s and watchpoint command into + "HT32F1xxxx_01_DebugSupport.ini" for debug stack/heap underflow, overflow, and overwrite. + + Update "USBD/HID_Keyboard_Joystick" and "USBD/HID_Mouse" example, change the set flag sequence + (before USBDCore_EPTWriteINData). + + Add GNU Make support of GNU Arm compiler. + + Others + + Add "objcooy.txt" which shows how to use obj tools of GNU Arm compiler. + + Update format and coding style. + +/*----------------------------------------------------------------------------------------------------------*/ +/* HT32F1xxxx_FWLib_v002_1367 */ +/*----------------------------------------------------------------------------------------------------------*/ + Release Date: 2018-08-02 + + Main Changes + + Add GNU Arm compiler support. + - Add project_template related files + - "startup_ht32f5xxxx_gcc_nn.s" + - "linker.ld" (link script) + + Update "ht32f5xxxx_tm.c/.h", add following functions which have TM_CH_n parameter. + void TM_ForcedOREF(HT_TM_TypeDef* TMx, TM_CH_Enum TM_CH_n, TM_OM_Enum ForcedAction) + void TM_SetCaptureCompare(HT_TM_TypeDef* TMx, TM_CH_Enum TM_CH_n, u16 Cmp) + void TM_SetAsymmetricCompare(HT_TM_TypeDef* TMx, TM_CH_Enum TM_CH_n, u16 Cmp) + u32 TM_GetCaptureCompare(HT_TM_TypeDef* TMx, TM_CH_Enum TM_CH_n) + + Others + + Add "USBD/HID_Keyboard_Virtual_COM" example. + + Fix compile error when turn on Library debug mode (HT32_LIB_DEBUG = 1). + + Modify "example/NVIC/Vector_Table_Offset" example code to support GUN compiler. + + Simplify "example/USART/HyperTerminal_TxRx_Interrupt" example. + +/*----------------------------------------------------------------------------------------------------------*/ +/* HT32F1xxxx_FWLib_v001_1302 */ +/*----------------------------------------------------------------------------------------------------------*/ + Release Date: 2018-06-11 + + Main Changes + + Add SourceryG++Lite compiler support. + - Add project_template related files + - "startup_ht32f1xxxx_cs3_nn.s" + - "linker.ld" (link script) + + Add DMA support of "utilities/common/spi_flash.c". + + Add "EXTI_GetEdgeFlag()" function. + + Add LIBCFG_AES_SWAP function to process endian issue of AES. + + Others + + Update "ht32f1xxxx_conf.h" for AUTO_RETURN (\r) option. + + Update format of IAR "startup_ht32f1xxxx_01.s". + + Fix "LIBCFC_CKCU_USB_PLL" typing error of ht32fxxxx_libcfg.h and example code (shall be LIBCFG_CKCU_USB_PLL). + + Fix IAP_PPBIT define error of "IAP/IAP_UI" example. + + Update "ht32f1xxxx_ckcu.c" to remove unnecessary register write of PLL. + +/*----------------------------------------------------------------------------------------------------------*/ +/* HT32F1xxxx_FWLib_v001_1153 */ +/*----------------------------------------------------------------------------------------------------------*/ + Release Date: 2018-02-28 + + Main Changes + + Add "USBD/USB_UAC_Sound_RateControl" Example. + + Add "I2C_SpeedOffset" parameter of I2C_InitTypeDef to reach real I2C speed. + Note: Related examples are also updated. + + Change EBI timing of "ebi_lcd.c" to fix LCD display problem on HT32F12345 with ESK32-A2A31. + + Add "CKCU/HSI_AutoTrim_By_USB" Example. + + Update "CKCU_HSIAutoTrimIsReady" function of "ht32f5xxxx_ckcu.c". + + Others + + Update format and coding style. + +/*----------------------------------------------------------------------------------------------------------*/ +/* HT32F1xxxx_FWLib_v001_1023 */ +/*----------------------------------------------------------------------------------------------------------*/ + Release Date: 2017-12-30 + + Main Changes + + Update boot related functions of "startup_ht32f1xxxx_nn.s" and "system_ht32f1xxxx_nn.c". + + Update "ht32_op.c" and "ht32_op.s" to support enable WDT function by Flash Option byte (Apply to specific + model only). + + Add "GPIO_DisableDebugPort()"" function to disable SWD function. + + Others + + Fix IAR Project setting error of IAP Example. + + Add "RTC_LSILoadTrimData()" function. + + Add "LIBCFG_RTC_LSI_LOAD_TRIM" define of HT32F165x. + + Remove useless "RTC_LSICmd()"" function. + + Update following examples, remove LSI enable code (LSI default on). + "PWRCU/DeepSleepMode1" + "PWRCU/BackupData" + "PWRCU/DeepSleepMode2" + "PWRCU/PowerDownMode" + "RTC/Calendar" + + Update I2S and USB UAC related examples (Coding style and remove unuse define). + + Update USB Example, remove invalid remote wakeup configuration by define (Only HID class support Remote + Wakeup). + +/*----------------------------------------------------------------------------------------------------------*/ +/* HT32F1xxxx_FWLib_v001_933 */ +/*----------------------------------------------------------------------------------------------------------*/ + Release Date: 2017-11-17 + + Main Changes + + Fix AES typing error of "ht32f1xxxx_aes.c/.h" (EBC to ECB). + + Fix TM define error of "ht32f1xxxx_tm.c/.h". + + Others + + Update "ht32_virtual_com.inf" file, add Digital Signature. + + Update typing error of example code. + +/*----------------------------------------------------------------------------------------------------------*/ +/* HT32F1xxxx_FWLib_v001_899 */ +/*----------------------------------------------------------------------------------------------------------*/ + Release Date: 2017-10-19 + + Main Changes + + Update "SDIO/SDCard" Example code. Fix read Card SCR problem which causes SDIO working on 1-bit mode + abnormally. + + Others + + Update project setting. + + Remove some project files. Use "CreateProject.bat" to copy project files automatically. + + Add "LIBCFG_CHIPNAME" define. + +/*----------------------------------------------------------------------------------------------------------*/ +/* HT32F1xxxx_FWLib_v001_785 */ +/*----------------------------------------------------------------------------------------------------------*/ + Release Date: 2017-08-31 + + Main Changes + + Fix "ht32f1xxxx_conf.h" typing error ("_ADC" to "_AES"). + + Fix AES typing error (EBC to ECB). + + Others + + Update "ht32_usbd_core.c" to support vendor function. + + Add "USE_MEM_HT32F1xxxx" define into project. + + Add "USE_MEM_HT32F1xxxx" default define into "ht32f1xxxx_xx_libcfg.h". + + Rename "system_ht32f1xxxx.h" to "system_ht32f1xxxx_01.h" for PACK requirement. + + Update IAP examples. + +/*----------------------------------------------------------------------------------------------------------*/ +/* HT32F1xxxx_FWLib_v001_671 */ +/*----------------------------------------------------------------------------------------------------------*/ + Release Date: 2017-07-27 + + Main Changes + + None + + Others + + Update "ht32_op.c", add CK_CODE/CK_DATA/CK_CODEOP in Option Bytes (same format with e-Writer32). + + Modify USB/Mass_Storage example for WIN10 compatibility issue. + + Add "USE_MEM_HT32F1xxxx" support for memory size define (LIBCFG_FLASH_SIZE/LIBCFG_RAM_SIZE). + + Add IAR EWARMv8 project template (create by IAR EWARM v8.11). + + Upgrade the version of IAR EWARM project template from v6.20 to v6.50. + Note: + 1. Supported CMSIS-DAP: IAR EWARM v6.50 and above. + 2. RDI/e-Link32 is not supported anymore from the v8.xx of IAR EWARM. + + Known Issue: + + IAP example is not ready, will be update in next release. + +/*----------------------------------------------------------------------------------------------------------*/ +/* HT32F1xxxx_FWLib_v001_552 */ +/*----------------------------------------------------------------------------------------------------------*/ + Release Date: 2017-07-17 + + Main Changes + + Add example code. + + Update TM for PDMA support. + + Fix "USART_RXTL_01/04/08/14" define error. + + Fix "HT32F_DVB_BuzzerFun()" define error of "ht32f1xxxx_board_01.c". + + Fix pin assignment error of "ht32f12366_sk.h" + + Others + + Add BUTTON_MODE_WAKE_UP support for "ht32f1xxxx_sk.c/.h". + + Update typing error and coding style. + + Remove warning on old MDK-ARM version. + + Update project setting. + + Add DEINIT_ENABLE setting of "ht32f1xxxx_system_nn.c". + +/*----------------------------------------------------------------------------------------------------------*/ +/* HT32F1xxxx_FWLib_v001_167 */ +/*----------------------------------------------------------------------------------------------------------*/ + Release Date: 2017-06-14 + + Main Changes + + Initial version. + + Others + + diff --git a/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/SConscript b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/SConscript new file mode 100644 index 0000000000..bae7234da6 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/SConscript @@ -0,0 +1,48 @@ +import rtconfig +from building import * + +cwd = GetCurrentDir() + +src = Split(""" + library/HT32F1xxxx_Driver/src/ht32_cm3_misc.c + library/HT32F1xxxx_Driver/src/ht32f1xxxx_adc.c + library/HT32F1xxxx_Driver/src/ht32f1xxxx_aes.c + library/HT32F1xxxx_Driver/src/ht32f1xxxx_bftm.c + library/HT32F1xxxx_Driver/src/ht32f1xxxx_ckcu.c + library/HT32F1xxxx_Driver/src/ht32f1xxxx_cmp.c + library/HT32F1xxxx_Driver/src/ht32f1xxxx_crc.c + library/HT32F1xxxx_Driver/src/ht32f1xxxx_ebi.c + library/HT32F1xxxx_Driver/src/ht32f1xxxx_exti.c + library/HT32F1xxxx_Driver/src/ht32f1xxxx_flash.c + library/HT32F1xxxx_Driver/src/ht32f1xxxx_gpio.c + library/HT32F1xxxx_Driver/src/ht32f1xxxx_i2c.c + library/HT32F1xxxx_Driver/src/ht32f1xxxx_i2s.c + library/HT32F1xxxx_Driver/src/ht32f1xxxx_mctm.c + library/HT32F1xxxx_Driver/src/ht32f1xxxx_pdma.c + library/HT32F1xxxx_Driver/src/ht32f1xxxx_pwrcu.c + library/HT32F1xxxx_Driver/src/ht32f1xxxx_rstcu.c + library/HT32F1xxxx_Driver/src/ht32f1xxxx_rtc.c + library/HT32F1xxxx_Driver/src/ht32f1xxxx_sci.c + library/HT32F1xxxx_Driver/src/ht32f1xxxx_sdio.c + library/HT32F1xxxx_Driver/src/ht32f1xxxx_spi.c + library/HT32F1xxxx_Driver/src/ht32f1xxxx_tm.c + library/HT32F1xxxx_Driver/src/ht32f1xxxx_usart.c + library/HT32F1xxxx_Driver/src/ht32f1xxxx_usbd.c + library/HT32F1xxxx_Driver/src/ht32f1xxxx_wdt.c + + library/Device/Holtek/HT32F1xxxx/Source/system_ht32f1xxxx_02.c +""") +#HT32F1xxxx_Driver/src/ht32f1xxxx_csif.c + +path = [ + cwd + '/library/HT32F1xxxx_Driver/inc', + cwd + '/library/CMSIS/Include', + cwd + '/library/Device/Holtek/HT32F1xxxx/Include' +] + +CPPDEFINES = ['USE_HT32_DRIVER'] + +group = DefineGroup('Libraries', src, depend = [''], CPPPATH = path, CPPDEFINES = CPPDEFINES) + +Return('group') + diff --git a/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/CMSIS/ARM.CMSIS.pdsc b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/CMSIS/ARM.CMSIS.pdsc new file mode 100644 index 0000000000..96775d502a --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/CMSIS/ARM.CMSIS.pdsc @@ -0,0 +1,3271 @@ + + + + CMSIS + CMSIS (Common Microcontroller Software Interface Standard) + ARM + + http://www.keil.com/pack/ + + + + CMSIS-Core(M): 5.6.0 + - Arm Cortex-M85 cpu support + - Arm China STAR-MC1 cpu support + - Updated system_ARMCM55.c + CMSIS-DSP: 1.10.0 (see revision history for details) + CMSIS-NN: 3.1.0 (see revision history for details) + - Support for int16 convolution and fully connected for reference implementation + - Support for DSP extension optimization for int16 convolution and fully connected + - Support dilation for int8 convolution + - Support dilation for int8 depthwise convolution + - Support for int16 depthwise conv for reference implementation including dilation + - Support for int16 average and max pooling for reference implementation + - Support for elementwise add and mul int16 scalar version + - Support for softmax int16 scalar version + - Support for SVDF with 8 bit state tensor + CMSIS-RTOS2: 2.1.3 (unchanged) + - RTX 5.5.4 (see revision history for details) + CMSIS-Pack: deprecated (moved to Open-CMSIS-Pack) + CMSIS-SVD: 1.3.9 (see revision history for details) + CMSIS-DAP: 2.1.1 (see revision history for details) + - Allow default clock frequency to use fast clock mode + Devices + - Support for Cortex-M85 + Utilities + - SVDConv 3.3.42 + - PackChk 1.3.95 + + + CMSIS-Core(M): 5.5.0 (see revision history for details) + - Updated GCC LinkerDescription, GCC Assembler startup + - Added Armv8-M Stack Sealing (to linker, startup) for toolchain ARM, GCC + - Changed C-Startup to default Startup. + - Updated Armv8-M Assembler startup to use GAS syntax + Note: Updating existing projects may need manual user interaction! + CMSIS-Core(A): 1.2.1 (see revision history for details) + - Bugfixes for Cortex-A32 + CMSIS-DAP: 2.1.0 (see revision history for details) + - Enhanced DAP_Info + - Added extra UART support + CMSIS-DSP: 1.9.0 (see revision history for details) + - Purged pre-built libs from Git + - Enhanced support for f16 datatype + - Fixed couple of GCC issues + CMSIS-NN: 3.0.0 (see revision history for details including version 2.0.0) + - Major interface change for functions compatible with TensorFlow Lite for Microcontroller + - Added optimization for SVDF kernel + - Improved MVE performance for fully Connected and max pool operator + - NULL bias support for fully connected operator in non-MVE case(Can affect performance) + - Expanded existing unit test suite along with support for FVP + - Removed Examples folder + CMSIS-RTOS2: + - RTX 5.5.3 (see revision history for details) + - CVE-2021-27431 vulnerability mitigation. + - Enhanced stack overrun checking. + - Various bug fixes and improvements. + CMSIS-Pack: 1.7.2 (see revision history for details) + - Support for Microchip XC32 compiler + - Support for Custom Datapath Extension + + + CMSIS-Build: 0.9.0 (beta) + - Draft for CMSIS Project description (CPRJ) + CMSIS-Core(M): 5.4.0 (see revision history for details) + - Cortex-M55 cpu support + - Enhanced MVE support for Armv8.1-MML + - Fixed device config define checks. + - L1 Cache functions for Armv7-M and later + CMSIS-Core(A): 1.2.0 (see revision history for details) + - Fixed GIC_SetPendingIRQ to use GICD_SGIR + - Added missing DSP intrinsics + - Reworked assembly intrinsics: volatile, barriers and clobber + CMSIS-DSP: 1.8.0 (see revision history for details) + - Added new functions and function groups + - Added MVE support + CMSIS-NN: 1.3.0 (see revision history for details) + - Added MVE support + - Further optimizations for kernels using DSP extension + CMSIS-RTOS2: + - RTX 5.5.2 (see revision history for details) + CMSIS-Driver: 2.8.0 + - Added VIO API 0.1.0 (Preview) + - removed volatile from status related typedefs in APIs + - enhanced WiFi Interface API with support for polling Socket Receive/Send + CMSIS-Pack: 1.6.3 (see revision history for details) + - deprecating all types specific to cpdsc format. Cpdsc is replaced by Cprj with dedicated schema. + Devices: + - ARMCM55 device + - ARMv81MML startup code recognizing __MVE_USED macro + - Refactored vector table references for all Cortex-M devices + - Reworked ARMCM* C-StartUp files. + - Include L1 Cache functions in ARMv8MML/ARMv81MML devices + Utilities: + Attention: Linux binaries moved to Linux64 folder! + - SVDConv 3.3.35 + - PackChk 1.3.89 + + + CMSIS-Core(M): 5.3.0 (see revision history for details) + - Added provisions for compiler-independent C startup code. + CMSIS-Core(A): 1.1.4 (see revision history for details) + - Fixed __FPU_Enable. + CMSIS-DSP: 1.7.0 (see revision history for details) + - New Neon versions of f32 functions + - Python wrapper + - Preliminary cmake build + - Compilation flags for FFTs + - Changes to arm_math.h + CMSIS-NN: 1.2.0 (see revision history for details) + - New function for depthwise convolution with asymmetric quantization. + - New support functions for requantization. + CMSIS-RTOS: + - RTX 4.82.0 (updated provisions for Arm Compiler 6 when using Cortex-M0/M0+) + CMSIS-RTOS2: + - RTX 5.5.1 (see revision history for details) + CMSIS-Driver: 2.7.1 + - WiFi Interface API 1.0.0 + Devices: + - Generalized C startup code for all Cortex-M family devices. + - Updated Cortex-A default memory regions and MMU configurations + - Moved Cortex-A memory and system config files to avoid include path issues + + + The following folders are deprecated + - CMSIS/Include/ (superseded by CMSIS/DSP/Include/ and CMSIS/Core/Include/) + + CMSIS-Core(M): 5.2.1 (see revision history for details) + - Fixed compilation issue in cmsis_armclang_ltm.h + + + The following folders have been removed: + - CMSIS/Lib/ (superseded by CMSIS/DSP/Lib/) + - CMSIS/DSP_Lib/ (superseded by CMSIS/DSP/) + The following folders are deprecated + - CMSIS/Include/ (superseded by CMSIS/DSP/Include/ and CMSIS/Core/Include/) + + CMSIS-Core(M): 5.2.0 (see revision history for details) + - Reworked Stack/Heap configuration for ARM startup files. + - Added Cortex-M35P device support. + - Added generic Armv8.1-M Mainline device support. + CMSIS-Core(A): 1.1.3 (see revision history for details) + CMSIS-DSP: 1.6.0 (see revision history for details) + - reworked DSP library source files + - reworked DSP library documentation + - Changed DSP folder structure + - moved DSP libraries to folder ./DSP/Lib + - ARM DSP Libraries are built with ARMCLANG + - Added DSP Libraries Source variant + CMSIS-RTOS2: + - RTX 5.5.0 (see revision history for details) + CMSIS-Driver: 2.7.0 + - Added WiFi Interface API 1.0.0-beta + - Added components for project specific driver implementations + CMSIS-Pack: 1.6.0 (see revision history for details) + Devices: + - Added Cortex-M35P and ARMv81MML device templates. + - Fixed C-Startup Code for GCC (aligned with other compilers) + Utilities: + - SVDConv 3.3.25 + - PackChk 1.3.82 + + + Aligned pack structure with repository. + The following folders are deprecated: + - CMSIS/Include/ + - CMSIS/DSP_Lib/ + + CMSIS-Core(M): 5.1.2 (see revision history for details) + - Added Cortex-M1 support (beta). + CMSIS-Core(A): 1.1.2 (see revision history for details) + CMSIS-NN: 1.1.0 + - Added new math functions. + CMSIS-RTOS2: + - API 2.1.3 (see revision history for details) + - RTX 5.4.0 (see revision history for details) + * Updated exception handling on Cortex-A + CMSIS-Driver: + - Flash Driver API V2.2.0 + Utilities: + - SVDConv 3.3.21 + - PackChk 1.3.71 + + + Updated Arm company brand. + CMSIS-Core(M): 5.1.1 (see revision history for details) + CMSIS-Core(A): 1.1.1 (see revision history for details) + CMSIS-DAP: 2.0.0 (see revision history for details) + CMSIS-NN: 1.0.0 + - Initial contribution of the bare metal Neural Network Library. + CMSIS-RTOS2: + - RTX 5.3.0 (see revision history for details) + - OS Tick API 1.0.1 + + + CMSIS-Core(M): 5.1.0 (see revision history for details) + - Added MPU Functions for ARMv8-M for Cortex-M23/M33. + - Added compiler_iccarm.h to replace compiler_iar.h shipped with the compiler. + CMSIS-Core(A): 1.1.0 (see revision history for details) + - Added compiler_iccarm.h. + - Added additional access functions for physical timer. + CMSIS-DAP: 1.2.0 (see revision history for details) + CMSIS-DSP: 1.5.2 (see revision history for details) + CMSIS-Driver: 2.6.0 (see revision history for details) + - CAN Driver API V1.2.0 + - NAND Driver API V2.3.0 + CMSIS-RTOS: + - RTX: added variant for Infineon XMC4 series affected by PMU_CM.001 errata. + CMSIS-RTOS2: + - API 2.1.2 (see revision history for details) + - RTX 5.2.3 (see revision history for details) + Devices: + - Added GCC startup and linker script for Cortex-A9. + - Added device ARMCM0plus_MPU for Cortex-M0+ with MPU. + - Added IAR startup code for Cortex-A9 + + + CMSIS-RTOS2: + - RTX 5.2.1 (see revision history for details) + + + CMSIS-Core(M): 5.0.2 (see revision history for details) + - Changed Version Control macros to be core agnostic. + - Added MPU Functions for ARMv7-M for Cortex-M0+/M3/M4/M7. + CMSIS-Core(A): 1.0.0 (see revision history for details) + - Initial release + - IRQ Controller API 1.0.0 + CMSIS-Driver: 2.05 (see revision history for details) + - All typedefs related to status have been made volatile. + CMSIS-RTOS2: + - API 2.1.1 (see revision history for details) + - RTX 5.2.0 (see revision history for details) + - OS Tick API 1.0.0 + CMSIS-DSP: 1.5.2 (see revision history for details) + - Fixed GNU Compiler specific diagnostics. + CMSIS-Pack: 1.5.0 (see revision history for details) + - added System Description File (*.SDF) Format + CMSIS-Zone: 0.0.1 (Preview) + - Initial specification draft + + + Package Description: + - added taxonomy for Cclass RTOS + CMSIS-RTOS2: + - API 2.1 (see revision history for details) + - RTX 5.1.0 (see revision history for details) + CMSIS-Core: 5.0.1 (see revision history for details) + - Added __PACKED_STRUCT macro + - Added uVisior support + - Updated cmsis_armcc.h: corrected macro __ARM_ARCH_6M__ + - Updated template for secure main function (main_s.c) + - Updated template for Context Management for ARMv8-M TrustZone (tz_context.c) + CMSIS-DSP: 1.5.1 (see revision history for details) + - added ARMv8M DSP libraries. + CMSIS-Pack:1.4.9 (see revision history for details) + - added Pack Index File specification and schema file + + + Changed open source license to Apache 2.0 + CMSIS_Core: + - Added support for Cortex-M23 and Cortex-M33. + - Added ARMv8-M device configurations for mainline and baseline. + - Added CMSE support and thread context management for TrustZone for ARMv8-M + - Added cmsis_compiler.h to unify compiler behaviour. + - Updated function SCB_EnableICache (for Cortex-M7). + - Added functions: NVIC_GetEnableIRQ, SCB_GetFPUType + CMSIS-RTOS: + - bug fix in RTX 4.82 (see revision history for details) + CMSIS-RTOS2: + - new API including compatibility layer to CMSIS-RTOS + - reference implementation based on RTX5 + - supports all Cortex-M variants including TrustZone for ARMv8-M + CMSIS-SVD: + - reworked SVD format documentation + - removed SVD file database documentation as SVD files are distributed in packs + - updated SVDConv for Win32 and Linux + CMSIS-DSP: + - Moved DSP libraries from CMSIS/DSP/Lib to CMSIS/Lib. + - Added DSP libraries build projects to CMSIS pack. + + + - CMSIS-Core 4.30.0 (see revision history for details) + - CMSIS-DAP 1.1.0 (unchanged) + - CMSIS-Driver 2.04.0 (see revision history for details) + - CMSIS-DSP 1.4.7 (no source code change [still labeled 1.4.5], see revision history for details) + - CMSIS-Pack 1.4.1 (see revision history for details) + - CMSIS-RTOS 4.80.0 Restored time delay parameter 'millisec' old behavior (prior V4.79) for software compatibility. (see revision history for details) + - CMSIS-SVD 1.3.1 (see revision history for details) + + + - CMSIS-Core 4.20 (see revision history for details) + - CMSIS-DSP 1.4.6 (no source code change [still labeled 1.4.5], see revision history for details) + - CMSIS-Pack 1.4.0 (adding memory attributes, algorithm style) + - CMSIS-Driver 2.03.0 (adding CAN [Controller Area Network] API) + - CMSIS-RTOS + -- API 1.02 (unchanged) + -- RTX 4.79 (see revision history for details) + - CMSIS-SVD 1.3.0 (see revision history for details) + - CMSIS-DAP 1.1.0 (extended with SWO support) + + + - CMSIS-Core 4.10 (Cortex-M7 extended Cache Maintenance functions) + - CMSIS-DSP 1.4.5 (see revision history for details) + - CMSIS-Driver 2.02 (adding SAI (Serial Audio Interface) API) + - CMSIS-Pack 1.3.3 (Semantic Versioning, Generator extensions) + - CMSIS-RTOS + -- API 1.02 (unchanged) + -- RTX 4.78 (see revision history for details) + - CMSIS-SVD 1.2 (unchanged) + + + Adding Cortex-M7 support + - CMSIS-Core 4.00 (Cortex-M7 support, corrected C++ include guards in core header files) + - CMSIS-DSP 1.4.4 (Cortex-M7 support and corrected out of bound issues) + - CMSIS-Pack 1.3.1 (Cortex-M7 updates, clarification, corrected batch files in Tutorial) + - CMSIS-SVD 1.2 (Cortex-M7 extensions) + - CMSIS-RTOS RTX 4.75 (see revision history for details) + + + - fixed conditions preventing the inclusion of the DSP library in projects for Infineon XMC4000 series devices + + + - CMSIS-Driver 2.02 (incompatible update) + - CMSIS-Pack 1.3 (see revision history for details) + - CMSIS-DSP 1.4.2 (unchanged) + - CMSIS-Core 3.30 (unchanged) + - CMSIS-RTOS RTX 4.74 (unchanged) + - CMSIS-RTOS API 1.02 (unchanged) + - CMSIS-SVD 1.10 (unchanged) + PACK: + - removed G++ specific files from PACK + - added Component Startup variant "C Startup" + - added Pack Checking Utility + - updated conditions to reflect tool-chain dependency + - added Taxonomy for Graphics + - updated Taxonomy for unified drivers from "Drivers" to "CMSIS Drivers" + + + + - CMSIS-RTOS 4.74 (see revision history for details) + - PACK Extensions (Boards, Device Features, Flash Programming, Generators, Configuration Wizard). Schema version 1.1. + + + + + + + + + Software components for audio processing + Generic Interfaces for Evaluation and Development Boards + Drivers that support an external component available on an evaluation board + Compiler Software Extensions + Cortex Microcontroller Software Interface Components + Unified Device Drivers compliant to CMSIS-Driver Specifications + Startup, System Setup + Data exchange or data formatter + Drivers that support an extension board or shield + File Drive Support and File System + IoT cloud client connector + IoT specific services + IoT specific software utility + Graphical User Interface + Network Stack using Internet Protocols + Real-time Operating System + Encryption for secure communication or storage + Universal Serial Bus Stack + Generic software utility components + + + + + + + +The Cortex-M0 processor is an entry-level 32-bit Arm Cortex processor designed for a broad range of embedded applications. It offers significant benefits to developers, including: +- simple, easy-to-use programmers model +- highly efficient ultra-low power operation +- excellent code density +- deterministic, high-performance interrupt handling +- upward compatibility with the rest of the Cortex-M processor family. + + + + + + + + + + + + + + + + +The Cortex-M0+ processor is an entry-level 32-bit Arm Cortex processor designed for a broad range of embedded applications. It offers significant benefits to developers, including: +- simple, easy-to-use programmers model +- highly efficient ultra-low power operation +- excellent code density +- deterministic, high-performance interrupt handling +- upward compatibility with the rest of the Cortex-M processor family. + + + + + + + + + + + + + + + + + + + + + +The ARM Cortex-M1 FPGA processor is intended for deeply embedded applications that require a small processor integrated into an FPGA. +The ARM Cortex-M1 processor implements the ARMv6-M architecture profile. + + + + + + + + + + + + + + + + +The Cortex-M3 processor is an entry-level 32-bit Arm Cortex processor designed for a broad range of embedded applications. It offers significant benefits to developers, including: +- simple, easy-to-use programmers model +- highly efficient ultra-low power operation +- excellent code density +- deterministic, high-performance interrupt handling +- upward compatibility with the rest of the Cortex-M processor family. + + + + + + + + + + + + + + + + +The Cortex-M4 processor is an entry-level 32-bit Arm Cortex processor designed for a broad range of embedded applications. It offers significant benefits to developers, including: +- simple, easy-to-use programmers model +- highly efficient ultra-low power operation +- excellent code density +- deterministic, high-performance interrupt handling +- upward compatibility with the rest of the Cortex-M processor family. + + + + + + + + + + + + + + + + + + + + + +The Cortex-M7 processor is an entry-level 32-bit Arm Cortex processor designed for a broad range of embedded applications. It offers significant benefits to developers, including: +- simple, easy-to-use programmers model +- highly efficient ultra-low power operation +- excellent code density +- deterministic, high-performance interrupt handling +- upward compatibility with the rest of the Cortex-M processor family. + + + + + + + + + + + + + + + + + + + + + + + + + + +The Arm Cortex-M23 is based on the Armv8-M baseline architecture. +It is the smallest and most energy efficient Arm processor with Arm TrustZone technology. +Cortex-M23 is the ideal processor for constrained embedded applications requiring efficient security. + + + + + + + + + + + + + + + + + + + + + + + +The Arm Cortex-M33 is the most configurable of all Cortex-M processors. It is a full featured microcontroller +class processor based on the Armv8-M mainline architecture with Arm TrustZone security. + + + + + + + + + + + + no DSP Instructions, no Floating Point Unit, no TrustZone + + + + + + + + no DSP Instructions, no Floating Point Unit, TrustZone + + + + + + + + DSP Instructions, Single Precision Floating Point Unit, no TrustZone + + + + + + + + DSP Instructions, Single Precision Floating Point Unit, TrustZone + + + + + + + + + +The Arm Cortex-M35P is the most configurable of all Cortex-M processors. It is a full featured microcontroller +class processor based on the Armv8-M mainline architecture with Arm TrustZone security designed for a broad range of secure embedded applications. + + + + + + + + + + + + + no DSP Instructions, no Floating Point Unit, no TrustZone + + + + + + + + no DSP Instructions, no Floating Point Unit, TrustZone + + + + + + + + DSP Instructions, Single Precision Floating Point Unit, no TrustZone + + + + + + + + DSP Instructions, Single Precision Floating Point Unit, TrustZone + + + + + + + + + +The Arm Cortex-M55 processor is a fully synthesizable, mid-range, microcontroller-class processor that implements the Armv8.1-M mainline architecture and includes support for the M-profile Vector Extension (MVE), also known as Arm Helium technology. +It is Arm's most AI-capable Cortex-M processor, delivering enhanced, energy-efficient digital signal processing (DSP) and machine learning (ML) performance. +The Cortex-M55 processor achieves high compute performance across scalar and vector operations, while maintaining low energy consumption. + + + + + + + + + + + + + Floating Point Vector Extensions, DSP Instructions, Double Precision Floating Point Unit, TrustZone + + + + + + + + + +The Arm Cortex-M85 processor is a fully synthesizable high-performance microcontroller class processor that implements the Armv8.1-M Mainline architecture which includes support for the M-profile Vector Extension (MVE). +The processor also supports previous Armv8-M architectural features. +The design is focused on compute applications such as Digital Signal Processing (DSP) and machine learning. +The Arm Cortex-M85 processor is energy efficient and achieves high compute performance across scalar and vector operations while maintaining low power consumption. + + + + + + + + + + + + + Floating Point Vector Extensions, DSP Instructions, Double Precision Floating Point Unit, TrustZone, PACBTI + + + + + + + + +The Arm SC000 processor is an entry-level 32-bit Arm Cortex processor designed for a broad range of secure embedded applications. It offers significant benefits to developers, including: +- simple, easy-to-use programmers model +- highly efficient ultra-low power operation +- excellent code density +- deterministic, high-performance interrupt handling + + + + + + + + + + + + + + + +The ARM SC300 processor is an entry-level 32-bit ARM Cortex processor designed for a broad range of secure embedded applications. It offers significant benefits to developers, including: +- simple, easy-to-use programmers model +- highly efficient ultra-low power operation +- excellent code density +- deterministic, high-performance interrupt handling + + + + + + + + + + + + + + + + +Armv8-M Baseline based device with TrustZone + + + + + + + + + + + + + + + + + + +Armv8-M Mainline based device with TrustZone + + + + + + + + + + + + no DSP Instructions, no Floating Point Unit, TrustZone + + + + + + + + DSP Instructions, no Floating Point Unit, TrustZone + + + + + + + + no DSP Instructions, Single Precision Floating Point Unit, TrustZone + + + + + + + + DSP Instructions, Single Precision Floating Point Unit, TrustZone + + + + + + + + no DSP Instructions, Double Precision Floating Point Unit, TrustZone + + + + + + + + DSP Instructions, Double Precision Floating Point Unit, TrustZone + + + + + + + + + +Armv8.1-M Mainline based device with TrustZone and MVE + + + + + + + + + + + + + Double Precision Vector Extensions, DSP Instructions, Double Precision Floating Point Unit, TrustZone + + + + + + + + + +The Arm Cortex-A5 processor is a high-performance, low-power, Arm macrocell with an L1 cache subsystem that provides full +virtual memory capabilities. The Cortex-A5 processor implements the Armv7-A architecture profile and can execute 32-bit +Arm instructions and 16-bit and 32-bit Thumb instructions. The Cortex-A5 is the smallest member of the Cortex-A processor family. + + + + + + + + + + + + + + + + + +The Cortex-A7 MPCore processor is a high-performance, low-power processor that implements the Armv7-A architecture. +The Cortex-A7 MPCore processor has one to four processors in a single multiprocessor device with a L1 cache subsystem, +an optional integrated GIC, and an optional L2 cache controller. + + + + + + + + + + + + + + + + + +The Cortex-A9 processor is a high-performance, low-power, Arm macrocell with an L1 cache subsystem that provides full virtual memory capabilities. +The Cortex-A9 processor implements the Armv7-A architecture and runs 32-bit Arm instructions, 16-bit and 32-bit Thumb instructions, +and 8-bit Java bytecodes in Jazelle state. + + + + + + + + + + + + + + + + + + + Device interrupt controller interface + + + + + + RTOS Kernel system tick timer interface + + + + + + + CMSIS-RTOS API for Cortex-M, SC000, and SC300 + + + + + + CMSIS-RTOS API for Cortex-M, SC000, and SC300 + + + + + + + + USART Driver API for Cortex-M + + + + + + + SPI Driver API for Cortex-M + + + + + + + SAI Driver API for Cortex-M + + + + + + + I2C Driver API for Cortex-M + + + + + + + CAN Driver API for Cortex-M + + + + + + + Flash Driver API for Cortex-M + + + + + + + MCI Driver API for Cortex-M + + + + + + + NAND Flash Driver API for Cortex-M + + + + + + + Ethernet MAC and PHY Driver API for Cortex-M + + + + + + + + Ethernet MAC Driver API for Cortex-M + + + + + + + Ethernet PHY Driver API for Cortex-M + + + + + + + USB Device Driver API for Cortex-M + + + + + + + USB Host Driver API for Cortex-M + + + + + + + WiFi driver + + + + + + + Virtual I/O + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Armv6-M architecture based device + + + + + + + Armv7-M architecture based device + + + + + + + Armv8-M base line architecture based device + + + + + Armv8-M main line architecture based device + + + + + + + Armv8.1-M main line architecture based device + + + + + + Armv8-M/Armv8.1-M architecture based device + + + + + Armv8-M architecture based device + + + + + + Armv6_7-M architecture based device + + + + + Armv6_7_8-M architecture based device + + + + + + Armv7-A architecture based device + + + + + + + TrustZone + + + + TrustZone (Secure) + + + + + TrustZone (Non-secure) + + + + + + + + Startup files for Arm Compiler 6 targeting TrustZone secure mode + + + + + Startup files for Arm Compiler 6 targeting non-TrustZone or TrustZone non-secure mode + + + + + + + Generic Arm Cortex-M0 device startup and depends on CMSIS Core + + + + + + Generic Arm Cortex-M0+ device startup and depends on CMSIS Core + + + + + + Generic Arm Cortex-M1 device startup and depends on CMSIS Core + + + + + + Generic Arm Cortex-M3 device startup and depends on CMSIS Core + + + + + + Generic Arm Cortex-M4 device startup and depends on CMSIS Core + + + + + + Generic Arm Cortex-M7 device startup and depends on CMSIS Core + + + + + + Generic Arm Cortex-M23 device startup and depends on CMSIS Core + + + + + + Generic Arm Cortex-M33 device startup and depends on CMSIS Core + + + + + + Generic Arm Cortex-M35P device startup and depends on CMSIS Core + + + + + + Generic Arm Cortex-M55 device startup and depends on CMSIS Core + + + + + + Generic Arm Cortex-M85 device startup and depends on CMSIS Core + + + + + + Generic Arm SC000 device startup and depends on CMSIS Core + + + + + + Generic Arm SC300 device startup and depends on CMSIS Core + + + + + + Generic Armv8-M Baseline device startup and depends on CMSIS Core + + + + + + Generic Armv8-M Mainline device startup and depends on CMSIS Core + + + + + + Generic Armv8.1-M Mainline device startup and depends on CMSIS Core + + + + + + Generic Arm Cortex-A5 device startup and depends on CMSIS Core + + + + + + Generic Arm Cortex-A7 device startup and depends on CMSIS Core + + + + + + Generic Arm Cortex-A9 device startup and depends on CMSIS Core + + + + + + + Components required for DSP + + + + + + + + Components required for NN + + + + + + Components required for RTOS RTX + + + + + + + Components required for RTOS RTX IFX + + + + + + + + Components required for RTOS RTX5 + + + + + + Components required for RTOS2 RTX5 + + + + + + + Components required for RTOS2 RTX5 on Armv7-A + + + + + + + + + Components required for RTOS2 RTX5 in Non-Secure Domain + + + + + + + + + Arm Compiler for Armv6-M architecture (little endian) + + + + + + Arm Compiler for Armv6-M architecture (big endian) + + + + + + Arm Compiler for Armv7-M architecture without FPU (little endian) + + + + + + + Arm Compiler for Armv7-M architecture without FPU (big endian) + + + + + + + Arm Compiler for Armv7-M architecture with FPU (little endian) + + + + + + + + Arm Compiler for Armv7-M architecture with FPU (big endian) + + + + + + + + Arm Compiler for Armv8-M base line architecture (little endian) + + + + + + Arm Compiler for Armv8-M/Armv8.1-M main line architecture without FPU/MVE (little endian) + + + + + + + + Arm Compiler for Armv8-M/Armv8.1-M main line architecture with FPU/MVE (little endian) + + + + + + + + + + + GNU Compiler for Armv6-M architecture (little endian) + + + + + + GNU Compiler for Armv6-M architecture (big endian) + + + + + + GNU Compiler for Armv7-M architecture without FPU (little endian) + + + + + + + GNU Compiler for Armv7-M architecture without FPU (big endian) + + + + + + + GNU Compiler for Armv7-M architecture with FPU (little endian) + + + + + + + + GNU Compiler for Armv7-M architecture with FPU (big endian) + + + + + + + + GNU Compiler for Armv8-M base line architecture (little endian) + + + + + + GNU Compiler for Armv8-M/Armv8.1-M main line architecture without FPU/MVE (little endian) + + + + + + + + GNU Compiler for Armv8-M/Armv8.1-M main line architecture with FPU/MVE (little endian) + + + + + + + + + + + IAR Compiler for Armv6-M architecture (little endian) + + + + + + IAR Compiler for Armv6-M architecture (big endian) + + + + + + IAR Compiler for Armv7-M architecture without FPU (little endian) + + + + + + + IAR Compiler for Armv7-M architecture without FPU (big endian) + + + + + + + IAR Compiler for Armv7-M architecture with FPU (little endian) + + + + + + + + IAR Compiler for Armv7-M architecture with FPU (big endian) + + + + + + + + IAR Compiler for Armv8-M base line architecture (little endian) + + + + + + IAR Compiler for Armv8-M main line architecture without FPU (little endian) + + + + + + + IAR Compiler for Armv8-M main line architecture with FPU (little endian) + + + + + + + + IAR Compiler for Armv8.1-M main line architecture without FPU/MVE (little endian) + + + + + + + + IAR Compiler for Armv8.1-M main line architecture with FPU/MVE (little endian) + + + + + + + + + + + Arm Assembler for Armv6-M architecture + + + + + GNU Assembler for Armv6-M architecture + + + + + + IAR Assembler for Armv6-M architecture + + + + + + Arm Assembler for Armv7-M architecture + + + + + GNU Assembler for Armv7-M architecture + + + + + + IAR Assembler for Armv7-M architecture + + + + + + GNU Assembler for Armv8-M base line architecture + + + + + GNU Assembler for Armv8-M/Armv8.1-M main line architecture + + + + + IAR Assembler for Armv8-M base line architecture + + + + + IAR Assembler for Armv8-M main line architecture + + + + + + Arm Assembler for Armv7-A architecture + + + + + GNU Assembler for Armv7-A architecture + + + + + + IAR Assembler for Armv7-A architecture + + + + + + + Components required for OS Tick Private Timer + + + + + + + Components required for OS Tick Generic Physical Timer + + + + + + + + + + CMSIS-CORE for Cortex-M, SC000, SC300, Star-MC1, ARMv8-M, ARMv8.1-M + + + + + + + + + + + + + CMSIS-CORE for Cortex-A + + + + + + + + + + + System and Startup for Generic Arm Cortex-M0 device + + + + + + + + + + + + + DEPRECATED: System and Startup for Generic Arm Cortex-M0 device + + + + + + + + + + + + + + + System and Startup for Generic Arm Cortex-M0+ device + + + + + + + + + + + + + DEPRECATED: System and Startup for Generic Arm Cortex-M0+ device + + + + + + + + + + + + + + + System and Startup for Generic Arm Cortex-M1 device + + + + + + + + + + + + + DEPRECATED: System and Startup for Generic Arm Cortex-M1 device + + + + + + + + + + + + + + + System and Startup for Generic Arm Cortex-M3 device + + + + + + + + + + + + + DEPRECATED: System and Startup for Generic Arm Cortex-M3 device + + + + + + + + + + + + + + + System and Startup for Generic Arm Cortex-M4 device + + + + + + + + + + + + + DEPRECATED: System and Startup for Generic Arm Cortex-M4 device + + + + + + + + + + + + + + + System and Startup for Generic Arm Cortex-M7 device + + + + + + + + + + + + + DEPRECATED: System and Startup for Generic Arm Cortex-M7 device + + + + + + + + + + + + + + + System and Startup for Generic Arm Cortex-M23 device + + + + + + + + + + + + + + + DEPRECATED: System and Startup for Generic Arm Cortex-M23 device + + + + + + + + + + + + + + + + + + + System and Startup for Generic Arm Cortex-M33 device + + + + + + + + + + + + + + + DEPRECATED: System and Startup for Generic Arm Cortex-M33 device + + + + + + + + + + + + + + + + + + + System and Startup for Generic Arm Cortex-M35P device + + + + + + + + + + + + + + + DEPRECATED: System and Startup for Generic Arm Cortex-M35P device + + + + + + + + + + + + + + + + + + + System and Startup for Generic Cortex-M55 device + + + + + + + + + + + + + + + + + System and Startup for Generic Cortex-M85 device + + + + + + + + + + + + + + + + + System and Startup for Generic Arm SC000 device + + + + + + + + + + + + + DEPRECATED: System and Startup for Generic Arm SC000 device + + + + + + + + + + + + + + + System and Startup for Generic Arm SC300 device + + + + + + + + + + + + + DEPRECATED: System and Startup for Generic Arm SC300 device + + + + + + + + + + + + + + + System and Startup for Generic Armv8-M Baseline device + + + + + + + + + + + + + + + DEPRECATED: System and Startup for Generic Armv8-M Baseline device + + + + + + + + + + + + + + + + + + System and Startup for Generic Armv8-M Mainline device + + + + + + + + + + + + + + + DEPRECATED: System and Startup for Generic Armv8-M Mainline device + + + + + + + + + + + + + + + + + + System and Startup for Generic Armv8.1-M Mainline device + + + + + + + + + + + + + + + + + System and Startup for Generic Arm Cortex-A5 device + + + + + + + + + + + + + + + + + + + + + + + System and Startup for Generic Arm Cortex-A7 device + + + + + + + + + + + + + + + + + + + + + + System and Startup for Generic Arm Cortex-A9 device + + + + + + + + + + + + + + + + + + + + + + IRQ Controller implementation using GIC + + + + + + + + OS Tick implementation using Private Timer + + + + + + + OS Tick implementation using Generic Physical Timer + + + + + + + + CMSIS-DSP Library for Cortex-M, SC000, and SC300 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + CMSIS-NN Neural Network Library + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + CMSIS-RTOS RTX implementation for Cortex-M, SC000, and SC300 + + + #define RTE_CMSIS_RTOS /* CMSIS-RTOS */ + #define RTE_CMSIS_RTOS_RTX /* CMSIS-RTOS Keil RTX */ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + CMSIS-RTOS RTX implementation for Infineon XMC4 series affected by PMU_CM.001 errata + + + #define RTE_CMSIS_RTOS /* CMSIS-RTOS */ + #define RTE_CMSIS_RTOS_RTX /* CMSIS-RTOS Keil RTX */ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + CMSIS-RTOS RTX5 implementation for Cortex-M, SC000, and SC300 + + + #define RTE_CMSIS_RTOS /* CMSIS-RTOS */ + #define RTE_CMSIS_RTOS_RTX5 /* CMSIS-RTOS Keil RTX5 */ + + + + + + + + + + + + CMSIS-RTOS2 RTX5 for Cortex-M, SC000, SC300, ARMv8-M, ARMv8.1-M (Library) + + + #define RTE_CMSIS_RTOS2 /* CMSIS-RTOS2 */ + #define RTE_CMSIS_RTOS2_RTX5 /* CMSIS-RTOS2 Keil RTX5 */ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + CMSIS-RTOS2 RTX5 for Armv8-M/Armv8.1-M Non-Secure Domain (Library) + + + #define RTE_CMSIS_RTOS2 /* CMSIS-RTOS2 */ + #define RTE_CMSIS_RTOS2_RTX5 /* CMSIS-RTOS2 Keil RTX5 */ + #define RTE_CMSIS_RTOS2_RTX5_ARMV8M_NS /* CMSIS-RTOS2 Keil RTX5 Armv8-M Non-secure domain */ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + CMSIS-RTOS2 RTX5 for Cortex-M, SC000, SC300, ARMv8-M, ARMv8.1-M (Source) + + + #define RTE_CMSIS_RTOS2 /* CMSIS-RTOS2 */ + #define RTE_CMSIS_RTOS2_RTX5 /* CMSIS-RTOS2 Keil RTX5 */ + #define RTE_CMSIS_RTOS2_RTX5_SOURCE /* CMSIS-RTOS2 Keil RTX5 Source */ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + CMSIS-RTOS2 RTX5 for Armv7-A (Source) + + + #define RTE_CMSIS_RTOS2 /* CMSIS-RTOS2 */ + #define RTE_CMSIS_RTOS2_RTX5 /* CMSIS-RTOS2 Keil RTX5 */ + #define RTE_CMSIS_RTOS2_RTX5_SOURCE /* CMSIS-RTOS2 Keil RTX5 Source */ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + CMSIS-RTOS2 RTX5 for Armv8-M/Armv8.1-M Non-Secure Domain (Source) + + + #define RTE_CMSIS_RTOS2 /* CMSIS-RTOS2 */ + #define RTE_CMSIS_RTOS2_RTX5 /* CMSIS-RTOS2 Keil RTX5 */ + #define RTE_CMSIS_RTOS2_RTX5_SOURCE /* CMSIS-RTOS2 Keil RTX5 Source */ + #define RTE_CMSIS_RTOS2_RTX5_ARMV8M_NS /* CMSIS-RTOS2 Keil RTX5 Armv8-M Non-secure domain */ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Access to #include Driver_USART.h file and code template for custom implementation + + + + + + + Access to #include Driver_SPI.h file and code template for custom implementation + + + + + + + Access to #include Driver_SAI.h file and code template for custom implementation + + + + + + + Access to #include Driver_I2C.h file and code template for custom implementation + + + + + + + Access to #include Driver_CAN.h file and code template for custom implementation + + + + + + + Access to #include Driver_Flash.h file and code template for custom implementation + + + + + + + Access to #include Driver_MCI.h file and code template for custom implementation + + + + + + + Access to #include Driver_NAND.h file and code template for custom implementation + + + + + + + Access to #include Driver_ETH_PHY/MAC.h files and code templates for custom implementation + + + + + + + + + Access to #include Driver_ETH_MAC.h file and code template for custom implementation + + + + + + + Access to #include Driver_ETH_PHY.h file and code template for custom implementation + + + + + + + Access to #include Driver_USBD.h file and code template for custom implementation + + + + + + + Access to #include Driver_USBH.h file and code template for custom implementation + + + + + + + Access to #include Driver_WiFi.h file + + + + + + + + + Virtual I/O custom implementation template + + + + + + Virtual I/O implementation using memory only + + + + + + + + + + uVision Simulator + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + EWARM Simulator + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + DSP_Lib Bayes example + + + + + + + + + Getting Started + + + + + DSP_Lib Class Marks example + + + + + + + + + Getting Started + + + + + DSP_Lib Convolution example + + + + + + + + + Getting Started + + + + + DSP_Lib Dotproduct example + + + + + + + + + Getting Started + + + + + DSP_Lib FFT Bin example + + + + + + + + + Getting Started + + + + + DSP_Lib FIR example + + + + + + + + + Getting Started + + + + + DSP_Lib Graphic Equalizer example + + + + + + + + + Getting Started + + + + + DSP_Lib Linear Interpolation example + + + + + + + + + Getting Started + + + + + DSP_Lib Matrix example + + + + + + + + + Getting Started + + + + + DSP_Lib Signal Convergence example + + + + + + + + + Getting Started + + + + + DSP_Lib Sinus/Cosinus example + + + + + + + + + Getting Started + + + + + DSP_Lib SVM example + + + + + + + + + Getting Started + + + + + DSP_Lib Variance example + + + + + + + + + Getting Started + + + + + CMSIS-RTOS2 Blinky example + + + + + + + + + Getting Started + + + + + CMSIS-RTOS2 mixed API v1 and v2 + + + + + + + + + Getting Started + + + + + CMSIS-RTOS2 Message Queue Example + + + + + + + + + + Getting Started + + + + + CMSIS-RTOS2 Memory Pool Example + + + + + + + + + + Getting Started + + + + + Bare-metal secure/non-secure example without RTOS + + + + + + + + + Getting Started + + + + + Secure/non-secure RTOS example with thread context management + + + + + + + + + Getting Started + + + + + Secure/non-secure RTOS example with security test cases and system recovery + + + + + + + + + Getting Started + + + + + CMSIS-RTOS2 Blinky example + + + + + + + + + Getting Started + + + + + CMSIS-RTOS2 Message Queue Example + + + + + + + + + Getting Started + + + + + + diff --git a/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/CMSIS/Core/Include/cachel1_armv7.h b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/CMSIS/Core/Include/cachel1_armv7.h new file mode 100644 index 0000000000..abebc95f94 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/CMSIS/Core/Include/cachel1_armv7.h @@ -0,0 +1,411 @@ +/****************************************************************************** + * @file cachel1_armv7.h + * @brief CMSIS Level 1 Cache API for Armv7-M and later + * @version V1.0.1 + * @date 19. April 2021 + ******************************************************************************/ +/* + * Copyright (c) 2020-2021 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef ARM_CACHEL1_ARMV7_H +#define ARM_CACHEL1_ARMV7_H + +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_CacheFunctions Cache Functions + \brief Functions that configure Instruction and Data cache. + @{ + */ + +/* Cache Size ID Register Macros */ +#define CCSIDR_WAYS(x) (((x) & SCB_CCSIDR_ASSOCIATIVITY_Msk) >> SCB_CCSIDR_ASSOCIATIVITY_Pos) +#define CCSIDR_SETS(x) (((x) & SCB_CCSIDR_NUMSETS_Msk ) >> SCB_CCSIDR_NUMSETS_Pos ) + +#ifndef __SCB_DCACHE_LINE_SIZE +#define __SCB_DCACHE_LINE_SIZE 32U /*!< Cortex-M7 cache line size is fixed to 32 bytes (8 words). See also register SCB_CCSIDR */ +#endif + +#ifndef __SCB_ICACHE_LINE_SIZE +#define __SCB_ICACHE_LINE_SIZE 32U /*!< Cortex-M7 cache line size is fixed to 32 bytes (8 words). See also register SCB_CCSIDR */ +#endif + +/** + \brief Enable I-Cache + \details Turns on I-Cache + */ +__STATIC_FORCEINLINE void SCB_EnableICache (void) +{ + #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) + if (SCB->CCR & SCB_CCR_IC_Msk) return; /* return if ICache is already enabled */ + + __DSB(); + __ISB(); + SCB->ICIALLU = 0UL; /* invalidate I-Cache */ + __DSB(); + __ISB(); + SCB->CCR |= (uint32_t)SCB_CCR_IC_Msk; /* enable I-Cache */ + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Disable I-Cache + \details Turns off I-Cache + */ +__STATIC_FORCEINLINE void SCB_DisableICache (void) +{ + #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) + __DSB(); + __ISB(); + SCB->CCR &= ~(uint32_t)SCB_CCR_IC_Msk; /* disable I-Cache */ + SCB->ICIALLU = 0UL; /* invalidate I-Cache */ + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Invalidate I-Cache + \details Invalidates I-Cache + */ +__STATIC_FORCEINLINE void SCB_InvalidateICache (void) +{ + #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) + __DSB(); + __ISB(); + SCB->ICIALLU = 0UL; + __DSB(); + __ISB(); + #endif +} + + +/** + \brief I-Cache Invalidate by address + \details Invalidates I-Cache for the given address. + I-Cache is invalidated starting from a 32 byte aligned address in 32 byte granularity. + I-Cache memory blocks which are part of given address + given size are invalidated. + \param[in] addr address + \param[in] isize size of memory block (in number of bytes) +*/ +__STATIC_FORCEINLINE void SCB_InvalidateICache_by_Addr (volatile void *addr, int32_t isize) +{ + #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) + if ( isize > 0 ) { + int32_t op_size = isize + (((uint32_t)addr) & (__SCB_ICACHE_LINE_SIZE - 1U)); + uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_ICACHE_LINE_SIZE - 1U) */; + + __DSB(); + + do { + SCB->ICIMVAU = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */ + op_addr += __SCB_ICACHE_LINE_SIZE; + op_size -= __SCB_ICACHE_LINE_SIZE; + } while ( op_size > 0 ); + + __DSB(); + __ISB(); + } + #endif +} + + +/** + \brief Enable D-Cache + \details Turns on D-Cache + */ +__STATIC_FORCEINLINE void SCB_EnableDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + if (SCB->CCR & SCB_CCR_DC_Msk) return; /* return if DCache is already enabled */ + + SCB->CSSELR = 0U; /* select Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) | + ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + __DSB(); + + SCB->CCR |= (uint32_t)SCB_CCR_DC_Msk; /* enable D-Cache */ + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Disable D-Cache + \details Turns off D-Cache + */ +__STATIC_FORCEINLINE void SCB_DisableDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /* select Level 1 data cache */ + __DSB(); + + SCB->CCR &= ~(uint32_t)SCB_CCR_DC_Msk; /* disable D-Cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* clean & invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) | + ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Invalidate D-Cache + \details Invalidates D-Cache + */ +__STATIC_FORCEINLINE void SCB_InvalidateDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /* select Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) | + ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Clean D-Cache + \details Cleans D-Cache + */ +__STATIC_FORCEINLINE void SCB_CleanDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /* select Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* clean D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCCSW = (((sets << SCB_DCCSW_SET_Pos) & SCB_DCCSW_SET_Msk) | + ((ways << SCB_DCCSW_WAY_Pos) & SCB_DCCSW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Clean & Invalidate D-Cache + \details Cleans and Invalidates D-Cache + */ +__STATIC_FORCEINLINE void SCB_CleanInvalidateDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /* select Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* clean & invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) | + ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief D-Cache Invalidate by address + \details Invalidates D-Cache for the given address. + D-Cache is invalidated starting from a 32 byte aligned address in 32 byte granularity. + D-Cache memory blocks which are part of given address + given size are invalidated. + \param[in] addr address + \param[in] dsize size of memory block (in number of bytes) +*/ +__STATIC_FORCEINLINE void SCB_InvalidateDCache_by_Addr (volatile void *addr, int32_t dsize) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + if ( dsize > 0 ) { + int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U)); + uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */; + + __DSB(); + + do { + SCB->DCIMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */ + op_addr += __SCB_DCACHE_LINE_SIZE; + op_size -= __SCB_DCACHE_LINE_SIZE; + } while ( op_size > 0 ); + + __DSB(); + __ISB(); + } + #endif +} + + +/** + \brief D-Cache Clean by address + \details Cleans D-Cache for the given address + D-Cache is cleaned starting from a 32 byte aligned address in 32 byte granularity. + D-Cache memory blocks which are part of given address + given size are cleaned. + \param[in] addr address + \param[in] dsize size of memory block (in number of bytes) +*/ +__STATIC_FORCEINLINE void SCB_CleanDCache_by_Addr (volatile void *addr, int32_t dsize) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + if ( dsize > 0 ) { + int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U)); + uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */; + + __DSB(); + + do { + SCB->DCCMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */ + op_addr += __SCB_DCACHE_LINE_SIZE; + op_size -= __SCB_DCACHE_LINE_SIZE; + } while ( op_size > 0 ); + + __DSB(); + __ISB(); + } + #endif +} + + +/** + \brief D-Cache Clean and Invalidate by address + \details Cleans and invalidates D_Cache for the given address + D-Cache is cleaned and invalidated starting from a 32 byte aligned address in 32 byte granularity. + D-Cache memory blocks which are part of given address + given size are cleaned and invalidated. + \param[in] addr address (aligned to 32-byte boundary) + \param[in] dsize size of memory block (in number of bytes) +*/ +__STATIC_FORCEINLINE void SCB_CleanInvalidateDCache_by_Addr (volatile void *addr, int32_t dsize) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + if ( dsize > 0 ) { + int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U)); + uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */; + + __DSB(); + + do { + SCB->DCCIMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */ + op_addr += __SCB_DCACHE_LINE_SIZE; + op_size -= __SCB_DCACHE_LINE_SIZE; + } while ( op_size > 0 ); + + __DSB(); + __ISB(); + } + #endif +} + +/*@} end of CMSIS_Core_CacheFunctions */ + +#endif /* ARM_CACHEL1_ARMV7_H */ diff --git a/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/CMSIS/Core/Include/cmsis_armcc.h b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/CMSIS/Core/Include/cmsis_armcc.h new file mode 100644 index 0000000000..a955d47139 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/CMSIS/Core/Include/cmsis_armcc.h @@ -0,0 +1,888 @@ +/**************************************************************************//** + * @file cmsis_armcc.h + * @brief CMSIS compiler ARMCC (Arm Compiler 5) header file + * @version V5.3.2 + * @date 27. May 2021 + ******************************************************************************/ +/* + * Copyright (c) 2009-2021 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_ARMCC_H +#define __CMSIS_ARMCC_H + + +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 400677) + #error "Please use Arm Compiler Toolchain V4.0.677 or later!" +#endif + +/* CMSIS compiler control architecture macros */ +#if ((defined (__TARGET_ARCH_6_M ) && (__TARGET_ARCH_6_M == 1)) || \ + (defined (__TARGET_ARCH_6S_M ) && (__TARGET_ARCH_6S_M == 1)) ) + #define __ARM_ARCH_6M__ 1 +#endif + +#if (defined (__TARGET_ARCH_7_M ) && (__TARGET_ARCH_7_M == 1)) + #define __ARM_ARCH_7M__ 1 +#endif + +#if (defined (__TARGET_ARCH_7E_M) && (__TARGET_ARCH_7E_M == 1)) + #define __ARM_ARCH_7EM__ 1 +#endif + + /* __ARM_ARCH_8M_BASE__ not applicable */ + /* __ARM_ARCH_8M_MAIN__ not applicable */ + /* __ARM_ARCH_8_1M_MAIN__ not applicable */ + +/* CMSIS compiler control DSP macros */ +#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + #define __ARM_FEATURE_DSP 1 +#endif + +/* CMSIS compiler specific defines */ +#ifndef __ASM + #define __ASM __asm +#endif +#ifndef __INLINE + #define __INLINE __inline +#endif +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static __inline +#endif +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE static __forceinline +#endif +#ifndef __NO_RETURN + #define __NO_RETURN __declspec(noreturn) +#endif +#ifndef __USED + #define __USED __attribute__((used)) +#endif +#ifndef __WEAK + #define __WEAK __attribute__((weak)) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed)) +#endif +#ifndef __PACKED_STRUCT + #define __PACKED_STRUCT __packed struct +#endif +#ifndef __PACKED_UNION + #define __PACKED_UNION __packed union +#endif +#ifndef __UNALIGNED_UINT32 /* deprecated */ + #define __UNALIGNED_UINT32(x) (*((__packed uint32_t *)(x))) +#endif +#ifndef __UNALIGNED_UINT16_WRITE + #define __UNALIGNED_UINT16_WRITE(addr, val) ((*((__packed uint16_t *)(addr))) = (val)) +#endif +#ifndef __UNALIGNED_UINT16_READ + #define __UNALIGNED_UINT16_READ(addr) (*((const __packed uint16_t *)(addr))) +#endif +#ifndef __UNALIGNED_UINT32_WRITE + #define __UNALIGNED_UINT32_WRITE(addr, val) ((*((__packed uint32_t *)(addr))) = (val)) +#endif +#ifndef __UNALIGNED_UINT32_READ + #define __UNALIGNED_UINT32_READ(addr) (*((const __packed uint32_t *)(addr))) +#endif +#ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __RESTRICT + #define __RESTRICT __restrict +#endif +#ifndef __COMPILER_BARRIER + #define __COMPILER_BARRIER() __memory_changed() +#endif + +/* ######################### Startup and Lowlevel Init ######################## */ + +#ifndef __PROGRAM_START +#define __PROGRAM_START __main +#endif + +#ifndef __INITIAL_SP +#define __INITIAL_SP Image$$ARM_LIB_STACK$$ZI$$Limit +#endif + +#ifndef __STACK_LIMIT +#define __STACK_LIMIT Image$$ARM_LIB_STACK$$ZI$$Base +#endif + +#ifndef __VECTOR_TABLE +#define __VECTOR_TABLE __Vectors +#endif + +#ifndef __VECTOR_TABLE_ATTRIBUTE +#define __VECTOR_TABLE_ATTRIBUTE __attribute__((used, section("RESET"))) +#endif + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP __nop + + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +#define __WFI __wfi + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE __wfe + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV __sev + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +#define __ISB() __isb(0xF) + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +#define __DSB() __dsb(0xF) + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +#define __DMB() __dmb(0xF) + + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV __rev + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. + \param [in] value Value to reverse + \return Reversed value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value) +{ + rev16 r0, r0 + bx lr +} +#endif + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. + \param [in] value Value to reverse + \return Reversed value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int16_t __REVSH(int16_t value) +{ + revsh r0, r0 + bx lr +} +#endif + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +#define __ROR __ror + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __breakpoint(value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + #define __RBIT __rbit +#else +__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value) +{ + uint32_t result; + uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */ + + result = value; /* r will be reversed bits of v; first get LSB of v */ + for (value >>= 1U; value != 0U; value >>= 1U) + { + result <<= 1U; + result |= value & 1U; + s--; + } + result <<= s; /* shift when v's highest bits are zero */ + return result; +} +#endif + + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +#define __CLZ __clz + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr)) +#else + #define __LDREXB(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint8_t ) __ldrex(ptr)) _Pragma("pop") +#endif + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __LDREXH(ptr) ((uint16_t) __ldrex(ptr)) +#else + #define __LDREXH(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint16_t) __ldrex(ptr)) _Pragma("pop") +#endif + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr)) +#else + #define __LDREXW(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex(ptr)) _Pragma("pop") +#endif + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __STREXB(value, ptr) __strex(value, ptr) +#else + #define __STREXB(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") +#endif + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __STREXH(value, ptr) __strex(value, ptr) +#else + #define __STREXH(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") +#endif + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __STREXW(value, ptr) __strex(value, ptr) +#else + #define __STREXW(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") +#endif + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +#define __CLREX __clrex + + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT __ssat + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT __usat + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value) +{ + rrx r0, r0 + bx lr +} +#endif + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDRBT(ptr) ((uint8_t ) __ldrt(ptr)) + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDRHT(ptr) ((uint16_t) __ldrt(ptr)) + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDRT(ptr) ((uint32_t ) __ldrt(ptr)) + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +#define __STRBT(value, ptr) __strt(value, ptr) + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +#define __STRHT(value, ptr) __strt(value, ptr) + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +#define __STRT(value, ptr) __strt(value, ptr) + +#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +__attribute__((always_inline)) __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat) +{ + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; +} + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat) +{ + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing special-purpose register PRIMASK. + Can only be executed in Privileged modes. + */ +/* intrinsic void __enable_irq(); */ + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting special-purpose register PRIMASK. + Can only be executed in Privileged modes. + */ +/* intrinsic void __disable_irq(); */ + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__STATIC_INLINE uint32_t __get_CONTROL(void) +{ + register uint32_t __regControl __ASM("control"); + return(__regControl); +} + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__STATIC_INLINE void __set_CONTROL(uint32_t control) +{ + register uint32_t __regControl __ASM("control"); + __regControl = control; + __ISB(); +} + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__STATIC_INLINE uint32_t __get_IPSR(void) +{ + register uint32_t __regIPSR __ASM("ipsr"); + return(__regIPSR); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__STATIC_INLINE uint32_t __get_APSR(void) +{ + register uint32_t __regAPSR __ASM("apsr"); + return(__regAPSR); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__STATIC_INLINE uint32_t __get_xPSR(void) +{ + register uint32_t __regXPSR __ASM("xpsr"); + return(__regXPSR); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__STATIC_INLINE uint32_t __get_PSP(void) +{ + register uint32_t __regProcessStackPointer __ASM("psp"); + return(__regProcessStackPointer); +} + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) +{ + register uint32_t __regProcessStackPointer __ASM("psp"); + __regProcessStackPointer = topOfProcStack; +} + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__STATIC_INLINE uint32_t __get_MSP(void) +{ + register uint32_t __regMainStackPointer __ASM("msp"); + return(__regMainStackPointer); +} + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) +{ + register uint32_t __regMainStackPointer __ASM("msp"); + __regMainStackPointer = topOfMainStack; +} + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__STATIC_INLINE uint32_t __get_PRIMASK(void) +{ + register uint32_t __regPriMask __ASM("primask"); + return(__regPriMask); +} + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__STATIC_INLINE void __set_PRIMASK(uint32_t priMask) +{ + register uint32_t __regPriMask __ASM("primask"); + __regPriMask = (priMask); +} + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing special-purpose register FAULTMASK. + Can only be executed in Privileged modes. + */ +#define __enable_fault_irq __enable_fiq + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting special-purpose register FAULTMASK. + Can only be executed in Privileged modes. + */ +#define __disable_fault_irq __disable_fiq + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__STATIC_INLINE uint32_t __get_BASEPRI(void) +{ + register uint32_t __regBasePri __ASM("basepri"); + return(__regBasePri); +} + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__STATIC_INLINE void __set_BASEPRI(uint32_t basePri) +{ + register uint32_t __regBasePri __ASM("basepri"); + __regBasePri = (basePri & 0xFFU); +} + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + register uint32_t __regBasePriMax __ASM("basepri_max"); + __regBasePriMax = (basePri & 0xFFU); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__STATIC_INLINE uint32_t __get_FAULTMASK(void) +{ + register uint32_t __regFaultMask __ASM("faultmask"); + return(__regFaultMask); +} + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) +{ + register uint32_t __regFaultMask __ASM("faultmask"); + __regFaultMask = (faultMask & (uint32_t)1U); +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ + + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +__STATIC_INLINE uint32_t __get_FPSCR(void) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) + register uint32_t __regfpscr __ASM("fpscr"); + return(__regfpscr); +#else + return(0U); +#endif +} + + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +__STATIC_INLINE void __set_FPSCR(uint32_t fpscr) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) + register uint32_t __regfpscr __ASM("fpscr"); + __regfpscr = (fpscr); +#else + (void)fpscr; +#endif +} + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + +#define __SADD8 __sadd8 +#define __QADD8 __qadd8 +#define __SHADD8 __shadd8 +#define __UADD8 __uadd8 +#define __UQADD8 __uqadd8 +#define __UHADD8 __uhadd8 +#define __SSUB8 __ssub8 +#define __QSUB8 __qsub8 +#define __SHSUB8 __shsub8 +#define __USUB8 __usub8 +#define __UQSUB8 __uqsub8 +#define __UHSUB8 __uhsub8 +#define __SADD16 __sadd16 +#define __QADD16 __qadd16 +#define __SHADD16 __shadd16 +#define __UADD16 __uadd16 +#define __UQADD16 __uqadd16 +#define __UHADD16 __uhadd16 +#define __SSUB16 __ssub16 +#define __QSUB16 __qsub16 +#define __SHSUB16 __shsub16 +#define __USUB16 __usub16 +#define __UQSUB16 __uqsub16 +#define __UHSUB16 __uhsub16 +#define __SASX __sasx +#define __QASX __qasx +#define __SHASX __shasx +#define __UASX __uasx +#define __UQASX __uqasx +#define __UHASX __uhasx +#define __SSAX __ssax +#define __QSAX __qsax +#define __SHSAX __shsax +#define __USAX __usax +#define __UQSAX __uqsax +#define __UHSAX __uhsax +#define __USAD8 __usad8 +#define __USADA8 __usada8 +#define __SSAT16 __ssat16 +#define __USAT16 __usat16 +#define __UXTB16 __uxtb16 +#define __UXTAB16 __uxtab16 +#define __SXTB16 __sxtb16 +#define __SXTAB16 __sxtab16 +#define __SMUAD __smuad +#define __SMUADX __smuadx +#define __SMLAD __smlad +#define __SMLADX __smladx +#define __SMLALD __smlald +#define __SMLALDX __smlaldx +#define __SMUSD __smusd +#define __SMUSDX __smusdx +#define __SMLSD __smlsd +#define __SMLSDX __smlsdx +#define __SMLSLD __smlsld +#define __SMLSLDX __smlsldx +#define __SEL __sel +#define __QADD __qadd +#define __QSUB __qsub + +#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ + ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) + +#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ + ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) + +#define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \ + ((int64_t)(ARG3) << 32U) ) >> 32U)) + +#define __SXTB16_RORn(ARG1, ARG2) __SXTB16(__ROR(ARG1, ARG2)) + +#define __SXTAB16_RORn(ARG1, ARG2, ARG3) __SXTAB16(ARG1, __ROR(ARG2, ARG3)) + +#endif /* ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#endif /* __CMSIS_ARMCC_H */ diff --git a/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/CMSIS/Core/Include/cmsis_armclang.h b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/CMSIS/Core/Include/cmsis_armclang.h new file mode 100644 index 0000000000..6911417747 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/CMSIS/Core/Include/cmsis_armclang.h @@ -0,0 +1,1503 @@ +/**************************************************************************//** + * @file cmsis_armclang.h + * @brief CMSIS compiler armclang (Arm Compiler 6) header file + * @version V5.4.3 + * @date 27. May 2021 + ******************************************************************************/ +/* + * Copyright (c) 2009-2021 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/*lint -esym(9058, IRQn)*/ /* disable MISRA 2012 Rule 2.4 for IRQn */ + +#ifndef __CMSIS_ARMCLANG_H +#define __CMSIS_ARMCLANG_H + +#pragma clang system_header /* treat file as system include file */ + +/* CMSIS compiler specific defines */ +#ifndef __ASM + #define __ASM __asm +#endif +#ifndef __INLINE + #define __INLINE __inline +#endif +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static __inline +#endif +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __attribute__((always_inline)) static __inline +#endif +#ifndef __NO_RETURN + #define __NO_RETURN __attribute__((__noreturn__)) +#endif +#ifndef __USED + #define __USED __attribute__((used)) +#endif +#ifndef __WEAK + #define __WEAK __attribute__((weak)) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_UNION + #define __PACKED_UNION union __attribute__((packed, aligned(1))) +#endif +#ifndef __UNALIGNED_UINT32 /* deprecated */ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32 */ + struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) +#endif +#ifndef __UNALIGNED_UINT16_WRITE + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT16_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_WRITE */ + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT16_READ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT16_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_READ */ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) +#endif +#ifndef __UNALIGNED_UINT32_WRITE + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_WRITE */ + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT32_READ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_READ */ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) +#endif +#ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __RESTRICT + #define __RESTRICT __restrict +#endif +#ifndef __COMPILER_BARRIER + #define __COMPILER_BARRIER() __ASM volatile("":::"memory") +#endif + +/* ######################### Startup and Lowlevel Init ######################## */ + +#ifndef __PROGRAM_START +#define __PROGRAM_START __main +#endif + +#ifndef __INITIAL_SP +#define __INITIAL_SP Image$$ARM_LIB_STACK$$ZI$$Limit +#endif + +#ifndef __STACK_LIMIT +#define __STACK_LIMIT Image$$ARM_LIB_STACK$$ZI$$Base +#endif + +#ifndef __VECTOR_TABLE +#define __VECTOR_TABLE __Vectors +#endif + +#ifndef __VECTOR_TABLE_ATTRIBUTE +#define __VECTOR_TABLE_ATTRIBUTE __attribute__((used, section("RESET"))) +#endif + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +#ifndef __STACK_SEAL +#define __STACK_SEAL Image$$STACKSEAL$$ZI$$Base +#endif + +#ifndef __TZ_STACK_SEAL_SIZE +#define __TZ_STACK_SEAL_SIZE 8U +#endif + +#ifndef __TZ_STACK_SEAL_VALUE +#define __TZ_STACK_SEAL_VALUE 0xFEF5EDA5FEF5EDA5ULL +#endif + + +__STATIC_FORCEINLINE void __TZ_set_STACKSEAL_S (uint32_t* stackTop) { + *((uint64_t *)stackTop) = __TZ_STACK_SEAL_VALUE; +} +#endif + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/* Define macros for porting to both thumb1 and thumb2. + * For thumb1, use low register (r0-r7), specified by constraint "l" + * Otherwise, use general registers, specified by constraint "r" */ +#if defined (__thumb__) && !defined (__thumb2__) +#define __CMSIS_GCC_OUT_REG(r) "=l" (r) +#define __CMSIS_GCC_RW_REG(r) "+l" (r) +#define __CMSIS_GCC_USE_REG(r) "l" (r) +#else +#define __CMSIS_GCC_OUT_REG(r) "=r" (r) +#define __CMSIS_GCC_RW_REG(r) "+r" (r) +#define __CMSIS_GCC_USE_REG(r) "r" (r) +#endif + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP __builtin_arm_nop + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +#define __WFI __builtin_arm_wfi + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE __builtin_arm_wfe + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV __builtin_arm_sev + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +#define __ISB() __builtin_arm_isb(0xF) + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +#define __DSB() __builtin_arm_dsb(0xF) + + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +#define __DMB() __builtin_arm_dmb(0xF) + + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV(value) __builtin_bswap32(value) + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV16(value) __ROR(__REV(value), 16) + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REVSH(value) (int16_t)__builtin_bswap16(value) + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) +{ + op2 %= 32U; + if (op2 == 0U) + { + return op1; + } + return (op1 >> op2) | (op1 << (32U - op2)); +} + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __ASM volatile ("bkpt "#value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +#define __RBIT __builtin_arm_rbit + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +__STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value) +{ + /* Even though __builtin_clz produces a CLZ instruction on ARM, formally + __builtin_clz(0) is undefined behaviour, so handle this case specially. + This guarantees ARM-compatible results if happening to compile on a non-ARM + target, and ensures the compiler doesn't decide to activate any + optimisations using the logic "value was passed to __builtin_clz, so it + is non-zero". + ARM Compiler 6.10 and possibly earlier will optimise this test away, leaving a + single CLZ instruction. + */ + if (value == 0U) + { + return 32U; + } + return __builtin_clz(value); +} + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) + +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDREXB (uint8_t)__builtin_arm_ldrex + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDREXH (uint16_t)__builtin_arm_ldrex + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDREXW (uint32_t)__builtin_arm_ldrex + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXB (uint32_t)__builtin_arm_strex + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXH (uint32_t)__builtin_arm_strex + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXW (uint32_t)__builtin_arm_strex + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +#define __CLREX __builtin_arm_clrex + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT __builtin_arm_ssat + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT __builtin_arm_usat + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) ); +} + +#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) */ + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat) +{ + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; +} + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat) +{ + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) + +/** + \brief Load-Acquire (8 bit) + \details Executes a LDAB instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return ((uint8_t) result); +} + + +/** + \brief Load-Acquire (16 bit) + \details Executes a LDAH instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return ((uint16_t) result); +} + + +/** + \brief Load-Acquire (32 bit) + \details Executes a LDA instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return(result); +} + + +/** + \brief Store-Release (8 bit) + \details Executes a STLB instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Store-Release (16 bit) + \details Executes a STLH instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Store-Release (32 bit) + \details Executes a STL instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Load-Acquire Exclusive (8 bit) + \details Executes a LDAB exclusive instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDAEXB (uint8_t)__builtin_arm_ldaex + + +/** + \brief Load-Acquire Exclusive (16 bit) + \details Executes a LDAH exclusive instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDAEXH (uint16_t)__builtin_arm_ldaex + + +/** + \brief Load-Acquire Exclusive (32 bit) + \details Executes a LDA exclusive instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDAEX (uint32_t)__builtin_arm_ldaex + + +/** + \brief Store-Release Exclusive (8 bit) + \details Executes a STLB exclusive instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEXB (uint32_t)__builtin_arm_stlex + + +/** + \brief Store-Release Exclusive (16 bit) + \details Executes a STLH exclusive instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEXH (uint32_t)__builtin_arm_stlex + + +/** + \brief Store-Release Exclusive (32 bit) + \details Executes a STL exclusive instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEX (uint32_t)__builtin_arm_stlex + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing special-purpose register PRIMASK. + Can only be executed in Privileged modes. + */ +#ifndef __ARM_COMPAT_H +__STATIC_FORCEINLINE void __enable_irq(void) +{ + __ASM volatile ("cpsie i" : : : "memory"); +} +#endif + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting special-purpose register PRIMASK. + Can only be executed in Privileged modes. + */ +#ifndef __ARM_COMPAT_H +__STATIC_FORCEINLINE void __disable_irq(void) +{ + __ASM volatile ("cpsid i" : : : "memory"); +} +#endif + + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CONTROL(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Control Register (non-secure) + \details Returns the content of the non-secure Control Register when in secure mode. + \return non-secure Control Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) +{ + __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); + __ISB(); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Control Register (non-secure) + \details Writes the given value to the non-secure Control Register when in secure state. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) +{ + __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); + __ISB(); +} +#endif + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_IPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_APSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_xPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer (non-secure) + \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state. + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state. + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); +} +#endif + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer (non-secure) + \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state. + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); +} +#endif + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Stack Pointer (non-secure) + \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state. + \return SP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, sp_ns" : "=r" (result) ); + return(result); +} + + +/** + \brief Set Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state. + \param [in] topOfStack Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack) +{ + __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : ); +} +#endif + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Priority Mask (non-secure) + \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Priority Mask (non-secure) + \details Assigns the given value to the non-secure Priority Mask Register when in secure state. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) +{ + __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); +} +#endif + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing special-purpose register FAULTMASK. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __enable_fault_irq(void) +{ + __ASM volatile ("cpsie f" : : : "memory"); +} + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting special-purpose register FAULTMASK. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __disable_fault_irq(void) +{ + __ASM volatile ("cpsid f" : : : "memory"); +} + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Base Priority (non-secure) + \details Returns the current value of the non-secure Base Priority register when in secure state. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri) +{ + __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Base Priority (non-secure) + \details Assigns the given value to the non-secure Base Priority register when in secure state. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); +} +#endif + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Fault Mask (non-secure) + \details Returns the current value of the non-secure Fault Mask register when in secure state. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Fault Mask (non-secure) + \details Assigns the given value to the non-secure Fault Mask register when in secure state. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); +} +#endif + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) + +/** + \brief Get Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void) +{ +#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim" : "=r" (result) ); + return result; +#endif +} + +#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) +{ +#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) ) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) +{ +#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) +{ +#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) ) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); +#endif +} +#endif + + +/** + \brief Get Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void) +{ +#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim" : "=r" (result) ); + return result; +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state. + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void) +{ +#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) ) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). + \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) +{ +#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state. + \param [in] MainStackPtrLimit Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) +{ +#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) ) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); +#endif +} +#endif + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) */ + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#define __get_FPSCR (uint32_t)__builtin_arm_get_fpscr +#else +#define __get_FPSCR() ((uint32_t)0U) +#endif + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#define __set_FPSCR __builtin_arm_set_fpscr +#else +#define __set_FPSCR(x) ((void)(x)) +#endif + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) + +#define __SADD8 __builtin_arm_sadd8 +#define __QADD8 __builtin_arm_qadd8 +#define __SHADD8 __builtin_arm_shadd8 +#define __UADD8 __builtin_arm_uadd8 +#define __UQADD8 __builtin_arm_uqadd8 +#define __UHADD8 __builtin_arm_uhadd8 +#define __SSUB8 __builtin_arm_ssub8 +#define __QSUB8 __builtin_arm_qsub8 +#define __SHSUB8 __builtin_arm_shsub8 +#define __USUB8 __builtin_arm_usub8 +#define __UQSUB8 __builtin_arm_uqsub8 +#define __UHSUB8 __builtin_arm_uhsub8 +#define __SADD16 __builtin_arm_sadd16 +#define __QADD16 __builtin_arm_qadd16 +#define __SHADD16 __builtin_arm_shadd16 +#define __UADD16 __builtin_arm_uadd16 +#define __UQADD16 __builtin_arm_uqadd16 +#define __UHADD16 __builtin_arm_uhadd16 +#define __SSUB16 __builtin_arm_ssub16 +#define __QSUB16 __builtin_arm_qsub16 +#define __SHSUB16 __builtin_arm_shsub16 +#define __USUB16 __builtin_arm_usub16 +#define __UQSUB16 __builtin_arm_uqsub16 +#define __UHSUB16 __builtin_arm_uhsub16 +#define __SASX __builtin_arm_sasx +#define __QASX __builtin_arm_qasx +#define __SHASX __builtin_arm_shasx +#define __UASX __builtin_arm_uasx +#define __UQASX __builtin_arm_uqasx +#define __UHASX __builtin_arm_uhasx +#define __SSAX __builtin_arm_ssax +#define __QSAX __builtin_arm_qsax +#define __SHSAX __builtin_arm_shsax +#define __USAX __builtin_arm_usax +#define __UQSAX __builtin_arm_uqsax +#define __UHSAX __builtin_arm_uhsax +#define __USAD8 __builtin_arm_usad8 +#define __USADA8 __builtin_arm_usada8 +#define __SSAT16 __builtin_arm_ssat16 +#define __USAT16 __builtin_arm_usat16 +#define __UXTB16 __builtin_arm_uxtb16 +#define __UXTAB16 __builtin_arm_uxtab16 +#define __SXTB16 __builtin_arm_sxtb16 +#define __SXTAB16 __builtin_arm_sxtab16 +#define __SMUAD __builtin_arm_smuad +#define __SMUADX __builtin_arm_smuadx +#define __SMLAD __builtin_arm_smlad +#define __SMLADX __builtin_arm_smladx +#define __SMLALD __builtin_arm_smlald +#define __SMLALDX __builtin_arm_smlaldx +#define __SMUSD __builtin_arm_smusd +#define __SMUSDX __builtin_arm_smusdx +#define __SMLSD __builtin_arm_smlsd +#define __SMLSDX __builtin_arm_smlsdx +#define __SMLSLD __builtin_arm_smlsld +#define __SMLSLDX __builtin_arm_smlsldx +#define __SEL __builtin_arm_sel +#define __QADD __builtin_arm_qadd +#define __QSUB __builtin_arm_qsub + +#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ + ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) + +#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ + ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) + +#define __SXTB16_RORn(ARG1, ARG2) __SXTB16(__ROR(ARG1, ARG2)) + +#define __SXTAB16_RORn(ARG1, ARG2, ARG3) __SXTAB16(ARG1, __ROR(ARG2, ARG3)) + +__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) +{ + int32_t result; + + __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#endif /* (__ARM_FEATURE_DSP == 1) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#endif /* __CMSIS_ARMCLANG_H */ diff --git a/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/CMSIS/Core/Include/cmsis_armclang_ltm.h b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/CMSIS/Core/Include/cmsis_armclang_ltm.h new file mode 100644 index 0000000000..1e255d5907 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/CMSIS/Core/Include/cmsis_armclang_ltm.h @@ -0,0 +1,1928 @@ +/**************************************************************************//** + * @file cmsis_armclang_ltm.h + * @brief CMSIS compiler armclang (Arm Compiler 6) header file + * @version V1.5.3 + * @date 27. May 2021 + ******************************************************************************/ +/* + * Copyright (c) 2018-2021 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/*lint -esym(9058, IRQn)*/ /* disable MISRA 2012 Rule 2.4 for IRQn */ + +#ifndef __CMSIS_ARMCLANG_H +#define __CMSIS_ARMCLANG_H + +#pragma clang system_header /* treat file as system include file */ + +/* CMSIS compiler specific defines */ +#ifndef __ASM + #define __ASM __asm +#endif +#ifndef __INLINE + #define __INLINE __inline +#endif +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static __inline +#endif +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __attribute__((always_inline)) static __inline +#endif +#ifndef __NO_RETURN + #define __NO_RETURN __attribute__((__noreturn__)) +#endif +#ifndef __USED + #define __USED __attribute__((used)) +#endif +#ifndef __WEAK + #define __WEAK __attribute__((weak)) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_UNION + #define __PACKED_UNION union __attribute__((packed, aligned(1))) +#endif +#ifndef __UNALIGNED_UINT32 /* deprecated */ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32 */ + struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) +#endif +#ifndef __UNALIGNED_UINT16_WRITE + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT16_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_WRITE */ + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT16_READ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT16_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_READ */ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) +#endif +#ifndef __UNALIGNED_UINT32_WRITE + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_WRITE */ + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT32_READ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_READ */ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) +#endif +#ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __RESTRICT + #define __RESTRICT __restrict +#endif +#ifndef __COMPILER_BARRIER + #define __COMPILER_BARRIER() __ASM volatile("":::"memory") +#endif + +/* ######################### Startup and Lowlevel Init ######################## */ + +#ifndef __PROGRAM_START +#define __PROGRAM_START __main +#endif + +#ifndef __INITIAL_SP +#define __INITIAL_SP Image$$ARM_LIB_STACK$$ZI$$Limit +#endif + +#ifndef __STACK_LIMIT +#define __STACK_LIMIT Image$$ARM_LIB_STACK$$ZI$$Base +#endif + +#ifndef __VECTOR_TABLE +#define __VECTOR_TABLE __Vectors +#endif + +#ifndef __VECTOR_TABLE_ATTRIBUTE +#define __VECTOR_TABLE_ATTRIBUTE __attribute__((used, section("RESET"))) +#endif + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +#ifndef __STACK_SEAL +#define __STACK_SEAL Image$$STACKSEAL$$ZI$$Base +#endif + +#ifndef __TZ_STACK_SEAL_SIZE +#define __TZ_STACK_SEAL_SIZE 8U +#endif + +#ifndef __TZ_STACK_SEAL_VALUE +#define __TZ_STACK_SEAL_VALUE 0xFEF5EDA5FEF5EDA5ULL +#endif + + +__STATIC_FORCEINLINE void __TZ_set_STACKSEAL_S (uint32_t* stackTop) { + *((uint64_t *)stackTop) = __TZ_STACK_SEAL_VALUE; +} +#endif + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/* Define macros for porting to both thumb1 and thumb2. + * For thumb1, use low register (r0-r7), specified by constraint "l" + * Otherwise, use general registers, specified by constraint "r" */ +#if defined (__thumb__) && !defined (__thumb2__) +#define __CMSIS_GCC_OUT_REG(r) "=l" (r) +#define __CMSIS_GCC_USE_REG(r) "l" (r) +#else +#define __CMSIS_GCC_OUT_REG(r) "=r" (r) +#define __CMSIS_GCC_USE_REG(r) "r" (r) +#endif + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP __builtin_arm_nop + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +#define __WFI __builtin_arm_wfi + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE __builtin_arm_wfe + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV __builtin_arm_sev + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +#define __ISB() __builtin_arm_isb(0xF) + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +#define __DSB() __builtin_arm_dsb(0xF) + + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +#define __DMB() __builtin_arm_dmb(0xF) + + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV(value) __builtin_bswap32(value) + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV16(value) __ROR(__REV(value), 16) + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REVSH(value) (int16_t)__builtin_bswap16(value) + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) +{ + op2 %= 32U; + if (op2 == 0U) + { + return op1; + } + return (op1 >> op2) | (op1 << (32U - op2)); +} + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __ASM volatile ("bkpt "#value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +#define __RBIT __builtin_arm_rbit + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +__STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value) +{ + /* Even though __builtin_clz produces a CLZ instruction on ARM, formally + __builtin_clz(0) is undefined behaviour, so handle this case specially. + This guarantees ARM-compatible results if happening to compile on a non-ARM + target, and ensures the compiler doesn't decide to activate any + optimisations using the logic "value was passed to __builtin_clz, so it + is non-zero". + ARM Compiler 6.10 and possibly earlier will optimise this test away, leaving a + single CLZ instruction. + */ + if (value == 0U) + { + return 32U; + } + return __builtin_clz(value); +} + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDREXB (uint8_t)__builtin_arm_ldrex + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDREXH (uint16_t)__builtin_arm_ldrex + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDREXW (uint32_t)__builtin_arm_ldrex + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXB (uint32_t)__builtin_arm_strex + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXH (uint32_t)__builtin_arm_strex + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXW (uint32_t)__builtin_arm_strex + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +#define __CLREX __builtin_arm_clrex + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT __builtin_arm_ssat + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT __builtin_arm_usat + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) ); +} + +#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat) +{ + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; +} + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat) +{ + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief Load-Acquire (8 bit) + \details Executes a LDAB instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return ((uint8_t) result); +} + + +/** + \brief Load-Acquire (16 bit) + \details Executes a LDAH instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return ((uint16_t) result); +} + + +/** + \brief Load-Acquire (32 bit) + \details Executes a LDA instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return(result); +} + + +/** + \brief Store-Release (8 bit) + \details Executes a STLB instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Store-Release (16 bit) + \details Executes a STLH instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Store-Release (32 bit) + \details Executes a STL instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Load-Acquire Exclusive (8 bit) + \details Executes a LDAB exclusive instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDAEXB (uint8_t)__builtin_arm_ldaex + + +/** + \brief Load-Acquire Exclusive (16 bit) + \details Executes a LDAH exclusive instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDAEXH (uint16_t)__builtin_arm_ldaex + + +/** + \brief Load-Acquire Exclusive (32 bit) + \details Executes a LDA exclusive instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDAEX (uint32_t)__builtin_arm_ldaex + + +/** + \brief Store-Release Exclusive (8 bit) + \details Executes a STLB exclusive instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEXB (uint32_t)__builtin_arm_stlex + + +/** + \brief Store-Release Exclusive (16 bit) + \details Executes a STLH exclusive instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEXH (uint32_t)__builtin_arm_stlex + + +/** + \brief Store-Release Exclusive (32 bit) + \details Executes a STL exclusive instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEX (uint32_t)__builtin_arm_stlex + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing special-purpose register PRIMASK. + Can only be executed in Privileged modes. + */ +#ifndef __ARM_COMPAT_H +__STATIC_FORCEINLINE void __enable_irq(void) +{ + __ASM volatile ("cpsie i" : : : "memory"); +} +#endif + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting special-purpose register PRIMASK. + Can only be executed in Privileged modes. + */ +#ifndef __ARM_COMPAT_H +__STATIC_FORCEINLINE void __disable_irq(void) +{ + __ASM volatile ("cpsid i" : : : "memory"); +} +#endif + + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CONTROL(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Control Register (non-secure) + \details Returns the content of the non-secure Control Register when in secure mode. + \return non-secure Control Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) +{ + __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); + __ISB(); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Control Register (non-secure) + \details Writes the given value to the non-secure Control Register when in secure state. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) +{ + __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); + __ISB(); +} +#endif + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_IPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_APSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_xPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer (non-secure) + \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state. + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state. + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); +} +#endif + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer (non-secure) + \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state. + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); +} +#endif + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Stack Pointer (non-secure) + \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state. + \return SP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, sp_ns" : "=r" (result) ); + return(result); +} + + +/** + \brief Set Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state. + \param [in] topOfStack Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack) +{ + __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : ); +} +#endif + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Priority Mask (non-secure) + \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Priority Mask (non-secure) + \details Assigns the given value to the non-secure Priority Mask Register when in secure state. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) +{ + __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); +} +#endif + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing special-purpose register FAULTMASK. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __enable_fault_irq(void) +{ + __ASM volatile ("cpsie f" : : : "memory"); +} + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting special-purpose register FAULTMASK. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __disable_fault_irq(void) +{ + __ASM volatile ("cpsid f" : : : "memory"); +} + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Base Priority (non-secure) + \details Returns the current value of the non-secure Base Priority register when in secure state. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri) +{ + __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Base Priority (non-secure) + \details Assigns the given value to the non-secure Base Priority register when in secure state. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); +} +#endif + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Fault Mask (non-secure) + \details Returns the current value of the non-secure Fault Mask register when in secure state. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Fault Mask (non-secure) + \details Assigns the given value to the non-secure Fault Mask register when in secure state. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); +} +#endif + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + +/** + \brief Get Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim" : "=r" (result) ); + return result; +#endif +} + +#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); +#endif +} +#endif + + +/** + \brief Get Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim" : "=r" (result) ); + return result; +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state. + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). + \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state. + \param [in] MainStackPtrLimit Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); +#endif +} +#endif + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#define __get_FPSCR (uint32_t)__builtin_arm_get_fpscr +#else +#define __get_FPSCR() ((uint32_t)0U) +#endif + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#define __set_FPSCR __builtin_arm_set_fpscr +#else +#define __set_FPSCR(x) ((void)(x)) +#endif + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) + +__STATIC_FORCEINLINE uint32_t __SADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__STATIC_FORCEINLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__STATIC_FORCEINLINE uint32_t __SADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USAD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#define __SSAT16(ARG1,ARG2) \ +({ \ + int32_t __RES, __ARG1 = (ARG1); \ + __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +#define __USAT16(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +__STATIC_FORCEINLINE uint32_t __UXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint32_t __SEL (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE int32_t __QADD( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE int32_t __QSUB( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ + ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) + +#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ + ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) + +#define __SXTB16_RORn(ARG1, ARG2) __SXTB16(__ROR(ARG1, ARG2)) + +#define __SXTAB16_RORn(ARG1, ARG2, ARG3) __SXTAB16(ARG1, __ROR(ARG2, ARG3)) + +__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) +{ + int32_t result; + + __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#endif /* (__ARM_FEATURE_DSP == 1) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#endif /* __CMSIS_ARMCLANG_H */ diff --git a/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/CMSIS/Core/Include/cmsis_compiler.h b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/CMSIS/Core/Include/cmsis_compiler.h new file mode 100644 index 0000000000..adbf296f15 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/CMSIS/Core/Include/cmsis_compiler.h @@ -0,0 +1,283 @@ +/**************************************************************************//** + * @file cmsis_compiler.h + * @brief CMSIS compiler generic header file + * @version V5.1.0 + * @date 09. October 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_COMPILER_H +#define __CMSIS_COMPILER_H + +#include + +/* + * Arm Compiler 4/5 + */ +#if defined ( __CC_ARM ) + #include "cmsis_armcc.h" + + +/* + * Arm Compiler 6.6 LTM (armclang) + */ +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) && (__ARMCC_VERSION < 6100100) + #include "cmsis_armclang_ltm.h" + + /* + * Arm Compiler above 6.10.1 (armclang) + */ +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6100100) + #include "cmsis_armclang.h" + + +/* + * GNU Compiler + */ +#elif defined ( __GNUC__ ) + #include "cmsis_gcc.h" + + +/* + * IAR Compiler + */ +#elif defined ( __ICCARM__ ) + #include + + +/* + * TI Arm Compiler + */ +#elif defined ( __TI_ARM__ ) + #include + + #ifndef __ASM + #define __ASM __asm + #endif + #ifndef __INLINE + #define __INLINE inline + #endif + #ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline + #endif + #ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __STATIC_INLINE + #endif + #ifndef __NO_RETURN + #define __NO_RETURN __attribute__((noreturn)) + #endif + #ifndef __USED + #define __USED __attribute__((used)) + #endif + #ifndef __WEAK + #define __WEAK __attribute__((weak)) + #endif + #ifndef __PACKED + #define __PACKED __attribute__((packed)) + #endif + #ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed)) + #endif + #ifndef __PACKED_UNION + #define __PACKED_UNION union __attribute__((packed)) + #endif + #ifndef __UNALIGNED_UINT32 /* deprecated */ + struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + #endif + #ifndef __UNALIGNED_UINT16_WRITE + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void*)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT16_READ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) + #endif + #ifndef __UNALIGNED_UINT32_WRITE + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT32_READ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) + #endif + #ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) + #endif + #ifndef __RESTRICT + #define __RESTRICT __restrict + #endif + #ifndef __COMPILER_BARRIER + #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored. + #define __COMPILER_BARRIER() (void)0 + #endif + + +/* + * TASKING Compiler + */ +#elif defined ( __TASKING__ ) + /* + * The CMSIS functions have been implemented as intrinsics in the compiler. + * Please use "carm -?i" to get an up to date list of all intrinsics, + * Including the CMSIS ones. + */ + + #ifndef __ASM + #define __ASM __asm + #endif + #ifndef __INLINE + #define __INLINE inline + #endif + #ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline + #endif + #ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __STATIC_INLINE + #endif + #ifndef __NO_RETURN + #define __NO_RETURN __attribute__((noreturn)) + #endif + #ifndef __USED + #define __USED __attribute__((used)) + #endif + #ifndef __WEAK + #define __WEAK __attribute__((weak)) + #endif + #ifndef __PACKED + #define __PACKED __packed__ + #endif + #ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __packed__ + #endif + #ifndef __PACKED_UNION + #define __PACKED_UNION union __packed__ + #endif + #ifndef __UNALIGNED_UINT32 /* deprecated */ + struct __packed__ T_UINT32 { uint32_t v; }; + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + #endif + #ifndef __UNALIGNED_UINT16_WRITE + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT16_READ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) + #endif + #ifndef __UNALIGNED_UINT32_WRITE + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT32_READ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) + #endif + #ifndef __ALIGNED + #define __ALIGNED(x) __align(x) + #endif + #ifndef __RESTRICT + #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. + #define __RESTRICT + #endif + #ifndef __COMPILER_BARRIER + #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored. + #define __COMPILER_BARRIER() (void)0 + #endif + + +/* + * COSMIC Compiler + */ +#elif defined ( __CSMC__ ) + #include + + #ifndef __ASM + #define __ASM _asm + #endif + #ifndef __INLINE + #define __INLINE inline + #endif + #ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline + #endif + #ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __STATIC_INLINE + #endif + #ifndef __NO_RETURN + // NO RETURN is automatically detected hence no warning here + #define __NO_RETURN + #endif + #ifndef __USED + #warning No compiler specific solution for __USED. __USED is ignored. + #define __USED + #endif + #ifndef __WEAK + #define __WEAK __weak + #endif + #ifndef __PACKED + #define __PACKED @packed + #endif + #ifndef __PACKED_STRUCT + #define __PACKED_STRUCT @packed struct + #endif + #ifndef __PACKED_UNION + #define __PACKED_UNION @packed union + #endif + #ifndef __UNALIGNED_UINT32 /* deprecated */ + @packed struct T_UINT32 { uint32_t v; }; + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + #endif + #ifndef __UNALIGNED_UINT16_WRITE + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT16_READ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) + #endif + #ifndef __UNALIGNED_UINT32_WRITE + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT32_READ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) + #endif + #ifndef __ALIGNED + #warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored. + #define __ALIGNED(x) + #endif + #ifndef __RESTRICT + #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. + #define __RESTRICT + #endif + #ifndef __COMPILER_BARRIER + #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored. + #define __COMPILER_BARRIER() (void)0 + #endif + + +#else + #error Unknown compiler. +#endif + + +#endif /* __CMSIS_COMPILER_H */ + diff --git a/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/CMSIS/Core/Include/cmsis_gcc.h b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/CMSIS/Core/Include/cmsis_gcc.h new file mode 100644 index 0000000000..67bda4ef3c --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/CMSIS/Core/Include/cmsis_gcc.h @@ -0,0 +1,2211 @@ +/**************************************************************************//** + * @file cmsis_gcc.h + * @brief CMSIS compiler GCC header file + * @version V5.4.1 + * @date 27. May 2021 + ******************************************************************************/ +/* + * Copyright (c) 2009-2021 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_GCC_H +#define __CMSIS_GCC_H + +/* ignore some GCC warnings */ +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wsign-conversion" +#pragma GCC diagnostic ignored "-Wconversion" +#pragma GCC diagnostic ignored "-Wunused-parameter" + +/* Fallback for __has_builtin */ +#ifndef __has_builtin + #define __has_builtin(x) (0) +#endif + +/* CMSIS compiler specific defines */ +#ifndef __ASM + #define __ASM __asm +#endif +#ifndef __INLINE + #define __INLINE inline +#endif +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline +#endif +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __attribute__((always_inline)) static inline +#endif +#ifndef __NO_RETURN + #define __NO_RETURN __attribute__((__noreturn__)) +#endif +#ifndef __USED + #define __USED __attribute__((used)) +#endif +#ifndef __WEAK + #define __WEAK __attribute__((weak)) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_UNION + #define __PACKED_UNION union __attribute__((packed, aligned(1))) +#endif +#ifndef __UNALIGNED_UINT32 /* deprecated */ + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) +#endif +#ifndef __UNALIGNED_UINT16_WRITE + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT16_READ + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) +#endif +#ifndef __UNALIGNED_UINT32_WRITE + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT32_READ + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) +#endif +#ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __RESTRICT + #define __RESTRICT __restrict +#endif +#ifndef __COMPILER_BARRIER + #define __COMPILER_BARRIER() __ASM volatile("":::"memory") +#endif + +/* ######################### Startup and Lowlevel Init ######################## */ + +#ifndef __PROGRAM_START + +/** + \brief Initializes data and bss sections + \details This default implementations initialized all data and additional bss + sections relying on .copy.table and .zero.table specified properly + in the used linker script. + + */ +__STATIC_FORCEINLINE __NO_RETURN void __cmsis_start(void) +{ + extern void _start(void) __NO_RETURN; + + typedef struct { + uint32_t const* src; + uint32_t* dest; + uint32_t wlen; + } __copy_table_t; + + typedef struct { + uint32_t* dest; + uint32_t wlen; + } __zero_table_t; + + extern const __copy_table_t __copy_table_start__; + extern const __copy_table_t __copy_table_end__; + extern const __zero_table_t __zero_table_start__; + extern const __zero_table_t __zero_table_end__; + + for (__copy_table_t const* pTable = &__copy_table_start__; pTable < &__copy_table_end__; ++pTable) { + for(uint32_t i=0u; iwlen; ++i) { + pTable->dest[i] = pTable->src[i]; + } + } + + for (__zero_table_t const* pTable = &__zero_table_start__; pTable < &__zero_table_end__; ++pTable) { + for(uint32_t i=0u; iwlen; ++i) { + pTable->dest[i] = 0u; + } + } + + _start(); +} + +#define __PROGRAM_START __cmsis_start +#endif + +#ifndef __INITIAL_SP +#define __INITIAL_SP __StackTop +#endif + +#ifndef __STACK_LIMIT +#define __STACK_LIMIT __StackLimit +#endif + +#ifndef __VECTOR_TABLE +#define __VECTOR_TABLE __Vectors +#endif + +#ifndef __VECTOR_TABLE_ATTRIBUTE +#define __VECTOR_TABLE_ATTRIBUTE __attribute__((used, section(".vectors"))) +#endif + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +#ifndef __STACK_SEAL +#define __STACK_SEAL __StackSeal +#endif + +#ifndef __TZ_STACK_SEAL_SIZE +#define __TZ_STACK_SEAL_SIZE 8U +#endif + +#ifndef __TZ_STACK_SEAL_VALUE +#define __TZ_STACK_SEAL_VALUE 0xFEF5EDA5FEF5EDA5ULL +#endif + + +__STATIC_FORCEINLINE void __TZ_set_STACKSEAL_S (uint32_t* stackTop) { + *((uint64_t *)stackTop) = __TZ_STACK_SEAL_VALUE; +} +#endif + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/* Define macros for porting to both thumb1 and thumb2. + * For thumb1, use low register (r0-r7), specified by constraint "l" + * Otherwise, use general registers, specified by constraint "r" */ +#if defined (__thumb__) && !defined (__thumb2__) +#define __CMSIS_GCC_OUT_REG(r) "=l" (r) +#define __CMSIS_GCC_RW_REG(r) "+l" (r) +#define __CMSIS_GCC_USE_REG(r) "l" (r) +#else +#define __CMSIS_GCC_OUT_REG(r) "=r" (r) +#define __CMSIS_GCC_RW_REG(r) "+r" (r) +#define __CMSIS_GCC_USE_REG(r) "r" (r) +#endif + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP() __ASM volatile ("nop") + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +#define __WFI() __ASM volatile ("wfi":::"memory") + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE() __ASM volatile ("wfe":::"memory") + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV() __ASM volatile ("sev") + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +__STATIC_FORCEINLINE void __ISB(void) +{ + __ASM volatile ("isb 0xF":::"memory"); +} + + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +__STATIC_FORCEINLINE void __DSB(void) +{ + __ASM volatile ("dsb 0xF":::"memory"); +} + + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +__STATIC_FORCEINLINE void __DMB(void) +{ + __ASM volatile ("dmb 0xF":::"memory"); +} + + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE uint32_t __REV(uint32_t value) +{ +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5) + return __builtin_bswap32(value); +#else + uint32_t result; + + __ASM ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return result; +#endif +} + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE uint32_t __REV16(uint32_t value) +{ + uint32_t result; + + __ASM ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return result; +} + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE int16_t __REVSH(int16_t value) +{ +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + return (int16_t)__builtin_bswap16(value); +#else + int16_t result; + + __ASM ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return result; +#endif +} + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) +{ + op2 %= 32U; + if (op2 == 0U) + { + return op1; + } + return (op1 >> op2) | (op1 << (32U - op2)); +} + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __ASM volatile ("bkpt "#value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE uint32_t __RBIT(uint32_t value) +{ + uint32_t result; + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) + __ASM ("rbit %0, %1" : "=r" (result) : "r" (value) ); +#else + uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */ + + result = value; /* r will be reversed bits of v; first get LSB of v */ + for (value >>= 1U; value != 0U; value >>= 1U) + { + result <<= 1U; + result |= value & 1U; + s--; + } + result <<= s; /* shift when v's highest bits are zero */ +#endif + return result; +} + + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +__STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value) +{ + /* Even though __builtin_clz produces a CLZ instruction on ARM, formally + __builtin_clz(0) is undefined behaviour, so handle this case specially. + This guarantees ARM-compatible results if happening to compile on a non-ARM + target, and ensures the compiler doesn't decide to activate any + optimisations using the logic "value was passed to __builtin_clz, so it + is non-zero". + ARM GCC 7.3 and possibly earlier will optimise this test away, leaving a + single CLZ instruction. + */ + if (value == 0U) + { + return 32U; + } + return __builtin_clz(value); +} + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDREXB(volatile uint8_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDREXH(volatile uint16_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDREXW(volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); + return(result); +} + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr) +{ + uint32_t result; + + __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr) +{ + uint32_t result; + + __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); + return(result); +} + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +__STATIC_FORCEINLINE void __CLREX(void) +{ + __ASM volatile ("clrex" ::: "memory"); +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] ARG1 Value to be saturated + \param [in] ARG2 Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT(ARG1, ARG2) \ +__extension__ \ +({ \ + int32_t __RES, __ARG1 = (ARG1); \ + __ASM volatile ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) : "cc" ); \ + __RES; \ + }) + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] ARG1 Value to be saturated + \param [in] ARG2 Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT(ARG1, ARG2) \ +__extension__ \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM volatile ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) : "cc" ); \ + __RES; \ + }) + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" ); +#endif + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" ); +#endif + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) ); +} + +#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat) +{ + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; +} + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat) +{ + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief Load-Acquire (8 bit) + \details Executes a LDAB instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return ((uint8_t) result); +} + + +/** + \brief Load-Acquire (16 bit) + \details Executes a LDAH instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return ((uint16_t) result); +} + + +/** + \brief Load-Acquire (32 bit) + \details Executes a LDA instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return(result); +} + + +/** + \brief Store-Release (8 bit) + \details Executes a STLB instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Store-Release (16 bit) + \details Executes a STLH instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Store-Release (32 bit) + \details Executes a STL instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Load-Acquire Exclusive (8 bit) + \details Executes a LDAB exclusive instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDAEXB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldaexb %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return ((uint8_t) result); +} + + +/** + \brief Load-Acquire Exclusive (16 bit) + \details Executes a LDAH exclusive instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDAEXH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldaexh %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return ((uint16_t) result); +} + + +/** + \brief Load-Acquire Exclusive (32 bit) + \details Executes a LDA exclusive instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDAEX(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldaex %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return(result); +} + + +/** + \brief Store-Release Exclusive (8 bit) + \details Executes a STLB exclusive instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("stlexb %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); + return(result); +} + + +/** + \brief Store-Release Exclusive (16 bit) + \details Executes a STLH exclusive instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("stlexh %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); + return(result); +} + + +/** + \brief Store-Release Exclusive (32 bit) + \details Executes a STL exclusive instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("stlex %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); + return(result); +} + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing special-purpose register PRIMASK. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __enable_irq(void) +{ + __ASM volatile ("cpsie i" : : : "memory"); +} + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting special-purpose register PRIMASK. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __disable_irq(void) +{ + __ASM volatile ("cpsid i" : : : "memory"); +} + + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CONTROL(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Control Register (non-secure) + \details Returns the content of the non-secure Control Register when in secure mode. + \return non-secure Control Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) +{ + __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); + __ISB(); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Control Register (non-secure) + \details Writes the given value to the non-secure Control Register when in secure state. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) +{ + __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); + __ISB(); +} +#endif + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_IPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_APSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_xPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer (non-secure) + \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state. + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state. + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); +} +#endif + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer (non-secure) + \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state. + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); +} +#endif + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Stack Pointer (non-secure) + \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state. + \return SP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, sp_ns" : "=r" (result) ); + return(result); +} + + +/** + \brief Set Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state. + \param [in] topOfStack Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack) +{ + __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : ); +} +#endif + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Priority Mask (non-secure) + \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Priority Mask (non-secure) + \details Assigns the given value to the non-secure Priority Mask Register when in secure state. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) +{ + __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); +} +#endif + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing special-purpose register FAULTMASK. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __enable_fault_irq(void) +{ + __ASM volatile ("cpsie f" : : : "memory"); +} + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting special-purpose register FAULTMASK. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __disable_fault_irq(void) +{ + __ASM volatile ("cpsid f" : : : "memory"); +} + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Base Priority (non-secure) + \details Returns the current value of the non-secure Base Priority register when in secure state. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri) +{ + __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Base Priority (non-secure) + \details Assigns the given value to the non-secure Base Priority register when in secure state. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); +} +#endif + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Fault Mask (non-secure) + \details Returns the current value of the non-secure Fault Mask register when in secure state. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Fault Mask (non-secure) + \details Assigns the given value to the non-secure Fault Mask register when in secure state. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); +} +#endif + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + +/** + \brief Get Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim" : "=r" (result) ); + return result; +#endif +} + +#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); +#endif +} +#endif + + +/** + \brief Get Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim" : "=r" (result) ); + return result; +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state. + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). + \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state. + \param [in] MainStackPtrLimit Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); +#endif +} +#endif + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +__STATIC_FORCEINLINE uint32_t __get_FPSCR(void) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#if __has_builtin(__builtin_arm_get_fpscr) +// Re-enable using built-in when GCC has been fixed +// || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2) + /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */ + return __builtin_arm_get_fpscr(); +#else + uint32_t result; + + __ASM volatile ("VMRS %0, fpscr" : "=r" (result) ); + return(result); +#endif +#else + return(0U); +#endif +} + + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +__STATIC_FORCEINLINE void __set_FPSCR(uint32_t fpscr) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#if __has_builtin(__builtin_arm_set_fpscr) +// Re-enable using built-in when GCC has been fixed +// || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2) + /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */ + __builtin_arm_set_fpscr(fpscr); +#else + __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc", "memory"); +#endif +#else + (void)fpscr; +#endif +} + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) + +__STATIC_FORCEINLINE uint32_t __SADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__STATIC_FORCEINLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__STATIC_FORCEINLINE uint32_t __SADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USAD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#define __SSAT16(ARG1, ARG2) \ +__extension__ \ +({ \ + int32_t __RES, __ARG1 = (ARG1); \ + __ASM volatile ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) : "cc" ); \ + __RES; \ + }) + +#define __USAT16(ARG1, ARG2) \ +__extension__ \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM volatile ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) : "cc" ); \ + __RES; \ + }) + +__STATIC_FORCEINLINE uint32_t __UXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM ("uxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM ("sxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTB16_RORn(uint32_t op1, uint32_t rotate) +{ + uint32_t result; + if (__builtin_constant_p(rotate) && ((rotate == 8U) || (rotate == 16U) || (rotate == 24U))) { + __ASM volatile ("sxtb16 %0, %1, ROR %2" : "=r" (result) : "r" (op1), "i" (rotate) ); + } else { + result = __SXTB16(__ROR(op1, rotate)) ; + } + return result; +} + +__STATIC_FORCEINLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTAB16_RORn(uint32_t op1, uint32_t op2, uint32_t rotate) +{ + uint32_t result; + if (__builtin_constant_p(rotate) && ((rotate == 8U) || (rotate == 16U) || (rotate == 24U))) { + __ASM volatile ("sxtab16 %0, %1, %2, ROR %3" : "=r" (result) : "r" (op1) , "r" (op2) , "i" (rotate)); + } else { + result = __SXTAB16(op1, __ROR(op2, rotate)); + } + return result; +} + + +__STATIC_FORCEINLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint32_t __SEL (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE int32_t __QADD( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE int32_t __QSUB( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +#define __PKHBT(ARG1,ARG2,ARG3) \ +__extension__ \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) + +#define __PKHTB(ARG1,ARG2,ARG3) \ +__extension__ \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + if (ARG3 == 0) \ + __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \ + else \ + __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) + + +__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) +{ + int32_t result; + + __ASM ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#endif /* (__ARM_FEATURE_DSP == 1) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#pragma GCC diagnostic pop + +#endif /* __CMSIS_GCC_H */ diff --git a/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/CMSIS/Core/Include/cmsis_iccarm.h b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/CMSIS/Core/Include/cmsis_iccarm.h new file mode 100644 index 0000000000..65b824b009 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/CMSIS/Core/Include/cmsis_iccarm.h @@ -0,0 +1,1002 @@ +/**************************************************************************//** + * @file cmsis_iccarm.h + * @brief CMSIS compiler ICCARM (IAR Compiler for Arm) header file + * @version V5.3.0 + * @date 14. April 2021 + ******************************************************************************/ + +//------------------------------------------------------------------------------ +// +// Copyright (c) 2017-2021 IAR Systems +// Copyright (c) 2017-2021 Arm Limited. All rights reserved. +// +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License") +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +//------------------------------------------------------------------------------ + + +#ifndef __CMSIS_ICCARM_H__ +#define __CMSIS_ICCARM_H__ + +#ifndef __ICCARM__ + #error This file should only be compiled by ICCARM +#endif + +#pragma system_include + +#define __IAR_FT _Pragma("inline=forced") __intrinsic + +#if (__VER__ >= 8000000) + #define __ICCARM_V8 1 +#else + #define __ICCARM_V8 0 +#endif + +#ifndef __ALIGNED + #if __ICCARM_V8 + #define __ALIGNED(x) __attribute__((aligned(x))) + #elif (__VER__ >= 7080000) + /* Needs IAR language extensions */ + #define __ALIGNED(x) __attribute__((aligned(x))) + #else + #warning No compiler specific solution for __ALIGNED.__ALIGNED is ignored. + #define __ALIGNED(x) + #endif +#endif + + +/* Define compiler macros for CPU architecture, used in CMSIS 5. + */ +#if __ARM_ARCH_6M__ || __ARM_ARCH_7M__ || __ARM_ARCH_7EM__ || __ARM_ARCH_8M_BASE__ || __ARM_ARCH_8M_MAIN__ +/* Macros already defined */ +#else + #if defined(__ARM8M_MAINLINE__) || defined(__ARM8EM_MAINLINE__) + #define __ARM_ARCH_8M_MAIN__ 1 + #elif defined(__ARM8M_BASELINE__) + #define __ARM_ARCH_8M_BASE__ 1 + #elif defined(__ARM_ARCH_PROFILE) && __ARM_ARCH_PROFILE == 'M' + #if __ARM_ARCH == 6 + #define __ARM_ARCH_6M__ 1 + #elif __ARM_ARCH == 7 + #if __ARM_FEATURE_DSP + #define __ARM_ARCH_7EM__ 1 + #else + #define __ARM_ARCH_7M__ 1 + #endif + #endif /* __ARM_ARCH */ + #endif /* __ARM_ARCH_PROFILE == 'M' */ +#endif + +/* Alternativ core deduction for older ICCARM's */ +#if !defined(__ARM_ARCH_6M__) && !defined(__ARM_ARCH_7M__) && !defined(__ARM_ARCH_7EM__) && \ + !defined(__ARM_ARCH_8M_BASE__) && !defined(__ARM_ARCH_8M_MAIN__) + #if defined(__ARM6M__) && (__CORE__ == __ARM6M__) + #define __ARM_ARCH_6M__ 1 + #elif defined(__ARM7M__) && (__CORE__ == __ARM7M__) + #define __ARM_ARCH_7M__ 1 + #elif defined(__ARM7EM__) && (__CORE__ == __ARM7EM__) + #define __ARM_ARCH_7EM__ 1 + #elif defined(__ARM8M_BASELINE__) && (__CORE == __ARM8M_BASELINE__) + #define __ARM_ARCH_8M_BASE__ 1 + #elif defined(__ARM8M_MAINLINE__) && (__CORE == __ARM8M_MAINLINE__) + #define __ARM_ARCH_8M_MAIN__ 1 + #elif defined(__ARM8EM_MAINLINE__) && (__CORE == __ARM8EM_MAINLINE__) + #define __ARM_ARCH_8M_MAIN__ 1 + #else + #error "Unknown target." + #endif +#endif + + + +#if defined(__ARM_ARCH_6M__) && __ARM_ARCH_6M__==1 + #define __IAR_M0_FAMILY 1 +#elif defined(__ARM_ARCH_8M_BASE__) && __ARM_ARCH_8M_BASE__==1 + #define __IAR_M0_FAMILY 1 +#else + #define __IAR_M0_FAMILY 0 +#endif + + +#ifndef __ASM + #define __ASM __asm +#endif + +#ifndef __COMPILER_BARRIER + #define __COMPILER_BARRIER() __ASM volatile("":::"memory") +#endif + +#ifndef __INLINE + #define __INLINE inline +#endif + +#ifndef __NO_RETURN + #if __ICCARM_V8 + #define __NO_RETURN __attribute__((__noreturn__)) + #else + #define __NO_RETURN _Pragma("object_attribute=__noreturn") + #endif +#endif + +#ifndef __PACKED + #if __ICCARM_V8 + #define __PACKED __attribute__((packed, aligned(1))) + #else + /* Needs IAR language extensions */ + #define __PACKED __packed + #endif +#endif + +#ifndef __PACKED_STRUCT + #if __ICCARM_V8 + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) + #else + /* Needs IAR language extensions */ + #define __PACKED_STRUCT __packed struct + #endif +#endif + +#ifndef __PACKED_UNION + #if __ICCARM_V8 + #define __PACKED_UNION union __attribute__((packed, aligned(1))) + #else + /* Needs IAR language extensions */ + #define __PACKED_UNION __packed union + #endif +#endif + +#ifndef __RESTRICT + #if __ICCARM_V8 + #define __RESTRICT __restrict + #else + /* Needs IAR language extensions */ + #define __RESTRICT restrict + #endif +#endif + +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline +#endif + +#ifndef __FORCEINLINE + #define __FORCEINLINE _Pragma("inline=forced") +#endif + +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __FORCEINLINE __STATIC_INLINE +#endif + +#ifndef __UNALIGNED_UINT16_READ +#pragma language=save +#pragma language=extended +__IAR_FT uint16_t __iar_uint16_read(void const *ptr) +{ + return *(__packed uint16_t*)(ptr); +} +#pragma language=restore +#define __UNALIGNED_UINT16_READ(PTR) __iar_uint16_read(PTR) +#endif + + +#ifndef __UNALIGNED_UINT16_WRITE +#pragma language=save +#pragma language=extended +__IAR_FT void __iar_uint16_write(void const *ptr, uint16_t val) +{ + *(__packed uint16_t*)(ptr) = val;; +} +#pragma language=restore +#define __UNALIGNED_UINT16_WRITE(PTR,VAL) __iar_uint16_write(PTR,VAL) +#endif + +#ifndef __UNALIGNED_UINT32_READ +#pragma language=save +#pragma language=extended +__IAR_FT uint32_t __iar_uint32_read(void const *ptr) +{ + return *(__packed uint32_t*)(ptr); +} +#pragma language=restore +#define __UNALIGNED_UINT32_READ(PTR) __iar_uint32_read(PTR) +#endif + +#ifndef __UNALIGNED_UINT32_WRITE +#pragma language=save +#pragma language=extended +__IAR_FT void __iar_uint32_write(void const *ptr, uint32_t val) +{ + *(__packed uint32_t*)(ptr) = val;; +} +#pragma language=restore +#define __UNALIGNED_UINT32_WRITE(PTR,VAL) __iar_uint32_write(PTR,VAL) +#endif + +#ifndef __UNALIGNED_UINT32 /* deprecated */ +#pragma language=save +#pragma language=extended +__packed struct __iar_u32 { uint32_t v; }; +#pragma language=restore +#define __UNALIGNED_UINT32(PTR) (((struct __iar_u32 *)(PTR))->v) +#endif + +#ifndef __USED + #if __ICCARM_V8 + #define __USED __attribute__((used)) + #else + #define __USED _Pragma("__root") + #endif +#endif + +#undef __WEAK /* undo the definition from DLib_Defaults.h */ +#ifndef __WEAK + #if __ICCARM_V8 + #define __WEAK __attribute__((weak)) + #else + #define __WEAK _Pragma("__weak") + #endif +#endif + +#ifndef __PROGRAM_START +#define __PROGRAM_START __iar_program_start +#endif + +#ifndef __INITIAL_SP +#define __INITIAL_SP CSTACK$$Limit +#endif + +#ifndef __STACK_LIMIT +#define __STACK_LIMIT CSTACK$$Base +#endif + +#ifndef __VECTOR_TABLE +#define __VECTOR_TABLE __vector_table +#endif + +#ifndef __VECTOR_TABLE_ATTRIBUTE +#define __VECTOR_TABLE_ATTRIBUTE @".intvec" +#endif + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +#ifndef __STACK_SEAL +#define __STACK_SEAL STACKSEAL$$Base +#endif + +#ifndef __TZ_STACK_SEAL_SIZE +#define __TZ_STACK_SEAL_SIZE 8U +#endif + +#ifndef __TZ_STACK_SEAL_VALUE +#define __TZ_STACK_SEAL_VALUE 0xFEF5EDA5FEF5EDA5ULL +#endif + +__STATIC_FORCEINLINE void __TZ_set_STACKSEAL_S (uint32_t* stackTop) { + *((uint64_t *)stackTop) = __TZ_STACK_SEAL_VALUE; +} +#endif + +#ifndef __ICCARM_INTRINSICS_VERSION__ + #define __ICCARM_INTRINSICS_VERSION__ 0 +#endif + +#if __ICCARM_INTRINSICS_VERSION__ == 2 + + #if defined(__CLZ) + #undef __CLZ + #endif + #if defined(__REVSH) + #undef __REVSH + #endif + #if defined(__RBIT) + #undef __RBIT + #endif + #if defined(__SSAT) + #undef __SSAT + #endif + #if defined(__USAT) + #undef __USAT + #endif + + #include "iccarm_builtin.h" + + #define __disable_fault_irq __iar_builtin_disable_fiq + #define __disable_irq __iar_builtin_disable_interrupt + #define __enable_fault_irq __iar_builtin_enable_fiq + #define __enable_irq __iar_builtin_enable_interrupt + #define __arm_rsr __iar_builtin_rsr + #define __arm_wsr __iar_builtin_wsr + + + #define __get_APSR() (__arm_rsr("APSR")) + #define __get_BASEPRI() (__arm_rsr("BASEPRI")) + #define __get_CONTROL() (__arm_rsr("CONTROL")) + #define __get_FAULTMASK() (__arm_rsr("FAULTMASK")) + + #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) + #define __get_FPSCR() (__arm_rsr("FPSCR")) + #define __set_FPSCR(VALUE) (__arm_wsr("FPSCR", (VALUE))) + #else + #define __get_FPSCR() ( 0 ) + #define __set_FPSCR(VALUE) ((void)VALUE) + #endif + + #define __get_IPSR() (__arm_rsr("IPSR")) + #define __get_MSP() (__arm_rsr("MSP")) + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + #define __get_MSPLIM() (0U) + #else + #define __get_MSPLIM() (__arm_rsr("MSPLIM")) + #endif + #define __get_PRIMASK() (__arm_rsr("PRIMASK")) + #define __get_PSP() (__arm_rsr("PSP")) + + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + #define __get_PSPLIM() (0U) + #else + #define __get_PSPLIM() (__arm_rsr("PSPLIM")) + #endif + + #define __get_xPSR() (__arm_rsr("xPSR")) + + #define __set_BASEPRI(VALUE) (__arm_wsr("BASEPRI", (VALUE))) + #define __set_BASEPRI_MAX(VALUE) (__arm_wsr("BASEPRI_MAX", (VALUE))) + +__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) +{ + __arm_wsr("CONTROL", control); + __iar_builtin_ISB(); +} + + #define __set_FAULTMASK(VALUE) (__arm_wsr("FAULTMASK", (VALUE))) + #define __set_MSP(VALUE) (__arm_wsr("MSP", (VALUE))) + + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + #define __set_MSPLIM(VALUE) ((void)(VALUE)) + #else + #define __set_MSPLIM(VALUE) (__arm_wsr("MSPLIM", (VALUE))) + #endif + #define __set_PRIMASK(VALUE) (__arm_wsr("PRIMASK", (VALUE))) + #define __set_PSP(VALUE) (__arm_wsr("PSP", (VALUE))) + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + #define __set_PSPLIM(VALUE) ((void)(VALUE)) + #else + #define __set_PSPLIM(VALUE) (__arm_wsr("PSPLIM", (VALUE))) + #endif + + #define __TZ_get_CONTROL_NS() (__arm_rsr("CONTROL_NS")) + +__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) +{ + __arm_wsr("CONTROL_NS", control); + __iar_builtin_ISB(); +} + + #define __TZ_get_PSP_NS() (__arm_rsr("PSP_NS")) + #define __TZ_set_PSP_NS(VALUE) (__arm_wsr("PSP_NS", (VALUE))) + #define __TZ_get_MSP_NS() (__arm_rsr("MSP_NS")) + #define __TZ_set_MSP_NS(VALUE) (__arm_wsr("MSP_NS", (VALUE))) + #define __TZ_get_SP_NS() (__arm_rsr("SP_NS")) + #define __TZ_set_SP_NS(VALUE) (__arm_wsr("SP_NS", (VALUE))) + #define __TZ_get_PRIMASK_NS() (__arm_rsr("PRIMASK_NS")) + #define __TZ_set_PRIMASK_NS(VALUE) (__arm_wsr("PRIMASK_NS", (VALUE))) + #define __TZ_get_BASEPRI_NS() (__arm_rsr("BASEPRI_NS")) + #define __TZ_set_BASEPRI_NS(VALUE) (__arm_wsr("BASEPRI_NS", (VALUE))) + #define __TZ_get_FAULTMASK_NS() (__arm_rsr("FAULTMASK_NS")) + #define __TZ_set_FAULTMASK_NS(VALUE)(__arm_wsr("FAULTMASK_NS", (VALUE))) + + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + #define __TZ_get_PSPLIM_NS() (0U) + #define __TZ_set_PSPLIM_NS(VALUE) ((void)(VALUE)) + #else + #define __TZ_get_PSPLIM_NS() (__arm_rsr("PSPLIM_NS")) + #define __TZ_set_PSPLIM_NS(VALUE) (__arm_wsr("PSPLIM_NS", (VALUE))) + #endif + + #define __TZ_get_MSPLIM_NS() (__arm_rsr("MSPLIM_NS")) + #define __TZ_set_MSPLIM_NS(VALUE) (__arm_wsr("MSPLIM_NS", (VALUE))) + + #define __NOP __iar_builtin_no_operation + + #define __CLZ __iar_builtin_CLZ + #define __CLREX __iar_builtin_CLREX + + #define __DMB __iar_builtin_DMB + #define __DSB __iar_builtin_DSB + #define __ISB __iar_builtin_ISB + + #define __LDREXB __iar_builtin_LDREXB + #define __LDREXH __iar_builtin_LDREXH + #define __LDREXW __iar_builtin_LDREX + + #define __RBIT __iar_builtin_RBIT + #define __REV __iar_builtin_REV + #define __REV16 __iar_builtin_REV16 + + __IAR_FT int16_t __REVSH(int16_t val) + { + return (int16_t) __iar_builtin_REVSH(val); + } + + #define __ROR __iar_builtin_ROR + #define __RRX __iar_builtin_RRX + + #define __SEV __iar_builtin_SEV + + #if !__IAR_M0_FAMILY + #define __SSAT __iar_builtin_SSAT + #endif + + #define __STREXB __iar_builtin_STREXB + #define __STREXH __iar_builtin_STREXH + #define __STREXW __iar_builtin_STREX + + #if !__IAR_M0_FAMILY + #define __USAT __iar_builtin_USAT + #endif + + #define __WFE __iar_builtin_WFE + #define __WFI __iar_builtin_WFI + + #if __ARM_MEDIA__ + #define __SADD8 __iar_builtin_SADD8 + #define __QADD8 __iar_builtin_QADD8 + #define __SHADD8 __iar_builtin_SHADD8 + #define __UADD8 __iar_builtin_UADD8 + #define __UQADD8 __iar_builtin_UQADD8 + #define __UHADD8 __iar_builtin_UHADD8 + #define __SSUB8 __iar_builtin_SSUB8 + #define __QSUB8 __iar_builtin_QSUB8 + #define __SHSUB8 __iar_builtin_SHSUB8 + #define __USUB8 __iar_builtin_USUB8 + #define __UQSUB8 __iar_builtin_UQSUB8 + #define __UHSUB8 __iar_builtin_UHSUB8 + #define __SADD16 __iar_builtin_SADD16 + #define __QADD16 __iar_builtin_QADD16 + #define __SHADD16 __iar_builtin_SHADD16 + #define __UADD16 __iar_builtin_UADD16 + #define __UQADD16 __iar_builtin_UQADD16 + #define __UHADD16 __iar_builtin_UHADD16 + #define __SSUB16 __iar_builtin_SSUB16 + #define __QSUB16 __iar_builtin_QSUB16 + #define __SHSUB16 __iar_builtin_SHSUB16 + #define __USUB16 __iar_builtin_USUB16 + #define __UQSUB16 __iar_builtin_UQSUB16 + #define __UHSUB16 __iar_builtin_UHSUB16 + #define __SASX __iar_builtin_SASX + #define __QASX __iar_builtin_QASX + #define __SHASX __iar_builtin_SHASX + #define __UASX __iar_builtin_UASX + #define __UQASX __iar_builtin_UQASX + #define __UHASX __iar_builtin_UHASX + #define __SSAX __iar_builtin_SSAX + #define __QSAX __iar_builtin_QSAX + #define __SHSAX __iar_builtin_SHSAX + #define __USAX __iar_builtin_USAX + #define __UQSAX __iar_builtin_UQSAX + #define __UHSAX __iar_builtin_UHSAX + #define __USAD8 __iar_builtin_USAD8 + #define __USADA8 __iar_builtin_USADA8 + #define __SSAT16 __iar_builtin_SSAT16 + #define __USAT16 __iar_builtin_USAT16 + #define __UXTB16 __iar_builtin_UXTB16 + #define __UXTAB16 __iar_builtin_UXTAB16 + #define __SXTB16 __iar_builtin_SXTB16 + #define __SXTAB16 __iar_builtin_SXTAB16 + #define __SMUAD __iar_builtin_SMUAD + #define __SMUADX __iar_builtin_SMUADX + #define __SMMLA __iar_builtin_SMMLA + #define __SMLAD __iar_builtin_SMLAD + #define __SMLADX __iar_builtin_SMLADX + #define __SMLALD __iar_builtin_SMLALD + #define __SMLALDX __iar_builtin_SMLALDX + #define __SMUSD __iar_builtin_SMUSD + #define __SMUSDX __iar_builtin_SMUSDX + #define __SMLSD __iar_builtin_SMLSD + #define __SMLSDX __iar_builtin_SMLSDX + #define __SMLSLD __iar_builtin_SMLSLD + #define __SMLSLDX __iar_builtin_SMLSLDX + #define __SEL __iar_builtin_SEL + #define __QADD __iar_builtin_QADD + #define __QSUB __iar_builtin_QSUB + #define __PKHBT __iar_builtin_PKHBT + #define __PKHTB __iar_builtin_PKHTB + #endif + +#else /* __ICCARM_INTRINSICS_VERSION__ == 2 */ + + #if __IAR_M0_FAMILY + /* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */ + #define __CLZ __cmsis_iar_clz_not_active + #define __SSAT __cmsis_iar_ssat_not_active + #define __USAT __cmsis_iar_usat_not_active + #define __RBIT __cmsis_iar_rbit_not_active + #define __get_APSR __cmsis_iar_get_APSR_not_active + #endif + + + #if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) )) + #define __get_FPSCR __cmsis_iar_get_FPSR_not_active + #define __set_FPSCR __cmsis_iar_set_FPSR_not_active + #endif + + #ifdef __INTRINSICS_INCLUDED + #error intrinsics.h is already included previously! + #endif + + #include + + #if __IAR_M0_FAMILY + /* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */ + #undef __CLZ + #undef __SSAT + #undef __USAT + #undef __RBIT + #undef __get_APSR + + __STATIC_INLINE uint8_t __CLZ(uint32_t data) + { + if (data == 0U) { return 32U; } + + uint32_t count = 0U; + uint32_t mask = 0x80000000U; + + while ((data & mask) == 0U) + { + count += 1U; + mask = mask >> 1U; + } + return count; + } + + __STATIC_INLINE uint32_t __RBIT(uint32_t v) + { + uint8_t sc = 31U; + uint32_t r = v; + for (v >>= 1U; v; v >>= 1U) + { + r <<= 1U; + r |= v & 1U; + sc--; + } + return (r << sc); + } + + __STATIC_INLINE uint32_t __get_APSR(void) + { + uint32_t res; + __asm("MRS %0,APSR" : "=r" (res)); + return res; + } + + #endif + + #if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) )) + #undef __get_FPSCR + #undef __set_FPSCR + #define __get_FPSCR() (0) + #define __set_FPSCR(VALUE) ((void)VALUE) + #endif + + #pragma diag_suppress=Pe940 + #pragma diag_suppress=Pe177 + + #define __enable_irq __enable_interrupt + #define __disable_irq __disable_interrupt + #define __NOP __no_operation + + #define __get_xPSR __get_PSR + + #if (!defined(__ARM_ARCH_6M__) || __ARM_ARCH_6M__==0) + + __IAR_FT uint32_t __LDREXW(uint32_t volatile *ptr) + { + return __LDREX((unsigned long *)ptr); + } + + __IAR_FT uint32_t __STREXW(uint32_t value, uint32_t volatile *ptr) + { + return __STREX(value, (unsigned long *)ptr); + } + #endif + + + /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */ + #if (__CORTEX_M >= 0x03) + + __IAR_FT uint32_t __RRX(uint32_t value) + { + uint32_t result; + __ASM volatile("RRX %0, %1" : "=r"(result) : "r" (value)); + return(result); + } + + __IAR_FT void __set_BASEPRI_MAX(uint32_t value) + { + __asm volatile("MSR BASEPRI_MAX,%0"::"r" (value)); + } + + + #define __enable_fault_irq __enable_fiq + #define __disable_fault_irq __disable_fiq + + + #endif /* (__CORTEX_M >= 0x03) */ + + __IAR_FT uint32_t __ROR(uint32_t op1, uint32_t op2) + { + return (op1 >> op2) | (op1 << ((sizeof(op1)*8)-op2)); + } + + #if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + + __IAR_FT uint32_t __get_MSPLIM(void) + { + uint32_t res; + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + res = 0U; + #else + __asm volatile("MRS %0,MSPLIM" : "=r" (res)); + #endif + return res; + } + + __IAR_FT void __set_MSPLIM(uint32_t value) + { + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)value; + #else + __asm volatile("MSR MSPLIM,%0" :: "r" (value)); + #endif + } + + __IAR_FT uint32_t __get_PSPLIM(void) + { + uint32_t res; + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + res = 0U; + #else + __asm volatile("MRS %0,PSPLIM" : "=r" (res)); + #endif + return res; + } + + __IAR_FT void __set_PSPLIM(uint32_t value) + { + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)value; + #else + __asm volatile("MSR PSPLIM,%0" :: "r" (value)); + #endif + } + + __IAR_FT uint32_t __TZ_get_CONTROL_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,CONTROL_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_CONTROL_NS(uint32_t value) + { + __asm volatile("MSR CONTROL_NS,%0" :: "r" (value)); + __iar_builtin_ISB(); + } + + __IAR_FT uint32_t __TZ_get_PSP_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,PSP_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_PSP_NS(uint32_t value) + { + __asm volatile("MSR PSP_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_MSP_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,MSP_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_MSP_NS(uint32_t value) + { + __asm volatile("MSR MSP_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_SP_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,SP_NS" : "=r" (res)); + return res; + } + __IAR_FT void __TZ_set_SP_NS(uint32_t value) + { + __asm volatile("MSR SP_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_PRIMASK_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,PRIMASK_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_PRIMASK_NS(uint32_t value) + { + __asm volatile("MSR PRIMASK_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_BASEPRI_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,BASEPRI_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_BASEPRI_NS(uint32_t value) + { + __asm volatile("MSR BASEPRI_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_FAULTMASK_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,FAULTMASK_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_FAULTMASK_NS(uint32_t value) + { + __asm volatile("MSR FAULTMASK_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_PSPLIM_NS(void) + { + uint32_t res; + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + res = 0U; + #else + __asm volatile("MRS %0,PSPLIM_NS" : "=r" (res)); + #endif + return res; + } + + __IAR_FT void __TZ_set_PSPLIM_NS(uint32_t value) + { + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)value; + #else + __asm volatile("MSR PSPLIM_NS,%0" :: "r" (value)); + #endif + } + + __IAR_FT uint32_t __TZ_get_MSPLIM_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,MSPLIM_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_MSPLIM_NS(uint32_t value) + { + __asm volatile("MSR MSPLIM_NS,%0" :: "r" (value)); + } + + #endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */ + +#endif /* __ICCARM_INTRINSICS_VERSION__ == 2 */ + +#define __BKPT(value) __asm volatile ("BKPT %0" : : "i"(value)) + +#if __IAR_M0_FAMILY + __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat) + { + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; + } + + __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat) + { + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; + } +#endif + +#if (__CORTEX_M >= 0x03) /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */ + + __IAR_FT uint8_t __LDRBT(volatile uint8_t *addr) + { + uint32_t res; + __ASM volatile ("LDRBT %0, [%1]" : "=r" (res) : "r" (addr) : "memory"); + return ((uint8_t)res); + } + + __IAR_FT uint16_t __LDRHT(volatile uint16_t *addr) + { + uint32_t res; + __ASM volatile ("LDRHT %0, [%1]" : "=r" (res) : "r" (addr) : "memory"); + return ((uint16_t)res); + } + + __IAR_FT uint32_t __LDRT(volatile uint32_t *addr) + { + uint32_t res; + __ASM volatile ("LDRT %0, [%1]" : "=r" (res) : "r" (addr) : "memory"); + return res; + } + + __IAR_FT void __STRBT(uint8_t value, volatile uint8_t *addr) + { + __ASM volatile ("STRBT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory"); + } + + __IAR_FT void __STRHT(uint16_t value, volatile uint16_t *addr) + { + __ASM volatile ("STRHT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory"); + } + + __IAR_FT void __STRT(uint32_t value, volatile uint32_t *addr) + { + __ASM volatile ("STRT %1, [%0]" : : "r" (addr), "r" (value) : "memory"); + } + +#endif /* (__CORTEX_M >= 0x03) */ + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + + + __IAR_FT uint8_t __LDAB(volatile uint8_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return ((uint8_t)res); + } + + __IAR_FT uint16_t __LDAH(volatile uint16_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return ((uint16_t)res); + } + + __IAR_FT uint32_t __LDA(volatile uint32_t *ptr) + { + uint32_t res; + __ASM volatile ("LDA %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return res; + } + + __IAR_FT void __STLB(uint8_t value, volatile uint8_t *ptr) + { + __ASM volatile ("STLB %1, [%0]" :: "r" (ptr), "r" (value) : "memory"); + } + + __IAR_FT void __STLH(uint16_t value, volatile uint16_t *ptr) + { + __ASM volatile ("STLH %1, [%0]" :: "r" (ptr), "r" (value) : "memory"); + } + + __IAR_FT void __STL(uint32_t value, volatile uint32_t *ptr) + { + __ASM volatile ("STL %1, [%0]" :: "r" (ptr), "r" (value) : "memory"); + } + + __IAR_FT uint8_t __LDAEXB(volatile uint8_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAEXB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return ((uint8_t)res); + } + + __IAR_FT uint16_t __LDAEXH(volatile uint16_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAEXH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return ((uint16_t)res); + } + + __IAR_FT uint32_t __LDAEX(volatile uint32_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAEX %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return res; + } + + __IAR_FT uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr) + { + uint32_t res; + __ASM volatile ("STLEXB %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory"); + return res; + } + + __IAR_FT uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr) + { + uint32_t res; + __ASM volatile ("STLEXH %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory"); + return res; + } + + __IAR_FT uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr) + { + uint32_t res; + __ASM volatile ("STLEX %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory"); + return res; + } + +#endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */ + +#undef __IAR_FT +#undef __IAR_M0_FAMILY +#undef __ICCARM_V8 + +#pragma diag_default=Pe940 +#pragma diag_default=Pe177 + +#define __SXTB16_RORn(ARG1, ARG2) __SXTB16(__ROR(ARG1, ARG2)) + +#define __SXTAB16_RORn(ARG1, ARG2, ARG3) __SXTAB16(ARG1, __ROR(ARG2, ARG3)) + +#endif /* __CMSIS_ICCARM_H__ */ diff --git a/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/CMSIS/Core/Include/cmsis_version.h b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/CMSIS/Core/Include/cmsis_version.h new file mode 100644 index 0000000000..8b4765f186 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/CMSIS/Core/Include/cmsis_version.h @@ -0,0 +1,39 @@ +/**************************************************************************//** + * @file cmsis_version.h + * @brief CMSIS Core(M) Version definitions + * @version V5.0.5 + * @date 02. February 2022 + ******************************************************************************/ +/* + * Copyright (c) 2009-2022 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CMSIS_VERSION_H +#define __CMSIS_VERSION_H + +/* CMSIS Version definitions */ +#define __CM_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS Core(M) main version */ +#define __CM_CMSIS_VERSION_SUB ( 6U) /*!< [15:0] CMSIS Core(M) sub version */ +#define __CM_CMSIS_VERSION ((__CM_CMSIS_VERSION_MAIN << 16U) | \ + __CM_CMSIS_VERSION_SUB ) /*!< CMSIS Core(M) version number */ +#endif diff --git a/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/CMSIS/Core/Include/core_armv81mml.h b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/CMSIS/Core/Include/core_armv81mml.h new file mode 100644 index 0000000000..94128a1a70 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/CMSIS/Core/Include/core_armv81mml.h @@ -0,0 +1,4228 @@ +/**************************************************************************//** + * @file core_armv81mml.h + * @brief CMSIS Armv8.1-M Mainline Core Peripheral Access Layer Header File + * @version V1.4.2 + * @date 13. October 2021 + ******************************************************************************/ +/* + * Copyright (c) 2018-2021 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#elif defined ( __GNUC__ ) + #pragma GCC diagnostic ignored "-Wpedantic" /* disable pedantic warning due to unnamed structs/unions */ +#endif + +#ifndef __CORE_ARMV81MML_H_GENERIC +#define __CORE_ARMV81MML_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_ARMV81MML + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS ARMV81MML definitions */ +#define __ARMv81MML_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __ARMv81MML_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __ARMv81MML_CMSIS_VERSION ((__ARMv81MML_CMSIS_VERSION_MAIN << 16U) | \ + __ARMv81MML_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (81U) /*!< Cortex-M Core */ + +#if defined ( __CC_ARM ) + #error Legacy Arm Compiler does not support Armv8.1-M target architecture. +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_ARMV81MML_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_ARMV81MML_H_DEPENDANT +#define __CORE_ARMV81MML_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __ARMv81MML_REV + #define __ARMv81MML_REV 0x0000U + #warning "__ARMv81MML_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #if __FPU_PRESENT != 0U + #ifndef __FPU_DP + #define __FPU_DP 0U + #warning "__FPU_DP not defined in device header file; using default!" + #endif + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __ICACHE_PRESENT + #define __ICACHE_PRESENT 0U + #warning "__ICACHE_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DCACHE_PRESENT + #define __DCACHE_PRESENT 0U + #warning "__DCACHE_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __PMU_PRESENT + #define __PMU_PRESENT 0U + #warning "__PMU_PRESENT not defined in device header file; using default!" + #endif + + #if __PMU_PRESENT != 0U + #ifndef __PMU_NUM_EVENTCNT + #define __PMU_NUM_EVENTCNT 2U + #warning "__PMU_NUM_EVENTCNT not defined in device header file; using default!" + #elif (__PMU_NUM_EVENTCNT > 31 || __PMU_NUM_EVENTCNT < 2) + #error "__PMU_NUM_EVENTCNT is out of range in device header file!" */ + #endif + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DSP_PRESENT + #define __DSP_PRESENT 0U + #warning "__DSP_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 1U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group ARMv81MML */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core SAU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ +#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */ + uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */ + uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */ +#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */ + +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED6[580U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ + __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ + __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ + __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */ + uint32_t RESERVED7[21U]; + __IOM uint32_t SFSR; /*!< Offset: 0x0E4 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x0E8 (R/W) Secure Fault Address Register */ + uint32_t RESERVED3[69U]; + __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ + __IOM uint32_t RFSR; /*!< Offset: 0x204 (R/W) RAS Fault Status Register */ + uint32_t RESERVED4[14U]; + __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ + uint32_t RESERVED5[1U]; + __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ + uint32_t RESERVED6[1U]; + __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ + __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ + __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ + __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ + __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ + __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ + __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ + __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ + __OM uint32_t BPIALL; /*!< Offset: 0x278 ( /W) Branch Predictor Invalidate All */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ +#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_IESB_Pos 5U /*!< SCB AIRCR: Implicit ESB Enable Position */ +#define SCB_AIRCR_IESB_Msk (1UL << SCB_AIRCR_IESB_Pos) /*!< SCB AIRCR: Implicit ESB Enable Mask */ + +#define SCB_AIRCR_DIT_Pos 4U /*!< SCB AIRCR: Data Independent Timing Position */ +#define SCB_AIRCR_DIT_Msk (1UL << SCB_AIRCR_DIT_Pos) /*!< SCB AIRCR: Data Independent Timing Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_TRD_Pos 20U /*!< SCB CCR: TRD Position */ +#define SCB_CCR_TRD_Msk (1UL << SCB_CCR_TRD_Pos) /*!< SCB CCR: TRD Mask */ + +#define SCB_CCR_LOB_Pos 19U /*!< SCB CCR: LOB Position */ +#define SCB_CCR_LOB_Msk (1UL << SCB_CCR_LOB_Pos) /*!< SCB CCR: LOB Mask */ + +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */ +#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */ +#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */ + +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */ +#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_CFSR_MEMFAULTSR_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */ +#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_PMU_Pos 5U /*!< SCB DFSR: PMU Position */ +#define SCB_DFSR_PMU_Msk (1UL << SCB_DFSR_PMU_Pos) /*!< SCB DFSR: PMU Mask */ + +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/* SCB Non-Secure Access Control Register Definitions */ +#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */ +#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */ + +#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */ +#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */ + +#define SCB_NSACR_CP7_Pos 7U /*!< SCB NSACR: CP7 Position */ +#define SCB_NSACR_CP7_Msk (1UL << SCB_NSACR_CP7_Pos) /*!< SCB NSACR: CP7 Mask */ + +#define SCB_NSACR_CP6_Pos 6U /*!< SCB NSACR: CP6 Position */ +#define SCB_NSACR_CP6_Msk (1UL << SCB_NSACR_CP6_Pos) /*!< SCB NSACR: CP6 Mask */ + +#define SCB_NSACR_CP5_Pos 5U /*!< SCB NSACR: CP5 Position */ +#define SCB_NSACR_CP5_Msk (1UL << SCB_NSACR_CP5_Pos) /*!< SCB NSACR: CP5 Mask */ + +#define SCB_NSACR_CP4_Pos 4U /*!< SCB NSACR: CP4 Position */ +#define SCB_NSACR_CP4_Msk (1UL << SCB_NSACR_CP4_Pos) /*!< SCB NSACR: CP4 Mask */ + +#define SCB_NSACR_CP3_Pos 3U /*!< SCB NSACR: CP3 Position */ +#define SCB_NSACR_CP3_Msk (1UL << SCB_NSACR_CP3_Pos) /*!< SCB NSACR: CP3 Mask */ + +#define SCB_NSACR_CP2_Pos 2U /*!< SCB NSACR: CP2 Position */ +#define SCB_NSACR_CP2_Msk (1UL << SCB_NSACR_CP2_Pos) /*!< SCB NSACR: CP2 Mask */ + +#define SCB_NSACR_CP1_Pos 1U /*!< SCB NSACR: CP1 Position */ +#define SCB_NSACR_CP1_Msk (1UL << SCB_NSACR_CP1_Pos) /*!< SCB NSACR: CP1 Mask */ + +#define SCB_NSACR_CP0_Pos 0U /*!< SCB NSACR: CP0 Position */ +#define SCB_NSACR_CP0_Msk (1UL /*<< SCB_NSACR_CP0_Pos*/) /*!< SCB NSACR: CP0 Mask */ + +/* SCB Debug Feature Register 0 Definitions */ +#define SCB_ID_DFR_UDE_Pos 28U /*!< SCB ID_DFR: UDE Position */ +#define SCB_ID_DFR_UDE_Msk (0xFUL << SCB_ID_DFR_UDE_Pos) /*!< SCB ID_DFR: UDE Mask */ + +#define SCB_ID_DFR_MProfDbg_Pos 20U /*!< SCB ID_DFR: MProfDbg Position */ +#define SCB_ID_DFR_MProfDbg_Msk (0xFUL << SCB_ID_DFR_MProfDbg_Pos) /*!< SCB ID_DFR: MProfDbg Mask */ + +/* SCB Cache Level ID Register Definitions */ +#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ +#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ + +#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ +#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ + +/* SCB Cache Type Register Definitions */ +#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ +#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ + +#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ +#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ + +#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ +#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ + +#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ +#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ + +#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ +#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ + +/* SCB Cache Size ID Register Definitions */ +#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ +#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ + +#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ +#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ + +#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ +#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ + +#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ +#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ + +#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ +#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ + +#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ +#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ + +#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ +#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ + +/* SCB Cache Size Selection Register Definitions */ +#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ +#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ + +#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ +#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ + +/* SCB Software Triggered Interrupt Register Definitions */ +#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ +#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ + +/* SCB RAS Fault Status Register Definitions */ +#define SCB_RFSR_V_Pos 31U /*!< SCB RFSR: V Position */ +#define SCB_RFSR_V_Msk (1UL << SCB_RFSR_V_Pos) /*!< SCB RFSR: V Mask */ + +#define SCB_RFSR_IS_Pos 16U /*!< SCB RFSR: IS Position */ +#define SCB_RFSR_IS_Msk (0x7FFFUL << SCB_RFSR_IS_Pos) /*!< SCB RFSR: IS Mask */ + +#define SCB_RFSR_UET_Pos 0U /*!< SCB RFSR: UET Position */ +#define SCB_RFSR_UET_Msk (3UL /*<< SCB_RFSR_UET_Pos*/) /*!< SCB RFSR: UET Mask */ + +/* SCB D-Cache Invalidate by Set-way Register Definitions */ +#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ +#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ + +#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ +#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ + +/* SCB D-Cache Clean by Set-way Register Definitions */ +#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ +#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ + +#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ +#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ + +/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ +#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ +#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ + +#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ +#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ + __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */ + uint32_t RESERVED6[3U]; + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) ITM Device Type Register */ + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Stimulus Port Register Definitions */ +#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */ +#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */ + +#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */ +#define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */ + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */ +#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */ + +#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */ +#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED14[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED15[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED16[1U]; + __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ + uint32_t RESERVED17[1U]; + __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ + uint32_t RESERVED18[1U]; + __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ + uint32_t RESERVED19[1U]; + __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ + uint32_t RESERVED20[1U]; + __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ + uint32_t RESERVED21[1U]; + __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ + uint32_t RESERVED22[1U]; + __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ + uint32_t RESERVED23[1U]; + __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ + uint32_t RESERVED24[1U]; + __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ + uint32_t RESERVED25[1U]; + __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ + uint32_t RESERVED26[1U]; + __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ + uint32_t RESERVED27[1U]; + __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ + uint32_t RESERVED28[1U]; + __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ + uint32_t RESERVED29[1U]; + __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ + uint32_t RESERVED30[1U]; + __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ + uint32_t RESERVED31[1U]; + __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ + uint32_t RESERVED32[934U]; + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ + uint32_t RESERVED33[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */ +#define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Sizes Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Sizes Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ + uint32_t RESERVED3[809U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) Software Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) Software Lock Status Register */ + uint32_t RESERVED4[4U]; + __IM uint32_t TYPE; /*!< Offset: 0xFC8 (R/ ) Device Identifier Register */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Register */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_SWOSCALER_Pos 0U /*!< TPI ACPR: SWOSCALER Position */ +#define TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/) /*!< TPI ACPR: SWOSCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ +#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ + +#define TPI_FFCR_EnFmt_Pos 0U /*!< TPI FFCR: EnFmt Position */ +#define TPI_FFCR_EnFmt_Msk (0x3UL << /*TPI_FFCR_EnFmt_Pos*/) /*!< TPI FFCR: EnFmt Mask */ + +/* TPI Periodic Synchronization Control Register Definitions */ +#define TPI_PSCR_PSCount_Pos 0U /*!< TPI PSCR: PSCount Position */ +#define TPI_PSCR_PSCount_Msk (0x1FUL /*<< TPI_PSCR_PSCount_Pos*/) /*!< TPI PSCR: TPSCount Mask */ + +/* TPI Software Lock Status Register Definitions */ +#define TPI_LSR_nTT_Pos 1U /*!< TPI LSR: Not thirty-two bit. Position */ +#define TPI_LSR_nTT_Msk (0x1UL << TPI_LSR_nTT_Pos) /*!< TPI LSR: Not thirty-two bit. Mask */ + +#define TPI_LSR_SLK_Pos 1U /*!< TPI LSR: Software Lock status Position */ +#define TPI_LSR_SLK_Msk (0x1UL << TPI_LSR_SLK_Pos) /*!< TPI LSR: Software Lock status Mask */ + +#define TPI_LSR_SLI_Pos 0U /*!< TPI LSR: Software Lock implemented Position */ +#define TPI_LSR_SLI_Msk (0x1UL /*<< TPI_LSR_SLI_Pos*/) /*!< TPI LSR: Software Lock implemented Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFO depth Position */ +#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFO depth Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + +#if defined (__PMU_PRESENT) && (__PMU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_PMU Performance Monitoring Unit (PMU) + \brief Type definitions for the Performance Monitoring Unit (PMU) + @{ + */ + +/** + \brief Structure type to access the Performance Monitoring Unit (PMU). + */ +typedef struct +{ + __IOM uint32_t EVCNTR[__PMU_NUM_EVENTCNT]; /*!< Offset: 0x0 (R/W) PMU Event Counter Registers */ +#if __PMU_NUM_EVENTCNT<31 + uint32_t RESERVED0[31U-__PMU_NUM_EVENTCNT]; +#endif + __IOM uint32_t CCNTR; /*!< Offset: 0x7C (R/W) PMU Cycle Counter Register */ + uint32_t RESERVED1[224]; + __IOM uint32_t EVTYPER[__PMU_NUM_EVENTCNT]; /*!< Offset: 0x400 (R/W) PMU Event Type and Filter Registers */ +#if __PMU_NUM_EVENTCNT<31 + uint32_t RESERVED2[31U-__PMU_NUM_EVENTCNT]; +#endif + __IOM uint32_t CCFILTR; /*!< Offset: 0x47C (R/W) PMU Cycle Counter Filter Register */ + uint32_t RESERVED3[480]; + __IOM uint32_t CNTENSET; /*!< Offset: 0xC00 (R/W) PMU Count Enable Set Register */ + uint32_t RESERVED4[7]; + __IOM uint32_t CNTENCLR; /*!< Offset: 0xC20 (R/W) PMU Count Enable Clear Register */ + uint32_t RESERVED5[7]; + __IOM uint32_t INTENSET; /*!< Offset: 0xC40 (R/W) PMU Interrupt Enable Set Register */ + uint32_t RESERVED6[7]; + __IOM uint32_t INTENCLR; /*!< Offset: 0xC60 (R/W) PMU Interrupt Enable Clear Register */ + uint32_t RESERVED7[7]; + __IOM uint32_t OVSCLR; /*!< Offset: 0xC80 (R/W) PMU Overflow Flag Status Clear Register */ + uint32_t RESERVED8[7]; + __IOM uint32_t SWINC; /*!< Offset: 0xCA0 (R/W) PMU Software Increment Register */ + uint32_t RESERVED9[7]; + __IOM uint32_t OVSSET; /*!< Offset: 0xCC0 (R/W) PMU Overflow Flag Status Set Register */ + uint32_t RESERVED10[79]; + __IOM uint32_t TYPE; /*!< Offset: 0xE00 (R/W) PMU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0xE04 (R/W) PMU Control Register */ + uint32_t RESERVED11[108]; + __IOM uint32_t AUTHSTATUS; /*!< Offset: 0xFB8 (R/W) PMU Authentication Status Register */ + __IOM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/W) PMU Device Architecture Register */ + uint32_t RESERVED12[3]; + __IOM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/W) PMU Device Type Register */ + __IOM uint32_t PIDR4; /*!< Offset: 0xFD0 (R/W) PMU Peripheral Identification Register 4 */ + uint32_t RESERVED13[3]; + __IOM uint32_t PIDR0; /*!< Offset: 0xFE0 (R/W) PMU Peripheral Identification Register 0 */ + __IOM uint32_t PIDR1; /*!< Offset: 0xFE4 (R/W) PMU Peripheral Identification Register 1 */ + __IOM uint32_t PIDR2; /*!< Offset: 0xFE8 (R/W) PMU Peripheral Identification Register 2 */ + __IOM uint32_t PIDR3; /*!< Offset: 0xFEC (R/W) PMU Peripheral Identification Register 3 */ + __IOM uint32_t CIDR0; /*!< Offset: 0xFF0 (R/W) PMU Component Identification Register 0 */ + __IOM uint32_t CIDR1; /*!< Offset: 0xFF4 (R/W) PMU Component Identification Register 1 */ + __IOM uint32_t CIDR2; /*!< Offset: 0xFF8 (R/W) PMU Component Identification Register 2 */ + __IOM uint32_t CIDR3; /*!< Offset: 0xFFC (R/W) PMU Component Identification Register 3 */ +} PMU_Type; + +/** \brief PMU Event Counter Registers (0-30) Definitions */ + +#define PMU_EVCNTR_CNT_Pos 0U /*!< PMU EVCNTR: Counter Position */ +#define PMU_EVCNTR_CNT_Msk (0xFFFFUL /*<< PMU_EVCNTRx_CNT_Pos*/) /*!< PMU EVCNTR: Counter Mask */ + +/** \brief PMU Event Type and Filter Registers (0-30) Definitions */ + +#define PMU_EVTYPER_EVENTTOCNT_Pos 0U /*!< PMU EVTYPER: Event to Count Position */ +#define PMU_EVTYPER_EVENTTOCNT_Msk (0xFFFFUL /*<< EVTYPERx_EVENTTOCNT_Pos*/) /*!< PMU EVTYPER: Event to Count Mask */ + +/** \brief PMU Count Enable Set Register Definitions */ + +#define PMU_CNTENSET_CNT0_ENABLE_Pos 0U /*!< PMU CNTENSET: Event Counter 0 Enable Set Position */ +#define PMU_CNTENSET_CNT0_ENABLE_Msk (1UL /*<< PMU_CNTENSET_CNT0_ENABLE_Pos*/) /*!< PMU CNTENSET: Event Counter 0 Enable Set Mask */ + +#define PMU_CNTENSET_CNT1_ENABLE_Pos 1U /*!< PMU CNTENSET: Event Counter 1 Enable Set Position */ +#define PMU_CNTENSET_CNT1_ENABLE_Msk (1UL << PMU_CNTENSET_CNT1_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 1 Enable Set Mask */ + +#define PMU_CNTENSET_CNT2_ENABLE_Pos 2U /*!< PMU CNTENSET: Event Counter 2 Enable Set Position */ +#define PMU_CNTENSET_CNT2_ENABLE_Msk (1UL << PMU_CNTENSET_CNT2_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 2 Enable Set Mask */ + +#define PMU_CNTENSET_CNT3_ENABLE_Pos 3U /*!< PMU CNTENSET: Event Counter 3 Enable Set Position */ +#define PMU_CNTENSET_CNT3_ENABLE_Msk (1UL << PMU_CNTENSET_CNT3_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 3 Enable Set Mask */ + +#define PMU_CNTENSET_CNT4_ENABLE_Pos 4U /*!< PMU CNTENSET: Event Counter 4 Enable Set Position */ +#define PMU_CNTENSET_CNT4_ENABLE_Msk (1UL << PMU_CNTENSET_CNT4_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 4 Enable Set Mask */ + +#define PMU_CNTENSET_CNT5_ENABLE_Pos 5U /*!< PMU CNTENSET: Event Counter 5 Enable Set Position */ +#define PMU_CNTENSET_CNT5_ENABLE_Msk (1UL << PMU_CNTENSET_CNT5_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 5 Enable Set Mask */ + +#define PMU_CNTENSET_CNT6_ENABLE_Pos 6U /*!< PMU CNTENSET: Event Counter 6 Enable Set Position */ +#define PMU_CNTENSET_CNT6_ENABLE_Msk (1UL << PMU_CNTENSET_CNT6_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 6 Enable Set Mask */ + +#define PMU_CNTENSET_CNT7_ENABLE_Pos 7U /*!< PMU CNTENSET: Event Counter 7 Enable Set Position */ +#define PMU_CNTENSET_CNT7_ENABLE_Msk (1UL << PMU_CNTENSET_CNT7_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 7 Enable Set Mask */ + +#define PMU_CNTENSET_CNT8_ENABLE_Pos 8U /*!< PMU CNTENSET: Event Counter 8 Enable Set Position */ +#define PMU_CNTENSET_CNT8_ENABLE_Msk (1UL << PMU_CNTENSET_CNT8_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 8 Enable Set Mask */ + +#define PMU_CNTENSET_CNT9_ENABLE_Pos 9U /*!< PMU CNTENSET: Event Counter 9 Enable Set Position */ +#define PMU_CNTENSET_CNT9_ENABLE_Msk (1UL << PMU_CNTENSET_CNT9_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 9 Enable Set Mask */ + +#define PMU_CNTENSET_CNT10_ENABLE_Pos 10U /*!< PMU CNTENSET: Event Counter 10 Enable Set Position */ +#define PMU_CNTENSET_CNT10_ENABLE_Msk (1UL << PMU_CNTENSET_CNT10_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 10 Enable Set Mask */ + +#define PMU_CNTENSET_CNT11_ENABLE_Pos 11U /*!< PMU CNTENSET: Event Counter 11 Enable Set Position */ +#define PMU_CNTENSET_CNT11_ENABLE_Msk (1UL << PMU_CNTENSET_CNT11_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 11 Enable Set Mask */ + +#define PMU_CNTENSET_CNT12_ENABLE_Pos 12U /*!< PMU CNTENSET: Event Counter 12 Enable Set Position */ +#define PMU_CNTENSET_CNT12_ENABLE_Msk (1UL << PMU_CNTENSET_CNT12_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 12 Enable Set Mask */ + +#define PMU_CNTENSET_CNT13_ENABLE_Pos 13U /*!< PMU CNTENSET: Event Counter 13 Enable Set Position */ +#define PMU_CNTENSET_CNT13_ENABLE_Msk (1UL << PMU_CNTENSET_CNT13_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 13 Enable Set Mask */ + +#define PMU_CNTENSET_CNT14_ENABLE_Pos 14U /*!< PMU CNTENSET: Event Counter 14 Enable Set Position */ +#define PMU_CNTENSET_CNT14_ENABLE_Msk (1UL << PMU_CNTENSET_CNT14_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 14 Enable Set Mask */ + +#define PMU_CNTENSET_CNT15_ENABLE_Pos 15U /*!< PMU CNTENSET: Event Counter 15 Enable Set Position */ +#define PMU_CNTENSET_CNT15_ENABLE_Msk (1UL << PMU_CNTENSET_CNT15_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 15 Enable Set Mask */ + +#define PMU_CNTENSET_CNT16_ENABLE_Pos 16U /*!< PMU CNTENSET: Event Counter 16 Enable Set Position */ +#define PMU_CNTENSET_CNT16_ENABLE_Msk (1UL << PMU_CNTENSET_CNT16_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 16 Enable Set Mask */ + +#define PMU_CNTENSET_CNT17_ENABLE_Pos 17U /*!< PMU CNTENSET: Event Counter 17 Enable Set Position */ +#define PMU_CNTENSET_CNT17_ENABLE_Msk (1UL << PMU_CNTENSET_CNT17_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 17 Enable Set Mask */ + +#define PMU_CNTENSET_CNT18_ENABLE_Pos 18U /*!< PMU CNTENSET: Event Counter 18 Enable Set Position */ +#define PMU_CNTENSET_CNT18_ENABLE_Msk (1UL << PMU_CNTENSET_CNT18_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 18 Enable Set Mask */ + +#define PMU_CNTENSET_CNT19_ENABLE_Pos 19U /*!< PMU CNTENSET: Event Counter 19 Enable Set Position */ +#define PMU_CNTENSET_CNT19_ENABLE_Msk (1UL << PMU_CNTENSET_CNT19_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 19 Enable Set Mask */ + +#define PMU_CNTENSET_CNT20_ENABLE_Pos 20U /*!< PMU CNTENSET: Event Counter 20 Enable Set Position */ +#define PMU_CNTENSET_CNT20_ENABLE_Msk (1UL << PMU_CNTENSET_CNT20_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 20 Enable Set Mask */ + +#define PMU_CNTENSET_CNT21_ENABLE_Pos 21U /*!< PMU CNTENSET: Event Counter 21 Enable Set Position */ +#define PMU_CNTENSET_CNT21_ENABLE_Msk (1UL << PMU_CNTENSET_CNT21_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 21 Enable Set Mask */ + +#define PMU_CNTENSET_CNT22_ENABLE_Pos 22U /*!< PMU CNTENSET: Event Counter 22 Enable Set Position */ +#define PMU_CNTENSET_CNT22_ENABLE_Msk (1UL << PMU_CNTENSET_CNT22_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 22 Enable Set Mask */ + +#define PMU_CNTENSET_CNT23_ENABLE_Pos 23U /*!< PMU CNTENSET: Event Counter 23 Enable Set Position */ +#define PMU_CNTENSET_CNT23_ENABLE_Msk (1UL << PMU_CNTENSET_CNT23_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 23 Enable Set Mask */ + +#define PMU_CNTENSET_CNT24_ENABLE_Pos 24U /*!< PMU CNTENSET: Event Counter 24 Enable Set Position */ +#define PMU_CNTENSET_CNT24_ENABLE_Msk (1UL << PMU_CNTENSET_CNT24_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 24 Enable Set Mask */ + +#define PMU_CNTENSET_CNT25_ENABLE_Pos 25U /*!< PMU CNTENSET: Event Counter 25 Enable Set Position */ +#define PMU_CNTENSET_CNT25_ENABLE_Msk (1UL << PMU_CNTENSET_CNT25_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 25 Enable Set Mask */ + +#define PMU_CNTENSET_CNT26_ENABLE_Pos 26U /*!< PMU CNTENSET: Event Counter 26 Enable Set Position */ +#define PMU_CNTENSET_CNT26_ENABLE_Msk (1UL << PMU_CNTENSET_CNT26_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 26 Enable Set Mask */ + +#define PMU_CNTENSET_CNT27_ENABLE_Pos 27U /*!< PMU CNTENSET: Event Counter 27 Enable Set Position */ +#define PMU_CNTENSET_CNT27_ENABLE_Msk (1UL << PMU_CNTENSET_CNT27_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 27 Enable Set Mask */ + +#define PMU_CNTENSET_CNT28_ENABLE_Pos 28U /*!< PMU CNTENSET: Event Counter 28 Enable Set Position */ +#define PMU_CNTENSET_CNT28_ENABLE_Msk (1UL << PMU_CNTENSET_CNT28_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 28 Enable Set Mask */ + +#define PMU_CNTENSET_CNT29_ENABLE_Pos 29U /*!< PMU CNTENSET: Event Counter 29 Enable Set Position */ +#define PMU_CNTENSET_CNT29_ENABLE_Msk (1UL << PMU_CNTENSET_CNT29_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 29 Enable Set Mask */ + +#define PMU_CNTENSET_CNT30_ENABLE_Pos 30U /*!< PMU CNTENSET: Event Counter 30 Enable Set Position */ +#define PMU_CNTENSET_CNT30_ENABLE_Msk (1UL << PMU_CNTENSET_CNT30_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 30 Enable Set Mask */ + +#define PMU_CNTENSET_CCNTR_ENABLE_Pos 31U /*!< PMU CNTENSET: Cycle Counter Enable Set Position */ +#define PMU_CNTENSET_CCNTR_ENABLE_Msk (1UL << PMU_CNTENSET_CCNTR_ENABLE_Pos) /*!< PMU CNTENSET: Cycle Counter Enable Set Mask */ + +/** \brief PMU Count Enable Clear Register Definitions */ + +#define PMU_CNTENSET_CNT0_ENABLE_Pos 0U /*!< PMU CNTENCLR: Event Counter 0 Enable Clear Position */ +#define PMU_CNTENCLR_CNT0_ENABLE_Msk (1UL /*<< PMU_CNTENCLR_CNT0_ENABLE_Pos*/) /*!< PMU CNTENCLR: Event Counter 0 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT1_ENABLE_Pos 1U /*!< PMU CNTENCLR: Event Counter 1 Enable Clear Position */ +#define PMU_CNTENCLR_CNT1_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT1_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 1 Enable Clear */ + +#define PMU_CNTENCLR_CNT2_ENABLE_Pos 2U /*!< PMU CNTENCLR: Event Counter 2 Enable Clear Position */ +#define PMU_CNTENCLR_CNT2_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT2_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 2 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT3_ENABLE_Pos 3U /*!< PMU CNTENCLR: Event Counter 3 Enable Clear Position */ +#define PMU_CNTENCLR_CNT3_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT3_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 3 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT4_ENABLE_Pos 4U /*!< PMU CNTENCLR: Event Counter 4 Enable Clear Position */ +#define PMU_CNTENCLR_CNT4_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT4_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 4 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT5_ENABLE_Pos 5U /*!< PMU CNTENCLR: Event Counter 5 Enable Clear Position */ +#define PMU_CNTENCLR_CNT5_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT5_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 5 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT6_ENABLE_Pos 6U /*!< PMU CNTENCLR: Event Counter 6 Enable Clear Position */ +#define PMU_CNTENCLR_CNT6_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT6_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 6 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT7_ENABLE_Pos 7U /*!< PMU CNTENCLR: Event Counter 7 Enable Clear Position */ +#define PMU_CNTENCLR_CNT7_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT7_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 7 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT8_ENABLE_Pos 8U /*!< PMU CNTENCLR: Event Counter 8 Enable Clear Position */ +#define PMU_CNTENCLR_CNT8_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT8_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 8 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT9_ENABLE_Pos 9U /*!< PMU CNTENCLR: Event Counter 9 Enable Clear Position */ +#define PMU_CNTENCLR_CNT9_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT9_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 9 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT10_ENABLE_Pos 10U /*!< PMU CNTENCLR: Event Counter 10 Enable Clear Position */ +#define PMU_CNTENCLR_CNT10_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT10_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 10 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT11_ENABLE_Pos 11U /*!< PMU CNTENCLR: Event Counter 11 Enable Clear Position */ +#define PMU_CNTENCLR_CNT11_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT11_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 11 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT12_ENABLE_Pos 12U /*!< PMU CNTENCLR: Event Counter 12 Enable Clear Position */ +#define PMU_CNTENCLR_CNT12_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT12_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 12 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT13_ENABLE_Pos 13U /*!< PMU CNTENCLR: Event Counter 13 Enable Clear Position */ +#define PMU_CNTENCLR_CNT13_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT13_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 13 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT14_ENABLE_Pos 14U /*!< PMU CNTENCLR: Event Counter 14 Enable Clear Position */ +#define PMU_CNTENCLR_CNT14_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT14_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 14 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT15_ENABLE_Pos 15U /*!< PMU CNTENCLR: Event Counter 15 Enable Clear Position */ +#define PMU_CNTENCLR_CNT15_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT15_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 15 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT16_ENABLE_Pos 16U /*!< PMU CNTENCLR: Event Counter 16 Enable Clear Position */ +#define PMU_CNTENCLR_CNT16_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT16_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 16 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT17_ENABLE_Pos 17U /*!< PMU CNTENCLR: Event Counter 17 Enable Clear Position */ +#define PMU_CNTENCLR_CNT17_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT17_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 17 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT18_ENABLE_Pos 18U /*!< PMU CNTENCLR: Event Counter 18 Enable Clear Position */ +#define PMU_CNTENCLR_CNT18_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT18_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 18 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT19_ENABLE_Pos 19U /*!< PMU CNTENCLR: Event Counter 19 Enable Clear Position */ +#define PMU_CNTENCLR_CNT19_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT19_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 19 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT20_ENABLE_Pos 20U /*!< PMU CNTENCLR: Event Counter 20 Enable Clear Position */ +#define PMU_CNTENCLR_CNT20_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT20_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 20 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT21_ENABLE_Pos 21U /*!< PMU CNTENCLR: Event Counter 21 Enable Clear Position */ +#define PMU_CNTENCLR_CNT21_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT21_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 21 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT22_ENABLE_Pos 22U /*!< PMU CNTENCLR: Event Counter 22 Enable Clear Position */ +#define PMU_CNTENCLR_CNT22_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT22_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 22 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT23_ENABLE_Pos 23U /*!< PMU CNTENCLR: Event Counter 23 Enable Clear Position */ +#define PMU_CNTENCLR_CNT23_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT23_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 23 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT24_ENABLE_Pos 24U /*!< PMU CNTENCLR: Event Counter 24 Enable Clear Position */ +#define PMU_CNTENCLR_CNT24_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT24_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 24 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT25_ENABLE_Pos 25U /*!< PMU CNTENCLR: Event Counter 25 Enable Clear Position */ +#define PMU_CNTENCLR_CNT25_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT25_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 25 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT26_ENABLE_Pos 26U /*!< PMU CNTENCLR: Event Counter 26 Enable Clear Position */ +#define PMU_CNTENCLR_CNT26_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT26_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 26 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT27_ENABLE_Pos 27U /*!< PMU CNTENCLR: Event Counter 27 Enable Clear Position */ +#define PMU_CNTENCLR_CNT27_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT27_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 27 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT28_ENABLE_Pos 28U /*!< PMU CNTENCLR: Event Counter 28 Enable Clear Position */ +#define PMU_CNTENCLR_CNT28_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT28_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 28 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT29_ENABLE_Pos 29U /*!< PMU CNTENCLR: Event Counter 29 Enable Clear Position */ +#define PMU_CNTENCLR_CNT29_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT29_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 29 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT30_ENABLE_Pos 30U /*!< PMU CNTENCLR: Event Counter 30 Enable Clear Position */ +#define PMU_CNTENCLR_CNT30_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT30_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 30 Enable Clear Mask */ + +#define PMU_CNTENCLR_CCNTR_ENABLE_Pos 31U /*!< PMU CNTENCLR: Cycle Counter Enable Clear Position */ +#define PMU_CNTENCLR_CCNTR_ENABLE_Msk (1UL << PMU_CNTENCLR_CCNTR_ENABLE_Pos) /*!< PMU CNTENCLR: Cycle Counter Enable Clear Mask */ + +/** \brief PMU Interrupt Enable Set Register Definitions */ + +#define PMU_INTENSET_CNT0_ENABLE_Pos 0U /*!< PMU INTENSET: Event Counter 0 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT0_ENABLE_Msk (1UL /*<< PMU_INTENSET_CNT0_ENABLE_Pos*/) /*!< PMU INTENSET: Event Counter 0 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT1_ENABLE_Pos 1U /*!< PMU INTENSET: Event Counter 1 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT1_ENABLE_Msk (1UL << PMU_INTENSET_CNT1_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 1 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT2_ENABLE_Pos 2U /*!< PMU INTENSET: Event Counter 2 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT2_ENABLE_Msk (1UL << PMU_INTENSET_CNT2_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 2 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT3_ENABLE_Pos 3U /*!< PMU INTENSET: Event Counter 3 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT3_ENABLE_Msk (1UL << PMU_INTENSET_CNT3_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 3 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT4_ENABLE_Pos 4U /*!< PMU INTENSET: Event Counter 4 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT4_ENABLE_Msk (1UL << PMU_INTENSET_CNT4_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 4 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT5_ENABLE_Pos 5U /*!< PMU INTENSET: Event Counter 5 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT5_ENABLE_Msk (1UL << PMU_INTENSET_CNT5_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 5 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT6_ENABLE_Pos 6U /*!< PMU INTENSET: Event Counter 6 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT6_ENABLE_Msk (1UL << PMU_INTENSET_CNT6_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 6 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT7_ENABLE_Pos 7U /*!< PMU INTENSET: Event Counter 7 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT7_ENABLE_Msk (1UL << PMU_INTENSET_CNT7_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 7 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT8_ENABLE_Pos 8U /*!< PMU INTENSET: Event Counter 8 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT8_ENABLE_Msk (1UL << PMU_INTENSET_CNT8_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 8 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT9_ENABLE_Pos 9U /*!< PMU INTENSET: Event Counter 9 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT9_ENABLE_Msk (1UL << PMU_INTENSET_CNT9_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 9 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT10_ENABLE_Pos 10U /*!< PMU INTENSET: Event Counter 10 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT10_ENABLE_Msk (1UL << PMU_INTENSET_CNT10_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 10 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT11_ENABLE_Pos 11U /*!< PMU INTENSET: Event Counter 11 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT11_ENABLE_Msk (1UL << PMU_INTENSET_CNT11_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 11 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT12_ENABLE_Pos 12U /*!< PMU INTENSET: Event Counter 12 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT12_ENABLE_Msk (1UL << PMU_INTENSET_CNT12_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 12 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT13_ENABLE_Pos 13U /*!< PMU INTENSET: Event Counter 13 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT13_ENABLE_Msk (1UL << PMU_INTENSET_CNT13_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 13 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT14_ENABLE_Pos 14U /*!< PMU INTENSET: Event Counter 14 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT14_ENABLE_Msk (1UL << PMU_INTENSET_CNT14_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 14 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT15_ENABLE_Pos 15U /*!< PMU INTENSET: Event Counter 15 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT15_ENABLE_Msk (1UL << PMU_INTENSET_CNT15_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 15 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT16_ENABLE_Pos 16U /*!< PMU INTENSET: Event Counter 16 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT16_ENABLE_Msk (1UL << PMU_INTENSET_CNT16_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 16 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT17_ENABLE_Pos 17U /*!< PMU INTENSET: Event Counter 17 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT17_ENABLE_Msk (1UL << PMU_INTENSET_CNT17_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 17 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT18_ENABLE_Pos 18U /*!< PMU INTENSET: Event Counter 18 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT18_ENABLE_Msk (1UL << PMU_INTENSET_CNT18_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 18 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT19_ENABLE_Pos 19U /*!< PMU INTENSET: Event Counter 19 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT19_ENABLE_Msk (1UL << PMU_INTENSET_CNT19_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 19 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT20_ENABLE_Pos 20U /*!< PMU INTENSET: Event Counter 20 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT20_ENABLE_Msk (1UL << PMU_INTENSET_CNT20_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 20 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT21_ENABLE_Pos 21U /*!< PMU INTENSET: Event Counter 21 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT21_ENABLE_Msk (1UL << PMU_INTENSET_CNT21_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 21 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT22_ENABLE_Pos 22U /*!< PMU INTENSET: Event Counter 22 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT22_ENABLE_Msk (1UL << PMU_INTENSET_CNT22_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 22 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT23_ENABLE_Pos 23U /*!< PMU INTENSET: Event Counter 23 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT23_ENABLE_Msk (1UL << PMU_INTENSET_CNT23_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 23 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT24_ENABLE_Pos 24U /*!< PMU INTENSET: Event Counter 24 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT24_ENABLE_Msk (1UL << PMU_INTENSET_CNT24_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 24 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT25_ENABLE_Pos 25U /*!< PMU INTENSET: Event Counter 25 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT25_ENABLE_Msk (1UL << PMU_INTENSET_CNT25_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 25 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT26_ENABLE_Pos 26U /*!< PMU INTENSET: Event Counter 26 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT26_ENABLE_Msk (1UL << PMU_INTENSET_CNT26_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 26 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT27_ENABLE_Pos 27U /*!< PMU INTENSET: Event Counter 27 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT27_ENABLE_Msk (1UL << PMU_INTENSET_CNT27_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 27 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT28_ENABLE_Pos 28U /*!< PMU INTENSET: Event Counter 28 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT28_ENABLE_Msk (1UL << PMU_INTENSET_CNT28_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 28 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT29_ENABLE_Pos 29U /*!< PMU INTENSET: Event Counter 29 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT29_ENABLE_Msk (1UL << PMU_INTENSET_CNT29_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 29 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT30_ENABLE_Pos 30U /*!< PMU INTENSET: Event Counter 30 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT30_ENABLE_Msk (1UL << PMU_INTENSET_CNT30_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 30 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CYCCNT_ENABLE_Pos 31U /*!< PMU INTENSET: Cycle Counter Interrupt Enable Set Position */ +#define PMU_INTENSET_CCYCNT_ENABLE_Msk (1UL << PMU_INTENSET_CYCCNT_ENABLE_Pos) /*!< PMU INTENSET: Cycle Counter Interrupt Enable Set Mask */ + +/** \brief PMU Interrupt Enable Clear Register Definitions */ + +#define PMU_INTENSET_CNT0_ENABLE_Pos 0U /*!< PMU INTENCLR: Event Counter 0 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT0_ENABLE_Msk (1UL /*<< PMU_INTENCLR_CNT0_ENABLE_Pos*/) /*!< PMU INTENCLR: Event Counter 0 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT1_ENABLE_Pos 1U /*!< PMU INTENCLR: Event Counter 1 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT1_ENABLE_Msk (1UL << PMU_INTENCLR_CNT1_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 1 Interrupt Enable Clear */ + +#define PMU_INTENCLR_CNT2_ENABLE_Pos 2U /*!< PMU INTENCLR: Event Counter 2 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT2_ENABLE_Msk (1UL << PMU_INTENCLR_CNT2_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 2 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT3_ENABLE_Pos 3U /*!< PMU INTENCLR: Event Counter 3 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT3_ENABLE_Msk (1UL << PMU_INTENCLR_CNT3_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 3 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT4_ENABLE_Pos 4U /*!< PMU INTENCLR: Event Counter 4 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT4_ENABLE_Msk (1UL << PMU_INTENCLR_CNT4_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 4 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT5_ENABLE_Pos 5U /*!< PMU INTENCLR: Event Counter 5 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT5_ENABLE_Msk (1UL << PMU_INTENCLR_CNT5_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 5 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT6_ENABLE_Pos 6U /*!< PMU INTENCLR: Event Counter 6 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT6_ENABLE_Msk (1UL << PMU_INTENCLR_CNT6_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 6 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT7_ENABLE_Pos 7U /*!< PMU INTENCLR: Event Counter 7 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT7_ENABLE_Msk (1UL << PMU_INTENCLR_CNT7_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 7 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT8_ENABLE_Pos 8U /*!< PMU INTENCLR: Event Counter 8 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT8_ENABLE_Msk (1UL << PMU_INTENCLR_CNT8_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 8 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT9_ENABLE_Pos 9U /*!< PMU INTENCLR: Event Counter 9 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT9_ENABLE_Msk (1UL << PMU_INTENCLR_CNT9_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 9 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT10_ENABLE_Pos 10U /*!< PMU INTENCLR: Event Counter 10 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT10_ENABLE_Msk (1UL << PMU_INTENCLR_CNT10_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 10 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT11_ENABLE_Pos 11U /*!< PMU INTENCLR: Event Counter 11 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT11_ENABLE_Msk (1UL << PMU_INTENCLR_CNT11_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 11 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT12_ENABLE_Pos 12U /*!< PMU INTENCLR: Event Counter 12 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT12_ENABLE_Msk (1UL << PMU_INTENCLR_CNT12_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 12 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT13_ENABLE_Pos 13U /*!< PMU INTENCLR: Event Counter 13 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT13_ENABLE_Msk (1UL << PMU_INTENCLR_CNT13_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 13 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT14_ENABLE_Pos 14U /*!< PMU INTENCLR: Event Counter 14 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT14_ENABLE_Msk (1UL << PMU_INTENCLR_CNT14_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 14 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT15_ENABLE_Pos 15U /*!< PMU INTENCLR: Event Counter 15 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT15_ENABLE_Msk (1UL << PMU_INTENCLR_CNT15_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 15 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT16_ENABLE_Pos 16U /*!< PMU INTENCLR: Event Counter 16 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT16_ENABLE_Msk (1UL << PMU_INTENCLR_CNT16_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 16 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT17_ENABLE_Pos 17U /*!< PMU INTENCLR: Event Counter 17 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT17_ENABLE_Msk (1UL << PMU_INTENCLR_CNT17_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 17 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT18_ENABLE_Pos 18U /*!< PMU INTENCLR: Event Counter 18 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT18_ENABLE_Msk (1UL << PMU_INTENCLR_CNT18_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 18 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT19_ENABLE_Pos 19U /*!< PMU INTENCLR: Event Counter 19 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT19_ENABLE_Msk (1UL << PMU_INTENCLR_CNT19_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 19 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT20_ENABLE_Pos 20U /*!< PMU INTENCLR: Event Counter 20 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT20_ENABLE_Msk (1UL << PMU_INTENCLR_CNT20_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 20 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT21_ENABLE_Pos 21U /*!< PMU INTENCLR: Event Counter 21 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT21_ENABLE_Msk (1UL << PMU_INTENCLR_CNT21_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 21 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT22_ENABLE_Pos 22U /*!< PMU INTENCLR: Event Counter 22 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT22_ENABLE_Msk (1UL << PMU_INTENCLR_CNT22_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 22 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT23_ENABLE_Pos 23U /*!< PMU INTENCLR: Event Counter 23 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT23_ENABLE_Msk (1UL << PMU_INTENCLR_CNT23_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 23 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT24_ENABLE_Pos 24U /*!< PMU INTENCLR: Event Counter 24 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT24_ENABLE_Msk (1UL << PMU_INTENCLR_CNT24_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 24 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT25_ENABLE_Pos 25U /*!< PMU INTENCLR: Event Counter 25 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT25_ENABLE_Msk (1UL << PMU_INTENCLR_CNT25_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 25 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT26_ENABLE_Pos 26U /*!< PMU INTENCLR: Event Counter 26 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT26_ENABLE_Msk (1UL << PMU_INTENCLR_CNT26_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 26 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT27_ENABLE_Pos 27U /*!< PMU INTENCLR: Event Counter 27 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT27_ENABLE_Msk (1UL << PMU_INTENCLR_CNT27_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 27 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT28_ENABLE_Pos 28U /*!< PMU INTENCLR: Event Counter 28 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT28_ENABLE_Msk (1UL << PMU_INTENCLR_CNT28_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 28 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT29_ENABLE_Pos 29U /*!< PMU INTENCLR: Event Counter 29 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT29_ENABLE_Msk (1UL << PMU_INTENCLR_CNT29_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 29 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT30_ENABLE_Pos 30U /*!< PMU INTENCLR: Event Counter 30 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT30_ENABLE_Msk (1UL << PMU_INTENCLR_CNT30_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 30 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CYCCNT_ENABLE_Pos 31U /*!< PMU INTENCLR: Cycle Counter Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CYCCNT_ENABLE_Msk (1UL << PMU_INTENCLR_CYCCNT_ENABLE_Pos) /*!< PMU INTENCLR: Cycle Counter Interrupt Enable Clear Mask */ + +/** \brief PMU Overflow Flag Status Set Register Definitions */ + +#define PMU_OVSSET_CNT0_STATUS_Pos 0U /*!< PMU OVSSET: Event Counter 0 Overflow Set Position */ +#define PMU_OVSSET_CNT0_STATUS_Msk (1UL /*<< PMU_OVSSET_CNT0_STATUS_Pos*/) /*!< PMU OVSSET: Event Counter 0 Overflow Set Mask */ + +#define PMU_OVSSET_CNT1_STATUS_Pos 1U /*!< PMU OVSSET: Event Counter 1 Overflow Set Position */ +#define PMU_OVSSET_CNT1_STATUS_Msk (1UL << PMU_OVSSET_CNT1_STATUS_Pos) /*!< PMU OVSSET: Event Counter 1 Overflow Set Mask */ + +#define PMU_OVSSET_CNT2_STATUS_Pos 2U /*!< PMU OVSSET: Event Counter 2 Overflow Set Position */ +#define PMU_OVSSET_CNT2_STATUS_Msk (1UL << PMU_OVSSET_CNT2_STATUS_Pos) /*!< PMU OVSSET: Event Counter 2 Overflow Set Mask */ + +#define PMU_OVSSET_CNT3_STATUS_Pos 3U /*!< PMU OVSSET: Event Counter 3 Overflow Set Position */ +#define PMU_OVSSET_CNT3_STATUS_Msk (1UL << PMU_OVSSET_CNT3_STATUS_Pos) /*!< PMU OVSSET: Event Counter 3 Overflow Set Mask */ + +#define PMU_OVSSET_CNT4_STATUS_Pos 4U /*!< PMU OVSSET: Event Counter 4 Overflow Set Position */ +#define PMU_OVSSET_CNT4_STATUS_Msk (1UL << PMU_OVSSET_CNT4_STATUS_Pos) /*!< PMU OVSSET: Event Counter 4 Overflow Set Mask */ + +#define PMU_OVSSET_CNT5_STATUS_Pos 5U /*!< PMU OVSSET: Event Counter 5 Overflow Set Position */ +#define PMU_OVSSET_CNT5_STATUS_Msk (1UL << PMU_OVSSET_CNT5_STATUS_Pos) /*!< PMU OVSSET: Event Counter 5 Overflow Set Mask */ + +#define PMU_OVSSET_CNT6_STATUS_Pos 6U /*!< PMU OVSSET: Event Counter 6 Overflow Set Position */ +#define PMU_OVSSET_CNT6_STATUS_Msk (1UL << PMU_OVSSET_CNT6_STATUS_Pos) /*!< PMU OVSSET: Event Counter 6 Overflow Set Mask */ + +#define PMU_OVSSET_CNT7_STATUS_Pos 7U /*!< PMU OVSSET: Event Counter 7 Overflow Set Position */ +#define PMU_OVSSET_CNT7_STATUS_Msk (1UL << PMU_OVSSET_CNT7_STATUS_Pos) /*!< PMU OVSSET: Event Counter 7 Overflow Set Mask */ + +#define PMU_OVSSET_CNT8_STATUS_Pos 8U /*!< PMU OVSSET: Event Counter 8 Overflow Set Position */ +#define PMU_OVSSET_CNT8_STATUS_Msk (1UL << PMU_OVSSET_CNT8_STATUS_Pos) /*!< PMU OVSSET: Event Counter 8 Overflow Set Mask */ + +#define PMU_OVSSET_CNT9_STATUS_Pos 9U /*!< PMU OVSSET: Event Counter 9 Overflow Set Position */ +#define PMU_OVSSET_CNT9_STATUS_Msk (1UL << PMU_OVSSET_CNT9_STATUS_Pos) /*!< PMU OVSSET: Event Counter 9 Overflow Set Mask */ + +#define PMU_OVSSET_CNT10_STATUS_Pos 10U /*!< PMU OVSSET: Event Counter 10 Overflow Set Position */ +#define PMU_OVSSET_CNT10_STATUS_Msk (1UL << PMU_OVSSET_CNT10_STATUS_Pos) /*!< PMU OVSSET: Event Counter 10 Overflow Set Mask */ + +#define PMU_OVSSET_CNT11_STATUS_Pos 11U /*!< PMU OVSSET: Event Counter 11 Overflow Set Position */ +#define PMU_OVSSET_CNT11_STATUS_Msk (1UL << PMU_OVSSET_CNT11_STATUS_Pos) /*!< PMU OVSSET: Event Counter 11 Overflow Set Mask */ + +#define PMU_OVSSET_CNT12_STATUS_Pos 12U /*!< PMU OVSSET: Event Counter 12 Overflow Set Position */ +#define PMU_OVSSET_CNT12_STATUS_Msk (1UL << PMU_OVSSET_CNT12_STATUS_Pos) /*!< PMU OVSSET: Event Counter 12 Overflow Set Mask */ + +#define PMU_OVSSET_CNT13_STATUS_Pos 13U /*!< PMU OVSSET: Event Counter 13 Overflow Set Position */ +#define PMU_OVSSET_CNT13_STATUS_Msk (1UL << PMU_OVSSET_CNT13_STATUS_Pos) /*!< PMU OVSSET: Event Counter 13 Overflow Set Mask */ + +#define PMU_OVSSET_CNT14_STATUS_Pos 14U /*!< PMU OVSSET: Event Counter 14 Overflow Set Position */ +#define PMU_OVSSET_CNT14_STATUS_Msk (1UL << PMU_OVSSET_CNT14_STATUS_Pos) /*!< PMU OVSSET: Event Counter 14 Overflow Set Mask */ + +#define PMU_OVSSET_CNT15_STATUS_Pos 15U /*!< PMU OVSSET: Event Counter 15 Overflow Set Position */ +#define PMU_OVSSET_CNT15_STATUS_Msk (1UL << PMU_OVSSET_CNT15_STATUS_Pos) /*!< PMU OVSSET: Event Counter 15 Overflow Set Mask */ + +#define PMU_OVSSET_CNT16_STATUS_Pos 16U /*!< PMU OVSSET: Event Counter 16 Overflow Set Position */ +#define PMU_OVSSET_CNT16_STATUS_Msk (1UL << PMU_OVSSET_CNT16_STATUS_Pos) /*!< PMU OVSSET: Event Counter 16 Overflow Set Mask */ + +#define PMU_OVSSET_CNT17_STATUS_Pos 17U /*!< PMU OVSSET: Event Counter 17 Overflow Set Position */ +#define PMU_OVSSET_CNT17_STATUS_Msk (1UL << PMU_OVSSET_CNT17_STATUS_Pos) /*!< PMU OVSSET: Event Counter 17 Overflow Set Mask */ + +#define PMU_OVSSET_CNT18_STATUS_Pos 18U /*!< PMU OVSSET: Event Counter 18 Overflow Set Position */ +#define PMU_OVSSET_CNT18_STATUS_Msk (1UL << PMU_OVSSET_CNT18_STATUS_Pos) /*!< PMU OVSSET: Event Counter 18 Overflow Set Mask */ + +#define PMU_OVSSET_CNT19_STATUS_Pos 19U /*!< PMU OVSSET: Event Counter 19 Overflow Set Position */ +#define PMU_OVSSET_CNT19_STATUS_Msk (1UL << PMU_OVSSET_CNT19_STATUS_Pos) /*!< PMU OVSSET: Event Counter 19 Overflow Set Mask */ + +#define PMU_OVSSET_CNT20_STATUS_Pos 20U /*!< PMU OVSSET: Event Counter 20 Overflow Set Position */ +#define PMU_OVSSET_CNT20_STATUS_Msk (1UL << PMU_OVSSET_CNT20_STATUS_Pos) /*!< PMU OVSSET: Event Counter 20 Overflow Set Mask */ + +#define PMU_OVSSET_CNT21_STATUS_Pos 21U /*!< PMU OVSSET: Event Counter 21 Overflow Set Position */ +#define PMU_OVSSET_CNT21_STATUS_Msk (1UL << PMU_OVSSET_CNT21_STATUS_Pos) /*!< PMU OVSSET: Event Counter 21 Overflow Set Mask */ + +#define PMU_OVSSET_CNT22_STATUS_Pos 22U /*!< PMU OVSSET: Event Counter 22 Overflow Set Position */ +#define PMU_OVSSET_CNT22_STATUS_Msk (1UL << PMU_OVSSET_CNT22_STATUS_Pos) /*!< PMU OVSSET: Event Counter 22 Overflow Set Mask */ + +#define PMU_OVSSET_CNT23_STATUS_Pos 23U /*!< PMU OVSSET: Event Counter 23 Overflow Set Position */ +#define PMU_OVSSET_CNT23_STATUS_Msk (1UL << PMU_OVSSET_CNT23_STATUS_Pos) /*!< PMU OVSSET: Event Counter 23 Overflow Set Mask */ + +#define PMU_OVSSET_CNT24_STATUS_Pos 24U /*!< PMU OVSSET: Event Counter 24 Overflow Set Position */ +#define PMU_OVSSET_CNT24_STATUS_Msk (1UL << PMU_OVSSET_CNT24_STATUS_Pos) /*!< PMU OVSSET: Event Counter 24 Overflow Set Mask */ + +#define PMU_OVSSET_CNT25_STATUS_Pos 25U /*!< PMU OVSSET: Event Counter 25 Overflow Set Position */ +#define PMU_OVSSET_CNT25_STATUS_Msk (1UL << PMU_OVSSET_CNT25_STATUS_Pos) /*!< PMU OVSSET: Event Counter 25 Overflow Set Mask */ + +#define PMU_OVSSET_CNT26_STATUS_Pos 26U /*!< PMU OVSSET: Event Counter 26 Overflow Set Position */ +#define PMU_OVSSET_CNT26_STATUS_Msk (1UL << PMU_OVSSET_CNT26_STATUS_Pos) /*!< PMU OVSSET: Event Counter 26 Overflow Set Mask */ + +#define PMU_OVSSET_CNT27_STATUS_Pos 27U /*!< PMU OVSSET: Event Counter 27 Overflow Set Position */ +#define PMU_OVSSET_CNT27_STATUS_Msk (1UL << PMU_OVSSET_CNT27_STATUS_Pos) /*!< PMU OVSSET: Event Counter 27 Overflow Set Mask */ + +#define PMU_OVSSET_CNT28_STATUS_Pos 28U /*!< PMU OVSSET: Event Counter 28 Overflow Set Position */ +#define PMU_OVSSET_CNT28_STATUS_Msk (1UL << PMU_OVSSET_CNT28_STATUS_Pos) /*!< PMU OVSSET: Event Counter 28 Overflow Set Mask */ + +#define PMU_OVSSET_CNT29_STATUS_Pos 29U /*!< PMU OVSSET: Event Counter 29 Overflow Set Position */ +#define PMU_OVSSET_CNT29_STATUS_Msk (1UL << PMU_OVSSET_CNT29_STATUS_Pos) /*!< PMU OVSSET: Event Counter 29 Overflow Set Mask */ + +#define PMU_OVSSET_CNT30_STATUS_Pos 30U /*!< PMU OVSSET: Event Counter 30 Overflow Set Position */ +#define PMU_OVSSET_CNT30_STATUS_Msk (1UL << PMU_OVSSET_CNT30_STATUS_Pos) /*!< PMU OVSSET: Event Counter 30 Overflow Set Mask */ + +#define PMU_OVSSET_CYCCNT_STATUS_Pos 31U /*!< PMU OVSSET: Cycle Counter Overflow Set Position */ +#define PMU_OVSSET_CYCCNT_STATUS_Msk (1UL << PMU_OVSSET_CYCCNT_STATUS_Pos) /*!< PMU OVSSET: Cycle Counter Overflow Set Mask */ + +/** \brief PMU Overflow Flag Status Clear Register Definitions */ + +#define PMU_OVSCLR_CNT0_STATUS_Pos 0U /*!< PMU OVSCLR: Event Counter 0 Overflow Clear Position */ +#define PMU_OVSCLR_CNT0_STATUS_Msk (1UL /*<< PMU_OVSCLR_CNT0_STATUS_Pos*/) /*!< PMU OVSCLR: Event Counter 0 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT1_STATUS_Pos 1U /*!< PMU OVSCLR: Event Counter 1 Overflow Clear Position */ +#define PMU_OVSCLR_CNT1_STATUS_Msk (1UL << PMU_OVSCLR_CNT1_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 1 Overflow Clear */ + +#define PMU_OVSCLR_CNT2_STATUS_Pos 2U /*!< PMU OVSCLR: Event Counter 2 Overflow Clear Position */ +#define PMU_OVSCLR_CNT2_STATUS_Msk (1UL << PMU_OVSCLR_CNT2_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 2 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT3_STATUS_Pos 3U /*!< PMU OVSCLR: Event Counter 3 Overflow Clear Position */ +#define PMU_OVSCLR_CNT3_STATUS_Msk (1UL << PMU_OVSCLR_CNT3_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 3 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT4_STATUS_Pos 4U /*!< PMU OVSCLR: Event Counter 4 Overflow Clear Position */ +#define PMU_OVSCLR_CNT4_STATUS_Msk (1UL << PMU_OVSCLR_CNT4_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 4 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT5_STATUS_Pos 5U /*!< PMU OVSCLR: Event Counter 5 Overflow Clear Position */ +#define PMU_OVSCLR_CNT5_STATUS_Msk (1UL << PMU_OVSCLR_CNT5_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 5 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT6_STATUS_Pos 6U /*!< PMU OVSCLR: Event Counter 6 Overflow Clear Position */ +#define PMU_OVSCLR_CNT6_STATUS_Msk (1UL << PMU_OVSCLR_CNT6_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 6 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT7_STATUS_Pos 7U /*!< PMU OVSCLR: Event Counter 7 Overflow Clear Position */ +#define PMU_OVSCLR_CNT7_STATUS_Msk (1UL << PMU_OVSCLR_CNT7_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 7 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT8_STATUS_Pos 8U /*!< PMU OVSCLR: Event Counter 8 Overflow Clear Position */ +#define PMU_OVSCLR_CNT8_STATUS_Msk (1UL << PMU_OVSCLR_CNT8_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 8 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT9_STATUS_Pos 9U /*!< PMU OVSCLR: Event Counter 9 Overflow Clear Position */ +#define PMU_OVSCLR_CNT9_STATUS_Msk (1UL << PMU_OVSCLR_CNT9_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 9 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT10_STATUS_Pos 10U /*!< PMU OVSCLR: Event Counter 10 Overflow Clear Position */ +#define PMU_OVSCLR_CNT10_STATUS_Msk (1UL << PMU_OVSCLR_CNT10_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 10 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT11_STATUS_Pos 11U /*!< PMU OVSCLR: Event Counter 11 Overflow Clear Position */ +#define PMU_OVSCLR_CNT11_STATUS_Msk (1UL << PMU_OVSCLR_CNT11_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 11 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT12_STATUS_Pos 12U /*!< PMU OVSCLR: Event Counter 12 Overflow Clear Position */ +#define PMU_OVSCLR_CNT12_STATUS_Msk (1UL << PMU_OVSCLR_CNT12_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 12 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT13_STATUS_Pos 13U /*!< PMU OVSCLR: Event Counter 13 Overflow Clear Position */ +#define PMU_OVSCLR_CNT13_STATUS_Msk (1UL << PMU_OVSCLR_CNT13_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 13 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT14_STATUS_Pos 14U /*!< PMU OVSCLR: Event Counter 14 Overflow Clear Position */ +#define PMU_OVSCLR_CNT14_STATUS_Msk (1UL << PMU_OVSCLR_CNT14_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 14 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT15_STATUS_Pos 15U /*!< PMU OVSCLR: Event Counter 15 Overflow Clear Position */ +#define PMU_OVSCLR_CNT15_STATUS_Msk (1UL << PMU_OVSCLR_CNT15_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 15 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT16_STATUS_Pos 16U /*!< PMU OVSCLR: Event Counter 16 Overflow Clear Position */ +#define PMU_OVSCLR_CNT16_STATUS_Msk (1UL << PMU_OVSCLR_CNT16_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 16 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT17_STATUS_Pos 17U /*!< PMU OVSCLR: Event Counter 17 Overflow Clear Position */ +#define PMU_OVSCLR_CNT17_STATUS_Msk (1UL << PMU_OVSCLR_CNT17_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 17 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT18_STATUS_Pos 18U /*!< PMU OVSCLR: Event Counter 18 Overflow Clear Position */ +#define PMU_OVSCLR_CNT18_STATUS_Msk (1UL << PMU_OVSCLR_CNT18_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 18 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT19_STATUS_Pos 19U /*!< PMU OVSCLR: Event Counter 19 Overflow Clear Position */ +#define PMU_OVSCLR_CNT19_STATUS_Msk (1UL << PMU_OVSCLR_CNT19_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 19 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT20_STATUS_Pos 20U /*!< PMU OVSCLR: Event Counter 20 Overflow Clear Position */ +#define PMU_OVSCLR_CNT20_STATUS_Msk (1UL << PMU_OVSCLR_CNT20_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 20 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT21_STATUS_Pos 21U /*!< PMU OVSCLR: Event Counter 21 Overflow Clear Position */ +#define PMU_OVSCLR_CNT21_STATUS_Msk (1UL << PMU_OVSCLR_CNT21_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 21 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT22_STATUS_Pos 22U /*!< PMU OVSCLR: Event Counter 22 Overflow Clear Position */ +#define PMU_OVSCLR_CNT22_STATUS_Msk (1UL << PMU_OVSCLR_CNT22_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 22 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT23_STATUS_Pos 23U /*!< PMU OVSCLR: Event Counter 23 Overflow Clear Position */ +#define PMU_OVSCLR_CNT23_STATUS_Msk (1UL << PMU_OVSCLR_CNT23_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 23 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT24_STATUS_Pos 24U /*!< PMU OVSCLR: Event Counter 24 Overflow Clear Position */ +#define PMU_OVSCLR_CNT24_STATUS_Msk (1UL << PMU_OVSCLR_CNT24_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 24 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT25_STATUS_Pos 25U /*!< PMU OVSCLR: Event Counter 25 Overflow Clear Position */ +#define PMU_OVSCLR_CNT25_STATUS_Msk (1UL << PMU_OVSCLR_CNT25_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 25 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT26_STATUS_Pos 26U /*!< PMU OVSCLR: Event Counter 26 Overflow Clear Position */ +#define PMU_OVSCLR_CNT26_STATUS_Msk (1UL << PMU_OVSCLR_CNT26_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 26 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT27_STATUS_Pos 27U /*!< PMU OVSCLR: Event Counter 27 Overflow Clear Position */ +#define PMU_OVSCLR_CNT27_STATUS_Msk (1UL << PMU_OVSCLR_CNT27_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 27 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT28_STATUS_Pos 28U /*!< PMU OVSCLR: Event Counter 28 Overflow Clear Position */ +#define PMU_OVSCLR_CNT28_STATUS_Msk (1UL << PMU_OVSCLR_CNT28_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 28 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT29_STATUS_Pos 29U /*!< PMU OVSCLR: Event Counter 29 Overflow Clear Position */ +#define PMU_OVSCLR_CNT29_STATUS_Msk (1UL << PMU_OVSCLR_CNT29_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 29 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT30_STATUS_Pos 30U /*!< PMU OVSCLR: Event Counter 30 Overflow Clear Position */ +#define PMU_OVSCLR_CNT30_STATUS_Msk (1UL << PMU_OVSCLR_CNT30_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 30 Overflow Clear Mask */ + +#define PMU_OVSCLR_CYCCNT_STATUS_Pos 31U /*!< PMU OVSCLR: Cycle Counter Overflow Clear Position */ +#define PMU_OVSCLR_CYCCNT_STATUS_Msk (1UL << PMU_OVSCLR_CYCCNT_STATUS_Pos) /*!< PMU OVSCLR: Cycle Counter Overflow Clear Mask */ + +/** \brief PMU Software Increment Counter */ + +#define PMU_SWINC_CNT0_Pos 0U /*!< PMU SWINC: Event Counter 0 Software Increment Position */ +#define PMU_SWINC_CNT0_Msk (1UL /*<< PMU_SWINC_CNT0_Pos */) /*!< PMU SWINC: Event Counter 0 Software Increment Mask */ + +#define PMU_SWINC_CNT1_Pos 1U /*!< PMU SWINC: Event Counter 1 Software Increment Position */ +#define PMU_SWINC_CNT1_Msk (1UL << PMU_SWINC_CNT1_Pos) /*!< PMU SWINC: Event Counter 1 Software Increment Mask */ + +#define PMU_SWINC_CNT2_Pos 2U /*!< PMU SWINC: Event Counter 2 Software Increment Position */ +#define PMU_SWINC_CNT2_Msk (1UL << PMU_SWINC_CNT2_Pos) /*!< PMU SWINC: Event Counter 2 Software Increment Mask */ + +#define PMU_SWINC_CNT3_Pos 3U /*!< PMU SWINC: Event Counter 3 Software Increment Position */ +#define PMU_SWINC_CNT3_Msk (1UL << PMU_SWINC_CNT3_Pos) /*!< PMU SWINC: Event Counter 3 Software Increment Mask */ + +#define PMU_SWINC_CNT4_Pos 4U /*!< PMU SWINC: Event Counter 4 Software Increment Position */ +#define PMU_SWINC_CNT4_Msk (1UL << PMU_SWINC_CNT4_Pos) /*!< PMU SWINC: Event Counter 4 Software Increment Mask */ + +#define PMU_SWINC_CNT5_Pos 5U /*!< PMU SWINC: Event Counter 5 Software Increment Position */ +#define PMU_SWINC_CNT5_Msk (1UL << PMU_SWINC_CNT5_Pos) /*!< PMU SWINC: Event Counter 5 Software Increment Mask */ + +#define PMU_SWINC_CNT6_Pos 6U /*!< PMU SWINC: Event Counter 6 Software Increment Position */ +#define PMU_SWINC_CNT6_Msk (1UL << PMU_SWINC_CNT6_Pos) /*!< PMU SWINC: Event Counter 6 Software Increment Mask */ + +#define PMU_SWINC_CNT7_Pos 7U /*!< PMU SWINC: Event Counter 7 Software Increment Position */ +#define PMU_SWINC_CNT7_Msk (1UL << PMU_SWINC_CNT7_Pos) /*!< PMU SWINC: Event Counter 7 Software Increment Mask */ + +#define PMU_SWINC_CNT8_Pos 8U /*!< PMU SWINC: Event Counter 8 Software Increment Position */ +#define PMU_SWINC_CNT8_Msk (1UL << PMU_SWINC_CNT8_Pos) /*!< PMU SWINC: Event Counter 8 Software Increment Mask */ + +#define PMU_SWINC_CNT9_Pos 9U /*!< PMU SWINC: Event Counter 9 Software Increment Position */ +#define PMU_SWINC_CNT9_Msk (1UL << PMU_SWINC_CNT9_Pos) /*!< PMU SWINC: Event Counter 9 Software Increment Mask */ + +#define PMU_SWINC_CNT10_Pos 10U /*!< PMU SWINC: Event Counter 10 Software Increment Position */ +#define PMU_SWINC_CNT10_Msk (1UL << PMU_SWINC_CNT10_Pos) /*!< PMU SWINC: Event Counter 10 Software Increment Mask */ + +#define PMU_SWINC_CNT11_Pos 11U /*!< PMU SWINC: Event Counter 11 Software Increment Position */ +#define PMU_SWINC_CNT11_Msk (1UL << PMU_SWINC_CNT11_Pos) /*!< PMU SWINC: Event Counter 11 Software Increment Mask */ + +#define PMU_SWINC_CNT12_Pos 12U /*!< PMU SWINC: Event Counter 12 Software Increment Position */ +#define PMU_SWINC_CNT12_Msk (1UL << PMU_SWINC_CNT12_Pos) /*!< PMU SWINC: Event Counter 12 Software Increment Mask */ + +#define PMU_SWINC_CNT13_Pos 13U /*!< PMU SWINC: Event Counter 13 Software Increment Position */ +#define PMU_SWINC_CNT13_Msk (1UL << PMU_SWINC_CNT13_Pos) /*!< PMU SWINC: Event Counter 13 Software Increment Mask */ + +#define PMU_SWINC_CNT14_Pos 14U /*!< PMU SWINC: Event Counter 14 Software Increment Position */ +#define PMU_SWINC_CNT14_Msk (1UL << PMU_SWINC_CNT14_Pos) /*!< PMU SWINC: Event Counter 14 Software Increment Mask */ + +#define PMU_SWINC_CNT15_Pos 15U /*!< PMU SWINC: Event Counter 15 Software Increment Position */ +#define PMU_SWINC_CNT15_Msk (1UL << PMU_SWINC_CNT15_Pos) /*!< PMU SWINC: Event Counter 15 Software Increment Mask */ + +#define PMU_SWINC_CNT16_Pos 16U /*!< PMU SWINC: Event Counter 16 Software Increment Position */ +#define PMU_SWINC_CNT16_Msk (1UL << PMU_SWINC_CNT16_Pos) /*!< PMU SWINC: Event Counter 16 Software Increment Mask */ + +#define PMU_SWINC_CNT17_Pos 17U /*!< PMU SWINC: Event Counter 17 Software Increment Position */ +#define PMU_SWINC_CNT17_Msk (1UL << PMU_SWINC_CNT17_Pos) /*!< PMU SWINC: Event Counter 17 Software Increment Mask */ + +#define PMU_SWINC_CNT18_Pos 18U /*!< PMU SWINC: Event Counter 18 Software Increment Position */ +#define PMU_SWINC_CNT18_Msk (1UL << PMU_SWINC_CNT18_Pos) /*!< PMU SWINC: Event Counter 18 Software Increment Mask */ + +#define PMU_SWINC_CNT19_Pos 19U /*!< PMU SWINC: Event Counter 19 Software Increment Position */ +#define PMU_SWINC_CNT19_Msk (1UL << PMU_SWINC_CNT19_Pos) /*!< PMU SWINC: Event Counter 19 Software Increment Mask */ + +#define PMU_SWINC_CNT20_Pos 20U /*!< PMU SWINC: Event Counter 20 Software Increment Position */ +#define PMU_SWINC_CNT20_Msk (1UL << PMU_SWINC_CNT20_Pos) /*!< PMU SWINC: Event Counter 20 Software Increment Mask */ + +#define PMU_SWINC_CNT21_Pos 21U /*!< PMU SWINC: Event Counter 21 Software Increment Position */ +#define PMU_SWINC_CNT21_Msk (1UL << PMU_SWINC_CNT21_Pos) /*!< PMU SWINC: Event Counter 21 Software Increment Mask */ + +#define PMU_SWINC_CNT22_Pos 22U /*!< PMU SWINC: Event Counter 22 Software Increment Position */ +#define PMU_SWINC_CNT22_Msk (1UL << PMU_SWINC_CNT22_Pos) /*!< PMU SWINC: Event Counter 22 Software Increment Mask */ + +#define PMU_SWINC_CNT23_Pos 23U /*!< PMU SWINC: Event Counter 23 Software Increment Position */ +#define PMU_SWINC_CNT23_Msk (1UL << PMU_SWINC_CNT23_Pos) /*!< PMU SWINC: Event Counter 23 Software Increment Mask */ + +#define PMU_SWINC_CNT24_Pos 24U /*!< PMU SWINC: Event Counter 24 Software Increment Position */ +#define PMU_SWINC_CNT24_Msk (1UL << PMU_SWINC_CNT24_Pos) /*!< PMU SWINC: Event Counter 24 Software Increment Mask */ + +#define PMU_SWINC_CNT25_Pos 25U /*!< PMU SWINC: Event Counter 25 Software Increment Position */ +#define PMU_SWINC_CNT25_Msk (1UL << PMU_SWINC_CNT25_Pos) /*!< PMU SWINC: Event Counter 25 Software Increment Mask */ + +#define PMU_SWINC_CNT26_Pos 26U /*!< PMU SWINC: Event Counter 26 Software Increment Position */ +#define PMU_SWINC_CNT26_Msk (1UL << PMU_SWINC_CNT26_Pos) /*!< PMU SWINC: Event Counter 26 Software Increment Mask */ + +#define PMU_SWINC_CNT27_Pos 27U /*!< PMU SWINC: Event Counter 27 Software Increment Position */ +#define PMU_SWINC_CNT27_Msk (1UL << PMU_SWINC_CNT27_Pos) /*!< PMU SWINC: Event Counter 27 Software Increment Mask */ + +#define PMU_SWINC_CNT28_Pos 28U /*!< PMU SWINC: Event Counter 28 Software Increment Position */ +#define PMU_SWINC_CNT28_Msk (1UL << PMU_SWINC_CNT28_Pos) /*!< PMU SWINC: Event Counter 28 Software Increment Mask */ + +#define PMU_SWINC_CNT29_Pos 29U /*!< PMU SWINC: Event Counter 29 Software Increment Position */ +#define PMU_SWINC_CNT29_Msk (1UL << PMU_SWINC_CNT29_Pos) /*!< PMU SWINC: Event Counter 29 Software Increment Mask */ + +#define PMU_SWINC_CNT30_Pos 30U /*!< PMU SWINC: Event Counter 30 Software Increment Position */ +#define PMU_SWINC_CNT30_Msk (1UL << PMU_SWINC_CNT30_Pos) /*!< PMU SWINC: Event Counter 30 Software Increment Mask */ + +/** \brief PMU Control Register Definitions */ + +#define PMU_CTRL_ENABLE_Pos 0U /*!< PMU CTRL: ENABLE Position */ +#define PMU_CTRL_ENABLE_Msk (1UL /*<< PMU_CTRL_ENABLE_Pos*/) /*!< PMU CTRL: ENABLE Mask */ + +#define PMU_CTRL_EVENTCNT_RESET_Pos 1U /*!< PMU CTRL: Event Counter Reset Position */ +#define PMU_CTRL_EVENTCNT_RESET_Msk (1UL << PMU_CTRL_EVENTCNT_RESET_Pos) /*!< PMU CTRL: Event Counter Reset Mask */ + +#define PMU_CTRL_CYCCNT_RESET_Pos 2U /*!< PMU CTRL: Cycle Counter Reset Position */ +#define PMU_CTRL_CYCCNT_RESET_Msk (1UL << PMU_CTRL_CYCCNT_RESET_Pos) /*!< PMU CTRL: Cycle Counter Reset Mask */ + +#define PMU_CTRL_CYCCNT_DISABLE_Pos 5U /*!< PMU CTRL: Disable Cycle Counter Position */ +#define PMU_CTRL_CYCCNT_DISABLE_Msk (1UL << PMU_CTRL_CYCCNT_DISABLE_Pos) /*!< PMU CTRL: Disable Cycle Counter Mask */ + +#define PMU_CTRL_FRZ_ON_OV_Pos 9U /*!< PMU CTRL: Freeze-on-overflow Position */ +#define PMU_CTRL_FRZ_ON_OV_Msk (1UL << PMU_CTRL_FRZ_ON_OVERFLOW_Pos) /*!< PMU CTRL: Freeze-on-overflow Mask */ + +#define PMU_CTRL_TRACE_ON_OV_Pos 11U /*!< PMU CTRL: Trace-on-overflow Position */ +#define PMU_CTRL_TRACE_ON_OV_Msk (1UL << PMU_CTRL_TRACE_ON_OVERFLOW_Pos) /*!< PMU CTRL: Trace-on-overflow Mask */ + +/** \brief PMU Type Register Definitions */ + +#define PMU_TYPE_NUM_CNTS_Pos 0U /*!< PMU TYPE: Number of Counters Position */ +#define PMU_TYPE_NUM_CNTS_Msk (0xFFUL /*<< PMU_TYPE_NUM_CNTS_Pos*/) /*!< PMU TYPE: Number of Counters Mask */ + +#define PMU_TYPE_SIZE_CNTS_Pos 8U /*!< PMU TYPE: Size of Counters Position */ +#define PMU_TYPE_SIZE_CNTS_Msk (0x3FUL << PMU_TYPE_SIZE_CNTS_Pos) /*!< PMU TYPE: Size of Counters Mask */ + +#define PMU_TYPE_CYCCNT_PRESENT_Pos 14U /*!< PMU TYPE: Cycle Counter Present Position */ +#define PMU_TYPE_CYCCNT_PRESENT_Msk (1UL << PMU_TYPE_CYCCNT_PRESENT_Pos) /*!< PMU TYPE: Cycle Counter Present Mask */ + +#define PMU_TYPE_FRZ_OV_SUPPORT_Pos 21U /*!< PMU TYPE: Freeze-on-overflow Support Position */ +#define PMU_TYPE_FRZ_OV_SUPPORT_Msk (1UL << PMU_TYPE_FRZ_OV_SUPPORT_Pos) /*!< PMU TYPE: Freeze-on-overflow Support Mask */ + +#define PMU_TYPE_TRACE_ON_OV_SUPPORT_Pos 23U /*!< PMU TYPE: Trace-on-overflow Support Position */ +#define PMU_TYPE_TRACE_ON_OV_SUPPORT_Msk (1UL << PMU_TYPE_FRZ_OV_SUPPORT_Pos) /*!< PMU TYPE: Trace-on-overflow Support Mask */ + +/** \brief PMU Authentication Status Register Definitions */ + +#define PMU_AUTHSTATUS_NSID_Pos 0U /*!< PMU AUTHSTATUS: Non-secure Invasive Debug Position */ +#define PMU_AUTHSTATUS_NSID_Msk (0x3UL /*<< PMU_AUTHSTATUS_NSID_Pos*/) /*!< PMU AUTHSTATUS: Non-secure Invasive Debug Mask */ + +#define PMU_AUTHSTATUS_NSNID_Pos 2U /*!< PMU AUTHSTATUS: Non-secure Non-invasive Debug Position */ +#define PMU_AUTHSTATUS_NSNID_Msk (0x3UL << PMU_AUTHSTATUS_NSNID_Pos) /*!< PMU AUTHSTATUS: Non-secure Non-invasive Debug Mask */ + +#define PMU_AUTHSTATUS_SID_Pos 4U /*!< PMU AUTHSTATUS: Secure Invasive Debug Position */ +#define PMU_AUTHSTATUS_SID_Msk (0x3UL << PMU_AUTHSTATUS_SID_Pos) /*!< PMU AUTHSTATUS: Secure Invasive Debug Mask */ + +#define PMU_AUTHSTATUS_SNID_Pos 6U /*!< PMU AUTHSTATUS: Secure Non-invasive Debug Position */ +#define PMU_AUTHSTATUS_SNID_Msk (0x3UL << PMU_AUTHSTATUS_SNID_Pos) /*!< PMU AUTHSTATUS: Secure Non-invasive Debug Mask */ + +#define PMU_AUTHSTATUS_NSUID_Pos 16U /*!< PMU AUTHSTATUS: Non-secure Unprivileged Invasive Debug Position */ +#define PMU_AUTHSTATUS_NSUID_Msk (0x3UL << PMU_AUTHSTATUS_NSUID_Pos) /*!< PMU AUTHSTATUS: Non-secure Unprivileged Invasive Debug Mask */ + +#define PMU_AUTHSTATUS_NSUNID_Pos 18U /*!< PMU AUTHSTATUS: Non-secure Unprivileged Non-invasive Debug Position */ +#define PMU_AUTHSTATUS_NSUNID_Msk (0x3UL << PMU_AUTHSTATUS_NSUNID_Pos) /*!< PMU AUTHSTATUS: Non-secure Unprivileged Non-invasive Debug Mask */ + +#define PMU_AUTHSTATUS_SUID_Pos 20U /*!< PMU AUTHSTATUS: Secure Unprivileged Invasive Debug Position */ +#define PMU_AUTHSTATUS_SUID_Msk (0x3UL << PMU_AUTHSTATUS_SUID_Pos) /*!< PMU AUTHSTATUS: Secure Unprivileged Invasive Debug Mask */ + +#define PMU_AUTHSTATUS_SUNID_Pos 22U /*!< PMU AUTHSTATUS: Secure Unprivileged Non-invasive Debug Position */ +#define PMU_AUTHSTATUS_SUNID_Msk (0x3UL << PMU_AUTHSTATUS_SUNID_Pos) /*!< PMU AUTHSTATUS: Secure Unprivileged Non-invasive Debug Mask */ + +/*@} end of group CMSIS_PMU */ +#endif + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */ + __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */ + __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */ + __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */ + uint32_t RESERVED0[1]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ +#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/* MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_PXN_Pos 4U /*!< MPU RLAR: PXN Position */ +#define MPU_RLAR_PXN_Msk (1UL << MPU_RLAR_PXN_Pos) /*!< MPU RLAR: PXN Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */ + +/* MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/* MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#else + uint32_t RESERVED0[3]; +#endif + __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */ +} SAU_Type; + +/* SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/* SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/* SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/* SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/* SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/* Secure Fault Status Register Definitions */ +#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */ +#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */ + +#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */ +#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */ + +#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */ +#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */ + +#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */ +#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */ + +#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */ +#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */ + +#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */ +#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */ + +#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */ +#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */ + +#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */ +#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and VFP Feature Register 2 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */ +#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */ + +#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */ +#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */ + +#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */ +#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */ + +#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */ +#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */ + +#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */ +#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */ + +#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */ +#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */ +#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */ +#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +#define FPU_FPDSCR_FZ16_Pos 19U /*!< FPDSCR: FZ16 bit Position */ +#define FPU_FPDSCR_FZ16_Msk (1UL << FPU_FPDSCR_FZ16_Pos) /*!< FPDSCR: FZ16 bit Mask */ + +#define FPU_FPDSCR_LTPSIZE_Pos 16U /*!< FPDSCR: LTPSIZE bit Position */ +#define FPU_FPDSCR_LTPSIZE_Msk (7UL << FPU_FPDSCR_LTPSIZE_Pos) /*!< FPDSCR: LTPSIZE bit Mask */ + +/* Media and VFP Feature Register 0 Definitions */ +#define FPU_MVFR0_FPRound_Pos 28U /*!< MVFR0: FPRound bits Position */ +#define FPU_MVFR0_FPRound_Msk (0xFUL << FPU_MVFR0_FPRound_Pos) /*!< MVFR0: FPRound bits Mask */ + +#define FPU_MVFR0_FPSqrt_Pos 20U /*!< MVFR0: FPSqrt bits Position */ +#define FPU_MVFR0_FPSqrt_Msk (0xFUL << FPU_MVFR0_FPSqrt_Pos) /*!< MVFR0: FPSqrt bits Mask */ + +#define FPU_MVFR0_FPDivide_Pos 16U /*!< MVFR0: FPDivide bits Position */ +#define FPU_MVFR0_FPDivide_Msk (0xFUL << FPU_MVFR0_FPDivide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FPDP_Pos 8U /*!< MVFR0: FPDP bits Position */ +#define FPU_MVFR0_FPDP_Msk (0xFUL << FPU_MVFR0_FPDP_Pos) /*!< MVFR0: FPDP bits Mask */ + +#define FPU_MVFR0_FPSP_Pos 4U /*!< MVFR0: FPSP bits Position */ +#define FPU_MVFR0_FPSP_Msk (0xFUL << FPU_MVFR0_FPSP_Pos) /*!< MVFR0: FPSP bits Mask */ + +#define FPU_MVFR0_SIMDReg_Pos 0U /*!< MVFR0: SIMDReg bits Position */ +#define FPU_MVFR0_SIMDReg_Msk (0xFUL /*<< FPU_MVFR0_SIMDReg_Pos*/) /*!< MVFR0: SIMDReg bits Mask */ + +/* Media and VFP Feature Register 1 Definitions */ +#define FPU_MVFR1_FMAC_Pos 28U /*!< MVFR1: FMAC bits Position */ +#define FPU_MVFR1_FMAC_Msk (0xFUL << FPU_MVFR1_FMAC_Pos) /*!< MVFR1: FMAC bits Mask */ + +#define FPU_MVFR1_FPHP_Pos 24U /*!< MVFR1: FPHP bits Position */ +#define FPU_MVFR1_FPHP_Msk (0xFUL << FPU_MVFR1_FPHP_Pos) /*!< MVFR1: FPHP bits Mask */ + +#define FPU_MVFR1_FP16_Pos 20U /*!< MVFR1: FP16 bits Position */ +#define FPU_MVFR1_FP16_Msk (0xFUL << FPU_MVFR1_FP16_Pos) /*!< MVFR1: FP16 bits Mask */ + +#define FPU_MVFR1_MVE_Pos 8U /*!< MVFR1: MVE bits Position */ +#define FPU_MVFR1_MVE_Msk (0xFUL << FPU_MVFR1_MVE_Pos) /*!< MVFR1: MVE bits Mask */ + +#define FPU_MVFR1_FPDNaN_Pos 4U /*!< MVFR1: FPDNaN bits Position */ +#define FPU_MVFR1_FPDNaN_Msk (0xFUL << FPU_MVFR1_FPDNaN_Pos) /*!< MVFR1: FPDNaN bits Mask */ + +#define FPU_MVFR1_FPFtZ_Pos 0U /*!< MVFR1: FPFtZ bits Position */ +#define FPU_MVFR1_FPFtZ_Msk (0xFUL /*<< FPU_MVFR1_FPFtZ_Pos*/) /*!< MVFR1: FPFtZ bits Mask */ + +/* Media and VFP Feature Register 2 Definitions */ +#define FPU_MVFR2_FPMisc_Pos 4U /*!< MVFR2: FPMisc bits Position */ +#define FPU_MVFR2_FPMisc_Msk (0xFUL << FPU_MVFR2_FPMisc_Pos) /*!< MVFR2: FPMisc bits Mask */ + +/*@} end of group CMSIS_FPU */ + +/* CoreDebug is deprecated. replaced by DCB (Debug Control Block) */ +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief \deprecated Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + __OM uint32_t DSCEMCR; /*!< Offset: 0x010 ( /W) Debug Set Clear Exception and Monitor Control Register */ + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< \deprecated CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< \deprecated CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Position */ +#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_FPD_Pos 23U /*!< \deprecated CoreDebug DHCSR: S_FPD Position */ +#define CoreDebug_DHCSR_S_FPD_Msk (1UL << CoreDebug_DHCSR_S_FPD_Pos) /*!< \deprecated CoreDebug DHCSR: S_FPD Mask */ + +#define CoreDebug_DHCSR_S_SUIDE_Pos 22U /*!< \deprecated CoreDebug DHCSR: S_SUIDE Position */ +#define CoreDebug_DHCSR_S_SUIDE_Msk (1UL << CoreDebug_DHCSR_S_SUIDE_Pos) /*!< \deprecated CoreDebug DHCSR: S_SUIDE Mask */ + +#define CoreDebug_DHCSR_S_NSUIDE_Pos 21U /*!< \deprecated CoreDebug DHCSR: S_NSUIDE Position */ +#define CoreDebug_DHCSR_S_NSUIDE_Msk (1UL << CoreDebug_DHCSR_S_NSUIDE_Pos) /*!< \deprecated CoreDebug DHCSR: S_NSUIDE Mask */ + +#define CoreDebug_DHCSR_S_SDE_Pos 20U /*!< \deprecated CoreDebug DHCSR: S_SDE Position */ +#define CoreDebug_DHCSR_S_SDE_Msk (1UL << CoreDebug_DHCSR_S_SDE_Pos) /*!< \deprecated CoreDebug DHCSR: S_SDE Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< \deprecated CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< \deprecated CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< \deprecated CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< \deprecated CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< \deprecated CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_PMOV_Pos 6U /*!< \deprecated CoreDebug DHCSR: C_PMOV Position */ +#define CoreDebug_DHCSR_C_PMOV_Msk (1UL << CoreDebug_DHCSR_C_PMOV_Pos) /*!< \deprecated CoreDebug DHCSR: C_PMOV Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< \deprecated CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< \deprecated CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< \deprecated CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< \deprecated CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< \deprecated CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< \deprecated CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< \deprecated CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< \deprecated CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< \deprecated CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< \deprecated CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< \deprecated CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< \deprecated CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< \deprecated CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< \deprecated CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< \deprecated CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< \deprecated CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< \deprecated CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< \deprecated CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< \deprecated CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< \deprecated CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< \deprecated CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< \deprecated CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< \deprecated CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< \deprecated CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< \deprecated CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Mask */ + +/* Debug Set Clear Exception and Monitor Control Register Definitions */ +#define CoreDebug_DSCEMCR_CLR_MON_REQ_Pos 19U /*!< \deprecated CoreDebug DSCEMCR: CLR_MON_REQ, Position */ +#define CoreDebug_DSCEMCR_CLR_MON_REQ_Msk (1UL << CoreDebug_DSCEMCR_CLR_MON_REQ_Pos) /*!< \deprecated CoreDebug DSCEMCR: CLR_MON_REQ, Mask */ + +#define CoreDebug_DSCEMCR_CLR_MON_PEND_Pos 17U /*!< \deprecated CoreDebug DSCEMCR: CLR_MON_PEND, Position */ +#define CoreDebug_DSCEMCR_CLR_MON_PEND_Msk (1UL << CoreDebug_DSCEMCR_CLR_MON_PEND_Pos) /*!< \deprecated CoreDebug DSCEMCR: CLR_MON_PEND, Mask */ + +#define CoreDebug_DSCEMCR_SET_MON_REQ_Pos 3U /*!< \deprecated CoreDebug DSCEMCR: SET_MON_REQ, Position */ +#define CoreDebug_DSCEMCR_SET_MON_REQ_Msk (1UL << CoreDebug_DSCEMCR_SET_MON_REQ_Pos) /*!< \deprecated CoreDebug DSCEMCR: SET_MON_REQ, Mask */ + +#define CoreDebug_DSCEMCR_SET_MON_PEND_Pos 1U /*!< \deprecated CoreDebug DSCEMCR: SET_MON_PEND, Position */ +#define CoreDebug_DSCEMCR_SET_MON_PEND_Msk (1UL << CoreDebug_DSCEMCR_SET_MON_PEND_Pos) /*!< \deprecated CoreDebug DSCEMCR: SET_MON_PEND, Mask */ + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_UIDEN_Pos 10U /*!< \deprecated CoreDebug DAUTHCTRL: UIDEN, Position */ +#define CoreDebug_DAUTHCTRL_UIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_UIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: UIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_UIDAPEN_Pos 9U /*!< \deprecated CoreDebug DAUTHCTRL: UIDAPEN, Position */ +#define CoreDebug_DAUTHCTRL_UIDAPEN_Msk (1UL << CoreDebug_DAUTHCTRL_UIDAPEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: UIDAPEN, Mask */ + +#define CoreDebug_DAUTHCTRL_FSDMA_Pos 8U /*!< \deprecated CoreDebug DAUTHCTRL: FSDMA, Position */ +#define CoreDebug_DAUTHCTRL_FSDMA_Msk (1UL << CoreDebug_DAUTHCTRL_FSDMA_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: FSDMA, Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Position */ +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Mask */ + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Mask */ + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos 16U /*!< \deprecated CoreDebug DSCSR: CDS Position */ +#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< \deprecated CoreDebug DSCSR: CDS Mask */ + +#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< \deprecated CoreDebug DSCSR: SBRSEL Position */ +#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< \deprecated CoreDebug DSCSR: SBRSEL Mask */ + +#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< \deprecated CoreDebug DSCSR: SBRSELEN Position */ +#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< \deprecated CoreDebug DSCSR: SBRSELEN Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DCB Debug Control Block + \brief Type definitions for the Debug Control Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Control Block Registers (DCB). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + __OM uint32_t DSCEMCR; /*!< Offset: 0x010 ( /W) Debug Set Clear Exception and Monitor Control Register */ + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} DCB_Type; + +/* DHCSR, Debug Halting Control and Status Register Definitions */ +#define DCB_DHCSR_DBGKEY_Pos 16U /*!< DCB DHCSR: Debug key Position */ +#define DCB_DHCSR_DBGKEY_Msk (0xFFFFUL << DCB_DHCSR_DBGKEY_Pos) /*!< DCB DHCSR: Debug key Mask */ + +#define DCB_DHCSR_S_RESTART_ST_Pos 26U /*!< DCB DHCSR: Restart sticky status Position */ +#define DCB_DHCSR_S_RESTART_ST_Msk (0x1UL << DCB_DHCSR_S_RESTART_ST_Pos) /*!< DCB DHCSR: Restart sticky status Mask */ + +#define DCB_DHCSR_S_RESET_ST_Pos 25U /*!< DCB DHCSR: Reset sticky status Position */ +#define DCB_DHCSR_S_RESET_ST_Msk (0x1UL << DCB_DHCSR_S_RESET_ST_Pos) /*!< DCB DHCSR: Reset sticky status Mask */ + +#define DCB_DHCSR_S_RETIRE_ST_Pos 24U /*!< DCB DHCSR: Retire sticky status Position */ +#define DCB_DHCSR_S_RETIRE_ST_Msk (0x1UL << DCB_DHCSR_S_RETIRE_ST_Pos) /*!< DCB DHCSR: Retire sticky status Mask */ + +#define DCB_DHCSR_S_FPD_Pos 23U /*!< DCB DHCSR: Floating-point registers Debuggable Position */ +#define DCB_DHCSR_S_FPD_Msk (0x1UL << DCB_DHCSR_S_FPD_Pos) /*!< DCB DHCSR: Floating-point registers Debuggable Mask */ + +#define DCB_DHCSR_S_SUIDE_Pos 22U /*!< DCB DHCSR: Secure unprivileged halting debug enabled Position */ +#define DCB_DHCSR_S_SUIDE_Msk (0x1UL << DCB_DHCSR_S_SUIDE_Pos) /*!< DCB DHCSR: Secure unprivileged halting debug enabled Mask */ + +#define DCB_DHCSR_S_NSUIDE_Pos 21U /*!< DCB DHCSR: Non-secure unprivileged halting debug enabled Position */ +#define DCB_DHCSR_S_NSUIDE_Msk (0x1UL << DCB_DHCSR_S_NSUIDE_Pos) /*!< DCB DHCSR: Non-secure unprivileged halting debug enabled Mask */ + +#define DCB_DHCSR_S_SDE_Pos 20U /*!< DCB DHCSR: Secure debug enabled Position */ +#define DCB_DHCSR_S_SDE_Msk (0x1UL << DCB_DHCSR_S_SDE_Pos) /*!< DCB DHCSR: Secure debug enabled Mask */ + +#define DCB_DHCSR_S_LOCKUP_Pos 19U /*!< DCB DHCSR: Lockup status Position */ +#define DCB_DHCSR_S_LOCKUP_Msk (0x1UL << DCB_DHCSR_S_LOCKUP_Pos) /*!< DCB DHCSR: Lockup status Mask */ + +#define DCB_DHCSR_S_SLEEP_Pos 18U /*!< DCB DHCSR: Sleeping status Position */ +#define DCB_DHCSR_S_SLEEP_Msk (0x1UL << DCB_DHCSR_S_SLEEP_Pos) /*!< DCB DHCSR: Sleeping status Mask */ + +#define DCB_DHCSR_S_HALT_Pos 17U /*!< DCB DHCSR: Halted status Position */ +#define DCB_DHCSR_S_HALT_Msk (0x1UL << DCB_DHCSR_S_HALT_Pos) /*!< DCB DHCSR: Halted status Mask */ + +#define DCB_DHCSR_S_REGRDY_Pos 16U /*!< DCB DHCSR: Register ready status Position */ +#define DCB_DHCSR_S_REGRDY_Msk (0x1UL << DCB_DHCSR_S_REGRDY_Pos) /*!< DCB DHCSR: Register ready status Mask */ + +#define DCB_DHCSR_C_PMOV_Pos 6U /*!< DCB DHCSR: Halt on PMU overflow control Position */ +#define DCB_DHCSR_C_PMOV_Msk (0x1UL << DCB_DHCSR_C_PMOV_Pos) /*!< DCB DHCSR: Halt on PMU overflow control Mask */ + +#define DCB_DHCSR_C_SNAPSTALL_Pos 5U /*!< DCB DHCSR: Snap stall control Position */ +#define DCB_DHCSR_C_SNAPSTALL_Msk (0x1UL << DCB_DHCSR_C_SNAPSTALL_Pos) /*!< DCB DHCSR: Snap stall control Mask */ + +#define DCB_DHCSR_C_MASKINTS_Pos 3U /*!< DCB DHCSR: Mask interrupts control Position */ +#define DCB_DHCSR_C_MASKINTS_Msk (0x1UL << DCB_DHCSR_C_MASKINTS_Pos) /*!< DCB DHCSR: Mask interrupts control Mask */ + +#define DCB_DHCSR_C_STEP_Pos 2U /*!< DCB DHCSR: Step control Position */ +#define DCB_DHCSR_C_STEP_Msk (0x1UL << DCB_DHCSR_C_STEP_Pos) /*!< DCB DHCSR: Step control Mask */ + +#define DCB_DHCSR_C_HALT_Pos 1U /*!< DCB DHCSR: Halt control Position */ +#define DCB_DHCSR_C_HALT_Msk (0x1UL << DCB_DHCSR_C_HALT_Pos) /*!< DCB DHCSR: Halt control Mask */ + +#define DCB_DHCSR_C_DEBUGEN_Pos 0U /*!< DCB DHCSR: Debug enable control Position */ +#define DCB_DHCSR_C_DEBUGEN_Msk (0x1UL /*<< DCB_DHCSR_C_DEBUGEN_Pos*/) /*!< DCB DHCSR: Debug enable control Mask */ + +/* DCRSR, Debug Core Register Select Register Definitions */ +#define DCB_DCRSR_REGWnR_Pos 16U /*!< DCB DCRSR: Register write/not-read Position */ +#define DCB_DCRSR_REGWnR_Msk (0x1UL << DCB_DCRSR_REGWnR_Pos) /*!< DCB DCRSR: Register write/not-read Mask */ + +#define DCB_DCRSR_REGSEL_Pos 0U /*!< DCB DCRSR: Register selector Position */ +#define DCB_DCRSR_REGSEL_Msk (0x7FUL /*<< DCB_DCRSR_REGSEL_Pos*/) /*!< DCB DCRSR: Register selector Mask */ + +/* DCRDR, Debug Core Register Data Register Definitions */ +#define DCB_DCRDR_DBGTMP_Pos 0U /*!< DCB DCRDR: Data temporary buffer Position */ +#define DCB_DCRDR_DBGTMP_Msk (0xFFFFFFFFUL /*<< DCB_DCRDR_DBGTMP_Pos*/) /*!< DCB DCRDR: Data temporary buffer Mask */ + +/* DEMCR, Debug Exception and Monitor Control Register Definitions */ +#define DCB_DEMCR_TRCENA_Pos 24U /*!< DCB DEMCR: Trace enable Position */ +#define DCB_DEMCR_TRCENA_Msk (0x1UL << DCB_DEMCR_TRCENA_Pos) /*!< DCB DEMCR: Trace enable Mask */ + +#define DCB_DEMCR_MONPRKEY_Pos 23U /*!< DCB DEMCR: Monitor pend req key Position */ +#define DCB_DEMCR_MONPRKEY_Msk (0x1UL << DCB_DEMCR_MONPRKEY_Pos) /*!< DCB DEMCR: Monitor pend req key Mask */ + +#define DCB_DEMCR_UMON_EN_Pos 21U /*!< DCB DEMCR: Unprivileged monitor enable Position */ +#define DCB_DEMCR_UMON_EN_Msk (0x1UL << DCB_DEMCR_UMON_EN_Pos) /*!< DCB DEMCR: Unprivileged monitor enable Mask */ + +#define DCB_DEMCR_SDME_Pos 20U /*!< DCB DEMCR: Secure DebugMonitor enable Position */ +#define DCB_DEMCR_SDME_Msk (0x1UL << DCB_DEMCR_SDME_Pos) /*!< DCB DEMCR: Secure DebugMonitor enable Mask */ + +#define DCB_DEMCR_MON_REQ_Pos 19U /*!< DCB DEMCR: Monitor request Position */ +#define DCB_DEMCR_MON_REQ_Msk (0x1UL << DCB_DEMCR_MON_REQ_Pos) /*!< DCB DEMCR: Monitor request Mask */ + +#define DCB_DEMCR_MON_STEP_Pos 18U /*!< DCB DEMCR: Monitor step Position */ +#define DCB_DEMCR_MON_STEP_Msk (0x1UL << DCB_DEMCR_MON_STEP_Pos) /*!< DCB DEMCR: Monitor step Mask */ + +#define DCB_DEMCR_MON_PEND_Pos 17U /*!< DCB DEMCR: Monitor pend Position */ +#define DCB_DEMCR_MON_PEND_Msk (0x1UL << DCB_DEMCR_MON_PEND_Pos) /*!< DCB DEMCR: Monitor pend Mask */ + +#define DCB_DEMCR_MON_EN_Pos 16U /*!< DCB DEMCR: Monitor enable Position */ +#define DCB_DEMCR_MON_EN_Msk (0x1UL << DCB_DEMCR_MON_EN_Pos) /*!< DCB DEMCR: Monitor enable Mask */ + +#define DCB_DEMCR_VC_SFERR_Pos 11U /*!< DCB DEMCR: Vector Catch SecureFault Position */ +#define DCB_DEMCR_VC_SFERR_Msk (0x1UL << DCB_DEMCR_VC_SFERR_Pos) /*!< DCB DEMCR: Vector Catch SecureFault Mask */ + +#define DCB_DEMCR_VC_HARDERR_Pos 10U /*!< DCB DEMCR: Vector Catch HardFault errors Position */ +#define DCB_DEMCR_VC_HARDERR_Msk (0x1UL << DCB_DEMCR_VC_HARDERR_Pos) /*!< DCB DEMCR: Vector Catch HardFault errors Mask */ + +#define DCB_DEMCR_VC_INTERR_Pos 9U /*!< DCB DEMCR: Vector Catch interrupt errors Position */ +#define DCB_DEMCR_VC_INTERR_Msk (0x1UL << DCB_DEMCR_VC_INTERR_Pos) /*!< DCB DEMCR: Vector Catch interrupt errors Mask */ + +#define DCB_DEMCR_VC_BUSERR_Pos 8U /*!< DCB DEMCR: Vector Catch BusFault errors Position */ +#define DCB_DEMCR_VC_BUSERR_Msk (0x1UL << DCB_DEMCR_VC_BUSERR_Pos) /*!< DCB DEMCR: Vector Catch BusFault errors Mask */ + +#define DCB_DEMCR_VC_STATERR_Pos 7U /*!< DCB DEMCR: Vector Catch state errors Position */ +#define DCB_DEMCR_VC_STATERR_Msk (0x1UL << DCB_DEMCR_VC_STATERR_Pos) /*!< DCB DEMCR: Vector Catch state errors Mask */ + +#define DCB_DEMCR_VC_CHKERR_Pos 6U /*!< DCB DEMCR: Vector Catch check errors Position */ +#define DCB_DEMCR_VC_CHKERR_Msk (0x1UL << DCB_DEMCR_VC_CHKERR_Pos) /*!< DCB DEMCR: Vector Catch check errors Mask */ + +#define DCB_DEMCR_VC_NOCPERR_Pos 5U /*!< DCB DEMCR: Vector Catch NOCP errors Position */ +#define DCB_DEMCR_VC_NOCPERR_Msk (0x1UL << DCB_DEMCR_VC_NOCPERR_Pos) /*!< DCB DEMCR: Vector Catch NOCP errors Mask */ + +#define DCB_DEMCR_VC_MMERR_Pos 4U /*!< DCB DEMCR: Vector Catch MemManage errors Position */ +#define DCB_DEMCR_VC_MMERR_Msk (0x1UL << DCB_DEMCR_VC_MMERR_Pos) /*!< DCB DEMCR: Vector Catch MemManage errors Mask */ + +#define DCB_DEMCR_VC_CORERESET_Pos 0U /*!< DCB DEMCR: Vector Catch Core reset Position */ +#define DCB_DEMCR_VC_CORERESET_Msk (0x1UL /*<< DCB_DEMCR_VC_CORERESET_Pos*/) /*!< DCB DEMCR: Vector Catch Core reset Mask */ + +/* DSCEMCR, Debug Set Clear Exception and Monitor Control Register Definitions */ +#define DCB_DSCEMCR_CLR_MON_REQ_Pos 19U /*!< DCB DSCEMCR: Clear monitor request Position */ +#define DCB_DSCEMCR_CLR_MON_REQ_Msk (0x1UL << DCB_DSCEMCR_CLR_MON_REQ_Pos) /*!< DCB DSCEMCR: Clear monitor request Mask */ + +#define DCB_DSCEMCR_CLR_MON_PEND_Pos 17U /*!< DCB DSCEMCR: Clear monitor pend Position */ +#define DCB_DSCEMCR_CLR_MON_PEND_Msk (0x1UL << DCB_DSCEMCR_CLR_MON_PEND_Pos) /*!< DCB DSCEMCR: Clear monitor pend Mask */ + +#define DCB_DSCEMCR_SET_MON_REQ_Pos 3U /*!< DCB DSCEMCR: Set monitor request Position */ +#define DCB_DSCEMCR_SET_MON_REQ_Msk (0x1UL << DCB_DSCEMCR_SET_MON_REQ_Pos) /*!< DCB DSCEMCR: Set monitor request Mask */ + +#define DCB_DSCEMCR_SET_MON_PEND_Pos 1U /*!< DCB DSCEMCR: Set monitor pend Position */ +#define DCB_DSCEMCR_SET_MON_PEND_Msk (0x1UL << DCB_DSCEMCR_SET_MON_PEND_Pos) /*!< DCB DSCEMCR: Set monitor pend Mask */ + +/* DAUTHCTRL, Debug Authentication Control Register Definitions */ +#define DCB_DAUTHCTRL_UIDEN_Pos 10U /*!< DCB DAUTHCTRL: Unprivileged Invasive Debug Enable Position */ +#define DCB_DAUTHCTRL_UIDEN_Msk (0x1UL << DCB_DAUTHCTRL_UIDEN_Pos) /*!< DCB DAUTHCTRL: Unprivileged Invasive Debug Enable Mask */ + +#define DCB_DAUTHCTRL_UIDAPEN_Pos 9U /*!< DCB DAUTHCTRL: Unprivileged Invasive DAP Access Enable Position */ +#define DCB_DAUTHCTRL_UIDAPEN_Msk (0x1UL << DCB_DAUTHCTRL_UIDAPEN_Pos) /*!< DCB DAUTHCTRL: Unprivileged Invasive DAP Access Enable Mask */ + +#define DCB_DAUTHCTRL_FSDMA_Pos 8U /*!< DCB DAUTHCTRL: Force Secure DebugMonitor Allowed Position */ +#define DCB_DAUTHCTRL_FSDMA_Msk (0x1UL << DCB_DAUTHCTRL_FSDMA_Pos) /*!< DCB DAUTHCTRL: Force Secure DebugMonitor Allowed Mask */ + +#define DCB_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPNIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPNIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPNIDENSEL_Msk (0x1UL << DCB_DAUTHCTRL_SPNIDENSEL_Pos) /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Mask */ + +#define DCB_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< DCB DAUTHCTRL: Secure invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPIDENSEL_Msk (0x1UL /*<< DCB_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< DCB DAUTHCTRL: Secure invasive debug enable select Mask */ + +/* DSCSR, Debug Security Control and Status Register Definitions */ +#define DCB_DSCSR_CDSKEY_Pos 17U /*!< DCB DSCSR: CDS write-enable key Position */ +#define DCB_DSCSR_CDSKEY_Msk (0x1UL << DCB_DSCSR_CDSKEY_Pos) /*!< DCB DSCSR: CDS write-enable key Mask */ + +#define DCB_DSCSR_CDS_Pos 16U /*!< DCB DSCSR: Current domain Secure Position */ +#define DCB_DSCSR_CDS_Msk (0x1UL << DCB_DSCSR_CDS_Pos) /*!< DCB DSCSR: Current domain Secure Mask */ + +#define DCB_DSCSR_SBRSEL_Pos 1U /*!< DCB DSCSR: Secure banked register select Position */ +#define DCB_DSCSR_SBRSEL_Msk (0x1UL << DCB_DSCSR_SBRSEL_Pos) /*!< DCB DSCSR: Secure banked register select Mask */ + +#define DCB_DSCSR_SBRSELEN_Pos 0U /*!< DCB DSCSR: Secure banked register select enable Position */ +#define DCB_DSCSR_SBRSELEN_Msk (0x1UL /*<< DCB_DSCSR_SBRSELEN_Pos*/) /*!< DCB DSCSR: Secure banked register select enable Mask */ + +/*@} end of group CMSIS_DCB */ + + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DIB Debug Identification Block + \brief Type definitions for the Debug Identification Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Identification Block Registers (DIB). + */ +typedef struct +{ + __OM uint32_t DLAR; /*!< Offset: 0x000 ( /W) SCS Software Lock Access Register */ + __IM uint32_t DLSR; /*!< Offset: 0x004 (R/ ) SCS Software Lock Status Register */ + __IM uint32_t DAUTHSTATUS; /*!< Offset: 0x008 (R/ ) Debug Authentication Status Register */ + __IM uint32_t DDEVARCH; /*!< Offset: 0x00C (R/ ) SCS Device Architecture Register */ + __IM uint32_t DDEVTYPE; /*!< Offset: 0x010 (R/ ) SCS Device Type Register */ +} DIB_Type; + +/* DLAR, SCS Software Lock Access Register Definitions */ +#define DIB_DLAR_KEY_Pos 0U /*!< DIB DLAR: KEY Position */ +#define DIB_DLAR_KEY_Msk (0xFFFFFFFFUL /*<< DIB_DLAR_KEY_Pos */) /*!< DIB DLAR: KEY Mask */ + +/* DLSR, SCS Software Lock Status Register Definitions */ +#define DIB_DLSR_nTT_Pos 2U /*!< DIB DLSR: Not thirty-two bit Position */ +#define DIB_DLSR_nTT_Msk (0x1UL << DIB_DLSR_nTT_Pos ) /*!< DIB DLSR: Not thirty-two bit Mask */ + +#define DIB_DLSR_SLK_Pos 1U /*!< DIB DLSR: Software Lock status Position */ +#define DIB_DLSR_SLK_Msk (0x1UL << DIB_DLSR_SLK_Pos ) /*!< DIB DLSR: Software Lock status Mask */ + +#define DIB_DLSR_SLI_Pos 0U /*!< DIB DLSR: Software Lock implemented Position */ +#define DIB_DLSR_SLI_Msk (0x1UL /*<< DIB_DLSR_SLI_Pos*/) /*!< DIB DLSR: Software Lock implemented Mask */ + +/* DAUTHSTATUS, Debug Authentication Status Register Definitions */ +#define DIB_DAUTHSTATUS_SUNID_Pos 22U /*!< DIB DAUTHSTATUS: Secure Unprivileged Non-invasive Debug Allowed Position */ +#define DIB_DAUTHSTATUS_SUNID_Msk (0x3UL << DIB_DAUTHSTATUS_SUNID_Pos ) /*!< DIB DAUTHSTATUS: Secure Unprivileged Non-invasive Debug Allowed Mask */ + +#define DIB_DAUTHSTATUS_SUID_Pos 20U /*!< DIB DAUTHSTATUS: Secure Unprivileged Invasive Debug Allowed Position */ +#define DIB_DAUTHSTATUS_SUID_Msk (0x3UL << DIB_DAUTHSTATUS_SUID_Pos ) /*!< DIB DAUTHSTATUS: Secure Unprivileged Invasive Debug Allowed Mask */ + +#define DIB_DAUTHSTATUS_NSUNID_Pos 18U /*!< DIB DAUTHSTATUS: Non-secure Unprivileged Non-invasive Debug Allo Position */ +#define DIB_DAUTHSTATUS_NSUNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSUNID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Unprivileged Non-invasive Debug Allo Mask */ + +#define DIB_DAUTHSTATUS_NSUID_Pos 16U /*!< DIB DAUTHSTATUS: Non-secure Unprivileged Invasive Debug Allowed Position */ +#define DIB_DAUTHSTATUS_NSUID_Msk (0x3UL << DIB_DAUTHSTATUS_NSUID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Unprivileged Invasive Debug Allowed Mask */ + +#define DIB_DAUTHSTATUS_SNID_Pos 6U /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_SNID_Msk (0x3UL << DIB_DAUTHSTATUS_SNID_Pos ) /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_SID_Pos 4U /*!< DIB DAUTHSTATUS: Secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_SID_Msk (0x3UL << DIB_DAUTHSTATUS_SID_Pos ) /*!< DIB DAUTHSTATUS: Secure Invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSNID_Pos 2U /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSNID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSID_Pos 0U /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSID_Msk (0x3UL /*<< DIB_DAUTHSTATUS_NSID_Pos*/) /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Mask */ + +/* DDEVARCH, SCS Device Architecture Register Definitions */ +#define DIB_DDEVARCH_ARCHITECT_Pos 21U /*!< DIB DDEVARCH: Architect Position */ +#define DIB_DDEVARCH_ARCHITECT_Msk (0x7FFUL << DIB_DDEVARCH_ARCHITECT_Pos ) /*!< DIB DDEVARCH: Architect Mask */ + +#define DIB_DDEVARCH_PRESENT_Pos 20U /*!< DIB DDEVARCH: DEVARCH Present Position */ +#define DIB_DDEVARCH_PRESENT_Msk (0x1FUL << DIB_DDEVARCH_PRESENT_Pos ) /*!< DIB DDEVARCH: DEVARCH Present Mask */ + +#define DIB_DDEVARCH_REVISION_Pos 16U /*!< DIB DDEVARCH: Revision Position */ +#define DIB_DDEVARCH_REVISION_Msk (0xFUL << DIB_DDEVARCH_REVISION_Pos ) /*!< DIB DDEVARCH: Revision Mask */ + +#define DIB_DDEVARCH_ARCHVER_Pos 12U /*!< DIB DDEVARCH: Architecture Version Position */ +#define DIB_DDEVARCH_ARCHVER_Msk (0xFUL << DIB_DDEVARCH_ARCHVER_Pos ) /*!< DIB DDEVARCH: Architecture Version Mask */ + +#define DIB_DDEVARCH_ARCHPART_Pos 0U /*!< DIB DDEVARCH: Architecture Part Position */ +#define DIB_DDEVARCH_ARCHPART_Msk (0xFFFUL /*<< DIB_DDEVARCH_ARCHPART_Pos*/) /*!< DIB DDEVARCH: Architecture Part Mask */ + +/* DDEVTYPE, SCS Device Type Register Definitions */ +#define DIB_DDEVTYPE_SUB_Pos 4U /*!< DIB DDEVTYPE: Sub-type Position */ +#define DIB_DDEVTYPE_SUB_Msk (0xFUL << DIB_DDEVTYPE_SUB_Pos ) /*!< DIB DDEVTYPE: Sub-type Mask */ + +#define DIB_DDEVTYPE_MAJOR_Pos 0U /*!< DIB DDEVTYPE: Major type Position */ +#define DIB_DDEVTYPE_MAJOR_Msk (0xFUL /*<< DIB_DDEVTYPE_MAJOR_Pos*/) /*!< DIB DDEVTYPE: Major type Mask */ + + +/*@} end of group CMSIS_DIB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ + #define CoreDebug_BASE (0xE000EDF0UL) /*!< \deprecated Core Debug Base Address */ + #define DCB_BASE (0xE000EDF0UL) /*!< DCB Base Address */ + #define DIB_BASE (0xE000EFB0UL) /*!< DIB Base Address */ + #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ + #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ + #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ + #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ + #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ + #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ + #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< \deprecated Core Debug configuration struct */ + #define DCB ((DCB_Type *) DCB_BASE ) /*!< DCB configuration struct */ + #define DIB ((DIB_Type *) DIB_BASE ) /*!< DIB configuration struct */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ + #endif + + #if defined (__PMU_PRESENT) && (__PMU_PRESENT == 1U) + #define PMU_BASE (0xE0003000UL) /*!< PMU Base Address */ + #define PMU ((PMU_Type *) PMU_BASE ) /*!< PMU configuration struct */ + #endif + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ + #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ + #endif + + #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ + #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ + #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< \deprecated Core Debug Base Address (non-secure address space) */ + #define DCB_BASE_NS (0xE002EDF0UL) /*!< DCB Base Address (non-secure address space) */ + #define DIB_BASE_NS (0xE002EFB0UL) /*!< DIB Base Address (non-secure address space) */ + #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ + #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ + #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + + #define SCnSCB_NS ((SCnSCB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */ + #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ + #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ + #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ + #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< \deprecated Core Debug configuration struct (non-secure address space) */ + #define DCB_NS ((DCB_Type *) DCB_BASE_NS ) /*!< DCB configuration struct (non-secure address space) */ + #define DIB_NS ((DIB_Type *) DIB_BASE_NS ) /*!< DIB configuration struct (non-secure address space) */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ + #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ + #endif + + #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */ + #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */ + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_register_aliases Backwards Compatibility Aliases + \brief Register alias definitions for backwards compatibility. + @{ + */ +#define ID_ADR (ID_AFR) /*!< SCB Auxiliary Feature Register */ +/*@} */ + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* Special LR values for Secure/Non-Secure call handling and exception handling */ + +/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ +#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ + +/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ +#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ +#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ +#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ +#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ +#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ +#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */ +#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ + +/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ +#else +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ +#endif + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + __DSB(); +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Priority Grouping (non-secure) + \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB_NS->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB_NS->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping (non-secure) + \details Reads the priority grouping field from the non-secure NVIC when in secure state. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void) +{ + return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv8.h" + +#endif + +/* ########################## PMU functions and events #################################### */ + +#if defined (__PMU_PRESENT) && (__PMU_PRESENT == 1U) + +#include "pmu_armv8.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = FPU->MVFR0; + if ((mvfr0 & (FPU_MVFR0_FPSP_Msk | FPU_MVFR0_FPDP_Msk)) == 0x220U) + { + return 2U; /* Double + Single precision FPU */ + } + else if ((mvfr0 & (FPU_MVFR0_FPSP_Msk | FPU_MVFR0_FPDP_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + +/* ########################## MVE functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_MveFunctions MVE Functions + \brief Function that provides MVE type. + @{ + */ + +/** + \brief get MVE type + \details returns the MVE type + \returns + - \b 0: No Vector Extension (MVE) + - \b 1: Integer Vector Extension (MVE-I) + - \b 2: Floating-point Vector Extension (MVE-F) + */ +__STATIC_INLINE uint32_t SCB_GetMVEType(void) +{ + const uint32_t mvfr1 = FPU->MVFR1; + if ((mvfr1 & FPU_MVFR1_MVE_Msk) == (0x2U << FPU_MVFR1_MVE_Pos)) + { + return 2U; + } + else if ((mvfr1 & FPU_MVFR1_MVE_Msk) == (0x1U << FPU_MVFR1_MVE_Pos)) + { + return 1U; + } + else + { + return 0U; + } +} + + +/*@} end of CMSIS_Core_MveFunctions */ + + +/* ########################## Cache functions #################################### */ + +#if ((defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)) || \ + (defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U))) +#include "cachel1_armv7.h" +#endif + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + + +/* ################################## Debug Control function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DCBFunctions Debug Control Functions + \brief Functions that access the Debug Control Block. + @{ + */ + + +/** + \brief Set Debug Authentication Control Register + \details writes to Debug Authentication Control register. + \param [in] value value to be writen. + */ +__STATIC_INLINE void DCB_SetAuthCtrl(uint32_t value) +{ + __DSB(); + __ISB(); + DCB->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register + \details Reads Debug Authentication Control register. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t DCB_GetAuthCtrl(void) +{ + return (DCB->DAUTHCTRL); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Debug Authentication Control Register (non-secure) + \details writes to non-secure Debug Authentication Control register when in secure state. + \param [in] value value to be writen + */ +__STATIC_INLINE void TZ_DCB_SetAuthCtrl_NS(uint32_t value) +{ + __DSB(); + __ISB(); + DCB_NS->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register (non-secure) + \details Reads non-secure Debug Authentication Control register when in secure state. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t TZ_DCB_GetAuthCtrl_NS(void) +{ + return (DCB_NS->DAUTHCTRL); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## Debug Identification function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DIBFunctions Debug Identification Functions + \brief Functions that access the Debug Identification Block. + @{ + */ + + +/** + \brief Get Debug Authentication Status Register + \details Reads Debug Authentication Status register. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t DIB_GetAuthStatus(void) +{ + return (DIB->DAUTHSTATUS); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Debug Authentication Status Register (non-secure) + \details Reads non-secure Debug Authentication Status register when in secure state. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t TZ_DIB_GetAuthStatus_NS(void) +{ + return (DIB_NS->DAUTHSTATUS); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_ARMV81MML_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/CMSIS/Core/Include/core_armv8mbl.h b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/CMSIS/Core/Include/core_armv8mbl.h new file mode 100644 index 0000000000..e9c9b5bf59 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/CMSIS/Core/Include/core_armv8mbl.h @@ -0,0 +1,2222 @@ +/**************************************************************************//** + * @file core_armv8mbl.h + * @brief CMSIS Armv8-M Baseline Core Peripheral Access Layer Header File + * @version V5.1.0 + * @date 27. March 2020 + ******************************************************************************/ +/* + * Copyright (c) 2009-2020 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#elif defined ( __GNUC__ ) + #pragma GCC diagnostic ignored "-Wpedantic" /* disable pedantic warning due to unnamed structs/unions */ +#endif + +#ifndef __CORE_ARMV8MBL_H_GENERIC +#define __CORE_ARMV8MBL_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_ARMv8MBL + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS definitions */ +#define __ARMv8MBL_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __ARMv8MBL_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __ARMv8MBL_CMSIS_VERSION ((__ARMv8MBL_CMSIS_VERSION_MAIN << 16U) | \ + __ARMv8MBL_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (2U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_ARMV8MBL_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_ARMV8MBL_H_DEPENDANT +#define __CORE_ARMV8MBL_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __ARMv8MBL_REV + #define __ARMv8MBL_REV 0x0000U + #warning "__ARMv8MBL_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 0U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif + + #ifndef __ETM_PRESENT + #define __ETM_PRESENT 0U + #warning "__ETM_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MTB_PRESENT + #define __MTB_PRESENT 0U + #warning "__MTB_PRESENT not defined in device header file; using default!" + #endif + +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group ARMv8MBL */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core SAU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint32_t IPR[124U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ +#else + uint32_t RESERVED0; +#endif + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IOM uint32_t SHPR[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ +#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#endif + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + uint32_t RESERVED0[6U]; + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED14[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED15[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED16[1U]; + __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ + uint32_t RESERVED17[1U]; + __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ + uint32_t RESERVED18[1U]; + __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ + uint32_t RESERVED19[1U]; + __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ + uint32_t RESERVED20[1U]; + __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ + uint32_t RESERVED21[1U]; + __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ + uint32_t RESERVED22[1U]; + __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ + uint32_t RESERVED23[1U]; + __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ + uint32_t RESERVED24[1U]; + __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ + uint32_t RESERVED25[1U]; + __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ + uint32_t RESERVED26[1U]; + __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ + uint32_t RESERVED27[1U]; + __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ + uint32_t RESERVED28[1U]; + __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ + uint32_t RESERVED29[1U]; + __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ + uint32_t RESERVED30[1U]; + __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ + uint32_t RESERVED31[1U]; + __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x3UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Sizes Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Sizes Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ + uint32_t RESERVED3[809U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) Software Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) Software Lock Status Register */ + uint32_t RESERVED4[4U]; + __IM uint32_t TYPE; /*!< Offset: 0xFC8 (R/ ) Device Identifier Register */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Register */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_SWOSCALER_Pos 0U /*!< TPI ACPR: SWOSCALER Position */ +#define TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/) /*!< TPI ACPR: SWOSCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ +#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI Periodic Synchronization Control Register Definitions */ +#define TPI_PSCR_PSCount_Pos 0U /*!< TPI PSCR: PSCount Position */ +#define TPI_PSCR_PSCount_Msk (0x1FUL /*<< TPI_PSCR_PSCount_Pos*/) /*!< TPI PSCR: TPSCount Mask */ + +/* TPI Software Lock Status Register Definitions */ +#define TPI_LSR_nTT_Pos 1U /*!< TPI LSR: Not thirty-two bit. Position */ +#define TPI_LSR_nTT_Msk (0x1UL << TPI_LSR_nTT_Pos) /*!< TPI LSR: Not thirty-two bit. Mask */ + +#define TPI_LSR_SLK_Pos 1U /*!< TPI LSR: Software Lock status Position */ +#define TPI_LSR_SLK_Msk (0x1UL << TPI_LSR_SLK_Pos) /*!< TPI LSR: Software Lock status Mask */ + +#define TPI_LSR_SLI_Pos 0U /*!< TPI LSR: Software Lock implemented Position */ +#define TPI_LSR_SLI_Msk (0x1UL /*<< TPI_LSR_SLI_Pos*/) /*!< TPI LSR: Software Lock implemented Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFO depth Position */ +#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFO depth Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + uint32_t RESERVED0[7U]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 1U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ +#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/* MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: EN Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: EN Mask */ + +/* MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/* MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#endif +} SAU_Type; + +/* SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/* SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/* SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/* SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/* SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/* CoreDebug is deprecated. replaced by DCB (Debug Control Block) */ +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief \deprecated Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED0[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< \deprecated CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< \deprecated CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Position */ +#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< \deprecated CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< \deprecated CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< \deprecated CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< \deprecated CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< \deprecated CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< \deprecated CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< \deprecated CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< \deprecated CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< \deprecated CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< \deprecated CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< \deprecated CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< \deprecated CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_DWTENA_Pos 24U /*!< \deprecated CoreDebug DEMCR: DWTENA Position */ +#define CoreDebug_DEMCR_DWTENA_Msk (1UL << CoreDebug_DEMCR_DWTENA_Pos) /*!< \deprecated CoreDebug DEMCR: DWTENA Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Mask */ + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Position */ +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Mask */ + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Mask */ + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos 16U /*!< \deprecated CoreDebug DSCSR: CDS Position */ +#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< \deprecated CoreDebug DSCSR: CDS Mask */ + +#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< \deprecated CoreDebug DSCSR: SBRSEL Position */ +#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< \deprecated CoreDebug DSCSR: SBRSEL Mask */ + +#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< \deprecated CoreDebug DSCSR: SBRSELEN Position */ +#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< \deprecated CoreDebug DSCSR: SBRSELEN Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DCB Debug Control Block + \brief Type definitions for the Debug Control Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Control Block Registers (DCB). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED0[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} DCB_Type; + +/* DHCSR, Debug Halting Control and Status Register Definitions */ +#define DCB_DHCSR_DBGKEY_Pos 16U /*!< DCB DHCSR: Debug key Position */ +#define DCB_DHCSR_DBGKEY_Msk (0xFFFFUL << DCB_DHCSR_DBGKEY_Pos) /*!< DCB DHCSR: Debug key Mask */ + +#define DCB_DHCSR_S_RESTART_ST_Pos 26U /*!< DCB DHCSR: Restart sticky status Position */ +#define DCB_DHCSR_S_RESTART_ST_Msk (0x1UL << DCB_DHCSR_S_RESTART_ST_Pos) /*!< DCB DHCSR: Restart sticky status Mask */ + +#define DCB_DHCSR_S_RESET_ST_Pos 25U /*!< DCB DHCSR: Reset sticky status Position */ +#define DCB_DHCSR_S_RESET_ST_Msk (0x1UL << DCB_DHCSR_S_RESET_ST_Pos) /*!< DCB DHCSR: Reset sticky status Mask */ + +#define DCB_DHCSR_S_RETIRE_ST_Pos 24U /*!< DCB DHCSR: Retire sticky status Position */ +#define DCB_DHCSR_S_RETIRE_ST_Msk (0x1UL << DCB_DHCSR_S_RETIRE_ST_Pos) /*!< DCB DHCSR: Retire sticky status Mask */ + +#define DCB_DHCSR_S_SDE_Pos 20U /*!< DCB DHCSR: Secure debug enabled Position */ +#define DCB_DHCSR_S_SDE_Msk (0x1UL << DCB_DHCSR_S_SDE_Pos) /*!< DCB DHCSR: Secure debug enabled Mask */ + +#define DCB_DHCSR_S_LOCKUP_Pos 19U /*!< DCB DHCSR: Lockup status Position */ +#define DCB_DHCSR_S_LOCKUP_Msk (0x1UL << DCB_DHCSR_S_LOCKUP_Pos) /*!< DCB DHCSR: Lockup status Mask */ + +#define DCB_DHCSR_S_SLEEP_Pos 18U /*!< DCB DHCSR: Sleeping status Position */ +#define DCB_DHCSR_S_SLEEP_Msk (0x1UL << DCB_DHCSR_S_SLEEP_Pos) /*!< DCB DHCSR: Sleeping status Mask */ + +#define DCB_DHCSR_S_HALT_Pos 17U /*!< DCB DHCSR: Halted status Position */ +#define DCB_DHCSR_S_HALT_Msk (0x1UL << DCB_DHCSR_S_HALT_Pos) /*!< DCB DHCSR: Halted status Mask */ + +#define DCB_DHCSR_S_REGRDY_Pos 16U /*!< DCB DHCSR: Register ready status Position */ +#define DCB_DHCSR_S_REGRDY_Msk (0x1UL << DCB_DHCSR_S_REGRDY_Pos) /*!< DCB DHCSR: Register ready status Mask */ + +#define DCB_DHCSR_C_MASKINTS_Pos 3U /*!< DCB DHCSR: Mask interrupts control Position */ +#define DCB_DHCSR_C_MASKINTS_Msk (0x1UL << DCB_DHCSR_C_MASKINTS_Pos) /*!< DCB DHCSR: Mask interrupts control Mask */ + +#define DCB_DHCSR_C_STEP_Pos 2U /*!< DCB DHCSR: Step control Position */ +#define DCB_DHCSR_C_STEP_Msk (0x1UL << DCB_DHCSR_C_STEP_Pos) /*!< DCB DHCSR: Step control Mask */ + +#define DCB_DHCSR_C_HALT_Pos 1U /*!< DCB DHCSR: Halt control Position */ +#define DCB_DHCSR_C_HALT_Msk (0x1UL << DCB_DHCSR_C_HALT_Pos) /*!< DCB DHCSR: Halt control Mask */ + +#define DCB_DHCSR_C_DEBUGEN_Pos 0U /*!< DCB DHCSR: Debug enable control Position */ +#define DCB_DHCSR_C_DEBUGEN_Msk (0x1UL /*<< DCB_DHCSR_C_DEBUGEN_Pos*/) /*!< DCB DHCSR: Debug enable control Mask */ + +/* DCRSR, Debug Core Register Select Register Definitions */ +#define DCB_DCRSR_REGWnR_Pos 16U /*!< DCB DCRSR: Register write/not-read Position */ +#define DCB_DCRSR_REGWnR_Msk (0x1UL << DCB_DCRSR_REGWnR_Pos) /*!< DCB DCRSR: Register write/not-read Mask */ + +#define DCB_DCRSR_REGSEL_Pos 0U /*!< DCB DCRSR: Register selector Position */ +#define DCB_DCRSR_REGSEL_Msk (0x7FUL /*<< DCB_DCRSR_REGSEL_Pos*/) /*!< DCB DCRSR: Register selector Mask */ + +/* DCRDR, Debug Core Register Data Register Definitions */ +#define DCB_DCRDR_DBGTMP_Pos 0U /*!< DCB DCRDR: Data temporary buffer Position */ +#define DCB_DCRDR_DBGTMP_Msk (0xFFFFFFFFUL /*<< DCB_DCRDR_DBGTMP_Pos*/) /*!< DCB DCRDR: Data temporary buffer Mask */ + +/* DEMCR, Debug Exception and Monitor Control Register Definitions */ +#define DCB_DEMCR_TRCENA_Pos 24U /*!< DCB DEMCR: Trace enable Position */ +#define DCB_DEMCR_TRCENA_Msk (0x1UL << DCB_DEMCR_TRCENA_Pos) /*!< DCB DEMCR: Trace enable Mask */ + +#define DCB_DEMCR_VC_HARDERR_Pos 10U /*!< DCB DEMCR: Vector Catch HardFault errors Position */ +#define DCB_DEMCR_VC_HARDERR_Msk (0x1UL << DCB_DEMCR_VC_HARDERR_Pos) /*!< DCB DEMCR: Vector Catch HardFault errors Mask */ + +#define DCB_DEMCR_VC_CORERESET_Pos 0U /*!< DCB DEMCR: Vector Catch Core reset Position */ +#define DCB_DEMCR_VC_CORERESET_Msk (0x1UL /*<< DCB_DEMCR_VC_CORERESET_Pos*/) /*!< DCB DEMCR: Vector Catch Core reset Mask */ + +/* DAUTHCTRL, Debug Authentication Control Register Definitions */ +#define DCB_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPNIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPNIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPNIDENSEL_Msk (0x1UL << DCB_DAUTHCTRL_SPNIDENSEL_Pos) /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Mask */ + +#define DCB_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< DCB DAUTHCTRL: Secure invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPIDENSEL_Msk (0x1UL /*<< DCB_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< DCB DAUTHCTRL: Secure invasive debug enable select Mask */ + +/* DSCSR, Debug Security Control and Status Register Definitions */ +#define DCB_DSCSR_CDSKEY_Pos 17U /*!< DCB DSCSR: CDS write-enable key Position */ +#define DCB_DSCSR_CDSKEY_Msk (0x1UL << DCB_DSCSR_CDSKEY_Pos) /*!< DCB DSCSR: CDS write-enable key Mask */ + +#define DCB_DSCSR_CDS_Pos 16U /*!< DCB DSCSR: Current domain Secure Position */ +#define DCB_DSCSR_CDS_Msk (0x1UL << DCB_DSCSR_CDS_Pos) /*!< DCB DSCSR: Current domain Secure Mask */ + +#define DCB_DSCSR_SBRSEL_Pos 1U /*!< DCB DSCSR: Secure banked register select Position */ +#define DCB_DSCSR_SBRSEL_Msk (0x1UL << DCB_DSCSR_SBRSEL_Pos) /*!< DCB DSCSR: Secure banked register select Mask */ + +#define DCB_DSCSR_SBRSELEN_Pos 0U /*!< DCB DSCSR: Secure banked register select enable Position */ +#define DCB_DSCSR_SBRSELEN_Msk (0x1UL /*<< DCB_DSCSR_SBRSELEN_Pos*/) /*!< DCB DSCSR: Secure banked register select enable Mask */ + +/*@} end of group CMSIS_DCB */ + + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DIB Debug Identification Block + \brief Type definitions for the Debug Identification Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Identification Block Registers (DIB). + */ +typedef struct +{ + __OM uint32_t DLAR; /*!< Offset: 0x000 ( /W) SCS Software Lock Access Register */ + __IM uint32_t DLSR; /*!< Offset: 0x004 (R/ ) SCS Software Lock Status Register */ + __IM uint32_t DAUTHSTATUS; /*!< Offset: 0x008 (R/ ) Debug Authentication Status Register */ + __IM uint32_t DDEVARCH; /*!< Offset: 0x00C (R/ ) SCS Device Architecture Register */ + __IM uint32_t DDEVTYPE; /*!< Offset: 0x010 (R/ ) SCS Device Type Register */ +} DIB_Type; + +/* DLAR, SCS Software Lock Access Register Definitions */ +#define DIB_DLAR_KEY_Pos 0U /*!< DIB DLAR: KEY Position */ +#define DIB_DLAR_KEY_Msk (0xFFFFFFFFUL /*<< DIB_DLAR_KEY_Pos */) /*!< DIB DLAR: KEY Mask */ + +/* DLSR, SCS Software Lock Status Register Definitions */ +#define DIB_DLSR_nTT_Pos 2U /*!< DIB DLSR: Not thirty-two bit Position */ +#define DIB_DLSR_nTT_Msk (0x1UL << DIB_DLSR_nTT_Pos ) /*!< DIB DLSR: Not thirty-two bit Mask */ + +#define DIB_DLSR_SLK_Pos 1U /*!< DIB DLSR: Software Lock status Position */ +#define DIB_DLSR_SLK_Msk (0x1UL << DIB_DLSR_SLK_Pos ) /*!< DIB DLSR: Software Lock status Mask */ + +#define DIB_DLSR_SLI_Pos 0U /*!< DIB DLSR: Software Lock implemented Position */ +#define DIB_DLSR_SLI_Msk (0x1UL /*<< DIB_DLSR_SLI_Pos*/) /*!< DIB DLSR: Software Lock implemented Mask */ + +/* DAUTHSTATUS, Debug Authentication Status Register Definitions */ +#define DIB_DAUTHSTATUS_SNID_Pos 6U /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_SNID_Msk (0x3UL << DIB_DAUTHSTATUS_SNID_Pos ) /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_SID_Pos 4U /*!< DIB DAUTHSTATUS: Secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_SID_Msk (0x3UL << DIB_DAUTHSTATUS_SID_Pos ) /*!< DIB DAUTHSTATUS: Secure Invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSNID_Pos 2U /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSNID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSID_Pos 0U /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSID_Msk (0x3UL /*<< DIB_DAUTHSTATUS_NSID_Pos*/) /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Mask */ + +/* DDEVARCH, SCS Device Architecture Register Definitions */ +#define DIB_DDEVARCH_ARCHITECT_Pos 21U /*!< DIB DDEVARCH: Architect Position */ +#define DIB_DDEVARCH_ARCHITECT_Msk (0x7FFUL << DIB_DDEVARCH_ARCHITECT_Pos ) /*!< DIB DDEVARCH: Architect Mask */ + +#define DIB_DDEVARCH_PRESENT_Pos 20U /*!< DIB DDEVARCH: DEVARCH Present Position */ +#define DIB_DDEVARCH_PRESENT_Msk (0x1FUL << DIB_DDEVARCH_PRESENT_Pos ) /*!< DIB DDEVARCH: DEVARCH Present Mask */ + +#define DIB_DDEVARCH_REVISION_Pos 16U /*!< DIB DDEVARCH: Revision Position */ +#define DIB_DDEVARCH_REVISION_Msk (0xFUL << DIB_DDEVARCH_REVISION_Pos ) /*!< DIB DDEVARCH: Revision Mask */ + +#define DIB_DDEVARCH_ARCHVER_Pos 12U /*!< DIB DDEVARCH: Architecture Version Position */ +#define DIB_DDEVARCH_ARCHVER_Msk (0xFUL << DIB_DDEVARCH_ARCHVER_Pos ) /*!< DIB DDEVARCH: Architecture Version Mask */ + +#define DIB_DDEVARCH_ARCHPART_Pos 0U /*!< DIB DDEVARCH: Architecture Part Position */ +#define DIB_DDEVARCH_ARCHPART_Msk (0xFFFUL /*<< DIB_DDEVARCH_ARCHPART_Pos*/) /*!< DIB DDEVARCH: Architecture Part Mask */ + +/* DDEVTYPE, SCS Device Type Register Definitions */ +#define DIB_DDEVTYPE_SUB_Pos 4U /*!< DIB DDEVTYPE: Sub-type Position */ +#define DIB_DDEVTYPE_SUB_Msk (0xFUL << DIB_DDEVTYPE_SUB_Pos ) /*!< DIB DDEVTYPE: Sub-type Mask */ + +#define DIB_DDEVTYPE_MAJOR_Pos 0U /*!< DIB DDEVTYPE: Major type Position */ +#define DIB_DDEVTYPE_MAJOR_Msk (0xFUL /*<< DIB_DDEVTYPE_MAJOR_Pos*/) /*!< DIB DDEVTYPE: Major type Mask */ + + +/*@} end of group CMSIS_DIB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ + #define CoreDebug_BASE (0xE000EDF0UL) /*!< \deprecated Core Debug Base Address */ + #define DCB_BASE (0xE000EDF0UL) /*!< DCB Base Address */ + #define DIB_BASE (0xE000EFB0UL) /*!< DIB Base Address */ + #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + + #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ + #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ + #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ + #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ + #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< \deprecated Core Debug configuration struct */ + #define DCB ((DCB_Type *) DCB_BASE ) /*!< DCB configuration struct */ + #define DIB ((DIB_Type *) DIB_BASE ) /*!< DIB configuration struct */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ + #endif + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ + #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ + #endif + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ + #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< \deprecated Core Debug Base Address (non-secure address space) */ + #define DCB_BASE_NS (0xE002EDF0UL) /*!< DCB Base Address (non-secure address space) */ + #define DIB_BASE_NS (0xE002EFB0UL) /*!< DIB Base Address (non-secure address space) */ + #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ + #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ + #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + + #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ + #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ + #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ + #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< \deprecated Core Debug configuration struct (non-secure address space) */ + #define DCB_NS ((DCB_Type *) DCB_BASE_NS ) /*!< DCB configuration struct (non-secure address space) */ + #define DIB_NS ((DIB_Type *) DIB_BASE_NS ) /*!< DIB configuration struct (non-secure address space) */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ + #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ + #endif + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* Special LR values for Secure/Non-Secure call handling and exception handling */ + +/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ +#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ + +/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ +#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ +#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ +#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ +#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ +#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ +#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */ +#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ + +/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ +#else +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ +#endif + + +/* Interrupt Priorities are WORD accessible only under Armv6-M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + +#define __NVIC_SetPriorityGrouping(X) (void)(X) +#define __NVIC_GetPriorityGrouping() (0U) + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + If VTOR is not present address 0 must be mapped to SRAM. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t *vectors = (uint32_t *)SCB->VTOR; +#else + uint32_t *vectors = (uint32_t *)0x0U; +#endif + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + __DSB(); +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t *vectors = (uint32_t *)SCB->VTOR; +#else + uint32_t *vectors = (uint32_t *)0x0U; +#endif + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC_NS->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB_NS->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB_NS->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB_NS->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv8.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + + +/* ################################## Debug Control function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DCBFunctions Debug Control Functions + \brief Functions that access the Debug Control Block. + @{ + */ + + +/** + \brief Set Debug Authentication Control Register + \details writes to Debug Authentication Control register. + \param [in] value value to be writen. + */ +__STATIC_INLINE void DCB_SetAuthCtrl(uint32_t value) +{ + __DSB(); + __ISB(); + DCB->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register + \details Reads Debug Authentication Control register. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t DCB_GetAuthCtrl(void) +{ + return (DCB->DAUTHCTRL); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Debug Authentication Control Register (non-secure) + \details writes to non-secure Debug Authentication Control register when in secure state. + \param [in] value value to be writen + */ +__STATIC_INLINE void TZ_DCB_SetAuthCtrl_NS(uint32_t value) +{ + __DSB(); + __ISB(); + DCB_NS->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register (non-secure) + \details Reads non-secure Debug Authentication Control register when in secure state. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t TZ_DCB_GetAuthCtrl_NS(void) +{ + return (DCB_NS->DAUTHCTRL); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## Debug Identification function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DIBFunctions Debug Identification Functions + \brief Functions that access the Debug Identification Block. + @{ + */ + + +/** + \brief Get Debug Authentication Status Register + \details Reads Debug Authentication Status register. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t DIB_GetAuthStatus(void) +{ + return (DIB->DAUTHSTATUS); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Debug Authentication Status Register (non-secure) + \details Reads non-secure Debug Authentication Status register when in secure state. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t TZ_DIB_GetAuthStatus_NS(void) +{ + return (DIB_NS->DAUTHSTATUS); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_ARMV8MBL_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/CMSIS/Core/Include/core_armv8mml.h b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/CMSIS/Core/Include/core_armv8mml.h new file mode 100644 index 0000000000..c119fbf242 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/CMSIS/Core/Include/core_armv8mml.h @@ -0,0 +1,3209 @@ +/**************************************************************************//** + * @file core_armv8mml.h + * @brief CMSIS Armv8-M Mainline Core Peripheral Access Layer Header File + * @version V5.2.3 + * @date 13. October 2021 + ******************************************************************************/ +/* + * Copyright (c) 2009-2021 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#elif defined ( __GNUC__ ) + #pragma GCC diagnostic ignored "-Wpedantic" /* disable pedantic warning due to unnamed structs/unions */ +#endif + +#ifndef __CORE_ARMV8MML_H_GENERIC +#define __CORE_ARMV8MML_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_ARMv8MML + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS Armv8MML definitions */ +#define __ARMv8MML_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __ARMv8MML_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __ARMv8MML_CMSIS_VERSION ((__ARMv8MML_CMSIS_VERSION_MAIN << 16U) | \ + __ARMv8MML_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (80U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_ARMV8MML_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_ARMV8MML_H_DEPENDANT +#define __CORE_ARMV8MML_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __ARMv8MML_REV + #define __ARMv8MML_REV 0x0000U + #warning "__ARMv8MML_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DSP_PRESENT + #define __DSP_PRESENT 0U + #warning "__DSP_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 1U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group ARMv8MML */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core SAU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ +#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */ + uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */ + uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */ +#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */ + +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED6[580U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ + __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ + __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ + __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */ + uint32_t RESERVED7[21U]; + __IOM uint32_t SFSR; /*!< Offset: 0x0E4 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x0E8 (R/W) Secure Fault Address Register */ + uint32_t RESERVED3[69U]; + __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ + uint32_t RESERVED4[15U]; + __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ + uint32_t RESERVED5[1U]; + __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ + uint32_t RESERVED6[1U]; + __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ + __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ + __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ + __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ + __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ + __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ + __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ + __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ + __OM uint32_t BPIALL; /*!< Offset: 0x278 ( /W) Branch Predictor Invalidate All */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ +#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */ +#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */ +#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */ + +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */ +#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_CFSR_MEMFAULTSR_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */ +#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/* SCB Non-Secure Access Control Register Definitions */ +#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */ +#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */ + +#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */ +#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */ + +#define SCB_NSACR_CPn_Pos 0U /*!< SCB NSACR: CPn Position */ +#define SCB_NSACR_CPn_Msk (1UL /*<< SCB_NSACR_CPn_Pos*/) /*!< SCB NSACR: CPn Mask */ + +/* SCB Cache Level ID Register Definitions */ +#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ +#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ + +#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ +#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ + +/* SCB Cache Type Register Definitions */ +#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ +#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ + +#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ +#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ + +#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ +#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ + +#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ +#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ + +#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ +#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ + +/* SCB Cache Size ID Register Definitions */ +#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ +#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ + +#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ +#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ + +#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ +#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ + +#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ +#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ + +#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ +#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ + +#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ +#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ + +#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ +#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ + +/* SCB Cache Size Selection Register Definitions */ +#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ +#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ + +#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ +#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ + +/* SCB Software Triggered Interrupt Register Definitions */ +#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ +#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ + +/* SCB D-Cache Invalidate by Set-way Register Definitions */ +#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ +#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ + +#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ +#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ + +/* SCB D-Cache Clean by Set-way Register Definitions */ +#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ +#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ + +#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ +#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ + +/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ +#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ +#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ + +#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ +#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ + __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */ + uint32_t RESERVED6[4U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Stimulus Port Register Definitions */ +#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */ +#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */ + +#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */ +#define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */ + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */ +#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */ + +#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */ +#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED14[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED15[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED16[1U]; + __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ + uint32_t RESERVED17[1U]; + __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ + uint32_t RESERVED18[1U]; + __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ + uint32_t RESERVED19[1U]; + __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ + uint32_t RESERVED20[1U]; + __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ + uint32_t RESERVED21[1U]; + __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ + uint32_t RESERVED22[1U]; + __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ + uint32_t RESERVED23[1U]; + __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ + uint32_t RESERVED24[1U]; + __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ + uint32_t RESERVED25[1U]; + __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ + uint32_t RESERVED26[1U]; + __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ + uint32_t RESERVED27[1U]; + __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ + uint32_t RESERVED28[1U]; + __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ + uint32_t RESERVED29[1U]; + __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ + uint32_t RESERVED30[1U]; + __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ + uint32_t RESERVED31[1U]; + __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ + uint32_t RESERVED32[934U]; + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ + uint32_t RESERVED33[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */ +#define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Sizes Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Sizes Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ + uint32_t RESERVED3[809U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) Software Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) Software Lock Status Register */ + uint32_t RESERVED4[4U]; + __IM uint32_t TYPE; /*!< Offset: 0xFC8 (R/ ) Device Identifier Register */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Register */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_SWOSCALER_Pos 0U /*!< TPI ACPR: SWOSCALER Position */ +#define TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/) /*!< TPI ACPR: SWOSCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ +#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI Periodic Synchronization Control Register Definitions */ +#define TPI_PSCR_PSCount_Pos 0U /*!< TPI PSCR: PSCount Position */ +#define TPI_PSCR_PSCount_Msk (0x1FUL /*<< TPI_PSCR_PSCount_Pos*/) /*!< TPI PSCR: TPSCount Mask */ + +/* TPI Software Lock Status Register Definitions */ +#define TPI_LSR_nTT_Pos 1U /*!< TPI LSR: Not thirty-two bit. Position */ +#define TPI_LSR_nTT_Msk (0x1UL << TPI_LSR_nTT_Pos) /*!< TPI LSR: Not thirty-two bit. Mask */ + +#define TPI_LSR_SLK_Pos 1U /*!< TPI LSR: Software Lock status Position */ +#define TPI_LSR_SLK_Msk (0x1UL << TPI_LSR_SLK_Pos) /*!< TPI LSR: Software Lock status Mask */ + +#define TPI_LSR_SLI_Pos 0U /*!< TPI LSR: Software Lock implemented Position */ +#define TPI_LSR_SLI_Msk (0x1UL /*<< TPI_LSR_SLI_Pos*/) /*!< TPI LSR: Software Lock implemented Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFO depth Position */ +#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFO depth Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */ + __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */ + __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */ + __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */ + uint32_t RESERVED0[1]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ +#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/* MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */ + +/* MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/* MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#else + uint32_t RESERVED0[3]; +#endif + __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */ +} SAU_Type; + +/* SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/* SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/* SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/* SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/* SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/* Secure Fault Status Register Definitions */ +#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */ +#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */ + +#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */ +#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */ + +#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */ +#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */ + +#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */ +#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */ + +#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */ +#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */ + +#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */ +#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */ + +#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */ +#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */ + +#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */ +#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and VFP Feature Register 2 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */ +#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */ + +#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */ +#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */ + +#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */ +#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */ + +#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */ +#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */ + +#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */ +#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */ + +#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */ +#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */ +#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */ +#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and VFP Feature Register 0 Definitions */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and VFP Feature Register 1 Definitions */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/* Media and VFP Feature Register 2 Definitions */ +#define FPU_MVFR2_FPMisc_Pos 4U /*!< MVFR2: FPMisc bits Position */ +#define FPU_MVFR2_FPMisc_Msk (0xFUL << FPU_MVFR2_FPMisc_Pos) /*!< MVFR2: FPMisc bits Mask */ + +/*@} end of group CMSIS_FPU */ + +/* CoreDebug is deprecated. replaced by DCB (Debug Control Block) */ +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief \deprecated Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED0[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< \deprecated CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< \deprecated CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Position */ +#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< \deprecated CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< \deprecated CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< \deprecated CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< \deprecated CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< \deprecated CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< \deprecated CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< \deprecated CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< \deprecated CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< \deprecated CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< \deprecated CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< \deprecated CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< \deprecated CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< \deprecated CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< \deprecated CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< \deprecated CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< \deprecated CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< \deprecated CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< \deprecated CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< \deprecated CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< \deprecated CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< \deprecated CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< \deprecated CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< \deprecated CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< \deprecated CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< \deprecated CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< \deprecated CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< \deprecated CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< \deprecated CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< \deprecated CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< \deprecated CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Mask */ + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Position */ +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Mask */ + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Mask */ + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos 16U /*!< \deprecated CoreDebug DSCSR: CDS Position */ +#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< \deprecated CoreDebug DSCSR: CDS Mask */ + +#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< \deprecated CoreDebug DSCSR: SBRSEL Position */ +#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< \deprecated CoreDebug DSCSR: SBRSEL Mask */ + +#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< \deprecated CoreDebug DSCSR: SBRSELEN Position */ +#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< \deprecated CoreDebug DSCSR: SBRSELEN Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DCB Debug Control Block + \brief Type definitions for the Debug Control Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Control Block Registers (DCB). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED0[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} DCB_Type; + +/* DHCSR, Debug Halting Control and Status Register Definitions */ +#define DCB_DHCSR_DBGKEY_Pos 16U /*!< DCB DHCSR: Debug key Position */ +#define DCB_DHCSR_DBGKEY_Msk (0xFFFFUL << DCB_DHCSR_DBGKEY_Pos) /*!< DCB DHCSR: Debug key Mask */ + +#define DCB_DHCSR_S_RESTART_ST_Pos 26U /*!< DCB DHCSR: Restart sticky status Position */ +#define DCB_DHCSR_S_RESTART_ST_Msk (0x1UL << DCB_DHCSR_S_RESTART_ST_Pos) /*!< DCB DHCSR: Restart sticky status Mask */ + +#define DCB_DHCSR_S_RESET_ST_Pos 25U /*!< DCB DHCSR: Reset sticky status Position */ +#define DCB_DHCSR_S_RESET_ST_Msk (0x1UL << DCB_DHCSR_S_RESET_ST_Pos) /*!< DCB DHCSR: Reset sticky status Mask */ + +#define DCB_DHCSR_S_RETIRE_ST_Pos 24U /*!< DCB DHCSR: Retire sticky status Position */ +#define DCB_DHCSR_S_RETIRE_ST_Msk (0x1UL << DCB_DHCSR_S_RETIRE_ST_Pos) /*!< DCB DHCSR: Retire sticky status Mask */ + +#define DCB_DHCSR_S_SDE_Pos 20U /*!< DCB DHCSR: Secure debug enabled Position */ +#define DCB_DHCSR_S_SDE_Msk (0x1UL << DCB_DHCSR_S_SDE_Pos) /*!< DCB DHCSR: Secure debug enabled Mask */ + +#define DCB_DHCSR_S_LOCKUP_Pos 19U /*!< DCB DHCSR: Lockup status Position */ +#define DCB_DHCSR_S_LOCKUP_Msk (0x1UL << DCB_DHCSR_S_LOCKUP_Pos) /*!< DCB DHCSR: Lockup status Mask */ + +#define DCB_DHCSR_S_SLEEP_Pos 18U /*!< DCB DHCSR: Sleeping status Position */ +#define DCB_DHCSR_S_SLEEP_Msk (0x1UL << DCB_DHCSR_S_SLEEP_Pos) /*!< DCB DHCSR: Sleeping status Mask */ + +#define DCB_DHCSR_S_HALT_Pos 17U /*!< DCB DHCSR: Halted status Position */ +#define DCB_DHCSR_S_HALT_Msk (0x1UL << DCB_DHCSR_S_HALT_Pos) /*!< DCB DHCSR: Halted status Mask */ + +#define DCB_DHCSR_S_REGRDY_Pos 16U /*!< DCB DHCSR: Register ready status Position */ +#define DCB_DHCSR_S_REGRDY_Msk (0x1UL << DCB_DHCSR_S_REGRDY_Pos) /*!< DCB DHCSR: Register ready status Mask */ + +#define DCB_DHCSR_C_SNAPSTALL_Pos 5U /*!< DCB DHCSR: Snap stall control Position */ +#define DCB_DHCSR_C_SNAPSTALL_Msk (0x1UL << DCB_DHCSR_C_SNAPSTALL_Pos) /*!< DCB DHCSR: Snap stall control Mask */ + +#define DCB_DHCSR_C_MASKINTS_Pos 3U /*!< DCB DHCSR: Mask interrupts control Position */ +#define DCB_DHCSR_C_MASKINTS_Msk (0x1UL << DCB_DHCSR_C_MASKINTS_Pos) /*!< DCB DHCSR: Mask interrupts control Mask */ + +#define DCB_DHCSR_C_STEP_Pos 2U /*!< DCB DHCSR: Step control Position */ +#define DCB_DHCSR_C_STEP_Msk (0x1UL << DCB_DHCSR_C_STEP_Pos) /*!< DCB DHCSR: Step control Mask */ + +#define DCB_DHCSR_C_HALT_Pos 1U /*!< DCB DHCSR: Halt control Position */ +#define DCB_DHCSR_C_HALT_Msk (0x1UL << DCB_DHCSR_C_HALT_Pos) /*!< DCB DHCSR: Halt control Mask */ + +#define DCB_DHCSR_C_DEBUGEN_Pos 0U /*!< DCB DHCSR: Debug enable control Position */ +#define DCB_DHCSR_C_DEBUGEN_Msk (0x1UL /*<< DCB_DHCSR_C_DEBUGEN_Pos*/) /*!< DCB DHCSR: Debug enable control Mask */ + +/* DCRSR, Debug Core Register Select Register Definitions */ +#define DCB_DCRSR_REGWnR_Pos 16U /*!< DCB DCRSR: Register write/not-read Position */ +#define DCB_DCRSR_REGWnR_Msk (0x1UL << DCB_DCRSR_REGWnR_Pos) /*!< DCB DCRSR: Register write/not-read Mask */ + +#define DCB_DCRSR_REGSEL_Pos 0U /*!< DCB DCRSR: Register selector Position */ +#define DCB_DCRSR_REGSEL_Msk (0x7FUL /*<< DCB_DCRSR_REGSEL_Pos*/) /*!< DCB DCRSR: Register selector Mask */ + +/* DCRDR, Debug Core Register Data Register Definitions */ +#define DCB_DCRDR_DBGTMP_Pos 0U /*!< DCB DCRDR: Data temporary buffer Position */ +#define DCB_DCRDR_DBGTMP_Msk (0xFFFFFFFFUL /*<< DCB_DCRDR_DBGTMP_Pos*/) /*!< DCB DCRDR: Data temporary buffer Mask */ + +/* DEMCR, Debug Exception and Monitor Control Register Definitions */ +#define DCB_DEMCR_TRCENA_Pos 24U /*!< DCB DEMCR: Trace enable Position */ +#define DCB_DEMCR_TRCENA_Msk (0x1UL << DCB_DEMCR_TRCENA_Pos) /*!< DCB DEMCR: Trace enable Mask */ + +#define DCB_DEMCR_MONPRKEY_Pos 23U /*!< DCB DEMCR: Monitor pend req key Position */ +#define DCB_DEMCR_MONPRKEY_Msk (0x1UL << DCB_DEMCR_MONPRKEY_Pos) /*!< DCB DEMCR: Monitor pend req key Mask */ + +#define DCB_DEMCR_UMON_EN_Pos 21U /*!< DCB DEMCR: Unprivileged monitor enable Position */ +#define DCB_DEMCR_UMON_EN_Msk (0x1UL << DCB_DEMCR_UMON_EN_Pos) /*!< DCB DEMCR: Unprivileged monitor enable Mask */ + +#define DCB_DEMCR_SDME_Pos 20U /*!< DCB DEMCR: Secure DebugMonitor enable Position */ +#define DCB_DEMCR_SDME_Msk (0x1UL << DCB_DEMCR_SDME_Pos) /*!< DCB DEMCR: Secure DebugMonitor enable Mask */ + +#define DCB_DEMCR_MON_REQ_Pos 19U /*!< DCB DEMCR: Monitor request Position */ +#define DCB_DEMCR_MON_REQ_Msk (0x1UL << DCB_DEMCR_MON_REQ_Pos) /*!< DCB DEMCR: Monitor request Mask */ + +#define DCB_DEMCR_MON_STEP_Pos 18U /*!< DCB DEMCR: Monitor step Position */ +#define DCB_DEMCR_MON_STEP_Msk (0x1UL << DCB_DEMCR_MON_STEP_Pos) /*!< DCB DEMCR: Monitor step Mask */ + +#define DCB_DEMCR_MON_PEND_Pos 17U /*!< DCB DEMCR: Monitor pend Position */ +#define DCB_DEMCR_MON_PEND_Msk (0x1UL << DCB_DEMCR_MON_PEND_Pos) /*!< DCB DEMCR: Monitor pend Mask */ + +#define DCB_DEMCR_MON_EN_Pos 16U /*!< DCB DEMCR: Monitor enable Position */ +#define DCB_DEMCR_MON_EN_Msk (0x1UL << DCB_DEMCR_MON_EN_Pos) /*!< DCB DEMCR: Monitor enable Mask */ + +#define DCB_DEMCR_VC_SFERR_Pos 11U /*!< DCB DEMCR: Vector Catch SecureFault Position */ +#define DCB_DEMCR_VC_SFERR_Msk (0x1UL << DCB_DEMCR_VC_SFERR_Pos) /*!< DCB DEMCR: Vector Catch SecureFault Mask */ + +#define DCB_DEMCR_VC_HARDERR_Pos 10U /*!< DCB DEMCR: Vector Catch HardFault errors Position */ +#define DCB_DEMCR_VC_HARDERR_Msk (0x1UL << DCB_DEMCR_VC_HARDERR_Pos) /*!< DCB DEMCR: Vector Catch HardFault errors Mask */ + +#define DCB_DEMCR_VC_INTERR_Pos 9U /*!< DCB DEMCR: Vector Catch interrupt errors Position */ +#define DCB_DEMCR_VC_INTERR_Msk (0x1UL << DCB_DEMCR_VC_INTERR_Pos) /*!< DCB DEMCR: Vector Catch interrupt errors Mask */ + +#define DCB_DEMCR_VC_BUSERR_Pos 8U /*!< DCB DEMCR: Vector Catch BusFault errors Position */ +#define DCB_DEMCR_VC_BUSERR_Msk (0x1UL << DCB_DEMCR_VC_BUSERR_Pos) /*!< DCB DEMCR: Vector Catch BusFault errors Mask */ + +#define DCB_DEMCR_VC_STATERR_Pos 7U /*!< DCB DEMCR: Vector Catch state errors Position */ +#define DCB_DEMCR_VC_STATERR_Msk (0x1UL << DCB_DEMCR_VC_STATERR_Pos) /*!< DCB DEMCR: Vector Catch state errors Mask */ + +#define DCB_DEMCR_VC_CHKERR_Pos 6U /*!< DCB DEMCR: Vector Catch check errors Position */ +#define DCB_DEMCR_VC_CHKERR_Msk (0x1UL << DCB_DEMCR_VC_CHKERR_Pos) /*!< DCB DEMCR: Vector Catch check errors Mask */ + +#define DCB_DEMCR_VC_NOCPERR_Pos 5U /*!< DCB DEMCR: Vector Catch NOCP errors Position */ +#define DCB_DEMCR_VC_NOCPERR_Msk (0x1UL << DCB_DEMCR_VC_NOCPERR_Pos) /*!< DCB DEMCR: Vector Catch NOCP errors Mask */ + +#define DCB_DEMCR_VC_MMERR_Pos 4U /*!< DCB DEMCR: Vector Catch MemManage errors Position */ +#define DCB_DEMCR_VC_MMERR_Msk (0x1UL << DCB_DEMCR_VC_MMERR_Pos) /*!< DCB DEMCR: Vector Catch MemManage errors Mask */ + +#define DCB_DEMCR_VC_CORERESET_Pos 0U /*!< DCB DEMCR: Vector Catch Core reset Position */ +#define DCB_DEMCR_VC_CORERESET_Msk (0x1UL /*<< DCB_DEMCR_VC_CORERESET_Pos*/) /*!< DCB DEMCR: Vector Catch Core reset Mask */ + +/* DAUTHCTRL, Debug Authentication Control Register Definitions */ +#define DCB_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPNIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPNIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPNIDENSEL_Msk (0x1UL << DCB_DAUTHCTRL_SPNIDENSEL_Pos) /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Mask */ + +#define DCB_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< DCB DAUTHCTRL: Secure invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPIDENSEL_Msk (0x1UL /*<< DCB_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< DCB DAUTHCTRL: Secure invasive debug enable select Mask */ + +/* DSCSR, Debug Security Control and Status Register Definitions */ +#define DCB_DSCSR_CDSKEY_Pos 17U /*!< DCB DSCSR: CDS write-enable key Position */ +#define DCB_DSCSR_CDSKEY_Msk (0x1UL << DCB_DSCSR_CDSKEY_Pos) /*!< DCB DSCSR: CDS write-enable key Mask */ + +#define DCB_DSCSR_CDS_Pos 16U /*!< DCB DSCSR: Current domain Secure Position */ +#define DCB_DSCSR_CDS_Msk (0x1UL << DCB_DSCSR_CDS_Pos) /*!< DCB DSCSR: Current domain Secure Mask */ + +#define DCB_DSCSR_SBRSEL_Pos 1U /*!< DCB DSCSR: Secure banked register select Position */ +#define DCB_DSCSR_SBRSEL_Msk (0x1UL << DCB_DSCSR_SBRSEL_Pos) /*!< DCB DSCSR: Secure banked register select Mask */ + +#define DCB_DSCSR_SBRSELEN_Pos 0U /*!< DCB DSCSR: Secure banked register select enable Position */ +#define DCB_DSCSR_SBRSELEN_Msk (0x1UL /*<< DCB_DSCSR_SBRSELEN_Pos*/) /*!< DCB DSCSR: Secure banked register select enable Mask */ + +/*@} end of group CMSIS_DCB */ + + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DIB Debug Identification Block + \brief Type definitions for the Debug Identification Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Identification Block Registers (DIB). + */ +typedef struct +{ + __OM uint32_t DLAR; /*!< Offset: 0x000 ( /W) SCS Software Lock Access Register */ + __IM uint32_t DLSR; /*!< Offset: 0x004 (R/ ) SCS Software Lock Status Register */ + __IM uint32_t DAUTHSTATUS; /*!< Offset: 0x008 (R/ ) Debug Authentication Status Register */ + __IM uint32_t DDEVARCH; /*!< Offset: 0x00C (R/ ) SCS Device Architecture Register */ + __IM uint32_t DDEVTYPE; /*!< Offset: 0x010 (R/ ) SCS Device Type Register */ +} DIB_Type; + +/* DLAR, SCS Software Lock Access Register Definitions */ +#define DIB_DLAR_KEY_Pos 0U /*!< DIB DLAR: KEY Position */ +#define DIB_DLAR_KEY_Msk (0xFFFFFFFFUL /*<< DIB_DLAR_KEY_Pos */) /*!< DIB DLAR: KEY Mask */ + +/* DLSR, SCS Software Lock Status Register Definitions */ +#define DIB_DLSR_nTT_Pos 2U /*!< DIB DLSR: Not thirty-two bit Position */ +#define DIB_DLSR_nTT_Msk (0x1UL << DIB_DLSR_nTT_Pos ) /*!< DIB DLSR: Not thirty-two bit Mask */ + +#define DIB_DLSR_SLK_Pos 1U /*!< DIB DLSR: Software Lock status Position */ +#define DIB_DLSR_SLK_Msk (0x1UL << DIB_DLSR_SLK_Pos ) /*!< DIB DLSR: Software Lock status Mask */ + +#define DIB_DLSR_SLI_Pos 0U /*!< DIB DLSR: Software Lock implemented Position */ +#define DIB_DLSR_SLI_Msk (0x1UL /*<< DIB_DLSR_SLI_Pos*/) /*!< DIB DLSR: Software Lock implemented Mask */ + +/* DAUTHSTATUS, Debug Authentication Status Register Definitions */ +#define DIB_DAUTHSTATUS_SNID_Pos 6U /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_SNID_Msk (0x3UL << DIB_DAUTHSTATUS_SNID_Pos ) /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_SID_Pos 4U /*!< DIB DAUTHSTATUS: Secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_SID_Msk (0x3UL << DIB_DAUTHSTATUS_SID_Pos ) /*!< DIB DAUTHSTATUS: Secure Invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSNID_Pos 2U /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSNID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSID_Pos 0U /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSID_Msk (0x3UL /*<< DIB_DAUTHSTATUS_NSID_Pos*/) /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Mask */ + +/* DDEVARCH, SCS Device Architecture Register Definitions */ +#define DIB_DDEVARCH_ARCHITECT_Pos 21U /*!< DIB DDEVARCH: Architect Position */ +#define DIB_DDEVARCH_ARCHITECT_Msk (0x7FFUL << DIB_DDEVARCH_ARCHITECT_Pos ) /*!< DIB DDEVARCH: Architect Mask */ + +#define DIB_DDEVARCH_PRESENT_Pos 20U /*!< DIB DDEVARCH: DEVARCH Present Position */ +#define DIB_DDEVARCH_PRESENT_Msk (0x1FUL << DIB_DDEVARCH_PRESENT_Pos ) /*!< DIB DDEVARCH: DEVARCH Present Mask */ + +#define DIB_DDEVARCH_REVISION_Pos 16U /*!< DIB DDEVARCH: Revision Position */ +#define DIB_DDEVARCH_REVISION_Msk (0xFUL << DIB_DDEVARCH_REVISION_Pos ) /*!< DIB DDEVARCH: Revision Mask */ + +#define DIB_DDEVARCH_ARCHVER_Pos 12U /*!< DIB DDEVARCH: Architecture Version Position */ +#define DIB_DDEVARCH_ARCHVER_Msk (0xFUL << DIB_DDEVARCH_ARCHVER_Pos ) /*!< DIB DDEVARCH: Architecture Version Mask */ + +#define DIB_DDEVARCH_ARCHPART_Pos 0U /*!< DIB DDEVARCH: Architecture Part Position */ +#define DIB_DDEVARCH_ARCHPART_Msk (0xFFFUL /*<< DIB_DDEVARCH_ARCHPART_Pos*/) /*!< DIB DDEVARCH: Architecture Part Mask */ + +/* DDEVTYPE, SCS Device Type Register Definitions */ +#define DIB_DDEVTYPE_SUB_Pos 4U /*!< DIB DDEVTYPE: Sub-type Position */ +#define DIB_DDEVTYPE_SUB_Msk (0xFUL << DIB_DDEVTYPE_SUB_Pos ) /*!< DIB DDEVTYPE: Sub-type Mask */ + +#define DIB_DDEVTYPE_MAJOR_Pos 0U /*!< DIB DDEVTYPE: Major type Position */ +#define DIB_DDEVTYPE_MAJOR_Msk (0xFUL /*<< DIB_DDEVTYPE_MAJOR_Pos*/) /*!< DIB DDEVTYPE: Major type Mask */ + + +/*@} end of group CMSIS_DIB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ + #define CoreDebug_BASE (0xE000EDF0UL) /*!< \deprecated Core Debug Base Address */ + #define DCB_BASE (0xE000EDF0UL) /*!< DCB Base Address */ + #define DIB_BASE (0xE000EFB0UL) /*!< DIB Base Address */ + #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ + #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ + #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ + #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ + #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ + #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ + #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< \deprecated Core Debug configuration struct */ + #define DCB ((DCB_Type *) DCB_BASE ) /*!< DCB configuration struct */ + #define DIB ((DIB_Type *) DIB_BASE ) /*!< DIB configuration struct */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ + #endif + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ + #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ + #endif + + #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ + #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ + #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< \deprecated Core Debug Base Address (non-secure address space) */ + #define DCB_BASE_NS (0xE002EDF0UL) /*!< DCB Base Address (non-secure address space) */ + #define DIB_BASE_NS (0xE002EFB0UL) /*!< DIB Base Address (non-secure address space) */ + #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ + #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ + #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + + #define SCnSCB_NS ((SCnSCB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */ + #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ + #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ + #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ + #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< \deprecated Core Debug configuration struct (non-secure address space) */ + #define DCB_NS ((DCB_Type *) DCB_BASE_NS ) /*!< DCB configuration struct (non-secure address space) */ + #define DIB_NS ((DIB_Type *) DIB_BASE_NS ) /*!< DIB configuration struct (non-secure address space) */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ + #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ + #endif + + #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */ + #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */ + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_register_aliases Backwards Compatibility Aliases + \brief Register alias definitions for backwards compatibility. + @{ + */ +#define ID_ADR (ID_AFR) /*!< SCB Auxiliary Feature Register */ +/*@} */ + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* Special LR values for Secure/Non-Secure call handling and exception handling */ + +/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ +#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ + +/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ +#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ +#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ +#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ +#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ +#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ +#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */ +#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ + +/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ +#else +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ +#endif + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + __DSB(); +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Priority Grouping (non-secure) + \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB_NS->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB_NS->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping (non-secure) + \details Reads the priority grouping field from the non-secure NVIC when in secure state. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void) +{ + return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv8.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = FPU->MVFR0; + if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U) + { + return 2U; /* Double + Single precision FPU */ + } + else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + +/* ########################## Cache functions #################################### */ + +#if ((defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)) || \ + (defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U))) +#include "cachel1_armv7.h" +#endif + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + + +/* ################################## Debug Control function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DCBFunctions Debug Control Functions + \brief Functions that access the Debug Control Block. + @{ + */ + + +/** + \brief Set Debug Authentication Control Register + \details writes to Debug Authentication Control register. + \param [in] value value to be writen. + */ +__STATIC_INLINE void DCB_SetAuthCtrl(uint32_t value) +{ + __DSB(); + __ISB(); + DCB->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register + \details Reads Debug Authentication Control register. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t DCB_GetAuthCtrl(void) +{ + return (DCB->DAUTHCTRL); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Debug Authentication Control Register (non-secure) + \details writes to non-secure Debug Authentication Control register when in secure state. + \param [in] value value to be writen + */ +__STATIC_INLINE void TZ_DCB_SetAuthCtrl_NS(uint32_t value) +{ + __DSB(); + __ISB(); + DCB_NS->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register (non-secure) + \details Reads non-secure Debug Authentication Control register when in secure state. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t TZ_DCB_GetAuthCtrl_NS(void) +{ + return (DCB_NS->DAUTHCTRL); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## Debug Identification function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DIBFunctions Debug Identification Functions + \brief Functions that access the Debug Identification Block. + @{ + */ + + +/** + \brief Get Debug Authentication Status Register + \details Reads Debug Authentication Status register. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t DIB_GetAuthStatus(void) +{ + return (DIB->DAUTHSTATUS); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Debug Authentication Status Register (non-secure) + \details Reads non-secure Debug Authentication Status register when in secure state. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t TZ_DIB_GetAuthStatus_NS(void) +{ + return (DIB_NS->DAUTHSTATUS); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_ARMV8MML_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/CMSIS/Core/Include/core_cm0.h b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/CMSIS/Core/Include/core_cm0.h new file mode 100644 index 0000000000..0a0ba223e1 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/CMSIS/Core/Include/core_cm0.h @@ -0,0 +1,952 @@ +/**************************************************************************//** + * @file core_cm0.h + * @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File + * @version V5.0.8 + * @date 21. August 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM0_H_GENERIC +#define __CORE_CM0_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M0 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM0 definitions */ +#define __CM0_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM0_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16U) | \ + __CM0_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (0U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM0_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM0_H_DEPENDANT +#define __CORE_CM0_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM0_REV + #define __CM0_REV 0x0000U + #warning "__CM0_REV not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M0 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t _reserved0:1; /*!< bit: 0 Reserved */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[31U]; + __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RESERVED1[31U]; + __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[31U]; + __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[31U]; + uint32_t RESERVED4[64U]; + __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + uint32_t RESERVED0; + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. + Therefore they are not covered by the Cortex-M0 header file. + @{ + */ +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ +/*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M0 */ + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ + + +/* Interrupt Priorities are WORD accessible only under Armv6-M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + +#define __NVIC_SetPriorityGrouping(X) (void)(X) +#define __NVIC_GetPriorityGrouping() (0U) + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + Address 0 must be mapped to SRAM. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)(NVIC_USER_IRQ_OFFSET << 2); /* point to 1st user interrupt */ + *(vectors + (int32_t)IRQn) = vector; /* use pointer arithmetic to access vector */ + /* ARM Application Note 321 states that the M0 does not require the architectural barrier */ +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)(NVIC_USER_IRQ_OFFSET << 2); /* point to 1st user interrupt */ + return *(vectors + (int32_t)IRQn); /* use pointer arithmetic to access vector */ +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM0_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/CMSIS/Core/Include/core_cm0plus.h b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/CMSIS/Core/Include/core_cm0plus.h new file mode 100644 index 0000000000..879a384124 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/CMSIS/Core/Include/core_cm0plus.h @@ -0,0 +1,1087 @@ +/**************************************************************************//** + * @file core_cm0plus.h + * @brief CMSIS Cortex-M0+ Core Peripheral Access Layer Header File + * @version V5.0.9 + * @date 21. August 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM0PLUS_H_GENERIC +#define __CORE_CM0PLUS_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex-M0+ + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM0+ definitions */ +#define __CM0PLUS_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM0PLUS_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM0PLUS_CMSIS_VERSION ((__CM0PLUS_CMSIS_VERSION_MAIN << 16U) | \ + __CM0PLUS_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (0U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM0PLUS_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM0PLUS_H_DEPENDANT +#define __CORE_CM0PLUS_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM0PLUS_REV + #define __CM0PLUS_REV 0x0000U + #warning "__CM0PLUS_REV not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 0U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex-M0+ */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core MPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[31U]; + __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RESERVED1[31U]; + __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[31U]; + __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[31U]; + uint32_t RESERVED4[64U]; + __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ +#else + uint32_t RESERVED0; +#endif + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) +/* SCB Interrupt Control State Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 8U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#endif + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ +} MPU_Type; + +#define MPU_TYPE_RALIASES 1U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 8U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. + Therefore they are not covered by the Cortex-M0+ header file. + @{ + */ +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ +/*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M0+ */ + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ + + +/* Interrupt Priorities are WORD accessible only under Armv6-M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + +#define __NVIC_SetPriorityGrouping(X) (void)(X) +#define __NVIC_GetPriorityGrouping() (0U) + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + If VTOR is not present address 0 must be mapped to SRAM. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; +#else + uint32_t *vectors = (uint32_t *)(NVIC_USER_IRQ_OFFSET << 2); /* point to 1st user interrupt */ + *(vectors + (int32_t)IRQn) = vector; /* use pointer arithmetic to access vector */ +#endif + /* ARM Application Note 321 states that the M0+ does not require the architectural barrier */ +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +#else + uint32_t *vectors = (uint32_t *)(NVIC_USER_IRQ_OFFSET << 2); /* point to 1st user interrupt */ + return *(vectors + (int32_t)IRQn); /* use pointer arithmetic to access vector */ +#endif +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv7.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM0PLUS_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/CMSIS/Core/Include/core_cm1.h b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/CMSIS/Core/Include/core_cm1.h new file mode 100644 index 0000000000..83b8fc6a0d --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/CMSIS/Core/Include/core_cm1.h @@ -0,0 +1,979 @@ +/**************************************************************************//** + * @file core_cm1.h + * @brief CMSIS Cortex-M1 Core Peripheral Access Layer Header File + * @version V1.0.1 + * @date 12. November 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM1_H_GENERIC +#define __CORE_CM1_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M1 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM1 definitions */ +#define __CM1_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM1_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM1_CMSIS_VERSION ((__CM1_CMSIS_VERSION_MAIN << 16U) | \ + __CM1_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (1U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM1_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM1_H_DEPENDANT +#define __CORE_CM1_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM1_REV + #define __CM1_REV 0x0100U + #warning "__CM1_REV not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M1 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t _reserved0:1; /*!< bit: 0 Reserved */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[31U]; + __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[31U]; + __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[31U]; + __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[31U]; + uint32_t RESERVED4[64U]; + __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + uint32_t RESERVED0; + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_ITCMUAEN_Pos 4U /*!< ACTLR: Instruction TCM Upper Alias Enable Position */ +#define SCnSCB_ACTLR_ITCMUAEN_Msk (1UL << SCnSCB_ACTLR_ITCMUAEN_Pos) /*!< ACTLR: Instruction TCM Upper Alias Enable Mask */ + +#define SCnSCB_ACTLR_ITCMLAEN_Pos 3U /*!< ACTLR: Instruction TCM Lower Alias Enable Position */ +#define SCnSCB_ACTLR_ITCMLAEN_Msk (1UL << SCnSCB_ACTLR_ITCMLAEN_Pos) /*!< ACTLR: Instruction TCM Lower Alias Enable Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Cortex-M1 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. + Therefore they are not covered by the Cortex-M1 header file. + @{ + */ +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ +/*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M1 */ + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ + + +/* Interrupt Priorities are WORD accessible only under Armv6-M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + +#define __NVIC_SetPriorityGrouping(X) (void)(X) +#define __NVIC_GetPriorityGrouping() (0U) + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + Address 0 must be mapped to SRAM. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)0x0U; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + /* ARM Application Note 321 states that the M1 does not require the architectural barrier */ +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)0x0U; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM1_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/CMSIS/Core/Include/core_cm23.h b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/CMSIS/Core/Include/core_cm23.h new file mode 100644 index 0000000000..f2cf49fb16 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/CMSIS/Core/Include/core_cm23.h @@ -0,0 +1,2297 @@ +/**************************************************************************//** + * @file core_cm23.h + * @brief CMSIS Cortex-M23 Core Peripheral Access Layer Header File + * @version V5.1.0 + * @date 11. February 2020 + ******************************************************************************/ +/* + * Copyright (c) 2009-2020 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#elif defined ( __GNUC__ ) + #pragma GCC diagnostic ignored "-Wpedantic" /* disable pedantic warning due to unnamed structs/unions */ +#endif + +#ifndef __CORE_CM23_H_GENERIC +#define __CORE_CM23_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M23 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS definitions */ +#define __CM23_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM23_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM23_CMSIS_VERSION ((__CM23_CMSIS_VERSION_MAIN << 16U) | \ + __CM23_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (23U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM23_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM23_H_DEPENDANT +#define __CORE_CM23_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM23_REV + #define __CM23_REV 0x0000U + #warning "__CM23_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 0U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif + + #ifndef __ETM_PRESENT + #define __ETM_PRESENT 0U + #warning "__ETM_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MTB_PRESENT + #define __MTB_PRESENT 0U + #warning "__MTB_PRESENT not defined in device header file; using default!" + #endif + +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M23 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core SAU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint32_t IPR[124U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ +#else + uint32_t RESERVED0; +#endif + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IOM uint32_t SHPR[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ +#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#endif + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + uint32_t RESERVED0[6U]; + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED14[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED15[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED16[1U]; + __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ + uint32_t RESERVED17[1U]; + __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ + uint32_t RESERVED18[1U]; + __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ + uint32_t RESERVED19[1U]; + __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ + uint32_t RESERVED20[1U]; + __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ + uint32_t RESERVED21[1U]; + __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ + uint32_t RESERVED22[1U]; + __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ + uint32_t RESERVED23[1U]; + __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ + uint32_t RESERVED24[1U]; + __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ + uint32_t RESERVED25[1U]; + __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ + uint32_t RESERVED26[1U]; + __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ + uint32_t RESERVED27[1U]; + __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ + uint32_t RESERVED28[1U]; + __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ + uint32_t RESERVED29[1U]; + __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ + uint32_t RESERVED30[1U]; + __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ + uint32_t RESERVED31[1U]; + __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x3UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t ITFTTD0; /*!< Offset: 0xEEC (R/ ) Integration Test FIFO Test Data 0 Register */ + __IOM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/W) Integration Test ATB Control Register 2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) Integration Test ATB Control Register 0 */ + __IM uint32_t ITFTTD1; /*!< Offset: 0xEFC (R/ ) Integration Test FIFO Test Data 1 Register */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) Device Configuration Register */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Identifier Register */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ +#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration Test FIFO Test Data 0 Register Definitions */ +#define TPI_ITFTTD0_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD0: ATB Interface 2 ATVALIDPosition */ +#define TPI_ITFTTD0_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 2 ATVALID Mask */ + +#define TPI_ITFTTD0_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD0: ATB Interface 2 byte count Position */ +#define TPI_ITFTTD0_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 2 byte count Mask */ + +#define TPI_ITFTTD0_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Position */ +#define TPI_ITFTTD0_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Mask */ + +#define TPI_ITFTTD0_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD0: ATB Interface 1 byte count Position */ +#define TPI_ITFTTD0_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 1 byte countt Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data2_Pos 16U /*!< TPI ITFTTD0: ATB Interface 1 data2 Position */ +#define TPI_ITFTTD0_ATB_IF1_data2_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data2 Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data1_Pos 8U /*!< TPI ITFTTD0: ATB Interface 1 data1 Position */ +#define TPI_ITFTTD0_ATB_IF1_data1_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data1 Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data0_Pos 0U /*!< TPI ITFTTD0: ATB Interface 1 data0 Position */ +#define TPI_ITFTTD0_ATB_IF1_data0_Msk (0xFFUL /*<< TPI_ITFTTD0_ATB_IF1_data0_Pos*/) /*!< TPI ITFTTD0: ATB Interface 1 data0 Mask */ + +/* TPI Integration Test ATB Control Register 2 Register Definitions */ +#define TPI_ITATBCTR2_AFVALID2S_Pos 1U /*!< TPI ITATBCTR2: AFVALID2S Position */ +#define TPI_ITATBCTR2_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID2S_Pos) /*!< TPI ITATBCTR2: AFVALID2SS Mask */ + +#define TPI_ITATBCTR2_AFVALID1S_Pos 1U /*!< TPI ITATBCTR2: AFVALID1S Position */ +#define TPI_ITATBCTR2_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID1S_Pos) /*!< TPI ITATBCTR2: AFVALID1SS Mask */ + +#define TPI_ITATBCTR2_ATREADY2S_Pos 0U /*!< TPI ITATBCTR2: ATREADY2S Position */ +#define TPI_ITATBCTR2_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2S_Pos*/) /*!< TPI ITATBCTR2: ATREADY2S Mask */ + +#define TPI_ITATBCTR2_ATREADY1S_Pos 0U /*!< TPI ITATBCTR2: ATREADY1S Position */ +#define TPI_ITATBCTR2_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1S_Pos*/) /*!< TPI ITATBCTR2: ATREADY1S Mask */ + +/* TPI Integration Test FIFO Test Data 1 Register Definitions */ +#define TPI_ITFTTD1_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Position */ +#define TPI_ITFTTD1_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Mask */ + +#define TPI_ITFTTD1_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD1: ATB Interface 2 byte count Position */ +#define TPI_ITFTTD1_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 2 byte count Mask */ + +#define TPI_ITFTTD1_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Position */ +#define TPI_ITFTTD1_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Mask */ + +#define TPI_ITFTTD1_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD1: ATB Interface 1 byte count Position */ +#define TPI_ITFTTD1_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 1 byte countt Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data2_Pos 16U /*!< TPI ITFTTD1: ATB Interface 2 data2 Position */ +#define TPI_ITFTTD1_ATB_IF2_data2_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data2 Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data1_Pos 8U /*!< TPI ITFTTD1: ATB Interface 2 data1 Position */ +#define TPI_ITFTTD1_ATB_IF2_data1_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data1 Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data0_Pos 0U /*!< TPI ITFTTD1: ATB Interface 2 data0 Position */ +#define TPI_ITFTTD1_ATB_IF2_data0_Msk (0xFFUL /*<< TPI_ITFTTD1_ATB_IF2_data0_Pos*/) /*!< TPI ITFTTD1: ATB Interface 2 data0 Mask */ + +/* TPI Integration Test ATB Control Register 0 Definitions */ +#define TPI_ITATBCTR0_AFVALID2S_Pos 1U /*!< TPI ITATBCTR0: AFVALID2S Position */ +#define TPI_ITATBCTR0_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID2S_Pos) /*!< TPI ITATBCTR0: AFVALID2SS Mask */ + +#define TPI_ITATBCTR0_AFVALID1S_Pos 1U /*!< TPI ITATBCTR0: AFVALID1S Position */ +#define TPI_ITATBCTR0_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID1S_Pos) /*!< TPI ITATBCTR0: AFVALID1SS Mask */ + +#define TPI_ITATBCTR0_ATREADY2S_Pos 0U /*!< TPI ITATBCTR0: ATREADY2S Position */ +#define TPI_ITATBCTR0_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2S_Pos*/) /*!< TPI ITATBCTR0: ATREADY2S Mask */ + +#define TPI_ITATBCTR0_ATREADY1S_Pos 0U /*!< TPI ITATBCTR0: ATREADY1S Position */ +#define TPI_ITATBCTR0_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1S_Pos*/) /*!< TPI ITATBCTR0: ATREADY1S Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFOSZ Position */ +#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFOSZ Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x3FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + uint32_t RESERVED0[7U]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 1U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ +#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/* MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: EN Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: EN Mask */ + +/* MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/* MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#endif +} SAU_Type; + +/* SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/* SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/* SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/* SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/* SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/* CoreDebug is deprecated. replaced by DCB (Debug Control Block) */ +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief \deprecated Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED0[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< \deprecated CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< \deprecated CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Position */ +#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< \deprecated CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< \deprecated CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< \deprecated CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< \deprecated CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< \deprecated CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< \deprecated CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< \deprecated CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< \deprecated CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< \deprecated CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< \deprecated CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< \deprecated CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< \deprecated CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register */ +#define CoreDebug_DEMCR_DWTENA_Pos 24U /*!< \deprecated CoreDebug DEMCR: DWTENA Position */ +#define CoreDebug_DEMCR_DWTENA_Msk (1UL << CoreDebug_DEMCR_DWTENA_Pos) /*!< \deprecated CoreDebug DEMCR: DWTENA Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Mask */ + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Position */ +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Mask */ + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Mask */ + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos 16U /*!< \deprecated CoreDebug DSCSR: CDS Position */ +#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< \deprecated CoreDebug DSCSR: CDS Mask */ + +#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< \deprecated CoreDebug DSCSR: SBRSEL Position */ +#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< \deprecated CoreDebug DSCSR: SBRSEL Mask */ + +#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< \deprecated CoreDebug DSCSR: SBRSELEN Position */ +#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< \deprecated CoreDebug DSCSR: SBRSELEN Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DCB Debug Control Block + \brief Type definitions for the Debug Control Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Control Block Registers (DCB). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED0[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} DCB_Type; + +/* DHCSR, Debug Halting Control and Status Register Definitions */ +#define DCB_DHCSR_DBGKEY_Pos 16U /*!< DCB DHCSR: Debug key Position */ +#define DCB_DHCSR_DBGKEY_Msk (0xFFFFUL << DCB_DHCSR_DBGKEY_Pos) /*!< DCB DHCSR: Debug key Mask */ + +#define DCB_DHCSR_S_RESTART_ST_Pos 26U /*!< DCB DHCSR: Restart sticky status Position */ +#define DCB_DHCSR_S_RESTART_ST_Msk (0x1UL << DCB_DHCSR_S_RESTART_ST_Pos) /*!< DCB DHCSR: Restart sticky status Mask */ + +#define DCB_DHCSR_S_RESET_ST_Pos 25U /*!< DCB DHCSR: Reset sticky status Position */ +#define DCB_DHCSR_S_RESET_ST_Msk (0x1UL << DCB_DHCSR_S_RESET_ST_Pos) /*!< DCB DHCSR: Reset sticky status Mask */ + +#define DCB_DHCSR_S_RETIRE_ST_Pos 24U /*!< DCB DHCSR: Retire sticky status Position */ +#define DCB_DHCSR_S_RETIRE_ST_Msk (0x1UL << DCB_DHCSR_S_RETIRE_ST_Pos) /*!< DCB DHCSR: Retire sticky status Mask */ + +#define DCB_DHCSR_S_SDE_Pos 20U /*!< DCB DHCSR: Secure debug enabled Position */ +#define DCB_DHCSR_S_SDE_Msk (0x1UL << DCB_DHCSR_S_SDE_Pos) /*!< DCB DHCSR: Secure debug enabled Mask */ + +#define DCB_DHCSR_S_LOCKUP_Pos 19U /*!< DCB DHCSR: Lockup status Position */ +#define DCB_DHCSR_S_LOCKUP_Msk (0x1UL << DCB_DHCSR_S_LOCKUP_Pos) /*!< DCB DHCSR: Lockup status Mask */ + +#define DCB_DHCSR_S_SLEEP_Pos 18U /*!< DCB DHCSR: Sleeping status Position */ +#define DCB_DHCSR_S_SLEEP_Msk (0x1UL << DCB_DHCSR_S_SLEEP_Pos) /*!< DCB DHCSR: Sleeping status Mask */ + +#define DCB_DHCSR_S_HALT_Pos 17U /*!< DCB DHCSR: Halted status Position */ +#define DCB_DHCSR_S_HALT_Msk (0x1UL << DCB_DHCSR_S_HALT_Pos) /*!< DCB DHCSR: Halted status Mask */ + +#define DCB_DHCSR_S_REGRDY_Pos 16U /*!< DCB DHCSR: Register ready status Position */ +#define DCB_DHCSR_S_REGRDY_Msk (0x1UL << DCB_DHCSR_S_REGRDY_Pos) /*!< DCB DHCSR: Register ready status Mask */ + +#define DCB_DHCSR_C_MASKINTS_Pos 3U /*!< DCB DHCSR: Mask interrupts control Position */ +#define DCB_DHCSR_C_MASKINTS_Msk (0x1UL << DCB_DHCSR_C_MASKINTS_Pos) /*!< DCB DHCSR: Mask interrupts control Mask */ + +#define DCB_DHCSR_C_STEP_Pos 2U /*!< DCB DHCSR: Step control Position */ +#define DCB_DHCSR_C_STEP_Msk (0x1UL << DCB_DHCSR_C_STEP_Pos) /*!< DCB DHCSR: Step control Mask */ + +#define DCB_DHCSR_C_HALT_Pos 1U /*!< DCB DHCSR: Halt control Position */ +#define DCB_DHCSR_C_HALT_Msk (0x1UL << DCB_DHCSR_C_HALT_Pos) /*!< DCB DHCSR: Halt control Mask */ + +#define DCB_DHCSR_C_DEBUGEN_Pos 0U /*!< DCB DHCSR: Debug enable control Position */ +#define DCB_DHCSR_C_DEBUGEN_Msk (0x1UL /*<< DCB_DHCSR_C_DEBUGEN_Pos*/) /*!< DCB DHCSR: Debug enable control Mask */ + +/* DCRSR, Debug Core Register Select Register Definitions */ +#define DCB_DCRSR_REGWnR_Pos 16U /*!< DCB DCRSR: Register write/not-read Position */ +#define DCB_DCRSR_REGWnR_Msk (0x1UL << DCB_DCRSR_REGWnR_Pos) /*!< DCB DCRSR: Register write/not-read Mask */ + +#define DCB_DCRSR_REGSEL_Pos 0U /*!< DCB DCRSR: Register selector Position */ +#define DCB_DCRSR_REGSEL_Msk (0x7FUL /*<< DCB_DCRSR_REGSEL_Pos*/) /*!< DCB DCRSR: Register selector Mask */ + +/* DCRDR, Debug Core Register Data Register Definitions */ +#define DCB_DCRDR_DBGTMP_Pos 0U /*!< DCB DCRDR: Data temporary buffer Position */ +#define DCB_DCRDR_DBGTMP_Msk (0xFFFFFFFFUL /*<< DCB_DCRDR_DBGTMP_Pos*/) /*!< DCB DCRDR: Data temporary buffer Mask */ + +/* DEMCR, Debug Exception and Monitor Control Register Definitions */ +#define DCB_DEMCR_TRCENA_Pos 24U /*!< DCB DEMCR: Trace enable Position */ +#define DCB_DEMCR_TRCENA_Msk (0x1UL << DCB_DEMCR_TRCENA_Pos) /*!< DCB DEMCR: Trace enable Mask */ + +#define DCB_DEMCR_VC_HARDERR_Pos 10U /*!< DCB DEMCR: Vector Catch HardFault errors Position */ +#define DCB_DEMCR_VC_HARDERR_Msk (0x1UL << DCB_DEMCR_VC_HARDERR_Pos) /*!< DCB DEMCR: Vector Catch HardFault errors Mask */ + +#define DCB_DEMCR_VC_CORERESET_Pos 0U /*!< DCB DEMCR: Vector Catch Core reset Position */ +#define DCB_DEMCR_VC_CORERESET_Msk (0x1UL /*<< DCB_DEMCR_VC_CORERESET_Pos*/) /*!< DCB DEMCR: Vector Catch Core reset Mask */ + +/* DAUTHCTRL, Debug Authentication Control Register Definitions */ +#define DCB_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPNIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPNIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPNIDENSEL_Msk (0x1UL << DCB_DAUTHCTRL_SPNIDENSEL_Pos) /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Mask */ + +#define DCB_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< DCB DAUTHCTRL: Secure invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPIDENSEL_Msk (0x1UL /*<< DCB_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< DCB DAUTHCTRL: Secure invasive debug enable select Mask */ + +/* DSCSR, Debug Security Control and Status Register Definitions */ +#define DCB_DSCSR_CDSKEY_Pos 17U /*!< DCB DSCSR: CDS write-enable key Position */ +#define DCB_DSCSR_CDSKEY_Msk (0x1UL << DCB_DSCSR_CDSKEY_Pos) /*!< DCB DSCSR: CDS write-enable key Mask */ + +#define DCB_DSCSR_CDS_Pos 16U /*!< DCB DSCSR: Current domain Secure Position */ +#define DCB_DSCSR_CDS_Msk (0x1UL << DCB_DSCSR_CDS_Pos) /*!< DCB DSCSR: Current domain Secure Mask */ + +#define DCB_DSCSR_SBRSEL_Pos 1U /*!< DCB DSCSR: Secure banked register select Position */ +#define DCB_DSCSR_SBRSEL_Msk (0x1UL << DCB_DSCSR_SBRSEL_Pos) /*!< DCB DSCSR: Secure banked register select Mask */ + +#define DCB_DSCSR_SBRSELEN_Pos 0U /*!< DCB DSCSR: Secure banked register select enable Position */ +#define DCB_DSCSR_SBRSELEN_Msk (0x1UL /*<< DCB_DSCSR_SBRSELEN_Pos*/) /*!< DCB DSCSR: Secure banked register select enable Mask */ + +/*@} end of group CMSIS_DCB */ + + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DIB Debug Identification Block + \brief Type definitions for the Debug Identification Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Identification Block Registers (DIB). + */ +typedef struct +{ + __OM uint32_t DLAR; /*!< Offset: 0x000 ( /W) SCS Software Lock Access Register */ + __IM uint32_t DLSR; /*!< Offset: 0x004 (R/ ) SCS Software Lock Status Register */ + __IM uint32_t DAUTHSTATUS; /*!< Offset: 0x008 (R/ ) Debug Authentication Status Register */ + __IM uint32_t DDEVARCH; /*!< Offset: 0x00C (R/ ) SCS Device Architecture Register */ + __IM uint32_t DDEVTYPE; /*!< Offset: 0x010 (R/ ) SCS Device Type Register */ +} DIB_Type; + +/* DLAR, SCS Software Lock Access Register Definitions */ +#define DIB_DLAR_KEY_Pos 0U /*!< DIB DLAR: KEY Position */ +#define DIB_DLAR_KEY_Msk (0xFFFFFFFFUL /*<< DIB_DLAR_KEY_Pos */) /*!< DIB DLAR: KEY Mask */ + +/* DLSR, SCS Software Lock Status Register Definitions */ +#define DIB_DLSR_nTT_Pos 2U /*!< DIB DLSR: Not thirty-two bit Position */ +#define DIB_DLSR_nTT_Msk (0x1UL << DIB_DLSR_nTT_Pos ) /*!< DIB DLSR: Not thirty-two bit Mask */ + +#define DIB_DLSR_SLK_Pos 1U /*!< DIB DLSR: Software Lock status Position */ +#define DIB_DLSR_SLK_Msk (0x1UL << DIB_DLSR_SLK_Pos ) /*!< DIB DLSR: Software Lock status Mask */ + +#define DIB_DLSR_SLI_Pos 0U /*!< DIB DLSR: Software Lock implemented Position */ +#define DIB_DLSR_SLI_Msk (0x1UL /*<< DIB_DLSR_SLI_Pos*/) /*!< DIB DLSR: Software Lock implemented Mask */ + +/* DAUTHSTATUS, Debug Authentication Status Register Definitions */ +#define DIB_DAUTHSTATUS_SNID_Pos 6U /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_SNID_Msk (0x3UL << DIB_DAUTHSTATUS_SNID_Pos ) /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_SID_Pos 4U /*!< DIB DAUTHSTATUS: Secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_SID_Msk (0x3UL << DIB_DAUTHSTATUS_SID_Pos ) /*!< DIB DAUTHSTATUS: Secure Invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSNID_Pos 2U /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSNID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSID_Pos 0U /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSID_Msk (0x3UL /*<< DIB_DAUTHSTATUS_NSID_Pos*/) /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Mask */ + +/* DDEVARCH, SCS Device Architecture Register Definitions */ +#define DIB_DDEVARCH_ARCHITECT_Pos 21U /*!< DIB DDEVARCH: Architect Position */ +#define DIB_DDEVARCH_ARCHITECT_Msk (0x7FFUL << DIB_DDEVARCH_ARCHITECT_Pos ) /*!< DIB DDEVARCH: Architect Mask */ + +#define DIB_DDEVARCH_PRESENT_Pos 20U /*!< DIB DDEVARCH: DEVARCH Present Position */ +#define DIB_DDEVARCH_PRESENT_Msk (0x1FUL << DIB_DDEVARCH_PRESENT_Pos ) /*!< DIB DDEVARCH: DEVARCH Present Mask */ + +#define DIB_DDEVARCH_REVISION_Pos 16U /*!< DIB DDEVARCH: Revision Position */ +#define DIB_DDEVARCH_REVISION_Msk (0xFUL << DIB_DDEVARCH_REVISION_Pos ) /*!< DIB DDEVARCH: Revision Mask */ + +#define DIB_DDEVARCH_ARCHVER_Pos 12U /*!< DIB DDEVARCH: Architecture Version Position */ +#define DIB_DDEVARCH_ARCHVER_Msk (0xFUL << DIB_DDEVARCH_ARCHVER_Pos ) /*!< DIB DDEVARCH: Architecture Version Mask */ + +#define DIB_DDEVARCH_ARCHPART_Pos 0U /*!< DIB DDEVARCH: Architecture Part Position */ +#define DIB_DDEVARCH_ARCHPART_Msk (0xFFFUL /*<< DIB_DDEVARCH_ARCHPART_Pos*/) /*!< DIB DDEVARCH: Architecture Part Mask */ + +/* DDEVTYPE, SCS Device Type Register Definitions */ +#define DIB_DDEVTYPE_SUB_Pos 4U /*!< DIB DDEVTYPE: Sub-type Position */ +#define DIB_DDEVTYPE_SUB_Msk (0xFUL << DIB_DDEVTYPE_SUB_Pos ) /*!< DIB DDEVTYPE: Sub-type Mask */ + +#define DIB_DDEVTYPE_MAJOR_Pos 0U /*!< DIB DDEVTYPE: Major type Position */ +#define DIB_DDEVTYPE_MAJOR_Msk (0xFUL /*<< DIB_DDEVTYPE_MAJOR_Pos*/) /*!< DIB DDEVTYPE: Major type Mask */ + + +/*@} end of group CMSIS_DIB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ + #define CoreDebug_BASE (0xE000EDF0UL) /*!< \deprecated Core Debug Base Address */ + #define DCB_BASE (0xE000EDF0UL) /*!< DCB Base Address */ + #define DIB_BASE (0xE000EFB0UL) /*!< DIB Base Address */ + #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + + #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ + #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ + #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ + #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ + #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< \deprecated Core Debug configuration struct */ + #define DCB ((DCB_Type *) DCB_BASE ) /*!< DCB configuration struct */ + #define DIB ((DIB_Type *) DIB_BASE ) /*!< DIB configuration struct */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ + #endif + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ + #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ + #endif + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ + #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< \deprecated Core Debug Base Address (non-secure address space) */ + #define DCB_BASE_NS (0xE002EDF0UL) /*!< DCB Base Address (non-secure address space) */ + #define DIB_BASE_NS (0xE002EFB0UL) /*!< DIB Base Address (non-secure address space) */ + #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ + #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ + #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + + #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ + #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ + #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ + #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< \deprecated Core Debug configuration struct (non-secure address space) */ + #define DCB_NS ((DCB_Type *) DCB_BASE_NS ) /*!< DCB configuration struct (non-secure address space) */ + #define DIB_NS ((DIB_Type *) DIB_BASE_NS ) /*!< DIB configuration struct (non-secure address space) */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ + #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ + #endif + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else +/*#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping not available for Cortex-M23 */ +/*#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping not available for Cortex-M23 */ + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* Special LR values for Secure/Non-Secure call handling and exception handling */ + +/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ +#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ + +/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ +#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ +#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ +#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ +#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ +#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ +#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */ +#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ + +/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ +#else +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ +#endif + + +/* Interrupt Priorities are WORD accessible only under Armv6-M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + +#define __NVIC_SetPriorityGrouping(X) (void)(X) +#define __NVIC_GetPriorityGrouping() (0U) + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + If VTOR is not present address 0 must be mapped to SRAM. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t *vectors = (uint32_t *)SCB->VTOR; +#else + uint32_t *vectors = (uint32_t *)0x0U; +#endif + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + __DSB(); +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t *vectors = (uint32_t *)SCB->VTOR; +#else + uint32_t *vectors = (uint32_t *)0x0U; +#endif + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC_NS->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB_NS->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB_NS->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB_NS->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv8.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + + +/* ################################## Debug Control function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DCBFunctions Debug Control Functions + \brief Functions that access the Debug Control Block. + @{ + */ + + +/** + \brief Set Debug Authentication Control Register + \details writes to Debug Authentication Control register. + \param [in] value value to be writen. + */ +__STATIC_INLINE void DCB_SetAuthCtrl(uint32_t value) +{ + __DSB(); + __ISB(); + DCB->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register + \details Reads Debug Authentication Control register. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t DCB_GetAuthCtrl(void) +{ + return (DCB->DAUTHCTRL); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Debug Authentication Control Register (non-secure) + \details writes to non-secure Debug Authentication Control register when in secure state. + \param [in] value value to be writen + */ +__STATIC_INLINE void TZ_DCB_SetAuthCtrl_NS(uint32_t value) +{ + __DSB(); + __ISB(); + DCB_NS->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register (non-secure) + \details Reads non-secure Debug Authentication Control register when in secure state. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t TZ_DCB_GetAuthCtrl_NS(void) +{ + return (DCB_NS->DAUTHCTRL); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## Debug Identification function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DIBFunctions Debug Identification Functions + \brief Functions that access the Debug Identification Block. + @{ + */ + + +/** + \brief Get Debug Authentication Status Register + \details Reads Debug Authentication Status register. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t DIB_GetAuthStatus(void) +{ + return (DIB->DAUTHSTATUS); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Debug Authentication Status Register (non-secure) + \details Reads non-secure Debug Authentication Status register when in secure state. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t TZ_DIB_GetAuthStatus_NS(void) +{ + return (DIB_NS->DAUTHSTATUS); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM23_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/CMSIS/Core/Include/core_cm3.h b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/CMSIS/Core/Include/core_cm3.h new file mode 100644 index 0000000000..74fb87e5c5 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/CMSIS/Core/Include/core_cm3.h @@ -0,0 +1,1943 @@ +/**************************************************************************//** + * @file core_cm3.h + * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File + * @version V5.1.2 + * @date 04. June 2021 + ******************************************************************************/ +/* + * Copyright (c) 2009-2021 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM3_H_GENERIC +#define __CORE_CM3_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M3 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM3 definitions */ +#define __CM3_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM3_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16U) | \ + __CM3_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (3U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM3_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM3_H_DEPENDANT +#define __CORE_CM3_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM3_REV + #define __CM3_REV 0x0200U + #warning "__CM3_REV not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 1U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M3 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:1; /*!< bit: 9 Reserved */ + uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */ + uint32_t _reserved1:8; /*!< bit: 16..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit */ + uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */ +#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */ +#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24U]; + __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RESERVED1[24U]; + __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24U]; + __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24U]; + __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56U]; + __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[5U]; + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#if defined (__CM3_REV) && (__CM3_REV < 0x0201U) /* core r2p1 */ +#define SCB_VTOR_TBLBASE_Pos 29U /*!< SCB VTOR: TBLBASE Position */ +#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */ + +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#else +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#endif + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_CFSR_MEMFAULTSR_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ +#if defined (__CM3_REV) && (__CM3_REV >= 0x200U) + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +#else + uint32_t RESERVED1[1U]; +#endif +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/* Auxiliary Control Register Definitions */ +#if defined (__CM3_REV) && (__CM3_REV >= 0x200U) +#define SCnSCB_ACTLR_DISOOFP_Pos 9U /*!< ACTLR: DISOOFP Position */ +#define SCnSCB_ACTLR_DISOOFP_Msk (1UL << SCnSCB_ACTLR_DISOOFP_Pos) /*!< ACTLR: DISOOFP Mask */ + +#define SCnSCB_ACTLR_DISFPCA_Pos 8U /*!< ACTLR: DISFPCA Position */ +#define SCnSCB_ACTLR_DISFPCA_Msk (1UL << SCnSCB_ACTLR_DISFPCA_Pos) /*!< ACTLR: DISFPCA Mask */ + +#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ +#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR: DISDEFWBUF Position */ +#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ + +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ +#endif + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x1UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x1UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY2_Pos 0U /*!< TPI ITATBCTR2: ATREADY2 Position */ +#define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/) /*!< TPI ITATBCTR2: ATREADY2 Mask */ + +#define TPI_ITATBCTR2_ATREADY1_Pos 0U /*!< TPI ITATBCTR2: ATREADY1 Position */ +#define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/) /*!< TPI ITATBCTR2: ATREADY1 Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x1UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x1UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY2_Pos 0U /*!< TPI ITATBCTR0: ATREADY2 Position */ +#define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/) /*!< TPI ITATBCTR0: ATREADY2 Mask */ + +#define TPI_ITATBCTR0_ATREADY1_Pos 0U /*!< TPI ITATBCTR0: ATREADY1 Position */ +#define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/) /*!< TPI ITATBCTR0: ATREADY1 Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + /* ARM Application Note 321 states that the M3 does not require the architectural barrier */ +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv7.h" + +#endif + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM3_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/CMSIS/Core/Include/core_cm33.h b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/CMSIS/Core/Include/core_cm33.h new file mode 100644 index 0000000000..18a2e6fb03 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/CMSIS/Core/Include/core_cm33.h @@ -0,0 +1,3277 @@ +/**************************************************************************//** + * @file core_cm33.h + * @brief CMSIS Cortex-M33 Core Peripheral Access Layer Header File + * @version V5.2.3 + * @date 13. October 2021 + ******************************************************************************/ +/* + * Copyright (c) 2009-2021 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#elif defined ( __GNUC__ ) + #pragma GCC diagnostic ignored "-Wpedantic" /* disable pedantic warning due to unnamed structs/unions */ +#endif + +#ifndef __CORE_CM33_H_GENERIC +#define __CORE_CM33_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M33 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM33 definitions */ +#define __CM33_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM33_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM33_CMSIS_VERSION ((__CM33_CMSIS_VERSION_MAIN << 16U) | \ + __CM33_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (33U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined (__TARGET_FPU_VFP) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined (__ARM_FP) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined (__ARMVFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined (__TI_VFP_SUPPORT__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined (__FPU_VFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM33_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM33_H_DEPENDANT +#define __CORE_CM33_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM33_REV + #define __CM33_REV 0x0000U + #warning "__CM33_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DSP_PRESENT + #define __DSP_PRESENT 0U + #warning "__DSP_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 1U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M33 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core SAU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ +#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */ + uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */ + uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */ +#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */ + +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED6[580U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ + __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ + __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ + __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */ + uint32_t RESERVED7[21U]; + __IOM uint32_t SFSR; /*!< Offset: 0x0E4 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x0E8 (R/W) Secure Fault Address Register */ + uint32_t RESERVED3[69U]; + __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ + uint32_t RESERVED4[15U]; + __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ + uint32_t RESERVED5[1U]; + __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ + uint32_t RESERVED6[1U]; + __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ + __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ + __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ + __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ + __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ + __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ + __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ + __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ + __OM uint32_t BPIALL; /*!< Offset: 0x278 ( /W) Branch Predictor Invalidate All */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ +#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */ +#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */ +#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */ + +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */ +#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_CFSR_MEMFAULTSR_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */ +#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/* SCB Non-Secure Access Control Register Definitions */ +#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */ +#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */ + +#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */ +#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */ + +#define SCB_NSACR_CPn_Pos 0U /*!< SCB NSACR: CPn Position */ +#define SCB_NSACR_CPn_Msk (1UL /*<< SCB_NSACR_CPn_Pos*/) /*!< SCB NSACR: CPn Mask */ + +/* SCB Cache Level ID Register Definitions */ +#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ +#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ + +#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ +#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ + +/* SCB Cache Type Register Definitions */ +#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ +#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ + +#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ +#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ + +#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ +#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ + +#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ +#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ + +#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ +#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ + +/* SCB Cache Size ID Register Definitions */ +#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ +#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ + +#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ +#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ + +#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ +#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ + +#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ +#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ + +#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ +#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ + +#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ +#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ + +#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ +#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ + +/* SCB Cache Size Selection Register Definitions */ +#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ +#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ + +#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ +#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ + +/* SCB Software Triggered Interrupt Register Definitions */ +#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ +#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ + +/* SCB D-Cache Invalidate by Set-way Register Definitions */ +#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ +#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ + +#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ +#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ + +/* SCB D-Cache Clean by Set-way Register Definitions */ +#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ +#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ + +#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ +#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ + +/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ +#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ +#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ + +#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ +#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ + __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */ + uint32_t RESERVED6[4U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Stimulus Port Register Definitions */ +#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */ +#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */ + +#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */ +#define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */ + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */ +#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */ + +#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */ +#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED14[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED15[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED16[1U]; + __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ + uint32_t RESERVED17[1U]; + __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ + uint32_t RESERVED18[1U]; + __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ + uint32_t RESERVED19[1U]; + __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ + uint32_t RESERVED20[1U]; + __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ + uint32_t RESERVED21[1U]; + __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ + uint32_t RESERVED22[1U]; + __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ + uint32_t RESERVED23[1U]; + __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ + uint32_t RESERVED24[1U]; + __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ + uint32_t RESERVED25[1U]; + __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ + uint32_t RESERVED26[1U]; + __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ + uint32_t RESERVED27[1U]; + __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ + uint32_t RESERVED28[1U]; + __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ + uint32_t RESERVED29[1U]; + __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ + uint32_t RESERVED30[1U]; + __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ + uint32_t RESERVED31[1U]; + __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ + uint32_t RESERVED32[934U]; + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ + uint32_t RESERVED33[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */ +#define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t ITFTTD0; /*!< Offset: 0xEEC (R/ ) Integration Test FIFO Test Data 0 Register */ + __IOM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/W) Integration Test ATB Control Register 2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) Integration Test ATB Control Register 0 */ + __IM uint32_t ITFTTD1; /*!< Offset: 0xEFC (R/ ) Integration Test FIFO Test Data 1 Register */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) Device Configuration Register */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Identifier Register */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ +#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration Test FIFO Test Data 0 Register Definitions */ +#define TPI_ITFTTD0_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD0: ATB Interface 2 ATVALIDPosition */ +#define TPI_ITFTTD0_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 2 ATVALID Mask */ + +#define TPI_ITFTTD0_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD0: ATB Interface 2 byte count Position */ +#define TPI_ITFTTD0_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 2 byte count Mask */ + +#define TPI_ITFTTD0_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Position */ +#define TPI_ITFTTD0_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Mask */ + +#define TPI_ITFTTD0_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD0: ATB Interface 1 byte count Position */ +#define TPI_ITFTTD0_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 1 byte countt Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data2_Pos 16U /*!< TPI ITFTTD0: ATB Interface 1 data2 Position */ +#define TPI_ITFTTD0_ATB_IF1_data2_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data2 Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data1_Pos 8U /*!< TPI ITFTTD0: ATB Interface 1 data1 Position */ +#define TPI_ITFTTD0_ATB_IF1_data1_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data1 Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data0_Pos 0U /*!< TPI ITFTTD0: ATB Interface 1 data0 Position */ +#define TPI_ITFTTD0_ATB_IF1_data0_Msk (0xFFUL /*<< TPI_ITFTTD0_ATB_IF1_data0_Pos*/) /*!< TPI ITFTTD0: ATB Interface 1 data0 Mask */ + +/* TPI Integration Test ATB Control Register 2 Register Definitions */ +#define TPI_ITATBCTR2_AFVALID2S_Pos 1U /*!< TPI ITATBCTR2: AFVALID2S Position */ +#define TPI_ITATBCTR2_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID2S_Pos) /*!< TPI ITATBCTR2: AFVALID2SS Mask */ + +#define TPI_ITATBCTR2_AFVALID1S_Pos 1U /*!< TPI ITATBCTR2: AFVALID1S Position */ +#define TPI_ITATBCTR2_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID1S_Pos) /*!< TPI ITATBCTR2: AFVALID1SS Mask */ + +#define TPI_ITATBCTR2_ATREADY2S_Pos 0U /*!< TPI ITATBCTR2: ATREADY2S Position */ +#define TPI_ITATBCTR2_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2S_Pos*/) /*!< TPI ITATBCTR2: ATREADY2S Mask */ + +#define TPI_ITATBCTR2_ATREADY1S_Pos 0U /*!< TPI ITATBCTR2: ATREADY1S Position */ +#define TPI_ITATBCTR2_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1S_Pos*/) /*!< TPI ITATBCTR2: ATREADY1S Mask */ + +/* TPI Integration Test FIFO Test Data 1 Register Definitions */ +#define TPI_ITFTTD1_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Position */ +#define TPI_ITFTTD1_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Mask */ + +#define TPI_ITFTTD1_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD1: ATB Interface 2 byte count Position */ +#define TPI_ITFTTD1_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 2 byte count Mask */ + +#define TPI_ITFTTD1_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Position */ +#define TPI_ITFTTD1_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Mask */ + +#define TPI_ITFTTD1_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD1: ATB Interface 1 byte count Position */ +#define TPI_ITFTTD1_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 1 byte countt Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data2_Pos 16U /*!< TPI ITFTTD1: ATB Interface 2 data2 Position */ +#define TPI_ITFTTD1_ATB_IF2_data2_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data2 Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data1_Pos 8U /*!< TPI ITFTTD1: ATB Interface 2 data1 Position */ +#define TPI_ITFTTD1_ATB_IF2_data1_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data1 Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data0_Pos 0U /*!< TPI ITFTTD1: ATB Interface 2 data0 Position */ +#define TPI_ITFTTD1_ATB_IF2_data0_Msk (0xFFUL /*<< TPI_ITFTTD1_ATB_IF2_data0_Pos*/) /*!< TPI ITFTTD1: ATB Interface 2 data0 Mask */ + +/* TPI Integration Test ATB Control Register 0 Definitions */ +#define TPI_ITATBCTR0_AFVALID2S_Pos 1U /*!< TPI ITATBCTR0: AFVALID2S Position */ +#define TPI_ITATBCTR0_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID2S_Pos) /*!< TPI ITATBCTR0: AFVALID2SS Mask */ + +#define TPI_ITATBCTR0_AFVALID1S_Pos 1U /*!< TPI ITATBCTR0: AFVALID1S Position */ +#define TPI_ITATBCTR0_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID1S_Pos) /*!< TPI ITATBCTR0: AFVALID1SS Mask */ + +#define TPI_ITATBCTR0_ATREADY2S_Pos 0U /*!< TPI ITATBCTR0: ATREADY2S Position */ +#define TPI_ITATBCTR0_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2S_Pos*/) /*!< TPI ITATBCTR0: ATREADY2S Mask */ + +#define TPI_ITATBCTR0_ATREADY1S_Pos 0U /*!< TPI ITATBCTR0: ATREADY1S Position */ +#define TPI_ITATBCTR0_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1S_Pos*/) /*!< TPI ITATBCTR0: ATREADY1S Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFOSZ Position */ +#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFOSZ Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x3FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */ + __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */ + __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */ + __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */ + uint32_t RESERVED0[1]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ +#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/* MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */ + +/* MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/* MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#else + uint32_t RESERVED0[3]; +#endif + __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */ +} SAU_Type; + +/* SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/* SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/* SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/* SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/* SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/* Secure Fault Status Register Definitions */ +#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */ +#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */ + +#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */ +#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */ + +#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */ +#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */ + +#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */ +#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */ + +#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */ +#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */ + +#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */ +#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */ + +#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */ +#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */ + +#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */ +#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and VFP Feature Register 2 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */ +#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */ + +#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */ +#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */ + +#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */ +#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */ + +#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */ +#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */ + +#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */ +#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */ + +#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */ +#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */ +#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */ +#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and VFP Feature Register 0 Definitions */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and VFP Feature Register 1 Definitions */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/* Media and VFP Feature Register 2 Definitions */ +#define FPU_MVFR2_FPMisc_Pos 4U /*!< MVFR2: FPMisc bits Position */ +#define FPU_MVFR2_FPMisc_Msk (0xFUL << FPU_MVFR2_FPMisc_Pos) /*!< MVFR2: FPMisc bits Mask */ + +/*@} end of group CMSIS_FPU */ + +/* CoreDebug is deprecated. replaced by DCB (Debug Control Block) */ +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief \deprecated Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED0[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< \deprecated CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< \deprecated CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Position */ +#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< \deprecated CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< \deprecated CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< \deprecated CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< \deprecated CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< \deprecated CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< \deprecated CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< \deprecated CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< \deprecated CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< \deprecated CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< \deprecated CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< \deprecated CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< \deprecated CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< \deprecated CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< \deprecated CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< \deprecated CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< \deprecated CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< \deprecated CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< \deprecated CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< \deprecated CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< \deprecated CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< \deprecated CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< \deprecated CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< \deprecated CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< \deprecated CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< \deprecated CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< \deprecated CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< \deprecated CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< \deprecated CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< \deprecated CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< \deprecated CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Mask */ + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Position */ +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Mask */ + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Mask */ + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos 16U /*!< \deprecated CoreDebug DSCSR: CDS Position */ +#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< \deprecated CoreDebug DSCSR: CDS Mask */ + +#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< \deprecated CoreDebug DSCSR: SBRSEL Position */ +#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< \deprecated CoreDebug DSCSR: SBRSEL Mask */ + +#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< \deprecated CoreDebug DSCSR: SBRSELEN Position */ +#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< \deprecated CoreDebug DSCSR: SBRSELEN Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DCB Debug Control Block + \brief Type definitions for the Debug Control Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Control Block Registers (DCB). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED0[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} DCB_Type; + +/* DHCSR, Debug Halting Control and Status Register Definitions */ +#define DCB_DHCSR_DBGKEY_Pos 16U /*!< DCB DHCSR: Debug key Position */ +#define DCB_DHCSR_DBGKEY_Msk (0xFFFFUL << DCB_DHCSR_DBGKEY_Pos) /*!< DCB DHCSR: Debug key Mask */ + +#define DCB_DHCSR_S_RESTART_ST_Pos 26U /*!< DCB DHCSR: Restart sticky status Position */ +#define DCB_DHCSR_S_RESTART_ST_Msk (0x1UL << DCB_DHCSR_S_RESTART_ST_Pos) /*!< DCB DHCSR: Restart sticky status Mask */ + +#define DCB_DHCSR_S_RESET_ST_Pos 25U /*!< DCB DHCSR: Reset sticky status Position */ +#define DCB_DHCSR_S_RESET_ST_Msk (0x1UL << DCB_DHCSR_S_RESET_ST_Pos) /*!< DCB DHCSR: Reset sticky status Mask */ + +#define DCB_DHCSR_S_RETIRE_ST_Pos 24U /*!< DCB DHCSR: Retire sticky status Position */ +#define DCB_DHCSR_S_RETIRE_ST_Msk (0x1UL << DCB_DHCSR_S_RETIRE_ST_Pos) /*!< DCB DHCSR: Retire sticky status Mask */ + +#define DCB_DHCSR_S_SDE_Pos 20U /*!< DCB DHCSR: Secure debug enabled Position */ +#define DCB_DHCSR_S_SDE_Msk (0x1UL << DCB_DHCSR_S_SDE_Pos) /*!< DCB DHCSR: Secure debug enabled Mask */ + +#define DCB_DHCSR_S_LOCKUP_Pos 19U /*!< DCB DHCSR: Lockup status Position */ +#define DCB_DHCSR_S_LOCKUP_Msk (0x1UL << DCB_DHCSR_S_LOCKUP_Pos) /*!< DCB DHCSR: Lockup status Mask */ + +#define DCB_DHCSR_S_SLEEP_Pos 18U /*!< DCB DHCSR: Sleeping status Position */ +#define DCB_DHCSR_S_SLEEP_Msk (0x1UL << DCB_DHCSR_S_SLEEP_Pos) /*!< DCB DHCSR: Sleeping status Mask */ + +#define DCB_DHCSR_S_HALT_Pos 17U /*!< DCB DHCSR: Halted status Position */ +#define DCB_DHCSR_S_HALT_Msk (0x1UL << DCB_DHCSR_S_HALT_Pos) /*!< DCB DHCSR: Halted status Mask */ + +#define DCB_DHCSR_S_REGRDY_Pos 16U /*!< DCB DHCSR: Register ready status Position */ +#define DCB_DHCSR_S_REGRDY_Msk (0x1UL << DCB_DHCSR_S_REGRDY_Pos) /*!< DCB DHCSR: Register ready status Mask */ + +#define DCB_DHCSR_C_SNAPSTALL_Pos 5U /*!< DCB DHCSR: Snap stall control Position */ +#define DCB_DHCSR_C_SNAPSTALL_Msk (0x1UL << DCB_DHCSR_C_SNAPSTALL_Pos) /*!< DCB DHCSR: Snap stall control Mask */ + +#define DCB_DHCSR_C_MASKINTS_Pos 3U /*!< DCB DHCSR: Mask interrupts control Position */ +#define DCB_DHCSR_C_MASKINTS_Msk (0x1UL << DCB_DHCSR_C_MASKINTS_Pos) /*!< DCB DHCSR: Mask interrupts control Mask */ + +#define DCB_DHCSR_C_STEP_Pos 2U /*!< DCB DHCSR: Step control Position */ +#define DCB_DHCSR_C_STEP_Msk (0x1UL << DCB_DHCSR_C_STEP_Pos) /*!< DCB DHCSR: Step control Mask */ + +#define DCB_DHCSR_C_HALT_Pos 1U /*!< DCB DHCSR: Halt control Position */ +#define DCB_DHCSR_C_HALT_Msk (0x1UL << DCB_DHCSR_C_HALT_Pos) /*!< DCB DHCSR: Halt control Mask */ + +#define DCB_DHCSR_C_DEBUGEN_Pos 0U /*!< DCB DHCSR: Debug enable control Position */ +#define DCB_DHCSR_C_DEBUGEN_Msk (0x1UL /*<< DCB_DHCSR_C_DEBUGEN_Pos*/) /*!< DCB DHCSR: Debug enable control Mask */ + +/* DCRSR, Debug Core Register Select Register Definitions */ +#define DCB_DCRSR_REGWnR_Pos 16U /*!< DCB DCRSR: Register write/not-read Position */ +#define DCB_DCRSR_REGWnR_Msk (0x1UL << DCB_DCRSR_REGWnR_Pos) /*!< DCB DCRSR: Register write/not-read Mask */ + +#define DCB_DCRSR_REGSEL_Pos 0U /*!< DCB DCRSR: Register selector Position */ +#define DCB_DCRSR_REGSEL_Msk (0x7FUL /*<< DCB_DCRSR_REGSEL_Pos*/) /*!< DCB DCRSR: Register selector Mask */ + +/* DCRDR, Debug Core Register Data Register Definitions */ +#define DCB_DCRDR_DBGTMP_Pos 0U /*!< DCB DCRDR: Data temporary buffer Position */ +#define DCB_DCRDR_DBGTMP_Msk (0xFFFFFFFFUL /*<< DCB_DCRDR_DBGTMP_Pos*/) /*!< DCB DCRDR: Data temporary buffer Mask */ + +/* DEMCR, Debug Exception and Monitor Control Register Definitions */ +#define DCB_DEMCR_TRCENA_Pos 24U /*!< DCB DEMCR: Trace enable Position */ +#define DCB_DEMCR_TRCENA_Msk (0x1UL << DCB_DEMCR_TRCENA_Pos) /*!< DCB DEMCR: Trace enable Mask */ + +#define DCB_DEMCR_MONPRKEY_Pos 23U /*!< DCB DEMCR: Monitor pend req key Position */ +#define DCB_DEMCR_MONPRKEY_Msk (0x1UL << DCB_DEMCR_MONPRKEY_Pos) /*!< DCB DEMCR: Monitor pend req key Mask */ + +#define DCB_DEMCR_UMON_EN_Pos 21U /*!< DCB DEMCR: Unprivileged monitor enable Position */ +#define DCB_DEMCR_UMON_EN_Msk (0x1UL << DCB_DEMCR_UMON_EN_Pos) /*!< DCB DEMCR: Unprivileged monitor enable Mask */ + +#define DCB_DEMCR_SDME_Pos 20U /*!< DCB DEMCR: Secure DebugMonitor enable Position */ +#define DCB_DEMCR_SDME_Msk (0x1UL << DCB_DEMCR_SDME_Pos) /*!< DCB DEMCR: Secure DebugMonitor enable Mask */ + +#define DCB_DEMCR_MON_REQ_Pos 19U /*!< DCB DEMCR: Monitor request Position */ +#define DCB_DEMCR_MON_REQ_Msk (0x1UL << DCB_DEMCR_MON_REQ_Pos) /*!< DCB DEMCR: Monitor request Mask */ + +#define DCB_DEMCR_MON_STEP_Pos 18U /*!< DCB DEMCR: Monitor step Position */ +#define DCB_DEMCR_MON_STEP_Msk (0x1UL << DCB_DEMCR_MON_STEP_Pos) /*!< DCB DEMCR: Monitor step Mask */ + +#define DCB_DEMCR_MON_PEND_Pos 17U /*!< DCB DEMCR: Monitor pend Position */ +#define DCB_DEMCR_MON_PEND_Msk (0x1UL << DCB_DEMCR_MON_PEND_Pos) /*!< DCB DEMCR: Monitor pend Mask */ + +#define DCB_DEMCR_MON_EN_Pos 16U /*!< DCB DEMCR: Monitor enable Position */ +#define DCB_DEMCR_MON_EN_Msk (0x1UL << DCB_DEMCR_MON_EN_Pos) /*!< DCB DEMCR: Monitor enable Mask */ + +#define DCB_DEMCR_VC_SFERR_Pos 11U /*!< DCB DEMCR: Vector Catch SecureFault Position */ +#define DCB_DEMCR_VC_SFERR_Msk (0x1UL << DCB_DEMCR_VC_SFERR_Pos) /*!< DCB DEMCR: Vector Catch SecureFault Mask */ + +#define DCB_DEMCR_VC_HARDERR_Pos 10U /*!< DCB DEMCR: Vector Catch HardFault errors Position */ +#define DCB_DEMCR_VC_HARDERR_Msk (0x1UL << DCB_DEMCR_VC_HARDERR_Pos) /*!< DCB DEMCR: Vector Catch HardFault errors Mask */ + +#define DCB_DEMCR_VC_INTERR_Pos 9U /*!< DCB DEMCR: Vector Catch interrupt errors Position */ +#define DCB_DEMCR_VC_INTERR_Msk (0x1UL << DCB_DEMCR_VC_INTERR_Pos) /*!< DCB DEMCR: Vector Catch interrupt errors Mask */ + +#define DCB_DEMCR_VC_BUSERR_Pos 8U /*!< DCB DEMCR: Vector Catch BusFault errors Position */ +#define DCB_DEMCR_VC_BUSERR_Msk (0x1UL << DCB_DEMCR_VC_BUSERR_Pos) /*!< DCB DEMCR: Vector Catch BusFault errors Mask */ + +#define DCB_DEMCR_VC_STATERR_Pos 7U /*!< DCB DEMCR: Vector Catch state errors Position */ +#define DCB_DEMCR_VC_STATERR_Msk (0x1UL << DCB_DEMCR_VC_STATERR_Pos) /*!< DCB DEMCR: Vector Catch state errors Mask */ + +#define DCB_DEMCR_VC_CHKERR_Pos 6U /*!< DCB DEMCR: Vector Catch check errors Position */ +#define DCB_DEMCR_VC_CHKERR_Msk (0x1UL << DCB_DEMCR_VC_CHKERR_Pos) /*!< DCB DEMCR: Vector Catch check errors Mask */ + +#define DCB_DEMCR_VC_NOCPERR_Pos 5U /*!< DCB DEMCR: Vector Catch NOCP errors Position */ +#define DCB_DEMCR_VC_NOCPERR_Msk (0x1UL << DCB_DEMCR_VC_NOCPERR_Pos) /*!< DCB DEMCR: Vector Catch NOCP errors Mask */ + +#define DCB_DEMCR_VC_MMERR_Pos 4U /*!< DCB DEMCR: Vector Catch MemManage errors Position */ +#define DCB_DEMCR_VC_MMERR_Msk (0x1UL << DCB_DEMCR_VC_MMERR_Pos) /*!< DCB DEMCR: Vector Catch MemManage errors Mask */ + +#define DCB_DEMCR_VC_CORERESET_Pos 0U /*!< DCB DEMCR: Vector Catch Core reset Position */ +#define DCB_DEMCR_VC_CORERESET_Msk (0x1UL /*<< DCB_DEMCR_VC_CORERESET_Pos*/) /*!< DCB DEMCR: Vector Catch Core reset Mask */ + +/* DAUTHCTRL, Debug Authentication Control Register Definitions */ +#define DCB_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPNIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPNIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPNIDENSEL_Msk (0x1UL << DCB_DAUTHCTRL_SPNIDENSEL_Pos) /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Mask */ + +#define DCB_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< DCB DAUTHCTRL: Secure invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPIDENSEL_Msk (0x1UL /*<< DCB_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< DCB DAUTHCTRL: Secure invasive debug enable select Mask */ + +/* DSCSR, Debug Security Control and Status Register Definitions */ +#define DCB_DSCSR_CDSKEY_Pos 17U /*!< DCB DSCSR: CDS write-enable key Position */ +#define DCB_DSCSR_CDSKEY_Msk (0x1UL << DCB_DSCSR_CDSKEY_Pos) /*!< DCB DSCSR: CDS write-enable key Mask */ + +#define DCB_DSCSR_CDS_Pos 16U /*!< DCB DSCSR: Current domain Secure Position */ +#define DCB_DSCSR_CDS_Msk (0x1UL << DCB_DSCSR_CDS_Pos) /*!< DCB DSCSR: Current domain Secure Mask */ + +#define DCB_DSCSR_SBRSEL_Pos 1U /*!< DCB DSCSR: Secure banked register select Position */ +#define DCB_DSCSR_SBRSEL_Msk (0x1UL << DCB_DSCSR_SBRSEL_Pos) /*!< DCB DSCSR: Secure banked register select Mask */ + +#define DCB_DSCSR_SBRSELEN_Pos 0U /*!< DCB DSCSR: Secure banked register select enable Position */ +#define DCB_DSCSR_SBRSELEN_Msk (0x1UL /*<< DCB_DSCSR_SBRSELEN_Pos*/) /*!< DCB DSCSR: Secure banked register select enable Mask */ + +/*@} end of group CMSIS_DCB */ + + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DIB Debug Identification Block + \brief Type definitions for the Debug Identification Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Identification Block Registers (DIB). + */ +typedef struct +{ + __OM uint32_t DLAR; /*!< Offset: 0x000 ( /W) SCS Software Lock Access Register */ + __IM uint32_t DLSR; /*!< Offset: 0x004 (R/ ) SCS Software Lock Status Register */ + __IM uint32_t DAUTHSTATUS; /*!< Offset: 0x008 (R/ ) Debug Authentication Status Register */ + __IM uint32_t DDEVARCH; /*!< Offset: 0x00C (R/ ) SCS Device Architecture Register */ + __IM uint32_t DDEVTYPE; /*!< Offset: 0x010 (R/ ) SCS Device Type Register */ +} DIB_Type; + +/* DLAR, SCS Software Lock Access Register Definitions */ +#define DIB_DLAR_KEY_Pos 0U /*!< DIB DLAR: KEY Position */ +#define DIB_DLAR_KEY_Msk (0xFFFFFFFFUL /*<< DIB_DLAR_KEY_Pos */) /*!< DIB DLAR: KEY Mask */ + +/* DLSR, SCS Software Lock Status Register Definitions */ +#define DIB_DLSR_nTT_Pos 2U /*!< DIB DLSR: Not thirty-two bit Position */ +#define DIB_DLSR_nTT_Msk (0x1UL << DIB_DLSR_nTT_Pos ) /*!< DIB DLSR: Not thirty-two bit Mask */ + +#define DIB_DLSR_SLK_Pos 1U /*!< DIB DLSR: Software Lock status Position */ +#define DIB_DLSR_SLK_Msk (0x1UL << DIB_DLSR_SLK_Pos ) /*!< DIB DLSR: Software Lock status Mask */ + +#define DIB_DLSR_SLI_Pos 0U /*!< DIB DLSR: Software Lock implemented Position */ +#define DIB_DLSR_SLI_Msk (0x1UL /*<< DIB_DLSR_SLI_Pos*/) /*!< DIB DLSR: Software Lock implemented Mask */ + +/* DAUTHSTATUS, Debug Authentication Status Register Definitions */ +#define DIB_DAUTHSTATUS_SNID_Pos 6U /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_SNID_Msk (0x3UL << DIB_DAUTHSTATUS_SNID_Pos ) /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_SID_Pos 4U /*!< DIB DAUTHSTATUS: Secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_SID_Msk (0x3UL << DIB_DAUTHSTATUS_SID_Pos ) /*!< DIB DAUTHSTATUS: Secure Invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSNID_Pos 2U /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSNID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSID_Pos 0U /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSID_Msk (0x3UL /*<< DIB_DAUTHSTATUS_NSID_Pos*/) /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Mask */ + +/* DDEVARCH, SCS Device Architecture Register Definitions */ +#define DIB_DDEVARCH_ARCHITECT_Pos 21U /*!< DIB DDEVARCH: Architect Position */ +#define DIB_DDEVARCH_ARCHITECT_Msk (0x7FFUL << DIB_DDEVARCH_ARCHITECT_Pos ) /*!< DIB DDEVARCH: Architect Mask */ + +#define DIB_DDEVARCH_PRESENT_Pos 20U /*!< DIB DDEVARCH: DEVARCH Present Position */ +#define DIB_DDEVARCH_PRESENT_Msk (0x1FUL << DIB_DDEVARCH_PRESENT_Pos ) /*!< DIB DDEVARCH: DEVARCH Present Mask */ + +#define DIB_DDEVARCH_REVISION_Pos 16U /*!< DIB DDEVARCH: Revision Position */ +#define DIB_DDEVARCH_REVISION_Msk (0xFUL << DIB_DDEVARCH_REVISION_Pos ) /*!< DIB DDEVARCH: Revision Mask */ + +#define DIB_DDEVARCH_ARCHVER_Pos 12U /*!< DIB DDEVARCH: Architecture Version Position */ +#define DIB_DDEVARCH_ARCHVER_Msk (0xFUL << DIB_DDEVARCH_ARCHVER_Pos ) /*!< DIB DDEVARCH: Architecture Version Mask */ + +#define DIB_DDEVARCH_ARCHPART_Pos 0U /*!< DIB DDEVARCH: Architecture Part Position */ +#define DIB_DDEVARCH_ARCHPART_Msk (0xFFFUL /*<< DIB_DDEVARCH_ARCHPART_Pos*/) /*!< DIB DDEVARCH: Architecture Part Mask */ + +/* DDEVTYPE, SCS Device Type Register Definitions */ +#define DIB_DDEVTYPE_SUB_Pos 4U /*!< DIB DDEVTYPE: Sub-type Position */ +#define DIB_DDEVTYPE_SUB_Msk (0xFUL << DIB_DDEVTYPE_SUB_Pos ) /*!< DIB DDEVTYPE: Sub-type Mask */ + +#define DIB_DDEVTYPE_MAJOR_Pos 0U /*!< DIB DDEVTYPE: Major type Position */ +#define DIB_DDEVTYPE_MAJOR_Msk (0xFUL /*<< DIB_DDEVTYPE_MAJOR_Pos*/) /*!< DIB DDEVTYPE: Major type Mask */ + + +/*@} end of group CMSIS_DIB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ + #define CoreDebug_BASE (0xE000EDF0UL) /*!< \deprecated Core Debug Base Address */ + #define DCB_BASE (0xE000EDF0UL) /*!< DCB Base Address */ + #define DIB_BASE (0xE000EFB0UL) /*!< DIB Base Address */ + #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ + #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ + #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ + #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ + #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ + #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ + #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< \deprecated Core Debug configuration struct */ + #define DCB ((DCB_Type *) DCB_BASE ) /*!< DCB configuration struct */ + #define DIB ((DIB_Type *) DIB_BASE ) /*!< DIB configuration struct */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ + #endif + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ + #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ + #endif + + #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ + #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ + #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< \deprecated Core Debug Base Address (non-secure address space) */ + #define DCB_BASE_NS (0xE002EDF0UL) /*!< DCB Base Address (non-secure address space) */ + #define DIB_BASE_NS (0xE002EFB0UL) /*!< DIB Base Address (non-secure address space) */ + #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ + #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ + #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + + #define SCnSCB_NS ((SCnSCB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */ + #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ + #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ + #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ + #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< \deprecated Core Debug configuration struct (non-secure address space) */ + #define DCB_NS ((DCB_Type *) DCB_BASE_NS ) /*!< DCB configuration struct (non-secure address space) */ + #define DIB_NS ((DIB_Type *) DIB_BASE_NS ) /*!< DIB configuration struct (non-secure address space) */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ + #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ + #endif + + #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */ + #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */ + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_register_aliases Backwards Compatibility Aliases + \brief Register alias definitions for backwards compatibility. + @{ + */ +#define ID_ADR (ID_AFR) /*!< SCB Auxiliary Feature Register */ +/*@} */ + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* Special LR values for Secure/Non-Secure call handling and exception handling */ + +/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ +#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ + +/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ +#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ +#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ +#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ +#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ +#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ +#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */ +#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ + +/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ +#else +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ +#endif + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + __DSB(); +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Priority Grouping (non-secure) + \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB_NS->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB_NS->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping (non-secure) + \details Reads the priority grouping field from the non-secure NVIC when in secure state. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void) +{ + return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv8.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = FPU->MVFR0; + if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U) + { + return 2U; /* Double + Single precision FPU */ + } + else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + + +/* ################################## Debug Control function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DCBFunctions Debug Control Functions + \brief Functions that access the Debug Control Block. + @{ + */ + + +/** + \brief Set Debug Authentication Control Register + \details writes to Debug Authentication Control register. + \param [in] value value to be writen. + */ +__STATIC_INLINE void DCB_SetAuthCtrl(uint32_t value) +{ + __DSB(); + __ISB(); + DCB->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register + \details Reads Debug Authentication Control register. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t DCB_GetAuthCtrl(void) +{ + return (DCB->DAUTHCTRL); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Debug Authentication Control Register (non-secure) + \details writes to non-secure Debug Authentication Control register when in secure state. + \param [in] value value to be writen + */ +__STATIC_INLINE void TZ_DCB_SetAuthCtrl_NS(uint32_t value) +{ + __DSB(); + __ISB(); + DCB_NS->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register (non-secure) + \details Reads non-secure Debug Authentication Control register when in secure state. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t TZ_DCB_GetAuthCtrl_NS(void) +{ + return (DCB_NS->DAUTHCTRL); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## Debug Identification function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DIBFunctions Debug Identification Functions + \brief Functions that access the Debug Identification Block. + @{ + */ + + +/** + \brief Get Debug Authentication Status Register + \details Reads Debug Authentication Status register. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t DIB_GetAuthStatus(void) +{ + return (DIB->DAUTHSTATUS); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Debug Authentication Status Register (non-secure) + \details Reads non-secure Debug Authentication Status register when in secure state. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t TZ_DIB_GetAuthStatus_NS(void) +{ + return (DIB_NS->DAUTHSTATUS); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM33_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/CMSIS/Core/Include/core_cm35p.h b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/CMSIS/Core/Include/core_cm35p.h new file mode 100644 index 0000000000..3843d9542c --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/CMSIS/Core/Include/core_cm35p.h @@ -0,0 +1,3277 @@ +/**************************************************************************//** + * @file core_cm35p.h + * @brief CMSIS Cortex-M35P Core Peripheral Access Layer Header File + * @version V1.1.3 + * @date 13. October 2021 + ******************************************************************************/ +/* + * Copyright (c) 2018-2021 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#elif defined ( __GNUC__ ) + #pragma GCC diagnostic ignored "-Wpedantic" /* disable pedantic warning due to unnamed structs/unions */ +#endif + +#ifndef __CORE_CM35P_H_GENERIC +#define __CORE_CM35P_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M35P + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM35P definitions */ +#define __CM35P_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM35P_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM35P_CMSIS_VERSION ((__CM35P_CMSIS_VERSION_MAIN << 16U) | \ + __CM35P_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (35U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined (__TARGET_FPU_VFP) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined (__ARM_FP) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined (__ARMVFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined (__TI_VFP_SUPPORT__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined (__FPU_VFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM35P_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM35P_H_DEPENDANT +#define __CORE_CM35P_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM35P_REV + #define __CM35P_REV 0x0000U + #warning "__CM35P_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DSP_PRESENT + #define __DSP_PRESENT 0U + #warning "__DSP_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 1U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M35P */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core SAU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ +#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */ + uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */ + uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */ +#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */ + +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED6[580U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ + __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ + __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ + __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */ + uint32_t RESERVED7[21U]; + __IOM uint32_t SFSR; /*!< Offset: 0x0E4 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x0E8 (R/W) Secure Fault Address Register */ + uint32_t RESERVED3[69U]; + __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ + uint32_t RESERVED4[15U]; + __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ + uint32_t RESERVED5[1U]; + __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ + uint32_t RESERVED6[1U]; + __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ + __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ + __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ + __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ + __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ + __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ + __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ + __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ + __OM uint32_t BPIALL; /*!< Offset: 0x278 ( /W) Branch Predictor Invalidate All */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ +#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */ +#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */ +#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */ + +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */ +#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_CFSR_MEMFAULTSR_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */ +#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/* SCB Non-Secure Access Control Register Definitions */ +#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */ +#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */ + +#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */ +#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */ + +#define SCB_NSACR_CPn_Pos 0U /*!< SCB NSACR: CPn Position */ +#define SCB_NSACR_CPn_Msk (1UL /*<< SCB_NSACR_CPn_Pos*/) /*!< SCB NSACR: CPn Mask */ + +/* SCB Cache Level ID Register Definitions */ +#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ +#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ + +#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ +#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ + +/* SCB Cache Type Register Definitions */ +#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ +#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ + +#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ +#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ + +#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ +#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ + +#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ +#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ + +#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ +#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ + +/* SCB Cache Size ID Register Definitions */ +#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ +#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ + +#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ +#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ + +#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ +#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ + +#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ +#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ + +#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ +#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ + +#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ +#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ + +#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ +#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ + +/* SCB Cache Size Selection Register Definitions */ +#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ +#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ + +#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ +#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ + +/* SCB Software Triggered Interrupt Register Definitions */ +#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ +#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ + +/* SCB D-Cache Invalidate by Set-way Register Definitions */ +#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ +#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ + +#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ +#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ + +/* SCB D-Cache Clean by Set-way Register Definitions */ +#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ +#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ + +#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ +#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ + +/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ +#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ +#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ + +#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ +#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ + __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */ + uint32_t RESERVED6[4U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Stimulus Port Register Definitions */ +#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */ +#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */ + +#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */ +#define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */ + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */ +#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */ + +#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */ +#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED14[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED15[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED16[1U]; + __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ + uint32_t RESERVED17[1U]; + __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ + uint32_t RESERVED18[1U]; + __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ + uint32_t RESERVED19[1U]; + __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ + uint32_t RESERVED20[1U]; + __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ + uint32_t RESERVED21[1U]; + __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ + uint32_t RESERVED22[1U]; + __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ + uint32_t RESERVED23[1U]; + __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ + uint32_t RESERVED24[1U]; + __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ + uint32_t RESERVED25[1U]; + __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ + uint32_t RESERVED26[1U]; + __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ + uint32_t RESERVED27[1U]; + __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ + uint32_t RESERVED28[1U]; + __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ + uint32_t RESERVED29[1U]; + __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ + uint32_t RESERVED30[1U]; + __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ + uint32_t RESERVED31[1U]; + __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ + uint32_t RESERVED32[934U]; + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ + uint32_t RESERVED33[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */ +#define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t ITFTTD0; /*!< Offset: 0xEEC (R/ ) Integration Test FIFO Test Data 0 Register */ + __IOM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/W) Integration Test ATB Control Register 2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) Integration Test ATB Control Register 0 */ + __IM uint32_t ITFTTD1; /*!< Offset: 0xEFC (R/ ) Integration Test FIFO Test Data 1 Register */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) Device Configuration Register */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Identifier Register */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ +#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration Test FIFO Test Data 0 Register Definitions */ +#define TPI_ITFTTD0_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD0: ATB Interface 2 ATVALIDPosition */ +#define TPI_ITFTTD0_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 2 ATVALID Mask */ + +#define TPI_ITFTTD0_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD0: ATB Interface 2 byte count Position */ +#define TPI_ITFTTD0_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 2 byte count Mask */ + +#define TPI_ITFTTD0_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Position */ +#define TPI_ITFTTD0_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Mask */ + +#define TPI_ITFTTD0_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD0: ATB Interface 1 byte count Position */ +#define TPI_ITFTTD0_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 1 byte countt Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data2_Pos 16U /*!< TPI ITFTTD0: ATB Interface 1 data2 Position */ +#define TPI_ITFTTD0_ATB_IF1_data2_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data2 Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data1_Pos 8U /*!< TPI ITFTTD0: ATB Interface 1 data1 Position */ +#define TPI_ITFTTD0_ATB_IF1_data1_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data1 Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data0_Pos 0U /*!< TPI ITFTTD0: ATB Interface 1 data0 Position */ +#define TPI_ITFTTD0_ATB_IF1_data0_Msk (0xFFUL /*<< TPI_ITFTTD0_ATB_IF1_data0_Pos*/) /*!< TPI ITFTTD0: ATB Interface 1 data0 Mask */ + +/* TPI Integration Test ATB Control Register 2 Register Definitions */ +#define TPI_ITATBCTR2_AFVALID2S_Pos 1U /*!< TPI ITATBCTR2: AFVALID2S Position */ +#define TPI_ITATBCTR2_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID2S_Pos) /*!< TPI ITATBCTR2: AFVALID2SS Mask */ + +#define TPI_ITATBCTR2_AFVALID1S_Pos 1U /*!< TPI ITATBCTR2: AFVALID1S Position */ +#define TPI_ITATBCTR2_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID1S_Pos) /*!< TPI ITATBCTR2: AFVALID1SS Mask */ + +#define TPI_ITATBCTR2_ATREADY2S_Pos 0U /*!< TPI ITATBCTR2: ATREADY2S Position */ +#define TPI_ITATBCTR2_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2S_Pos*/) /*!< TPI ITATBCTR2: ATREADY2S Mask */ + +#define TPI_ITATBCTR2_ATREADY1S_Pos 0U /*!< TPI ITATBCTR2: ATREADY1S Position */ +#define TPI_ITATBCTR2_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1S_Pos*/) /*!< TPI ITATBCTR2: ATREADY1S Mask */ + +/* TPI Integration Test FIFO Test Data 1 Register Definitions */ +#define TPI_ITFTTD1_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Position */ +#define TPI_ITFTTD1_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Mask */ + +#define TPI_ITFTTD1_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD1: ATB Interface 2 byte count Position */ +#define TPI_ITFTTD1_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 2 byte count Mask */ + +#define TPI_ITFTTD1_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Position */ +#define TPI_ITFTTD1_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Mask */ + +#define TPI_ITFTTD1_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD1: ATB Interface 1 byte count Position */ +#define TPI_ITFTTD1_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 1 byte countt Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data2_Pos 16U /*!< TPI ITFTTD1: ATB Interface 2 data2 Position */ +#define TPI_ITFTTD1_ATB_IF2_data2_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data2 Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data1_Pos 8U /*!< TPI ITFTTD1: ATB Interface 2 data1 Position */ +#define TPI_ITFTTD1_ATB_IF2_data1_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data1 Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data0_Pos 0U /*!< TPI ITFTTD1: ATB Interface 2 data0 Position */ +#define TPI_ITFTTD1_ATB_IF2_data0_Msk (0xFFUL /*<< TPI_ITFTTD1_ATB_IF2_data0_Pos*/) /*!< TPI ITFTTD1: ATB Interface 2 data0 Mask */ + +/* TPI Integration Test ATB Control Register 0 Definitions */ +#define TPI_ITATBCTR0_AFVALID2S_Pos 1U /*!< TPI ITATBCTR0: AFVALID2S Position */ +#define TPI_ITATBCTR0_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID2S_Pos) /*!< TPI ITATBCTR0: AFVALID2SS Mask */ + +#define TPI_ITATBCTR0_AFVALID1S_Pos 1U /*!< TPI ITATBCTR0: AFVALID1S Position */ +#define TPI_ITATBCTR0_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID1S_Pos) /*!< TPI ITATBCTR0: AFVALID1SS Mask */ + +#define TPI_ITATBCTR0_ATREADY2S_Pos 0U /*!< TPI ITATBCTR0: ATREADY2S Position */ +#define TPI_ITATBCTR0_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2S_Pos*/) /*!< TPI ITATBCTR0: ATREADY2S Mask */ + +#define TPI_ITATBCTR0_ATREADY1S_Pos 0U /*!< TPI ITATBCTR0: ATREADY1S Position */ +#define TPI_ITATBCTR0_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1S_Pos*/) /*!< TPI ITATBCTR0: ATREADY1S Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFOSZ Position */ +#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFOSZ Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x3FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */ + __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */ + __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */ + __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */ + uint32_t RESERVED0[1]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ +#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/* MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */ + +/* MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/* MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#else + uint32_t RESERVED0[3]; +#endif + __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */ +} SAU_Type; + +/* SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/* SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/* SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/* SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/* SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/* Secure Fault Status Register Definitions */ +#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */ +#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */ + +#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */ +#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */ + +#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */ +#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */ + +#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */ +#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */ + +#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */ +#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */ + +#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */ +#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */ + +#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */ +#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */ + +#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */ +#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and VFP Feature Register 2 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */ +#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */ + +#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */ +#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */ + +#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */ +#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */ + +#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */ +#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */ + +#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */ +#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */ + +#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */ +#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */ +#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */ +#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and VFP Feature Register 0 Definitions */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and VFP Feature Register 1 Definitions */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/* Media and VFP Feature Register 2 Definitions */ +#define FPU_MVFR2_FPMisc_Pos 4U /*!< MVFR2: FPMisc bits Position */ +#define FPU_MVFR2_FPMisc_Msk (0xFUL << FPU_MVFR2_FPMisc_Pos) /*!< MVFR2: FPMisc bits Mask */ + +/*@} end of group CMSIS_FPU */ + +/* CoreDebug is deprecated. replaced by DCB (Debug Control Block) */ +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief \deprecated Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED0[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< \deprecated CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< \deprecated CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Position */ +#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< \deprecated CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< \deprecated CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< \deprecated CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< \deprecated CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< \deprecated CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< \deprecated CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< \deprecated CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< \deprecated CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< \deprecated CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< \deprecated CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< \deprecated CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< \deprecated CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< \deprecated CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< \deprecated CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< \deprecated CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< \deprecated CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< \deprecated CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< \deprecated CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< \deprecated CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< \deprecated CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< \deprecated CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< \deprecated CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< \deprecated CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< \deprecated CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< \deprecated CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< \deprecated CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< \deprecated CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< \deprecated CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< \deprecated CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< \deprecated CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Mask */ + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Position */ +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Mask */ + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Mask */ + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos 16U /*!< \deprecated CoreDebug DSCSR: CDS Position */ +#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< \deprecated CoreDebug DSCSR: CDS Mask */ + +#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< \deprecated CoreDebug DSCSR: SBRSEL Position */ +#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< \deprecated CoreDebug DSCSR: SBRSEL Mask */ + +#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< \deprecated CoreDebug DSCSR: SBRSELEN Position */ +#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< \deprecated CoreDebug DSCSR: SBRSELEN Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DCB Debug Control Block + \brief Type definitions for the Debug Control Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Control Block Registers (DCB). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED0[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} DCB_Type; + +/* DHCSR, Debug Halting Control and Status Register Definitions */ +#define DCB_DHCSR_DBGKEY_Pos 16U /*!< DCB DHCSR: Debug key Position */ +#define DCB_DHCSR_DBGKEY_Msk (0xFFFFUL << DCB_DHCSR_DBGKEY_Pos) /*!< DCB DHCSR: Debug key Mask */ + +#define DCB_DHCSR_S_RESTART_ST_Pos 26U /*!< DCB DHCSR: Restart sticky status Position */ +#define DCB_DHCSR_S_RESTART_ST_Msk (0x1UL << DCB_DHCSR_S_RESTART_ST_Pos) /*!< DCB DHCSR: Restart sticky status Mask */ + +#define DCB_DHCSR_S_RESET_ST_Pos 25U /*!< DCB DHCSR: Reset sticky status Position */ +#define DCB_DHCSR_S_RESET_ST_Msk (0x1UL << DCB_DHCSR_S_RESET_ST_Pos) /*!< DCB DHCSR: Reset sticky status Mask */ + +#define DCB_DHCSR_S_RETIRE_ST_Pos 24U /*!< DCB DHCSR: Retire sticky status Position */ +#define DCB_DHCSR_S_RETIRE_ST_Msk (0x1UL << DCB_DHCSR_S_RETIRE_ST_Pos) /*!< DCB DHCSR: Retire sticky status Mask */ + +#define DCB_DHCSR_S_SDE_Pos 20U /*!< DCB DHCSR: Secure debug enabled Position */ +#define DCB_DHCSR_S_SDE_Msk (0x1UL << DCB_DHCSR_S_SDE_Pos) /*!< DCB DHCSR: Secure debug enabled Mask */ + +#define DCB_DHCSR_S_LOCKUP_Pos 19U /*!< DCB DHCSR: Lockup status Position */ +#define DCB_DHCSR_S_LOCKUP_Msk (0x1UL << DCB_DHCSR_S_LOCKUP_Pos) /*!< DCB DHCSR: Lockup status Mask */ + +#define DCB_DHCSR_S_SLEEP_Pos 18U /*!< DCB DHCSR: Sleeping status Position */ +#define DCB_DHCSR_S_SLEEP_Msk (0x1UL << DCB_DHCSR_S_SLEEP_Pos) /*!< DCB DHCSR: Sleeping status Mask */ + +#define DCB_DHCSR_S_HALT_Pos 17U /*!< DCB DHCSR: Halted status Position */ +#define DCB_DHCSR_S_HALT_Msk (0x1UL << DCB_DHCSR_S_HALT_Pos) /*!< DCB DHCSR: Halted status Mask */ + +#define DCB_DHCSR_S_REGRDY_Pos 16U /*!< DCB DHCSR: Register ready status Position */ +#define DCB_DHCSR_S_REGRDY_Msk (0x1UL << DCB_DHCSR_S_REGRDY_Pos) /*!< DCB DHCSR: Register ready status Mask */ + +#define DCB_DHCSR_C_SNAPSTALL_Pos 5U /*!< DCB DHCSR: Snap stall control Position */ +#define DCB_DHCSR_C_SNAPSTALL_Msk (0x1UL << DCB_DHCSR_C_SNAPSTALL_Pos) /*!< DCB DHCSR: Snap stall control Mask */ + +#define DCB_DHCSR_C_MASKINTS_Pos 3U /*!< DCB DHCSR: Mask interrupts control Position */ +#define DCB_DHCSR_C_MASKINTS_Msk (0x1UL << DCB_DHCSR_C_MASKINTS_Pos) /*!< DCB DHCSR: Mask interrupts control Mask */ + +#define DCB_DHCSR_C_STEP_Pos 2U /*!< DCB DHCSR: Step control Position */ +#define DCB_DHCSR_C_STEP_Msk (0x1UL << DCB_DHCSR_C_STEP_Pos) /*!< DCB DHCSR: Step control Mask */ + +#define DCB_DHCSR_C_HALT_Pos 1U /*!< DCB DHCSR: Halt control Position */ +#define DCB_DHCSR_C_HALT_Msk (0x1UL << DCB_DHCSR_C_HALT_Pos) /*!< DCB DHCSR: Halt control Mask */ + +#define DCB_DHCSR_C_DEBUGEN_Pos 0U /*!< DCB DHCSR: Debug enable control Position */ +#define DCB_DHCSR_C_DEBUGEN_Msk (0x1UL /*<< DCB_DHCSR_C_DEBUGEN_Pos*/) /*!< DCB DHCSR: Debug enable control Mask */ + +/* DCRSR, Debug Core Register Select Register Definitions */ +#define DCB_DCRSR_REGWnR_Pos 16U /*!< DCB DCRSR: Register write/not-read Position */ +#define DCB_DCRSR_REGWnR_Msk (0x1UL << DCB_DCRSR_REGWnR_Pos) /*!< DCB DCRSR: Register write/not-read Mask */ + +#define DCB_DCRSR_REGSEL_Pos 0U /*!< DCB DCRSR: Register selector Position */ +#define DCB_DCRSR_REGSEL_Msk (0x7FUL /*<< DCB_DCRSR_REGSEL_Pos*/) /*!< DCB DCRSR: Register selector Mask */ + +/* DCRDR, Debug Core Register Data Register Definitions */ +#define DCB_DCRDR_DBGTMP_Pos 0U /*!< DCB DCRDR: Data temporary buffer Position */ +#define DCB_DCRDR_DBGTMP_Msk (0xFFFFFFFFUL /*<< DCB_DCRDR_DBGTMP_Pos*/) /*!< DCB DCRDR: Data temporary buffer Mask */ + +/* DEMCR, Debug Exception and Monitor Control Register Definitions */ +#define DCB_DEMCR_TRCENA_Pos 24U /*!< DCB DEMCR: Trace enable Position */ +#define DCB_DEMCR_TRCENA_Msk (0x1UL << DCB_DEMCR_TRCENA_Pos) /*!< DCB DEMCR: Trace enable Mask */ + +#define DCB_DEMCR_MONPRKEY_Pos 23U /*!< DCB DEMCR: Monitor pend req key Position */ +#define DCB_DEMCR_MONPRKEY_Msk (0x1UL << DCB_DEMCR_MONPRKEY_Pos) /*!< DCB DEMCR: Monitor pend req key Mask */ + +#define DCB_DEMCR_UMON_EN_Pos 21U /*!< DCB DEMCR: Unprivileged monitor enable Position */ +#define DCB_DEMCR_UMON_EN_Msk (0x1UL << DCB_DEMCR_UMON_EN_Pos) /*!< DCB DEMCR: Unprivileged monitor enable Mask */ + +#define DCB_DEMCR_SDME_Pos 20U /*!< DCB DEMCR: Secure DebugMonitor enable Position */ +#define DCB_DEMCR_SDME_Msk (0x1UL << DCB_DEMCR_SDME_Pos) /*!< DCB DEMCR: Secure DebugMonitor enable Mask */ + +#define DCB_DEMCR_MON_REQ_Pos 19U /*!< DCB DEMCR: Monitor request Position */ +#define DCB_DEMCR_MON_REQ_Msk (0x1UL << DCB_DEMCR_MON_REQ_Pos) /*!< DCB DEMCR: Monitor request Mask */ + +#define DCB_DEMCR_MON_STEP_Pos 18U /*!< DCB DEMCR: Monitor step Position */ +#define DCB_DEMCR_MON_STEP_Msk (0x1UL << DCB_DEMCR_MON_STEP_Pos) /*!< DCB DEMCR: Monitor step Mask */ + +#define DCB_DEMCR_MON_PEND_Pos 17U /*!< DCB DEMCR: Monitor pend Position */ +#define DCB_DEMCR_MON_PEND_Msk (0x1UL << DCB_DEMCR_MON_PEND_Pos) /*!< DCB DEMCR: Monitor pend Mask */ + +#define DCB_DEMCR_MON_EN_Pos 16U /*!< DCB DEMCR: Monitor enable Position */ +#define DCB_DEMCR_MON_EN_Msk (0x1UL << DCB_DEMCR_MON_EN_Pos) /*!< DCB DEMCR: Monitor enable Mask */ + +#define DCB_DEMCR_VC_SFERR_Pos 11U /*!< DCB DEMCR: Vector Catch SecureFault Position */ +#define DCB_DEMCR_VC_SFERR_Msk (0x1UL << DCB_DEMCR_VC_SFERR_Pos) /*!< DCB DEMCR: Vector Catch SecureFault Mask */ + +#define DCB_DEMCR_VC_HARDERR_Pos 10U /*!< DCB DEMCR: Vector Catch HardFault errors Position */ +#define DCB_DEMCR_VC_HARDERR_Msk (0x1UL << DCB_DEMCR_VC_HARDERR_Pos) /*!< DCB DEMCR: Vector Catch HardFault errors Mask */ + +#define DCB_DEMCR_VC_INTERR_Pos 9U /*!< DCB DEMCR: Vector Catch interrupt errors Position */ +#define DCB_DEMCR_VC_INTERR_Msk (0x1UL << DCB_DEMCR_VC_INTERR_Pos) /*!< DCB DEMCR: Vector Catch interrupt errors Mask */ + +#define DCB_DEMCR_VC_BUSERR_Pos 8U /*!< DCB DEMCR: Vector Catch BusFault errors Position */ +#define DCB_DEMCR_VC_BUSERR_Msk (0x1UL << DCB_DEMCR_VC_BUSERR_Pos) /*!< DCB DEMCR: Vector Catch BusFault errors Mask */ + +#define DCB_DEMCR_VC_STATERR_Pos 7U /*!< DCB DEMCR: Vector Catch state errors Position */ +#define DCB_DEMCR_VC_STATERR_Msk (0x1UL << DCB_DEMCR_VC_STATERR_Pos) /*!< DCB DEMCR: Vector Catch state errors Mask */ + +#define DCB_DEMCR_VC_CHKERR_Pos 6U /*!< DCB DEMCR: Vector Catch check errors Position */ +#define DCB_DEMCR_VC_CHKERR_Msk (0x1UL << DCB_DEMCR_VC_CHKERR_Pos) /*!< DCB DEMCR: Vector Catch check errors Mask */ + +#define DCB_DEMCR_VC_NOCPERR_Pos 5U /*!< DCB DEMCR: Vector Catch NOCP errors Position */ +#define DCB_DEMCR_VC_NOCPERR_Msk (0x1UL << DCB_DEMCR_VC_NOCPERR_Pos) /*!< DCB DEMCR: Vector Catch NOCP errors Mask */ + +#define DCB_DEMCR_VC_MMERR_Pos 4U /*!< DCB DEMCR: Vector Catch MemManage errors Position */ +#define DCB_DEMCR_VC_MMERR_Msk (0x1UL << DCB_DEMCR_VC_MMERR_Pos) /*!< DCB DEMCR: Vector Catch MemManage errors Mask */ + +#define DCB_DEMCR_VC_CORERESET_Pos 0U /*!< DCB DEMCR: Vector Catch Core reset Position */ +#define DCB_DEMCR_VC_CORERESET_Msk (0x1UL /*<< DCB_DEMCR_VC_CORERESET_Pos*/) /*!< DCB DEMCR: Vector Catch Core reset Mask */ + +/* DAUTHCTRL, Debug Authentication Control Register Definitions */ +#define DCB_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPNIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPNIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPNIDENSEL_Msk (0x1UL << DCB_DAUTHCTRL_SPNIDENSEL_Pos) /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Mask */ + +#define DCB_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< DCB DAUTHCTRL: Secure invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPIDENSEL_Msk (0x1UL /*<< DCB_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< DCB DAUTHCTRL: Secure invasive debug enable select Mask */ + +/* DSCSR, Debug Security Control and Status Register Definitions */ +#define DCB_DSCSR_CDSKEY_Pos 17U /*!< DCB DSCSR: CDS write-enable key Position */ +#define DCB_DSCSR_CDSKEY_Msk (0x1UL << DCB_DSCSR_CDSKEY_Pos) /*!< DCB DSCSR: CDS write-enable key Mask */ + +#define DCB_DSCSR_CDS_Pos 16U /*!< DCB DSCSR: Current domain Secure Position */ +#define DCB_DSCSR_CDS_Msk (0x1UL << DCB_DSCSR_CDS_Pos) /*!< DCB DSCSR: Current domain Secure Mask */ + +#define DCB_DSCSR_SBRSEL_Pos 1U /*!< DCB DSCSR: Secure banked register select Position */ +#define DCB_DSCSR_SBRSEL_Msk (0x1UL << DCB_DSCSR_SBRSEL_Pos) /*!< DCB DSCSR: Secure banked register select Mask */ + +#define DCB_DSCSR_SBRSELEN_Pos 0U /*!< DCB DSCSR: Secure banked register select enable Position */ +#define DCB_DSCSR_SBRSELEN_Msk (0x1UL /*<< DCB_DSCSR_SBRSELEN_Pos*/) /*!< DCB DSCSR: Secure banked register select enable Mask */ + +/*@} end of group CMSIS_DCB */ + + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DIB Debug Identification Block + \brief Type definitions for the Debug Identification Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Identification Block Registers (DIB). + */ +typedef struct +{ + __OM uint32_t DLAR; /*!< Offset: 0x000 ( /W) SCS Software Lock Access Register */ + __IM uint32_t DLSR; /*!< Offset: 0x004 (R/ ) SCS Software Lock Status Register */ + __IM uint32_t DAUTHSTATUS; /*!< Offset: 0x008 (R/ ) Debug Authentication Status Register */ + __IM uint32_t DDEVARCH; /*!< Offset: 0x00C (R/ ) SCS Device Architecture Register */ + __IM uint32_t DDEVTYPE; /*!< Offset: 0x010 (R/ ) SCS Device Type Register */ +} DIB_Type; + +/* DLAR, SCS Software Lock Access Register Definitions */ +#define DIB_DLAR_KEY_Pos 0U /*!< DIB DLAR: KEY Position */ +#define DIB_DLAR_KEY_Msk (0xFFFFFFFFUL /*<< DIB_DLAR_KEY_Pos */) /*!< DIB DLAR: KEY Mask */ + +/* DLSR, SCS Software Lock Status Register Definitions */ +#define DIB_DLSR_nTT_Pos 2U /*!< DIB DLSR: Not thirty-two bit Position */ +#define DIB_DLSR_nTT_Msk (0x1UL << DIB_DLSR_nTT_Pos ) /*!< DIB DLSR: Not thirty-two bit Mask */ + +#define DIB_DLSR_SLK_Pos 1U /*!< DIB DLSR: Software Lock status Position */ +#define DIB_DLSR_SLK_Msk (0x1UL << DIB_DLSR_SLK_Pos ) /*!< DIB DLSR: Software Lock status Mask */ + +#define DIB_DLSR_SLI_Pos 0U /*!< DIB DLSR: Software Lock implemented Position */ +#define DIB_DLSR_SLI_Msk (0x1UL /*<< DIB_DLSR_SLI_Pos*/) /*!< DIB DLSR: Software Lock implemented Mask */ + +/* DAUTHSTATUS, Debug Authentication Status Register Definitions */ +#define DIB_DAUTHSTATUS_SNID_Pos 6U /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_SNID_Msk (0x3UL << DIB_DAUTHSTATUS_SNID_Pos ) /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_SID_Pos 4U /*!< DIB DAUTHSTATUS: Secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_SID_Msk (0x3UL << DIB_DAUTHSTATUS_SID_Pos ) /*!< DIB DAUTHSTATUS: Secure Invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSNID_Pos 2U /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSNID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSID_Pos 0U /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSID_Msk (0x3UL /*<< DIB_DAUTHSTATUS_NSID_Pos*/) /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Mask */ + +/* DDEVARCH, SCS Device Architecture Register Definitions */ +#define DIB_DDEVARCH_ARCHITECT_Pos 21U /*!< DIB DDEVARCH: Architect Position */ +#define DIB_DDEVARCH_ARCHITECT_Msk (0x7FFUL << DIB_DDEVARCH_ARCHITECT_Pos ) /*!< DIB DDEVARCH: Architect Mask */ + +#define DIB_DDEVARCH_PRESENT_Pos 20U /*!< DIB DDEVARCH: DEVARCH Present Position */ +#define DIB_DDEVARCH_PRESENT_Msk (0x1FUL << DIB_DDEVARCH_PRESENT_Pos ) /*!< DIB DDEVARCH: DEVARCH Present Mask */ + +#define DIB_DDEVARCH_REVISION_Pos 16U /*!< DIB DDEVARCH: Revision Position */ +#define DIB_DDEVARCH_REVISION_Msk (0xFUL << DIB_DDEVARCH_REVISION_Pos ) /*!< DIB DDEVARCH: Revision Mask */ + +#define DIB_DDEVARCH_ARCHVER_Pos 12U /*!< DIB DDEVARCH: Architecture Version Position */ +#define DIB_DDEVARCH_ARCHVER_Msk (0xFUL << DIB_DDEVARCH_ARCHVER_Pos ) /*!< DIB DDEVARCH: Architecture Version Mask */ + +#define DIB_DDEVARCH_ARCHPART_Pos 0U /*!< DIB DDEVARCH: Architecture Part Position */ +#define DIB_DDEVARCH_ARCHPART_Msk (0xFFFUL /*<< DIB_DDEVARCH_ARCHPART_Pos*/) /*!< DIB DDEVARCH: Architecture Part Mask */ + +/* DDEVTYPE, SCS Device Type Register Definitions */ +#define DIB_DDEVTYPE_SUB_Pos 4U /*!< DIB DDEVTYPE: Sub-type Position */ +#define DIB_DDEVTYPE_SUB_Msk (0xFUL << DIB_DDEVTYPE_SUB_Pos ) /*!< DIB DDEVTYPE: Sub-type Mask */ + +#define DIB_DDEVTYPE_MAJOR_Pos 0U /*!< DIB DDEVTYPE: Major type Position */ +#define DIB_DDEVTYPE_MAJOR_Msk (0xFUL /*<< DIB_DDEVTYPE_MAJOR_Pos*/) /*!< DIB DDEVTYPE: Major type Mask */ + + +/*@} end of group CMSIS_DIB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ + #define CoreDebug_BASE (0xE000EDF0UL) /*!< \deprecated Core Debug Base Address */ + #define DCB_BASE (0xE000EDF0UL) /*!< DCB Base Address */ + #define DIB_BASE (0xE000EFB0UL) /*!< DIB Base Address */ + #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ + #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ + #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ + #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ + #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ + #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ + #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< \deprecated Core Debug configuration struct */ + #define DCB ((DCB_Type *) DCB_BASE ) /*!< DCB configuration struct */ + #define DIB ((DIB_Type *) DIB_BASE ) /*!< DIB configuration struct */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ + #endif + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ + #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ + #endif + + #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ + #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ + #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< \deprecated Core Debug Base Address (non-secure address space) */ + #define DCB_BASE_NS (0xE002EDF0UL) /*!< DCB Base Address (non-secure address space) */ + #define DIB_BASE_NS (0xE002EFB0UL) /*!< DIB Base Address (non-secure address space) */ + #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ + #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ + #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + + #define SCnSCB_NS ((SCnSCB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */ + #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ + #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ + #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ + #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< \deprecated Core Debug configuration struct (non-secure address space) */ + #define DCB_NS ((DCB_Type *) DCB_BASE_NS ) /*!< DCB configuration struct (non-secure address space) */ + #define DIB_NS ((DIB_Type *) DIB_BASE_NS ) /*!< DIB configuration struct (non-secure address space) */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ + #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ + #endif + + #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */ + #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */ + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_register_aliases Backwards Compatibility Aliases + \brief Register alias definitions for backwards compatibility. + @{ + */ +#define ID_ADR (ID_AFR) /*!< SCB Auxiliary Feature Register */ +/*@} */ + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* Special LR values for Secure/Non-Secure call handling and exception handling */ + +/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ +#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ + +/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ +#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ +#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ +#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ +#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ +#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ +#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */ +#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ + +/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ +#else +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ +#endif + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + __DSB(); +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Priority Grouping (non-secure) + \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB_NS->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB_NS->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping (non-secure) + \details Reads the priority grouping field from the non-secure NVIC when in secure state. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void) +{ + return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv8.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = FPU->MVFR0; + if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U) + { + return 2U; /* Double + Single precision FPU */ + } + else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + + +/* ################################## Debug Control function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DCBFunctions Debug Control Functions + \brief Functions that access the Debug Control Block. + @{ + */ + + +/** + \brief Set Debug Authentication Control Register + \details writes to Debug Authentication Control register. + \param [in] value value to be writen. + */ +__STATIC_INLINE void DCB_SetAuthCtrl(uint32_t value) +{ + __DSB(); + __ISB(); + DCB->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register + \details Reads Debug Authentication Control register. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t DCB_GetAuthCtrl(void) +{ + return (DCB->DAUTHCTRL); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Debug Authentication Control Register (non-secure) + \details writes to non-secure Debug Authentication Control register when in secure state. + \param [in] value value to be writen + */ +__STATIC_INLINE void TZ_DCB_SetAuthCtrl_NS(uint32_t value) +{ + __DSB(); + __ISB(); + DCB_NS->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register (non-secure) + \details Reads non-secure Debug Authentication Control register when in secure state. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t TZ_DCB_GetAuthCtrl_NS(void) +{ + return (DCB_NS->DAUTHCTRL); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## Debug Identification function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DIBFunctions Debug Identification Functions + \brief Functions that access the Debug Identification Block. + @{ + */ + + +/** + \brief Get Debug Authentication Status Register + \details Reads Debug Authentication Status register. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t DIB_GetAuthStatus(void) +{ + return (DIB->DAUTHSTATUS); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Debug Authentication Status Register (non-secure) + \details Reads non-secure Debug Authentication Status register when in secure state. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t TZ_DIB_GetAuthStatus_NS(void) +{ + return (DIB_NS->DAUTHSTATUS); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM35P_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/CMSIS/Core/Include/core_cm4.h b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/CMSIS/Core/Include/core_cm4.h new file mode 100644 index 0000000000..e21cd14925 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/CMSIS/Core/Include/core_cm4.h @@ -0,0 +1,2129 @@ +/**************************************************************************//** + * @file core_cm4.h + * @brief CMSIS Cortex-M4 Core Peripheral Access Layer Header File + * @version V5.1.2 + * @date 04. June 2021 + ******************************************************************************/ +/* + * Copyright (c) 2009-2020 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM4_H_GENERIC +#define __CORE_CM4_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M4 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM4 definitions */ +#define __CM4_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM4_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM4_CMSIS_VERSION ((__CM4_CMSIS_VERSION_MAIN << 16U) | \ + __CM4_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (4U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM4_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM4_H_DEPENDANT +#define __CORE_CM4_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM4_REV + #define __CM4_REV 0x0000U + #warning "__CM4_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 1U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M4 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:1; /*!< bit: 9 Reserved */ + uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit */ + uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */ +#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */ +#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ + uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24U]; + __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RESERVED1[24U]; + __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24U]; + __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24U]; + __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56U]; + __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[5U]; + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_CFSR_MEMFAULTSR_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_DISOOFP_Pos 9U /*!< ACTLR: DISOOFP Position */ +#define SCnSCB_ACTLR_DISOOFP_Msk (1UL << SCnSCB_ACTLR_DISOOFP_Pos) /*!< ACTLR: DISOOFP Mask */ + +#define SCnSCB_ACTLR_DISFPCA_Pos 8U /*!< ACTLR: DISFPCA Position */ +#define SCnSCB_ACTLR_DISFPCA_Msk (1UL << SCnSCB_ACTLR_DISFPCA_Pos) /*!< ACTLR: DISFPCA Mask */ + +#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ +#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR: DISDEFWBUF Position */ +#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ + +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x1UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x1UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY2_Pos 0U /*!< TPI ITATBCTR2: ATREADY2 Position */ +#define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/) /*!< TPI ITATBCTR2: ATREADY2 Mask */ + +#define TPI_ITATBCTR2_ATREADY1_Pos 0U /*!< TPI ITATBCTR2: ATREADY1 Position */ +#define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/) /*!< TPI ITATBCTR2: ATREADY1 Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x1UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x1UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY2_Pos 0U /*!< TPI ITATBCTR0: ATREADY2 Position */ +#define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/) /*!< TPI ITATBCTR0: ATREADY2 Mask */ + +#define TPI_ITATBCTR0_ATREADY1_Pos 0U /*!< TPI ITATBCTR0: ATREADY1 Position */ +#define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/) /*!< TPI ITATBCTR0: ATREADY1 Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif /* defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and FP Feature Register 2 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and FP Feature Register 0 Definitions */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and FP Feature Register 1 Definitions */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/* Media and FP Feature Register 2 Definitions */ + +#define FPU_MVFR2_VFP_Misc_Pos 4U /*!< MVFR2: VFP Misc bits Position */ +#define FPU_MVFR2_VFP_Misc_Msk (0xFUL << FPU_MVFR2_VFP_Misc_Pos) /*!< MVFR2: VFP Misc bits Mask */ + +/*@} end of group CMSIS_FPU */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +#define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ +#define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ +#define EXC_RETURN_HANDLER_FPU (0xFFFFFFE1UL) /* return to Handler mode, uses MSP after return, restore floating-point state */ +#define EXC_RETURN_THREAD_MSP_FPU (0xFFFFFFE9UL) /* return to Thread mode, uses MSP after return, restore floating-point state */ +#define EXC_RETURN_THREAD_PSP_FPU (0xFFFFFFEDUL) /* return to Thread mode, uses PSP after return, restore floating-point state */ + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + /* ARM Application Note 321 states that the M4 does not require the architectural barrier */ +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv7.h" + +#endif + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = FPU->MVFR0; + if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM4_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/CMSIS/Core/Include/core_cm55.h b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/CMSIS/Core/Include/core_cm55.h new file mode 100644 index 0000000000..faa30ce36a --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/CMSIS/Core/Include/core_cm55.h @@ -0,0 +1,4817 @@ +/**************************************************************************//** + * @file core_cm55.h + * @brief CMSIS Cortex-M55 Core Peripheral Access Layer Header File + * @version V1.2.4 + * @date 21. April 2022 + ******************************************************************************/ +/* + * Copyright (c) 2018-2022 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#elif defined ( __GNUC__ ) + #pragma GCC diagnostic ignored "-Wpedantic" /* disable pedantic warning due to unnamed structs/unions */ +#endif + +#ifndef __CORE_CM55_H_GENERIC +#define __CORE_CM55_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M55 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM55 definitions */ +#define __CM55_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM55_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM55_CMSIS_VERSION ((__CM55_CMSIS_VERSION_MAIN << 16U) | \ + __CM55_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (55U) /*!< Cortex-M Core */ + +#if defined ( __CC_ARM ) + #error Legacy Arm Compiler does not support Armv8.1-M target architecture. +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM55_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM55_H_DEPENDANT +#define __CORE_CM55_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM55_REV + #define __CM55_REV 0x0000U + #warning "__CM55_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #if __FPU_PRESENT != 0U + #ifndef __FPU_DP + #define __FPU_DP 0U + #warning "__FPU_DP not defined in device header file; using default!" + #endif + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __ICACHE_PRESENT + #define __ICACHE_PRESENT 0U + #warning "__ICACHE_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DCACHE_PRESENT + #define __DCACHE_PRESENT 0U + #warning "__DCACHE_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 1U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __PMU_PRESENT + #define __PMU_PRESENT 0U + #warning "__PMU_PRESENT not defined in device header file; using default!" + #endif + + #if __PMU_PRESENT != 0U + #ifndef __PMU_NUM_EVENTCNT + #define __PMU_NUM_EVENTCNT 8U + #warning "__PMU_NUM_EVENTCNT not defined in device header file; using default!" + #elif (__PMU_NUM_EVENTCNT > 8 || __PMU_NUM_EVENTCNT < 2) + #error "__PMU_NUM_EVENTCNT is out of range in device header file!" */ + #endif + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DSP_PRESENT + #define __DSP_PRESENT 0U + #warning "__DSP_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M55 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core EWIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core PMU Register + - Core MPU Register + - Core SAU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ +#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */ + uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */ + uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */ +#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */ + +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED6[580U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ + __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ + __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ + __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */ + uint32_t RESERVED7[21U]; + __IOM uint32_t SFSR; /*!< Offset: 0x0E4 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x0E8 (R/W) Secure Fault Address Register */ + uint32_t RESERVED3[69U]; + __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ + __IOM uint32_t RFSR; /*!< Offset: 0x204 (R/W) RAS Fault Status Register */ + uint32_t RESERVED4[14U]; + __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ + uint32_t RESERVED5[1U]; + __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ + uint32_t RESERVED6[1U]; + __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ + __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ + __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ + __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ + __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ + __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ + __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ + __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ + __OM uint32_t BPIALL; /*!< Offset: 0x278 ( /W) Branch Predictor Invalidate All */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ +#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_IESB_Pos 5U /*!< SCB AIRCR: Implicit ESB Enable Position */ +#define SCB_AIRCR_IESB_Msk (1UL << SCB_AIRCR_IESB_Pos) /*!< SCB AIRCR: Implicit ESB Enable Mask */ + +#define SCB_AIRCR_DIT_Pos 4U /*!< SCB AIRCR: Data Independent Timing Position */ +#define SCB_AIRCR_DIT_Msk (1UL << SCB_AIRCR_DIT_Pos) /*!< SCB AIRCR: Data Independent Timing Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_TRD_Pos 20U /*!< SCB CCR: TRD Position */ +#define SCB_CCR_TRD_Msk (1UL << SCB_CCR_TRD_Pos) /*!< SCB CCR: TRD Mask */ + +#define SCB_CCR_LOB_Pos 19U /*!< SCB CCR: LOB Position */ +#define SCB_CCR_LOB_Msk (1UL << SCB_CCR_LOB_Pos) /*!< SCB CCR: LOB Mask */ + +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */ +#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */ +#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */ + +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */ +#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_CFSR_MEMFAULTSR_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */ +#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_PMU_Pos 5U /*!< SCB DFSR: PMU Position */ +#define SCB_DFSR_PMU_Msk (1UL << SCB_DFSR_PMU_Pos) /*!< SCB DFSR: PMU Mask */ + +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/* SCB Non-Secure Access Control Register Definitions */ +#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */ +#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */ + +#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */ +#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */ + +#define SCB_NSACR_CP7_Pos 7U /*!< SCB NSACR: CP7 Position */ +#define SCB_NSACR_CP7_Msk (1UL << SCB_NSACR_CP7_Pos) /*!< SCB NSACR: CP7 Mask */ + +#define SCB_NSACR_CP6_Pos 6U /*!< SCB NSACR: CP6 Position */ +#define SCB_NSACR_CP6_Msk (1UL << SCB_NSACR_CP6_Pos) /*!< SCB NSACR: CP6 Mask */ + +#define SCB_NSACR_CP5_Pos 5U /*!< SCB NSACR: CP5 Position */ +#define SCB_NSACR_CP5_Msk (1UL << SCB_NSACR_CP5_Pos) /*!< SCB NSACR: CP5 Mask */ + +#define SCB_NSACR_CP4_Pos 4U /*!< SCB NSACR: CP4 Position */ +#define SCB_NSACR_CP4_Msk (1UL << SCB_NSACR_CP4_Pos) /*!< SCB NSACR: CP4 Mask */ + +#define SCB_NSACR_CP3_Pos 3U /*!< SCB NSACR: CP3 Position */ +#define SCB_NSACR_CP3_Msk (1UL << SCB_NSACR_CP3_Pos) /*!< SCB NSACR: CP3 Mask */ + +#define SCB_NSACR_CP2_Pos 2U /*!< SCB NSACR: CP2 Position */ +#define SCB_NSACR_CP2_Msk (1UL << SCB_NSACR_CP2_Pos) /*!< SCB NSACR: CP2 Mask */ + +#define SCB_NSACR_CP1_Pos 1U /*!< SCB NSACR: CP1 Position */ +#define SCB_NSACR_CP1_Msk (1UL << SCB_NSACR_CP1_Pos) /*!< SCB NSACR: CP1 Mask */ + +#define SCB_NSACR_CP0_Pos 0U /*!< SCB NSACR: CP0 Position */ +#define SCB_NSACR_CP0_Msk (1UL /*<< SCB_NSACR_CP0_Pos*/) /*!< SCB NSACR: CP0 Mask */ + +/* SCB Debug Feature Register 0 Definitions */ +#define SCB_ID_DFR_UDE_Pos 28U /*!< SCB ID_DFR: UDE Position */ +#define SCB_ID_DFR_UDE_Msk (0xFUL << SCB_ID_DFR_UDE_Pos) /*!< SCB ID_DFR: UDE Mask */ + +#define SCB_ID_DFR_MProfDbg_Pos 20U /*!< SCB ID_DFR: MProfDbg Position */ +#define SCB_ID_DFR_MProfDbg_Msk (0xFUL << SCB_ID_DFR_MProfDbg_Pos) /*!< SCB ID_DFR: MProfDbg Mask */ + +/* SCB Cache Level ID Register Definitions */ +#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ +#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ + +#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ +#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ + +/* SCB Cache Type Register Definitions */ +#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ +#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ + +#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ +#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ + +#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ +#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ + +#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ +#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ + +#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ +#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ + +/* SCB Cache Size ID Register Definitions */ +#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ +#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ + +#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ +#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ + +#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ +#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ + +#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ +#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ + +#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ +#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ + +#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ +#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ + +#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ +#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ + +/* SCB Cache Size Selection Register Definitions */ +#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ +#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ + +#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ +#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ + +/* SCB Software Triggered Interrupt Register Definitions */ +#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ +#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ + +/* SCB RAS Fault Status Register Definitions */ +#define SCB_RFSR_V_Pos 31U /*!< SCB RFSR: V Position */ +#define SCB_RFSR_V_Msk (1UL << SCB_RFSR_V_Pos) /*!< SCB RFSR: V Mask */ + +#define SCB_RFSR_IS_Pos 16U /*!< SCB RFSR: IS Position */ +#define SCB_RFSR_IS_Msk (0x7FFFUL << SCB_RFSR_IS_Pos) /*!< SCB RFSR: IS Mask */ + +#define SCB_RFSR_UET_Pos 0U /*!< SCB RFSR: UET Position */ +#define SCB_RFSR_UET_Msk (3UL /*<< SCB_RFSR_UET_Pos*/) /*!< SCB RFSR: UET Mask */ + +/* SCB D-Cache Invalidate by Set-way Register Definitions */ +#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ +#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ + +#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ +#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ + +/* SCB D-Cache Clean by Set-way Register Definitions */ +#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ +#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ + +#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ +#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ + +/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ +#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ +#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ + +#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ +#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ICB Implementation Control Block register (ICB) + \brief Type definitions for the Implementation Control Block Register + @{ + */ + +/** + \brief Structure type to access the Implementation Control Block (ICB). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ + __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */ +} ICB_Type; + +/* Auxiliary Control Register Definitions */ +#define ICB_ACTLR_DISCRITAXIRUW_Pos 27U /*!< ACTLR: DISCRITAXIRUW Position */ +#define ICB_ACTLR_DISCRITAXIRUW_Msk (1UL << ICB_ACTLR_DISCRITAXIRUW_Pos) /*!< ACTLR: DISCRITAXIRUW Mask */ + +#define ICB_ACTLR_DISDI_Pos 16U /*!< ACTLR: DISDI Position */ +#define ICB_ACTLR_DISDI_Msk (3UL << ICB_ACTLR_DISDI_Pos) /*!< ACTLR: DISDI Mask */ + +#define ICB_ACTLR_DISCRITAXIRUR_Pos 15U /*!< ACTLR: DISCRITAXIRUR Position */ +#define ICB_ACTLR_DISCRITAXIRUR_Msk (1UL << ICB_ACTLR_DISCRITAXIRUR_Pos) /*!< ACTLR: DISCRITAXIRUR Mask */ + +#define ICB_ACTLR_EVENTBUSEN_Pos 14U /*!< ACTLR: EVENTBUSEN Position */ +#define ICB_ACTLR_EVENTBUSEN_Msk (1UL << ICB_ACTLR_EVENTBUSEN_Pos) /*!< ACTLR: EVENTBUSEN Mask */ + +#define ICB_ACTLR_EVENTBUSEN_S_Pos 13U /*!< ACTLR: EVENTBUSEN_S Position */ +#define ICB_ACTLR_EVENTBUSEN_S_Msk (1UL << ICB_ACTLR_EVENTBUSEN_S_Pos) /*!< ACTLR: EVENTBUSEN_S Mask */ + +#define ICB_ACTLR_DISITMATBFLUSH_Pos 12U /*!< ACTLR: DISITMATBFLUSH Position */ +#define ICB_ACTLR_DISITMATBFLUSH_Msk (1UL << ICB_ACTLR_DISITMATBFLUSH_Pos) /*!< ACTLR: DISITMATBFLUSH Mask */ + +#define ICB_ACTLR_DISNWAMODE_Pos 11U /*!< ACTLR: DISNWAMODE Position */ +#define ICB_ACTLR_DISNWAMODE_Msk (1UL << ICB_ACTLR_DISNWAMODE_Pos) /*!< ACTLR: DISNWAMODE Mask */ + +#define ICB_ACTLR_FPEXCODIS_Pos 10U /*!< ACTLR: FPEXCODIS Position */ +#define ICB_ACTLR_FPEXCODIS_Msk (1UL << ICB_ACTLR_FPEXCODIS_Pos) /*!< ACTLR: FPEXCODIS Mask */ + +#define ICB_ACTLR_DISOLAP_Pos 7U /*!< ACTLR: DISOLAP Position */ +#define ICB_ACTLR_DISOLAP_Msk (1UL << ICB_ACTLR_DISOLAP_Pos) /*!< ACTLR: DISOLAP Mask */ + +#define ICB_ACTLR_DISOLAPS_Pos 6U /*!< ACTLR: DISOLAPS Position */ +#define ICB_ACTLR_DISOLAPS_Msk (1UL << ICB_ACTLR_DISOLAPS_Pos) /*!< ACTLR: DISOLAPS Mask */ + +#define ICB_ACTLR_DISLOBR_Pos 5U /*!< ACTLR: DISLOBR Position */ +#define ICB_ACTLR_DISLOBR_Msk (1UL << ICB_ACTLR_DISLOBR_Pos) /*!< ACTLR: DISLOBR Mask */ + +#define ICB_ACTLR_DISLO_Pos 4U /*!< ACTLR: DISLO Position */ +#define ICB_ACTLR_DISLO_Msk (1UL << ICB_ACTLR_DISLO_Pos) /*!< ACTLR: DISLO Mask */ + +#define ICB_ACTLR_DISLOLEP_Pos 3U /*!< ACTLR: DISLOLEP Position */ +#define ICB_ACTLR_DISLOLEP_Msk (1UL << ICB_ACTLR_DISLOLEP_Pos) /*!< ACTLR: DISLOLEP Mask */ + +#define ICB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ +#define ICB_ACTLR_DISFOLD_Msk (1UL << ICB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +/* Interrupt Controller Type Register Definitions */ +#define ICB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define ICB_ICTR_INTLINESNUM_Msk (0xFUL /*<< ICB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_ICB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */ + uint32_t RESERVED6[3U]; + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) ITM Device Type Register */ + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Stimulus Port Register Definitions */ +#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */ +#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */ + +#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */ +#define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */ + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */ +#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */ + +#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */ +#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED14[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED15[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED16[1U]; + __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ + uint32_t RESERVED17[1U]; + __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ + uint32_t RESERVED18[1U]; + __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ + uint32_t RESERVED19[1U]; + __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ + uint32_t RESERVED20[1U]; + __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ + uint32_t RESERVED21[1U]; + __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ + uint32_t RESERVED22[1U]; + __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ + uint32_t RESERVED23[1U]; + __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ + uint32_t RESERVED24[1U]; + __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ + uint32_t RESERVED25[1U]; + __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ + uint32_t RESERVED26[1U]; + __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ + uint32_t RESERVED27[1U]; + __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ + uint32_t RESERVED28[1U]; + __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ + uint32_t RESERVED29[1U]; + __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ + uint32_t RESERVED30[1U]; + __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ + uint32_t RESERVED31[1U]; + __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ + uint32_t RESERVED32[934U]; + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ + uint32_t RESERVED33[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */ +#define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup MemSysCtl_Type Memory System Control Registers (IMPLEMENTATION DEFINED) + \brief Type definitions for the Memory System Control Registers (MEMSYSCTL) + @{ + */ + +/** + \brief Structure type to access the Memory System Control Registers (MEMSYSCTL). + */ +typedef struct +{ + __IOM uint32_t MSCR; /*!< Offset: 0x000 (R/W) Memory System Control Register */ + __IOM uint32_t PFCR; /*!< Offset: 0x004 (R/W) Prefetcher Control Register */ + uint32_t RESERVED1[2U]; + __IOM uint32_t ITCMCR; /*!< Offset: 0x010 (R/W) ITCM Control Register */ + __IOM uint32_t DTCMCR; /*!< Offset: 0x014 (R/W) DTCM Control Register */ + __IOM uint32_t PAHBCR; /*!< Offset: 0x018 (R/W) P-AHB Control Register */ + uint32_t RESERVED2[313U]; + __IOM uint32_t ITGU_CTRL; /*!< Offset: 0x500 (R/W) ITGU Control Register */ + __IOM uint32_t ITGU_CFG; /*!< Offset: 0x504 (R/W) ITGU Configuration Register */ + uint32_t RESERVED3[2U]; + __IOM uint32_t ITGU_LUT[16U]; /*!< Offset: 0x510 (R/W) ITGU Look Up Table Register */ + uint32_t RESERVED4[44U]; + __IOM uint32_t DTGU_CTRL; /*!< Offset: 0x600 (R/W) DTGU Control Registers */ + __IOM uint32_t DTGU_CFG; /*!< Offset: 0x604 (R/W) DTGU Configuration Register */ + uint32_t RESERVED5[2U]; + __IOM uint32_t DTGU_LUT[16U]; /*!< Offset: 0x610 (R/W) DTGU Look Up Table Register */ +} MemSysCtl_Type; + +/* MEMSYSCTL Memory System Control Register (MSCR) Register Definitions */ +#define MEMSYSCTL_MSCR_CPWRDN_Pos 17U /*!< MEMSYSCTL MSCR: CPWRDN Position */ +#define MEMSYSCTL_MSCR_CPWRDN_Msk (0x1UL << MEMSYSCTL_MSCR_CPWRDN_Pos) /*!< MEMSYSCTL MSCR: CPWRDN Mask */ + +#define MEMSYSCTL_MSCR_DCCLEAN_Pos 16U /*!< MEMSYSCTL MSCR: DCCLEAN Position */ +#define MEMSYSCTL_MSCR_DCCLEAN_Msk (0x1UL << MEMSYSCTL_MSCR_DCCLEAN_Pos) /*!< MEMSYSCTL MSCR: DCCLEAN Mask */ + +#define MEMSYSCTL_MSCR_ICACTIVE_Pos 13U /*!< MEMSYSCTL MSCR: ICACTIVE Position */ +#define MEMSYSCTL_MSCR_ICACTIVE_Msk (0x1UL << MEMSYSCTL_MSCR_ICACTIVE_Pos) /*!< MEMSYSCTL MSCR: ICACTIVE Mask */ + +#define MEMSYSCTL_MSCR_DCACTIVE_Pos 12U /*!< MEMSYSCTL MSCR: DCACTIVE Position */ +#define MEMSYSCTL_MSCR_DCACTIVE_Msk (0x1UL << MEMSYSCTL_MSCR_DCACTIVE_Pos) /*!< MEMSYSCTL MSCR: DCACTIVE Mask */ + +#define MEMSYSCTL_MSCR_TECCCHKDIS_Pos 4U /*!< MEMSYSCTL MSCR: TECCCHKDIS Position */ +#define MEMSYSCTL_MSCR_TECCCHKDIS_Msk (0x1UL << MEMSYSCTL_MSCR_TECCCHKDIS_Pos) /*!< MEMSYSCTL MSCR: TECCCHKDIS Mask */ + +#define MEMSYSCTL_MSCR_EVECCFAULT_Pos 3U /*!< MEMSYSCTL MSCR: EVECCFAULT Position */ +#define MEMSYSCTL_MSCR_EVECCFAULT_Msk (0x1UL << MEMSYSCTL_MSCR_EVECCFAULT_Pos) /*!< MEMSYSCTL MSCR: EVECCFAULT Mask */ + +#define MEMSYSCTL_MSCR_FORCEWT_Pos 2U /*!< MEMSYSCTL MSCR: FORCEWT Position */ +#define MEMSYSCTL_MSCR_FORCEWT_Msk (0x1UL << MEMSYSCTL_MSCR_FORCEWT_Pos) /*!< MEMSYSCTL MSCR: FORCEWT Mask */ + +#define MEMSYSCTL_MSCR_ECCEN_Pos 1U /*!< MEMSYSCTL MSCR: ECCEN Position */ +#define MEMSYSCTL_MSCR_ECCEN_Msk (0x1UL << MEMSYSCTL_MSCR_ECCEN_Pos) /*!< MEMSYSCTL MSCR: ECCEN Mask */ + +/* MEMSYSCTL Prefetcher Control Register (PFCR) Register Definitions */ +#define MEMSYSCTL_PFCR_MAX_OS_Pos 7U /*!< MEMSYSCTL PFCR: MAX_OS Position */ +#define MEMSYSCTL_PFCR_MAX_OS_Msk (0x7UL << MEMSYSCTL_PFCR_MAX_OS_Pos) /*!< MEMSYSCTL PFCR: MAX_OS Mask */ + +#define MEMSYSCTL_PFCR_MAX_LA_Pos 4U /*!< MEMSYSCTL PFCR: MAX_LA Position */ +#define MEMSYSCTL_PFCR_MAX_LA_Msk (0x7UL << MEMSYSCTL_PFCR_MAX_LA_Pos) /*!< MEMSYSCTL PFCR: MAX_LA Mask */ + +#define MEMSYSCTL_PFCR_MIN_LA_Pos 1U /*!< MEMSYSCTL PFCR: MIN_LA Position */ +#define MEMSYSCTL_PFCR_MIN_LA_Msk (0x7UL << MEMSYSCTL_PFCR_MIN_LA_Pos) /*!< MEMSYSCTL PFCR: MIN_LA Mask */ + +#define MEMSYSCTL_PFCR_ENABLE_Pos 0U /*!< MEMSYSCTL PFCR: ENABLE Position */ +#define MEMSYSCTL_PFCR_ENABLE_Msk (0x1UL /*<< MEMSYSCTL_PFCR_ENABLE_Pos*/) /*!< MEMSYSCTL PFCR: ENABLE Mask */ + +/* MEMSYSCTL ITCM Control Register (ITCMCR) Register Definitions */ +#define MEMSYSCTL_ITCMCR_SZ_Pos 3U /*!< MEMSYSCTL ITCMCR: SZ Position */ +#define MEMSYSCTL_ITCMCR_SZ_Msk (0xFUL << MEMSYSCTL_ITCMCR_SZ_Pos) /*!< MEMSYSCTL ITCMCR: SZ Mask */ + +#define MEMSYSCTL_ITCMCR_EN_Pos 0U /*!< MEMSYSCTL ITCMCR: EN Position */ +#define MEMSYSCTL_ITCMCR_EN_Msk (0x1UL /*<< MEMSYSCTL_ITCMCR_EN_Pos*/) /*!< MEMSYSCTL ITCMCR: EN Mask */ + +/* MEMSYSCTL DTCM Control Register (DTCMCR) Register Definitions */ +#define MEMSYSCTL_DTCMCR_SZ_Pos 3U /*!< MEMSYSCTL DTCMCR: SZ Position */ +#define MEMSYSCTL_DTCMCR_SZ_Msk (0xFUL << MEMSYSCTL_DTCMCR_SZ_Pos) /*!< MEMSYSCTL DTCMCR: SZ Mask */ + +#define MEMSYSCTL_DTCMCR_EN_Pos 0U /*!< MEMSYSCTL DTCMCR: EN Position */ +#define MEMSYSCTL_DTCMCR_EN_Msk (0x1UL /*<< MEMSYSCTL_DTCMCR_EN_Pos*/) /*!< MEMSYSCTL DTCMCR: EN Mask */ + +/* MEMSYSCTL P-AHB Control Register (PAHBCR) Register Definitions */ +#define MEMSYSCTL_PAHBCR_SZ_Pos 1U /*!< MEMSYSCTL PAHBCR: SZ Position */ +#define MEMSYSCTL_PAHBCR_SZ_Msk (0x7UL << MEMSYSCTL_PAHBCR_SZ_Pos) /*!< MEMSYSCTL PAHBCR: SZ Mask */ + +#define MEMSYSCTL_PAHBCR_EN_Pos 0U /*!< MEMSYSCTL PAHBCR: EN Position */ +#define MEMSYSCTL_PAHBCR_EN_Msk (0x1UL /*<< MEMSYSCTL_PAHBCR_EN_Pos*/) /*!< MEMSYSCTL PAHBCR: EN Mask */ + +/* MEMSYSCTL ITGU Control Register (ITGU_CTRL) Register Definitions */ +#define MEMSYSCTL_ITGU_CTRL_DEREN_Pos 1U /*!< MEMSYSCTL ITGU_CTRL: DEREN Position */ +#define MEMSYSCTL_ITGU_CTRL_DEREN_Msk (0x1UL << MEMSYSCTL_ITGU_CTRL_DEREN_Pos) /*!< MEMSYSCTL ITGU_CTRL: DEREN Mask */ + +#define MEMSYSCTL_ITGU_CTRL_DBFEN_Pos 0U /*!< MEMSYSCTL ITGU_CTRL: DBFEN Position */ +#define MEMSYSCTL_ITGU_CTRL_DBFEN_Msk (0x1UL /*<< MEMSYSCTL_ITGU_CTRL_DBFEN_Pos*/) /*!< MEMSYSCTL ITGU_CTRL: DBFEN Mask */ + +/* MEMSYSCTL ITGU Configuration Register (ITGU_CFG) Register Definitions */ +#define MEMSYSCTL_ITGU_CFG_PRESENT_Pos 31U /*!< MEMSYSCTL ITGU_CFG: PRESENT Position */ +#define MEMSYSCTL_ITGU_CFG_PRESENT_Msk (0x1UL << MEMSYSCTL_ITGU_CFG_PRESENT_Pos) /*!< MEMSYSCTL ITGU_CFG: PRESENT Mask */ + +#define MEMSYSCTL_ITGU_CFG_NUMBLKS_Pos 8U /*!< MEMSYSCTL ITGU_CFG: NUMBLKS Position */ +#define MEMSYSCTL_ITGU_CFG_NUMBLKS_Msk (0xFUL << MEMSYSCTL_ITGU_CFG_NUMBLKS_Pos) /*!< MEMSYSCTL ITGU_CFG: NUMBLKS Mask */ + +#define MEMSYSCTL_ITGU_CFG_BLKSZ_Pos 0U /*!< MEMSYSCTL ITGU_CFG: BLKSZ Position */ +#define MEMSYSCTL_ITGU_CFG_BLKSZ_Msk (0xFUL /*<< MEMSYSCTL_ITGU_CFG_BLKSZ_Pos*/) /*!< MEMSYSCTL ITGU_CFG: BLKSZ Mask */ + +/* MEMSYSCTL DTGU Control Registers (DTGU_CTRL) Register Definitions */ +#define MEMSYSCTL_DTGU_CTRL_DEREN_Pos 1U /*!< MEMSYSCTL DTGU_CTRL: DEREN Position */ +#define MEMSYSCTL_DTGU_CTRL_DEREN_Msk (0x1UL << MEMSYSCTL_DTGU_CTRL_DEREN_Pos) /*!< MEMSYSCTL DTGU_CTRL: DEREN Mask */ + +#define MEMSYSCTL_DTGU_CTRL_DBFEN_Pos 0U /*!< MEMSYSCTL DTGU_CTRL: DBFEN Position */ +#define MEMSYSCTL_DTGU_CTRL_DBFEN_Msk (0x1UL /*<< MEMSYSCTL_DTGU_CTRL_DBFEN_Pos*/) /*!< MEMSYSCTL DTGU_CTRL: DBFEN Mask */ + +/* MEMSYSCTL DTGU Configuration Register (DTGU_CFG) Register Definitions */ +#define MEMSYSCTL_DTGU_CFG_PRESENT_Pos 31U /*!< MEMSYSCTL DTGU_CFG: PRESENT Position */ +#define MEMSYSCTL_DTGU_CFG_PRESENT_Msk (0x1UL << MEMSYSCTL_DTGU_CFG_PRESENT_Pos) /*!< MEMSYSCTL DTGU_CFG: PRESENT Mask */ + +#define MEMSYSCTL_DTGU_CFG_NUMBLKS_Pos 8U /*!< MEMSYSCTL DTGU_CFG: NUMBLKS Position */ +#define MEMSYSCTL_DTGU_CFG_NUMBLKS_Msk (0xFUL << MEMSYSCTL_DTGU_CFG_NUMBLKS_Pos) /*!< MEMSYSCTL DTGU_CFG: NUMBLKS Mask */ + +#define MEMSYSCTL_DTGU_CFG_BLKSZ_Pos 0U /*!< MEMSYSCTL DTGU_CFG: BLKSZ Position */ +#define MEMSYSCTL_DTGU_CFG_BLKSZ_Msk (0xFUL /*<< MEMSYSCTL_DTGU_CFG_BLKSZ_Pos*/) /*!< MEMSYSCTL DTGU_CFG: BLKSZ Mask */ + + +/*@}*/ /* end of group MemSysCtl_Type */ + + +/** + \ingroup CMSIS_core_register + \defgroup PwrModCtl_Type Power Mode Control Registers + \brief Type definitions for the Power Mode Control Registers (PWRMODCTL) + @{ + */ + +/** + \brief Structure type to access the Power Mode Control Registers (PWRMODCTL). + */ +typedef struct +{ + __IOM uint32_t CPDLPSTATE; /*!< Offset: 0x000 (R/W) Core Power Domain Low Power State Register */ + __IOM uint32_t DPDLPSTATE; /*!< Offset: 0x004 (R/W) Debug Power Domain Low Power State Register */ +} PwrModCtl_Type; + +/* PWRMODCTL Core Power Domain Low Power State (CPDLPSTATE) Register Definitions */ +#define PWRMODCTL_CPDLPSTATE_RLPSTATE_Pos 8U /*!< PWRMODCTL CPDLPSTATE: RLPSTATE Position */ +#define PWRMODCTL_CPDLPSTATE_RLPSTATE_Msk (0x3UL << PWRMODCTL_CPDLPSTATE_RLPSTATE_Pos) /*!< PWRMODCTL CPDLPSTATE: RLPSTATE Mask */ + +#define PWRMODCTL_CPDLPSTATE_ELPSTATE_Pos 4U /*!< PWRMODCTL CPDLPSTATE: ELPSTATE Position */ +#define PWRMODCTL_CPDLPSTATE_ELPSTATE_Msk (0x3UL << PWRMODCTL_CPDLPSTATE_ELPSTATE_Pos) /*!< PWRMODCTL CPDLPSTATE: ELPSTATE Mask */ + +#define PWRMODCTL_CPDLPSTATE_CLPSTATE_Pos 0U /*!< PWRMODCTL CPDLPSTATE: CLPSTATE Position */ +#define PWRMODCTL_CPDLPSTATE_CLPSTATE_Msk (0x3UL /*<< PWRMODCTL_CPDLPSTATE_CLPSTATE_Pos*/) /*!< PWRMODCTL CPDLPSTATE: CLPSTATE Mask */ + +/* PWRMODCTL Debug Power Domain Low Power State (DPDLPSTATE) Register Definitions */ +#define PWRMODCTL_DPDLPSTATE_DLPSTATE_Pos 0U /*!< PWRMODCTL DPDLPSTATE: DLPSTATE Position */ +#define PWRMODCTL_DPDLPSTATE_DLPSTATE_Msk (0x3UL /*<< PWRMODCTL_DPDLPSTATE_DLPSTATE_Pos*/) /*!< PWRMODCTL DPDLPSTATE: DLPSTATE Mask */ + +/*@}*/ /* end of group PwrModCtl_Type */ + + +/** + \ingroup CMSIS_core_register + \defgroup EWIC_Type External Wakeup Interrupt Controller Registers + \brief Type definitions for the External Wakeup Interrupt Controller Registers (EWIC) + @{ + */ + +/** + \brief Structure type to access the External Wakeup Interrupt Controller Registers (EWIC). + */ +typedef struct +{ + __OM uint32_t EVENTSPR; /*!< Offset: 0x000 ( /W) Event Set Pending Register */ + uint32_t RESERVED0[31U]; + __IM uint32_t EVENTMASKA; /*!< Offset: 0x080 (R/W) Event Mask A Register */ + __IM uint32_t EVENTMASK[15]; /*!< Offset: 0x084 (R/W) Event Mask Register */ +} EWIC_Type; + +/* EWIC External Wakeup Interrupt Controller (EVENTSPR) Register Definitions */ +#define EWIC_EVENTSPR_EDBGREQ_Pos 2U /*!< EWIC EVENTSPR: EDBGREQ Position */ +#define EWIC_EVENTSPR_EDBGREQ_Msk (0x1UL << EWIC_EVENTSPR_EDBGREQ_Pos) /*!< EWIC EVENTSPR: EDBGREQ Mask */ + +#define EWIC_EVENTSPR_NMI_Pos 1U /*!< EWIC EVENTSPR: NMI Position */ +#define EWIC_EVENTSPR_NMI_Msk (0x1UL << EWIC_EVENTSPR_NMI_Pos) /*!< EWIC EVENTSPR: NMI Mask */ + +#define EWIC_EVENTSPR_EVENT_Pos 0U /*!< EWIC EVENTSPR: EVENT Position */ +#define EWIC_EVENTSPR_EVENT_Msk (0x1UL /*<< EWIC_EVENTSPR_EVENT_Pos*/) /*!< EWIC EVENTSPR: EVENT Mask */ + +/* EWIC External Wakeup Interrupt Controller (EVENTMASKA) Register Definitions */ +#define EWIC_EVENTMASKA_EDBGREQ_Pos 2U /*!< EWIC EVENTMASKA: EDBGREQ Position */ +#define EWIC_EVENTMASKA_EDBGREQ_Msk (0x1UL << EWIC_EVENTMASKA_EDBGREQ_Pos) /*!< EWIC EVENTMASKA: EDBGREQ Mask */ + +#define EWIC_EVENTMASKA_NMI_Pos 1U /*!< EWIC EVENTMASKA: NMI Position */ +#define EWIC_EVENTMASKA_NMI_Msk (0x1UL << EWIC_EVENTMASKA_NMI_Pos) /*!< EWIC EVENTMASKA: NMI Mask */ + +#define EWIC_EVENTMASKA_EVENT_Pos 0U /*!< EWIC EVENTMASKA: EVENT Position */ +#define EWIC_EVENTMASKA_EVENT_Msk (0x1UL /*<< EWIC_EVENTMASKA_EVENT_Pos*/) /*!< EWIC EVENTMASKA: EVENT Mask */ + +/* EWIC External Wakeup Interrupt Controller (EVENTMASK) Register Definitions */ +#define EWIC_EVENTMASK_IRQ_Pos 0U /*!< EWIC EVENTMASKA: IRQ Position */ +#define EWIC_EVENTMASK_IRQ_Msk (0xFFFFFFFFUL /*<< EWIC_EVENTMASKA_IRQ_Pos*/) /*!< EWIC EVENTMASKA: IRQ Mask */ + +/*@}*/ /* end of group EWIC_Type */ + + +/** + \ingroup CMSIS_core_register + \defgroup ErrBnk_Type Error Banking Registers (IMPLEMENTATION DEFINED) + \brief Type definitions for the Error Banking Registers (ERRBNK) + @{ + */ + +/** + \brief Structure type to access the Error Banking Registers (ERRBNK). + */ +typedef struct +{ + __IOM uint32_t IEBR0; /*!< Offset: 0x000 (R/W) Instruction Cache Error Bank Register 0 */ + __IOM uint32_t IEBR1; /*!< Offset: 0x004 (R/W) Instruction Cache Error Bank Register 1 */ + uint32_t RESERVED0[2U]; + __IOM uint32_t DEBR0; /*!< Offset: 0x010 (R/W) Data Cache Error Bank Register 0 */ + __IOM uint32_t DEBR1; /*!< Offset: 0x014 (R/W) Data Cache Error Bank Register 1 */ + uint32_t RESERVED1[2U]; + __IOM uint32_t TEBR0; /*!< Offset: 0x020 (R/W) TCM Error Bank Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t TEBR1; /*!< Offset: 0x028 (R/W) TCM Error Bank Register 1 */ +} ErrBnk_Type; + +/* ERRBNK Instruction Cache Error Bank Register 0 (IEBR0) Register Definitions */ +#define ERRBNK_IEBR0_SWDEF_Pos 30U /*!< ERRBNK IEBR0: SWDEF Position */ +#define ERRBNK_IEBR0_SWDEF_Msk (0x3UL << ERRBNK_IEBR0_SWDEF_Pos) /*!< ERRBNK IEBR0: SWDEF Mask */ + +#define ERRBNK_IEBR0_BANK_Pos 16U /*!< ERRBNK IEBR0: BANK Position */ +#define ERRBNK_IEBR0_BANK_Msk (0x1UL << ERRBNK_IEBR0_BANK_Pos) /*!< ERRBNK IEBR0: BANK Mask */ + +#define ERRBNK_IEBR0_LOCATION_Pos 2U /*!< ERRBNK IEBR0: LOCATION Position */ +#define ERRBNK_IEBR0_LOCATION_Msk (0x3FFFUL << ERRBNK_IEBR0_LOCATION_Pos) /*!< ERRBNK IEBR0: LOCATION Mask */ + +#define ERRBNK_IEBR0_LOCKED_Pos 1U /*!< ERRBNK IEBR0: LOCKED Position */ +#define ERRBNK_IEBR0_LOCKED_Msk (0x1UL << ERRBNK_IEBR0_LOCKED_Pos) /*!< ERRBNK IEBR0: LOCKED Mask */ + +#define ERRBNK_IEBR0_VALID_Pos 0U /*!< ERRBNK IEBR0: VALID Position */ +#define ERRBNK_IEBR0_VALID_Msk (0x1UL << /*ERRBNK_IEBR0_VALID_Pos*/) /*!< ERRBNK IEBR0: VALID Mask */ + +/* ERRBNK Instruction Cache Error Bank Register 1 (IEBR1) Register Definitions */ +#define ERRBNK_IEBR1_SWDEF_Pos 30U /*!< ERRBNK IEBR1: SWDEF Position */ +#define ERRBNK_IEBR1_SWDEF_Msk (0x3UL << ERRBNK_IEBR1_SWDEF_Pos) /*!< ERRBNK IEBR1: SWDEF Mask */ + +#define ERRBNK_IEBR1_BANK_Pos 16U /*!< ERRBNK IEBR1: BANK Position */ +#define ERRBNK_IEBR1_BANK_Msk (0x1UL << ERRBNK_IEBR1_BANK_Pos) /*!< ERRBNK IEBR1: BANK Mask */ + +#define ERRBNK_IEBR1_LOCATION_Pos 2U /*!< ERRBNK IEBR1: LOCATION Position */ +#define ERRBNK_IEBR1_LOCATION_Msk (0x3FFFUL << ERRBNK_IEBR1_LOCATION_Pos) /*!< ERRBNK IEBR1: LOCATION Mask */ + +#define ERRBNK_IEBR1_LOCKED_Pos 1U /*!< ERRBNK IEBR1: LOCKED Position */ +#define ERRBNK_IEBR1_LOCKED_Msk (0x1UL << ERRBNK_IEBR1_LOCKED_Pos) /*!< ERRBNK IEBR1: LOCKED Mask */ + +#define ERRBNK_IEBR1_VALID_Pos 0U /*!< ERRBNK IEBR1: VALID Position */ +#define ERRBNK_IEBR1_VALID_Msk (0x1UL << /*ERRBNK_IEBR1_VALID_Pos*/) /*!< ERRBNK IEBR1: VALID Mask */ + +/* ERRBNK Data Cache Error Bank Register 0 (DEBR0) Register Definitions */ +#define ERRBNK_DEBR0_SWDEF_Pos 30U /*!< ERRBNK DEBR0: SWDEF Position */ +#define ERRBNK_DEBR0_SWDEF_Msk (0x3UL << ERRBNK_DEBR0_SWDEF_Pos) /*!< ERRBNK DEBR0: SWDEF Mask */ + +#define ERRBNK_DEBR0_TYPE_Pos 17U /*!< ERRBNK DEBR0: TYPE Position */ +#define ERRBNK_DEBR0_TYPE_Msk (0x1UL << ERRBNK_DEBR0_TYPE_Pos) /*!< ERRBNK DEBR0: TYPE Mask */ + +#define ERRBNK_DEBR0_BANK_Pos 16U /*!< ERRBNK DEBR0: BANK Position */ +#define ERRBNK_DEBR0_BANK_Msk (0x1UL << ERRBNK_DEBR0_BANK_Pos) /*!< ERRBNK DEBR0: BANK Mask */ + +#define ERRBNK_DEBR0_LOCATION_Pos 2U /*!< ERRBNK DEBR0: LOCATION Position */ +#define ERRBNK_DEBR0_LOCATION_Msk (0x3FFFUL << ERRBNK_DEBR0_LOCATION_Pos) /*!< ERRBNK DEBR0: LOCATION Mask */ + +#define ERRBNK_DEBR0_LOCKED_Pos 1U /*!< ERRBNK DEBR0: LOCKED Position */ +#define ERRBNK_DEBR0_LOCKED_Msk (0x1UL << ERRBNK_DEBR0_LOCKED_Pos) /*!< ERRBNK DEBR0: LOCKED Mask */ + +#define ERRBNK_DEBR0_VALID_Pos 0U /*!< ERRBNK DEBR0: VALID Position */ +#define ERRBNK_DEBR0_VALID_Msk (0x1UL << /*ERRBNK_DEBR0_VALID_Pos*/) /*!< ERRBNK DEBR0: VALID Mask */ + +/* ERRBNK Data Cache Error Bank Register 1 (DEBR1) Register Definitions */ +#define ERRBNK_DEBR1_SWDEF_Pos 30U /*!< ERRBNK DEBR1: SWDEF Position */ +#define ERRBNK_DEBR1_SWDEF_Msk (0x3UL << ERRBNK_DEBR1_SWDEF_Pos) /*!< ERRBNK DEBR1: SWDEF Mask */ + +#define ERRBNK_DEBR1_TYPE_Pos 17U /*!< ERRBNK DEBR1: TYPE Position */ +#define ERRBNK_DEBR1_TYPE_Msk (0x1UL << ERRBNK_DEBR1_TYPE_Pos) /*!< ERRBNK DEBR1: TYPE Mask */ + +#define ERRBNK_DEBR1_BANK_Pos 16U /*!< ERRBNK DEBR1: BANK Position */ +#define ERRBNK_DEBR1_BANK_Msk (0x1UL << ERRBNK_DEBR1_BANK_Pos) /*!< ERRBNK DEBR1: BANK Mask */ + +#define ERRBNK_DEBR1_LOCATION_Pos 2U /*!< ERRBNK DEBR1: LOCATION Position */ +#define ERRBNK_DEBR1_LOCATION_Msk (0x3FFFUL << ERRBNK_DEBR1_LOCATION_Pos) /*!< ERRBNK DEBR1: LOCATION Mask */ + +#define ERRBNK_DEBR1_LOCKED_Pos 1U /*!< ERRBNK DEBR1: LOCKED Position */ +#define ERRBNK_DEBR1_LOCKED_Msk (0x1UL << ERRBNK_DEBR1_LOCKED_Pos) /*!< ERRBNK DEBR1: LOCKED Mask */ + +#define ERRBNK_DEBR1_VALID_Pos 0U /*!< ERRBNK DEBR1: VALID Position */ +#define ERRBNK_DEBR1_VALID_Msk (0x1UL << /*ERRBNK_DEBR1_VALID_Pos*/) /*!< ERRBNK DEBR1: VALID Mask */ + +/* ERRBNK TCM Error Bank Register 0 (TEBR0) Register Definitions */ +#define ERRBNK_TEBR0_SWDEF_Pos 30U /*!< ERRBNK TEBR0: SWDEF Position */ +#define ERRBNK_TEBR0_SWDEF_Msk (0x3UL << ERRBNK_TEBR0_SWDEF_Pos) /*!< ERRBNK TEBR0: SWDEF Mask */ + +#define ERRBNK_TEBR0_POISON_Pos 28U /*!< ERRBNK TEBR0: POISON Position */ +#define ERRBNK_TEBR0_POISON_Msk (0x1UL << ERRBNK_TEBR0_POISON_Pos) /*!< ERRBNK TEBR0: POISON Mask */ + +#define ERRBNK_TEBR0_TYPE_Pos 27U /*!< ERRBNK TEBR0: TYPE Position */ +#define ERRBNK_TEBR0_TYPE_Msk (0x1UL << ERRBNK_TEBR0_TYPE_Pos) /*!< ERRBNK TEBR0: TYPE Mask */ + +#define ERRBNK_TEBR0_BANK_Pos 24U /*!< ERRBNK TEBR0: BANK Position */ +#define ERRBNK_TEBR0_BANK_Msk (0x3UL << ERRBNK_TEBR0_BANK_Pos) /*!< ERRBNK TEBR0: BANK Mask */ + +#define ERRBNK_TEBR0_LOCATION_Pos 2U /*!< ERRBNK TEBR0: LOCATION Position */ +#define ERRBNK_TEBR0_LOCATION_Msk (0x3FFFFFUL << ERRBNK_TEBR0_LOCATION_Pos) /*!< ERRBNK TEBR0: LOCATION Mask */ + +#define ERRBNK_TEBR0_LOCKED_Pos 1U /*!< ERRBNK TEBR0: LOCKED Position */ +#define ERRBNK_TEBR0_LOCKED_Msk (0x1UL << ERRBNK_TEBR0_LOCKED_Pos) /*!< ERRBNK TEBR0: LOCKED Mask */ + +#define ERRBNK_TEBR0_VALID_Pos 0U /*!< ERRBNK TEBR0: VALID Position */ +#define ERRBNK_TEBR0_VALID_Msk (0x1UL << /*ERRBNK_TEBR0_VALID_Pos*/) /*!< ERRBNK TEBR0: VALID Mask */ + +/* ERRBNK TCM Error Bank Register 1 (TEBR1) Register Definitions */ +#define ERRBNK_TEBR1_SWDEF_Pos 30U /*!< ERRBNK TEBR1: SWDEF Position */ +#define ERRBNK_TEBR1_SWDEF_Msk (0x3UL << ERRBNK_TEBR1_SWDEF_Pos) /*!< ERRBNK TEBR1: SWDEF Mask */ + +#define ERRBNK_TEBR1_POISON_Pos 28U /*!< ERRBNK TEBR1: POISON Position */ +#define ERRBNK_TEBR1_POISON_Msk (0x1UL << ERRBNK_TEBR1_POISON_Pos) /*!< ERRBNK TEBR1: POISON Mask */ + +#define ERRBNK_TEBR1_TYPE_Pos 27U /*!< ERRBNK TEBR1: TYPE Position */ +#define ERRBNK_TEBR1_TYPE_Msk (0x1UL << ERRBNK_TEBR1_TYPE_Pos) /*!< ERRBNK TEBR1: TYPE Mask */ + +#define ERRBNK_TEBR1_BANK_Pos 24U /*!< ERRBNK TEBR1: BANK Position */ +#define ERRBNK_TEBR1_BANK_Msk (0x3UL << ERRBNK_TEBR1_BANK_Pos) /*!< ERRBNK TEBR1: BANK Mask */ + +#define ERRBNK_TEBR1_LOCATION_Pos 2U /*!< ERRBNK TEBR1: LOCATION Position */ +#define ERRBNK_TEBR1_LOCATION_Msk (0x3FFFFFUL << ERRBNK_TEBR1_LOCATION_Pos) /*!< ERRBNK TEBR1: LOCATION Mask */ + +#define ERRBNK_TEBR1_LOCKED_Pos 1U /*!< ERRBNK TEBR1: LOCKED Position */ +#define ERRBNK_TEBR1_LOCKED_Msk (0x1UL << ERRBNK_TEBR1_LOCKED_Pos) /*!< ERRBNK TEBR1: LOCKED Mask */ + +#define ERRBNK_TEBR1_VALID_Pos 0U /*!< ERRBNK TEBR1: VALID Position */ +#define ERRBNK_TEBR1_VALID_Msk (0x1UL << /*ERRBNK_TEBR1_VALID_Pos*/) /*!< ERRBNK TEBR1: VALID Mask */ + +/*@}*/ /* end of group ErrBnk_Type */ + + +/** + \ingroup CMSIS_core_register + \defgroup PrcCfgInf_Type Processor Configuration Information Registers (IMPLEMENTATION DEFINED) + \brief Type definitions for the Processor Configuration Information Registerss (PRCCFGINF) + @{ + */ + +/** + \brief Structure type to access the Processor Configuration Information Registerss (PRCCFGINF). + */ +typedef struct +{ + __OM uint32_t CFGINFOSEL; /*!< Offset: 0x000 ( /W) Processor Configuration Information Selection Register */ + __IM uint32_t CFGINFORD; /*!< Offset: 0x004 (R/ ) Processor Configuration Information Read Data Register */ +} PrcCfgInf_Type; + +/* PRCCFGINF Processor Configuration Information Selection Register (CFGINFOSEL) Definitions */ + +/* PRCCFGINF Processor Configuration Information Read Data Register (CFGINFORD) Definitions */ + +/*@}*/ /* end of group PrcCfgInf_Type */ + + +/** + \ingroup CMSIS_core_register + \defgroup STL_Type Software Test Library Observation Registers + \brief Type definitions for the Software Test Library Observation Registerss (STL) + @{ + */ + +/** + \brief Structure type to access the Software Test Library Observation Registerss (STL). + */ +typedef struct +{ + __IM uint32_t STLNVICPENDOR; /*!< Offset: 0x000 (R/ ) NVIC Pending Priority Tree Register */ + __IM uint32_t STLNVICACTVOR; /*!< Offset: 0x004 (R/ ) NVIC Active Priority Tree Register */ + uint32_t RESERVED0[2U]; + __OM uint32_t STLIDMPUSR; /*!< Offset: 0x010 ( /W) MPU Sanple Register */ + __IM uint32_t STLIMPUOR; /*!< Offset: 0x014 (R/ ) MPU Region Hit Register */ + __IM uint32_t STLD0MPUOR; /*!< Offset: 0x018 (R/ ) MPU Memory Attributes Register 0 */ + __IM uint32_t STLD1MPUOR; /*!< Offset: 0x01C (R/ ) MPU Memory Attributes Register 1 */ + +} STL_Type; + +/* STL Software Test Library Observation Register (STLNVICPENDOR) Definitions */ +#define STL_STLNVICPENDOR_VALID_Pos 18U /*!< STL STLNVICPENDOR: VALID Position */ +#define STL_STLNVICPENDOR_VALID_Msk (0x1UL << STL_STLNVICPENDOR_VALID_Pos) /*!< STL STLNVICPENDOR: VALID Mask */ + +#define STL_STLNVICPENDOR_TARGET_Pos 17U /*!< STL STLNVICPENDOR: TARGET Position */ +#define STL_STLNVICPENDOR_TARGET_Msk (0x1UL << STL_STLNVICPENDOR_TARGET_Pos) /*!< STL STLNVICPENDOR: TARGET Mask */ + +#define STL_STLNVICPENDOR_PRIORITY_Pos 9U /*!< STL STLNVICPENDOR: PRIORITY Position */ +#define STL_STLNVICPENDOR_PRIORITY_Msk (0xFFUL << STL_STLNVICPENDOR_PRIORITY_Pos) /*!< STL STLNVICPENDOR: PRIORITY Mask */ + +#define STL_STLNVICPENDOR_INTNUM_Pos 0U /*!< STL STLNVICPENDOR: INTNUM Position */ +#define STL_STLNVICPENDOR_INTNUM_Msk (0x1FFUL /*<< STL_STLNVICPENDOR_INTNUM_Pos*/) /*!< STL STLNVICPENDOR: INTNUM Mask */ + +/* STL Software Test Library Observation Register (STLNVICACTVOR) Definitions */ +#define STL_STLNVICACTVOR_VALID_Pos 18U /*!< STL STLNVICACTVOR: VALID Position */ +#define STL_STLNVICACTVOR_VALID_Msk (0x1UL << STL_STLNVICACTVOR_VALID_Pos) /*!< STL STLNVICACTVOR: VALID Mask */ + +#define STL_STLNVICACTVOR_TARGET_Pos 17U /*!< STL STLNVICACTVOR: TARGET Position */ +#define STL_STLNVICACTVOR_TARGET_Msk (0x1UL << STL_STLNVICACTVOR_TARGET_Pos) /*!< STL STLNVICACTVOR: TARGET Mask */ + +#define STL_STLNVICACTVOR_PRIORITY_Pos 9U /*!< STL STLNVICACTVOR: PRIORITY Position */ +#define STL_STLNVICACTVOR_PRIORITY_Msk (0xFFUL << STL_STLNVICACTVOR_PRIORITY_Pos) /*!< STL STLNVICACTVOR: PRIORITY Mask */ + +#define STL_STLNVICACTVOR_INTNUM_Pos 0U /*!< STL STLNVICACTVOR: INTNUM Position */ +#define STL_STLNVICACTVOR_INTNUM_Msk (0x1FFUL /*<< STL_STLNVICACTVOR_INTNUM_Pos*/) /*!< STL STLNVICACTVOR: INTNUM Mask */ + +/* STL Software Test Library Observation Register (STLIDMPUSR) Definitions */ +#define STL_STLIDMPUSR_ADDR_Pos 5U /*!< STL STLIDMPUSR: ADDR Position */ +#define STL_STLIDMPUSR_ADDR_Msk (0x7FFFFFFUL << STL_STLIDMPUSR_ADDR_Pos) /*!< STL STLIDMPUSR: ADDR Mask */ + +#define STL_STLIDMPUSR_INSTR_Pos 2U /*!< STL STLIDMPUSR: INSTR Position */ +#define STL_STLIDMPUSR_INSTR_Msk (0x1UL << STL_STLIDMPUSR_INSTR_Pos) /*!< STL STLIDMPUSR: INSTR Mask */ + +#define STL_STLIDMPUSR_DATA_Pos 1U /*!< STL STLIDMPUSR: DATA Position */ +#define STL_STLIDMPUSR_DATA_Msk (0x1UL << STL_STLIDMPUSR_DATA_Pos) /*!< STL STLIDMPUSR: DATA Mask */ + +/* STL Software Test Library Observation Register (STLIMPUOR) Definitions */ +#define STL_STLIMPUOR_HITREGION_Pos 9U /*!< STL STLIMPUOR: HITREGION Position */ +#define STL_STLIMPUOR_HITREGION_Msk (0xFFUL << STL_STLIMPUOR_HITREGION_Pos) /*!< STL STLIMPUOR: HITREGION Mask */ + +#define STL_STLIMPUOR_ATTR_Pos 0U /*!< STL STLIMPUOR: ATTR Position */ +#define STL_STLIMPUOR_ATTR_Msk (0x1FFUL /*<< STL_STLIMPUOR_ATTR_Pos*/) /*!< STL STLIMPUOR: ATTR Mask */ + +/* STL Software Test Library Observation Register (STLD0MPUOR) Definitions */ +#define STL_STLD0MPUOR_HITREGION_Pos 9U /*!< STL STLD0MPUOR: HITREGION Position */ +#define STL_STLD0MPUOR_HITREGION_Msk (0xFFUL << STL_STLD0MPUOR_HITREGION_Pos) /*!< STL STLD0MPUOR: HITREGION Mask */ + +#define STL_STLD0MPUOR_ATTR_Pos 0U /*!< STL STLD0MPUOR: ATTR Position */ +#define STL_STLD0MPUOR_ATTR_Msk (0x1FFUL /*<< STL_STLD0MPUOR_ATTR_Pos*/) /*!< STL STLD0MPUOR: ATTR Mask */ + +/* STL Software Test Library Observation Register (STLD1MPUOR) Definitions */ +#define STL_STLD1MPUOR_HITREGION_Pos 9U /*!< STL STLD1MPUOR: HITREGION Position */ +#define STL_STLD1MPUOR_HITREGION_Msk (0xFFUL << STL_STLD1MPUOR_HITREGION_Pos) /*!< STL STLD1MPUOR: HITREGION Mask */ + +#define STL_STLD1MPUOR_ATTR_Pos 0U /*!< STL STLD1MPUOR: ATTR Position */ +#define STL_STLD1MPUOR_ATTR_Msk (0x1FFUL /*<< STL_STLD1MPUOR_ATTR_Pos*/) /*!< STL STLD1MPUOR: ATTR Mask */ + +/*@}*/ /* end of group STL_Type */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Sizes Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Sizes Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ + uint32_t RESERVED3[809U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) Software Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) Software Lock Status Register */ + uint32_t RESERVED4[4U]; + __IM uint32_t TYPE; /*!< Offset: 0xFC8 (R/ ) Device Identifier Register */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Register */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_SWOSCALER_Pos 0U /*!< TPI ACPR: SWOSCALER Position */ +#define TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/) /*!< TPI ACPR: SWOSCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ +#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ + +#define TPI_FFCR_EnFmt_Pos 0U /*!< TPI FFCR: EnFmt Position */ +#define TPI_FFCR_EnFmt_Msk (0x3UL << /*TPI_FFCR_EnFmt_Pos*/) /*!< TPI FFCR: EnFmt Mask */ + +/* TPI Periodic Synchronization Control Register Definitions */ +#define TPI_PSCR_PSCount_Pos 0U /*!< TPI PSCR: PSCount Position */ +#define TPI_PSCR_PSCount_Msk (0x1FUL /*<< TPI_PSCR_PSCount_Pos*/) /*!< TPI PSCR: TPSCount Mask */ + +/* TPI Software Lock Status Register Definitions */ +#define TPI_LSR_nTT_Pos 1U /*!< TPI LSR: Not thirty-two bit. Position */ +#define TPI_LSR_nTT_Msk (0x1UL << TPI_LSR_nTT_Pos) /*!< TPI LSR: Not thirty-two bit. Mask */ + +#define TPI_LSR_SLK_Pos 1U /*!< TPI LSR: Software Lock status Position */ +#define TPI_LSR_SLK_Msk (0x1UL << TPI_LSR_SLK_Pos) /*!< TPI LSR: Software Lock status Mask */ + +#define TPI_LSR_SLI_Pos 0U /*!< TPI LSR: Software Lock implemented Position */ +#define TPI_LSR_SLI_Msk (0x1UL /*<< TPI_LSR_SLI_Pos*/) /*!< TPI LSR: Software Lock implemented Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFO depth Position */ +#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFO depth Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + +#if defined (__PMU_PRESENT) && (__PMU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_PMU Performance Monitoring Unit (PMU) + \brief Type definitions for the Performance Monitoring Unit (PMU) + @{ + */ + +/** + \brief Structure type to access the Performance Monitoring Unit (PMU). + */ +typedef struct +{ + __IOM uint32_t EVCNTR[__PMU_NUM_EVENTCNT]; /*!< Offset: 0x0 (R/W) PMU Event Counter Registers */ +#if __PMU_NUM_EVENTCNT<31 + uint32_t RESERVED0[31U-__PMU_NUM_EVENTCNT]; +#endif + __IOM uint32_t CCNTR; /*!< Offset: 0x7C (R/W) PMU Cycle Counter Register */ + uint32_t RESERVED1[224]; + __IOM uint32_t EVTYPER[__PMU_NUM_EVENTCNT]; /*!< Offset: 0x400 (R/W) PMU Event Type and Filter Registers */ +#if __PMU_NUM_EVENTCNT<31 + uint32_t RESERVED2[31U-__PMU_NUM_EVENTCNT]; +#endif + __IOM uint32_t CCFILTR; /*!< Offset: 0x47C (R/W) PMU Cycle Counter Filter Register */ + uint32_t RESERVED3[480]; + __IOM uint32_t CNTENSET; /*!< Offset: 0xC00 (R/W) PMU Count Enable Set Register */ + uint32_t RESERVED4[7]; + __IOM uint32_t CNTENCLR; /*!< Offset: 0xC20 (R/W) PMU Count Enable Clear Register */ + uint32_t RESERVED5[7]; + __IOM uint32_t INTENSET; /*!< Offset: 0xC40 (R/W) PMU Interrupt Enable Set Register */ + uint32_t RESERVED6[7]; + __IOM uint32_t INTENCLR; /*!< Offset: 0xC60 (R/W) PMU Interrupt Enable Clear Register */ + uint32_t RESERVED7[7]; + __IOM uint32_t OVSCLR; /*!< Offset: 0xC80 (R/W) PMU Overflow Flag Status Clear Register */ + uint32_t RESERVED8[7]; + __IOM uint32_t SWINC; /*!< Offset: 0xCA0 (R/W) PMU Software Increment Register */ + uint32_t RESERVED9[7]; + __IOM uint32_t OVSSET; /*!< Offset: 0xCC0 (R/W) PMU Overflow Flag Status Set Register */ + uint32_t RESERVED10[79]; + __IOM uint32_t TYPE; /*!< Offset: 0xE00 (R/W) PMU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0xE04 (R/W) PMU Control Register */ + uint32_t RESERVED11[108]; + __IOM uint32_t AUTHSTATUS; /*!< Offset: 0xFB8 (R/W) PMU Authentication Status Register */ + __IOM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/W) PMU Device Architecture Register */ + uint32_t RESERVED12[3]; + __IOM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/W) PMU Device Type Register */ + __IOM uint32_t PIDR4; /*!< Offset: 0xFD0 (R/W) PMU Peripheral Identification Register 4 */ + uint32_t RESERVED13[3]; + __IOM uint32_t PIDR0; /*!< Offset: 0xFE0 (R/W) PMU Peripheral Identification Register 0 */ + __IOM uint32_t PIDR1; /*!< Offset: 0xFE4 (R/W) PMU Peripheral Identification Register 1 */ + __IOM uint32_t PIDR2; /*!< Offset: 0xFE8 (R/W) PMU Peripheral Identification Register 2 */ + __IOM uint32_t PIDR3; /*!< Offset: 0xFEC (R/W) PMU Peripheral Identification Register 3 */ + __IOM uint32_t CIDR0; /*!< Offset: 0xFF0 (R/W) PMU Component Identification Register 0 */ + __IOM uint32_t CIDR1; /*!< Offset: 0xFF4 (R/W) PMU Component Identification Register 1 */ + __IOM uint32_t CIDR2; /*!< Offset: 0xFF8 (R/W) PMU Component Identification Register 2 */ + __IOM uint32_t CIDR3; /*!< Offset: 0xFFC (R/W) PMU Component Identification Register 3 */ +} PMU_Type; + +/** \brief PMU Event Counter Registers (0-30) Definitions */ + +#define PMU_EVCNTR_CNT_Pos 0U /*!< PMU EVCNTR: Counter Position */ +#define PMU_EVCNTR_CNT_Msk (0xFFFFUL /*<< PMU_EVCNTRx_CNT_Pos*/) /*!< PMU EVCNTR: Counter Mask */ + +/** \brief PMU Event Type and Filter Registers (0-30) Definitions */ + +#define PMU_EVTYPER_EVENTTOCNT_Pos 0U /*!< PMU EVTYPER: Event to Count Position */ +#define PMU_EVTYPER_EVENTTOCNT_Msk (0xFFFFUL /*<< EVTYPERx_EVENTTOCNT_Pos*/) /*!< PMU EVTYPER: Event to Count Mask */ + +/** \brief PMU Count Enable Set Register Definitions */ + +#define PMU_CNTENSET_CNT0_ENABLE_Pos 0U /*!< PMU CNTENSET: Event Counter 0 Enable Set Position */ +#define PMU_CNTENSET_CNT0_ENABLE_Msk (1UL /*<< PMU_CNTENSET_CNT0_ENABLE_Pos*/) /*!< PMU CNTENSET: Event Counter 0 Enable Set Mask */ + +#define PMU_CNTENSET_CNT1_ENABLE_Pos 1U /*!< PMU CNTENSET: Event Counter 1 Enable Set Position */ +#define PMU_CNTENSET_CNT1_ENABLE_Msk (1UL << PMU_CNTENSET_CNT1_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 1 Enable Set Mask */ + +#define PMU_CNTENSET_CNT2_ENABLE_Pos 2U /*!< PMU CNTENSET: Event Counter 2 Enable Set Position */ +#define PMU_CNTENSET_CNT2_ENABLE_Msk (1UL << PMU_CNTENSET_CNT2_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 2 Enable Set Mask */ + +#define PMU_CNTENSET_CNT3_ENABLE_Pos 3U /*!< PMU CNTENSET: Event Counter 3 Enable Set Position */ +#define PMU_CNTENSET_CNT3_ENABLE_Msk (1UL << PMU_CNTENSET_CNT3_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 3 Enable Set Mask */ + +#define PMU_CNTENSET_CNT4_ENABLE_Pos 4U /*!< PMU CNTENSET: Event Counter 4 Enable Set Position */ +#define PMU_CNTENSET_CNT4_ENABLE_Msk (1UL << PMU_CNTENSET_CNT4_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 4 Enable Set Mask */ + +#define PMU_CNTENSET_CNT5_ENABLE_Pos 5U /*!< PMU CNTENSET: Event Counter 5 Enable Set Position */ +#define PMU_CNTENSET_CNT5_ENABLE_Msk (1UL << PMU_CNTENSET_CNT5_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 5 Enable Set Mask */ + +#define PMU_CNTENSET_CNT6_ENABLE_Pos 6U /*!< PMU CNTENSET: Event Counter 6 Enable Set Position */ +#define PMU_CNTENSET_CNT6_ENABLE_Msk (1UL << PMU_CNTENSET_CNT6_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 6 Enable Set Mask */ + +#define PMU_CNTENSET_CNT7_ENABLE_Pos 7U /*!< PMU CNTENSET: Event Counter 7 Enable Set Position */ +#define PMU_CNTENSET_CNT7_ENABLE_Msk (1UL << PMU_CNTENSET_CNT7_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 7 Enable Set Mask */ + +#define PMU_CNTENSET_CNT8_ENABLE_Pos 8U /*!< PMU CNTENSET: Event Counter 8 Enable Set Position */ +#define PMU_CNTENSET_CNT8_ENABLE_Msk (1UL << PMU_CNTENSET_CNT8_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 8 Enable Set Mask */ + +#define PMU_CNTENSET_CNT9_ENABLE_Pos 9U /*!< PMU CNTENSET: Event Counter 9 Enable Set Position */ +#define PMU_CNTENSET_CNT9_ENABLE_Msk (1UL << PMU_CNTENSET_CNT9_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 9 Enable Set Mask */ + +#define PMU_CNTENSET_CNT10_ENABLE_Pos 10U /*!< PMU CNTENSET: Event Counter 10 Enable Set Position */ +#define PMU_CNTENSET_CNT10_ENABLE_Msk (1UL << PMU_CNTENSET_CNT10_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 10 Enable Set Mask */ + +#define PMU_CNTENSET_CNT11_ENABLE_Pos 11U /*!< PMU CNTENSET: Event Counter 11 Enable Set Position */ +#define PMU_CNTENSET_CNT11_ENABLE_Msk (1UL << PMU_CNTENSET_CNT11_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 11 Enable Set Mask */ + +#define PMU_CNTENSET_CNT12_ENABLE_Pos 12U /*!< PMU CNTENSET: Event Counter 12 Enable Set Position */ +#define PMU_CNTENSET_CNT12_ENABLE_Msk (1UL << PMU_CNTENSET_CNT12_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 12 Enable Set Mask */ + +#define PMU_CNTENSET_CNT13_ENABLE_Pos 13U /*!< PMU CNTENSET: Event Counter 13 Enable Set Position */ +#define PMU_CNTENSET_CNT13_ENABLE_Msk (1UL << PMU_CNTENSET_CNT13_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 13 Enable Set Mask */ + +#define PMU_CNTENSET_CNT14_ENABLE_Pos 14U /*!< PMU CNTENSET: Event Counter 14 Enable Set Position */ +#define PMU_CNTENSET_CNT14_ENABLE_Msk (1UL << PMU_CNTENSET_CNT14_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 14 Enable Set Mask */ + +#define PMU_CNTENSET_CNT15_ENABLE_Pos 15U /*!< PMU CNTENSET: Event Counter 15 Enable Set Position */ +#define PMU_CNTENSET_CNT15_ENABLE_Msk (1UL << PMU_CNTENSET_CNT15_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 15 Enable Set Mask */ + +#define PMU_CNTENSET_CNT16_ENABLE_Pos 16U /*!< PMU CNTENSET: Event Counter 16 Enable Set Position */ +#define PMU_CNTENSET_CNT16_ENABLE_Msk (1UL << PMU_CNTENSET_CNT16_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 16 Enable Set Mask */ + +#define PMU_CNTENSET_CNT17_ENABLE_Pos 17U /*!< PMU CNTENSET: Event Counter 17 Enable Set Position */ +#define PMU_CNTENSET_CNT17_ENABLE_Msk (1UL << PMU_CNTENSET_CNT17_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 17 Enable Set Mask */ + +#define PMU_CNTENSET_CNT18_ENABLE_Pos 18U /*!< PMU CNTENSET: Event Counter 18 Enable Set Position */ +#define PMU_CNTENSET_CNT18_ENABLE_Msk (1UL << PMU_CNTENSET_CNT18_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 18 Enable Set Mask */ + +#define PMU_CNTENSET_CNT19_ENABLE_Pos 19U /*!< PMU CNTENSET: Event Counter 19 Enable Set Position */ +#define PMU_CNTENSET_CNT19_ENABLE_Msk (1UL << PMU_CNTENSET_CNT19_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 19 Enable Set Mask */ + +#define PMU_CNTENSET_CNT20_ENABLE_Pos 20U /*!< PMU CNTENSET: Event Counter 20 Enable Set Position */ +#define PMU_CNTENSET_CNT20_ENABLE_Msk (1UL << PMU_CNTENSET_CNT20_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 20 Enable Set Mask */ + +#define PMU_CNTENSET_CNT21_ENABLE_Pos 21U /*!< PMU CNTENSET: Event Counter 21 Enable Set Position */ +#define PMU_CNTENSET_CNT21_ENABLE_Msk (1UL << PMU_CNTENSET_CNT21_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 21 Enable Set Mask */ + +#define PMU_CNTENSET_CNT22_ENABLE_Pos 22U /*!< PMU CNTENSET: Event Counter 22 Enable Set Position */ +#define PMU_CNTENSET_CNT22_ENABLE_Msk (1UL << PMU_CNTENSET_CNT22_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 22 Enable Set Mask */ + +#define PMU_CNTENSET_CNT23_ENABLE_Pos 23U /*!< PMU CNTENSET: Event Counter 23 Enable Set Position */ +#define PMU_CNTENSET_CNT23_ENABLE_Msk (1UL << PMU_CNTENSET_CNT23_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 23 Enable Set Mask */ + +#define PMU_CNTENSET_CNT24_ENABLE_Pos 24U /*!< PMU CNTENSET: Event Counter 24 Enable Set Position */ +#define PMU_CNTENSET_CNT24_ENABLE_Msk (1UL << PMU_CNTENSET_CNT24_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 24 Enable Set Mask */ + +#define PMU_CNTENSET_CNT25_ENABLE_Pos 25U /*!< PMU CNTENSET: Event Counter 25 Enable Set Position */ +#define PMU_CNTENSET_CNT25_ENABLE_Msk (1UL << PMU_CNTENSET_CNT25_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 25 Enable Set Mask */ + +#define PMU_CNTENSET_CNT26_ENABLE_Pos 26U /*!< PMU CNTENSET: Event Counter 26 Enable Set Position */ +#define PMU_CNTENSET_CNT26_ENABLE_Msk (1UL << PMU_CNTENSET_CNT26_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 26 Enable Set Mask */ + +#define PMU_CNTENSET_CNT27_ENABLE_Pos 27U /*!< PMU CNTENSET: Event Counter 27 Enable Set Position */ +#define PMU_CNTENSET_CNT27_ENABLE_Msk (1UL << PMU_CNTENSET_CNT27_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 27 Enable Set Mask */ + +#define PMU_CNTENSET_CNT28_ENABLE_Pos 28U /*!< PMU CNTENSET: Event Counter 28 Enable Set Position */ +#define PMU_CNTENSET_CNT28_ENABLE_Msk (1UL << PMU_CNTENSET_CNT28_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 28 Enable Set Mask */ + +#define PMU_CNTENSET_CNT29_ENABLE_Pos 29U /*!< PMU CNTENSET: Event Counter 29 Enable Set Position */ +#define PMU_CNTENSET_CNT29_ENABLE_Msk (1UL << PMU_CNTENSET_CNT29_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 29 Enable Set Mask */ + +#define PMU_CNTENSET_CNT30_ENABLE_Pos 30U /*!< PMU CNTENSET: Event Counter 30 Enable Set Position */ +#define PMU_CNTENSET_CNT30_ENABLE_Msk (1UL << PMU_CNTENSET_CNT30_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 30 Enable Set Mask */ + +#define PMU_CNTENSET_CCNTR_ENABLE_Pos 31U /*!< PMU CNTENSET: Cycle Counter Enable Set Position */ +#define PMU_CNTENSET_CCNTR_ENABLE_Msk (1UL << PMU_CNTENSET_CCNTR_ENABLE_Pos) /*!< PMU CNTENSET: Cycle Counter Enable Set Mask */ + +/** \brief PMU Count Enable Clear Register Definitions */ + +#define PMU_CNTENSET_CNT0_ENABLE_Pos 0U /*!< PMU CNTENCLR: Event Counter 0 Enable Clear Position */ +#define PMU_CNTENCLR_CNT0_ENABLE_Msk (1UL /*<< PMU_CNTENCLR_CNT0_ENABLE_Pos*/) /*!< PMU CNTENCLR: Event Counter 0 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT1_ENABLE_Pos 1U /*!< PMU CNTENCLR: Event Counter 1 Enable Clear Position */ +#define PMU_CNTENCLR_CNT1_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT1_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 1 Enable Clear */ + +#define PMU_CNTENCLR_CNT2_ENABLE_Pos 2U /*!< PMU CNTENCLR: Event Counter 2 Enable Clear Position */ +#define PMU_CNTENCLR_CNT2_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT2_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 2 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT3_ENABLE_Pos 3U /*!< PMU CNTENCLR: Event Counter 3 Enable Clear Position */ +#define PMU_CNTENCLR_CNT3_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT3_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 3 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT4_ENABLE_Pos 4U /*!< PMU CNTENCLR: Event Counter 4 Enable Clear Position */ +#define PMU_CNTENCLR_CNT4_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT4_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 4 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT5_ENABLE_Pos 5U /*!< PMU CNTENCLR: Event Counter 5 Enable Clear Position */ +#define PMU_CNTENCLR_CNT5_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT5_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 5 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT6_ENABLE_Pos 6U /*!< PMU CNTENCLR: Event Counter 6 Enable Clear Position */ +#define PMU_CNTENCLR_CNT6_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT6_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 6 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT7_ENABLE_Pos 7U /*!< PMU CNTENCLR: Event Counter 7 Enable Clear Position */ +#define PMU_CNTENCLR_CNT7_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT7_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 7 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT8_ENABLE_Pos 8U /*!< PMU CNTENCLR: Event Counter 8 Enable Clear Position */ +#define PMU_CNTENCLR_CNT8_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT8_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 8 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT9_ENABLE_Pos 9U /*!< PMU CNTENCLR: Event Counter 9 Enable Clear Position */ +#define PMU_CNTENCLR_CNT9_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT9_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 9 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT10_ENABLE_Pos 10U /*!< PMU CNTENCLR: Event Counter 10 Enable Clear Position */ +#define PMU_CNTENCLR_CNT10_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT10_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 10 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT11_ENABLE_Pos 11U /*!< PMU CNTENCLR: Event Counter 11 Enable Clear Position */ +#define PMU_CNTENCLR_CNT11_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT11_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 11 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT12_ENABLE_Pos 12U /*!< PMU CNTENCLR: Event Counter 12 Enable Clear Position */ +#define PMU_CNTENCLR_CNT12_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT12_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 12 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT13_ENABLE_Pos 13U /*!< PMU CNTENCLR: Event Counter 13 Enable Clear Position */ +#define PMU_CNTENCLR_CNT13_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT13_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 13 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT14_ENABLE_Pos 14U /*!< PMU CNTENCLR: Event Counter 14 Enable Clear Position */ +#define PMU_CNTENCLR_CNT14_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT14_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 14 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT15_ENABLE_Pos 15U /*!< PMU CNTENCLR: Event Counter 15 Enable Clear Position */ +#define PMU_CNTENCLR_CNT15_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT15_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 15 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT16_ENABLE_Pos 16U /*!< PMU CNTENCLR: Event Counter 16 Enable Clear Position */ +#define PMU_CNTENCLR_CNT16_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT16_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 16 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT17_ENABLE_Pos 17U /*!< PMU CNTENCLR: Event Counter 17 Enable Clear Position */ +#define PMU_CNTENCLR_CNT17_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT17_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 17 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT18_ENABLE_Pos 18U /*!< PMU CNTENCLR: Event Counter 18 Enable Clear Position */ +#define PMU_CNTENCLR_CNT18_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT18_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 18 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT19_ENABLE_Pos 19U /*!< PMU CNTENCLR: Event Counter 19 Enable Clear Position */ +#define PMU_CNTENCLR_CNT19_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT19_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 19 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT20_ENABLE_Pos 20U /*!< PMU CNTENCLR: Event Counter 20 Enable Clear Position */ +#define PMU_CNTENCLR_CNT20_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT20_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 20 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT21_ENABLE_Pos 21U /*!< PMU CNTENCLR: Event Counter 21 Enable Clear Position */ +#define PMU_CNTENCLR_CNT21_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT21_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 21 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT22_ENABLE_Pos 22U /*!< PMU CNTENCLR: Event Counter 22 Enable Clear Position */ +#define PMU_CNTENCLR_CNT22_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT22_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 22 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT23_ENABLE_Pos 23U /*!< PMU CNTENCLR: Event Counter 23 Enable Clear Position */ +#define PMU_CNTENCLR_CNT23_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT23_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 23 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT24_ENABLE_Pos 24U /*!< PMU CNTENCLR: Event Counter 24 Enable Clear Position */ +#define PMU_CNTENCLR_CNT24_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT24_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 24 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT25_ENABLE_Pos 25U /*!< PMU CNTENCLR: Event Counter 25 Enable Clear Position */ +#define PMU_CNTENCLR_CNT25_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT25_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 25 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT26_ENABLE_Pos 26U /*!< PMU CNTENCLR: Event Counter 26 Enable Clear Position */ +#define PMU_CNTENCLR_CNT26_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT26_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 26 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT27_ENABLE_Pos 27U /*!< PMU CNTENCLR: Event Counter 27 Enable Clear Position */ +#define PMU_CNTENCLR_CNT27_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT27_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 27 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT28_ENABLE_Pos 28U /*!< PMU CNTENCLR: Event Counter 28 Enable Clear Position */ +#define PMU_CNTENCLR_CNT28_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT28_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 28 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT29_ENABLE_Pos 29U /*!< PMU CNTENCLR: Event Counter 29 Enable Clear Position */ +#define PMU_CNTENCLR_CNT29_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT29_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 29 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT30_ENABLE_Pos 30U /*!< PMU CNTENCLR: Event Counter 30 Enable Clear Position */ +#define PMU_CNTENCLR_CNT30_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT30_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 30 Enable Clear Mask */ + +#define PMU_CNTENCLR_CCNTR_ENABLE_Pos 31U /*!< PMU CNTENCLR: Cycle Counter Enable Clear Position */ +#define PMU_CNTENCLR_CCNTR_ENABLE_Msk (1UL << PMU_CNTENCLR_CCNTR_ENABLE_Pos) /*!< PMU CNTENCLR: Cycle Counter Enable Clear Mask */ + +/** \brief PMU Interrupt Enable Set Register Definitions */ + +#define PMU_INTENSET_CNT0_ENABLE_Pos 0U /*!< PMU INTENSET: Event Counter 0 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT0_ENABLE_Msk (1UL /*<< PMU_INTENSET_CNT0_ENABLE_Pos*/) /*!< PMU INTENSET: Event Counter 0 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT1_ENABLE_Pos 1U /*!< PMU INTENSET: Event Counter 1 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT1_ENABLE_Msk (1UL << PMU_INTENSET_CNT1_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 1 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT2_ENABLE_Pos 2U /*!< PMU INTENSET: Event Counter 2 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT2_ENABLE_Msk (1UL << PMU_INTENSET_CNT2_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 2 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT3_ENABLE_Pos 3U /*!< PMU INTENSET: Event Counter 3 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT3_ENABLE_Msk (1UL << PMU_INTENSET_CNT3_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 3 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT4_ENABLE_Pos 4U /*!< PMU INTENSET: Event Counter 4 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT4_ENABLE_Msk (1UL << PMU_INTENSET_CNT4_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 4 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT5_ENABLE_Pos 5U /*!< PMU INTENSET: Event Counter 5 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT5_ENABLE_Msk (1UL << PMU_INTENSET_CNT5_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 5 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT6_ENABLE_Pos 6U /*!< PMU INTENSET: Event Counter 6 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT6_ENABLE_Msk (1UL << PMU_INTENSET_CNT6_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 6 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT7_ENABLE_Pos 7U /*!< PMU INTENSET: Event Counter 7 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT7_ENABLE_Msk (1UL << PMU_INTENSET_CNT7_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 7 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT8_ENABLE_Pos 8U /*!< PMU INTENSET: Event Counter 8 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT8_ENABLE_Msk (1UL << PMU_INTENSET_CNT8_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 8 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT9_ENABLE_Pos 9U /*!< PMU INTENSET: Event Counter 9 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT9_ENABLE_Msk (1UL << PMU_INTENSET_CNT9_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 9 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT10_ENABLE_Pos 10U /*!< PMU INTENSET: Event Counter 10 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT10_ENABLE_Msk (1UL << PMU_INTENSET_CNT10_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 10 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT11_ENABLE_Pos 11U /*!< PMU INTENSET: Event Counter 11 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT11_ENABLE_Msk (1UL << PMU_INTENSET_CNT11_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 11 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT12_ENABLE_Pos 12U /*!< PMU INTENSET: Event Counter 12 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT12_ENABLE_Msk (1UL << PMU_INTENSET_CNT12_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 12 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT13_ENABLE_Pos 13U /*!< PMU INTENSET: Event Counter 13 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT13_ENABLE_Msk (1UL << PMU_INTENSET_CNT13_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 13 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT14_ENABLE_Pos 14U /*!< PMU INTENSET: Event Counter 14 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT14_ENABLE_Msk (1UL << PMU_INTENSET_CNT14_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 14 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT15_ENABLE_Pos 15U /*!< PMU INTENSET: Event Counter 15 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT15_ENABLE_Msk (1UL << PMU_INTENSET_CNT15_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 15 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT16_ENABLE_Pos 16U /*!< PMU INTENSET: Event Counter 16 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT16_ENABLE_Msk (1UL << PMU_INTENSET_CNT16_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 16 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT17_ENABLE_Pos 17U /*!< PMU INTENSET: Event Counter 17 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT17_ENABLE_Msk (1UL << PMU_INTENSET_CNT17_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 17 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT18_ENABLE_Pos 18U /*!< PMU INTENSET: Event Counter 18 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT18_ENABLE_Msk (1UL << PMU_INTENSET_CNT18_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 18 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT19_ENABLE_Pos 19U /*!< PMU INTENSET: Event Counter 19 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT19_ENABLE_Msk (1UL << PMU_INTENSET_CNT19_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 19 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT20_ENABLE_Pos 20U /*!< PMU INTENSET: Event Counter 20 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT20_ENABLE_Msk (1UL << PMU_INTENSET_CNT20_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 20 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT21_ENABLE_Pos 21U /*!< PMU INTENSET: Event Counter 21 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT21_ENABLE_Msk (1UL << PMU_INTENSET_CNT21_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 21 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT22_ENABLE_Pos 22U /*!< PMU INTENSET: Event Counter 22 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT22_ENABLE_Msk (1UL << PMU_INTENSET_CNT22_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 22 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT23_ENABLE_Pos 23U /*!< PMU INTENSET: Event Counter 23 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT23_ENABLE_Msk (1UL << PMU_INTENSET_CNT23_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 23 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT24_ENABLE_Pos 24U /*!< PMU INTENSET: Event Counter 24 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT24_ENABLE_Msk (1UL << PMU_INTENSET_CNT24_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 24 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT25_ENABLE_Pos 25U /*!< PMU INTENSET: Event Counter 25 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT25_ENABLE_Msk (1UL << PMU_INTENSET_CNT25_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 25 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT26_ENABLE_Pos 26U /*!< PMU INTENSET: Event Counter 26 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT26_ENABLE_Msk (1UL << PMU_INTENSET_CNT26_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 26 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT27_ENABLE_Pos 27U /*!< PMU INTENSET: Event Counter 27 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT27_ENABLE_Msk (1UL << PMU_INTENSET_CNT27_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 27 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT28_ENABLE_Pos 28U /*!< PMU INTENSET: Event Counter 28 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT28_ENABLE_Msk (1UL << PMU_INTENSET_CNT28_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 28 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT29_ENABLE_Pos 29U /*!< PMU INTENSET: Event Counter 29 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT29_ENABLE_Msk (1UL << PMU_INTENSET_CNT29_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 29 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT30_ENABLE_Pos 30U /*!< PMU INTENSET: Event Counter 30 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT30_ENABLE_Msk (1UL << PMU_INTENSET_CNT30_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 30 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CYCCNT_ENABLE_Pos 31U /*!< PMU INTENSET: Cycle Counter Interrupt Enable Set Position */ +#define PMU_INTENSET_CCYCNT_ENABLE_Msk (1UL << PMU_INTENSET_CYCCNT_ENABLE_Pos) /*!< PMU INTENSET: Cycle Counter Interrupt Enable Set Mask */ + +/** \brief PMU Interrupt Enable Clear Register Definitions */ + +#define PMU_INTENSET_CNT0_ENABLE_Pos 0U /*!< PMU INTENCLR: Event Counter 0 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT0_ENABLE_Msk (1UL /*<< PMU_INTENCLR_CNT0_ENABLE_Pos*/) /*!< PMU INTENCLR: Event Counter 0 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT1_ENABLE_Pos 1U /*!< PMU INTENCLR: Event Counter 1 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT1_ENABLE_Msk (1UL << PMU_INTENCLR_CNT1_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 1 Interrupt Enable Clear */ + +#define PMU_INTENCLR_CNT2_ENABLE_Pos 2U /*!< PMU INTENCLR: Event Counter 2 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT2_ENABLE_Msk (1UL << PMU_INTENCLR_CNT2_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 2 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT3_ENABLE_Pos 3U /*!< PMU INTENCLR: Event Counter 3 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT3_ENABLE_Msk (1UL << PMU_INTENCLR_CNT3_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 3 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT4_ENABLE_Pos 4U /*!< PMU INTENCLR: Event Counter 4 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT4_ENABLE_Msk (1UL << PMU_INTENCLR_CNT4_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 4 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT5_ENABLE_Pos 5U /*!< PMU INTENCLR: Event Counter 5 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT5_ENABLE_Msk (1UL << PMU_INTENCLR_CNT5_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 5 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT6_ENABLE_Pos 6U /*!< PMU INTENCLR: Event Counter 6 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT6_ENABLE_Msk (1UL << PMU_INTENCLR_CNT6_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 6 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT7_ENABLE_Pos 7U /*!< PMU INTENCLR: Event Counter 7 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT7_ENABLE_Msk (1UL << PMU_INTENCLR_CNT7_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 7 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT8_ENABLE_Pos 8U /*!< PMU INTENCLR: Event Counter 8 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT8_ENABLE_Msk (1UL << PMU_INTENCLR_CNT8_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 8 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT9_ENABLE_Pos 9U /*!< PMU INTENCLR: Event Counter 9 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT9_ENABLE_Msk (1UL << PMU_INTENCLR_CNT9_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 9 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT10_ENABLE_Pos 10U /*!< PMU INTENCLR: Event Counter 10 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT10_ENABLE_Msk (1UL << PMU_INTENCLR_CNT10_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 10 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT11_ENABLE_Pos 11U /*!< PMU INTENCLR: Event Counter 11 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT11_ENABLE_Msk (1UL << PMU_INTENCLR_CNT11_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 11 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT12_ENABLE_Pos 12U /*!< PMU INTENCLR: Event Counter 12 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT12_ENABLE_Msk (1UL << PMU_INTENCLR_CNT12_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 12 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT13_ENABLE_Pos 13U /*!< PMU INTENCLR: Event Counter 13 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT13_ENABLE_Msk (1UL << PMU_INTENCLR_CNT13_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 13 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT14_ENABLE_Pos 14U /*!< PMU INTENCLR: Event Counter 14 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT14_ENABLE_Msk (1UL << PMU_INTENCLR_CNT14_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 14 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT15_ENABLE_Pos 15U /*!< PMU INTENCLR: Event Counter 15 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT15_ENABLE_Msk (1UL << PMU_INTENCLR_CNT15_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 15 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT16_ENABLE_Pos 16U /*!< PMU INTENCLR: Event Counter 16 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT16_ENABLE_Msk (1UL << PMU_INTENCLR_CNT16_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 16 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT17_ENABLE_Pos 17U /*!< PMU INTENCLR: Event Counter 17 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT17_ENABLE_Msk (1UL << PMU_INTENCLR_CNT17_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 17 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT18_ENABLE_Pos 18U /*!< PMU INTENCLR: Event Counter 18 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT18_ENABLE_Msk (1UL << PMU_INTENCLR_CNT18_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 18 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT19_ENABLE_Pos 19U /*!< PMU INTENCLR: Event Counter 19 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT19_ENABLE_Msk (1UL << PMU_INTENCLR_CNT19_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 19 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT20_ENABLE_Pos 20U /*!< PMU INTENCLR: Event Counter 20 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT20_ENABLE_Msk (1UL << PMU_INTENCLR_CNT20_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 20 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT21_ENABLE_Pos 21U /*!< PMU INTENCLR: Event Counter 21 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT21_ENABLE_Msk (1UL << PMU_INTENCLR_CNT21_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 21 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT22_ENABLE_Pos 22U /*!< PMU INTENCLR: Event Counter 22 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT22_ENABLE_Msk (1UL << PMU_INTENCLR_CNT22_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 22 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT23_ENABLE_Pos 23U /*!< PMU INTENCLR: Event Counter 23 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT23_ENABLE_Msk (1UL << PMU_INTENCLR_CNT23_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 23 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT24_ENABLE_Pos 24U /*!< PMU INTENCLR: Event Counter 24 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT24_ENABLE_Msk (1UL << PMU_INTENCLR_CNT24_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 24 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT25_ENABLE_Pos 25U /*!< PMU INTENCLR: Event Counter 25 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT25_ENABLE_Msk (1UL << PMU_INTENCLR_CNT25_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 25 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT26_ENABLE_Pos 26U /*!< PMU INTENCLR: Event Counter 26 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT26_ENABLE_Msk (1UL << PMU_INTENCLR_CNT26_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 26 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT27_ENABLE_Pos 27U /*!< PMU INTENCLR: Event Counter 27 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT27_ENABLE_Msk (1UL << PMU_INTENCLR_CNT27_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 27 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT28_ENABLE_Pos 28U /*!< PMU INTENCLR: Event Counter 28 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT28_ENABLE_Msk (1UL << PMU_INTENCLR_CNT28_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 28 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT29_ENABLE_Pos 29U /*!< PMU INTENCLR: Event Counter 29 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT29_ENABLE_Msk (1UL << PMU_INTENCLR_CNT29_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 29 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT30_ENABLE_Pos 30U /*!< PMU INTENCLR: Event Counter 30 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT30_ENABLE_Msk (1UL << PMU_INTENCLR_CNT30_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 30 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CYCCNT_ENABLE_Pos 31U /*!< PMU INTENCLR: Cycle Counter Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CYCCNT_ENABLE_Msk (1UL << PMU_INTENCLR_CYCCNT_ENABLE_Pos) /*!< PMU INTENCLR: Cycle Counter Interrupt Enable Clear Mask */ + +/** \brief PMU Overflow Flag Status Set Register Definitions */ + +#define PMU_OVSSET_CNT0_STATUS_Pos 0U /*!< PMU OVSSET: Event Counter 0 Overflow Set Position */ +#define PMU_OVSSET_CNT0_STATUS_Msk (1UL /*<< PMU_OVSSET_CNT0_STATUS_Pos*/) /*!< PMU OVSSET: Event Counter 0 Overflow Set Mask */ + +#define PMU_OVSSET_CNT1_STATUS_Pos 1U /*!< PMU OVSSET: Event Counter 1 Overflow Set Position */ +#define PMU_OVSSET_CNT1_STATUS_Msk (1UL << PMU_OVSSET_CNT1_STATUS_Pos) /*!< PMU OVSSET: Event Counter 1 Overflow Set Mask */ + +#define PMU_OVSSET_CNT2_STATUS_Pos 2U /*!< PMU OVSSET: Event Counter 2 Overflow Set Position */ +#define PMU_OVSSET_CNT2_STATUS_Msk (1UL << PMU_OVSSET_CNT2_STATUS_Pos) /*!< PMU OVSSET: Event Counter 2 Overflow Set Mask */ + +#define PMU_OVSSET_CNT3_STATUS_Pos 3U /*!< PMU OVSSET: Event Counter 3 Overflow Set Position */ +#define PMU_OVSSET_CNT3_STATUS_Msk (1UL << PMU_OVSSET_CNT3_STATUS_Pos) /*!< PMU OVSSET: Event Counter 3 Overflow Set Mask */ + +#define PMU_OVSSET_CNT4_STATUS_Pos 4U /*!< PMU OVSSET: Event Counter 4 Overflow Set Position */ +#define PMU_OVSSET_CNT4_STATUS_Msk (1UL << PMU_OVSSET_CNT4_STATUS_Pos) /*!< PMU OVSSET: Event Counter 4 Overflow Set Mask */ + +#define PMU_OVSSET_CNT5_STATUS_Pos 5U /*!< PMU OVSSET: Event Counter 5 Overflow Set Position */ +#define PMU_OVSSET_CNT5_STATUS_Msk (1UL << PMU_OVSSET_CNT5_STATUS_Pos) /*!< PMU OVSSET: Event Counter 5 Overflow Set Mask */ + +#define PMU_OVSSET_CNT6_STATUS_Pos 6U /*!< PMU OVSSET: Event Counter 6 Overflow Set Position */ +#define PMU_OVSSET_CNT6_STATUS_Msk (1UL << PMU_OVSSET_CNT6_STATUS_Pos) /*!< PMU OVSSET: Event Counter 6 Overflow Set Mask */ + +#define PMU_OVSSET_CNT7_STATUS_Pos 7U /*!< PMU OVSSET: Event Counter 7 Overflow Set Position */ +#define PMU_OVSSET_CNT7_STATUS_Msk (1UL << PMU_OVSSET_CNT7_STATUS_Pos) /*!< PMU OVSSET: Event Counter 7 Overflow Set Mask */ + +#define PMU_OVSSET_CNT8_STATUS_Pos 8U /*!< PMU OVSSET: Event Counter 8 Overflow Set Position */ +#define PMU_OVSSET_CNT8_STATUS_Msk (1UL << PMU_OVSSET_CNT8_STATUS_Pos) /*!< PMU OVSSET: Event Counter 8 Overflow Set Mask */ + +#define PMU_OVSSET_CNT9_STATUS_Pos 9U /*!< PMU OVSSET: Event Counter 9 Overflow Set Position */ +#define PMU_OVSSET_CNT9_STATUS_Msk (1UL << PMU_OVSSET_CNT9_STATUS_Pos) /*!< PMU OVSSET: Event Counter 9 Overflow Set Mask */ + +#define PMU_OVSSET_CNT10_STATUS_Pos 10U /*!< PMU OVSSET: Event Counter 10 Overflow Set Position */ +#define PMU_OVSSET_CNT10_STATUS_Msk (1UL << PMU_OVSSET_CNT10_STATUS_Pos) /*!< PMU OVSSET: Event Counter 10 Overflow Set Mask */ + +#define PMU_OVSSET_CNT11_STATUS_Pos 11U /*!< PMU OVSSET: Event Counter 11 Overflow Set Position */ +#define PMU_OVSSET_CNT11_STATUS_Msk (1UL << PMU_OVSSET_CNT11_STATUS_Pos) /*!< PMU OVSSET: Event Counter 11 Overflow Set Mask */ + +#define PMU_OVSSET_CNT12_STATUS_Pos 12U /*!< PMU OVSSET: Event Counter 12 Overflow Set Position */ +#define PMU_OVSSET_CNT12_STATUS_Msk (1UL << PMU_OVSSET_CNT12_STATUS_Pos) /*!< PMU OVSSET: Event Counter 12 Overflow Set Mask */ + +#define PMU_OVSSET_CNT13_STATUS_Pos 13U /*!< PMU OVSSET: Event Counter 13 Overflow Set Position */ +#define PMU_OVSSET_CNT13_STATUS_Msk (1UL << PMU_OVSSET_CNT13_STATUS_Pos) /*!< PMU OVSSET: Event Counter 13 Overflow Set Mask */ + +#define PMU_OVSSET_CNT14_STATUS_Pos 14U /*!< PMU OVSSET: Event Counter 14 Overflow Set Position */ +#define PMU_OVSSET_CNT14_STATUS_Msk (1UL << PMU_OVSSET_CNT14_STATUS_Pos) /*!< PMU OVSSET: Event Counter 14 Overflow Set Mask */ + +#define PMU_OVSSET_CNT15_STATUS_Pos 15U /*!< PMU OVSSET: Event Counter 15 Overflow Set Position */ +#define PMU_OVSSET_CNT15_STATUS_Msk (1UL << PMU_OVSSET_CNT15_STATUS_Pos) /*!< PMU OVSSET: Event Counter 15 Overflow Set Mask */ + +#define PMU_OVSSET_CNT16_STATUS_Pos 16U /*!< PMU OVSSET: Event Counter 16 Overflow Set Position */ +#define PMU_OVSSET_CNT16_STATUS_Msk (1UL << PMU_OVSSET_CNT16_STATUS_Pos) /*!< PMU OVSSET: Event Counter 16 Overflow Set Mask */ + +#define PMU_OVSSET_CNT17_STATUS_Pos 17U /*!< PMU OVSSET: Event Counter 17 Overflow Set Position */ +#define PMU_OVSSET_CNT17_STATUS_Msk (1UL << PMU_OVSSET_CNT17_STATUS_Pos) /*!< PMU OVSSET: Event Counter 17 Overflow Set Mask */ + +#define PMU_OVSSET_CNT18_STATUS_Pos 18U /*!< PMU OVSSET: Event Counter 18 Overflow Set Position */ +#define PMU_OVSSET_CNT18_STATUS_Msk (1UL << PMU_OVSSET_CNT18_STATUS_Pos) /*!< PMU OVSSET: Event Counter 18 Overflow Set Mask */ + +#define PMU_OVSSET_CNT19_STATUS_Pos 19U /*!< PMU OVSSET: Event Counter 19 Overflow Set Position */ +#define PMU_OVSSET_CNT19_STATUS_Msk (1UL << PMU_OVSSET_CNT19_STATUS_Pos) /*!< PMU OVSSET: Event Counter 19 Overflow Set Mask */ + +#define PMU_OVSSET_CNT20_STATUS_Pos 20U /*!< PMU OVSSET: Event Counter 20 Overflow Set Position */ +#define PMU_OVSSET_CNT20_STATUS_Msk (1UL << PMU_OVSSET_CNT20_STATUS_Pos) /*!< PMU OVSSET: Event Counter 20 Overflow Set Mask */ + +#define PMU_OVSSET_CNT21_STATUS_Pos 21U /*!< PMU OVSSET: Event Counter 21 Overflow Set Position */ +#define PMU_OVSSET_CNT21_STATUS_Msk (1UL << PMU_OVSSET_CNT21_STATUS_Pos) /*!< PMU OVSSET: Event Counter 21 Overflow Set Mask */ + +#define PMU_OVSSET_CNT22_STATUS_Pos 22U /*!< PMU OVSSET: Event Counter 22 Overflow Set Position */ +#define PMU_OVSSET_CNT22_STATUS_Msk (1UL << PMU_OVSSET_CNT22_STATUS_Pos) /*!< PMU OVSSET: Event Counter 22 Overflow Set Mask */ + +#define PMU_OVSSET_CNT23_STATUS_Pos 23U /*!< PMU OVSSET: Event Counter 23 Overflow Set Position */ +#define PMU_OVSSET_CNT23_STATUS_Msk (1UL << PMU_OVSSET_CNT23_STATUS_Pos) /*!< PMU OVSSET: Event Counter 23 Overflow Set Mask */ + +#define PMU_OVSSET_CNT24_STATUS_Pos 24U /*!< PMU OVSSET: Event Counter 24 Overflow Set Position */ +#define PMU_OVSSET_CNT24_STATUS_Msk (1UL << PMU_OVSSET_CNT24_STATUS_Pos) /*!< PMU OVSSET: Event Counter 24 Overflow Set Mask */ + +#define PMU_OVSSET_CNT25_STATUS_Pos 25U /*!< PMU OVSSET: Event Counter 25 Overflow Set Position */ +#define PMU_OVSSET_CNT25_STATUS_Msk (1UL << PMU_OVSSET_CNT25_STATUS_Pos) /*!< PMU OVSSET: Event Counter 25 Overflow Set Mask */ + +#define PMU_OVSSET_CNT26_STATUS_Pos 26U /*!< PMU OVSSET: Event Counter 26 Overflow Set Position */ +#define PMU_OVSSET_CNT26_STATUS_Msk (1UL << PMU_OVSSET_CNT26_STATUS_Pos) /*!< PMU OVSSET: Event Counter 26 Overflow Set Mask */ + +#define PMU_OVSSET_CNT27_STATUS_Pos 27U /*!< PMU OVSSET: Event Counter 27 Overflow Set Position */ +#define PMU_OVSSET_CNT27_STATUS_Msk (1UL << PMU_OVSSET_CNT27_STATUS_Pos) /*!< PMU OVSSET: Event Counter 27 Overflow Set Mask */ + +#define PMU_OVSSET_CNT28_STATUS_Pos 28U /*!< PMU OVSSET: Event Counter 28 Overflow Set Position */ +#define PMU_OVSSET_CNT28_STATUS_Msk (1UL << PMU_OVSSET_CNT28_STATUS_Pos) /*!< PMU OVSSET: Event Counter 28 Overflow Set Mask */ + +#define PMU_OVSSET_CNT29_STATUS_Pos 29U /*!< PMU OVSSET: Event Counter 29 Overflow Set Position */ +#define PMU_OVSSET_CNT29_STATUS_Msk (1UL << PMU_OVSSET_CNT29_STATUS_Pos) /*!< PMU OVSSET: Event Counter 29 Overflow Set Mask */ + +#define PMU_OVSSET_CNT30_STATUS_Pos 30U /*!< PMU OVSSET: Event Counter 30 Overflow Set Position */ +#define PMU_OVSSET_CNT30_STATUS_Msk (1UL << PMU_OVSSET_CNT30_STATUS_Pos) /*!< PMU OVSSET: Event Counter 30 Overflow Set Mask */ + +#define PMU_OVSSET_CYCCNT_STATUS_Pos 31U /*!< PMU OVSSET: Cycle Counter Overflow Set Position */ +#define PMU_OVSSET_CYCCNT_STATUS_Msk (1UL << PMU_OVSSET_CYCCNT_STATUS_Pos) /*!< PMU OVSSET: Cycle Counter Overflow Set Mask */ + +/** \brief PMU Overflow Flag Status Clear Register Definitions */ + +#define PMU_OVSCLR_CNT0_STATUS_Pos 0U /*!< PMU OVSCLR: Event Counter 0 Overflow Clear Position */ +#define PMU_OVSCLR_CNT0_STATUS_Msk (1UL /*<< PMU_OVSCLR_CNT0_STATUS_Pos*/) /*!< PMU OVSCLR: Event Counter 0 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT1_STATUS_Pos 1U /*!< PMU OVSCLR: Event Counter 1 Overflow Clear Position */ +#define PMU_OVSCLR_CNT1_STATUS_Msk (1UL << PMU_OVSCLR_CNT1_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 1 Overflow Clear */ + +#define PMU_OVSCLR_CNT2_STATUS_Pos 2U /*!< PMU OVSCLR: Event Counter 2 Overflow Clear Position */ +#define PMU_OVSCLR_CNT2_STATUS_Msk (1UL << PMU_OVSCLR_CNT2_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 2 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT3_STATUS_Pos 3U /*!< PMU OVSCLR: Event Counter 3 Overflow Clear Position */ +#define PMU_OVSCLR_CNT3_STATUS_Msk (1UL << PMU_OVSCLR_CNT3_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 3 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT4_STATUS_Pos 4U /*!< PMU OVSCLR: Event Counter 4 Overflow Clear Position */ +#define PMU_OVSCLR_CNT4_STATUS_Msk (1UL << PMU_OVSCLR_CNT4_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 4 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT5_STATUS_Pos 5U /*!< PMU OVSCLR: Event Counter 5 Overflow Clear Position */ +#define PMU_OVSCLR_CNT5_STATUS_Msk (1UL << PMU_OVSCLR_CNT5_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 5 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT6_STATUS_Pos 6U /*!< PMU OVSCLR: Event Counter 6 Overflow Clear Position */ +#define PMU_OVSCLR_CNT6_STATUS_Msk (1UL << PMU_OVSCLR_CNT6_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 6 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT7_STATUS_Pos 7U /*!< PMU OVSCLR: Event Counter 7 Overflow Clear Position */ +#define PMU_OVSCLR_CNT7_STATUS_Msk (1UL << PMU_OVSCLR_CNT7_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 7 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT8_STATUS_Pos 8U /*!< PMU OVSCLR: Event Counter 8 Overflow Clear Position */ +#define PMU_OVSCLR_CNT8_STATUS_Msk (1UL << PMU_OVSCLR_CNT8_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 8 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT9_STATUS_Pos 9U /*!< PMU OVSCLR: Event Counter 9 Overflow Clear Position */ +#define PMU_OVSCLR_CNT9_STATUS_Msk (1UL << PMU_OVSCLR_CNT9_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 9 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT10_STATUS_Pos 10U /*!< PMU OVSCLR: Event Counter 10 Overflow Clear Position */ +#define PMU_OVSCLR_CNT10_STATUS_Msk (1UL << PMU_OVSCLR_CNT10_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 10 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT11_STATUS_Pos 11U /*!< PMU OVSCLR: Event Counter 11 Overflow Clear Position */ +#define PMU_OVSCLR_CNT11_STATUS_Msk (1UL << PMU_OVSCLR_CNT11_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 11 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT12_STATUS_Pos 12U /*!< PMU OVSCLR: Event Counter 12 Overflow Clear Position */ +#define PMU_OVSCLR_CNT12_STATUS_Msk (1UL << PMU_OVSCLR_CNT12_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 12 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT13_STATUS_Pos 13U /*!< PMU OVSCLR: Event Counter 13 Overflow Clear Position */ +#define PMU_OVSCLR_CNT13_STATUS_Msk (1UL << PMU_OVSCLR_CNT13_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 13 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT14_STATUS_Pos 14U /*!< PMU OVSCLR: Event Counter 14 Overflow Clear Position */ +#define PMU_OVSCLR_CNT14_STATUS_Msk (1UL << PMU_OVSCLR_CNT14_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 14 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT15_STATUS_Pos 15U /*!< PMU OVSCLR: Event Counter 15 Overflow Clear Position */ +#define PMU_OVSCLR_CNT15_STATUS_Msk (1UL << PMU_OVSCLR_CNT15_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 15 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT16_STATUS_Pos 16U /*!< PMU OVSCLR: Event Counter 16 Overflow Clear Position */ +#define PMU_OVSCLR_CNT16_STATUS_Msk (1UL << PMU_OVSCLR_CNT16_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 16 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT17_STATUS_Pos 17U /*!< PMU OVSCLR: Event Counter 17 Overflow Clear Position */ +#define PMU_OVSCLR_CNT17_STATUS_Msk (1UL << PMU_OVSCLR_CNT17_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 17 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT18_STATUS_Pos 18U /*!< PMU OVSCLR: Event Counter 18 Overflow Clear Position */ +#define PMU_OVSCLR_CNT18_STATUS_Msk (1UL << PMU_OVSCLR_CNT18_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 18 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT19_STATUS_Pos 19U /*!< PMU OVSCLR: Event Counter 19 Overflow Clear Position */ +#define PMU_OVSCLR_CNT19_STATUS_Msk (1UL << PMU_OVSCLR_CNT19_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 19 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT20_STATUS_Pos 20U /*!< PMU OVSCLR: Event Counter 20 Overflow Clear Position */ +#define PMU_OVSCLR_CNT20_STATUS_Msk (1UL << PMU_OVSCLR_CNT20_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 20 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT21_STATUS_Pos 21U /*!< PMU OVSCLR: Event Counter 21 Overflow Clear Position */ +#define PMU_OVSCLR_CNT21_STATUS_Msk (1UL << PMU_OVSCLR_CNT21_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 21 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT22_STATUS_Pos 22U /*!< PMU OVSCLR: Event Counter 22 Overflow Clear Position */ +#define PMU_OVSCLR_CNT22_STATUS_Msk (1UL << PMU_OVSCLR_CNT22_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 22 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT23_STATUS_Pos 23U /*!< PMU OVSCLR: Event Counter 23 Overflow Clear Position */ +#define PMU_OVSCLR_CNT23_STATUS_Msk (1UL << PMU_OVSCLR_CNT23_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 23 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT24_STATUS_Pos 24U /*!< PMU OVSCLR: Event Counter 24 Overflow Clear Position */ +#define PMU_OVSCLR_CNT24_STATUS_Msk (1UL << PMU_OVSCLR_CNT24_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 24 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT25_STATUS_Pos 25U /*!< PMU OVSCLR: Event Counter 25 Overflow Clear Position */ +#define PMU_OVSCLR_CNT25_STATUS_Msk (1UL << PMU_OVSCLR_CNT25_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 25 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT26_STATUS_Pos 26U /*!< PMU OVSCLR: Event Counter 26 Overflow Clear Position */ +#define PMU_OVSCLR_CNT26_STATUS_Msk (1UL << PMU_OVSCLR_CNT26_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 26 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT27_STATUS_Pos 27U /*!< PMU OVSCLR: Event Counter 27 Overflow Clear Position */ +#define PMU_OVSCLR_CNT27_STATUS_Msk (1UL << PMU_OVSCLR_CNT27_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 27 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT28_STATUS_Pos 28U /*!< PMU OVSCLR: Event Counter 28 Overflow Clear Position */ +#define PMU_OVSCLR_CNT28_STATUS_Msk (1UL << PMU_OVSCLR_CNT28_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 28 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT29_STATUS_Pos 29U /*!< PMU OVSCLR: Event Counter 29 Overflow Clear Position */ +#define PMU_OVSCLR_CNT29_STATUS_Msk (1UL << PMU_OVSCLR_CNT29_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 29 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT30_STATUS_Pos 30U /*!< PMU OVSCLR: Event Counter 30 Overflow Clear Position */ +#define PMU_OVSCLR_CNT30_STATUS_Msk (1UL << PMU_OVSCLR_CNT30_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 30 Overflow Clear Mask */ + +#define PMU_OVSCLR_CYCCNT_STATUS_Pos 31U /*!< PMU OVSCLR: Cycle Counter Overflow Clear Position */ +#define PMU_OVSCLR_CYCCNT_STATUS_Msk (1UL << PMU_OVSCLR_CYCCNT_STATUS_Pos) /*!< PMU OVSCLR: Cycle Counter Overflow Clear Mask */ + +/** \brief PMU Software Increment Counter */ + +#define PMU_SWINC_CNT0_Pos 0U /*!< PMU SWINC: Event Counter 0 Software Increment Position */ +#define PMU_SWINC_CNT0_Msk (1UL /*<< PMU_SWINC_CNT0_Pos */) /*!< PMU SWINC: Event Counter 0 Software Increment Mask */ + +#define PMU_SWINC_CNT1_Pos 1U /*!< PMU SWINC: Event Counter 1 Software Increment Position */ +#define PMU_SWINC_CNT1_Msk (1UL << PMU_SWINC_CNT1_Pos) /*!< PMU SWINC: Event Counter 1 Software Increment Mask */ + +#define PMU_SWINC_CNT2_Pos 2U /*!< PMU SWINC: Event Counter 2 Software Increment Position */ +#define PMU_SWINC_CNT2_Msk (1UL << PMU_SWINC_CNT2_Pos) /*!< PMU SWINC: Event Counter 2 Software Increment Mask */ + +#define PMU_SWINC_CNT3_Pos 3U /*!< PMU SWINC: Event Counter 3 Software Increment Position */ +#define PMU_SWINC_CNT3_Msk (1UL << PMU_SWINC_CNT3_Pos) /*!< PMU SWINC: Event Counter 3 Software Increment Mask */ + +#define PMU_SWINC_CNT4_Pos 4U /*!< PMU SWINC: Event Counter 4 Software Increment Position */ +#define PMU_SWINC_CNT4_Msk (1UL << PMU_SWINC_CNT4_Pos) /*!< PMU SWINC: Event Counter 4 Software Increment Mask */ + +#define PMU_SWINC_CNT5_Pos 5U /*!< PMU SWINC: Event Counter 5 Software Increment Position */ +#define PMU_SWINC_CNT5_Msk (1UL << PMU_SWINC_CNT5_Pos) /*!< PMU SWINC: Event Counter 5 Software Increment Mask */ + +#define PMU_SWINC_CNT6_Pos 6U /*!< PMU SWINC: Event Counter 6 Software Increment Position */ +#define PMU_SWINC_CNT6_Msk (1UL << PMU_SWINC_CNT6_Pos) /*!< PMU SWINC: Event Counter 6 Software Increment Mask */ + +#define PMU_SWINC_CNT7_Pos 7U /*!< PMU SWINC: Event Counter 7 Software Increment Position */ +#define PMU_SWINC_CNT7_Msk (1UL << PMU_SWINC_CNT7_Pos) /*!< PMU SWINC: Event Counter 7 Software Increment Mask */ + +#define PMU_SWINC_CNT8_Pos 8U /*!< PMU SWINC: Event Counter 8 Software Increment Position */ +#define PMU_SWINC_CNT8_Msk (1UL << PMU_SWINC_CNT8_Pos) /*!< PMU SWINC: Event Counter 8 Software Increment Mask */ + +#define PMU_SWINC_CNT9_Pos 9U /*!< PMU SWINC: Event Counter 9 Software Increment Position */ +#define PMU_SWINC_CNT9_Msk (1UL << PMU_SWINC_CNT9_Pos) /*!< PMU SWINC: Event Counter 9 Software Increment Mask */ + +#define PMU_SWINC_CNT10_Pos 10U /*!< PMU SWINC: Event Counter 10 Software Increment Position */ +#define PMU_SWINC_CNT10_Msk (1UL << PMU_SWINC_CNT10_Pos) /*!< PMU SWINC: Event Counter 10 Software Increment Mask */ + +#define PMU_SWINC_CNT11_Pos 11U /*!< PMU SWINC: Event Counter 11 Software Increment Position */ +#define PMU_SWINC_CNT11_Msk (1UL << PMU_SWINC_CNT11_Pos) /*!< PMU SWINC: Event Counter 11 Software Increment Mask */ + +#define PMU_SWINC_CNT12_Pos 12U /*!< PMU SWINC: Event Counter 12 Software Increment Position */ +#define PMU_SWINC_CNT12_Msk (1UL << PMU_SWINC_CNT12_Pos) /*!< PMU SWINC: Event Counter 12 Software Increment Mask */ + +#define PMU_SWINC_CNT13_Pos 13U /*!< PMU SWINC: Event Counter 13 Software Increment Position */ +#define PMU_SWINC_CNT13_Msk (1UL << PMU_SWINC_CNT13_Pos) /*!< PMU SWINC: Event Counter 13 Software Increment Mask */ + +#define PMU_SWINC_CNT14_Pos 14U /*!< PMU SWINC: Event Counter 14 Software Increment Position */ +#define PMU_SWINC_CNT14_Msk (1UL << PMU_SWINC_CNT14_Pos) /*!< PMU SWINC: Event Counter 14 Software Increment Mask */ + +#define PMU_SWINC_CNT15_Pos 15U /*!< PMU SWINC: Event Counter 15 Software Increment Position */ +#define PMU_SWINC_CNT15_Msk (1UL << PMU_SWINC_CNT15_Pos) /*!< PMU SWINC: Event Counter 15 Software Increment Mask */ + +#define PMU_SWINC_CNT16_Pos 16U /*!< PMU SWINC: Event Counter 16 Software Increment Position */ +#define PMU_SWINC_CNT16_Msk (1UL << PMU_SWINC_CNT16_Pos) /*!< PMU SWINC: Event Counter 16 Software Increment Mask */ + +#define PMU_SWINC_CNT17_Pos 17U /*!< PMU SWINC: Event Counter 17 Software Increment Position */ +#define PMU_SWINC_CNT17_Msk (1UL << PMU_SWINC_CNT17_Pos) /*!< PMU SWINC: Event Counter 17 Software Increment Mask */ + +#define PMU_SWINC_CNT18_Pos 18U /*!< PMU SWINC: Event Counter 18 Software Increment Position */ +#define PMU_SWINC_CNT18_Msk (1UL << PMU_SWINC_CNT18_Pos) /*!< PMU SWINC: Event Counter 18 Software Increment Mask */ + +#define PMU_SWINC_CNT19_Pos 19U /*!< PMU SWINC: Event Counter 19 Software Increment Position */ +#define PMU_SWINC_CNT19_Msk (1UL << PMU_SWINC_CNT19_Pos) /*!< PMU SWINC: Event Counter 19 Software Increment Mask */ + +#define PMU_SWINC_CNT20_Pos 20U /*!< PMU SWINC: Event Counter 20 Software Increment Position */ +#define PMU_SWINC_CNT20_Msk (1UL << PMU_SWINC_CNT20_Pos) /*!< PMU SWINC: Event Counter 20 Software Increment Mask */ + +#define PMU_SWINC_CNT21_Pos 21U /*!< PMU SWINC: Event Counter 21 Software Increment Position */ +#define PMU_SWINC_CNT21_Msk (1UL << PMU_SWINC_CNT21_Pos) /*!< PMU SWINC: Event Counter 21 Software Increment Mask */ + +#define PMU_SWINC_CNT22_Pos 22U /*!< PMU SWINC: Event Counter 22 Software Increment Position */ +#define PMU_SWINC_CNT22_Msk (1UL << PMU_SWINC_CNT22_Pos) /*!< PMU SWINC: Event Counter 22 Software Increment Mask */ + +#define PMU_SWINC_CNT23_Pos 23U /*!< PMU SWINC: Event Counter 23 Software Increment Position */ +#define PMU_SWINC_CNT23_Msk (1UL << PMU_SWINC_CNT23_Pos) /*!< PMU SWINC: Event Counter 23 Software Increment Mask */ + +#define PMU_SWINC_CNT24_Pos 24U /*!< PMU SWINC: Event Counter 24 Software Increment Position */ +#define PMU_SWINC_CNT24_Msk (1UL << PMU_SWINC_CNT24_Pos) /*!< PMU SWINC: Event Counter 24 Software Increment Mask */ + +#define PMU_SWINC_CNT25_Pos 25U /*!< PMU SWINC: Event Counter 25 Software Increment Position */ +#define PMU_SWINC_CNT25_Msk (1UL << PMU_SWINC_CNT25_Pos) /*!< PMU SWINC: Event Counter 25 Software Increment Mask */ + +#define PMU_SWINC_CNT26_Pos 26U /*!< PMU SWINC: Event Counter 26 Software Increment Position */ +#define PMU_SWINC_CNT26_Msk (1UL << PMU_SWINC_CNT26_Pos) /*!< PMU SWINC: Event Counter 26 Software Increment Mask */ + +#define PMU_SWINC_CNT27_Pos 27U /*!< PMU SWINC: Event Counter 27 Software Increment Position */ +#define PMU_SWINC_CNT27_Msk (1UL << PMU_SWINC_CNT27_Pos) /*!< PMU SWINC: Event Counter 27 Software Increment Mask */ + +#define PMU_SWINC_CNT28_Pos 28U /*!< PMU SWINC: Event Counter 28 Software Increment Position */ +#define PMU_SWINC_CNT28_Msk (1UL << PMU_SWINC_CNT28_Pos) /*!< PMU SWINC: Event Counter 28 Software Increment Mask */ + +#define PMU_SWINC_CNT29_Pos 29U /*!< PMU SWINC: Event Counter 29 Software Increment Position */ +#define PMU_SWINC_CNT29_Msk (1UL << PMU_SWINC_CNT29_Pos) /*!< PMU SWINC: Event Counter 29 Software Increment Mask */ + +#define PMU_SWINC_CNT30_Pos 30U /*!< PMU SWINC: Event Counter 30 Software Increment Position */ +#define PMU_SWINC_CNT30_Msk (1UL << PMU_SWINC_CNT30_Pos) /*!< PMU SWINC: Event Counter 30 Software Increment Mask */ + +/** \brief PMU Control Register Definitions */ + +#define PMU_CTRL_ENABLE_Pos 0U /*!< PMU CTRL: ENABLE Position */ +#define PMU_CTRL_ENABLE_Msk (1UL /*<< PMU_CTRL_ENABLE_Pos*/) /*!< PMU CTRL: ENABLE Mask */ + +#define PMU_CTRL_EVENTCNT_RESET_Pos 1U /*!< PMU CTRL: Event Counter Reset Position */ +#define PMU_CTRL_EVENTCNT_RESET_Msk (1UL << PMU_CTRL_EVENTCNT_RESET_Pos) /*!< PMU CTRL: Event Counter Reset Mask */ + +#define PMU_CTRL_CYCCNT_RESET_Pos 2U /*!< PMU CTRL: Cycle Counter Reset Position */ +#define PMU_CTRL_CYCCNT_RESET_Msk (1UL << PMU_CTRL_CYCCNT_RESET_Pos) /*!< PMU CTRL: Cycle Counter Reset Mask */ + +#define PMU_CTRL_CYCCNT_DISABLE_Pos 5U /*!< PMU CTRL: Disable Cycle Counter Position */ +#define PMU_CTRL_CYCCNT_DISABLE_Msk (1UL << PMU_CTRL_CYCCNT_DISABLE_Pos) /*!< PMU CTRL: Disable Cycle Counter Mask */ + +#define PMU_CTRL_FRZ_ON_OV_Pos 9U /*!< PMU CTRL: Freeze-on-overflow Position */ +#define PMU_CTRL_FRZ_ON_OV_Msk (1UL << PMU_CTRL_FRZ_ON_OVERFLOW_Pos) /*!< PMU CTRL: Freeze-on-overflow Mask */ + +#define PMU_CTRL_TRACE_ON_OV_Pos 11U /*!< PMU CTRL: Trace-on-overflow Position */ +#define PMU_CTRL_TRACE_ON_OV_Msk (1UL << PMU_CTRL_TRACE_ON_OVERFLOW_Pos) /*!< PMU CTRL: Trace-on-overflow Mask */ + +/** \brief PMU Type Register Definitions */ + +#define PMU_TYPE_NUM_CNTS_Pos 0U /*!< PMU TYPE: Number of Counters Position */ +#define PMU_TYPE_NUM_CNTS_Msk (0xFFUL /*<< PMU_TYPE_NUM_CNTS_Pos*/) /*!< PMU TYPE: Number of Counters Mask */ + +#define PMU_TYPE_SIZE_CNTS_Pos 8U /*!< PMU TYPE: Size of Counters Position */ +#define PMU_TYPE_SIZE_CNTS_Msk (0x3FUL << PMU_TYPE_SIZE_CNTS_Pos) /*!< PMU TYPE: Size of Counters Mask */ + +#define PMU_TYPE_CYCCNT_PRESENT_Pos 14U /*!< PMU TYPE: Cycle Counter Present Position */ +#define PMU_TYPE_CYCCNT_PRESENT_Msk (1UL << PMU_TYPE_CYCCNT_PRESENT_Pos) /*!< PMU TYPE: Cycle Counter Present Mask */ + +#define PMU_TYPE_FRZ_OV_SUPPORT_Pos 21U /*!< PMU TYPE: Freeze-on-overflow Support Position */ +#define PMU_TYPE_FRZ_OV_SUPPORT_Msk (1UL << PMU_TYPE_FRZ_OV_SUPPORT_Pos) /*!< PMU TYPE: Freeze-on-overflow Support Mask */ + +#define PMU_TYPE_TRACE_ON_OV_SUPPORT_Pos 23U /*!< PMU TYPE: Trace-on-overflow Support Position */ +#define PMU_TYPE_TRACE_ON_OV_SUPPORT_Msk (1UL << PMU_TYPE_FRZ_OV_SUPPORT_Pos) /*!< PMU TYPE: Trace-on-overflow Support Mask */ + +/** \brief PMU Authentication Status Register Definitions */ + +#define PMU_AUTHSTATUS_NSID_Pos 0U /*!< PMU AUTHSTATUS: Non-secure Invasive Debug Position */ +#define PMU_AUTHSTATUS_NSID_Msk (0x3UL /*<< PMU_AUTHSTATUS_NSID_Pos*/) /*!< PMU AUTHSTATUS: Non-secure Invasive Debug Mask */ + +#define PMU_AUTHSTATUS_NSNID_Pos 2U /*!< PMU AUTHSTATUS: Non-secure Non-invasive Debug Position */ +#define PMU_AUTHSTATUS_NSNID_Msk (0x3UL << PMU_AUTHSTATUS_NSNID_Pos) /*!< PMU AUTHSTATUS: Non-secure Non-invasive Debug Mask */ + +#define PMU_AUTHSTATUS_SID_Pos 4U /*!< PMU AUTHSTATUS: Secure Invasive Debug Position */ +#define PMU_AUTHSTATUS_SID_Msk (0x3UL << PMU_AUTHSTATUS_SID_Pos) /*!< PMU AUTHSTATUS: Secure Invasive Debug Mask */ + +#define PMU_AUTHSTATUS_SNID_Pos 6U /*!< PMU AUTHSTATUS: Secure Non-invasive Debug Position */ +#define PMU_AUTHSTATUS_SNID_Msk (0x3UL << PMU_AUTHSTATUS_SNID_Pos) /*!< PMU AUTHSTATUS: Secure Non-invasive Debug Mask */ + +#define PMU_AUTHSTATUS_NSUID_Pos 16U /*!< PMU AUTHSTATUS: Non-secure Unprivileged Invasive Debug Position */ +#define PMU_AUTHSTATUS_NSUID_Msk (0x3UL << PMU_AUTHSTATUS_NSUID_Pos) /*!< PMU AUTHSTATUS: Non-secure Unprivileged Invasive Debug Mask */ + +#define PMU_AUTHSTATUS_NSUNID_Pos 18U /*!< PMU AUTHSTATUS: Non-secure Unprivileged Non-invasive Debug Position */ +#define PMU_AUTHSTATUS_NSUNID_Msk (0x3UL << PMU_AUTHSTATUS_NSUNID_Pos) /*!< PMU AUTHSTATUS: Non-secure Unprivileged Non-invasive Debug Mask */ + +#define PMU_AUTHSTATUS_SUID_Pos 20U /*!< PMU AUTHSTATUS: Secure Unprivileged Invasive Debug Position */ +#define PMU_AUTHSTATUS_SUID_Msk (0x3UL << PMU_AUTHSTATUS_SUID_Pos) /*!< PMU AUTHSTATUS: Secure Unprivileged Invasive Debug Mask */ + +#define PMU_AUTHSTATUS_SUNID_Pos 22U /*!< PMU AUTHSTATUS: Secure Unprivileged Non-invasive Debug Position */ +#define PMU_AUTHSTATUS_SUNID_Msk (0x3UL << PMU_AUTHSTATUS_SUNID_Pos) /*!< PMU AUTHSTATUS: Secure Unprivileged Non-invasive Debug Mask */ + + +/*@} end of group CMSIS_PMU */ +#endif + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */ + __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */ + __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */ + __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */ + uint32_t RESERVED0[1]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ +#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/* MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_PXN_Pos 4U /*!< MPU RLAR: PXN Position */ +#define MPU_RLAR_PXN_Msk (1UL << MPU_RLAR_PXN_Pos) /*!< MPU RLAR: PXN Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */ + +/* MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/* MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#else + uint32_t RESERVED0[3]; +#endif + __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */ +} SAU_Type; + +/* SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/* SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/* SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/* SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/* SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/* Secure Fault Status Register Definitions */ +#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */ +#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */ + +#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */ +#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */ + +#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */ +#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */ + +#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */ +#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */ + +#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */ +#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */ + +#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */ +#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */ + +#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */ +#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */ + +#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */ +#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and VFP Feature Register 2 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */ +#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */ + +#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */ +#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */ + +#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */ +#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */ + +#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */ +#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */ + +#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */ +#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */ + +#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */ +#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */ +#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */ +#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +#define FPU_FPDSCR_FZ16_Pos 19U /*!< FPDSCR: FZ16 bit Position */ +#define FPU_FPDSCR_FZ16_Msk (1UL << FPU_FPDSCR_FZ16_Pos) /*!< FPDSCR: FZ16 bit Mask */ + +#define FPU_FPDSCR_LTPSIZE_Pos 16U /*!< FPDSCR: LTPSIZE bit Position */ +#define FPU_FPDSCR_LTPSIZE_Msk (7UL << FPU_FPDSCR_LTPSIZE_Pos) /*!< FPDSCR: LTPSIZE bit Mask */ + +/* Media and VFP Feature Register 0 Definitions */ +#define FPU_MVFR0_FPRound_Pos 28U /*!< MVFR0: FPRound bits Position */ +#define FPU_MVFR0_FPRound_Msk (0xFUL << FPU_MVFR0_FPRound_Pos) /*!< MVFR0: FPRound bits Mask */ + +#define FPU_MVFR0_FPSqrt_Pos 20U /*!< MVFR0: FPSqrt bits Position */ +#define FPU_MVFR0_FPSqrt_Msk (0xFUL << FPU_MVFR0_FPSqrt_Pos) /*!< MVFR0: FPSqrt bits Mask */ + +#define FPU_MVFR0_FPDivide_Pos 16U /*!< MVFR0: FPDivide bits Position */ +#define FPU_MVFR0_FPDivide_Msk (0xFUL << FPU_MVFR0_FPDivide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FPDP_Pos 8U /*!< MVFR0: FPDP bits Position */ +#define FPU_MVFR0_FPDP_Msk (0xFUL << FPU_MVFR0_FPDP_Pos) /*!< MVFR0: FPDP bits Mask */ + +#define FPU_MVFR0_FPSP_Pos 4U /*!< MVFR0: FPSP bits Position */ +#define FPU_MVFR0_FPSP_Msk (0xFUL << FPU_MVFR0_FPSP_Pos) /*!< MVFR0: FPSP bits Mask */ + +#define FPU_MVFR0_SIMDReg_Pos 0U /*!< MVFR0: SIMDReg bits Position */ +#define FPU_MVFR0_SIMDReg_Msk (0xFUL /*<< FPU_MVFR0_SIMDReg_Pos*/) /*!< MVFR0: SIMDReg bits Mask */ + +/* Media and VFP Feature Register 1 Definitions */ +#define FPU_MVFR1_FMAC_Pos 28U /*!< MVFR1: FMAC bits Position */ +#define FPU_MVFR1_FMAC_Msk (0xFUL << FPU_MVFR1_FMAC_Pos) /*!< MVFR1: FMAC bits Mask */ + +#define FPU_MVFR1_FPHP_Pos 24U /*!< MVFR1: FPHP bits Position */ +#define FPU_MVFR1_FPHP_Msk (0xFUL << FPU_MVFR1_FPHP_Pos) /*!< MVFR1: FPHP bits Mask */ + +#define FPU_MVFR1_FP16_Pos 20U /*!< MVFR1: FP16 bits Position */ +#define FPU_MVFR1_FP16_Msk (0xFUL << FPU_MVFR1_FP16_Pos) /*!< MVFR1: FP16 bits Mask */ + +#define FPU_MVFR1_MVE_Pos 8U /*!< MVFR1: MVE bits Position */ +#define FPU_MVFR1_MVE_Msk (0xFUL << FPU_MVFR1_MVE_Pos) /*!< MVFR1: MVE bits Mask */ + +#define FPU_MVFR1_FPDNaN_Pos 4U /*!< MVFR1: FPDNaN bits Position */ +#define FPU_MVFR1_FPDNaN_Msk (0xFUL << FPU_MVFR1_FPDNaN_Pos) /*!< MVFR1: FPDNaN bits Mask */ + +#define FPU_MVFR1_FPFtZ_Pos 0U /*!< MVFR1: FPFtZ bits Position */ +#define FPU_MVFR1_FPFtZ_Msk (0xFUL /*<< FPU_MVFR1_FPFtZ_Pos*/) /*!< MVFR1: FPFtZ bits Mask */ + +/* Media and VFP Feature Register 2 Definitions */ +#define FPU_MVFR2_FPMisc_Pos 4U /*!< MVFR2: FPMisc bits Position */ +#define FPU_MVFR2_FPMisc_Msk (0xFUL << FPU_MVFR2_FPMisc_Pos) /*!< MVFR2: FPMisc bits Mask */ + +/*@} end of group CMSIS_FPU */ + +/* CoreDebug is deprecated. replaced by DCB (Debug Control Block) */ +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief \deprecated Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + __OM uint32_t DSCEMCR; /*!< Offset: 0x010 ( /W) Debug Set Clear Exception and Monitor Control Register */ + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< \deprecated CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< \deprecated CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Position */ +#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_FPD_Pos 23U /*!< \deprecated CoreDebug DHCSR: S_FPD Position */ +#define CoreDebug_DHCSR_S_FPD_Msk (1UL << CoreDebug_DHCSR_S_FPD_Pos) /*!< \deprecated CoreDebug DHCSR: S_FPD Mask */ + +#define CoreDebug_DHCSR_S_SUIDE_Pos 22U /*!< \deprecated CoreDebug DHCSR: S_SUIDE Position */ +#define CoreDebug_DHCSR_S_SUIDE_Msk (1UL << CoreDebug_DHCSR_S_SUIDE_Pos) /*!< \deprecated CoreDebug DHCSR: S_SUIDE Mask */ + +#define CoreDebug_DHCSR_S_NSUIDE_Pos 21U /*!< \deprecated CoreDebug DHCSR: S_NSUIDE Position */ +#define CoreDebug_DHCSR_S_NSUIDE_Msk (1UL << CoreDebug_DHCSR_S_NSUIDE_Pos) /*!< \deprecated CoreDebug DHCSR: S_NSUIDE Mask */ + +#define CoreDebug_DHCSR_S_SDE_Pos 20U /*!< \deprecated CoreDebug DHCSR: S_SDE Position */ +#define CoreDebug_DHCSR_S_SDE_Msk (1UL << CoreDebug_DHCSR_S_SDE_Pos) /*!< \deprecated CoreDebug DHCSR: S_SDE Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< \deprecated CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< \deprecated CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< \deprecated CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< \deprecated CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< \deprecated CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_PMOV_Pos 6U /*!< \deprecated CoreDebug DHCSR: C_PMOV Position */ +#define CoreDebug_DHCSR_C_PMOV_Msk (1UL << CoreDebug_DHCSR_C_PMOV_Pos) /*!< \deprecated CoreDebug DHCSR: C_PMOV Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< \deprecated CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< \deprecated CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< \deprecated CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< \deprecated CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< \deprecated CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< \deprecated CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< \deprecated CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< \deprecated CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< \deprecated CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< \deprecated CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< \deprecated CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< \deprecated CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< \deprecated CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< \deprecated CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< \deprecated CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< \deprecated CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< \deprecated CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< \deprecated CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< \deprecated CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< \deprecated CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< \deprecated CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< \deprecated CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< \deprecated CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< \deprecated CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< \deprecated CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Mask */ + +/* Debug Set Clear Exception and Monitor Control Register Definitions */ +#define CoreDebug_DSCEMCR_CLR_MON_REQ_Pos 19U /*!< \deprecated CoreDebug DSCEMCR: CLR_MON_REQ, Position */ +#define CoreDebug_DSCEMCR_CLR_MON_REQ_Msk (1UL << CoreDebug_DSCEMCR_CLR_MON_REQ_Pos) /*!< \deprecated CoreDebug DSCEMCR: CLR_MON_REQ, Mask */ + +#define CoreDebug_DSCEMCR_CLR_MON_PEND_Pos 17U /*!< \deprecated CoreDebug DSCEMCR: CLR_MON_PEND, Position */ +#define CoreDebug_DSCEMCR_CLR_MON_PEND_Msk (1UL << CoreDebug_DSCEMCR_CLR_MON_PEND_Pos) /*!< \deprecated CoreDebug DSCEMCR: CLR_MON_PEND, Mask */ + +#define CoreDebug_DSCEMCR_SET_MON_REQ_Pos 3U /*!< \deprecated CoreDebug DSCEMCR: SET_MON_REQ, Position */ +#define CoreDebug_DSCEMCR_SET_MON_REQ_Msk (1UL << CoreDebug_DSCEMCR_SET_MON_REQ_Pos) /*!< \deprecated CoreDebug DSCEMCR: SET_MON_REQ, Mask */ + +#define CoreDebug_DSCEMCR_SET_MON_PEND_Pos 1U /*!< \deprecated CoreDebug DSCEMCR: SET_MON_PEND, Position */ +#define CoreDebug_DSCEMCR_SET_MON_PEND_Msk (1UL << CoreDebug_DSCEMCR_SET_MON_PEND_Pos) /*!< \deprecated CoreDebug DSCEMCR: SET_MON_PEND, Mask */ + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_UIDEN_Pos 10U /*!< \deprecated CoreDebug DAUTHCTRL: UIDEN, Position */ +#define CoreDebug_DAUTHCTRL_UIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_UIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: UIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_UIDAPEN_Pos 9U /*!< \deprecated CoreDebug DAUTHCTRL: UIDAPEN, Position */ +#define CoreDebug_DAUTHCTRL_UIDAPEN_Msk (1UL << CoreDebug_DAUTHCTRL_UIDAPEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: UIDAPEN, Mask */ + +#define CoreDebug_DAUTHCTRL_FSDMA_Pos 8U /*!< \deprecated CoreDebug DAUTHCTRL: FSDMA, Position */ +#define CoreDebug_DAUTHCTRL_FSDMA_Msk (1UL << CoreDebug_DAUTHCTRL_FSDMA_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: FSDMA, Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Position */ +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Mask */ + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Mask */ + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos 16U /*!< \deprecated CoreDebug DSCSR: CDS Position */ +#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< \deprecated CoreDebug DSCSR: CDS Mask */ + +#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< \deprecated CoreDebug DSCSR: SBRSEL Position */ +#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< \deprecated CoreDebug DSCSR: SBRSEL Mask */ + +#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< \deprecated CoreDebug DSCSR: SBRSELEN Position */ +#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< \deprecated CoreDebug DSCSR: SBRSELEN Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DCB Debug Control Block + \brief Type definitions for the Debug Control Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Control Block Registers (DCB). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + __OM uint32_t DSCEMCR; /*!< Offset: 0x010 ( /W) Debug Set Clear Exception and Monitor Control Register */ + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} DCB_Type; + +/* DHCSR, Debug Halting Control and Status Register Definitions */ +#define DCB_DHCSR_DBGKEY_Pos 16U /*!< DCB DHCSR: Debug key Position */ +#define DCB_DHCSR_DBGKEY_Msk (0xFFFFUL << DCB_DHCSR_DBGKEY_Pos) /*!< DCB DHCSR: Debug key Mask */ + +#define DCB_DHCSR_S_RESTART_ST_Pos 26U /*!< DCB DHCSR: Restart sticky status Position */ +#define DCB_DHCSR_S_RESTART_ST_Msk (0x1UL << DCB_DHCSR_S_RESTART_ST_Pos) /*!< DCB DHCSR: Restart sticky status Mask */ + +#define DCB_DHCSR_S_RESET_ST_Pos 25U /*!< DCB DHCSR: Reset sticky status Position */ +#define DCB_DHCSR_S_RESET_ST_Msk (0x1UL << DCB_DHCSR_S_RESET_ST_Pos) /*!< DCB DHCSR: Reset sticky status Mask */ + +#define DCB_DHCSR_S_RETIRE_ST_Pos 24U /*!< DCB DHCSR: Retire sticky status Position */ +#define DCB_DHCSR_S_RETIRE_ST_Msk (0x1UL << DCB_DHCSR_S_RETIRE_ST_Pos) /*!< DCB DHCSR: Retire sticky status Mask */ + +#define DCB_DHCSR_S_FPD_Pos 23U /*!< DCB DHCSR: Floating-point registers Debuggable Position */ +#define DCB_DHCSR_S_FPD_Msk (0x1UL << DCB_DHCSR_S_FPD_Pos) /*!< DCB DHCSR: Floating-point registers Debuggable Mask */ + +#define DCB_DHCSR_S_SUIDE_Pos 22U /*!< DCB DHCSR: Secure unprivileged halting debug enabled Position */ +#define DCB_DHCSR_S_SUIDE_Msk (0x1UL << DCB_DHCSR_S_SUIDE_Pos) /*!< DCB DHCSR: Secure unprivileged halting debug enabled Mask */ + +#define DCB_DHCSR_S_NSUIDE_Pos 21U /*!< DCB DHCSR: Non-secure unprivileged halting debug enabled Position */ +#define DCB_DHCSR_S_NSUIDE_Msk (0x1UL << DCB_DHCSR_S_NSUIDE_Pos) /*!< DCB DHCSR: Non-secure unprivileged halting debug enabled Mask */ + +#define DCB_DHCSR_S_SDE_Pos 20U /*!< DCB DHCSR: Secure debug enabled Position */ +#define DCB_DHCSR_S_SDE_Msk (0x1UL << DCB_DHCSR_S_SDE_Pos) /*!< DCB DHCSR: Secure debug enabled Mask */ + +#define DCB_DHCSR_S_LOCKUP_Pos 19U /*!< DCB DHCSR: Lockup status Position */ +#define DCB_DHCSR_S_LOCKUP_Msk (0x1UL << DCB_DHCSR_S_LOCKUP_Pos) /*!< DCB DHCSR: Lockup status Mask */ + +#define DCB_DHCSR_S_SLEEP_Pos 18U /*!< DCB DHCSR: Sleeping status Position */ +#define DCB_DHCSR_S_SLEEP_Msk (0x1UL << DCB_DHCSR_S_SLEEP_Pos) /*!< DCB DHCSR: Sleeping status Mask */ + +#define DCB_DHCSR_S_HALT_Pos 17U /*!< DCB DHCSR: Halted status Position */ +#define DCB_DHCSR_S_HALT_Msk (0x1UL << DCB_DHCSR_S_HALT_Pos) /*!< DCB DHCSR: Halted status Mask */ + +#define DCB_DHCSR_S_REGRDY_Pos 16U /*!< DCB DHCSR: Register ready status Position */ +#define DCB_DHCSR_S_REGRDY_Msk (0x1UL << DCB_DHCSR_S_REGRDY_Pos) /*!< DCB DHCSR: Register ready status Mask */ + +#define DCB_DHCSR_C_PMOV_Pos 6U /*!< DCB DHCSR: Halt on PMU overflow control Position */ +#define DCB_DHCSR_C_PMOV_Msk (0x1UL << DCB_DHCSR_C_PMOV_Pos) /*!< DCB DHCSR: Halt on PMU overflow control Mask */ + +#define DCB_DHCSR_C_SNAPSTALL_Pos 5U /*!< DCB DHCSR: Snap stall control Position */ +#define DCB_DHCSR_C_SNAPSTALL_Msk (0x1UL << DCB_DHCSR_C_SNAPSTALL_Pos) /*!< DCB DHCSR: Snap stall control Mask */ + +#define DCB_DHCSR_C_MASKINTS_Pos 3U /*!< DCB DHCSR: Mask interrupts control Position */ +#define DCB_DHCSR_C_MASKINTS_Msk (0x1UL << DCB_DHCSR_C_MASKINTS_Pos) /*!< DCB DHCSR: Mask interrupts control Mask */ + +#define DCB_DHCSR_C_STEP_Pos 2U /*!< DCB DHCSR: Step control Position */ +#define DCB_DHCSR_C_STEP_Msk (0x1UL << DCB_DHCSR_C_STEP_Pos) /*!< DCB DHCSR: Step control Mask */ + +#define DCB_DHCSR_C_HALT_Pos 1U /*!< DCB DHCSR: Halt control Position */ +#define DCB_DHCSR_C_HALT_Msk (0x1UL << DCB_DHCSR_C_HALT_Pos) /*!< DCB DHCSR: Halt control Mask */ + +#define DCB_DHCSR_C_DEBUGEN_Pos 0U /*!< DCB DHCSR: Debug enable control Position */ +#define DCB_DHCSR_C_DEBUGEN_Msk (0x1UL /*<< DCB_DHCSR_C_DEBUGEN_Pos*/) /*!< DCB DHCSR: Debug enable control Mask */ + +/* DCRSR, Debug Core Register Select Register Definitions */ +#define DCB_DCRSR_REGWnR_Pos 16U /*!< DCB DCRSR: Register write/not-read Position */ +#define DCB_DCRSR_REGWnR_Msk (0x1UL << DCB_DCRSR_REGWnR_Pos) /*!< DCB DCRSR: Register write/not-read Mask */ + +#define DCB_DCRSR_REGSEL_Pos 0U /*!< DCB DCRSR: Register selector Position */ +#define DCB_DCRSR_REGSEL_Msk (0x7FUL /*<< DCB_DCRSR_REGSEL_Pos*/) /*!< DCB DCRSR: Register selector Mask */ + +/* DCRDR, Debug Core Register Data Register Definitions */ +#define DCB_DCRDR_DBGTMP_Pos 0U /*!< DCB DCRDR: Data temporary buffer Position */ +#define DCB_DCRDR_DBGTMP_Msk (0xFFFFFFFFUL /*<< DCB_DCRDR_DBGTMP_Pos*/) /*!< DCB DCRDR: Data temporary buffer Mask */ + +/* DEMCR, Debug Exception and Monitor Control Register Definitions */ +#define DCB_DEMCR_TRCENA_Pos 24U /*!< DCB DEMCR: Trace enable Position */ +#define DCB_DEMCR_TRCENA_Msk (0x1UL << DCB_DEMCR_TRCENA_Pos) /*!< DCB DEMCR: Trace enable Mask */ + +#define DCB_DEMCR_MONPRKEY_Pos 23U /*!< DCB DEMCR: Monitor pend req key Position */ +#define DCB_DEMCR_MONPRKEY_Msk (0x1UL << DCB_DEMCR_MONPRKEY_Pos) /*!< DCB DEMCR: Monitor pend req key Mask */ + +#define DCB_DEMCR_UMON_EN_Pos 21U /*!< DCB DEMCR: Unprivileged monitor enable Position */ +#define DCB_DEMCR_UMON_EN_Msk (0x1UL << DCB_DEMCR_UMON_EN_Pos) /*!< DCB DEMCR: Unprivileged monitor enable Mask */ + +#define DCB_DEMCR_SDME_Pos 20U /*!< DCB DEMCR: Secure DebugMonitor enable Position */ +#define DCB_DEMCR_SDME_Msk (0x1UL << DCB_DEMCR_SDME_Pos) /*!< DCB DEMCR: Secure DebugMonitor enable Mask */ + +#define DCB_DEMCR_MON_REQ_Pos 19U /*!< DCB DEMCR: Monitor request Position */ +#define DCB_DEMCR_MON_REQ_Msk (0x1UL << DCB_DEMCR_MON_REQ_Pos) /*!< DCB DEMCR: Monitor request Mask */ + +#define DCB_DEMCR_MON_STEP_Pos 18U /*!< DCB DEMCR: Monitor step Position */ +#define DCB_DEMCR_MON_STEP_Msk (0x1UL << DCB_DEMCR_MON_STEP_Pos) /*!< DCB DEMCR: Monitor step Mask */ + +#define DCB_DEMCR_MON_PEND_Pos 17U /*!< DCB DEMCR: Monitor pend Position */ +#define DCB_DEMCR_MON_PEND_Msk (0x1UL << DCB_DEMCR_MON_PEND_Pos) /*!< DCB DEMCR: Monitor pend Mask */ + +#define DCB_DEMCR_MON_EN_Pos 16U /*!< DCB DEMCR: Monitor enable Position */ +#define DCB_DEMCR_MON_EN_Msk (0x1UL << DCB_DEMCR_MON_EN_Pos) /*!< DCB DEMCR: Monitor enable Mask */ + +#define DCB_DEMCR_VC_SFERR_Pos 11U /*!< DCB DEMCR: Vector Catch SecureFault Position */ +#define DCB_DEMCR_VC_SFERR_Msk (0x1UL << DCB_DEMCR_VC_SFERR_Pos) /*!< DCB DEMCR: Vector Catch SecureFault Mask */ + +#define DCB_DEMCR_VC_HARDERR_Pos 10U /*!< DCB DEMCR: Vector Catch HardFault errors Position */ +#define DCB_DEMCR_VC_HARDERR_Msk (0x1UL << DCB_DEMCR_VC_HARDERR_Pos) /*!< DCB DEMCR: Vector Catch HardFault errors Mask */ + +#define DCB_DEMCR_VC_INTERR_Pos 9U /*!< DCB DEMCR: Vector Catch interrupt errors Position */ +#define DCB_DEMCR_VC_INTERR_Msk (0x1UL << DCB_DEMCR_VC_INTERR_Pos) /*!< DCB DEMCR: Vector Catch interrupt errors Mask */ + +#define DCB_DEMCR_VC_BUSERR_Pos 8U /*!< DCB DEMCR: Vector Catch BusFault errors Position */ +#define DCB_DEMCR_VC_BUSERR_Msk (0x1UL << DCB_DEMCR_VC_BUSERR_Pos) /*!< DCB DEMCR: Vector Catch BusFault errors Mask */ + +#define DCB_DEMCR_VC_STATERR_Pos 7U /*!< DCB DEMCR: Vector Catch state errors Position */ +#define DCB_DEMCR_VC_STATERR_Msk (0x1UL << DCB_DEMCR_VC_STATERR_Pos) /*!< DCB DEMCR: Vector Catch state errors Mask */ + +#define DCB_DEMCR_VC_CHKERR_Pos 6U /*!< DCB DEMCR: Vector Catch check errors Position */ +#define DCB_DEMCR_VC_CHKERR_Msk (0x1UL << DCB_DEMCR_VC_CHKERR_Pos) /*!< DCB DEMCR: Vector Catch check errors Mask */ + +#define DCB_DEMCR_VC_NOCPERR_Pos 5U /*!< DCB DEMCR: Vector Catch NOCP errors Position */ +#define DCB_DEMCR_VC_NOCPERR_Msk (0x1UL << DCB_DEMCR_VC_NOCPERR_Pos) /*!< DCB DEMCR: Vector Catch NOCP errors Mask */ + +#define DCB_DEMCR_VC_MMERR_Pos 4U /*!< DCB DEMCR: Vector Catch MemManage errors Position */ +#define DCB_DEMCR_VC_MMERR_Msk (0x1UL << DCB_DEMCR_VC_MMERR_Pos) /*!< DCB DEMCR: Vector Catch MemManage errors Mask */ + +#define DCB_DEMCR_VC_CORERESET_Pos 0U /*!< DCB DEMCR: Vector Catch Core reset Position */ +#define DCB_DEMCR_VC_CORERESET_Msk (0x1UL /*<< DCB_DEMCR_VC_CORERESET_Pos*/) /*!< DCB DEMCR: Vector Catch Core reset Mask */ + +/* DSCEMCR, Debug Set Clear Exception and Monitor Control Register Definitions */ +#define DCB_DSCEMCR_CLR_MON_REQ_Pos 19U /*!< DCB DSCEMCR: Clear monitor request Position */ +#define DCB_DSCEMCR_CLR_MON_REQ_Msk (0x1UL << DCB_DSCEMCR_CLR_MON_REQ_Pos) /*!< DCB DSCEMCR: Clear monitor request Mask */ + +#define DCB_DSCEMCR_CLR_MON_PEND_Pos 17U /*!< DCB DSCEMCR: Clear monitor pend Position */ +#define DCB_DSCEMCR_CLR_MON_PEND_Msk (0x1UL << DCB_DSCEMCR_CLR_MON_PEND_Pos) /*!< DCB DSCEMCR: Clear monitor pend Mask */ + +#define DCB_DSCEMCR_SET_MON_REQ_Pos 3U /*!< DCB DSCEMCR: Set monitor request Position */ +#define DCB_DSCEMCR_SET_MON_REQ_Msk (0x1UL << DCB_DSCEMCR_SET_MON_REQ_Pos) /*!< DCB DSCEMCR: Set monitor request Mask */ + +#define DCB_DSCEMCR_SET_MON_PEND_Pos 1U /*!< DCB DSCEMCR: Set monitor pend Position */ +#define DCB_DSCEMCR_SET_MON_PEND_Msk (0x1UL << DCB_DSCEMCR_SET_MON_PEND_Pos) /*!< DCB DSCEMCR: Set monitor pend Mask */ + +/* DAUTHCTRL, Debug Authentication Control Register Definitions */ +#define DCB_DAUTHCTRL_UIDEN_Pos 10U /*!< DCB DAUTHCTRL: Unprivileged Invasive Debug Enable Position */ +#define DCB_DAUTHCTRL_UIDEN_Msk (0x1UL << DCB_DAUTHCTRL_UIDEN_Pos) /*!< DCB DAUTHCTRL: Unprivileged Invasive Debug Enable Mask */ + +#define DCB_DAUTHCTRL_UIDAPEN_Pos 9U /*!< DCB DAUTHCTRL: Unprivileged Invasive DAP Access Enable Position */ +#define DCB_DAUTHCTRL_UIDAPEN_Msk (0x1UL << DCB_DAUTHCTRL_UIDAPEN_Pos) /*!< DCB DAUTHCTRL: Unprivileged Invasive DAP Access Enable Mask */ + +#define DCB_DAUTHCTRL_FSDMA_Pos 8U /*!< DCB DAUTHCTRL: Force Secure DebugMonitor Allowed Position */ +#define DCB_DAUTHCTRL_FSDMA_Msk (0x1UL << DCB_DAUTHCTRL_FSDMA_Pos) /*!< DCB DAUTHCTRL: Force Secure DebugMonitor Allowed Mask */ + +#define DCB_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPNIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPNIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPNIDENSEL_Msk (0x1UL << DCB_DAUTHCTRL_SPNIDENSEL_Pos) /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Mask */ + +#define DCB_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< DCB DAUTHCTRL: Secure invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPIDENSEL_Msk (0x1UL /*<< DCB_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< DCB DAUTHCTRL: Secure invasive debug enable select Mask */ + +/* DSCSR, Debug Security Control and Status Register Definitions */ +#define DCB_DSCSR_CDSKEY_Pos 17U /*!< DCB DSCSR: CDS write-enable key Position */ +#define DCB_DSCSR_CDSKEY_Msk (0x1UL << DCB_DSCSR_CDSKEY_Pos) /*!< DCB DSCSR: CDS write-enable key Mask */ + +#define DCB_DSCSR_CDS_Pos 16U /*!< DCB DSCSR: Current domain Secure Position */ +#define DCB_DSCSR_CDS_Msk (0x1UL << DCB_DSCSR_CDS_Pos) /*!< DCB DSCSR: Current domain Secure Mask */ + +#define DCB_DSCSR_SBRSEL_Pos 1U /*!< DCB DSCSR: Secure banked register select Position */ +#define DCB_DSCSR_SBRSEL_Msk (0x1UL << DCB_DSCSR_SBRSEL_Pos) /*!< DCB DSCSR: Secure banked register select Mask */ + +#define DCB_DSCSR_SBRSELEN_Pos 0U /*!< DCB DSCSR: Secure banked register select enable Position */ +#define DCB_DSCSR_SBRSELEN_Msk (0x1UL /*<< DCB_DSCSR_SBRSELEN_Pos*/) /*!< DCB DSCSR: Secure banked register select enable Mask */ + +/*@} end of group CMSIS_DCB */ + + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DIB Debug Identification Block + \brief Type definitions for the Debug Identification Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Identification Block Registers (DIB). + */ +typedef struct +{ + __OM uint32_t DLAR; /*!< Offset: 0x000 ( /W) SCS Software Lock Access Register */ + __IM uint32_t DLSR; /*!< Offset: 0x004 (R/ ) SCS Software Lock Status Register */ + __IM uint32_t DAUTHSTATUS; /*!< Offset: 0x008 (R/ ) Debug Authentication Status Register */ + __IM uint32_t DDEVARCH; /*!< Offset: 0x00C (R/ ) SCS Device Architecture Register */ + __IM uint32_t DDEVTYPE; /*!< Offset: 0x010 (R/ ) SCS Device Type Register */ +} DIB_Type; + +/* DLAR, SCS Software Lock Access Register Definitions */ +#define DIB_DLAR_KEY_Pos 0U /*!< DIB DLAR: KEY Position */ +#define DIB_DLAR_KEY_Msk (0xFFFFFFFFUL /*<< DIB_DLAR_KEY_Pos */) /*!< DIB DLAR: KEY Mask */ + +/* DLSR, SCS Software Lock Status Register Definitions */ +#define DIB_DLSR_nTT_Pos 2U /*!< DIB DLSR: Not thirty-two bit Position */ +#define DIB_DLSR_nTT_Msk (0x1UL << DIB_DLSR_nTT_Pos ) /*!< DIB DLSR: Not thirty-two bit Mask */ + +#define DIB_DLSR_SLK_Pos 1U /*!< DIB DLSR: Software Lock status Position */ +#define DIB_DLSR_SLK_Msk (0x1UL << DIB_DLSR_SLK_Pos ) /*!< DIB DLSR: Software Lock status Mask */ + +#define DIB_DLSR_SLI_Pos 0U /*!< DIB DLSR: Software Lock implemented Position */ +#define DIB_DLSR_SLI_Msk (0x1UL /*<< DIB_DLSR_SLI_Pos*/) /*!< DIB DLSR: Software Lock implemented Mask */ + +/* DAUTHSTATUS, Debug Authentication Status Register Definitions */ +#define DIB_DAUTHSTATUS_SUNID_Pos 22U /*!< DIB DAUTHSTATUS: Secure Unprivileged Non-invasive Debug Allowed Position */ +#define DIB_DAUTHSTATUS_SUNID_Msk (0x3UL << DIB_DAUTHSTATUS_SUNID_Pos ) /*!< DIB DAUTHSTATUS: Secure Unprivileged Non-invasive Debug Allowed Mask */ + +#define DIB_DAUTHSTATUS_SUID_Pos 20U /*!< DIB DAUTHSTATUS: Secure Unprivileged Invasive Debug Allowed Position */ +#define DIB_DAUTHSTATUS_SUID_Msk (0x3UL << DIB_DAUTHSTATUS_SUID_Pos ) /*!< DIB DAUTHSTATUS: Secure Unprivileged Invasive Debug Allowed Mask */ + +#define DIB_DAUTHSTATUS_NSUNID_Pos 18U /*!< DIB DAUTHSTATUS: Non-secure Unprivileged Non-invasive Debug Allo Position */ +#define DIB_DAUTHSTATUS_NSUNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSUNID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Unprivileged Non-invasive Debug Allo Mask */ + +#define DIB_DAUTHSTATUS_NSUID_Pos 16U /*!< DIB DAUTHSTATUS: Non-secure Unprivileged Invasive Debug Allowed Position */ +#define DIB_DAUTHSTATUS_NSUID_Msk (0x3UL << DIB_DAUTHSTATUS_NSUID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Unprivileged Invasive Debug Allowed Mask */ + +#define DIB_DAUTHSTATUS_SNID_Pos 6U /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_SNID_Msk (0x3UL << DIB_DAUTHSTATUS_SNID_Pos ) /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_SID_Pos 4U /*!< DIB DAUTHSTATUS: Secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_SID_Msk (0x3UL << DIB_DAUTHSTATUS_SID_Pos ) /*!< DIB DAUTHSTATUS: Secure Invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSNID_Pos 2U /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSNID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSID_Pos 0U /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSID_Msk (0x3UL /*<< DIB_DAUTHSTATUS_NSID_Pos*/) /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Mask */ + +/* DDEVARCH, SCS Device Architecture Register Definitions */ +#define DIB_DDEVARCH_ARCHITECT_Pos 21U /*!< DIB DDEVARCH: Architect Position */ +#define DIB_DDEVARCH_ARCHITECT_Msk (0x7FFUL << DIB_DDEVARCH_ARCHITECT_Pos ) /*!< DIB DDEVARCH: Architect Mask */ + +#define DIB_DDEVARCH_PRESENT_Pos 20U /*!< DIB DDEVARCH: DEVARCH Present Position */ +#define DIB_DDEVARCH_PRESENT_Msk (0x1FUL << DIB_DDEVARCH_PRESENT_Pos ) /*!< DIB DDEVARCH: DEVARCH Present Mask */ + +#define DIB_DDEVARCH_REVISION_Pos 16U /*!< DIB DDEVARCH: Revision Position */ +#define DIB_DDEVARCH_REVISION_Msk (0xFUL << DIB_DDEVARCH_REVISION_Pos ) /*!< DIB DDEVARCH: Revision Mask */ + +#define DIB_DDEVARCH_ARCHVER_Pos 12U /*!< DIB DDEVARCH: Architecture Version Position */ +#define DIB_DDEVARCH_ARCHVER_Msk (0xFUL << DIB_DDEVARCH_ARCHVER_Pos ) /*!< DIB DDEVARCH: Architecture Version Mask */ + +#define DIB_DDEVARCH_ARCHPART_Pos 0U /*!< DIB DDEVARCH: Architecture Part Position */ +#define DIB_DDEVARCH_ARCHPART_Msk (0xFFFUL /*<< DIB_DDEVARCH_ARCHPART_Pos*/) /*!< DIB DDEVARCH: Architecture Part Mask */ + +/* DDEVTYPE, SCS Device Type Register Definitions */ +#define DIB_DDEVTYPE_SUB_Pos 4U /*!< DIB DDEVTYPE: Sub-type Position */ +#define DIB_DDEVTYPE_SUB_Msk (0xFUL << DIB_DDEVTYPE_SUB_Pos ) /*!< DIB DDEVTYPE: Sub-type Mask */ + +#define DIB_DDEVTYPE_MAJOR_Pos 0U /*!< DIB DDEVTYPE: Major type Position */ +#define DIB_DDEVTYPE_MAJOR_Msk (0xFUL /*<< DIB_DDEVTYPE_MAJOR_Pos*/) /*!< DIB DDEVTYPE: Major type Mask */ + + +/*@} end of group CMSIS_DIB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define MEMSYSCTL_BASE (0xE001E000UL) /*!< Memory System Control Base Address */ + #define ERRBNK_BASE (0xE001E100UL) /*!< Error Banking Base Address */ + #define PWRMODCTL_BASE (0xE001E300UL) /*!< Power Mode Control Base Address */ + #define EWIC_BASE (0xE001E400UL) /*!< External Wakeup Interrupt Controller Base Address */ + #define PRCCFGINF_BASE (0xE001E700UL) /*!< Processor Configuration Information Base Address */ + #define STL_BASE (0xE001E800UL) /*!< Software Test Library Base Address */ + #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ + #define CoreDebug_BASE (0xE000EDF0UL) /*!< \deprecated Core Debug Base Address */ + #define DCB_BASE (0xE000EDF0UL) /*!< DCB Base Address */ + #define DIB_BASE (0xE000EFB0UL) /*!< DIB Base Address */ + #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + #define ICB ((ICB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ + #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ + #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ + #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ + #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ + #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ + #define MEMSYSCTL ((MemSysCtl_Type *) MEMSYSCTL_BASE ) /*!< Memory System Control configuration struct */ + #define ERRBNK ((ErrBnk_Type *) ERRBNK_BASE ) /*!< Error Banking configuration struct */ + #define PWRMODCTL ((PwrModCtl_Type *) PWRMODCTL_BASE ) /*!< Power Mode Control configuration struct */ + #define EWIC ((EWIC_Type *) EWIC_BASE ) /*!< EWIC configuration struct */ + #define PRCCFGINF ((PrcCfgInf_Type *) PRCCFGINF_BASE ) /*!< Processor Configuration Information configuration struct */ + #define STL ((STL_Type *) STL_BASE ) /*!< Software Test Library configuration struct */ + #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< \deprecated Core Debug configuration struct */ + #define DCB ((DCB_Type *) DCB_BASE ) /*!< DCB configuration struct */ + #define DIB ((DIB_Type *) DIB_BASE ) /*!< DIB configuration struct */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ + #endif + + #if defined (__PMU_PRESENT) && (__PMU_PRESENT == 1U) + #define PMU_BASE (0xE0003000UL) /*!< PMU Base Address */ + #define PMU ((PMU_Type *) PMU_BASE ) /*!< PMU configuration struct */ + #endif + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ + #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ + #endif + + #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ + #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ + #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< \deprecated Core Debug Base Address (non-secure address space) */ + #define DCB_BASE_NS (0xE002EDF0UL) /*!< DCB Base Address (non-secure address space) */ + #define DIB_BASE_NS (0xE002EFB0UL) /*!< DIB Base Address (non-secure address space) */ + #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ + #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ + #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + + #define ICB_NS ((ICB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */ + #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ + #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ + #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ + #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< \deprecated Core Debug configuration struct (non-secure address space) */ + #define DCB_NS ((DCB_Type *) DCB_BASE_NS ) /*!< DCB configuration struct (non-secure address space) */ + #define DIB_NS ((DIB_Type *) DIB_BASE_NS ) /*!< DIB configuration struct (non-secure address space) */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ + #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ + #endif + + #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */ + #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */ + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_register_aliases Backwards Compatibility Aliases + \brief Register alias definitions for backwards compatibility. + @{ + */ +#define ID_ADR (ID_AFR) /*!< SCB Auxiliary Feature Register */ + +/* 'SCnSCB' is deprecated and replaced by 'ICB' */ +typedef ICB_Type SCnSCB_Type; + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_DISCRITAXIRUW_Pos (ICB_ACTLR_DISCRITAXIRUW_Pos) +#define SCnSCB_ACTLR_DISCRITAXIRUW_Msk (ICB_ACTLR_DISCRITAXIRUW_Msk) + +#define SCnSCB_ACTLR_DISDI_Pos (ICB_ACTLR_DISDI_Pos) +#define SCnSCB_ACTLR_DISDI_Msk (ICB_ACTLR_DISDI_Msk) + +#define SCnSCB_ACTLR_DISCRITAXIRUR_Pos (ICB_ACTLR_DISCRITAXIRUR_Pos) +#define SCnSCB_ACTLR_DISCRITAXIRUR_Msk (ICB_ACTLR_DISCRITAXIRUR_Msk) + +#define SCnSCB_ACTLR_EVENTBUSEN_Pos (ICB_ACTLR_EVENTBUSEN_Pos) +#define SCnSCB_ACTLR_EVENTBUSEN_Msk (ICB_ACTLR_EVENTBUSEN_Msk) + +#define SCnSCB_ACTLR_EVENTBUSEN_S_Pos (ICB_ACTLR_EVENTBUSEN_S_Pos) +#define SCnSCB_ACTLR_EVENTBUSEN_S_Msk (ICB_ACTLR_EVENTBUSEN_S_Msk) + +#define SCnSCB_ACTLR_DISITMATBFLUSH_Pos (ICB_ACTLR_DISITMATBFLUSH_Pos) +#define SCnSCB_ACTLR_DISITMATBFLUSH_Msk (ICB_ACTLR_DISITMATBFLUSH_Msk) + +#define SCnSCB_ACTLR_DISNWAMODE_Pos (ICB_ACTLR_DISNWAMODE_Pos) +#define SCnSCB_ACTLR_DISNWAMODE_Msk (ICB_ACTLR_DISNWAMODE_Msk) + +#define SCnSCB_ACTLR_FPEXCODIS_Pos (ICB_ACTLR_FPEXCODIS_Pos) +#define SCnSCB_ACTLR_FPEXCODIS_Msk (ICB_ACTLR_FPEXCODIS_Msk) + +#define SCnSCB_ACTLR_DISOLAP_Pos (ICB_ACTLR_DISOLAP_Pos) +#define SCnSCB_ACTLR_DISOLAP_Msk (ICB_ACTLR_DISOLAP_Msk) + +#define SCnSCB_ACTLR_DISOLAPS_Pos (ICB_ACTLR_DISOLAPS_Pos) +#define SCnSCB_ACTLR_DISOLAPS_Msk (ICB_ACTLR_DISOLAPS_Msk) + +#define SCnSCB_ACTLR_DISLOBR_Pos (ICB_ACTLR_DISLOBR_Pos) +#define SCnSCB_ACTLR_DISLOBR_Msk (ICB_ACTLR_DISLOBR_Msk) + +#define SCnSCB_ACTLR_DISLO_Pos (ICB_ACTLR_DISLO_Pos) +#define SCnSCB_ACTLR_DISLO_Msk (ICB_ACTLR_DISLO_Msk) + +#define SCnSCB_ACTLR_DISLOLEP_Pos (ICB_ACTLR_DISLOLEP_Pos) +#define SCnSCB_ACTLR_DISLOLEP_Msk (ICB_ACTLR_DISLOLEP_Msk) + +#define SCnSCB_ACTLR_DISFOLD_Pos (ICB_ACTLR_DISFOLD_Pos) +#define SCnSCB_ACTLR_DISFOLD_Msk (ICB_ACTLR_DISFOLD_Msk) + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos (ICB_ICTR_INTLINESNUM_Pos) +#define SCnSCB_ICTR_INTLINESNUM_Msk (ICB_ICTR_INTLINESNUM_Msk) + +#define SCnSCB (ICB) +#define SCnSCB_NS (ICB_NS) + +/*@} */ + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* Special LR values for Secure/Non-Secure call handling and exception handling */ + +/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ +#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ + +/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ +#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ +#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ +#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ +#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ +#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ +#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */ +#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ + +/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ +#else +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ +#endif + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + __DSB(); +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Priority Grouping (non-secure) + \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB_NS->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB_NS->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping (non-secure) + \details Reads the priority grouping field from the non-secure NVIC when in secure state. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void) +{ + return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv8.h" + +#endif + +/* ########################## PMU functions and events #################################### */ + +#if defined (__PMU_PRESENT) && (__PMU_PRESENT == 1U) + +#include "pmu_armv8.h" + +/** + \brief Cortex-M55 PMU events + \note Architectural PMU events can be found in pmu_armv8.h +*/ + +#define ARMCM55_PMU_ECC_ERR 0xC000 /*!< Any ECC error */ +#define ARMCM55_PMU_ECC_ERR_FATAL 0xC001 /*!< Any fatal ECC error */ +#define ARMCM55_PMU_ECC_ERR_DCACHE 0xC010 /*!< Any ECC error in the data cache */ +#define ARMCM55_PMU_ECC_ERR_ICACHE 0xC011 /*!< Any ECC error in the instruction cache */ +#define ARMCM55_PMU_ECC_ERR_FATAL_DCACHE 0xC012 /*!< Any fatal ECC error in the data cache */ +#define ARMCM55_PMU_ECC_ERR_FATAL_ICACHE 0xC013 /*!< Any fatal ECC error in the instruction cache*/ +#define ARMCM55_PMU_ECC_ERR_DTCM 0xC020 /*!< Any ECC error in the DTCM */ +#define ARMCM55_PMU_ECC_ERR_ITCM 0xC021 /*!< Any ECC error in the ITCM */ +#define ARMCM55_PMU_ECC_ERR_FATAL_DTCM 0xC022 /*!< Any fatal ECC error in the DTCM */ +#define ARMCM55_PMU_ECC_ERR_FATAL_ITCM 0xC023 /*!< Any fatal ECC error in the ITCM */ +#define ARMCM55_PMU_PF_LINEFILL 0xC100 /*!< A prefetcher starts a line-fill */ +#define ARMCM55_PMU_PF_CANCEL 0xC101 /*!< A prefetcher stops prefetching */ +#define ARMCM55_PMU_PF_DROP_LINEFILL 0xC102 /*!< A linefill triggered by a prefetcher has been dropped because of lack of buffering */ +#define ARMCM55_PMU_NWAMODE_ENTER 0xC200 /*!< No write-allocate mode entry */ +#define ARMCM55_PMU_NWAMODE 0xC201 /*!< Write-allocate store is not allocated into the data cache due to no-write-allocate mode */ +#define ARMCM55_PMU_SAHB_ACCESS 0xC300 /*!< Read or write access on the S-AHB interface to the TCM */ +#define ARMCM55_PMU_PAHB_ACCESS 0xC301 /*!< Read or write access to the P-AHB write interface */ +#define ARMCM55_PMU_AXI_WRITE_ACCESS 0xC302 /*!< Any beat access to M-AXI write interface */ +#define ARMCM55_PMU_AXI_READ_ACCESS 0xC303 /*!< Any beat access to M-AXI read interface */ +#define ARMCM55_PMU_DOSTIMEOUT_DOUBLE 0xC400 /*!< Denial of Service timeout has fired twice and caused buffers to drain to allow forward progress */ +#define ARMCM55_PMU_DOSTIMEOUT_TRIPLE 0xC401 /*!< Denial of Service timeout has fired three times and blocked the LSU to force forward progress */ + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = FPU->MVFR0; + if ((mvfr0 & (FPU_MVFR0_FPSP_Msk | FPU_MVFR0_FPDP_Msk)) == 0x220U) + { + return 2U; /* Double + Single precision FPU */ + } + else if ((mvfr0 & (FPU_MVFR0_FPSP_Msk | FPU_MVFR0_FPDP_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + +/* ########################## MVE functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_MveFunctions MVE Functions + \brief Function that provides MVE type. + @{ + */ + +/** + \brief get MVE type + \details returns the MVE type + \returns + - \b 0: No Vector Extension (MVE) + - \b 1: Integer Vector Extension (MVE-I) + - \b 2: Floating-point Vector Extension (MVE-F) + */ +__STATIC_INLINE uint32_t SCB_GetMVEType(void) +{ + const uint32_t mvfr1 = FPU->MVFR1; + if ((mvfr1 & FPU_MVFR1_MVE_Msk) == (0x2U << FPU_MVFR1_MVE_Pos)) + { + return 2U; + } + else if ((mvfr1 & FPU_MVFR1_MVE_Msk) == (0x1U << FPU_MVFR1_MVE_Pos)) + { + return 1U; + } + else + { + return 0U; + } +} + + +/*@} end of CMSIS_Core_MveFunctions */ + + +/* ########################## Cache functions #################################### */ + +#if ((defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)) || \ + (defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U))) +#include "cachel1_armv7.h" +#endif + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + + +/* ################################## Debug Control function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DCBFunctions Debug Control Functions + \brief Functions that access the Debug Control Block. + @{ + */ + + +/** + \brief Set Debug Authentication Control Register + \details writes to Debug Authentication Control register. + \param [in] value value to be writen. + */ +__STATIC_INLINE void DCB_SetAuthCtrl(uint32_t value) +{ + __DSB(); + __ISB(); + DCB->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register + \details Reads Debug Authentication Control register. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t DCB_GetAuthCtrl(void) +{ + return (DCB->DAUTHCTRL); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Debug Authentication Control Register (non-secure) + \details writes to non-secure Debug Authentication Control register when in secure state. + \param [in] value value to be writen + */ +__STATIC_INLINE void TZ_DCB_SetAuthCtrl_NS(uint32_t value) +{ + __DSB(); + __ISB(); + DCB_NS->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register (non-secure) + \details Reads non-secure Debug Authentication Control register when in secure state. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t TZ_DCB_GetAuthCtrl_NS(void) +{ + return (DCB_NS->DAUTHCTRL); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## Debug Identification function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DIBFunctions Debug Identification Functions + \brief Functions that access the Debug Identification Block. + @{ + */ + + +/** + \brief Get Debug Authentication Status Register + \details Reads Debug Authentication Status register. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t DIB_GetAuthStatus(void) +{ + return (DIB->DAUTHSTATUS); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Debug Authentication Status Register (non-secure) + \details Reads non-secure Debug Authentication Status register when in secure state. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t TZ_DIB_GetAuthStatus_NS(void) +{ + return (DIB_NS->DAUTHSTATUS); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM55_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/CMSIS/Core/Include/core_cm7.h b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/CMSIS/Core/Include/core_cm7.h new file mode 100644 index 0000000000..010506e9fa --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/CMSIS/Core/Include/core_cm7.h @@ -0,0 +1,2366 @@ +/**************************************************************************//** + * @file core_cm7.h + * @brief CMSIS Cortex-M7 Core Peripheral Access Layer Header File + * @version V5.1.6 + * @date 04. June 2021 + ******************************************************************************/ +/* + * Copyright (c) 2009-2021 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM7_H_GENERIC +#define __CORE_CM7_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M7 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM7 definitions */ +#define __CM7_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM7_CMSIS_VERSION_SUB ( __CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM7_CMSIS_VERSION ((__CM7_CMSIS_VERSION_MAIN << 16U) | \ + __CM7_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (7U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM7_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM7_H_DEPENDANT +#define __CORE_CM7_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM7_REV + #define __CM7_REV 0x0000U + #warning "__CM7_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __ICACHE_PRESENT + #define __ICACHE_PRESENT 0U + #warning "__ICACHE_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DCACHE_PRESENT + #define __DCACHE_PRESENT 0U + #warning "__DCACHE_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DTCM_PRESENT + #define __DTCM_PRESENT 0U + #warning "__DTCM_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 1U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M7 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:1; /*!< bit: 9 Reserved */ + uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit */ + uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */ +#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */ +#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ + uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24U]; + __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RESERVED1[24U]; + __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24U]; + __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24U]; + __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56U]; + __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t ID_MFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ID_ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[1U]; + __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ + __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ + __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ + __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + uint32_t RESERVED3[93U]; + __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ + uint32_t RESERVED4[15U]; + __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ + uint32_t RESERVED5[1U]; + __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ + uint32_t RESERVED6[1U]; + __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ + __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ + __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ + __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ + __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ + __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ + __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ + __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ + __OM uint32_t BPIALL; /*!< Offset: 0x278 ( /W) Branch Predictor Invalidate All */ + uint32_t RESERVED7[5U]; + __IOM uint32_t ITCMCR; /*!< Offset: 0x290 (R/W) Instruction Tightly-Coupled Memory Control Register */ + __IOM uint32_t DTCMCR; /*!< Offset: 0x294 (R/W) Data Tightly-Coupled Memory Control Registers */ + __IOM uint32_t AHBPCR; /*!< Offset: 0x298 (R/W) AHBP Control Register */ + __IOM uint32_t CACR; /*!< Offset: 0x29C (R/W) L1 Cache Control Register */ + __IOM uint32_t AHBSCR; /*!< Offset: 0x2A0 (R/W) AHB Slave Control Register */ + uint32_t RESERVED8[1U]; + __IOM uint32_t ABFSR; /*!< Offset: 0x2A8 (R/W) Auxiliary Bus Fault Status Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: Branch prediction enable bit Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: Branch prediction enable bit Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: Instruction cache enable bit Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: Instruction cache enable bit Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: Cache enable bit Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: Cache enable bit Mask */ + +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_CFSR_MEMFAULTSR_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/* SCB Cache Level ID Register Definitions */ +#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ +#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ + +#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ +#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ + +/* SCB Cache Type Register Definitions */ +#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ +#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ + +#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ +#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ + +#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ +#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ + +#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ +#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ + +#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ +#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ + +/* SCB Cache Size ID Register Definitions */ +#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ +#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ + +#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ +#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ + +#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ +#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ + +#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ +#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ + +#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ +#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ + +#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ +#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ + +#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ +#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ + +/* SCB Cache Size Selection Register Definitions */ +#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ +#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ + +#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ +#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ + +/* SCB Software Triggered Interrupt Register Definitions */ +#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ +#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ + +/* SCB D-Cache Invalidate by Set-way Register Definitions */ +#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ +#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ + +#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ +#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ + +/* SCB D-Cache Clean by Set-way Register Definitions */ +#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ +#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ + +#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ +#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ + +/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ +#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ +#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ + +#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ +#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ + +/* Instruction Tightly-Coupled Memory Control Register Definitions */ +#define SCB_ITCMCR_SZ_Pos 3U /*!< SCB ITCMCR: SZ Position */ +#define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) /*!< SCB ITCMCR: SZ Mask */ + +#define SCB_ITCMCR_RETEN_Pos 2U /*!< SCB ITCMCR: RETEN Position */ +#define SCB_ITCMCR_RETEN_Msk (1UL << SCB_ITCMCR_RETEN_Pos) /*!< SCB ITCMCR: RETEN Mask */ + +#define SCB_ITCMCR_RMW_Pos 1U /*!< SCB ITCMCR: RMW Position */ +#define SCB_ITCMCR_RMW_Msk (1UL << SCB_ITCMCR_RMW_Pos) /*!< SCB ITCMCR: RMW Mask */ + +#define SCB_ITCMCR_EN_Pos 0U /*!< SCB ITCMCR: EN Position */ +#define SCB_ITCMCR_EN_Msk (1UL /*<< SCB_ITCMCR_EN_Pos*/) /*!< SCB ITCMCR: EN Mask */ + +/* Data Tightly-Coupled Memory Control Register Definitions */ +#define SCB_DTCMCR_SZ_Pos 3U /*!< SCB DTCMCR: SZ Position */ +#define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) /*!< SCB DTCMCR: SZ Mask */ + +#define SCB_DTCMCR_RETEN_Pos 2U /*!< SCB DTCMCR: RETEN Position */ +#define SCB_DTCMCR_RETEN_Msk (1UL << SCB_DTCMCR_RETEN_Pos) /*!< SCB DTCMCR: RETEN Mask */ + +#define SCB_DTCMCR_RMW_Pos 1U /*!< SCB DTCMCR: RMW Position */ +#define SCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos) /*!< SCB DTCMCR: RMW Mask */ + +#define SCB_DTCMCR_EN_Pos 0U /*!< SCB DTCMCR: EN Position */ +#define SCB_DTCMCR_EN_Msk (1UL /*<< SCB_DTCMCR_EN_Pos*/) /*!< SCB DTCMCR: EN Mask */ + +/* AHBP Control Register Definitions */ +#define SCB_AHBPCR_SZ_Pos 1U /*!< SCB AHBPCR: SZ Position */ +#define SCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos) /*!< SCB AHBPCR: SZ Mask */ + +#define SCB_AHBPCR_EN_Pos 0U /*!< SCB AHBPCR: EN Position */ +#define SCB_AHBPCR_EN_Msk (1UL /*<< SCB_AHBPCR_EN_Pos*/) /*!< SCB AHBPCR: EN Mask */ + +/* L1 Cache Control Register Definitions */ +#define SCB_CACR_FORCEWT_Pos 2U /*!< SCB CACR: FORCEWT Position */ +#define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: FORCEWT Mask */ + +#define SCB_CACR_ECCEN_Pos 1U /*!< \deprecated SCB CACR: ECCEN Position */ +#define SCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos) /*!< \deprecated SCB CACR: ECCEN Mask */ + +#define SCB_CACR_ECCDIS_Pos 1U /*!< SCB CACR: ECCDIS Position */ +#define SCB_CACR_ECCDIS_Msk (1UL << SCB_CACR_ECCDIS_Pos) /*!< SCB CACR: ECCDIS Mask */ + +#define SCB_CACR_SIWT_Pos 0U /*!< SCB CACR: SIWT Position */ +#define SCB_CACR_SIWT_Msk (1UL /*<< SCB_CACR_SIWT_Pos*/) /*!< SCB CACR: SIWT Mask */ + +/* AHBS Control Register Definitions */ +#define SCB_AHBSCR_INITCOUNT_Pos 11U /*!< SCB AHBSCR: INITCOUNT Position */ +#define SCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBSCR_INITCOUNT_Pos) /*!< SCB AHBSCR: INITCOUNT Mask */ + +#define SCB_AHBSCR_TPRI_Pos 2U /*!< SCB AHBSCR: TPRI Position */ +#define SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBSCR_TPRI_Pos) /*!< SCB AHBSCR: TPRI Mask */ + +#define SCB_AHBSCR_CTL_Pos 0U /*!< SCB AHBSCR: CTL Position*/ +#define SCB_AHBSCR_CTL_Msk (3UL /*<< SCB_AHBSCR_CTL_Pos*/) /*!< SCB AHBSCR: CTL Mask */ + +/* Auxiliary Bus Fault Status Register Definitions */ +#define SCB_ABFSR_AXIMTYPE_Pos 8U /*!< SCB ABFSR: AXIMTYPE Position*/ +#define SCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos) /*!< SCB ABFSR: AXIMTYPE Mask */ + +#define SCB_ABFSR_EPPB_Pos 4U /*!< SCB ABFSR: EPPB Position*/ +#define SCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos) /*!< SCB ABFSR: EPPB Mask */ + +#define SCB_ABFSR_AXIM_Pos 3U /*!< SCB ABFSR: AXIM Position*/ +#define SCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos) /*!< SCB ABFSR: AXIM Mask */ + +#define SCB_ABFSR_AHBP_Pos 2U /*!< SCB ABFSR: AHBP Position*/ +#define SCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos) /*!< SCB ABFSR: AHBP Mask */ + +#define SCB_ABFSR_DTCM_Pos 1U /*!< SCB ABFSR: DTCM Position*/ +#define SCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos) /*!< SCB ABFSR: DTCM Mask */ + +#define SCB_ABFSR_ITCM_Pos 0U /*!< SCB ABFSR: ITCM Position*/ +#define SCB_ABFSR_ITCM_Msk (1UL /*<< SCB_ABFSR_ITCM_Pos*/) /*!< SCB ABFSR: ITCM Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_DISDYNADD_Pos 26U /*!< ACTLR: DISDYNADD Position */ +#define SCnSCB_ACTLR_DISDYNADD_Msk (1UL << SCnSCB_ACTLR_DISDYNADD_Pos) /*!< ACTLR: DISDYNADD Mask */ + +#define SCnSCB_ACTLR_DISISSCH1_Pos 21U /*!< ACTLR: DISISSCH1 Position */ +#define SCnSCB_ACTLR_DISISSCH1_Msk (0x1FUL << SCnSCB_ACTLR_DISISSCH1_Pos) /*!< ACTLR: DISISSCH1 Mask */ + +#define SCnSCB_ACTLR_DISDI_Pos 16U /*!< ACTLR: DISDI Position */ +#define SCnSCB_ACTLR_DISDI_Msk (0x1FUL << SCnSCB_ACTLR_DISDI_Pos) /*!< ACTLR: DISDI Mask */ + +#define SCnSCB_ACTLR_DISCRITAXIRUR_Pos 15U /*!< ACTLR: DISCRITAXIRUR Position */ +#define SCnSCB_ACTLR_DISCRITAXIRUR_Msk (1UL << SCnSCB_ACTLR_DISCRITAXIRUR_Pos) /*!< ACTLR: DISCRITAXIRUR Mask */ + +#define SCnSCB_ACTLR_DISBTACALLOC_Pos 14U /*!< ACTLR: DISBTACALLOC Position */ +#define SCnSCB_ACTLR_DISBTACALLOC_Msk (1UL << SCnSCB_ACTLR_DISBTACALLOC_Pos) /*!< ACTLR: DISBTACALLOC Mask */ + +#define SCnSCB_ACTLR_DISBTACREAD_Pos 13U /*!< ACTLR: DISBTACREAD Position */ +#define SCnSCB_ACTLR_DISBTACREAD_Msk (1UL << SCnSCB_ACTLR_DISBTACREAD_Pos) /*!< ACTLR: DISBTACREAD Mask */ + +#define SCnSCB_ACTLR_DISITMATBFLUSH_Pos 12U /*!< ACTLR: DISITMATBFLUSH Position */ +#define SCnSCB_ACTLR_DISITMATBFLUSH_Msk (1UL << SCnSCB_ACTLR_DISITMATBFLUSH_Pos) /*!< ACTLR: DISITMATBFLUSH Mask */ + +#define SCnSCB_ACTLR_DISRAMODE_Pos 11U /*!< ACTLR: DISRAMODE Position */ +#define SCnSCB_ACTLR_DISRAMODE_Msk (1UL << SCnSCB_ACTLR_DISRAMODE_Pos) /*!< ACTLR: DISRAMODE Mask */ + +#define SCnSCB_ACTLR_FPEXCODIS_Pos 10U /*!< ACTLR: FPEXCODIS Position */ +#define SCnSCB_ACTLR_FPEXCODIS_Msk (1UL << SCnSCB_ACTLR_FPEXCODIS_Pos) /*!< ACTLR: FPEXCODIS Mask */ + +#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ +#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED3[981U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( W) Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x1UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x1UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY2_Pos 0U /*!< TPI ITATBCTR2: ATREADY2 Position */ +#define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/) /*!< TPI ITATBCTR2: ATREADY2 Mask */ + +#define TPI_ITATBCTR2_ATREADY1_Pos 0U /*!< TPI ITATBCTR2: ATREADY1 Position */ +#define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/) /*!< TPI ITATBCTR2: ATREADY1 Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x1UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x1UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY2_Pos 0U /*!< TPI ITATBCTR0: ATREADY2 Position */ +#define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/) /*!< TPI ITATBCTR0: ATREADY2 Mask */ + +#define TPI_ITATBCTR0_ATREADY1_Pos 0U /*!< TPI ITATBCTR0: ATREADY1 Position */ +#define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/) /*!< TPI ITATBCTR0: ATREADY1 Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif /* defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and FP Feature Register 2 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and FP Feature Register 0 Definitions */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and FP Feature Register 1 Definitions */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/* Media and FP Feature Register 2 Definitions */ + +#define FPU_MVFR2_VFP_Misc_Pos 4U /*!< MVFR2: VFP Misc bits Position */ +#define FPU_MVFR2_VFP_Misc_Msk (0xFUL << FPU_MVFR2_VFP_Misc_Pos) /*!< MVFR2: VFP Misc bits Mask */ + +/*@} end of group CMSIS_FPU */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +#define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ +#define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ +#define EXC_RETURN_HANDLER_FPU (0xFFFFFFE1UL) /* return to Handler mode, uses MSP after return, restore floating-point state */ +#define EXC_RETURN_THREAD_MSP_FPU (0xFFFFFFE9UL) /* return to Thread mode, uses MSP after return, restore floating-point state */ +#define EXC_RETURN_THREAD_PSP_FPU (0xFFFFFFEDUL) /* return to Thread mode, uses PSP after return, restore floating-point state */ + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + __DSB(); +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv7.h" + +#endif + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = SCB->MVFR0; + if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U) + { + return 2U; /* Double + Single precision FPU */ + } + else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + +/*@} end of CMSIS_Core_FpuFunctions */ + + +/* ########################## Cache functions #################################### */ + +#if ((defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)) || \ + (defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U))) +#include "cachel1_armv7.h" +#endif + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM7_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/CMSIS/Core/Include/core_cm85.h b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/CMSIS/Core/Include/core_cm85.h new file mode 100644 index 0000000000..6046311189 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/CMSIS/Core/Include/core_cm85.h @@ -0,0 +1,4672 @@ +/**************************************************************************//** + * @file core_cm85.h + * @brief CMSIS Cortex-M85 Core Peripheral Access Layer Header File + * @version V1.0.4 + * @date 21. April 2022 + ******************************************************************************/ +/* + * Copyright (c) 2022 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#elif defined ( __GNUC__ ) + #pragma GCC diagnostic ignored "-Wpedantic" /* disable pedantic warning due to unnamed structs/unions */ +#endif + +#ifndef __CORE_CM85_H_GENERIC +#define __CORE_CM85_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M85 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM85 definitions */ + +#define __CORTEX_M (85U) /*!< Cortex-M Core */ + +#if defined ( __CC_ARM ) + #error Legacy Arm Compiler does not support Armv8.1-M target architecture. +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM85_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM85_H_DEPENDANT +#define __CORE_CM85_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM85_REV + #define __CM85_REV 0x0001U + #warning "__CM85_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #if __FPU_PRESENT != 0U + #ifndef __FPU_DP + #define __FPU_DP 0U + #warning "__FPU_DP not defined in device header file; using default!" + #endif + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __ICACHE_PRESENT + #define __ICACHE_PRESENT 0U + #warning "__ICACHE_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DCACHE_PRESENT + #define __DCACHE_PRESENT 0U + #warning "__DCACHE_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 1U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __PMU_PRESENT + #define __PMU_PRESENT 0U + #warning "__PMU_PRESENT not defined in device header file; using default!" + #endif + + #if __PMU_PRESENT != 0U + #ifndef __PMU_NUM_EVENTCNT + #define __PMU_NUM_EVENTCNT 8U + #warning "__PMU_NUM_EVENTCNT not defined in device header file; using default!" + #elif (__PMU_NUM_EVENTCNT > 8 || __PMU_NUM_EVENTCNT < 2) + #error "__PMU_NUM_EVENTCNT is out of range in device header file!" */ + #endif + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DSP_PRESENT + #define __DSP_PRESENT 0U + #warning "__DSP_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M85 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core EWIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core PMU Register + - Core MPU Register + - Core SAU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:1; /*!< bit: 20 Reserved */ + uint32_t B:1; /*!< bit: 21 BTI active (read 0) */ + uint32_t _reserved2:2; /*!< bit: 22..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ +#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_B_Pos 21U /*!< xPSR: B Position */ +#define xPSR_B_Msk (1UL << xPSR_B_Pos) /*!< xPSR: B Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */ + uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */ + uint32_t BTI_EN:1; /*!< bit: 4 Privileged branch target identification enable */ + uint32_t UBTI_EN:1; /*!< bit: 5 Unprivileged branch target identification enable */ + uint32_t PAC_EN:1; /*!< bit: 6 Privileged pointer authentication enable */ + uint32_t UPAC_EN:1; /*!< bit: 7 Unprivileged pointer authentication enable */ + uint32_t _reserved1:24; /*!< bit: 8..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_UPAC_EN_Pos 7U /*!< CONTROL: UPAC_EN Position */ +#define CONTROL_UPAC_EN_Msk (1UL << CONTROL_UPAC_EN_Pos) /*!< CONTROL: UPAC_EN Mask */ + +#define CONTROL_PAC_EN_Pos 6U /*!< CONTROL: PAC_EN Position */ +#define CONTROL_PAC_EN_Msk (1UL << CONTROL_PAC_EN_Pos) /*!< CONTROL: PAC_EN Mask */ + +#define CONTROL_UBTI_EN_Pos 5U /*!< CONTROL: UBTI_EN Position */ +#define CONTROL_UBTI_EN_Msk (1UL << CONTROL_UBTI_EN_Pos) /*!< CONTROL: UBTI_EN Mask */ + +#define CONTROL_BTI_EN_Pos 4U /*!< CONTROL: BTI_EN Position */ +#define CONTROL_BTI_EN_Msk (1UL << CONTROL_BTI_EN_Pos) /*!< CONTROL: BTI_EN Mask */ + +#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */ +#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */ + +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED6[580U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ + __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ + __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ + __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */ + uint32_t RESERVED7[21U]; + __IOM uint32_t SFSR; /*!< Offset: 0x0E4 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x0E8 (R/W) Secure Fault Address Register */ + uint32_t RESERVED3[69U]; + __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ + __IOM uint32_t RFSR; /*!< Offset: 0x204 (R/W) RAS Fault Status Register */ + uint32_t RESERVED4[14U]; + __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ + uint32_t RESERVED5[1U]; + __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ + uint32_t RESERVED6[1U]; + __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ + __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ + __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ + __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ + __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ + __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ + __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ + __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ + __OM uint32_t BPIALL; /*!< Offset: 0x278 ( /W) Branch Predictor Invalidate All */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ +#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_IESB_Pos 5U /*!< SCB AIRCR: Implicit ESB Enable Position */ +#define SCB_AIRCR_IESB_Msk (1UL << SCB_AIRCR_IESB_Pos) /*!< SCB AIRCR: Implicit ESB Enable Mask */ + +#define SCB_AIRCR_DIT_Pos 4U /*!< SCB AIRCR: Data Independent Timing Position */ +#define SCB_AIRCR_DIT_Msk (1UL << SCB_AIRCR_DIT_Pos) /*!< SCB AIRCR: Data Independent Timing Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_TRD_Pos 20U /*!< SCB CCR: TRD Position */ +#define SCB_CCR_TRD_Msk (1UL << SCB_CCR_TRD_Pos) /*!< SCB CCR: TRD Mask */ + +#define SCB_CCR_LOB_Pos 19U /*!< SCB CCR: LOB Position */ +#define SCB_CCR_LOB_Msk (1UL << SCB_CCR_LOB_Pos) /*!< SCB CCR: LOB Mask */ + +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */ +#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */ +#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */ + +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */ +#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_CFSR_MEMFAULTSR_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */ +#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_PMU_Pos 5U /*!< SCB DFSR: PMU Position */ +#define SCB_DFSR_PMU_Msk (1UL << SCB_DFSR_PMU_Pos) /*!< SCB DFSR: PMU Mask */ + +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/* SCB Non-Secure Access Control Register Definitions */ +#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */ +#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */ + +#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */ +#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */ + +#define SCB_NSACR_CP7_Pos 7U /*!< SCB NSACR: CP7 Position */ +#define SCB_NSACR_CP7_Msk (1UL << SCB_NSACR_CP7_Pos) /*!< SCB NSACR: CP7 Mask */ + +#define SCB_NSACR_CP6_Pos 6U /*!< SCB NSACR: CP6 Position */ +#define SCB_NSACR_CP6_Msk (1UL << SCB_NSACR_CP6_Pos) /*!< SCB NSACR: CP6 Mask */ + +#define SCB_NSACR_CP5_Pos 5U /*!< SCB NSACR: CP5 Position */ +#define SCB_NSACR_CP5_Msk (1UL << SCB_NSACR_CP5_Pos) /*!< SCB NSACR: CP5 Mask */ + +#define SCB_NSACR_CP4_Pos 4U /*!< SCB NSACR: CP4 Position */ +#define SCB_NSACR_CP4_Msk (1UL << SCB_NSACR_CP4_Pos) /*!< SCB NSACR: CP4 Mask */ + +#define SCB_NSACR_CP3_Pos 3U /*!< SCB NSACR: CP3 Position */ +#define SCB_NSACR_CP3_Msk (1UL << SCB_NSACR_CP3_Pos) /*!< SCB NSACR: CP3 Mask */ + +#define SCB_NSACR_CP2_Pos 2U /*!< SCB NSACR: CP2 Position */ +#define SCB_NSACR_CP2_Msk (1UL << SCB_NSACR_CP2_Pos) /*!< SCB NSACR: CP2 Mask */ + +#define SCB_NSACR_CP1_Pos 1U /*!< SCB NSACR: CP1 Position */ +#define SCB_NSACR_CP1_Msk (1UL << SCB_NSACR_CP1_Pos) /*!< SCB NSACR: CP1 Mask */ + +#define SCB_NSACR_CP0_Pos 0U /*!< SCB NSACR: CP0 Position */ +#define SCB_NSACR_CP0_Msk (1UL /*<< SCB_NSACR_CP0_Pos*/) /*!< SCB NSACR: CP0 Mask */ + +/* SCB Debug Feature Register 0 Definitions */ +#define SCB_ID_DFR_UDE_Pos 28U /*!< SCB ID_DFR: UDE Position */ +#define SCB_ID_DFR_UDE_Msk (0xFUL << SCB_ID_DFR_UDE_Pos) /*!< SCB ID_DFR: UDE Mask */ + +#define SCB_ID_DFR_MProfDbg_Pos 20U /*!< SCB ID_DFR: MProfDbg Position */ +#define SCB_ID_DFR_MProfDbg_Msk (0xFUL << SCB_ID_DFR_MProfDbg_Pos) /*!< SCB ID_DFR: MProfDbg Mask */ + +/* SCB Cache Level ID Register Definitions */ +#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ +#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ + +#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ +#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ + +/* SCB Cache Type Register Definitions */ +#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ +#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ + +#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ +#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ + +#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ +#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ + +#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ +#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ + +#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ +#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ + +/* SCB Cache Size ID Register Definitions */ +#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ +#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ + +#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ +#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ + +#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ +#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ + +#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ +#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ + +#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ +#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ + +#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ +#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ + +#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ +#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ + +/* SCB Cache Size Selection Register Definitions */ +#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ +#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ + +#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ +#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ + +/* SCB Software Triggered Interrupt Register Definitions */ +#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ +#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ + +/* SCB RAS Fault Status Register Definitions */ +#define SCB_RFSR_V_Pos 31U /*!< SCB RFSR: V Position */ +#define SCB_RFSR_V_Msk (1UL << SCB_RFSR_V_Pos) /*!< SCB RFSR: V Mask */ + +#define SCB_RFSR_IS_Pos 16U /*!< SCB RFSR: IS Position */ +#define SCB_RFSR_IS_Msk (0x7FFFUL << SCB_RFSR_IS_Pos) /*!< SCB RFSR: IS Mask */ + +#define SCB_RFSR_UET_Pos 0U /*!< SCB RFSR: UET Position */ +#define SCB_RFSR_UET_Msk (3UL /*<< SCB_RFSR_UET_Pos*/) /*!< SCB RFSR: UET Mask */ + +/* SCB D-Cache Invalidate by Set-way Register Definitions */ +#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ +#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ + +#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ +#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ + +/* SCB D-Cache Clean by Set-way Register Definitions */ +#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ +#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ + +#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ +#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ + +/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ +#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ +#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ + +#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ +#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ICB Implementation Control Block register (ICB) + \brief Type definitions for the Implementation Control Block Register + @{ + */ + +/** + \brief Structure type to access the Implementation Control Block (ICB). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ + __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */ +} ICB_Type; + +/* Auxiliary Control Register Definitions */ +#define ICB_ACTLR_DISCRITAXIRUW_Pos 27U /*!< ACTLR: DISCRITAXIRUW Position */ +#define ICB_ACTLR_DISCRITAXIRUW_Msk (1UL << ICB_ACTLR_DISCRITAXIRUW_Pos) /*!< ACTLR: DISCRITAXIRUW Mask */ + +#define ICB_ACTLR_DISCRITAXIRUR_Pos 15U /*!< ACTLR: DISCRITAXIRUR Position */ +#define ICB_ACTLR_DISCRITAXIRUR_Msk (1UL << ICB_ACTLR_DISCRITAXIRUR_Pos) /*!< ACTLR: DISCRITAXIRUR Mask */ + +#define ICB_ACTLR_EVENTBUSEN_Pos 14U /*!< ACTLR: EVENTBUSEN Position */ +#define ICB_ACTLR_EVENTBUSEN_Msk (1UL << ICB_ACTLR_EVENTBUSEN_Pos) /*!< ACTLR: EVENTBUSEN Mask */ + +#define ICB_ACTLR_EVENTBUSEN_S_Pos 13U /*!< ACTLR: EVENTBUSEN_S Position */ +#define ICB_ACTLR_EVENTBUSEN_S_Msk (1UL << ICB_ACTLR_EVENTBUSEN_S_Pos) /*!< ACTLR: EVENTBUSEN_S Mask */ + +#define ICB_ACTLR_DISITMATBFLUSH_Pos 12U /*!< ACTLR: DISITMATBFLUSH Position */ +#define ICB_ACTLR_DISITMATBFLUSH_Msk (1UL << ICB_ACTLR_DISITMATBFLUSH_Pos) /*!< ACTLR: DISITMATBFLUSH Mask */ + +#define ICB_ACTLR_DISNWAMODE_Pos 11U /*!< ACTLR: DISNWAMODE Position */ +#define ICB_ACTLR_DISNWAMODE_Msk (1UL << ICB_ACTLR_DISNWAMODE_Pos) /*!< ACTLR: DISNWAMODE Mask */ + +#define ICB_ACTLR_FPEXCODIS_Pos 10U /*!< ACTLR: FPEXCODIS Position */ +#define ICB_ACTLR_FPEXCODIS_Msk (1UL << ICB_ACTLR_FPEXCODIS_Pos) /*!< ACTLR: FPEXCODIS Mask */ + +/* Interrupt Controller Type Register Definitions */ +#define ICB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define ICB_ICTR_INTLINESNUM_Msk (0xFUL /*<< ICB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_ICB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */ + uint32_t RESERVED6[3U]; + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) ITM Device Type Register */ + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Stimulus Port Register Definitions */ +#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */ +#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */ + +#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */ +#define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */ + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */ +#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */ + +#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */ +#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED14[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED15[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED16[1U]; + __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ + uint32_t RESERVED17[1U]; + __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ + uint32_t RESERVED18[1U]; + __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ + uint32_t RESERVED19[1U]; + __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ + uint32_t RESERVED20[1U]; + __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ + uint32_t RESERVED21[1U]; + __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ + uint32_t RESERVED22[1U]; + __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ + uint32_t RESERVED23[1U]; + __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ + uint32_t RESERVED24[1U]; + __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ + uint32_t RESERVED25[1U]; + __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ + uint32_t RESERVED26[1U]; + __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ + uint32_t RESERVED27[1U]; + __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ + uint32_t RESERVED28[1U]; + __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ + uint32_t RESERVED29[1U]; + __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ + uint32_t RESERVED30[1U]; + __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ + uint32_t RESERVED31[1U]; + __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ + uint32_t RESERVED32[934U]; + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ + uint32_t RESERVED33[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */ +#define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup MemSysCtl_Type Memory System Control Registers (IMPLEMENTATION DEFINED) + \brief Type definitions for the Memory System Control Registers (MEMSYSCTL) + @{ + */ + +/** + \brief Structure type to access the Memory System Control Registers (MEMSYSCTL). + */ +typedef struct +{ + __IOM uint32_t MSCR; /*!< Offset: 0x000 (R/W) Memory System Control Register */ + __IOM uint32_t PFCR; /*!< Offset: 0x004 (R/W) Prefetcher Control Register */ + uint32_t RESERVED1[2U]; + __IOM uint32_t ITCMCR; /*!< Offset: 0x010 (R/W) ITCM Control Register */ + __IOM uint32_t DTCMCR; /*!< Offset: 0x014 (R/W) DTCM Control Register */ + __IOM uint32_t PAHBCR; /*!< Offset: 0x018 (R/W) P-AHB Control Register */ + uint32_t RESERVED2[313U]; + __IOM uint32_t ITGU_CTRL; /*!< Offset: 0x500 (R/W) ITGU Control Register */ + __IOM uint32_t ITGU_CFG; /*!< Offset: 0x504 (R/W) ITGU Configuration Register */ + uint32_t RESERVED3[2U]; + __IOM uint32_t ITGU_LUT[16U]; /*!< Offset: 0x510 (R/W) ITGU Look Up Table Register */ + uint32_t RESERVED4[44U]; + __IOM uint32_t DTGU_CTRL; /*!< Offset: 0x600 (R/W) DTGU Control Registers */ + __IOM uint32_t DTGU_CFG; /*!< Offset: 0x604 (R/W) DTGU Configuration Register */ + uint32_t RESERVED5[2U]; + __IOM uint32_t DTGU_LUT[16U]; /*!< Offset: 0x610 (R/W) DTGU Look Up Table Register */ +} MemSysCtl_Type; + +/* MEMSYSCTL Memory System Control Register (MSCR) Register Definitions */ +#define MEMSYSCTL_MSCR_CPWRDN_Pos 17U /*!< MEMSYSCTL MSCR: CPWRDN Position */ +#define MEMSYSCTL_MSCR_CPWRDN_Msk (0x1UL << MEMSYSCTL_MSCR_CPWRDN_Pos) /*!< MEMSYSCTL MSCR: CPWRDN Mask */ + +#define MEMSYSCTL_MSCR_DCCLEAN_Pos 16U /*!< MEMSYSCTL MSCR: DCCLEAN Position */ +#define MEMSYSCTL_MSCR_DCCLEAN_Msk (0x1UL << MEMSYSCTL_MSCR_DCCLEAN_Pos) /*!< MEMSYSCTL MSCR: DCCLEAN Mask */ + +#define MEMSYSCTL_MSCR_ICACTIVE_Pos 13U /*!< MEMSYSCTL MSCR: ICACTIVE Position */ +#define MEMSYSCTL_MSCR_ICACTIVE_Msk (0x1UL << MEMSYSCTL_MSCR_ICACTIVE_Pos) /*!< MEMSYSCTL MSCR: ICACTIVE Mask */ + +#define MEMSYSCTL_MSCR_DCACTIVE_Pos 12U /*!< MEMSYSCTL MSCR: DCACTIVE Position */ +#define MEMSYSCTL_MSCR_DCACTIVE_Msk (0x1UL << MEMSYSCTL_MSCR_DCACTIVE_Pos) /*!< MEMSYSCTL MSCR: DCACTIVE Mask */ + +#define MEMSYSCTL_MSCR_EVECCFAULT_Pos 3U /*!< MEMSYSCTL MSCR: EVECCFAULT Position */ +#define MEMSYSCTL_MSCR_EVECCFAULT_Msk (0x1UL << MEMSYSCTL_MSCR_EVECCFAULT_Pos) /*!< MEMSYSCTL MSCR: EVECCFAULT Mask */ + +#define MEMSYSCTL_MSCR_FORCEWT_Pos 2U /*!< MEMSYSCTL MSCR: FORCEWT Position */ +#define MEMSYSCTL_MSCR_FORCEWT_Msk (0x1UL << MEMSYSCTL_MSCR_FORCEWT_Pos) /*!< MEMSYSCTL MSCR: FORCEWT Mask */ + +#define MEMSYSCTL_MSCR_ECCEN_Pos 1U /*!< MEMSYSCTL MSCR: ECCEN Position */ +#define MEMSYSCTL_MSCR_ECCEN_Msk (0x1UL << MEMSYSCTL_MSCR_ECCEN_Pos) /*!< MEMSYSCTL MSCR: ECCEN Mask */ + +/* MEMSYSCTL Prefetcher Control Register (PFCR) Register Definitions */ +#define MEMSYSCTL_PFCR_DIS_NLP_Pos 7U /*!< MEMSYSCTL PFCR: DIS_NLP Position */ +#define MEMSYSCTL_PFCR_DIS_NLP_Msk (0x1UL << MEMSYSCTL_PFCR_DIS_NLP_Pos) /*!< MEMSYSCTL PFCR: DIS_NLP Mask */ + +#define MEMSYSCTL_PFCR_ENABLE_Pos 0U /*!< MEMSYSCTL PFCR: ENABLE Position */ +#define MEMSYSCTL_PFCR_ENABLE_Msk (0x1UL /*<< MEMSYSCTL_PFCR_ENABLE_Pos*/) /*!< MEMSYSCTL PFCR: ENABLE Mask */ + +/* MEMSYSCTL ITCM Control Register (ITCMCR) Register Definitions */ +#define MEMSYSCTL_ITCMCR_SZ_Pos 3U /*!< MEMSYSCTL ITCMCR: SZ Position */ +#define MEMSYSCTL_ITCMCR_SZ_Msk (0xFUL << MEMSYSCTL_ITCMCR_SZ_Pos) /*!< MEMSYSCTL ITCMCR: SZ Mask */ + +#define MEMSYSCTL_ITCMCR_EN_Pos 0U /*!< MEMSYSCTL ITCMCR: EN Position */ +#define MEMSYSCTL_ITCMCR_EN_Msk (0x1UL /*<< MEMSYSCTL_ITCMCR_EN_Pos*/) /*!< MEMSYSCTL ITCMCR: EN Mask */ + +/* MEMSYSCTL DTCM Control Register (DTCMCR) Register Definitions */ +#define MEMSYSCTL_DTCMCR_SZ_Pos 3U /*!< MEMSYSCTL DTCMCR: SZ Position */ +#define MEMSYSCTL_DTCMCR_SZ_Msk (0xFUL << MEMSYSCTL_DTCMCR_SZ_Pos) /*!< MEMSYSCTL DTCMCR: SZ Mask */ + +#define MEMSYSCTL_DTCMCR_EN_Pos 0U /*!< MEMSYSCTL DTCMCR: EN Position */ +#define MEMSYSCTL_DTCMCR_EN_Msk (0x1UL /*<< MEMSYSCTL_DTCMCR_EN_Pos*/) /*!< MEMSYSCTL DTCMCR: EN Mask */ + +/* MEMSYSCTL P-AHB Control Register (PAHBCR) Register Definitions */ +#define MEMSYSCTL_PAHBCR_SZ_Pos 1U /*!< MEMSYSCTL PAHBCR: SZ Position */ +#define MEMSYSCTL_PAHBCR_SZ_Msk (0x7UL << MEMSYSCTL_PAHBCR_SZ_Pos) /*!< MEMSYSCTL PAHBCR: SZ Mask */ + +#define MEMSYSCTL_PAHBCR_EN_Pos 0U /*!< MEMSYSCTL PAHBCR: EN Position */ +#define MEMSYSCTL_PAHBCR_EN_Msk (0x1UL /*<< MEMSYSCTL_PAHBCR_EN_Pos*/) /*!< MEMSYSCTL PAHBCR: EN Mask */ + +/* MEMSYSCTL ITGU Control Register (ITGU_CTRL) Register Definitions */ +#define MEMSYSCTL_ITGU_CTRL_DEREN_Pos 1U /*!< MEMSYSCTL ITGU_CTRL: DEREN Position */ +#define MEMSYSCTL_ITGU_CTRL_DEREN_Msk (0x1UL << MEMSYSCTL_ITGU_CTRL_DEREN_Pos) /*!< MEMSYSCTL ITGU_CTRL: DEREN Mask */ + +#define MEMSYSCTL_ITGU_CTRL_DBFEN_Pos 0U /*!< MEMSYSCTL ITGU_CTRL: DBFEN Position */ +#define MEMSYSCTL_ITGU_CTRL_DBFEN_Msk (0x1UL /*<< MEMSYSCTL_ITGU_CTRL_DBFEN_Pos*/) /*!< MEMSYSCTL ITGU_CTRL: DBFEN Mask */ + +/* MEMSYSCTL ITGU Configuration Register (ITGU_CFG) Register Definitions */ +#define MEMSYSCTL_ITGU_CFG_PRESENT_Pos 31U /*!< MEMSYSCTL ITGU_CFG: PRESENT Position */ +#define MEMSYSCTL_ITGU_CFG_PRESENT_Msk (0x1UL << MEMSYSCTL_ITGU_CFG_PRESENT_Pos) /*!< MEMSYSCTL ITGU_CFG: PRESENT Mask */ + +#define MEMSYSCTL_ITGU_CFG_NUMBLKS_Pos 8U /*!< MEMSYSCTL ITGU_CFG: NUMBLKS Position */ +#define MEMSYSCTL_ITGU_CFG_NUMBLKS_Msk (0xFUL << MEMSYSCTL_ITGU_CFG_NUMBLKS_Pos) /*!< MEMSYSCTL ITGU_CFG: NUMBLKS Mask */ + +#define MEMSYSCTL_ITGU_CFG_BLKSZ_Pos 0U /*!< MEMSYSCTL ITGU_CFG: BLKSZ Position */ +#define MEMSYSCTL_ITGU_CFG_BLKSZ_Msk (0xFUL /*<< MEMSYSCTL_ITGU_CFG_BLKSZ_Pos*/) /*!< MEMSYSCTL ITGU_CFG: BLKSZ Mask */ + +/* MEMSYSCTL DTGU Control Registers (DTGU_CTRL) Register Definitions */ +#define MEMSYSCTL_DTGU_CTRL_DEREN_Pos 1U /*!< MEMSYSCTL DTGU_CTRL: DEREN Position */ +#define MEMSYSCTL_DTGU_CTRL_DEREN_Msk (0x1UL << MEMSYSCTL_DTGU_CTRL_DEREN_Pos) /*!< MEMSYSCTL DTGU_CTRL: DEREN Mask */ + +#define MEMSYSCTL_DTGU_CTRL_DBFEN_Pos 0U /*!< MEMSYSCTL DTGU_CTRL: DBFEN Position */ +#define MEMSYSCTL_DTGU_CTRL_DBFEN_Msk (0x1UL /*<< MEMSYSCTL_DTGU_CTRL_DBFEN_Pos*/) /*!< MEMSYSCTL DTGU_CTRL: DBFEN Mask */ + +/* MEMSYSCTL DTGU Configuration Register (DTGU_CFG) Register Definitions */ +#define MEMSYSCTL_DTGU_CFG_PRESENT_Pos 31U /*!< MEMSYSCTL DTGU_CFG: PRESENT Position */ +#define MEMSYSCTL_DTGU_CFG_PRESENT_Msk (0x1UL << MEMSYSCTL_DTGU_CFG_PRESENT_Pos) /*!< MEMSYSCTL DTGU_CFG: PRESENT Mask */ + +#define MEMSYSCTL_DTGU_CFG_NUMBLKS_Pos 8U /*!< MEMSYSCTL DTGU_CFG: NUMBLKS Position */ +#define MEMSYSCTL_DTGU_CFG_NUMBLKS_Msk (0xFUL << MEMSYSCTL_DTGU_CFG_NUMBLKS_Pos) /*!< MEMSYSCTL DTGU_CFG: NUMBLKS Mask */ + +#define MEMSYSCTL_DTGU_CFG_BLKSZ_Pos 0U /*!< MEMSYSCTL DTGU_CFG: BLKSZ Position */ +#define MEMSYSCTL_DTGU_CFG_BLKSZ_Msk (0xFUL /*<< MEMSYSCTL_DTGU_CFG_BLKSZ_Pos*/) /*!< MEMSYSCTL DTGU_CFG: BLKSZ Mask */ + + +/*@}*/ /* end of group MemSysCtl_Type */ + + +/** + \ingroup CMSIS_core_register + \defgroup PwrModCtl_Type Power Mode Control Registers + \brief Type definitions for the Power Mode Control Registers (PWRMODCTL) + @{ + */ + +/** + \brief Structure type to access the Power Mode Control Registers (PWRMODCTL). + */ +typedef struct +{ + __IOM uint32_t CPDLPSTATE; /*!< Offset: 0x000 (R/W) Core Power Domain Low Power State Register */ + __IOM uint32_t DPDLPSTATE; /*!< Offset: 0x004 (R/W) Debug Power Domain Low Power State Register */ +} PwrModCtl_Type; + +/* PWRMODCTL Core Power Domain Low Power State (CPDLPSTATE) Register Definitions */ +#define PWRMODCTL_CPDLPSTATE_RLPSTATE_Pos 8U /*!< PWRMODCTL CPDLPSTATE: RLPSTATE Position */ +#define PWRMODCTL_CPDLPSTATE_RLPSTATE_Msk (0x3UL << PWRMODCTL_CPDLPSTATE_RLPSTATE_Pos) /*!< PWRMODCTL CPDLPSTATE: RLPSTATE Mask */ + +#define PWRMODCTL_CPDLPSTATE_ELPSTATE_Pos 4U /*!< PWRMODCTL CPDLPSTATE: ELPSTATE Position */ +#define PWRMODCTL_CPDLPSTATE_ELPSTATE_Msk (0x3UL << PWRMODCTL_CPDLPSTATE_ELPSTATE_Pos) /*!< PWRMODCTL CPDLPSTATE: ELPSTATE Mask */ + +#define PWRMODCTL_CPDLPSTATE_CLPSTATE_Pos 0U /*!< PWRMODCTL CPDLPSTATE: CLPSTATE Position */ +#define PWRMODCTL_CPDLPSTATE_CLPSTATE_Msk (0x3UL /*<< PWRMODCTL_CPDLPSTATE_CLPSTATE_Pos*/) /*!< PWRMODCTL CPDLPSTATE: CLPSTATE Mask */ + +/* PWRMODCTL Debug Power Domain Low Power State (DPDLPSTATE) Register Definitions */ +#define PWRMODCTL_DPDLPSTATE_DLPSTATE_Pos 0U /*!< PWRMODCTL DPDLPSTATE: DLPSTATE Position */ +#define PWRMODCTL_DPDLPSTATE_DLPSTATE_Msk (0x3UL /*<< PWRMODCTL_DPDLPSTATE_DLPSTATE_Pos*/) /*!< PWRMODCTL DPDLPSTATE: DLPSTATE Mask */ + +/*@}*/ /* end of group PwrModCtl_Type */ + + +/** + \ingroup CMSIS_core_register + \defgroup EWIC_Type External Wakeup Interrupt Controller Registers + \brief Type definitions for the External Wakeup Interrupt Controller Registers (EWIC) + @{ + */ + +/** + \brief Structure type to access the External Wakeup Interrupt Controller Registers (EWIC). + */ +typedef struct +{ + __OM uint32_t EVENTSPR; /*!< Offset: 0x000 ( /W) Event Set Pending Register */ + uint32_t RESERVED0[31U]; + __IM uint32_t EVENTMASKA; /*!< Offset: 0x080 (R/W) Event Mask A Register */ + __IM uint32_t EVENTMASK[15]; /*!< Offset: 0x084 (R/W) Event Mask Register */ +} EWIC_Type; + +/* EWIC External Wakeup Interrupt Controller (EVENTSPR) Register Definitions */ +#define EWIC_EVENTSPR_EDBGREQ_Pos 2U /*!< EWIC EVENTSPR: EDBGREQ Position */ +#define EWIC_EVENTSPR_EDBGREQ_Msk (0x1UL << EWIC_EVENTSPR_EDBGREQ_Pos) /*!< EWIC EVENTSPR: EDBGREQ Mask */ + +#define EWIC_EVENTSPR_NMI_Pos 1U /*!< EWIC EVENTSPR: NMI Position */ +#define EWIC_EVENTSPR_NMI_Msk (0x1UL << EWIC_EVENTSPR_NMI_Pos) /*!< EWIC EVENTSPR: NMI Mask */ + +#define EWIC_EVENTSPR_EVENT_Pos 0U /*!< EWIC EVENTSPR: EVENT Position */ +#define EWIC_EVENTSPR_EVENT_Msk (0x1UL /*<< EWIC_EVENTSPR_EVENT_Pos*/) /*!< EWIC EVENTSPR: EVENT Mask */ + +/* EWIC External Wakeup Interrupt Controller (EVENTMASKA) Register Definitions */ +#define EWIC_EVENTMASKA_EDBGREQ_Pos 2U /*!< EWIC EVENTMASKA: EDBGREQ Position */ +#define EWIC_EVENTMASKA_EDBGREQ_Msk (0x1UL << EWIC_EVENTMASKA_EDBGREQ_Pos) /*!< EWIC EVENTMASKA: EDBGREQ Mask */ + +#define EWIC_EVENTMASKA_NMI_Pos 1U /*!< EWIC EVENTMASKA: NMI Position */ +#define EWIC_EVENTMASKA_NMI_Msk (0x1UL << EWIC_EVENTMASKA_NMI_Pos) /*!< EWIC EVENTMASKA: NMI Mask */ + +#define EWIC_EVENTMASKA_EVENT_Pos 0U /*!< EWIC EVENTMASKA: EVENT Position */ +#define EWIC_EVENTMASKA_EVENT_Msk (0x1UL /*<< EWIC_EVENTMASKA_EVENT_Pos*/) /*!< EWIC EVENTMASKA: EVENT Mask */ + +/* EWIC External Wakeup Interrupt Controller (EVENTMASK) Register Definitions */ +#define EWIC_EVENTMASK_IRQ_Pos 0U /*!< EWIC EVENTMASKA: IRQ Position */ +#define EWIC_EVENTMASK_IRQ_Msk (0xFFFFFFFFUL /*<< EWIC_EVENTMASKA_IRQ_Pos*/) /*!< EWIC EVENTMASKA: IRQ Mask */ + +/*@}*/ /* end of group EWIC_Type */ + + +/** + \ingroup CMSIS_core_register + \defgroup ErrBnk_Type Error Banking Registers (IMPLEMENTATION DEFINED) + \brief Type definitions for the Error Banking Registers (ERRBNK) + @{ + */ + +/** + \brief Structure type to access the Error Banking Registers (ERRBNK). + */ +typedef struct +{ + __IOM uint32_t IEBR0; /*!< Offset: 0x000 (R/W) Instruction Cache Error Bank Register 0 */ + __IOM uint32_t IEBR1; /*!< Offset: 0x004 (R/W) Instruction Cache Error Bank Register 1 */ + uint32_t RESERVED0[2U]; + __IOM uint32_t DEBR0; /*!< Offset: 0x010 (R/W) Data Cache Error Bank Register 0 */ + __IOM uint32_t DEBR1; /*!< Offset: 0x014 (R/W) Data Cache Error Bank Register 1 */ + uint32_t RESERVED1[2U]; + __IOM uint32_t TEBR0; /*!< Offset: 0x020 (R/W) TCM Error Bank Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t TEBR1; /*!< Offset: 0x028 (R/W) TCM Error Bank Register 1 */ +} ErrBnk_Type; + +/* ERRBNK Instruction Cache Error Bank Register 0 (IEBR0) Register Definitions */ +#define ERRBNK_IEBR0_SWDEF_Pos 30U /*!< ERRBNK IEBR0: SWDEF Position */ +#define ERRBNK_IEBR0_SWDEF_Msk (0x3UL << ERRBNK_IEBR0_SWDEF_Pos) /*!< ERRBNK IEBR0: SWDEF Mask */ + +#define ERRBNK_IEBR0_BANK_Pos 16U /*!< ERRBNK IEBR0: BANK Position */ +#define ERRBNK_IEBR0_BANK_Msk (0x1UL << ERRBNK_IEBR0_BANK_Pos) /*!< ERRBNK IEBR0: BANK Mask */ + +#define ERRBNK_IEBR0_LOCATION_Pos 2U /*!< ERRBNK IEBR0: LOCATION Position */ +#define ERRBNK_IEBR0_LOCATION_Msk (0x3FFFUL << ERRBNK_IEBR0_LOCATION_Pos) /*!< ERRBNK IEBR0: LOCATION Mask */ + +#define ERRBNK_IEBR0_LOCKED_Pos 1U /*!< ERRBNK IEBR0: LOCKED Position */ +#define ERRBNK_IEBR0_LOCKED_Msk (0x1UL << ERRBNK_IEBR0_LOCKED_Pos) /*!< ERRBNK IEBR0: LOCKED Mask */ + +#define ERRBNK_IEBR0_VALID_Pos 0U /*!< ERRBNK IEBR0: VALID Position */ +#define ERRBNK_IEBR0_VALID_Msk (0x1UL << /*ERRBNK_IEBR0_VALID_Pos*/) /*!< ERRBNK IEBR0: VALID Mask */ + +/* ERRBNK Instruction Cache Error Bank Register 1 (IEBR1) Register Definitions */ +#define ERRBNK_IEBR1_SWDEF_Pos 30U /*!< ERRBNK IEBR1: SWDEF Position */ +#define ERRBNK_IEBR1_SWDEF_Msk (0x3UL << ERRBNK_IEBR1_SWDEF_Pos) /*!< ERRBNK IEBR1: SWDEF Mask */ + +#define ERRBNK_IEBR1_BANK_Pos 16U /*!< ERRBNK IEBR1: BANK Position */ +#define ERRBNK_IEBR1_BANK_Msk (0x1UL << ERRBNK_IEBR1_BANK_Pos) /*!< ERRBNK IEBR1: BANK Mask */ + +#define ERRBNK_IEBR1_LOCATION_Pos 2U /*!< ERRBNK IEBR1: LOCATION Position */ +#define ERRBNK_IEBR1_LOCATION_Msk (0x3FFFUL << ERRBNK_IEBR1_LOCATION_Pos) /*!< ERRBNK IEBR1: LOCATION Mask */ + +#define ERRBNK_IEBR1_LOCKED_Pos 1U /*!< ERRBNK IEBR1: LOCKED Position */ +#define ERRBNK_IEBR1_LOCKED_Msk (0x1UL << ERRBNK_IEBR1_LOCKED_Pos) /*!< ERRBNK IEBR1: LOCKED Mask */ + +#define ERRBNK_IEBR1_VALID_Pos 0U /*!< ERRBNK IEBR1: VALID Position */ +#define ERRBNK_IEBR1_VALID_Msk (0x1UL << /*ERRBNK_IEBR1_VALID_Pos*/) /*!< ERRBNK IEBR1: VALID Mask */ + +/* ERRBNK Data Cache Error Bank Register 0 (DEBR0) Register Definitions */ +#define ERRBNK_DEBR0_SWDEF_Pos 30U /*!< ERRBNK DEBR0: SWDEF Position */ +#define ERRBNK_DEBR0_SWDEF_Msk (0x3UL << ERRBNK_DEBR0_SWDEF_Pos) /*!< ERRBNK DEBR0: SWDEF Mask */ + +#define ERRBNK_DEBR0_TYPE_Pos 17U /*!< ERRBNK DEBR0: TYPE Position */ +#define ERRBNK_DEBR0_TYPE_Msk (0x1UL << ERRBNK_DEBR0_TYPE_Pos) /*!< ERRBNK DEBR0: TYPE Mask */ + +#define ERRBNK_DEBR0_BANK_Pos 16U /*!< ERRBNK DEBR0: BANK Position */ +#define ERRBNK_DEBR0_BANK_Msk (0x1UL << ERRBNK_DEBR0_BANK_Pos) /*!< ERRBNK DEBR0: BANK Mask */ + +#define ERRBNK_DEBR0_LOCATION_Pos 2U /*!< ERRBNK DEBR0: LOCATION Position */ +#define ERRBNK_DEBR0_LOCATION_Msk (0x3FFFUL << ERRBNK_DEBR0_LOCATION_Pos) /*!< ERRBNK DEBR0: LOCATION Mask */ + +#define ERRBNK_DEBR0_LOCKED_Pos 1U /*!< ERRBNK DEBR0: LOCKED Position */ +#define ERRBNK_DEBR0_LOCKED_Msk (0x1UL << ERRBNK_DEBR0_LOCKED_Pos) /*!< ERRBNK DEBR0: LOCKED Mask */ + +#define ERRBNK_DEBR0_VALID_Pos 0U /*!< ERRBNK DEBR0: VALID Position */ +#define ERRBNK_DEBR0_VALID_Msk (0x1UL << /*ERRBNK_DEBR0_VALID_Pos*/) /*!< ERRBNK DEBR0: VALID Mask */ + +/* ERRBNK Data Cache Error Bank Register 1 (DEBR1) Register Definitions */ +#define ERRBNK_DEBR1_SWDEF_Pos 30U /*!< ERRBNK DEBR1: SWDEF Position */ +#define ERRBNK_DEBR1_SWDEF_Msk (0x3UL << ERRBNK_DEBR1_SWDEF_Pos) /*!< ERRBNK DEBR1: SWDEF Mask */ + +#define ERRBNK_DEBR1_TYPE_Pos 17U /*!< ERRBNK DEBR1: TYPE Position */ +#define ERRBNK_DEBR1_TYPE_Msk (0x1UL << ERRBNK_DEBR1_TYPE_Pos) /*!< ERRBNK DEBR1: TYPE Mask */ + +#define ERRBNK_DEBR1_BANK_Pos 16U /*!< ERRBNK DEBR1: BANK Position */ +#define ERRBNK_DEBR1_BANK_Msk (0x1UL << ERRBNK_DEBR1_BANK_Pos) /*!< ERRBNK DEBR1: BANK Mask */ + +#define ERRBNK_DEBR1_LOCATION_Pos 2U /*!< ERRBNK DEBR1: LOCATION Position */ +#define ERRBNK_DEBR1_LOCATION_Msk (0x3FFFUL << ERRBNK_DEBR1_LOCATION_Pos) /*!< ERRBNK DEBR1: LOCATION Mask */ + +#define ERRBNK_DEBR1_LOCKED_Pos 1U /*!< ERRBNK DEBR1: LOCKED Position */ +#define ERRBNK_DEBR1_LOCKED_Msk (0x1UL << ERRBNK_DEBR1_LOCKED_Pos) /*!< ERRBNK DEBR1: LOCKED Mask */ + +#define ERRBNK_DEBR1_VALID_Pos 0U /*!< ERRBNK DEBR1: VALID Position */ +#define ERRBNK_DEBR1_VALID_Msk (0x1UL << /*ERRBNK_DEBR1_VALID_Pos*/) /*!< ERRBNK DEBR1: VALID Mask */ + +/* ERRBNK TCM Error Bank Register 0 (TEBR0) Register Definitions */ +#define ERRBNK_TEBR0_SWDEF_Pos 30U /*!< ERRBNK TEBR0: SWDEF Position */ +#define ERRBNK_TEBR0_SWDEF_Msk (0x3UL << ERRBNK_TEBR0_SWDEF_Pos) /*!< ERRBNK TEBR0: SWDEF Mask */ + +#define ERRBNK_TEBR0_POISON_Pos 28U /*!< ERRBNK TEBR0: POISON Position */ +#define ERRBNK_TEBR0_POISON_Msk (0x1UL << ERRBNK_TEBR0_POISON_Pos) /*!< ERRBNK TEBR0: POISON Mask */ + +#define ERRBNK_TEBR0_TYPE_Pos 27U /*!< ERRBNK TEBR0: TYPE Position */ +#define ERRBNK_TEBR0_TYPE_Msk (0x1UL << ERRBNK_TEBR0_TYPE_Pos) /*!< ERRBNK TEBR0: TYPE Mask */ + +#define ERRBNK_TEBR0_BANK_Pos 24U /*!< ERRBNK TEBR0: BANK Position */ +#define ERRBNK_TEBR0_BANK_Msk (0x3UL << ERRBNK_TEBR0_BANK_Pos) /*!< ERRBNK TEBR0: BANK Mask */ + +#define ERRBNK_TEBR0_LOCATION_Pos 2U /*!< ERRBNK TEBR0: LOCATION Position */ +#define ERRBNK_TEBR0_LOCATION_Msk (0x3FFFFFUL << ERRBNK_TEBR0_LOCATION_Pos) /*!< ERRBNK TEBR0: LOCATION Mask */ + +#define ERRBNK_TEBR0_LOCKED_Pos 1U /*!< ERRBNK TEBR0: LOCKED Position */ +#define ERRBNK_TEBR0_LOCKED_Msk (0x1UL << ERRBNK_TEBR0_LOCKED_Pos) /*!< ERRBNK TEBR0: LOCKED Mask */ + +#define ERRBNK_TEBR0_VALID_Pos 0U /*!< ERRBNK TEBR0: VALID Position */ +#define ERRBNK_TEBR0_VALID_Msk (0x1UL << /*ERRBNK_TEBR0_VALID_Pos*/) /*!< ERRBNK TEBR0: VALID Mask */ + +/* ERRBNK TCM Error Bank Register 1 (TEBR1) Register Definitions */ +#define ERRBNK_TEBR1_SWDEF_Pos 30U /*!< ERRBNK TEBR1: SWDEF Position */ +#define ERRBNK_TEBR1_SWDEF_Msk (0x3UL << ERRBNK_TEBR1_SWDEF_Pos) /*!< ERRBNK TEBR1: SWDEF Mask */ + +#define ERRBNK_TEBR1_POISON_Pos 28U /*!< ERRBNK TEBR1: POISON Position */ +#define ERRBNK_TEBR1_POISON_Msk (0x1UL << ERRBNK_TEBR1_POISON_Pos) /*!< ERRBNK TEBR1: POISON Mask */ + +#define ERRBNK_TEBR1_TYPE_Pos 27U /*!< ERRBNK TEBR1: TYPE Position */ +#define ERRBNK_TEBR1_TYPE_Msk (0x1UL << ERRBNK_TEBR1_TYPE_Pos) /*!< ERRBNK TEBR1: TYPE Mask */ + +#define ERRBNK_TEBR1_BANK_Pos 24U /*!< ERRBNK TEBR1: BANK Position */ +#define ERRBNK_TEBR1_BANK_Msk (0x3UL << ERRBNK_TEBR1_BANK_Pos) /*!< ERRBNK TEBR1: BANK Mask */ + +#define ERRBNK_TEBR1_LOCATION_Pos 2U /*!< ERRBNK TEBR1: LOCATION Position */ +#define ERRBNK_TEBR1_LOCATION_Msk (0x3FFFFFUL << ERRBNK_TEBR1_LOCATION_Pos) /*!< ERRBNK TEBR1: LOCATION Mask */ + +#define ERRBNK_TEBR1_LOCKED_Pos 1U /*!< ERRBNK TEBR1: LOCKED Position */ +#define ERRBNK_TEBR1_LOCKED_Msk (0x1UL << ERRBNK_TEBR1_LOCKED_Pos) /*!< ERRBNK TEBR1: LOCKED Mask */ + +#define ERRBNK_TEBR1_VALID_Pos 0U /*!< ERRBNK TEBR1: VALID Position */ +#define ERRBNK_TEBR1_VALID_Msk (0x1UL << /*ERRBNK_TEBR1_VALID_Pos*/) /*!< ERRBNK TEBR1: VALID Mask */ + +/*@}*/ /* end of group ErrBnk_Type */ + + +/** + \ingroup CMSIS_core_register + \defgroup PrcCfgInf_Type Processor Configuration Information Registers (IMPLEMENTATION DEFINED) + \brief Type definitions for the Processor Configuration Information Registerss (PRCCFGINF) + @{ + */ + +/** + \brief Structure type to access the Processor Configuration Information Registerss (PRCCFGINF). + */ +typedef struct +{ + __OM uint32_t CFGINFOSEL; /*!< Offset: 0x000 ( /W) Processor Configuration Information Selection Register */ + __IM uint32_t CFGINFORD; /*!< Offset: 0x004 (R/ ) Processor Configuration Information Read Data Register */ +} PrcCfgInf_Type; + +/* PRCCFGINF Processor Configuration Information Selection Register (CFGINFOSEL) Definitions */ + +/* PRCCFGINF Processor Configuration Information Read Data Register (CFGINFORD) Definitions */ + +/*@}*/ /* end of group PrcCfgInf_Type */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Sizes Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Sizes Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ + uint32_t RESERVED3[809U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) Software Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) Software Lock Status Register */ + uint32_t RESERVED4[4U]; + __IM uint32_t TYPE; /*!< Offset: 0xFC8 (R/ ) Device Identifier Register */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Register */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_SWOSCALER_Pos 0U /*!< TPI ACPR: SWOSCALER Position */ +#define TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/) /*!< TPI ACPR: SWOSCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ +#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ + +#define TPI_FFCR_EnFmt_Pos 0U /*!< TPI FFCR: EnFmt Position */ +#define TPI_FFCR_EnFmt_Msk (0x3UL << /*TPI_FFCR_EnFmt_Pos*/) /*!< TPI FFCR: EnFmt Mask */ + +/* TPI Periodic Synchronization Control Register Definitions */ +#define TPI_PSCR_PSCount_Pos 0U /*!< TPI PSCR: PSCount Position */ +#define TPI_PSCR_PSCount_Msk (0x1FUL /*<< TPI_PSCR_PSCount_Pos*/) /*!< TPI PSCR: TPSCount Mask */ + +/* TPI Software Lock Status Register Definitions */ +#define TPI_LSR_nTT_Pos 1U /*!< TPI LSR: Not thirty-two bit. Position */ +#define TPI_LSR_nTT_Msk (0x1UL << TPI_LSR_nTT_Pos) /*!< TPI LSR: Not thirty-two bit. Mask */ + +#define TPI_LSR_SLK_Pos 1U /*!< TPI LSR: Software Lock status Position */ +#define TPI_LSR_SLK_Msk (0x1UL << TPI_LSR_SLK_Pos) /*!< TPI LSR: Software Lock status Mask */ + +#define TPI_LSR_SLI_Pos 0U /*!< TPI LSR: Software Lock implemented Position */ +#define TPI_LSR_SLI_Msk (0x1UL /*<< TPI_LSR_SLI_Pos*/) /*!< TPI LSR: Software Lock implemented Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFO depth Position */ +#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFO depth Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + +#if defined (__PMU_PRESENT) && (__PMU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_PMU Performance Monitoring Unit (PMU) + \brief Type definitions for the Performance Monitoring Unit (PMU) + @{ + */ + +/** + \brief Structure type to access the Performance Monitoring Unit (PMU). + */ +typedef struct +{ + __IOM uint32_t EVCNTR[__PMU_NUM_EVENTCNT]; /*!< Offset: 0x0 (R/W) PMU Event Counter Registers */ +#if __PMU_NUM_EVENTCNT<31 + uint32_t RESERVED0[31U-__PMU_NUM_EVENTCNT]; +#endif + __IOM uint32_t CCNTR; /*!< Offset: 0x7C (R/W) PMU Cycle Counter Register */ + uint32_t RESERVED1[224]; + __IOM uint32_t EVTYPER[__PMU_NUM_EVENTCNT]; /*!< Offset: 0x400 (R/W) PMU Event Type and Filter Registers */ +#if __PMU_NUM_EVENTCNT<31 + uint32_t RESERVED2[31U-__PMU_NUM_EVENTCNT]; +#endif + __IOM uint32_t CCFILTR; /*!< Offset: 0x47C (R/W) PMU Cycle Counter Filter Register */ + uint32_t RESERVED3[480]; + __IOM uint32_t CNTENSET; /*!< Offset: 0xC00 (R/W) PMU Count Enable Set Register */ + uint32_t RESERVED4[7]; + __IOM uint32_t CNTENCLR; /*!< Offset: 0xC20 (R/W) PMU Count Enable Clear Register */ + uint32_t RESERVED5[7]; + __IOM uint32_t INTENSET; /*!< Offset: 0xC40 (R/W) PMU Interrupt Enable Set Register */ + uint32_t RESERVED6[7]; + __IOM uint32_t INTENCLR; /*!< Offset: 0xC60 (R/W) PMU Interrupt Enable Clear Register */ + uint32_t RESERVED7[7]; + __IOM uint32_t OVSCLR; /*!< Offset: 0xC80 (R/W) PMU Overflow Flag Status Clear Register */ + uint32_t RESERVED8[7]; + __IOM uint32_t SWINC; /*!< Offset: 0xCA0 (R/W) PMU Software Increment Register */ + uint32_t RESERVED9[7]; + __IOM uint32_t OVSSET; /*!< Offset: 0xCC0 (R/W) PMU Overflow Flag Status Set Register */ + uint32_t RESERVED10[79]; + __IOM uint32_t TYPE; /*!< Offset: 0xE00 (R/W) PMU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0xE04 (R/W) PMU Control Register */ + uint32_t RESERVED11[108]; + __IOM uint32_t AUTHSTATUS; /*!< Offset: 0xFB8 (R/W) PMU Authentication Status Register */ + __IOM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/W) PMU Device Architecture Register */ + uint32_t RESERVED12[3]; + __IOM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/W) PMU Device Type Register */ + __IOM uint32_t PIDR4; /*!< Offset: 0xFD0 (R/W) PMU Peripheral Identification Register 4 */ + uint32_t RESERVED13[3]; + __IOM uint32_t PIDR0; /*!< Offset: 0xFE0 (R/W) PMU Peripheral Identification Register 0 */ + __IOM uint32_t PIDR1; /*!< Offset: 0xFE4 (R/W) PMU Peripheral Identification Register 1 */ + __IOM uint32_t PIDR2; /*!< Offset: 0xFE8 (R/W) PMU Peripheral Identification Register 2 */ + __IOM uint32_t PIDR3; /*!< Offset: 0xFEC (R/W) PMU Peripheral Identification Register 3 */ + __IOM uint32_t CIDR0; /*!< Offset: 0xFF0 (R/W) PMU Component Identification Register 0 */ + __IOM uint32_t CIDR1; /*!< Offset: 0xFF4 (R/W) PMU Component Identification Register 1 */ + __IOM uint32_t CIDR2; /*!< Offset: 0xFF8 (R/W) PMU Component Identification Register 2 */ + __IOM uint32_t CIDR3; /*!< Offset: 0xFFC (R/W) PMU Component Identification Register 3 */ +} PMU_Type; + +/** \brief PMU Event Counter Registers (0-30) Definitions */ + +#define PMU_EVCNTR_CNT_Pos 0U /*!< PMU EVCNTR: Counter Position */ +#define PMU_EVCNTR_CNT_Msk (0xFFFFUL /*<< PMU_EVCNTRx_CNT_Pos*/) /*!< PMU EVCNTR: Counter Mask */ + +/** \brief PMU Event Type and Filter Registers (0-30) Definitions */ + +#define PMU_EVTYPER_EVENTTOCNT_Pos 0U /*!< PMU EVTYPER: Event to Count Position */ +#define PMU_EVTYPER_EVENTTOCNT_Msk (0xFFFFUL /*<< EVTYPERx_EVENTTOCNT_Pos*/) /*!< PMU EVTYPER: Event to Count Mask */ + +/** \brief PMU Count Enable Set Register Definitions */ + +#define PMU_CNTENSET_CNT0_ENABLE_Pos 0U /*!< PMU CNTENSET: Event Counter 0 Enable Set Position */ +#define PMU_CNTENSET_CNT0_ENABLE_Msk (1UL /*<< PMU_CNTENSET_CNT0_ENABLE_Pos*/) /*!< PMU CNTENSET: Event Counter 0 Enable Set Mask */ + +#define PMU_CNTENSET_CNT1_ENABLE_Pos 1U /*!< PMU CNTENSET: Event Counter 1 Enable Set Position */ +#define PMU_CNTENSET_CNT1_ENABLE_Msk (1UL << PMU_CNTENSET_CNT1_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 1 Enable Set Mask */ + +#define PMU_CNTENSET_CNT2_ENABLE_Pos 2U /*!< PMU CNTENSET: Event Counter 2 Enable Set Position */ +#define PMU_CNTENSET_CNT2_ENABLE_Msk (1UL << PMU_CNTENSET_CNT2_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 2 Enable Set Mask */ + +#define PMU_CNTENSET_CNT3_ENABLE_Pos 3U /*!< PMU CNTENSET: Event Counter 3 Enable Set Position */ +#define PMU_CNTENSET_CNT3_ENABLE_Msk (1UL << PMU_CNTENSET_CNT3_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 3 Enable Set Mask */ + +#define PMU_CNTENSET_CNT4_ENABLE_Pos 4U /*!< PMU CNTENSET: Event Counter 4 Enable Set Position */ +#define PMU_CNTENSET_CNT4_ENABLE_Msk (1UL << PMU_CNTENSET_CNT4_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 4 Enable Set Mask */ + +#define PMU_CNTENSET_CNT5_ENABLE_Pos 5U /*!< PMU CNTENSET: Event Counter 5 Enable Set Position */ +#define PMU_CNTENSET_CNT5_ENABLE_Msk (1UL << PMU_CNTENSET_CNT5_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 5 Enable Set Mask */ + +#define PMU_CNTENSET_CNT6_ENABLE_Pos 6U /*!< PMU CNTENSET: Event Counter 6 Enable Set Position */ +#define PMU_CNTENSET_CNT6_ENABLE_Msk (1UL << PMU_CNTENSET_CNT6_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 6 Enable Set Mask */ + +#define PMU_CNTENSET_CNT7_ENABLE_Pos 7U /*!< PMU CNTENSET: Event Counter 7 Enable Set Position */ +#define PMU_CNTENSET_CNT7_ENABLE_Msk (1UL << PMU_CNTENSET_CNT7_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 7 Enable Set Mask */ + +#define PMU_CNTENSET_CNT8_ENABLE_Pos 8U /*!< PMU CNTENSET: Event Counter 8 Enable Set Position */ +#define PMU_CNTENSET_CNT8_ENABLE_Msk (1UL << PMU_CNTENSET_CNT8_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 8 Enable Set Mask */ + +#define PMU_CNTENSET_CNT9_ENABLE_Pos 9U /*!< PMU CNTENSET: Event Counter 9 Enable Set Position */ +#define PMU_CNTENSET_CNT9_ENABLE_Msk (1UL << PMU_CNTENSET_CNT9_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 9 Enable Set Mask */ + +#define PMU_CNTENSET_CNT10_ENABLE_Pos 10U /*!< PMU CNTENSET: Event Counter 10 Enable Set Position */ +#define PMU_CNTENSET_CNT10_ENABLE_Msk (1UL << PMU_CNTENSET_CNT10_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 10 Enable Set Mask */ + +#define PMU_CNTENSET_CNT11_ENABLE_Pos 11U /*!< PMU CNTENSET: Event Counter 11 Enable Set Position */ +#define PMU_CNTENSET_CNT11_ENABLE_Msk (1UL << PMU_CNTENSET_CNT11_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 11 Enable Set Mask */ + +#define PMU_CNTENSET_CNT12_ENABLE_Pos 12U /*!< PMU CNTENSET: Event Counter 12 Enable Set Position */ +#define PMU_CNTENSET_CNT12_ENABLE_Msk (1UL << PMU_CNTENSET_CNT12_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 12 Enable Set Mask */ + +#define PMU_CNTENSET_CNT13_ENABLE_Pos 13U /*!< PMU CNTENSET: Event Counter 13 Enable Set Position */ +#define PMU_CNTENSET_CNT13_ENABLE_Msk (1UL << PMU_CNTENSET_CNT13_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 13 Enable Set Mask */ + +#define PMU_CNTENSET_CNT14_ENABLE_Pos 14U /*!< PMU CNTENSET: Event Counter 14 Enable Set Position */ +#define PMU_CNTENSET_CNT14_ENABLE_Msk (1UL << PMU_CNTENSET_CNT14_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 14 Enable Set Mask */ + +#define PMU_CNTENSET_CNT15_ENABLE_Pos 15U /*!< PMU CNTENSET: Event Counter 15 Enable Set Position */ +#define PMU_CNTENSET_CNT15_ENABLE_Msk (1UL << PMU_CNTENSET_CNT15_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 15 Enable Set Mask */ + +#define PMU_CNTENSET_CNT16_ENABLE_Pos 16U /*!< PMU CNTENSET: Event Counter 16 Enable Set Position */ +#define PMU_CNTENSET_CNT16_ENABLE_Msk (1UL << PMU_CNTENSET_CNT16_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 16 Enable Set Mask */ + +#define PMU_CNTENSET_CNT17_ENABLE_Pos 17U /*!< PMU CNTENSET: Event Counter 17 Enable Set Position */ +#define PMU_CNTENSET_CNT17_ENABLE_Msk (1UL << PMU_CNTENSET_CNT17_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 17 Enable Set Mask */ + +#define PMU_CNTENSET_CNT18_ENABLE_Pos 18U /*!< PMU CNTENSET: Event Counter 18 Enable Set Position */ +#define PMU_CNTENSET_CNT18_ENABLE_Msk (1UL << PMU_CNTENSET_CNT18_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 18 Enable Set Mask */ + +#define PMU_CNTENSET_CNT19_ENABLE_Pos 19U /*!< PMU CNTENSET: Event Counter 19 Enable Set Position */ +#define PMU_CNTENSET_CNT19_ENABLE_Msk (1UL << PMU_CNTENSET_CNT19_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 19 Enable Set Mask */ + +#define PMU_CNTENSET_CNT20_ENABLE_Pos 20U /*!< PMU CNTENSET: Event Counter 20 Enable Set Position */ +#define PMU_CNTENSET_CNT20_ENABLE_Msk (1UL << PMU_CNTENSET_CNT20_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 20 Enable Set Mask */ + +#define PMU_CNTENSET_CNT21_ENABLE_Pos 21U /*!< PMU CNTENSET: Event Counter 21 Enable Set Position */ +#define PMU_CNTENSET_CNT21_ENABLE_Msk (1UL << PMU_CNTENSET_CNT21_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 21 Enable Set Mask */ + +#define PMU_CNTENSET_CNT22_ENABLE_Pos 22U /*!< PMU CNTENSET: Event Counter 22 Enable Set Position */ +#define PMU_CNTENSET_CNT22_ENABLE_Msk (1UL << PMU_CNTENSET_CNT22_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 22 Enable Set Mask */ + +#define PMU_CNTENSET_CNT23_ENABLE_Pos 23U /*!< PMU CNTENSET: Event Counter 23 Enable Set Position */ +#define PMU_CNTENSET_CNT23_ENABLE_Msk (1UL << PMU_CNTENSET_CNT23_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 23 Enable Set Mask */ + +#define PMU_CNTENSET_CNT24_ENABLE_Pos 24U /*!< PMU CNTENSET: Event Counter 24 Enable Set Position */ +#define PMU_CNTENSET_CNT24_ENABLE_Msk (1UL << PMU_CNTENSET_CNT24_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 24 Enable Set Mask */ + +#define PMU_CNTENSET_CNT25_ENABLE_Pos 25U /*!< PMU CNTENSET: Event Counter 25 Enable Set Position */ +#define PMU_CNTENSET_CNT25_ENABLE_Msk (1UL << PMU_CNTENSET_CNT25_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 25 Enable Set Mask */ + +#define PMU_CNTENSET_CNT26_ENABLE_Pos 26U /*!< PMU CNTENSET: Event Counter 26 Enable Set Position */ +#define PMU_CNTENSET_CNT26_ENABLE_Msk (1UL << PMU_CNTENSET_CNT26_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 26 Enable Set Mask */ + +#define PMU_CNTENSET_CNT27_ENABLE_Pos 27U /*!< PMU CNTENSET: Event Counter 27 Enable Set Position */ +#define PMU_CNTENSET_CNT27_ENABLE_Msk (1UL << PMU_CNTENSET_CNT27_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 27 Enable Set Mask */ + +#define PMU_CNTENSET_CNT28_ENABLE_Pos 28U /*!< PMU CNTENSET: Event Counter 28 Enable Set Position */ +#define PMU_CNTENSET_CNT28_ENABLE_Msk (1UL << PMU_CNTENSET_CNT28_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 28 Enable Set Mask */ + +#define PMU_CNTENSET_CNT29_ENABLE_Pos 29U /*!< PMU CNTENSET: Event Counter 29 Enable Set Position */ +#define PMU_CNTENSET_CNT29_ENABLE_Msk (1UL << PMU_CNTENSET_CNT29_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 29 Enable Set Mask */ + +#define PMU_CNTENSET_CNT30_ENABLE_Pos 30U /*!< PMU CNTENSET: Event Counter 30 Enable Set Position */ +#define PMU_CNTENSET_CNT30_ENABLE_Msk (1UL << PMU_CNTENSET_CNT30_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 30 Enable Set Mask */ + +#define PMU_CNTENSET_CCNTR_ENABLE_Pos 31U /*!< PMU CNTENSET: Cycle Counter Enable Set Position */ +#define PMU_CNTENSET_CCNTR_ENABLE_Msk (1UL << PMU_CNTENSET_CCNTR_ENABLE_Pos) /*!< PMU CNTENSET: Cycle Counter Enable Set Mask */ + +/** \brief PMU Count Enable Clear Register Definitions */ + +#define PMU_CNTENSET_CNT0_ENABLE_Pos 0U /*!< PMU CNTENCLR: Event Counter 0 Enable Clear Position */ +#define PMU_CNTENCLR_CNT0_ENABLE_Msk (1UL /*<< PMU_CNTENCLR_CNT0_ENABLE_Pos*/) /*!< PMU CNTENCLR: Event Counter 0 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT1_ENABLE_Pos 1U /*!< PMU CNTENCLR: Event Counter 1 Enable Clear Position */ +#define PMU_CNTENCLR_CNT1_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT1_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 1 Enable Clear */ + +#define PMU_CNTENCLR_CNT2_ENABLE_Pos 2U /*!< PMU CNTENCLR: Event Counter 2 Enable Clear Position */ +#define PMU_CNTENCLR_CNT2_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT2_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 2 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT3_ENABLE_Pos 3U /*!< PMU CNTENCLR: Event Counter 3 Enable Clear Position */ +#define PMU_CNTENCLR_CNT3_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT3_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 3 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT4_ENABLE_Pos 4U /*!< PMU CNTENCLR: Event Counter 4 Enable Clear Position */ +#define PMU_CNTENCLR_CNT4_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT4_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 4 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT5_ENABLE_Pos 5U /*!< PMU CNTENCLR: Event Counter 5 Enable Clear Position */ +#define PMU_CNTENCLR_CNT5_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT5_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 5 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT6_ENABLE_Pos 6U /*!< PMU CNTENCLR: Event Counter 6 Enable Clear Position */ +#define PMU_CNTENCLR_CNT6_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT6_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 6 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT7_ENABLE_Pos 7U /*!< PMU CNTENCLR: Event Counter 7 Enable Clear Position */ +#define PMU_CNTENCLR_CNT7_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT7_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 7 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT8_ENABLE_Pos 8U /*!< PMU CNTENCLR: Event Counter 8 Enable Clear Position */ +#define PMU_CNTENCLR_CNT8_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT8_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 8 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT9_ENABLE_Pos 9U /*!< PMU CNTENCLR: Event Counter 9 Enable Clear Position */ +#define PMU_CNTENCLR_CNT9_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT9_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 9 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT10_ENABLE_Pos 10U /*!< PMU CNTENCLR: Event Counter 10 Enable Clear Position */ +#define PMU_CNTENCLR_CNT10_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT10_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 10 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT11_ENABLE_Pos 11U /*!< PMU CNTENCLR: Event Counter 11 Enable Clear Position */ +#define PMU_CNTENCLR_CNT11_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT11_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 11 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT12_ENABLE_Pos 12U /*!< PMU CNTENCLR: Event Counter 12 Enable Clear Position */ +#define PMU_CNTENCLR_CNT12_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT12_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 12 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT13_ENABLE_Pos 13U /*!< PMU CNTENCLR: Event Counter 13 Enable Clear Position */ +#define PMU_CNTENCLR_CNT13_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT13_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 13 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT14_ENABLE_Pos 14U /*!< PMU CNTENCLR: Event Counter 14 Enable Clear Position */ +#define PMU_CNTENCLR_CNT14_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT14_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 14 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT15_ENABLE_Pos 15U /*!< PMU CNTENCLR: Event Counter 15 Enable Clear Position */ +#define PMU_CNTENCLR_CNT15_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT15_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 15 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT16_ENABLE_Pos 16U /*!< PMU CNTENCLR: Event Counter 16 Enable Clear Position */ +#define PMU_CNTENCLR_CNT16_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT16_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 16 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT17_ENABLE_Pos 17U /*!< PMU CNTENCLR: Event Counter 17 Enable Clear Position */ +#define PMU_CNTENCLR_CNT17_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT17_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 17 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT18_ENABLE_Pos 18U /*!< PMU CNTENCLR: Event Counter 18 Enable Clear Position */ +#define PMU_CNTENCLR_CNT18_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT18_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 18 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT19_ENABLE_Pos 19U /*!< PMU CNTENCLR: Event Counter 19 Enable Clear Position */ +#define PMU_CNTENCLR_CNT19_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT19_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 19 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT20_ENABLE_Pos 20U /*!< PMU CNTENCLR: Event Counter 20 Enable Clear Position */ +#define PMU_CNTENCLR_CNT20_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT20_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 20 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT21_ENABLE_Pos 21U /*!< PMU CNTENCLR: Event Counter 21 Enable Clear Position */ +#define PMU_CNTENCLR_CNT21_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT21_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 21 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT22_ENABLE_Pos 22U /*!< PMU CNTENCLR: Event Counter 22 Enable Clear Position */ +#define PMU_CNTENCLR_CNT22_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT22_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 22 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT23_ENABLE_Pos 23U /*!< PMU CNTENCLR: Event Counter 23 Enable Clear Position */ +#define PMU_CNTENCLR_CNT23_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT23_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 23 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT24_ENABLE_Pos 24U /*!< PMU CNTENCLR: Event Counter 24 Enable Clear Position */ +#define PMU_CNTENCLR_CNT24_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT24_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 24 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT25_ENABLE_Pos 25U /*!< PMU CNTENCLR: Event Counter 25 Enable Clear Position */ +#define PMU_CNTENCLR_CNT25_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT25_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 25 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT26_ENABLE_Pos 26U /*!< PMU CNTENCLR: Event Counter 26 Enable Clear Position */ +#define PMU_CNTENCLR_CNT26_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT26_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 26 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT27_ENABLE_Pos 27U /*!< PMU CNTENCLR: Event Counter 27 Enable Clear Position */ +#define PMU_CNTENCLR_CNT27_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT27_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 27 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT28_ENABLE_Pos 28U /*!< PMU CNTENCLR: Event Counter 28 Enable Clear Position */ +#define PMU_CNTENCLR_CNT28_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT28_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 28 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT29_ENABLE_Pos 29U /*!< PMU CNTENCLR: Event Counter 29 Enable Clear Position */ +#define PMU_CNTENCLR_CNT29_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT29_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 29 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT30_ENABLE_Pos 30U /*!< PMU CNTENCLR: Event Counter 30 Enable Clear Position */ +#define PMU_CNTENCLR_CNT30_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT30_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 30 Enable Clear Mask */ + +#define PMU_CNTENCLR_CCNTR_ENABLE_Pos 31U /*!< PMU CNTENCLR: Cycle Counter Enable Clear Position */ +#define PMU_CNTENCLR_CCNTR_ENABLE_Msk (1UL << PMU_CNTENCLR_CCNTR_ENABLE_Pos) /*!< PMU CNTENCLR: Cycle Counter Enable Clear Mask */ + +/** \brief PMU Interrupt Enable Set Register Definitions */ + +#define PMU_INTENSET_CNT0_ENABLE_Pos 0U /*!< PMU INTENSET: Event Counter 0 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT0_ENABLE_Msk (1UL /*<< PMU_INTENSET_CNT0_ENABLE_Pos*/) /*!< PMU INTENSET: Event Counter 0 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT1_ENABLE_Pos 1U /*!< PMU INTENSET: Event Counter 1 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT1_ENABLE_Msk (1UL << PMU_INTENSET_CNT1_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 1 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT2_ENABLE_Pos 2U /*!< PMU INTENSET: Event Counter 2 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT2_ENABLE_Msk (1UL << PMU_INTENSET_CNT2_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 2 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT3_ENABLE_Pos 3U /*!< PMU INTENSET: Event Counter 3 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT3_ENABLE_Msk (1UL << PMU_INTENSET_CNT3_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 3 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT4_ENABLE_Pos 4U /*!< PMU INTENSET: Event Counter 4 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT4_ENABLE_Msk (1UL << PMU_INTENSET_CNT4_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 4 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT5_ENABLE_Pos 5U /*!< PMU INTENSET: Event Counter 5 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT5_ENABLE_Msk (1UL << PMU_INTENSET_CNT5_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 5 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT6_ENABLE_Pos 6U /*!< PMU INTENSET: Event Counter 6 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT6_ENABLE_Msk (1UL << PMU_INTENSET_CNT6_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 6 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT7_ENABLE_Pos 7U /*!< PMU INTENSET: Event Counter 7 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT7_ENABLE_Msk (1UL << PMU_INTENSET_CNT7_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 7 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT8_ENABLE_Pos 8U /*!< PMU INTENSET: Event Counter 8 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT8_ENABLE_Msk (1UL << PMU_INTENSET_CNT8_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 8 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT9_ENABLE_Pos 9U /*!< PMU INTENSET: Event Counter 9 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT9_ENABLE_Msk (1UL << PMU_INTENSET_CNT9_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 9 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT10_ENABLE_Pos 10U /*!< PMU INTENSET: Event Counter 10 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT10_ENABLE_Msk (1UL << PMU_INTENSET_CNT10_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 10 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT11_ENABLE_Pos 11U /*!< PMU INTENSET: Event Counter 11 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT11_ENABLE_Msk (1UL << PMU_INTENSET_CNT11_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 11 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT12_ENABLE_Pos 12U /*!< PMU INTENSET: Event Counter 12 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT12_ENABLE_Msk (1UL << PMU_INTENSET_CNT12_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 12 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT13_ENABLE_Pos 13U /*!< PMU INTENSET: Event Counter 13 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT13_ENABLE_Msk (1UL << PMU_INTENSET_CNT13_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 13 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT14_ENABLE_Pos 14U /*!< PMU INTENSET: Event Counter 14 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT14_ENABLE_Msk (1UL << PMU_INTENSET_CNT14_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 14 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT15_ENABLE_Pos 15U /*!< PMU INTENSET: Event Counter 15 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT15_ENABLE_Msk (1UL << PMU_INTENSET_CNT15_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 15 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT16_ENABLE_Pos 16U /*!< PMU INTENSET: Event Counter 16 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT16_ENABLE_Msk (1UL << PMU_INTENSET_CNT16_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 16 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT17_ENABLE_Pos 17U /*!< PMU INTENSET: Event Counter 17 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT17_ENABLE_Msk (1UL << PMU_INTENSET_CNT17_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 17 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT18_ENABLE_Pos 18U /*!< PMU INTENSET: Event Counter 18 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT18_ENABLE_Msk (1UL << PMU_INTENSET_CNT18_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 18 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT19_ENABLE_Pos 19U /*!< PMU INTENSET: Event Counter 19 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT19_ENABLE_Msk (1UL << PMU_INTENSET_CNT19_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 19 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT20_ENABLE_Pos 20U /*!< PMU INTENSET: Event Counter 20 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT20_ENABLE_Msk (1UL << PMU_INTENSET_CNT20_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 20 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT21_ENABLE_Pos 21U /*!< PMU INTENSET: Event Counter 21 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT21_ENABLE_Msk (1UL << PMU_INTENSET_CNT21_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 21 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT22_ENABLE_Pos 22U /*!< PMU INTENSET: Event Counter 22 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT22_ENABLE_Msk (1UL << PMU_INTENSET_CNT22_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 22 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT23_ENABLE_Pos 23U /*!< PMU INTENSET: Event Counter 23 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT23_ENABLE_Msk (1UL << PMU_INTENSET_CNT23_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 23 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT24_ENABLE_Pos 24U /*!< PMU INTENSET: Event Counter 24 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT24_ENABLE_Msk (1UL << PMU_INTENSET_CNT24_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 24 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT25_ENABLE_Pos 25U /*!< PMU INTENSET: Event Counter 25 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT25_ENABLE_Msk (1UL << PMU_INTENSET_CNT25_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 25 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT26_ENABLE_Pos 26U /*!< PMU INTENSET: Event Counter 26 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT26_ENABLE_Msk (1UL << PMU_INTENSET_CNT26_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 26 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT27_ENABLE_Pos 27U /*!< PMU INTENSET: Event Counter 27 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT27_ENABLE_Msk (1UL << PMU_INTENSET_CNT27_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 27 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT28_ENABLE_Pos 28U /*!< PMU INTENSET: Event Counter 28 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT28_ENABLE_Msk (1UL << PMU_INTENSET_CNT28_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 28 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT29_ENABLE_Pos 29U /*!< PMU INTENSET: Event Counter 29 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT29_ENABLE_Msk (1UL << PMU_INTENSET_CNT29_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 29 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT30_ENABLE_Pos 30U /*!< PMU INTENSET: Event Counter 30 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT30_ENABLE_Msk (1UL << PMU_INTENSET_CNT30_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 30 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CYCCNT_ENABLE_Pos 31U /*!< PMU INTENSET: Cycle Counter Interrupt Enable Set Position */ +#define PMU_INTENSET_CCYCNT_ENABLE_Msk (1UL << PMU_INTENSET_CYCCNT_ENABLE_Pos) /*!< PMU INTENSET: Cycle Counter Interrupt Enable Set Mask */ + +/** \brief PMU Interrupt Enable Clear Register Definitions */ + +#define PMU_INTENSET_CNT0_ENABLE_Pos 0U /*!< PMU INTENCLR: Event Counter 0 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT0_ENABLE_Msk (1UL /*<< PMU_INTENCLR_CNT0_ENABLE_Pos*/) /*!< PMU INTENCLR: Event Counter 0 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT1_ENABLE_Pos 1U /*!< PMU INTENCLR: Event Counter 1 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT1_ENABLE_Msk (1UL << PMU_INTENCLR_CNT1_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 1 Interrupt Enable Clear */ + +#define PMU_INTENCLR_CNT2_ENABLE_Pos 2U /*!< PMU INTENCLR: Event Counter 2 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT2_ENABLE_Msk (1UL << PMU_INTENCLR_CNT2_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 2 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT3_ENABLE_Pos 3U /*!< PMU INTENCLR: Event Counter 3 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT3_ENABLE_Msk (1UL << PMU_INTENCLR_CNT3_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 3 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT4_ENABLE_Pos 4U /*!< PMU INTENCLR: Event Counter 4 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT4_ENABLE_Msk (1UL << PMU_INTENCLR_CNT4_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 4 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT5_ENABLE_Pos 5U /*!< PMU INTENCLR: Event Counter 5 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT5_ENABLE_Msk (1UL << PMU_INTENCLR_CNT5_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 5 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT6_ENABLE_Pos 6U /*!< PMU INTENCLR: Event Counter 6 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT6_ENABLE_Msk (1UL << PMU_INTENCLR_CNT6_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 6 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT7_ENABLE_Pos 7U /*!< PMU INTENCLR: Event Counter 7 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT7_ENABLE_Msk (1UL << PMU_INTENCLR_CNT7_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 7 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT8_ENABLE_Pos 8U /*!< PMU INTENCLR: Event Counter 8 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT8_ENABLE_Msk (1UL << PMU_INTENCLR_CNT8_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 8 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT9_ENABLE_Pos 9U /*!< PMU INTENCLR: Event Counter 9 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT9_ENABLE_Msk (1UL << PMU_INTENCLR_CNT9_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 9 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT10_ENABLE_Pos 10U /*!< PMU INTENCLR: Event Counter 10 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT10_ENABLE_Msk (1UL << PMU_INTENCLR_CNT10_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 10 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT11_ENABLE_Pos 11U /*!< PMU INTENCLR: Event Counter 11 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT11_ENABLE_Msk (1UL << PMU_INTENCLR_CNT11_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 11 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT12_ENABLE_Pos 12U /*!< PMU INTENCLR: Event Counter 12 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT12_ENABLE_Msk (1UL << PMU_INTENCLR_CNT12_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 12 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT13_ENABLE_Pos 13U /*!< PMU INTENCLR: Event Counter 13 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT13_ENABLE_Msk (1UL << PMU_INTENCLR_CNT13_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 13 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT14_ENABLE_Pos 14U /*!< PMU INTENCLR: Event Counter 14 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT14_ENABLE_Msk (1UL << PMU_INTENCLR_CNT14_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 14 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT15_ENABLE_Pos 15U /*!< PMU INTENCLR: Event Counter 15 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT15_ENABLE_Msk (1UL << PMU_INTENCLR_CNT15_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 15 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT16_ENABLE_Pos 16U /*!< PMU INTENCLR: Event Counter 16 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT16_ENABLE_Msk (1UL << PMU_INTENCLR_CNT16_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 16 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT17_ENABLE_Pos 17U /*!< PMU INTENCLR: Event Counter 17 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT17_ENABLE_Msk (1UL << PMU_INTENCLR_CNT17_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 17 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT18_ENABLE_Pos 18U /*!< PMU INTENCLR: Event Counter 18 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT18_ENABLE_Msk (1UL << PMU_INTENCLR_CNT18_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 18 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT19_ENABLE_Pos 19U /*!< PMU INTENCLR: Event Counter 19 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT19_ENABLE_Msk (1UL << PMU_INTENCLR_CNT19_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 19 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT20_ENABLE_Pos 20U /*!< PMU INTENCLR: Event Counter 20 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT20_ENABLE_Msk (1UL << PMU_INTENCLR_CNT20_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 20 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT21_ENABLE_Pos 21U /*!< PMU INTENCLR: Event Counter 21 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT21_ENABLE_Msk (1UL << PMU_INTENCLR_CNT21_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 21 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT22_ENABLE_Pos 22U /*!< PMU INTENCLR: Event Counter 22 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT22_ENABLE_Msk (1UL << PMU_INTENCLR_CNT22_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 22 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT23_ENABLE_Pos 23U /*!< PMU INTENCLR: Event Counter 23 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT23_ENABLE_Msk (1UL << PMU_INTENCLR_CNT23_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 23 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT24_ENABLE_Pos 24U /*!< PMU INTENCLR: Event Counter 24 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT24_ENABLE_Msk (1UL << PMU_INTENCLR_CNT24_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 24 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT25_ENABLE_Pos 25U /*!< PMU INTENCLR: Event Counter 25 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT25_ENABLE_Msk (1UL << PMU_INTENCLR_CNT25_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 25 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT26_ENABLE_Pos 26U /*!< PMU INTENCLR: Event Counter 26 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT26_ENABLE_Msk (1UL << PMU_INTENCLR_CNT26_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 26 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT27_ENABLE_Pos 27U /*!< PMU INTENCLR: Event Counter 27 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT27_ENABLE_Msk (1UL << PMU_INTENCLR_CNT27_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 27 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT28_ENABLE_Pos 28U /*!< PMU INTENCLR: Event Counter 28 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT28_ENABLE_Msk (1UL << PMU_INTENCLR_CNT28_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 28 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT29_ENABLE_Pos 29U /*!< PMU INTENCLR: Event Counter 29 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT29_ENABLE_Msk (1UL << PMU_INTENCLR_CNT29_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 29 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT30_ENABLE_Pos 30U /*!< PMU INTENCLR: Event Counter 30 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT30_ENABLE_Msk (1UL << PMU_INTENCLR_CNT30_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 30 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CYCCNT_ENABLE_Pos 31U /*!< PMU INTENCLR: Cycle Counter Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CYCCNT_ENABLE_Msk (1UL << PMU_INTENCLR_CYCCNT_ENABLE_Pos) /*!< PMU INTENCLR: Cycle Counter Interrupt Enable Clear Mask */ + +/** \brief PMU Overflow Flag Status Set Register Definitions */ + +#define PMU_OVSSET_CNT0_STATUS_Pos 0U /*!< PMU OVSSET: Event Counter 0 Overflow Set Position */ +#define PMU_OVSSET_CNT0_STATUS_Msk (1UL /*<< PMU_OVSSET_CNT0_STATUS_Pos*/) /*!< PMU OVSSET: Event Counter 0 Overflow Set Mask */ + +#define PMU_OVSSET_CNT1_STATUS_Pos 1U /*!< PMU OVSSET: Event Counter 1 Overflow Set Position */ +#define PMU_OVSSET_CNT1_STATUS_Msk (1UL << PMU_OVSSET_CNT1_STATUS_Pos) /*!< PMU OVSSET: Event Counter 1 Overflow Set Mask */ + +#define PMU_OVSSET_CNT2_STATUS_Pos 2U /*!< PMU OVSSET: Event Counter 2 Overflow Set Position */ +#define PMU_OVSSET_CNT2_STATUS_Msk (1UL << PMU_OVSSET_CNT2_STATUS_Pos) /*!< PMU OVSSET: Event Counter 2 Overflow Set Mask */ + +#define PMU_OVSSET_CNT3_STATUS_Pos 3U /*!< PMU OVSSET: Event Counter 3 Overflow Set Position */ +#define PMU_OVSSET_CNT3_STATUS_Msk (1UL << PMU_OVSSET_CNT3_STATUS_Pos) /*!< PMU OVSSET: Event Counter 3 Overflow Set Mask */ + +#define PMU_OVSSET_CNT4_STATUS_Pos 4U /*!< PMU OVSSET: Event Counter 4 Overflow Set Position */ +#define PMU_OVSSET_CNT4_STATUS_Msk (1UL << PMU_OVSSET_CNT4_STATUS_Pos) /*!< PMU OVSSET: Event Counter 4 Overflow Set Mask */ + +#define PMU_OVSSET_CNT5_STATUS_Pos 5U /*!< PMU OVSSET: Event Counter 5 Overflow Set Position */ +#define PMU_OVSSET_CNT5_STATUS_Msk (1UL << PMU_OVSSET_CNT5_STATUS_Pos) /*!< PMU OVSSET: Event Counter 5 Overflow Set Mask */ + +#define PMU_OVSSET_CNT6_STATUS_Pos 6U /*!< PMU OVSSET: Event Counter 6 Overflow Set Position */ +#define PMU_OVSSET_CNT6_STATUS_Msk (1UL << PMU_OVSSET_CNT6_STATUS_Pos) /*!< PMU OVSSET: Event Counter 6 Overflow Set Mask */ + +#define PMU_OVSSET_CNT7_STATUS_Pos 7U /*!< PMU OVSSET: Event Counter 7 Overflow Set Position */ +#define PMU_OVSSET_CNT7_STATUS_Msk (1UL << PMU_OVSSET_CNT7_STATUS_Pos) /*!< PMU OVSSET: Event Counter 7 Overflow Set Mask */ + +#define PMU_OVSSET_CNT8_STATUS_Pos 8U /*!< PMU OVSSET: Event Counter 8 Overflow Set Position */ +#define PMU_OVSSET_CNT8_STATUS_Msk (1UL << PMU_OVSSET_CNT8_STATUS_Pos) /*!< PMU OVSSET: Event Counter 8 Overflow Set Mask */ + +#define PMU_OVSSET_CNT9_STATUS_Pos 9U /*!< PMU OVSSET: Event Counter 9 Overflow Set Position */ +#define PMU_OVSSET_CNT9_STATUS_Msk (1UL << PMU_OVSSET_CNT9_STATUS_Pos) /*!< PMU OVSSET: Event Counter 9 Overflow Set Mask */ + +#define PMU_OVSSET_CNT10_STATUS_Pos 10U /*!< PMU OVSSET: Event Counter 10 Overflow Set Position */ +#define PMU_OVSSET_CNT10_STATUS_Msk (1UL << PMU_OVSSET_CNT10_STATUS_Pos) /*!< PMU OVSSET: Event Counter 10 Overflow Set Mask */ + +#define PMU_OVSSET_CNT11_STATUS_Pos 11U /*!< PMU OVSSET: Event Counter 11 Overflow Set Position */ +#define PMU_OVSSET_CNT11_STATUS_Msk (1UL << PMU_OVSSET_CNT11_STATUS_Pos) /*!< PMU OVSSET: Event Counter 11 Overflow Set Mask */ + +#define PMU_OVSSET_CNT12_STATUS_Pos 12U /*!< PMU OVSSET: Event Counter 12 Overflow Set Position */ +#define PMU_OVSSET_CNT12_STATUS_Msk (1UL << PMU_OVSSET_CNT12_STATUS_Pos) /*!< PMU OVSSET: Event Counter 12 Overflow Set Mask */ + +#define PMU_OVSSET_CNT13_STATUS_Pos 13U /*!< PMU OVSSET: Event Counter 13 Overflow Set Position */ +#define PMU_OVSSET_CNT13_STATUS_Msk (1UL << PMU_OVSSET_CNT13_STATUS_Pos) /*!< PMU OVSSET: Event Counter 13 Overflow Set Mask */ + +#define PMU_OVSSET_CNT14_STATUS_Pos 14U /*!< PMU OVSSET: Event Counter 14 Overflow Set Position */ +#define PMU_OVSSET_CNT14_STATUS_Msk (1UL << PMU_OVSSET_CNT14_STATUS_Pos) /*!< PMU OVSSET: Event Counter 14 Overflow Set Mask */ + +#define PMU_OVSSET_CNT15_STATUS_Pos 15U /*!< PMU OVSSET: Event Counter 15 Overflow Set Position */ +#define PMU_OVSSET_CNT15_STATUS_Msk (1UL << PMU_OVSSET_CNT15_STATUS_Pos) /*!< PMU OVSSET: Event Counter 15 Overflow Set Mask */ + +#define PMU_OVSSET_CNT16_STATUS_Pos 16U /*!< PMU OVSSET: Event Counter 16 Overflow Set Position */ +#define PMU_OVSSET_CNT16_STATUS_Msk (1UL << PMU_OVSSET_CNT16_STATUS_Pos) /*!< PMU OVSSET: Event Counter 16 Overflow Set Mask */ + +#define PMU_OVSSET_CNT17_STATUS_Pos 17U /*!< PMU OVSSET: Event Counter 17 Overflow Set Position */ +#define PMU_OVSSET_CNT17_STATUS_Msk (1UL << PMU_OVSSET_CNT17_STATUS_Pos) /*!< PMU OVSSET: Event Counter 17 Overflow Set Mask */ + +#define PMU_OVSSET_CNT18_STATUS_Pos 18U /*!< PMU OVSSET: Event Counter 18 Overflow Set Position */ +#define PMU_OVSSET_CNT18_STATUS_Msk (1UL << PMU_OVSSET_CNT18_STATUS_Pos) /*!< PMU OVSSET: Event Counter 18 Overflow Set Mask */ + +#define PMU_OVSSET_CNT19_STATUS_Pos 19U /*!< PMU OVSSET: Event Counter 19 Overflow Set Position */ +#define PMU_OVSSET_CNT19_STATUS_Msk (1UL << PMU_OVSSET_CNT19_STATUS_Pos) /*!< PMU OVSSET: Event Counter 19 Overflow Set Mask */ + +#define PMU_OVSSET_CNT20_STATUS_Pos 20U /*!< PMU OVSSET: Event Counter 20 Overflow Set Position */ +#define PMU_OVSSET_CNT20_STATUS_Msk (1UL << PMU_OVSSET_CNT20_STATUS_Pos) /*!< PMU OVSSET: Event Counter 20 Overflow Set Mask */ + +#define PMU_OVSSET_CNT21_STATUS_Pos 21U /*!< PMU OVSSET: Event Counter 21 Overflow Set Position */ +#define PMU_OVSSET_CNT21_STATUS_Msk (1UL << PMU_OVSSET_CNT21_STATUS_Pos) /*!< PMU OVSSET: Event Counter 21 Overflow Set Mask */ + +#define PMU_OVSSET_CNT22_STATUS_Pos 22U /*!< PMU OVSSET: Event Counter 22 Overflow Set Position */ +#define PMU_OVSSET_CNT22_STATUS_Msk (1UL << PMU_OVSSET_CNT22_STATUS_Pos) /*!< PMU OVSSET: Event Counter 22 Overflow Set Mask */ + +#define PMU_OVSSET_CNT23_STATUS_Pos 23U /*!< PMU OVSSET: Event Counter 23 Overflow Set Position */ +#define PMU_OVSSET_CNT23_STATUS_Msk (1UL << PMU_OVSSET_CNT23_STATUS_Pos) /*!< PMU OVSSET: Event Counter 23 Overflow Set Mask */ + +#define PMU_OVSSET_CNT24_STATUS_Pos 24U /*!< PMU OVSSET: Event Counter 24 Overflow Set Position */ +#define PMU_OVSSET_CNT24_STATUS_Msk (1UL << PMU_OVSSET_CNT24_STATUS_Pos) /*!< PMU OVSSET: Event Counter 24 Overflow Set Mask */ + +#define PMU_OVSSET_CNT25_STATUS_Pos 25U /*!< PMU OVSSET: Event Counter 25 Overflow Set Position */ +#define PMU_OVSSET_CNT25_STATUS_Msk (1UL << PMU_OVSSET_CNT25_STATUS_Pos) /*!< PMU OVSSET: Event Counter 25 Overflow Set Mask */ + +#define PMU_OVSSET_CNT26_STATUS_Pos 26U /*!< PMU OVSSET: Event Counter 26 Overflow Set Position */ +#define PMU_OVSSET_CNT26_STATUS_Msk (1UL << PMU_OVSSET_CNT26_STATUS_Pos) /*!< PMU OVSSET: Event Counter 26 Overflow Set Mask */ + +#define PMU_OVSSET_CNT27_STATUS_Pos 27U /*!< PMU OVSSET: Event Counter 27 Overflow Set Position */ +#define PMU_OVSSET_CNT27_STATUS_Msk (1UL << PMU_OVSSET_CNT27_STATUS_Pos) /*!< PMU OVSSET: Event Counter 27 Overflow Set Mask */ + +#define PMU_OVSSET_CNT28_STATUS_Pos 28U /*!< PMU OVSSET: Event Counter 28 Overflow Set Position */ +#define PMU_OVSSET_CNT28_STATUS_Msk (1UL << PMU_OVSSET_CNT28_STATUS_Pos) /*!< PMU OVSSET: Event Counter 28 Overflow Set Mask */ + +#define PMU_OVSSET_CNT29_STATUS_Pos 29U /*!< PMU OVSSET: Event Counter 29 Overflow Set Position */ +#define PMU_OVSSET_CNT29_STATUS_Msk (1UL << PMU_OVSSET_CNT29_STATUS_Pos) /*!< PMU OVSSET: Event Counter 29 Overflow Set Mask */ + +#define PMU_OVSSET_CNT30_STATUS_Pos 30U /*!< PMU OVSSET: Event Counter 30 Overflow Set Position */ +#define PMU_OVSSET_CNT30_STATUS_Msk (1UL << PMU_OVSSET_CNT30_STATUS_Pos) /*!< PMU OVSSET: Event Counter 30 Overflow Set Mask */ + +#define PMU_OVSSET_CYCCNT_STATUS_Pos 31U /*!< PMU OVSSET: Cycle Counter Overflow Set Position */ +#define PMU_OVSSET_CYCCNT_STATUS_Msk (1UL << PMU_OVSSET_CYCCNT_STATUS_Pos) /*!< PMU OVSSET: Cycle Counter Overflow Set Mask */ + +/** \brief PMU Overflow Flag Status Clear Register Definitions */ + +#define PMU_OVSCLR_CNT0_STATUS_Pos 0U /*!< PMU OVSCLR: Event Counter 0 Overflow Clear Position */ +#define PMU_OVSCLR_CNT0_STATUS_Msk (1UL /*<< PMU_OVSCLR_CNT0_STATUS_Pos*/) /*!< PMU OVSCLR: Event Counter 0 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT1_STATUS_Pos 1U /*!< PMU OVSCLR: Event Counter 1 Overflow Clear Position */ +#define PMU_OVSCLR_CNT1_STATUS_Msk (1UL << PMU_OVSCLR_CNT1_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 1 Overflow Clear */ + +#define PMU_OVSCLR_CNT2_STATUS_Pos 2U /*!< PMU OVSCLR: Event Counter 2 Overflow Clear Position */ +#define PMU_OVSCLR_CNT2_STATUS_Msk (1UL << PMU_OVSCLR_CNT2_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 2 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT3_STATUS_Pos 3U /*!< PMU OVSCLR: Event Counter 3 Overflow Clear Position */ +#define PMU_OVSCLR_CNT3_STATUS_Msk (1UL << PMU_OVSCLR_CNT3_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 3 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT4_STATUS_Pos 4U /*!< PMU OVSCLR: Event Counter 4 Overflow Clear Position */ +#define PMU_OVSCLR_CNT4_STATUS_Msk (1UL << PMU_OVSCLR_CNT4_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 4 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT5_STATUS_Pos 5U /*!< PMU OVSCLR: Event Counter 5 Overflow Clear Position */ +#define PMU_OVSCLR_CNT5_STATUS_Msk (1UL << PMU_OVSCLR_CNT5_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 5 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT6_STATUS_Pos 6U /*!< PMU OVSCLR: Event Counter 6 Overflow Clear Position */ +#define PMU_OVSCLR_CNT6_STATUS_Msk (1UL << PMU_OVSCLR_CNT6_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 6 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT7_STATUS_Pos 7U /*!< PMU OVSCLR: Event Counter 7 Overflow Clear Position */ +#define PMU_OVSCLR_CNT7_STATUS_Msk (1UL << PMU_OVSCLR_CNT7_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 7 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT8_STATUS_Pos 8U /*!< PMU OVSCLR: Event Counter 8 Overflow Clear Position */ +#define PMU_OVSCLR_CNT8_STATUS_Msk (1UL << PMU_OVSCLR_CNT8_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 8 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT9_STATUS_Pos 9U /*!< PMU OVSCLR: Event Counter 9 Overflow Clear Position */ +#define PMU_OVSCLR_CNT9_STATUS_Msk (1UL << PMU_OVSCLR_CNT9_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 9 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT10_STATUS_Pos 10U /*!< PMU OVSCLR: Event Counter 10 Overflow Clear Position */ +#define PMU_OVSCLR_CNT10_STATUS_Msk (1UL << PMU_OVSCLR_CNT10_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 10 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT11_STATUS_Pos 11U /*!< PMU OVSCLR: Event Counter 11 Overflow Clear Position */ +#define PMU_OVSCLR_CNT11_STATUS_Msk (1UL << PMU_OVSCLR_CNT11_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 11 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT12_STATUS_Pos 12U /*!< PMU OVSCLR: Event Counter 12 Overflow Clear Position */ +#define PMU_OVSCLR_CNT12_STATUS_Msk (1UL << PMU_OVSCLR_CNT12_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 12 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT13_STATUS_Pos 13U /*!< PMU OVSCLR: Event Counter 13 Overflow Clear Position */ +#define PMU_OVSCLR_CNT13_STATUS_Msk (1UL << PMU_OVSCLR_CNT13_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 13 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT14_STATUS_Pos 14U /*!< PMU OVSCLR: Event Counter 14 Overflow Clear Position */ +#define PMU_OVSCLR_CNT14_STATUS_Msk (1UL << PMU_OVSCLR_CNT14_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 14 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT15_STATUS_Pos 15U /*!< PMU OVSCLR: Event Counter 15 Overflow Clear Position */ +#define PMU_OVSCLR_CNT15_STATUS_Msk (1UL << PMU_OVSCLR_CNT15_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 15 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT16_STATUS_Pos 16U /*!< PMU OVSCLR: Event Counter 16 Overflow Clear Position */ +#define PMU_OVSCLR_CNT16_STATUS_Msk (1UL << PMU_OVSCLR_CNT16_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 16 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT17_STATUS_Pos 17U /*!< PMU OVSCLR: Event Counter 17 Overflow Clear Position */ +#define PMU_OVSCLR_CNT17_STATUS_Msk (1UL << PMU_OVSCLR_CNT17_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 17 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT18_STATUS_Pos 18U /*!< PMU OVSCLR: Event Counter 18 Overflow Clear Position */ +#define PMU_OVSCLR_CNT18_STATUS_Msk (1UL << PMU_OVSCLR_CNT18_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 18 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT19_STATUS_Pos 19U /*!< PMU OVSCLR: Event Counter 19 Overflow Clear Position */ +#define PMU_OVSCLR_CNT19_STATUS_Msk (1UL << PMU_OVSCLR_CNT19_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 19 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT20_STATUS_Pos 20U /*!< PMU OVSCLR: Event Counter 20 Overflow Clear Position */ +#define PMU_OVSCLR_CNT20_STATUS_Msk (1UL << PMU_OVSCLR_CNT20_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 20 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT21_STATUS_Pos 21U /*!< PMU OVSCLR: Event Counter 21 Overflow Clear Position */ +#define PMU_OVSCLR_CNT21_STATUS_Msk (1UL << PMU_OVSCLR_CNT21_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 21 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT22_STATUS_Pos 22U /*!< PMU OVSCLR: Event Counter 22 Overflow Clear Position */ +#define PMU_OVSCLR_CNT22_STATUS_Msk (1UL << PMU_OVSCLR_CNT22_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 22 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT23_STATUS_Pos 23U /*!< PMU OVSCLR: Event Counter 23 Overflow Clear Position */ +#define PMU_OVSCLR_CNT23_STATUS_Msk (1UL << PMU_OVSCLR_CNT23_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 23 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT24_STATUS_Pos 24U /*!< PMU OVSCLR: Event Counter 24 Overflow Clear Position */ +#define PMU_OVSCLR_CNT24_STATUS_Msk (1UL << PMU_OVSCLR_CNT24_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 24 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT25_STATUS_Pos 25U /*!< PMU OVSCLR: Event Counter 25 Overflow Clear Position */ +#define PMU_OVSCLR_CNT25_STATUS_Msk (1UL << PMU_OVSCLR_CNT25_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 25 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT26_STATUS_Pos 26U /*!< PMU OVSCLR: Event Counter 26 Overflow Clear Position */ +#define PMU_OVSCLR_CNT26_STATUS_Msk (1UL << PMU_OVSCLR_CNT26_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 26 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT27_STATUS_Pos 27U /*!< PMU OVSCLR: Event Counter 27 Overflow Clear Position */ +#define PMU_OVSCLR_CNT27_STATUS_Msk (1UL << PMU_OVSCLR_CNT27_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 27 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT28_STATUS_Pos 28U /*!< PMU OVSCLR: Event Counter 28 Overflow Clear Position */ +#define PMU_OVSCLR_CNT28_STATUS_Msk (1UL << PMU_OVSCLR_CNT28_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 28 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT29_STATUS_Pos 29U /*!< PMU OVSCLR: Event Counter 29 Overflow Clear Position */ +#define PMU_OVSCLR_CNT29_STATUS_Msk (1UL << PMU_OVSCLR_CNT29_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 29 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT30_STATUS_Pos 30U /*!< PMU OVSCLR: Event Counter 30 Overflow Clear Position */ +#define PMU_OVSCLR_CNT30_STATUS_Msk (1UL << PMU_OVSCLR_CNT30_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 30 Overflow Clear Mask */ + +#define PMU_OVSCLR_CYCCNT_STATUS_Pos 31U /*!< PMU OVSCLR: Cycle Counter Overflow Clear Position */ +#define PMU_OVSCLR_CYCCNT_STATUS_Msk (1UL << PMU_OVSCLR_CYCCNT_STATUS_Pos) /*!< PMU OVSCLR: Cycle Counter Overflow Clear Mask */ + +/** \brief PMU Software Increment Counter */ + +#define PMU_SWINC_CNT0_Pos 0U /*!< PMU SWINC: Event Counter 0 Software Increment Position */ +#define PMU_SWINC_CNT0_Msk (1UL /*<< PMU_SWINC_CNT0_Pos */) /*!< PMU SWINC: Event Counter 0 Software Increment Mask */ + +#define PMU_SWINC_CNT1_Pos 1U /*!< PMU SWINC: Event Counter 1 Software Increment Position */ +#define PMU_SWINC_CNT1_Msk (1UL << PMU_SWINC_CNT1_Pos) /*!< PMU SWINC: Event Counter 1 Software Increment Mask */ + +#define PMU_SWINC_CNT2_Pos 2U /*!< PMU SWINC: Event Counter 2 Software Increment Position */ +#define PMU_SWINC_CNT2_Msk (1UL << PMU_SWINC_CNT2_Pos) /*!< PMU SWINC: Event Counter 2 Software Increment Mask */ + +#define PMU_SWINC_CNT3_Pos 3U /*!< PMU SWINC: Event Counter 3 Software Increment Position */ +#define PMU_SWINC_CNT3_Msk (1UL << PMU_SWINC_CNT3_Pos) /*!< PMU SWINC: Event Counter 3 Software Increment Mask */ + +#define PMU_SWINC_CNT4_Pos 4U /*!< PMU SWINC: Event Counter 4 Software Increment Position */ +#define PMU_SWINC_CNT4_Msk (1UL << PMU_SWINC_CNT4_Pos) /*!< PMU SWINC: Event Counter 4 Software Increment Mask */ + +#define PMU_SWINC_CNT5_Pos 5U /*!< PMU SWINC: Event Counter 5 Software Increment Position */ +#define PMU_SWINC_CNT5_Msk (1UL << PMU_SWINC_CNT5_Pos) /*!< PMU SWINC: Event Counter 5 Software Increment Mask */ + +#define PMU_SWINC_CNT6_Pos 6U /*!< PMU SWINC: Event Counter 6 Software Increment Position */ +#define PMU_SWINC_CNT6_Msk (1UL << PMU_SWINC_CNT6_Pos) /*!< PMU SWINC: Event Counter 6 Software Increment Mask */ + +#define PMU_SWINC_CNT7_Pos 7U /*!< PMU SWINC: Event Counter 7 Software Increment Position */ +#define PMU_SWINC_CNT7_Msk (1UL << PMU_SWINC_CNT7_Pos) /*!< PMU SWINC: Event Counter 7 Software Increment Mask */ + +#define PMU_SWINC_CNT8_Pos 8U /*!< PMU SWINC: Event Counter 8 Software Increment Position */ +#define PMU_SWINC_CNT8_Msk (1UL << PMU_SWINC_CNT8_Pos) /*!< PMU SWINC: Event Counter 8 Software Increment Mask */ + +#define PMU_SWINC_CNT9_Pos 9U /*!< PMU SWINC: Event Counter 9 Software Increment Position */ +#define PMU_SWINC_CNT9_Msk (1UL << PMU_SWINC_CNT9_Pos) /*!< PMU SWINC: Event Counter 9 Software Increment Mask */ + +#define PMU_SWINC_CNT10_Pos 10U /*!< PMU SWINC: Event Counter 10 Software Increment Position */ +#define PMU_SWINC_CNT10_Msk (1UL << PMU_SWINC_CNT10_Pos) /*!< PMU SWINC: Event Counter 10 Software Increment Mask */ + +#define PMU_SWINC_CNT11_Pos 11U /*!< PMU SWINC: Event Counter 11 Software Increment Position */ +#define PMU_SWINC_CNT11_Msk (1UL << PMU_SWINC_CNT11_Pos) /*!< PMU SWINC: Event Counter 11 Software Increment Mask */ + +#define PMU_SWINC_CNT12_Pos 12U /*!< PMU SWINC: Event Counter 12 Software Increment Position */ +#define PMU_SWINC_CNT12_Msk (1UL << PMU_SWINC_CNT12_Pos) /*!< PMU SWINC: Event Counter 12 Software Increment Mask */ + +#define PMU_SWINC_CNT13_Pos 13U /*!< PMU SWINC: Event Counter 13 Software Increment Position */ +#define PMU_SWINC_CNT13_Msk (1UL << PMU_SWINC_CNT13_Pos) /*!< PMU SWINC: Event Counter 13 Software Increment Mask */ + +#define PMU_SWINC_CNT14_Pos 14U /*!< PMU SWINC: Event Counter 14 Software Increment Position */ +#define PMU_SWINC_CNT14_Msk (1UL << PMU_SWINC_CNT14_Pos) /*!< PMU SWINC: Event Counter 14 Software Increment Mask */ + +#define PMU_SWINC_CNT15_Pos 15U /*!< PMU SWINC: Event Counter 15 Software Increment Position */ +#define PMU_SWINC_CNT15_Msk (1UL << PMU_SWINC_CNT15_Pos) /*!< PMU SWINC: Event Counter 15 Software Increment Mask */ + +#define PMU_SWINC_CNT16_Pos 16U /*!< PMU SWINC: Event Counter 16 Software Increment Position */ +#define PMU_SWINC_CNT16_Msk (1UL << PMU_SWINC_CNT16_Pos) /*!< PMU SWINC: Event Counter 16 Software Increment Mask */ + +#define PMU_SWINC_CNT17_Pos 17U /*!< PMU SWINC: Event Counter 17 Software Increment Position */ +#define PMU_SWINC_CNT17_Msk (1UL << PMU_SWINC_CNT17_Pos) /*!< PMU SWINC: Event Counter 17 Software Increment Mask */ + +#define PMU_SWINC_CNT18_Pos 18U /*!< PMU SWINC: Event Counter 18 Software Increment Position */ +#define PMU_SWINC_CNT18_Msk (1UL << PMU_SWINC_CNT18_Pos) /*!< PMU SWINC: Event Counter 18 Software Increment Mask */ + +#define PMU_SWINC_CNT19_Pos 19U /*!< PMU SWINC: Event Counter 19 Software Increment Position */ +#define PMU_SWINC_CNT19_Msk (1UL << PMU_SWINC_CNT19_Pos) /*!< PMU SWINC: Event Counter 19 Software Increment Mask */ + +#define PMU_SWINC_CNT20_Pos 20U /*!< PMU SWINC: Event Counter 20 Software Increment Position */ +#define PMU_SWINC_CNT20_Msk (1UL << PMU_SWINC_CNT20_Pos) /*!< PMU SWINC: Event Counter 20 Software Increment Mask */ + +#define PMU_SWINC_CNT21_Pos 21U /*!< PMU SWINC: Event Counter 21 Software Increment Position */ +#define PMU_SWINC_CNT21_Msk (1UL << PMU_SWINC_CNT21_Pos) /*!< PMU SWINC: Event Counter 21 Software Increment Mask */ + +#define PMU_SWINC_CNT22_Pos 22U /*!< PMU SWINC: Event Counter 22 Software Increment Position */ +#define PMU_SWINC_CNT22_Msk (1UL << PMU_SWINC_CNT22_Pos) /*!< PMU SWINC: Event Counter 22 Software Increment Mask */ + +#define PMU_SWINC_CNT23_Pos 23U /*!< PMU SWINC: Event Counter 23 Software Increment Position */ +#define PMU_SWINC_CNT23_Msk (1UL << PMU_SWINC_CNT23_Pos) /*!< PMU SWINC: Event Counter 23 Software Increment Mask */ + +#define PMU_SWINC_CNT24_Pos 24U /*!< PMU SWINC: Event Counter 24 Software Increment Position */ +#define PMU_SWINC_CNT24_Msk (1UL << PMU_SWINC_CNT24_Pos) /*!< PMU SWINC: Event Counter 24 Software Increment Mask */ + +#define PMU_SWINC_CNT25_Pos 25U /*!< PMU SWINC: Event Counter 25 Software Increment Position */ +#define PMU_SWINC_CNT25_Msk (1UL << PMU_SWINC_CNT25_Pos) /*!< PMU SWINC: Event Counter 25 Software Increment Mask */ + +#define PMU_SWINC_CNT26_Pos 26U /*!< PMU SWINC: Event Counter 26 Software Increment Position */ +#define PMU_SWINC_CNT26_Msk (1UL << PMU_SWINC_CNT26_Pos) /*!< PMU SWINC: Event Counter 26 Software Increment Mask */ + +#define PMU_SWINC_CNT27_Pos 27U /*!< PMU SWINC: Event Counter 27 Software Increment Position */ +#define PMU_SWINC_CNT27_Msk (1UL << PMU_SWINC_CNT27_Pos) /*!< PMU SWINC: Event Counter 27 Software Increment Mask */ + +#define PMU_SWINC_CNT28_Pos 28U /*!< PMU SWINC: Event Counter 28 Software Increment Position */ +#define PMU_SWINC_CNT28_Msk (1UL << PMU_SWINC_CNT28_Pos) /*!< PMU SWINC: Event Counter 28 Software Increment Mask */ + +#define PMU_SWINC_CNT29_Pos 29U /*!< PMU SWINC: Event Counter 29 Software Increment Position */ +#define PMU_SWINC_CNT29_Msk (1UL << PMU_SWINC_CNT29_Pos) /*!< PMU SWINC: Event Counter 29 Software Increment Mask */ + +#define PMU_SWINC_CNT30_Pos 30U /*!< PMU SWINC: Event Counter 30 Software Increment Position */ +#define PMU_SWINC_CNT30_Msk (1UL << PMU_SWINC_CNT30_Pos) /*!< PMU SWINC: Event Counter 30 Software Increment Mask */ + +/** \brief PMU Control Register Definitions */ + +#define PMU_CTRL_ENABLE_Pos 0U /*!< PMU CTRL: ENABLE Position */ +#define PMU_CTRL_ENABLE_Msk (1UL /*<< PMU_CTRL_ENABLE_Pos*/) /*!< PMU CTRL: ENABLE Mask */ + +#define PMU_CTRL_EVENTCNT_RESET_Pos 1U /*!< PMU CTRL: Event Counter Reset Position */ +#define PMU_CTRL_EVENTCNT_RESET_Msk (1UL << PMU_CTRL_EVENTCNT_RESET_Pos) /*!< PMU CTRL: Event Counter Reset Mask */ + +#define PMU_CTRL_CYCCNT_RESET_Pos 2U /*!< PMU CTRL: Cycle Counter Reset Position */ +#define PMU_CTRL_CYCCNT_RESET_Msk (1UL << PMU_CTRL_CYCCNT_RESET_Pos) /*!< PMU CTRL: Cycle Counter Reset Mask */ + +#define PMU_CTRL_CYCCNT_DISABLE_Pos 5U /*!< PMU CTRL: Disable Cycle Counter Position */ +#define PMU_CTRL_CYCCNT_DISABLE_Msk (1UL << PMU_CTRL_CYCCNT_DISABLE_Pos) /*!< PMU CTRL: Disable Cycle Counter Mask */ + +#define PMU_CTRL_FRZ_ON_OV_Pos 9U /*!< PMU CTRL: Freeze-on-overflow Position */ +#define PMU_CTRL_FRZ_ON_OV_Msk (1UL << PMU_CTRL_FRZ_ON_OVERFLOW_Pos) /*!< PMU CTRL: Freeze-on-overflow Mask */ + +#define PMU_CTRL_TRACE_ON_OV_Pos 11U /*!< PMU CTRL: Trace-on-overflow Position */ +#define PMU_CTRL_TRACE_ON_OV_Msk (1UL << PMU_CTRL_TRACE_ON_OVERFLOW_Pos) /*!< PMU CTRL: Trace-on-overflow Mask */ + +/** \brief PMU Type Register Definitions */ + +#define PMU_TYPE_NUM_CNTS_Pos 0U /*!< PMU TYPE: Number of Counters Position */ +#define PMU_TYPE_NUM_CNTS_Msk (0xFFUL /*<< PMU_TYPE_NUM_CNTS_Pos*/) /*!< PMU TYPE: Number of Counters Mask */ + +#define PMU_TYPE_SIZE_CNTS_Pos 8U /*!< PMU TYPE: Size of Counters Position */ +#define PMU_TYPE_SIZE_CNTS_Msk (0x3FUL << PMU_TYPE_SIZE_CNTS_Pos) /*!< PMU TYPE: Size of Counters Mask */ + +#define PMU_TYPE_CYCCNT_PRESENT_Pos 14U /*!< PMU TYPE: Cycle Counter Present Position */ +#define PMU_TYPE_CYCCNT_PRESENT_Msk (1UL << PMU_TYPE_CYCCNT_PRESENT_Pos) /*!< PMU TYPE: Cycle Counter Present Mask */ + +#define PMU_TYPE_FRZ_OV_SUPPORT_Pos 21U /*!< PMU TYPE: Freeze-on-overflow Support Position */ +#define PMU_TYPE_FRZ_OV_SUPPORT_Msk (1UL << PMU_TYPE_FRZ_OV_SUPPORT_Pos) /*!< PMU TYPE: Freeze-on-overflow Support Mask */ + +#define PMU_TYPE_TRACE_ON_OV_SUPPORT_Pos 23U /*!< PMU TYPE: Trace-on-overflow Support Position */ +#define PMU_TYPE_TRACE_ON_OV_SUPPORT_Msk (1UL << PMU_TYPE_FRZ_OV_SUPPORT_Pos) /*!< PMU TYPE: Trace-on-overflow Support Mask */ + +/** \brief PMU Authentication Status Register Definitions */ + +#define PMU_AUTHSTATUS_NSID_Pos 0U /*!< PMU AUTHSTATUS: Non-secure Invasive Debug Position */ +#define PMU_AUTHSTATUS_NSID_Msk (0x3UL /*<< PMU_AUTHSTATUS_NSID_Pos*/) /*!< PMU AUTHSTATUS: Non-secure Invasive Debug Mask */ + +#define PMU_AUTHSTATUS_NSNID_Pos 2U /*!< PMU AUTHSTATUS: Non-secure Non-invasive Debug Position */ +#define PMU_AUTHSTATUS_NSNID_Msk (0x3UL << PMU_AUTHSTATUS_NSNID_Pos) /*!< PMU AUTHSTATUS: Non-secure Non-invasive Debug Mask */ + +#define PMU_AUTHSTATUS_SID_Pos 4U /*!< PMU AUTHSTATUS: Secure Invasive Debug Position */ +#define PMU_AUTHSTATUS_SID_Msk (0x3UL << PMU_AUTHSTATUS_SID_Pos) /*!< PMU AUTHSTATUS: Secure Invasive Debug Mask */ + +#define PMU_AUTHSTATUS_SNID_Pos 6U /*!< PMU AUTHSTATUS: Secure Non-invasive Debug Position */ +#define PMU_AUTHSTATUS_SNID_Msk (0x3UL << PMU_AUTHSTATUS_SNID_Pos) /*!< PMU AUTHSTATUS: Secure Non-invasive Debug Mask */ + +#define PMU_AUTHSTATUS_NSUID_Pos 16U /*!< PMU AUTHSTATUS: Non-secure Unprivileged Invasive Debug Position */ +#define PMU_AUTHSTATUS_NSUID_Msk (0x3UL << PMU_AUTHSTATUS_NSUID_Pos) /*!< PMU AUTHSTATUS: Non-secure Unprivileged Invasive Debug Mask */ + +#define PMU_AUTHSTATUS_NSUNID_Pos 18U /*!< PMU AUTHSTATUS: Non-secure Unprivileged Non-invasive Debug Position */ +#define PMU_AUTHSTATUS_NSUNID_Msk (0x3UL << PMU_AUTHSTATUS_NSUNID_Pos) /*!< PMU AUTHSTATUS: Non-secure Unprivileged Non-invasive Debug Mask */ + +#define PMU_AUTHSTATUS_SUID_Pos 20U /*!< PMU AUTHSTATUS: Secure Unprivileged Invasive Debug Position */ +#define PMU_AUTHSTATUS_SUID_Msk (0x3UL << PMU_AUTHSTATUS_SUID_Pos) /*!< PMU AUTHSTATUS: Secure Unprivileged Invasive Debug Mask */ + +#define PMU_AUTHSTATUS_SUNID_Pos 22U /*!< PMU AUTHSTATUS: Secure Unprivileged Non-invasive Debug Position */ +#define PMU_AUTHSTATUS_SUNID_Msk (0x3UL << PMU_AUTHSTATUS_SUNID_Pos) /*!< PMU AUTHSTATUS: Secure Unprivileged Non-invasive Debug Mask */ + + +/*@} end of group CMSIS_PMU */ +#endif + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */ + __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */ + __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */ + __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */ + uint32_t RESERVED0[1]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ +#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/* MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_PXN_Pos 4U /*!< MPU RLAR: PXN Position */ +#define MPU_RLAR_PXN_Msk (1UL << MPU_RLAR_PXN_Pos) /*!< MPU RLAR: PXN Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */ + +/* MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/* MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#else + uint32_t RESERVED0[3]; +#endif + __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */ +} SAU_Type; + +/* SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/* SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/* SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/* SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/* SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/* Secure Fault Status Register Definitions */ +#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */ +#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */ + +#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */ +#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */ + +#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */ +#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */ + +#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */ +#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */ + +#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */ +#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */ + +#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */ +#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */ + +#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */ +#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */ + +#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */ +#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and VFP Feature Register 2 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */ +#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */ + +#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */ +#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */ + +#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */ +#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */ + +#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */ +#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */ + +#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */ +#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */ + +#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */ +#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */ +#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */ +#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +#define FPU_FPDSCR_FZ16_Pos 19U /*!< FPDSCR: FZ16 bit Position */ +#define FPU_FPDSCR_FZ16_Msk (1UL << FPU_FPDSCR_FZ16_Pos) /*!< FPDSCR: FZ16 bit Mask */ + +#define FPU_FPDSCR_LTPSIZE_Pos 16U /*!< FPDSCR: LTPSIZE bit Position */ +#define FPU_FPDSCR_LTPSIZE_Msk (7UL << FPU_FPDSCR_LTPSIZE_Pos) /*!< FPDSCR: LTPSIZE bit Mask */ + +/* Media and VFP Feature Register 0 Definitions */ +#define FPU_MVFR0_FPRound_Pos 28U /*!< MVFR0: FPRound bits Position */ +#define FPU_MVFR0_FPRound_Msk (0xFUL << FPU_MVFR0_FPRound_Pos) /*!< MVFR0: FPRound bits Mask */ + +#define FPU_MVFR0_FPSqrt_Pos 20U /*!< MVFR0: FPSqrt bits Position */ +#define FPU_MVFR0_FPSqrt_Msk (0xFUL << FPU_MVFR0_FPSqrt_Pos) /*!< MVFR0: FPSqrt bits Mask */ + +#define FPU_MVFR0_FPDivide_Pos 16U /*!< MVFR0: FPDivide bits Position */ +#define FPU_MVFR0_FPDivide_Msk (0xFUL << FPU_MVFR0_FPDivide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FPDP_Pos 8U /*!< MVFR0: FPDP bits Position */ +#define FPU_MVFR0_FPDP_Msk (0xFUL << FPU_MVFR0_FPDP_Pos) /*!< MVFR0: FPDP bits Mask */ + +#define FPU_MVFR0_FPSP_Pos 4U /*!< MVFR0: FPSP bits Position */ +#define FPU_MVFR0_FPSP_Msk (0xFUL << FPU_MVFR0_FPSP_Pos) /*!< MVFR0: FPSP bits Mask */ + +#define FPU_MVFR0_SIMDReg_Pos 0U /*!< MVFR0: SIMDReg bits Position */ +#define FPU_MVFR0_SIMDReg_Msk (0xFUL /*<< FPU_MVFR0_SIMDReg_Pos*/) /*!< MVFR0: SIMDReg bits Mask */ + +/* Media and VFP Feature Register 1 Definitions */ +#define FPU_MVFR1_FMAC_Pos 28U /*!< MVFR1: FMAC bits Position */ +#define FPU_MVFR1_FMAC_Msk (0xFUL << FPU_MVFR1_FMAC_Pos) /*!< MVFR1: FMAC bits Mask */ + +#define FPU_MVFR1_FPHP_Pos 24U /*!< MVFR1: FPHP bits Position */ +#define FPU_MVFR1_FPHP_Msk (0xFUL << FPU_MVFR1_FPHP_Pos) /*!< MVFR1: FPHP bits Mask */ + +#define FPU_MVFR1_FP16_Pos 20U /*!< MVFR1: FP16 bits Position */ +#define FPU_MVFR1_FP16_Msk (0xFUL << FPU_MVFR1_FP16_Pos) /*!< MVFR1: FP16 bits Mask */ + +#define FPU_MVFR1_MVE_Pos 8U /*!< MVFR1: MVE bits Position */ +#define FPU_MVFR1_MVE_Msk (0xFUL << FPU_MVFR1_MVE_Pos) /*!< MVFR1: MVE bits Mask */ + +#define FPU_MVFR1_FPDNaN_Pos 4U /*!< MVFR1: FPDNaN bits Position */ +#define FPU_MVFR1_FPDNaN_Msk (0xFUL << FPU_MVFR1_FPDNaN_Pos) /*!< MVFR1: FPDNaN bits Mask */ + +#define FPU_MVFR1_FPFtZ_Pos 0U /*!< MVFR1: FPFtZ bits Position */ +#define FPU_MVFR1_FPFtZ_Msk (0xFUL /*<< FPU_MVFR1_FPFtZ_Pos*/) /*!< MVFR1: FPFtZ bits Mask */ + +/* Media and VFP Feature Register 2 Definitions */ +#define FPU_MVFR2_FPMisc_Pos 4U /*!< MVFR2: FPMisc bits Position */ +#define FPU_MVFR2_FPMisc_Msk (0xFUL << FPU_MVFR2_FPMisc_Pos) /*!< MVFR2: FPMisc bits Mask */ + +/*@} end of group CMSIS_FPU */ + +/* CoreDebug is deprecated. replaced by DCB (Debug Control Block) */ +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief \deprecated Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + __OM uint32_t DSCEMCR; /*!< Offset: 0x010 ( /W) Debug Set Clear Exception and Monitor Control Register */ + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< \deprecated CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< \deprecated CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Position */ +#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_FPD_Pos 23U /*!< \deprecated CoreDebug DHCSR: S_FPD Position */ +#define CoreDebug_DHCSR_S_FPD_Msk (1UL << CoreDebug_DHCSR_S_FPD_Pos) /*!< \deprecated CoreDebug DHCSR: S_FPD Mask */ + +#define CoreDebug_DHCSR_S_SUIDE_Pos 22U /*!< \deprecated CoreDebug DHCSR: S_SUIDE Position */ +#define CoreDebug_DHCSR_S_SUIDE_Msk (1UL << CoreDebug_DHCSR_S_SUIDE_Pos) /*!< \deprecated CoreDebug DHCSR: S_SUIDE Mask */ + +#define CoreDebug_DHCSR_S_NSUIDE_Pos 21U /*!< \deprecated CoreDebug DHCSR: S_NSUIDE Position */ +#define CoreDebug_DHCSR_S_NSUIDE_Msk (1UL << CoreDebug_DHCSR_S_NSUIDE_Pos) /*!< \deprecated CoreDebug DHCSR: S_NSUIDE Mask */ + +#define CoreDebug_DHCSR_S_SDE_Pos 20U /*!< \deprecated CoreDebug DHCSR: S_SDE Position */ +#define CoreDebug_DHCSR_S_SDE_Msk (1UL << CoreDebug_DHCSR_S_SDE_Pos) /*!< \deprecated CoreDebug DHCSR: S_SDE Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< \deprecated CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< \deprecated CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< \deprecated CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< \deprecated CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< \deprecated CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_PMOV_Pos 6U /*!< \deprecated CoreDebug DHCSR: C_PMOV Position */ +#define CoreDebug_DHCSR_C_PMOV_Msk (1UL << CoreDebug_DHCSR_C_PMOV_Pos) /*!< \deprecated CoreDebug DHCSR: C_PMOV Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< \deprecated CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< \deprecated CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< \deprecated CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< \deprecated CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< \deprecated CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< \deprecated CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< \deprecated CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< \deprecated CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< \deprecated CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< \deprecated CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< \deprecated CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< \deprecated CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< \deprecated CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< \deprecated CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< \deprecated CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< \deprecated CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< \deprecated CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< \deprecated CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< \deprecated CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< \deprecated CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< \deprecated CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< \deprecated CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< \deprecated CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< \deprecated CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< \deprecated CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Mask */ + +/* Debug Set Clear Exception and Monitor Control Register Definitions */ +#define CoreDebug_DSCEMCR_CLR_MON_REQ_Pos 19U /*!< \deprecated CoreDebug DSCEMCR: CLR_MON_REQ, Position */ +#define CoreDebug_DSCEMCR_CLR_MON_REQ_Msk (1UL << CoreDebug_DSCEMCR_CLR_MON_REQ_Pos) /*!< \deprecated CoreDebug DSCEMCR: CLR_MON_REQ, Mask */ + +#define CoreDebug_DSCEMCR_CLR_MON_PEND_Pos 17U /*!< \deprecated CoreDebug DSCEMCR: CLR_MON_PEND, Position */ +#define CoreDebug_DSCEMCR_CLR_MON_PEND_Msk (1UL << CoreDebug_DSCEMCR_CLR_MON_PEND_Pos) /*!< \deprecated CoreDebug DSCEMCR: CLR_MON_PEND, Mask */ + +#define CoreDebug_DSCEMCR_SET_MON_REQ_Pos 3U /*!< \deprecated CoreDebug DSCEMCR: SET_MON_REQ, Position */ +#define CoreDebug_DSCEMCR_SET_MON_REQ_Msk (1UL << CoreDebug_DSCEMCR_SET_MON_REQ_Pos) /*!< \deprecated CoreDebug DSCEMCR: SET_MON_REQ, Mask */ + +#define CoreDebug_DSCEMCR_SET_MON_PEND_Pos 1U /*!< \deprecated CoreDebug DSCEMCR: SET_MON_PEND, Position */ +#define CoreDebug_DSCEMCR_SET_MON_PEND_Msk (1UL << CoreDebug_DSCEMCR_SET_MON_PEND_Pos) /*!< \deprecated CoreDebug DSCEMCR: SET_MON_PEND, Mask */ + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_UIDEN_Pos 10U /*!< \deprecated CoreDebug DAUTHCTRL: UIDEN, Position */ +#define CoreDebug_DAUTHCTRL_UIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_UIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: UIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_UIDAPEN_Pos 9U /*!< \deprecated CoreDebug DAUTHCTRL: UIDAPEN, Position */ +#define CoreDebug_DAUTHCTRL_UIDAPEN_Msk (1UL << CoreDebug_DAUTHCTRL_UIDAPEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: UIDAPEN, Mask */ + +#define CoreDebug_DAUTHCTRL_FSDMA_Pos 8U /*!< \deprecated CoreDebug DAUTHCTRL: FSDMA, Position */ +#define CoreDebug_DAUTHCTRL_FSDMA_Msk (1UL << CoreDebug_DAUTHCTRL_FSDMA_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: FSDMA, Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Position */ +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Mask */ + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Mask */ + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos 16U /*!< \deprecated CoreDebug DSCSR: CDS Position */ +#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< \deprecated CoreDebug DSCSR: CDS Mask */ + +#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< \deprecated CoreDebug DSCSR: SBRSEL Position */ +#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< \deprecated CoreDebug DSCSR: SBRSEL Mask */ + +#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< \deprecated CoreDebug DSCSR: SBRSELEN Position */ +#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< \deprecated CoreDebug DSCSR: SBRSELEN Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DCB Debug Control Block + \brief Type definitions for the Debug Control Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Control Block Registers (DCB). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + __OM uint32_t DSCEMCR; /*!< Offset: 0x010 ( /W) Debug Set Clear Exception and Monitor Control Register */ + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} DCB_Type; + +/* DHCSR, Debug Halting Control and Status Register Definitions */ +#define DCB_DHCSR_DBGKEY_Pos 16U /*!< DCB DHCSR: Debug key Position */ +#define DCB_DHCSR_DBGKEY_Msk (0xFFFFUL << DCB_DHCSR_DBGKEY_Pos) /*!< DCB DHCSR: Debug key Mask */ + +#define DCB_DHCSR_S_RESTART_ST_Pos 26U /*!< DCB DHCSR: Restart sticky status Position */ +#define DCB_DHCSR_S_RESTART_ST_Msk (0x1UL << DCB_DHCSR_S_RESTART_ST_Pos) /*!< DCB DHCSR: Restart sticky status Mask */ + +#define DCB_DHCSR_S_RESET_ST_Pos 25U /*!< DCB DHCSR: Reset sticky status Position */ +#define DCB_DHCSR_S_RESET_ST_Msk (0x1UL << DCB_DHCSR_S_RESET_ST_Pos) /*!< DCB DHCSR: Reset sticky status Mask */ + +#define DCB_DHCSR_S_RETIRE_ST_Pos 24U /*!< DCB DHCSR: Retire sticky status Position */ +#define DCB_DHCSR_S_RETIRE_ST_Msk (0x1UL << DCB_DHCSR_S_RETIRE_ST_Pos) /*!< DCB DHCSR: Retire sticky status Mask */ + +#define DCB_DHCSR_S_FPD_Pos 23U /*!< DCB DHCSR: Floating-point registers Debuggable Position */ +#define DCB_DHCSR_S_FPD_Msk (0x1UL << DCB_DHCSR_S_FPD_Pos) /*!< DCB DHCSR: Floating-point registers Debuggable Mask */ + +#define DCB_DHCSR_S_SUIDE_Pos 22U /*!< DCB DHCSR: Secure unprivileged halting debug enabled Position */ +#define DCB_DHCSR_S_SUIDE_Msk (0x1UL << DCB_DHCSR_S_SUIDE_Pos) /*!< DCB DHCSR: Secure unprivileged halting debug enabled Mask */ + +#define DCB_DHCSR_S_NSUIDE_Pos 21U /*!< DCB DHCSR: Non-secure unprivileged halting debug enabled Position */ +#define DCB_DHCSR_S_NSUIDE_Msk (0x1UL << DCB_DHCSR_S_NSUIDE_Pos) /*!< DCB DHCSR: Non-secure unprivileged halting debug enabled Mask */ + +#define DCB_DHCSR_S_SDE_Pos 20U /*!< DCB DHCSR: Secure debug enabled Position */ +#define DCB_DHCSR_S_SDE_Msk (0x1UL << DCB_DHCSR_S_SDE_Pos) /*!< DCB DHCSR: Secure debug enabled Mask */ + +#define DCB_DHCSR_S_LOCKUP_Pos 19U /*!< DCB DHCSR: Lockup status Position */ +#define DCB_DHCSR_S_LOCKUP_Msk (0x1UL << DCB_DHCSR_S_LOCKUP_Pos) /*!< DCB DHCSR: Lockup status Mask */ + +#define DCB_DHCSR_S_SLEEP_Pos 18U /*!< DCB DHCSR: Sleeping status Position */ +#define DCB_DHCSR_S_SLEEP_Msk (0x1UL << DCB_DHCSR_S_SLEEP_Pos) /*!< DCB DHCSR: Sleeping status Mask */ + +#define DCB_DHCSR_S_HALT_Pos 17U /*!< DCB DHCSR: Halted status Position */ +#define DCB_DHCSR_S_HALT_Msk (0x1UL << DCB_DHCSR_S_HALT_Pos) /*!< DCB DHCSR: Halted status Mask */ + +#define DCB_DHCSR_S_REGRDY_Pos 16U /*!< DCB DHCSR: Register ready status Position */ +#define DCB_DHCSR_S_REGRDY_Msk (0x1UL << DCB_DHCSR_S_REGRDY_Pos) /*!< DCB DHCSR: Register ready status Mask */ + +#define DCB_DHCSR_C_PMOV_Pos 6U /*!< DCB DHCSR: Halt on PMU overflow control Position */ +#define DCB_DHCSR_C_PMOV_Msk (0x1UL << DCB_DHCSR_C_PMOV_Pos) /*!< DCB DHCSR: Halt on PMU overflow control Mask */ + +#define DCB_DHCSR_C_SNAPSTALL_Pos 5U /*!< DCB DHCSR: Snap stall control Position */ +#define DCB_DHCSR_C_SNAPSTALL_Msk (0x1UL << DCB_DHCSR_C_SNAPSTALL_Pos) /*!< DCB DHCSR: Snap stall control Mask */ + +#define DCB_DHCSR_C_MASKINTS_Pos 3U /*!< DCB DHCSR: Mask interrupts control Position */ +#define DCB_DHCSR_C_MASKINTS_Msk (0x1UL << DCB_DHCSR_C_MASKINTS_Pos) /*!< DCB DHCSR: Mask interrupts control Mask */ + +#define DCB_DHCSR_C_STEP_Pos 2U /*!< DCB DHCSR: Step control Position */ +#define DCB_DHCSR_C_STEP_Msk (0x1UL << DCB_DHCSR_C_STEP_Pos) /*!< DCB DHCSR: Step control Mask */ + +#define DCB_DHCSR_C_HALT_Pos 1U /*!< DCB DHCSR: Halt control Position */ +#define DCB_DHCSR_C_HALT_Msk (0x1UL << DCB_DHCSR_C_HALT_Pos) /*!< DCB DHCSR: Halt control Mask */ + +#define DCB_DHCSR_C_DEBUGEN_Pos 0U /*!< DCB DHCSR: Debug enable control Position */ +#define DCB_DHCSR_C_DEBUGEN_Msk (0x1UL /*<< DCB_DHCSR_C_DEBUGEN_Pos*/) /*!< DCB DHCSR: Debug enable control Mask */ + +/* DCRSR, Debug Core Register Select Register Definitions */ +#define DCB_DCRSR_REGWnR_Pos 16U /*!< DCB DCRSR: Register write/not-read Position */ +#define DCB_DCRSR_REGWnR_Msk (0x1UL << DCB_DCRSR_REGWnR_Pos) /*!< DCB DCRSR: Register write/not-read Mask */ + +#define DCB_DCRSR_REGSEL_Pos 0U /*!< DCB DCRSR: Register selector Position */ +#define DCB_DCRSR_REGSEL_Msk (0x7FUL /*<< DCB_DCRSR_REGSEL_Pos*/) /*!< DCB DCRSR: Register selector Mask */ + +/* DCRDR, Debug Core Register Data Register Definitions */ +#define DCB_DCRDR_DBGTMP_Pos 0U /*!< DCB DCRDR: Data temporary buffer Position */ +#define DCB_DCRDR_DBGTMP_Msk (0xFFFFFFFFUL /*<< DCB_DCRDR_DBGTMP_Pos*/) /*!< DCB DCRDR: Data temporary buffer Mask */ + +/* DEMCR, Debug Exception and Monitor Control Register Definitions */ +#define DCB_DEMCR_TRCENA_Pos 24U /*!< DCB DEMCR: Trace enable Position */ +#define DCB_DEMCR_TRCENA_Msk (0x1UL << DCB_DEMCR_TRCENA_Pos) /*!< DCB DEMCR: Trace enable Mask */ + +#define DCB_DEMCR_MONPRKEY_Pos 23U /*!< DCB DEMCR: Monitor pend req key Position */ +#define DCB_DEMCR_MONPRKEY_Msk (0x1UL << DCB_DEMCR_MONPRKEY_Pos) /*!< DCB DEMCR: Monitor pend req key Mask */ + +#define DCB_DEMCR_UMON_EN_Pos 21U /*!< DCB DEMCR: Unprivileged monitor enable Position */ +#define DCB_DEMCR_UMON_EN_Msk (0x1UL << DCB_DEMCR_UMON_EN_Pos) /*!< DCB DEMCR: Unprivileged monitor enable Mask */ + +#define DCB_DEMCR_SDME_Pos 20U /*!< DCB DEMCR: Secure DebugMonitor enable Position */ +#define DCB_DEMCR_SDME_Msk (0x1UL << DCB_DEMCR_SDME_Pos) /*!< DCB DEMCR: Secure DebugMonitor enable Mask */ + +#define DCB_DEMCR_MON_REQ_Pos 19U /*!< DCB DEMCR: Monitor request Position */ +#define DCB_DEMCR_MON_REQ_Msk (0x1UL << DCB_DEMCR_MON_REQ_Pos) /*!< DCB DEMCR: Monitor request Mask */ + +#define DCB_DEMCR_MON_STEP_Pos 18U /*!< DCB DEMCR: Monitor step Position */ +#define DCB_DEMCR_MON_STEP_Msk (0x1UL << DCB_DEMCR_MON_STEP_Pos) /*!< DCB DEMCR: Monitor step Mask */ + +#define DCB_DEMCR_MON_PEND_Pos 17U /*!< DCB DEMCR: Monitor pend Position */ +#define DCB_DEMCR_MON_PEND_Msk (0x1UL << DCB_DEMCR_MON_PEND_Pos) /*!< DCB DEMCR: Monitor pend Mask */ + +#define DCB_DEMCR_MON_EN_Pos 16U /*!< DCB DEMCR: Monitor enable Position */ +#define DCB_DEMCR_MON_EN_Msk (0x1UL << DCB_DEMCR_MON_EN_Pos) /*!< DCB DEMCR: Monitor enable Mask */ + +#define DCB_DEMCR_VC_SFERR_Pos 11U /*!< DCB DEMCR: Vector Catch SecureFault Position */ +#define DCB_DEMCR_VC_SFERR_Msk (0x1UL << DCB_DEMCR_VC_SFERR_Pos) /*!< DCB DEMCR: Vector Catch SecureFault Mask */ + +#define DCB_DEMCR_VC_HARDERR_Pos 10U /*!< DCB DEMCR: Vector Catch HardFault errors Position */ +#define DCB_DEMCR_VC_HARDERR_Msk (0x1UL << DCB_DEMCR_VC_HARDERR_Pos) /*!< DCB DEMCR: Vector Catch HardFault errors Mask */ + +#define DCB_DEMCR_VC_INTERR_Pos 9U /*!< DCB DEMCR: Vector Catch interrupt errors Position */ +#define DCB_DEMCR_VC_INTERR_Msk (0x1UL << DCB_DEMCR_VC_INTERR_Pos) /*!< DCB DEMCR: Vector Catch interrupt errors Mask */ + +#define DCB_DEMCR_VC_BUSERR_Pos 8U /*!< DCB DEMCR: Vector Catch BusFault errors Position */ +#define DCB_DEMCR_VC_BUSERR_Msk (0x1UL << DCB_DEMCR_VC_BUSERR_Pos) /*!< DCB DEMCR: Vector Catch BusFault errors Mask */ + +#define DCB_DEMCR_VC_STATERR_Pos 7U /*!< DCB DEMCR: Vector Catch state errors Position */ +#define DCB_DEMCR_VC_STATERR_Msk (0x1UL << DCB_DEMCR_VC_STATERR_Pos) /*!< DCB DEMCR: Vector Catch state errors Mask */ + +#define DCB_DEMCR_VC_CHKERR_Pos 6U /*!< DCB DEMCR: Vector Catch check errors Position */ +#define DCB_DEMCR_VC_CHKERR_Msk (0x1UL << DCB_DEMCR_VC_CHKERR_Pos) /*!< DCB DEMCR: Vector Catch check errors Mask */ + +#define DCB_DEMCR_VC_NOCPERR_Pos 5U /*!< DCB DEMCR: Vector Catch NOCP errors Position */ +#define DCB_DEMCR_VC_NOCPERR_Msk (0x1UL << DCB_DEMCR_VC_NOCPERR_Pos) /*!< DCB DEMCR: Vector Catch NOCP errors Mask */ + +#define DCB_DEMCR_VC_MMERR_Pos 4U /*!< DCB DEMCR: Vector Catch MemManage errors Position */ +#define DCB_DEMCR_VC_MMERR_Msk (0x1UL << DCB_DEMCR_VC_MMERR_Pos) /*!< DCB DEMCR: Vector Catch MemManage errors Mask */ + +#define DCB_DEMCR_VC_CORERESET_Pos 0U /*!< DCB DEMCR: Vector Catch Core reset Position */ +#define DCB_DEMCR_VC_CORERESET_Msk (0x1UL /*<< DCB_DEMCR_VC_CORERESET_Pos*/) /*!< DCB DEMCR: Vector Catch Core reset Mask */ + +/* DSCEMCR, Debug Set Clear Exception and Monitor Control Register Definitions */ +#define DCB_DSCEMCR_CLR_MON_REQ_Pos 19U /*!< DCB DSCEMCR: Clear monitor request Position */ +#define DCB_DSCEMCR_CLR_MON_REQ_Msk (0x1UL << DCB_DSCEMCR_CLR_MON_REQ_Pos) /*!< DCB DSCEMCR: Clear monitor request Mask */ + +#define DCB_DSCEMCR_CLR_MON_PEND_Pos 17U /*!< DCB DSCEMCR: Clear monitor pend Position */ +#define DCB_DSCEMCR_CLR_MON_PEND_Msk (0x1UL << DCB_DSCEMCR_CLR_MON_PEND_Pos) /*!< DCB DSCEMCR: Clear monitor pend Mask */ + +#define DCB_DSCEMCR_SET_MON_REQ_Pos 3U /*!< DCB DSCEMCR: Set monitor request Position */ +#define DCB_DSCEMCR_SET_MON_REQ_Msk (0x1UL << DCB_DSCEMCR_SET_MON_REQ_Pos) /*!< DCB DSCEMCR: Set monitor request Mask */ + +#define DCB_DSCEMCR_SET_MON_PEND_Pos 1U /*!< DCB DSCEMCR: Set monitor pend Position */ +#define DCB_DSCEMCR_SET_MON_PEND_Msk (0x1UL << DCB_DSCEMCR_SET_MON_PEND_Pos) /*!< DCB DSCEMCR: Set monitor pend Mask */ + +/* DAUTHCTRL, Debug Authentication Control Register Definitions */ +#define DCB_DAUTHCTRL_UIDEN_Pos 10U /*!< DCB DAUTHCTRL: Unprivileged Invasive Debug Enable Position */ +#define DCB_DAUTHCTRL_UIDEN_Msk (0x1UL << DCB_DAUTHCTRL_UIDEN_Pos) /*!< DCB DAUTHCTRL: Unprivileged Invasive Debug Enable Mask */ + +#define DCB_DAUTHCTRL_UIDAPEN_Pos 9U /*!< DCB DAUTHCTRL: Unprivileged Invasive DAP Access Enable Position */ +#define DCB_DAUTHCTRL_UIDAPEN_Msk (0x1UL << DCB_DAUTHCTRL_UIDAPEN_Pos) /*!< DCB DAUTHCTRL: Unprivileged Invasive DAP Access Enable Mask */ + +#define DCB_DAUTHCTRL_FSDMA_Pos 8U /*!< DCB DAUTHCTRL: Force Secure DebugMonitor Allowed Position */ +#define DCB_DAUTHCTRL_FSDMA_Msk (0x1UL << DCB_DAUTHCTRL_FSDMA_Pos) /*!< DCB DAUTHCTRL: Force Secure DebugMonitor Allowed Mask */ + +#define DCB_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPNIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPNIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPNIDENSEL_Msk (0x1UL << DCB_DAUTHCTRL_SPNIDENSEL_Pos) /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Mask */ + +#define DCB_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< DCB DAUTHCTRL: Secure invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPIDENSEL_Msk (0x1UL /*<< DCB_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< DCB DAUTHCTRL: Secure invasive debug enable select Mask */ + +/* DSCSR, Debug Security Control and Status Register Definitions */ +#define DCB_DSCSR_CDSKEY_Pos 17U /*!< DCB DSCSR: CDS write-enable key Position */ +#define DCB_DSCSR_CDSKEY_Msk (0x1UL << DCB_DSCSR_CDSKEY_Pos) /*!< DCB DSCSR: CDS write-enable key Mask */ + +#define DCB_DSCSR_CDS_Pos 16U /*!< DCB DSCSR: Current domain Secure Position */ +#define DCB_DSCSR_CDS_Msk (0x1UL << DCB_DSCSR_CDS_Pos) /*!< DCB DSCSR: Current domain Secure Mask */ + +#define DCB_DSCSR_SBRSEL_Pos 1U /*!< DCB DSCSR: Secure banked register select Position */ +#define DCB_DSCSR_SBRSEL_Msk (0x1UL << DCB_DSCSR_SBRSEL_Pos) /*!< DCB DSCSR: Secure banked register select Mask */ + +#define DCB_DSCSR_SBRSELEN_Pos 0U /*!< DCB DSCSR: Secure banked register select enable Position */ +#define DCB_DSCSR_SBRSELEN_Msk (0x1UL /*<< DCB_DSCSR_SBRSELEN_Pos*/) /*!< DCB DSCSR: Secure banked register select enable Mask */ + +/*@} end of group CMSIS_DCB */ + + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DIB Debug Identification Block + \brief Type definitions for the Debug Identification Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Identification Block Registers (DIB). + */ +typedef struct +{ + __OM uint32_t DLAR; /*!< Offset: 0x000 ( /W) SCS Software Lock Access Register */ + __IM uint32_t DLSR; /*!< Offset: 0x004 (R/ ) SCS Software Lock Status Register */ + __IM uint32_t DAUTHSTATUS; /*!< Offset: 0x008 (R/ ) Debug Authentication Status Register */ + __IM uint32_t DDEVARCH; /*!< Offset: 0x00C (R/ ) SCS Device Architecture Register */ + __IM uint32_t DDEVTYPE; /*!< Offset: 0x010 (R/ ) SCS Device Type Register */ +} DIB_Type; + +/* DLAR, SCS Software Lock Access Register Definitions */ +#define DIB_DLAR_KEY_Pos 0U /*!< DIB DLAR: KEY Position */ +#define DIB_DLAR_KEY_Msk (0xFFFFFFFFUL /*<< DIB_DLAR_KEY_Pos */) /*!< DIB DLAR: KEY Mask */ + +/* DLSR, SCS Software Lock Status Register Definitions */ +#define DIB_DLSR_nTT_Pos 2U /*!< DIB DLSR: Not thirty-two bit Position */ +#define DIB_DLSR_nTT_Msk (0x1UL << DIB_DLSR_nTT_Pos ) /*!< DIB DLSR: Not thirty-two bit Mask */ + +#define DIB_DLSR_SLK_Pos 1U /*!< DIB DLSR: Software Lock status Position */ +#define DIB_DLSR_SLK_Msk (0x1UL << DIB_DLSR_SLK_Pos ) /*!< DIB DLSR: Software Lock status Mask */ + +#define DIB_DLSR_SLI_Pos 0U /*!< DIB DLSR: Software Lock implemented Position */ +#define DIB_DLSR_SLI_Msk (0x1UL /*<< DIB_DLSR_SLI_Pos*/) /*!< DIB DLSR: Software Lock implemented Mask */ + +/* DAUTHSTATUS, Debug Authentication Status Register Definitions */ +#define DIB_DAUTHSTATUS_SUNID_Pos 22U /*!< DIB DAUTHSTATUS: Secure Unprivileged Non-invasive Debug Allowed Position */ +#define DIB_DAUTHSTATUS_SUNID_Msk (0x3UL << DIB_DAUTHSTATUS_SUNID_Pos ) /*!< DIB DAUTHSTATUS: Secure Unprivileged Non-invasive Debug Allowed Mask */ + +#define DIB_DAUTHSTATUS_SUID_Pos 20U /*!< DIB DAUTHSTATUS: Secure Unprivileged Invasive Debug Allowed Position */ +#define DIB_DAUTHSTATUS_SUID_Msk (0x3UL << DIB_DAUTHSTATUS_SUID_Pos ) /*!< DIB DAUTHSTATUS: Secure Unprivileged Invasive Debug Allowed Mask */ + +#define DIB_DAUTHSTATUS_NSUNID_Pos 18U /*!< DIB DAUTHSTATUS: Non-secure Unprivileged Non-invasive Debug Allo Position */ +#define DIB_DAUTHSTATUS_NSUNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSUNID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Unprivileged Non-invasive Debug Allo Mask */ + +#define DIB_DAUTHSTATUS_NSUID_Pos 16U /*!< DIB DAUTHSTATUS: Non-secure Unprivileged Invasive Debug Allowed Position */ +#define DIB_DAUTHSTATUS_NSUID_Msk (0x3UL << DIB_DAUTHSTATUS_NSUID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Unprivileged Invasive Debug Allowed Mask */ + +#define DIB_DAUTHSTATUS_SNID_Pos 6U /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_SNID_Msk (0x3UL << DIB_DAUTHSTATUS_SNID_Pos ) /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_SID_Pos 4U /*!< DIB DAUTHSTATUS: Secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_SID_Msk (0x3UL << DIB_DAUTHSTATUS_SID_Pos ) /*!< DIB DAUTHSTATUS: Secure Invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSNID_Pos 2U /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSNID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSID_Pos 0U /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSID_Msk (0x3UL /*<< DIB_DAUTHSTATUS_NSID_Pos*/) /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Mask */ + +/* DDEVARCH, SCS Device Architecture Register Definitions */ +#define DIB_DDEVARCH_ARCHITECT_Pos 21U /*!< DIB DDEVARCH: Architect Position */ +#define DIB_DDEVARCH_ARCHITECT_Msk (0x7FFUL << DIB_DDEVARCH_ARCHITECT_Pos ) /*!< DIB DDEVARCH: Architect Mask */ + +#define DIB_DDEVARCH_PRESENT_Pos 20U /*!< DIB DDEVARCH: DEVARCH Present Position */ +#define DIB_DDEVARCH_PRESENT_Msk (0x1FUL << DIB_DDEVARCH_PRESENT_Pos ) /*!< DIB DDEVARCH: DEVARCH Present Mask */ + +#define DIB_DDEVARCH_REVISION_Pos 16U /*!< DIB DDEVARCH: Revision Position */ +#define DIB_DDEVARCH_REVISION_Msk (0xFUL << DIB_DDEVARCH_REVISION_Pos ) /*!< DIB DDEVARCH: Revision Mask */ + +#define DIB_DDEVARCH_ARCHVER_Pos 12U /*!< DIB DDEVARCH: Architecture Version Position */ +#define DIB_DDEVARCH_ARCHVER_Msk (0xFUL << DIB_DDEVARCH_ARCHVER_Pos ) /*!< DIB DDEVARCH: Architecture Version Mask */ + +#define DIB_DDEVARCH_ARCHPART_Pos 0U /*!< DIB DDEVARCH: Architecture Part Position */ +#define DIB_DDEVARCH_ARCHPART_Msk (0xFFFUL /*<< DIB_DDEVARCH_ARCHPART_Pos*/) /*!< DIB DDEVARCH: Architecture Part Mask */ + +/* DDEVTYPE, SCS Device Type Register Definitions */ +#define DIB_DDEVTYPE_SUB_Pos 4U /*!< DIB DDEVTYPE: Sub-type Position */ +#define DIB_DDEVTYPE_SUB_Msk (0xFUL << DIB_DDEVTYPE_SUB_Pos ) /*!< DIB DDEVTYPE: Sub-type Mask */ + +#define DIB_DDEVTYPE_MAJOR_Pos 0U /*!< DIB DDEVTYPE: Major type Position */ +#define DIB_DDEVTYPE_MAJOR_Msk (0xFUL /*<< DIB_DDEVTYPE_MAJOR_Pos*/) /*!< DIB DDEVTYPE: Major type Mask */ + + +/*@} end of group CMSIS_DIB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define MEMSYSCTL_BASE (0xE001E000UL) /*!< Memory System Control Base Address */ + #define ERRBNK_BASE (0xE001E100UL) /*!< Error Banking Base Address */ + #define PWRMODCTL_BASE (0xE001E300UL) /*!< Power Mode Control Base Address */ + #define EWIC_BASE (0xE001E400UL) /*!< External Wakeup Interrupt Controller Base Address */ + #define PRCCFGINF_BASE (0xE001E700UL) /*!< Processor Configuration Information Base Address */ + #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ + #define CoreDebug_BASE (0xE000EDF0UL) /*!< \deprecated Core Debug Base Address */ + #define DCB_BASE (0xE000EDF0UL) /*!< DCB Base Address */ + #define DIB_BASE (0xE000EFB0UL) /*!< DIB Base Address */ + #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + #define ICB ((ICB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ + #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ + #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ + #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ + #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ + #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ + #define MEMSYSCTL ((MemSysCtl_Type *) MEMSYSCTL_BASE ) /*!< Memory System Control configuration struct */ + #define ERRBNK ((ErrBnk_Type *) ERRBNK_BASE ) /*!< Error Banking configuration struct */ + #define PWRMODCTL ((PwrModCtl_Type *) PWRMODCTL_BASE ) /*!< Power Mode Control configuration struct */ + #define EWIC ((EWIC_Type *) EWIC_BASE ) /*!< EWIC configuration struct */ + #define PRCCFGINF ((PrcCfgInf_Type *) PRCCFGINF_BASE ) /*!< Processor Configuration Information configuration struct */ + #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< \deprecated Core Debug configuration struct */ + #define DCB ((DCB_Type *) DCB_BASE ) /*!< DCB configuration struct */ + #define DIB ((DIB_Type *) DIB_BASE ) /*!< DIB configuration struct */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ + #endif + + #if defined (__PMU_PRESENT) && (__PMU_PRESENT == 1U) + #define PMU_BASE (0xE0003000UL) /*!< PMU Base Address */ + #define PMU ((PMU_Type *) PMU_BASE ) /*!< PMU configuration struct */ + #endif + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ + #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ + #endif + + #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ + #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ + #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< \deprecated Core Debug Base Address (non-secure address space) */ + #define DCB_BASE_NS (0xE002EDF0UL) /*!< DCB Base Address (non-secure address space) */ + #define DIB_BASE_NS (0xE002EFB0UL) /*!< DIB Base Address (non-secure address space) */ + #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ + #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ + #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + + #define ICB_NS ((ICB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */ + #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ + #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ + #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ + #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< \deprecated Core Debug configuration struct (non-secure address space) */ + #define DCB_NS ((DCB_Type *) DCB_BASE_NS ) /*!< DCB configuration struct (non-secure address space) */ + #define DIB_NS ((DIB_Type *) DIB_BASE_NS ) /*!< DIB configuration struct (non-secure address space) */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ + #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ + #endif + + #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */ + #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */ + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_register_aliases Backwards Compatibility Aliases + \brief Register alias definitions for backwards compatibility. + @{ + */ + +/*@} */ + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* Special LR values for Secure/Non-Secure call handling and exception handling */ + +/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ +#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ + +/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ +#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ +#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ +#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ +#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ +#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ +#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */ +#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ + +/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ +#else +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ +#endif + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + __DSB(); +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Priority Grouping (non-secure) + \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB_NS->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB_NS->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping (non-secure) + \details Reads the priority grouping field from the non-secure NVIC when in secure state. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void) +{ + return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv8.h" + +#endif + +/* ########################## PMU functions and events #################################### */ + +#if defined (__PMU_PRESENT) && (__PMU_PRESENT == 1U) + +#include "pmu_armv8.h" + +/** + \brief Cortex-M85 PMU events + \note Architectural PMU events can be found in pmu_armv8.h +*/ + +#define ARMCM85_PMU_ECC_ERR 0xC000 /*!< One or more Error Correcting Code (ECC) errors detected */ +#define ARMCM85_PMU_ECC_ERR_MBIT 0xC001 /*!< One or more multi-bit ECC errors detected */ +#define ARMCM85_PMU_ECC_ERR_DCACHE 0xC010 /*!< One or more ECC errors in the data cache */ +#define ARMCM85_PMU_ECC_ERR_ICACHE 0xC011 /*!< One or more ECC errors in the instruction cache */ +#define ARMCM85_PMU_ECC_ERR_MBIT_DCACHE 0xC012 /*!< One or more multi-bit ECC errors in the data cache */ +#define ARMCM85_PMU_ECC_ERR_MBIT_ICACHE 0xC013 /*!< One or more multi-bit ECC errors in the instruction cache */ +#define ARMCM85_PMU_ECC_ERR_DTCM 0xC020 /*!< One or more ECC errors in the Data Tightly Coupled Memory (DTCM) */ +#define ARMCM85_PMU_ECC_ERR_ITCM 0xC021 /*!< One or more ECC errors in the Instruction Tightly Coupled Memory (ITCM) */ +#define ARMCM85_PMU_ECC_ERR_MBIT_DTCM 0xC022 /*!< One or more multi-bit ECC errors in the DTCM */ +#define ARMCM85_PMU_ECC_ERR_MBIT_ITCM 0xC023 /*!< One or more multi-bit ECC errors in the ITCM */ +#define ARMCM85_PMU_PF_LINEFILL 0xC100 /*!< The prefetcher starts a line-fill */ +#define ARMCM85_PMU_PF_CANCEL 0xC101 /*!< The prefetcher stops prefetching */ +#define ARMCM85_PMU_PF_DROP_LINEFILL 0xC102 /*!< A linefill triggered by a prefetcher has been dropped because of lack of buffering */ +#define ARMCM85_PMU_NWAMODE_ENTER 0xC200 /*!< No write-allocate mode entry */ +#define ARMCM85_PMU_NWAMODE 0xC201 /*!< Write-allocate store is not allocated into the data cache due to no-write-allocate mode */ +#define ARMCM85_PMU_SAHB_ACCESS 0xC300 /*!< Read or write access on the S-AHB interface to the TCM */ +#define ARMCM85_PMU_PAHB_ACCESS 0xC301 /*!< Read or write access on the P-AHB write interface */ +#define ARMCM85_PMU_AXI_WRITE_ACCESS 0xC302 /*!< Any beat access to M-AXI write interface */ +#define ARMCM85_PMU_AXI_READ_ACCESS 0xC303 /*!< Any beat access to M-AXI read interface */ +#define ARMCM85_PMU_DOSTIMEOUT_DOUBLE 0xC400 /*!< Denial of Service timeout has fired twice and caused buffers to drain to allow forward progress */ +#define ARMCM85_PMU_DOSTIMEOUT_TRIPLE 0xC401 /*!< Denial of Service timeout has fired three times and blocked the LSU to force forward progress */ + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = FPU->MVFR0; + if ((mvfr0 & (FPU_MVFR0_FPSP_Msk | FPU_MVFR0_FPDP_Msk)) == 0x220U) + { + return 2U; /* Double + Single precision FPU */ + } + else if ((mvfr0 & (FPU_MVFR0_FPSP_Msk | FPU_MVFR0_FPDP_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + +/* ########################## MVE functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_MveFunctions MVE Functions + \brief Function that provides MVE type. + @{ + */ + +/** + \brief get MVE type + \details returns the MVE type + \returns + - \b 0: No Vector Extension (MVE) + - \b 1: Integer Vector Extension (MVE-I) + - \b 2: Floating-point Vector Extension (MVE-F) + */ +__STATIC_INLINE uint32_t SCB_GetMVEType(void) +{ + const uint32_t mvfr1 = FPU->MVFR1; + if ((mvfr1 & FPU_MVFR1_MVE_Msk) == (0x2U << FPU_MVFR1_MVE_Pos)) + { + return 2U; + } + else if ((mvfr1 & FPU_MVFR1_MVE_Msk) == (0x1U << FPU_MVFR1_MVE_Pos)) + { + return 1U; + } + else + { + return 0U; + } +} + + +/*@} end of CMSIS_Core_MveFunctions */ + + +/* ########################## Cache functions #################################### */ + +#if ((defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)) || \ + (defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U))) +#include "cachel1_armv7.h" +#endif + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + +/* ################### PAC Key functions ########################### */ + +#if (defined (__ARM_FEATURE_PAUTH) && (__ARM_FEATURE_PAUTH == 1)) +#include "pac_armv81.h" +#endif + + +/* ################################## Debug Control function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DCBFunctions Debug Control Functions + \brief Functions that access the Debug Control Block. + @{ + */ + + +/** + \brief Set Debug Authentication Control Register + \details writes to Debug Authentication Control register. + \param [in] value value to be writen. + */ +__STATIC_INLINE void DCB_SetAuthCtrl(uint32_t value) +{ + __DSB(); + __ISB(); + DCB->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register + \details Reads Debug Authentication Control register. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t DCB_GetAuthCtrl(void) +{ + return (DCB->DAUTHCTRL); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Debug Authentication Control Register (non-secure) + \details writes to non-secure Debug Authentication Control register when in secure state. + \param [in] value value to be writen + */ +__STATIC_INLINE void TZ_DCB_SetAuthCtrl_NS(uint32_t value) +{ + __DSB(); + __ISB(); + DCB_NS->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register (non-secure) + \details Reads non-secure Debug Authentication Control register when in secure state. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t TZ_DCB_GetAuthCtrl_NS(void) +{ + return (DCB_NS->DAUTHCTRL); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## Debug Identification function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DIBFunctions Debug Identification Functions + \brief Functions that access the Debug Identification Block. + @{ + */ + + +/** + \brief Get Debug Authentication Status Register + \details Reads Debug Authentication Status register. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t DIB_GetAuthStatus(void) +{ + return (DIB->DAUTHSTATUS); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Debug Authentication Status Register (non-secure) + \details Reads non-secure Debug Authentication Status register when in secure state. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t TZ_DIB_GetAuthStatus_NS(void) +{ + return (DIB_NS->DAUTHSTATUS); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM85_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/CMSIS/Core/Include/core_sc000.h b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/CMSIS/Core/Include/core_sc000.h new file mode 100644 index 0000000000..e252068ce6 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/CMSIS/Core/Include/core_sc000.h @@ -0,0 +1,1030 @@ +/**************************************************************************//** + * @file core_sc000.h + * @brief CMSIS SC000 Core Peripheral Access Layer Header File + * @version V5.0.7 + * @date 27. March 2020 + ******************************************************************************/ +/* + * Copyright (c) 2009-2020 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_SC000_H_GENERIC +#define __CORE_SC000_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup SC000 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS SC000 definitions */ +#define __SC000_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __SC000_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __SC000_CMSIS_VERSION ((__SC000_CMSIS_VERSION_MAIN << 16U) | \ + __SC000_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_SC (000U) /*!< Cortex secure core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_SC000_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_SC000_H_DEPENDANT +#define __CORE_SC000_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __SC000_REV + #define __SC000_REV 0x0000U + #warning "__SC000_REV not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 0U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group SC000 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core MPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t _reserved0:1; /*!< bit: 0 Reserved */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[31U]; + __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[31U]; + __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[31U]; + __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[31U]; + uint32_t RESERVED4[64U]; + __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED0[1U]; + __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + uint32_t RESERVED1[154U]; + __IOM uint32_t SFCR; /*!< Offset: 0x290 (R/W) Security Features Control Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ +} MPU_Type; + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 8U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief SC000 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. + Therefore they are not covered by the SC000 header file. + @{ + */ +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else +/*#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping not available for SC000 */ +/*#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping not available for SC000 */ + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ +/*#define NVIC_GetActive __NVIC_GetActive not available for SC000 */ + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ + + +/* Interrupt Priorities are WORD accessible only under Armv6-M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + /* ARM Application Note 321 states that the M0 and M0+ do not require the architectural barrier - assume SC000 is the same */ +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_SC000_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/CMSIS/Core/Include/core_sc300.h b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/CMSIS/Core/Include/core_sc300.h new file mode 100644 index 0000000000..d66621031e --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/CMSIS/Core/Include/core_sc300.h @@ -0,0 +1,1917 @@ +/**************************************************************************//** + * @file core_sc300.h + * @brief CMSIS SC300 Core Peripheral Access Layer Header File + * @version V5.0.10 + * @date 04. June 2021 + ******************************************************************************/ +/* + * Copyright (c) 2009-2021 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_SC300_H_GENERIC +#define __CORE_SC300_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup SC3000 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS SC300 definitions */ +#define __SC300_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __SC300_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __SC300_CMSIS_VERSION ((__SC300_CMSIS_VERSION_MAIN << 16U) | \ + __SC300_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_SC (300U) /*!< Cortex secure core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_SC300_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_SC300_H_DEPENDANT +#define __CORE_SC300_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __SC300_REV + #define __SC300_REV 0x0000U + #warning "__SC300_REV not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 1U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group SC300 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:1; /*!< bit: 9 Reserved */ + uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */ + uint32_t _reserved1:8; /*!< bit: 16..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit */ + uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */ +#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */ +#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24U]; + __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RESERVED1[24U]; + __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24U]; + __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24U]; + __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56U]; + __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[5U]; + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + uint32_t RESERVED1[129U]; + __IOM uint32_t SFCR; /*!< Offset: 0x290 (R/W) Security Features Control Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLBASE_Pos 29U /*!< SCB VTOR: TBLBASE Position */ +#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */ + +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_CFSR_MEMFAULTSR_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ +#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR: DISDEFWBUF Position */ +#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ + +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x1UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x1UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY2_Pos 0U /*!< TPI ITATBCTR2: ATREADY2 Position */ +#define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/) /*!< TPI ITATBCTR2: ATREADY2 Mask */ + +#define TPI_ITATBCTR2_ATREADY1_Pos 0U /*!< TPI ITATBCTR2: ATREADY1 Position */ +#define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/) /*!< TPI ITATBCTR2: ATREADY1 Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x1UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x1UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY2_Pos 0U /*!< TPI ITATBCTR0: ATREADY2 Position */ +#define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/) /*!< TPI ITATBCTR0: ATREADY2 Mask */ + +#define TPI_ITATBCTR0_ATREADY1_Pos 0U /*!< TPI ITATBCTR0: ATREADY1 Position */ +#define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/) /*!< TPI ITATBCTR0: ATREADY1 Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + /* ARM Application Note 321 states that the M3 does not require the architectural barrier */ +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_SC300_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/CMSIS/Core/Include/core_starmc1.h b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/CMSIS/Core/Include/core_starmc1.h new file mode 100644 index 0000000000..ebc0f77eb7 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/CMSIS/Core/Include/core_starmc1.h @@ -0,0 +1,3592 @@ +/**************************************************************************//** + * @file core_starmc1.h + * @brief CMSIS ArmChina STAR-MC1 Core Peripheral Access Layer Header File + * @version V1.0.2 + * @date 07. April 2022 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. + * Copyright (c) 2018-2022 Arm China. + * All rights reserved. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#elif defined ( __GNUC__ ) + #pragma GCC diagnostic ignored "-Wpedantic" /* disable pedantic warning due to unnamed structs/unions */ +#endif + +#ifndef __CORE_STAR_H_GENERIC +#define __CORE_STAR_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup STAR-MC1 + @{ + */ + +#include "cmsis_version.h" + +/* Macro Define for STAR-MC1 */ +#define __STAR_MC (1U) /*!< STAR-MC Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined (__TARGET_FPU_VFP) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined (__ARM_FP) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined (__ARMVFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined (__TI_VFP_SUPPORT__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined (__FPU_VFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_STAR_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_STAR_H_DEPENDANT +#define __CORE_STAR_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __STAR_REV + #define __STAR_REV 0x0000U + #warning "__STAR_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DSP_PRESENT + #define __DSP_PRESENT 0U + #warning "__DSP_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __ICACHE_PRESENT + #define __ICACHE_PRESENT 0U + #warning "__ICACHE_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DCACHE_PRESENT + #define __DCACHE_PRESENT 0U + #warning "__DCACHE_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DTCM_PRESENT + #define __DTCM_PRESENT 0U + #warning "__DTCM_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group STAR-MC1 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core SAU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for STAR-MC1 processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ +#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */ + uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */ + uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */ +#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */ + +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED6[580U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ID_ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[1U]; + __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ + __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ + __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ + __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */ + uint32_t RESERVED_ADD1[21U]; + __IOM uint32_t SFSR; /*!< Offset: 0x0E4 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x0E8 (R/W) Secure Fault Address Register */ + uint32_t RESERVED3[69U]; + __OM uint32_t STIR; /*!< Offset: F00-D00=0x200 ( /W) Software Triggered Interrupt Register */ + uint32_t RESERVED4[15U]; + __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ + uint32_t RESERVED5[1U]; + __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ + uint32_t RESERVED6[1U]; + __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ + __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ + __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ + __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ + __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ + __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ + __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ + __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ +} SCB_Type; + +typedef struct +{ + __IOM uint32_t CACR; /*!< Offset: 0x0 (R/W) L1 Cache Control Register */ + __IOM uint32_t ITCMCR; /*!< Offset: 0x10 (R/W) Instruction Tightly-Coupled Memory Control Register */ + __IOM uint32_t DTCMCR; /*!< Offset: 0x14 (R/W) Data Tightly-Coupled Memory Control Registers */ +}EMSS_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ +#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */ +#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */ +#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */ + +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */ +#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_CFSR_MEMFAULTSR_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */ +#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/* SCB Non-Secure Access Control Register Definitions */ +#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */ +#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */ + +#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */ +#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */ + +#define SCB_NSACR_CPn_Pos 0U /*!< SCB NSACR: CPn Position */ +#define SCB_NSACR_CPn_Msk (1UL /*<< SCB_NSACR_CPn_Pos*/) /*!< SCB NSACR: CPn Mask */ + +/* SCB Cache Level ID Register Definitions */ +#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ +#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ + +#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ +#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ + +#define SCB_CLIDR_IC_Pos 0U /*!< SCB CLIDR: IC Position */ +#define SCB_CLIDR_IC_Msk (1UL << SCB_CLIDR_IC_Pos) /*!< SCB CLIDR: IC Mask */ + +#define SCB_CLIDR_DC_Pos 1U /*!< SCB CLIDR: DC Position */ +#define SCB_CLIDR_DC_Msk (1UL << SCB_CLIDR_DC_Pos) /*!< SCB CLIDR: DC Mask */ + + + +/* SCB Cache Type Register Definitions */ +#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ +#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ + +#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ +#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ + +#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ +#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ + +#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ +#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ + +#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ +#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ + +/* SCB Cache Size ID Register Definitions */ +#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ +#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ + +#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ +#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ + +#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ +#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ + +#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ +#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ + +#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ +#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ + +#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ +#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ + +#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ +#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ + +/* SCB Cache Size Selection Register Definitions */ +#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ +#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ + +#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ +#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ + +/* SCB Software Triggered Interrupt Register Definitions */ +#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ +#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ + +/* SCB D-Cache line Invalidate by Set-way Register Definitions */ +#define SCB_DCISW_LEVEL_Pos 1U /*!< SCB DCISW: Level Position */ +#define SCB_DCISW_LEVEL_Msk (7UL << SCB_DCISW_LEVEL_Pos) /*!< SCB DCISW: Level Mask */ + +#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ +#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ + +#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ +#define SCB_DCISW_SET_Msk (0xFFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ + +/* SCB D-Cache Clean line by Set-way Register Definitions */ +#define SCB_DCCSW_LEVEL_Pos 1U /*!< SCB DCCSW: Level Position */ +#define SCB_DCCSW_LEVEL_Msk (7UL << SCB_DCCSW_LEVEL_Pos) /*!< SCB DCCSW: Level Mask */ + +#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ +#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ + +#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ +#define SCB_DCCSW_SET_Msk (0xFFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ + +/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ +#define SCB_DCCISW_LEVEL_Pos 1U /*!< SCB DCCISW: Level Position */ +#define SCB_DCCISW_LEVEL_Msk (7UL << SCB_DCCISW_LEVEL_Pos) /*!< SCB DCCISW: Level Mask */ + +#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ +#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ + +#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ +#define SCB_DCCISW_SET_Msk (0xFFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ + +/* ArmChina: Implementation Defined */ +/* Instruction Tightly-Coupled Memory Control Register Definitions */ +#define SCB_ITCMCR_SZ_Pos 3U /*!< SCB ITCMCR: SZ Position */ +#define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) /*!< SCB ITCMCR: SZ Mask */ + +#define SCB_ITCMCR_EN_Pos 0U /*!< SCB ITCMCR: EN Position */ +#define SCB_ITCMCR_EN_Msk (1UL /*<< SCB_ITCMCR_EN_Pos*/) /*!< SCB ITCMCR: EN Mask */ + +/* Data Tightly-Coupled Memory Control Register Definitions */ +#define SCB_DTCMCR_SZ_Pos 3U /*!< SCB DTCMCR: SZ Position */ +#define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) /*!< SCB DTCMCR: SZ Mask */ + +#define SCB_DTCMCR_EN_Pos 0U /*!< SCB DTCMCR: EN Position */ +#define SCB_DTCMCR_EN_Msk (1UL /*<< SCB_DTCMCR_EN_Pos*/) /*!< SCB DTCMCR: EN Mask */ + +/* L1 Cache Control Register Definitions */ +#define SCB_CACR_DCCLEAN_Pos 16U /*!< SCB CACR: DCCLEAN Position */ +#define SCB_CACR_DCCLEAN_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: DCCLEAN Mask */ + +#define SCB_CACR_ICACTIVE_Pos 13U /*!< SCB CACR: ICACTIVE Position */ +#define SCB_CACR_ICACTIVE_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: ICACTIVE Mask */ + +#define SCB_CACR_DCACTIVE_Pos 12U /*!< SCB CACR: DCACTIVE Position */ +#define SCB_CACR_DCACTIVE_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: DCACTIVE Mask */ + +#define SCB_CACR_FORCEWT_Pos 2U /*!< SCB CACR: FORCEWT Position */ +#define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: FORCEWT Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ + __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */ + uint32_t RESERVED6[4U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Stimulus Port Register Definitions */ +#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */ +#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */ + +#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */ +#define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */ + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */ +#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */ + +#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */ +#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED14[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED15[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED16[1U]; + __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ + uint32_t RESERVED17[1U]; + __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ + uint32_t RESERVED18[1U]; + __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ + uint32_t RESERVED19[1U]; + __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ + uint32_t RESERVED20[1U]; + __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ + uint32_t RESERVED21[1U]; + __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ + uint32_t RESERVED22[1U]; + __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ + uint32_t RESERVED23[1U]; + __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ + uint32_t RESERVED24[1U]; + __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ + uint32_t RESERVED25[1U]; + __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ + uint32_t RESERVED26[1U]; + __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ + uint32_t RESERVED27[1U]; + __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ + uint32_t RESERVED28[1U]; + __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ + uint32_t RESERVED29[1U]; + __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ + uint32_t RESERVED30[1U]; + __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ + uint32_t RESERVED31[1U]; + __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ + uint32_t RESERVED32[934U]; + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ + uint32_t RESERVED33[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */ +#define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t ITFTTD0; /*!< Offset: 0xEEC (R/ ) Integration Test FIFO Test Data 0 Register */ + __IOM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/W) Integration Test ATB Control Register 2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) Integration Test ATB Control Register 0 */ + __IM uint32_t ITFTTD1; /*!< Offset: 0xEFC (R/ ) Integration Test FIFO Test Data 1 Register */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) Device Configuration Register */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Identifier Register */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ +#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration Test FIFO Test Data 0 Register Definitions */ +#define TPI_ITFTTD0_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD0: ATB Interface 2 ATVALIDPosition */ +#define TPI_ITFTTD0_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 2 ATVALID Mask */ + +#define TPI_ITFTTD0_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD0: ATB Interface 2 byte count Position */ +#define TPI_ITFTTD0_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 2 byte count Mask */ + +#define TPI_ITFTTD0_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Position */ +#define TPI_ITFTTD0_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Mask */ + +#define TPI_ITFTTD0_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD0: ATB Interface 1 byte count Position */ +#define TPI_ITFTTD0_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 1 byte countt Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data2_Pos 16U /*!< TPI ITFTTD0: ATB Interface 1 data2 Position */ +#define TPI_ITFTTD0_ATB_IF1_data2_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data2 Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data1_Pos 8U /*!< TPI ITFTTD0: ATB Interface 1 data1 Position */ +#define TPI_ITFTTD0_ATB_IF1_data1_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data1 Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data0_Pos 0U /*!< TPI ITFTTD0: ATB Interface 1 data0 Position */ +#define TPI_ITFTTD0_ATB_IF1_data0_Msk (0xFFUL /*<< TPI_ITFTTD0_ATB_IF1_data0_Pos*/) /*!< TPI ITFTTD0: ATB Interface 1 data0 Mask */ + +/* TPI Integration Test ATB Control Register 2 Register Definitions */ +#define TPI_ITATBCTR2_AFVALID2S_Pos 1U /*!< TPI ITATBCTR2: AFVALID2S Position */ +#define TPI_ITATBCTR2_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID2S_Pos) /*!< TPI ITATBCTR2: AFVALID2SS Mask */ + +#define TPI_ITATBCTR2_AFVALID1S_Pos 1U /*!< TPI ITATBCTR2: AFVALID1S Position */ +#define TPI_ITATBCTR2_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID1S_Pos) /*!< TPI ITATBCTR2: AFVALID1SS Mask */ + +#define TPI_ITATBCTR2_ATREADY2S_Pos 0U /*!< TPI ITATBCTR2: ATREADY2S Position */ +#define TPI_ITATBCTR2_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2S_Pos*/) /*!< TPI ITATBCTR2: ATREADY2S Mask */ + +#define TPI_ITATBCTR2_ATREADY1S_Pos 0U /*!< TPI ITATBCTR2: ATREADY1S Position */ +#define TPI_ITATBCTR2_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1S_Pos*/) /*!< TPI ITATBCTR2: ATREADY1S Mask */ + +/* TPI Integration Test FIFO Test Data 1 Register Definitions */ +#define TPI_ITFTTD1_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Position */ +#define TPI_ITFTTD1_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Mask */ + +#define TPI_ITFTTD1_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD1: ATB Interface 2 byte count Position */ +#define TPI_ITFTTD1_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 2 byte count Mask */ + +#define TPI_ITFTTD1_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Position */ +#define TPI_ITFTTD1_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Mask */ + +#define TPI_ITFTTD1_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD1: ATB Interface 1 byte count Position */ +#define TPI_ITFTTD1_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 1 byte countt Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data2_Pos 16U /*!< TPI ITFTTD1: ATB Interface 2 data2 Position */ +#define TPI_ITFTTD1_ATB_IF2_data2_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data2 Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data1_Pos 8U /*!< TPI ITFTTD1: ATB Interface 2 data1 Position */ +#define TPI_ITFTTD1_ATB_IF2_data1_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data1 Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data0_Pos 0U /*!< TPI ITFTTD1: ATB Interface 2 data0 Position */ +#define TPI_ITFTTD1_ATB_IF2_data0_Msk (0xFFUL /*<< TPI_ITFTTD1_ATB_IF2_data0_Pos*/) /*!< TPI ITFTTD1: ATB Interface 2 data0 Mask */ + +/* TPI Integration Test ATB Control Register 0 Definitions */ +#define TPI_ITATBCTR0_AFVALID2S_Pos 1U /*!< TPI ITATBCTR0: AFVALID2S Position */ +#define TPI_ITATBCTR0_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID2S_Pos) /*!< TPI ITATBCTR0: AFVALID2SS Mask */ + +#define TPI_ITATBCTR0_AFVALID1S_Pos 1U /*!< TPI ITATBCTR0: AFVALID1S Position */ +#define TPI_ITATBCTR0_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID1S_Pos) /*!< TPI ITATBCTR0: AFVALID1SS Mask */ + +#define TPI_ITATBCTR0_ATREADY2S_Pos 0U /*!< TPI ITATBCTR0: ATREADY2S Position */ +#define TPI_ITATBCTR0_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2S_Pos*/) /*!< TPI ITATBCTR0: ATREADY2S Mask */ + +#define TPI_ITATBCTR0_ATREADY1S_Pos 0U /*!< TPI ITATBCTR0: ATREADY1S Position */ +#define TPI_ITATBCTR0_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1S_Pos*/) /*!< TPI ITATBCTR0: ATREADY1S Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFOSZ Position */ +#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFOSZ Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x3FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */ + __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */ + __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */ + __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */ + uint32_t RESERVED0[1]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ +#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/* MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */ + +/* MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/* MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#else + uint32_t RESERVED0[3]; +#endif + __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */ +} SAU_Type; + +/* SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/* SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/* SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/* SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/* SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/* Secure Fault Status Register Definitions */ +#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */ +#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */ + +#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */ +#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */ + +#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */ +#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */ + +#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */ +#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */ + +#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */ +#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */ + +#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */ +#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */ + +#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */ +#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */ + +#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */ +#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and VFP Feature Register 2 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */ +#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */ + +#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */ +#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */ + +#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */ +#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */ + +#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */ +#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */ + +#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */ +#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */ + +#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */ +#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */ +#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */ +#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and VFP Feature Register 0 Definitions */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and VFP Feature Register 1 Definitions */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/* Media and VFP Feature Register 2 Definitions */ +#define FPU_MVFR2_FPMisc_Pos 4U /*!< MVFR2: FPMisc bits Position */ +#define FPU_MVFR2_FPMisc_Msk (0xFUL << FPU_MVFR2_FPMisc_Pos) /*!< MVFR2: FPMisc bits Mask */ + +/*@} end of group CMSIS_FPU */ + + + + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DCB Debug Control Block + \brief Type definitions for the Debug Control Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Control Block Registers (DCB). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED0[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} DCB_Type; + +/* DHCSR, Debug Halting Control and Status Register Definitions */ +#define DCB_DHCSR_DBGKEY_Pos 16U /*!< DCB DHCSR: Debug key Position */ +#define DCB_DHCSR_DBGKEY_Msk (0xFFFFUL << DCB_DHCSR_DBGKEY_Pos) /*!< DCB DHCSR: Debug key Mask */ + +#define DCB_DHCSR_S_RESTART_ST_Pos 26U /*!< DCB DHCSR: Restart sticky status Position */ +#define DCB_DHCSR_S_RESTART_ST_Msk (0x1UL << DCB_DHCSR_S_RESTART_ST_Pos) /*!< DCB DHCSR: Restart sticky status Mask */ + +#define DCB_DHCSR_S_RESET_ST_Pos 25U /*!< DCB DHCSR: Reset sticky status Position */ +#define DCB_DHCSR_S_RESET_ST_Msk (0x1UL << DCB_DHCSR_S_RESET_ST_Pos) /*!< DCB DHCSR: Reset sticky status Mask */ + +#define DCB_DHCSR_S_RETIRE_ST_Pos 24U /*!< DCB DHCSR: Retire sticky status Position */ +#define DCB_DHCSR_S_RETIRE_ST_Msk (0x1UL << DCB_DHCSR_S_RETIRE_ST_Pos) /*!< DCB DHCSR: Retire sticky status Mask */ + +#define DCB_DHCSR_S_SDE_Pos 20U /*!< DCB DHCSR: Secure debug enabled Position */ +#define DCB_DHCSR_S_SDE_Msk (0x1UL << DCB_DHCSR_S_SDE_Pos) /*!< DCB DHCSR: Secure debug enabled Mask */ + +#define DCB_DHCSR_S_LOCKUP_Pos 19U /*!< DCB DHCSR: Lockup status Position */ +#define DCB_DHCSR_S_LOCKUP_Msk (0x1UL << DCB_DHCSR_S_LOCKUP_Pos) /*!< DCB DHCSR: Lockup status Mask */ + +#define DCB_DHCSR_S_SLEEP_Pos 18U /*!< DCB DHCSR: Sleeping status Position */ +#define DCB_DHCSR_S_SLEEP_Msk (0x1UL << DCB_DHCSR_S_SLEEP_Pos) /*!< DCB DHCSR: Sleeping status Mask */ + +#define DCB_DHCSR_S_HALT_Pos 17U /*!< DCB DHCSR: Halted status Position */ +#define DCB_DHCSR_S_HALT_Msk (0x1UL << DCB_DHCSR_S_HALT_Pos) /*!< DCB DHCSR: Halted status Mask */ + +#define DCB_DHCSR_S_REGRDY_Pos 16U /*!< DCB DHCSR: Register ready status Position */ +#define DCB_DHCSR_S_REGRDY_Msk (0x1UL << DCB_DHCSR_S_REGRDY_Pos) /*!< DCB DHCSR: Register ready status Mask */ + +#define DCB_DHCSR_C_SNAPSTALL_Pos 5U /*!< DCB DHCSR: Snap stall control Position */ +#define DCB_DHCSR_C_SNAPSTALL_Msk (0x1UL << DCB_DHCSR_C_SNAPSTALL_Pos) /*!< DCB DHCSR: Snap stall control Mask */ + +#define DCB_DHCSR_C_MASKINTS_Pos 3U /*!< DCB DHCSR: Mask interrupts control Position */ +#define DCB_DHCSR_C_MASKINTS_Msk (0x1UL << DCB_DHCSR_C_MASKINTS_Pos) /*!< DCB DHCSR: Mask interrupts control Mask */ + +#define DCB_DHCSR_C_STEP_Pos 2U /*!< DCB DHCSR: Step control Position */ +#define DCB_DHCSR_C_STEP_Msk (0x1UL << DCB_DHCSR_C_STEP_Pos) /*!< DCB DHCSR: Step control Mask */ + +#define DCB_DHCSR_C_HALT_Pos 1U /*!< DCB DHCSR: Halt control Position */ +#define DCB_DHCSR_C_HALT_Msk (0x1UL << DCB_DHCSR_C_HALT_Pos) /*!< DCB DHCSR: Halt control Mask */ + +#define DCB_DHCSR_C_DEBUGEN_Pos 0U /*!< DCB DHCSR: Debug enable control Position */ +#define DCB_DHCSR_C_DEBUGEN_Msk (0x1UL /*<< DCB_DHCSR_C_DEBUGEN_Pos*/) /*!< DCB DHCSR: Debug enable control Mask */ + +/* DCRSR, Debug Core Register Select Register Definitions */ +#define DCB_DCRSR_REGWnR_Pos 16U /*!< DCB DCRSR: Register write/not-read Position */ +#define DCB_DCRSR_REGWnR_Msk (0x1UL << DCB_DCRSR_REGWnR_Pos) /*!< DCB DCRSR: Register write/not-read Mask */ + +#define DCB_DCRSR_REGSEL_Pos 0U /*!< DCB DCRSR: Register selector Position */ +#define DCB_DCRSR_REGSEL_Msk (0x7FUL /*<< DCB_DCRSR_REGSEL_Pos*/) /*!< DCB DCRSR: Register selector Mask */ + +/* DCRDR, Debug Core Register Data Register Definitions */ +#define DCB_DCRDR_DBGTMP_Pos 0U /*!< DCB DCRDR: Data temporary buffer Position */ +#define DCB_DCRDR_DBGTMP_Msk (0xFFFFFFFFUL /*<< DCB_DCRDR_DBGTMP_Pos*/) /*!< DCB DCRDR: Data temporary buffer Mask */ + +/* DEMCR, Debug Exception and Monitor Control Register Definitions */ +#define DCB_DEMCR_TRCENA_Pos 24U /*!< DCB DEMCR: Trace enable Position */ +#define DCB_DEMCR_TRCENA_Msk (0x1UL << DCB_DEMCR_TRCENA_Pos) /*!< DCB DEMCR: Trace enable Mask */ + +#define DCB_DEMCR_MONPRKEY_Pos 23U /*!< DCB DEMCR: Monitor pend req key Position */ +#define DCB_DEMCR_MONPRKEY_Msk (0x1UL << DCB_DEMCR_MONPRKEY_Pos) /*!< DCB DEMCR: Monitor pend req key Mask */ + +#define DCB_DEMCR_UMON_EN_Pos 21U /*!< DCB DEMCR: Unprivileged monitor enable Position */ +#define DCB_DEMCR_UMON_EN_Msk (0x1UL << DCB_DEMCR_UMON_EN_Pos) /*!< DCB DEMCR: Unprivileged monitor enable Mask */ + +#define DCB_DEMCR_SDME_Pos 20U /*!< DCB DEMCR: Secure DebugMonitor enable Position */ +#define DCB_DEMCR_SDME_Msk (0x1UL << DCB_DEMCR_SDME_Pos) /*!< DCB DEMCR: Secure DebugMonitor enable Mask */ + +#define DCB_DEMCR_MON_REQ_Pos 19U /*!< DCB DEMCR: Monitor request Position */ +#define DCB_DEMCR_MON_REQ_Msk (0x1UL << DCB_DEMCR_MON_REQ_Pos) /*!< DCB DEMCR: Monitor request Mask */ + +#define DCB_DEMCR_MON_STEP_Pos 18U /*!< DCB DEMCR: Monitor step Position */ +#define DCB_DEMCR_MON_STEP_Msk (0x1UL << DCB_DEMCR_MON_STEP_Pos) /*!< DCB DEMCR: Monitor step Mask */ + +#define DCB_DEMCR_MON_PEND_Pos 17U /*!< DCB DEMCR: Monitor pend Position */ +#define DCB_DEMCR_MON_PEND_Msk (0x1UL << DCB_DEMCR_MON_PEND_Pos) /*!< DCB DEMCR: Monitor pend Mask */ + +#define DCB_DEMCR_MON_EN_Pos 16U /*!< DCB DEMCR: Monitor enable Position */ +#define DCB_DEMCR_MON_EN_Msk (0x1UL << DCB_DEMCR_MON_EN_Pos) /*!< DCB DEMCR: Monitor enable Mask */ + +#define DCB_DEMCR_VC_SFERR_Pos 11U /*!< DCB DEMCR: Vector Catch SecureFault Position */ +#define DCB_DEMCR_VC_SFERR_Msk (0x1UL << DCB_DEMCR_VC_SFERR_Pos) /*!< DCB DEMCR: Vector Catch SecureFault Mask */ + +#define DCB_DEMCR_VC_HARDERR_Pos 10U /*!< DCB DEMCR: Vector Catch HardFault errors Position */ +#define DCB_DEMCR_VC_HARDERR_Msk (0x1UL << DCB_DEMCR_VC_HARDERR_Pos) /*!< DCB DEMCR: Vector Catch HardFault errors Mask */ + +#define DCB_DEMCR_VC_INTERR_Pos 9U /*!< DCB DEMCR: Vector Catch interrupt errors Position */ +#define DCB_DEMCR_VC_INTERR_Msk (0x1UL << DCB_DEMCR_VC_INTERR_Pos) /*!< DCB DEMCR: Vector Catch interrupt errors Mask */ + +#define DCB_DEMCR_VC_BUSERR_Pos 8U /*!< DCB DEMCR: Vector Catch BusFault errors Position */ +#define DCB_DEMCR_VC_BUSERR_Msk (0x1UL << DCB_DEMCR_VC_BUSERR_Pos) /*!< DCB DEMCR: Vector Catch BusFault errors Mask */ + +#define DCB_DEMCR_VC_STATERR_Pos 7U /*!< DCB DEMCR: Vector Catch state errors Position */ +#define DCB_DEMCR_VC_STATERR_Msk (0x1UL << DCB_DEMCR_VC_STATERR_Pos) /*!< DCB DEMCR: Vector Catch state errors Mask */ + +#define DCB_DEMCR_VC_CHKERR_Pos 6U /*!< DCB DEMCR: Vector Catch check errors Position */ +#define DCB_DEMCR_VC_CHKERR_Msk (0x1UL << DCB_DEMCR_VC_CHKERR_Pos) /*!< DCB DEMCR: Vector Catch check errors Mask */ + +#define DCB_DEMCR_VC_NOCPERR_Pos 5U /*!< DCB DEMCR: Vector Catch NOCP errors Position */ +#define DCB_DEMCR_VC_NOCPERR_Msk (0x1UL << DCB_DEMCR_VC_NOCPERR_Pos) /*!< DCB DEMCR: Vector Catch NOCP errors Mask */ + +#define DCB_DEMCR_VC_MMERR_Pos 4U /*!< DCB DEMCR: Vector Catch MemManage errors Position */ +#define DCB_DEMCR_VC_MMERR_Msk (0x1UL << DCB_DEMCR_VC_MMERR_Pos) /*!< DCB DEMCR: Vector Catch MemManage errors Mask */ + +#define DCB_DEMCR_VC_CORERESET_Pos 0U /*!< DCB DEMCR: Vector Catch Core reset Position */ +#define DCB_DEMCR_VC_CORERESET_Msk (0x1UL /*<< DCB_DEMCR_VC_CORERESET_Pos*/) /*!< DCB DEMCR: Vector Catch Core reset Mask */ + +/* DAUTHCTRL, Debug Authentication Control Register Definitions */ +#define DCB_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPNIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPNIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPNIDENSEL_Msk (0x1UL << DCB_DAUTHCTRL_SPNIDENSEL_Pos) /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Mask */ + +#define DCB_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< DCB DAUTHCTRL: Secure invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPIDENSEL_Msk (0x1UL /*<< DCB_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< DCB DAUTHCTRL: Secure invasive debug enable select Mask */ + +/* DSCSR, Debug Security Control and Status Register Definitions */ +#define DCB_DSCSR_CDSKEY_Pos 17U /*!< DCB DSCSR: CDS write-enable key Position */ +#define DCB_DSCSR_CDSKEY_Msk (0x1UL << DCB_DSCSR_CDSKEY_Pos) /*!< DCB DSCSR: CDS write-enable key Mask */ + +#define DCB_DSCSR_CDS_Pos 16U /*!< DCB DSCSR: Current domain Secure Position */ +#define DCB_DSCSR_CDS_Msk (0x1UL << DCB_DSCSR_CDS_Pos) /*!< DCB DSCSR: Current domain Secure Mask */ + +#define DCB_DSCSR_SBRSEL_Pos 1U /*!< DCB DSCSR: Secure banked register select Position */ +#define DCB_DSCSR_SBRSEL_Msk (0x1UL << DCB_DSCSR_SBRSEL_Pos) /*!< DCB DSCSR: Secure banked register select Mask */ + +#define DCB_DSCSR_SBRSELEN_Pos 0U /*!< DCB DSCSR: Secure banked register select enable Position */ +#define DCB_DSCSR_SBRSELEN_Msk (0x1UL /*<< DCB_DSCSR_SBRSELEN_Pos*/) /*!< DCB DSCSR: Secure banked register select enable Mask */ + +/*@} end of group CMSIS_DCB */ + + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DIB Debug Identification Block + \brief Type definitions for the Debug Identification Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Identification Block Registers (DIB). + */ +typedef struct +{ + __OM uint32_t DLAR; /*!< Offset: 0x000 ( /W) SCS Software Lock Access Register */ + __IM uint32_t DLSR; /*!< Offset: 0x004 (R/ ) SCS Software Lock Status Register */ + __IM uint32_t DAUTHSTATUS; /*!< Offset: 0x008 (R/ ) Debug Authentication Status Register */ + __IM uint32_t DDEVARCH; /*!< Offset: 0x00C (R/ ) SCS Device Architecture Register */ + __IM uint32_t DDEVTYPE; /*!< Offset: 0x010 (R/ ) SCS Device Type Register */ +} DIB_Type; + +/* DLAR, SCS Software Lock Access Register Definitions */ +#define DIB_DLAR_KEY_Pos 0U /*!< DIB DLAR: KEY Position */ +#define DIB_DLAR_KEY_Msk (0xFFFFFFFFUL /*<< DIB_DLAR_KEY_Pos */) /*!< DIB DLAR: KEY Mask */ + +/* DLSR, SCS Software Lock Status Register Definitions */ +#define DIB_DLSR_nTT_Pos 2U /*!< DIB DLSR: Not thirty-two bit Position */ +#define DIB_DLSR_nTT_Msk (0x1UL << DIB_DLSR_nTT_Pos ) /*!< DIB DLSR: Not thirty-two bit Mask */ + +#define DIB_DLSR_SLK_Pos 1U /*!< DIB DLSR: Software Lock status Position */ +#define DIB_DLSR_SLK_Msk (0x1UL << DIB_DLSR_SLK_Pos ) /*!< DIB DLSR: Software Lock status Mask */ + +#define DIB_DLSR_SLI_Pos 0U /*!< DIB DLSR: Software Lock implemented Position */ +#define DIB_DLSR_SLI_Msk (0x1UL /*<< DIB_DLSR_SLI_Pos*/) /*!< DIB DLSR: Software Lock implemented Mask */ + +/* DAUTHSTATUS, Debug Authentication Status Register Definitions */ +#define DIB_DAUTHSTATUS_SNID_Pos 6U /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_SNID_Msk (0x3UL << DIB_DAUTHSTATUS_SNID_Pos ) /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_SID_Pos 4U /*!< DIB DAUTHSTATUS: Secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_SID_Msk (0x3UL << DIB_DAUTHSTATUS_SID_Pos ) /*!< DIB DAUTHSTATUS: Secure Invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSNID_Pos 2U /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSNID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSID_Pos 0U /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSID_Msk (0x3UL /*<< DIB_DAUTHSTATUS_NSID_Pos*/) /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Mask */ + +/* DDEVARCH, SCS Device Architecture Register Definitions */ +#define DIB_DDEVARCH_ARCHITECT_Pos 21U /*!< DIB DDEVARCH: Architect Position */ +#define DIB_DDEVARCH_ARCHITECT_Msk (0x7FFUL << DIB_DDEVARCH_ARCHITECT_Pos ) /*!< DIB DDEVARCH: Architect Mask */ + +#define DIB_DDEVARCH_PRESENT_Pos 20U /*!< DIB DDEVARCH: DEVARCH Present Position */ +#define DIB_DDEVARCH_PRESENT_Msk (0x1FUL << DIB_DDEVARCH_PRESENT_Pos ) /*!< DIB DDEVARCH: DEVARCH Present Mask */ + +#define DIB_DDEVARCH_REVISION_Pos 16U /*!< DIB DDEVARCH: Revision Position */ +#define DIB_DDEVARCH_REVISION_Msk (0xFUL << DIB_DDEVARCH_REVISION_Pos ) /*!< DIB DDEVARCH: Revision Mask */ + +#define DIB_DDEVARCH_ARCHVER_Pos 12U /*!< DIB DDEVARCH: Architecture Version Position */ +#define DIB_DDEVARCH_ARCHVER_Msk (0xFUL << DIB_DDEVARCH_ARCHVER_Pos ) /*!< DIB DDEVARCH: Architecture Version Mask */ + +#define DIB_DDEVARCH_ARCHPART_Pos 0U /*!< DIB DDEVARCH: Architecture Part Position */ +#define DIB_DDEVARCH_ARCHPART_Msk (0xFFFUL /*<< DIB_DDEVARCH_ARCHPART_Pos*/) /*!< DIB DDEVARCH: Architecture Part Mask */ + +/* DDEVTYPE, SCS Device Type Register Definitions */ +#define DIB_DDEVTYPE_SUB_Pos 4U /*!< DIB DDEVTYPE: Sub-type Position */ +#define DIB_DDEVTYPE_SUB_Msk (0xFUL << DIB_DDEVTYPE_SUB_Pos ) /*!< DIB DDEVTYPE: Sub-type Mask */ + +#define DIB_DDEVTYPE_MAJOR_Pos 0U /*!< DIB DDEVTYPE: Major type Position */ +#define DIB_DDEVTYPE_MAJOR_Msk (0xFUL /*<< DIB_DDEVTYPE_MAJOR_Pos*/) /*!< DIB DDEVTYPE: Major type Mask */ + + +/*@} end of group CMSIS_DIB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ + #define DCB_BASE (0xE000EDF0UL) /*!< DCB Base Address */ + #define DIB_BASE (0xE000EFB0UL) /*!< DIB Base Address */ + #define EMSS_BASE (0xE001E000UL) /*!AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + __DSB(); +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses including + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/** + \brief Software Reset + \details Initiates a system reset request to reset the CPU. + */ +__NO_RETURN __STATIC_INLINE void __SW_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses including + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_BFHFNMINS_Msk) | /* Keep BFHFNMINS unchanged. Use this Reset function in case your case need to keep it */ + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | /* Keep priority group unchanged */ + SCB_AIRCR_SYSRESETREQ_Msk ); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Priority Grouping (non-secure) + \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB_NS->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB_NS->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping (non-secure) + \details Reads the priority grouping field from the non-secure NVIC when in secure state. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void) +{ + return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv8.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = FPU->MVFR0; + if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U) + { + return 2U; /* Double + Single precision FPU */ + } + else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + +/* ################################## Debug Control function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DCBFunctions Debug Control Functions + \brief Functions that access the Debug Control Block. + @{ + */ + + +/** + \brief Set Debug Authentication Control Register + \details writes to Debug Authentication Control register. + \param [in] value value to be writen. + */ +__STATIC_INLINE void DCB_SetAuthCtrl(uint32_t value) +{ + __DSB(); + __ISB(); + DCB->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register + \details Reads Debug Authentication Control register. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t DCB_GetAuthCtrl(void) +{ + return (DCB->DAUTHCTRL); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Debug Authentication Control Register (non-secure) + \details writes to non-secure Debug Authentication Control register when in secure state. + \param [in] value value to be writen + */ +__STATIC_INLINE void TZ_DCB_SetAuthCtrl_NS(uint32_t value) +{ + __DSB(); + __ISB(); + DCB_NS->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register (non-secure) + \details Reads non-secure Debug Authentication Control register when in secure state. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t TZ_DCB_GetAuthCtrl_NS(void) +{ + return (DCB_NS->DAUTHCTRL); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## Debug Identification function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DIBFunctions Debug Identification Functions + \brief Functions that access the Debug Identification Block. + @{ + */ + + +/** + \brief Get Debug Authentication Status Register + \details Reads Debug Authentication Status register. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t DIB_GetAuthStatus(void) +{ + return (DIB->DAUTHSTATUS); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Debug Authentication Status Register (non-secure) + \details Reads non-secure Debug Authentication Status register when in secure state. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t TZ_DIB_GetAuthStatus_NS(void) +{ + return (DIB_NS->DAUTHSTATUS); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + +#if ((defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)) || \ + (defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U))) + +/* ########################## Cache functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_CacheFunctions Cache Functions + \brief Functions that configure Instruction and Data cache. + @{ + */ + +/* Cache Size ID Register Macros */ +#define CCSIDR_WAYS(x) (((x) & SCB_CCSIDR_ASSOCIATIVITY_Msk) >> SCB_CCSIDR_ASSOCIATIVITY_Pos) +#define CCSIDR_SETS(x) (((x) & SCB_CCSIDR_NUMSETS_Msk ) >> SCB_CCSIDR_NUMSETS_Pos ) + +#define __SCB_DCACHE_LINE_SIZE 32U /*!< STAR-MC1 cache line size is fixed to 32 bytes (8 words). See also register SCB_CCSIDR */ +#define __SCB_ICACHE_LINE_SIZE 32U /*!< STAR-MC1 cache line size is fixed to 32 bytes (8 words). See also register SCB_CCSIDR */ + +/** + \brief Enable I-Cache + \details Turns on I-Cache + */ +__STATIC_FORCEINLINE void SCB_EnableICache (void) +{ + #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) + if (SCB->CCR & SCB_CCR_IC_Msk) return; /* return if ICache is already enabled */ + + __DSB(); + __ISB(); + SCB->ICIALLU = 0UL; /* invalidate I-Cache */ + __DSB(); + __ISB(); + SCB->CCR |= (uint32_t)SCB_CCR_IC_Msk; /* enable I-Cache */ + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Disable I-Cache + \details Turns off I-Cache + */ +__STATIC_FORCEINLINE void SCB_DisableICache (void) +{ + #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) + __DSB(); + __ISB(); + SCB->CCR &= ~(uint32_t)SCB_CCR_IC_Msk; /* disable I-Cache */ + SCB->ICIALLU = 0UL; /* invalidate I-Cache */ + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Invalidate I-Cache + \details Invalidates I-Cache + */ +__STATIC_FORCEINLINE void SCB_InvalidateICache (void) +{ + #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) + __DSB(); + __ISB(); + SCB->ICIALLU = 0UL; + __DSB(); + __ISB(); + #endif +} + + +/** + \brief I-Cache Invalidate by address + \details Invalidates I-Cache for the given address. + I-Cache is invalidated starting from a 32 byte aligned address in 32 byte granularity. + I-Cache memory blocks which are part of given address + given size are invalidated. + \param[in] addr address + \param[in] isize size of memory block (in number of bytes) +*/ +__STATIC_FORCEINLINE void SCB_InvalidateICache_by_Addr (void *addr, int32_t isize) +{ + #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) + if ( isize > 0 ) { + int32_t op_size = isize + (((uint32_t)addr) & (__SCB_ICACHE_LINE_SIZE - 1U)); + uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_ICACHE_LINE_SIZE - 1U) */; + + __DSB(); + + do { + SCB->ICIMVAU = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */ + op_addr += __SCB_ICACHE_LINE_SIZE; + op_size -= __SCB_ICACHE_LINE_SIZE; + } while ( op_size > 0 ); + + __DSB(); + __ISB(); + } + #endif +} + + +/** + \brief Enable D-Cache + \details Turns on D-Cache + */ +__STATIC_FORCEINLINE void SCB_EnableDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + if (SCB->CCR & SCB_CCR_DC_Msk) return; /* return if DCache is already enabled */ + + SCB->CSSELR = 0U; /* select Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) | + ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + __DSB(); + + SCB->CCR |= (uint32_t)SCB_CCR_DC_Msk; /* enable D-Cache */ + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Disable D-Cache + \details Turns off D-Cache + */ +__STATIC_FORCEINLINE void SCB_DisableDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /* select Level 1 data cache */ + __DSB(); + + SCB->CCR &= ~(uint32_t)SCB_CCR_DC_Msk; /* disable D-Cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* clean & invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) | + ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Invalidate D-Cache + \details Invalidates D-Cache + */ +__STATIC_FORCEINLINE void SCB_InvalidateDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /* select Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) | + ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Clean D-Cache + \details Cleans D-Cache + */ +__STATIC_FORCEINLINE void SCB_CleanDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /* select Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* clean D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCCSW = (((sets << SCB_DCCSW_SET_Pos) & SCB_DCCSW_SET_Msk) | + ((ways << SCB_DCCSW_WAY_Pos) & SCB_DCCSW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Clean & Invalidate D-Cache + \details Cleans and Invalidates D-Cache + */ +__STATIC_FORCEINLINE void SCB_CleanInvalidateDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /* select Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* clean & invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) | + ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief D-Cache Invalidate by address + \details Invalidates D-Cache for the given address. + D-Cache is invalidated starting from a 32 byte aligned address in 32 byte granularity. + D-Cache memory blocks which are part of given address + given size are invalidated. + \param[in] addr address + \param[in] dsize size of memory block (in number of bytes) +*/ +__STATIC_FORCEINLINE void SCB_InvalidateDCache_by_Addr (void *addr, int32_t dsize) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + if ( dsize > 0 ) { + int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U)); + uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */; + + __DSB(); + + do { + SCB->DCIMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */ + op_addr += __SCB_DCACHE_LINE_SIZE; + op_size -= __SCB_DCACHE_LINE_SIZE; + } while ( op_size > 0 ); + + __DSB(); + __ISB(); + } + #endif +} + + +/** + \brief D-Cache Clean by address + \details Cleans D-Cache for the given address + D-Cache is cleaned starting from a 32 byte aligned address in 32 byte granularity. + D-Cache memory blocks which are part of given address + given size are cleaned. + \param[in] addr address + \param[in] dsize size of memory block (in number of bytes) +*/ +__STATIC_FORCEINLINE void SCB_CleanDCache_by_Addr (uint32_t *addr, int32_t dsize) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + if ( dsize > 0 ) { + int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U)); + uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */; + + __DSB(); + + do { + SCB->DCCMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */ + op_addr += __SCB_DCACHE_LINE_SIZE; + op_size -= __SCB_DCACHE_LINE_SIZE; + } while ( op_size > 0 ); + + __DSB(); + __ISB(); + } + #endif +} + + +/** + \brief D-Cache Clean and Invalidate by address + \details Cleans and invalidates D_Cache for the given address + D-Cache is cleaned and invalidated starting from a 32 byte aligned address in 32 byte granularity. + D-Cache memory blocks which are part of given address + given size are cleaned and invalidated. + \param[in] addr address (aligned to 32-byte boundary) + \param[in] dsize size of memory block (in number of bytes) +*/ +__STATIC_FORCEINLINE void SCB_CleanInvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + if ( dsize > 0 ) { + int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U)); + uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */; + + __DSB(); + + do { + SCB->DCCIMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */ + op_addr += __SCB_DCACHE_LINE_SIZE; + op_size -= __SCB_DCACHE_LINE_SIZE; + } while ( op_size > 0 ); + + __DSB(); + __ISB(); + } + #endif +} + +/*@} end of CMSIS_Core_CacheFunctions */ +#endif + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_STAR_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/CMSIS/Core/Include/mpu_armv7.h b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/CMSIS/Core/Include/mpu_armv7.h new file mode 100644 index 0000000000..9909f83990 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/CMSIS/Core/Include/mpu_armv7.h @@ -0,0 +1,275 @@ +/****************************************************************************** + * @file mpu_armv7.h + * @brief CMSIS MPU API for Armv7-M MPU + * @version V5.1.2 + * @date 25. May 2020 + ******************************************************************************/ +/* + * Copyright (c) 2017-2020 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef ARM_MPU_ARMV7_H +#define ARM_MPU_ARMV7_H + +#define ARM_MPU_REGION_SIZE_32B ((uint8_t)0x04U) ///!< MPU Region Size 32 Bytes +#define ARM_MPU_REGION_SIZE_64B ((uint8_t)0x05U) ///!< MPU Region Size 64 Bytes +#define ARM_MPU_REGION_SIZE_128B ((uint8_t)0x06U) ///!< MPU Region Size 128 Bytes +#define ARM_MPU_REGION_SIZE_256B ((uint8_t)0x07U) ///!< MPU Region Size 256 Bytes +#define ARM_MPU_REGION_SIZE_512B ((uint8_t)0x08U) ///!< MPU Region Size 512 Bytes +#define ARM_MPU_REGION_SIZE_1KB ((uint8_t)0x09U) ///!< MPU Region Size 1 KByte +#define ARM_MPU_REGION_SIZE_2KB ((uint8_t)0x0AU) ///!< MPU Region Size 2 KBytes +#define ARM_MPU_REGION_SIZE_4KB ((uint8_t)0x0BU) ///!< MPU Region Size 4 KBytes +#define ARM_MPU_REGION_SIZE_8KB ((uint8_t)0x0CU) ///!< MPU Region Size 8 KBytes +#define ARM_MPU_REGION_SIZE_16KB ((uint8_t)0x0DU) ///!< MPU Region Size 16 KBytes +#define ARM_MPU_REGION_SIZE_32KB ((uint8_t)0x0EU) ///!< MPU Region Size 32 KBytes +#define ARM_MPU_REGION_SIZE_64KB ((uint8_t)0x0FU) ///!< MPU Region Size 64 KBytes +#define ARM_MPU_REGION_SIZE_128KB ((uint8_t)0x10U) ///!< MPU Region Size 128 KBytes +#define ARM_MPU_REGION_SIZE_256KB ((uint8_t)0x11U) ///!< MPU Region Size 256 KBytes +#define ARM_MPU_REGION_SIZE_512KB ((uint8_t)0x12U) ///!< MPU Region Size 512 KBytes +#define ARM_MPU_REGION_SIZE_1MB ((uint8_t)0x13U) ///!< MPU Region Size 1 MByte +#define ARM_MPU_REGION_SIZE_2MB ((uint8_t)0x14U) ///!< MPU Region Size 2 MBytes +#define ARM_MPU_REGION_SIZE_4MB ((uint8_t)0x15U) ///!< MPU Region Size 4 MBytes +#define ARM_MPU_REGION_SIZE_8MB ((uint8_t)0x16U) ///!< MPU Region Size 8 MBytes +#define ARM_MPU_REGION_SIZE_16MB ((uint8_t)0x17U) ///!< MPU Region Size 16 MBytes +#define ARM_MPU_REGION_SIZE_32MB ((uint8_t)0x18U) ///!< MPU Region Size 32 MBytes +#define ARM_MPU_REGION_SIZE_64MB ((uint8_t)0x19U) ///!< MPU Region Size 64 MBytes +#define ARM_MPU_REGION_SIZE_128MB ((uint8_t)0x1AU) ///!< MPU Region Size 128 MBytes +#define ARM_MPU_REGION_SIZE_256MB ((uint8_t)0x1BU) ///!< MPU Region Size 256 MBytes +#define ARM_MPU_REGION_SIZE_512MB ((uint8_t)0x1CU) ///!< MPU Region Size 512 MBytes +#define ARM_MPU_REGION_SIZE_1GB ((uint8_t)0x1DU) ///!< MPU Region Size 1 GByte +#define ARM_MPU_REGION_SIZE_2GB ((uint8_t)0x1EU) ///!< MPU Region Size 2 GBytes +#define ARM_MPU_REGION_SIZE_4GB ((uint8_t)0x1FU) ///!< MPU Region Size 4 GBytes + +#define ARM_MPU_AP_NONE 0U ///!< MPU Access Permission no access +#define ARM_MPU_AP_PRIV 1U ///!< MPU Access Permission privileged access only +#define ARM_MPU_AP_URO 2U ///!< MPU Access Permission unprivileged access read-only +#define ARM_MPU_AP_FULL 3U ///!< MPU Access Permission full access +#define ARM_MPU_AP_PRO 5U ///!< MPU Access Permission privileged access read-only +#define ARM_MPU_AP_RO 6U ///!< MPU Access Permission read-only access + +/** MPU Region Base Address Register Value +* +* \param Region The region to be configured, number 0 to 15. +* \param BaseAddress The base address for the region. +*/ +#define ARM_MPU_RBAR(Region, BaseAddress) \ + (((BaseAddress) & MPU_RBAR_ADDR_Msk) | \ + ((Region) & MPU_RBAR_REGION_Msk) | \ + (MPU_RBAR_VALID_Msk)) + +/** +* MPU Memory Access Attributes +* +* \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral. +* \param IsShareable Region is shareable between multiple bus masters. +* \param IsCacheable Region is cacheable, i.e. its value may be kept in cache. +* \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy. +*/ +#define ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable) \ + ((((TypeExtField) << MPU_RASR_TEX_Pos) & MPU_RASR_TEX_Msk) | \ + (((IsShareable) << MPU_RASR_S_Pos) & MPU_RASR_S_Msk) | \ + (((IsCacheable) << MPU_RASR_C_Pos) & MPU_RASR_C_Msk) | \ + (((IsBufferable) << MPU_RASR_B_Pos) & MPU_RASR_B_Msk)) + +/** +* MPU Region Attribute and Size Register Value +* +* \param DisableExec Instruction access disable bit, 1= disable instruction fetches. +* \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode. +* \param AccessAttributes Memory access attribution, see \ref ARM_MPU_ACCESS_. +* \param SubRegionDisable Sub-region disable field. +* \param Size Region size of the region to be configured, for example 4K, 8K. +*/ +#define ARM_MPU_RASR_EX(DisableExec, AccessPermission, AccessAttributes, SubRegionDisable, Size) \ + ((((DisableExec) << MPU_RASR_XN_Pos) & MPU_RASR_XN_Msk) | \ + (((AccessPermission) << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk) | \ + (((AccessAttributes) & (MPU_RASR_TEX_Msk | MPU_RASR_S_Msk | MPU_RASR_C_Msk | MPU_RASR_B_Msk))) | \ + (((SubRegionDisable) << MPU_RASR_SRD_Pos) & MPU_RASR_SRD_Msk) | \ + (((Size) << MPU_RASR_SIZE_Pos) & MPU_RASR_SIZE_Msk) | \ + (((MPU_RASR_ENABLE_Msk)))) + +/** +* MPU Region Attribute and Size Register Value +* +* \param DisableExec Instruction access disable bit, 1= disable instruction fetches. +* \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode. +* \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral. +* \param IsShareable Region is shareable between multiple bus masters. +* \param IsCacheable Region is cacheable, i.e. its value may be kept in cache. +* \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy. +* \param SubRegionDisable Sub-region disable field. +* \param Size Region size of the region to be configured, for example 4K, 8K. +*/ +#define ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable, SubRegionDisable, Size) \ + ARM_MPU_RASR_EX(DisableExec, AccessPermission, ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable), SubRegionDisable, Size) + +/** +* MPU Memory Access Attribute for strongly ordered memory. +* - TEX: 000b +* - Shareable +* - Non-cacheable +* - Non-bufferable +*/ +#define ARM_MPU_ACCESS_ORDERED ARM_MPU_ACCESS_(0U, 1U, 0U, 0U) + +/** +* MPU Memory Access Attribute for device memory. +* - TEX: 000b (if shareable) or 010b (if non-shareable) +* - Shareable or non-shareable +* - Non-cacheable +* - Bufferable (if shareable) or non-bufferable (if non-shareable) +* +* \param IsShareable Configures the device memory as shareable or non-shareable. +*/ +#define ARM_MPU_ACCESS_DEVICE(IsShareable) ((IsShareable) ? ARM_MPU_ACCESS_(0U, 1U, 0U, 1U) : ARM_MPU_ACCESS_(2U, 0U, 0U, 0U)) + +/** +* MPU Memory Access Attribute for normal memory. +* - TEX: 1BBb (reflecting outer cacheability rules) +* - Shareable or non-shareable +* - Cacheable or non-cacheable (reflecting inner cacheability rules) +* - Bufferable or non-bufferable (reflecting inner cacheability rules) +* +* \param OuterCp Configures the outer cache policy. +* \param InnerCp Configures the inner cache policy. +* \param IsShareable Configures the memory as shareable or non-shareable. +*/ +#define ARM_MPU_ACCESS_NORMAL(OuterCp, InnerCp, IsShareable) ARM_MPU_ACCESS_((4U | (OuterCp)), IsShareable, ((InnerCp) >> 1U), ((InnerCp) & 1U)) + +/** +* MPU Memory Access Attribute non-cacheable policy. +*/ +#define ARM_MPU_CACHEP_NOCACHE 0U + +/** +* MPU Memory Access Attribute write-back, write and read allocate policy. +*/ +#define ARM_MPU_CACHEP_WB_WRA 1U + +/** +* MPU Memory Access Attribute write-through, no write allocate policy. +*/ +#define ARM_MPU_CACHEP_WT_NWA 2U + +/** +* MPU Memory Access Attribute write-back, no write allocate policy. +*/ +#define ARM_MPU_CACHEP_WB_NWA 3U + + +/** +* Struct for a single MPU Region +*/ +typedef struct { + uint32_t RBAR; //!< The region base address register value (RBAR) + uint32_t RASR; //!< The region attribute and size register value (RASR) \ref MPU_RASR +} ARM_MPU_Region_t; + +/** Enable the MPU. +* \param MPU_Control Default access permissions for unconfigured regions. +*/ +__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control) +{ + __DMB(); + MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; +#endif + __DSB(); + __ISB(); +} + +/** Disable the MPU. +*/ +__STATIC_INLINE void ARM_MPU_Disable(void) +{ + __DMB(); +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; +#endif + MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk; + __DSB(); + __ISB(); +} + +/** Clear and disable the given MPU region. +* \param rnr Region number to be cleared. +*/ +__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr) +{ + MPU->RNR = rnr; + MPU->RASR = 0U; +} + +/** Configure an MPU region. +* \param rbar Value for RBAR register. +* \param rasr Value for RASR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rbar, uint32_t rasr) +{ + MPU->RBAR = rbar; + MPU->RASR = rasr; +} + +/** Configure the given MPU region. +* \param rnr Region number to be configured. +* \param rbar Value for RBAR register. +* \param rasr Value for RASR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegionEx(uint32_t rnr, uint32_t rbar, uint32_t rasr) +{ + MPU->RNR = rnr; + MPU->RBAR = rbar; + MPU->RASR = rasr; +} + +/** Memcpy with strictly ordered memory access, e.g. used by code in ARM_MPU_Load(). +* \param dst Destination data is copied to. +* \param src Source data is copied from. +* \param len Amount of data words to be copied. +*/ +__STATIC_INLINE void ARM_MPU_OrderedMemcpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len) +{ + uint32_t i; + for (i = 0U; i < len; ++i) + { + dst[i] = src[i]; + } +} + +/** Load the given number of MPU regions from a table. +* \param table Pointer to the MPU configuration table. +* \param cnt Amount of regions to be configured. +*/ +__STATIC_INLINE void ARM_MPU_Load(ARM_MPU_Region_t const* table, uint32_t cnt) +{ + const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U; + while (cnt > MPU_TYPE_RALIASES) { + ARM_MPU_OrderedMemcpy(&(MPU->RBAR), &(table->RBAR), MPU_TYPE_RALIASES*rowWordSize); + table += MPU_TYPE_RALIASES; + cnt -= MPU_TYPE_RALIASES; + } + ARM_MPU_OrderedMemcpy(&(MPU->RBAR), &(table->RBAR), cnt*rowWordSize); +} + +#endif diff --git a/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/CMSIS/Core/Include/mpu_armv8.h b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/CMSIS/Core/Include/mpu_armv8.h new file mode 100644 index 0000000000..19855b9667 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/CMSIS/Core/Include/mpu_armv8.h @@ -0,0 +1,352 @@ +/****************************************************************************** + * @file mpu_armv8.h + * @brief CMSIS MPU API for Armv8-M and Armv8.1-M MPU + * @version V5.1.3 + * @date 03. February 2021 + ******************************************************************************/ +/* + * Copyright (c) 2017-2021 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef ARM_MPU_ARMV8_H +#define ARM_MPU_ARMV8_H + +/** \brief Attribute for device memory (outer only) */ +#define ARM_MPU_ATTR_DEVICE ( 0U ) + +/** \brief Attribute for non-cacheable, normal memory */ +#define ARM_MPU_ATTR_NON_CACHEABLE ( 4U ) + +/** \brief Attribute for normal memory (outer and inner) +* \param NT Non-Transient: Set to 1 for non-transient data. +* \param WB Write-Back: Set to 1 to use write-back update policy. +* \param RA Read Allocation: Set to 1 to use cache allocation on read miss. +* \param WA Write Allocation: Set to 1 to use cache allocation on write miss. +*/ +#define ARM_MPU_ATTR_MEMORY_(NT, WB, RA, WA) \ + ((((NT) & 1U) << 3U) | (((WB) & 1U) << 2U) | (((RA) & 1U) << 1U) | ((WA) & 1U)) + +/** \brief Device memory type non Gathering, non Re-ordering, non Early Write Acknowledgement */ +#define ARM_MPU_ATTR_DEVICE_nGnRnE (0U) + +/** \brief Device memory type non Gathering, non Re-ordering, Early Write Acknowledgement */ +#define ARM_MPU_ATTR_DEVICE_nGnRE (1U) + +/** \brief Device memory type non Gathering, Re-ordering, Early Write Acknowledgement */ +#define ARM_MPU_ATTR_DEVICE_nGRE (2U) + +/** \brief Device memory type Gathering, Re-ordering, Early Write Acknowledgement */ +#define ARM_MPU_ATTR_DEVICE_GRE (3U) + +/** \brief Memory Attribute +* \param O Outer memory attributes +* \param I O == ARM_MPU_ATTR_DEVICE: Device memory attributes, else: Inner memory attributes +*/ +#define ARM_MPU_ATTR(O, I) ((((O) & 0xFU) << 4U) | ((((O) & 0xFU) != 0U) ? ((I) & 0xFU) : (((I) & 0x3U) << 2U))) + +/** \brief Normal memory non-shareable */ +#define ARM_MPU_SH_NON (0U) + +/** \brief Normal memory outer shareable */ +#define ARM_MPU_SH_OUTER (2U) + +/** \brief Normal memory inner shareable */ +#define ARM_MPU_SH_INNER (3U) + +/** \brief Memory access permissions +* \param RO Read-Only: Set to 1 for read-only memory. +* \param NP Non-Privileged: Set to 1 for non-privileged memory. +*/ +#define ARM_MPU_AP_(RO, NP) ((((RO) & 1U) << 1U) | ((NP) & 1U)) + +/** \brief Region Base Address Register value +* \param BASE The base address bits [31:5] of a memory region. The value is zero extended. Effective address gets 32 byte aligned. +* \param SH Defines the Shareability domain for this memory region. +* \param RO Read-Only: Set to 1 for a read-only memory region. +* \param NP Non-Privileged: Set to 1 for a non-privileged memory region. +* \oaram XN eXecute Never: Set to 1 for a non-executable memory region. +*/ +#define ARM_MPU_RBAR(BASE, SH, RO, NP, XN) \ + (((BASE) & MPU_RBAR_BASE_Msk) | \ + (((SH) << MPU_RBAR_SH_Pos) & MPU_RBAR_SH_Msk) | \ + ((ARM_MPU_AP_(RO, NP) << MPU_RBAR_AP_Pos) & MPU_RBAR_AP_Msk) | \ + (((XN) << MPU_RBAR_XN_Pos) & MPU_RBAR_XN_Msk)) + +/** \brief Region Limit Address Register value +* \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended. +* \param IDX The attribute index to be associated with this memory region. +*/ +#define ARM_MPU_RLAR(LIMIT, IDX) \ + (((LIMIT) & MPU_RLAR_LIMIT_Msk) | \ + (((IDX) << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \ + (MPU_RLAR_EN_Msk)) + +#if defined(MPU_RLAR_PXN_Pos) + +/** \brief Region Limit Address Register with PXN value +* \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended. +* \param PXN Privileged execute never. Defines whether code can be executed from this privileged region. +* \param IDX The attribute index to be associated with this memory region. +*/ +#define ARM_MPU_RLAR_PXN(LIMIT, PXN, IDX) \ + (((LIMIT) & MPU_RLAR_LIMIT_Msk) | \ + (((PXN) << MPU_RLAR_PXN_Pos) & MPU_RLAR_PXN_Msk) | \ + (((IDX) << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \ + (MPU_RLAR_EN_Msk)) + +#endif + +/** +* Struct for a single MPU Region +*/ +typedef struct { + uint32_t RBAR; /*!< Region Base Address Register value */ + uint32_t RLAR; /*!< Region Limit Address Register value */ +} ARM_MPU_Region_t; + +/** Enable the MPU. +* \param MPU_Control Default access permissions for unconfigured regions. +*/ +__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control) +{ + __DMB(); + MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; +#endif + __DSB(); + __ISB(); +} + +/** Disable the MPU. +*/ +__STATIC_INLINE void ARM_MPU_Disable(void) +{ + __DMB(); +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; +#endif + MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk; + __DSB(); + __ISB(); +} + +#ifdef MPU_NS +/** Enable the Non-secure MPU. +* \param MPU_Control Default access permissions for unconfigured regions. +*/ +__STATIC_INLINE void ARM_MPU_Enable_NS(uint32_t MPU_Control) +{ + __DMB(); + MPU_NS->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB_NS->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; +#endif + __DSB(); + __ISB(); +} + +/** Disable the Non-secure MPU. +*/ +__STATIC_INLINE void ARM_MPU_Disable_NS(void) +{ + __DMB(); +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB_NS->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; +#endif + MPU_NS->CTRL &= ~MPU_CTRL_ENABLE_Msk; + __DSB(); + __ISB(); +} +#endif + +/** Set the memory attribute encoding to the given MPU. +* \param mpu Pointer to the MPU to be configured. +* \param idx The attribute index to be set [0-7] +* \param attr The attribute value to be set. +*/ +__STATIC_INLINE void ARM_MPU_SetMemAttrEx(MPU_Type* mpu, uint8_t idx, uint8_t attr) +{ + const uint8_t reg = idx / 4U; + const uint32_t pos = ((idx % 4U) * 8U); + const uint32_t mask = 0xFFU << pos; + + if (reg >= (sizeof(mpu->MAIR) / sizeof(mpu->MAIR[0]))) { + return; // invalid index + } + + mpu->MAIR[reg] = ((mpu->MAIR[reg] & ~mask) | ((attr << pos) & mask)); +} + +/** Set the memory attribute encoding. +* \param idx The attribute index to be set [0-7] +* \param attr The attribute value to be set. +*/ +__STATIC_INLINE void ARM_MPU_SetMemAttr(uint8_t idx, uint8_t attr) +{ + ARM_MPU_SetMemAttrEx(MPU, idx, attr); +} + +#ifdef MPU_NS +/** Set the memory attribute encoding to the Non-secure MPU. +* \param idx The attribute index to be set [0-7] +* \param attr The attribute value to be set. +*/ +__STATIC_INLINE void ARM_MPU_SetMemAttr_NS(uint8_t idx, uint8_t attr) +{ + ARM_MPU_SetMemAttrEx(MPU_NS, idx, attr); +} +#endif + +/** Clear and disable the given MPU region of the given MPU. +* \param mpu Pointer to MPU to be used. +* \param rnr Region number to be cleared. +*/ +__STATIC_INLINE void ARM_MPU_ClrRegionEx(MPU_Type* mpu, uint32_t rnr) +{ + mpu->RNR = rnr; + mpu->RLAR = 0U; +} + +/** Clear and disable the given MPU region. +* \param rnr Region number to be cleared. +*/ +__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr) +{ + ARM_MPU_ClrRegionEx(MPU, rnr); +} + +#ifdef MPU_NS +/** Clear and disable the given Non-secure MPU region. +* \param rnr Region number to be cleared. +*/ +__STATIC_INLINE void ARM_MPU_ClrRegion_NS(uint32_t rnr) +{ + ARM_MPU_ClrRegionEx(MPU_NS, rnr); +} +#endif + +/** Configure the given MPU region of the given MPU. +* \param mpu Pointer to MPU to be used. +* \param rnr Region number to be configured. +* \param rbar Value for RBAR register. +* \param rlar Value for RLAR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegionEx(MPU_Type* mpu, uint32_t rnr, uint32_t rbar, uint32_t rlar) +{ + mpu->RNR = rnr; + mpu->RBAR = rbar; + mpu->RLAR = rlar; +} + +/** Configure the given MPU region. +* \param rnr Region number to be configured. +* \param rbar Value for RBAR register. +* \param rlar Value for RLAR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rnr, uint32_t rbar, uint32_t rlar) +{ + ARM_MPU_SetRegionEx(MPU, rnr, rbar, rlar); +} + +#ifdef MPU_NS +/** Configure the given Non-secure MPU region. +* \param rnr Region number to be configured. +* \param rbar Value for RBAR register. +* \param rlar Value for RLAR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegion_NS(uint32_t rnr, uint32_t rbar, uint32_t rlar) +{ + ARM_MPU_SetRegionEx(MPU_NS, rnr, rbar, rlar); +} +#endif + +/** Memcpy with strictly ordered memory access, e.g. used by code in ARM_MPU_LoadEx() +* \param dst Destination data is copied to. +* \param src Source data is copied from. +* \param len Amount of data words to be copied. +*/ +__STATIC_INLINE void ARM_MPU_OrderedMemcpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len) +{ + uint32_t i; + for (i = 0U; i < len; ++i) + { + dst[i] = src[i]; + } +} + +/** Load the given number of MPU regions from a table to the given MPU. +* \param mpu Pointer to the MPU registers to be used. +* \param rnr First region number to be configured. +* \param table Pointer to the MPU configuration table. +* \param cnt Amount of regions to be configured. +*/ +__STATIC_INLINE void ARM_MPU_LoadEx(MPU_Type* mpu, uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) +{ + const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U; + if (cnt == 1U) { + mpu->RNR = rnr; + ARM_MPU_OrderedMemcpy(&(mpu->RBAR), &(table->RBAR), rowWordSize); + } else { + uint32_t rnrBase = rnr & ~(MPU_TYPE_RALIASES-1U); + uint32_t rnrOffset = rnr % MPU_TYPE_RALIASES; + + mpu->RNR = rnrBase; + while ((rnrOffset + cnt) > MPU_TYPE_RALIASES) { + uint32_t c = MPU_TYPE_RALIASES - rnrOffset; + ARM_MPU_OrderedMemcpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), c*rowWordSize); + table += c; + cnt -= c; + rnrOffset = 0U; + rnrBase += MPU_TYPE_RALIASES; + mpu->RNR = rnrBase; + } + + ARM_MPU_OrderedMemcpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), cnt*rowWordSize); + } +} + +/** Load the given number of MPU regions from a table. +* \param rnr First region number to be configured. +* \param table Pointer to the MPU configuration table. +* \param cnt Amount of regions to be configured. +*/ +__STATIC_INLINE void ARM_MPU_Load(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) +{ + ARM_MPU_LoadEx(MPU, rnr, table, cnt); +} + +#ifdef MPU_NS +/** Load the given number of MPU regions from a table to the Non-secure MPU. +* \param rnr First region number to be configured. +* \param table Pointer to the MPU configuration table. +* \param cnt Amount of regions to be configured. +*/ +__STATIC_INLINE void ARM_MPU_Load_NS(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) +{ + ARM_MPU_LoadEx(MPU_NS, rnr, table, cnt); +} +#endif + +#endif + diff --git a/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/CMSIS/Core/Include/pac_armv81.h b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/CMSIS/Core/Include/pac_armv81.h new file mode 100644 index 0000000000..854b60a204 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/CMSIS/Core/Include/pac_armv81.h @@ -0,0 +1,206 @@ +/****************************************************************************** + * @file pac_armv81.h + * @brief CMSIS PAC key functions for Armv8.1-M PAC extension + * @version V1.0.0 + * @date 23. March 2022 + ******************************************************************************/ +/* + * Copyright (c) 2022 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef PAC_ARMV81_H +#define PAC_ARMV81_H + + +/* ################### PAC Key functions ########################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_PacKeyFunctions PAC Key functions + \brief Functions that access the PAC keys. + @{ + */ + +#if (defined (__ARM_FEATURE_PAUTH) && (__ARM_FEATURE_PAUTH == 1)) + +/** + \brief read the PAC key used for privileged mode + \details Reads the PAC key stored in the PAC_KEY_P registers. + \param [out] pPacKey 128bit PAC key + */ +__STATIC_FORCEINLINE void __get_PAC_KEY_P (uint32_t* pPacKey) { + __ASM volatile ( + "mrs r1, pac_key_p_0\n" + "str r1,[%0,#0]\n" + "mrs r1, pac_key_p_1\n" + "str r1,[%0,#4]\n" + "mrs r1, pac_key_p_2\n" + "str r1,[%0,#8]\n" + "mrs r1, pac_key_p_3\n" + "str r1,[%0,#12]\n" + : : "r" (pPacKey) : "memory", "r1" + ); +} + +/** + \brief write the PAC key used for privileged mode + \details writes the given PAC key to the PAC_KEY_P registers. + \param [in] pPacKey 128bit PAC key + */ +__STATIC_FORCEINLINE void __set_PAC_KEY_P (uint32_t* pPacKey) { + __ASM volatile ( + "ldr r1,[%0,#0]\n" + "msr pac_key_p_0, r1\n" + "ldr r1,[%0,#4]\n" + "msr pac_key_p_1, r1\n" + "ldr r1,[%0,#8]\n" + "msr pac_key_p_2, r1\n" + "ldr r1,[%0,#12]\n" + "msr pac_key_p_3, r1\n" + : : "r" (pPacKey) : "memory", "r1" + ); +} + +/** + \brief read the PAC key used for unprivileged mode + \details Reads the PAC key stored in the PAC_KEY_U registers. + \param [out] pPacKey 128bit PAC key + */ +__STATIC_FORCEINLINE void __get_PAC_KEY_U (uint32_t* pPacKey) { + __ASM volatile ( + "mrs r1, pac_key_u_0\n" + "str r1,[%0,#0]\n" + "mrs r1, pac_key_u_1\n" + "str r1,[%0,#4]\n" + "mrs r1, pac_key_u_2\n" + "str r1,[%0,#8]\n" + "mrs r1, pac_key_u_3\n" + "str r1,[%0,#12]\n" + : : "r" (pPacKey) : "memory", "r1" + ); +} + +/** + \brief write the PAC key used for unprivileged mode + \details writes the given PAC key to the PAC_KEY_U registers. + \param [in] pPacKey 128bit PAC key + */ +__STATIC_FORCEINLINE void __set_PAC_KEY_U (uint32_t* pPacKey) { + __ASM volatile ( + "ldr r1,[%0,#0]\n" + "msr pac_key_u_0, r1\n" + "ldr r1,[%0,#4]\n" + "msr pac_key_u_1, r1\n" + "ldr r1,[%0,#8]\n" + "msr pac_key_u_2, r1\n" + "ldr r1,[%0,#12]\n" + "msr pac_key_u_3, r1\n" + : : "r" (pPacKey) : "memory", "r1" + ); +} + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + +/** + \brief read the PAC key used for privileged mode (non-secure) + \details Reads the PAC key stored in the non-secure PAC_KEY_P registers when in secure mode. + \param [out] pPacKey 128bit PAC key + */ +__STATIC_FORCEINLINE void __TZ_get_PAC_KEY_P_NS (uint32_t* pPacKey) { + __ASM volatile ( + "mrs r1, pac_key_p_0_ns\n" + "str r1,[%0,#0]\n" + "mrs r1, pac_key_p_1_ns\n" + "str r1,[%0,#4]\n" + "mrs r1, pac_key_p_2_ns\n" + "str r1,[%0,#8]\n" + "mrs r1, pac_key_p_3_ns\n" + "str r1,[%0,#12]\n" + : : "r" (pPacKey) : "memory", "r1" + ); +} + +/** + \brief write the PAC key used for privileged mode (non-secure) + \details writes the given PAC key to the non-secure PAC_KEY_P registers when in secure mode. + \param [in] pPacKey 128bit PAC key + */ +__STATIC_FORCEINLINE void __TZ_set_PAC_KEY_P_NS (uint32_t* pPacKey) { + __ASM volatile ( + "ldr r1,[%0,#0]\n" + "msr pac_key_p_0_ns, r1\n" + "ldr r1,[%0,#4]\n" + "msr pac_key_p_1_ns, r1\n" + "ldr r1,[%0,#8]\n" + "msr pac_key_p_2_ns, r1\n" + "ldr r1,[%0,#12]\n" + "msr pac_key_p_3_ns, r1\n" + : : "r" (pPacKey) : "memory", "r1" + ); +} + +/** + \brief read the PAC key used for unprivileged mode (non-secure) + \details Reads the PAC key stored in the non-secure PAC_KEY_U registers when in secure mode. + \param [out] pPacKey 128bit PAC key + */ +__STATIC_FORCEINLINE void __TZ_get_PAC_KEY_U_NS (uint32_t* pPacKey) { + __ASM volatile ( + "mrs r1, pac_key_u_0_ns\n" + "str r1,[%0,#0]\n" + "mrs r1, pac_key_u_1_ns\n" + "str r1,[%0,#4]\n" + "mrs r1, pac_key_u_2_ns\n" + "str r1,[%0,#8]\n" + "mrs r1, pac_key_u_3_ns\n" + "str r1,[%0,#12]\n" + : : "r" (pPacKey) : "memory", "r1" + ); +} + +/** + \brief write the PAC key used for unprivileged mode (non-secure) + \details writes the given PAC key to the non-secure PAC_KEY_U registers when in secure mode. + \param [in] pPacKey 128bit PAC key + */ +__STATIC_FORCEINLINE void __TZ_set_PAC_KEY_U_NS (uint32_t* pPacKey) { + __ASM volatile ( + "ldr r1,[%0,#0]\n" + "msr pac_key_u_0_ns, r1\n" + "ldr r1,[%0,#4]\n" + "msr pac_key_u_1_ns, r1\n" + "ldr r1,[%0,#8]\n" + "msr pac_key_u_2_ns, r1\n" + "ldr r1,[%0,#12]\n" + "msr pac_key_u_3_ns, r1\n" + : : "r" (pPacKey) : "memory", "r1" + ); +} + +#endif /* (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) */ + +#endif /* (defined (__ARM_FEATURE_PAUTH) && (__ARM_FEATURE_PAUTH == 1)) */ + +/*@} end of CMSIS_Core_PacKeyFunctions */ + + +#endif /* PAC_ARMV81_H */ diff --git a/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/CMSIS/Core/Include/pmu_armv8.h b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/CMSIS/Core/Include/pmu_armv8.h new file mode 100644 index 0000000000..aa53bb47c1 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/CMSIS/Core/Include/pmu_armv8.h @@ -0,0 +1,337 @@ +/****************************************************************************** + * @file pmu_armv8.h + * @brief CMSIS PMU API for Armv8.1-M PMU + * @version V1.0.1 + * @date 15. April 2020 + ******************************************************************************/ +/* + * Copyright (c) 2020 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef ARM_PMU_ARMV8_H +#define ARM_PMU_ARMV8_H + +/** + * \brief PMU Events + * \note See the Armv8.1-M Architecture Reference Manual for full details on these PMU events. + * */ + +#define ARM_PMU_SW_INCR 0x0000 /*!< Software update to the PMU_SWINC register, architecturally executed and condition code check pass */ +#define ARM_PMU_L1I_CACHE_REFILL 0x0001 /*!< L1 I-Cache refill */ +#define ARM_PMU_L1D_CACHE_REFILL 0x0003 /*!< L1 D-Cache refill */ +#define ARM_PMU_L1D_CACHE 0x0004 /*!< L1 D-Cache access */ +#define ARM_PMU_LD_RETIRED 0x0006 /*!< Memory-reading instruction architecturally executed and condition code check pass */ +#define ARM_PMU_ST_RETIRED 0x0007 /*!< Memory-writing instruction architecturally executed and condition code check pass */ +#define ARM_PMU_INST_RETIRED 0x0008 /*!< Instruction architecturally executed */ +#define ARM_PMU_EXC_TAKEN 0x0009 /*!< Exception entry */ +#define ARM_PMU_EXC_RETURN 0x000A /*!< Exception return instruction architecturally executed and the condition code check pass */ +#define ARM_PMU_PC_WRITE_RETIRED 0x000C /*!< Software change to the Program Counter (PC). Instruction is architecturally executed and condition code check pass */ +#define ARM_PMU_BR_IMMED_RETIRED 0x000D /*!< Immediate branch architecturally executed */ +#define ARM_PMU_BR_RETURN_RETIRED 0x000E /*!< Function return instruction architecturally executed and the condition code check pass */ +#define ARM_PMU_UNALIGNED_LDST_RETIRED 0x000F /*!< Unaligned memory memory-reading or memory-writing instruction architecturally executed and condition code check pass */ +#define ARM_PMU_BR_MIS_PRED 0x0010 /*!< Mispredicted or not predicted branch speculatively executed */ +#define ARM_PMU_CPU_CYCLES 0x0011 /*!< Cycle */ +#define ARM_PMU_BR_PRED 0x0012 /*!< Predictable branch speculatively executed */ +#define ARM_PMU_MEM_ACCESS 0x0013 /*!< Data memory access */ +#define ARM_PMU_L1I_CACHE 0x0014 /*!< Level 1 instruction cache access */ +#define ARM_PMU_L1D_CACHE_WB 0x0015 /*!< Level 1 data cache write-back */ +#define ARM_PMU_L2D_CACHE 0x0016 /*!< Level 2 data cache access */ +#define ARM_PMU_L2D_CACHE_REFILL 0x0017 /*!< Level 2 data cache refill */ +#define ARM_PMU_L2D_CACHE_WB 0x0018 /*!< Level 2 data cache write-back */ +#define ARM_PMU_BUS_ACCESS 0x0019 /*!< Bus access */ +#define ARM_PMU_MEMORY_ERROR 0x001A /*!< Local memory error */ +#define ARM_PMU_INST_SPEC 0x001B /*!< Instruction speculatively executed */ +#define ARM_PMU_BUS_CYCLES 0x001D /*!< Bus cycles */ +#define ARM_PMU_CHAIN 0x001E /*!< For an odd numbered counter, increment when an overflow occurs on the preceding even-numbered counter on the same PE */ +#define ARM_PMU_L1D_CACHE_ALLOCATE 0x001F /*!< Level 1 data cache allocation without refill */ +#define ARM_PMU_L2D_CACHE_ALLOCATE 0x0020 /*!< Level 2 data cache allocation without refill */ +#define ARM_PMU_BR_RETIRED 0x0021 /*!< Branch instruction architecturally executed */ +#define ARM_PMU_BR_MIS_PRED_RETIRED 0x0022 /*!< Mispredicted branch instruction architecturally executed */ +#define ARM_PMU_STALL_FRONTEND 0x0023 /*!< No operation issued because of the frontend */ +#define ARM_PMU_STALL_BACKEND 0x0024 /*!< No operation issued because of the backend */ +#define ARM_PMU_L2I_CACHE 0x0027 /*!< Level 2 instruction cache access */ +#define ARM_PMU_L2I_CACHE_REFILL 0x0028 /*!< Level 2 instruction cache refill */ +#define ARM_PMU_L3D_CACHE_ALLOCATE 0x0029 /*!< Level 3 data cache allocation without refill */ +#define ARM_PMU_L3D_CACHE_REFILL 0x002A /*!< Level 3 data cache refill */ +#define ARM_PMU_L3D_CACHE 0x002B /*!< Level 3 data cache access */ +#define ARM_PMU_L3D_CACHE_WB 0x002C /*!< Level 3 data cache write-back */ +#define ARM_PMU_LL_CACHE_RD 0x0036 /*!< Last level data cache read */ +#define ARM_PMU_LL_CACHE_MISS_RD 0x0037 /*!< Last level data cache read miss */ +#define ARM_PMU_L1D_CACHE_MISS_RD 0x0039 /*!< Level 1 data cache read miss */ +#define ARM_PMU_OP_COMPLETE 0x003A /*!< Operation retired */ +#define ARM_PMU_OP_SPEC 0x003B /*!< Operation speculatively executed */ +#define ARM_PMU_STALL 0x003C /*!< Stall cycle for instruction or operation not sent for execution */ +#define ARM_PMU_STALL_OP_BACKEND 0x003D /*!< Stall cycle for instruction or operation not sent for execution due to pipeline backend */ +#define ARM_PMU_STALL_OP_FRONTEND 0x003E /*!< Stall cycle for instruction or operation not sent for execution due to pipeline frontend */ +#define ARM_PMU_STALL_OP 0x003F /*!< Instruction or operation slots not occupied each cycle */ +#define ARM_PMU_L1D_CACHE_RD 0x0040 /*!< Level 1 data cache read */ +#define ARM_PMU_LE_RETIRED 0x0100 /*!< Loop end instruction executed */ +#define ARM_PMU_LE_SPEC 0x0101 /*!< Loop end instruction speculatively executed */ +#define ARM_PMU_BF_RETIRED 0x0104 /*!< Branch future instruction architecturally executed and condition code check pass */ +#define ARM_PMU_BF_SPEC 0x0105 /*!< Branch future instruction speculatively executed and condition code check pass */ +#define ARM_PMU_LE_CANCEL 0x0108 /*!< Loop end instruction not taken */ +#define ARM_PMU_BF_CANCEL 0x0109 /*!< Branch future instruction not taken */ +#define ARM_PMU_SE_CALL_S 0x0114 /*!< Call to secure function, resulting in Security state change */ +#define ARM_PMU_SE_CALL_NS 0x0115 /*!< Call to non-secure function, resulting in Security state change */ +#define ARM_PMU_DWT_CMPMATCH0 0x0118 /*!< DWT comparator 0 match */ +#define ARM_PMU_DWT_CMPMATCH1 0x0119 /*!< DWT comparator 1 match */ +#define ARM_PMU_DWT_CMPMATCH2 0x011A /*!< DWT comparator 2 match */ +#define ARM_PMU_DWT_CMPMATCH3 0x011B /*!< DWT comparator 3 match */ +#define ARM_PMU_MVE_INST_RETIRED 0x0200 /*!< MVE instruction architecturally executed */ +#define ARM_PMU_MVE_INST_SPEC 0x0201 /*!< MVE instruction speculatively executed */ +#define ARM_PMU_MVE_FP_RETIRED 0x0204 /*!< MVE floating-point instruction architecturally executed */ +#define ARM_PMU_MVE_FP_SPEC 0x0205 /*!< MVE floating-point instruction speculatively executed */ +#define ARM_PMU_MVE_FP_HP_RETIRED 0x0208 /*!< MVE half-precision floating-point instruction architecturally executed */ +#define ARM_PMU_MVE_FP_HP_SPEC 0x0209 /*!< MVE half-precision floating-point instruction speculatively executed */ +#define ARM_PMU_MVE_FP_SP_RETIRED 0x020C /*!< MVE single-precision floating-point instruction architecturally executed */ +#define ARM_PMU_MVE_FP_SP_SPEC 0x020D /*!< MVE single-precision floating-point instruction speculatively executed */ +#define ARM_PMU_MVE_FP_MAC_RETIRED 0x0214 /*!< MVE floating-point multiply or multiply-accumulate instruction architecturally executed */ +#define ARM_PMU_MVE_FP_MAC_SPEC 0x0215 /*!< MVE floating-point multiply or multiply-accumulate instruction speculatively executed */ +#define ARM_PMU_MVE_INT_RETIRED 0x0224 /*!< MVE integer instruction architecturally executed */ +#define ARM_PMU_MVE_INT_SPEC 0x0225 /*!< MVE integer instruction speculatively executed */ +#define ARM_PMU_MVE_INT_MAC_RETIRED 0x0228 /*!< MVE multiply or multiply-accumulate instruction architecturally executed */ +#define ARM_PMU_MVE_INT_MAC_SPEC 0x0229 /*!< MVE multiply or multiply-accumulate instruction speculatively executed */ +#define ARM_PMU_MVE_LDST_RETIRED 0x0238 /*!< MVE load or store instruction architecturally executed */ +#define ARM_PMU_MVE_LDST_SPEC 0x0239 /*!< MVE load or store instruction speculatively executed */ +#define ARM_PMU_MVE_LD_RETIRED 0x023C /*!< MVE load instruction architecturally executed */ +#define ARM_PMU_MVE_LD_SPEC 0x023D /*!< MVE load instruction speculatively executed */ +#define ARM_PMU_MVE_ST_RETIRED 0x0240 /*!< MVE store instruction architecturally executed */ +#define ARM_PMU_MVE_ST_SPEC 0x0241 /*!< MVE store instruction speculatively executed */ +#define ARM_PMU_MVE_LDST_CONTIG_RETIRED 0x0244 /*!< MVE contiguous load or store instruction architecturally executed */ +#define ARM_PMU_MVE_LDST_CONTIG_SPEC 0x0245 /*!< MVE contiguous load or store instruction speculatively executed */ +#define ARM_PMU_MVE_LD_CONTIG_RETIRED 0x0248 /*!< MVE contiguous load instruction architecturally executed */ +#define ARM_PMU_MVE_LD_CONTIG_SPEC 0x0249 /*!< MVE contiguous load instruction speculatively executed */ +#define ARM_PMU_MVE_ST_CONTIG_RETIRED 0x024C /*!< MVE contiguous store instruction architecturally executed */ +#define ARM_PMU_MVE_ST_CONTIG_SPEC 0x024D /*!< MVE contiguous store instruction speculatively executed */ +#define ARM_PMU_MVE_LDST_NONCONTIG_RETIRED 0x0250 /*!< MVE non-contiguous load or store instruction architecturally executed */ +#define ARM_PMU_MVE_LDST_NONCONTIG_SPEC 0x0251 /*!< MVE non-contiguous load or store instruction speculatively executed */ +#define ARM_PMU_MVE_LD_NONCONTIG_RETIRED 0x0254 /*!< MVE non-contiguous load instruction architecturally executed */ +#define ARM_PMU_MVE_LD_NONCONTIG_SPEC 0x0255 /*!< MVE non-contiguous load instruction speculatively executed */ +#define ARM_PMU_MVE_ST_NONCONTIG_RETIRED 0x0258 /*!< MVE non-contiguous store instruction architecturally executed */ +#define ARM_PMU_MVE_ST_NONCONTIG_SPEC 0x0259 /*!< MVE non-contiguous store instruction speculatively executed */ +#define ARM_PMU_MVE_LDST_MULTI_RETIRED 0x025C /*!< MVE memory instruction targeting multiple registers architecturally executed */ +#define ARM_PMU_MVE_LDST_MULTI_SPEC 0x025D /*!< MVE memory instruction targeting multiple registers speculatively executed */ +#define ARM_PMU_MVE_LD_MULTI_RETIRED 0x0260 /*!< MVE memory load instruction targeting multiple registers architecturally executed */ +#define ARM_PMU_MVE_LD_MULTI_SPEC 0x0261 /*!< MVE memory load instruction targeting multiple registers speculatively executed */ +#define ARM_PMU_MVE_ST_MULTI_RETIRED 0x0261 /*!< MVE memory store instruction targeting multiple registers architecturally executed */ +#define ARM_PMU_MVE_ST_MULTI_SPEC 0x0265 /*!< MVE memory store instruction targeting multiple registers speculatively executed */ +#define ARM_PMU_MVE_LDST_UNALIGNED_RETIRED 0x028C /*!< MVE unaligned memory load or store instruction architecturally executed */ +#define ARM_PMU_MVE_LDST_UNALIGNED_SPEC 0x028D /*!< MVE unaligned memory load or store instruction speculatively executed */ +#define ARM_PMU_MVE_LD_UNALIGNED_RETIRED 0x0290 /*!< MVE unaligned load instruction architecturally executed */ +#define ARM_PMU_MVE_LD_UNALIGNED_SPEC 0x0291 /*!< MVE unaligned load instruction speculatively executed */ +#define ARM_PMU_MVE_ST_UNALIGNED_RETIRED 0x0294 /*!< MVE unaligned store instruction architecturally executed */ +#define ARM_PMU_MVE_ST_UNALIGNED_SPEC 0x0295 /*!< MVE unaligned store instruction speculatively executed */ +#define ARM_PMU_MVE_LDST_UNALIGNED_NONCONTIG_RETIRED 0x0298 /*!< MVE unaligned noncontiguous load or store instruction architecturally executed */ +#define ARM_PMU_MVE_LDST_UNALIGNED_NONCONTIG_SPEC 0x0299 /*!< MVE unaligned noncontiguous load or store instruction speculatively executed */ +#define ARM_PMU_MVE_VREDUCE_RETIRED 0x02A0 /*!< MVE vector reduction instruction architecturally executed */ +#define ARM_PMU_MVE_VREDUCE_SPEC 0x02A1 /*!< MVE vector reduction instruction speculatively executed */ +#define ARM_PMU_MVE_VREDUCE_FP_RETIRED 0x02A4 /*!< MVE floating-point vector reduction instruction architecturally executed */ +#define ARM_PMU_MVE_VREDUCE_FP_SPEC 0x02A5 /*!< MVE floating-point vector reduction instruction speculatively executed */ +#define ARM_PMU_MVE_VREDUCE_INT_RETIRED 0x02A8 /*!< MVE integer vector reduction instruction architecturally executed */ +#define ARM_PMU_MVE_VREDUCE_INT_SPEC 0x02A9 /*!< MVE integer vector reduction instruction speculatively executed */ +#define ARM_PMU_MVE_PRED 0x02B8 /*!< Cycles where one or more predicated beats architecturally executed */ +#define ARM_PMU_MVE_STALL 0x02CC /*!< Stall cycles caused by an MVE instruction */ +#define ARM_PMU_MVE_STALL_RESOURCE 0x02CD /*!< Stall cycles caused by an MVE instruction because of resource conflicts */ +#define ARM_PMU_MVE_STALL_RESOURCE_MEM 0x02CE /*!< Stall cycles caused by an MVE instruction because of memory resource conflicts */ +#define ARM_PMU_MVE_STALL_RESOURCE_FP 0x02CF /*!< Stall cycles caused by an MVE instruction because of floating-point resource conflicts */ +#define ARM_PMU_MVE_STALL_RESOURCE_INT 0x02D0 /*!< Stall cycles caused by an MVE instruction because of integer resource conflicts */ +#define ARM_PMU_MVE_STALL_BREAK 0x02D3 /*!< Stall cycles caused by an MVE chain break */ +#define ARM_PMU_MVE_STALL_DEPENDENCY 0x02D4 /*!< Stall cycles caused by MVE register dependency */ +#define ARM_PMU_ITCM_ACCESS 0x4007 /*!< Instruction TCM access */ +#define ARM_PMU_DTCM_ACCESS 0x4008 /*!< Data TCM access */ +#define ARM_PMU_TRCEXTOUT0 0x4010 /*!< ETM external output 0 */ +#define ARM_PMU_TRCEXTOUT1 0x4011 /*!< ETM external output 1 */ +#define ARM_PMU_TRCEXTOUT2 0x4012 /*!< ETM external output 2 */ +#define ARM_PMU_TRCEXTOUT3 0x4013 /*!< ETM external output 3 */ +#define ARM_PMU_CTI_TRIGOUT4 0x4018 /*!< Cross-trigger Interface output trigger 4 */ +#define ARM_PMU_CTI_TRIGOUT5 0x4019 /*!< Cross-trigger Interface output trigger 5 */ +#define ARM_PMU_CTI_TRIGOUT6 0x401A /*!< Cross-trigger Interface output trigger 6 */ +#define ARM_PMU_CTI_TRIGOUT7 0x401B /*!< Cross-trigger Interface output trigger 7 */ + +/** \brief PMU Functions */ + +__STATIC_INLINE void ARM_PMU_Enable(void); +__STATIC_INLINE void ARM_PMU_Disable(void); + +__STATIC_INLINE void ARM_PMU_Set_EVTYPER(uint32_t num, uint32_t type); + +__STATIC_INLINE void ARM_PMU_CYCCNT_Reset(void); +__STATIC_INLINE void ARM_PMU_EVCNTR_ALL_Reset(void); + +__STATIC_INLINE void ARM_PMU_CNTR_Enable(uint32_t mask); +__STATIC_INLINE void ARM_PMU_CNTR_Disable(uint32_t mask); + +__STATIC_INLINE uint32_t ARM_PMU_Get_CCNTR(void); +__STATIC_INLINE uint32_t ARM_PMU_Get_EVCNTR(uint32_t num); + +__STATIC_INLINE uint32_t ARM_PMU_Get_CNTR_OVS(void); +__STATIC_INLINE void ARM_PMU_Set_CNTR_OVS(uint32_t mask); + +__STATIC_INLINE void ARM_PMU_Set_CNTR_IRQ_Enable(uint32_t mask); +__STATIC_INLINE void ARM_PMU_Set_CNTR_IRQ_Disable(uint32_t mask); + +__STATIC_INLINE void ARM_PMU_CNTR_Increment(uint32_t mask); + +/** + \brief Enable the PMU +*/ +__STATIC_INLINE void ARM_PMU_Enable(void) +{ + PMU->CTRL |= PMU_CTRL_ENABLE_Msk; +} + +/** + \brief Disable the PMU +*/ +__STATIC_INLINE void ARM_PMU_Disable(void) +{ + PMU->CTRL &= ~PMU_CTRL_ENABLE_Msk; +} + +/** + \brief Set event to count for PMU eventer counter + \param [in] num Event counter (0-30) to configure + \param [in] type Event to count +*/ +__STATIC_INLINE void ARM_PMU_Set_EVTYPER(uint32_t num, uint32_t type) +{ + PMU->EVTYPER[num] = type; +} + +/** + \brief Reset cycle counter +*/ +__STATIC_INLINE void ARM_PMU_CYCCNT_Reset(void) +{ + PMU->CTRL |= PMU_CTRL_CYCCNT_RESET_Msk; +} + +/** + \brief Reset all event counters +*/ +__STATIC_INLINE void ARM_PMU_EVCNTR_ALL_Reset(void) +{ + PMU->CTRL |= PMU_CTRL_EVENTCNT_RESET_Msk; +} + +/** + \brief Enable counters + \param [in] mask Counters to enable + \note Enables one or more of the following: + - event counters (0-30) + - cycle counter +*/ +__STATIC_INLINE void ARM_PMU_CNTR_Enable(uint32_t mask) +{ + PMU->CNTENSET = mask; +} + +/** + \brief Disable counters + \param [in] mask Counters to enable + \note Disables one or more of the following: + - event counters (0-30) + - cycle counter +*/ +__STATIC_INLINE void ARM_PMU_CNTR_Disable(uint32_t mask) +{ + PMU->CNTENCLR = mask; +} + +/** + \brief Read cycle counter + \return Cycle count +*/ +__STATIC_INLINE uint32_t ARM_PMU_Get_CCNTR(void) +{ + return PMU->CCNTR; +} + +/** + \brief Read event counter + \param [in] num Event counter (0-30) to read + \return Event count +*/ +__STATIC_INLINE uint32_t ARM_PMU_Get_EVCNTR(uint32_t num) +{ + return PMU_EVCNTR_CNT_Msk & PMU->EVCNTR[num]; +} + +/** + \brief Read counter overflow status + \return Counter overflow status bits for the following: + - event counters (0-30) + - cycle counter +*/ +__STATIC_INLINE uint32_t ARM_PMU_Get_CNTR_OVS(void) +{ + return PMU->OVSSET; +} + +/** + \brief Clear counter overflow status + \param [in] mask Counter overflow status bits to clear + \note Clears overflow status bits for one or more of the following: + - event counters (0-30) + - cycle counter +*/ +__STATIC_INLINE void ARM_PMU_Set_CNTR_OVS(uint32_t mask) +{ + PMU->OVSCLR = mask; +} + +/** + \brief Enable counter overflow interrupt request + \param [in] mask Counter overflow interrupt request bits to set + \note Sets overflow interrupt request bits for one or more of the following: + - event counters (0-30) + - cycle counter +*/ +__STATIC_INLINE void ARM_PMU_Set_CNTR_IRQ_Enable(uint32_t mask) +{ + PMU->INTENSET = mask; +} + +/** + \brief Disable counter overflow interrupt request + \param [in] mask Counter overflow interrupt request bits to clear + \note Clears overflow interrupt request bits for one or more of the following: + - event counters (0-30) + - cycle counter +*/ +__STATIC_INLINE void ARM_PMU_Set_CNTR_IRQ_Disable(uint32_t mask) +{ + PMU->INTENCLR = mask; +} + +/** + \brief Software increment event counter + \param [in] mask Counters to increment + \note Software increment bits for one or more event counters (0-30) +*/ +__STATIC_INLINE void ARM_PMU_CNTR_Increment(uint32_t mask) +{ + PMU->SWINC = mask; +} + +#endif diff --git a/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/CMSIS/Core/Include/tz_context.h b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/CMSIS/Core/Include/tz_context.h new file mode 100644 index 0000000000..facc2c9a47 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/CMSIS/Core/Include/tz_context.h @@ -0,0 +1,70 @@ +/****************************************************************************** + * @file tz_context.h + * @brief Context Management for Armv8-M TrustZone + * @version V1.0.1 + * @date 10. January 2018 + ******************************************************************************/ +/* + * Copyright (c) 2017-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef TZ_CONTEXT_H +#define TZ_CONTEXT_H + +#include + +#ifndef TZ_MODULEID_T +#define TZ_MODULEID_T +/// \details Data type that identifies secure software modules called by a process. +typedef uint32_t TZ_ModuleId_t; +#endif + +/// \details TZ Memory ID identifies an allocated memory slot. +typedef uint32_t TZ_MemoryId_t; + +/// Initialize secure context memory system +/// \return execution status (1: success, 0: error) +uint32_t TZ_InitContextSystem_S (void); + +/// Allocate context memory for calling secure software modules in TrustZone +/// \param[in] module identifies software modules called from non-secure mode +/// \return value != 0 id TrustZone memory slot identifier +/// \return value 0 no memory available or internal error +TZ_MemoryId_t TZ_AllocModuleContext_S (TZ_ModuleId_t module); + +/// Free context memory that was previously allocated with \ref TZ_AllocModuleContext_S +/// \param[in] id TrustZone memory slot identifier +/// \return execution status (1: success, 0: error) +uint32_t TZ_FreeModuleContext_S (TZ_MemoryId_t id); + +/// Load secure context (called on RTOS thread context switch) +/// \param[in] id TrustZone memory slot identifier +/// \return execution status (1: success, 0: error) +uint32_t TZ_LoadContext_S (TZ_MemoryId_t id); + +/// Store secure context (called on RTOS thread context switch) +/// \param[in] id TrustZone memory slot identifier +/// \return execution status (1: success, 0: error) +uint32_t TZ_StoreContext_S (TZ_MemoryId_t id); + +#endif // TZ_CONTEXT_H diff --git a/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/CMSIS/Core/Template/ARMv8-M/main_s.c b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/CMSIS/Core/Template/ARMv8-M/main_s.c new file mode 100644 index 0000000000..0e56b7cb94 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/CMSIS/Core/Template/ARMv8-M/main_s.c @@ -0,0 +1,58 @@ +/****************************************************************************** + * @file main_s.c + * @brief Code template for secure main function + * @version V1.1.1 + * @date 10. January 2018 + ******************************************************************************/ +/* + * Copyright (c) 2013-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* Use CMSE intrinsics */ +#include + +#include "RTE_Components.h" +#include CMSIS_device_header + +/* TZ_START_NS: Start address of non-secure application */ +#ifndef TZ_START_NS +#define TZ_START_NS (0x200000U) +#endif + +/* typedef for non-secure callback functions */ +typedef void (*funcptr_void) (void) __attribute__((cmse_nonsecure_call)); + +/* Secure main() */ +int main(void) { + funcptr_void NonSecure_ResetHandler; + + /* Add user setup code for secure part here*/ + + /* Set non-secure main stack (MSP_NS) */ + __TZ_set_MSP_NS(*((uint32_t *)(TZ_START_NS))); + + /* Get non-secure reset handler */ + NonSecure_ResetHandler = (funcptr_void)(*((uint32_t *)((TZ_START_NS) + 4U))); + + /* Start non-secure state software application */ + NonSecure_ResetHandler(); + + /* Non-secure software does not return, this code is not executed */ + while (1) { + __NOP(); + } +} diff --git a/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/CMSIS/Core/Template/ARMv8-M/tz_context.c b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/CMSIS/Core/Template/ARMv8-M/tz_context.c new file mode 100644 index 0000000000..e2e82942f8 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/CMSIS/Core/Template/ARMv8-M/tz_context.c @@ -0,0 +1,200 @@ +/****************************************************************************** + * @file tz_context.c + * @brief Context Management for Armv8-M TrustZone - Sample implementation + * @version V1.1.1 + * @date 10. January 2018 + ******************************************************************************/ +/* + * Copyright (c) 2016-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "RTE_Components.h" +#include CMSIS_device_header +#include "tz_context.h" + +/// Number of process slots (threads may call secure library code) +#ifndef TZ_PROCESS_STACK_SLOTS +#define TZ_PROCESS_STACK_SLOTS 8U +#endif + +/// Stack size of the secure library code +#ifndef TZ_PROCESS_STACK_SIZE +#define TZ_PROCESS_STACK_SIZE 256U +#endif + +typedef struct { + uint32_t sp_top; // stack space top + uint32_t sp_limit; // stack space limit + uint32_t sp; // current stack pointer +} stack_info_t; + +static stack_info_t ProcessStackInfo [TZ_PROCESS_STACK_SLOTS]; +static uint64_t ProcessStackMemory[TZ_PROCESS_STACK_SLOTS][TZ_PROCESS_STACK_SIZE/8U]; +static uint32_t ProcessStackFreeSlot = 0xFFFFFFFFU; + + +/// Initialize secure context memory system +/// \return execution status (1: success, 0: error) +__attribute__((cmse_nonsecure_entry)) +uint32_t TZ_InitContextSystem_S (void) { + uint32_t n; + + if (__get_IPSR() == 0U) { + return 0U; // Thread Mode + } + + for (n = 0U; n < TZ_PROCESS_STACK_SLOTS; n++) { + ProcessStackInfo[n].sp = 0U; + ProcessStackInfo[n].sp_limit = (uint32_t)&ProcessStackMemory[n]; + ProcessStackInfo[n].sp_top = (uint32_t)&ProcessStackMemory[n] + TZ_PROCESS_STACK_SIZE; + *((uint32_t *)ProcessStackMemory[n]) = n + 1U; + } + *((uint32_t *)ProcessStackMemory[--n]) = 0xFFFFFFFFU; + + ProcessStackFreeSlot = 0U; + + // Default process stack pointer and stack limit + __set_PSPLIM((uint32_t)ProcessStackMemory); + __set_PSP ((uint32_t)ProcessStackMemory); + + // Privileged Thread Mode using PSP + __set_CONTROL(0x02U); + + return 1U; // Success +} + + +/// Allocate context memory for calling secure software modules in TrustZone +/// \param[in] module identifies software modules called from non-secure mode +/// \return value != 0 id TrustZone memory slot identifier +/// \return value 0 no memory available or internal error +__attribute__((cmse_nonsecure_entry)) +TZ_MemoryId_t TZ_AllocModuleContext_S (TZ_ModuleId_t module) { + uint32_t slot; + + (void)module; // Ignore (fixed Stack size) + + if (__get_IPSR() == 0U) { + return 0U; // Thread Mode + } + + if (ProcessStackFreeSlot == 0xFFFFFFFFU) { + return 0U; // No slot available + } + + slot = ProcessStackFreeSlot; + ProcessStackFreeSlot = *((uint32_t *)ProcessStackMemory[slot]); + + ProcessStackInfo[slot].sp = ProcessStackInfo[slot].sp_top; + + return (slot + 1U); +} + + +/// Free context memory that was previously allocated with \ref TZ_AllocModuleContext_S +/// \param[in] id TrustZone memory slot identifier +/// \return execution status (1: success, 0: error) +__attribute__((cmse_nonsecure_entry)) +uint32_t TZ_FreeModuleContext_S (TZ_MemoryId_t id) { + uint32_t slot; + + if (__get_IPSR() == 0U) { + return 0U; // Thread Mode + } + + if ((id == 0U) || (id > TZ_PROCESS_STACK_SLOTS)) { + return 0U; // Invalid ID + } + + slot = id - 1U; + + if (ProcessStackInfo[slot].sp == 0U) { + return 0U; // Inactive slot + } + ProcessStackInfo[slot].sp = 0U; + + *((uint32_t *)ProcessStackMemory[slot]) = ProcessStackFreeSlot; + ProcessStackFreeSlot = slot; + + return 1U; // Success +} + + +/// Load secure context (called on RTOS thread context switch) +/// \param[in] id TrustZone memory slot identifier +/// \return execution status (1: success, 0: error) +__attribute__((cmse_nonsecure_entry)) +uint32_t TZ_LoadContext_S (TZ_MemoryId_t id) { + uint32_t slot; + + if ((__get_IPSR() == 0U) || ((__get_CONTROL() & 2U) == 0U)) { + return 0U; // Thread Mode or using Main Stack for threads + } + + if ((id == 0U) || (id > TZ_PROCESS_STACK_SLOTS)) { + return 0U; // Invalid ID + } + + slot = id - 1U; + + if (ProcessStackInfo[slot].sp == 0U) { + return 0U; // Inactive slot + } + + // Setup process stack pointer and stack limit + __set_PSPLIM(ProcessStackInfo[slot].sp_limit); + __set_PSP (ProcessStackInfo[slot].sp); + + return 1U; // Success +} + + +/// Store secure context (called on RTOS thread context switch) +/// \param[in] id TrustZone memory slot identifier +/// \return execution status (1: success, 0: error) +__attribute__((cmse_nonsecure_entry)) +uint32_t TZ_StoreContext_S (TZ_MemoryId_t id) { + uint32_t slot; + uint32_t sp; + + if ((__get_IPSR() == 0U) || ((__get_CONTROL() & 2U) == 0U)) { + return 0U; // Thread Mode or using Main Stack for threads + } + + if ((id == 0U) || (id > TZ_PROCESS_STACK_SLOTS)) { + return 0U; // Invalid ID + } + + slot = id - 1U; + + if (ProcessStackInfo[slot].sp == 0U) { + return 0U; // Inactive slot + } + + sp = __get_PSP(); + if ((sp < ProcessStackInfo[slot].sp_limit) || + (sp > ProcessStackInfo[slot].sp_top)) { + return 0U; // SP out of range + } + ProcessStackInfo[slot].sp = sp; + + // Default process stack pointer and stack limit + __set_PSPLIM((uint32_t)ProcessStackMemory); + __set_PSP ((uint32_t)ProcessStackMemory); + + return 1U; // Success +} diff --git a/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/CMSIS/Include/cmsis_armcc.h b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/CMSIS/Include/cmsis_armcc.h new file mode 100644 index 0000000000..a955d47139 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/CMSIS/Include/cmsis_armcc.h @@ -0,0 +1,888 @@ +/**************************************************************************//** + * @file cmsis_armcc.h + * @brief CMSIS compiler ARMCC (Arm Compiler 5) header file + * @version V5.3.2 + * @date 27. May 2021 + ******************************************************************************/ +/* + * Copyright (c) 2009-2021 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_ARMCC_H +#define __CMSIS_ARMCC_H + + +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 400677) + #error "Please use Arm Compiler Toolchain V4.0.677 or later!" +#endif + +/* CMSIS compiler control architecture macros */ +#if ((defined (__TARGET_ARCH_6_M ) && (__TARGET_ARCH_6_M == 1)) || \ + (defined (__TARGET_ARCH_6S_M ) && (__TARGET_ARCH_6S_M == 1)) ) + #define __ARM_ARCH_6M__ 1 +#endif + +#if (defined (__TARGET_ARCH_7_M ) && (__TARGET_ARCH_7_M == 1)) + #define __ARM_ARCH_7M__ 1 +#endif + +#if (defined (__TARGET_ARCH_7E_M) && (__TARGET_ARCH_7E_M == 1)) + #define __ARM_ARCH_7EM__ 1 +#endif + + /* __ARM_ARCH_8M_BASE__ not applicable */ + /* __ARM_ARCH_8M_MAIN__ not applicable */ + /* __ARM_ARCH_8_1M_MAIN__ not applicable */ + +/* CMSIS compiler control DSP macros */ +#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + #define __ARM_FEATURE_DSP 1 +#endif + +/* CMSIS compiler specific defines */ +#ifndef __ASM + #define __ASM __asm +#endif +#ifndef __INLINE + #define __INLINE __inline +#endif +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static __inline +#endif +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE static __forceinline +#endif +#ifndef __NO_RETURN + #define __NO_RETURN __declspec(noreturn) +#endif +#ifndef __USED + #define __USED __attribute__((used)) +#endif +#ifndef __WEAK + #define __WEAK __attribute__((weak)) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed)) +#endif +#ifndef __PACKED_STRUCT + #define __PACKED_STRUCT __packed struct +#endif +#ifndef __PACKED_UNION + #define __PACKED_UNION __packed union +#endif +#ifndef __UNALIGNED_UINT32 /* deprecated */ + #define __UNALIGNED_UINT32(x) (*((__packed uint32_t *)(x))) +#endif +#ifndef __UNALIGNED_UINT16_WRITE + #define __UNALIGNED_UINT16_WRITE(addr, val) ((*((__packed uint16_t *)(addr))) = (val)) +#endif +#ifndef __UNALIGNED_UINT16_READ + #define __UNALIGNED_UINT16_READ(addr) (*((const __packed uint16_t *)(addr))) +#endif +#ifndef __UNALIGNED_UINT32_WRITE + #define __UNALIGNED_UINT32_WRITE(addr, val) ((*((__packed uint32_t *)(addr))) = (val)) +#endif +#ifndef __UNALIGNED_UINT32_READ + #define __UNALIGNED_UINT32_READ(addr) (*((const __packed uint32_t *)(addr))) +#endif +#ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __RESTRICT + #define __RESTRICT __restrict +#endif +#ifndef __COMPILER_BARRIER + #define __COMPILER_BARRIER() __memory_changed() +#endif + +/* ######################### Startup and Lowlevel Init ######################## */ + +#ifndef __PROGRAM_START +#define __PROGRAM_START __main +#endif + +#ifndef __INITIAL_SP +#define __INITIAL_SP Image$$ARM_LIB_STACK$$ZI$$Limit +#endif + +#ifndef __STACK_LIMIT +#define __STACK_LIMIT Image$$ARM_LIB_STACK$$ZI$$Base +#endif + +#ifndef __VECTOR_TABLE +#define __VECTOR_TABLE __Vectors +#endif + +#ifndef __VECTOR_TABLE_ATTRIBUTE +#define __VECTOR_TABLE_ATTRIBUTE __attribute__((used, section("RESET"))) +#endif + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP __nop + + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +#define __WFI __wfi + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE __wfe + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV __sev + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +#define __ISB() __isb(0xF) + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +#define __DSB() __dsb(0xF) + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +#define __DMB() __dmb(0xF) + + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV __rev + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. + \param [in] value Value to reverse + \return Reversed value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value) +{ + rev16 r0, r0 + bx lr +} +#endif + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. + \param [in] value Value to reverse + \return Reversed value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int16_t __REVSH(int16_t value) +{ + revsh r0, r0 + bx lr +} +#endif + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +#define __ROR __ror + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __breakpoint(value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + #define __RBIT __rbit +#else +__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value) +{ + uint32_t result; + uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */ + + result = value; /* r will be reversed bits of v; first get LSB of v */ + for (value >>= 1U; value != 0U; value >>= 1U) + { + result <<= 1U; + result |= value & 1U; + s--; + } + result <<= s; /* shift when v's highest bits are zero */ + return result; +} +#endif + + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +#define __CLZ __clz + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr)) +#else + #define __LDREXB(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint8_t ) __ldrex(ptr)) _Pragma("pop") +#endif + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __LDREXH(ptr) ((uint16_t) __ldrex(ptr)) +#else + #define __LDREXH(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint16_t) __ldrex(ptr)) _Pragma("pop") +#endif + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr)) +#else + #define __LDREXW(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex(ptr)) _Pragma("pop") +#endif + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __STREXB(value, ptr) __strex(value, ptr) +#else + #define __STREXB(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") +#endif + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __STREXH(value, ptr) __strex(value, ptr) +#else + #define __STREXH(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") +#endif + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __STREXW(value, ptr) __strex(value, ptr) +#else + #define __STREXW(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") +#endif + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +#define __CLREX __clrex + + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT __ssat + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT __usat + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value) +{ + rrx r0, r0 + bx lr +} +#endif + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDRBT(ptr) ((uint8_t ) __ldrt(ptr)) + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDRHT(ptr) ((uint16_t) __ldrt(ptr)) + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDRT(ptr) ((uint32_t ) __ldrt(ptr)) + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +#define __STRBT(value, ptr) __strt(value, ptr) + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +#define __STRHT(value, ptr) __strt(value, ptr) + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +#define __STRT(value, ptr) __strt(value, ptr) + +#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +__attribute__((always_inline)) __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat) +{ + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; +} + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat) +{ + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing special-purpose register PRIMASK. + Can only be executed in Privileged modes. + */ +/* intrinsic void __enable_irq(); */ + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting special-purpose register PRIMASK. + Can only be executed in Privileged modes. + */ +/* intrinsic void __disable_irq(); */ + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__STATIC_INLINE uint32_t __get_CONTROL(void) +{ + register uint32_t __regControl __ASM("control"); + return(__regControl); +} + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__STATIC_INLINE void __set_CONTROL(uint32_t control) +{ + register uint32_t __regControl __ASM("control"); + __regControl = control; + __ISB(); +} + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__STATIC_INLINE uint32_t __get_IPSR(void) +{ + register uint32_t __regIPSR __ASM("ipsr"); + return(__regIPSR); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__STATIC_INLINE uint32_t __get_APSR(void) +{ + register uint32_t __regAPSR __ASM("apsr"); + return(__regAPSR); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__STATIC_INLINE uint32_t __get_xPSR(void) +{ + register uint32_t __regXPSR __ASM("xpsr"); + return(__regXPSR); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__STATIC_INLINE uint32_t __get_PSP(void) +{ + register uint32_t __regProcessStackPointer __ASM("psp"); + return(__regProcessStackPointer); +} + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) +{ + register uint32_t __regProcessStackPointer __ASM("psp"); + __regProcessStackPointer = topOfProcStack; +} + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__STATIC_INLINE uint32_t __get_MSP(void) +{ + register uint32_t __regMainStackPointer __ASM("msp"); + return(__regMainStackPointer); +} + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) +{ + register uint32_t __regMainStackPointer __ASM("msp"); + __regMainStackPointer = topOfMainStack; +} + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__STATIC_INLINE uint32_t __get_PRIMASK(void) +{ + register uint32_t __regPriMask __ASM("primask"); + return(__regPriMask); +} + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__STATIC_INLINE void __set_PRIMASK(uint32_t priMask) +{ + register uint32_t __regPriMask __ASM("primask"); + __regPriMask = (priMask); +} + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing special-purpose register FAULTMASK. + Can only be executed in Privileged modes. + */ +#define __enable_fault_irq __enable_fiq + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting special-purpose register FAULTMASK. + Can only be executed in Privileged modes. + */ +#define __disable_fault_irq __disable_fiq + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__STATIC_INLINE uint32_t __get_BASEPRI(void) +{ + register uint32_t __regBasePri __ASM("basepri"); + return(__regBasePri); +} + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__STATIC_INLINE void __set_BASEPRI(uint32_t basePri) +{ + register uint32_t __regBasePri __ASM("basepri"); + __regBasePri = (basePri & 0xFFU); +} + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + register uint32_t __regBasePriMax __ASM("basepri_max"); + __regBasePriMax = (basePri & 0xFFU); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__STATIC_INLINE uint32_t __get_FAULTMASK(void) +{ + register uint32_t __regFaultMask __ASM("faultmask"); + return(__regFaultMask); +} + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) +{ + register uint32_t __regFaultMask __ASM("faultmask"); + __regFaultMask = (faultMask & (uint32_t)1U); +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ + + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +__STATIC_INLINE uint32_t __get_FPSCR(void) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) + register uint32_t __regfpscr __ASM("fpscr"); + return(__regfpscr); +#else + return(0U); +#endif +} + + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +__STATIC_INLINE void __set_FPSCR(uint32_t fpscr) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) + register uint32_t __regfpscr __ASM("fpscr"); + __regfpscr = (fpscr); +#else + (void)fpscr; +#endif +} + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + +#define __SADD8 __sadd8 +#define __QADD8 __qadd8 +#define __SHADD8 __shadd8 +#define __UADD8 __uadd8 +#define __UQADD8 __uqadd8 +#define __UHADD8 __uhadd8 +#define __SSUB8 __ssub8 +#define __QSUB8 __qsub8 +#define __SHSUB8 __shsub8 +#define __USUB8 __usub8 +#define __UQSUB8 __uqsub8 +#define __UHSUB8 __uhsub8 +#define __SADD16 __sadd16 +#define __QADD16 __qadd16 +#define __SHADD16 __shadd16 +#define __UADD16 __uadd16 +#define __UQADD16 __uqadd16 +#define __UHADD16 __uhadd16 +#define __SSUB16 __ssub16 +#define __QSUB16 __qsub16 +#define __SHSUB16 __shsub16 +#define __USUB16 __usub16 +#define __UQSUB16 __uqsub16 +#define __UHSUB16 __uhsub16 +#define __SASX __sasx +#define __QASX __qasx +#define __SHASX __shasx +#define __UASX __uasx +#define __UQASX __uqasx +#define __UHASX __uhasx +#define __SSAX __ssax +#define __QSAX __qsax +#define __SHSAX __shsax +#define __USAX __usax +#define __UQSAX __uqsax +#define __UHSAX __uhsax +#define __USAD8 __usad8 +#define __USADA8 __usada8 +#define __SSAT16 __ssat16 +#define __USAT16 __usat16 +#define __UXTB16 __uxtb16 +#define __UXTAB16 __uxtab16 +#define __SXTB16 __sxtb16 +#define __SXTAB16 __sxtab16 +#define __SMUAD __smuad +#define __SMUADX __smuadx +#define __SMLAD __smlad +#define __SMLADX __smladx +#define __SMLALD __smlald +#define __SMLALDX __smlaldx +#define __SMUSD __smusd +#define __SMUSDX __smusdx +#define __SMLSD __smlsd +#define __SMLSDX __smlsdx +#define __SMLSLD __smlsld +#define __SMLSLDX __smlsldx +#define __SEL __sel +#define __QADD __qadd +#define __QSUB __qsub + +#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ + ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) + +#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ + ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) + +#define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \ + ((int64_t)(ARG3) << 32U) ) >> 32U)) + +#define __SXTB16_RORn(ARG1, ARG2) __SXTB16(__ROR(ARG1, ARG2)) + +#define __SXTAB16_RORn(ARG1, ARG2, ARG3) __SXTAB16(ARG1, __ROR(ARG2, ARG3)) + +#endif /* ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#endif /* __CMSIS_ARMCC_H */ diff --git a/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/CMSIS/Include/cmsis_armclang.h b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/CMSIS/Include/cmsis_armclang.h new file mode 100644 index 0000000000..6911417747 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/CMSIS/Include/cmsis_armclang.h @@ -0,0 +1,1503 @@ +/**************************************************************************//** + * @file cmsis_armclang.h + * @brief CMSIS compiler armclang (Arm Compiler 6) header file + * @version V5.4.3 + * @date 27. May 2021 + ******************************************************************************/ +/* + * Copyright (c) 2009-2021 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/*lint -esym(9058, IRQn)*/ /* disable MISRA 2012 Rule 2.4 for IRQn */ + +#ifndef __CMSIS_ARMCLANG_H +#define __CMSIS_ARMCLANG_H + +#pragma clang system_header /* treat file as system include file */ + +/* CMSIS compiler specific defines */ +#ifndef __ASM + #define __ASM __asm +#endif +#ifndef __INLINE + #define __INLINE __inline +#endif +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static __inline +#endif +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __attribute__((always_inline)) static __inline +#endif +#ifndef __NO_RETURN + #define __NO_RETURN __attribute__((__noreturn__)) +#endif +#ifndef __USED + #define __USED __attribute__((used)) +#endif +#ifndef __WEAK + #define __WEAK __attribute__((weak)) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_UNION + #define __PACKED_UNION union __attribute__((packed, aligned(1))) +#endif +#ifndef __UNALIGNED_UINT32 /* deprecated */ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32 */ + struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) +#endif +#ifndef __UNALIGNED_UINT16_WRITE + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT16_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_WRITE */ + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT16_READ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT16_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_READ */ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) +#endif +#ifndef __UNALIGNED_UINT32_WRITE + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_WRITE */ + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT32_READ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_READ */ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) +#endif +#ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __RESTRICT + #define __RESTRICT __restrict +#endif +#ifndef __COMPILER_BARRIER + #define __COMPILER_BARRIER() __ASM volatile("":::"memory") +#endif + +/* ######################### Startup and Lowlevel Init ######################## */ + +#ifndef __PROGRAM_START +#define __PROGRAM_START __main +#endif + +#ifndef __INITIAL_SP +#define __INITIAL_SP Image$$ARM_LIB_STACK$$ZI$$Limit +#endif + +#ifndef __STACK_LIMIT +#define __STACK_LIMIT Image$$ARM_LIB_STACK$$ZI$$Base +#endif + +#ifndef __VECTOR_TABLE +#define __VECTOR_TABLE __Vectors +#endif + +#ifndef __VECTOR_TABLE_ATTRIBUTE +#define __VECTOR_TABLE_ATTRIBUTE __attribute__((used, section("RESET"))) +#endif + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +#ifndef __STACK_SEAL +#define __STACK_SEAL Image$$STACKSEAL$$ZI$$Base +#endif + +#ifndef __TZ_STACK_SEAL_SIZE +#define __TZ_STACK_SEAL_SIZE 8U +#endif + +#ifndef __TZ_STACK_SEAL_VALUE +#define __TZ_STACK_SEAL_VALUE 0xFEF5EDA5FEF5EDA5ULL +#endif + + +__STATIC_FORCEINLINE void __TZ_set_STACKSEAL_S (uint32_t* stackTop) { + *((uint64_t *)stackTop) = __TZ_STACK_SEAL_VALUE; +} +#endif + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/* Define macros for porting to both thumb1 and thumb2. + * For thumb1, use low register (r0-r7), specified by constraint "l" + * Otherwise, use general registers, specified by constraint "r" */ +#if defined (__thumb__) && !defined (__thumb2__) +#define __CMSIS_GCC_OUT_REG(r) "=l" (r) +#define __CMSIS_GCC_RW_REG(r) "+l" (r) +#define __CMSIS_GCC_USE_REG(r) "l" (r) +#else +#define __CMSIS_GCC_OUT_REG(r) "=r" (r) +#define __CMSIS_GCC_RW_REG(r) "+r" (r) +#define __CMSIS_GCC_USE_REG(r) "r" (r) +#endif + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP __builtin_arm_nop + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +#define __WFI __builtin_arm_wfi + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE __builtin_arm_wfe + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV __builtin_arm_sev + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +#define __ISB() __builtin_arm_isb(0xF) + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +#define __DSB() __builtin_arm_dsb(0xF) + + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +#define __DMB() __builtin_arm_dmb(0xF) + + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV(value) __builtin_bswap32(value) + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV16(value) __ROR(__REV(value), 16) + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REVSH(value) (int16_t)__builtin_bswap16(value) + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) +{ + op2 %= 32U; + if (op2 == 0U) + { + return op1; + } + return (op1 >> op2) | (op1 << (32U - op2)); +} + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __ASM volatile ("bkpt "#value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +#define __RBIT __builtin_arm_rbit + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +__STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value) +{ + /* Even though __builtin_clz produces a CLZ instruction on ARM, formally + __builtin_clz(0) is undefined behaviour, so handle this case specially. + This guarantees ARM-compatible results if happening to compile on a non-ARM + target, and ensures the compiler doesn't decide to activate any + optimisations using the logic "value was passed to __builtin_clz, so it + is non-zero". + ARM Compiler 6.10 and possibly earlier will optimise this test away, leaving a + single CLZ instruction. + */ + if (value == 0U) + { + return 32U; + } + return __builtin_clz(value); +} + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) + +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDREXB (uint8_t)__builtin_arm_ldrex + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDREXH (uint16_t)__builtin_arm_ldrex + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDREXW (uint32_t)__builtin_arm_ldrex + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXB (uint32_t)__builtin_arm_strex + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXH (uint32_t)__builtin_arm_strex + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXW (uint32_t)__builtin_arm_strex + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +#define __CLREX __builtin_arm_clrex + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT __builtin_arm_ssat + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT __builtin_arm_usat + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) ); +} + +#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) */ + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat) +{ + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; +} + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat) +{ + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) + +/** + \brief Load-Acquire (8 bit) + \details Executes a LDAB instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return ((uint8_t) result); +} + + +/** + \brief Load-Acquire (16 bit) + \details Executes a LDAH instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return ((uint16_t) result); +} + + +/** + \brief Load-Acquire (32 bit) + \details Executes a LDA instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return(result); +} + + +/** + \brief Store-Release (8 bit) + \details Executes a STLB instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Store-Release (16 bit) + \details Executes a STLH instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Store-Release (32 bit) + \details Executes a STL instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Load-Acquire Exclusive (8 bit) + \details Executes a LDAB exclusive instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDAEXB (uint8_t)__builtin_arm_ldaex + + +/** + \brief Load-Acquire Exclusive (16 bit) + \details Executes a LDAH exclusive instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDAEXH (uint16_t)__builtin_arm_ldaex + + +/** + \brief Load-Acquire Exclusive (32 bit) + \details Executes a LDA exclusive instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDAEX (uint32_t)__builtin_arm_ldaex + + +/** + \brief Store-Release Exclusive (8 bit) + \details Executes a STLB exclusive instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEXB (uint32_t)__builtin_arm_stlex + + +/** + \brief Store-Release Exclusive (16 bit) + \details Executes a STLH exclusive instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEXH (uint32_t)__builtin_arm_stlex + + +/** + \brief Store-Release Exclusive (32 bit) + \details Executes a STL exclusive instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEX (uint32_t)__builtin_arm_stlex + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing special-purpose register PRIMASK. + Can only be executed in Privileged modes. + */ +#ifndef __ARM_COMPAT_H +__STATIC_FORCEINLINE void __enable_irq(void) +{ + __ASM volatile ("cpsie i" : : : "memory"); +} +#endif + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting special-purpose register PRIMASK. + Can only be executed in Privileged modes. + */ +#ifndef __ARM_COMPAT_H +__STATIC_FORCEINLINE void __disable_irq(void) +{ + __ASM volatile ("cpsid i" : : : "memory"); +} +#endif + + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CONTROL(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Control Register (non-secure) + \details Returns the content of the non-secure Control Register when in secure mode. + \return non-secure Control Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) +{ + __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); + __ISB(); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Control Register (non-secure) + \details Writes the given value to the non-secure Control Register when in secure state. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) +{ + __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); + __ISB(); +} +#endif + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_IPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_APSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_xPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer (non-secure) + \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state. + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state. + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); +} +#endif + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer (non-secure) + \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state. + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); +} +#endif + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Stack Pointer (non-secure) + \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state. + \return SP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, sp_ns" : "=r" (result) ); + return(result); +} + + +/** + \brief Set Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state. + \param [in] topOfStack Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack) +{ + __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : ); +} +#endif + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Priority Mask (non-secure) + \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Priority Mask (non-secure) + \details Assigns the given value to the non-secure Priority Mask Register when in secure state. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) +{ + __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); +} +#endif + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing special-purpose register FAULTMASK. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __enable_fault_irq(void) +{ + __ASM volatile ("cpsie f" : : : "memory"); +} + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting special-purpose register FAULTMASK. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __disable_fault_irq(void) +{ + __ASM volatile ("cpsid f" : : : "memory"); +} + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Base Priority (non-secure) + \details Returns the current value of the non-secure Base Priority register when in secure state. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri) +{ + __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Base Priority (non-secure) + \details Assigns the given value to the non-secure Base Priority register when in secure state. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); +} +#endif + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Fault Mask (non-secure) + \details Returns the current value of the non-secure Fault Mask register when in secure state. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Fault Mask (non-secure) + \details Assigns the given value to the non-secure Fault Mask register when in secure state. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); +} +#endif + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) + +/** + \brief Get Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void) +{ +#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim" : "=r" (result) ); + return result; +#endif +} + +#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) +{ +#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) ) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) +{ +#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) +{ +#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) ) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); +#endif +} +#endif + + +/** + \brief Get Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void) +{ +#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim" : "=r" (result) ); + return result; +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state. + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void) +{ +#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) ) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). + \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) +{ +#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state. + \param [in] MainStackPtrLimit Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) +{ +#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) ) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); +#endif +} +#endif + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) */ + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#define __get_FPSCR (uint32_t)__builtin_arm_get_fpscr +#else +#define __get_FPSCR() ((uint32_t)0U) +#endif + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#define __set_FPSCR __builtin_arm_set_fpscr +#else +#define __set_FPSCR(x) ((void)(x)) +#endif + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) + +#define __SADD8 __builtin_arm_sadd8 +#define __QADD8 __builtin_arm_qadd8 +#define __SHADD8 __builtin_arm_shadd8 +#define __UADD8 __builtin_arm_uadd8 +#define __UQADD8 __builtin_arm_uqadd8 +#define __UHADD8 __builtin_arm_uhadd8 +#define __SSUB8 __builtin_arm_ssub8 +#define __QSUB8 __builtin_arm_qsub8 +#define __SHSUB8 __builtin_arm_shsub8 +#define __USUB8 __builtin_arm_usub8 +#define __UQSUB8 __builtin_arm_uqsub8 +#define __UHSUB8 __builtin_arm_uhsub8 +#define __SADD16 __builtin_arm_sadd16 +#define __QADD16 __builtin_arm_qadd16 +#define __SHADD16 __builtin_arm_shadd16 +#define __UADD16 __builtin_arm_uadd16 +#define __UQADD16 __builtin_arm_uqadd16 +#define __UHADD16 __builtin_arm_uhadd16 +#define __SSUB16 __builtin_arm_ssub16 +#define __QSUB16 __builtin_arm_qsub16 +#define __SHSUB16 __builtin_arm_shsub16 +#define __USUB16 __builtin_arm_usub16 +#define __UQSUB16 __builtin_arm_uqsub16 +#define __UHSUB16 __builtin_arm_uhsub16 +#define __SASX __builtin_arm_sasx +#define __QASX __builtin_arm_qasx +#define __SHASX __builtin_arm_shasx +#define __UASX __builtin_arm_uasx +#define __UQASX __builtin_arm_uqasx +#define __UHASX __builtin_arm_uhasx +#define __SSAX __builtin_arm_ssax +#define __QSAX __builtin_arm_qsax +#define __SHSAX __builtin_arm_shsax +#define __USAX __builtin_arm_usax +#define __UQSAX __builtin_arm_uqsax +#define __UHSAX __builtin_arm_uhsax +#define __USAD8 __builtin_arm_usad8 +#define __USADA8 __builtin_arm_usada8 +#define __SSAT16 __builtin_arm_ssat16 +#define __USAT16 __builtin_arm_usat16 +#define __UXTB16 __builtin_arm_uxtb16 +#define __UXTAB16 __builtin_arm_uxtab16 +#define __SXTB16 __builtin_arm_sxtb16 +#define __SXTAB16 __builtin_arm_sxtab16 +#define __SMUAD __builtin_arm_smuad +#define __SMUADX __builtin_arm_smuadx +#define __SMLAD __builtin_arm_smlad +#define __SMLADX __builtin_arm_smladx +#define __SMLALD __builtin_arm_smlald +#define __SMLALDX __builtin_arm_smlaldx +#define __SMUSD __builtin_arm_smusd +#define __SMUSDX __builtin_arm_smusdx +#define __SMLSD __builtin_arm_smlsd +#define __SMLSDX __builtin_arm_smlsdx +#define __SMLSLD __builtin_arm_smlsld +#define __SMLSLDX __builtin_arm_smlsldx +#define __SEL __builtin_arm_sel +#define __QADD __builtin_arm_qadd +#define __QSUB __builtin_arm_qsub + +#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ + ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) + +#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ + ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) + +#define __SXTB16_RORn(ARG1, ARG2) __SXTB16(__ROR(ARG1, ARG2)) + +#define __SXTAB16_RORn(ARG1, ARG2, ARG3) __SXTAB16(ARG1, __ROR(ARG2, ARG3)) + +__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) +{ + int32_t result; + + __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#endif /* (__ARM_FEATURE_DSP == 1) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#endif /* __CMSIS_ARMCLANG_H */ diff --git a/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/CMSIS/Include/cmsis_armclang_ltm.h b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/CMSIS/Include/cmsis_armclang_ltm.h new file mode 100644 index 0000000000..1e255d5907 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/CMSIS/Include/cmsis_armclang_ltm.h @@ -0,0 +1,1928 @@ +/**************************************************************************//** + * @file cmsis_armclang_ltm.h + * @brief CMSIS compiler armclang (Arm Compiler 6) header file + * @version V1.5.3 + * @date 27. May 2021 + ******************************************************************************/ +/* + * Copyright (c) 2018-2021 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/*lint -esym(9058, IRQn)*/ /* disable MISRA 2012 Rule 2.4 for IRQn */ + +#ifndef __CMSIS_ARMCLANG_H +#define __CMSIS_ARMCLANG_H + +#pragma clang system_header /* treat file as system include file */ + +/* CMSIS compiler specific defines */ +#ifndef __ASM + #define __ASM __asm +#endif +#ifndef __INLINE + #define __INLINE __inline +#endif +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static __inline +#endif +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __attribute__((always_inline)) static __inline +#endif +#ifndef __NO_RETURN + #define __NO_RETURN __attribute__((__noreturn__)) +#endif +#ifndef __USED + #define __USED __attribute__((used)) +#endif +#ifndef __WEAK + #define __WEAK __attribute__((weak)) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_UNION + #define __PACKED_UNION union __attribute__((packed, aligned(1))) +#endif +#ifndef __UNALIGNED_UINT32 /* deprecated */ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32 */ + struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) +#endif +#ifndef __UNALIGNED_UINT16_WRITE + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT16_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_WRITE */ + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT16_READ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT16_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_READ */ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) +#endif +#ifndef __UNALIGNED_UINT32_WRITE + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_WRITE */ + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT32_READ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_READ */ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) +#endif +#ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __RESTRICT + #define __RESTRICT __restrict +#endif +#ifndef __COMPILER_BARRIER + #define __COMPILER_BARRIER() __ASM volatile("":::"memory") +#endif + +/* ######################### Startup and Lowlevel Init ######################## */ + +#ifndef __PROGRAM_START +#define __PROGRAM_START __main +#endif + +#ifndef __INITIAL_SP +#define __INITIAL_SP Image$$ARM_LIB_STACK$$ZI$$Limit +#endif + +#ifndef __STACK_LIMIT +#define __STACK_LIMIT Image$$ARM_LIB_STACK$$ZI$$Base +#endif + +#ifndef __VECTOR_TABLE +#define __VECTOR_TABLE __Vectors +#endif + +#ifndef __VECTOR_TABLE_ATTRIBUTE +#define __VECTOR_TABLE_ATTRIBUTE __attribute__((used, section("RESET"))) +#endif + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +#ifndef __STACK_SEAL +#define __STACK_SEAL Image$$STACKSEAL$$ZI$$Base +#endif + +#ifndef __TZ_STACK_SEAL_SIZE +#define __TZ_STACK_SEAL_SIZE 8U +#endif + +#ifndef __TZ_STACK_SEAL_VALUE +#define __TZ_STACK_SEAL_VALUE 0xFEF5EDA5FEF5EDA5ULL +#endif + + +__STATIC_FORCEINLINE void __TZ_set_STACKSEAL_S (uint32_t* stackTop) { + *((uint64_t *)stackTop) = __TZ_STACK_SEAL_VALUE; +} +#endif + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/* Define macros for porting to both thumb1 and thumb2. + * For thumb1, use low register (r0-r7), specified by constraint "l" + * Otherwise, use general registers, specified by constraint "r" */ +#if defined (__thumb__) && !defined (__thumb2__) +#define __CMSIS_GCC_OUT_REG(r) "=l" (r) +#define __CMSIS_GCC_USE_REG(r) "l" (r) +#else +#define __CMSIS_GCC_OUT_REG(r) "=r" (r) +#define __CMSIS_GCC_USE_REG(r) "r" (r) +#endif + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP __builtin_arm_nop + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +#define __WFI __builtin_arm_wfi + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE __builtin_arm_wfe + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV __builtin_arm_sev + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +#define __ISB() __builtin_arm_isb(0xF) + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +#define __DSB() __builtin_arm_dsb(0xF) + + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +#define __DMB() __builtin_arm_dmb(0xF) + + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV(value) __builtin_bswap32(value) + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV16(value) __ROR(__REV(value), 16) + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REVSH(value) (int16_t)__builtin_bswap16(value) + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) +{ + op2 %= 32U; + if (op2 == 0U) + { + return op1; + } + return (op1 >> op2) | (op1 << (32U - op2)); +} + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __ASM volatile ("bkpt "#value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +#define __RBIT __builtin_arm_rbit + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +__STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value) +{ + /* Even though __builtin_clz produces a CLZ instruction on ARM, formally + __builtin_clz(0) is undefined behaviour, so handle this case specially. + This guarantees ARM-compatible results if happening to compile on a non-ARM + target, and ensures the compiler doesn't decide to activate any + optimisations using the logic "value was passed to __builtin_clz, so it + is non-zero". + ARM Compiler 6.10 and possibly earlier will optimise this test away, leaving a + single CLZ instruction. + */ + if (value == 0U) + { + return 32U; + } + return __builtin_clz(value); +} + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDREXB (uint8_t)__builtin_arm_ldrex + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDREXH (uint16_t)__builtin_arm_ldrex + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDREXW (uint32_t)__builtin_arm_ldrex + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXB (uint32_t)__builtin_arm_strex + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXH (uint32_t)__builtin_arm_strex + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXW (uint32_t)__builtin_arm_strex + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +#define __CLREX __builtin_arm_clrex + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT __builtin_arm_ssat + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT __builtin_arm_usat + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) ); +} + +#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat) +{ + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; +} + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat) +{ + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief Load-Acquire (8 bit) + \details Executes a LDAB instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return ((uint8_t) result); +} + + +/** + \brief Load-Acquire (16 bit) + \details Executes a LDAH instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return ((uint16_t) result); +} + + +/** + \brief Load-Acquire (32 bit) + \details Executes a LDA instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return(result); +} + + +/** + \brief Store-Release (8 bit) + \details Executes a STLB instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Store-Release (16 bit) + \details Executes a STLH instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Store-Release (32 bit) + \details Executes a STL instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Load-Acquire Exclusive (8 bit) + \details Executes a LDAB exclusive instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDAEXB (uint8_t)__builtin_arm_ldaex + + +/** + \brief Load-Acquire Exclusive (16 bit) + \details Executes a LDAH exclusive instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDAEXH (uint16_t)__builtin_arm_ldaex + + +/** + \brief Load-Acquire Exclusive (32 bit) + \details Executes a LDA exclusive instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDAEX (uint32_t)__builtin_arm_ldaex + + +/** + \brief Store-Release Exclusive (8 bit) + \details Executes a STLB exclusive instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEXB (uint32_t)__builtin_arm_stlex + + +/** + \brief Store-Release Exclusive (16 bit) + \details Executes a STLH exclusive instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEXH (uint32_t)__builtin_arm_stlex + + +/** + \brief Store-Release Exclusive (32 bit) + \details Executes a STL exclusive instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEX (uint32_t)__builtin_arm_stlex + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing special-purpose register PRIMASK. + Can only be executed in Privileged modes. + */ +#ifndef __ARM_COMPAT_H +__STATIC_FORCEINLINE void __enable_irq(void) +{ + __ASM volatile ("cpsie i" : : : "memory"); +} +#endif + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting special-purpose register PRIMASK. + Can only be executed in Privileged modes. + */ +#ifndef __ARM_COMPAT_H +__STATIC_FORCEINLINE void __disable_irq(void) +{ + __ASM volatile ("cpsid i" : : : "memory"); +} +#endif + + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CONTROL(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Control Register (non-secure) + \details Returns the content of the non-secure Control Register when in secure mode. + \return non-secure Control Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) +{ + __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); + __ISB(); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Control Register (non-secure) + \details Writes the given value to the non-secure Control Register when in secure state. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) +{ + __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); + __ISB(); +} +#endif + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_IPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_APSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_xPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer (non-secure) + \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state. + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state. + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); +} +#endif + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer (non-secure) + \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state. + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); +} +#endif + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Stack Pointer (non-secure) + \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state. + \return SP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, sp_ns" : "=r" (result) ); + return(result); +} + + +/** + \brief Set Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state. + \param [in] topOfStack Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack) +{ + __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : ); +} +#endif + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Priority Mask (non-secure) + \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Priority Mask (non-secure) + \details Assigns the given value to the non-secure Priority Mask Register when in secure state. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) +{ + __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); +} +#endif + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing special-purpose register FAULTMASK. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __enable_fault_irq(void) +{ + __ASM volatile ("cpsie f" : : : "memory"); +} + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting special-purpose register FAULTMASK. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __disable_fault_irq(void) +{ + __ASM volatile ("cpsid f" : : : "memory"); +} + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Base Priority (non-secure) + \details Returns the current value of the non-secure Base Priority register when in secure state. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri) +{ + __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Base Priority (non-secure) + \details Assigns the given value to the non-secure Base Priority register when in secure state. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); +} +#endif + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Fault Mask (non-secure) + \details Returns the current value of the non-secure Fault Mask register when in secure state. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Fault Mask (non-secure) + \details Assigns the given value to the non-secure Fault Mask register when in secure state. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); +} +#endif + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + +/** + \brief Get Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim" : "=r" (result) ); + return result; +#endif +} + +#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); +#endif +} +#endif + + +/** + \brief Get Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim" : "=r" (result) ); + return result; +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state. + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). + \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state. + \param [in] MainStackPtrLimit Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); +#endif +} +#endif + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#define __get_FPSCR (uint32_t)__builtin_arm_get_fpscr +#else +#define __get_FPSCR() ((uint32_t)0U) +#endif + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#define __set_FPSCR __builtin_arm_set_fpscr +#else +#define __set_FPSCR(x) ((void)(x)) +#endif + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) + +__STATIC_FORCEINLINE uint32_t __SADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__STATIC_FORCEINLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__STATIC_FORCEINLINE uint32_t __SADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USAD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#define __SSAT16(ARG1,ARG2) \ +({ \ + int32_t __RES, __ARG1 = (ARG1); \ + __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +#define __USAT16(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +__STATIC_FORCEINLINE uint32_t __UXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint32_t __SEL (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE int32_t __QADD( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE int32_t __QSUB( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ + ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) + +#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ + ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) + +#define __SXTB16_RORn(ARG1, ARG2) __SXTB16(__ROR(ARG1, ARG2)) + +#define __SXTAB16_RORn(ARG1, ARG2, ARG3) __SXTAB16(ARG1, __ROR(ARG2, ARG3)) + +__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) +{ + int32_t result; + + __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#endif /* (__ARM_FEATURE_DSP == 1) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#endif /* __CMSIS_ARMCLANG_H */ diff --git a/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/CMSIS/Include/cmsis_compiler.h b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/CMSIS/Include/cmsis_compiler.h new file mode 100644 index 0000000000..adbf296f15 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/CMSIS/Include/cmsis_compiler.h @@ -0,0 +1,283 @@ +/**************************************************************************//** + * @file cmsis_compiler.h + * @brief CMSIS compiler generic header file + * @version V5.1.0 + * @date 09. October 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_COMPILER_H +#define __CMSIS_COMPILER_H + +#include + +/* + * Arm Compiler 4/5 + */ +#if defined ( __CC_ARM ) + #include "cmsis_armcc.h" + + +/* + * Arm Compiler 6.6 LTM (armclang) + */ +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) && (__ARMCC_VERSION < 6100100) + #include "cmsis_armclang_ltm.h" + + /* + * Arm Compiler above 6.10.1 (armclang) + */ +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6100100) + #include "cmsis_armclang.h" + + +/* + * GNU Compiler + */ +#elif defined ( __GNUC__ ) + #include "cmsis_gcc.h" + + +/* + * IAR Compiler + */ +#elif defined ( __ICCARM__ ) + #include + + +/* + * TI Arm Compiler + */ +#elif defined ( __TI_ARM__ ) + #include + + #ifndef __ASM + #define __ASM __asm + #endif + #ifndef __INLINE + #define __INLINE inline + #endif + #ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline + #endif + #ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __STATIC_INLINE + #endif + #ifndef __NO_RETURN + #define __NO_RETURN __attribute__((noreturn)) + #endif + #ifndef __USED + #define __USED __attribute__((used)) + #endif + #ifndef __WEAK + #define __WEAK __attribute__((weak)) + #endif + #ifndef __PACKED + #define __PACKED __attribute__((packed)) + #endif + #ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed)) + #endif + #ifndef __PACKED_UNION + #define __PACKED_UNION union __attribute__((packed)) + #endif + #ifndef __UNALIGNED_UINT32 /* deprecated */ + struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + #endif + #ifndef __UNALIGNED_UINT16_WRITE + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void*)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT16_READ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) + #endif + #ifndef __UNALIGNED_UINT32_WRITE + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT32_READ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) + #endif + #ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) + #endif + #ifndef __RESTRICT + #define __RESTRICT __restrict + #endif + #ifndef __COMPILER_BARRIER + #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored. + #define __COMPILER_BARRIER() (void)0 + #endif + + +/* + * TASKING Compiler + */ +#elif defined ( __TASKING__ ) + /* + * The CMSIS functions have been implemented as intrinsics in the compiler. + * Please use "carm -?i" to get an up to date list of all intrinsics, + * Including the CMSIS ones. + */ + + #ifndef __ASM + #define __ASM __asm + #endif + #ifndef __INLINE + #define __INLINE inline + #endif + #ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline + #endif + #ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __STATIC_INLINE + #endif + #ifndef __NO_RETURN + #define __NO_RETURN __attribute__((noreturn)) + #endif + #ifndef __USED + #define __USED __attribute__((used)) + #endif + #ifndef __WEAK + #define __WEAK __attribute__((weak)) + #endif + #ifndef __PACKED + #define __PACKED __packed__ + #endif + #ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __packed__ + #endif + #ifndef __PACKED_UNION + #define __PACKED_UNION union __packed__ + #endif + #ifndef __UNALIGNED_UINT32 /* deprecated */ + struct __packed__ T_UINT32 { uint32_t v; }; + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + #endif + #ifndef __UNALIGNED_UINT16_WRITE + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT16_READ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) + #endif + #ifndef __UNALIGNED_UINT32_WRITE + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT32_READ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) + #endif + #ifndef __ALIGNED + #define __ALIGNED(x) __align(x) + #endif + #ifndef __RESTRICT + #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. + #define __RESTRICT + #endif + #ifndef __COMPILER_BARRIER + #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored. + #define __COMPILER_BARRIER() (void)0 + #endif + + +/* + * COSMIC Compiler + */ +#elif defined ( __CSMC__ ) + #include + + #ifndef __ASM + #define __ASM _asm + #endif + #ifndef __INLINE + #define __INLINE inline + #endif + #ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline + #endif + #ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __STATIC_INLINE + #endif + #ifndef __NO_RETURN + // NO RETURN is automatically detected hence no warning here + #define __NO_RETURN + #endif + #ifndef __USED + #warning No compiler specific solution for __USED. __USED is ignored. + #define __USED + #endif + #ifndef __WEAK + #define __WEAK __weak + #endif + #ifndef __PACKED + #define __PACKED @packed + #endif + #ifndef __PACKED_STRUCT + #define __PACKED_STRUCT @packed struct + #endif + #ifndef __PACKED_UNION + #define __PACKED_UNION @packed union + #endif + #ifndef __UNALIGNED_UINT32 /* deprecated */ + @packed struct T_UINT32 { uint32_t v; }; + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + #endif + #ifndef __UNALIGNED_UINT16_WRITE + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT16_READ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) + #endif + #ifndef __UNALIGNED_UINT32_WRITE + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT32_READ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) + #endif + #ifndef __ALIGNED + #warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored. + #define __ALIGNED(x) + #endif + #ifndef __RESTRICT + #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. + #define __RESTRICT + #endif + #ifndef __COMPILER_BARRIER + #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored. + #define __COMPILER_BARRIER() (void)0 + #endif + + +#else + #error Unknown compiler. +#endif + + +#endif /* __CMSIS_COMPILER_H */ + diff --git a/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/CMSIS/Include/cmsis_gcc.h b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/CMSIS/Include/cmsis_gcc.h new file mode 100644 index 0000000000..67bda4ef3c --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/CMSIS/Include/cmsis_gcc.h @@ -0,0 +1,2211 @@ +/**************************************************************************//** + * @file cmsis_gcc.h + * @brief CMSIS compiler GCC header file + * @version V5.4.1 + * @date 27. May 2021 + ******************************************************************************/ +/* + * Copyright (c) 2009-2021 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_GCC_H +#define __CMSIS_GCC_H + +/* ignore some GCC warnings */ +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wsign-conversion" +#pragma GCC diagnostic ignored "-Wconversion" +#pragma GCC diagnostic ignored "-Wunused-parameter" + +/* Fallback for __has_builtin */ +#ifndef __has_builtin + #define __has_builtin(x) (0) +#endif + +/* CMSIS compiler specific defines */ +#ifndef __ASM + #define __ASM __asm +#endif +#ifndef __INLINE + #define __INLINE inline +#endif +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline +#endif +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __attribute__((always_inline)) static inline +#endif +#ifndef __NO_RETURN + #define __NO_RETURN __attribute__((__noreturn__)) +#endif +#ifndef __USED + #define __USED __attribute__((used)) +#endif +#ifndef __WEAK + #define __WEAK __attribute__((weak)) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_UNION + #define __PACKED_UNION union __attribute__((packed, aligned(1))) +#endif +#ifndef __UNALIGNED_UINT32 /* deprecated */ + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) +#endif +#ifndef __UNALIGNED_UINT16_WRITE + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT16_READ + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) +#endif +#ifndef __UNALIGNED_UINT32_WRITE + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT32_READ + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) +#endif +#ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __RESTRICT + #define __RESTRICT __restrict +#endif +#ifndef __COMPILER_BARRIER + #define __COMPILER_BARRIER() __ASM volatile("":::"memory") +#endif + +/* ######################### Startup and Lowlevel Init ######################## */ + +#ifndef __PROGRAM_START + +/** + \brief Initializes data and bss sections + \details This default implementations initialized all data and additional bss + sections relying on .copy.table and .zero.table specified properly + in the used linker script. + + */ +__STATIC_FORCEINLINE __NO_RETURN void __cmsis_start(void) +{ + extern void _start(void) __NO_RETURN; + + typedef struct { + uint32_t const* src; + uint32_t* dest; + uint32_t wlen; + } __copy_table_t; + + typedef struct { + uint32_t* dest; + uint32_t wlen; + } __zero_table_t; + + extern const __copy_table_t __copy_table_start__; + extern const __copy_table_t __copy_table_end__; + extern const __zero_table_t __zero_table_start__; + extern const __zero_table_t __zero_table_end__; + + for (__copy_table_t const* pTable = &__copy_table_start__; pTable < &__copy_table_end__; ++pTable) { + for(uint32_t i=0u; iwlen; ++i) { + pTable->dest[i] = pTable->src[i]; + } + } + + for (__zero_table_t const* pTable = &__zero_table_start__; pTable < &__zero_table_end__; ++pTable) { + for(uint32_t i=0u; iwlen; ++i) { + pTable->dest[i] = 0u; + } + } + + _start(); +} + +#define __PROGRAM_START __cmsis_start +#endif + +#ifndef __INITIAL_SP +#define __INITIAL_SP __StackTop +#endif + +#ifndef __STACK_LIMIT +#define __STACK_LIMIT __StackLimit +#endif + +#ifndef __VECTOR_TABLE +#define __VECTOR_TABLE __Vectors +#endif + +#ifndef __VECTOR_TABLE_ATTRIBUTE +#define __VECTOR_TABLE_ATTRIBUTE __attribute__((used, section(".vectors"))) +#endif + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +#ifndef __STACK_SEAL +#define __STACK_SEAL __StackSeal +#endif + +#ifndef __TZ_STACK_SEAL_SIZE +#define __TZ_STACK_SEAL_SIZE 8U +#endif + +#ifndef __TZ_STACK_SEAL_VALUE +#define __TZ_STACK_SEAL_VALUE 0xFEF5EDA5FEF5EDA5ULL +#endif + + +__STATIC_FORCEINLINE void __TZ_set_STACKSEAL_S (uint32_t* stackTop) { + *((uint64_t *)stackTop) = __TZ_STACK_SEAL_VALUE; +} +#endif + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/* Define macros for porting to both thumb1 and thumb2. + * For thumb1, use low register (r0-r7), specified by constraint "l" + * Otherwise, use general registers, specified by constraint "r" */ +#if defined (__thumb__) && !defined (__thumb2__) +#define __CMSIS_GCC_OUT_REG(r) "=l" (r) +#define __CMSIS_GCC_RW_REG(r) "+l" (r) +#define __CMSIS_GCC_USE_REG(r) "l" (r) +#else +#define __CMSIS_GCC_OUT_REG(r) "=r" (r) +#define __CMSIS_GCC_RW_REG(r) "+r" (r) +#define __CMSIS_GCC_USE_REG(r) "r" (r) +#endif + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP() __ASM volatile ("nop") + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +#define __WFI() __ASM volatile ("wfi":::"memory") + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE() __ASM volatile ("wfe":::"memory") + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV() __ASM volatile ("sev") + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +__STATIC_FORCEINLINE void __ISB(void) +{ + __ASM volatile ("isb 0xF":::"memory"); +} + + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +__STATIC_FORCEINLINE void __DSB(void) +{ + __ASM volatile ("dsb 0xF":::"memory"); +} + + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +__STATIC_FORCEINLINE void __DMB(void) +{ + __ASM volatile ("dmb 0xF":::"memory"); +} + + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE uint32_t __REV(uint32_t value) +{ +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5) + return __builtin_bswap32(value); +#else + uint32_t result; + + __ASM ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return result; +#endif +} + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE uint32_t __REV16(uint32_t value) +{ + uint32_t result; + + __ASM ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return result; +} + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE int16_t __REVSH(int16_t value) +{ +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + return (int16_t)__builtin_bswap16(value); +#else + int16_t result; + + __ASM ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return result; +#endif +} + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) +{ + op2 %= 32U; + if (op2 == 0U) + { + return op1; + } + return (op1 >> op2) | (op1 << (32U - op2)); +} + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __ASM volatile ("bkpt "#value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE uint32_t __RBIT(uint32_t value) +{ + uint32_t result; + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) + __ASM ("rbit %0, %1" : "=r" (result) : "r" (value) ); +#else + uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */ + + result = value; /* r will be reversed bits of v; first get LSB of v */ + for (value >>= 1U; value != 0U; value >>= 1U) + { + result <<= 1U; + result |= value & 1U; + s--; + } + result <<= s; /* shift when v's highest bits are zero */ +#endif + return result; +} + + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +__STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value) +{ + /* Even though __builtin_clz produces a CLZ instruction on ARM, formally + __builtin_clz(0) is undefined behaviour, so handle this case specially. + This guarantees ARM-compatible results if happening to compile on a non-ARM + target, and ensures the compiler doesn't decide to activate any + optimisations using the logic "value was passed to __builtin_clz, so it + is non-zero". + ARM GCC 7.3 and possibly earlier will optimise this test away, leaving a + single CLZ instruction. + */ + if (value == 0U) + { + return 32U; + } + return __builtin_clz(value); +} + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDREXB(volatile uint8_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDREXH(volatile uint16_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDREXW(volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); + return(result); +} + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr) +{ + uint32_t result; + + __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr) +{ + uint32_t result; + + __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); + return(result); +} + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +__STATIC_FORCEINLINE void __CLREX(void) +{ + __ASM volatile ("clrex" ::: "memory"); +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] ARG1 Value to be saturated + \param [in] ARG2 Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT(ARG1, ARG2) \ +__extension__ \ +({ \ + int32_t __RES, __ARG1 = (ARG1); \ + __ASM volatile ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) : "cc" ); \ + __RES; \ + }) + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] ARG1 Value to be saturated + \param [in] ARG2 Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT(ARG1, ARG2) \ +__extension__ \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM volatile ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) : "cc" ); \ + __RES; \ + }) + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" ); +#endif + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" ); +#endif + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) ); +} + +#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat) +{ + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; +} + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat) +{ + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief Load-Acquire (8 bit) + \details Executes a LDAB instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return ((uint8_t) result); +} + + +/** + \brief Load-Acquire (16 bit) + \details Executes a LDAH instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return ((uint16_t) result); +} + + +/** + \brief Load-Acquire (32 bit) + \details Executes a LDA instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return(result); +} + + +/** + \brief Store-Release (8 bit) + \details Executes a STLB instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Store-Release (16 bit) + \details Executes a STLH instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Store-Release (32 bit) + \details Executes a STL instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Load-Acquire Exclusive (8 bit) + \details Executes a LDAB exclusive instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDAEXB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldaexb %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return ((uint8_t) result); +} + + +/** + \brief Load-Acquire Exclusive (16 bit) + \details Executes a LDAH exclusive instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDAEXH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldaexh %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return ((uint16_t) result); +} + + +/** + \brief Load-Acquire Exclusive (32 bit) + \details Executes a LDA exclusive instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDAEX(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldaex %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return(result); +} + + +/** + \brief Store-Release Exclusive (8 bit) + \details Executes a STLB exclusive instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("stlexb %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); + return(result); +} + + +/** + \brief Store-Release Exclusive (16 bit) + \details Executes a STLH exclusive instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("stlexh %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); + return(result); +} + + +/** + \brief Store-Release Exclusive (32 bit) + \details Executes a STL exclusive instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("stlex %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); + return(result); +} + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing special-purpose register PRIMASK. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __enable_irq(void) +{ + __ASM volatile ("cpsie i" : : : "memory"); +} + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting special-purpose register PRIMASK. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __disable_irq(void) +{ + __ASM volatile ("cpsid i" : : : "memory"); +} + + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CONTROL(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Control Register (non-secure) + \details Returns the content of the non-secure Control Register when in secure mode. + \return non-secure Control Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) +{ + __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); + __ISB(); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Control Register (non-secure) + \details Writes the given value to the non-secure Control Register when in secure state. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) +{ + __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); + __ISB(); +} +#endif + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_IPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_APSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_xPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer (non-secure) + \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state. + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state. + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); +} +#endif + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer (non-secure) + \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state. + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); +} +#endif + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Stack Pointer (non-secure) + \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state. + \return SP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, sp_ns" : "=r" (result) ); + return(result); +} + + +/** + \brief Set Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state. + \param [in] topOfStack Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack) +{ + __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : ); +} +#endif + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Priority Mask (non-secure) + \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Priority Mask (non-secure) + \details Assigns the given value to the non-secure Priority Mask Register when in secure state. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) +{ + __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); +} +#endif + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing special-purpose register FAULTMASK. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __enable_fault_irq(void) +{ + __ASM volatile ("cpsie f" : : : "memory"); +} + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting special-purpose register FAULTMASK. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __disable_fault_irq(void) +{ + __ASM volatile ("cpsid f" : : : "memory"); +} + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Base Priority (non-secure) + \details Returns the current value of the non-secure Base Priority register when in secure state. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri) +{ + __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Base Priority (non-secure) + \details Assigns the given value to the non-secure Base Priority register when in secure state. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); +} +#endif + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Fault Mask (non-secure) + \details Returns the current value of the non-secure Fault Mask register when in secure state. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Fault Mask (non-secure) + \details Assigns the given value to the non-secure Fault Mask register when in secure state. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); +} +#endif + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + +/** + \brief Get Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim" : "=r" (result) ); + return result; +#endif +} + +#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); +#endif +} +#endif + + +/** + \brief Get Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim" : "=r" (result) ); + return result; +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state. + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). + \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state. + \param [in] MainStackPtrLimit Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); +#endif +} +#endif + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +__STATIC_FORCEINLINE uint32_t __get_FPSCR(void) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#if __has_builtin(__builtin_arm_get_fpscr) +// Re-enable using built-in when GCC has been fixed +// || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2) + /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */ + return __builtin_arm_get_fpscr(); +#else + uint32_t result; + + __ASM volatile ("VMRS %0, fpscr" : "=r" (result) ); + return(result); +#endif +#else + return(0U); +#endif +} + + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +__STATIC_FORCEINLINE void __set_FPSCR(uint32_t fpscr) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#if __has_builtin(__builtin_arm_set_fpscr) +// Re-enable using built-in when GCC has been fixed +// || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2) + /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */ + __builtin_arm_set_fpscr(fpscr); +#else + __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc", "memory"); +#endif +#else + (void)fpscr; +#endif +} + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) + +__STATIC_FORCEINLINE uint32_t __SADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__STATIC_FORCEINLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__STATIC_FORCEINLINE uint32_t __SADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USAD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#define __SSAT16(ARG1, ARG2) \ +__extension__ \ +({ \ + int32_t __RES, __ARG1 = (ARG1); \ + __ASM volatile ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) : "cc" ); \ + __RES; \ + }) + +#define __USAT16(ARG1, ARG2) \ +__extension__ \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM volatile ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) : "cc" ); \ + __RES; \ + }) + +__STATIC_FORCEINLINE uint32_t __UXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM ("uxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM ("sxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTB16_RORn(uint32_t op1, uint32_t rotate) +{ + uint32_t result; + if (__builtin_constant_p(rotate) && ((rotate == 8U) || (rotate == 16U) || (rotate == 24U))) { + __ASM volatile ("sxtb16 %0, %1, ROR %2" : "=r" (result) : "r" (op1), "i" (rotate) ); + } else { + result = __SXTB16(__ROR(op1, rotate)) ; + } + return result; +} + +__STATIC_FORCEINLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTAB16_RORn(uint32_t op1, uint32_t op2, uint32_t rotate) +{ + uint32_t result; + if (__builtin_constant_p(rotate) && ((rotate == 8U) || (rotate == 16U) || (rotate == 24U))) { + __ASM volatile ("sxtab16 %0, %1, %2, ROR %3" : "=r" (result) : "r" (op1) , "r" (op2) , "i" (rotate)); + } else { + result = __SXTAB16(op1, __ROR(op2, rotate)); + } + return result; +} + + +__STATIC_FORCEINLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint32_t __SEL (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE int32_t __QADD( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE int32_t __QSUB( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +#define __PKHBT(ARG1,ARG2,ARG3) \ +__extension__ \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) + +#define __PKHTB(ARG1,ARG2,ARG3) \ +__extension__ \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + if (ARG3 == 0) \ + __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \ + else \ + __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) + + +__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) +{ + int32_t result; + + __ASM ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#endif /* (__ARM_FEATURE_DSP == 1) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#pragma GCC diagnostic pop + +#endif /* __CMSIS_GCC_H */ diff --git a/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/CMSIS/Include/cmsis_iccarm.h b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/CMSIS/Include/cmsis_iccarm.h new file mode 100644 index 0000000000..65b824b009 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/CMSIS/Include/cmsis_iccarm.h @@ -0,0 +1,1002 @@ +/**************************************************************************//** + * @file cmsis_iccarm.h + * @brief CMSIS compiler ICCARM (IAR Compiler for Arm) header file + * @version V5.3.0 + * @date 14. April 2021 + ******************************************************************************/ + +//------------------------------------------------------------------------------ +// +// Copyright (c) 2017-2021 IAR Systems +// Copyright (c) 2017-2021 Arm Limited. All rights reserved. +// +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License") +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +//------------------------------------------------------------------------------ + + +#ifndef __CMSIS_ICCARM_H__ +#define __CMSIS_ICCARM_H__ + +#ifndef __ICCARM__ + #error This file should only be compiled by ICCARM +#endif + +#pragma system_include + +#define __IAR_FT _Pragma("inline=forced") __intrinsic + +#if (__VER__ >= 8000000) + #define __ICCARM_V8 1 +#else + #define __ICCARM_V8 0 +#endif + +#ifndef __ALIGNED + #if __ICCARM_V8 + #define __ALIGNED(x) __attribute__((aligned(x))) + #elif (__VER__ >= 7080000) + /* Needs IAR language extensions */ + #define __ALIGNED(x) __attribute__((aligned(x))) + #else + #warning No compiler specific solution for __ALIGNED.__ALIGNED is ignored. + #define __ALIGNED(x) + #endif +#endif + + +/* Define compiler macros for CPU architecture, used in CMSIS 5. + */ +#if __ARM_ARCH_6M__ || __ARM_ARCH_7M__ || __ARM_ARCH_7EM__ || __ARM_ARCH_8M_BASE__ || __ARM_ARCH_8M_MAIN__ +/* Macros already defined */ +#else + #if defined(__ARM8M_MAINLINE__) || defined(__ARM8EM_MAINLINE__) + #define __ARM_ARCH_8M_MAIN__ 1 + #elif defined(__ARM8M_BASELINE__) + #define __ARM_ARCH_8M_BASE__ 1 + #elif defined(__ARM_ARCH_PROFILE) && __ARM_ARCH_PROFILE == 'M' + #if __ARM_ARCH == 6 + #define __ARM_ARCH_6M__ 1 + #elif __ARM_ARCH == 7 + #if __ARM_FEATURE_DSP + #define __ARM_ARCH_7EM__ 1 + #else + #define __ARM_ARCH_7M__ 1 + #endif + #endif /* __ARM_ARCH */ + #endif /* __ARM_ARCH_PROFILE == 'M' */ +#endif + +/* Alternativ core deduction for older ICCARM's */ +#if !defined(__ARM_ARCH_6M__) && !defined(__ARM_ARCH_7M__) && !defined(__ARM_ARCH_7EM__) && \ + !defined(__ARM_ARCH_8M_BASE__) && !defined(__ARM_ARCH_8M_MAIN__) + #if defined(__ARM6M__) && (__CORE__ == __ARM6M__) + #define __ARM_ARCH_6M__ 1 + #elif defined(__ARM7M__) && (__CORE__ == __ARM7M__) + #define __ARM_ARCH_7M__ 1 + #elif defined(__ARM7EM__) && (__CORE__ == __ARM7EM__) + #define __ARM_ARCH_7EM__ 1 + #elif defined(__ARM8M_BASELINE__) && (__CORE == __ARM8M_BASELINE__) + #define __ARM_ARCH_8M_BASE__ 1 + #elif defined(__ARM8M_MAINLINE__) && (__CORE == __ARM8M_MAINLINE__) + #define __ARM_ARCH_8M_MAIN__ 1 + #elif defined(__ARM8EM_MAINLINE__) && (__CORE == __ARM8EM_MAINLINE__) + #define __ARM_ARCH_8M_MAIN__ 1 + #else + #error "Unknown target." + #endif +#endif + + + +#if defined(__ARM_ARCH_6M__) && __ARM_ARCH_6M__==1 + #define __IAR_M0_FAMILY 1 +#elif defined(__ARM_ARCH_8M_BASE__) && __ARM_ARCH_8M_BASE__==1 + #define __IAR_M0_FAMILY 1 +#else + #define __IAR_M0_FAMILY 0 +#endif + + +#ifndef __ASM + #define __ASM __asm +#endif + +#ifndef __COMPILER_BARRIER + #define __COMPILER_BARRIER() __ASM volatile("":::"memory") +#endif + +#ifndef __INLINE + #define __INLINE inline +#endif + +#ifndef __NO_RETURN + #if __ICCARM_V8 + #define __NO_RETURN __attribute__((__noreturn__)) + #else + #define __NO_RETURN _Pragma("object_attribute=__noreturn") + #endif +#endif + +#ifndef __PACKED + #if __ICCARM_V8 + #define __PACKED __attribute__((packed, aligned(1))) + #else + /* Needs IAR language extensions */ + #define __PACKED __packed + #endif +#endif + +#ifndef __PACKED_STRUCT + #if __ICCARM_V8 + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) + #else + /* Needs IAR language extensions */ + #define __PACKED_STRUCT __packed struct + #endif +#endif + +#ifndef __PACKED_UNION + #if __ICCARM_V8 + #define __PACKED_UNION union __attribute__((packed, aligned(1))) + #else + /* Needs IAR language extensions */ + #define __PACKED_UNION __packed union + #endif +#endif + +#ifndef __RESTRICT + #if __ICCARM_V8 + #define __RESTRICT __restrict + #else + /* Needs IAR language extensions */ + #define __RESTRICT restrict + #endif +#endif + +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline +#endif + +#ifndef __FORCEINLINE + #define __FORCEINLINE _Pragma("inline=forced") +#endif + +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __FORCEINLINE __STATIC_INLINE +#endif + +#ifndef __UNALIGNED_UINT16_READ +#pragma language=save +#pragma language=extended +__IAR_FT uint16_t __iar_uint16_read(void const *ptr) +{ + return *(__packed uint16_t*)(ptr); +} +#pragma language=restore +#define __UNALIGNED_UINT16_READ(PTR) __iar_uint16_read(PTR) +#endif + + +#ifndef __UNALIGNED_UINT16_WRITE +#pragma language=save +#pragma language=extended +__IAR_FT void __iar_uint16_write(void const *ptr, uint16_t val) +{ + *(__packed uint16_t*)(ptr) = val;; +} +#pragma language=restore +#define __UNALIGNED_UINT16_WRITE(PTR,VAL) __iar_uint16_write(PTR,VAL) +#endif + +#ifndef __UNALIGNED_UINT32_READ +#pragma language=save +#pragma language=extended +__IAR_FT uint32_t __iar_uint32_read(void const *ptr) +{ + return *(__packed uint32_t*)(ptr); +} +#pragma language=restore +#define __UNALIGNED_UINT32_READ(PTR) __iar_uint32_read(PTR) +#endif + +#ifndef __UNALIGNED_UINT32_WRITE +#pragma language=save +#pragma language=extended +__IAR_FT void __iar_uint32_write(void const *ptr, uint32_t val) +{ + *(__packed uint32_t*)(ptr) = val;; +} +#pragma language=restore +#define __UNALIGNED_UINT32_WRITE(PTR,VAL) __iar_uint32_write(PTR,VAL) +#endif + +#ifndef __UNALIGNED_UINT32 /* deprecated */ +#pragma language=save +#pragma language=extended +__packed struct __iar_u32 { uint32_t v; }; +#pragma language=restore +#define __UNALIGNED_UINT32(PTR) (((struct __iar_u32 *)(PTR))->v) +#endif + +#ifndef __USED + #if __ICCARM_V8 + #define __USED __attribute__((used)) + #else + #define __USED _Pragma("__root") + #endif +#endif + +#undef __WEAK /* undo the definition from DLib_Defaults.h */ +#ifndef __WEAK + #if __ICCARM_V8 + #define __WEAK __attribute__((weak)) + #else + #define __WEAK _Pragma("__weak") + #endif +#endif + +#ifndef __PROGRAM_START +#define __PROGRAM_START __iar_program_start +#endif + +#ifndef __INITIAL_SP +#define __INITIAL_SP CSTACK$$Limit +#endif + +#ifndef __STACK_LIMIT +#define __STACK_LIMIT CSTACK$$Base +#endif + +#ifndef __VECTOR_TABLE +#define __VECTOR_TABLE __vector_table +#endif + +#ifndef __VECTOR_TABLE_ATTRIBUTE +#define __VECTOR_TABLE_ATTRIBUTE @".intvec" +#endif + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +#ifndef __STACK_SEAL +#define __STACK_SEAL STACKSEAL$$Base +#endif + +#ifndef __TZ_STACK_SEAL_SIZE +#define __TZ_STACK_SEAL_SIZE 8U +#endif + +#ifndef __TZ_STACK_SEAL_VALUE +#define __TZ_STACK_SEAL_VALUE 0xFEF5EDA5FEF5EDA5ULL +#endif + +__STATIC_FORCEINLINE void __TZ_set_STACKSEAL_S (uint32_t* stackTop) { + *((uint64_t *)stackTop) = __TZ_STACK_SEAL_VALUE; +} +#endif + +#ifndef __ICCARM_INTRINSICS_VERSION__ + #define __ICCARM_INTRINSICS_VERSION__ 0 +#endif + +#if __ICCARM_INTRINSICS_VERSION__ == 2 + + #if defined(__CLZ) + #undef __CLZ + #endif + #if defined(__REVSH) + #undef __REVSH + #endif + #if defined(__RBIT) + #undef __RBIT + #endif + #if defined(__SSAT) + #undef __SSAT + #endif + #if defined(__USAT) + #undef __USAT + #endif + + #include "iccarm_builtin.h" + + #define __disable_fault_irq __iar_builtin_disable_fiq + #define __disable_irq __iar_builtin_disable_interrupt + #define __enable_fault_irq __iar_builtin_enable_fiq + #define __enable_irq __iar_builtin_enable_interrupt + #define __arm_rsr __iar_builtin_rsr + #define __arm_wsr __iar_builtin_wsr + + + #define __get_APSR() (__arm_rsr("APSR")) + #define __get_BASEPRI() (__arm_rsr("BASEPRI")) + #define __get_CONTROL() (__arm_rsr("CONTROL")) + #define __get_FAULTMASK() (__arm_rsr("FAULTMASK")) + + #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) + #define __get_FPSCR() (__arm_rsr("FPSCR")) + #define __set_FPSCR(VALUE) (__arm_wsr("FPSCR", (VALUE))) + #else + #define __get_FPSCR() ( 0 ) + #define __set_FPSCR(VALUE) ((void)VALUE) + #endif + + #define __get_IPSR() (__arm_rsr("IPSR")) + #define __get_MSP() (__arm_rsr("MSP")) + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + #define __get_MSPLIM() (0U) + #else + #define __get_MSPLIM() (__arm_rsr("MSPLIM")) + #endif + #define __get_PRIMASK() (__arm_rsr("PRIMASK")) + #define __get_PSP() (__arm_rsr("PSP")) + + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + #define __get_PSPLIM() (0U) + #else + #define __get_PSPLIM() (__arm_rsr("PSPLIM")) + #endif + + #define __get_xPSR() (__arm_rsr("xPSR")) + + #define __set_BASEPRI(VALUE) (__arm_wsr("BASEPRI", (VALUE))) + #define __set_BASEPRI_MAX(VALUE) (__arm_wsr("BASEPRI_MAX", (VALUE))) + +__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) +{ + __arm_wsr("CONTROL", control); + __iar_builtin_ISB(); +} + + #define __set_FAULTMASK(VALUE) (__arm_wsr("FAULTMASK", (VALUE))) + #define __set_MSP(VALUE) (__arm_wsr("MSP", (VALUE))) + + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + #define __set_MSPLIM(VALUE) ((void)(VALUE)) + #else + #define __set_MSPLIM(VALUE) (__arm_wsr("MSPLIM", (VALUE))) + #endif + #define __set_PRIMASK(VALUE) (__arm_wsr("PRIMASK", (VALUE))) + #define __set_PSP(VALUE) (__arm_wsr("PSP", (VALUE))) + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + #define __set_PSPLIM(VALUE) ((void)(VALUE)) + #else + #define __set_PSPLIM(VALUE) (__arm_wsr("PSPLIM", (VALUE))) + #endif + + #define __TZ_get_CONTROL_NS() (__arm_rsr("CONTROL_NS")) + +__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) +{ + __arm_wsr("CONTROL_NS", control); + __iar_builtin_ISB(); +} + + #define __TZ_get_PSP_NS() (__arm_rsr("PSP_NS")) + #define __TZ_set_PSP_NS(VALUE) (__arm_wsr("PSP_NS", (VALUE))) + #define __TZ_get_MSP_NS() (__arm_rsr("MSP_NS")) + #define __TZ_set_MSP_NS(VALUE) (__arm_wsr("MSP_NS", (VALUE))) + #define __TZ_get_SP_NS() (__arm_rsr("SP_NS")) + #define __TZ_set_SP_NS(VALUE) (__arm_wsr("SP_NS", (VALUE))) + #define __TZ_get_PRIMASK_NS() (__arm_rsr("PRIMASK_NS")) + #define __TZ_set_PRIMASK_NS(VALUE) (__arm_wsr("PRIMASK_NS", (VALUE))) + #define __TZ_get_BASEPRI_NS() (__arm_rsr("BASEPRI_NS")) + #define __TZ_set_BASEPRI_NS(VALUE) (__arm_wsr("BASEPRI_NS", (VALUE))) + #define __TZ_get_FAULTMASK_NS() (__arm_rsr("FAULTMASK_NS")) + #define __TZ_set_FAULTMASK_NS(VALUE)(__arm_wsr("FAULTMASK_NS", (VALUE))) + + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + #define __TZ_get_PSPLIM_NS() (0U) + #define __TZ_set_PSPLIM_NS(VALUE) ((void)(VALUE)) + #else + #define __TZ_get_PSPLIM_NS() (__arm_rsr("PSPLIM_NS")) + #define __TZ_set_PSPLIM_NS(VALUE) (__arm_wsr("PSPLIM_NS", (VALUE))) + #endif + + #define __TZ_get_MSPLIM_NS() (__arm_rsr("MSPLIM_NS")) + #define __TZ_set_MSPLIM_NS(VALUE) (__arm_wsr("MSPLIM_NS", (VALUE))) + + #define __NOP __iar_builtin_no_operation + + #define __CLZ __iar_builtin_CLZ + #define __CLREX __iar_builtin_CLREX + + #define __DMB __iar_builtin_DMB + #define __DSB __iar_builtin_DSB + #define __ISB __iar_builtin_ISB + + #define __LDREXB __iar_builtin_LDREXB + #define __LDREXH __iar_builtin_LDREXH + #define __LDREXW __iar_builtin_LDREX + + #define __RBIT __iar_builtin_RBIT + #define __REV __iar_builtin_REV + #define __REV16 __iar_builtin_REV16 + + __IAR_FT int16_t __REVSH(int16_t val) + { + return (int16_t) __iar_builtin_REVSH(val); + } + + #define __ROR __iar_builtin_ROR + #define __RRX __iar_builtin_RRX + + #define __SEV __iar_builtin_SEV + + #if !__IAR_M0_FAMILY + #define __SSAT __iar_builtin_SSAT + #endif + + #define __STREXB __iar_builtin_STREXB + #define __STREXH __iar_builtin_STREXH + #define __STREXW __iar_builtin_STREX + + #if !__IAR_M0_FAMILY + #define __USAT __iar_builtin_USAT + #endif + + #define __WFE __iar_builtin_WFE + #define __WFI __iar_builtin_WFI + + #if __ARM_MEDIA__ + #define __SADD8 __iar_builtin_SADD8 + #define __QADD8 __iar_builtin_QADD8 + #define __SHADD8 __iar_builtin_SHADD8 + #define __UADD8 __iar_builtin_UADD8 + #define __UQADD8 __iar_builtin_UQADD8 + #define __UHADD8 __iar_builtin_UHADD8 + #define __SSUB8 __iar_builtin_SSUB8 + #define __QSUB8 __iar_builtin_QSUB8 + #define __SHSUB8 __iar_builtin_SHSUB8 + #define __USUB8 __iar_builtin_USUB8 + #define __UQSUB8 __iar_builtin_UQSUB8 + #define __UHSUB8 __iar_builtin_UHSUB8 + #define __SADD16 __iar_builtin_SADD16 + #define __QADD16 __iar_builtin_QADD16 + #define __SHADD16 __iar_builtin_SHADD16 + #define __UADD16 __iar_builtin_UADD16 + #define __UQADD16 __iar_builtin_UQADD16 + #define __UHADD16 __iar_builtin_UHADD16 + #define __SSUB16 __iar_builtin_SSUB16 + #define __QSUB16 __iar_builtin_QSUB16 + #define __SHSUB16 __iar_builtin_SHSUB16 + #define __USUB16 __iar_builtin_USUB16 + #define __UQSUB16 __iar_builtin_UQSUB16 + #define __UHSUB16 __iar_builtin_UHSUB16 + #define __SASX __iar_builtin_SASX + #define __QASX __iar_builtin_QASX + #define __SHASX __iar_builtin_SHASX + #define __UASX __iar_builtin_UASX + #define __UQASX __iar_builtin_UQASX + #define __UHASX __iar_builtin_UHASX + #define __SSAX __iar_builtin_SSAX + #define __QSAX __iar_builtin_QSAX + #define __SHSAX __iar_builtin_SHSAX + #define __USAX __iar_builtin_USAX + #define __UQSAX __iar_builtin_UQSAX + #define __UHSAX __iar_builtin_UHSAX + #define __USAD8 __iar_builtin_USAD8 + #define __USADA8 __iar_builtin_USADA8 + #define __SSAT16 __iar_builtin_SSAT16 + #define __USAT16 __iar_builtin_USAT16 + #define __UXTB16 __iar_builtin_UXTB16 + #define __UXTAB16 __iar_builtin_UXTAB16 + #define __SXTB16 __iar_builtin_SXTB16 + #define __SXTAB16 __iar_builtin_SXTAB16 + #define __SMUAD __iar_builtin_SMUAD + #define __SMUADX __iar_builtin_SMUADX + #define __SMMLA __iar_builtin_SMMLA + #define __SMLAD __iar_builtin_SMLAD + #define __SMLADX __iar_builtin_SMLADX + #define __SMLALD __iar_builtin_SMLALD + #define __SMLALDX __iar_builtin_SMLALDX + #define __SMUSD __iar_builtin_SMUSD + #define __SMUSDX __iar_builtin_SMUSDX + #define __SMLSD __iar_builtin_SMLSD + #define __SMLSDX __iar_builtin_SMLSDX + #define __SMLSLD __iar_builtin_SMLSLD + #define __SMLSLDX __iar_builtin_SMLSLDX + #define __SEL __iar_builtin_SEL + #define __QADD __iar_builtin_QADD + #define __QSUB __iar_builtin_QSUB + #define __PKHBT __iar_builtin_PKHBT + #define __PKHTB __iar_builtin_PKHTB + #endif + +#else /* __ICCARM_INTRINSICS_VERSION__ == 2 */ + + #if __IAR_M0_FAMILY + /* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */ + #define __CLZ __cmsis_iar_clz_not_active + #define __SSAT __cmsis_iar_ssat_not_active + #define __USAT __cmsis_iar_usat_not_active + #define __RBIT __cmsis_iar_rbit_not_active + #define __get_APSR __cmsis_iar_get_APSR_not_active + #endif + + + #if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) )) + #define __get_FPSCR __cmsis_iar_get_FPSR_not_active + #define __set_FPSCR __cmsis_iar_set_FPSR_not_active + #endif + + #ifdef __INTRINSICS_INCLUDED + #error intrinsics.h is already included previously! + #endif + + #include + + #if __IAR_M0_FAMILY + /* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */ + #undef __CLZ + #undef __SSAT + #undef __USAT + #undef __RBIT + #undef __get_APSR + + __STATIC_INLINE uint8_t __CLZ(uint32_t data) + { + if (data == 0U) { return 32U; } + + uint32_t count = 0U; + uint32_t mask = 0x80000000U; + + while ((data & mask) == 0U) + { + count += 1U; + mask = mask >> 1U; + } + return count; + } + + __STATIC_INLINE uint32_t __RBIT(uint32_t v) + { + uint8_t sc = 31U; + uint32_t r = v; + for (v >>= 1U; v; v >>= 1U) + { + r <<= 1U; + r |= v & 1U; + sc--; + } + return (r << sc); + } + + __STATIC_INLINE uint32_t __get_APSR(void) + { + uint32_t res; + __asm("MRS %0,APSR" : "=r" (res)); + return res; + } + + #endif + + #if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) )) + #undef __get_FPSCR + #undef __set_FPSCR + #define __get_FPSCR() (0) + #define __set_FPSCR(VALUE) ((void)VALUE) + #endif + + #pragma diag_suppress=Pe940 + #pragma diag_suppress=Pe177 + + #define __enable_irq __enable_interrupt + #define __disable_irq __disable_interrupt + #define __NOP __no_operation + + #define __get_xPSR __get_PSR + + #if (!defined(__ARM_ARCH_6M__) || __ARM_ARCH_6M__==0) + + __IAR_FT uint32_t __LDREXW(uint32_t volatile *ptr) + { + return __LDREX((unsigned long *)ptr); + } + + __IAR_FT uint32_t __STREXW(uint32_t value, uint32_t volatile *ptr) + { + return __STREX(value, (unsigned long *)ptr); + } + #endif + + + /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */ + #if (__CORTEX_M >= 0x03) + + __IAR_FT uint32_t __RRX(uint32_t value) + { + uint32_t result; + __ASM volatile("RRX %0, %1" : "=r"(result) : "r" (value)); + return(result); + } + + __IAR_FT void __set_BASEPRI_MAX(uint32_t value) + { + __asm volatile("MSR BASEPRI_MAX,%0"::"r" (value)); + } + + + #define __enable_fault_irq __enable_fiq + #define __disable_fault_irq __disable_fiq + + + #endif /* (__CORTEX_M >= 0x03) */ + + __IAR_FT uint32_t __ROR(uint32_t op1, uint32_t op2) + { + return (op1 >> op2) | (op1 << ((sizeof(op1)*8)-op2)); + } + + #if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + + __IAR_FT uint32_t __get_MSPLIM(void) + { + uint32_t res; + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + res = 0U; + #else + __asm volatile("MRS %0,MSPLIM" : "=r" (res)); + #endif + return res; + } + + __IAR_FT void __set_MSPLIM(uint32_t value) + { + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)value; + #else + __asm volatile("MSR MSPLIM,%0" :: "r" (value)); + #endif + } + + __IAR_FT uint32_t __get_PSPLIM(void) + { + uint32_t res; + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + res = 0U; + #else + __asm volatile("MRS %0,PSPLIM" : "=r" (res)); + #endif + return res; + } + + __IAR_FT void __set_PSPLIM(uint32_t value) + { + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)value; + #else + __asm volatile("MSR PSPLIM,%0" :: "r" (value)); + #endif + } + + __IAR_FT uint32_t __TZ_get_CONTROL_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,CONTROL_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_CONTROL_NS(uint32_t value) + { + __asm volatile("MSR CONTROL_NS,%0" :: "r" (value)); + __iar_builtin_ISB(); + } + + __IAR_FT uint32_t __TZ_get_PSP_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,PSP_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_PSP_NS(uint32_t value) + { + __asm volatile("MSR PSP_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_MSP_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,MSP_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_MSP_NS(uint32_t value) + { + __asm volatile("MSR MSP_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_SP_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,SP_NS" : "=r" (res)); + return res; + } + __IAR_FT void __TZ_set_SP_NS(uint32_t value) + { + __asm volatile("MSR SP_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_PRIMASK_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,PRIMASK_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_PRIMASK_NS(uint32_t value) + { + __asm volatile("MSR PRIMASK_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_BASEPRI_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,BASEPRI_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_BASEPRI_NS(uint32_t value) + { + __asm volatile("MSR BASEPRI_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_FAULTMASK_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,FAULTMASK_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_FAULTMASK_NS(uint32_t value) + { + __asm volatile("MSR FAULTMASK_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_PSPLIM_NS(void) + { + uint32_t res; + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + res = 0U; + #else + __asm volatile("MRS %0,PSPLIM_NS" : "=r" (res)); + #endif + return res; + } + + __IAR_FT void __TZ_set_PSPLIM_NS(uint32_t value) + { + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)value; + #else + __asm volatile("MSR PSPLIM_NS,%0" :: "r" (value)); + #endif + } + + __IAR_FT uint32_t __TZ_get_MSPLIM_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,MSPLIM_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_MSPLIM_NS(uint32_t value) + { + __asm volatile("MSR MSPLIM_NS,%0" :: "r" (value)); + } + + #endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */ + +#endif /* __ICCARM_INTRINSICS_VERSION__ == 2 */ + +#define __BKPT(value) __asm volatile ("BKPT %0" : : "i"(value)) + +#if __IAR_M0_FAMILY + __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat) + { + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; + } + + __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat) + { + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; + } +#endif + +#if (__CORTEX_M >= 0x03) /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */ + + __IAR_FT uint8_t __LDRBT(volatile uint8_t *addr) + { + uint32_t res; + __ASM volatile ("LDRBT %0, [%1]" : "=r" (res) : "r" (addr) : "memory"); + return ((uint8_t)res); + } + + __IAR_FT uint16_t __LDRHT(volatile uint16_t *addr) + { + uint32_t res; + __ASM volatile ("LDRHT %0, [%1]" : "=r" (res) : "r" (addr) : "memory"); + return ((uint16_t)res); + } + + __IAR_FT uint32_t __LDRT(volatile uint32_t *addr) + { + uint32_t res; + __ASM volatile ("LDRT %0, [%1]" : "=r" (res) : "r" (addr) : "memory"); + return res; + } + + __IAR_FT void __STRBT(uint8_t value, volatile uint8_t *addr) + { + __ASM volatile ("STRBT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory"); + } + + __IAR_FT void __STRHT(uint16_t value, volatile uint16_t *addr) + { + __ASM volatile ("STRHT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory"); + } + + __IAR_FT void __STRT(uint32_t value, volatile uint32_t *addr) + { + __ASM volatile ("STRT %1, [%0]" : : "r" (addr), "r" (value) : "memory"); + } + +#endif /* (__CORTEX_M >= 0x03) */ + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + + + __IAR_FT uint8_t __LDAB(volatile uint8_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return ((uint8_t)res); + } + + __IAR_FT uint16_t __LDAH(volatile uint16_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return ((uint16_t)res); + } + + __IAR_FT uint32_t __LDA(volatile uint32_t *ptr) + { + uint32_t res; + __ASM volatile ("LDA %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return res; + } + + __IAR_FT void __STLB(uint8_t value, volatile uint8_t *ptr) + { + __ASM volatile ("STLB %1, [%0]" :: "r" (ptr), "r" (value) : "memory"); + } + + __IAR_FT void __STLH(uint16_t value, volatile uint16_t *ptr) + { + __ASM volatile ("STLH %1, [%0]" :: "r" (ptr), "r" (value) : "memory"); + } + + __IAR_FT void __STL(uint32_t value, volatile uint32_t *ptr) + { + __ASM volatile ("STL %1, [%0]" :: "r" (ptr), "r" (value) : "memory"); + } + + __IAR_FT uint8_t __LDAEXB(volatile uint8_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAEXB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return ((uint8_t)res); + } + + __IAR_FT uint16_t __LDAEXH(volatile uint16_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAEXH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return ((uint16_t)res); + } + + __IAR_FT uint32_t __LDAEX(volatile uint32_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAEX %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return res; + } + + __IAR_FT uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr) + { + uint32_t res; + __ASM volatile ("STLEXB %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory"); + return res; + } + + __IAR_FT uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr) + { + uint32_t res; + __ASM volatile ("STLEXH %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory"); + return res; + } + + __IAR_FT uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr) + { + uint32_t res; + __ASM volatile ("STLEX %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory"); + return res; + } + +#endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */ + +#undef __IAR_FT +#undef __IAR_M0_FAMILY +#undef __ICCARM_V8 + +#pragma diag_default=Pe940 +#pragma diag_default=Pe177 + +#define __SXTB16_RORn(ARG1, ARG2) __SXTB16(__ROR(ARG1, ARG2)) + +#define __SXTAB16_RORn(ARG1, ARG2, ARG3) __SXTAB16(ARG1, __ROR(ARG2, ARG3)) + +#endif /* __CMSIS_ICCARM_H__ */ diff --git a/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/CMSIS/Include/cmsis_version.h b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/CMSIS/Include/cmsis_version.h new file mode 100644 index 0000000000..8b4765f186 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/CMSIS/Include/cmsis_version.h @@ -0,0 +1,39 @@ +/**************************************************************************//** + * @file cmsis_version.h + * @brief CMSIS Core(M) Version definitions + * @version V5.0.5 + * @date 02. February 2022 + ******************************************************************************/ +/* + * Copyright (c) 2009-2022 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CMSIS_VERSION_H +#define __CMSIS_VERSION_H + +/* CMSIS Version definitions */ +#define __CM_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS Core(M) main version */ +#define __CM_CMSIS_VERSION_SUB ( 6U) /*!< [15:0] CMSIS Core(M) sub version */ +#define __CM_CMSIS_VERSION ((__CM_CMSIS_VERSION_MAIN << 16U) | \ + __CM_CMSIS_VERSION_SUB ) /*!< CMSIS Core(M) version number */ +#endif diff --git a/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/CMSIS/Include/core_cm0plus.h b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/CMSIS/Include/core_cm0plus.h new file mode 100644 index 0000000000..879a384124 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/CMSIS/Include/core_cm0plus.h @@ -0,0 +1,1087 @@ +/**************************************************************************//** + * @file core_cm0plus.h + * @brief CMSIS Cortex-M0+ Core Peripheral Access Layer Header File + * @version V5.0.9 + * @date 21. August 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM0PLUS_H_GENERIC +#define __CORE_CM0PLUS_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex-M0+ + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM0+ definitions */ +#define __CM0PLUS_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM0PLUS_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM0PLUS_CMSIS_VERSION ((__CM0PLUS_CMSIS_VERSION_MAIN << 16U) | \ + __CM0PLUS_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (0U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM0PLUS_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM0PLUS_H_DEPENDANT +#define __CORE_CM0PLUS_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM0PLUS_REV + #define __CM0PLUS_REV 0x0000U + #warning "__CM0PLUS_REV not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 0U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex-M0+ */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core MPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[31U]; + __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RESERVED1[31U]; + __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[31U]; + __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[31U]; + uint32_t RESERVED4[64U]; + __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ +#else + uint32_t RESERVED0; +#endif + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) +/* SCB Interrupt Control State Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 8U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#endif + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ +} MPU_Type; + +#define MPU_TYPE_RALIASES 1U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 8U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. + Therefore they are not covered by the Cortex-M0+ header file. + @{ + */ +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ +/*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M0+ */ + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ + + +/* Interrupt Priorities are WORD accessible only under Armv6-M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + +#define __NVIC_SetPriorityGrouping(X) (void)(X) +#define __NVIC_GetPriorityGrouping() (0U) + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + If VTOR is not present address 0 must be mapped to SRAM. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; +#else + uint32_t *vectors = (uint32_t *)(NVIC_USER_IRQ_OFFSET << 2); /* point to 1st user interrupt */ + *(vectors + (int32_t)IRQn) = vector; /* use pointer arithmetic to access vector */ +#endif + /* ARM Application Note 321 states that the M0+ does not require the architectural barrier */ +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +#else + uint32_t *vectors = (uint32_t *)(NVIC_USER_IRQ_OFFSET << 2); /* point to 1st user interrupt */ + return *(vectors + (int32_t)IRQn); /* use pointer arithmetic to access vector */ +#endif +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv7.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM0PLUS_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/CMSIS/Include/core_cm3.h b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/CMSIS/Include/core_cm3.h new file mode 100644 index 0000000000..74fb87e5c5 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/CMSIS/Include/core_cm3.h @@ -0,0 +1,1943 @@ +/**************************************************************************//** + * @file core_cm3.h + * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File + * @version V5.1.2 + * @date 04. June 2021 + ******************************************************************************/ +/* + * Copyright (c) 2009-2021 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM3_H_GENERIC +#define __CORE_CM3_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M3 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM3 definitions */ +#define __CM3_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM3_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16U) | \ + __CM3_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (3U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM3_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM3_H_DEPENDANT +#define __CORE_CM3_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM3_REV + #define __CM3_REV 0x0200U + #warning "__CM3_REV not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 1U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M3 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:1; /*!< bit: 9 Reserved */ + uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */ + uint32_t _reserved1:8; /*!< bit: 16..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit */ + uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */ +#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */ +#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24U]; + __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RESERVED1[24U]; + __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24U]; + __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24U]; + __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56U]; + __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[5U]; + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#if defined (__CM3_REV) && (__CM3_REV < 0x0201U) /* core r2p1 */ +#define SCB_VTOR_TBLBASE_Pos 29U /*!< SCB VTOR: TBLBASE Position */ +#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */ + +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#else +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#endif + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_CFSR_MEMFAULTSR_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ +#if defined (__CM3_REV) && (__CM3_REV >= 0x200U) + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +#else + uint32_t RESERVED1[1U]; +#endif +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/* Auxiliary Control Register Definitions */ +#if defined (__CM3_REV) && (__CM3_REV >= 0x200U) +#define SCnSCB_ACTLR_DISOOFP_Pos 9U /*!< ACTLR: DISOOFP Position */ +#define SCnSCB_ACTLR_DISOOFP_Msk (1UL << SCnSCB_ACTLR_DISOOFP_Pos) /*!< ACTLR: DISOOFP Mask */ + +#define SCnSCB_ACTLR_DISFPCA_Pos 8U /*!< ACTLR: DISFPCA Position */ +#define SCnSCB_ACTLR_DISFPCA_Msk (1UL << SCnSCB_ACTLR_DISFPCA_Pos) /*!< ACTLR: DISFPCA Mask */ + +#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ +#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR: DISDEFWBUF Position */ +#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ + +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ +#endif + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x1UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x1UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY2_Pos 0U /*!< TPI ITATBCTR2: ATREADY2 Position */ +#define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/) /*!< TPI ITATBCTR2: ATREADY2 Mask */ + +#define TPI_ITATBCTR2_ATREADY1_Pos 0U /*!< TPI ITATBCTR2: ATREADY1 Position */ +#define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/) /*!< TPI ITATBCTR2: ATREADY1 Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x1UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x1UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY2_Pos 0U /*!< TPI ITATBCTR0: ATREADY2 Position */ +#define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/) /*!< TPI ITATBCTR0: ATREADY2 Mask */ + +#define TPI_ITATBCTR0_ATREADY1_Pos 0U /*!< TPI ITATBCTR0: ATREADY1 Position */ +#define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/) /*!< TPI ITATBCTR0: ATREADY1 Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + /* ARM Application Note 321 states that the M3 does not require the architectural barrier */ +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv7.h" + +#endif + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM3_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/CMSIS/Include/mpu_armv7.h b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/CMSIS/Include/mpu_armv7.h new file mode 100644 index 0000000000..9909f83990 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/CMSIS/Include/mpu_armv7.h @@ -0,0 +1,275 @@ +/****************************************************************************** + * @file mpu_armv7.h + * @brief CMSIS MPU API for Armv7-M MPU + * @version V5.1.2 + * @date 25. May 2020 + ******************************************************************************/ +/* + * Copyright (c) 2017-2020 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef ARM_MPU_ARMV7_H +#define ARM_MPU_ARMV7_H + +#define ARM_MPU_REGION_SIZE_32B ((uint8_t)0x04U) ///!< MPU Region Size 32 Bytes +#define ARM_MPU_REGION_SIZE_64B ((uint8_t)0x05U) ///!< MPU Region Size 64 Bytes +#define ARM_MPU_REGION_SIZE_128B ((uint8_t)0x06U) ///!< MPU Region Size 128 Bytes +#define ARM_MPU_REGION_SIZE_256B ((uint8_t)0x07U) ///!< MPU Region Size 256 Bytes +#define ARM_MPU_REGION_SIZE_512B ((uint8_t)0x08U) ///!< MPU Region Size 512 Bytes +#define ARM_MPU_REGION_SIZE_1KB ((uint8_t)0x09U) ///!< MPU Region Size 1 KByte +#define ARM_MPU_REGION_SIZE_2KB ((uint8_t)0x0AU) ///!< MPU Region Size 2 KBytes +#define ARM_MPU_REGION_SIZE_4KB ((uint8_t)0x0BU) ///!< MPU Region Size 4 KBytes +#define ARM_MPU_REGION_SIZE_8KB ((uint8_t)0x0CU) ///!< MPU Region Size 8 KBytes +#define ARM_MPU_REGION_SIZE_16KB ((uint8_t)0x0DU) ///!< MPU Region Size 16 KBytes +#define ARM_MPU_REGION_SIZE_32KB ((uint8_t)0x0EU) ///!< MPU Region Size 32 KBytes +#define ARM_MPU_REGION_SIZE_64KB ((uint8_t)0x0FU) ///!< MPU Region Size 64 KBytes +#define ARM_MPU_REGION_SIZE_128KB ((uint8_t)0x10U) ///!< MPU Region Size 128 KBytes +#define ARM_MPU_REGION_SIZE_256KB ((uint8_t)0x11U) ///!< MPU Region Size 256 KBytes +#define ARM_MPU_REGION_SIZE_512KB ((uint8_t)0x12U) ///!< MPU Region Size 512 KBytes +#define ARM_MPU_REGION_SIZE_1MB ((uint8_t)0x13U) ///!< MPU Region Size 1 MByte +#define ARM_MPU_REGION_SIZE_2MB ((uint8_t)0x14U) ///!< MPU Region Size 2 MBytes +#define ARM_MPU_REGION_SIZE_4MB ((uint8_t)0x15U) ///!< MPU Region Size 4 MBytes +#define ARM_MPU_REGION_SIZE_8MB ((uint8_t)0x16U) ///!< MPU Region Size 8 MBytes +#define ARM_MPU_REGION_SIZE_16MB ((uint8_t)0x17U) ///!< MPU Region Size 16 MBytes +#define ARM_MPU_REGION_SIZE_32MB ((uint8_t)0x18U) ///!< MPU Region Size 32 MBytes +#define ARM_MPU_REGION_SIZE_64MB ((uint8_t)0x19U) ///!< MPU Region Size 64 MBytes +#define ARM_MPU_REGION_SIZE_128MB ((uint8_t)0x1AU) ///!< MPU Region Size 128 MBytes +#define ARM_MPU_REGION_SIZE_256MB ((uint8_t)0x1BU) ///!< MPU Region Size 256 MBytes +#define ARM_MPU_REGION_SIZE_512MB ((uint8_t)0x1CU) ///!< MPU Region Size 512 MBytes +#define ARM_MPU_REGION_SIZE_1GB ((uint8_t)0x1DU) ///!< MPU Region Size 1 GByte +#define ARM_MPU_REGION_SIZE_2GB ((uint8_t)0x1EU) ///!< MPU Region Size 2 GBytes +#define ARM_MPU_REGION_SIZE_4GB ((uint8_t)0x1FU) ///!< MPU Region Size 4 GBytes + +#define ARM_MPU_AP_NONE 0U ///!< MPU Access Permission no access +#define ARM_MPU_AP_PRIV 1U ///!< MPU Access Permission privileged access only +#define ARM_MPU_AP_URO 2U ///!< MPU Access Permission unprivileged access read-only +#define ARM_MPU_AP_FULL 3U ///!< MPU Access Permission full access +#define ARM_MPU_AP_PRO 5U ///!< MPU Access Permission privileged access read-only +#define ARM_MPU_AP_RO 6U ///!< MPU Access Permission read-only access + +/** MPU Region Base Address Register Value +* +* \param Region The region to be configured, number 0 to 15. +* \param BaseAddress The base address for the region. +*/ +#define ARM_MPU_RBAR(Region, BaseAddress) \ + (((BaseAddress) & MPU_RBAR_ADDR_Msk) | \ + ((Region) & MPU_RBAR_REGION_Msk) | \ + (MPU_RBAR_VALID_Msk)) + +/** +* MPU Memory Access Attributes +* +* \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral. +* \param IsShareable Region is shareable between multiple bus masters. +* \param IsCacheable Region is cacheable, i.e. its value may be kept in cache. +* \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy. +*/ +#define ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable) \ + ((((TypeExtField) << MPU_RASR_TEX_Pos) & MPU_RASR_TEX_Msk) | \ + (((IsShareable) << MPU_RASR_S_Pos) & MPU_RASR_S_Msk) | \ + (((IsCacheable) << MPU_RASR_C_Pos) & MPU_RASR_C_Msk) | \ + (((IsBufferable) << MPU_RASR_B_Pos) & MPU_RASR_B_Msk)) + +/** +* MPU Region Attribute and Size Register Value +* +* \param DisableExec Instruction access disable bit, 1= disable instruction fetches. +* \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode. +* \param AccessAttributes Memory access attribution, see \ref ARM_MPU_ACCESS_. +* \param SubRegionDisable Sub-region disable field. +* \param Size Region size of the region to be configured, for example 4K, 8K. +*/ +#define ARM_MPU_RASR_EX(DisableExec, AccessPermission, AccessAttributes, SubRegionDisable, Size) \ + ((((DisableExec) << MPU_RASR_XN_Pos) & MPU_RASR_XN_Msk) | \ + (((AccessPermission) << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk) | \ + (((AccessAttributes) & (MPU_RASR_TEX_Msk | MPU_RASR_S_Msk | MPU_RASR_C_Msk | MPU_RASR_B_Msk))) | \ + (((SubRegionDisable) << MPU_RASR_SRD_Pos) & MPU_RASR_SRD_Msk) | \ + (((Size) << MPU_RASR_SIZE_Pos) & MPU_RASR_SIZE_Msk) | \ + (((MPU_RASR_ENABLE_Msk)))) + +/** +* MPU Region Attribute and Size Register Value +* +* \param DisableExec Instruction access disable bit, 1= disable instruction fetches. +* \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode. +* \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral. +* \param IsShareable Region is shareable between multiple bus masters. +* \param IsCacheable Region is cacheable, i.e. its value may be kept in cache. +* \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy. +* \param SubRegionDisable Sub-region disable field. +* \param Size Region size of the region to be configured, for example 4K, 8K. +*/ +#define ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable, SubRegionDisable, Size) \ + ARM_MPU_RASR_EX(DisableExec, AccessPermission, ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable), SubRegionDisable, Size) + +/** +* MPU Memory Access Attribute for strongly ordered memory. +* - TEX: 000b +* - Shareable +* - Non-cacheable +* - Non-bufferable +*/ +#define ARM_MPU_ACCESS_ORDERED ARM_MPU_ACCESS_(0U, 1U, 0U, 0U) + +/** +* MPU Memory Access Attribute for device memory. +* - TEX: 000b (if shareable) or 010b (if non-shareable) +* - Shareable or non-shareable +* - Non-cacheable +* - Bufferable (if shareable) or non-bufferable (if non-shareable) +* +* \param IsShareable Configures the device memory as shareable or non-shareable. +*/ +#define ARM_MPU_ACCESS_DEVICE(IsShareable) ((IsShareable) ? ARM_MPU_ACCESS_(0U, 1U, 0U, 1U) : ARM_MPU_ACCESS_(2U, 0U, 0U, 0U)) + +/** +* MPU Memory Access Attribute for normal memory. +* - TEX: 1BBb (reflecting outer cacheability rules) +* - Shareable or non-shareable +* - Cacheable or non-cacheable (reflecting inner cacheability rules) +* - Bufferable or non-bufferable (reflecting inner cacheability rules) +* +* \param OuterCp Configures the outer cache policy. +* \param InnerCp Configures the inner cache policy. +* \param IsShareable Configures the memory as shareable or non-shareable. +*/ +#define ARM_MPU_ACCESS_NORMAL(OuterCp, InnerCp, IsShareable) ARM_MPU_ACCESS_((4U | (OuterCp)), IsShareable, ((InnerCp) >> 1U), ((InnerCp) & 1U)) + +/** +* MPU Memory Access Attribute non-cacheable policy. +*/ +#define ARM_MPU_CACHEP_NOCACHE 0U + +/** +* MPU Memory Access Attribute write-back, write and read allocate policy. +*/ +#define ARM_MPU_CACHEP_WB_WRA 1U + +/** +* MPU Memory Access Attribute write-through, no write allocate policy. +*/ +#define ARM_MPU_CACHEP_WT_NWA 2U + +/** +* MPU Memory Access Attribute write-back, no write allocate policy. +*/ +#define ARM_MPU_CACHEP_WB_NWA 3U + + +/** +* Struct for a single MPU Region +*/ +typedef struct { + uint32_t RBAR; //!< The region base address register value (RBAR) + uint32_t RASR; //!< The region attribute and size register value (RASR) \ref MPU_RASR +} ARM_MPU_Region_t; + +/** Enable the MPU. +* \param MPU_Control Default access permissions for unconfigured regions. +*/ +__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control) +{ + __DMB(); + MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; +#endif + __DSB(); + __ISB(); +} + +/** Disable the MPU. +*/ +__STATIC_INLINE void ARM_MPU_Disable(void) +{ + __DMB(); +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; +#endif + MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk; + __DSB(); + __ISB(); +} + +/** Clear and disable the given MPU region. +* \param rnr Region number to be cleared. +*/ +__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr) +{ + MPU->RNR = rnr; + MPU->RASR = 0U; +} + +/** Configure an MPU region. +* \param rbar Value for RBAR register. +* \param rasr Value for RASR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rbar, uint32_t rasr) +{ + MPU->RBAR = rbar; + MPU->RASR = rasr; +} + +/** Configure the given MPU region. +* \param rnr Region number to be configured. +* \param rbar Value for RBAR register. +* \param rasr Value for RASR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegionEx(uint32_t rnr, uint32_t rbar, uint32_t rasr) +{ + MPU->RNR = rnr; + MPU->RBAR = rbar; + MPU->RASR = rasr; +} + +/** Memcpy with strictly ordered memory access, e.g. used by code in ARM_MPU_Load(). +* \param dst Destination data is copied to. +* \param src Source data is copied from. +* \param len Amount of data words to be copied. +*/ +__STATIC_INLINE void ARM_MPU_OrderedMemcpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len) +{ + uint32_t i; + for (i = 0U; i < len; ++i) + { + dst[i] = src[i]; + } +} + +/** Load the given number of MPU regions from a table. +* \param table Pointer to the MPU configuration table. +* \param cnt Amount of regions to be configured. +*/ +__STATIC_INLINE void ARM_MPU_Load(ARM_MPU_Region_t const* table, uint32_t cnt) +{ + const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U; + while (cnt > MPU_TYPE_RALIASES) { + ARM_MPU_OrderedMemcpy(&(MPU->RBAR), &(table->RBAR), MPU_TYPE_RALIASES*rowWordSize); + table += MPU_TYPE_RALIASES; + cnt -= MPU_TYPE_RALIASES; + } + ARM_MPU_OrderedMemcpy(&(MPU->RBAR), &(table->RBAR), cnt*rowWordSize); +} + +#endif diff --git a/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/CMSIS/LICENSE.txt b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/CMSIS/LICENSE.txt new file mode 100644 index 0000000000..8dada3edaf --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/CMSIS/LICENSE.txt @@ -0,0 +1,201 @@ + Apache License + Version 2.0, January 2004 + http://www.apache.org/licenses/ + + TERMS AND CONDITIONS FOR USE, REPRODUCTION, AND DISTRIBUTION + + 1. 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It gives our users and partners contiguous access to the CMSIS development. It allows you to review the work and provide feedback or create pull requests for contributions. + +A [pre-built documentation](https://arm-software.github.io/CMSIS_5/develop/General/html/index.html) is updated from time to time, but may be also generated using the instructions under [Generate CMSIS Pack for Release](https://github.com/ARM-software/CMSIS_5#generate-cmsis-pack-for-release). + +## Overview of CMSIS Components + +The following is an list of all CMSIS components that are available. + +| CMSIS-... | Target Processors | Description | +|:----------|:--------------------|:-------------| +|[Core(M)](http://arm-software.github.io/CMSIS_5/Core/html/index.html) | All Cortex-M, SecurCore | Standardized API for the Cortex-M processor core and peripherals. Includes intrinsic functions for Cortex-M4/M7/M33/M35P SIMD instructions.| +|[Core(A)](http://arm-software.github.io/CMSIS_5/Core_A/html/index.html)| Cortex-A5/A7/A9 | API and basic run-time system for the Cortex-A5/A7/A9 processor core and peripherals.| +|[Driver](http://arm-software.github.io/CMSIS_5/Driver/html/index.html) | All Cortex-M, SecurCore | Generic peripheral driver interfaces for middleware. Connects microcontroller peripherals with middleware that implements for example communication stacks, file systems, or graphic user interfaces.| +|[DSP](http://arm-software.github.io/CMSIS_5/DSP/html/index.html) | All Cortex-M | DSP library collection with over 60 Functions for various data types: fixed-point (fractional q7, q15, q31) and single precision floating-point (32-bit). Implementations optimized for the SIMD instruction set are available for Cortex-M4/M7/M33/M35P.| +|[NN](http://arm-software.github.io/CMSIS_5/NN/html/index.html) | All Cortex-M | Collection of efficient neural network kernels developed to maximize the performance and minimize the memory footprint on Cortex-M processor cores.| +|[RTOS v1](http://arm-software.github.io/CMSIS_5/RTOS/html/index.html) | Cortex-M0/M0+/M3/M4/M7 | Common API for real-time operating systems along with a reference implementation based on RTX. It enables software components that can work across multiple RTOS systems.| +|[RTOS v2](http://arm-software.github.io/CMSIS_5/RTOS2/html/index.html)| All Cortex-M, Cortex-A5/A7/A9 | Extends CMSIS-RTOS v1 with Armv8-M support, dynamic object creation, provisions for multi-core systems, binary compatible interface. | +|[Pack](http://arm-software.github.io/CMSIS_5/Pack/html/index.html) | All Cortex-M, SecurCore, Cortex-A5/A7/A9 | Describes a delivery mechanism for software components, device parameters, and evaluation board support. It simplifies software re-use and product life-cycle management (PLM).
Is part of the [Open CMSIS Pack project](https://www.open-cmsis-pack.org). | +|[Build](http://arm-software.github.io/CMSIS_5/Build/html/index.html) | All Cortex-M, SecurCore, Cortex-A5/A7/A9 | A set of tools, software frameworks, and work flows that improve productivity, for example with Continuous Integration (CI) support.
Is replaced with the [CMSIS-Toolbox](https://github.com/Open-CMSIS-Pack/devtools/tree/main/tools). | +|[SVD](http://arm-software.github.io/CMSIS_5/SVD/html/index.html) | All Cortex-M, SecurCore | Peripheral description of a device that can be used to create peripheral awareness in debuggers or CMSIS-Core header files.| +|[DAP](http://arm-software.github.io/CMSIS_5/DAP/html/index.html) | All Cortex | Firmware for a debug unit that interfaces to the CoreSight Debug Access Port. | +|[Zone](http://arm-software.github.io/CMSIS_5/Zone/html/index.html) | All Cortex-M | Defines methods to describe system resources and to partition these resources into multiple projects and execution areas. | + +## Implemented Enhancements + - CMSIS-Pack generation with [shell script template](https://arm-software.github.io/CMSIS_5/Pack/html/bash_script.html) for Windows and Linux + - CMSIS-Pack: [Git workflow](https://arm-software.github.io/CMSIS_5/Pack/html/element_repository.html) via Eclipse menu *Window - Preferences - CMSIS Packs - Manage Local Repositories* and [MDK](http://www.keil.com/support/man/docs/uv4/uv4_ca_packinst_repo.htm) + - [CMSIS-Zone release 1.0](https://arm-software.github.io/CMSIS_5/Zone/html/index.html) with support for multi-processor, TrustZone, and MPU configuration + - Support for Armv8.1M Architecture and Cortex-M55 (release in March 2020) + - CMSIS-DSP is fully ported to SIMD for Cortex-M family (Armv8.1-M) and Cortex-A & Cortex-R with NEON, using the same APIs. + +## Further Planned Enhancements + - CMSIS-Pack: + - System Description SDF Format: describe more complex debug topologies than with a Debug Description in a tool agnostic way + - CPDSC project file format: allows project templates that are agnostic of an IDE + - Minimize need for IDE specific settings: CMSIS-Pack supports IDE specific parameters. Analyze and minimize + - CMSIS-Build: command-line driven make system for CMSIS-Pack based projects (to support CI tests) + +For further details see also the [Slides of the Embedded World CMSIS Partner Meeting](https://github.com/ARM-software/CMSIS_5/blob/develop/CMSIS_Review_Meeting_2020.pdf). + +## Other related GitHub repositories + +| Repository | Description | +|:--------------------------- |:--------------------------------------------------------- | +| [cmsis-pack-eclipse](https://github.com/ARM-software/cmsis-pack-eclipse) | CMSIS-Pack Management for Eclipse reference implementation Pack support | +| [CMSIS-FreeRTOS](https://github.com/arm-software/CMSIS-FreeRTOS) | CMSIS-RTOS adoption of FreeRTOS | +| [CMSIS-Driver](https://github.com/arm-software/CMSIS-Driver) | Generic MCU driver implementations and templates for Ethernet MAC/PHY and Flash. | +| [CMSIS-Driver_Validation](https://github.com/ARM-software/CMSIS-Driver_Validation) | CMSIS-Driver Validation can be used to verify CMSIS-Driver in a user system | +| [CMSIS-Zone](https://github.com/ARM-software/CMSIS-Zone) | CMSIS-Zone Utility along with example projects and FreeMarker templates | +| [NXP_LPC](https://github.com/ARM-software/NXP_LPC) | CMSIS Driver Implementations for the NXP LPC Microcontroller Series | +| [mdk-packs](https://github.com/mdk-packs) | IoT cloud connectors as trail implementations for MDK (help us to make it generic)| +| [trustedfirmware.org](https://www.trustedfirmware.org/) | Arm Trusted Firmware provides a reference implementation of secure world software for Armv8-A and Armv8-M.| + + +## Directory Structure + +| Directory | Content | +|:-------------------- |:--------------------------------------------------------- | +| CMSIS/Core | CMSIS-Core(M) related files (for release) | +| CMSIS/Core_A | CMSIS-Core(A) related files (for release) | +| CMSIS/CoreValidation | Validation for Core(M) and Core(A) (NOT part of release) | +| CMSIS/DAP | CMSIS-DAP related files and examples | +| CMSIS/Driver | CMSIS-Driver API headers and template files | +| CMSIS/DSP | CMSIS-DSP related files | +| CMSIS/NN | CMSIS-NN related files | +| CMSIS/RTOS | RTOS v1 related files (for Cortex-M) | +| CMSIS/RTOS2 | RTOS v2 related files (for Cortex-M & Armv8-M) | +| CMSIS/Pack | CMSIS-Pack examples and tutorials | +| CMSIS/DoxyGen | Source of the documentation | +| CMSIS/Utilities | Utility programs | + +## Generate CMSIS Pack for Release + +This GitHub development repository lacks pre-built libraries of various software components (RTOS, RTOS2). +In order to generate a full pack one needs to have the build environment available to build these libraries. +This causes some sort of inconvenience. Hence the pre-built libraries may be moved out into separate pack(s) +in the future. + +To build a complete CMSIS pack for installation the following additional tools are required: + - **doxygen.exe** Version: 1.8.6 (Documentation Generator) + - **mscgen.exe** Version: 0.20 (Message Sequence Chart Converter) + - **7z.exe (7-Zip)** Version: 16.02 (File Archiver) + +Using these tools, you can generate on a Windows PC: + - **CMSIS Documentation** using the batch file **gen_doc.sh** (located in ./CMSIS/Doxygen). + - **CMSIS Software Pack** using the batch file **gen_pack.sh** (located in ./CMSIS/Utilities). + The bash script does not generate the documentation. The pre-built libraries for RTX4 and RTX5 + are not included within this repository. + +The file ./CMSIS/DoxyGen/How2Doc.txt describes the rules for creating API documentation. + +## License + +Arm CMSIS is licensed under Apache 2.0. + +## Contributions and Pull Requests + +Contributions are accepted under Apache 2.0. Only submit contributions where you have authored all of the code. + +### Issues and Labels + +Please feel free to raise an [issue on GitHub](https://github.com/ARM-software/CMSIS_5/issues) +to report misbehavior (i.e. bugs) or start discussions about enhancements. This +is your best way to interact directly with the maintenance team and the community. +We encourage you to append implementation suggestions as this helps to decrease the +workload of the very limited maintenance team. + +We will be monitoring and responding to issues as best we can. +Please attempt to avoid filing duplicates of open or closed items when possible. +In the spirit of openness we will be tagging issues with the following: + +- **bug** – We consider this issue to be a bug that will be investigated. + +- **wontfix** - We appreciate this issue but decided not to change the current behavior. + +- **enhancement** – Denotes something that will be implemented soon. + +- **future** - Denotes something not yet schedule for implementation. + +- **out-of-scope** - We consider this issue loosely related to CMSIS. It might by implemented outside of CMSIS. Let us know about your work. + +- **question** – We have further questions to this issue. Please review and provide feedback. + +- **documentation** - This issue is a documentation flaw that will be improved in future. + +- **review** - This issue is under review. Please be patient. + +- **DONE** - We consider this issue as resolved - please review and close it. In case of no further activity this issues will be closed after a week. + +- **duplicate** - This issue is already addressed elsewhere, see comment with provided references. + +- **Important Information** - We provide essential information regarding planned or resolved major enhancements. + diff --git a/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/Device/Holtek/HT32F1xxxx/Include/ht32f1xxxx_01.h b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/Device/Holtek/HT32F1xxxx/Include/ht32f1xxxx_01.h new file mode 100644 index 0000000000..f2bcf5de2a --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/Device/Holtek/HT32F1xxxx/Include/ht32f1xxxx_01.h @@ -0,0 +1,1462 @@ +/***************************************************************************//** + * @file ht32f1xxxx_01.h + * @brief CMSIS Cortex-M3 Device Peripheral Access Layer Header File + * @version $Rev:: 2914 $ + * @date $Date:: 2023-05-18 #$ + * + * @note + * Copyright (C) Holtek Semiconductor Inc. All rights reserved. + * + * @par + * Holtek supplies this software for Cortex-M processor-based + * microcontrollers. This file can be freely distributed within + * development tools that are supporting such ARM-based processors. + * + * @par + * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR + * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + ******************************************************************************/ + +// Supported Device +// ======================================== +// HT32F1653, HT32F1654 +// HT32F1655, HT32F1656 +// HT32F12345 +// HT32F12365, HT32F12366 +// HT32F22366 +// HT32F12364 + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup HT32F1xxxx HT32F1xxxx + * @{ + */ + + +#ifndef __HT32F1XXXX_01_H__ +#define __HT32F1XXXX_01_H__ + +#ifdef __cplusplus + extern "C" { +#endif + +#if !defined(USE_HT32F1653_54) && \ + !defined(USE_HT32F1655_56) && \ + !defined(USE_HT32F12345) && \ + !defined(USE_HT32F12365_66) && \ + !defined(USE_HT32F12364) + + //#define USE_HT32F1653_54 + //#define USE_HT32F1655_56 + //#define USE_HT32F12345 + //#define USE_HT32F12365_66 + +#endif + +#if !defined(USE_NOCHIP) && \ + !defined(USE_HT32F1653_54) && \ + !defined(USE_HT32F1655_56) && \ + !defined(USE_HT32F12345) && \ + !defined(USE_HT32F12365_66) && \ + !defined(USE_HT32F12364) + + #error Please add "USE_HT32Fxxxxx_xx" define into C Preprocessor Symbols of the Project configuration. + +#endif + +/** @addtogroup Library_configuration_section + * @{ + */ +/** + * @brief Value of the High Speed Internal oscillator in Hz + */ +#define HSI_VALUE 8000000UL /*!< Value of the High Speed Internal oscillator in Hz */ + +/** + * @brief Value of the Low Speed Internal oscillator in Hz + */ +#define LSI_VALUE 32000UL /*!< Value of the Low Speed Internal oscillator in Hz */ + +/** + * @brief Value of the Low Speed External oscillator in Hz + */ +#define LSE_VALUE 32768UL /*!< Value of the Low Speed External oscillator in Hz */ + +/** + * @brief Adjust the High Speed External oscillator (HSE) Startup Timeout value + */ +#define HSE_READY_TIME ((uint16_t)0xFFFF) /*!< Time out for HSE start up */ +/** + * @} + */ + +/** @addtogroup Configuration_section_for_CMSIS + * @{ + */ +#define __MPU_PRESENT 0 /*!< MPU present or not */ +#define __NVIC_PRIO_BITS 4 /*!< Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ + +/** + * @} + */ + + +/** @addtogroup Configuration_for_Interrupt_Number + * @{ + */ +typedef enum IRQn +{ +/****** Cortex-M3 Processor Exceptions Numbers ****************************** */ + NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13, /*!< 3 Cortex-M3 Hard Fault Interrupt */ + MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Int */ + BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */ + SVCall_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */ + +/****** HT32 Specific Interrupt Numbers ************************************ */ + CKRDY_IRQn = 0, /*!< Clock ready interrupt */ + LVD_IRQn = 1, /*!< Low voltage detection interrupt */ + BOD_IRQn = 2, /*!< Brown-Out detection interrupt */ + #if defined(USE_HT32F1653_54) || defined(USE_HT32F1655_56) + WDT_IRQn = 3, /*!< WDT global interrupt */ + #endif + RTC_IRQn = 4, /*!< RTC Wake-up Interrupt */ + FLASH_IRQn = 5, /*!< FLASH global Interrupt */ + EVWUP_IRQn = 6, /*!< Event Wake-up Interrupt */ + LPWUP_IRQn = 7, /*!< WAKEUP pin Interrupt */ + EXTI0_IRQn = 8, /*!< EXTI0 Line detection Interrupt */ + EXTI1_IRQn = 9, /*!< EXTI1 Line detection Interrupt */ + EXTI2_IRQn = 10, /*!< EXTI2 Line detection Interrupt */ + EXTI3_IRQn = 11, /*!< EXTI3 Line detection Interrupt */ + EXTI4_IRQn = 12, /*!< EXTI4 Line detection Interrupt */ + EXTI5_IRQn = 13, /*!< EXTI5 Line detection Interrupt */ + EXTI6_IRQn = 14, /*!< EXTI6 Line detection Interrupt */ + EXTI7_IRQn = 15, /*!< EXTI7 Line detection Interrupt */ + EXTI8_IRQn = 16, /*!< EXTI8 Line detection Interrupt */ + EXTI9_IRQn = 17, /*!< EXTI9 Line detection Interrupt */ + EXTI10_IRQn = 18, /*!< EXTI10 Line detection Interrupt */ + EXTI11_IRQn = 19, /*!< EXTI11 Line detection Interrupt */ + EXTI12_IRQn = 20, /*!< EXTI12 Line detection Interrupt */ + EXTI13_IRQn = 21, /*!< EXTI13 Line detection Interrupt */ + EXTI14_IRQn = 22, /*!< EXTI14 Line detection Interrupt */ + EXTI15_IRQn = 23, /*!< EXTI15 Line detection Interrupt */ + #if !defined(USE_HT32F12364) + COMP_IRQn = 24, /*!< Comparator global Interrupt */ + #endif + ADC0_IRQn = 25, /*!< ADC Interrupt */ + #if !defined(USE_HT32F12364) + MCTM0BRK_IRQn = 27, /*!< MCTM0 BRK interrupt */ + MCTM0UP_IRQn = 28, /*!< MCTM0 UP interrupt */ + MCTM0TR_IRQn = 29, /*!< MCTM0 TR interrupt */ + MCTM0CC_IRQn = 30, /*!< MCTM0 CC interrupt */ + MCTM1BRK_IRQn = 31, /*!< MCTM1 BRK interrupt */ + MCTM1UP_IRQn = 32, /*!< MCTM1 UP interrupt */ + MCTM1TR_IRQn = 33, /*!< MCTM1 TR interrupt */ + MCTM1CC_IRQn = 34, /*!< MCTM1 CC interrupt */ + #endif + GPTM0_IRQn = 35, /*!< General-Purpose Timer0 Interrupt */ + #if !defined(USE_HT32F12364) + GPTM1_IRQn = 36, /*!< General-Purpose Timer1 Interrupt */ + #endif + #if defined(USE_HT32F12364) + SCTM0_IRQn = 37, /*!< Single-Channel Timer0 Interrupt */ + SCTM1_IRQn = 38, /*!< Single-Channel Timer1 Interrupt */ + PWM0_IRQn = 39, /*!< Pulse Width Modulator Timer0 Interrupt */ + #endif + BFTM0_IRQn = 41, /*!< Basic Function Timer0 interrupt */ + BFTM1_IRQn = 42, /*!< Basic Function Timer1 interrupt */ + I2C0_IRQn = 43, /*!< I2C0 global Interrupt */ + I2C1_IRQn = 44, /*!< I2C1 global Interrupt */ + SPI0_IRQn = 45, /*!< SPI0 global Interrupt */ + SPI1_IRQn = 46, /*!< SPI1 global Interrupt */ + USART0_IRQn = 47, /*!< USART0 global Interrupt */ + #if !defined(USE_HT32F12364) + USART1_IRQn = 48, /*!< USART1 global Interrupt */ + #endif + UART0_IRQn = 49, /*!< UART0 global Interrupt */ + UART1_IRQn = 50, /*!< UART1 global Interrupt */ + #if !defined(USE_HT32F12345) + SCI_IRQn = 51, /*!< Smart Card interface interrupt */ + #endif + #if !defined(USE_HT32F12364) + I2S_IRQn = 52, /*!< I2S global Interrupt */ + #endif + USB_IRQn = 53, /*!< USB interrupt */ + #if defined(USE_HT32F12365_66) || defined(USE_HT32F12345) + SDIO_IRQn = 54, /*!< SDIO interrupt */ + #endif + PDMACH0_IRQn = 55, /*!< PDMA channel 0 global interrupt */ + PDMACH1_IRQn = 56, /*!< PDMA channel 1 global interrupt */ + PDMACH2_IRQn = 57, /*!< PDMA channel 2 global interrupt */ + PDMACH3_IRQn = 58, /*!< PDMA channel 3 global interrupt */ + PDMACH4_IRQn = 59, /*!< PDMA channel 4 global interrupt */ + PDMACH5_IRQn = 60, /*!< PDMA channel 5 global interrupt */ + #if !defined(USE_HT32F12364) + PDMACH6_IRQn = 61, /*!< PDMA channel 6 global interrupt */ + PDMACH7_IRQn = 62, /*!< PDMA channel 7 global interrupt */ + #endif + #if defined(USE_HT32F12365_66) || defined(USE_HT32F12345) + PDMACH8_IRQn = 63, /*!< PDMA channel 8 global interrupt */ + PDMACH9_IRQn = 64, /*!< PDMA channel 9 global interrupt */ + PDMACH10_IRQn = 65, /*!< PDMA channel 10 global interrupt */ + PDMACH11_IRQn = 66, /*!< PDMA channel 11 global interrupt */ + #endif + #if defined(USE_HT32F12365_66) + CSIF_IRQn = 67, /*!< CMOS sensor interface interrupt */ + #endif + #if !defined(USE_HT32F12364) + EBI_IRQn = 68, /*!< External bus interface interrupt */ + #endif + #if defined(USE_HT32F12365_66) || defined(USE_HT32F12364) + AES_IRQn = 69, /*!< AES interrupt */ + #endif +} IRQn_Type; + +#define MCTM0_IRQn MCTM0UP_IRQn +#define MCTM0_IRQHandler MCTM0UP_IRQHandler +#define MCTM1_IRQn MCTM1UP_IRQn +#define MCTM1_IRQHandler MCTM1UP_IRQHandler + + +/** + * @} + */ + +#include "core_cm3.h" /* Cortex-M3 processor and core peripherals */ +#include "system_ht32f1xxxx_01.h" /* HT32 system */ + + +/** @addtogroup Exported_Types + * @{ + */ + +typedef signed long long s64; +typedef signed int s32; +typedef signed short s16; +typedef signed char s8; + +typedef const s64 sc64; /*!< Read Only */ +typedef const s32 sc32; /*!< Read Only */ +typedef const s16 sc16; /*!< Read Only */ +typedef const s8 sc8; /*!< Read Only */ + +typedef __IO s64 vs64; +typedef __IO s32 vs32; +typedef __IO s16 vs16; +typedef __IO s8 vs8; + +typedef __I s64 vsc64; /*!< Read Only */ +typedef __I s32 vsc32; /*!< Read Only */ +typedef __I s16 vsc16; /*!< Read Only */ +typedef __I s8 vsc8; /*!< Read Only */ + +typedef unsigned long long u64; +typedef unsigned int u32; +typedef unsigned short u16; +typedef unsigned char u8; + +typedef const u64 uc64; /*!< Read Only */ +typedef const u32 uc32; /*!< Read Only */ +typedef const u16 uc16; /*!< Read Only */ +typedef const u8 uc8; /*!< Read Only */ + +typedef __IO u64 vu64; +typedef __IO u32 vu32; +typedef __IO u16 vu16; +typedef __IO u8 vu8; + +typedef __I u64 vuc64; /*!< Read Only */ +typedef __I u32 vuc32; /*!< Read Only */ +typedef __I u16 vuc16; /*!< Read Only */ +typedef __I u8 vuc8; /*!< Read Only */ + + +typedef enum {DISABLE = 0, ENABLE = !DISABLE} EventStatus, ControlStatus; + +#if !defined(bool) && !defined(__cplusplus) // user may already included or CPP +typedef enum {FALSE = 0, TRUE = !FALSE} bool; +#define false FALSE +#define true TRUE +#else +#define FALSE 0 +#define TRUE 1 +#endif + +typedef enum {RESET = 0, SET = !RESET} FlagStatus; + +typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrStatus; + +/** + * @} + */ + +#if defined (__CC_ARM) + #define __ALIGN4 __align(4) +#elif defined (__ICCARM__) + #define __ALIGN4 _Pragma("data_alignment = 4") +#elif defined (__GNUC__) + #define __ALIGN4 __attribute__((aligned(4))) +#endif + +#if defined (__GNUC__) + #define __PACKED_H + #define __PACKED_F __attribute__ ((packed)) +#elif defined (__ICCARM__) || (__CC_ARM) + #define __PACKED_H __packed + #define __PACKED_F +#endif + +#if defined (__CC_ARM) +#pragma anon_unions +#endif + + +#define U8_MAX ((u8)255) +#define S8_MAX ((s8)127) +#define S8_MIN ((s8)-128) +#define U16_MAX ((u16)65535u) +#define S16_MAX ((s16)32767) +#define S16_MIN ((s16)-32768) +#define U32_MAX ((u32)4294967295uL) +#define S32_MAX ((s32)2147483647) +#define S32_MIN ((s32)-2147483648) + + +/** + * @brief Exported constants and macro + */ +#define IS_CONTROL_STATUS(STATUS) ((STATUS == DISABLE) || (STATUS == ENABLE)) + +#define wb(addr, value) (*((u8 volatile *) (addr)) = value) +#define rb(addr) (*((u8 volatile *) (addr))) +#define whw(addr, value) (*((u16 volatile *) (addr)) = value) +#define rhw(addr) (*((u16 volatile *) (addr))) +#define ww(addr, value) (*((u32 volatile *) (addr)) = value) +#define rw(addr) (*((u32 volatile *) (addr))) + + +#define ResetBit_BB(Addr, BitNumber) (*(vu32 *) ((Addr & 0xF0000000) + 0x02000000 + \ + ((Addr & 0xFFFFF) << 5) + (BitNumber << 2)) = 0) +#define SetBit_BB(Addr, BitNumber) (*(vu32 *) ((Addr & 0xF0000000) + 0x02000000 + \ + ((Addr & 0xFFFFF) << 5) + (BitNumber << 2)) = 1) +#define GetBit_BB(Addr, BitNumber) (*(vu32 *) ((Addr & 0xF0000000) + 0x02000000 + \ + ((Addr & 0xFFFFF) << 5) + (BitNumber << 2))) +#define BitBand(Addr, BitNumber) (*(vu32 *) ((Addr & 0xF0000000) + 0x02000000 + \ + ((Addr & 0xFFFFF) << 5) + (BitNumber << 2))) + +#define STRCAT2_(a, b) a##b +#define STRCAT2(a, b) STRCAT2_(a, b) +#define STRCAT3_(a, b, c) a##b##c +#define STRCAT3(a, b, c) STRCAT3_(a, b, c) + +#define IPN_NULL (0) +#define IPN_MCTM0 (0x4002C000) +#define IPN_MCTM1 (0x4002D000) +#define IPN_GPTM0 (0x4006E000) +#define IPN_GPTM1 (0x4006F000) +#define IPN_CHECK(IP) STRCAT2(IPN_, IP) +#define IS_IPN_MCTM(IP) (IPN_CHECK(IP) == IPN_MCTM0) || (IPN_CHECK(IP) == IPN_MCTM1) +#define IS_IPN_GPTM(IP) (IPN_CHECK(IP) == IPN_GPTM0) || (IPN_CHECK(IP) == IPN_GPTM1) + + +/** @addtogroup Peripheral_Registers_Structures + * @{ + */ + + +/** + * @brief Universal Synchronous Asynchronous Receiver Transmitter + */ +typedef struct +{ + /* USART0: 0x40000000 */ + /* USART1: 0x40040000 */ + /* UART0: 0x40001000 */ + /* UART1: 0x40041000 */ + #if defined(USE_HT32F1653_54) || defined(USE_HT32F1655_56) + union { + __IO uint32_t DR; /*!< 0x000 Data Register */ + __IO uint32_t RBR; /*!< 0x000 Receive Buffer Register */ + __IO uint32_t TBR; /*!< 0x000 Transmit Holding Register */ + }; + __IO uint32_t IER; /*!< 0x004 Interrupt Enable Register */ + __IO uint32_t IIR; /*!< 0x008 Interrupt Identification Register/FIFO Control Register */ + __IO uint32_t FCR; /*!< 0x00C FIFO Control Register */ + __IO uint32_t LCR; /*!< 0x010 Line Control Register */ + __IO uint32_t MCR; /*!< 0x014 Modem Control Register */ + union { + __IO uint32_t LSR; /*!< 0x018 Line Status Register */ + __IO uint32_t SR; /*!< 0x018 Line Status Register */ + }; + __IO uint32_t MSR; /*!< 0x01C Modem Status Register */ + __IO uint32_t TPR; /*!< 0x020 Timing Parameter Register */ + __IO uint32_t MDR; /*!< 0x024 Mode Register */ + __IO uint32_t ICR; /*!< 0x028 IrDA Register */ + __IO uint32_t RCR; /*!< 0x02C RS485 Control Register */ + __IO uint32_t SCR; /*!< 0x030 Synchronous Control Register */ + __IO uint32_t FSR; /*!< 0x034 FIFO Status Register */ + __IO uint32_t DLR; /*!< 0x038 Divisor Latch Register */ + __IO uint32_t DTR; /*!< 0x040 Debug/Test Register */ + #else + __IO uint32_t DR; /*!< 0x000 Data Register */ + __IO uint32_t CR; /*!< 0x004 Control Register */ + __IO uint32_t FCR; /*!< 0x008 FIFO Control Register */ + __IO uint32_t IER; /*!< 0x00C Interrupt Enable Register */ + __IO uint32_t SR; /*!< 0x010 Status Register */ + __IO uint32_t TPR; /*!< 0x014 Timing Parameter Register */ + __IO uint32_t ICR; /*!< 0x018 IrDA COntrol Register */ + __IO uint32_t RCR; /*!< 0x01C RS485 Control Register */ + __IO uint32_t SCR; /*!< 0x020 Synchronous Control Register */ + __IO uint32_t DLR; /*!< 0x024 Divisor Latch Register */ + __IO uint32_t DTR; /*!< 0x028 Debug/Test Register */ + #endif +} HT_USART_TypeDef; + + +/** + * @brief SPI + */ +typedef struct +{ + /* SPI0: 0x40004000 */ + /* SPI1: 0x40044000 */ + __IO uint32_t CR0; /*!< 0x000 Control Register 0 */ + __IO uint32_t CR1; /*!< 0x004 Control Register 1 */ + __IO uint32_t IER; /*!< 0x008 Interrupt Enable Register */ + __IO uint32_t CPR; /*!< 0x00C Clock Prescaler Register */ + __IO uint32_t DR; /*!< 0x010 Data Register */ + __IO uint32_t SR; /*!< 0x014 Status Register */ + __IO uint32_t FCR; /*!< 0x018 FIFO Control Register */ + __IO uint32_t FSR; /*!< 0x01C FIFO Status Register */ + __IO uint32_t FTOCR; /*!< 0x020 FIFO Time Out Counter Register */ +} HT_SPI_TypeDef; + + +/** + * @brief Analog to Digital Converter + */ +typedef struct +{ + /* ADC: 0x40010000 */ +#if defined(USE_HT32F12364) + __IO uint32_t CR; /*!< 0x000 ADC Conversion Control Register */ + __IO uint32_t LST[2]; /*!< 0x004 - 0x008 ADC Conversion List Register 0-1 */ + uint32_t RESERVE0[5]; /*!< 0x00C - 0x01C Reserved */ + __IO uint32_t STR; /*!< 0x020 ADC Input Sampling Time Register */ + uint32_t RESERVE1[3]; /*!< 0x024 - 0x02C Reserved */ + __IO uint32_t DR[8]; /*!< 0x030 - 0x04C ADC Conversion Data Register 0-7 */ + uint32_t RESERVE2[8]; /*!< 0x050 - 0x06C Reserved */ + __IO uint32_t TCR; /*!< 0x070 ADC Trigger Control Register */ + __IO uint32_t TSR; /*!< 0x074 ADC Trigger Source Register */ + __IO uint32_t WCR; /*!< 0x078 ADC Watchdog Control Register */ + __IO uint32_t WTR; /*!< 0x07C ADC Watchdog Threshold Register */ + __IO uint32_t IER; /*!< 0x080 ADC Interrupt Enable Register */ + __IO uint32_t IRAW; /*!< 0x084 ADC Interrupt Raw Status Register */ + __IO uint32_t ISR; /*!< 0x088 ADC Interrupt Status Register */ + __IO uint32_t ICLR; /*!< 0x08C ADC Interrupt Clear Register */ + __IO uint32_t PDMAR; /*!< 0x090 ADC PDMA Request Register */ + uint32_t RESERVE3[3]; /*!< 0x094 - 0x09C Reserved */ + __IO uint32_t VREFCR; /*!< 0x0A0 ADC Reference Voltage Control Register */ + __IO uint32_t VREFVALR; /*!< 0x0A4 ADC Reference Voltage Value Register */ +#else + uint32_t RESERVE0[1]; /*!< 0x000 Reserved */ + __IO uint32_t RST; /*!< 0x004 ADC Reset Register */ + __IO uint32_t CONV; /*!< 0x008 ADC Regular Conversion Mode Register */ + __IO uint32_t HCONV; /*!< 0x00C ADC High-priority Conversion Mode Register */ + __IO uint32_t LST[4]; /*!< 0x010 - 0x01C ADC Regular Conversion List Register 0-3 */ + __IO uint32_t HLST; /*!< 0x020 ADC High-priority Conversion List Register */ + uint32_t RESERVE1[3]; /*!< 0x024 - 0x02C Reserved */ + __IO uint32_t OFR[16]; /*!< 0x030 - 0x06C ADC Input Offset Register 0-15 */ + __IO uint32_t STR[16]; /*!< 0x070 - 0x0AC ADC Input Sampling Time Register 0-15 */ + __IO uint32_t DR[16]; /*!< 0x0B0 - 0x0EC ADC Regular Conversion Data Register 0-15 */ + __IO uint32_t HDR[4]; /*!< 0x0F0 - 0x0FC ADC High-priority Conversion Data Register 0-3 */ + __IO uint32_t TCR; /*!< 0x100 ADC Regular Trigger Control Register */ + __IO uint32_t TSR; /*!< 0x104 ADC Regular Trigger Source Register */ + uint32_t RESERVE2[2]; /*!< 0x108 - 0x10C Reserved */ + __IO uint32_t HTCR; /*!< 0x110 ADC High-priority Trigger Control Register */ + __IO uint32_t HTSR; /*!< 0x114 ADC High-priority Trigger Source Register */ + uint32_t RESERVE3[2]; /*!< 0x118 - 0x11C Reserved */ + __IO uint32_t WCR; /*!< 0x120 ADC Watchdog Control Register */ + __IO uint32_t LTR; /*!< 0x124 ADC Lower Threshold Register */ + __IO uint32_t UTR; /*!< 0x128 ADC Upper Threshold Register */ + uint32_t RESERVE4[1]; /*!< 0x12C Reserved */ + __IO uint32_t IER; /*!< 0x130 ADC Interrupt Enable Register */ + __IO uint32_t IRAW; /*!< 0x134 ADC Interrupt Raw Status Register */ + __IO uint32_t ISR; /*!< 0x138 ADC Interrupt Status Register */ + __IO uint32_t ICLR; /*!< 0x13C ADC Interrupt Clear Register */ + __IO uint32_t PDMAR; /*!< 0x140 ADC PDMA Request Register */ +#endif +} HT_ADC_TypeDef; + + +/** + * @brief Op Amp/Comparator + */ +typedef struct +{ + /* CMP_OP0: 0x40018000 */ + /* CMP_OP1: 0x40018100 */ + __IO uint32_t OPACR; /*!< 0x000 Operational Amplifier control register */ + __IO uint32_t OFVCR; /*!< 0x004 Comparator input offset voltage cancellation register */ + __IO uint32_t CMPIER; /*!< 0x008 Comparator interrupt enable register */ + __IO uint32_t CMPRSR; /*!< 0x00C Comparator raw status register */ + __IO uint32_t CMPISR; /*!< 0x010 Comparator interrupt status register */ + __IO uint32_t CMPICLR; /*!< 0x014 Comparator interrupt clear register */ +} HT_CMP_OP_TypeDef; + +/** + * @brief Comparator + */ +typedef struct +{ + /* CMP0: 0x40058000 */ + /* CMP1: 0x40058100 */ + __IO uint32_t CR; /*!< 0x000 Comparator Control Register */ + __IO uint32_t VALR; /*!< 0x004 Comparator Voltage Reference Value Register */ + __IO uint32_t IER; /*!< 0x008 Comparator Interrupt Enable Register */ + __IO uint32_t TFR; /*!< 0x00C Comparator Transition Flag Register */ +} HT_CMP_TypeDef; + + +/** + * @brief General Purpose I/O + */ +typedef struct +{ + /* GPIOA: 0x400B0000 */ + /* GPIOB: 0x400B2000 */ + /* GPIOC: 0x400B4000 */ + /* GPIOD: 0x400B6000 */ + /* GPIOE: 0x400B8000 */ + /* GPIOF: 0x400BA000 */ + __IO uint32_t DIRCR; /*!< 0x000 Data Direction Control Register */ + __IO uint32_t INER; /*!< 0x004 Input function enable register */ + __IO uint32_t PUR; /*!< 0x008 Pull-Up Selection Register */ + __IO uint32_t PDR; /*!< 0x00C Pull-Down Selection Register */ + __IO uint32_t ODR; /*!< 0x010 Open Drain Selection Register */ + __IO uint32_t DRVR; /*!< 0x014 Drive Current Selection Register */ + __IO uint32_t LOCKR; /*!< 0x018 Lock Register */ + __IO uint32_t DINR; /*!< 0x01c Data Input Register */ + __IO uint32_t DOUTR; /*!< 0x020 Data Output Register */ + __IO uint32_t SRR; /*!< 0x024 Output Set and Reset Control Register */ + __IO uint32_t RR; /*!< 0x028 Output Reset Control Register */ +} HT_GPIO_TypeDef; + + +/** + * @brief AFIO + */ +typedef struct +{ + /* AFIO: 0x40022000 */ + __IO uint32_t ESSR[2]; /*!< 0x000 EXTI Source Selection Register 0 ~ 1 */ + uint32_t RESERVE0[6]; /*!< 0x008 - 0x01C Reserved */ + __IO uint32_t GPACFGR[2]; /*!< 0x020 GPIO Port A Configuration Register 0 ~ 1 */ + __IO uint32_t GPBCFGR[2]; /*!< 0x028 GPIO Port B Configuration Register 0 ~ 1 */ + __IO uint32_t GPCCFGR[2]; /*!< 0x030 GPIO Port C Configuration Register 0 ~ 1 */ + __IO uint32_t GPDCFGR[2]; /*!< 0x038 GPIO Port D Configuration Register 0 ~ 1 */ +#if defined(USE_HT32F1655_56) || defined(USE_HT32F12365_66) + __IO uint32_t GPECFGR[2]; /*!< 0x040 GPIO Port E Configuration Register 0 ~ 1 */ +#else + uint32_t RESERVE1[2]; /*!< 0x040 - 0x044 Reserved */ +#endif +#if defined(USE_HT32F12364) + __IO uint32_t GPECFGR[2]; /*!< 0x048 GPIO Port F Configuration Register 0 ~ 1 */ +#endif +} HT_AFIO_TypeDef; + + +/** + * @brief External Interrupt/Event Controller + */ +typedef struct +{ + /* EXTI: 0x40024000 */ + __IO uint32_t CFGR0; /*!< 0x000 EXTI Interrupt 0 Configuration Register */ + __IO uint32_t CFGR1; /*!< 0x004 EXTI Interrupt 1 Configuration Register */ + __IO uint32_t CFGR2; /*!< 0x008 EXTI Interrupt 2 Configuration Register */ + __IO uint32_t CFGR3; /*!< 0x00C EXTI Interrupt 3 Configuration Register */ + __IO uint32_t CFGR4; /*!< 0x010 EXTI Interrupt 4 Configuration Register */ + __IO uint32_t CFGR5; /*!< 0x014 EXTI Interrupt 5 Configuration Register */ + __IO uint32_t CFGR6; /*!< 0x018 EXTI Interrupt 6 Configuration Register */ + __IO uint32_t CFGR7; /*!< 0x01C EXTI Interrupt 7 Configuration Register */ + __IO uint32_t CFGR8; /*!< 0x020 EXTI Interrupt 8 Configuration Register */ + __IO uint32_t CFGR9; /*!< 0x024 EXTI Interrupt 9 Configuration Register */ + __IO uint32_t CFGR10; /*!< 0x028 EXTI Interrupt 10 Configuration Register */ + __IO uint32_t CFGR11; /*!< 0x02C EXTI Interrupt 11 Configuration Register */ + __IO uint32_t CFGR12; /*!< 0x030 EXTI Interrupt 12 Configuration Register */ + __IO uint32_t CFGR13; /*!< 0x034 EXTI Interrupt 13 Configuration Register */ + __IO uint32_t CFGR14; /*!< 0x038 EXTI Interrupt 14 Configuration Register */ + __IO uint32_t CFGR15; /*!< 0x03C EXTI Interrupt 15 Configuration Register */ + __IO uint32_t CR; /*!< 0x040 EXTI Interrupt Control Register */ + __IO uint32_t EDGEFLGR; /*!< 0x044 EXTI Interrupt Edge Flag Register */ + __IO uint32_t EDGESR; /*!< 0x048 EXTI Interrupt Edge Status Register */ + __IO uint32_t SSCR; /*!< 0x04C EXTI Interrupt Software Set Command Register */ + __IO uint32_t WAKUPCR; /*!< 0x050 EXTI Interrupt Wakeup Control Register */ + __IO uint32_t WAKUPPOLR; /*!< 0x054 EXTI Interrupt Wakeup Polarity Register */ + __IO uint32_t WAKUPFLG; /*!< 0x058 EXTI Interrupt Wakeup Flag Register */ +} HT_EXTI_TypeDef; + + +/** + * @brief Inter-integrated Circuit Interface + */ +typedef struct +{ + /* I2C0: 0x40048000 */ + /* I2C1: 0x40049000 */ + __IO uint32_t CR; /*!< 0x000 Control Register */ + __IO uint32_t IER; /*!< 0x004 Interrupt Enable Register */ + __IO uint32_t ADDR; /*!< 0x008 Address Register */ + __IO uint32_t SR; /*!< 0x00C Status Register */ + __IO uint32_t SHPGR; /*!< 0x010 SCL High Period Generation Register */ + __IO uint32_t SLPGR; /*!< 0x014 SCL Low Period Generation Register */ + __IO uint32_t DR; /*!< 0x018 Data Register */ + __IO uint32_t TAR; /*!< 0x01C Target Register */ + __IO uint32_t ADDMR; /*!< 0x020 Address Mask Register */ + __IO uint32_t ADDSR; /*!< 0x024 Address Snoop Register */ + __IO uint32_t TOUT; /*!< 0x028 Timeout Register */ +} HT_I2C_TypeDef; + + +/** + * @brief WATCHDOG + */ +typedef struct +{ + /* WDT: 0x40068000 */ + __IO uint32_t CR; /*!< 0x000 Control Register */ + __IO uint32_t MR0; /*!< 0x004 Mode 0 Register */ + __IO uint32_t MR1; /*!< 0x008 Mode 1 Register */ + __IO uint32_t SR; /*!< 0x00C Status Register */ + __IO uint32_t PR; /*!< 0x010 Write Protect Register */ +#if defined(USE_HT32F1655_56) + __IO uint32_t CNTR; /*!< 0x014 Counter Register */ +#else + uint32_t RESERVED0[1]; /*!< 0x014 Reserved */ +#endif + __IO uint32_t CSR; /*!< 0x018 Clock Selection Register */ +} HT_WDT_TypeDef; + + +/** + * @brief Real-Time Clock + */ +typedef struct +{ + /* RTC: 0x4006A000 */ + __IO uint32_t CNT; /*!< 0x000 RTC Counter Register */ + __IO uint32_t CMP; /*!< 0x004 RTC Compare Register */ + __IO uint32_t CR; /*!< 0x008 RTC Control Register */ + __IO uint32_t SR; /*!< 0x00C RTC Status Register */ + __IO uint32_t IWEN; /*!< 0x010 RTC Interrupt/Wake-up Enable Register */ +} HT_RTC_TypeDef; + + +/** + * @brief Power Control Unit + */ +typedef struct +{ + /* PWRCU: 0x4006A100 */ + __IO uint32_t SR; /*!< 0x000 Status Register */ + __IO uint32_t CR; /*!< 0x004 Control Register */ + __IO uint32_t TEST; /*!< 0x008 Test Register */ + __IO uint32_t HSIRCR; /*!< 0x00C HSI Ready Counter Control Register */ + __IO uint32_t LVDCSR; /*!< 0x010 Low Voltage/Brown Out Detect Control and Status Register*/ + uint32_t RESERVE1[59]; /*!< 0x014 ~ 0x0FC Reserved */ +#if !defined(USE_HT32F12364) + __IO uint32_t BAKREG[10]; /*!< 0x100 ~ 0x124 Backup Register 0 ~ 9 */ +#endif +} HT_PWRCU_TypeDef; + + +#if 0 +/** + * @brief General-Purpose Timer + */ +typedef struct +{ + /* GPTM0: 0x4006E000 */ + /* GPTM1: 0x4006F000 */ + __IO uint32_t CNTCFR; /*!< 0x000 Counter Configuration Register */ + __IO uint32_t MDCFR; /*!< 0x004 Mode Configuration Register */ + __IO uint32_t TRCFR; /*!< 0x008 Trigger Configuration Register */ + uint32_t RESERVED0[1]; /*!< 0x00C Reserved */ + __IO uint32_t CTR; /*!< 0x010 Control Register */ + uint32_t RESERVED1[3]; /*!< 0x014 - 0x01C Reserved */ + __IO uint32_t CH0ICFR; /*!< 0x020 Channel-0 Input Configuration Register */ + __IO uint32_t CH1ICFR; /*!< 0x024 Channel-1 Input Configuration Register */ + __IO uint32_t CH2ICFR; /*!< 0x028 Channel-2 Input Configuration Register */ + __IO uint32_t CH3ICFR; /*!< 0x02C Channel-3 Input Configuration Register */ + uint32_t RESERVED2[4]; /*!< 0x030 - 0x03C Reserved */ + __IO uint32_t CH0OCFR; /*!< 0x040 Channel-0 Output Configuration Register */ + __IO uint32_t CH1OCFR; /*!< 0x044 Channel-1 Output Configuration Register */ + __IO uint32_t CH2OCFR; /*!< 0x048 Channel-2 Output Configuration Register */ + __IO uint32_t CH3OCFR; /*!< 0x04C Channel-3 Output Configuration Register */ + __IO uint32_t CHCTR; /*!< 0x050 Channel Control Register */ + __IO uint32_t CHPOLR; /*!< 0x054 Channel Polarity Configuration Register */ + uint32_t RESERVED3[7]; /*!< 0x058 - 0x070 Reserved */ + __IO uint32_t DICTR; /*!< 0x074 DMA / Interrupt Control Register */ + __IO uint32_t EVGR; /*!< 0x078 Event Generator Register */ + __IO uint32_t INTSR; /*!< 0x07C Interrupt Status Register */ + __IO uint32_t CNTR; /*!< 0x080 Counter Register */ + __IO uint32_t PSCR; /*!< 0x084 Prescaler Register */ + __IO uint32_t CRR; /*!< 0x088 Counter Reload Register */ + uint32_t RESERVED4[1]; /*!< 0x08C Reserved */ + __IO uint32_t CH0CCR; /*!< 0x090 Channel 0 Capture/Compare Register */ + __IO uint32_t CH1CCR; /*!< 0x094 Channel 1 Capture/Compare Register */ + __IO uint32_t CH2CCR; /*!< 0x098 Channel 2 Capture/Compare Register */ + __IO uint32_t CH3CCR; /*!< 0x09C Channel 3 Capture/Compare Register */ + __IO uint32_t CH0ACR; /*!< 0x0A0 Channel 0 Asymmetric Compare Register */ + __IO uint32_t CH1ACR; /*!< 0x0A4 Channel 1 Asymmetric Compare Register */ + __IO uint32_t CH2ACR; /*!< 0x0A8 Channel 2 Asymmetric Compare Register */ + __IO uint32_t CH3ACR; /*!< 0x0AC Channel 3 Asymmetric Compare Register */ +} HT_GPTM_TypeDef; +#endif + + +/** + * @brief Flash Memory Controller + */ +typedef struct +{ + /* FLASH: 0x40080000 */ + __IO uint32_t TADR; /*!< 0x000 Flash Target Address Register */ + __IO uint32_t WRDR; /*!< 0x004 Flash Write Data Register */ + uint32_t RESERVED0[1]; /*!< 0x008 Reserved */ + __IO uint32_t OCMR; /*!< 0x00C Flash Operation Command Register */ + __IO uint32_t OPCR; /*!< 0x010 Flash Operation Control Register */ + __IO uint32_t OIER; /*!< 0x014 Flash Operation Interrupt Enable Register */ + __IO uint32_t OISR; /*!< 0x018 Flash Operation Interrupt and Status Register */ + uint32_t RESERVED1[1]; /*!< 0x01C Reserved */ + __IO uint32_t PPSR[4]; /*!< 0x020 ~ 0x02C Flash Page Erase/Program Protection Status Register */ + __IO uint32_t CPSR; /*!< 0x030 Flash Security Protection Status Register */ + uint32_t RESERVED2[51]; /*!< 0x034 ~ 0x0FC Reserved */ + __IO uint32_t VMCR; /*!< 0x100 Flash Vector Mapping Control Register */ + uint32_t RESERVED3[31]; /*!< 0x104 ~ 0x17C Reserved */ + __IO uint32_t MDID; /*!< 0x180 Manufacturer and Device ID Register */ + __IO uint32_t PNSR; /*!< 0x184 Flash Page Number Status Register */ + __IO uint32_t PSSR; /*!< 0x188 Flash Page Size Status Register */ +#if defined(USE_HT32F1653_54) | defined(USE_HT32F1655_56) + uint32_t RESERVED4[29]; /*!< 0x18C ~ 0x1FC Reserved */ +#else + __IO uint32_t DID; /*!< 0x18C Device ID Register */ + uint32_t RESERVED4[28]; /*!< 0x190 ~ 0x1FC Reserved */ +#endif + __IO uint32_t CFCR; /*!< 0x200 Flash Cache and Pre-fetch Control Register */ + uint32_t RESERVED5[63]; /*!< 0x204 ~ 0x2FC Reserved */ + __IO uint32_t SBVT[4]; /*!< 0x300 ~ 0x30C SRAM Booting Vector (4x32Bit) */ +#if defined(USE_HT32F1653_54) | defined(USE_HT32F1655_56) +#else + __IO uint32_t CID[4]; /*!< 0x310 ~ 0x31C Custom ID Register */ +#endif +} HT_FLASH_TypeDef; + + +/** + * @brief Clock Control Unit + */ +typedef struct +{ + /* CKCU: 0x40088000 */ + __IO uint32_t GCFGR; /*!< 0x000 Global Clock Configuration Register */ + __IO uint32_t GCCR; /*!< 0x004 Global Clock Control Register */ + __IO uint32_t GCSR; /*!< 0x008 Global Clock Status Register */ + __IO uint32_t GCIR; /*!< 0x00C Global Clock Interrupt Register */ + uint32_t RESERVED0[2]; /*!< 0x010 ~ 0x14 Reserved */ + __IO uint32_t PLLCFGR; /*!< 0x018 PLL Configuration Register */ + __IO uint32_t PLLCR; /*!< 0x01C PLL Control Register */ + __IO uint32_t AHBCFGR; /*!< 0x020 AHB Configuration Register */ + __IO uint32_t AHBCCR; /*!< 0x024 AHB Clock Control Register */ + __IO uint32_t APBCFGR; /*!< 0x028 APB Configuration Register */ + __IO uint32_t APBCCR0; /*!< 0x02C APB Clock Control Register 0 */ + __IO uint32_t APBCCR1; /*!< 0x030 APB Clock Control Register 1 */ + __IO uint32_t CKST; /*!< 0x034 Clock source status Register */ +#if defined(USE_HT32F1655_56) + uint32_t RESERVED1[4]; /*!< 0x038 ~ 0x44 Reserved */ +#else + __IO uint32_t APBPCSR0; /*!< 0x038 APB Peripheral Clock Selection Register 0 */ + __IO uint32_t APBPCSR1; /*!< 0x03C APB Peripheral Clock Selection Register 1 */ + __IO uint32_t HSICR; /*!< 0x040 HSI Control Register */ + __IO uint32_t HSIATCR; /*!< 0x044 HSI Auto Trimming Counter Register */ +#endif +#if defined(USE_HT32F12364) + __IO uint32_t APBPCSR2; /*!< 0x048 APB Peripheral Clock Selection Register 2 */ + uint32_t RESERVED2[173]; /*!< 0x04C ~ 0x2FC Reserved */ +#else + uint32_t RESERVED2[174]; /*!< 0x048 ~ 0x2FC Reserved */ +#endif + __IO uint32_t LPCR; /*!< 0x300 Low Power Control Register */ + __IO uint32_t MCUDBGCR; /*!< 0x304 MCU Debug Control Register */ +} HT_CKCU_TypeDef; + + +/** + * @brief Reset Control Unit + */ +typedef struct +{ + /* RSTCU: 0x40088100 */ + __IO uint32_t GRSR; /*!< 0x000 Global Reset Status Register */ + __IO uint32_t AHBPRST; /*!< 0x004 AHB Peripheral Reset Register */ + __IO uint32_t APBPRST0; /*!< 0x008 APB Peripheral Reset Register 0 */ + __IO uint32_t APBPRST1; /*!< 0x00C APB Peripheral Reset Register 1 */ +} HT_RSTCU_TypeDef; + + +/** + * @brief Smart Card Interface + */ +typedef struct +{ + /* SCI0: 0x40043000 */ + /* SCI1: 0x4003A000 */ + __IO uint32_t CR; /*!< 0x000 Control Register */ + __IO uint32_t SR; /*!< 0x004 Status Register */ + __IO uint32_t CCR; /*!< 0x008 Contact Control Register */ + __IO uint32_t ETU; /*!< 0x00C Elementary Time Unit Register */ + __IO uint32_t GT; /*!< 0x010 Guardtime Register */ + __IO uint32_t WT; /*!< 0x014 Waiting Time Register */ + __IO uint32_t IER; /*!< 0x018 Interrupt Enable Register */ + __IO uint32_t IPR; /*!< 0x01C Interrupt Pending Register */ + __IO uint32_t TXB; /*!< 0x020 Transmit Buffer Register */ + __IO uint32_t RXB; /*!< 0x024 Receive Buffer Register */ + __IO uint32_t PSC; /*!< 0x028 Prescaler Register */ +} HT_SCI_TypeDef; + + +/** + * @brief Basic Function Timer + */ +typedef struct +{ + /* BFTM0: 0x40076000 */ + /* BFTM1: 0x40077000 */ + __IO uint32_t CR; /*!< 0x000 Control Register */ + __IO uint32_t SR; /*!< 0x004 Status Register */ + __IO uint32_t CNTR; /*!< 0x008 Counter Value Register */ + __IO uint32_t CMP; /*!< 0x00C Compare Value Register */ +} HT_BFTM_TypeDef; + + +#if 0 +/** + * @brief Motor Control Timer + */ +typedef struct +{ + /* MCTM0: 0x4002C000 */ + /* MCTM1: 0x4002D000 */ + __IO uint32_t CNTCFR; /*!< 0x000 Counter Configuration Register */ + __IO uint32_t MDCFR; /*!< 0x004 Mode Configuration Register */ + __IO uint32_t TRCFR; /*!< 0x008 Trigger Configuration Register */ + uint32_t RESERVED0[1]; /*!< 0x00C Reserved */ + __IO uint32_t CTR; /*!< 0x010 Control Register */ + uint32_t RESERVED1[3]; /*!< 0x014 - 0x01C Reserved */ + __IO uint32_t CH0ICFR; /*!< 0x020 Channel-0 Input Configuration Register */ + __IO uint32_t CH1ICFR; /*!< 0x024 Channel-1 Input Configuration Register */ + __IO uint32_t CH2ICFR; /*!< 0x028 Channel-2 Input Configuration Register */ + __IO uint32_t CH3ICFR; /*!< 0x02C Channel-3 Input Configuration Register */ + uint32_t RESERVED2[4]; /*!< 0x030 - 0x03C Reserved */ + __IO uint32_t CH0OCFR; /*!< 0x040 Channel-0 Output Configuration Register */ + __IO uint32_t CH1OCFR; /*!< 0x044 Channel-1 Output Configuration Register */ + __IO uint32_t CH2OCFR; /*!< 0x048 Channel-2 Output Configuration Register */ + __IO uint32_t CH3OCFR; /*!< 0x04C Channel-3 Output Configuration Register */ + __IO uint32_t CHCTR; /*!< 0x050 Channel Control Register */ + __IO uint32_t CHPOLR; /*!< 0x054 Channel Polarity Configuration Register */ + uint32_t RESERVED3[5]; /*!< 0x058 - 0x068 Reserved */ + __IO uint32_t CHBRKCFR; /*!< 0x06C Channel Break Configuration Register */ + __IO uint32_t CHBRKCTR; /*!< 0x070 Channel Break Control Register */ + __IO uint32_t DICTR; /*!< 0x074 DMA / Interrupt Control Register */ + __IO uint32_t EVGR; /*!< 0x078 Event Generator Register */ + __IO uint32_t INTSR; /*!< 0x07C Interrupt Status Register */ + __IO uint32_t CNTR; /*!< 0x080 Counter Register */ + __IO uint32_t PSCR; /*!< 0x084 Prescaler Register */ + __IO uint32_t CRR; /*!< 0x088 Counter Reload Register */ + __IO uint32_t REPR; /*!< 0x08C Repetition Register */ + __IO uint32_t CH0CCR; /*!< 0x090 Channel 0 Capture/Compare Register */ + __IO uint32_t CH1CCR; /*!< 0x094 Channel 1 Capture/Compare Register */ + __IO uint32_t CH2CCR; /*!< 0x098 Channel 2 Capture/Compare Register */ + __IO uint32_t CH3CCR; /*!< 0x09C Channel 3 Capture/Compare Register */ + __IO uint32_t CH0ACR; /*!< 0x0A0 Channel 0 Asymmetric Compare Register */ + __IO uint32_t CH1ACR; /*!< 0x0A4 Channel 1 Asymmetric Compare Register */ + __IO uint32_t CH2ACR; /*!< 0x0A8 Channel 2 Asymmetric Compare Register */ + __IO uint32_t CH3ACR; /*!< 0x0AC Channel 3 Asymmetric Compare Register */ +} HT_MCTM_TypeDef; +#endif + + +/** + * @brief Timer + */ +typedef struct +{ + __IO uint32_t CNTCFR; /*!< 0x000 Counter Configuration Register */ + __IO uint32_t MDCFR; /*!< 0x004 Mode Configuration Register */ + __IO uint32_t TRCFR; /*!< 0x008 Trigger Configuration Register */ + uint32_t RESERVED0[1]; /*!< 0x00C Reserved */ + __IO uint32_t CTR; /*!< 0x010 Control Register */ + uint32_t RESERVED1[3]; /*!< 0x014 - 0x01C Reserved */ + __IO uint32_t CH0ICFR; /*!< 0x020 Channel-0 Input Configuration Register */ + __IO uint32_t CH1ICFR; /*!< 0x024 Channel-1 Input Configuration Register */ + __IO uint32_t CH2ICFR; /*!< 0x028 Channel-2 Input Configuration Register */ + __IO uint32_t CH3ICFR; /*!< 0x02C Channel-3 Input Configuration Register */ + uint32_t RESERVED2[4]; /*!< 0x030 - 0x03C Reserved */ + __IO uint32_t CH0OCFR; /*!< 0x040 Channel-0 Output Configuration Register */ + __IO uint32_t CH1OCFR; /*!< 0x044 Channel-1 Output Configuration Register */ + __IO uint32_t CH2OCFR; /*!< 0x048 Channel-2 Output Configuration Register */ + __IO uint32_t CH3OCFR; /*!< 0x04C Channel-3 Output Configuration Register */ + __IO uint32_t CHCTR; /*!< 0x050 Channel Control Register */ + __IO uint32_t CHPOLR; /*!< 0x054 Channel Polarity Configuration Register */ + uint32_t RESERVED3[5]; /*!< 0x058 - 0x068 Reserved */ + __IO uint32_t CHBRKCFR; /*!< 0x06C Channel Break Configuration Register */ + __IO uint32_t CHBRKCTR; /*!< 0x070 Channel Break Control Register */ + __IO uint32_t DICTR; /*!< 0x074 DMA / Interrupt Control Register */ + __IO uint32_t EVGR; /*!< 0x078 Event Generator Register */ + __IO uint32_t INTSR; /*!< 0x07C Interrupt Status Register */ + __IO uint32_t CNTR; /*!< 0x080 Counter Register */ + __IO uint32_t PSCR; /*!< 0x084 Prescaler Register */ + __IO uint32_t CRR; /*!< 0x088 Counter Reload Register */ + __IO uint32_t REPR; /*!< 0x08C Repetition Register */ + __IO uint32_t CH0CCR; /*!< 0x090 Channel 0 Capture/Compare Register */ + __IO uint32_t CH1CCR; /*!< 0x094 Channel 1 Capture/Compare Register */ + __IO uint32_t CH2CCR; /*!< 0x098 Channel 2 Capture/Compare Register */ + __IO uint32_t CH3CCR; /*!< 0x09C Channel 3 Capture/Compare Register */ + __IO uint32_t CH0ACR; /*!< 0x0A0 Channel 0 Asymmetric Compare Register */ + __IO uint32_t CH1ACR; /*!< 0x0A4 Channel 1 Asymmetric Compare Register */ + __IO uint32_t CH2ACR; /*!< 0x0A8 Channel 2 Asymmetric Compare Register */ + __IO uint32_t CH3ACR; /*!< 0x0AC Channel 3 Asymmetric Compare Register */ +} HT_TM_TypeDef; + + +/** + * @brief Peripheral Direct Memory Access Channel + */ +typedef struct +{ + __IO uint32_t CR; /*!< 0x000 PDMA Channel Control Register */ + __IO uint32_t SADR; /*!< 0x004 PDMA Channel Source Address Register */ + __IO uint32_t DADR; /*!< 0x008 PDMA Channel Destination Address Register */ +#if defined(USE_HT32F1653_54) || defined(USE_HT32F1655_56) + __IO uint32_t CADR; /*!< 0x00C PDMA Channel Current Address Register */ +#else + uint32_t RESERVED0[1]; /*!< 0x00C Reserved */ +#endif + __IO uint32_t TSR; /*!< 0x010 PDMA Channel Transfer Size Register */ + __IO uint32_t CTSR; /*!< 0x014 PDMA Channel Current Transfer Size Register */ +} HT_PDMACH_TypeDef; + + +/** + * @brief Peripheral Direct Memory Access Global + */ +typedef struct +{ + /* PDMA: 0x40090000 */ + HT_PDMACH_TypeDef PDMACH0; /*!< 0x000 PDMA channel 0 registers */ + HT_PDMACH_TypeDef PDMACH1; /*!< 0x018 PDMA channel 1 registers */ + HT_PDMACH_TypeDef PDMACH2; /*!< 0x030 PDMA channel 2 registers */ + HT_PDMACH_TypeDef PDMACH3; /*!< 0x048 PDMA channel 3 registers */ + HT_PDMACH_TypeDef PDMACH4; /*!< 0x060 PDMA channel 4 registers */ + HT_PDMACH_TypeDef PDMACH5; /*!< 0x078 PDMA channel 5 registers */ +#if !defined(USE_HT32F12364) + HT_PDMACH_TypeDef PDMACH6; /*!< 0x090 PDMA channel 6 registers */ + HT_PDMACH_TypeDef PDMACH7; /*!< 0x0A8 PDMA channel 7 registers */ +#endif +#if defined(USE_HT32F1653_54) || defined(USE_HT32F1655_56) + uint32_t RESERVED0[24];/*!< 0x0C0 - 0x011C Reserved */ +#elif defined(USE_HT32F12365_66) || defined(USE_HT32F12345) + HT_PDMACH_TypeDef PDMACH8; /*!< 0x0C0 PDMA channel 8 registers */ + HT_PDMACH_TypeDef PDMACH9; /*!< 0x0D8 PDMA channel 9 registers */ + HT_PDMACH_TypeDef PDMACH10; /*!< 0x0F0 PDMA channel 10 registers */ + HT_PDMACH_TypeDef PDMACH11; /*!< 0x108 PDMA channel 11 registers */ +#elif defined(USE_HT32F12364) + uint32_t RESERVED0[36];/*!< 0x090 - 0x11C Reserved */ +#endif + __IO uint32_t ISR0; /*!< 0x120 PDMA Interrupt Status Register 0 */ +#if !defined(USE_HT32F12364) + __IO uint32_t ISR1; /*!< 0x124 PDMA Interrupt Status Register 1 */ +#else + uint32_t RESERVED1[1]; /*!< 0x124 Reserved */ +#endif + __IO uint32_t ISCR0; /*!< 0x128 PDMA Interrupt Status Clear Register 0 */ +#if !defined(USE_HT32F12364) + __IO uint32_t ISCR1; /*!< 0x12C PDMA Interrupt Status Clear Register 1 */ +#else + uint32_t RESERVED2[1]; /*!< 0x12C Reserved */ +#endif + __IO uint32_t IER0; /*!< 0x130 PDMA Interrupt Enable Register 0 */ +#if !defined(USE_HT32F12364) + __IO uint32_t IER1; /*!< 0x134 PDMA Interrupt Enable Register 1 */ +#endif +} HT_PDMA_TypeDef; + + +/** + * @brief Universal Serial Bus Global + */ +typedef struct +{ + /* USB: 0x400A8000 */ + __IO uint32_t CSR; /*!< 0x000 USB Control and Status Register */ + __IO uint32_t IER; /*!< 0x004 USB Interrupt Enable Register */ + __IO uint32_t ISR; /*!< 0x008 USB Interrupt Status Register */ + __IO uint32_t FCR; /*!< 0x00C USB Frame Count Register */ + __IO uint32_t DEVAR; /*!< 0x010 USB Device Address Register */ + __IO uint32_t EP0CSR; /*!< 0x014 USB Endpoint 0 Control and Status Register */ + __IO uint32_t EP0IER; /*!< 0x018 USB Endpoint 0 Interrupt Enable Register */ + __IO uint32_t EP0ISR; /*!< 0x01C USB Endpoint 0 Interrupt Status Register */ + __IO uint32_t EP0TCR; /*!< 0x020 USB Endpoint 0 Transfer Count Register */ + __IO uint32_t EP0CFGR; /*!< 0x024 USB Endpoint 0 Configuration Register */ + __IO uint32_t EP1CSR; /*!< 0x028 USB Endpoint 1 Control and Status Register */ + __IO uint32_t EP1IER; /*!< 0x02C USB Endpoint 1 Interrupt Enable Register */ + __IO uint32_t EP1ISR; /*!< 0x030 USB Endpoint 1 Interrupt Status Register */ + __IO uint32_t EP1TCR; /*!< 0x034 USB Endpoint 1 Transfer Count Register */ + __IO uint32_t EP1CFGR; /*!< 0x038 USB Endpoint 1 Configuration Register */ + __IO uint32_t EP2CSR; /*!< 0x03C USB Endpoint 2 Control and Status Register */ + __IO uint32_t EP2IER; /*!< 0x040 USB Endpoint 2 Interrupt Enable Register */ + __IO uint32_t EP2ISR; /*!< 0x044 USB Endpoint 2 Interrupt Status Register */ + __IO uint32_t EP2TCR; /*!< 0x048 USB Endpoint 2 Transfer Count Register */ + __IO uint32_t EP2CFGR; /*!< 0x04C USB Endpoint 2 Configuration Register */ + __IO uint32_t EP3CSR; /*!< 0x050 USB Endpoint 3 Control and Status Register */ + __IO uint32_t EP3IER; /*!< 0x054 USB Endpoint 3 Interrupt Enable Register */ + __IO uint32_t EP3ISR; /*!< 0x058 USB Endpoint 3 Interrupt Status Register */ + __IO uint32_t EP3TCR; /*!< 0x05C USB Endpoint 3 Transfer Count Register */ + __IO uint32_t EP3CFGR; /*!< 0x060 USB Endpoint 3 Configuration Register */ + __IO uint32_t EP4CSR; /*!< 0x064 USB Endpoint 4 Control and Status Register */ + __IO uint32_t EP4IER; /*!< 0x068 USB Endpoint 4 Interrupt Enable Register */ + __IO uint32_t EP4ISR; /*!< 0x06C USB Endpoint 4 Interrupt Status Register */ + __IO uint32_t EP4TCR; /*!< 0x070 USB Endpoint 4 Transfer Count Register */ + __IO uint32_t EP4CFGR; /*!< 0x074 USB Endpoint 4 Configuration Register */ + __IO uint32_t EP5CSR; /*!< 0x078 USB Endpoint 5 Control and Status Register */ + __IO uint32_t EP5IER; /*!< 0x07C USB Endpoint 5 Interrupt Enable Register */ + __IO uint32_t EP5ISR; /*!< 0x080 USB Endpoint 5 Interrupt Status Register */ + __IO uint32_t EP5TCR; /*!< 0x084 USB Endpoint 5 Transfer Count Register */ + __IO uint32_t EP5CFGR; /*!< 0x088 USB Endpoint 5 Configuration Register */ + __IO uint32_t EP6CSR; /*!< 0x08C USB Endpoint 6 Control and Status Register */ + __IO uint32_t EP6IER; /*!< 0x090 USB Endpoint 6 Interrupt Enable Register */ + __IO uint32_t EP6ISR; /*!< 0x094 USB Endpoint 6 Interrupt Status Register */ + __IO uint32_t EP6TCR; /*!< 0x098 USB Endpoint 6 Transfer Count Register */ + __IO uint32_t EP6CFGR; /*!< 0x09C USB Endpoint 6 Configuration Register */ + __IO uint32_t EP7CSR; /*!< 0x0A0 USB Endpoint 7 Control and Status Register */ + __IO uint32_t EP7IER; /*!< 0x0A4 USB Endpoint 7 Interrupt Enable Register */ + __IO uint32_t EP7ISR; /*!< 0x0A8 USB Endpoint 7 Interrupt Status Register */ + __IO uint32_t EP7TCR; /*!< 0x0AC USB Endpoint 7 Transfer Count Register */ + __IO uint32_t EP7CFGR; /*!< 0x0B0 USB Endpoint 7 Configuration Register */ +} HT_USB_TypeDef; + + +/** + * @brief Universal Serial Bus Endpoint + */ +typedef struct +{ + /* USB Endpoint0: 0x400A8014 */ + /* USB Endpoint1: 0x400A8028 */ + /* USB Endpoint2: 0x400A803C */ + /* USB Endpoint3: 0x400A8050 */ + /* USB Endpoint4: 0x400A8064 */ + /* USB Endpoint5: 0x400A8078 */ + /* USB Endpoint6: 0x400A808C */ + /* USB Endpoint7: 0x400A80A0 */ + __IO uint32_t CSR; /*!< 0x000 USB Endpoint n Control and Status Register */ + __IO uint32_t IER; /*!< 0x004 USB Endpoint n Interrupt Enable Register */ + __IO uint32_t ISR; /*!< 0x008 USB Endpoint n Interrupt Status Register */ + __IO uint32_t TCR; /*!< 0x00C USB Endpoint n Transfer Count Register */ + __IO uint32_t CFGR; /*!< 0x010 USB Endpoint n Configuration Register */ +} HT_USBEP_TypeDef; + + +/** + * @brief External Bus Interface + */ +typedef struct +{ + /* EBI: 0x40098000 */ + __IO uint32_t CR; /*!< 0x000 EBI Control Register */ +#if !defined(USE_HT32F12364) + __IO uint32_t PCR; /*!< 0x004 EBI Page Control Register */ +#else + uint32_t RESERVED0[1]; /*!< 0x004 Reserved */ +#endif + __IO uint32_t SR; /*!< 0x008 EBI Status Register */ + uint32_t RESERVED1[1]; /*!< 0x00C Reserved */ + __IO uint32_t ATR0; /*!< 0x010 EBI Address Timing Register 0 */ + __IO uint32_t RTR0; /*!< 0x014 EBI Read Timing Register 0 */ + __IO uint32_t WTR0; /*!< 0x018 EBI Write Timing Register 0 */ + __IO uint32_t PR0; /*!< 0x01C EBI Parity Register 0 */ +#if !defined(USE_HT32F12364) + __IO uint32_t ATR1; /*!< 0x020 EBI Address Timing Register 1 */ + __IO uint32_t RTR1; /*!< 0x024 EBI Read Timing Register 1 */ + __IO uint32_t WTR1; /*!< 0x028 EBI Write Timing Register 1 */ + __IO uint32_t PR1; /*!< 0x02C EBI Parity Register 1 */ + __IO uint32_t ATR2; /*!< 0x030 EBI Address Timing Register 2 */ + __IO uint32_t RTR2; /*!< 0x034 EBI Read Timing Register 2 */ + __IO uint32_t WTR2; /*!< 0x038 EBI Write Timing Register 2 */ + __IO uint32_t PR2; /*!< 0x03C EBI Parity Register 2 */ + __IO uint32_t ATR3; /*!< 0x040 EBI Address Timing Register 3 */ + __IO uint32_t RTR3; /*!< 0x044 EBI Read Timing Register 3 */ + __IO uint32_t WTR3; /*!< 0x048 EBI Write Timing Register 3 */ + __IO uint32_t PR3; /*!< 0x04C EBI Parity Register 3 */ + __IO uint32_t IEN; /*!< 0x050 EBI Interrupt Enable Register */ + __IO uint32_t IF; /*!< 0x054 EBI Interrupt Flag Register */ + __IO uint32_t IFC; /*!< 0x058 EBI Interrupt Clear Register */ +#endif +} HT_EBI_TypeDef; + + +/** + * @brief Cyclic Redundancy Check + */ +typedef struct +{ + /* CRC: 0x4008A000 */ + __IO uint32_t CR; /*!< 0x000 CRC Control Register */ + __IO uint32_t SDR; /*!< 0x004 CRC Seed Register */ + __IO uint32_t CSR; /*!< 0x008 CRC Checksum Register */ + __IO uint32_t DR; /*!< 0x00C CRC Data Register */ +} HT_CRC_TypeDef; + + +/** + * @brief Integrated Interchip Sound + */ +typedef struct +{ + /* I2S: 0x40026000 */ + __IO uint32_t CR; /*!< 0x000 I2S Control Register */ + __IO uint32_t IER; /*!< 0x004 I2S Interrupt Enable Register */ + __IO uint32_t CDR; /*!< 0x008 I2S Clock Divider Register */ + __IO uint32_t TXDR; /*!< 0x00C I2S TX Data Register */ + __IO uint32_t RXDR; /*!< 0x010 I2S RX Data Register */ + __IO uint32_t FCR; /*!< 0x014 I2S FIFO Control Register */ + __IO uint32_t SR; /*!< 0x018 I2S Status Register */ + __IO uint32_t RCNTR; /*!< 0x01C I2S Rate Counter Register */ +} HT_I2S_TypeDef; + + +/** + * @brief Secure digital input/output + */ +typedef struct +{ + /* SDIO: 0x400A0000 */ + __IO uint32_t BLKSIZE; /*!< 0x000 Block Size Register */ + __IO uint32_t BLKCNT; /*!< 0x004 Block Count Register */ + __IO uint32_t ARG; /*!< 0x008 Argument Register */ + __IO uint32_t TMR; /*!< 0x00C Transfer Mode Register */ + __IO uint32_t CMD; /*!< 0x010 Command Register Register */ + __IO uint32_t RESP0; /*!< 0x014 Response Register 0 */ + __IO uint32_t RESP1; /*!< 0x018 Response Register 1 */ + __IO uint32_t RESP2; /*!< 0x01C Response Register 2 */ + __IO uint32_t RESP3; /*!< 0x020 Response Register 3 */ + __IO uint32_t DR; /*!< 0x024 Data Register */ + __IO uint32_t PSR; /*!< 0x028 Present Status Register */ + __IO uint32_t CR; /*!< 0x02C Control Register */ + uint32_t RESERVED0[2]; /*!< 0x030 - 0x034 Reserved */ + __IO uint32_t CLKCR; /*!< 0x038 Clock Control Register */ + __IO uint32_t TMOCR; /*!< 0x03C Timeout Control Register */ + __IO uint32_t SWRST; /*!< 0x040 Software Reset Register */ + __IO uint32_t SR; /*!< 0x044 Status Register */ + __IO uint32_t SER; /*!< 0x048 Status Enable Register */ + __IO uint32_t IER; /*!< 0x04C Interrupt Enable Register */ +} HT_SDIO_TypeDef; + + +/** + * @brief CMOS Sensor Interface + */ +typedef struct +{ + /* CSIF: 0x400CC000 */ + __IO uint32_t ENR; /*!< 0x000 Enable Register */ + __IO uint32_t CR; /*!< 0x004 Control Register */ + __IO uint32_t IMGWH; /*!< 0x008 Image Width/Height Register */ + __IO uint32_t WCR0; /*!< 0x00C Window Capture 0 Register */ + __IO uint32_t WCR1; /*!< 0x010 Window Capture 1 Register */ + __IO uint32_t SMP; /*!< 0x014 Row & Column Sub-Sample Register */ + __IO uint32_t SMPCOL; /*!< 0x018 Column Sub-Sample Register */ + __IO uint32_t SMPROW; /*!< 0x01C Row Sub-Sample Register */ + __IO uint32_t FIFO0; /*!< 0x020 FIFO Register 0 */ + __IO uint32_t FIFO1; /*!< 0x024 FIFO Register 1 */ + __IO uint32_t FIFO2; /*!< 0x028 FIFO Register 2 */ + __IO uint32_t FIFO3; /*!< 0x02C FIFO Register 3 */ + __IO uint32_t FIFO4; /*!< 0x030 FIFO Register 4 */ + __IO uint32_t FIFO5; /*!< 0x034 FIFO Register 5 */ + __IO uint32_t FIFO6; /*!< 0x038 FIFO Register 6 */ + __IO uint32_t FIFO7; /*!< 0x03C FIFO Register 7 */ + __IO uint32_t IER; /*!< 0x040 Interrupt Enable Register */ + __IO uint32_t SR; /*!< 0x044 Status Register */ +} HT_CSIF_TypeDef; + + +/** + * @brief Advanced Encryption Standard + */ +typedef struct +{ + /* AES: 0x400C8000 */ + __IO uint32_t CR; /*!< 0x000 Control Register */ + __IO uint32_t SR; /*!< 0x004 Status Register */ + __IO uint32_t PDMAR; /*!< 0x008 PDMA Register */ + __IO uint32_t ISR; /*!< 0x00C Interrupt Status Register */ + __IO uint32_t IER; /*!< 0x010 Interrupt Enable Register */ + __IO uint32_t DINR; /*!< 0x014 Data Input Register */ + __IO uint32_t DOUTR; /*!< 0x018 Data Output Register */ + __IO uint32_t KEYR[8]; /*!< 0x01C - 0x038 Key Register 0~7 */ + __IO uint32_t IVR[4]; /*!< 0x03C - 0x048 Initial Vector Register 0~3 */ +} HT_AES_TypeDef; + + +/** + * @} + */ + + +/** @addtogroup Peripheral_Memory_Map + * @{ + */ + +#define HT_SRAM_BASE (0x20000000UL) +#define HT_SRAM_BB_BASE (0x22000000UL) + +#define HT_PERIPH_BASE (0x40000000UL) +#define HT_PERIPH_BB_BASE (0x42000000UL) + +#define HT_APB0PERIPH_BASE (HT_PERIPH_BASE) /* 0x40000000 */ +#define HT_APB1PERIPH_BASE (HT_PERIPH_BASE + 0x40000) /* 0x40040000 */ +#define HT_AHBPERIPH_BASE (HT_PERIPH_BASE + 0x80000) /* 0x40080000 */ + +/* APB0 */ +#define HT_USART0_BASE (HT_APB0PERIPH_BASE + 0x0000) /* 0x40000000 */ +#define HT_UART0_BASE (HT_APB0PERIPH_BASE + 0x1000) /* 0x40001000 */ +#define HT_SPI0_BASE (HT_APB0PERIPH_BASE + 0x4000) /* 0x40004000 */ +#define HT_ADC0_BASE (HT_APB0PERIPH_BASE + 0x10000) /* 0x40010000 */ +#define HT_CMP_OP0_BASE (HT_APB0PERIPH_BASE + 0x18000) /* 0x40018000 */ +#define HT_CMP_OP1_BASE (HT_APB0PERIPH_BASE + 0x18100) /* 0x40018100 */ +#define HT_AFIO_BASE (HT_APB0PERIPH_BASE + 0x22000) /* 0x40022000 */ +#define HT_EXTI_BASE (HT_APB0PERIPH_BASE + 0x24000) /* 0x40024000 */ +#define HT_I2S_BASE (HT_APB0PERIPH_BASE + 0x26000) /* 0x40026000 */ +#define HT_MCTM0_BASE (HT_APB0PERIPH_BASE + 0x2C000) /* 0x4002C000 */ +#define HT_MCTM1_BASE (HT_APB0PERIPH_BASE + 0x2D000) /* 0x4002D000 */ +#define HT_PWM0_BASE (HT_APB0PERIPH_BASE + 0x31000) /* 0x40031000 */ +#define HT_SCTM0_BASE (HT_APB0PERIPH_BASE + 0x34000) /* 0x40034000 */ +#define HT_SCI1_BASE (HT_APB0PERIPH_BASE + 0x3A000) /* 0x4003A000 */ + +/* APB1 */ +#define HT_USART1_BASE (HT_APB1PERIPH_BASE + 0x0000) /* 0x40040000 */ +#define HT_UART1_BASE (HT_APB1PERIPH_BASE + 0x1000) /* 0x40041000 */ +#define HT_SCI0_BASE (HT_APB1PERIPH_BASE + 0x3000) /* 0x40043000 */ +#define HT_SPI1_BASE (HT_APB1PERIPH_BASE + 0x4000) /* 0x40044000 */ +#define HT_I2C0_BASE (HT_APB1PERIPH_BASE + 0x8000) /* 0x40048000 */ +#define HT_I2C1_BASE (HT_APB1PERIPH_BASE + 0x9000) /* 0x40049000 */ +#define HT_CMP0_BASE (HT_APB1PERIPH_BASE + 0x18000) /* 0x40058000 */ +#define HT_CMP1_BASE (HT_APB1PERIPH_BASE + 0x18100) /* 0x40058100 */ +#define HT_WDT_BASE (HT_APB1PERIPH_BASE + 0x28000) /* 0x40068000 */ +#define HT_RTC_BASE (HT_APB1PERIPH_BASE + 0x2A000) /* 0x4006A000 */ +#define HT_PWRCU_BASE (HT_APB1PERIPH_BASE + 0x2A100) /* 0x4006A100 */ +#define HT_GPTM0_BASE (HT_APB1PERIPH_BASE + 0x2E000) /* 0x4006E000 */ +#define HT_GPTM1_BASE (HT_APB1PERIPH_BASE + 0x2F000) /* 0x4006F000 */ +#define HT_SCTM1_BASE (HT_APB1PERIPH_BASE + 0x34000) /* 0x40074000 */ +#define HT_BFTM0_BASE (HT_APB1PERIPH_BASE + 0x36000) /* 0x40076000 */ +#define HT_BFTM1_BASE (HT_APB1PERIPH_BASE + 0x37000) /* 0x40077000 */ + +/* AHB */ +#define HT_FLASH_BASE (HT_AHBPERIPH_BASE + 0x0000) /* 0x40080000 */ +#define HT_CKCU_BASE (HT_AHBPERIPH_BASE + 0x8000) /* 0x40088000 */ +#define HT_RSTCU_BASE (HT_AHBPERIPH_BASE + 0x8100) /* 0x40088100 */ +#define HT_CRC_BASE (HT_AHBPERIPH_BASE + 0xA000) /* 0x4008A000 */ +#define HT_PDMA_BASE (HT_AHBPERIPH_BASE + 0x10000) /* 0x40090000 */ +#define HT_EBI_BASE (HT_AHBPERIPH_BASE + 0x18000) /* 0x40098000 */ +#define HT_SDIO_BASE (HT_AHBPERIPH_BASE + 0x20000) /* 0x400A0000 */ +#define HT_USB_BASE (HT_AHBPERIPH_BASE + 0x28000) /* 0x400A8000 */ +#define HT_USB_EP0_BASE (HT_USB_BASE + 0x0014) /* 0x400A8014 */ +#define HT_USB_EP1_BASE (HT_USB_BASE + 0x0028) /* 0x400A8028 */ +#define HT_USB_EP2_BASE (HT_USB_BASE + 0x003C) /* 0x400A803C */ +#define HT_USB_EP3_BASE (HT_USB_BASE + 0x0050) /* 0x400A8050 */ +#define HT_USB_EP4_BASE (HT_USB_BASE + 0x0064) /* 0x400A8064 */ +#define HT_USB_EP5_BASE (HT_USB_BASE + 0x0078) /* 0x400A8078 */ +#define HT_USB_EP6_BASE (HT_USB_BASE + 0x008C) /* 0x400A808C */ +#define HT_USB_EP7_BASE (HT_USB_BASE + 0x00A0) /* 0x400A80A0 */ +#define HT_USB_SRAM_BASE (HT_AHBPERIPH_BASE + 0x2A000) /* 0x400AA000 */ +#define HT_GPIOA_BASE (HT_AHBPERIPH_BASE + 0x30000) /* 0x400B0000 */ +#define HT_GPIOB_BASE (HT_AHBPERIPH_BASE + 0x32000) /* 0x400B2000 */ +#define HT_GPIOC_BASE (HT_AHBPERIPH_BASE + 0x34000) /* 0x400B4000 */ +#define HT_GPIOD_BASE (HT_AHBPERIPH_BASE + 0x36000) /* 0x400B6000 */ +#define HT_GPIOE_BASE (HT_AHBPERIPH_BASE + 0x38000) /* 0x400B8000 */ +#define HT_GPIOF_BASE (HT_AHBPERIPH_BASE + 0x3A000) /* 0x400BA000 */ +#define HT_AES_BASE (HT_AHBPERIPH_BASE + 0x48000) /* 0x400C8000 */ +#define HT_CSIF_BASE (HT_AHBPERIPH_BASE + 0x4C000) /* 0x400CC000 */ + +/** + * @} + */ + +/* Peripheral declaration */ +#define HT_ADC0 ((HT_ADC_TypeDef *) HT_ADC0_BASE) +#define HT_AFIO ((HT_AFIO_TypeDef *) HT_AFIO_BASE) +#define HT_BFTM0 ((HT_BFTM_TypeDef *) HT_BFTM0_BASE) +#define HT_BFTM1 ((HT_BFTM_TypeDef *) HT_BFTM1_BASE) +#define HT_CKCU ((HT_CKCU_TypeDef *) HT_CKCU_BASE) +#define HT_CRC ((HT_CRC_TypeDef *) HT_CRC_BASE) +#define HT_EXTI ((HT_EXTI_TypeDef *) HT_EXTI_BASE) +#define HT_FLASH ((HT_FLASH_TypeDef *) HT_FLASH_BASE) +#define HT_GPIOA ((HT_GPIO_TypeDef *) HT_GPIOA_BASE) +#define HT_GPIOB ((HT_GPIO_TypeDef *) HT_GPIOB_BASE) +#define HT_GPIOC ((HT_GPIO_TypeDef *) HT_GPIOC_BASE) +#define HT_GPIOD ((HT_GPIO_TypeDef *) HT_GPIOD_BASE) +#define HT_GPTM0 ((HT_TM_TypeDef *) HT_GPTM0_BASE) +#define HT_I2C0 ((HT_I2C_TypeDef *) HT_I2C0_BASE) +#define HT_PDMA ((HT_PDMA_TypeDef *) HT_PDMA_BASE) +#define HT_PWRCU ((HT_PWRCU_TypeDef *) HT_PWRCU_BASE) +#define HT_RSTCU ((HT_RSTCU_TypeDef *) HT_RSTCU_BASE) +#define HT_RTC ((HT_RTC_TypeDef *) HT_RTC_BASE) +#define HT_SPI0 ((HT_SPI_TypeDef *) HT_SPI0_BASE) +#define HT_UART0 ((HT_USART_TypeDef *) HT_UART0_BASE) +#define HT_USART0 ((HT_USART_TypeDef *) HT_USART0_BASE) +#define HT_USB ((HT_USB_TypeDef *) HT_USB_BASE) +#define HT_USBEP0 ((HT_USBEP_TypeDef *) HT_USB_EP0_BASE) +#define HT_USBEP1 ((HT_USBEP_TypeDef *) HT_USB_EP1_BASE) +#define HT_USBEP2 ((HT_USBEP_TypeDef *) HT_USB_EP2_BASE) +#define HT_USBEP3 ((HT_USBEP_TypeDef *) HT_USB_EP3_BASE) +#define HT_USBEP4 ((HT_USBEP_TypeDef *) HT_USB_EP4_BASE) +#define HT_USBEP5 ((HT_USBEP_TypeDef *) HT_USB_EP5_BASE) +#define HT_USBEP6 ((HT_USBEP_TypeDef *) HT_USB_EP6_BASE) +#define HT_USBEP7 ((HT_USBEP_TypeDef *) HT_USB_EP7_BASE) +#define HT_WDT ((HT_WDT_TypeDef *) HT_WDT_BASE) + + +#if defined(USE_HT32F1655_56) +#define HT_USART1 ((HT_USART_TypeDef *) HT_USART1_BASE) +#define HT_UART1 ((HT_USART_TypeDef *) HT_UART1_BASE) +#define HT_SPI1 ((HT_SPI_TypeDef *) HT_SPI1_BASE) +#define HT_I2C1 ((HT_I2C_TypeDef *) HT_I2C1_BASE) +#define HT_CMP_OP0 ((HT_CMP_OP_TypeDef *) HT_CMP_OP0_BASE) +#define HT_CMP_OP1 ((HT_CMP_OP_TypeDef *) HT_CMP_OP1_BASE) +#define HT_I2S ((HT_I2S_TypeDef *) HT_I2S_BASE) +#define HT_MCTM0 ((HT_TM_TypeDef *) HT_MCTM0_BASE) +#define HT_MCTM1 ((HT_TM_TypeDef *) HT_MCTM1_BASE) +#define HT_GPTM1 ((HT_TM_TypeDef *) HT_GPTM1_BASE) +#define HT_SCI0 ((HT_SCI_TypeDef *) HT_SCI0_BASE) +#define HT_EBI ((HT_EBI_TypeDef *) HT_EBI_BASE) +#define HT_GPIOE ((HT_GPIO_TypeDef *) HT_GPIOE_BASE) +#endif + +#if defined(USE_HT32F1653_54) +#define HT_USART1 ((HT_USART_TypeDef *) HT_USART1_BASE) +#define HT_UART1 ((HT_USART_TypeDef *) HT_UART1_BASE) +#define HT_SPI1 ((HT_SPI_TypeDef *) HT_SPI1_BASE) +#define HT_I2C1 ((HT_I2C_TypeDef *) HT_I2C1_BASE) +#define HT_CMP0 ((HT_CMP_TypeDef *) HT_CMP0_BASE) +#define HT_CMP1 ((HT_CMP_TypeDef *) HT_CMP1_BASE) +#define HT_I2S ((HT_I2S_TypeDef *) HT_I2S_BASE) +#define HT_MCTM0 ((HT_TM_TypeDef *) HT_MCTM0_BASE) +#define HT_MCTM1 ((HT_TM_TypeDef *) HT_MCTM1_BASE) +#define HT_GPTM1 ((HT_TM_TypeDef *) HT_GPTM1_BASE) +#define HT_SCI0 ((HT_SCI_TypeDef *) HT_SCI0_BASE) +#define HT_EBI ((HT_EBI_TypeDef *) HT_EBI_BASE) +#endif + +#if defined(USE_HT32F12365_66) +#define HT_USART1 ((HT_USART_TypeDef *) HT_USART1_BASE) +#define HT_UART1 ((HT_USART_TypeDef *) HT_UART1_BASE) +#define HT_SPI1 ((HT_SPI_TypeDef *) HT_SPI1_BASE) +#define HT_I2C1 ((HT_I2C_TypeDef *) HT_I2C1_BASE) +#define HT_CMP0 ((HT_CMP_TypeDef *) HT_CMP0_BASE) +#define HT_CMP1 ((HT_CMP_TypeDef *) HT_CMP1_BASE) +#define HT_I2S ((HT_I2S_TypeDef *) HT_I2S_BASE) +#define HT_MCTM0 ((HT_TM_TypeDef *) HT_MCTM0_BASE) +#define HT_MCTM1 ((HT_TM_TypeDef *) HT_MCTM1_BASE) +#define HT_GPTM1 ((HT_TM_TypeDef *) HT_GPTM1_BASE) +#define HT_SCI0 ((HT_SCI_TypeDef *) HT_SCI0_BASE) +#define HT_SCI1 ((HT_SCI_TypeDef *) HT_SCI1_BASE) +#define HT_EBI ((HT_EBI_TypeDef *) HT_EBI_BASE) +#define HT_GPIOE ((HT_GPIO_TypeDef *) HT_GPIOE_BASE) +#define HT_SDIO ((HT_SDIO_TypeDef *) HT_SDIO_BASE) +#define HT_AES ((HT_AES_TypeDef *) HT_AES_BASE) +#define HT_CSIF ((HT_CSIF_TypeDef *) HT_CSIF_BASE) +#endif + +#if defined(USE_HT32F12345) +#define HT_USART1 ((HT_USART_TypeDef *) HT_USART1_BASE) +#define HT_UART1 ((HT_USART_TypeDef *) HT_UART1_BASE) +#define HT_SPI1 ((HT_SPI_TypeDef *) HT_SPI1_BASE) +#define HT_I2C1 ((HT_I2C_TypeDef *) HT_I2C1_BASE) +#define HT_CMP0 ((HT_CMP_TypeDef *) HT_CMP0_BASE) +#define HT_CMP1 ((HT_CMP_TypeDef *) HT_CMP1_BASE) +#define HT_I2S ((HT_I2S_TypeDef *) HT_I2S_BASE) +#define HT_MCTM0 ((HT_TM_TypeDef *) HT_MCTM0_BASE) +#define HT_MCTM1 ((HT_TM_TypeDef *) HT_MCTM1_BASE) +#define HT_GPTM1 ((HT_TM_TypeDef *) HT_GPTM1_BASE) +#define HT_EBI ((HT_EBI_TypeDef *) HT_EBI_BASE) +#define HT_SDIO ((HT_SDIO_TypeDef *) HT_SDIO_BASE) +#endif + +#if defined(USE_HT32F12364) +#define HT_UART1 ((HT_USART_TypeDef *) HT_UART1_BASE) +#define HT_SPI1 ((HT_SPI_TypeDef *) HT_SPI1_BASE) +#define HT_I2C1 ((HT_I2C_TypeDef *) HT_I2C1_BASE) +#define HT_SCI0 ((HT_SCI_TypeDef *) HT_SCI0_BASE) +#define HT_EBI ((HT_EBI_TypeDef *) HT_EBI_BASE) +#define HT_GPIOF ((HT_GPIO_TypeDef *) HT_GPIOF_BASE) +#define HT_AES ((HT_AES_TypeDef *) HT_AES_BASE) +#define HT_PWM0 ((HT_TM_TypeDef *) HT_PWM0_BASE) +#define HT_SCTM0 ((HT_TM_TypeDef *) HT_SCTM0_BASE) +#define HT_SCTM1 ((HT_TM_TypeDef *) HT_SCTM1_BASE) +#endif + +#if defined USE_HT32_DRIVER + #include "ht32f1xxxx_lib.h" +#endif + +/** + * @brief Adjust the value of High Speed External oscillator (HSE) + Tip: To avoid from modifying every time for different HSE, please define + the "HSE_VALUE=n000000" ("n" represents n MHz) in your own toolchain compiler preprocessor, + or edit the "HSE_VALUE" in the "ht32f1xxxx_conf.h" file. + */ +#if !defined HSE_VALUE + /* Available HSE_VALUE: 4 MHz ~ 16 MHz */ + #define HSE_VALUE 8000000UL /*!< Value of the External oscillator in Hz */ +#endif + +/** + * @brief Define for backward compatibility + */ +#define HT_ADC HT_ADC0 +#define ADC ADC0 +#define ADC_IRQn ADC0_IRQn + + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif + + +/** + * @} + */ + +/** + * @} + */ + +/******************* (C) COPYRIGHT Holtek Semiconductor Inc. *****END OF FILE*** */ diff --git a/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/Device/Holtek/HT32F1xxxx/Include/system_ht32f1xxxx_01.h b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/Device/Holtek/HT32F1xxxx/Include/system_ht32f1xxxx_01.h new file mode 100644 index 0000000000..bdba227af0 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/Device/Holtek/HT32F1xxxx/Include/system_ht32f1xxxx_01.h @@ -0,0 +1,74 @@ +/**************************************************************************//** + * @file system_ht32f1xxxx_01.h + * @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Header File + * for the Holtek HT32F1xxxx Device Series + * @version $Rev:: 735 $ + * @date $Date:: 2017-08-24 #$ + * + * @note + * Copyright (C) Holtek Semiconductor Inc. All rights reserved. + * + * @par + * ARM Limited (ARM) supplies this software for use with Cortex-M processor-based + * microcontrollers. This file can be freely distributed within development + * tools that are supporting such ARM based processors. + * + * @par + * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR + * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + ******************************************************************************/ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup HT32F1xxxx_system + * @{ + */ + + +#ifndef __SYSTEM_HT32F1XXXX_01_H +#define __SYSTEM_HT32F1XXXX_01_H + +#ifdef __cplusplus + extern "C" { +#endif + +/** @addtogroup HT32F1xxxx_System_Exported_types + * @{ + */ +extern __IO uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ +/** + * @} + */ + + +/** @addtogroup HT32F1xxxx_System_Exported_Functions + * @{ + */ +extern void SystemInit(void); +extern void SystemCoreClockUpdate(void); +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif + + +/** + * @} + */ + +/** + * @} + */ + +/******************* (C) COPYRIGHT Holtek Semiconductor Inc. *****END OF FILE*** */ diff --git a/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/Device/Holtek/HT32F1xxxx/Include/system_ht32f1xxxx_02.h b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/Device/Holtek/HT32F1xxxx/Include/system_ht32f1xxxx_02.h new file mode 100644 index 0000000000..ea20c74d67 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/Device/Holtek/HT32F1xxxx/Include/system_ht32f1xxxx_02.h @@ -0,0 +1,74 @@ +/**************************************************************************//** + * @file system_ht32f1xxxx_02.h + * @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Header File + * for the Holtek HT32F1xxxx Device Series + * @version $Rev:: 735 $ + * @date $Date:: 2017-08-24 #$ + * + * @note + * Copyright (C) Holtek Semiconductor Inc. All rights reserved. + * + * @par + * ARM Limited (ARM) supplies this software for use with Cortex-M processor-based + * microcontrollers. This file can be freely distributed within development + * tools that are supporting such ARM based processors. + * + * @par + * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR + * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + ******************************************************************************/ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup HT32F1xxxx_system + * @{ + */ + + +#ifndef __SYSTEM_HT32F1XXXX_02_H +#define __SYSTEM_HT32F1XXXX_02_H + +#ifdef __cplusplus + extern "C" { +#endif + +/** @addtogroup HT32F1xxxx_System_Exported_types + * @{ + */ +extern __IO uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ +/** + * @} + */ + + +/** @addtogroup HT32F1xxxx_System_Exported_Functions + * @{ + */ +extern void SystemInit(void); +extern void SystemCoreClockUpdate(void); +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif + + +/** + * @} + */ + +/** + * @} + */ + +/******************* (C) COPYRIGHT Holtek Semiconductor Inc. *****END OF FILE*** */ diff --git a/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/Device/Holtek/HT32F1xxxx/Include/system_ht32f1xxxx_03.h b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/Device/Holtek/HT32F1xxxx/Include/system_ht32f1xxxx_03.h new file mode 100644 index 0000000000..214d0008f7 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/Device/Holtek/HT32F1xxxx/Include/system_ht32f1xxxx_03.h @@ -0,0 +1,74 @@ +/**************************************************************************//** + * @file system_ht32f1xxxx_03.h + * @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Header File + * for the Holtek HT32F1xxxx Device Series + * @version $Rev:: 735 $ + * @date $Date:: 2019-06-12 #$ + * + * @note + * Copyright (C) Holtek Semiconductor Inc. All rights reserved. + * + * @par + * ARM Limited (ARM) supplies this software for use with Cortex-M processor-based + * microcontrollers. This file can be freely distributed within development + * tools that are supporting such ARM based processors. + * + * @par + * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR + * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + ******************************************************************************/ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup HT32F1xxxx_system + * @{ + */ + + +#ifndef __system_ht32f1xxxx_03_H +#define __system_ht32f1xxxx_03_H + +#ifdef __cplusplus + extern "C" { +#endif + +/** @addtogroup HT32F1xxxx_System_Exported_types + * @{ + */ +extern __IO uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ +/** + * @} + */ + + +/** @addtogroup HT32F1xxxx_System_Exported_Functions + * @{ + */ +extern void SystemInit(void); +extern void SystemCoreClockUpdate(void); +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif + + +/** + * @} + */ + +/** + * @} + */ + +/******************* (C) COPYRIGHT Holtek Semiconductor Inc. *****END OF FILE*** */ diff --git a/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/Device/Holtek/HT32F1xxxx/Source/ARM/startup_ht32f12345.s b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/Device/Holtek/HT32F1xxxx/Source/ARM/startup_ht32f12345.s new file mode 100644 index 0000000000..f3f24a1faf --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/Device/Holtek/HT32F1xxxx/Source/ARM/startup_ht32f12345.s @@ -0,0 +1,469 @@ +;/*---------------------------------------------------------------------------------------------------------*/ +;/* Holtek Semiconductor Inc. */ +;/* */ +;/* Copyright (C) Holtek Semiconductor Inc. */ +;/* All rights reserved. */ +;/* */ +;/*----------------------------------------------------------------------------------------------------------- +; File Name : startup_ht32f1xxxx_01.s +; Version : $Rev:: 2524 $ +; Date : $Date:: 2022-02-17 #$ +; Description : Startup code. +;-----------------------------------------------------------------------------------------------------------*/ + +; Supported Device +; ======================================== +; HT32F1653, HT32F1654 +; HT32F1655, HT32F1656 +; HT32F12365, HT32F12366 +; HT32F12345 + +;/* <<< Use Configuration Wizard in Context Menu >>> */ + +;// HT32 Device +;// Select HT32 Device for the assembly setting. +;// Notice that the project's Asm Define has the higher priority. +;// <0=> By Project Asm Define +;// <1=> HT32F1653/1654/1655/1656 +;// <2=> HT32F12365/12366 +;// <3=> HT32F12345 +USE_HT32_CHIP_SET EQU 3 ; Notice that the project's Asm Define has the higher priority. + +_HT32FWID EQU 0xFFFFFFFF +;_HT32FWID EQU 0x00012366 + +HT32F1653_54_55_56 EQU 1 +HT32F12365_66 EQU 2 +HT32F12345 EQU 3 + + IF USE_HT32_CHIP_SET=0 + ; Use project's Asm Define setting (default) + ELSE + IF :DEF:USE_HT32_CHIP + ; Use project's Asm Define setting (higher priority than the "USE_HT32_CHIP_SET") + ELSE + ; Use "USE_HT32_CHIP_SET" in the "startup_ht32xxxxx_xx.s" file +USE_HT32_CHIP EQU USE_HT32_CHIP_SET + ENDIF + ENDIF + +; Amount of memory (in bytes) allocated for Stack and Heap +; Tailor those values to your application needs +;// Stack Size (in Bytes, must 8 byte aligned) <0-131072:8> +Stack_Size EQU 512 + + AREA STACK, NOINIT, READWRITE, ALIGN = 3 +__HT_check_sp +Stack_Mem SPACE Stack_Size +__initial_sp + +;// Heap Size (in Bytes) <0-131072:8> +Heap_Size EQU 0 + + AREA HEAP, NOINIT, READWRITE, ALIGN = 3 +__HT_check_heap +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + PRESERVE8 + THUMB + +;******************************************************************************* +; Fill-up the Vector Table entries with the exceptions ISR address +;******************************************************************************* + AREA RESET, CODE, READONLY + EXPORT __Vectors +_RESERVED EQU 0xFFFFFFFF +__Vectors + DCD __initial_sp ; ---, 00, 0x000, Top address of Stack + DCD Reset_Handler ; ---, 01, 0x004, Reset Handler + DCD NMI_Handler ; ---, 02, 0x008, NMI Handler + DCD HardFault_Handler ; ---, 03, 0x00C, Hard Fault Handler + DCD MemManage_Handler ; ---, 04, 0x010, Memory Management Fault Handler + DCD BusFault_Handler ; ---, 05, 0x014, Bus Fault Handler + DCD UsageFault_Handler ; ---, 06, 0x018, Usage Fault Handler + DCD _RESERVED ; ---, 07, 0x01C, Reserved + DCD _HT32FWID ; ---, 08, 0x020, Reserved + DCD _RESERVED ; ---, 09, 0x024, Reserved + DCD _RESERVED ; ---, 10, 0x028, Reserved + DCD SVC_Handler ; ---, 11, 0x02C, SVC Handler + DCD DebugMon_Handler ; ---, 12, 0x030, Debug Monitor Handler + DCD _RESERVED ; ---, 13, 0x034, Reserved + DCD PendSV_Handler ; ---, 14, 0x038, PendSV Handler + DCD SysTick_Handler ; ---, 15, 0x03C, SysTick Handler + + ; External Interrupt Handler + DCD CKRDY_IRQHandler ; 00, 16, 0x040, + DCD LVD_IRQHandler ; 01, 17, 0x044, + DCD BOD_IRQHandler ; 02, 18, 0x048, + IF (USE_HT32_CHIP=HT32F1653_54_55_56) + DCD WDT_IRQHandler ; 03, 19, 0x04C, + ELSE + DCD _RESERVED ; 03, 19, 0x04C, + ENDIF + DCD RTC_IRQHandler ; 04, 20, 0x050, + DCD FLASH_IRQHandler ; 05, 21, 0x054, + DCD EVWUP_IRQHandler ; 06, 22, 0x058, + DCD LPWUP_IRQHandler ; 07, 23, 0x05C, + DCD EXTI0_IRQHandler ; 08, 24, 0x060, + DCD EXTI1_IRQHandler ; 09, 25, 0x064, + DCD EXTI2_IRQHandler ; 10, 26, 0x068, + DCD EXTI3_IRQHandler ; 11, 27, 0x06C, + DCD EXTI4_IRQHandler ; 12, 28, 0x070, + DCD EXTI5_IRQHandler ; 13, 29, 0x074, + DCD EXTI6_IRQHandler ; 14, 30, 0x078, + DCD EXTI7_IRQHandler ; 15, 31, 0x07C, + DCD EXTI8_IRQHandler ; 16, 32, 0x080, + DCD EXTI9_IRQHandler ; 17, 33, 0x084, + DCD EXTI10_IRQHandler ; 18, 34, 0x088, + DCD EXTI11_IRQHandler ; 19, 35, 0x08C, + DCD EXTI12_IRQHandler ; 20, 36, 0x090, + DCD EXTI13_IRQHandler ; 21, 37, 0x094, + DCD EXTI14_IRQHandler ; 22, 38, 0x098, + DCD EXTI15_IRQHandler ; 23, 39, 0x09C, + DCD COMP_IRQHandler ; 24, 40, 0x0A0, + DCD ADC_IRQHandler ; 25, 41, 0x0A4, + DCD _RESERVED ; 26, 42, 0x0A8, + DCD MCTM0BRK_IRQHandler ; 27, 43, 0x0AC, + DCD MCTM0UP_IRQHandler ; 28, 44, 0x0B0, + DCD MCTM0TR_IRQHandler ; 29, 45, 0x0B4, + DCD MCTM0CC_IRQHandler ; 30, 46, 0x0B8, + DCD MCTM1BRK_IRQHandler ; 31, 47, 0x0BC, + DCD MCTM1UP_IRQHandler ; 32, 48, 0x0C0, + DCD MCTM1TR_IRQHandler ; 33, 49, 0x0C4, + DCD MCTM1CC_IRQHandler ; 34, 50, 0x0C8, + DCD GPTM0_IRQHandler ; 35, 51, 0x0CC, + DCD GPTM1_IRQHandler ; 36, 52, 0x0D0, + DCD _RESERVED ; 37, 53, 0x0D4, + DCD _RESERVED ; 38, 54, 0x0D8, + DCD _RESERVED ; 39, 55, 0x0DC, + DCD _RESERVED ; 40, 56, 0x0E0, + DCD BFTM0_IRQHandler ; 41, 57, 0x0E4, + DCD BFTM1_IRQHandler ; 42, 58, 0x0E8, + DCD I2C0_IRQHandler ; 43, 59, 0x0EC, + DCD I2C1_IRQHandler ; 44, 60, 0x0F0, + DCD SPI0_IRQHandler ; 45, 61, 0x0F4, + DCD SPI1_IRQHandler ; 46, 62, 0x0F8, + DCD USART0_IRQHandler ; 47, 63, 0x0FC, + DCD USART1_IRQHandler ; 48, 64, 0x100, + DCD UART0_IRQHandler ; 49, 65, 0x104, + DCD UART1_IRQHandler ; 50, 66, 0x108, + IF (USE_HT32_CHIP=HT32F12345) + DCD _RESERVED ; 51, 67, 0x10C, + ELSE + DCD SCI_IRQHandler ; 51, 67, 0x10C, + ENDIF + DCD I2S_IRQHandler ; 52, 68, 0x110, + DCD USB_IRQHandler ; 53, 69, 0x114, + IF (USE_HT32_CHIP=HT32F1653_54_55_56) + DCD _RESERVED ; 54, 70, 0x118, + ELSE + DCD SDIO_IRQHandler ; 54, 70, 0x118, + ENDIF + DCD PDMA_CH0_IRQHandler ; 55, 71, 0x11C, + DCD PDMA_CH1_IRQHandler ; 56, 72, 0x120, + DCD PDMA_CH2_IRQHandler ; 57, 73, 0x124, + DCD PDMA_CH3_IRQHandler ; 58, 74, 0x128, + DCD PDMA_CH4_IRQHandler ; 59, 75, 0x12C, + DCD PDMA_CH5_IRQHandler ; 60, 76, 0x130, + DCD PDMA_CH6_IRQHandler ; 61, 77, 0x134, + DCD PDMA_CH7_IRQHandler ; 62, 78, 0x138, + IF (USE_HT32_CHIP=HT32F1653_54_55_56) + DCD _RESERVED ; 63, 79, 0x13C, + DCD _RESERVED ; 64, 80, 0x140, + DCD _RESERVED ; 65, 81, 0x144, + DCD _RESERVED ; 66, 82, 0x148, + ELSE + DCD PDMA_CH8_IRQHandler ; 63, 79, 0x13C, + DCD PDMA_CH9_IRQHandler ; 64, 80, 0x140, + DCD PDMA_CH10_IRQHandler ; 65, 81, 0x144, + DCD PDMA_CH11_IRQHandler ; 66, 82, 0x148, + ENDIF + IF (USE_HT32_CHIP=HT32F12365_66) + DCD CSIF_IRQHandler ; 67, 83, 0x14C, + ELSE + DCD _RESERVED ; 67, 83, 0x14C, + ENDIF + DCD EBI_IRQHandler ; 68, 84, 0x150, + IF (USE_HT32_CHIP=HT32F12365_66) + DCD AES_IRQHandler ; 69, 85, 0x154, + ENDIF + +; Reset handler routine +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + IF (USE_HT32_CHIP=HT32F1653_54_55_56) + ELSE + LDR R0, =BootProcess + BLX R0 + ENDIF + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + + IF (USE_HT32_CHIP=HT32F1653_54_55_56) + ELSE +BootProcess PROC + LDR R0, =0x40080300 + LDR R1,[R0, #0x10] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x14] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x18] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x1C] + CMP R1, #0 + BEQ BP2 +BP1 LDR R0, =0x40080180 + LDR R1,[R0, #0xC] + LSLS R1, R1, #4 + LSRS R1, R1, #20 + CMP R1, #0 + BEQ BP3 + CMP R1, #1 + BEQ BP3 + CMP R1, #2 + BEQ BP3 +BP2 DSB + LDR R0, =0x20000000 + LDR R1, =0x05fa0004 + STR R1, [R0] + LDR R1, =0xe000ed00 + LDR R0, =0x05fa0004 + STR R0, [R1, #0xC] + DSB + B . +BP3 LDR R0, =0x20000000 + LDR R1, [R0] + LDR R0, =0x05fa0004 + CMP R0, R1 + BEQ BP4 + BX LR +BP4 LDR R0, =0x40088100 + LDR R1, =0x00000001 + STR R1, [R0] + LDR R0, =0x20000000 + LDR R1, =0x0 + STR R1, [R0] + BX LR + ENDP + ENDIF + +; Dummy Exception Handlers +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP + +HardFault_Handler PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP + +MemManage_Handler PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP + +BusFault_Handler PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP + +UsageFault_Handler PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP + +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP + +DebugMon_Handler PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP + +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP + +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + EXPORT CKRDY_IRQHandler [WEAK] + EXPORT LVD_IRQHandler [WEAK] + EXPORT BOD_IRQHandler [WEAK] + EXPORT WDT_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT EVWUP_IRQHandler [WEAK] + EXPORT LPWUP_IRQHandler [WEAK] + EXPORT EXTI0_IRQHandler [WEAK] + EXPORT EXTI1_IRQHandler [WEAK] + EXPORT EXTI2_IRQHandler [WEAK] + EXPORT EXTI3_IRQHandler [WEAK] + EXPORT EXTI4_IRQHandler [WEAK] + EXPORT EXTI5_IRQHandler [WEAK] + EXPORT EXTI6_IRQHandler [WEAK] + EXPORT EXTI7_IRQHandler [WEAK] + EXPORT EXTI8_IRQHandler [WEAK] + EXPORT EXTI9_IRQHandler [WEAK] + EXPORT EXTI10_IRQHandler [WEAK] + EXPORT EXTI11_IRQHandler [WEAK] + EXPORT EXTI12_IRQHandler [WEAK] + EXPORT EXTI13_IRQHandler [WEAK] + EXPORT EXTI14_IRQHandler [WEAK] + EXPORT EXTI15_IRQHandler [WEAK] + EXPORT COMP_IRQHandler [WEAK] + EXPORT ADC_IRQHandler [WEAK] + EXPORT MCTM0BRK_IRQHandler [WEAK] + EXPORT MCTM0UP_IRQHandler [WEAK] + EXPORT MCTM0TR_IRQHandler [WEAK] + EXPORT MCTM0CC_IRQHandler [WEAK] + EXPORT MCTM1BRK_IRQHandler [WEAK] + EXPORT MCTM1UP_IRQHandler [WEAK] + EXPORT MCTM1TR_IRQHandler [WEAK] + EXPORT MCTM1CC_IRQHandler [WEAK] + EXPORT GPTM0_IRQHandler [WEAK] + EXPORT GPTM1_IRQHandler [WEAK] + EXPORT BFTM0_IRQHandler [WEAK] + EXPORT BFTM1_IRQHandler [WEAK] + EXPORT I2C0_IRQHandler [WEAK] + EXPORT I2C1_IRQHandler [WEAK] + EXPORT SPI0_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT USART0_IRQHandler [WEAK] + EXPORT USART1_IRQHandler [WEAK] + EXPORT UART0_IRQHandler [WEAK] + EXPORT UART1_IRQHandler [WEAK] + EXPORT SCI_IRQHandler [WEAK] + EXPORT I2S_IRQHandler [WEAK] + EXPORT USB_IRQHandler [WEAK] + EXPORT SDIO_IRQHandler [WEAK] + EXPORT PDMA_CH0_IRQHandler [WEAK] + EXPORT PDMA_CH1_IRQHandler [WEAK] + EXPORT PDMA_CH2_IRQHandler [WEAK] + EXPORT PDMA_CH3_IRQHandler [WEAK] + EXPORT PDMA_CH4_IRQHandler [WEAK] + EXPORT PDMA_CH5_IRQHandler [WEAK] + EXPORT PDMA_CH6_IRQHandler [WEAK] + EXPORT PDMA_CH7_IRQHandler [WEAK] + EXPORT PDMA_CH8_IRQHandler [WEAK] + EXPORT PDMA_CH9_IRQHandler [WEAK] + EXPORT PDMA_CH10_IRQHandler [WEAK] + EXPORT PDMA_CH11_IRQHandler [WEAK] + EXPORT CSIF_IRQHandler [WEAK] + EXPORT EBI_IRQHandler [WEAK] + EXPORT AES_IRQHandler [WEAK] +CKRDY_IRQHandler +LVD_IRQHandler +BOD_IRQHandler +WDT_IRQHandler +RTC_IRQHandler +FLASH_IRQHandler +EVWUP_IRQHandler +LPWUP_IRQHandler +EXTI0_IRQHandler +EXTI1_IRQHandler +EXTI2_IRQHandler +EXTI3_IRQHandler +EXTI4_IRQHandler +EXTI5_IRQHandler +EXTI6_IRQHandler +EXTI7_IRQHandler +EXTI8_IRQHandler +EXTI9_IRQHandler +EXTI10_IRQHandler +EXTI11_IRQHandler +EXTI12_IRQHandler +EXTI13_IRQHandler +EXTI14_IRQHandler +EXTI15_IRQHandler +COMP_IRQHandler +ADC_IRQHandler +MCTM0BRK_IRQHandler +MCTM0UP_IRQHandler +MCTM0TR_IRQHandler +MCTM0CC_IRQHandler +MCTM1BRK_IRQHandler +MCTM1UP_IRQHandler +MCTM1TR_IRQHandler +MCTM1CC_IRQHandler +GPTM0_IRQHandler +GPTM1_IRQHandler +BFTM0_IRQHandler +BFTM1_IRQHandler +I2C0_IRQHandler +I2C1_IRQHandler +SPI0_IRQHandler +SPI1_IRQHandler +USART0_IRQHandler +USART1_IRQHandler +UART0_IRQHandler +UART1_IRQHandler +SCI_IRQHandler +I2S_IRQHandler +USB_IRQHandler +SDIO_IRQHandler +PDMA_CH0_IRQHandler +PDMA_CH1_IRQHandler +PDMA_CH2_IRQHandler +PDMA_CH3_IRQHandler +PDMA_CH4_IRQHandler +PDMA_CH5_IRQHandler +PDMA_CH6_IRQHandler +PDMA_CH7_IRQHandler +PDMA_CH8_IRQHandler +PDMA_CH9_IRQHandler +PDMA_CH10_IRQHandler +PDMA_CH11_IRQHandler +CSIF_IRQHandler +EBI_IRQHandler +AES_IRQHandler + B . + ENDP + + ALIGN + +;******************************************************************************* +; User Stack and Heap initialization +;******************************************************************************* + IF :DEF:__MICROLIB + + EXPORT __HT_check_heap + EXPORT __HT_check_sp + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, = (Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + + ENDIF + + END diff --git a/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/Device/Holtek/HT32F1xxxx/Source/ARM/startup_ht32f12364.s b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/Device/Holtek/HT32F1xxxx/Source/ARM/startup_ht32f12364.s new file mode 100644 index 0000000000..a1a24ab522 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/Device/Holtek/HT32F1xxxx/Source/ARM/startup_ht32f12364.s @@ -0,0 +1,393 @@ +;/*---------------------------------------------------------------------------------------------------------*/ +;/* Holtek Semiconductor Inc. */ +;/* */ +;/* Copyright (C) Holtek Semiconductor Inc. */ +;/* All rights reserved. */ +;/* */ +;/*----------------------------------------------------------------------------------------------------------- +; File Name : startup_ht32f1xxxx_03.s +; Version : $Rev:: 2524 $ +; Date : $Date:: 2022-02-17 #$ +; Description : Startup code. +;-----------------------------------------------------------------------------------------------------------*/ + +; Supported Device +; ======================================== +; HT32F12364 + +;/* <<< Use Configuration Wizard in Context Menu >>> */ + +;// HT32 Device +;// Select HT32 Device for the assembly setting. +;// Notice that the project's Asm Define has the higher priority. +;// <0=> By Project Asm Define +;// <16=> HT32F12364 +USE_HT32_CHIP_SET EQU 16 ; Notice that the project's Asm Define has the higher priority. + +_HT32FWID EQU 0xFFFFFFFF +;_HT32FWID EQU 0x00012364 + +HT32F12364 EQU 16 + + IF USE_HT32_CHIP_SET=0 + ; Use project's Asm Define setting (default) + ELSE + IF :DEF:USE_HT32_CHIP + ; Use project's Asm Define setting (higher priority than the "USE_HT32_CHIP_SET") + ELSE + ; Use "USE_HT32_CHIP_SET" in the "startup_ht32xxxxx_xx.s" file +USE_HT32_CHIP EQU USE_HT32_CHIP_SET + ENDIF + ENDIF + +; Amount of memory (in bytes) allocated for Stack and Heap +; Tailor those values to your application needs +;// Stack Size (in Bytes, must 8 byte aligned) <0-131072:8> +Stack_Size EQU 512 + + AREA STACK, NOINIT, READWRITE, ALIGN = 3 +__HT_check_sp +Stack_Mem SPACE Stack_Size +__initial_sp + +;// Heap Size (in Bytes) <0-131072:8> +Heap_Size EQU 0 + + AREA HEAP, NOINIT, READWRITE, ALIGN = 3 +__HT_check_heap +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + PRESERVE8 + THUMB + +;******************************************************************************* +; Fill-up the Vector Table entries with the exceptions ISR address +;******************************************************************************* + AREA RESET, CODE, READONLY + EXPORT __Vectors +_RESERVED EQU 0xFFFFFFFF +__Vectors + DCD __initial_sp ; ---, 00, 0x000, Top address of Stack + DCD Reset_Handler ; ---, 01, 0x004, Reset Handler + DCD NMI_Handler ; ---, 02, 0x008, NMI Handler + DCD HardFault_Handler ; ---, 03, 0x00C, Hard Fault Handler + DCD MemManage_Handler ; ---, 04, 0x010, Memory Management Fault Handler + DCD BusFault_Handler ; ---, 05, 0x014, Bus Fault Handler + DCD UsageFault_Handler ; ---, 06, 0x018, Usage Fault Handler + DCD _RESERVED ; ---, 07, 0x01C, Reserved + DCD _HT32FWID ; ---, 08, 0x020, Reserved + DCD _RESERVED ; ---, 09, 0x024, Reserved + DCD _RESERVED ; ---, 10, 0x028, Reserved + DCD SVC_Handler ; ---, 11, 0x02C, SVC Handler + DCD DebugMon_Handler ; ---, 12, 0x030, Debug Monitor Handler + DCD _RESERVED ; ---, 13, 0x034, Reserved + DCD PendSV_Handler ; ---, 14, 0x038, PendSV Handler + DCD SysTick_Handler ; ---, 15, 0x03C, SysTick Handler + + ; External Interrupt Handler + DCD CKRDY_IRQHandler ; 00, 16, 0x040, + DCD LVD_IRQHandler ; 01, 17, 0x044, + DCD BOD_IRQHandler ; 02, 18, 0x048, + DCD _RESERVED ; 03, 19, 0x04C, + DCD RTC_IRQHandler ; 04, 20, 0x050, + DCD FLASH_IRQHandler ; 05, 21, 0x054, + DCD EVWUP_IRQHandler ; 06, 22, 0x058, + DCD LPWUP_IRQHandler ; 07, 23, 0x05C, + DCD EXTI0_IRQHandler ; 08, 24, 0x060, + DCD EXTI1_IRQHandler ; 09, 25, 0x064, + DCD EXTI2_IRQHandler ; 10, 26, 0x068, + DCD EXTI3_IRQHandler ; 11, 27, 0x06C, + DCD EXTI4_IRQHandler ; 12, 28, 0x070, + DCD EXTI5_IRQHandler ; 13, 29, 0x074, + DCD EXTI6_IRQHandler ; 14, 30, 0x078, + DCD EXTI7_IRQHandler ; 15, 31, 0x07C, + DCD EXTI8_IRQHandler ; 16, 32, 0x080, + DCD EXTI9_IRQHandler ; 17, 33, 0x084, + DCD EXTI10_IRQHandler ; 18, 34, 0x088, + DCD EXTI11_IRQHandler ; 19, 35, 0x08C, + DCD EXTI12_IRQHandler ; 20, 36, 0x090, + DCD EXTI13_IRQHandler ; 21, 37, 0x094, + DCD EXTI14_IRQHandler ; 22, 38, 0x098, + DCD EXTI15_IRQHandler ; 23, 39, 0x09C, + DCD _RESERVED ; 24, 40, 0x0A0, + DCD ADC_IRQHandler ; 25, 41, 0x0A4, + DCD _RESERVED ; 26, 42, 0x0A8, + DCD _RESERVED ; 27, 43, 0x0AC, + DCD _RESERVED ; 28, 44, 0x0B0, + DCD _RESERVED ; 29, 45, 0x0B4, + DCD _RESERVED ; 30, 46, 0x0B8, + DCD _RESERVED ; 31, 47, 0x0BC, + DCD _RESERVED ; 32, 48, 0x0C0, + DCD _RESERVED ; 33, 49, 0x0C4, + DCD _RESERVED ; 34, 50, 0x0C8, + DCD GPTM0_IRQHandler ; 35, 51, 0x0CC, + DCD _RESERVED ; 36, 52, 0x0D0, + DCD SCTM0_IRQHandler ; 37, 53, 0x0D4, + DCD SCTM1_IRQHandler ; 38, 54, 0x0D8, + DCD PWM0_IRQHandler ; 39, 55, 0x0DC, + DCD _RESERVED ; 40, 56, 0x0E0, + DCD BFTM0_IRQHandler ; 41, 57, 0x0E4, + DCD BFTM1_IRQHandler ; 42, 58, 0x0E8, + DCD I2C0_IRQHandler ; 43, 59, 0x0EC, + DCD I2C1_IRQHandler ; 44, 60, 0x0F0, + DCD SPI0_IRQHandler ; 45, 61, 0x0F4, + DCD SPI1_IRQHandler ; 46, 62, 0x0F8, + DCD USART0_IRQHandler ; 47, 63, 0x0FC, + DCD _RESERVED ; 48, 64, 0x100, + DCD UART0_IRQHandler ; 49, 65, 0x104, + DCD UART1_IRQHandler ; 50, 66, 0x108, + DCD SCI_IRQHandler ; 51, 67, 0x10C, + DCD _RESERVED ; 52, 68, 0x110, + DCD USB_IRQHandler ; 53, 69, 0x114, + DCD _RESERVED ; 54, 70, 0x118, + DCD PDMA_CH0_IRQHandler ; 55, 71, 0x11C, + DCD PDMA_CH1_IRQHandler ; 56, 72, 0x120, + DCD PDMA_CH2_IRQHandler ; 57, 73, 0x124, + DCD PDMA_CH3_IRQHandler ; 58, 74, 0x128, + DCD PDMA_CH4_IRQHandler ; 59, 75, 0x12C, + DCD PDMA_CH5_IRQHandler ; 60, 76, 0x130, + DCD _RESERVED ; 61, 77, 0x134, + DCD _RESERVED ; 62, 78, 0x138, + DCD _RESERVED ; 63, 79, 0x13C, + DCD _RESERVED ; 64, 80, 0x140, + DCD _RESERVED ; 65, 81, 0x144, + DCD _RESERVED ; 66, 82, 0x148, + DCD _RESERVED ; 67, 83, 0x14C, + DCD _RESERVED ; 68, 84, 0x150, + DCD AES_IRQHandler ; 69, 85, 0x154, + +; Reset handler routine +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + LDR R0, =BootProcess + BLX R0 + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +BootProcess PROC + LDR R0, =0x40080300 + LDR R1,[R0, #0x10] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x14] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x18] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x1C] + CMP R1, #0 + BEQ BP2 +BP1 LDR R0, =0x40080180 + LDR R1,[R0, #0xC] + LSLS R1, R1, #4 + LSRS R1, R1, #20 + CMP R1, #0 + BEQ BP3 + CMP R1, #1 + BEQ BP3 + CMP R1, #2 + BEQ BP3 +BP2 DSB + LDR R0, =0x20000000 + LDR R1, =0x05fa0004 + STR R1, [R0] + LDR R1, =0xe000ed00 + LDR R0, =0x05fa0004 + STR R0, [R1, #0xC] + DSB + B . +BP3 LDR R0, =0x20000000 + LDR R1, [R0] + LDR R0, =0x05fa0004 + CMP R0, R1 + BEQ BP4 + BX LR +BP4 LDR R0, =0x40088100 + LDR R1, =0x00000001 + STR R1, [R0] + LDR R0, =0x20000000 + LDR R1, =0x0 + STR R1, [R0] + BX LR + ENDP + +; Dummy Exception Handlers +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP + +HardFault_Handler PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP + +MemManage_Handler PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP + +BusFault_Handler PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP + +UsageFault_Handler PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP + +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP + +DebugMon_Handler PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP + +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP + +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + EXPORT CKRDY_IRQHandler [WEAK] + EXPORT LVD_IRQHandler [WEAK] + EXPORT BOD_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT EVWUP_IRQHandler [WEAK] + EXPORT LPWUP_IRQHandler [WEAK] + EXPORT EXTI0_IRQHandler [WEAK] + EXPORT EXTI1_IRQHandler [WEAK] + EXPORT EXTI2_IRQHandler [WEAK] + EXPORT EXTI3_IRQHandler [WEAK] + EXPORT EXTI4_IRQHandler [WEAK] + EXPORT EXTI5_IRQHandler [WEAK] + EXPORT EXTI6_IRQHandler [WEAK] + EXPORT EXTI7_IRQHandler [WEAK] + EXPORT EXTI8_IRQHandler [WEAK] + EXPORT EXTI9_IRQHandler [WEAK] + EXPORT EXTI10_IRQHandler [WEAK] + EXPORT EXTI11_IRQHandler [WEAK] + EXPORT EXTI12_IRQHandler [WEAK] + EXPORT EXTI13_IRQHandler [WEAK] + EXPORT EXTI14_IRQHandler [WEAK] + EXPORT EXTI15_IRQHandler [WEAK] + EXPORT ADC_IRQHandler [WEAK] + EXPORT GPTM0_IRQHandler [WEAK] + EXPORT SCTM0_IRQHandler [WEAK] + EXPORT SCTM1_IRQHandler [WEAK] + EXPORT PWM0_IRQHandler [WEAK] + EXPORT BFTM0_IRQHandler [WEAK] + EXPORT BFTM1_IRQHandler [WEAK] + EXPORT I2C0_IRQHandler [WEAK] + EXPORT I2C1_IRQHandler [WEAK] + EXPORT SPI0_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT USART0_IRQHandler [WEAK] + EXPORT UART0_IRQHandler [WEAK] + EXPORT UART1_IRQHandler [WEAK] + EXPORT SCI_IRQHandler [WEAK] + EXPORT USB_IRQHandler [WEAK] + EXPORT PDMA_CH0_IRQHandler [WEAK] + EXPORT PDMA_CH1_IRQHandler [WEAK] + EXPORT PDMA_CH2_IRQHandler [WEAK] + EXPORT PDMA_CH3_IRQHandler [WEAK] + EXPORT PDMA_CH4_IRQHandler [WEAK] + EXPORT PDMA_CH5_IRQHandler [WEAK] + EXPORT AES_IRQHandler [WEAK] +CKRDY_IRQHandler +LVD_IRQHandler +BOD_IRQHandler +RTC_IRQHandler +FLASH_IRQHandler +EVWUP_IRQHandler +LPWUP_IRQHandler +EXTI0_IRQHandler +EXTI1_IRQHandler +EXTI2_IRQHandler +EXTI3_IRQHandler +EXTI4_IRQHandler +EXTI5_IRQHandler +EXTI6_IRQHandler +EXTI7_IRQHandler +EXTI8_IRQHandler +EXTI9_IRQHandler +EXTI10_IRQHandler +EXTI11_IRQHandler +EXTI12_IRQHandler +EXTI13_IRQHandler +EXTI14_IRQHandler +EXTI15_IRQHandler +ADC_IRQHandler +GPTM0_IRQHandler +SCTM0_IRQHandler +SCTM1_IRQHandler +PWM0_IRQHandler +BFTM0_IRQHandler +BFTM1_IRQHandler +I2C0_IRQHandler +I2C1_IRQHandler +SPI0_IRQHandler +SPI1_IRQHandler +USART0_IRQHandler +UART0_IRQHandler +UART1_IRQHandler +SCI_IRQHandler +USB_IRQHandler +PDMA_CH0_IRQHandler +PDMA_CH1_IRQHandler +PDMA_CH2_IRQHandler +PDMA_CH3_IRQHandler +PDMA_CH4_IRQHandler +PDMA_CH5_IRQHandler +AES_IRQHandler + B . + ENDP + + ALIGN + +;******************************************************************************* +; User Stack and Heap initialization +;******************************************************************************* + IF :DEF:__MICROLIB + + EXPORT __HT_check_heap + EXPORT __HT_check_sp + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, = (Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + + ENDIF + + END diff --git a/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/Device/Holtek/HT32F1xxxx/Source/ARM/startup_ht32f12365_66.s b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/Device/Holtek/HT32F1xxxx/Source/ARM/startup_ht32f12365_66.s new file mode 100644 index 0000000000..3381f58240 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/Device/Holtek/HT32F1xxxx/Source/ARM/startup_ht32f12365_66.s @@ -0,0 +1,469 @@ +;/*---------------------------------------------------------------------------------------------------------*/ +;/* Holtek Semiconductor Inc. */ +;/* */ +;/* Copyright (C) Holtek Semiconductor Inc. */ +;/* All rights reserved. */ +;/* */ +;/*----------------------------------------------------------------------------------------------------------- +; File Name : startup_ht32f1xxxx_01.s +; Version : $Rev:: 2524 $ +; Date : $Date:: 2022-02-17 #$ +; Description : Startup code. +;-----------------------------------------------------------------------------------------------------------*/ + +; Supported Device +; ======================================== +; HT32F1653, HT32F1654 +; HT32F1655, HT32F1656 +; HT32F12365, HT32F12366 +; HT32F12345 + +;/* <<< Use Configuration Wizard in Context Menu >>> */ + +;// HT32 Device +;// Select HT32 Device for the assembly setting. +;// Notice that the project's Asm Define has the higher priority. +;// <0=> By Project Asm Define +;// <1=> HT32F1653/1654/1655/1656 +;// <2=> HT32F12365/12366 +;// <3=> HT32F12345 +USE_HT32_CHIP_SET EQU 2 ; Notice that the project's Asm Define has the higher priority. + +_HT32FWID EQU 0xFFFFFFFF +;_HT32FWID EQU 0x00012366 + +HT32F1653_54_55_56 EQU 1 +HT32F12365_66 EQU 2 +HT32F12345 EQU 3 + + IF USE_HT32_CHIP_SET=0 + ; Use project's Asm Define setting (default) + ELSE + IF :DEF:USE_HT32_CHIP + ; Use project's Asm Define setting (higher priority than the "USE_HT32_CHIP_SET") + ELSE + ; Use "USE_HT32_CHIP_SET" in the "startup_ht32xxxxx_xx.s" file +USE_HT32_CHIP EQU USE_HT32_CHIP_SET + ENDIF + ENDIF + +; Amount of memory (in bytes) allocated for Stack and Heap +; Tailor those values to your application needs +;// Stack Size (in Bytes, must 8 byte aligned) <0-131072:8> +Stack_Size EQU 512 + + AREA STACK, NOINIT, READWRITE, ALIGN = 3 +__HT_check_sp +Stack_Mem SPACE Stack_Size +__initial_sp + +;// Heap Size (in Bytes) <0-131072:8> +Heap_Size EQU 0 + + AREA HEAP, NOINIT, READWRITE, ALIGN = 3 +__HT_check_heap +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + PRESERVE8 + THUMB + +;******************************************************************************* +; Fill-up the Vector Table entries with the exceptions ISR address +;******************************************************************************* + AREA RESET, CODE, READONLY + EXPORT __Vectors +_RESERVED EQU 0xFFFFFFFF +__Vectors + DCD __initial_sp ; ---, 00, 0x000, Top address of Stack + DCD Reset_Handler ; ---, 01, 0x004, Reset Handler + DCD NMI_Handler ; ---, 02, 0x008, NMI Handler + DCD HardFault_Handler ; ---, 03, 0x00C, Hard Fault Handler + DCD MemManage_Handler ; ---, 04, 0x010, Memory Management Fault Handler + DCD BusFault_Handler ; ---, 05, 0x014, Bus Fault Handler + DCD UsageFault_Handler ; ---, 06, 0x018, Usage Fault Handler + DCD _RESERVED ; ---, 07, 0x01C, Reserved + DCD _HT32FWID ; ---, 08, 0x020, Reserved + DCD _RESERVED ; ---, 09, 0x024, Reserved + DCD _RESERVED ; ---, 10, 0x028, Reserved + DCD SVC_Handler ; ---, 11, 0x02C, SVC Handler + DCD DebugMon_Handler ; ---, 12, 0x030, Debug Monitor Handler + DCD _RESERVED ; ---, 13, 0x034, Reserved + DCD PendSV_Handler ; ---, 14, 0x038, PendSV Handler + DCD SysTick_Handler ; ---, 15, 0x03C, SysTick Handler + + ; External Interrupt Handler + DCD CKRDY_IRQHandler ; 00, 16, 0x040, + DCD LVD_IRQHandler ; 01, 17, 0x044, + DCD BOD_IRQHandler ; 02, 18, 0x048, + IF (USE_HT32_CHIP=HT32F1653_54_55_56) + DCD WDT_IRQHandler ; 03, 19, 0x04C, + ELSE + DCD _RESERVED ; 03, 19, 0x04C, + ENDIF + DCD RTC_IRQHandler ; 04, 20, 0x050, + DCD FLASH_IRQHandler ; 05, 21, 0x054, + DCD EVWUP_IRQHandler ; 06, 22, 0x058, + DCD LPWUP_IRQHandler ; 07, 23, 0x05C, + DCD EXTI0_IRQHandler ; 08, 24, 0x060, + DCD EXTI1_IRQHandler ; 09, 25, 0x064, + DCD EXTI2_IRQHandler ; 10, 26, 0x068, + DCD EXTI3_IRQHandler ; 11, 27, 0x06C, + DCD EXTI4_IRQHandler ; 12, 28, 0x070, + DCD EXTI5_IRQHandler ; 13, 29, 0x074, + DCD EXTI6_IRQHandler ; 14, 30, 0x078, + DCD EXTI7_IRQHandler ; 15, 31, 0x07C, + DCD EXTI8_IRQHandler ; 16, 32, 0x080, + DCD EXTI9_IRQHandler ; 17, 33, 0x084, + DCD EXTI10_IRQHandler ; 18, 34, 0x088, + DCD EXTI11_IRQHandler ; 19, 35, 0x08C, + DCD EXTI12_IRQHandler ; 20, 36, 0x090, + DCD EXTI13_IRQHandler ; 21, 37, 0x094, + DCD EXTI14_IRQHandler ; 22, 38, 0x098, + DCD EXTI15_IRQHandler ; 23, 39, 0x09C, + DCD COMP_IRQHandler ; 24, 40, 0x0A0, + DCD ADC_IRQHandler ; 25, 41, 0x0A4, + DCD _RESERVED ; 26, 42, 0x0A8, + DCD MCTM0BRK_IRQHandler ; 27, 43, 0x0AC, + DCD MCTM0UP_IRQHandler ; 28, 44, 0x0B0, + DCD MCTM0TR_IRQHandler ; 29, 45, 0x0B4, + DCD MCTM0CC_IRQHandler ; 30, 46, 0x0B8, + DCD MCTM1BRK_IRQHandler ; 31, 47, 0x0BC, + DCD MCTM1UP_IRQHandler ; 32, 48, 0x0C0, + DCD MCTM1TR_IRQHandler ; 33, 49, 0x0C4, + DCD MCTM1CC_IRQHandler ; 34, 50, 0x0C8, + DCD GPTM0_IRQHandler ; 35, 51, 0x0CC, + DCD GPTM1_IRQHandler ; 36, 52, 0x0D0, + DCD _RESERVED ; 37, 53, 0x0D4, + DCD _RESERVED ; 38, 54, 0x0D8, + DCD _RESERVED ; 39, 55, 0x0DC, + DCD _RESERVED ; 40, 56, 0x0E0, + DCD BFTM0_IRQHandler ; 41, 57, 0x0E4, + DCD BFTM1_IRQHandler ; 42, 58, 0x0E8, + DCD I2C0_IRQHandler ; 43, 59, 0x0EC, + DCD I2C1_IRQHandler ; 44, 60, 0x0F0, + DCD SPI0_IRQHandler ; 45, 61, 0x0F4, + DCD SPI1_IRQHandler ; 46, 62, 0x0F8, + DCD USART0_IRQHandler ; 47, 63, 0x0FC, + DCD USART1_IRQHandler ; 48, 64, 0x100, + DCD UART0_IRQHandler ; 49, 65, 0x104, + DCD UART1_IRQHandler ; 50, 66, 0x108, + IF (USE_HT32_CHIP=HT32F12345) + DCD _RESERVED ; 51, 67, 0x10C, + ELSE + DCD SCI_IRQHandler ; 51, 67, 0x10C, + ENDIF + DCD I2S_IRQHandler ; 52, 68, 0x110, + DCD USB_IRQHandler ; 53, 69, 0x114, + IF (USE_HT32_CHIP=HT32F1653_54_55_56) + DCD _RESERVED ; 54, 70, 0x118, + ELSE + DCD SDIO_IRQHandler ; 54, 70, 0x118, + ENDIF + DCD PDMA_CH0_IRQHandler ; 55, 71, 0x11C, + DCD PDMA_CH1_IRQHandler ; 56, 72, 0x120, + DCD PDMA_CH2_IRQHandler ; 57, 73, 0x124, + DCD PDMA_CH3_IRQHandler ; 58, 74, 0x128, + DCD PDMA_CH4_IRQHandler ; 59, 75, 0x12C, + DCD PDMA_CH5_IRQHandler ; 60, 76, 0x130, + DCD PDMA_CH6_IRQHandler ; 61, 77, 0x134, + DCD PDMA_CH7_IRQHandler ; 62, 78, 0x138, + IF (USE_HT32_CHIP=HT32F1653_54_55_56) + DCD _RESERVED ; 63, 79, 0x13C, + DCD _RESERVED ; 64, 80, 0x140, + DCD _RESERVED ; 65, 81, 0x144, + DCD _RESERVED ; 66, 82, 0x148, + ELSE + DCD PDMA_CH8_IRQHandler ; 63, 79, 0x13C, + DCD PDMA_CH9_IRQHandler ; 64, 80, 0x140, + DCD PDMA_CH10_IRQHandler ; 65, 81, 0x144, + DCD PDMA_CH11_IRQHandler ; 66, 82, 0x148, + ENDIF + IF (USE_HT32_CHIP=HT32F12365_66) + DCD CSIF_IRQHandler ; 67, 83, 0x14C, + ELSE + DCD _RESERVED ; 67, 83, 0x14C, + ENDIF + DCD EBI_IRQHandler ; 68, 84, 0x150, + IF (USE_HT32_CHIP=HT32F12365_66) + DCD AES_IRQHandler ; 69, 85, 0x154, + ENDIF + +; Reset handler routine +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + IF (USE_HT32_CHIP=HT32F1653_54_55_56) + ELSE + LDR R0, =BootProcess + BLX R0 + ENDIF + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + + IF (USE_HT32_CHIP=HT32F1653_54_55_56) + ELSE +BootProcess PROC + LDR R0, =0x40080300 + LDR R1,[R0, #0x10] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x14] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x18] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x1C] + CMP R1, #0 + BEQ BP2 +BP1 LDR R0, =0x40080180 + LDR R1,[R0, #0xC] + LSLS R1, R1, #4 + LSRS R1, R1, #20 + CMP R1, #0 + BEQ BP3 + CMP R1, #1 + BEQ BP3 + CMP R1, #2 + BEQ BP3 +BP2 DSB + LDR R0, =0x20000000 + LDR R1, =0x05fa0004 + STR R1, [R0] + LDR R1, =0xe000ed00 + LDR R0, =0x05fa0004 + STR R0, [R1, #0xC] + DSB + B . +BP3 LDR R0, =0x20000000 + LDR R1, [R0] + LDR R0, =0x05fa0004 + CMP R0, R1 + BEQ BP4 + BX LR +BP4 LDR R0, =0x40088100 + LDR R1, =0x00000001 + STR R1, [R0] + LDR R0, =0x20000000 + LDR R1, =0x0 + STR R1, [R0] + BX LR + ENDP + ENDIF + +; Dummy Exception Handlers +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP + +HardFault_Handler PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP + +MemManage_Handler PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP + +BusFault_Handler PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP + +UsageFault_Handler PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP + +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP + +DebugMon_Handler PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP + +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP + +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + EXPORT CKRDY_IRQHandler [WEAK] + EXPORT LVD_IRQHandler [WEAK] + EXPORT BOD_IRQHandler [WEAK] + EXPORT WDT_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT EVWUP_IRQHandler [WEAK] + EXPORT LPWUP_IRQHandler [WEAK] + EXPORT EXTI0_IRQHandler [WEAK] + EXPORT EXTI1_IRQHandler [WEAK] + EXPORT EXTI2_IRQHandler [WEAK] + EXPORT EXTI3_IRQHandler [WEAK] + EXPORT EXTI4_IRQHandler [WEAK] + EXPORT EXTI5_IRQHandler [WEAK] + EXPORT EXTI6_IRQHandler [WEAK] + EXPORT EXTI7_IRQHandler [WEAK] + EXPORT EXTI8_IRQHandler [WEAK] + EXPORT EXTI9_IRQHandler [WEAK] + EXPORT EXTI10_IRQHandler [WEAK] + EXPORT EXTI11_IRQHandler [WEAK] + EXPORT EXTI12_IRQHandler [WEAK] + EXPORT EXTI13_IRQHandler [WEAK] + EXPORT EXTI14_IRQHandler [WEAK] + EXPORT EXTI15_IRQHandler [WEAK] + EXPORT COMP_IRQHandler [WEAK] + EXPORT ADC_IRQHandler [WEAK] + EXPORT MCTM0BRK_IRQHandler [WEAK] + EXPORT MCTM0UP_IRQHandler [WEAK] + EXPORT MCTM0TR_IRQHandler [WEAK] + EXPORT MCTM0CC_IRQHandler [WEAK] + EXPORT MCTM1BRK_IRQHandler [WEAK] + EXPORT MCTM1UP_IRQHandler [WEAK] + EXPORT MCTM1TR_IRQHandler [WEAK] + EXPORT MCTM1CC_IRQHandler [WEAK] + EXPORT GPTM0_IRQHandler [WEAK] + EXPORT GPTM1_IRQHandler [WEAK] + EXPORT BFTM0_IRQHandler [WEAK] + EXPORT BFTM1_IRQHandler [WEAK] + EXPORT I2C0_IRQHandler [WEAK] + EXPORT I2C1_IRQHandler [WEAK] + EXPORT SPI0_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT USART0_IRQHandler [WEAK] + EXPORT USART1_IRQHandler [WEAK] + EXPORT UART0_IRQHandler [WEAK] + EXPORT UART1_IRQHandler [WEAK] + EXPORT SCI_IRQHandler [WEAK] + EXPORT I2S_IRQHandler [WEAK] + EXPORT USB_IRQHandler [WEAK] + EXPORT SDIO_IRQHandler [WEAK] + EXPORT PDMA_CH0_IRQHandler [WEAK] + EXPORT PDMA_CH1_IRQHandler [WEAK] + EXPORT PDMA_CH2_IRQHandler [WEAK] + EXPORT PDMA_CH3_IRQHandler [WEAK] + EXPORT PDMA_CH4_IRQHandler [WEAK] + EXPORT PDMA_CH5_IRQHandler [WEAK] + EXPORT PDMA_CH6_IRQHandler [WEAK] + EXPORT PDMA_CH7_IRQHandler [WEAK] + EXPORT PDMA_CH8_IRQHandler [WEAK] + EXPORT PDMA_CH9_IRQHandler [WEAK] + EXPORT PDMA_CH10_IRQHandler [WEAK] + EXPORT PDMA_CH11_IRQHandler [WEAK] + EXPORT CSIF_IRQHandler [WEAK] + EXPORT EBI_IRQHandler [WEAK] + EXPORT AES_IRQHandler [WEAK] +CKRDY_IRQHandler +LVD_IRQHandler +BOD_IRQHandler +WDT_IRQHandler +RTC_IRQHandler +FLASH_IRQHandler +EVWUP_IRQHandler +LPWUP_IRQHandler +EXTI0_IRQHandler +EXTI1_IRQHandler +EXTI2_IRQHandler +EXTI3_IRQHandler +EXTI4_IRQHandler +EXTI5_IRQHandler +EXTI6_IRQHandler +EXTI7_IRQHandler +EXTI8_IRQHandler +EXTI9_IRQHandler +EXTI10_IRQHandler +EXTI11_IRQHandler +EXTI12_IRQHandler +EXTI13_IRQHandler +EXTI14_IRQHandler +EXTI15_IRQHandler +COMP_IRQHandler +ADC_IRQHandler +MCTM0BRK_IRQHandler +MCTM0UP_IRQHandler +MCTM0TR_IRQHandler +MCTM0CC_IRQHandler +MCTM1BRK_IRQHandler +MCTM1UP_IRQHandler +MCTM1TR_IRQHandler +MCTM1CC_IRQHandler +GPTM0_IRQHandler +GPTM1_IRQHandler +BFTM0_IRQHandler +BFTM1_IRQHandler +I2C0_IRQHandler +I2C1_IRQHandler +SPI0_IRQHandler +SPI1_IRQHandler +USART0_IRQHandler +USART1_IRQHandler +UART0_IRQHandler +UART1_IRQHandler +SCI_IRQHandler +I2S_IRQHandler +USB_IRQHandler +SDIO_IRQHandler +PDMA_CH0_IRQHandler +PDMA_CH1_IRQHandler +PDMA_CH2_IRQHandler +PDMA_CH3_IRQHandler +PDMA_CH4_IRQHandler +PDMA_CH5_IRQHandler +PDMA_CH6_IRQHandler +PDMA_CH7_IRQHandler +PDMA_CH8_IRQHandler +PDMA_CH9_IRQHandler +PDMA_CH10_IRQHandler +PDMA_CH11_IRQHandler +CSIF_IRQHandler +EBI_IRQHandler +AES_IRQHandler + B . + ENDP + + ALIGN + +;******************************************************************************* +; User Stack and Heap initialization +;******************************************************************************* + IF :DEF:__MICROLIB + + EXPORT __HT_check_heap + EXPORT __HT_check_sp + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, = (Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + + ENDIF + + END diff --git a/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/Device/Holtek/HT32F1xxxx/Source/ARM/startup_ht32f165x.s b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/Device/Holtek/HT32F1xxxx/Source/ARM/startup_ht32f165x.s new file mode 100644 index 0000000000..9a0fd83e61 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/Device/Holtek/HT32F1xxxx/Source/ARM/startup_ht32f165x.s @@ -0,0 +1,469 @@ +;/*---------------------------------------------------------------------------------------------------------*/ +;/* Holtek Semiconductor Inc. */ +;/* */ +;/* Copyright (C) Holtek Semiconductor Inc. */ +;/* All rights reserved. */ +;/* */ +;/*----------------------------------------------------------------------------------------------------------- +; File Name : startup_ht32f1xxxx_01.s +; Version : $Rev:: 2524 $ +; Date : $Date:: 2022-02-17 #$ +; Description : Startup code. +;-----------------------------------------------------------------------------------------------------------*/ + +; Supported Device +; ======================================== +; HT32F1653, HT32F1654 +; HT32F1655, HT32F1656 +; HT32F12365, HT32F12366 +; HT32F12345 + +;/* <<< Use Configuration Wizard in Context Menu >>> */ + +;// HT32 Device +;// Select HT32 Device for the assembly setting. +;// Notice that the project's Asm Define has the higher priority. +;// <0=> By Project Asm Define +;// <1=> HT32F1653/1654/1655/1656 +;// <2=> HT32F12365/12366 +;// <3=> HT32F12345 +USE_HT32_CHIP_SET EQU 1 ; Notice that the project's Asm Define has the higher priority. + +_HT32FWID EQU 0xFFFFFFFF +;_HT32FWID EQU 0x00012366 + +HT32F1653_54_55_56 EQU 1 +HT32F12365_66 EQU 2 +HT32F12345 EQU 3 + + IF USE_HT32_CHIP_SET=0 + ; Use project's Asm Define setting (default) + ELSE + IF :DEF:USE_HT32_CHIP + ; Use project's Asm Define setting (higher priority than the "USE_HT32_CHIP_SET") + ELSE + ; Use "USE_HT32_CHIP_SET" in the "startup_ht32xxxxx_xx.s" file +USE_HT32_CHIP EQU USE_HT32_CHIP_SET + ENDIF + ENDIF + +; Amount of memory (in bytes) allocated for Stack and Heap +; Tailor those values to your application needs +;// Stack Size (in Bytes, must 8 byte aligned) <0-131072:8> +Stack_Size EQU 512 + + AREA STACK, NOINIT, READWRITE, ALIGN = 3 +__HT_check_sp +Stack_Mem SPACE Stack_Size +__initial_sp + +;// Heap Size (in Bytes) <0-131072:8> +Heap_Size EQU 0 + + AREA HEAP, NOINIT, READWRITE, ALIGN = 3 +__HT_check_heap +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + PRESERVE8 + THUMB + +;******************************************************************************* +; Fill-up the Vector Table entries with the exceptions ISR address +;******************************************************************************* + AREA RESET, CODE, READONLY + EXPORT __Vectors +_RESERVED EQU 0xFFFFFFFF +__Vectors + DCD __initial_sp ; ---, 00, 0x000, Top address of Stack + DCD Reset_Handler ; ---, 01, 0x004, Reset Handler + DCD NMI_Handler ; ---, 02, 0x008, NMI Handler + DCD HardFault_Handler ; ---, 03, 0x00C, Hard Fault Handler + DCD MemManage_Handler ; ---, 04, 0x010, Memory Management Fault Handler + DCD BusFault_Handler ; ---, 05, 0x014, Bus Fault Handler + DCD UsageFault_Handler ; ---, 06, 0x018, Usage Fault Handler + DCD _RESERVED ; ---, 07, 0x01C, Reserved + DCD _HT32FWID ; ---, 08, 0x020, Reserved + DCD _RESERVED ; ---, 09, 0x024, Reserved + DCD _RESERVED ; ---, 10, 0x028, Reserved + DCD SVC_Handler ; ---, 11, 0x02C, SVC Handler + DCD DebugMon_Handler ; ---, 12, 0x030, Debug Monitor Handler + DCD _RESERVED ; ---, 13, 0x034, Reserved + DCD PendSV_Handler ; ---, 14, 0x038, PendSV Handler + DCD SysTick_Handler ; ---, 15, 0x03C, SysTick Handler + + ; External Interrupt Handler + DCD CKRDY_IRQHandler ; 00, 16, 0x040, + DCD LVD_IRQHandler ; 01, 17, 0x044, + DCD BOD_IRQHandler ; 02, 18, 0x048, + IF (USE_HT32_CHIP=HT32F1653_54_55_56) + DCD WDT_IRQHandler ; 03, 19, 0x04C, + ELSE + DCD _RESERVED ; 03, 19, 0x04C, + ENDIF + DCD RTC_IRQHandler ; 04, 20, 0x050, + DCD FLASH_IRQHandler ; 05, 21, 0x054, + DCD EVWUP_IRQHandler ; 06, 22, 0x058, + DCD LPWUP_IRQHandler ; 07, 23, 0x05C, + DCD EXTI0_IRQHandler ; 08, 24, 0x060, + DCD EXTI1_IRQHandler ; 09, 25, 0x064, + DCD EXTI2_IRQHandler ; 10, 26, 0x068, + DCD EXTI3_IRQHandler ; 11, 27, 0x06C, + DCD EXTI4_IRQHandler ; 12, 28, 0x070, + DCD EXTI5_IRQHandler ; 13, 29, 0x074, + DCD EXTI6_IRQHandler ; 14, 30, 0x078, + DCD EXTI7_IRQHandler ; 15, 31, 0x07C, + DCD EXTI8_IRQHandler ; 16, 32, 0x080, + DCD EXTI9_IRQHandler ; 17, 33, 0x084, + DCD EXTI10_IRQHandler ; 18, 34, 0x088, + DCD EXTI11_IRQHandler ; 19, 35, 0x08C, + DCD EXTI12_IRQHandler ; 20, 36, 0x090, + DCD EXTI13_IRQHandler ; 21, 37, 0x094, + DCD EXTI14_IRQHandler ; 22, 38, 0x098, + DCD EXTI15_IRQHandler ; 23, 39, 0x09C, + DCD COMP_IRQHandler ; 24, 40, 0x0A0, + DCD ADC_IRQHandler ; 25, 41, 0x0A4, + DCD _RESERVED ; 26, 42, 0x0A8, + DCD MCTM0BRK_IRQHandler ; 27, 43, 0x0AC, + DCD MCTM0UP_IRQHandler ; 28, 44, 0x0B0, + DCD MCTM0TR_IRQHandler ; 29, 45, 0x0B4, + DCD MCTM0CC_IRQHandler ; 30, 46, 0x0B8, + DCD MCTM1BRK_IRQHandler ; 31, 47, 0x0BC, + DCD MCTM1UP_IRQHandler ; 32, 48, 0x0C0, + DCD MCTM1TR_IRQHandler ; 33, 49, 0x0C4, + DCD MCTM1CC_IRQHandler ; 34, 50, 0x0C8, + DCD GPTM0_IRQHandler ; 35, 51, 0x0CC, + DCD GPTM1_IRQHandler ; 36, 52, 0x0D0, + DCD _RESERVED ; 37, 53, 0x0D4, + DCD _RESERVED ; 38, 54, 0x0D8, + DCD _RESERVED ; 39, 55, 0x0DC, + DCD _RESERVED ; 40, 56, 0x0E0, + DCD BFTM0_IRQHandler ; 41, 57, 0x0E4, + DCD BFTM1_IRQHandler ; 42, 58, 0x0E8, + DCD I2C0_IRQHandler ; 43, 59, 0x0EC, + DCD I2C1_IRQHandler ; 44, 60, 0x0F0, + DCD SPI0_IRQHandler ; 45, 61, 0x0F4, + DCD SPI1_IRQHandler ; 46, 62, 0x0F8, + DCD USART0_IRQHandler ; 47, 63, 0x0FC, + DCD USART1_IRQHandler ; 48, 64, 0x100, + DCD UART0_IRQHandler ; 49, 65, 0x104, + DCD UART1_IRQHandler ; 50, 66, 0x108, + IF (USE_HT32_CHIP=HT32F12345) + DCD _RESERVED ; 51, 67, 0x10C, + ELSE + DCD SCI_IRQHandler ; 51, 67, 0x10C, + ENDIF + DCD I2S_IRQHandler ; 52, 68, 0x110, + DCD USB_IRQHandler ; 53, 69, 0x114, + IF (USE_HT32_CHIP=HT32F1653_54_55_56) + DCD _RESERVED ; 54, 70, 0x118, + ELSE + DCD SDIO_IRQHandler ; 54, 70, 0x118, + ENDIF + DCD PDMA_CH0_IRQHandler ; 55, 71, 0x11C, + DCD PDMA_CH1_IRQHandler ; 56, 72, 0x120, + DCD PDMA_CH2_IRQHandler ; 57, 73, 0x124, + DCD PDMA_CH3_IRQHandler ; 58, 74, 0x128, + DCD PDMA_CH4_IRQHandler ; 59, 75, 0x12C, + DCD PDMA_CH5_IRQHandler ; 60, 76, 0x130, + DCD PDMA_CH6_IRQHandler ; 61, 77, 0x134, + DCD PDMA_CH7_IRQHandler ; 62, 78, 0x138, + IF (USE_HT32_CHIP=HT32F1653_54_55_56) + DCD _RESERVED ; 63, 79, 0x13C, + DCD _RESERVED ; 64, 80, 0x140, + DCD _RESERVED ; 65, 81, 0x144, + DCD _RESERVED ; 66, 82, 0x148, + ELSE + DCD PDMA_CH8_IRQHandler ; 63, 79, 0x13C, + DCD PDMA_CH9_IRQHandler ; 64, 80, 0x140, + DCD PDMA_CH10_IRQHandler ; 65, 81, 0x144, + DCD PDMA_CH11_IRQHandler ; 66, 82, 0x148, + ENDIF + IF (USE_HT32_CHIP=HT32F12365_66) + DCD CSIF_IRQHandler ; 67, 83, 0x14C, + ELSE + DCD _RESERVED ; 67, 83, 0x14C, + ENDIF + DCD EBI_IRQHandler ; 68, 84, 0x150, + IF (USE_HT32_CHIP=HT32F12365_66) + DCD AES_IRQHandler ; 69, 85, 0x154, + ENDIF + +; Reset handler routine +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + IF (USE_HT32_CHIP=HT32F1653_54_55_56) + ELSE + LDR R0, =BootProcess + BLX R0 + ENDIF + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + + IF (USE_HT32_CHIP=HT32F1653_54_55_56) + ELSE +BootProcess PROC + LDR R0, =0x40080300 + LDR R1,[R0, #0x10] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x14] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x18] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x1C] + CMP R1, #0 + BEQ BP2 +BP1 LDR R0, =0x40080180 + LDR R1,[R0, #0xC] + LSLS R1, R1, #4 + LSRS R1, R1, #20 + CMP R1, #0 + BEQ BP3 + CMP R1, #1 + BEQ BP3 + CMP R1, #2 + BEQ BP3 +BP2 DSB + LDR R0, =0x20000000 + LDR R1, =0x05fa0004 + STR R1, [R0] + LDR R1, =0xe000ed00 + LDR R0, =0x05fa0004 + STR R0, [R1, #0xC] + DSB + B . +BP3 LDR R0, =0x20000000 + LDR R1, [R0] + LDR R0, =0x05fa0004 + CMP R0, R1 + BEQ BP4 + BX LR +BP4 LDR R0, =0x40088100 + LDR R1, =0x00000001 + STR R1, [R0] + LDR R0, =0x20000000 + LDR R1, =0x0 + STR R1, [R0] + BX LR + ENDP + ENDIF + +; Dummy Exception Handlers +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP + +HardFault_Handler PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP + +MemManage_Handler PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP + +BusFault_Handler PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP + +UsageFault_Handler PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP + +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP + +DebugMon_Handler PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP + +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP + +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + EXPORT CKRDY_IRQHandler [WEAK] + EXPORT LVD_IRQHandler [WEAK] + EXPORT BOD_IRQHandler [WEAK] + EXPORT WDT_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT EVWUP_IRQHandler [WEAK] + EXPORT LPWUP_IRQHandler [WEAK] + EXPORT EXTI0_IRQHandler [WEAK] + EXPORT EXTI1_IRQHandler [WEAK] + EXPORT EXTI2_IRQHandler [WEAK] + EXPORT EXTI3_IRQHandler [WEAK] + EXPORT EXTI4_IRQHandler [WEAK] + EXPORT EXTI5_IRQHandler [WEAK] + EXPORT EXTI6_IRQHandler [WEAK] + EXPORT EXTI7_IRQHandler [WEAK] + EXPORT EXTI8_IRQHandler [WEAK] + EXPORT EXTI9_IRQHandler [WEAK] + EXPORT EXTI10_IRQHandler [WEAK] + EXPORT EXTI11_IRQHandler [WEAK] + EXPORT EXTI12_IRQHandler [WEAK] + EXPORT EXTI13_IRQHandler [WEAK] + EXPORT EXTI14_IRQHandler [WEAK] + EXPORT EXTI15_IRQHandler [WEAK] + EXPORT COMP_IRQHandler [WEAK] + EXPORT ADC_IRQHandler [WEAK] + EXPORT MCTM0BRK_IRQHandler [WEAK] + EXPORT MCTM0UP_IRQHandler [WEAK] + EXPORT MCTM0TR_IRQHandler [WEAK] + EXPORT MCTM0CC_IRQHandler [WEAK] + EXPORT MCTM1BRK_IRQHandler [WEAK] + EXPORT MCTM1UP_IRQHandler [WEAK] + EXPORT MCTM1TR_IRQHandler [WEAK] + EXPORT MCTM1CC_IRQHandler [WEAK] + EXPORT GPTM0_IRQHandler [WEAK] + EXPORT GPTM1_IRQHandler [WEAK] + EXPORT BFTM0_IRQHandler [WEAK] + EXPORT BFTM1_IRQHandler [WEAK] + EXPORT I2C0_IRQHandler [WEAK] + EXPORT I2C1_IRQHandler [WEAK] + EXPORT SPI0_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT USART0_IRQHandler [WEAK] + EXPORT USART1_IRQHandler [WEAK] + EXPORT UART0_IRQHandler [WEAK] + EXPORT UART1_IRQHandler [WEAK] + EXPORT SCI_IRQHandler [WEAK] + EXPORT I2S_IRQHandler [WEAK] + EXPORT USB_IRQHandler [WEAK] + EXPORT SDIO_IRQHandler [WEAK] + EXPORT PDMA_CH0_IRQHandler [WEAK] + EXPORT PDMA_CH1_IRQHandler [WEAK] + EXPORT PDMA_CH2_IRQHandler [WEAK] + EXPORT PDMA_CH3_IRQHandler [WEAK] + EXPORT PDMA_CH4_IRQHandler [WEAK] + EXPORT PDMA_CH5_IRQHandler [WEAK] + EXPORT PDMA_CH6_IRQHandler [WEAK] + EXPORT PDMA_CH7_IRQHandler [WEAK] + EXPORT PDMA_CH8_IRQHandler [WEAK] + EXPORT PDMA_CH9_IRQHandler [WEAK] + EXPORT PDMA_CH10_IRQHandler [WEAK] + EXPORT PDMA_CH11_IRQHandler [WEAK] + EXPORT CSIF_IRQHandler [WEAK] + EXPORT EBI_IRQHandler [WEAK] + EXPORT AES_IRQHandler [WEAK] +CKRDY_IRQHandler +LVD_IRQHandler +BOD_IRQHandler +WDT_IRQHandler +RTC_IRQHandler +FLASH_IRQHandler +EVWUP_IRQHandler +LPWUP_IRQHandler +EXTI0_IRQHandler +EXTI1_IRQHandler +EXTI2_IRQHandler +EXTI3_IRQHandler +EXTI4_IRQHandler +EXTI5_IRQHandler +EXTI6_IRQHandler +EXTI7_IRQHandler +EXTI8_IRQHandler +EXTI9_IRQHandler +EXTI10_IRQHandler +EXTI11_IRQHandler +EXTI12_IRQHandler +EXTI13_IRQHandler +EXTI14_IRQHandler +EXTI15_IRQHandler +COMP_IRQHandler +ADC_IRQHandler +MCTM0BRK_IRQHandler +MCTM0UP_IRQHandler +MCTM0TR_IRQHandler +MCTM0CC_IRQHandler +MCTM1BRK_IRQHandler +MCTM1UP_IRQHandler +MCTM1TR_IRQHandler +MCTM1CC_IRQHandler +GPTM0_IRQHandler +GPTM1_IRQHandler +BFTM0_IRQHandler +BFTM1_IRQHandler +I2C0_IRQHandler +I2C1_IRQHandler +SPI0_IRQHandler +SPI1_IRQHandler +USART0_IRQHandler +USART1_IRQHandler +UART0_IRQHandler +UART1_IRQHandler +SCI_IRQHandler +I2S_IRQHandler +USB_IRQHandler +SDIO_IRQHandler +PDMA_CH0_IRQHandler +PDMA_CH1_IRQHandler +PDMA_CH2_IRQHandler +PDMA_CH3_IRQHandler +PDMA_CH4_IRQHandler +PDMA_CH5_IRQHandler +PDMA_CH6_IRQHandler +PDMA_CH7_IRQHandler +PDMA_CH8_IRQHandler +PDMA_CH9_IRQHandler +PDMA_CH10_IRQHandler +PDMA_CH11_IRQHandler +CSIF_IRQHandler +EBI_IRQHandler +AES_IRQHandler + B . + ENDP + + ALIGN + +;******************************************************************************* +; User Stack and Heap initialization +;******************************************************************************* + IF :DEF:__MICROLIB + + EXPORT __HT_check_heap + EXPORT __HT_check_sp + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, = (Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + + ENDIF + + END diff --git a/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/Device/Holtek/HT32F1xxxx/Source/ARM/startup_ht32f1xxxx_01.s b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/Device/Holtek/HT32F1xxxx/Source/ARM/startup_ht32f1xxxx_01.s new file mode 100644 index 0000000000..481edd75d0 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/Device/Holtek/HT32F1xxxx/Source/ARM/startup_ht32f1xxxx_01.s @@ -0,0 +1,469 @@ +;/*---------------------------------------------------------------------------------------------------------*/ +;/* Holtek Semiconductor Inc. */ +;/* */ +;/* Copyright (C) Holtek Semiconductor Inc. */ +;/* All rights reserved. */ +;/* */ +;/*----------------------------------------------------------------------------------------------------------- +; File Name : startup_ht32f1xxxx_01.s +; Version : $Rev:: 2524 $ +; Date : $Date:: 2022-02-17 #$ +; Description : Startup code. +;-----------------------------------------------------------------------------------------------------------*/ + +; Supported Device +; ======================================== +; HT32F1653, HT32F1654 +; HT32F1655, HT32F1656 +; HT32F12365, HT32F12366 +; HT32F12345 + +;/* <<< Use Configuration Wizard in Context Menu >>> */ + +;// HT32 Device +;// Select HT32 Device for the assembly setting. +;// Notice that the project's Asm Define has the higher priority. +;// <0=> By Project Asm Define +;// <1=> HT32F1653/1654/1655/1656 +;// <2=> HT32F12365/12366 +;// <3=> HT32F12345 +USE_HT32_CHIP_SET EQU 0 ; Notice that the project's Asm Define has the higher priority. + +_HT32FWID EQU 0xFFFFFFFF +;_HT32FWID EQU 0x00012366 + +HT32F1653_54_55_56 EQU 1 +HT32F12365_66 EQU 2 +HT32F12345 EQU 3 + + IF USE_HT32_CHIP_SET=0 + ; Use project's Asm Define setting (default) + ELSE + IF :DEF:USE_HT32_CHIP + ; Use project's Asm Define setting (higher priority than the "USE_HT32_CHIP_SET") + ELSE + ; Use "USE_HT32_CHIP_SET" in the "startup_ht32xxxxx_xx.s" file +USE_HT32_CHIP EQU USE_HT32_CHIP_SET + ENDIF + ENDIF + +; Amount of memory (in bytes) allocated for Stack and Heap +; Tailor those values to your application needs +;// Stack Size (in Bytes, must 8 byte aligned) <0-131072:8> +Stack_Size EQU 512 + + AREA STACK, NOINIT, READWRITE, ALIGN = 3 +__HT_check_sp +Stack_Mem SPACE Stack_Size +__initial_sp + +;// Heap Size (in Bytes) <0-131072:8> +Heap_Size EQU 0 + + AREA HEAP, NOINIT, READWRITE, ALIGN = 3 +__HT_check_heap +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + PRESERVE8 + THUMB + +;******************************************************************************* +; Fill-up the Vector Table entries with the exceptions ISR address +;******************************************************************************* + AREA RESET, CODE, READONLY + EXPORT __Vectors +_RESERVED EQU 0xFFFFFFFF +__Vectors + DCD __initial_sp ; ---, 00, 0x000, Top address of Stack + DCD Reset_Handler ; ---, 01, 0x004, Reset Handler + DCD NMI_Handler ; ---, 02, 0x008, NMI Handler + DCD HardFault_Handler ; ---, 03, 0x00C, Hard Fault Handler + DCD MemManage_Handler ; ---, 04, 0x010, Memory Management Fault Handler + DCD BusFault_Handler ; ---, 05, 0x014, Bus Fault Handler + DCD UsageFault_Handler ; ---, 06, 0x018, Usage Fault Handler + DCD _RESERVED ; ---, 07, 0x01C, Reserved + DCD _HT32FWID ; ---, 08, 0x020, Reserved + DCD _RESERVED ; ---, 09, 0x024, Reserved + DCD _RESERVED ; ---, 10, 0x028, Reserved + DCD SVC_Handler ; ---, 11, 0x02C, SVC Handler + DCD DebugMon_Handler ; ---, 12, 0x030, Debug Monitor Handler + DCD _RESERVED ; ---, 13, 0x034, Reserved + DCD PendSV_Handler ; ---, 14, 0x038, PendSV Handler + DCD SysTick_Handler ; ---, 15, 0x03C, SysTick Handler + + ; External Interrupt Handler + DCD CKRDY_IRQHandler ; 00, 16, 0x040, + DCD LVD_IRQHandler ; 01, 17, 0x044, + DCD BOD_IRQHandler ; 02, 18, 0x048, + IF (USE_HT32_CHIP=HT32F1653_54_55_56) + DCD WDT_IRQHandler ; 03, 19, 0x04C, + ELSE + DCD _RESERVED ; 03, 19, 0x04C, + ENDIF + DCD RTC_IRQHandler ; 04, 20, 0x050, + DCD FLASH_IRQHandler ; 05, 21, 0x054, + DCD EVWUP_IRQHandler ; 06, 22, 0x058, + DCD LPWUP_IRQHandler ; 07, 23, 0x05C, + DCD EXTI0_IRQHandler ; 08, 24, 0x060, + DCD EXTI1_IRQHandler ; 09, 25, 0x064, + DCD EXTI2_IRQHandler ; 10, 26, 0x068, + DCD EXTI3_IRQHandler ; 11, 27, 0x06C, + DCD EXTI4_IRQHandler ; 12, 28, 0x070, + DCD EXTI5_IRQHandler ; 13, 29, 0x074, + DCD EXTI6_IRQHandler ; 14, 30, 0x078, + DCD EXTI7_IRQHandler ; 15, 31, 0x07C, + DCD EXTI8_IRQHandler ; 16, 32, 0x080, + DCD EXTI9_IRQHandler ; 17, 33, 0x084, + DCD EXTI10_IRQHandler ; 18, 34, 0x088, + DCD EXTI11_IRQHandler ; 19, 35, 0x08C, + DCD EXTI12_IRQHandler ; 20, 36, 0x090, + DCD EXTI13_IRQHandler ; 21, 37, 0x094, + DCD EXTI14_IRQHandler ; 22, 38, 0x098, + DCD EXTI15_IRQHandler ; 23, 39, 0x09C, + DCD COMP_IRQHandler ; 24, 40, 0x0A0, + DCD ADC_IRQHandler ; 25, 41, 0x0A4, + DCD _RESERVED ; 26, 42, 0x0A8, + DCD MCTM0BRK_IRQHandler ; 27, 43, 0x0AC, + DCD MCTM0UP_IRQHandler ; 28, 44, 0x0B0, + DCD MCTM0TR_IRQHandler ; 29, 45, 0x0B4, + DCD MCTM0CC_IRQHandler ; 30, 46, 0x0B8, + DCD MCTM1BRK_IRQHandler ; 31, 47, 0x0BC, + DCD MCTM1UP_IRQHandler ; 32, 48, 0x0C0, + DCD MCTM1TR_IRQHandler ; 33, 49, 0x0C4, + DCD MCTM1CC_IRQHandler ; 34, 50, 0x0C8, + DCD GPTM0_IRQHandler ; 35, 51, 0x0CC, + DCD GPTM1_IRQHandler ; 36, 52, 0x0D0, + DCD _RESERVED ; 37, 53, 0x0D4, + DCD _RESERVED ; 38, 54, 0x0D8, + DCD _RESERVED ; 39, 55, 0x0DC, + DCD _RESERVED ; 40, 56, 0x0E0, + DCD BFTM0_IRQHandler ; 41, 57, 0x0E4, + DCD BFTM1_IRQHandler ; 42, 58, 0x0E8, + DCD I2C0_IRQHandler ; 43, 59, 0x0EC, + DCD I2C1_IRQHandler ; 44, 60, 0x0F0, + DCD SPI0_IRQHandler ; 45, 61, 0x0F4, + DCD SPI1_IRQHandler ; 46, 62, 0x0F8, + DCD USART0_IRQHandler ; 47, 63, 0x0FC, + DCD USART1_IRQHandler ; 48, 64, 0x100, + DCD UART0_IRQHandler ; 49, 65, 0x104, + DCD UART1_IRQHandler ; 50, 66, 0x108, + IF (USE_HT32_CHIP=HT32F12345) + DCD _RESERVED ; 51, 67, 0x10C, + ELSE + DCD SCI_IRQHandler ; 51, 67, 0x10C, + ENDIF + DCD I2S_IRQHandler ; 52, 68, 0x110, + DCD USB_IRQHandler ; 53, 69, 0x114, + IF (USE_HT32_CHIP=HT32F1653_54_55_56) + DCD _RESERVED ; 54, 70, 0x118, + ELSE + DCD SDIO_IRQHandler ; 54, 70, 0x118, + ENDIF + DCD PDMA_CH0_IRQHandler ; 55, 71, 0x11C, + DCD PDMA_CH1_IRQHandler ; 56, 72, 0x120, + DCD PDMA_CH2_IRQHandler ; 57, 73, 0x124, + DCD PDMA_CH3_IRQHandler ; 58, 74, 0x128, + DCD PDMA_CH4_IRQHandler ; 59, 75, 0x12C, + DCD PDMA_CH5_IRQHandler ; 60, 76, 0x130, + DCD PDMA_CH6_IRQHandler ; 61, 77, 0x134, + DCD PDMA_CH7_IRQHandler ; 62, 78, 0x138, + IF (USE_HT32_CHIP=HT32F1653_54_55_56) + DCD _RESERVED ; 63, 79, 0x13C, + DCD _RESERVED ; 64, 80, 0x140, + DCD _RESERVED ; 65, 81, 0x144, + DCD _RESERVED ; 66, 82, 0x148, + ELSE + DCD PDMA_CH8_IRQHandler ; 63, 79, 0x13C, + DCD PDMA_CH9_IRQHandler ; 64, 80, 0x140, + DCD PDMA_CH10_IRQHandler ; 65, 81, 0x144, + DCD PDMA_CH11_IRQHandler ; 66, 82, 0x148, + ENDIF + IF (USE_HT32_CHIP=HT32F12365_66) + DCD CSIF_IRQHandler ; 67, 83, 0x14C, + ELSE + DCD _RESERVED ; 67, 83, 0x14C, + ENDIF + DCD EBI_IRQHandler ; 68, 84, 0x150, + IF (USE_HT32_CHIP=HT32F12365_66) + DCD AES_IRQHandler ; 69, 85, 0x154, + ENDIF + +; Reset handler routine +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + IF (USE_HT32_CHIP=HT32F1653_54_55_56) + ELSE + LDR R0, =BootProcess + BLX R0 + ENDIF + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + + IF (USE_HT32_CHIP=HT32F1653_54_55_56) + ELSE +BootProcess PROC + LDR R0, =0x40080300 + LDR R1,[R0, #0x10] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x14] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x18] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x1C] + CMP R1, #0 + BEQ BP2 +BP1 LDR R0, =0x40080180 + LDR R1,[R0, #0xC] + LSLS R1, R1, #4 + LSRS R1, R1, #20 + CMP R1, #0 + BEQ BP3 + CMP R1, #1 + BEQ BP3 + CMP R1, #2 + BEQ BP3 +BP2 DSB + LDR R0, =0x20000000 + LDR R1, =0x05fa0004 + STR R1, [R0] + LDR R1, =0xe000ed00 + LDR R0, =0x05fa0004 + STR R0, [R1, #0xC] + DSB + B . +BP3 LDR R0, =0x20000000 + LDR R1, [R0] + LDR R0, =0x05fa0004 + CMP R0, R1 + BEQ BP4 + BX LR +BP4 LDR R0, =0x40088100 + LDR R1, =0x00000001 + STR R1, [R0] + LDR R0, =0x20000000 + LDR R1, =0x0 + STR R1, [R0] + BX LR + ENDP + ENDIF + +; Dummy Exception Handlers +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP + +HardFault_Handler PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP + +MemManage_Handler PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP + +BusFault_Handler PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP + +UsageFault_Handler PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP + +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP + +DebugMon_Handler PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP + +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP + +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + EXPORT CKRDY_IRQHandler [WEAK] + EXPORT LVD_IRQHandler [WEAK] + EXPORT BOD_IRQHandler [WEAK] + EXPORT WDT_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT EVWUP_IRQHandler [WEAK] + EXPORT LPWUP_IRQHandler [WEAK] + EXPORT EXTI0_IRQHandler [WEAK] + EXPORT EXTI1_IRQHandler [WEAK] + EXPORT EXTI2_IRQHandler [WEAK] + EXPORT EXTI3_IRQHandler [WEAK] + EXPORT EXTI4_IRQHandler [WEAK] + EXPORT EXTI5_IRQHandler [WEAK] + EXPORT EXTI6_IRQHandler [WEAK] + EXPORT EXTI7_IRQHandler [WEAK] + EXPORT EXTI8_IRQHandler [WEAK] + EXPORT EXTI9_IRQHandler [WEAK] + EXPORT EXTI10_IRQHandler [WEAK] + EXPORT EXTI11_IRQHandler [WEAK] + EXPORT EXTI12_IRQHandler [WEAK] + EXPORT EXTI13_IRQHandler [WEAK] + EXPORT EXTI14_IRQHandler [WEAK] + EXPORT EXTI15_IRQHandler [WEAK] + EXPORT COMP_IRQHandler [WEAK] + EXPORT ADC_IRQHandler [WEAK] + EXPORT MCTM0BRK_IRQHandler [WEAK] + EXPORT MCTM0UP_IRQHandler [WEAK] + EXPORT MCTM0TR_IRQHandler [WEAK] + EXPORT MCTM0CC_IRQHandler [WEAK] + EXPORT MCTM1BRK_IRQHandler [WEAK] + EXPORT MCTM1UP_IRQHandler [WEAK] + EXPORT MCTM1TR_IRQHandler [WEAK] + EXPORT MCTM1CC_IRQHandler [WEAK] + EXPORT GPTM0_IRQHandler [WEAK] + EXPORT GPTM1_IRQHandler [WEAK] + EXPORT BFTM0_IRQHandler [WEAK] + EXPORT BFTM1_IRQHandler [WEAK] + EXPORT I2C0_IRQHandler [WEAK] + EXPORT I2C1_IRQHandler [WEAK] + EXPORT SPI0_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT USART0_IRQHandler [WEAK] + EXPORT USART1_IRQHandler [WEAK] + EXPORT UART0_IRQHandler [WEAK] + EXPORT UART1_IRQHandler [WEAK] + EXPORT SCI_IRQHandler [WEAK] + EXPORT I2S_IRQHandler [WEAK] + EXPORT USB_IRQHandler [WEAK] + EXPORT SDIO_IRQHandler [WEAK] + EXPORT PDMA_CH0_IRQHandler [WEAK] + EXPORT PDMA_CH1_IRQHandler [WEAK] + EXPORT PDMA_CH2_IRQHandler [WEAK] + EXPORT PDMA_CH3_IRQHandler [WEAK] + EXPORT PDMA_CH4_IRQHandler [WEAK] + EXPORT PDMA_CH5_IRQHandler [WEAK] + EXPORT PDMA_CH6_IRQHandler [WEAK] + EXPORT PDMA_CH7_IRQHandler [WEAK] + EXPORT PDMA_CH8_IRQHandler [WEAK] + EXPORT PDMA_CH9_IRQHandler [WEAK] + EXPORT PDMA_CH10_IRQHandler [WEAK] + EXPORT PDMA_CH11_IRQHandler [WEAK] + EXPORT CSIF_IRQHandler [WEAK] + EXPORT EBI_IRQHandler [WEAK] + EXPORT AES_IRQHandler [WEAK] +CKRDY_IRQHandler +LVD_IRQHandler +BOD_IRQHandler +WDT_IRQHandler +RTC_IRQHandler +FLASH_IRQHandler +EVWUP_IRQHandler +LPWUP_IRQHandler +EXTI0_IRQHandler +EXTI1_IRQHandler +EXTI2_IRQHandler +EXTI3_IRQHandler +EXTI4_IRQHandler +EXTI5_IRQHandler +EXTI6_IRQHandler +EXTI7_IRQHandler +EXTI8_IRQHandler +EXTI9_IRQHandler +EXTI10_IRQHandler +EXTI11_IRQHandler +EXTI12_IRQHandler +EXTI13_IRQHandler +EXTI14_IRQHandler +EXTI15_IRQHandler +COMP_IRQHandler +ADC_IRQHandler +MCTM0BRK_IRQHandler +MCTM0UP_IRQHandler +MCTM0TR_IRQHandler +MCTM0CC_IRQHandler +MCTM1BRK_IRQHandler +MCTM1UP_IRQHandler +MCTM1TR_IRQHandler +MCTM1CC_IRQHandler +GPTM0_IRQHandler +GPTM1_IRQHandler +BFTM0_IRQHandler +BFTM1_IRQHandler +I2C0_IRQHandler +I2C1_IRQHandler +SPI0_IRQHandler +SPI1_IRQHandler +USART0_IRQHandler +USART1_IRQHandler +UART0_IRQHandler +UART1_IRQHandler +SCI_IRQHandler +I2S_IRQHandler +USB_IRQHandler +SDIO_IRQHandler +PDMA_CH0_IRQHandler +PDMA_CH1_IRQHandler +PDMA_CH2_IRQHandler +PDMA_CH3_IRQHandler +PDMA_CH4_IRQHandler +PDMA_CH5_IRQHandler +PDMA_CH6_IRQHandler +PDMA_CH7_IRQHandler +PDMA_CH8_IRQHandler +PDMA_CH9_IRQHandler +PDMA_CH10_IRQHandler +PDMA_CH11_IRQHandler +CSIF_IRQHandler +EBI_IRQHandler +AES_IRQHandler + B . + ENDP + + ALIGN + +;******************************************************************************* +; User Stack and Heap initialization +;******************************************************************************* + IF :DEF:__MICROLIB + + EXPORT __HT_check_heap + EXPORT __HT_check_sp + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, = (Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + + ENDIF + + END diff --git a/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/Device/Holtek/HT32F1xxxx/Source/ARM/startup_ht32f1xxxx_03.s b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/Device/Holtek/HT32F1xxxx/Source/ARM/startup_ht32f1xxxx_03.s new file mode 100644 index 0000000000..323e76c6b6 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/Device/Holtek/HT32F1xxxx/Source/ARM/startup_ht32f1xxxx_03.s @@ -0,0 +1,393 @@ +;/*---------------------------------------------------------------------------------------------------------*/ +;/* Holtek Semiconductor Inc. */ +;/* */ +;/* Copyright (C) Holtek Semiconductor Inc. */ +;/* All rights reserved. */ +;/* */ +;/*----------------------------------------------------------------------------------------------------------- +; File Name : startup_ht32f1xxxx_03.s +; Version : $Rev:: 2524 $ +; Date : $Date:: 2022-02-17 #$ +; Description : Startup code. +;-----------------------------------------------------------------------------------------------------------*/ + +; Supported Device +; ======================================== +; HT32F12364 + +;/* <<< Use Configuration Wizard in Context Menu >>> */ + +;// HT32 Device +;// Select HT32 Device for the assembly setting. +;// Notice that the project's Asm Define has the higher priority. +;// <0=> By Project Asm Define +;// <16=> HT32F12364 +USE_HT32_CHIP_SET EQU 0 ; Notice that the project's Asm Define has the higher priority. + +_HT32FWID EQU 0xFFFFFFFF +;_HT32FWID EQU 0x00012364 + +HT32F12364 EQU 16 + + IF USE_HT32_CHIP_SET=0 + ; Use project's Asm Define setting (default) + ELSE + IF :DEF:USE_HT32_CHIP + ; Use project's Asm Define setting (higher priority than the "USE_HT32_CHIP_SET") + ELSE + ; Use "USE_HT32_CHIP_SET" in the "startup_ht32xxxxx_xx.s" file +USE_HT32_CHIP EQU USE_HT32_CHIP_SET + ENDIF + ENDIF + +; Amount of memory (in bytes) allocated for Stack and Heap +; Tailor those values to your application needs +;// Stack Size (in Bytes, must 8 byte aligned) <0-131072:8> +Stack_Size EQU 512 + + AREA STACK, NOINIT, READWRITE, ALIGN = 3 +__HT_check_sp +Stack_Mem SPACE Stack_Size +__initial_sp + +;// Heap Size (in Bytes) <0-131072:8> +Heap_Size EQU 0 + + AREA HEAP, NOINIT, READWRITE, ALIGN = 3 +__HT_check_heap +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + PRESERVE8 + THUMB + +;******************************************************************************* +; Fill-up the Vector Table entries with the exceptions ISR address +;******************************************************************************* + AREA RESET, CODE, READONLY + EXPORT __Vectors +_RESERVED EQU 0xFFFFFFFF +__Vectors + DCD __initial_sp ; ---, 00, 0x000, Top address of Stack + DCD Reset_Handler ; ---, 01, 0x004, Reset Handler + DCD NMI_Handler ; ---, 02, 0x008, NMI Handler + DCD HardFault_Handler ; ---, 03, 0x00C, Hard Fault Handler + DCD MemManage_Handler ; ---, 04, 0x010, Memory Management Fault Handler + DCD BusFault_Handler ; ---, 05, 0x014, Bus Fault Handler + DCD UsageFault_Handler ; ---, 06, 0x018, Usage Fault Handler + DCD _RESERVED ; ---, 07, 0x01C, Reserved + DCD _HT32FWID ; ---, 08, 0x020, Reserved + DCD _RESERVED ; ---, 09, 0x024, Reserved + DCD _RESERVED ; ---, 10, 0x028, Reserved + DCD SVC_Handler ; ---, 11, 0x02C, SVC Handler + DCD DebugMon_Handler ; ---, 12, 0x030, Debug Monitor Handler + DCD _RESERVED ; ---, 13, 0x034, Reserved + DCD PendSV_Handler ; ---, 14, 0x038, PendSV Handler + DCD SysTick_Handler ; ---, 15, 0x03C, SysTick Handler + + ; External Interrupt Handler + DCD CKRDY_IRQHandler ; 00, 16, 0x040, + DCD LVD_IRQHandler ; 01, 17, 0x044, + DCD BOD_IRQHandler ; 02, 18, 0x048, + DCD _RESERVED ; 03, 19, 0x04C, + DCD RTC_IRQHandler ; 04, 20, 0x050, + DCD FLASH_IRQHandler ; 05, 21, 0x054, + DCD EVWUP_IRQHandler ; 06, 22, 0x058, + DCD LPWUP_IRQHandler ; 07, 23, 0x05C, + DCD EXTI0_IRQHandler ; 08, 24, 0x060, + DCD EXTI1_IRQHandler ; 09, 25, 0x064, + DCD EXTI2_IRQHandler ; 10, 26, 0x068, + DCD EXTI3_IRQHandler ; 11, 27, 0x06C, + DCD EXTI4_IRQHandler ; 12, 28, 0x070, + DCD EXTI5_IRQHandler ; 13, 29, 0x074, + DCD EXTI6_IRQHandler ; 14, 30, 0x078, + DCD EXTI7_IRQHandler ; 15, 31, 0x07C, + DCD EXTI8_IRQHandler ; 16, 32, 0x080, + DCD EXTI9_IRQHandler ; 17, 33, 0x084, + DCD EXTI10_IRQHandler ; 18, 34, 0x088, + DCD EXTI11_IRQHandler ; 19, 35, 0x08C, + DCD EXTI12_IRQHandler ; 20, 36, 0x090, + DCD EXTI13_IRQHandler ; 21, 37, 0x094, + DCD EXTI14_IRQHandler ; 22, 38, 0x098, + DCD EXTI15_IRQHandler ; 23, 39, 0x09C, + DCD _RESERVED ; 24, 40, 0x0A0, + DCD ADC_IRQHandler ; 25, 41, 0x0A4, + DCD _RESERVED ; 26, 42, 0x0A8, + DCD _RESERVED ; 27, 43, 0x0AC, + DCD _RESERVED ; 28, 44, 0x0B0, + DCD _RESERVED ; 29, 45, 0x0B4, + DCD _RESERVED ; 30, 46, 0x0B8, + DCD _RESERVED ; 31, 47, 0x0BC, + DCD _RESERVED ; 32, 48, 0x0C0, + DCD _RESERVED ; 33, 49, 0x0C4, + DCD _RESERVED ; 34, 50, 0x0C8, + DCD GPTM0_IRQHandler ; 35, 51, 0x0CC, + DCD _RESERVED ; 36, 52, 0x0D0, + DCD SCTM0_IRQHandler ; 37, 53, 0x0D4, + DCD SCTM1_IRQHandler ; 38, 54, 0x0D8, + DCD PWM0_IRQHandler ; 39, 55, 0x0DC, + DCD _RESERVED ; 40, 56, 0x0E0, + DCD BFTM0_IRQHandler ; 41, 57, 0x0E4, + DCD BFTM1_IRQHandler ; 42, 58, 0x0E8, + DCD I2C0_IRQHandler ; 43, 59, 0x0EC, + DCD I2C1_IRQHandler ; 44, 60, 0x0F0, + DCD SPI0_IRQHandler ; 45, 61, 0x0F4, + DCD SPI1_IRQHandler ; 46, 62, 0x0F8, + DCD USART0_IRQHandler ; 47, 63, 0x0FC, + DCD _RESERVED ; 48, 64, 0x100, + DCD UART0_IRQHandler ; 49, 65, 0x104, + DCD UART1_IRQHandler ; 50, 66, 0x108, + DCD SCI_IRQHandler ; 51, 67, 0x10C, + DCD _RESERVED ; 52, 68, 0x110, + DCD USB_IRQHandler ; 53, 69, 0x114, + DCD _RESERVED ; 54, 70, 0x118, + DCD PDMA_CH0_IRQHandler ; 55, 71, 0x11C, + DCD PDMA_CH1_IRQHandler ; 56, 72, 0x120, + DCD PDMA_CH2_IRQHandler ; 57, 73, 0x124, + DCD PDMA_CH3_IRQHandler ; 58, 74, 0x128, + DCD PDMA_CH4_IRQHandler ; 59, 75, 0x12C, + DCD PDMA_CH5_IRQHandler ; 60, 76, 0x130, + DCD _RESERVED ; 61, 77, 0x134, + DCD _RESERVED ; 62, 78, 0x138, + DCD _RESERVED ; 63, 79, 0x13C, + DCD _RESERVED ; 64, 80, 0x140, + DCD _RESERVED ; 65, 81, 0x144, + DCD _RESERVED ; 66, 82, 0x148, + DCD _RESERVED ; 67, 83, 0x14C, + DCD _RESERVED ; 68, 84, 0x150, + DCD AES_IRQHandler ; 69, 85, 0x154, + +; Reset handler routine +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + LDR R0, =BootProcess + BLX R0 + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +BootProcess PROC + LDR R0, =0x40080300 + LDR R1,[R0, #0x10] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x14] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x18] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x1C] + CMP R1, #0 + BEQ BP2 +BP1 LDR R0, =0x40080180 + LDR R1,[R0, #0xC] + LSLS R1, R1, #4 + LSRS R1, R1, #20 + CMP R1, #0 + BEQ BP3 + CMP R1, #1 + BEQ BP3 + CMP R1, #2 + BEQ BP3 +BP2 DSB + LDR R0, =0x20000000 + LDR R1, =0x05fa0004 + STR R1, [R0] + LDR R1, =0xe000ed00 + LDR R0, =0x05fa0004 + STR R0, [R1, #0xC] + DSB + B . +BP3 LDR R0, =0x20000000 + LDR R1, [R0] + LDR R0, =0x05fa0004 + CMP R0, R1 + BEQ BP4 + BX LR +BP4 LDR R0, =0x40088100 + LDR R1, =0x00000001 + STR R1, [R0] + LDR R0, =0x20000000 + LDR R1, =0x0 + STR R1, [R0] + BX LR + ENDP + +; Dummy Exception Handlers +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP + +HardFault_Handler PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP + +MemManage_Handler PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP + +BusFault_Handler PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP + +UsageFault_Handler PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP + +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP + +DebugMon_Handler PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP + +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP + +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + EXPORT CKRDY_IRQHandler [WEAK] + EXPORT LVD_IRQHandler [WEAK] + EXPORT BOD_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT EVWUP_IRQHandler [WEAK] + EXPORT LPWUP_IRQHandler [WEAK] + EXPORT EXTI0_IRQHandler [WEAK] + EXPORT EXTI1_IRQHandler [WEAK] + EXPORT EXTI2_IRQHandler [WEAK] + EXPORT EXTI3_IRQHandler [WEAK] + EXPORT EXTI4_IRQHandler [WEAK] + EXPORT EXTI5_IRQHandler [WEAK] + EXPORT EXTI6_IRQHandler [WEAK] + EXPORT EXTI7_IRQHandler [WEAK] + EXPORT EXTI8_IRQHandler [WEAK] + EXPORT EXTI9_IRQHandler [WEAK] + EXPORT EXTI10_IRQHandler [WEAK] + EXPORT EXTI11_IRQHandler [WEAK] + EXPORT EXTI12_IRQHandler [WEAK] + EXPORT EXTI13_IRQHandler [WEAK] + EXPORT EXTI14_IRQHandler [WEAK] + EXPORT EXTI15_IRQHandler [WEAK] + EXPORT ADC_IRQHandler [WEAK] + EXPORT GPTM0_IRQHandler [WEAK] + EXPORT SCTM0_IRQHandler [WEAK] + EXPORT SCTM1_IRQHandler [WEAK] + EXPORT PWM0_IRQHandler [WEAK] + EXPORT BFTM0_IRQHandler [WEAK] + EXPORT BFTM1_IRQHandler [WEAK] + EXPORT I2C0_IRQHandler [WEAK] + EXPORT I2C1_IRQHandler [WEAK] + EXPORT SPI0_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT USART0_IRQHandler [WEAK] + EXPORT UART0_IRQHandler [WEAK] + EXPORT UART1_IRQHandler [WEAK] + EXPORT SCI_IRQHandler [WEAK] + EXPORT USB_IRQHandler [WEAK] + EXPORT PDMA_CH0_IRQHandler [WEAK] + EXPORT PDMA_CH1_IRQHandler [WEAK] + EXPORT PDMA_CH2_IRQHandler [WEAK] + EXPORT PDMA_CH3_IRQHandler [WEAK] + EXPORT PDMA_CH4_IRQHandler [WEAK] + EXPORT PDMA_CH5_IRQHandler [WEAK] + EXPORT AES_IRQHandler [WEAK] +CKRDY_IRQHandler +LVD_IRQHandler +BOD_IRQHandler +RTC_IRQHandler +FLASH_IRQHandler +EVWUP_IRQHandler +LPWUP_IRQHandler +EXTI0_IRQHandler +EXTI1_IRQHandler +EXTI2_IRQHandler +EXTI3_IRQHandler +EXTI4_IRQHandler +EXTI5_IRQHandler +EXTI6_IRQHandler +EXTI7_IRQHandler +EXTI8_IRQHandler +EXTI9_IRQHandler +EXTI10_IRQHandler +EXTI11_IRQHandler +EXTI12_IRQHandler +EXTI13_IRQHandler +EXTI14_IRQHandler +EXTI15_IRQHandler +ADC_IRQHandler +GPTM0_IRQHandler +SCTM0_IRQHandler +SCTM1_IRQHandler +PWM0_IRQHandler +BFTM0_IRQHandler +BFTM1_IRQHandler +I2C0_IRQHandler +I2C1_IRQHandler +SPI0_IRQHandler +SPI1_IRQHandler +USART0_IRQHandler +UART0_IRQHandler +UART1_IRQHandler +SCI_IRQHandler +USB_IRQHandler +PDMA_CH0_IRQHandler +PDMA_CH1_IRQHandler +PDMA_CH2_IRQHandler +PDMA_CH3_IRQHandler +PDMA_CH4_IRQHandler +PDMA_CH5_IRQHandler +AES_IRQHandler + B . + ENDP + + ALIGN + +;******************************************************************************* +; User Stack and Heap initialization +;******************************************************************************* + IF :DEF:__MICROLIB + + EXPORT __HT_check_heap + EXPORT __HT_check_sp + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, = (Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + + ENDIF + + END diff --git a/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/Device/Holtek/HT32F1xxxx/Source/CodeSourcery/startup_ht32f1xxxx_cs3_01.s b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/Device/Holtek/HT32F1xxxx/Source/CodeSourcery/startup_ht32f1xxxx_cs3_01.s new file mode 100644 index 0000000000..0e11813688 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/Device/Holtek/HT32F1xxxx/Source/CodeSourcery/startup_ht32f1xxxx_cs3_01.s @@ -0,0 +1,427 @@ +/*---------------------------------------------------------------------------------------------------------*/ +/* Holtek Semiconductor Inc. */ +/* */ +/* Copyright (C) Holtek Semiconductor Inc. */ +/* All rights reserved. */ +/* */ +/*----------------------------------------------------------------------------------------------------------- +; File Name : startup_ht32f1xxxx_cs3_01.s +; Version : $Rev:: 1578 $ +; Date : $Date:: 2019-03-29 #$ +; Description : Startup code. +;-----------------------------------------------------------------------------------------------------------*/ + +/* +; Supported Device +; ======================================== +; HT32F1653, HT32F1654 +; HT32F1655, HT32F1656 +; HT32F12365, HT32F12366 +; HT32F12345 +*/ + +;/* <<< Use Configuration Wizard in Context Menu >>> */ +/* +;// HT32 Device +;// <0=> By Project Asm Define +;// <1=> HT32F1653/1654/1655/1656 +;// <2=> HT32F12365/12366 +;// <3=> HT32F12345 +*/ + .equ USE_HT32_CHIP_SET, 0 + + .equ _HT32FWID, 0xFFFFFFFF +/* + .equ _HT32FWID, 0x00012366 +*/ + + .equ HT32F1653_54_55_56, 1 + .equ HT32F12365_66, 2 + .equ HT32F12345, 3 + + .if USE_HT32_CHIP_SET == 0 + .else + .equ USE_HT32_CHIP, USE_HT32_CHIP_SET + .endif + +/* +; Amount of memory (in bytes) allocated for Stack and Heap +; Tailor those values to your application needs +;// Stack Size (in Bytes, must 8 byte aligned) <:8> +*/ + .equ Stack_Size, 512 + .section ".stack", "w" + .align 3 + .globl __cs3_stack_mem + .globl __cs3_stack + .globl __cs3_stack_size + .globl __HT_check_sp +__HT_check_sp: +__cs3_stack_mem: + .if Stack_Size + .space Stack_Size + .endif +__cs3_stack: + .size __cs3_stack_mem, . - __cs3_stack_mem + .set __cs3_stack_size, . - __cs3_stack_mem + +/* +;// Heap Size (in Bytes) <:8> +*/ + .equ Heap_Size, 0 + .section ".heap", "w" + .align 3 + .globl __cs3_heap_start + .globl __cs3_heap_end + .globl __HT_check_heap +__HT_check_heap: +__cs3_heap_start: + .if Heap_Size + .space Heap_Size + .endif +__cs3_heap_end: + + .equ _RESERVED, 0xFFFFFFFF +/* +;******************************************************************************* +; Fill-up the Vector Table entries with the exceptions ISR address +;********************************************************************************/ + .section ".cs3.interrupt_vector" + .globl __cs3_interrupt_vector_cortex_m + .type __cs3_interrupt_vector_cortex_m, %object +__cs3_interrupt_vector_cortex_m: + .long __cs3_stack /* ---, 00, 0x000, Top address of Stack */ + .long __cs3_reset /* ---, 01, 0x004, Reset Handler */ + .long NMI_Handler /* ---, 02, 0x008, NMI Handler */ + .long HardFault_Handler /* ---, 03, 0x00C, Hard Fault Handler */ + .long MemManage_Handler /* ---, 04, 0x010, MPU Fault Handler */ + .long BusFault_Handler /* ---, 05, 0x014, Bus Fault Handler */ + .long UsageFault_Handler /* ---, 06, 0x018, Usage Fault Handler */ + .long _RESERVED /* ---, 07, 0x01C, Reserved */ + .long _HT32FWID /* ---, 08, 0x020, Reserved */ + .long _RESERVED /* ---, 09, 0x024, Reserved */ + .long _RESERVED /* ---, 10, 0x028, Reserved */ + .long SVC_Handler /* ---, 11, 0x02C, SVC Handler */ + .long DebugMon_Handler /* ---, 12, 0x030, Debug Monitor Handler */ + .long _RESERVED /* ---, 13, 0x034, Reserved */ + .long PendSV_Handler /* ---, 14, 0x038, PendSV Handler */ + .long SysTick_Handler /* ---, 15, 0x03C, SysTick Handler */ + + /* External Interrupt Handler */ + .long CKRDY_IRQHandler /* 00, 16, 0x040, */ + .long LVD_IRQHandler /* 01, 17, 0x044, */ + .long BOD_IRQHandler /* 02, 18, 0x048, */ + .if (USE_HT32_CHIP==HT32F1653_54_55_56) + .long WDT_IRQHandler /* 03, 19, 0x04C, */ + .else + .long _RESERVED /* 03, 19, 0x04C, */ + .endif + .long RTC_IRQHandler /* 04, 20, 0x050, */ + .long FLASH_IRQHandler /* 05, 21, 0x054, */ + .long EVWUP_IRQHandler /* 06, 22, 0x058, */ + .long LPWUP_IRQHandler /* 07, 23, 0x05C, */ + .long EXTI0_IRQHandler /* 08, 24, 0x060, */ + .long EXTI1_IRQHandler /* 09, 25, 0x064, */ + .long EXTI2_IRQHandler /* 10, 26, 0x068, */ + .long EXTI3_IRQHandler /* 11, 27, 0x06C, */ + .long EXTI4_IRQHandler /* 12, 28, 0x070, */ + .long EXTI5_IRQHandler /* 13, 29, 0x074, */ + .long EXTI6_IRQHandler /* 14, 30, 0x078, */ + .long EXTI7_IRQHandler /* 15, 31, 0x07C, */ + .long EXTI8_IRQHandler /* 16, 32, 0x080, */ + .long EXTI9_IRQHandler /* 17, 33, 0x084, */ + .long EXTI10_IRQHandler /* 18, 34, 0x088, */ + .long EXTI11_IRQHandler /* 19, 35, 0x08C, */ + .long EXTI12_IRQHandler /* 20, 36, 0x090, */ + .long EXTI13_IRQHandler /* 21, 37, 0x094, */ + .long EXTI14_IRQHandler /* 22, 38, 0x098, */ + .long EXTI15_IRQHandler /* 23, 39, 0x09C, */ + .long COMP_IRQHandler /* 24, 40, 0x0A0, */ + .long ADC_IRQHandler /* 25, 41, 0x0A4, */ + .long _RESERVED /* 26, 42, 0x0A8, */ + .long MCTM0BRK_IRQHandler /* 27, 43, 0x0AC, */ + .long MCTM0UP_IRQHandler /* 28, 44, 0x0B0, */ + .long MCTM0TR_IRQHandler /* 29, 45, 0x0B4, */ + .long MCTM0CC_IRQHandler /* 30, 46, 0x0B8, */ + .long MCTM1BRK_IRQHandler /* 31, 47, 0x0BC, */ + .long MCTM1UP_IRQHandler /* 32, 48, 0x0C0, */ + .long MCTM1TR_IRQHandler /* 33, 49, 0x0C4, */ + .long MCTM1CC_IRQHandler /* 34, 50, 0x0C8, */ + .long GPTM0_IRQHandler /* 35, 51, 0x0CC, */ + .long GPTM1_IRQHandler /* 36, 52, 0x0D0, */ + .long _RESERVED /* 37, 53, 0x0D4, */ + .long _RESERVED /* 38, 54, 0x0D8, */ + .long _RESERVED /* 39, 55, 0x0DC, */ + .long _RESERVED /* 40, 56, 0x0E0, */ + .long BFTM0_IRQHandler /* 41, 57, 0x0E4, */ + .long BFTM1_IRQHandler /* 42, 58, 0x0E8, */ + .long I2C0_IRQHandler /* 43, 59, 0x0EC, */ + .long I2C1_IRQHandler /* 44, 60, 0x0F0, */ + .long SPI0_IRQHandler /* 45, 61, 0x0F4, */ + .long SPI1_IRQHandler /* 46, 62, 0x0F8, */ + .long USART0_IRQHandler /* 47, 63, 0x0FC, */ + .long USART1_IRQHandler /* 48, 64, 0x100, */ + .long UART0_IRQHandler /* 49, 65, 0x104, */ + .long UART1_IRQHandler /* 50, 66, 0x108, */ + .if (USE_HT32_CHIP==HT32F12345) + .long _RESERVED /* 51, 67, 0x10C, */ + .else + .long SCI_IRQHandler /* 51, 67, 0x10C, */ + .endif + .long I2S_IRQHandler /* 52, 68, 0x110, */ + .long USB_IRQHandler /* 53, 69, 0x114, */ + .if (USE_HT32_CHIP==HT32F1653_54_55_56) + .long _RESERVED /* 54, 70, 0x118, */ + .else + .long SDIO_IRQHandler /* 54, 70, 0x118, */ + .endif + .long PDMA_CH0_IRQHandler /* 55, 71, 0x11C, */ + .long PDMA_CH1_IRQHandler /* 56, 72, 0x120, */ + .long PDMA_CH2_IRQHandler /* 57, 73, 0x124, */ + .long PDMA_CH3_IRQHandler /* 58, 74, 0x128, */ + .long PDMA_CH4_IRQHandler /* 59, 75, 0x12C, */ + .long PDMA_CH5_IRQHandler /* 60, 76, 0x130, */ + .long PDMA_CH6_IRQHandler /* 61, 77, 0x134, */ + .long PDMA_CH7_IRQHandler /* 62, 78, 0x138, */ + .if (USE_HT32_CHIP==HT32F1653_54_55_56) + .long _RESERVED /* 63, 79, 0x13C, */ + .long _RESERVED /* 64, 80, 0x140, */ + .long _RESERVED /* 65, 81, 0x144, */ + .long _RESERVED /* 66, 82, 0x148, */ + .else + .long PDMA_CH8_IRQHandler /* 63, 79, 0x13C, */ + .long PDMA_CH9_IRQHandler /* 64, 80, 0x140, */ + .long PDMA_CH10_IRQHandler /* 65, 81, 0x144, */ + .long PDMA_CH11_IRQHandler /* 66, 82, 0x148, */ + .endif + .if (USE_HT32_CHIP==HT32F12365_66) + .long CSIF_IRQHandler /* 67, 83, 0x14C, */ + .else + .long _RESERVED /* 67, 83, 0x14C, */ + .endif + .long EBI_IRQHandler /* 68, 84, 0x150, */ + .if (USE_HT32_CHIP==HT32F12365_66) + .long AES_IRQHandler /* 69, 85, 0x154, */ + .endif + + .size __cs3_interrupt_vector_cortex_m, . - __cs3_interrupt_vector_cortex_m + + + .thumb + + +/* Reset Handler */ + + .section .cs3.reset,"x",%progbits + .thumb_func + .globl __cs3_reset_cortex_m + .type __cs3_reset_cortex_m, %function +__cs3_reset_cortex_m: + .fnstart + .if (USE_HT32_CHIP==HT32F1653_54_55_56) + .else + LDR R0, =BootProcess + BLX R0 + .endif + LDR R0, =SystemInit + BLX R0 + LDR R0, =_start + BX R0 + .if (USE_HT32_CHIP==HT32F1653_54_55_56) + .else + .thumb_func +BootProcess: + LDR R0, =0x40080300 + LDR R1,[R0, #0x10] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x14] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x18] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x1C] + CMP R1, #0 + BEQ BP2 +BP1: + LDR R0, =0x40080180 + LDR R1,[R0, #0xC] + LSL R1, R1, #4 + LSR R1, R1, #20 + CMP R1, #0 + BEQ BP3 + CMP R1, #1 + BEQ BP3 + CMP R1, #2 + BEQ BP3 +BP2: + DSB + LDR R0, =0x20000000 + LDR R1, =0x05fa0004 + STR R1, [R0] + LDR R1, =0xe000ed00 + LDR R0, =0x05fa0004 + STR R0, [R1, #0xC] + DSB + B . +BP3: + LDR R0, =0x20000000 + LDR R1, [R0] + LDR R0, =0x05fa0004 + CMP R0, R1 + BEQ BP4 + BX LR +BP4: + LDR R0, =0x40088100 + LDR R1, =0x00000001 + STR R1, [R0] + LDR R0, =0x20000000 + LDR R1, =0x0 + STR R1, [R0] + BX LR + .endif + .pool + .cantunwind + .fnend + .size __cs3_reset_cortex_m,.-__cs3_reset_cortex_m + + .section ".text" + +/* Exception Handlers */ + + .weak NMI_Handler + .type NMI_Handler, %function +NMI_Handler: + B . + .size NMI_Handler, . - NMI_Handler + + .weak HardFault_Handler + .type HardFault_Handler, %function +HardFault_Handler: + B . + .size HardFault_Handler, . - HardFault_Handler + + .weak MemManage_Handler + .type MemManage_Handler, %function +MemManage_Handler: + B . + .size MemManage_Handler, . - MemManage_Handler + + .weak BusFault_Handler + .type BusFault_Handler, %function +BusFault_Handler: + B . + .size BusFault_Handler, . - BusFault_Handler + + .weak UsageFault_Handler + .type UsageFault_Handler, %function +UsageFault_Handler: + B . + .size UsageFault_Handler, . - UsageFault_Handler + + .weak SVC_Handler + .type SVC_Handler, %function +SVC_Handler: + B . + .size SVC_Handler, . - SVC_Handler + + .weak DebugMon_Handler + .type DebugMon_Handler, %function +DebugMon_Handler: + B . + .size DebugMon_Handler, . - DebugMon_Handler + + .weak PendSV_Handler + .type PendSV_Handler, %function +PendSV_Handler: + B . + .size PendSV_Handler, . - PendSV_Handler + + .weak SysTick_Handler + .type SysTick_Handler, %function +SysTick_Handler: + B . + .size SysTick_Handler, . - SysTick_Handler + + +/* IRQ Handlers */ + + .globl Default_Handler + .type Default_Handler, %function +Default_Handler: + B . + .size Default_Handler, . - Default_Handler + + .macro IRQ handler + .weak \handler + .set \handler, Default_Handler + .endm + + IRQ CKRDY_IRQHandler + IRQ LVD_IRQHandler + IRQ BOD_IRQHandler + IRQ WDT_IRQHandler + IRQ RTC_IRQHandler + IRQ FLASH_IRQHandler + IRQ EVWUP_IRQHandler + IRQ LPWUP_IRQHandler + IRQ EXTI0_IRQHandler + IRQ EXTI1_IRQHandler + IRQ EXTI2_IRQHandler + IRQ EXTI3_IRQHandler + IRQ EXTI4_IRQHandler + IRQ EXTI5_IRQHandler + IRQ EXTI6_IRQHandler + IRQ EXTI7_IRQHandler + IRQ EXTI8_IRQHandler + IRQ EXTI9_IRQHandler + IRQ EXTI10_IRQHandler + IRQ EXTI11_IRQHandler + IRQ EXTI12_IRQHandler + IRQ EXTI13_IRQHandler + IRQ EXTI14_IRQHandler + IRQ EXTI15_IRQHandler + IRQ COMP_IRQHandler + IRQ ADC_IRQHandler + IRQ MCTM0BRK_IRQHandler + IRQ MCTM0UP_IRQHandler + IRQ MCTM0TR_IRQHandler + IRQ MCTM0CC_IRQHandler + IRQ MCTM1BRK_IRQHandler + IRQ MCTM1UP_IRQHandler + IRQ MCTM1TR_IRQHandler + IRQ MCTM1CC_IRQHandler + IRQ GPTM0_IRQHandler + IRQ GPTM1_IRQHandler + IRQ BFTM0_IRQHandler + IRQ BFTM1_IRQHandler + IRQ I2C0_IRQHandler + IRQ I2C1_IRQHandler + IRQ SPI0_IRQHandler + IRQ SPI1_IRQHandler + IRQ USART0_IRQHandler + IRQ USART1_IRQHandler + IRQ UART0_IRQHandler + IRQ UART1_IRQHandler + IRQ SCI_IRQHandler + IRQ I2S_IRQHandler + IRQ USB_IRQHandler + IRQ SDIO_IRQHandler + IRQ PDMA_CH0_IRQHandler + IRQ PDMA_CH1_IRQHandler + IRQ PDMA_CH2_IRQHandler + IRQ PDMA_CH3_IRQHandler + IRQ PDMA_CH4_IRQHandler + IRQ PDMA_CH5_IRQHandler + IRQ PDMA_CH6_IRQHandler + IRQ PDMA_CH7_IRQHandler + IRQ PDMA_CH8_IRQHandler + IRQ PDMA_CH9_IRQHandler + IRQ PDMA_CH10_IRQHandler + IRQ PDMA_CH11_IRQHandler + IRQ CSIF_IRQHandler + IRQ EBI_IRQHandler + IRQ AES_IRQHandler + + .end diff --git a/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/Device/Holtek/HT32F1xxxx/Source/CodeSourcery/startup_ht32f1xxxx_cs3_03.s b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/Device/Holtek/HT32F1xxxx/Source/CodeSourcery/startup_ht32f1xxxx_cs3_03.s new file mode 100644 index 0000000000..2d3a6034d9 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/Device/Holtek/HT32F1xxxx/Source/CodeSourcery/startup_ht32f1xxxx_cs3_03.s @@ -0,0 +1,370 @@ +/*---------------------------------------------------------------------------------------------------------*/ +/* Holtek Semiconductor Inc. */ +/* */ +/* Copyright (C) Holtek Semiconductor Inc. */ +/* All rights reserved. */ +/* */ +/*----------------------------------------------------------------------------------------------------------- +; File Name : startup_ht32f1xxxx_cs3_03.s +; Version : $Rev:: 1771 $ +; Date : $Date:: 2019-07-25 #$ +; Description : Startup code. +;-----------------------------------------------------------------------------------------------------------*/ + +/* +; Supported Device +; ======================================== +; HT32F12364 +*/ + +;/* <<< Use Configuration Wizard in Context Menu >>> */ +/* +;// HT32 Device +;// <0=> By Project Asm Define +;// <16=> HT32F12364 +*/ + .equ USE_HT32_CHIP_SET, 0 + + .equ _HT32FWID, 0xFFFFFFFF +/* + .equ _HT32FWID, 0x00012364 +*/ + + .equ HT32F12364, 16 + + .if USE_HT32_CHIP_SET == 0 + .else + .equ USE_HT32_CHIP, USE_HT32_CHIP_SET + .endif + +/* +; Amount of memory (in bytes) allocated for Stack and Heap +; Tailor those values to your application needs +;// Stack Size (in Bytes, must 8 byte aligned) <:8> +*/ + .equ Stack_Size, 512 + .section ".stack", "w" + .align 3 + .globl __cs3_stack_mem + .globl __cs3_stack + .globl __cs3_stack_size + .globl __HT_check_sp +__HT_check_sp: +__cs3_stack_mem: + .if Stack_Size + .space Stack_Size + .endif +__cs3_stack: + .size __cs3_stack_mem, . - __cs3_stack_mem + .set __cs3_stack_size, . - __cs3_stack_mem + +/* +;// Heap Size (in Bytes) <:8> +*/ + .equ Heap_Size, 0 + .section ".heap", "w" + .align 3 + .globl __cs3_heap_start + .globl __cs3_heap_end + .globl __HT_check_heap +__HT_check_heap: +__cs3_heap_start: + .if Heap_Size + .space Heap_Size + .endif +__cs3_heap_end: + + .equ _RESERVED, 0xFFFFFFFF +/* +;******************************************************************************* +; Fill-up the Vector Table entries with the exceptions ISR address +;********************************************************************************/ + .section ".cs3.interrupt_vector" + .globl __cs3_interrupt_vector_cortex_m + .type __cs3_interrupt_vector_cortex_m, %object +__cs3_interrupt_vector_cortex_m: + .long __cs3_stack /* ---, 00, 0x000, Top address of Stack */ + .long __cs3_reset /* ---, 01, 0x004, Reset Handler */ + .long NMI_Handler /* ---, 02, 0x008, NMI Handler */ + .long HardFault_Handler /* ---, 03, 0x00C, Hard Fault Handler */ + .long MemManage_Handler /* ---, 04, 0x010, MPU Fault Handler */ + .long BusFault_Handler /* ---, 05, 0x014, Bus Fault Handler */ + .long UsageFault_Handler /* ---, 06, 0x018, Usage Fault Handler */ + .long _RESERVED /* ---, 07, 0x01C, Reserved */ + .long _HT32FWID /* ---, 08, 0x020, Reserved */ + .long _RESERVED /* ---, 09, 0x024, Reserved */ + .long _RESERVED /* ---, 10, 0x028, Reserved */ + .long SVC_Handler /* ---, 11, 0x02C, SVC Handler */ + .long DebugMon_Handler /* ---, 12, 0x030, Debug Monitor Handler */ + .long _RESERVED /* ---, 13, 0x034, Reserved */ + .long PendSV_Handler /* ---, 14, 0x038, PendSV Handler */ + .long SysTick_Handler /* ---, 15, 0x03C, SysTick Handler */ + + /* External Interrupt Handler */ + .long CKRDY_IRQHandler /* 00, 16, 0x040, */ + .long LVD_IRQHandler /* 01, 17, 0x044, */ + .long BOD_IRQHandler /* 02, 18, 0x048, */ + .long _RESERVED /* 03, 19, 0x04C, */ + .long RTC_IRQHandler /* 04, 20, 0x050, */ + .long FLASH_IRQHandler /* 05, 21, 0x054, */ + .long EVWUP_IRQHandler /* 06, 22, 0x058, */ + .long LPWUP_IRQHandler /* 07, 23, 0x05C, */ + .long EXTI0_IRQHandler /* 08, 24, 0x060, */ + .long EXTI1_IRQHandler /* 09, 25, 0x064, */ + .long EXTI2_IRQHandler /* 10, 26, 0x068, */ + .long EXTI3_IRQHandler /* 11, 27, 0x06C, */ + .long EXTI4_IRQHandler /* 12, 28, 0x070, */ + .long EXTI5_IRQHandler /* 13, 29, 0x074, */ + .long EXTI6_IRQHandler /* 14, 30, 0x078, */ + .long EXTI7_IRQHandler /* 15, 31, 0x07C, */ + .long EXTI8_IRQHandler /* 16, 32, 0x080, */ + .long EXTI9_IRQHandler /* 17, 33, 0x084, */ + .long EXTI10_IRQHandler /* 18, 34, 0x088, */ + .long EXTI11_IRQHandler /* 19, 35, 0x08C, */ + .long EXTI12_IRQHandler /* 20, 36, 0x090, */ + .long EXTI13_IRQHandler /* 21, 37, 0x094, */ + .long EXTI14_IRQHandler /* 22, 38, 0x098, */ + .long EXTI15_IRQHandler /* 23, 39, 0x09C, */ + .long _RESERVED /* 24, 40, 0x0A0, */ + .long ADC_IRQHandler /* 25, 41, 0x0A4, */ + .long _RESERVED /* 26, 42, 0x0A8, */ + .long _RESERVED /* 27, 43, 0x0AC, */ + .long _RESERVED /* 28, 44, 0x0B0, */ + .long _RESERVED /* 29, 45, 0x0B4, */ + .long _RESERVED /* 30, 46, 0x0B8, */ + .long _RESERVED /* 31, 47, 0x0BC, */ + .long _RESERVED /* 32, 48, 0x0C0, */ + .long _RESERVED /* 33, 49, 0x0C4, */ + .long _RESERVED /* 34, 50, 0x0C8, */ + .long GPTM0_IRQHandler /* 35, 51, 0x0CC, */ + .long _RESERVED /* 36, 52, 0x0D0, */ + .long SCTM0_IRQHandler /* 37, 53, 0x0D4, */ + .long SCTM1_IRQHandler /* 38, 54, 0x0D8, */ + .long PWM0_IRQHandler /* 39, 55, 0x0DC, */ + .long _RESERVED /* 40, 56, 0x0E0, */ + .long BFTM0_IRQHandler /* 41, 57, 0x0E4, */ + .long BFTM1_IRQHandler /* 42, 58, 0x0E8, */ + .long I2C0_IRQHandler /* 43, 59, 0x0EC, */ + .long I2C1_IRQHandler /* 44, 60, 0x0F0, */ + .long SPI0_IRQHandler /* 45, 61, 0x0F4, */ + .long SPI1_IRQHandler /* 46, 62, 0x0F8, */ + .long USART0_IRQHandler /* 47, 63, 0x0FC, */ + .long _RESERVED /* 48, 64, 0x100, */ + .long UART0_IRQHandler /* 49, 65, 0x104, */ + .long UART1_IRQHandler /* 50, 66, 0x108, */ + .long SCI_IRQHandler /* 51, 67, 0x10C, */ + .long _RESERVED /* 52, 68, 0x110, */ + .long USB_IRQHandler /* 53, 69, 0x114, */ + .long _RESERVED /* 54, 70, 0x118, */ + .long PDMA_CH0_IRQHandler /* 55, 71, 0x11C, */ + .long PDMA_CH1_IRQHandler /* 56, 72, 0x120, */ + .long PDMA_CH2_IRQHandler /* 57, 73, 0x124, */ + .long PDMA_CH3_IRQHandler /* 58, 74, 0x128, */ + .long PDMA_CH4_IRQHandler /* 59, 75, 0x12C, */ + .long PDMA_CH5_IRQHandler /* 60, 76, 0x130, */ + .long _RESERVED /* 61, 77, 0x134, */ + .long _RESERVED /* 62, 78, 0x138, */ + .long _RESERVED /* 63, 79, 0x13C, */ + .long _RESERVED /* 64, 80, 0x140, */ + .long _RESERVED /* 65, 81, 0x144, */ + .long _RESERVED /* 66, 82, 0x148, */ + .long _RESERVED /* 67, 83, 0x14C, */ + .long _RESERVED /* 68, 84, 0x150, */ + .long AES_IRQHandler /* 69, 85, 0x154, */ + + .size __cs3_interrupt_vector_cortex_m, . - __cs3_interrupt_vector_cortex_m + + + .thumb + + +/* Reset Handler */ + + .section .cs3.reset,"x",%progbits + .thumb_func + .globl __cs3_reset_cortex_m + .type __cs3_reset_cortex_m, %function +__cs3_reset_cortex_m: + .fnstart + LDR R0, =BootProcess + BLX R0 + LDR R0, =SystemInit + BLX R0 + LDR R0, =_start + BX R0 + .thumb_func +BootProcess: + LDR R0, =0x40080300 + LDR R1,[R0, #0x10] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x14] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x18] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x1C] + CMP R1, #0 + BEQ BP2 +BP1: + LDR R0, =0x40080180 + LDR R1,[R0, #0xC] + LSL R1, R1, #4 + LSR R1, R1, #20 + CMP R1, #0 + BEQ BP3 + CMP R1, #1 + BEQ BP3 + CMP R1, #2 + BEQ BP3 +BP2: + DSB + LDR R0, =0x20000000 + LDR R1, =0x05fa0004 + STR R1, [R0] + LDR R1, =0xe000ed00 + LDR R0, =0x05fa0004 + STR R0, [R1, #0xC] + DSB + B . +BP3: + LDR R0, =0x20000000 + LDR R1, [R0] + LDR R0, =0x05fa0004 + CMP R0, R1 + BEQ BP4 + BX LR +BP4: + LDR R0, =0x40088100 + LDR R1, =0x00000001 + STR R1, [R0] + LDR R0, =0x20000000 + LDR R1, =0x0 + STR R1, [R0] + BX LR + .pool + .cantunwind + .fnend + .size __cs3_reset_cortex_m,.-__cs3_reset_cortex_m + + .section ".text" + +/* Exception Handlers */ + + .weak NMI_Handler + .type NMI_Handler, %function +NMI_Handler: + B . + .size NMI_Handler, . - NMI_Handler + + .weak HardFault_Handler + .type HardFault_Handler, %function +HardFault_Handler: + B . + .size HardFault_Handler, . - HardFault_Handler + + .weak MemManage_Handler + .type MemManage_Handler, %function +MemManage_Handler: + B . + .size MemManage_Handler, . - MemManage_Handler + + .weak BusFault_Handler + .type BusFault_Handler, %function +BusFault_Handler: + B . + .size BusFault_Handler, . - BusFault_Handler + + .weak UsageFault_Handler + .type UsageFault_Handler, %function +UsageFault_Handler: + B . + .size UsageFault_Handler, . - UsageFault_Handler + + .weak SVC_Handler + .type SVC_Handler, %function +SVC_Handler: + B . + .size SVC_Handler, . - SVC_Handler + + .weak DebugMon_Handler + .type DebugMon_Handler, %function +DebugMon_Handler: + B . + .size DebugMon_Handler, . - DebugMon_Handler + + .weak PendSV_Handler + .type PendSV_Handler, %function +PendSV_Handler: + B . + .size PendSV_Handler, . - PendSV_Handler + + .weak SysTick_Handler + .type SysTick_Handler, %function +SysTick_Handler: + B . + .size SysTick_Handler, . - SysTick_Handler + + +/* IRQ Handlers */ + + .globl Default_Handler + .type Default_Handler, %function +Default_Handler: + B . + .size Default_Handler, . - Default_Handler + + .macro IRQ handler + .weak \handler + .set \handler, Default_Handler + .endm + + IRQ CKRDY_IRQHandler + IRQ LVD_IRQHandler + IRQ BOD_IRQHandler + IRQ RTC_IRQHandler + IRQ FLASH_IRQHandler + IRQ EVWUP_IRQHandler + IRQ LPWUP_IRQHandler + IRQ EXTI0_IRQHandler + IRQ EXTI1_IRQHandler + IRQ EXTI2_IRQHandler + IRQ EXTI3_IRQHandler + IRQ EXTI4_IRQHandler + IRQ EXTI5_IRQHandler + IRQ EXTI6_IRQHandler + IRQ EXTI7_IRQHandler + IRQ EXTI8_IRQHandler + IRQ EXTI9_IRQHandler + IRQ EXTI10_IRQHandler + IRQ EXTI11_IRQHandler + IRQ EXTI12_IRQHandler + IRQ EXTI13_IRQHandler + IRQ EXTI14_IRQHandler + IRQ EXTI15_IRQHandler + IRQ ADC_IRQHandler + IRQ GPTM0_IRQHandler + IRQ SCTM0_IRQHandler + IRQ SCTM1_IRQHandler + IRQ PWM0_IRQHandler + IRQ BFTM0_IRQHandler + IRQ BFTM1_IRQHandler + IRQ I2C0_IRQHandler + IRQ I2C1_IRQHandler + IRQ SPI0_IRQHandler + IRQ SPI1_IRQHandler + IRQ USART0_IRQHandler + IRQ UART0_IRQHandler + IRQ UART1_IRQHandler + IRQ SCI_IRQHandler + IRQ USB_IRQHandler + IRQ PDMA_CH0_IRQHandler + IRQ PDMA_CH1_IRQHandler + IRQ PDMA_CH2_IRQHandler + IRQ PDMA_CH3_IRQHandler + IRQ PDMA_CH4_IRQHandler + IRQ PDMA_CH5_IRQHandler + IRQ AES_IRQHandler + + .end diff --git a/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/Device/Holtek/HT32F1xxxx/Source/GCC/startup_ht32f1xxxx_gcc_01.s b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/Device/Holtek/HT32F1xxxx/Source/GCC/startup_ht32f1xxxx_gcc_01.s new file mode 100644 index 0000000000..623ce3b725 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/Device/Holtek/HT32F1xxxx/Source/GCC/startup_ht32f1xxxx_gcc_01.s @@ -0,0 +1,485 @@ +/*---------------------------------------------------------------------------------------------------------*/ +/* Holtek Semiconductor Inc. */ +/* */ +/* Copyright (C) Holtek Semiconductor Inc. */ +/* All rights reserved. */ +/* */ +/*----------------------------------------------------------------------------------------------------------- +; File Name : startup_ht32f1xxxx_gcc_01.s +; Version : $Rev:: 1578 $ +; Date : $Date:: 2019-03-29 #$ +; Description : Startup code. +;-----------------------------------------------------------------------------------------------------------*/ + +/* +; Supported Device +; ======================================== +; HT32F1653, HT32F1654 +; HT32F1655, HT32F1656 +; HT32F12365, HT32F12366 +; HT32F12345 +*/ + +;/* <<< Use Configuration Wizard in Context Menu >>> */ +/* +;// HT32 Device +;// <0=> By Project Asm Define +;// <1=> HT32F1653/1654/1655/1656 +;// <2=> HT32F12365/12366 +;// <3=> HT32F12345 +*/ + .equ USE_HT32_CHIP_SET, 0 + + .equ _HT32FWID, 0xFFFFFFFF +/* + .equ _HT32FWID, 0x00012366 +*/ + + .equ HT32F1653_54_55_56, 1 + .equ HT32F12365_66, 2 + .equ HT32F12345, 3 + + .if USE_HT32_CHIP_SET == 0 + .else + .equ USE_HT32_CHIP, USE_HT32_CHIP_SET + .endif + + .syntax unified + .cpu cortex-m3 + .fpu softvfp + .thumb + +/* start address for the initialization values of the .data section. defined in linker script */ +.word _sidata + +/* start address for the .data section. defined in linker script */ +.word _sdata + +/* end address for the .data section. defined in linker script */ +.word _edata + +/* start address for the .bss section. defined in linker script */ +.word _sbss + +/* end address for the .bss section. defined in linker script */ +.word _ebss + + +/* +; Amount of memory (in bytes) allocated for Stack and Heap +; Tailor those values to your application needs +;// Stack Size (in Bytes, must 8 byte aligned) <:8> +*/ + .equ Stack_Size, 512 + .section ".stack", "w" + .align 3 + .globl __StackTop + .globl __StackLimit + .globl __HT_check_sp +__HT_check_sp: +__StackLimit: + .if Stack_Size + .space Stack_Size + .endif + .size __StackLimit, . - __StackLimit +__StackTop: + .size __StackTop, . - __StackTop + +/* +;// Heap Size (in Bytes) <:8> +*/ + .equ Heap_Size, 0 + .section ".heap", "w" + .align 3 + .globl __HeapBase + .globl _end + .globl __HeapLimit + .globl __HT_check_heap +__HT_check_heap: +__HeapBase: +_end: + .if Heap_Size + .space Heap_Size + .endif + .size __HeapBase, . - __HeapBase +__HeapLimit: + .size __HeapLimit, . - __HeapLimit + + .equ _RESERVED, 0xFFFFFFFF +/* +;******************************************************************************* +; Fill-up the Vector Table entries with the exceptions ISR address +;********************************************************************************/ + .section .isr_vector,"a",%progbits + .global __interrupt_vector_cortex_m + .type __interrupt_vector_cortex_m, %object +__interrupt_vector_cortex_m: + .long __StackTop /* ---, 00, 0x000, Top address of Stack */ + .long Reset_Handler /* ---, 01, 0x004, Reset Handler */ + .long NMI_Handler /* ---, 02, 0x008, NMI Handler */ + .long HardFault_Handler /* ---, 03, 0x00C, Hard Fault Handler */ + .long MemManage_Handler /* ---, 04, 0x010, MPU Fault Handler */ + .long BusFault_Handler /* ---, 05, 0x014, Bus Fault Handler */ + .long UsageFault_Handler /* ---, 06, 0x018, Usage Fault Handler */ + .long _RESERVED /* ---, 07, 0x01C, Reserved */ + .long _HT32FWID /* ---, 08, 0x020, Reserved */ + .long _RESERVED /* ---, 09, 0x024, Reserved */ + .long _RESERVED /* ---, 10, 0x028, Reserved */ + .long SVC_Handler /* ---, 11, 0x02C, SVC Handler */ + .long DebugMon_Handler /* ---, 12, 0x030, Debug Monitor Handler */ + .long _RESERVED /* ---, 13, 0x034, Reserved */ + .long PendSV_Handler /* ---, 14, 0x038, PendSV Handler */ + .long SysTick_Handler /* ---, 15, 0x03C, SysTick Handler */ + + /* External Interrupt Handler */ + .long CKRDY_IRQHandler /* 00, 16, 0x040, */ + .long LVD_IRQHandler /* 01, 17, 0x044, */ + .long BOD_IRQHandler /* 02, 18, 0x048, */ + .if (USE_HT32_CHIP==HT32F1653_54_55_56) + .long WDT_IRQHandler /* 03, 19, 0x04C, */ + .else + .long _RESERVED /* 03, 19, 0x04C, */ + .endif + .long RTC_IRQHandler /* 04, 20, 0x050, */ + .long FLASH_IRQHandler /* 05, 21, 0x054, */ + .long EVWUP_IRQHandler /* 06, 22, 0x058, */ + .long LPWUP_IRQHandler /* 07, 23, 0x05C, */ + .long EXTI0_IRQHandler /* 08, 24, 0x060, */ + .long EXTI1_IRQHandler /* 09, 25, 0x064, */ + .long EXTI2_IRQHandler /* 10, 26, 0x068, */ + .long EXTI3_IRQHandler /* 11, 27, 0x06C, */ + .long EXTI4_IRQHandler /* 12, 28, 0x070, */ + .long EXTI5_IRQHandler /* 13, 29, 0x074, */ + .long EXTI6_IRQHandler /* 14, 30, 0x078, */ + .long EXTI7_IRQHandler /* 15, 31, 0x07C, */ + .long EXTI8_IRQHandler /* 16, 32, 0x080, */ + .long EXTI9_IRQHandler /* 17, 33, 0x084, */ + .long EXTI10_IRQHandler /* 18, 34, 0x088, */ + .long EXTI11_IRQHandler /* 19, 35, 0x08C, */ + .long EXTI12_IRQHandler /* 20, 36, 0x090, */ + .long EXTI13_IRQHandler /* 21, 37, 0x094, */ + .long EXTI14_IRQHandler /* 22, 38, 0x098, */ + .long EXTI15_IRQHandler /* 23, 39, 0x09C, */ + .long COMP_IRQHandler /* 24, 40, 0x0A0, */ + .long ADC_IRQHandler /* 25, 41, 0x0A4, */ + .long _RESERVED /* 26, 42, 0x0A8, */ + .long MCTM0BRK_IRQHandler /* 27, 43, 0x0AC, */ + .long MCTM0UP_IRQHandler /* 28, 44, 0x0B0, */ + .long MCTM0TR_IRQHandler /* 29, 45, 0x0B4, */ + .long MCTM0CC_IRQHandler /* 30, 46, 0x0B8, */ + .long MCTM1BRK_IRQHandler /* 31, 47, 0x0BC, */ + .long MCTM1UP_IRQHandler /* 32, 48, 0x0C0, */ + .long MCTM1TR_IRQHandler /* 33, 49, 0x0C4, */ + .long MCTM1CC_IRQHandler /* 34, 50, 0x0C8, */ + .long GPTM0_IRQHandler /* 35, 51, 0x0CC, */ + .long GPTM1_IRQHandler /* 36, 52, 0x0D0, */ + .long _RESERVED /* 37, 53, 0x0D4, */ + .long _RESERVED /* 38, 54, 0x0D8, */ + .long _RESERVED /* 39, 55, 0x0DC, */ + .long _RESERVED /* 40, 56, 0x0E0, */ + .long BFTM0_IRQHandler /* 41, 57, 0x0E4, */ + .long BFTM1_IRQHandler /* 42, 58, 0x0E8, */ + .long I2C0_IRQHandler /* 43, 59, 0x0EC, */ + .long I2C1_IRQHandler /* 44, 60, 0x0F0, */ + .long SPI0_IRQHandler /* 45, 61, 0x0F4, */ + .long SPI1_IRQHandler /* 46, 62, 0x0F8, */ + .long USART0_IRQHandler /* 47, 63, 0x0FC, */ + .long USART1_IRQHandler /* 48, 64, 0x100, */ + .long UART0_IRQHandler /* 49, 65, 0x104, */ + .long UART1_IRQHandler /* 50, 66, 0x108, */ + .if (USE_HT32_CHIP==HT32F12345) + .long _RESERVED /* 51, 67, 0x10C, */ + .else + .long SCI_IRQHandler /* 51, 67, 0x10C, */ + .endif + .long I2S_IRQHandler /* 52, 68, 0x110, */ + .long USB_IRQHandler /* 53, 69, 0x114, */ + .if (USE_HT32_CHIP==HT32F1653_54_55_56) + .long _RESERVED /* 54, 70, 0x118, */ + .else + .long SDIO_IRQHandler /* 54, 70, 0x118, */ + .endif + .long PDMA_CH0_IRQHandler /* 55, 71, 0x11C, */ + .long PDMA_CH1_IRQHandler /* 56, 72, 0x120, */ + .long PDMA_CH2_IRQHandler /* 57, 73, 0x124, */ + .long PDMA_CH3_IRQHandler /* 58, 74, 0x128, */ + .long PDMA_CH4_IRQHandler /* 59, 75, 0x12C, */ + .long PDMA_CH5_IRQHandler /* 60, 76, 0x130, */ + .long PDMA_CH6_IRQHandler /* 61, 77, 0x134, */ + .long PDMA_CH7_IRQHandler /* 62, 78, 0x138, */ + .if (USE_HT32_CHIP==HT32F1653_54_55_56) + .long _RESERVED /* 63, 79, 0x13C, */ + .long _RESERVED /* 64, 80, 0x140, */ + .long _RESERVED /* 65, 81, 0x144, */ + .long _RESERVED /* 66, 82, 0x148, */ + .else + .long PDMA_CH8_IRQHandler /* 63, 79, 0x13C, */ + .long PDMA_CH9_IRQHandler /* 64, 80, 0x140, */ + .long PDMA_CH10_IRQHandler /* 65, 81, 0x144, */ + .long PDMA_CH11_IRQHandler /* 66, 82, 0x148, */ + .endif + .if (USE_HT32_CHIP==HT32F12365_66) + .long CSIF_IRQHandler /* 67, 83, 0x14C, */ + .else + .long _RESERVED /* 67, 83, 0x14C, */ + .endif + .long EBI_IRQHandler /* 68, 84, 0x150, */ + .if (USE_HT32_CHIP==HT32F12365_66) + .long AES_IRQHandler /* 69, 85, 0x154, */ + .endif + + .size __interrupt_vector_cortex_m, . - __interrupt_vector_cortex_m + + + .thumb + + +/* Reset Handler */ + + .section .text.Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + LDR R0, =__StackTop /* set stack pointer */ + MOV SP, R0 + .if (USE_HT32_CHIP==HT32F1653_54_55_56) + .else + LDR R0, =BootProcess + BLX R0 + .endif + LDR R0, =SystemInit + BLX R0 + + /* Copy the data segment initializers from flash to SRAM */ + MOVS R1, #0 + B LoopCopyDataInit + +CopyDataInit: + LDR R3, =_sidata + LDR R3, [R3, R1] + STR R3, [R0, R1] + ADDS R1, R1, #4 + +LoopCopyDataInit: + LDR R0, =_sdata + LDR R3, =_edata + ADDS R2, R0, R1 + CMP R2, R3 + BCC CopyDataInit + LDR R2, =_sbss + B LoopFillZerobss + +/* Zero fill the bss segment. */ +FillZerobss: + MOVS R3, #0 + STR R3, [R2] + ADDS R2, R2, #4 + +LoopFillZerobss: + LDR R3, =_ebss + CMP R2, R3 + BCC FillZerobss + + /* Call static constructors */ + BL __libc_init_array + + /* Call the application's entry point.*/ + BL main + +LoopForever: + B LoopForever + + .if (USE_HT32_CHIP==HT32F1653_54_55_56) + .else + .thumb_func +BootProcess: + LDR R0, =0x40080300 + LDR R1,[R0, #0x10] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x14] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x18] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x1C] + CMP R1, #0 + BEQ BP2 +BP1: + LDR R0, =0x40080180 + LDR R1,[R0, #0xC] + LSLS R1, R1, #4 + LSRS R1, R1, #20 + CMP R1, #0 + BEQ BP3 + CMP R1, #1 + BEQ BP3 + CMP R1, #2 + BEQ BP3 +BP2: + DSB + LDR R0, =0x20000000 + LDR R1, =0x05fa0004 + STR R1, [R0] + LDR R1, =0xe000ed00 + LDR R0, =0x05fa0004 + STR R0, [R1, #0xC] + DSB + B . +BP3: + LDR R0, =0x20000000 + LDR R1, [R0] + LDR R0, =0x05fa0004 + CMP R0, R1 + BEQ BP4 + BX LR +BP4: + LDR R0, =0x40088100 + LDR R1, =0x00000001 + STR R1, [R0] + LDR R0, =0x20000000 + LDR R1, =0x0 + STR R1, [R0] + BX LR + .endif + + .size Reset_Handler, .-Reset_Handler + +/* Exception Handlers */ + + .weak NMI_Handler + .type NMI_Handler, %function +NMI_Handler: + B . + .size NMI_Handler, . - NMI_Handler + + .weak HardFault_Handler + .type HardFault_Handler, %function +HardFault_Handler: + B . + .size HardFault_Handler, . - HardFault_Handler + + .weak MemManage_Handler + .type MemManage_Handler, %function +MemManage_Handler: + B . + .size MemManage_Handler, . - MemManage_Handler + + .weak BusFault_Handler + .type BusFault_Handler, %function +BusFault_Handler: + B . + .size BusFault_Handler, . - BusFault_Handler + + .weak UsageFault_Handler + .type UsageFault_Handler, %function +UsageFault_Handler: + B . + .size UsageFault_Handler, . - UsageFault_Handler + + .weak SVC_Handler + .type SVC_Handler, %function +SVC_Handler: + B . + .size SVC_Handler, . - SVC_Handler + + .weak DebugMon_Handler + .type DebugMon_Handler, %function +DebugMon_Handler: + B . + .size DebugMon_Handler, . - DebugMon_Handler + + .weak PendSV_Handler + .type PendSV_Handler, %function +PendSV_Handler: + B . + .size PendSV_Handler, . - PendSV_Handler + + .weak SysTick_Handler + .type SysTick_Handler, %function +SysTick_Handler: + B . + .size SysTick_Handler, . - SysTick_Handler + + +/* IRQ Handlers */ + + .globl Default_Handler + .type Default_Handler, %function +Default_Handler: + B . + .size Default_Handler, . - Default_Handler + + .macro IRQ handler + .weak \handler + .set \handler, Default_Handler + .endm + + IRQ CKRDY_IRQHandler + IRQ LVD_IRQHandler + IRQ BOD_IRQHandler + IRQ WDT_IRQHandler + IRQ RTC_IRQHandler + IRQ FLASH_IRQHandler + IRQ EVWUP_IRQHandler + IRQ LPWUP_IRQHandler + IRQ EXTI0_IRQHandler + IRQ EXTI1_IRQHandler + IRQ EXTI2_IRQHandler + IRQ EXTI3_IRQHandler + IRQ EXTI4_IRQHandler + IRQ EXTI5_IRQHandler + IRQ EXTI6_IRQHandler + IRQ EXTI7_IRQHandler + IRQ EXTI8_IRQHandler + IRQ EXTI9_IRQHandler + IRQ EXTI10_IRQHandler + IRQ EXTI11_IRQHandler + IRQ EXTI12_IRQHandler + IRQ EXTI13_IRQHandler + IRQ EXTI14_IRQHandler + IRQ EXTI15_IRQHandler + IRQ COMP_IRQHandler + IRQ ADC_IRQHandler + IRQ MCTM0BRK_IRQHandler + IRQ MCTM0UP_IRQHandler + IRQ MCTM0TR_IRQHandler + IRQ MCTM0CC_IRQHandler + IRQ MCTM1BRK_IRQHandler + IRQ MCTM1UP_IRQHandler + IRQ MCTM1TR_IRQHandler + IRQ MCTM1CC_IRQHandler + IRQ GPTM0_IRQHandler + IRQ GPTM1_IRQHandler + IRQ BFTM0_IRQHandler + IRQ BFTM1_IRQHandler + IRQ I2C0_IRQHandler + IRQ I2C1_IRQHandler + IRQ SPI0_IRQHandler + IRQ SPI1_IRQHandler + IRQ USART0_IRQHandler + IRQ USART1_IRQHandler + IRQ UART0_IRQHandler + IRQ UART1_IRQHandler + IRQ SCI_IRQHandler + IRQ I2S_IRQHandler + IRQ USB_IRQHandler + IRQ SDIO_IRQHandler + IRQ PDMA_CH0_IRQHandler + IRQ PDMA_CH1_IRQHandler + IRQ PDMA_CH2_IRQHandler + IRQ PDMA_CH3_IRQHandler + IRQ PDMA_CH4_IRQHandler + IRQ PDMA_CH5_IRQHandler + IRQ PDMA_CH6_IRQHandler + IRQ PDMA_CH7_IRQHandler + IRQ PDMA_CH8_IRQHandler + IRQ PDMA_CH9_IRQHandler + IRQ PDMA_CH10_IRQHandler + IRQ PDMA_CH11_IRQHandler + IRQ CSIF_IRQHandler + IRQ EBI_IRQHandler + IRQ AES_IRQHandler + + .end diff --git a/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/Device/Holtek/HT32F1xxxx/Source/GCC/startup_ht32f1xxxx_gcc_03.s b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/Device/Holtek/HT32F1xxxx/Source/GCC/startup_ht32f1xxxx_gcc_03.s new file mode 100644 index 0000000000..652eb11061 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/Device/Holtek/HT32F1xxxx/Source/GCC/startup_ht32f1xxxx_gcc_03.s @@ -0,0 +1,428 @@ +/*---------------------------------------------------------------------------------------------------------*/ +/* Holtek Semiconductor Inc. */ +/* */ +/* Copyright (C) Holtek Semiconductor Inc. */ +/* All rights reserved. */ +/* */ +/*----------------------------------------------------------------------------------------------------------- +; File Name : startup_ht32f1xxxx_gcc_03.s +; Version : $Rev:: 1771 $ +; Date : $Date:: 2019-07-25 #$ +; Description : Startup code. +;-----------------------------------------------------------------------------------------------------------*/ + +/* +; Supported Device +; ======================================== +; HT32F12364 +*/ + +;/* <<< Use Configuration Wizard in Context Menu >>> */ +/* +;// HT32 Device +;// <0=> By Project Asm Define +;// <16=> HT32F12364 +*/ + .equ USE_HT32_CHIP_SET, 0 + + .equ _HT32FWID, 0xFFFFFFFF +/* + .equ _HT32FWID, 0x00012364 +*/ + + .equ HT32F12364, 16 + + .if USE_HT32_CHIP_SET == 0 + .else + .equ USE_HT32_CHIP, USE_HT32_CHIP_SET + .endif + + .syntax unified + .cpu cortex-m3 + .fpu softvfp + .thumb + +/* start address for the initialization values of the .data section. defined in linker script */ +.word _sidata + +/* start address for the .data section. defined in linker script */ +.word _sdata + +/* end address for the .data section. defined in linker script */ +.word _edata + +/* start address for the .bss section. defined in linker script */ +.word _sbss + +/* end address for the .bss section. defined in linker script */ +.word _ebss + + +/* +; Amount of memory (in bytes) allocated for Stack and Heap +; Tailor those values to your application needs +;// Stack Size (in Bytes, must 8 byte aligned) <:8> +*/ + .equ Stack_Size, 512 + .section ".stack", "w" + .align 3 + .globl __StackTop + .globl __StackLimit + .globl __HT_check_sp +__HT_check_sp: +__StackLimit: + .if Stack_Size + .space Stack_Size + .endif + .size __StackLimit, . - __StackLimit +__StackTop: + .size __StackTop, . - __StackTop + +/* +;// Heap Size (in Bytes) <:8> +*/ + .equ Heap_Size, 0 + .section ".heap", "w" + .align 3 + .globl __HeapBase + .globl _end + .globl __HeapLimit + .globl __HT_check_heap +__HT_check_heap: +__HeapBase: +_end: + .if Heap_Size + .space Heap_Size + .endif + .size __HeapBase, . - __HeapBase +__HeapLimit: + .size __HeapLimit, . - __HeapLimit + + .equ _RESERVED, 0xFFFFFFFF +/* +;******************************************************************************* +; Fill-up the Vector Table entries with the exceptions ISR address +;********************************************************************************/ + .section .isr_vector,"a",%progbits + .global __interrupt_vector_cortex_m + .type __interrupt_vector_cortex_m, %object +__interrupt_vector_cortex_m: + .long __StackTop /* ---, 00, 0x000, Top address of Stack */ + .long Reset_Handler /* ---, 01, 0x004, Reset Handler */ + .long NMI_Handler /* ---, 02, 0x008, NMI Handler */ + .long HardFault_Handler /* ---, 03, 0x00C, Hard Fault Handler */ + .long MemManage_Handler /* ---, 04, 0x010, MPU Fault Handler */ + .long BusFault_Handler /* ---, 05, 0x014, Bus Fault Handler */ + .long UsageFault_Handler /* ---, 06, 0x018, Usage Fault Handler */ + .long _RESERVED /* ---, 07, 0x01C, Reserved */ + .long _HT32FWID /* ---, 08, 0x020, Reserved */ + .long _RESERVED /* ---, 09, 0x024, Reserved */ + .long _RESERVED /* ---, 10, 0x028, Reserved */ + .long SVC_Handler /* ---, 11, 0x02C, SVC Handler */ + .long DebugMon_Handler /* ---, 12, 0x030, Debug Monitor Handler */ + .long _RESERVED /* ---, 13, 0x034, Reserved */ + .long PendSV_Handler /* ---, 14, 0x038, PendSV Handler */ + .long SysTick_Handler /* ---, 15, 0x03C, SysTick Handler */ + + /* External Interrupt Handler */ + .long CKRDY_IRQHandler /* 00, 16, 0x040, */ + .long LVD_IRQHandler /* 01, 17, 0x044, */ + .long BOD_IRQHandler /* 02, 18, 0x048, */ + .long _RESERVED /* 03, 19, 0x04C, */ + .long RTC_IRQHandler /* 04, 20, 0x050, */ + .long FLASH_IRQHandler /* 05, 21, 0x054, */ + .long EVWUP_IRQHandler /* 06, 22, 0x058, */ + .long LPWUP_IRQHandler /* 07, 23, 0x05C, */ + .long EXTI0_IRQHandler /* 08, 24, 0x060, */ + .long EXTI1_IRQHandler /* 09, 25, 0x064, */ + .long EXTI2_IRQHandler /* 10, 26, 0x068, */ + .long EXTI3_IRQHandler /* 11, 27, 0x06C, */ + .long EXTI4_IRQHandler /* 12, 28, 0x070, */ + .long EXTI5_IRQHandler /* 13, 29, 0x074, */ + .long EXTI6_IRQHandler /* 14, 30, 0x078, */ + .long EXTI7_IRQHandler /* 15, 31, 0x07C, */ + .long EXTI8_IRQHandler /* 16, 32, 0x080, */ + .long EXTI9_IRQHandler /* 17, 33, 0x084, */ + .long EXTI10_IRQHandler /* 18, 34, 0x088, */ + .long EXTI11_IRQHandler /* 19, 35, 0x08C, */ + .long EXTI12_IRQHandler /* 20, 36, 0x090, */ + .long EXTI13_IRQHandler /* 21, 37, 0x094, */ + .long EXTI14_IRQHandler /* 22, 38, 0x098, */ + .long EXTI15_IRQHandler /* 23, 39, 0x09C, */ + .long _RESERVED /* 24, 40, 0x0A0, */ + .long ADC_IRQHandler /* 25, 41, 0x0A4, */ + .long _RESERVED /* 26, 42, 0x0A8, */ + .long _RESERVED /* 27, 43, 0x0AC, */ + .long _RESERVED /* 28, 44, 0x0B0, */ + .long _RESERVED /* 29, 45, 0x0B4, */ + .long _RESERVED /* 30, 46, 0x0B8, */ + .long _RESERVED /* 31, 47, 0x0BC, */ + .long _RESERVED /* 32, 48, 0x0C0, */ + .long _RESERVED /* 33, 49, 0x0C4, */ + .long _RESERVED /* 34, 50, 0x0C8, */ + .long GPTM0_IRQHandler /* 35, 51, 0x0CC, */ + .long _RESERVED /* 36, 52, 0x0D0, */ + .long SCTM0_IRQHandler /* 37, 53, 0x0D4, */ + .long SCTM1_IRQHandler /* 38, 54, 0x0D8, */ + .long PWM0_IRQHandler /* 39, 55, 0x0DC, */ + .long _RESERVED /* 40, 56, 0x0E0, */ + .long BFTM0_IRQHandler /* 41, 57, 0x0E4, */ + .long BFTM1_IRQHandler /* 42, 58, 0x0E8, */ + .long I2C0_IRQHandler /* 43, 59, 0x0EC, */ + .long I2C1_IRQHandler /* 44, 60, 0x0F0, */ + .long SPI0_IRQHandler /* 45, 61, 0x0F4, */ + .long SPI1_IRQHandler /* 46, 62, 0x0F8, */ + .long USART0_IRQHandler /* 47, 63, 0x0FC, */ + .long _RESERVED /* 48, 64, 0x100, */ + .long UART0_IRQHandler /* 49, 65, 0x104, */ + .long UART1_IRQHandler /* 50, 66, 0x108, */ + .long SCI_IRQHandler /* 51, 67, 0x10C, */ + .long _RESERVED /* 52, 68, 0x110, */ + .long USB_IRQHandler /* 53, 69, 0x114, */ + .long _RESERVED /* 54, 70, 0x118, */ + .long PDMA_CH0_IRQHandler /* 55, 71, 0x11C, */ + .long PDMA_CH1_IRQHandler /* 56, 72, 0x120, */ + .long PDMA_CH2_IRQHandler /* 57, 73, 0x124, */ + .long PDMA_CH3_IRQHandler /* 58, 74, 0x128, */ + .long PDMA_CH4_IRQHandler /* 59, 75, 0x12C, */ + .long PDMA_CH5_IRQHandler /* 60, 76, 0x130, */ + .long _RESERVED /* 61, 77, 0x134, */ + .long _RESERVED /* 62, 78, 0x138, */ + .long _RESERVED /* 63, 79, 0x13C, */ + .long _RESERVED /* 64, 80, 0x140, */ + .long _RESERVED /* 65, 81, 0x144, */ + .long _RESERVED /* 66, 82, 0x148, */ + .long _RESERVED /* 67, 83, 0x14C, */ + .long _RESERVED /* 68, 84, 0x150, */ + .long AES_IRQHandler /* 69, 85, 0x154, */ + + .size __interrupt_vector_cortex_m, . - __interrupt_vector_cortex_m + + + .thumb + + +/* Reset Handler */ + + .section .text.Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + LDR R0, =__StackTop /* set stack pointer */ + MOV SP, R0 + LDR R0, =BootProcess + BLX R0 + LDR R0, =SystemInit + BLX R0 + + /* Copy the data segment initializers from flash to SRAM */ + MOVS R1, #0 + B LoopCopyDataInit + +CopyDataInit: + LDR R3, =_sidata + LDR R3, [R3, R1] + STR R3, [R0, R1] + ADDS R1, R1, #4 + +LoopCopyDataInit: + LDR R0, =_sdata + LDR R3, =_edata + ADDS R2, R0, R1 + CMP R2, R3 + BCC CopyDataInit + LDR R2, =_sbss + B LoopFillZerobss + +/* Zero fill the bss segment. */ +FillZerobss: + MOVS R3, #0 + STR R3, [R2] + ADDS R2, R2, #4 + +LoopFillZerobss: + LDR R3, =_ebss + CMP R2, R3 + BCC FillZerobss + + /* Call static constructors */ + BL __libc_init_array + + /* Call the application's entry point.*/ + BL main + +LoopForever: + B LoopForever + + .thumb_func +BootProcess: + LDR R0, =0x40080300 + LDR R1,[R0, #0x10] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x14] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x18] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x1C] + CMP R1, #0 + BEQ BP2 +BP1: + LDR R0, =0x40080180 + LDR R1,[R0, #0xC] + LSLS R1, R1, #4 + LSRS R1, R1, #20 + CMP R1, #0 + BEQ BP3 + CMP R1, #1 + BEQ BP3 + CMP R1, #2 + BEQ BP3 +BP2: + DSB + LDR R0, =0x20000000 + LDR R1, =0x05fa0004 + STR R1, [R0] + LDR R1, =0xe000ed00 + LDR R0, =0x05fa0004 + STR R0, [R1, #0xC] + DSB + B . +BP3: + LDR R0, =0x20000000 + LDR R1, [R0] + LDR R0, =0x05fa0004 + CMP R0, R1 + BEQ BP4 + BX LR +BP4: + LDR R0, =0x40088100 + LDR R1, =0x00000001 + STR R1, [R0] + LDR R0, =0x20000000 + LDR R1, =0x0 + STR R1, [R0] + BX LR + + .size Reset_Handler, .-Reset_Handler + +/* Exception Handlers */ + + .weak NMI_Handler + .type NMI_Handler, %function +NMI_Handler: + B . + .size NMI_Handler, . - NMI_Handler + + .weak HardFault_Handler + .type HardFault_Handler, %function +HardFault_Handler: + B . + .size HardFault_Handler, . - HardFault_Handler + + .weak MemManage_Handler + .type MemManage_Handler, %function +MemManage_Handler: + B . + .size MemManage_Handler, . - MemManage_Handler + + .weak BusFault_Handler + .type BusFault_Handler, %function +BusFault_Handler: + B . + .size BusFault_Handler, . - BusFault_Handler + + .weak UsageFault_Handler + .type UsageFault_Handler, %function +UsageFault_Handler: + B . + .size UsageFault_Handler, . - UsageFault_Handler + + .weak SVC_Handler + .type SVC_Handler, %function +SVC_Handler: + B . + .size SVC_Handler, . - SVC_Handler + + .weak DebugMon_Handler + .type DebugMon_Handler, %function +DebugMon_Handler: + B . + .size DebugMon_Handler, . - DebugMon_Handler + + .weak PendSV_Handler + .type PendSV_Handler, %function +PendSV_Handler: + B . + .size PendSV_Handler, . - PendSV_Handler + + .weak SysTick_Handler + .type SysTick_Handler, %function +SysTick_Handler: + B . + .size SysTick_Handler, . - SysTick_Handler + + +/* IRQ Handlers */ + + .globl Default_Handler + .type Default_Handler, %function +Default_Handler: + B . + .size Default_Handler, . - Default_Handler + + .macro IRQ handler + .weak \handler + .set \handler, Default_Handler + .endm + + IRQ CKRDY_IRQHandler + IRQ LVD_IRQHandler + IRQ BOD_IRQHandler + IRQ RTC_IRQHandler + IRQ FLASH_IRQHandler + IRQ EVWUP_IRQHandler + IRQ LPWUP_IRQHandler + IRQ EXTI0_IRQHandler + IRQ EXTI1_IRQHandler + IRQ EXTI2_IRQHandler + IRQ EXTI3_IRQHandler + IRQ EXTI4_IRQHandler + IRQ EXTI5_IRQHandler + IRQ EXTI6_IRQHandler + IRQ EXTI7_IRQHandler + IRQ EXTI8_IRQHandler + IRQ EXTI9_IRQHandler + IRQ EXTI10_IRQHandler + IRQ EXTI11_IRQHandler + IRQ EXTI12_IRQHandler + IRQ EXTI13_IRQHandler + IRQ EXTI14_IRQHandler + IRQ EXTI15_IRQHandler + IRQ ADC_IRQHandler + IRQ GPTM0_IRQHandler + IRQ SCTM0_IRQHandler + IRQ SCTM1_IRQHandler + IRQ PWM0_IRQHandler + IRQ BFTM0_IRQHandler + IRQ BFTM1_IRQHandler + IRQ I2C0_IRQHandler + IRQ I2C1_IRQHandler + IRQ SPI0_IRQHandler + IRQ SPI1_IRQHandler + IRQ USART0_IRQHandler + IRQ UART0_IRQHandler + IRQ UART1_IRQHandler + IRQ SCI_IRQHandler + IRQ USB_IRQHandler + IRQ PDMA_CH0_IRQHandler + IRQ PDMA_CH1_IRQHandler + IRQ PDMA_CH2_IRQHandler + IRQ PDMA_CH3_IRQHandler + IRQ PDMA_CH4_IRQHandler + IRQ PDMA_CH5_IRQHandler + IRQ AES_IRQHandler + + .end diff --git a/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/Device/Holtek/HT32F1xxxx/Source/IAR/startup_ht32f1xxxx_iar_01.s b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/Device/Holtek/HT32F1xxxx/Source/IAR/startup_ht32f1xxxx_iar_01.s new file mode 100644 index 0000000000..331f561dc0 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/Device/Holtek/HT32F1xxxx/Source/IAR/startup_ht32f1xxxx_iar_01.s @@ -0,0 +1,416 @@ +;/*---------------------------------------------------------------------------------------------------------*/ +;/* Holtek Semiconductor Inc. */ +;/* */ +;/* Copyright (C) Holtek Semiconductor Inc. */ +;/* All rights reserved. */ +;/* */ +;/*----------------------------------------------------------------------------------------------------------- +; File Name : startup_ht32f1xxxx_iar_01.s +; Version : $Rev:: 1774 $ +; Date : $Date:: 2019-07-25 #$ +; Description : Startup code. +;-----------------------------------------------------------------------------------------------------------*/ + +; Supported Device +; ======================================== +; HT32F1653, HT32F1654 +; HT32F1655, HT32F1656 +; HT32F12365, HT32F12366 +; HT32F12345 + +;// HT32 Device +;// <0=> By Project Asm Define +;// <1=> HT32F1653/1654/1655/1656 +;// <2=> HT32F12365/12366 +;// <3=> HT32F12345 +USE_HT32_CHIP_SET EQU 0 + +_HT32FWID EQU 0xFFFFFFFF +;_HT32FWID EQU 0x00012366 + +HT32F1653_54_55_56 EQU 1 +HT32F12365_66 EQU 2 +HT32F12345 EQU 3 + + IF USE_HT32_CHIP_SET=0 + ELSE + #undef USE_HT32_CHIP + #define USE_HT32_CHIP USE_HT32_CHIP_SET + ENDIF + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + EXTERN SystemInit + PUBLIC __vector_table + +;******************************************************************************* +; Fill-up the Vector Table entries with the exceptions ISR address +;******************************************************************************* + DATA +_RESERVED EQU 0xFFFFFFFF +__vector_table + DCD sfe(CSTACK) ; ---, 00, 0x000, Top address of Stack + DCD Reset_Handler ; ---, 01, 0x004, Reset Handler + DCD NMI_Handler ; ---, 02, 0x008, NMI Handler + DCD HardFault_Handler ; ---, 03, 0x00C, Hard Fault Handler + DCD MemManage_Handler ; ---, 04, 0x010, Memory Management Fault Handler + DCD BusFault_Handler ; ---, 05, 0x014, Bus Fault Handler + DCD UsageFault_Handler ; ---, 06, 0x018, Usage Fault Handler + DCD _RESERVED ; ---, 07, 0x01C, Reserved + DCD _HT32FWID ; ---, 08, 0x020, Reserved + DCD _RESERVED ; ---, 09, 0x024, Reserved + DCD _RESERVED ; ---, 10, 0x028, Reserved + DCD SVC_Handler ; ---, 11, 0x02C, SVC Handler + DCD DebugMon_Handler ; ---, 12, 0x030, Debug Monitor Handler + DCD _RESERVED ; ---, 13, 0x034, Reserved + DCD PendSV_Handler ; ---, 14, 0x038, PendSV Handler + DCD SysTick_Handler ; ---, 15, 0x03C, SysTick Handler + + ; External Interrupt Handler + DCD CKRDY_IRQHandler ; 00, 16, 0x040, + DCD LVD_IRQHandler ; 01, 17, 0x044, + DCD BOD_IRQHandler ; 02, 18, 0x048, + IF (USE_HT32_CHIP=HT32F1653_54_55_56) + DCD WDT_IRQHandler ; 03, 19, 0x04C, + ELSE + DCD _RESERVED ; 03, 19, 0x04C, + ENDIF + DCD RTC_IRQHandler ; 04, 20, 0x050, + DCD FLASH_IRQHandler ; 05, 21, 0x054, + DCD EVWUP_IRQHandler ; 06, 22, 0x058, + DCD LPWUP_IRQHandler ; 07, 23, 0x05C, + DCD EXTI0_IRQHandler ; 08, 24, 0x060, + DCD EXTI1_IRQHandler ; 09, 25, 0x064, + DCD EXTI2_IRQHandler ; 10, 26, 0x068, + DCD EXTI3_IRQHandler ; 11, 27, 0x06C, + DCD EXTI4_IRQHandler ; 12, 28, 0x070, + DCD EXTI5_IRQHandler ; 13, 29, 0x074, + DCD EXTI6_IRQHandler ; 14, 30, 0x078, + DCD EXTI7_IRQHandler ; 15, 31, 0x07C, + DCD EXTI8_IRQHandler ; 16, 32, 0x080, + DCD EXTI9_IRQHandler ; 17, 33, 0x084, + DCD EXTI10_IRQHandler ; 18, 34, 0x088, + DCD EXTI11_IRQHandler ; 19, 35, 0x08C, + DCD EXTI12_IRQHandler ; 20, 36, 0x090, + DCD EXTI13_IRQHandler ; 21, 37, 0x094, + DCD EXTI14_IRQHandler ; 22, 38, 0x098, + DCD EXTI15_IRQHandler ; 23, 39, 0x09C, + DCD COMP_IRQHandler ; 24, 40, 0x0A0, + DCD ADC_IRQHandler ; 25, 41, 0x0A4, + DCD _RESERVED ; 26, 42, 0x0A8, + DCD MCTM0BRK_IRQHandler ; 27, 43, 0x0AC, + DCD MCTM0UP_IRQHandler ; 28, 44, 0x0B0, + DCD MCTM0TR_IRQHandler ; 29, 45, 0x0B4, + DCD MCTM0CC_IRQHandler ; 30, 46, 0x0B8, + DCD MCTM1BRK_IRQHandler ; 31, 47, 0x0BC, + DCD MCTM1UP_IRQHandler ; 32, 48, 0x0C0, + DCD MCTM1TR_IRQHandler ; 33, 49, 0x0C4, + DCD MCTM1CC_IRQHandler ; 34, 50, 0x0C8, + DCD GPTM0_IRQHandler ; 35, 51, 0x0CC, + DCD GPTM1_IRQHandler ; 36, 52, 0x0D0, + DCD _RESERVED ; 37, 53, 0x0D4, + DCD _RESERVED ; 38, 54, 0x0D8, + DCD _RESERVED ; 39, 55, 0x0DC, + DCD _RESERVED ; 40, 56, 0x0E0, + DCD BFTM0_IRQHandler ; 41, 57, 0x0E4, + DCD BFTM1_IRQHandler ; 42, 58, 0x0E8, + DCD I2C0_IRQHandler ; 43, 59, 0x0EC, + DCD I2C1_IRQHandler ; 44, 60, 0x0F0, + DCD SPI0_IRQHandler ; 45, 61, 0x0F4, + DCD SPI1_IRQHandler ; 46, 62, 0x0F8, + DCD USART0_IRQHandler ; 47, 63, 0x0FC, + DCD USART1_IRQHandler ; 48, 64, 0x100, + DCD UART0_IRQHandler ; 49, 65, 0x104, + DCD UART1_IRQHandler ; 50, 66, 0x108, + IF (USE_HT32_CHIP=HT32F12345) + DCD _RESERVED ; 51, 67, 0x10C, + ELSE + DCD SCI_IRQHandler ; 51, 67, 0x10C, + ENDIF + DCD I2S_IRQHandler ; 52, 68, 0x110, + DCD USB_IRQHandler ; 53, 69, 0x114, + IF (USE_HT32_CHIP=HT32F1653_54_55_56) + DCD _RESERVED ; 54, 70, 0x118, + ELSE + DCD SDIO_IRQHandler ; 54, 70, 0x118, + ENDIF + DCD PDMA_CH0_IRQHandler ; 55, 71, 0x11C, + DCD PDMA_CH1_IRQHandler ; 56, 72, 0x120, + DCD PDMA_CH2_IRQHandler ; 57, 73, 0x124, + DCD PDMA_CH3_IRQHandler ; 58, 74, 0x128, + DCD PDMA_CH4_IRQHandler ; 59, 75, 0x12C, + DCD PDMA_CH5_IRQHandler ; 60, 76, 0x130, + DCD PDMA_CH6_IRQHandler ; 61, 77, 0x134, + DCD PDMA_CH7_IRQHandler ; 62, 78, 0x138, + IF (USE_HT32_CHIP=HT32F1653_54_55_56) + DCD _RESERVED ; 63, 79, 0x13C, + DCD _RESERVED ; 64, 80, 0x140, + DCD _RESERVED ; 65, 81, 0x144, + DCD _RESERVED ; 66, 82, 0x148, + ELSE + DCD PDMA_CH8_IRQHandler ; 63, 79, 0x13C, + DCD PDMA_CH9_IRQHandler ; 64, 80, 0x140, + DCD PDMA_CH10_IRQHandler ; 65, 81, 0x144, + DCD PDMA_CH11_IRQHandler ; 66, 82, 0x148, + ENDIF + IF (USE_HT32_CHIP=HT32F12365_66) + DCD CSIF_IRQHandler ; 67, 83, 0x14C, + ELSE + DCD _RESERVED ; 67, 83, 0x14C, + ENDIF + DCD EBI_IRQHandler ; 68, 84, 0x150, + IF (USE_HT32_CHIP=HT32F12365_66) + DCD AES_IRQHandler ; 69, 85, 0x154, + ENDIF + + THUMB + + PUBWEAK Reset_Handler + SECTION .text:CODE:REORDER:NOROOT(2) +Reset_Handler + IF (USE_HT32_CHIP=HT32F1653_54_55_56) + ELSE + LDR R0, =BootProcess + BLX R0 + ENDIF + LDR R0, =SystemInit + BLX R0 + LDR R0, =__iar_program_start + BX R0 + + IF (USE_HT32_CHIP=HT32F1653_54_55_56) + ELSE +BootProcess + LDR R0, =0x40080300 + LDR R1,[R0, #0x10] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x14] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x18] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x1C] + CMP R1, #0 + BEQ BP2 +BP1 LDR R0, =0x40080180 + LDR R1,[R0, #0xC] + LSLS R1, R1, #4 + LSRS R1, R1, #20 + CMP R1, #0 + BEQ BP3 + CMP R1, #1 + BEQ BP3 + CMP R1, #2 + BEQ BP3 +BP2 DSB + LDR R0, =0x20000000 + LDR R1, =0x05fa0004 + STR R1, [R0] + LDR R1, =0xe000ed00 + LDR R0, =0x05fa0004 + STR R0, [R1, #0xC] + DSB + B . +BP3 LDR R0, =0x20000000 + LDR R1, [R0] + LDR R0, =0x05fa0004 + CMP R0, R1 + BEQ BP4 + BX LR +BP4 LDR R0, =0x40088100 + LDR R1, =0x00000001 + STR R1, [R0] + LDR R0, =0x20000000 + LDR R1, =0x0 + STR R1, [R0] + BX LR + ENDIF + + PUBWEAK NMI_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +NMI_Handler + B . + + PUBWEAK HardFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +HardFault_Handler + B . + + PUBWEAK MemManage_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +MemManage_Handler + B . + + PUBWEAK BusFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +BusFault_Handler + B . + + PUBWEAK UsageFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +UsageFault_Handler + B . + + PUBWEAK SVC_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SVC_Handler + B . + + PUBWEAK DebugMon_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +DebugMon_Handler + B . + + PUBWEAK PendSV_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PendSV_Handler + B . + + PUBWEAK SysTick_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SysTick_Handler + B . + + + PUBWEAK CKRDY_IRQHandler + PUBWEAK LVD_IRQHandler + PUBWEAK BOD_IRQHandler + PUBWEAK WDT_IRQHandler + PUBWEAK RTC_IRQHandler + PUBWEAK FLASH_IRQHandler + PUBWEAK EVWUP_IRQHandler + PUBWEAK LPWUP_IRQHandler + PUBWEAK EXTI0_IRQHandler + PUBWEAK EXTI1_IRQHandler + PUBWEAK EXTI2_IRQHandler + PUBWEAK EXTI3_IRQHandler + PUBWEAK EXTI4_IRQHandler + PUBWEAK EXTI5_IRQHandler + PUBWEAK EXTI6_IRQHandler + PUBWEAK EXTI7_IRQHandler + PUBWEAK EXTI8_IRQHandler + PUBWEAK EXTI9_IRQHandler + PUBWEAK EXTI10_IRQHandler + PUBWEAK EXTI11_IRQHandler + PUBWEAK EXTI12_IRQHandler + PUBWEAK EXTI13_IRQHandler + PUBWEAK EXTI14_IRQHandler + PUBWEAK EXTI15_IRQHandler + PUBWEAK COMP_IRQHandler + PUBWEAK ADC_IRQHandler + PUBWEAK MCTM0BRK_IRQHandler + PUBWEAK MCTM0UP_IRQHandler + PUBWEAK MCTM0TR_IRQHandler + PUBWEAK MCTM0CC_IRQHandler + PUBWEAK MCTM1BRK_IRQHandler + PUBWEAK MCTM1UP_IRQHandler + PUBWEAK MCTM1TR_IRQHandler + PUBWEAK MCTM1CC_IRQHandler + PUBWEAK GPTM0_IRQHandler + PUBWEAK GPTM1_IRQHandler + PUBWEAK BFTM0_IRQHandler + PUBWEAK BFTM1_IRQHandler + PUBWEAK I2C0_IRQHandler + PUBWEAK I2C1_IRQHandler + PUBWEAK SPI0_IRQHandler + PUBWEAK SPI1_IRQHandler + PUBWEAK USART0_IRQHandler + PUBWEAK USART1_IRQHandler + PUBWEAK UART0_IRQHandler + PUBWEAK UART1_IRQHandler + PUBWEAK SCI_IRQHandler + PUBWEAK I2S_IRQHandler + PUBWEAK USB_IRQHandler + PUBWEAK SDIO_IRQHandler + PUBWEAK PDMA_CH0_IRQHandler + PUBWEAK PDMA_CH1_IRQHandler + PUBWEAK PDMA_CH2_IRQHandler + PUBWEAK PDMA_CH3_IRQHandler + PUBWEAK PDMA_CH4_IRQHandler + PUBWEAK PDMA_CH5_IRQHandler + PUBWEAK PDMA_CH6_IRQHandler + PUBWEAK PDMA_CH7_IRQHandler + PUBWEAK PDMA_CH8_IRQHandler + PUBWEAK PDMA_CH9_IRQHandler + PUBWEAK PDMA_CH10_IRQHandler + PUBWEAK PDMA_CH11_IRQHandler + PUBWEAK CSIF_IRQHandler + PUBWEAK EBI_IRQHandler + PUBWEAK AES_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +CKRDY_IRQHandler +LVD_IRQHandler +BOD_IRQHandler +WDT_IRQHandler +RTC_IRQHandler +FLASH_IRQHandler +EVWUP_IRQHandler +LPWUP_IRQHandler +EXTI0_IRQHandler +EXTI1_IRQHandler +EXTI2_IRQHandler +EXTI3_IRQHandler +EXTI4_IRQHandler +EXTI5_IRQHandler +EXTI6_IRQHandler +EXTI7_IRQHandler +EXTI8_IRQHandler +EXTI9_IRQHandler +EXTI10_IRQHandler +EXTI11_IRQHandler +EXTI12_IRQHandler +EXTI13_IRQHandler +EXTI14_IRQHandler +EXTI15_IRQHandler +COMP_IRQHandler +ADC_IRQHandler +MCTM0BRK_IRQHandler +MCTM0UP_IRQHandler +MCTM0TR_IRQHandler +MCTM0CC_IRQHandler +MCTM1BRK_IRQHandler +MCTM1UP_IRQHandler +MCTM1TR_IRQHandler +MCTM1CC_IRQHandler +GPTM0_IRQHandler +GPTM1_IRQHandler +BFTM0_IRQHandler +BFTM1_IRQHandler +I2C0_IRQHandler +I2C1_IRQHandler +SPI0_IRQHandler +SPI1_IRQHandler +USART0_IRQHandler +USART1_IRQHandler +UART0_IRQHandler +UART1_IRQHandler +SCI_IRQHandler +I2S_IRQHandler +USB_IRQHandler +SDIO_IRQHandler +PDMA_CH0_IRQHandler +PDMA_CH1_IRQHandler +PDMA_CH2_IRQHandler +PDMA_CH3_IRQHandler +PDMA_CH4_IRQHandler +PDMA_CH5_IRQHandler +PDMA_CH6_IRQHandler +PDMA_CH7_IRQHandler +PDMA_CH8_IRQHandler +PDMA_CH9_IRQHandler +PDMA_CH10_IRQHandler +PDMA_CH11_IRQHandler +CSIF_IRQHandler +EBI_IRQHandler +AES_IRQHandler + B . + + END diff --git a/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/Device/Holtek/HT32F1xxxx/Source/IAR/startup_ht32f1xxxx_iar_03.s b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/Device/Holtek/HT32F1xxxx/Source/IAR/startup_ht32f1xxxx_iar_03.s new file mode 100644 index 0000000000..dc39012845 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/Device/Holtek/HT32F1xxxx/Source/IAR/startup_ht32f1xxxx_iar_03.s @@ -0,0 +1,339 @@ +;/*---------------------------------------------------------------------------------------------------------*/ +;/* Holtek Semiconductor Inc. */ +;/* */ +;/* Copyright (C) Holtek Semiconductor Inc. */ +;/* All rights reserved. */ +;/* */ +;/*----------------------------------------------------------------------------------------------------------- +; File Name : startup_ht32f1xxxx_iar_03.s +; Version : $Rev:: 1774 $ +; Date : $Date:: 2019-07-25 #$ +; Description : Startup code. +;-----------------------------------------------------------------------------------------------------------*/ + +; Supported Device +; ======================================== +; HT32F12364 + +;// HT32 Device +;// <0=> By Project Asm Define +;// <16=> HT32F12364 +USE_HT32_CHIP_SET EQU 0 + +_HT32FWID EQU 0xFFFFFFFF +;_HT32FWID EQU 0x00012364 + +HT32F12364 EQU 16 + + IF USE_HT32_CHIP_SET=0 + ELSE + #undef USE_HT32_CHIP + #define USE_HT32_CHIP USE_HT32_CHIP_SET + ENDIF + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + EXTERN SystemInit + PUBLIC __vector_table + +;******************************************************************************* +; Fill-up the Vector Table entries with the exceptions ISR address +;******************************************************************************* + DATA +_RESERVED EQU 0xFFFFFFFF +__vector_table + DCD sfe(CSTACK) ; ---, 00, 0x000, Top address of Stack + DCD Reset_Handler ; ---, 01, 0x004, Reset Handler + DCD NMI_Handler ; ---, 02, 0x008, NMI Handler + DCD HardFault_Handler ; ---, 03, 0x00C, Hard Fault Handler + DCD MemManage_Handler ; ---, 04, 0x010, Memory Management Fault Handler + DCD BusFault_Handler ; ---, 05, 0x014, Bus Fault Handler + DCD UsageFault_Handler ; ---, 06, 0x018, Usage Fault Handler + DCD _RESERVED ; ---, 07, 0x01C, Reserved + DCD _HT32FWID ; ---, 08, 0x020, Reserved + DCD _RESERVED ; ---, 09, 0x024, Reserved + DCD _RESERVED ; ---, 10, 0x028, Reserved + DCD SVC_Handler ; ---, 11, 0x02C, SVC Handler + DCD DebugMon_Handler ; ---, 12, 0x030, Debug Monitor Handler + DCD _RESERVED ; ---, 13, 0x034, Reserved + DCD PendSV_Handler ; ---, 14, 0x038, PendSV Handler + DCD SysTick_Handler ; ---, 15, 0x03C, SysTick Handler + + ; External Interrupt Handler + DCD CKRDY_IRQHandler ; 00, 16, 0x040, + DCD LVD_IRQHandler ; 01, 17, 0x044, + DCD BOD_IRQHandler ; 02, 18, 0x048, + DCD _RESERVED ; 03, 19, 0x04C, + DCD RTC_IRQHandler ; 04, 20, 0x050, + DCD FLASH_IRQHandler ; 05, 21, 0x054, + DCD EVWUP_IRQHandler ; 06, 22, 0x058, + DCD LPWUP_IRQHandler ; 07, 23, 0x05C, + DCD EXTI0_IRQHandler ; 08, 24, 0x060, + DCD EXTI1_IRQHandler ; 09, 25, 0x064, + DCD EXTI2_IRQHandler ; 10, 26, 0x068, + DCD EXTI3_IRQHandler ; 11, 27, 0x06C, + DCD EXTI4_IRQHandler ; 12, 28, 0x070, + DCD EXTI5_IRQHandler ; 13, 29, 0x074, + DCD EXTI6_IRQHandler ; 14, 30, 0x078, + DCD EXTI7_IRQHandler ; 15, 31, 0x07C, + DCD EXTI8_IRQHandler ; 16, 32, 0x080, + DCD EXTI9_IRQHandler ; 17, 33, 0x084, + DCD EXTI10_IRQHandler ; 18, 34, 0x088, + DCD EXTI11_IRQHandler ; 19, 35, 0x08C, + DCD EXTI12_IRQHandler ; 20, 36, 0x090, + DCD EXTI13_IRQHandler ; 21, 37, 0x094, + DCD EXTI14_IRQHandler ; 22, 38, 0x098, + DCD EXTI15_IRQHandler ; 23, 39, 0x09C, + DCD _RESERVED ; 24, 40, 0x0A0, + DCD ADC_IRQHandler ; 25, 41, 0x0A4, + DCD _RESERVED ; 26, 42, 0x0A8, + DCD _RESERVED ; 27, 43, 0x0AC, + DCD _RESERVED ; 28, 44, 0x0B0, + DCD _RESERVED ; 29, 45, 0x0B4, + DCD _RESERVED ; 30, 46, 0x0B8, + DCD _RESERVED ; 31, 47, 0x0BC, + DCD _RESERVED ; 32, 48, 0x0C0, + DCD _RESERVED ; 33, 49, 0x0C4, + DCD _RESERVED ; 34, 50, 0x0C8, + DCD GPTM0_IRQHandler ; 35, 51, 0x0CC, + DCD _RESERVED ; 36, 52, 0x0D0, + DCD SCTM0_IRQHandler ; 37, 53, 0x0D4, + DCD SCTM1_IRQHandler ; 38, 54, 0x0D8, + DCD PWM0_IRQHandler ; 39, 55, 0x0DC, + DCD _RESERVED ; 40, 56, 0x0E0, + DCD BFTM0_IRQHandler ; 41, 57, 0x0E4, + DCD BFTM1_IRQHandler ; 42, 58, 0x0E8, + DCD I2C0_IRQHandler ; 43, 59, 0x0EC, + DCD I2C1_IRQHandler ; 44, 60, 0x0F0, + DCD SPI0_IRQHandler ; 45, 61, 0x0F4, + DCD SPI1_IRQHandler ; 46, 62, 0x0F8, + DCD USART0_IRQHandler ; 47, 63, 0x0FC, + DCD _RESERVED ; 48, 64, 0x100, + DCD UART0_IRQHandler ; 49, 65, 0x104, + DCD UART1_IRQHandler ; 50, 66, 0x108, + DCD SCI_IRQHandler ; 51, 67, 0x10C, + DCD _RESERVED ; 52, 68, 0x110, + DCD USB_IRQHandler ; 53, 69, 0x114, + DCD _RESERVED ; 54, 70, 0x118, + DCD PDMA_CH0_IRQHandler ; 55, 71, 0x11C, + DCD PDMA_CH1_IRQHandler ; 56, 72, 0x120, + DCD PDMA_CH2_IRQHandler ; 57, 73, 0x124, + DCD PDMA_CH3_IRQHandler ; 58, 74, 0x128, + DCD PDMA_CH4_IRQHandler ; 59, 75, 0x12C, + DCD PDMA_CH5_IRQHandler ; 60, 76, 0x130, + DCD _RESERVED ; 61, 77, 0x134, + DCD _RESERVED ; 62, 78, 0x138, + DCD _RESERVED ; 63, 79, 0x13C, + DCD _RESERVED ; 64, 80, 0x140, + DCD _RESERVED ; 65, 81, 0x144, + DCD _RESERVED ; 66, 82, 0x148, + DCD _RESERVED ; 67, 83, 0x14C, + DCD _RESERVED ; 68, 84, 0x150, + DCD AES_IRQHandler ; 69, 85, 0x154, + THUMB + + PUBWEAK Reset_Handler + SECTION .text:CODE:REORDER:NOROOT(2) +Reset_Handler + LDR R0, =BootProcess + BLX R0 + LDR R0, =SystemInit + BLX R0 + LDR R0, =__iar_program_start + BX R0 + +BootProcess + LDR R0, =0x40080300 + LDR R1,[R0, #0x10] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x14] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x18] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x1C] + CMP R1, #0 + BEQ BP2 +BP1 LDR R0, =0x40080180 + LDR R1,[R0, #0xC] + LSLS R1, R1, #4 + LSRS R1, R1, #20 + CMP R1, #0 + BEQ BP3 + CMP R1, #1 + BEQ BP3 + CMP R1, #2 + BEQ BP3 +BP2 DSB + LDR R0, =0x20000000 + LDR R1, =0x05fa0004 + STR R1, [R0] + LDR R1, =0xe000ed00 + LDR R0, =0x05fa0004 + STR R0, [R1, #0xC] + DSB + B . +BP3 LDR R0, =0x20000000 + LDR R1, [R0] + LDR R0, =0x05fa0004 + CMP R0, R1 + BEQ BP4 + BX LR +BP4 LDR R0, =0x40088100 + LDR R1, =0x00000001 + STR R1, [R0] + LDR R0, =0x20000000 + LDR R1, =0x0 + STR R1, [R0] + BX LR + + PUBWEAK NMI_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +NMI_Handler + B . + + PUBWEAK HardFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +HardFault_Handler + B . + + PUBWEAK MemManage_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +MemManage_Handler + B . + + PUBWEAK BusFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +BusFault_Handler + B . + + PUBWEAK UsageFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +UsageFault_Handler + B . + + PUBWEAK SVC_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SVC_Handler + B . + + PUBWEAK DebugMon_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +DebugMon_Handler + B . + + PUBWEAK PendSV_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PendSV_Handler + B . + + PUBWEAK SysTick_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SysTick_Handler + B . + + + PUBWEAK CKRDY_IRQHandler + PUBWEAK LVD_IRQHandler + PUBWEAK BOD_IRQHandler + PUBWEAK RTC_IRQHandler + PUBWEAK FLASH_IRQHandler + PUBWEAK EVWUP_IRQHandler + PUBWEAK LPWUP_IRQHandler + PUBWEAK EXTI0_IRQHandler + PUBWEAK EXTI1_IRQHandler + PUBWEAK EXTI2_IRQHandler + PUBWEAK EXTI3_IRQHandler + PUBWEAK EXTI4_IRQHandler + PUBWEAK EXTI5_IRQHandler + PUBWEAK EXTI6_IRQHandler + PUBWEAK EXTI7_IRQHandler + PUBWEAK EXTI8_IRQHandler + PUBWEAK EXTI9_IRQHandler + PUBWEAK EXTI10_IRQHandler + PUBWEAK EXTI11_IRQHandler + PUBWEAK EXTI12_IRQHandler + PUBWEAK EXTI13_IRQHandler + PUBWEAK EXTI14_IRQHandler + PUBWEAK EXTI15_IRQHandler + PUBWEAK ADC_IRQHandler + PUBWEAK GPTM0_IRQHandler + PUBWEAK SCTM0_IRQHandler + PUBWEAK SCTM1_IRQHandler + PUBWEAK PWM0_IRQHandler + PUBWEAK BFTM0_IRQHandler + PUBWEAK BFTM1_IRQHandler + PUBWEAK I2C0_IRQHandler + PUBWEAK I2C1_IRQHandler + PUBWEAK SPI0_IRQHandler + PUBWEAK SPI1_IRQHandler + PUBWEAK USART0_IRQHandler + PUBWEAK UART0_IRQHandler + PUBWEAK UART1_IRQHandler + PUBWEAK SCI_IRQHandler + PUBWEAK USB_IRQHandler + PUBWEAK PDMA_CH0_IRQHandler + PUBWEAK PDMA_CH1_IRQHandler + PUBWEAK PDMA_CH2_IRQHandler + PUBWEAK PDMA_CH3_IRQHandler + PUBWEAK PDMA_CH4_IRQHandler + PUBWEAK PDMA_CH5_IRQHandler + PUBWEAK AES_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +CKRDY_IRQHandler +LVD_IRQHandler +BOD_IRQHandler +RTC_IRQHandler +FLASH_IRQHandler +EVWUP_IRQHandler +LPWUP_IRQHandler +EXTI0_IRQHandler +EXTI1_IRQHandler +EXTI2_IRQHandler +EXTI3_IRQHandler +EXTI4_IRQHandler +EXTI5_IRQHandler +EXTI6_IRQHandler +EXTI7_IRQHandler +EXTI8_IRQHandler +EXTI9_IRQHandler +EXTI10_IRQHandler +EXTI11_IRQHandler +EXTI12_IRQHandler +EXTI13_IRQHandler +EXTI14_IRQHandler +EXTI15_IRQHandler +ADC_IRQHandler +GPTM0_IRQHandler +SCTM0_IRQHandler +SCTM1_IRQHandler +PWM0_IRQHandler +BFTM0_IRQHandler +BFTM1_IRQHandler +I2C0_IRQHandler +I2C1_IRQHandler +SPI0_IRQHandler +SPI1_IRQHandler +USART0_IRQHandler +UART0_IRQHandler +UART1_IRQHandler +SCI_IRQHandler +USB_IRQHandler +PDMA_CH0_IRQHandler +PDMA_CH1_IRQHandler +PDMA_CH2_IRQHandler +PDMA_CH3_IRQHandler +PDMA_CH4_IRQHandler +PDMA_CH5_IRQHandler +AES_IRQHandler + B . + + END diff --git a/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/Device/Holtek/HT32F1xxxx/Source/emStudio/SEGGER_THUMB_Startup.s b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/Device/Holtek/HT32F1xxxx/Source/emStudio/SEGGER_THUMB_Startup.s new file mode 100644 index 0000000000..63a379c804 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/Device/Holtek/HT32F1xxxx/Source/emStudio/SEGGER_THUMB_Startup.s @@ -0,0 +1,435 @@ +// ********************************************************************** +// * SEGGER Microcontroller GmbH * +// * The Embedded Experts * +// ********************************************************************** +// * * +// * (c) 2014 - 2018 SEGGER Microcontroller GmbH * +// * (c) 2001 - 2018 Rowley Associates Limited * +// * * +// * www.segger.com Support: support@segger.com * +// * * +// ********************************************************************** +// * * +// * All rights reserved. * +// * * +// * Redistribution and use in source and binary forms, with or * +// * without modification, are permitted provided that the following * +// * conditions are met: * +// * * +// * - Redistributions of source code must retain the above copyright * +// * notice, this list of conditions and the following disclaimer. * +// * * +// * - Neither the name of SEGGER Microcontroller GmbH * +// * nor the names of its contributors may be used to endorse or * +// * promote products derived from this software without specific * +// * prior written permission. * +// * * +// * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND * +// * CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, * +// * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * +// * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * +// * DISCLAIMED. * +// * IN NO EVENT SHALL SEGGER Microcontroller GmbH BE LIABLE FOR * +// * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * +// * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT * +// * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; * +// * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF * +// * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * +// * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE * +// * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH * +// * DAMAGE. * +// * * +// ********************************************************************** +// Preprocessor Definitions +// ------------------------ +// +// FULL_LIBRARY +// +// If defined then +// - argc, argv are setup by the debug_getargs. +// - the exit symbol is defined and executes on return from main. +// - the exit symbol calls destructors, atexit functions and then debug_exit. +// +// If not defined then +// - argc and argv are zero. +// - the exit symbol is defined, executes on return from main and loops +// + + .syntax unified + + .section .segger.init.__SEGGER_init_lzss, "ax" + .code 16 + .balign 2 + .global __SEGGER_init_lzss +.thumb_func +__SEGGER_init_lzss: + ldr r0, [r4] @ destination + ldr r1, [r4, #4] @ source stream + adds r4, r4, #8 +2: + ldrb r2, [r1] + adds r1, r1, #1 + tst r2, r2 + beq 9f @ 0 -> end of table + cmp r2, #0x80 + bcc 1f @ +ve -> literal run +// +// -ve -> copy run +// +// r0 = pointer to output stream +// r1 = pointer to input stream +// r2 = run length +// r3 = copy byte +// r4 = pointer to initialization table +// +3: + subs r2, r2, #0x80 // convert to run length + beq 10f + ldrb r3, [r1] // r3 = first byte of distance + adds r1, r1, #1 + cmp r3, #0x80 + bcc 5f // r3 < 128, short run + subs r3, r3, #0x80 // Adjust to recover true run length high byte + lsls r3, r3, #8 // Prepare to fuse + ldrb r5, [r1] // extract run length low byte + adds r1, r1, #1 + adds r3, r3, r5 // construct run length +5: + subs r5, r0, r3 // source of where to copy from +4: + ldrb r3, [r5] // source byte of run + strb r3, [r0] // store to destination + adds r5, r5, #1 + adds r0, r0, #1 + subs r2, r2, #1 + bne 4b + b 2b +// +// +ve -> literal run +// +// r0 = pointer to output stream +// r1 = pointer to input stream +// r2 = run length +// r3 = copy byte +// r4 = pointer to initialization table +// +1: + ldrb r3, [r1] // source byte of run + adds r1, r1, #1 + strb r3, [r0] // store to destination + adds r0, r0, #1 + subs r2, r2, #1 + bne 1b + b 2b +9: + bx lr +10: + b 10b + + .section .segger.init.__SEGGER_init_zero, "ax" + .code 16 + .balign 2 + .global __SEGGER_init_zero +.thumb_func +__SEGGER_init_zero: + ldr r0, [r4] @ destination + ldr r1, [r4, #4] @ size + adds r4, r4, #8 + tst r1, r1 + beq 2f + movs r2, #0 +1: + strb r2, [r0] + adds r0, r0, #1 + subs r1, r1, #1 + bne 1b +2: + bx lr + + .section .segger.init.__SEGGER_init_copy, "ax" + .code 16 + .balign 2 + .global __SEGGER_init_copy +.thumb_func +__SEGGER_init_copy: + ldr r0, [r4] @ destination + ldr r1, [r4, #4] @ source + ldr r2, [r4, #8] @ size + adds r4, r4, #12 + tst r2, r2 + beq 2f +1: + ldrb r3, [r1] + strb r3, [r0] + adds r0, r0, #1 + adds r1, r1, #1 + subs r2, r2, #1 + bne 1b +2: + bx lr + + .section .segger.init.__SEGGER_init_pack, "ax" + .code 16 + .balign 2 + .global __SEGGER_init_pack +.thumb_func +__SEGGER_init_pack: + ldr r0, [r4] @ destination + ldr r1, [r4, #4] @ source stream + adds r4, r4, #8 +1: + ldrb r2, [r1] + adds r1, r1, #1 + cmp r2, #0x80 + beq 4f + bcc 3f + ldrb r3, [r1] @ byte to replicate + adds r1, r1, #1 + negs r2, r2 + adds r2, r2, #255 + adds r2, r2, #1 +2: + strb r3, [r0] + adds r0, r0, #1 + subs r2, r2, #1 + bpl 2b + b 1b + +3: @ 1+n literal bytes + ldrb r3, [r1] + strb r3, [r0] + adds r0, r0, #1 + adds r1, r1, #1 + subs r2, r2, #1 + bpl 3b + b 1b +4: + bx lr + + .section .segger.init.__SEGGER_init_zpak, "ax" + .code 16 + .balign 2 + .global __SEGGER_init_zpak +.thumb_func +__SEGGER_init_zpak: + ldr r0, [r4] @ destination + ldr r1, [r4, #4] @ source stream + ldr r2, [r4, #8] @ size + adds r4, r4, #12 @ skip table entries +1: + ldrb r3, [r1] @ get control byte from source stream + adds r1, r1, #1 + movs r6, #8 +2: + movs r5, #0 @ prepare zero filler + lsrs r3, r3, #1 @ get byte control flag + bcs 3f @ carry set -> zero filler + ldrb r5, [r1] @ get literal byte from source stream + adds r1, r1, #1 +3: + strb r5, [r0] @ store initialization byte + adds r0, r0, #1 + subs r2, r2, #1 @ size -= 1 + beq 4f @ exit when destination filled + subs r6, r6, #1 @ decrement bit count + bne 2b @ still within this control byte + b 1b @ get next control byte +4: + bx lr + +#ifndef APP_ENTRY_POINT +#define APP_ENTRY_POINT main +#endif + +#ifndef ARGSSPACE +#define ARGSSPACE 128 +#endif + + .global _start + .extern APP_ENTRY_POINT + .global exit + .weak exit + +#ifdef INITIALIZE_USER_SECTIONS + .extern InitializeUserMemorySections +#endif + + .section .init, "ax" + .code 16 + .align 1 + .thumb_func + +_start: + ldr r0, = __stack_end__ + mov sp, r0 + ldr r4, =__SEGGER_init_table__ +1: + ldr r0, [r4] + adds r4, r4, #4 + tst r0, r0 + beq 2f + blx r0 + b 1b +2: + + /* Initialize the heap */ + ldr r0, = __heap_start__ + ldr r1, = __heap_end__ + subs r1, r1, r0 + cmp r1, #8 + blt 1f + movs r2, #0 + str r2, [r0] + adds r0, r0, #4 + str r1, [r0] +1: + +#ifdef INITIALIZE_USER_SECTIONS + ldr r2, =InitializeUserMemorySections + blx r2 +#endif + + /* Call constructors */ + ldr r0, =__ctors_start__ + ldr r1, =__ctors_end__ +ctor_loop: + cmp r0, r1 + beq ctor_end + ldr r2, [r0] + adds r0, #4 + push {r0-r1} + blx r2 + pop {r0-r1} + b ctor_loop +ctor_end: + + /* Setup initial call frame */ + movs r0, #0 + mov lr, r0 + mov r12, sp + + .type start, function +start: + /* Jump to application entry point */ +#ifdef FULL_LIBRARY + movs r0, #ARGSSPACE + ldr r1, =args + ldr r2, =debug_getargs + blx r2 + ldr r1, =args +#else + movs r0, #0 + movs r1, #0 +#endif + ldr r2, =APP_ENTRY_POINT + blx r2 + + .thumb_func +exit: +#ifdef FULL_LIBRARY + mov r5, r0 // save the exit parameter/return result + + /* Call destructors */ + ldr r0, =__dtors_start__ + ldr r1, =__dtors_end__ +dtor_loop: + cmp r0, r1 + beq dtor_end + ldr r2, [r0] + add r0, #4 + push {r0-r1} + blx r2 + pop {r0-r1} + b dtor_loop +dtor_end: + + /* Call atexit functions */ + ldr r2, =_execute_at_exit_fns + blx r2 + + /* Call debug_exit with return result/exit parameter */ + mov r0, r5 + ldr r2, =debug_exit + blx r2 +#endif + + /* Returned from application entry point, loop forever. */ +exit_loop: + b exit_loop + + // default C/C++ library helpers + +.macro HELPER helper_name + .section .text.\helper_name, "ax", %progbits + .global \helper_name + .align 1 + .weak \helper_name +\helper_name: + .thumb_func +.endm + +.macro JUMPTO name +#if defined(__thumb__) && !defined(__thumb2__) + mov r12, r0 + ldr r0, =\name + push {r0} + mov r0, r12 + pop {pc} +#else + b \name +#endif +.endm + +HELPER __aeabi_read_tp + ldr r0, =__tbss_start__-8 + bx lr +HELPER abort + b . +HELPER __assert + b . +HELPER __aeabi_assert + b . +HELPER __sync_synchronize + bx lr +HELPER __getchar + JUMPTO debug_getchar +HELPER __putchar + JUMPTO debug_putchar +HELPER __open + JUMPTO debug_fopen +HELPER __close + JUMPTO debug_fclose +HELPER __write + mov r3, r0 + mov r0, r1 + movs r1, #1 + JUMPTO debug_fwrite +HELPER __read + mov r3, r0 + mov r0, r1 + movs r1, #1 + JUMPTO debug_fread +HELPER __seek + push {r4, lr} + mov r4, r0 + bl debug_fseek + cmp r0, #0 + bne 1f + mov r0, r4 + bl debug_ftell + pop {r4, pc} +1: + ldr r0, =-1 + pop {r4, pc} + // char __user_locale_name_buffer[]; + .section .bss.__user_locale_name_buffer, "aw", %nobits + .global __user_locale_name_buffer + .weak __user_locale_name_buffer + __user_locale_name_buffer: + .word 0x0 + +#ifdef FULL_LIBRARY + .bss +args: + .space ARGSSPACE +#endif diff --git a/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/Device/Holtek/HT32F1xxxx/Source/emStudio/startup_ht32f1xxxx_es_01.s b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/Device/Holtek/HT32F1xxxx/Source/emStudio/startup_ht32f1xxxx_es_01.s new file mode 100644 index 0000000000..5f60bca990 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/Device/Holtek/HT32F1xxxx/Source/emStudio/startup_ht32f1xxxx_es_01.s @@ -0,0 +1,391 @@ +/*---------------------------------------------------------------------------------------------------------*/ +/* Holtek Semiconductor Inc. */ +/* */ +/* Copyright (C) Holtek Semiconductor Inc. */ +/* All rights reserved. */ +/* */ +/*----------------------------------------------------------------------------------------------------------- +; File Name : startup_ht32f1xxxx_es_01.s +; Version : $Rev:: 1578 $ +; Date : $Date:: 2019-03-29 #$ +; Description : Startup code. +;-----------------------------------------------------------------------------------------------------------*/ + +/* +; Supported Device +; ======================================== +; HT32F1653, HT32F1654 +; HT32F1655, HT32F1656 +; HT32F12365, HT32F12366 +; HT32F12345 +*/ + +;/* <<< Use Configuration Wizard in Context Menu >>> */ +/* +;// HT32 Device +;// <0=> By Project Asm Define +;// <1=> HT32F1653/1654/1655/1656 +;// <2=> HT32F12365/12366 +;// <3=> HT32F12345 +*/ + .equ USE_HT32_CHIP_SET, 0 + + .equ _HT32FWID, 0xFFFFFFFF +/* + .equ _HT32FWID, 0x00012366 +*/ + + .equ HT32F1653_54_55_56, 1 + .equ HT32F12365_66, 2 + .equ HT32F12345, 3 + + .if USE_HT32_CHIP_SET == 0 + .else + .equ USE_HT32_CHIP, USE_HT32_CHIP_SET + .endif + + .equ _RESERVED, 0xFFFFFFFF +/* +;******************************************************************************* +; Fill-up the Vector Table entries with the exceptions ISR address +;********************************************************************************/ + .syntax unified + .global reset_handler + .global Reset_Handler + .equ Reset_Handler, reset_handler + + .section .vectors, "ax" + .section .vectors, "ax" + .code 16 + .balign 2 + .global _vectors +_vectors: + .long __stack_end__ /* ---, 00, 0x000, Top address of Stack */ + .long reset_handler /* ---, 01, 0x004, Reset Handler */ + .long NMI_Handler /* ---, 02, 0x008, NMI Handler */ + .long HardFault_Handler /* ---, 03, 0x00C, Hard Fault Handler */ + .long MemManage_Handler /* ---, 04, 0x010, MPU Fault Handler */ + .long BusFault_Handler /* ---, 05, 0x014, Bus Fault Handler */ + .long UsageFault_Handler /* ---, 06, 0x018, Usage Fault Handler */ + .long _RESERVED /* ---, 07, 0x01C, Reserved */ + .long _HT32FWID /* ---, 08, 0x020, Reserved */ + .long _RESERVED /* ---, 09, 0x024, Reserved */ + .long _RESERVED /* ---, 10, 0x028, Reserved */ + .long SVC_Handler /* ---, 11, 0x02C, SVC Handler */ + .long DebugMon_Handler /* ---, 12, 0x030, Debug Monitor Handler */ + .long _RESERVED /* ---, 13, 0x034, Reserved */ + .long PendSV_Handler /* ---, 14, 0x038, PendSV Handler */ + .long SysTick_Handler /* ---, 15, 0x03C, SysTick Handler */ + + /* External Interrupt Handler */ + .long CKRDY_IRQHandler /* 00, 16, 0x040, */ + .long LVD_IRQHandler /* 01, 17, 0x044, */ + .long BOD_IRQHandler /* 02, 18, 0x048, */ + .if (USE_HT32_CHIP==HT32F1653_54_55_56) + .long WDT_IRQHandler /* 03, 19, 0x04C, */ + .else + .long _RESERVED /* 03, 19, 0x04C, */ + .endif + .long RTC_IRQHandler /* 04, 20, 0x050, */ + .long FLASH_IRQHandler /* 05, 21, 0x054, */ + .long EVWUP_IRQHandler /* 06, 22, 0x058, */ + .long LPWUP_IRQHandler /* 07, 23, 0x05C, */ + .long EXTI0_IRQHandler /* 08, 24, 0x060, */ + .long EXTI1_IRQHandler /* 09, 25, 0x064, */ + .long EXTI2_IRQHandler /* 10, 26, 0x068, */ + .long EXTI3_IRQHandler /* 11, 27, 0x06C, */ + .long EXTI4_IRQHandler /* 12, 28, 0x070, */ + .long EXTI5_IRQHandler /* 13, 29, 0x074, */ + .long EXTI6_IRQHandler /* 14, 30, 0x078, */ + .long EXTI7_IRQHandler /* 15, 31, 0x07C, */ + .long EXTI8_IRQHandler /* 16, 32, 0x080, */ + .long EXTI9_IRQHandler /* 17, 33, 0x084, */ + .long EXTI10_IRQHandler /* 18, 34, 0x088, */ + .long EXTI11_IRQHandler /* 19, 35, 0x08C, */ + .long EXTI12_IRQHandler /* 20, 36, 0x090, */ + .long EXTI13_IRQHandler /* 21, 37, 0x094, */ + .long EXTI14_IRQHandler /* 22, 38, 0x098, */ + .long EXTI15_IRQHandler /* 23, 39, 0x09C, */ + .long COMP_IRQHandler /* 24, 40, 0x0A0, */ + .long ADC_IRQHandler /* 25, 41, 0x0A4, */ + .long _RESERVED /* 26, 42, 0x0A8, */ + .long MCTM0BRK_IRQHandler /* 27, 43, 0x0AC, */ + .long MCTM0UP_IRQHandler /* 28, 44, 0x0B0, */ + .long MCTM0TR_IRQHandler /* 29, 45, 0x0B4, */ + .long MCTM0CC_IRQHandler /* 30, 46, 0x0B8, */ + .long MCTM1BRK_IRQHandler /* 31, 47, 0x0BC, */ + .long MCTM1UP_IRQHandler /* 32, 48, 0x0C0, */ + .long MCTM1TR_IRQHandler /* 33, 49, 0x0C4, */ + .long MCTM1CC_IRQHandler /* 34, 50, 0x0C8, */ + .long GPTM0_IRQHandler /* 35, 51, 0x0CC, */ + .long GPTM1_IRQHandler /* 36, 52, 0x0D0, */ + .long _RESERVED /* 37, 53, 0x0D4, */ + .long _RESERVED /* 38, 54, 0x0D8, */ + .long _RESERVED /* 39, 55, 0x0DC, */ + .long _RESERVED /* 40, 56, 0x0E0, */ + .long BFTM0_IRQHandler /* 41, 57, 0x0E4, */ + .long BFTM1_IRQHandler /* 42, 58, 0x0E8, */ + .long I2C0_IRQHandler /* 43, 59, 0x0EC, */ + .long I2C1_IRQHandler /* 44, 60, 0x0F0, */ + .long SPI0_IRQHandler /* 45, 61, 0x0F4, */ + .long SPI1_IRQHandler /* 46, 62, 0x0F8, */ + .long USART0_IRQHandler /* 47, 63, 0x0FC, */ + .long USART1_IRQHandler /* 48, 64, 0x100, */ + .long UART0_IRQHandler /* 49, 65, 0x104, */ + .long UART1_IRQHandler /* 50, 66, 0x108, */ + .if (USE_HT32_CHIP==HT32F12345) + .long _RESERVED /* 51, 67, 0x10C, */ + .else + .long SCI_IRQHandler /* 51, 67, 0x10C, */ + .endif + .long I2S_IRQHandler /* 52, 68, 0x110, */ + .long USB_IRQHandler /* 53, 69, 0x114, */ + .if (USE_HT32_CHIP==HT32F1653_54_55_56) + .long _RESERVED /* 54, 70, 0x118, */ + .else + .long SDIO_IRQHandler /* 54, 70, 0x118, */ + .endif + .long PDMA_CH0_IRQHandler /* 55, 71, 0x11C, */ + .long PDMA_CH1_IRQHandler /* 56, 72, 0x120, */ + .long PDMA_CH2_IRQHandler /* 57, 73, 0x124, */ + .long PDMA_CH3_IRQHandler /* 58, 74, 0x128, */ + .long PDMA_CH4_IRQHandler /* 59, 75, 0x12C, */ + .long PDMA_CH5_IRQHandler /* 60, 76, 0x130, */ + .long PDMA_CH6_IRQHandler /* 61, 77, 0x134, */ + .long PDMA_CH7_IRQHandler /* 62, 78, 0x138, */ + .if (USE_HT32_CHIP==HT32F1653_54_55_56) + .long _RESERVED /* 63, 79, 0x13C, */ + .long _RESERVED /* 64, 80, 0x140, */ + .long _RESERVED /* 65, 81, 0x144, */ + .long _RESERVED /* 66, 82, 0x148, */ + .else + .long PDMA_CH8_IRQHandler /* 63, 79, 0x13C, */ + .long PDMA_CH9_IRQHandler /* 64, 80, 0x140, */ + .long PDMA_CH10_IRQHandler /* 65, 81, 0x144, */ + .long PDMA_CH11_IRQHandler /* 66, 82, 0x148, */ + .endif + .if (USE_HT32_CHIP==HT32F12365_66) + .long CSIF_IRQHandler /* 67, 83, 0x14C, */ + .else + .long _RESERVED /* 67, 83, 0x14C, */ + .endif + .long EBI_IRQHandler /* 68, 84, 0x150, */ + .if (USE_HT32_CHIP==HT32F12365_66) + .long AES_IRQHandler /* 69, 85, 0x154, */ + .endif + + + + .thumb + + +/* Reset Handler */ + + .section .text.reset_handler + .weak reset_handler + .type reset_handler, %function +reset_handler: + LDR R0, =__stack_end__ /* set stack pointer */ + MOV SP, R0 + .if (USE_HT32_CHIP==HT32F1653_54_55_56) + .else + LDR R0, =BootProcess + BLX R0 + .endif + LDR R0, =SystemInit + BLX R0 + BL _start + .if (USE_HT32_CHIP==HT32F1653_54_55_56) + .else + .thumb_func +BootProcess: + LDR R0, =0x40080300 + LDR R1,[R0, #0x10] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x14] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x18] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x1C] + CMP R1, #0 + BEQ BP2 +BP1: + LDR R0, =0x40080180 + LDR R1,[R0, #0xC] + LSLS R1, R1, #4 + LSRS R1, R1, #20 + CMP R1, #0 + BEQ BP3 + CMP R1, #1 + BEQ BP3 + CMP R1, #2 + BEQ BP3 +BP2: + DSB + LDR R0, =0x20000000 + LDR R1, =0x05fa0004 + STR R1, [R0] + LDR R1, =0xe000ed00 + LDR R0, =0x05fa0004 + STR R0, [R1, #0xC] + DSB + B . +BP3: + LDR R0, =0x20000000 + LDR R1, [R0] + LDR R0, =0x05fa0004 + CMP R0, R1 + BEQ BP4 + BX LR +BP4: + LDR R0, =0x40088100 + LDR R1, =0x00000001 + STR R1, [R0] + LDR R0, =0x20000000 + LDR R1, =0x0 + STR R1, [R0] + BX LR + .endif + + .size Reset_Handler, .-Reset_Handler + +/* Exception Handlers */ + + .weak NMI_Handler + .type NMI_Handler, %function +NMI_Handler: + B . + .size NMI_Handler, . - NMI_Handler + + .weak HardFault_Handler + .type HardFault_Handler, %function +HardFault_Handler: + B . + .size HardFault_Handler, . - HardFault_Handler + + .weak MemManage_Handler + .type MemManage_Handler, %function +MemManage_Handler: + B . + .size MemManage_Handler, . - MemManage_Handler + + .weak BusFault_Handler + .type BusFault_Handler, %function +BusFault_Handler: + B . + .size BusFault_Handler, . - BusFault_Handler + + .weak UsageFault_Handler + .type UsageFault_Handler, %function +UsageFault_Handler: + B . + .size UsageFault_Handler, . - UsageFault_Handler + + .weak SVC_Handler + .type SVC_Handler, %function +SVC_Handler: + B . + .size SVC_Handler, . - SVC_Handler + + .weak DebugMon_Handler + .type DebugMon_Handler, %function +DebugMon_Handler: + B . + .size DebugMon_Handler, . - DebugMon_Handler + + .weak PendSV_Handler + .type PendSV_Handler, %function +PendSV_Handler: + B . + .size PendSV_Handler, . - PendSV_Handler + + .weak SysTick_Handler + .type SysTick_Handler, %function +SysTick_Handler: + B . + .size SysTick_Handler, . - SysTick_Handler + + +/* IRQ Handlers */ + + .globl Default_Handler + .type Default_Handler, %function +Default_Handler: + B . + .size Default_Handler, . - Default_Handler + + .macro IRQ handler + .weak \handler + .set \handler, Default_Handler + .endm + + IRQ CKRDY_IRQHandler + IRQ LVD_IRQHandler + IRQ BOD_IRQHandler + IRQ WDT_IRQHandler + IRQ RTC_IRQHandler + IRQ FLASH_IRQHandler + IRQ EVWUP_IRQHandler + IRQ LPWUP_IRQHandler + IRQ EXTI0_IRQHandler + IRQ EXTI1_IRQHandler + IRQ EXTI2_IRQHandler + IRQ EXTI3_IRQHandler + IRQ EXTI4_IRQHandler + IRQ EXTI5_IRQHandler + IRQ EXTI6_IRQHandler + IRQ EXTI7_IRQHandler + IRQ EXTI8_IRQHandler + IRQ EXTI9_IRQHandler + IRQ EXTI10_IRQHandler + IRQ EXTI11_IRQHandler + IRQ EXTI12_IRQHandler + IRQ EXTI13_IRQHandler + IRQ EXTI14_IRQHandler + IRQ EXTI15_IRQHandler + IRQ COMP_IRQHandler + IRQ ADC_IRQHandler + IRQ MCTM0BRK_IRQHandler + IRQ MCTM0UP_IRQHandler + IRQ MCTM0TR_IRQHandler + IRQ MCTM0CC_IRQHandler + IRQ MCTM1BRK_IRQHandler + IRQ MCTM1UP_IRQHandler + IRQ MCTM1TR_IRQHandler + IRQ MCTM1CC_IRQHandler + IRQ GPTM0_IRQHandler + IRQ GPTM1_IRQHandler + IRQ BFTM0_IRQHandler + IRQ BFTM1_IRQHandler + IRQ I2C0_IRQHandler + IRQ I2C1_IRQHandler + IRQ SPI0_IRQHandler + IRQ SPI1_IRQHandler + IRQ USART0_IRQHandler + IRQ USART1_IRQHandler + IRQ UART0_IRQHandler + IRQ UART1_IRQHandler + IRQ SCI_IRQHandler + IRQ I2S_IRQHandler + IRQ USB_IRQHandler + IRQ SDIO_IRQHandler + IRQ PDMA_CH0_IRQHandler + IRQ PDMA_CH1_IRQHandler + IRQ PDMA_CH2_IRQHandler + IRQ PDMA_CH3_IRQHandler + IRQ PDMA_CH4_IRQHandler + IRQ PDMA_CH5_IRQHandler + IRQ PDMA_CH6_IRQHandler + IRQ PDMA_CH7_IRQHandler + IRQ PDMA_CH8_IRQHandler + IRQ PDMA_CH9_IRQHandler + IRQ PDMA_CH10_IRQHandler + IRQ PDMA_CH11_IRQHandler + IRQ CSIF_IRQHandler + IRQ EBI_IRQHandler + IRQ AES_IRQHandler + + .end diff --git a/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/Device/Holtek/HT32F1xxxx/Source/emStudio/startup_ht32f1xxxx_es_03.s b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/Device/Holtek/HT32F1xxxx/Source/emStudio/startup_ht32f1xxxx_es_03.s new file mode 100644 index 0000000000..4360057e33 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/Device/Holtek/HT32F1xxxx/Source/emStudio/startup_ht32f1xxxx_es_03.s @@ -0,0 +1,335 @@ +/*---------------------------------------------------------------------------------------------------------*/ +/* Holtek Semiconductor Inc. */ +/* */ +/* Copyright (C) Holtek Semiconductor Inc. */ +/* All rights reserved. */ +/* */ +/*----------------------------------------------------------------------------------------------------------- +; File Name : startup_ht32f1xxxx_es_03.s +; Version : $Rev:: 1771 $ +; Date : $Date:: 2019-07-25 #$ +; Description : Startup code. +;-----------------------------------------------------------------------------------------------------------*/ + +/* +; Supported Device +; ======================================== +; HT32F12364 +*/ + +;/* <<< Use Configuration Wizard in Context Menu >>> */ +/* +;// HT32 Device +;// <0=> By Project Asm Define +;// <16=> HT32F12364 +*/ + .equ USE_HT32_CHIP_SET, 0 + + .equ _HT32FWID, 0xFFFFFFFF +/* + .equ _HT32FWID, 0x00012364 +*/ + + .equ HT32F12364, 16 + + .if USE_HT32_CHIP_SET == 0 + .else + .equ USE_HT32_CHIP, USE_HT32_CHIP_SET + .endif + + .equ _RESERVED, 0xFFFFFFFF +/* +;******************************************************************************* +; Fill-up the Vector Table entries with the exceptions ISR address +;********************************************************************************/ + .syntax unified + .global reset_handler + .global Reset_Handler + .equ Reset_Handler, reset_handler + + .section .vectors, "ax" + .section .vectors, "ax" + .code 16 + .balign 2 + .global _vectors +_vectors: + .long __stack_end__ /* ---, 00, 0x000, Top address of Stack */ + .long reset_handler /* ---, 01, 0x004, Reset Handler */ + .long NMI_Handler /* ---, 02, 0x008, NMI Handler */ + .long HardFault_Handler /* ---, 03, 0x00C, Hard Fault Handler */ + .long MemManage_Handler /* ---, 04, 0x010, MPU Fault Handler */ + .long BusFault_Handler /* ---, 05, 0x014, Bus Fault Handler */ + .long UsageFault_Handler /* ---, 06, 0x018, Usage Fault Handler */ + .long _RESERVED /* ---, 07, 0x01C, Reserved */ + .long _HT32FWID /* ---, 08, 0x020, Reserved */ + .long _RESERVED /* ---, 09, 0x024, Reserved */ + .long _RESERVED /* ---, 10, 0x028, Reserved */ + .long SVC_Handler /* ---, 11, 0x02C, SVC Handler */ + .long DebugMon_Handler /* ---, 12, 0x030, Debug Monitor Handler */ + .long _RESERVED /* ---, 13, 0x034, Reserved */ + .long PendSV_Handler /* ---, 14, 0x038, PendSV Handler */ + .long SysTick_Handler /* ---, 15, 0x03C, SysTick Handler */ + + /* External Interrupt Handler */ + .long CKRDY_IRQHandler /* 00, 16, 0x040, */ + .long LVD_IRQHandler /* 01, 17, 0x044, */ + .long BOD_IRQHandler /* 02, 18, 0x048, */ + .long _RESERVED /* 03, 19, 0x04C, */ + .long RTC_IRQHandler /* 04, 20, 0x050, */ + .long FLASH_IRQHandler /* 05, 21, 0x054, */ + .long EVWUP_IRQHandler /* 06, 22, 0x058, */ + .long LPWUP_IRQHandler /* 07, 23, 0x05C, */ + .long EXTI0_IRQHandler /* 08, 24, 0x060, */ + .long EXTI1_IRQHandler /* 09, 25, 0x064, */ + .long EXTI2_IRQHandler /* 10, 26, 0x068, */ + .long EXTI3_IRQHandler /* 11, 27, 0x06C, */ + .long EXTI4_IRQHandler /* 12, 28, 0x070, */ + .long EXTI5_IRQHandler /* 13, 29, 0x074, */ + .long EXTI6_IRQHandler /* 14, 30, 0x078, */ + .long EXTI7_IRQHandler /* 15, 31, 0x07C, */ + .long EXTI8_IRQHandler /* 16, 32, 0x080, */ + .long EXTI9_IRQHandler /* 17, 33, 0x084, */ + .long EXTI10_IRQHandler /* 18, 34, 0x088, */ + .long EXTI11_IRQHandler /* 19, 35, 0x08C, */ + .long EXTI12_IRQHandler /* 20, 36, 0x090, */ + .long EXTI13_IRQHandler /* 21, 37, 0x094, */ + .long EXTI14_IRQHandler /* 22, 38, 0x098, */ + .long EXTI15_IRQHandler /* 23, 39, 0x09C, */ + .long _RESERVED /* 24, 40, 0x0A0, */ + .long ADC_IRQHandler /* 25, 41, 0x0A4, */ + .long _RESERVED /* 26, 42, 0x0A8, */ + .long _RESERVED /* 27, 43, 0x0AC, */ + .long _RESERVED /* 28, 44, 0x0B0, */ + .long _RESERVED /* 29, 45, 0x0B4, */ + .long _RESERVED /* 30, 46, 0x0B8, */ + .long _RESERVED /* 31, 47, 0x0BC, */ + .long _RESERVED /* 32, 48, 0x0C0, */ + .long _RESERVED /* 33, 49, 0x0C4, */ + .long _RESERVED /* 34, 50, 0x0C8, */ + .long GPTM0_IRQHandler /* 35, 51, 0x0CC, */ + .long _RESERVED /* 36, 52, 0x0D0, */ + .long SCTM0_IRQHandler /* 37, 53, 0x0D4, */ + .long SCTM1_IRQHandler /* 38, 54, 0x0D8, */ + .long PWM0_IRQHandler /* 39, 55, 0x0DC, */ + .long _RESERVED /* 40, 56, 0x0E0, */ + .long BFTM0_IRQHandler /* 41, 57, 0x0E4, */ + .long BFTM1_IRQHandler /* 42, 58, 0x0E8, */ + .long I2C0_IRQHandler /* 43, 59, 0x0EC, */ + .long I2C1_IRQHandler /* 44, 60, 0x0F0, */ + .long SPI0_IRQHandler /* 45, 61, 0x0F4, */ + .long SPI1_IRQHandler /* 46, 62, 0x0F8, */ + .long USART0_IRQHandler /* 47, 63, 0x0FC, */ + .long _RESERVED /* 48, 64, 0x100, */ + .long UART0_IRQHandler /* 49, 65, 0x104, */ + .long UART1_IRQHandler /* 50, 66, 0x108, */ + .long SCI_IRQHandler /* 51, 67, 0x10C, */ + .long _RESERVED /* 52, 68, 0x110, */ + .long USB_IRQHandler /* 53, 69, 0x114, */ + .long _RESERVED /* 54, 70, 0x118, */ + .long PDMA_CH0_IRQHandler /* 55, 71, 0x11C, */ + .long PDMA_CH1_IRQHandler /* 56, 72, 0x120, */ + .long PDMA_CH2_IRQHandler /* 57, 73, 0x124, */ + .long PDMA_CH3_IRQHandler /* 58, 74, 0x128, */ + .long PDMA_CH4_IRQHandler /* 59, 75, 0x12C, */ + .long PDMA_CH5_IRQHandler /* 60, 76, 0x130, */ + .long _RESERVED /* 61, 77, 0x134, */ + .long _RESERVED /* 62, 78, 0x138, */ + .long _RESERVED /* 63, 79, 0x13C, */ + .long _RESERVED /* 64, 80, 0x140, */ + .long _RESERVED /* 65, 81, 0x144, */ + .long _RESERVED /* 66, 82, 0x148, */ + .long _RESERVED /* 67, 83, 0x14C, */ + .long _RESERVED /* 68, 84, 0x150, */ + .long AES_IRQHandler /* 69, 85, 0x154, */ + + + + .thumb + + +/* Reset Handler */ + + .section .text.reset_handler + .weak reset_handler + .type reset_handler, %function +reset_handler: + LDR R0, =__stack_end__ /* set stack pointer */ + MOV SP, R0 + LDR R0, =BootProcess + BLX R0 + LDR R0, =SystemInit + BLX R0 + BL _start + + .thumb_func +BootProcess: + LDR R0, =0x40080300 + LDR R1,[R0, #0x10] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x14] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x18] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x1C] + CMP R1, #0 + BEQ BP2 +BP1: + LDR R0, =0x40080180 + LDR R1,[R0, #0xC] + LSLS R1, R1, #4 + LSRS R1, R1, #20 + CMP R1, #0 + BEQ BP3 + CMP R1, #1 + BEQ BP3 + CMP R1, #2 + BEQ BP3 +BP2: + DSB + LDR R0, =0x20000000 + LDR R1, =0x05fa0004 + STR R1, [R0] + LDR R1, =0xe000ed00 + LDR R0, =0x05fa0004 + STR R0, [R1, #0xC] + DSB + B . +BP3: + LDR R0, =0x20000000 + LDR R1, [R0] + LDR R0, =0x05fa0004 + CMP R0, R1 + BEQ BP4 + BX LR +BP4: + LDR R0, =0x40088100 + LDR R1, =0x00000001 + STR R1, [R0] + LDR R0, =0x20000000 + LDR R1, =0x0 + STR R1, [R0] + BX LR + + .size Reset_Handler, .-Reset_Handler + +/* Exception Handlers */ + + .weak NMI_Handler + .type NMI_Handler, %function +NMI_Handler: + B . + .size NMI_Handler, . - NMI_Handler + + .weak HardFault_Handler + .type HardFault_Handler, %function +HardFault_Handler: + B . + .size HardFault_Handler, . - HardFault_Handler + + .weak MemManage_Handler + .type MemManage_Handler, %function +MemManage_Handler: + B . + .size MemManage_Handler, . - MemManage_Handler + + .weak BusFault_Handler + .type BusFault_Handler, %function +BusFault_Handler: + B . + .size BusFault_Handler, . - BusFault_Handler + + .weak UsageFault_Handler + .type UsageFault_Handler, %function +UsageFault_Handler: + B . + .size UsageFault_Handler, . - UsageFault_Handler + + .weak SVC_Handler + .type SVC_Handler, %function +SVC_Handler: + B . + .size SVC_Handler, . - SVC_Handler + + .weak DebugMon_Handler + .type DebugMon_Handler, %function +DebugMon_Handler: + B . + .size DebugMon_Handler, . - DebugMon_Handler + + .weak PendSV_Handler + .type PendSV_Handler, %function +PendSV_Handler: + B . + .size PendSV_Handler, . - PendSV_Handler + + .weak SysTick_Handler + .type SysTick_Handler, %function +SysTick_Handler: + B . + .size SysTick_Handler, . - SysTick_Handler + + +/* IRQ Handlers */ + + .globl Default_Handler + .type Default_Handler, %function +Default_Handler: + B . + .size Default_Handler, . - Default_Handler + + .macro IRQ handler + .weak \handler + .set \handler, Default_Handler + .endm + + IRQ CKRDY_IRQHandler + IRQ LVD_IRQHandler + IRQ BOD_IRQHandler + IRQ RTC_IRQHandler + IRQ FLASH_IRQHandler + IRQ EVWUP_IRQHandler + IRQ LPWUP_IRQHandler + IRQ EXTI0_IRQHandler + IRQ EXTI1_IRQHandler + IRQ EXTI2_IRQHandler + IRQ EXTI3_IRQHandler + IRQ EXTI4_IRQHandler + IRQ EXTI5_IRQHandler + IRQ EXTI6_IRQHandler + IRQ EXTI7_IRQHandler + IRQ EXTI8_IRQHandler + IRQ EXTI9_IRQHandler + IRQ EXTI10_IRQHandler + IRQ EXTI11_IRQHandler + IRQ EXTI12_IRQHandler + IRQ EXTI13_IRQHandler + IRQ EXTI14_IRQHandler + IRQ EXTI15_IRQHandler + IRQ ADC_IRQHandler + IRQ GPTM0_IRQHandler + IRQ SCTM0_IRQHandler + IRQ SCTM1_IRQHandler + IRQ PWM0_IRQHandler + IRQ BFTM0_IRQHandler + IRQ BFTM1_IRQHandler + IRQ I2C0_IRQHandler + IRQ I2C1_IRQHandler + IRQ SPI0_IRQHandler + IRQ SPI1_IRQHandler + IRQ USART0_IRQHandler + IRQ UART0_IRQHandler + IRQ UART1_IRQHandler + IRQ SCI_IRQHandler + IRQ USB_IRQHandler + IRQ PDMA_CH0_IRQHandler + IRQ PDMA_CH1_IRQHandler + IRQ PDMA_CH2_IRQHandler + IRQ PDMA_CH3_IRQHandler + IRQ PDMA_CH4_IRQHandler + IRQ PDMA_CH5_IRQHandler + IRQ AES_IRQHandler + + .end diff --git a/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/Device/Holtek/HT32F1xxxx/Source/system_ht32f1xxxx_01.c b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/Device/Holtek/HT32F1xxxx/Source/system_ht32f1xxxx_01.c new file mode 100644 index 0000000000..37cb60ba18 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/Device/Holtek/HT32F1xxxx/Source/system_ht32f1xxxx_01.c @@ -0,0 +1,462 @@ +/**************************************************************************//** + * @file library/Device/Holtek/HT32F1xxxx/Source/system_ht32f1xxxx_01.c + * @brief CMSIS Cortex-M3 Device Peripheral Access Layer Source File + * for the Holtek HT32F165x Device Series + * @version $Rev:: 2817 $ + * @date $Date:: 2022-12-27 #$ + * + * @note + * Copyright (C) Holtek Semiconductor Inc. All rights reserved. + * + * @par + * ARM Limited (ARM) supplies this software for Cortex-M processor-based + * microcontrollers. This file can be freely distributed within development + * tools that are supporting such ARM based processors. + * + * @par + * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR + * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + ******************************************************************************/ + +// Supported Device +// ======================================== +// HT32F1653, HT32F1654 +// HT32F1655, HT32F1656 + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup HT32F1xxxx_system HT32F1xxxx System + * @{ + */ + + +#include "ht32f1xxxx_01.h" + +/** @addtogroup HT32F1xxxx_System_Private_Defines + * @{ + */ +/* +//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ +*/ + +/*--------------------- Clock Configuration ---------------------------------- +// +// Enable High Speed External Crystal Oscillator (HSE) +// Default HSE = DISABLE +// +// Enable Low Speed External Crystal Oscillator (LSE) +// Default LSE = DISABLE +// +// Enable PLL +// Default PLL = DISABLE +// PLL Out = ((HSE or HSI) x NF2 ) / NO2 +// PLL Clock Source +// <0=> CK_HSE +// <1=> CK_HSI +// Default PLL clock source = CK_HSI +// PLL source clock must be in the range of 4 MHz to 16 MHz +// PLL Feedback Clock Divider (NF2): 1 ~ 64 +// <1-64:1> +// PLL feedback clock = PLL clock source x NF2 +// PLL feedback clock must be in the range of 64 MHz to 144 MHz +// PLL Output Clock Divider (NO2) +// <0=> 1 +// <1=> 2 +// <2=> 4 +// <3=> 8 +// PLL output clock = PLL feedback clock / NO2 +// PLL output clock must be in the range of 8 MHz to 144 MHz +// +// +// SystemCoreClock Configuration (CK_AHB) +// SystemCoreClock Source +// <1=> CK_PLL +// <2=> CK_HSE +// <3=> CK_HSI +// Default SystemCoreClock source = CK_HSI +// SystemCoreClock Source Divider +// <0=> 1 +// <1=> 2 +// <2=> 4 +// <3=> 8 +// Default SystemCoreClock source divider = 1 +// +// +// FLASH Configuration +// Wait state +// <0=> 0 WS +// <1=> 1 WS +// <2=> 2 WS +// <9=> AUTO +// 0 WS: 1 MHz <= CK_AHB <= 24 MHz +// 1 WS: 24 MHz < CK_AHB <= 48 MHz +// 2 WS: 48 MHz < CK_AHB <= 72 MHz +// Pre-fetch Buffer Enable +// Default pre-fetch buffer = ENABLE +// Branch cache Enable +// Default branch cache = ENABLE +// Dcode cache-able +// <0=> YES +// <1=> NO +// Default Dcode cache-able = NO +// +// +*/ + +/* !!! NOTICE !!! + HSI must keep turn on when doing the Flash operation (Erase/Program). +*/ + +/* !!! NOTICE !!! + * How to adjust the value of High Speed External oscillator (HSE)? + The default value of HSE is define by "HSE_VALUE" in "ht32fxxxxx_nn.h". + If your board uses a different HSE speed, please add a new compiler preprocessor + C define, "HSE_VALUE=n000000" ("n" represents n MHz) in the toolchain/IDE, + or edit the "HSE_VALUE" in the "ht32f1xxxx_conf.h" file. + Take Keil MDK-ARM for instance, to set HSE as 16 MHz: + "Option of Taret -> C/C++ > Preprocessor Symbols" + Define: USE_HT32_DRIVER, USE_HT32Fxxxxx_SK, USE_HT32Fxxxxx_xx, USE_MEM_HT32Fxxxxx, HSE_VALUE=16000000 + ^^ Add "HSE_VALUE" + define as above. +*/ +#define HSI_ENABLE (1) /*!< 0: DISABLE, 1: ENABLE */ +#define HSE_ENABLE (1) /*!< 0: DISABLE, 1: ENABLE */ +#define LSI_ENABLE (1) /*!< 0: DISABLE, 1: ENABLE */ +#define LSE_ENABLE (0) /*!< 0: DISABLE, 1: ENABLE */ +#define PLL_ENABLE (1) /*!< 0: DISABLE, 1: ENABLE */ +#define PLL_CLK_SRC (0) /*!< 0: HSE, 1: HSI */ +#define PLL_NF2_DIV (18) /*!< 1~64: DIV1~DIV64 */ +#define PLL_NO2_DIV (0) /*!< 0: DIV1, 1: DIV2, 2: DIV4, 3: DIV8 */ +#define HCLK_SRC (1) /*!< 0: PLL, 1: PLL, 2: HSE, 3: HSI */ +#define HCLK_DIV (1) /*!< 0: DIV1, 1: DIV2, 2: DIV4, 3: DIV8 */ +#define WAIT_STATE (9) /*!< 0: WS = 0, 1: WS = 1, 2: WS = 2, 9: WS = AUTO */ +#define PRE_FETCH_ENABLE (1) /*!< 0: DISABLE, 1: ENABLE */ +#define BCACHE_ENABLE (1) /*!< 0: DISABLE, 1: ENABLE */ +#define DCODE_CACHE_ABLE (1) /*!< 0: YES, 1: NO */ +#define DEINIT_ENABLE (1) /* Set 0 for reduce code size */ + +/*----------------------------------------------------------------------------------------------------------*/ +/* PLL Out = ((HSE or HSI) x PLL_NF2) / PLL_NO2 */ +/*----------------------------------------------------------------------------------------------------------*/ + + +/*--------------------- WDT Configuration ---------------------------------- +// +// Enable WDT Configuration +// WDT Prescaler Selection +// <0=> CK_WDT / 1 +// <1=> CK_WDT / 2 +// <2=> CK_WDT / 4 +// <3=> CK_WDT / 8 +// <4=> CK_WDT / 16 +// <5=> CK_WDT / 32 +// <6=> CK_WDT / 64 +// <7=> CK_WDT / 128 +// WDT Reload Value <1-4095:1> +// Enable WDT Reset function +// WDT Sleep Halt mode +// <0=> No halt +// <1=> Halt in DeepSleep1 +// <2=> Halt in Sleep & DeepSleep1 +// +*/ +#define WDT_ENABLE (0) /*!< 0: DISABLE, 1: ENABLE */ +#define WDT_PRESCALER (5) /*!< 0: 1/1, 1: 1/2, 2: 1/4, 3: 1/8, 4: 1/16, 5: 1/32, 6: 1/64, 7: 1/128 */ +#define WDT_RELOAD (2000) /*!< 0 ~ 4095, 12 bit */ +#define WDT_RESET_ENABLE (1) /*!< 0: No Reset, 1: Reset when WDT over flow */ +#define WDT_SLEEP_HALT (2) /*!< 0: No halt, 1: Halt in DeepSleep1, 2: Halt in Sleep & DeepSleep1 */ + +/** + * @brief Check HSI frequency + */ +#if (HSI_VALUE != 8000000UL) + #error "CK_HSI clock issue: must be 8 MHz!" +#endif + +/** + * @brief Check HSE frequency + */ +#if ((HSE_VALUE < 4000000UL) || (HSE_VALUE > 16000000UL)) + #error "CK_HSE clock issue: must be in the range of 4 MHz to 16 MHz!" +#endif + +/** + * @brief Check LSI frequency + */ +#if (LSI_VALUE != 32000UL) + #error "CK_LSI clock issue: must be 32 kHz!" +#endif + +/** + * @brief Check LSE frequency + */ +#if (LSE_VALUE != 32768UL) + #error "CK_LSE clock issue: must be 32.768 kHz!" +#endif + +/** + * @brief CK_PLL definition + */ +#if (PLL_ENABLE == 1) + /* Get CK_VCO frequency */ + #if (PLL_CLK_SRC == 1) + #if (HSI_ENABLE == 0) + #error "CK_PLL clock source issue: HSI has not been enabled" + #else + #define __CK_VCO (HSI_VALUE * PLL_NF2_DIV) /*!< Select HSI as PLL source */ + #endif + #else + #if (HSE_ENABLE == 0) + #error "CK_PLL clock source issue: HSE has not been enabled!" + #else + #define __CK_VCO (HSE_VALUE * PLL_NF2_DIV) /*!< Select HSE as PLL source */ + #endif + #endif + + #define VCO_MIN 64000000UL + #define VCO_MAX 144000000UL + #define PLL_MIN 8000000UL + #define PLL_MAX 144000000UL + + /* Check CK_VCO frequency */ + #if ((__CK_VCO < VCO_MIN) || (__CK_VCO > VCO_MAX)) + #error "CK_VCO clock issue: must be in the range!" + #endif + + #define __CK_PLL (__CK_VCO >> PLL_NO2_DIV) /*!< Get CK_PLL frequency */ + + /* Check CK_PLL frequency */ + #if ((__CK_PLL < PLL_MIN) || (__CK_PLL > PLL_MAX)) + #error "CK_PLL clock issue: must be in the range!" + #endif +#endif + +/** + * @brief CK_SYS definition + */ +#if (HCLK_SRC == 1) + #if (PLL_ENABLE == 1) + #define __CK_SYS __CK_PLL /*!< Select PLL as CK_SYS source */ + #else + #error "CK_SYS clock source issue: PLL is not enable!" + #endif +#elif (HCLK_SRC == 2) + #if (HSE_ENABLE == 1) + #define __CK_SYS HSE_VALUE /*!< Select HSE as CK_SYS source */ + #else + #error "CK_SYS clock source issue: HSE is not enable!" + #endif +#elif (HCLK_SRC == 3) + #if (HSI_ENABLE == 1) + #define __CK_SYS HSI_VALUE /*!< Select HSI as CK_SYS source */ + #else + #error "CK_SYS clock source issue: HSI is not enable!" + #endif +#endif + +/** + * @brief CK_AHB definition + */ +#define __CK_AHB (__CK_SYS >> HCLK_DIV) /*!< Get CK_AHB frequency */ + +#define CKAHB_MIN 1000000UL +#define CKAHB_MAX 72000000UL +#define WS0_CLK 24000000UL +#define WS1_CLK 48000000UL + +/* Check CK_AHB frequency */ +#if ((__CK_AHB < CKAHB_MIN) || (__CK_AHB > CKAHB_MAX)) + #error "CK_AHB clock issue: must be in the range!" +#endif + +/* Check FLASH wait-state setting */ +#if ((__CK_AHB > WS1_CLK) && (WAIT_STATE < 2) || \ + (__CK_AHB > WS0_CLK) && (WAIT_STATE < 1)) + #error "FLASH wait state configuration issue!" +#endif +/** + * @} + */ + +/** @addtogroup HT32F1xxxx_System_Private_Variables + * @{ + */ +__IO uint32_t SystemCoreClock = __CK_AHB; /*!< SystemCoreClock = CK_AHB */ +/** + * @} + */ + +/** @addtogroup HT32F1xxxx_System_Private_Functions + * @{ + */ + +/** + * @brief Setup the microcontroller system. + * Initializes the system clocks and the embedded Flash. + * @note This function should be used after reset. + * @retval None + */ +void SystemInit(void) +{ +#if (WDT_ENABLE == 1) + HT_CKCU->APBCCR1 |= (0x1 << 4); + HT_WDT->PR = 0x35CA; + HT_WDT->MR0 = 0; + HT_WDT->MR1 = ((HT_WDT->MR1 & 0xFFF) | (WDT_PRESCALER << 12)); + HT_WDT->MR0 = WDT_RELOAD | (WDT_RESET_ENABLE << 13) | (WDT_SLEEP_HALT << 14) | (0x1 << 16); + HT_WDT->CR = 0x5FA00001; +#else + #if (DEINIT_ENABLE == 1) + HT_RSTCU->APBPRST1 = (1 << 4); + #endif +#endif + + HT_CKCU->LPCR = 1; /* configure Backup domain isolation */ + SetBit_BB((u32)(&HT_CKCU->APBCCR1), 6); /* enable Backup domain register clock */ + while (HT_PWRCU->TEST != 0x27); /* wait for Backup domain register ready */ + +#if (DEINIT_ENABLE == 1) + /* De-init the setting */ + HT_CKCU->AHBCCR &= ~(0x3 << 10); /* disable IP who may use PLL as source */ + SetBit_BB((u32)(&HT_CKCU->GCCR), 11); /* enable HSI */ + while (!GetBit_BB((u32)(&HT_CKCU->GCSR), 3)); /* wait for HSI ready */ + HT_CKCU->GCCR = ((HT_CKCU->GCCR & ~7UL) | 3UL); /* select CK_SYS source */ + while (((HT_CKCU->CKST >> 30) & 3UL) != 3UL); /* wait for clock switch complete */ + HT_FLASH->CFCR = (((HT_FLASH->CFCR) & ~7UL) | 1UL); /* set Wait State as 0 WS */ + HT_CKCU->AHBCFGR = 0; /* set CK_AHB prescaler */ + ResetBit_BB((u32)(&HT_CKCU->GCCR), 9); /* disable PLL */ + SetBit_BB((u32)(&HT_CKCU->GCFGR), 8); /* select PLL source as HSI */ +#endif + + /* HSE initiation */ +#if (HSE_ENABLE == 1) + SetBit_BB((u32)(&HT_CKCU->GCCR), 10); /* enable HSE */ + while (!GetBit_BB((u32)(&HT_CKCU->GCSR), 2)){}; /* wait for HSE ready */ +#endif + + /* LSE initiation */ +#if (LSE_ENABLE == 1) + do { + SetBit_BB((u32)(&HT_RTC->CR), 3); /* enable LSE */ + } while (!GetBit_BB((u32)(&HT_RTC->CR), 3)); + while (!GetBit_BB((u32)(&HT_CKCU->GCSR), 4)); /* wait for LSE ready */ +#endif + + ResetBit_BB((u32)(&HT_CKCU->APBCCR1), 6); /* disable Backup domain register clock */ + + /* PLL initiation */ +#if (PLL_ENABLE == 1) + #if (PLL_CLK_SRC == 0) + ResetBit_BB((u32)(&HT_CKCU->GCFGR), 8); /* select PLL source as HSE */ + #else + SetBit_BB((u32)(&HT_CKCU->GCFGR), 8); /* select PLL source as HSI */ + #endif + HT_CKCU->PLLCFGR = ((PLL_NF2_DIV & 0x3F) << 23) | (PLL_NO2_DIV << 21); /* set PLL divider */ + SetBit_BB((u32)(&HT_CKCU->GCCR), 9); /* enable PLL */ + while (!GetBit_BB((u32)(&HT_CKCU->GCSR), 1)){}; /* wait for PLL ready */ +#endif + + /* CK_AHB initiation */ +#if (WAIT_STATE == 9) + #if (__CK_AHB > WS1_CLK) + HT_FLASH->CFCR = (((HT_FLASH->CFCR) & ~7UL) | 3UL); /* auto-select wait state */ + #elif (__CK_AHB > WS0_CLK) + HT_FLASH->CFCR = (((HT_FLASH->CFCR) & ~7UL) | 2UL); /* auto-select wait state */ + #endif +#else + HT_FLASH->CFCR = (((HT_FLASH->CFCR) & ~7UL) | (WAIT_STATE + 1)); /* manual wait state */ +#endif + + HT_CKCU->AHBCFGR = HCLK_DIV; /* set CK_AHB prescaler */ + HT_CKCU->GCCR = ((HT_CKCU->GCCR & ~3UL) | HCLK_SRC); /* select CK_SYS source */ + while (((HT_CKCU->CKST >> 30) & 3UL) != HCLK_SRC); /* wait for clock switch complete */ + + /* Pre-fetch buffer configuration */ +#if (PRE_FETCH_ENABLE == 0) + ResetBit_BB((u32)(&HT_FLASH->CFCR), 4); /* 0: pre-fetch disable, 1: pre-fetch enable */ +#else + SetBit_BB((u32)(&HT_FLASH->CFCR), 4); /* 0: pre-fetch disable, 1: pre-fetch enable */ +#endif + + /* Branch cache configuration */ +#if (BCACHE_ENABLE == 0) + ResetBit_BB((u32)(&HT_FLASH->CFCR), 12); /* 0: branch cache disable, 1: branch cache enable */ +#else + SetBit_BB((u32)(&HT_FLASH->CFCR), 12); /* 0: branch cache disable, 1: branch cache enable */ + #if (DCODE_CACHE_ABLE == 0) + ResetBit_BB((u32)(&HT_FLASH->CFCR), 7); /* 0: DCODE cache-able, 1: DCODE non cache-able */ + #else + SetBit_BB((u32)(&HT_FLASH->CFCR), 7); /* 0: DCODE cache-able, 1: DCODE non cache-able */ + #endif +#endif + + /* HSE power down */ +#if ((HSE_ENABLE == 0) && (HCLK_SRC != 2) && ((PLL_ENABLE == 0) || (PLL_CLK_SRC == 1))) + ResetBit_BB((u32)(&HT_CKCU->GCCR), 10); +#endif + + /* HSI power down */ +#if ((HSI_ENABLE == 0) && (HCLK_SRC != 3) && ((PLL_ENABLE == 0) || (PLL_CLK_SRC == 0))) + ResetBit_BB((u32)(&HT_CKCU->GCCR), 11); +#endif +} + +/** + * @brief Update SystemCoreClock + * @retval None + */ +void SystemCoreClockUpdate(void) +{ + u32 SystemCoreClockDiv = HT_CKCU->AHBCFGR & 3UL; + u32 PllFeedbackClockDiv = ((HT_CKCU->PLLCFGR >> 23) == 0) ? (64) : (HT_CKCU->PLLCFGR >> 23); + u32 PllOutputClockDiv = (HT_CKCU->PLLCFGR >> 21) & 3UL; + u32 SystemCoreClockSrc = (HT_CKCU->CKST >> 30) & 3UL; + + /* Get system core clock according to global clock control & configuration registers */ + if (SystemCoreClockSrc == 1) + { + if (GetBit_BB((u32)(&HT_CKCU->PLLCR), 31)) + { + PllFeedbackClockDiv = 1; + PllOutputClockDiv = 0; + } + + if (GetBit_BB((u32)(&HT_CKCU->GCFGR), 8)) + { + SystemCoreClock = ((HSI_VALUE * PllFeedbackClockDiv) >> PllOutputClockDiv) >> SystemCoreClockDiv; + } + else + { + SystemCoreClock = ((HSE_VALUE * PllFeedbackClockDiv) >> PllOutputClockDiv) >> SystemCoreClockDiv; + } + } + else if (SystemCoreClockSrc == 2) + { + SystemCoreClock = HSE_VALUE >> SystemCoreClockDiv; + } + else if (SystemCoreClockSrc == 3) + { + SystemCoreClock = HSI_VALUE >> SystemCoreClockDiv; + } +} + +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ + +/******************* (C) COPYRIGHT Holtek Semiconductor Inc. *****END OF FILE*** */ diff --git a/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/Device/Holtek/HT32F1xxxx/Source/system_ht32f1xxxx_02.c b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/Device/Holtek/HT32F1xxxx/Source/system_ht32f1xxxx_02.c new file mode 100644 index 0000000000..c0d6be9038 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/Device/Holtek/HT32F1xxxx/Source/system_ht32f1xxxx_02.c @@ -0,0 +1,525 @@ +/**************************************************************************//** + * @file library/Device/Holtek/HT32F1xxxx/Source/system_ht32f1xxxx_02.c + * @brief CMSIS Cortex-M3 Device Peripheral Access Layer Source File + * for the Holtek HT32F1xxxx Device Series + * @version $Rev:: 2817 $ + * @date $Date:: 2022-12-27 #$ + * + * @note + * Copyright (C) Holtek Semiconductor Inc. All rights reserved. + * + * @par + * ARM Limited (ARM) supplies this software for Cortex-M processor-based + * microcontrollers. This file can be freely distributed within development + * tools that are supporting such ARM based processors. + * + * @par + * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR + * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + ******************************************************************************/ + +// Supported Device +// ======================================== +// HT32F12345 +// HT32F12365, HT32F12366 +// HT32F22366 + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup HT32F1xxxx_system HT32F1xxxx System + * @{ + */ + + +#include "ht32f1xxxx_01.h" + +/** @addtogroup HT32F1xxxx_System_Private_Defines + * @{ + */ +/* +//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ +*/ + +/*--------------------- Clock Configuration ---------------------------------- +// +// Enable High Speed External Crystal Oscillator (HSE) +// Default HSE = DISABLE +// +// Enable Low Speed External Crystal Oscillator (LSE) +// Default LSE = DISABLE +// +// Enable PLL +// Default PLL = DISABLE +// PLL Out = ((HSE or HSI) x NF2 ) / NO2 +// PLL Clock Source +// <0=> CK_HSE +// <1=> CK_HSI +// Default PLL clock source = CK_HSI +// PLL source clock must be in the range of 4 MHz to 16 MHz +// PLL Feedback Clock Divider (NF2): 1 ~ 32 +// <1-32:1> +// PLL feedback clock = PLL clock source x NF2 +// PLL feedback clock must be in the range of 64 MHz to 96 MHz +// PLL Output Clock Divider (NO2) +// <0=> 1 +// <1=> 2 +// <2=> 4 +// <3=> 8 +// PLL output clock = PLL feedback clock / NO2 +// PLL output clock must be in the range of 8 MHz to 96 MHz +// +// +// SystemCoreClock Configuration (CK_AHB) +// SystemCoreClock Source +// <1=> CK_PLL +// <2=> CK_HSE +// <3=> CK_HSI +// <6=> CK_LSE +// <7=> CK_LSI +// Default SystemCoreClock source = CK_HSI +// SystemCoreClock Source Divider +// <0=> 1 +// <1=> 2 +// <2=> 4 +// <3=> 8 +// <4=> 16 +// <5=> 32 +// Default SystemCoreClock source divider = 1 +// +// +// FLASH Configuration +// Wait state +// <0=> 0 WS +// <1=> 1 WS +// <2=> 2 WS +// <3=> 3 WS +// <9=> AUTO +// 0 WS: 1 kHz <= CK_AHB <= 24 MHz +// 1 WS: 24 MHz < CK_AHB <= 48 MHz +// 2 WS: 48 MHz < CK_AHB <= 72 MHz +// 3 WS: 72 MHz < CK_AHB <= 96 MHz +// Pre-fetch Buffer Enable +// Default pre-fetch buffer = ENABLE +// Branch cache Enable +// Default branch cache = ENABLE +// Dcode cache-able +// <0=> YES +// <1=> NO +// Default Dcode cache-able = NO +// +// +*/ + +/* !!! NOTICE !!! + HSI must keep turn on when doing the Flash operation (Erase/Program). +*/ + +/* !!! NOTICE !!! + * How to adjust the value of High Speed External oscillator (HSE)? + The default value of HSE is define by "HSE_VALUE" in "ht32fxxxxx_nn.h". + If your board uses a different HSE speed, please add a new compiler preprocessor + C define, "HSE_VALUE=n000000" ("n" represents n MHz) in the toolchain/IDE, + or edit the "HSE_VALUE" in the "ht32f1xxxx_conf.h" file. + Take Keil MDK-ARM for instance, to set HSE as 16 MHz: + "Option of Taret -> C/C++ > Preprocessor Symbols" + Define: USE_HT32_DRIVER, USE_HT32Fxxxxx_SK, USE_HT32Fxxxxx_xx, USE_MEM_HT32Fxxxxx, HSE_VALUE=16000000 + ^^ Add "HSE_VALUE" + define as above. +*/ +#define HSI_ENABLE (1) /*!< 0: DISABLE, 1: ENABLE */ +#define HSE_ENABLE (1) /*!< 0: DISABLE, 1: ENABLE */ +#define LSI_ENABLE (1) /*!< 0: DISABLE, 1: ENABLE */ +#define LSE_ENABLE (0) /*!< 0: DISABLE, 1: ENABLE */ +#define PLL_ENABLE (1) /*!< 0: DISABLE, 1: ENABLE */ +#define PLL_CLK_SRC (0) /*!< 0: HSE, 1: HSI */ +#define PLL_NF2_DIV (12) /*!< 1~32: DIV1~DIV32 */ +#define PLL_NO2_DIV (0) /*!< 0: DIV1, 1: DIV2, 2: DIV4, 3: DIV8 */ +#define HCLK_SRC (1) /*!< 0: PLL, 1: PLL, 2: HSE, 3: HSI 6: LSE, 7: LSI */ +#define HCLK_DIV (0) /*!< 0: DIV1, 1: DIV2, 2: DIV4, 3: DIV8, 4: DIV16, 5: DIV32 */ +#define WAIT_STATE (9) /*!< 0: WS = 0, 1: WS = 1, 2: WS = 2, 3: WS = 3, 9: WS = AUTO */ +#define PRE_FETCH_ENABLE (1) /*!< 0: DISABLE, 1: ENABLE */ +#define BCACHE_ENABLE (1) /*!< 0: DISABLE, 1: ENABLE */ +#define DCODE_CACHE_ABLE (1) /*!< 0: YES, 1: NO */ +#define DEINIT_ENABLE (1) /* Set 0 for reduce code size */ + +/*----------------------------------------------------------------------------------------------------------*/ +/* PLL Out = ((HSE or HSI) x PLL_NF2) / PLL_NO2 */ +/*----------------------------------------------------------------------------------------------------------*/ + + +/*--------------------- WDT Configuration ---------------------------------- +// +// Enable WDT Configuration +// WDT Prescaler Selection +// <0=> CK_WDT / 1 +// <1=> CK_WDT / 2 +// <2=> CK_WDT / 4 +// <3=> CK_WDT / 8 +// <4=> CK_WDT / 16 +// <5=> CK_WDT / 32 +// <6=> CK_WDT / 64 +// <7=> CK_WDT / 128 +// WDT Reload Value <1-4095:1> +// Enable WDT Reset function +// WDT Sleep Halt mode +// <0=> No halt +// <1=> Halt in DeepSleep1 +// <2=> Halt in Sleep & DeepSleep1 +// +*/ +#define WDT_ENABLE (0) /*!< 0: DISABLE, 1: ENABLE */ +#define WDT_PRESCALER (5) /*!< 0: 1/1, 1: 1/2, 2: 1/4, 3: 1/8, 4: 1/16, 5: 1/32, 6: 1/64, 7: 1/128 */ +#define WDT_RELOAD (2000) /*!< 0 ~ 4095, 12 bit */ +#define WDT_RESET_ENABLE (1) /*!< 0: No Reset, 1: Reset when WDT over flow */ +#define WDT_SLEEP_HALT (2) /*!< 0: No halt, 1: Halt in DeepSleep1, 2: Halt in Sleep & DeepSleep1 */ + +/** + * @brief Check HSI frequency + */ +#if (HSI_VALUE != 8000000UL) + #error "CK_HSI clock issue: must be 8 MHz!" +#endif + +/** + * @brief Check HSE frequency + */ +#if ((HSE_VALUE < 4000000UL) || (HSE_VALUE > 16000000UL)) + #error "CK_HSE clock issue: must be in the range of 4 MHz to 16 MHz!" +#endif + +/** + * @brief Check LSI frequency + */ +#if (LSI_VALUE != 32000UL) + #error "CK_LSI clock issue: must be 32 kHz!" +#endif + +/** + * @brief Check LSE frequency + */ +#if (LSE_VALUE != 32768UL) + #error "CK_LSE clock issue: must be 32.768 kHz!" +#endif + +/** + * @brief CK_PLL definition + */ +#if (PLL_ENABLE == 1) + /* Get CK_VCO frequency */ + #if (PLL_CLK_SRC == 1) + #if (HSI_ENABLE == 0) + #error "CK_PLL clock source issue: HSI has not been enabled" + #else + #define __CK_VCO (HSI_VALUE * PLL_NF2_DIV) /*!< Select HSI as PLL source */ + #endif + #else + #if (HSE_ENABLE == 0) + #error "CK_PLL clock source issue: HSE has not been enabled!" + #else + #define __CK_VCO (HSE_VALUE * PLL_NF2_DIV) /*!< Select HSE as PLL source */ + #endif + #endif + + #define VCO_MIN 64000000UL + #define VCO_MAX 96000000UL + #define PLL_MIN 8000000UL + #define PLL_MAX 96000000UL + + /* Check CK_VCO frequency */ + #if ((__CK_VCO < VCO_MIN) || (__CK_VCO > VCO_MAX)) + #error "CK_VCO clock issue: must be in the range!" + #endif + + #define __CK_PLL (__CK_VCO >> PLL_NO2_DIV) /*!< Get CK_PLL frequency */ + + /* Check CK_PLL frequency */ + #if ((__CK_PLL < PLL_MIN) || (__CK_PLL > PLL_MAX)) + #error "CK_PLL clock issue: must be in the range!" + #endif +#endif + +/** + * @brief CK_SYS definition + */ +#if (HCLK_SRC == 1) + #if (PLL_ENABLE == 1) + #define __CK_SYS __CK_PLL /*!< Select PLL as CK_SYS source */ + #else + #error "CK_SYS clock source issue: PLL is not enable!" + #endif +#elif (HCLK_SRC == 2) + #if (HSE_ENABLE == 1) + #define __CK_SYS HSE_VALUE /*!< Select HSE as CK_SYS source */ + #else + #error "CK_SYS clock source issue: HSE is not enable!" + #endif +#elif (HCLK_SRC == 3) + #if (HSI_ENABLE == 1) + #define __CK_SYS HSI_VALUE /*!< Select HSI as CK_SYS source */ + #else + #error "CK_SYS clock source issue: HSI is not enable!" + #endif +#elif (HCLK_SRC == 6) + #if (LSE_ENABLE == 1) + #define __CK_SYS LSE_VALUE /*!< Select LSE as CK_SYS source */ + #else + #error "CK_SYS clock source issue: LSE is not enable!" + #endif +#elif (HCLK_SRC == 7) + #if (LSI_ENABLE == 1) + #define __CK_SYS LSI_VALUE /*!< Select LSI as CK_SYS source */ + #else + #error "CK_SYS clock source issue: LSI is not enable!" + #endif +#else + #error "CK_SYS clock source issue: No clock source is selected!" +#endif + +/** + * @brief CK_AHB definition + */ +#define __CK_AHB (__CK_SYS >> HCLK_DIV) /*!< Get CK_AHB frequency */ + +#define CKAHB_MIN 1000UL +#define CKAHB_MAX 96000000UL +#define WS0_CLK 24000000UL +#define WS1_CLK 48000000UL +#define WS2_CLK 72000000UL + +/* Check CK_AHB frequency */ +#if ((__CK_AHB < CKAHB_MIN) || (__CK_AHB > CKAHB_MAX)) + #error "CK_AHB clock issue: must be in the range!" +#endif + +/* Check FLASH wait-state setting */ +#if ((__CK_AHB > WS2_CLK) && (WAIT_STATE < 3) || \ + (__CK_AHB > WS1_CLK) && (WAIT_STATE < 2) || \ + (__CK_AHB > WS0_CLK) && (WAIT_STATE < 1)) + #error "FLASH wait state configuration issue!" +#endif + +/** + * @brief LDO_MODE definition + */ +#if (__CK_AHB > 90000000UL) + #define __LDO_MODE (3) +#elif (__CK_AHB > 80000000UL) + #define __LDO_MODE (2) +#endif +/** + * @} + */ + +/** @addtogroup HT32F1xxxx_System_Private_Variables + * @{ + */ +__IO uint32_t SystemCoreClock = __CK_AHB; /*!< SystemCoreClock = CK_AHB */ +/** + * @} + */ + +/** @addtogroup HT32F1xxxx_System_Private_Functions + * @{ + */ + +/** + * @brief Setup the microcontroller system. + * Initializes the system clocks and the embedded Flash. + * @note This function should be used after reset. + * @retval None + */ +void SystemInit(void) +{ +#if (WDT_ENABLE == 1) + HT_CKCU->APBCCR1 |= (0x1 << 4); + HT_WDT->PR = 0x35CA; + HT_WDT->MR0 = 0; + HT_WDT->MR1 = ((HT_WDT->MR1 & 0xFFF) | (WDT_PRESCALER << 12)); + HT_WDT->MR0 = WDT_RELOAD | (WDT_RESET_ENABLE << 13) | (WDT_SLEEP_HALT << 14) | (0x1 << 16); + HT_WDT->CR = 0x5FA00001; +#else + #if (DEINIT_ENABLE == 1) + HT_RSTCU->APBPRST1 = (1 << 4); + #endif +#endif + + SetBit_BB((u32)(&HT_CKCU->APBCCR1), 6); /* enable Backup domain register clock */ + while (HT_PWRCU->TEST != 0x27); /* wait for Backup domain register ready */ + +#if (DEINIT_ENABLE == 1) + /* De-init the setting */ + HT_CKCU->AHBCCR &= ~(0x3 << 10); /* disable IP who may use PLL as source */ + SetBit_BB((u32)(&HT_CKCU->GCCR), 11); /* enable HSI */ + while (!GetBit_BB((u32)(&HT_CKCU->GCSR), 3)); /* wait for HSI ready */ + HT_CKCU->GCCR = ((HT_CKCU->GCCR & ~7UL) | 3UL); /* select CK_SYS source */ + while ((HT_CKCU->CKST & 7UL) != 3UL); /* wait for clock switch complete */ + HT_FLASH->CFCR = (((HT_FLASH->CFCR) & ~7UL) | 1UL); /* set Wait State as 0 WS */ + HT_CKCU->AHBCFGR = 0; /* set CK_AHB prescaler */ + ResetBit_BB((u32)(&HT_CKCU->GCCR), 9); /* disable PLL */ + SetBit_BB((u32)(&HT_CKCU->GCFGR), 8); /* select PLL source as HSI */ + ResetBit_BB((u32)(&HT_CKCU->GCCR), 3); /* disable USB PLL */ + SetBit_BB((u32)(&HT_CKCU->GCFGR), 9); /* select USB PLL source as HSI */ +#endif + + /* LDO initiation */ +#if (__CK_AHB > 80000000UL) + do { + HT_PWRCU->CR = (HT_PWRCU->CR & ~(3UL << 4)) | (__LDO_MODE << 4); + } while (((HT_PWRCU->CR >> 4) & 3UL) != __LDO_MODE); +#endif + + /* HSE initiation */ +#if (HSE_ENABLE == 1) + SetBit_BB((u32)(&HT_CKCU->GCCR), 10); /* enable HSE */ + while (!GetBit_BB((u32)(&HT_CKCU->GCSR), 2)){}; /* wait for HSE ready */ +#endif + + /* LSE initiation */ +#if (LSE_ENABLE == 1) + do { + SetBit_BB((u32)(&HT_RTC->CR), 3); /* enable LSE */ + } while (!GetBit_BB((u32)(&HT_RTC->CR), 3)); + while (!GetBit_BB((u32)(&HT_CKCU->GCSR), 4)); /* wait for LSE ready */ +#endif + + /* LSI initiation */ +#if (HCLK_SRC == 7) + while (!GetBit_BB((u32)(&HT_CKCU->GCSR), 5)){}; /* wait for LSI ready */ +#endif + + /* PLL initiation */ +#if (PLL_ENABLE == 1) + #if (PLL_CLK_SRC == 0) + ResetBit_BB((u32)(&HT_CKCU->GCFGR), 8); /* select PLL source as HSE */ + #else + SetBit_BB((u32)(&HT_CKCU->GCFGR), 8); /* select PLL source as HSI */ + #endif + HT_CKCU->PLLCFGR = ((PLL_NF2_DIV & 0x1F) << 23) | (PLL_NO2_DIV << 21); /* set PLL divider */ + SetBit_BB((u32)(&HT_CKCU->GCCR), 9); /* enable PLL */ + while (!GetBit_BB((u32)(&HT_CKCU->GCSR), 1)){}; /* wait for PLL ready */ +#endif + + /* CK_AHB initiation */ +#if (WAIT_STATE == 9) + #if (__CK_AHB > WS2_CLK) + HT_FLASH->CFCR = (((HT_FLASH->CFCR) & ~7UL) | 4UL); /* auto-select wait state */ + #elif (__CK_AHB > WS1_CLK) + HT_FLASH->CFCR = (((HT_FLASH->CFCR) & ~7UL) | 3UL); /* auto-select wait state */ + #elif (__CK_AHB > WS0_CLK) + HT_FLASH->CFCR = (((HT_FLASH->CFCR) & ~7UL) | 2UL); /* auto-select wait state */ + #endif +#else + HT_FLASH->CFCR = (((HT_FLASH->CFCR) & ~7UL) | (WAIT_STATE + 1)); /* manual wait state */ +#endif + + HT_CKCU->AHBCFGR = HCLK_DIV; /* set CK_AHB prescaler */ + HT_CKCU->GCCR = ((HT_CKCU->GCCR & ~7UL) | HCLK_SRC); /* select CK_SYS source */ + while ((HT_CKCU->CKST & 7UL) != HCLK_SRC); /* wait for clock switch complete */ + + /* LDO initiation */ +#if (__CK_AHB > 80000000UL) +#else + do { + HT_PWRCU->CR = (HT_PWRCU->CR & ~(3UL << 4)); + } while (((HT_PWRCU->CR >> 4) & 3UL) != 0x0); +#endif + + ResetBit_BB((u32)(&HT_CKCU->APBCCR1), 6); /* disable Backup domain register clock */ + + /* Pre-fetch buffer configuration */ +#if (PRE_FETCH_ENABLE == 0) + ResetBit_BB((u32)(&HT_FLASH->CFCR), 4); /* 0: pre-fetch disable, 1: pre-fetch enable */ +#else + SetBit_BB((u32)(&HT_FLASH->CFCR), 4); /* 0: pre-fetch disable, 1: pre-fetch enable */ +#endif + + /* Branch cache configuration */ +#if (BCACHE_ENABLE == 0) + ResetBit_BB((u32)(&HT_FLASH->CFCR), 12); /* 0: branch cache disable, 1: branch cache enable */ +#else + SetBit_BB((u32)(&HT_FLASH->CFCR), 12); /* 0: branch cache disable, 1: branch cache enable */ + #if (DCODE_CACHE_ABLE == 0) + ResetBit_BB((u32)(&HT_FLASH->CFCR), 7); /* 0: DCODE cache-able, 1: DCODE non cache-able */ + #else + SetBit_BB((u32)(&HT_FLASH->CFCR), 7); /* 0: DCODE cache-able, 1: DCODE non cache-able */ + #endif +#endif + + /* HSE power down */ +#if ((HSE_ENABLE == 0) && (HCLK_SRC != 2) && ((PLL_ENABLE == 0) || (PLL_CLK_SRC == 1))) + ResetBit_BB((u32)(&HT_CKCU->GCCR), 10); +#endif + + /* HSI power down */ +#if ((HSI_ENABLE == 0) && (HCLK_SRC != 3) && ((PLL_ENABLE == 0) || (PLL_CLK_SRC == 0))) + ResetBit_BB((u32)(&HT_CKCU->GCCR), 11); +#endif +} + +/** + * @brief Update SystemCoreClock + * @retval None + */ +void SystemCoreClockUpdate(void) +{ + u32 SystemCoreClockDiv = HT_CKCU->AHBCFGR & 7UL; + u32 PllFeedbackClockDiv = ((HT_CKCU->PLLCFGR >> 23) == 0) ? (32) : (HT_CKCU->PLLCFGR >> 23); + u32 PllOutputClockDiv = (HT_CKCU->PLLCFGR >> 21) & 3UL; + u32 SystemCoreClockSrc = HT_CKCU->CKST & 7UL; + + /* Get system core clock according to global clock control & configuration registers */ + if (SystemCoreClockSrc == 1) + { + if (GetBit_BB((u32)(&HT_CKCU->PLLCR), 31)) + { + PllFeedbackClockDiv = 1; + PllOutputClockDiv = 0; + } + + if (GetBit_BB((u32)(&HT_CKCU->GCFGR), 8)) + { + SystemCoreClock = ((HSI_VALUE * PllFeedbackClockDiv) >> PllOutputClockDiv) >> SystemCoreClockDiv; + } + else + { + SystemCoreClock = ((HSE_VALUE * PllFeedbackClockDiv) >> PllOutputClockDiv) >> SystemCoreClockDiv; + } + } + else if (SystemCoreClockSrc == 2) + { + SystemCoreClock = HSE_VALUE >> SystemCoreClockDiv; + } + else if (SystemCoreClockSrc == 3) + { + SystemCoreClock = HSI_VALUE >> SystemCoreClockDiv; + } + else if (SystemCoreClockSrc == 6) + { + SystemCoreClock = LSE_VALUE >> SystemCoreClockDiv; + } + else if (SystemCoreClockSrc == 7) + { + SystemCoreClock = LSI_VALUE >> SystemCoreClockDiv; + } +} + +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ + +/******************* (C) COPYRIGHT Holtek Semiconductor Inc. *****END OF FILE*** */ diff --git a/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/Device/Holtek/HT32F1xxxx/Source/system_ht32f1xxxx_03.c b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/Device/Holtek/HT32F1xxxx/Source/system_ht32f1xxxx_03.c new file mode 100644 index 0000000000..64d7a6b6f7 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/Device/Holtek/HT32F1xxxx/Source/system_ht32f1xxxx_03.c @@ -0,0 +1,526 @@ +/**************************************************************************//** + * @file library/Device/Holtek/HT32F1xxxx/Source/system_ht32f1xxxx_03.c + * @brief CMSIS Cortex-M3 Device Peripheral Access Layer Source File + * for the Holtek HT32F1xxxx Device Series + * @version $Rev:: 2817 $ + * @date $Date:: 2022-12-27 #$ + * + * @note + * Copyright (C) Holtek Semiconductor Inc. All rights reserved. + * + * @par + * ARM Limited (ARM) supplies this software for Cortex-M processor-based + * microcontrollers. This file can be freely distributed within development + * tools that are supporting such ARM based processors. + * + * @par + * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR + * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + ******************************************************************************/ + +// Supported Device +// ======================================== +// HT32F12364 + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup HT32F1xxxx_system HT32F1xxxx System + * @{ + */ + + +#include "ht32f1xxxx_01.h" + +/** @addtogroup HT32F1xxxx_System_Private_Defines + * @{ + */ +/* +//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ +*/ + +/*--------------------- Clock Configuration ---------------------------------- +// +// Enable High Speed External Crystal Oscillator (HSE) +// Default HSE = DISABLE +// +// Enable Low Speed External Crystal Oscillator (LSE) +// Default LSE = DISABLE +// +// Enable PLL +// Default PLL = DISABLE +// PLL Out = (((HSE or HSI) / SRC_DIV) x NF2 ) / NO2 +// PLL Clock Source +// <0=> CK_HSE +// <1=> CK_HSI +// Default PLL clock source = CK_HSI +// PLL source clock must be in the range of 4 MHz to 16 MHz +// PLL Clock Source Divider (SRC_DIV) +// <0=> 1 +// <1=> 2 +// PLL input clock = PLL Clock Source / (SRC_DIV) +// PLL Feedback Clock Divider (NF2): 1 ~ 32 +// <1-32:1> +// PLL feedback clock = PLL clock source x NF2 +// PLL feedback clock must be in the range of 64 MHz to 76 MHz +// PLL Output Clock Divider (NO2) +// <0=> 1 +// <1=> 2 +// <2=> 4 +// <3=> 8 +// PLL output clock = PLL feedback clock / NO2 +// PLL output clock must be in the range of 8 MHz to 76 MHz +// +// +// SystemCoreClock Configuration (CK_AHB) +// SystemCoreClock Source +// <1=> CK_PLL +// <2=> CK_HSE +// <3=> CK_HSI +// <6=> CK_LSE +// <7=> CK_LSI +// Default SystemCoreClock source = CK_HSI +// SystemCoreClock Source Divider +// <0=> 1 +// <1=> 2 +// <2=> 4 +// <3=> 8 +// <4=> 16 +// <5=> 32 +// Default SystemCoreClock source divider = 1 +// +// +// FLASH Configuration +// Wait state +// <0=> 0 WS +// <1=> 1 WS +// <2=> 2 WS +// <3=> 3 WS +// <9=> AUTO +// 0 WS: 1 kHz <= CK_AHB <= 20 MHz +// 1 WS: 20 MHz < CK_AHB <= 40 MHz +// 2 WS: 40 MHz < CK_AHB <= 60 MHz +// 3 WS: 60 MHz < CK_AHB <= 76 MHz +// Pre-fetch Buffer Enable +// Default pre-fetch buffer = ENABLE +// Branch cache Enable +// Default branch cache = ENABLE +// Dcode cache-able +// <0=> YES +// <1=> NO +// Default Dcode cache-able = NO +// +// +*/ + +/* !!! NOTICE !!! + HSI must keep turn on when doing the Flash operation (Erase/Program). +*/ + +/* !!! NOTICE !!! + * How to adjust the value of High Speed External oscillator (HSE)? + The default value of HSE is define by "HSE_VALUE" in "ht32fxxxxx_nn.h". + If your board uses a different HSE speed, please add a new compiler preprocessor + C define, "HSE_VALUE=n000000" ("n" represents n MHz) in the toolchain/IDE, + or edit the "HSE_VALUE" in the "ht32f1xxxx_conf.h" file. + Take Keil MDK-ARM for instance, to set HSE as 16 MHz: + "Option of Taret -> C/C++ > Preprocessor Symbols" + Define: USE_HT32_DRIVER, USE_HT32Fxxxxx_SK, USE_HT32Fxxxxx_xx, USE_MEM_HT32Fxxxxx, HSE_VALUE=16000000 + ^^ Add "HSE_VALUE" + define as above. +*/ +#define HSI_ENABLE (1) /*!< 0: DISABLE, 1: ENABLE */ +#define HSE_ENABLE (1) /*!< 0: DISABLE, 1: ENABLE */ +#define LSI_ENABLE (1) /*!< 0: DISABLE, 1: ENABLE */ +#define LSE_ENABLE (0) /*!< 0: DISABLE, 1: ENABLE */ +#define PLL_ENABLE (1) /*!< 0: DISABLE, 1: ENABLE */ +#define PLL_CLK_SRC (0) /*!< 0: HSE, 1: HSI */ +#define PLL_CLK_SRC_DIV (0) /*!< 0: DIV1, 1: DIV2 */ +#define PLL_NF2_DIV (9) /*!< 1~32: DIV1~DIV32 */ +#define PLL_NO2_DIV (0) /*!< 0: DIV1, 1: DIV2, 2: DIV4, 3: DIV8 */ +#define HCLK_SRC (1) /*!< 0: PLL, 1: PLL, 2: HSE, 3: HSI 6: LSE, 7: LSI */ +#define HCLK_DIV (0) /*!< 0: DIV1, 1: DIV2, 2: DIV4, 3: DIV8, 4: DIV16, 5: DIV32 */ +#define WAIT_STATE (9) /*!< 0: WS = 0, 1: WS = 1, 2: WS = 2, 3: WS = 3, 9: WS = AUTO */ +#define PRE_FETCH_ENABLE (1) /*!< 0: DISABLE, 1: ENABLE */ +#define BCACHE_ENABLE (1) /*!< 0: DISABLE, 1: ENABLE */ +#define DCODE_CACHE_ABLE (1) /*!< 0: YES, 1: NO */ +#define DEINIT_ENABLE (1) /* Set 0 for reduce code size */ + +/*----------------------------------------------------------------------------------------------------------*/ +/* PLL Out = (((HSE or HSI) / (PLL_CLK_SRC_DIV + 1)) x PLL_NF2) / PLL_NO2 */ +/*----------------------------------------------------------------------------------------------------------*/ + + +/*--------------------- WDT Configuration ---------------------------------- +// +// Enable WDT Configuration +// WDT Prescaler Selection +// <0=> CK_WDT / 1 +// <1=> CK_WDT / 2 +// <2=> CK_WDT / 4 +// <3=> CK_WDT / 8 +// <4=> CK_WDT / 16 +// <5=> CK_WDT / 32 +// <6=> CK_WDT / 64 +// <7=> CK_WDT / 128 +// WDT Reload Value <1-4095:1> +// Enable WDT Reset function +// WDT Sleep Halt mode +// <0=> No halt +// <1=> Halt in DeepSleep1 +// <2=> Halt in Sleep & DeepSleep1 +// +*/ +#define WDT_ENABLE (0) /*!< 0: DISABLE, 1: ENABLE */ +#define WDT_PRESCALER (5) /*!< 0: 1/1, 1: 1/2, 2: 1/4, 3: 1/8, 4: 1/16, 5: 1/32, 6: 1/64, 7: 1/128 */ +#define WDT_RELOAD (2000) /*!< 0 ~ 4095, 12 bit */ +#define WDT_RESET_ENABLE (1) /*!< 0: No Reset, 1: Reset when WDT over flow */ +#define WDT_SLEEP_HALT (2) /*!< 0: No halt, 1: Halt in DeepSleep1, 2: Halt in Sleep & DeepSleep1 */ + +/** + * @brief Check HSI frequency + */ +#if (HSI_VALUE != 8000000UL) + #error "CK_HSI clock issue: must be 8 MHz!" +#endif + +/** + * @brief Check HSE frequency + */ +#if ((HSE_VALUE < 4000000UL) || (HSE_VALUE > 16000000UL)) + #error "CK_HSE clock issue: must be in the range of 4 MHz to 16 MHz!" +#endif + +/** + * @brief Check LSI frequency + */ +#if (LSI_VALUE != 32000UL) + #error "CK_LSI clock issue: must be 32 kHz!" +#endif + +/** + * @brief Check LSE frequency + */ +#if (LSE_VALUE != 32768UL) + #error "CK_LSE clock issue: must be 32.768 kHz!" +#endif + +/** + * @brief CK_PLL definition + */ +#if (PLL_ENABLE == 1) + /* Get CK_VCO frequency */ + #if (PLL_CLK_SRC == 1) + #if (HSI_ENABLE == 0) + #error "CK_PLL clock source issue: HSI has not been enabled" + #else + #define __CK_VCO ((HSI_VALUE >> PLL_CLK_SRC_DIV) * PLL_NF2_DIV) /*!< Select HSI as PLL source */ + #endif + #else + #if (HSE_ENABLE == 0) + #error "CK_PLL clock source issue: HSE has not been enabled!" + #else + #define __CK_VCO ((HSE_VALUE >> PLL_CLK_SRC_DIV) * PLL_NF2_DIV) /*!< Select HSE as PLL source */ + #endif + #endif + + #define VCO_MIN 64000000UL + #define VCO_MAX 76000000UL + #define PLL_MIN 8000000UL + #define PLL_MAX 76000000UL + + /* Check CK_VCO frequency */ + #if ((__CK_VCO < VCO_MIN) || (__CK_VCO > VCO_MAX)) + #error "CK_VCO clock issue: must be in the range!" + #endif + + #define __CK_PLL (__CK_VCO >> PLL_NO2_DIV) /*!< Get CK_PLL frequency */ + + /* Check CK_PLL frequency */ + #if ((__CK_PLL < PLL_MIN) || (__CK_PLL > PLL_MAX)) + #error "CK_PLL clock issue: must be in the range!" + #endif +#endif + +/** + * @brief CK_SYS definition + */ +#if (HCLK_SRC == 1) + #if (PLL_ENABLE == 1) + #define __CK_SYS __CK_PLL /*!< Select PLL as CK_SYS source */ + #else + #error "CK_SYS clock source issue: PLL is not enable!" + #endif +#elif (HCLK_SRC == 2) + #if (HSE_ENABLE == 1) + #define __CK_SYS HSE_VALUE /*!< Select HSE as CK_SYS source */ + #else + #error "CK_SYS clock source issue: HSE is not enable!" + #endif +#elif (HCLK_SRC == 3) + #if (HSI_ENABLE == 1) + #define __CK_SYS HSI_VALUE /*!< Select HSI as CK_SYS source */ + #else + #error "CK_SYS clock source issue: HSI is not enable!" + #endif +#elif (HCLK_SRC == 6) + #if (LSE_ENABLE == 1) + #define __CK_SYS LSE_VALUE /*!< Select LSE as CK_SYS source */ + #else + #error "CK_SYS clock source issue: LSE is not enable!" + #endif +#elif (HCLK_SRC == 7) + #if (LSI_ENABLE == 1) + #define __CK_SYS LSI_VALUE /*!< Select LSI as CK_SYS source */ + #else + #error "CK_SYS clock source issue: LSI is not enable!" + #endif +#else + #error "CK_SYS clock source issue: No clock source is selected!" +#endif + +/** + * @brief CK_AHB definition + */ +#define __CK_AHB (__CK_SYS >> HCLK_DIV) /*!< Get CK_AHB frequency */ + +#define CKAHB_MIN 1000UL +#define CKAHB_MAX 76000000UL +#define WS0_CLK 20000000UL +#define WS1_CLK 40000000UL +#define WS2_CLK 60000000UL + +/* Check CK_AHB frequency */ +#if ((__CK_AHB < CKAHB_MIN) || (__CK_AHB > CKAHB_MAX)) + #error "CK_AHB clock issue: must be in the range!" +#endif + +/* Check FLASH wait-state setting */ +#if ((__CK_AHB > WS2_CLK) && (WAIT_STATE < 3) || \ + (__CK_AHB > WS1_CLK) && (WAIT_STATE < 2) || \ + (__CK_AHB > WS0_CLK) && (WAIT_STATE < 1)) + #error "FLASH wait state configuration issue!" +#endif +/** + * @} + */ + +/** @addtogroup HT32F1xxxx_System_Private_Variables + * @{ + */ +__IO uint32_t SystemCoreClock = __CK_AHB; /*!< SystemCoreClock = CK_AHB */ +/** + * @} + */ + +/** @addtogroup HT32F1xxxx_System_Private_Functions + * @{ + */ + +/** + * @brief Setup the microcontroller system. + * Initializes the system clocks and the embedded Flash. + * @note This function should be used after reset. + * @retval None + */ +void SystemInit(void) +{ +#if (WDT_ENABLE == 1) + HT_CKCU->APBCCR1 |= (0x1 << 4); + HT_WDT->PR = 0x35CA; + HT_WDT->MR0 = 0; + HT_WDT->MR1 = ((HT_WDT->MR1 & 0xFFF) | (WDT_PRESCALER << 12)); + HT_WDT->MR0 = WDT_RELOAD | (WDT_RESET_ENABLE << 13) | (WDT_SLEEP_HALT << 14) | (0x1 << 16); + HT_WDT->CR = 0x5FA00001; +#else + #if (DEINIT_ENABLE == 1) + HT_RSTCU->APBPRST1 = (1 << 4); + #endif +#endif + + SetBit_BB((u32)(&HT_CKCU->APBCCR1), 6); /* enable VDD power domain register clock */ + +#if (DEINIT_ENABLE == 1) + /* De-init the setting */ + HT_CKCU->AHBCCR &= ~(0x3 << 10); /* disable IP who may use PLL as source */ + SetBit_BB((u32)(&HT_CKCU->GCCR), 11); /* enable HSI */ + while (!GetBit_BB((u32)(&HT_CKCU->GCSR), 3)); /* wait for HSI ready */ + HT_CKCU->GCCR = ((HT_CKCU->GCCR & ~7UL) | 3UL); /* select CK_SYS source */ + while ((HT_CKCU->CKST & 7UL) != 3UL); /* wait for clock switch complete */ + HT_FLASH->CFCR = (((HT_FLASH->CFCR) & ~7UL) | 1UL); /* set Wait State as 0 WS */ + HT_CKCU->AHBCFGR = 0; /* set CK_AHB prescaler */ + ResetBit_BB((u32)(&HT_CKCU->GCCR), 9); /* disable PLL */ + SetBit_BB((u32)(&HT_CKCU->GCFGR), 8); /* select PLL source as HSI */ + ResetBit_BB((u32)(&HT_CKCU->GCCR), 3); /* disable USB PLL */ + SetBit_BB((u32)(&HT_CKCU->GCFGR), 9); /* select USB PLL source as HSI */ +#endif + + /* LDO initiation */ +#if (__CK_AHB > 72000000UL) + do { + HT_PWRCU->CR = (HT_PWRCU->CR & ~(3UL << 4)) | (3UL << 4); + } while (((HT_PWRCU->CR >> 4) & 3UL) != 3UL); +#endif + + /* HSE initiation */ +#if (HSE_ENABLE == 1) + SetBit_BB((u32)(&HT_CKCU->GCCR), 10); /* enable HSE */ + while (!GetBit_BB((u32)(&HT_CKCU->GCSR), 2)){}; /* wait for HSE ready */ +#endif + + /* LSE initiation */ +#if (LSE_ENABLE == 1) + do { + SetBit_BB((u32)(&HT_RTC->CR), 3); /* enable LSE */ + } while (!GetBit_BB((u32)(&HT_RTC->CR), 3)); + while (!GetBit_BB((u32)(&HT_CKCU->GCSR), 4)); /* wait for LSE ready */ +#endif + + /* LSI initiation */ +#if (HCLK_SRC == 7) + while (!GetBit_BB((u32)(&HT_CKCU->GCSR), 5)){}; /* wait for LSI ready */ +#endif + + /* PLL initiation */ +#if (PLL_ENABLE == 1) + HT_CKCU->PLLCFGR = ((PLL_NF2_DIV & 0x1F) << 23) | (PLL_NO2_DIV << 21); /* set PLL divider */ + + #if (PLL_CLK_SRC_DIV == 1) + SetBit_BB((u32)(&HT_CKCU->PLLCFGR), 28); /* set PLL clock source divider */ + #else + ResetBit_BB((u32)(&HT_CKCU->PLLCFGR), 28); /* reset PLL clock source divider */ + #endif + + #if (PLL_CLK_SRC == 0) + ResetBit_BB((u32)(&HT_CKCU->GCFGR), 8); /* select PLL source as HSE */ + #else + SetBit_BB((u32)(&HT_CKCU->GCFGR), 8); /* select PLL source as HSI */ + #endif + SetBit_BB((u32)(&HT_CKCU->GCCR), 9); /* enable PLL */ + while (!GetBit_BB((u32)(&HT_CKCU->GCSR), 1)){}; /* wait for PLL ready */ +#endif + + /* CK_AHB initiation */ +#if (WAIT_STATE == 9) + #if (__CK_AHB > WS2_CLK) + HT_FLASH->CFCR = (((HT_FLASH->CFCR) & ~7UL) | 4UL); /* auto-select wait state */ + #elif (__CK_AHB > WS1_CLK) + HT_FLASH->CFCR = (((HT_FLASH->CFCR) & ~7UL) | 3UL); /* auto-select wait state */ + #elif (__CK_AHB > WS0_CLK) + HT_FLASH->CFCR = (((HT_FLASH->CFCR) & ~7UL) | 2UL); /* auto-select wait state */ + #endif +#else + HT_FLASH->CFCR = (((HT_FLASH->CFCR) & ~7UL) | (WAIT_STATE + 1)); /* manual wait state */ +#endif + + HT_CKCU->AHBCFGR = HCLK_DIV; /* set CK_AHB prescaler */ + HT_CKCU->GCCR = ((HT_CKCU->GCCR & ~7UL) | HCLK_SRC); /* select CK_SYS source */ + while ((HT_CKCU->CKST & 7UL) != HCLK_SRC); /* wait for clock switch complete */ + + /* LDO initiation */ +#if (__CK_AHB > 72000000UL) +#else + do { + HT_PWRCU->CR = (HT_PWRCU->CR & ~(3UL << 4)); + } while (((HT_PWRCU->CR >> 4) & 3UL) != 0x0); +#endif + + ResetBit_BB((u32)(&HT_CKCU->APBCCR1), 6); /* disable Backup domain register clock */ + + /* Pre-fetch buffer configuration */ +#if (PRE_FETCH_ENABLE == 0) + ResetBit_BB((u32)(&HT_FLASH->CFCR), 4); /* 0: pre-fetch disable, 1: pre-fetch enable */ +#else + SetBit_BB((u32)(&HT_FLASH->CFCR), 4); /* 0: pre-fetch disable, 1: pre-fetch enable */ +#endif + + /* Branch cache configuration */ +#if (BCACHE_ENABLE == 0) + ResetBit_BB((u32)(&HT_FLASH->CFCR), 12); /* 0: branch cache disable, 1: branch cache enable */ +#else + SetBit_BB((u32)(&HT_FLASH->CFCR), 12); /* 0: branch cache disable, 1: branch cache enable */ + #if (DCODE_CACHE_ABLE == 0) + ResetBit_BB((u32)(&HT_FLASH->CFCR), 7); /* 0: DCODE cache-able, 1: DCODE non cache-able */ + #else + SetBit_BB((u32)(&HT_FLASH->CFCR), 7); /* 0: DCODE cache-able, 1: DCODE non cache-able */ + #endif +#endif + + /* HSE power down */ +#if ((HSE_ENABLE == 0) && (HCLK_SRC != 2) && ((PLL_ENABLE == 0) || (PLL_CLK_SRC == 1))) + ResetBit_BB((u32)(&HT_CKCU->GCCR), 10); +#endif + + /* HSI power down */ +#if ((HSI_ENABLE == 0) && (HCLK_SRC != 3) && ((PLL_ENABLE == 0) || (PLL_CLK_SRC == 0))) + ResetBit_BB((u32)(&HT_CKCU->GCCR), 11); +#endif +} + +/** + * @brief Update SystemCoreClock + * @retval None + */ +void SystemCoreClockUpdate(void) +{ + u32 SystemCoreClockDiv = HT_CKCU->AHBCFGR & 7UL; + u32 PllSourceClockDiv = (HT_CKCU->PLLCFGR >> 28) & 1UL; + u32 PllFeedbackClockDiv = (((HT_CKCU->PLLCFGR >> 23) & 31UL) == 0) ? (32) : ((HT_CKCU->PLLCFGR >> 23) & 31UL); + u32 PllOutputClockDiv = (HT_CKCU->PLLCFGR >> 21) & 3UL; + u32 SystemCoreClockSrc = HT_CKCU->CKST & 7UL; + + /* Get system core clock according to global clock control & configuration registers */ + if (SystemCoreClockSrc == 1) + { + if (GetBit_BB((u32)(&HT_CKCU->PLLCR), 31)) + { + PllFeedbackClockDiv = 1; + PllOutputClockDiv = 0; + } + + if (GetBit_BB((u32)(&HT_CKCU->GCFGR), 8)) + { + SystemCoreClock = (((HSI_VALUE >> PllSourceClockDiv) * PllFeedbackClockDiv) >> PllOutputClockDiv) >> SystemCoreClockDiv; + } + else + { + SystemCoreClock = (((HSE_VALUE >> PllSourceClockDiv) * PllFeedbackClockDiv) >> PllOutputClockDiv) >> SystemCoreClockDiv; + } + } + else if (SystemCoreClockSrc == 2) + { + SystemCoreClock = HSE_VALUE >> SystemCoreClockDiv; + } + else if (SystemCoreClockSrc == 3) + { + SystemCoreClock = HSI_VALUE >> SystemCoreClockDiv; + } + else if (SystemCoreClockSrc == 6) + { + SystemCoreClock = LSE_VALUE >> SystemCoreClockDiv; + } + else if (SystemCoreClockSrc == 7) + { + SystemCoreClock = LSI_VALUE >> SystemCoreClockDiv; + } +} + +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ + +/******************* (C) COPYRIGHT Holtek Semiconductor Inc. *****END OF FILE*** */ diff --git a/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/inc/ht32.h b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/inc/ht32.h new file mode 100644 index 0000000000..bbfcf8bd2c --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/inc/ht32.h @@ -0,0 +1,35 @@ +/*********************************************************************************************************//** + * @file ht32.h + * @version $Rev:: 80 $ + * @date $Date:: 2017-05-25 #$ + * @brief The API between application and HT32FXXXX Firmware Library. + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------------------------------------*/ +#ifndef __HT32_H +#define __HT32_H + +/* Includes ------------------------------------------------------------------------------------------------*/ +#include "ht32f1xxxx_01.h" + +#endif /* __HT32_H -----------------------------------------------------------------------------------------*/ diff --git a/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/inc/ht32_cm3_misc.h b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/inc/ht32_cm3_misc.h new file mode 100644 index 0000000000..2acc00f77a --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/inc/ht32_cm3_misc.h @@ -0,0 +1,132 @@ +/*********************************************************************************************************//** + * @file ht32_cm3_misc.h + * @version $Rev:: 5 $ + * @date $Date:: 2017-05-11 #$ + * @brief All the function prototypes for the miscellaneous firmware library. + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------------------------------------*/ +#ifndef __HT32_CM3_MISC_H +#define __HT32_CM3_MISC_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------------------------------------*/ +#include "ht32.h" + +/** @addtogroup HT32_Peripheral_Driver + * @{ + */ + +/** @addtogroup MISC + * @{ + */ + + +/* Exported constants --------------------------------------------------------------------------------------*/ +/** @defgroup MISC_Exported_Constants MISC exported constants + * @{ + */ + +/* Vector Table Base */ +#define NVIC_VECTTABLE_RAM ((u32)0x20000000) +#define NVIC_VECTTABLE_FLASH ((u32)0x00000000) + +#define IS_NVIC_VECTTABLE(VECTTABLE) ((VECTTABLE == NVIC_VECTTABLE_RAM) || \ + (VECTTABLE == NVIC_VECTTABLE_FLASH)) + +#define IS_NVIC_OFFSET(OFFSET) (OFFSET < 0x0001FFFF) + +/* System Low Power */ +#define NVIC_LOWPOWER_SEVONPEND ((u8)0x10) +#define NVIC_LOWPOWER_SLEEPDEEP ((u8)0x04) +#define NVIC_LOWPOWER_SLEEPONEXIT ((u8)0x02) + +#define IS_NVIC_LOWPOWER(LOWPOWER) ((LOWPOWER == NVIC_LOWPOWER_SEVONPEND) || \ + (LOWPOWER == NVIC_LOWPOWER_SLEEPDEEP) || \ + (LOWPOWER == NVIC_LOWPOWER_SLEEPONEXIT)) + +/* System Handler */ +#define SYSTEMHANDLER_NMI ((u32)0x80000000) +#define SYSTEMHANDLER_PSV ((u32)0x10000000) +#define SYSTEMHANDLER_SYSTICK ((u32)0x04000000) +#define SYSTEMHANDLER_ALL ((u32)0x94000000) + +#define IS_NVIC_SYSTEMHANDLER(HANDLER) ((HANDLER == SYSTEMHANDLER_NMI) || \ + (HANDLER == SYSTEMHANDLER_PSV) || \ + (HANDLER == SYSTEMHANDLER_SYSTICK) ||\ + (HANDLER == SYSTEMHANDLER_ALL)) + +/* SysTick clock source */ +#define SYSTICK_SRC_STCLK ((u32)0xFFFFFFFB) +#define SYSTICK_SRC_FCLK ((u32)0x00000004) + +#define IS_SYSTICK_CLOCK_SOURCE(SOURCE) ((SOURCE == SYSTICK_SRC_STCLK) || \ + (SOURCE == SYSTICK_SRC_FCLK) ) + +/* SysTick counter state */ +#define SYSTICK_COUNTER_DISABLE ((u32)0xFFFFFFFE) +#define SYSTICK_COUNTER_ENABLE ((u32)0x00000001) +#define SYSTICK_COUNTER_CLEAR ((u32)0x00000000) + +#define IS_SYSTICK_COUNTER(COUNTER) ((COUNTER == SYSTICK_COUNTER_DISABLE) || \ + (COUNTER == SYSTICK_COUNTER_ENABLE) || \ + (COUNTER == SYSTICK_COUNTER_CLEAR)) + +#define IS_SYSTICK_RELOAD(RELOAD) ((RELOAD > 0) && (RELOAD <= 0xFFFFFF)) +/** + * @} + */ + +/* Exported functions --------------------------------------------------------------------------------------*/ +/** @defgroup MISC_Exported_Functions MISC exported functions + * @{ + */ +void NVIC_SetVectorTable(u32 NVIC_VectTable, u32 NVIC_Offset); +void NVIC_LowPowerConfig(u8 NVIC_LowPowerMode, ControlStatus NewState); +void NVIC_CoreReset(void); +void NVIC_SetPendingSystemHandler(u32 SystemHandler); +void SYSTICK_ClockSourceConfig(u32 SysTick_ClockSource); +void SYSTICK_CounterCmd(u32 SysTick_Counter); +void SYSTICK_IntConfig(ControlStatus NewState); +void SYSTICK_SetReloadValue(u32 SysTick_Reload); +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/inc/ht32_dependency.h b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/inc/ht32_dependency.h new file mode 100644 index 0000000000..46eef808e9 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/inc/ht32_dependency.h @@ -0,0 +1,86 @@ +/*********************************************************************************************************//** + * @file ht32_dependency.h + * @version $Rev:: 2971 $ + * @date $Date:: 2023-10-25 #$ + * @brief The header file of dependency check. + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ +#ifdef __cplusplus + extern "C" { +#endif + + +#if 0 // Version setting example for module + +/* Dependency check ----------------------------------------------------------------------------------------*/ +#define MIN_HT32_FWLIB_VER (0x01000005) //0xmmnnnrrr -> Vm.n.r +#define MIN_HT32_FWLIB_SVN (0x2200) +#include "ht32_dependency.h" // Not exist means the version of HT32 Firmware Library is older than the module required. + +#endif + +#if 0 // Version setting example for module + +/* Dependency check ----------------------------------------------------------------------------------------*/ +#if (__CORTEX_M == 0) +#define MIN_HT32_FWLIB_VER (0x01000024) //0xmmnnnrrr -> Vm.n.r +#define MIN_HT32_FWLIB_SVN (0x5762) +#endif +#if (__CORTEX_M == 3) +#define MIN_HT32_FWLIB_VER (0x01000009) //0xmmnnnrrr -> Vm.n.r +#define MIN_HT32_FWLIB_SVN (0x2556) +#endif +#include "ht32_dependency.h" // Not exist means the version of HT32 Firmware Library is older than the module required. + +#endif + + +#if 0 // Enable for test +#undef HT32_FWLIB_VER +#undef HT32_FWLIB_SVN +#define HT32_FWLIB_VER (0x00000004) +#define HT32_FWLIB_SVN (0x1074) +#endif + + +// Check "ht32fxxxxx_lib.h" for the version of HT32 Firmwar Library +#if (HT32_FWLIB_VER != 999999) +#if HT32_FWLIB_VER < MIN_HT32_FWLIB_VER + #error !!! The version of HT32 Firmware Library is older than the module required. Please update HT32 Firmware Library. +#endif + +#if HT32_FWLIB_SVN < MIN_HT32_FWLIB_SVN + #error !!! The version of HT32 Firmware Library is older than the module required. Please update HT32 Firmware Library. +#endif +#endif + + +// Un-defined for next module of the .C include .C case +#undef MIN_HT32_FWLIB_VER +#undef MIN_HT32_FWLIB_SVN + + +#ifdef __cplusplus +} +#endif + +//#endif diff --git a/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/inc/ht32_rand.h b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/inc/ht32_rand.h new file mode 100644 index 0000000000..c3ffdc9ec6 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/inc/ht32_rand.h @@ -0,0 +1,43 @@ +/*********************************************************************************************************//** + * @file ht32_rand.h + * @version $Rev:: 133 $ + * @date $Date:: 2017-06-14 #$ + * @brief The header file of random number. + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ +/* Define to prevent recursive inclusion -------------------------------------------------------------------*/ +#ifndef __HT32_RAND_H +#define __HT32_RAND_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Exported functions --------------------------------------------------------------------------------------*/ +void Rand_Init(u32 *uSeed, u32 uCount, u32 a, u32 b); +extern u32 (*Rand_Get)(u32 *, u32); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/inc/ht32_retarget_desc.h b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/inc/ht32_retarget_desc.h new file mode 100644 index 0000000000..8cc8805086 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/inc/ht32_retarget_desc.h @@ -0,0 +1,182 @@ +/*********************************************************************************************************//** + * @file ht32_retarget_desc.h + * @version $Rev:: 5 $ + * @date $Date:: 2017-05-11 #$ + * @brief The USB VCP descriptor file of retarget. + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------------------------------------*/ +#ifndef __HT32_RETARGET_DESC_H +#define __HT32_RETARGET_DESC_H + +/* Exported constants --------------------------------------------------------------------------------------*/ + + /*--------------------------------------------------------------------------------------------------------*/ + /* IAD to associate the two CDC interfaces */ + /*--------------------------------------------------------------------------------------------------------*/ + /* Field Size Description */ + 8, // bLength 1 Size of this descriptor in bytes + 11, // bDescriptorType 1 Descriptor Type + 11, // bFirstInterface 1 + 2, // bInterfaceCount 1 + 2, // bFunctionClass 1 + 2, // bFunctionSubClass 1 + 0, // bFunctionProtocol 1 + 0x00, // iFunction 1 Index of string descriptor describing this function. + + /*--------------------------------------------------------------------------------------------------------*/ + /* Interface descriptor */ + /*--------------------------------------------------------------------------------------------------------*/ + /* Field Size Description */ + /*----------------------------------------------------------------------------*/ + DESC_LEN_INF, // bLength 1 Size of this descriptor in bytes + DESC_TYPE_04_INF, // bDescriptorType 1 INTERFACE Descriptor Type + 11, // bInterfaceNumber 1 Number of this interface (Zero-based 0) + 0x00, // bAlternateSetting 1 Value used to select alternate setting + 1, // bNumEndpoints 1 Number of endpoints used by this interface + DESC_CLASS_02_CDC_CTRL, // bInterfaceClass 1 Class code (assigned by USB-IF) + 2, // bInterfaceSubClass 1 Subclass code (assigned by USB-IF) + 0, // bInterfaceProtocol 1 Protocol code (assigned by USB) + 0x00, // iInterface 1 Index of string descriptor describing this interface + + /*--------------------------------------------------------------------------------------------------------*/ + /* Header Functional descriptor */ + /*--------------------------------------------------------------------------------------------------------*/ + /* Field Size Description */ + /*----------------------------------------------------------------------------*/ + 5, // bFunctionLength 1 Size of this descriptor in bytes + 0x24, // bDescriptorType 1 CS_INTERFACE descriptor type + 0, // bDescriptorSubtype 1 header functional descriptor + DESC_H2B(0x0110), // bcdCDC 2 spec release number + + /*--------------------------------------------------------------------------------------------------------*/ + /* Abstract control management Functional */ + /*--------------------------------------------------------------------------------------------------------*/ + /* Field Size Description */ + /*----------------------------------------------------------------------------*/ + 4, // bFunctionLength 1 Size of this descriptor in bytes + 0x24, // bDescriptorType 1 CS_INTERFACE descriptor type + 2, // bDescriptorSubtype 1 Abstract Control Management Functional descriptor + 0x02, // bmCapabilities 1 + + /*--------------------------------------------------------------------------------------------------------*/ + /* Union Functional */ + /*--------------------------------------------------------------------------------------------------------*/ + /* Field Size Description */ + /*----------------------------------------------------------------------------*/ + 5, // bFunctionLength 1 Size of this descriptor in bytes + 0x24, // bDescriptorType 1 CS_INTERFACE descriptor type + 5, // bDescriptorSubtype 1 Union Functional descriptor + 0x00, // bMasterInterface 1 Communication class interface + 0x01, // bSlaveInterface0 1 Data Class Interface + + /*--------------------------------------------------------------------------------------------------------*/ + /* Call Management Functional */ + /*--------------------------------------------------------------------------------------------------------*/ + /* Field Size Description */ + /*----------------------------------------------------------------------------*/ + 5, // bFunctionLength 1 Size of this descriptor in bytes + 0x24, // bDescriptorType 1 CS_INTERFACE descriptor type + 1, // bDescriptorSubtype 1 Call Management Functional descriptor + 0x00, // bmCapabilities 1 + 0x01, // bDataInterface 1 Interface number of Data + + /*--------------------------------------------------------------------------------------------------------*/ + /* Endpoint descriptor */ + /*--------------------------------------------------------------------------------------------------------*/ + /* Field Size Description */ + /*----------------------------------------------------------------------------*/ + DESC_LEN_EPT, // bLengthE 1 Size of this descriptor in bytes + DESC_TYPE_05_EPT, // bDescriptorType 1 ENDPOINT Descriptor Type + (0x80 | RETARGET_CTRL_EPT), // bEndpointAddress 1 The address of the endpoint + // Bit 3..0: The endpoint number + // Bit 6..4: Reserved + // Bit 7 : Direction (0 = Out/1 = In) + 0x03, // bmAttribute 1 Endpoint Attribute + // Bit 1..0: Transfer type + // 00 = Control + // 01 = Isochronous + // 10 = Bulk + // 11 = Interrupt + // All other reserved + DESC_H2B(RETARGET_CTRL_LEN),// wMaxPacketSize 2 Maximum packet size + 0x00, // bInterval 1 Interval for polling endpoint + + /*--------------------------------------------------------------------------------------------------------*/ + /* Data class interface descriptor */ + /*--------------------------------------------------------------------------------------------------------*/ + /* Field Size Description */ + /*----------------------------------------------------------------------------*/ + DESC_LEN_INF, // bLength 1 Endpoint Descriptor size + DESC_TYPE_04_INF, // bDescriptorType 1 + 12, // bInterfaceNumber 1 Number of Interface + 0x00, // bAlternateSetting 1 Alternate setting + 2, // bNumEndpoints 1 Two endpoints used + DESC_CLASS_0A_CDC_DATA, // bInterfaceClass 1 + 0, // bInterfaceSubClass 1 + 0, // bInterfaceProtocol 1 + 0x00, // iInterface 1 + + /*--------------------------------------------------------------------------------------------------------*/ + /* Endpoint n Out descriptor */ + /*--------------------------------------------------------------------------------------------------------*/ + /* Field Size Description */ + /*----------------------------------------------------------------------------*/ + DESC_LEN_EPT, // bLength 1 Size of this descriptor in bytes + DESC_TYPE_05_EPT, // bDescriptorType 1 ENDPOINT Descriptor Type + (0x00 | RETARGET_RX_EPT), // bEndpointAddress 1 The address of the endpoint + // Bit 3..0: The endpoint number + // Bit 6..4: Reserved + // Bit 7 : Direction (0 = Out/1 = In) + 0x02, // bmAttribute 1 Endpoint Attribute + // Bit 1..0: Transfer type + // 00 = Control + // 01 = Isochronous + // 10 = Bulk + // 11 = Interrupt + // All other reserved + DESC_H2B(RETARGET_RX_LEN), // wMaxPacketSize 2 Maximum packet size + 0x00, // bInterval 1 Interval for polling endpoint + + /*--------------------------------------------------------------------------------------------------------*/ + /* Endpoint n In Descriptor */ + /*--------------------------------------------------------------------------------------------------------*/ + /* Field Size Description */ + /*----------------------------------------------------------------------------*/ + DESC_LEN_EPT, // bLength 1 Size of this descriptor in bytes + DESC_TYPE_05_EPT, // bDescriptorType 1 ENDPOINT Descriptor Type + (0x80 | RETARGET_TX_EPT), // bEndpointAddress 1 The address of the endpoint + // Bit 3..0: The endpoint number + // Bit 6..4: Reserved + // Bit 7 : Direction (0 = Out/1 = In) + 0x02, // bmAttribute 1 Endpoint Attribute + // Bit 1..0: Transfer type + // 00 = Control + // 01 = Isochronous + // 10 = Bulk + // 11 = Interrupt + // All other reserved + DESC_H2B(RETARGET_TX_LEN), // wMaxPacketSize 2 Maximum packet size + 0x00, // bInterval 1 Interval for polling endpoint + +#endif /* __HT32_RETARGET_DESC_H ---------------------------------------------------------------------------*/ diff --git a/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/inc/ht32_retarget_usbdconf.h b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/inc/ht32_retarget_usbdconf.h new file mode 100644 index 0000000000..e333957f6b --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/inc/ht32_retarget_usbdconf.h @@ -0,0 +1,321 @@ +/*********************************************************************************************************//** + * @file ht32_retarget_usbdconf.h + * @version $Rev:: 1958 $ + * @date $Date:: 2019-12-27 #$ + * @brief The USB Device configuration of retarget + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------------------------------------*/ +#ifndef __HT32_RETARGET_USBDCONF_H +#define __HT32_RETARGET_USBDCONF_H + +/* Settings ------------------------------------------------------------------------------------------------*/ +#define RETARGET_INF (0) +#define RETARGET_DLEN (0) + +#if (_RETARGET == 1) + + #ifdef RETARGET_IS_USB + + #undef RETARGET_INF + #undef RETARGET_DLEN + #define RETARGET_INF (2) + #define RETARGET_DLEN (8 + DESC_LEN_INF * 2 + 5 + 4 + 5 + 5 + DESC_LEN_EPT * 3) + + #if (_EP1_ENABLE == 0 && _EP2_ENABLE == 0 && _EP3_ENABLE == 0 && _EP4_ENABLE == 0 && \ + _EP5_ENABLE == 0 && _EP6_ENABLE == 0 && _EP7_ENABLE == 0) + #define NON_USB_IN_APP + #undef _UIER + #undef _EP0LEN + #undef _EP0_IER + #define _EP0LEN (64) + #define _EP0_IER (0x212) + #define _UIER (0x011D) + #endif + + #define _UIER_ALL (_UIER | (EP0IE << RETARGET_RX_EPT) | (EP0IE << RETARGET_TX_EPT)) + + #if (RETARGET_RX_EPT == 1 || RETARGET_TX_EPT == 1 || RETARGET_CTRL_EPT == 1) + #if (_EP1_ENABLE == 1) + #define _RERATGET1_ERR + #else + #undef _EP1_ENABLE + #undef _EP1_CFG_EPADR + #undef _EP1_CFG_EPEN_TMP + #undef _EP1_TYPR + #undef _EP1_CFG_EPDIR + #undef _EP1LEN_TMP + #undef _EP1_IER + + #define _EP1_ENABLE (1) + #define _EP1_CFG_EPADR (1) + #define _EP1_CFG_EPEN_TMP (1) + #if (RETARGET_RX_EPT == 1) + #define _EP1_TYPR (2) + #define _EP1_CFG_EPDIR (0) + #define _EP1LEN_TMP (RETARGET_RX_EPTLEN) + #define _EP1_IER (0x02) + #define RETARGET_RX_LEN (_EP1LEN) + #elif (RETARGET_TX_EPT == 1) + #define _EP1_TYPR (2) + #define _EP1_CFG_EPDIR (1) + #define _EP1LEN_TMP (RETARGET_TX_EPTLEN) + #define _EP1_IER (0x10) + #define RETARGET_TX_LEN (_EP1LEN) + #elif (RETARGET_CTRL_EPT == 1) + #define _EP1_TYPR (3) + #define _EP1_CFG_EPDIR (1) + #define _EP1LEN_TMP (RETARGET_CTRL_EPTLEN) + #define _EP1_IER (0x10) + #define RETARGET_CTRL_LEN (_EP1LEN) + #endif + #endif + #endif + + #if (RETARGET_RX_EPT == 2 || RETARGET_TX_EPT == 2 || RETARGET_CTRL_EPT == 2) + #if (_EP2_ENABLE == 1) + #define _RERATGET2_ERR + #else + #undef _EP2_ENABLE + #undef _EP2_CFG_EPADR + #undef _EP2_CFG_EPEN_TMP + #undef _EP2_TYPR + #undef _EP2_CFG_EPDIR + #undef _EP2LEN_TMP + #undef _EP2_IER + + #define _EP2_ENABLE (1) + #define _EP2_CFG_EPADR (2) + #define _EP2_CFG_EPEN_TMP (1) + #if (RETARGET_RX_EPT == 2) + #define _EP2_TYPR (2) + #define _EP2_CFG_EPDIR (0) + #define _EP2LEN_TMP (RETARGET_RX_EPTLEN) + #define _EP2_IER (0x02) + #define RETARGET_RX_LEN (_EP2LEN) + #elif (RETARGET_TX_EPT == 2) + #define _EP2_TYPR (2) + #define _EP2_CFG_EPDIR (1) + #define _EP2LEN_TMP (RETARGET_TX_EPTLEN) + #define _EP2_IER (0x10) + #define RETARGET_TX_LEN (_EP2LEN) + #elif (RETARGET_CTRL_EPT == 2) + #define _EP2_TYPR (3) + #define _EP2_CFG_EPDIR (1) + #define _EP2LEN_TMP (RETARGET_CTRL_EPTLEN) + #define _EP2_IER (0x10) + #define RETARGET_CTRL_LEN (_EP2LEN) + #endif + #endif + #endif + + #if (RETARGET_RX_EPT == 3 || RETARGET_TX_EPT == 3 || RETARGET_CTRL_EPT == 3) + #if (_EP3_ENABLE == 1) + #define _RERATGET3_ERR + #else + #undef _EP3_ENABLE + #undef _EP3_CFG_EPADR + #undef _EP3_CFG_EPEN_TMP + #undef _EP3_TYPR + #undef _EP3_CFG_EPDIR + #undef _EP3LEN_TMP + #undef _EP3_IER + + #define _EP3_ENABLE (1) + #define _EP3_CFG_EPADR (3) + #define _EP3_CFG_EPEN_TMP (1) + #if (RETARGET_RX_EPT == 3) + #define _EP3_TYPR (2) + #define _EP3_CFG_EPDIR (0) + #define _EP3LEN_TMP (RETARGET_RX_EPTLEN) + #define _EP3_IER (0x02) + #define RETARGET_RX_LEN (_EP3LEN) + #elif (RETARGET_TX_EPT == 3) + #define _EP3_TYPR (2) + #define _EP3_CFG_EPDIR (1) + #define _EP3LEN_TMP (RETARGET_TX_EPTLEN) + #define _EP3_IER (0x10) + #define RETARGET_TX_LEN (_EP3LEN) + #elif (RETARGET_CTRL_EPT == 3) + #define _EP3_TYPR (3) + #define _EP3_CFG_EPDIR (1) + #define _EP3LEN_TMP (RETARGET_CTRL_EPTLEN) + #define _EP3_IER (0x10) + #define RETARGET_CTRL_LEN (_EP3LEN) + #endif + #endif + #endif + + #if (RETARGET_RX_EPT == 4 || RETARGET_TX_EPT == 4 || RETARGET_CTRL_EPT == 4) + #if (_EP4_ENABLE == 1) + #define _RERATGET4_ERR + #else + #undef _EP4_ENABLE + #undef _EP4_CFG_EPADR + #undef _EP4_CFG_EPEN_TMP + #undef _EP4_TYPR + #undef _EP4_CFG_EPDIR + #undef _EP4LEN_TMP + #undef _EP4_IER + + #define _EP4_ENABLE (1) + #define _EP4_CFG_EPADR (4) + #define _EP4_CFG_EPEN_TMP (1) + #if (RETARGET_RX_EPT == 4) + #define _EP4_TYPR (2) + #define _EP4_CFG_EPDIR (0) + #define _EP4LEN_TMP (RETARGET_RX_EPTLEN) + #define _EP4_IER (0x02) + #define RETARGET_RX_LEN (_EP4LEN) + #elif (RETARGET_TX_EPT == 4) + #define _EP4_TYPR (2) + #define _EP4_CFG_EPDIR (1) + #define _EP4LEN_TMP (RETARGET_TX_EPTLEN) + #define _EP4_IER (0x10) + #define RETARGET_TX_LEN (_EP4LEN) + #elif (RETARGET_CTRL_EPT == 4) + #define _EP4_TYPR (3) + #define _EP4_CFG_EPDIR (1) + #define _EP4LEN_TMP (RETARGET_CTRL_EPTLEN) + #define _EP4_IER (0x10) + #define RETARGET_CTRL_LEN (_EP4LEN) + #endif + #endif + #endif + + #if (RETARGET_RX_EPT == 5 || RETARGET_TX_EPT == 5 || RETARGET_CTRL_EPT == 5) + #if (_EP5_ENABLE == 1) + #define _RERATGET5_ERR + #else + #undef _EP5_ENABLE + #undef _EP5_CFG_EPADR + #undef _EP5_CFG_EPEN_TMP + #undef _EP5_TYPR + #undef _EP5_CFG_EPDIR + #undef _EP5LEN_TMP + #undef _EP5_IER + + #define _EP5_ENABLE (1) + #define _EP5_CFG_EPADR (5) + #define _EP5_CFG_EPEN_TMP (1) + #if (RETARGET_RX_EPT == 5) + #define _EP5_TYPR (2) + #define _EP5_CFG_EPDIR (0) + #define _EP5LEN_TMP (RETARGET_RX_EPTLEN) + #define _EP5_IER (0x02) + #define RETARGET_RX_LEN (_EP5LEN) + #elif (RETARGET_TX_EPT == 5) + #define _EP5_TYPR (2) + #define _EP5_CFG_EPDIR (1) + #define _EP5LEN_TMP (RETARGET_TX_EPTLEN) + #define _EP5_IER (0x10) + #define RETARGET_TX_LEN (_EP5LEN) + #elif (RETARGET_CTRL_EPT == 5) + #define _EP5_TYPR (3) + #define _EP5_CFG_EPDIR (1) + #define _EP5LEN_TMP (RETARGET_CTRL_EPTLEN) + #define _EP5_IER (0x10) + #define RETARGET_CTRL_LEN (_EP5LEN) + #endif + #endif + #endif + + #if (RETARGET_RX_EPT == 6 || RETARGET_TX_EPT == 6 || RETARGET_CTRL_EPT == 6) + #if (_EP6_ENABLE == 1) + #define _RERATGET6_ERR + #else + #undef _EP6_ENABLE + #undef _EP6_CFG_EPADR + #undef _EP6_CFG_EPEN_TMP + #undef _EP6_TYPR + #undef _EP6_CFG_EPDIR + #undef _EP6LEN_TMP + #undef _EP6_IER + + #define _EP6_ENABLE (1) + #define _EP6_CFG_EPADR (6) + #define _EP6_CFG_EPEN_TMP (1) + #if (RETARGET_RX_EPT == 6) + #define _EP6_TYPR (2) + #define _EP6_CFG_EPDIR (0) + #define _EP6LEN_TMP (RETARGET_RX_EPTLEN) + #define _EP6_IER (0x02) + #define RETARGET_RX_LEN (_EP6LEN) + #elif (RETARGET_TX_EPT == 6) + #define _EP6_TYPR (2) + #define _EP6_CFG_EPDIR (1) + #define _EP6LEN_TMP (RETARGET_TX_EPTLEN) + #define _EP6_IER (0x10) + #define RETARGET_TX_LEN (_EP6LEN) + #elif (RETARGET_CTRL_EPT == 6) + #define _EP6_TYPR (3) + #define _EP6_CFG_EPDIR (1) + #define _EP6LEN_TMP (RETARGET_CTRL_EPTLEN) + #define _EP6_IER (0x10) + #define RETARGET_CTRL_LEN (_EP6LEN) + #endif + #endif + #endif + + #if (RETARGET_RX_EPT == 7 || RETARGET_TX_EPT == 7 || RETARGET_CTRL_EPT == 7) + #if (_EP7_ENABLE == 1) + #define _RERATGET7_ERR + #else + #undef _EP7_ENABLE + #undef _EP7_CFG_EPADR + #undef _EP7_CFG_EPEN_TMP + #undef _EP7_TYPR + #undef _EP7_CFG_EPDIR + #undef _EP7LEN_TMP + #undef _EP7_IER + + #define _EP7_ENABLE (1) + #define _EP7_CFG_EPADR (7) + #define _EP7_CFG_EPEN_TMP (1) + #if (RETARGET_RX_EPT == 7) + #define _EP7_TYPR (2) + #define _EP7_CFG_EPDIR (0) + #define _EP7LEN_TMP (RETARGET_RX_EPTLEN) + #define _EP7_IER (0x02) + #define RETARGET_RX_LEN (_EP7LEN) + #elif (RETARGET_TX_EPT == 7) + #define _EP7_TYPR (2) + #define _EP7_CFG_EPDIR (1) + #define _EP7LEN_TMP (RETARGET_TX_EPTLEN) + #define _EP7_IER (0x10) + #define RETARGET_TX_LEN (_EP7LEN) + #elif (RETARGET_CTRL_EPT == 7) + #define _EP7_TYPR (3) + #define _EP7_CFG_EPDIR (1) + #define _EP7LEN_TMP (RETARGET_CTRL_EPTLEN) + #define _EP7_IER (0x10) + #define RETARGET_CTRL_LEN (_EP7LEN) + #endif + #endif + #endif + + #endif /* #ifdef RETARGET_IS_USB */ + +#endif /* #if (_RETARGET == 1) */ + +#endif /* __HT32_RETARGET_USBDCONF_H -----------------------------------------------------------------------*/ diff --git a/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/inc/ht32_serial.h b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/inc/ht32_serial.h new file mode 100644 index 0000000000..641fb91d51 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/inc/ht32_serial.h @@ -0,0 +1,84 @@ +/*********************************************************************************************************//** + * @file ht32_serial.h + * @version $Rev:: 2765 $ + * @date $Date:: 2022-11-11 #$ + * @brief The header file of the Serial library. + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------------------------------------*/ +#ifndef __HT32_SERIAL_H +#define __HT32_SERIAL_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------------------------------------*/ +#ifdef RETARGET_IS_USB +#include "ht32_usbd_core.h" +#endif + +/** @addtogroup HT32_Peripheral_Driver HT32 Peripheral Driver + * @{ + */ + +/** @addtogroup SERIAL + * @brief Serial related functions + * @{ + */ + + +/* Exported functions --------------------------------------------------------------------------------------*/ +/** @defgroup SERIAL_Exported_Functions Serial exported functions + * @{ + */ +void RETARGET_UART_IRQHandler(void); +u32 SERIAL_GetChar(void); +u32 SERIAL_PutChar(u32 ch); +#ifdef RETARGET_IS_USB +void SERIAL_USBDClass_Request(USBDCore_Device_TypeDef *pDev); +void SERIAL_USBDClass_RXHandler(USBD_EPTn_Enum EPTn); +void SERIAL_USBDClass_TXHandler(USBD_EPTn_Enum EPTn); +void SERIAL_USBDInit(void); +void SERIAL_Flush(void); +#else +#define SERIAL_Flush(...) +#endif +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/inc/ht32_time.h b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/inc/ht32_time.h new file mode 100644 index 0000000000..1fc44cdc7c --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/inc/ht32_time.h @@ -0,0 +1,170 @@ +/*********************************************************************************************************//** + * @file ht32_time.h + * @version $Rev:: 2896 $ + * @date $Date:: 2023-03-04 #$ + * @brief The header file of time function. + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ +/* Define to prevent recursive inclusion -------------------------------------------------------------------*/ +#ifndef __HT32_TIME_H +#define __HT32_TIME_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------------------------------------*/ +#include "ht32.h" +#ifndef HTCFG_TIME_IPSEL +#include "ht32_time_conf.h" +#endif + +/* Settings ------------------------------------------------------------------------------------------------*/ +#ifdef HTCFG_TIME_IPSEL +#if (HTCFG_TIME_IPSEL == 0) +#define HTCFG_TIME_IPN BFTM0 +#endif +#if (HTCFG_TIME_IPSEL == 1) +#define HTCFG_TIME_IPN BFTM1 +#endif +#if (HTCFG_TIME_IPSEL == 2) +#define HTCFG_TIME_IPN SCTM0 +#endif +#if (HTCFG_TIME_IPSEL == 3) +#define HTCFG_TIME_IPN SCTM1 +#endif +#if (HTCFG_TIME_IPSEL == 4) +#define HTCFG_TIME_IPN SCTM2 +#endif +#if (HTCFG_TIME_IPSEL == 5) +#define HTCFG_TIME_IPN SCTM3 +#endif +#if (HTCFG_TIME_IPSEL == 6) +#define HTCFG_TIME_IPN PWM0 +#endif +#if (HTCFG_TIME_IPSEL == 7) +#define HTCFG_TIME_IPN PWM1 +#endif +#if (HTCFG_TIME_IPSEL == 8) +#define HTCFG_TIME_IPN PWM2 +#endif +#if (HTCFG_TIME_IPSEL == 9) +#define HTCFG_TIME_IPN GPTM0 +#endif +#if (HTCFG_TIME_IPSEL == 10) +#define HTCFG_TIME_IPN GPTM1 +#endif +#if (HTCFG_TIME_IPSEL == 11) +#define HTCFG_TIME_IPN MCTM0 +#endif +#endif + +/* Exported constants --------------------------------------------------------------------------------------*/ +#ifndef IS_IPN_BFTM +#undef IPN_MCTM0 +#undef IPN_MCTM1 +#undef IPN_GPTM0 +#undef IPN_GPTM1 + +#define IPN_NULL (0) +#define IPN_MCTM0 (0x4002C000) +#define IPN_MCTM1 (0x4002D000) +#define IPN_GPTM0 (0x4006E000) +#define IPN_GPTM1 (0x4006F000) +#define IPN_SCTM0 (0x40034000) +#define IPN_SCTM1 (0x40074000) +#define IPN_SCTM2 (0x40035000) +#define IPN_SCTM3 (0x40075000) +#define IPN_PWM0 (0x40031000) +#define IPN_PWM1 (0x40071000) +#define IPN_PWM2 (0x40031000) +#define IPN_BFTM0 (0x40076000) +#define IPN_BFTM1 (0x40077000) +#define IPN_CHECK(IP) STRCAT2(IPN_, IP) +#define IS_IPN_BFTM(IP) (IPN_CHECK(IP) == IPN_BFTM0) || (IPN_CHECK(IP) == IPN_BFTM1) +#define IS_IPN_MCTM(IP) (IPN_CHECK(IP) == IPN_MCTM0) || (IPN_CHECK(IP) == IPN_MCTM1) +#define IS_IPN_GPTM(IP) (IPN_CHECK(IP) == IPN_GPTM0) || (IPN_CHECK(IP) == IPN_GPTM1) +#define IS_IPN_SCTM(IP) (IPN_CHECK(IP) == IPN_SCTM0) || (IPN_CHECK(IP) == IPN_SCTM1) || (IPN_CHECK(IP) == IPN_SCTM2) || (IPN_CHECK(IP) == IPN_SCTM3) +#define IS_IPN_PWM(IP) (IPN_CHECK(IP) == IPN_PWM0) || (IPN_CHECK(IP) == IPN_PWM1) || (IPN_CHECK(IP) == IPN_PWM2) +#define IS_IPN_TM(IP) (IS_IPN_MCTM(IP) || IS_IPN_GPTM(IP) || IS_IPN_SCTM(IP) || IS_IPN_PWM(IP)) +#endif + +#define _HTCFG_TIME_PORT STRCAT2(HT_, HTCFG_TIME_IPN) + +#if (HTCFG_TIME_CLKSEL == 0) +#define _HTCFG_TIME_CORECLK (LIBCFG_MAX_SPEED) +#else +#define _HTCFG_TIME_CORECLK (HTCFG_TIME_CLK_MANUAL) +#endif + +#if (LIBCFG_CKCU_NO_APB_PRESCALER == 1) +#undef HTCFG_TIME_PCLK_DIV +#define HTCFG_TIME_PCLK_DIV (0) +#endif + +#define HTCFG_TIME_CLKSRC (_HTCFG_TIME_CORECLK >> HTCFG_TIME_PCLK_DIV) + +#if (IS_IPN_BFTM(HTCFG_TIME_IPN)) +#undef HTCFG_TIME_TICKHZ +#define HTCFG_TIME_TICKHZ HTCFG_TIME_CLKSRC +#endif + +/* Exported macro ------------------------------------------------------------------------------------------*/ +#define TIME_TICKDIFF(start, current) ((current >= start) ? (u32)(current - start) : (u32)(0xFFFFFFFF - start + 1 + current)) + +#if (HTCFG_TIME_TICKHZ < 1000000) +#define TIME_US2TICK(us) (us / (1000000UL / HTCFG_TIME_TICKHZ)) +#define TIME_TICK2US(t) (t * (1000000UL / HTCFG_TIME_TICKHZ)) +#else +#define TIME_US2TICK(us) (us * (HTCFG_TIME_TICKHZ / 1000000UL)) +#define TIME_TICK2US(t) (t / (HTCFG_TIME_TICKHZ / 1000000UL)) +#endif + +#if (HTCFG_TIME_TICKHZ < 1000) +#define TIME_MS2TICK(ms) (ms / (1000UL / HTCFG_TIME_TICKHZ)) +#define TIME_TICK2MS(t) (t * (1000UL / HTCFG_TIME_TICKHZ)) +#else +#define TIME_MS2TICK(ms) (ms * (HTCFG_TIME_TICKHZ / 1000UL)) +#define TIME_TICK2MS(t) (t / (HTCFG_TIME_TICKHZ / 1000UL)) +#endif + +#define TIME_S2TICK(s) (s * (u32)(HTCFG_TIME_TICKHZ)) +#define TIME_TICK2S(t) (t / (HTCFG_TIME_TICKHZ)) + + +#define GET_CNT() (_HTCFG_TIME_PORT->CNTR) + +/* Exported functions --------------------------------------------------------------------------------------*/ +void Time_Init(void); +void Time_Delay(u32 delay); +u32 Time_GetTick(void); + +#if (IS_IPN_BFTM(HTCFG_TIME_IPN)) +// BFTM +#define Time_GetTick GET_CNT +#endif + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/inc/ht32_undef_IP.h b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/inc/ht32_undef_IP.h new file mode 100644 index 0000000000..4339a8135d --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/inc/ht32_undef_IP.h @@ -0,0 +1,200 @@ +/*********************************************************************************************************//** + * @file ht32_undef_IP.h + * @version $Rev:: 2962 $ + * @date $Date:: 2023-10-18 #$ + * @brief Header file for undefined IP. + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ +/* Define to prevent recursive inclusion -------------------------------------------------------------------*/ + +#ifndef __HT32_UNDEF_IP_H +#define __HT32_UNDEF_IP_H + +#ifdef __cplusplus + extern "C" { +#endif + +#if _AES +#undef _AES +#endif + +#ifdef _ADC +#undef _ADC +#endif + +#ifdef _BFTM +#undef _BFTM +#endif + +#ifdef _CAN +#undef _CAN +#endif + +#ifdef _CKCU +#undef _CKCU +#endif + +#ifdef _CMP +#undef _CMP +#endif + +#ifdef _CRC +#undef _CRC +#endif + +#ifdef _CSIF +#undef _CSIF +#endif + +#ifdef _DAC +#undef _DAC +#endif + +#ifdef _DIV +#undef _DIV +#endif + +#ifdef _EBI +#undef _EBI +#endif + +#ifdef _EXTI +#undef _EXTI +#endif + +#ifdef _FLASH +#undef _FLASH +#endif + +#ifdef _GPIO +#undef _GPIO +#endif + +#ifdef _GPTM +#undef _GPTM +#endif + +#ifdef _I2C +#undef _I2C +#endif + +#ifdef _I2S +#undef _I2S +#endif + +#ifdef _LCD +#undef _LCD +#endif + +#ifdef _LEDC +#undef _LEDC +#endif + +#ifdef _MCTM +#undef _MCTM +#endif + +#ifdef _MIDI +#undef _MIDI +#endif + +#ifdef _OPA +#undef _OPA +#endif + +#ifdef _PDMA +#undef _PDMA +#endif + +#ifdef _PWRCU +#undef _PWRCU +#endif + +#ifdef _PWM +#undef _PWM +#endif + +#ifdef _RSTCU +#undef _RSTCU +#endif + +#ifdef _RTC +#undef _RTC +#endif + +#ifdef _SCI +#undef _SCI +#endif + +#ifdef _SCTM +#undef _SCTM +#endif + +#ifdef _SDIO +#undef _SDIO +#endif + +#ifdef _SLED +#undef _SLED +#endif + +#ifdef _SPI +#undef _SPI +#endif + +#ifdef _TKEY +#undef _TKEY +#endif + +#ifdef _USART +#undef _USART +#endif + +#ifdef _USB +#undef _USB +#endif + +#ifdef _WDT +#undef _WDT +#endif + +#ifdef _MISC +#undef _MISC +#endif + +#ifdef _SERIAL +#undef _SERIAL +#endif + +#ifdef _SWDIV +#undef _SWDIV +#endif + +#ifdef _SWRAND +#undef _SWRAND +#endif + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/inc/ht32f12345_libcfg.h b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/inc/ht32f12345_libcfg.h new file mode 100644 index 0000000000..3e435d4b16 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/inc/ht32f12345_libcfg.h @@ -0,0 +1,57 @@ +/*********************************************************************************************************//** + * @file ht32f12345_libcfg.h + * @version $Rev:: 2805 $ + * @date $Date:: 2022-12-01 #$ + * @brief The library configuration file. + ************************************************************************************************************* +* @attention +* +* Firmware Disclaimer Information +* +* 1. The customer hereby acknowledges and agrees that the program technical documentation, including the +* code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the +* proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and +* other intellectual property laws. +* +* 2. The customer hereby acknowledges and agrees that the program technical documentation, including the +* code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties +* other than HOLTEK and the customer. +* +* 3. The program technical documentation, including the code, is provided "as is" and for customer reference +* only. After delivery by HOLTEK, the customer shall use the program technical documentation, including +* the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including +* the warranties of merchantability, satisfactory quality and fitness for a particular purpose. +* +*

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ +/* Define to prevent recursive inclusion -------------------------------------------------------------------*/ +#ifndef __HT32F12345_LIBCFG_H +#define __HT32F12345_LIBCFG_H + +/* Settings ------------------------------------------------------------------------------------------------*/ + +#if !defined(USE_MEM_HT32F12345) +#define USE_MEM_HT32F12345 +#endif + +#define LIBCFG_MAX_SPEED (96000000) + +#define LIBCFG_FLASH_PAGESIZE (1024) + +#ifdef USE_MEM_HT32F12345 + #define LIBCFG_FLASH_SIZE (LIBCFG_FLASH_PAGESIZE * 63) + #define LIBCFG_RAM_SIZE (1024 * 16) + #define LIBCFG_CHIPNAME (0x12345) +#endif + +#define LIBCFG_SDIO (1) + +#define LIBCFG_CKCU_NO_ADCPRE_DIV1 (1) +#define LIBCFG_CKCU_USB_PLL (1) +#define LIBCFG_FMC_WAIT_STATE_3 (1) +#define LIBCFG_PDMA_CH8_11 (1) +#define LIBCFG_PDMA_CH3FIX (1) +#define LIBCFG_RTC_LSI_LOAD_TRIM (1) +#define LIBCFG_CKCU_AUTO_TRIM_LEGACY (1) + +#endif diff --git a/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/inc/ht32f12364_libcfg.h b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/inc/ht32f12364_libcfg.h new file mode 100644 index 0000000000..5093b68847 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/inc/ht32f12364_libcfg.h @@ -0,0 +1,77 @@ +/*********************************************************************************************************//** + * @file ht32f12364_libcfg.h + * @version $Rev:: 2805 $ + * @date $Date:: 2022-12-01 #$ + * @brief The library configuration file. + ************************************************************************************************************* +* @attention +* +* Firmware Disclaimer Information +* +* 1. The customer hereby acknowledges and agrees that the program technical documentation, including the +* code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the +* proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and +* other intellectual property laws. +* +* 2. The customer hereby acknowledges and agrees that the program technical documentation, including the +* code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties +* other than HOLTEK and the customer. +* +* 3. The program technical documentation, including the code, is provided "as is" and for customer reference +* only. After delivery by HOLTEK, the customer shall use the program technical documentation, including +* the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including +* the warranties of merchantability, satisfactory quality and fitness for a particular purpose. +* +*

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ +/* Define to prevent recursive inclusion -------------------------------------------------------------------*/ +#ifndef __HT32F12364_LIBCFG_H +#define __HT32F12364_LIBCFG_H + +/* Settings ------------------------------------------------------------------------------------------------*/ + +#if !defined(USE_MEM_HT32F12364) +#define USE_MEM_HT32F12364 +#endif + +#define LIBCFG_MAX_SPEED (72000000) + +#define LIBCFG_FLASH_PAGESIZE (1024) + +#ifdef USE_MEM_HT32F12364 + #define LIBCFG_FLASH_SIZE (LIBCFG_FLASH_PAGESIZE * 255) + #define LIBCFG_RAM_SIZE (1024 * 128) + #define LIBCFG_CHIPNAME (0x12364) +#endif + +#define LIBCFG_ADC_V01 (1) +#define LIBCFG_ADC_IVREF (1) +#define LIBCFG_AES (1) +#define LIBCFG_CKCU_APBPCSR2 (1) +#define LIBCFG_CKCU_ADCPRE_DIV5 (1) +#define LIBCFG_CKCU_ATM_V01 (1) +#define LIBCFG_CKCU_USB_PLL (1) +#define LIBCFG_EBI_V01 (1) +#define LIBCFG_FLASH_2PAGE_PER_WPBIT (1) +#define LIBCFG_FMC_WAIT_STATE_3 (1) +#define LIBCFG_GPIOF (1) +#define LIBCFG_NO_ADC_CH8_15 (1) +#define LIBCFG_NO_BACK_DOMAIN (1) +#define LIBCFG_NO_CKCU_USBPRE (1) +#define LIBCFG_NO_CMP_TRIG_ADC (1) +#define LIBCFG_NO_CMP_HPTRIG_ADC (1) +#define LIBCFG_NO_GPTM1 (1) +#define LIBCFG_NO_I2S (1) +#define LIBCFG_NO_MCTM0 (1) +#define LIBCFG_NO_MCTM1 (1) +#define LIBCFG_NO_PDMA_CH6_11 (1) +#define LIBCFG_NO_USART1 (1) +#define LIBCFG_PDMA_V01 (1) +#define LIBCFG_PWM0 (1) +#define LIBCFG_PWRCU_LVDS_17_31 (1) +#define LIBCFG_SCI0 (1) +#define LIBCFG_SCTM0 (1) +#define LIBCFG_SCTM1 (1) +#define LIBCFG_SPI_CLK_PRE_V01 (1) + +#endif diff --git a/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/inc/ht32f12365_66_libcfg.h b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/inc/ht32f12365_66_libcfg.h new file mode 100644 index 0000000000..ee16bf2fa1 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/inc/ht32f12365_66_libcfg.h @@ -0,0 +1,78 @@ +/*********************************************************************************************************//** + * @file ht32f12365_66_libcfg.h + * @version $Rev:: 2805 $ + * @date $Date:: 2022-12-01 #$ + * @brief The library configuration file. + ************************************************************************************************************* +* @attention +* +* Firmware Disclaimer Information +* +* 1. The customer hereby acknowledges and agrees that the program technical documentation, including the +* code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the +* proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and +* other intellectual property laws. +* +* 2. The customer hereby acknowledges and agrees that the program technical documentation, including the +* code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties +* other than HOLTEK and the customer. +* +* 3. The program technical documentation, including the code, is provided "as is" and for customer reference +* only. After delivery by HOLTEK, the customer shall use the program technical documentation, including +* the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including +* the warranties of merchantability, satisfactory quality and fitness for a particular purpose. +* +*

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ +/* Define to prevent recursive inclusion -------------------------------------------------------------------*/ +#ifndef __HT32F12365_66_LIBCFG_H +#define __HT32F12365_66_LIBCFG_H + +/* Settings ------------------------------------------------------------------------------------------------*/ + +#if !defined(USE_MEM_HT32F12365) && !defined(USE_MEM_HT32F12366) && !defined(USE_MEM_HT32F22366) +#define USE_MEM_HT32F12366 +#endif + +#define LIBCFG_MAX_SPEED (96000000) + +#define LIBCFG_FLASH_PAGESIZE (1024) + +#ifdef USE_MEM_HT32F12365 + #define LIBCFG_FLASH_SIZE (LIBCFG_FLASH_PAGESIZE * 255) + #define LIBCFG_RAM_SIZE (1024 * 64) + #define LIBCFG_CHIPNAME (0x12365) +#endif + +#ifdef USE_MEM_HT32F12366 + #define LIBCFG_FLASH_SIZE (LIBCFG_FLASH_PAGESIZE * 255) + #define LIBCFG_RAM_SIZE (1024 * 128) + #define LIBCFG_CHIPNAME (0x12366) +#endif + +#ifdef USE_MEM_HT32F22366 + #define LIBCFG_FLASH_SIZE (LIBCFG_FLASH_PAGESIZE * 255) + #define LIBCFG_RAM_SIZE (1024 * 128) + #define LIBCFG_CHIPNAME (0x22366) +#endif + +#define LIBCFG_AES (1) +#define LIBCFG_CSIF (1) +#define LIBCFG_GPIOE (1) +#define LIBCFG_SCI0 (1) +#define LIBCFG_SCI1 (1) +#define LIBCFG_SDIO (1) + +#define LIBCFG_ADC_CH12_15 (1) +#define LIBCFG_CKCU_NO_ADCPRE_DIV1 (1) +#define LIBCFG_CKCU_USB_PLL (1) +#define LIBCFG_EBI_BYTELAND_ASYNCREADY (1) +#define LIBCFG_FLASH_2PAGE_PER_WPBIT (1) +#define LIBCFG_FMC_WAIT_STATE_3 (1) +#define LIBCFG_PDMA_CH8_11 (1) +#define LIBCFG_PDMA_CH3FIX (1) +#define LIBCFG_RTC_LSI_LOAD_TRIM (1) +#define LIBCFG_CKCU_AUTO_TRIM_LEGACY (1) +#define LIBCFG_AES_SWAP (1) + +#endif diff --git a/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/inc/ht32f1653_54_libcfg.h b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/inc/ht32f1653_54_libcfg.h new file mode 100644 index 0000000000..cebe74e637 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/inc/ht32f1653_54_libcfg.h @@ -0,0 +1,77 @@ +/*********************************************************************************************************//** + * @file ht32f1653_54_libcfg.h + * @version $Rev:: 2805 $ + * @date $Date:: 2022-12-01 #$ + * @brief The library configuration file. + ************************************************************************************************************* +* @attention +* +* Firmware Disclaimer Information +* +* 1. The customer hereby acknowledges and agrees that the program technical documentation, including the +* code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the +* proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and +* other intellectual property laws. +* +* 2. The customer hereby acknowledges and agrees that the program technical documentation, including the +* code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties +* other than HOLTEK and the customer. +* +* 3. The program technical documentation, including the code, is provided "as is" and for customer reference +* only. After delivery by HOLTEK, the customer shall use the program technical documentation, including +* the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including +* the warranties of merchantability, satisfactory quality and fitness for a particular purpose. +* +*

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ +/* Define to prevent recursive inclusion -------------------------------------------------------------------*/ +#ifndef __HT32F1653_54_LIBCFG_H +#define __HT32F1653_54_LIBCFG_H + +/* Settings ------------------------------------------------------------------------------------------------*/ + +#if !defined(USE_MEM_HT32F1653) && !defined(USE_MEM_HT32F1654) +#define USE_MEM_HT32F1654 +#endif + +#define LIBCFG_MAX_SPEED (72000000) + +#define LIBCFG_FLASH_PAGESIZE (1024) + +#ifdef USE_MEM_HT32F1653 + #define LIBCFG_FLASH_SIZE (LIBCFG_FLASH_PAGESIZE * 32) + #define LIBCFG_RAM_SIZE (1024 * 8) + #define LIBCFG_CHIPNAME (0x1653) +#endif + +#ifdef USE_MEM_HT32F1654 + #define LIBCFG_FLASH_SIZE (LIBCFG_FLASH_PAGESIZE * 63) + #define LIBCFG_RAM_SIZE (1024 * 16) + #define LIBCFG_CHIPNAME (0x1654) +#endif + +#define LIBCFG_SCI0 (1) + +#define LIBCFG_ADC_NOENBIT (1) +#define LIBCFG_CKCU_AUTOTRIM_NOCKIN (1) +#define LIBCFG_CKCU_CKSWST_LEGACY (1) +#define LIBCFG_CKCU_NO_ADCPRE_DIV1 (1) +#define LIBCFG_CKCU_NO_HCLK_LOW_SPEED (1) +#define LIBCDG_CKCU_PLL_144M (1) +#define LIBCDG_CKCU_SYSCLK_DIV8_ONLY (1) +#define LIBCFG_CKCU_USB_DIV3 (1) +#define LIBCFG_FLASH_HALFCYCYLE (1) +#define LIBCFG_FLASH_ZWPWESAVING (1) +#define LIBCFG_NO_CMP_HPTRIG_ADC (1) +#define LIBCFG_GPIO_DV_4_8MA_ONLY (1) +#define LIBCFG_PDMA_BLKLEN65536 (1) +#define LIBCFG_PDMA_CH3FIX (1) +#define LIBCFG_PWRCU_HSI_READY_COUNTER (1) +#define LIBCFG_PWRCU_LDO_LEGACY (1) +#define LIBCFG_PWRCU_LVDS_27_35 (1) +#define LIBCFG_RTC_LSI_LOAD_TRIM (1) +#define LIBCFG_USART_V01 (1) +#define LIBCFG_WDT_INT (1) +#define LIBCFC_WEAK_AF1 (1) + +#endif diff --git a/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/inc/ht32f1655_56_libcfg.h b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/inc/ht32f1655_56_libcfg.h new file mode 100644 index 0000000000..30ac2b2792 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/inc/ht32f1655_56_libcfg.h @@ -0,0 +1,86 @@ +/*********************************************************************************************************//** + * @file ht32f1655_56_libcfg.h + * @version $Rev:: 2887 $ + * @date $Date:: 2023-03-02 #$ + * @brief The library configuration file. + ************************************************************************************************************* +* @attention +* +* Firmware Disclaimer Information +* +* 1. The customer hereby acknowledges and agrees that the program technical documentation, including the +* code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the +* proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and +* other intellectual property laws. +* +* 2. The customer hereby acknowledges and agrees that the program technical documentation, including the +* code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties +* other than HOLTEK and the customer. +* +* 3. The program technical documentation, including the code, is provided "as is" and for customer reference +* only. After delivery by HOLTEK, the customer shall use the program technical documentation, including +* the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including +* the warranties of merchantability, satisfactory quality and fitness for a particular purpose. +* +*

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ +/* Define to prevent recursive inclusion -------------------------------------------------------------------*/ +#ifndef __HT32F1655_56_LIBCFG_H +#define __HT32F1655_56_LIBCFG_H + +/* Settings ------------------------------------------------------------------------------------------------*/ + +#if !defined(USE_MEM_HT32F1655) && !defined(USE_MEM_HT32F1656) +#define USE_MEM_HT32F1656 +#endif + +#define LIBCFG_MAX_SPEED (72000000) + +#define LIBCFG_FLASH_PAGESIZE (1024) + +#ifdef USE_MEM_HT32F1655 + #define LIBCFG_FLASH_SIZE (LIBCFG_FLASH_PAGESIZE * 128) + #define LIBCFG_RAM_SIZE (1024 * 32) + #define LIBCFG_CHIPNAME (0x1655) +#endif + +#ifdef USE_MEM_HT32F1656 + #define LIBCFG_FLASH_SIZE (LIBCFG_FLASH_PAGESIZE * 255) + #define LIBCFG_RAM_SIZE (1024 * 32) + #define LIBCFG_CHIPNAME (0x1656) +#endif + +#define LIBCFG_CMP_OPA (1) +#define LIBCFG_GPIOE (1) +#define LIBCFG_SCI0 (1) + +#define LIBCFG_ADC_CH12_15 (1) +#define LIBCFG_ADC_NOENBIT (1) +#define LIBCFG_CKCU_NO_APB_PRESCALER (1) +#define LIBCFG_CKCU_CKSWST_LEGACY (1) +#define LIBCFG_CKCU_HSI_NO_AUTOTRIM (1) +#define LIBCFG_CKCU_NO_ADCPRE_DIV1 (1) +#define LIBCFG_CKCU_NO_HCLK_LOW_SPEED (1) +#define LIBCDG_CKCU_PLL_144M (1) +#define LIBCDG_CKCU_SYSCLK_DIV8_ONLY (1) +#define LIBCFG_CKCU_USART_PRESCALER (1) +#define LIBCFG_CKCU_USB_DIV3 (1) +#define LIBCFG_EBI_BYTELAND_ASYNCREADY (1) +#define LIBCFG_EXTI_8BIT_DEBOUNCE_COUNTER (1) +#define LIBCFG_GPIO_DV_4_8MA_ONLY (1) +#define LIBCFG_FLASH_2PAGE_PER_WPBIT (1) +#define LIBCFG_FLASH_HALFCYCYLE (1) +#define LIBCFG_FLASH_ZWPWESAVING (1) +#define LIBCFG_NO_CMP_TRIG_ADC (1) +#define LIBCFG_NO_CMP_HPTRIG_ADC (1) +#define LIBCFG_PDMA_BLKLEN65536 (1) +#define LIBCFG_PDMA_CH3FIX (1) +#define LIBCFG_PWRCU_HSI_READY_COUNTER (1) +#define LIBCFG_PWRCU_LDO_LEGACY (1) +#define LIBCFG_PWRCU_LVDS_27_35 (1) +#define LIBCFG_RTC_LSI_LOAD_TRIM (1) +#define LIBCFG_USART_V01 (1) +#define LIBCFG_WDT_INT (1) +#define LIBCFC_WEAK_AF1 (1) + +#endif diff --git a/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/inc/ht32f1xxxx_adc.h b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/inc/ht32f1xxxx_adc.h new file mode 100644 index 0000000000..92e286f14b --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/inc/ht32f1xxxx_adc.h @@ -0,0 +1,498 @@ +/*********************************************************************************************************//** + * @file ht32f1xxxx_adc.h + * @version $Rev:: 2791 $ + * @date $Date:: 2022-11-24 #$ + * @brief The header file of the ADC library. + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------------------------------------*/ +#ifndef __HT32F1XXXX_ADC_H +#define __HT32F1XXXX_ADC_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------------------------------------*/ +#include "ht32.h" + +/** @addtogroup HT32F1xxxx_Peripheral_Driver HT32F1xxxx Peripheral Driver + * @{ + */ + +/** @addtogroup ADC + * @{ + */ + + +/* Exported constants --------------------------------------------------------------------------------------*/ +/** @defgroup ADC_Exported_Constants ADC exported constants + * @{ + */ +#define IS_ADC(x) (x == HT_ADC) + +#define ONE_SHOT_MODE (0x00000000) +#define CONTINUOUS_MODE (0x00000002) +#define DISCONTINUOUS_MODE (0x00000003) + +#define IS_ADC_CONVERSION_MODE(REGULAR_MODE) (((REGULAR_MODE) == ONE_SHOT_MODE) || \ + ((REGULAR_MODE) == CONTINUOUS_MODE) || \ + ((REGULAR_MODE) == DISCONTINUOUS_MODE)) + +#define IS_ADC_HP_CONVERSION_MODE(HP_MODE) (((HP_MODE) == ONE_SHOT_MODE) || \ + ((HP_MODE) == CONTINUOUS_MODE) || \ + ((HP_MODE) == DISCONTINUOUS_MODE)) + + +#define ADC_CH_0 (0) +#define ADC_CH_1 (1) +#define ADC_CH_2 (2) +#define ADC_CH_3 (3) +#define ADC_CH_4 (4) +#define ADC_CH_5 (5) +#define ADC_CH_6 (6) +#define ADC_CH_7 (7) +#if !(LIBCFG_NO_ADC_CH8_15) +#define ADC_CH_8 (8) +#define ADC_CH_9 (9) +#define ADC_CH_10 (10) +#define ADC_CH_11 (11) +#if (LIBCFG_ADC_CH12_15) +#define ADC_CH_12 (12) +#define ADC_CH_13 (13) +#define ADC_CH_14 (14) +#define ADC_CH_15 (15) +#define IS_ADC_CHANNEL12_15(CHANNEL) (((CHANNEL) == ADC_CH_12) || ((CHANNEL) == ADC_CH_13) || \ + ((CHANNEL) == ADC_CH_14) || ((CHANNEL) == ADC_CH_15)) +#else +#define IS_ADC_CHANNEL12_15(CHANNEL) (0) +#endif +#else +#define IS_ADC_CHANNEL8_14(CHANNEL) (0) +#define ADC_CH_IVREF (15) +#endif +#define ADC_CH_GND_VREF (16) +#define ADC_CH_VDD_VREF (17) + +#define ADC_CH_GNDREF ADC_CH_GND_VREF +#define ADC_CH_VREF ADC_CH_VDD_VREF + + +#if (LIBCFG_NO_ADC_CH8_15) +#define IS_ADC_CHANNEL(CHANNEL) (((CHANNEL) == ADC_CH_0) || ((CHANNEL) == ADC_CH_1) || \ + ((CHANNEL) == ADC_CH_2) || ((CHANNEL) == ADC_CH_3) || \ + ((CHANNEL) == ADC_CH_4) || ((CHANNEL) == ADC_CH_5) || \ + ((CHANNEL) == ADC_CH_6) || ((CHANNEL) == ADC_CH_7) || \ + (IS_ADC_CHANNEL8_14(CHANNEL)) || \ + ((CHANNEL) == ADC_CH_IVREF) || ((CHANNEL) == ADC_CH_GND_VREF) || \ + ((CHANNEL) == ADC_CH_VDD_VREF)) +#else +#define IS_ADC_CHANNEL(CHANNEL) (((CHANNEL) == ADC_CH_0) || ((CHANNEL) == ADC_CH_1) || \ + ((CHANNEL) == ADC_CH_2) || ((CHANNEL) == ADC_CH_3) || \ + ((CHANNEL) == ADC_CH_4) || ((CHANNEL) == ADC_CH_5) || \ + ((CHANNEL) == ADC_CH_6) || ((CHANNEL) == ADC_CH_7) || \ + ((CHANNEL) == ADC_CH_8) || ((CHANNEL) == ADC_CH_9) || \ + ((CHANNEL) == ADC_CH_10) || ((CHANNEL) == ADC_CH_11) || \ + (IS_ADC_CHANNEL12_15(CHANNEL)) || \ + ((CHANNEL) == ADC_CH_GND_VREF) || ((CHANNEL) == ADC_CH_VDD_VREF)) +#endif + +#if (LIBCFG_NO_ADC_CH8_15) +#define IS_ADC_INPUT_CHANNEL(CHANNEL) (((CHANNEL) == ADC_CH_0) || ((CHANNEL) == ADC_CH_1) || \ + ((CHANNEL) == ADC_CH_2) || ((CHANNEL) == ADC_CH_3) || \ + ((CHANNEL) == ADC_CH_4) || ((CHANNEL) == ADC_CH_5) || \ + ((CHANNEL) == ADC_CH_6) || ((CHANNEL) == ADC_CH_7)) +#else +#define IS_ADC_INPUT_CHANNEL(CHANNEL) (((CHANNEL) == ADC_CH_0) || ((CHANNEL) == ADC_CH_1) || \ + ((CHANNEL) == ADC_CH_2) || ((CHANNEL) == ADC_CH_3) || \ + ((CHANNEL) == ADC_CH_4) || ((CHANNEL) == ADC_CH_5) || \ + ((CHANNEL) == ADC_CH_6) || ((CHANNEL) == ADC_CH_7) || \ + ((CHANNEL) == ADC_CH_8) || ((CHANNEL) == ADC_CH_9) || \ + ((CHANNEL) == ADC_CH_10) || ((CHANNEL) == ADC_CH_11) || \ + (IS_ADC_CHANNEL12_15(CHANNEL))) +#endif + +#define ADC_TRIG_SOFTWARE (1UL << 0) + +/* ((ADCTCR[4] << 4) | (ADCTSR[20] << 20)) */ +#if (!LIBCFG_NO_CMP_TRIG_ADC) +#define ADC_TRIG_CMP0 ((1UL << 4) | (0UL << 20)) +#define ADC_TRIG_CMP1 ((1UL << 4) | (1UL << 20)) +#endif + +#if (!LIBCFG_NO_CMP_HPTRIG_ADC) +#define ADC_HPTRIG_CMP0 ADC_TRIG_CMP0 +#define ADC_HPTRIG_CMP1 ADC_TRIG_CMP1 +#endif + +/* ((ADCTCR[3] << 3) | (ADCTSR[23:22] << 22) | (ADCTSR[19] << 19)) */ +#define ADC_TRIG_BFTM0 ((1UL << 3) | (0UL << 22) | (0UL << 19)) +#define ADC_TRIG_BFTM1 ((1UL << 3) | (0UL << 22) | (1UL << 19)) + +/* ((ADCTCR[3] << 3) | (ADCTSR[29:27]) << 27) | (ADCTSR[23:22] << 22) | (ADCTSR[19] << 19)) */ +#if (LIBCFG_PWM0) +#define ADC_TRIG_PWM0_MTO ((1UL << 3) | (0UL << 27) | (1UL << 22) | (0UL << 19)) +#define ADC_TRIG_PWM0_CH0O ((1UL << 3) | (1UL << 27) | (1UL << 22) | (0UL << 19)) +#define ADC_TRIG_PWM0_CH1O ((1UL << 3) | (2UL << 27) | (1UL << 22) | (0UL << 19)) +#define ADC_TRIG_PWM0_CH2O ((1UL << 3) | (3UL << 27) | (1UL << 22) | (0UL << 19)) +#define ADC_TRIG_PWM0_CH3O ((1UL << 3) | (4UL << 27) | (1UL << 22) | (0UL << 19)) +#endif +#if (LIBCFG_PWM1) +#define ADC_TRIG_PWM1_MTO ((1UL << 3) | (0UL << 27) | (1UL << 22) | (1UL << 19)) +#define ADC_TRIG_PWM1_CH0O ((1UL << 3) | (1UL << 27) | (1UL << 22) | (1UL << 19)) +#define ADC_TRIG_PWM1_CH1O ((1UL << 3) | (2UL << 27) | (1UL << 22) | (1UL << 19)) +#define ADC_TRIG_PWM1_CH2O ((1UL << 3) | (3UL << 27) | (1UL << 22) | (1UL << 19)) +#define ADC_TRIG_PWM1_CH3O ((1UL << 3) | (4UL << 27) | (1UL << 22) | (1UL << 19)) +#endif + +/* ((ADCTCR[2] << 2) | (ADCTSR[26:24] << 24) | (ADCTSR[18:16] << 16)) */ +#if (!LIBCFG_NO_MCTM0) +#define ADC_TRIG_MCTM0_MTO ((1UL << 2) | (0UL << 24) | (0UL << 16)) +#define ADC_TRIG_MCTM0_CH0O ((1UL << 2) | (1UL << 24) | (0UL << 16)) +#define ADC_TRIG_MCTM0_CH1O ((1UL << 2) | (2UL << 24) | (0UL << 16)) +#define ADC_TRIG_MCTM0_CH2O ((1UL << 2) | (3UL << 24) | (0UL << 16)) +#define ADC_TRIG_MCTM0_CH3O ((1UL << 2) | (4UL << 24) | (0UL << 16)) +#endif + +#if (!LIBCFG_NO_MCTM1) +#define ADC_TRIG_MCTM1_MTO ((1UL << 2) | (0UL << 24) | (1UL << 16)) +#define ADC_TRIG_MCTM1_CH0O ((1UL << 2) | (1UL << 24) | (1UL << 16)) +#define ADC_TRIG_MCTM1_CH1O ((1UL << 2) | (2UL << 24) | (1UL << 16)) +#define ADC_TRIG_MCTM1_CH2O ((1UL << 2) | (3UL << 24) | (1UL << 16)) +#define ADC_TRIG_MCTM1_CH3O ((1UL << 2) | (4UL << 24) | (1UL << 16)) +#endif + +#define ADC_TRIG_GPTM0_MTO ((1UL << 2) | (0UL << 24) | (2UL << 16)) +#define ADC_TRIG_GPTM0_CH0O ((1UL << 2) | (1UL << 24) | (2UL << 16)) +#define ADC_TRIG_GPTM0_CH1O ((1UL << 2) | (2UL << 24) | (2UL << 16)) +#define ADC_TRIG_GPTM0_CH2O ((1UL << 2) | (3UL << 24) | (2UL << 16)) +#define ADC_TRIG_GPTM0_CH3O ((1UL << 2) | (4UL << 24) | (2UL << 16)) + +#if (!LIBCFG_NO_GPTM1) +#define ADC_TRIG_GPTM1_MTO ((1UL << 2) | (0UL << 24) | (3UL << 16)) +#define ADC_TRIG_GPTM1_CH0O ((1UL << 2) | (1UL << 24) | (3UL << 16)) +#define ADC_TRIG_GPTM1_CH1O ((1UL << 2) | (2UL << 24) | (3UL << 16)) +#define ADC_TRIG_GPTM1_CH2O ((1UL << 2) | (3UL << 24) | (3UL << 16)) +#define ADC_TRIG_GPTM1_CH3O ((1UL << 2) | (4UL << 24) | (3UL << 16)) +#endif + +/* (ADCTCR[1] << 1) | (ADCTSR[11:8] << 8) */ +#define ADC_TRIG_EXTI_0 ((1UL << 1) | ( 0UL << 8)) +#define ADC_TRIG_EXTI_1 ((1UL << 1) | ( 1UL << 8)) +#define ADC_TRIG_EXTI_2 ((1UL << 1) | ( 2UL << 8)) +#define ADC_TRIG_EXTI_3 ((1UL << 1) | ( 3UL << 8)) +#define ADC_TRIG_EXTI_4 ((1UL << 1) | ( 4UL << 8)) +#define ADC_TRIG_EXTI_5 ((1UL << 1) | ( 5UL << 8)) +#define ADC_TRIG_EXTI_6 ((1UL << 1) | ( 6UL << 8)) +#define ADC_TRIG_EXTI_7 ((1UL << 1) | ( 7UL << 8)) +#define ADC_TRIG_EXTI_8 ((1UL << 1) | ( 8UL << 8)) +#define ADC_TRIG_EXTI_9 ((1UL << 1) | ( 9UL << 8)) +#define ADC_TRIG_EXTI_10 ((1UL << 1) | (10UL << 8)) +#define ADC_TRIG_EXTI_11 ((1UL << 1) | (11UL << 8)) +#define ADC_TRIG_EXTI_12 ((1UL << 1) | (12UL << 8)) +#define ADC_TRIG_EXTI_13 ((1UL << 1) | (13UL << 8)) +#define ADC_TRIG_EXTI_14 ((1UL << 1) | (14UL << 8)) +#define ADC_TRIG_EXTI_15 ((1UL << 1) | (15UL << 8)) + + +#define IS_ADC_TRIG(REGTRIG) (IS_ADC_TRIG1(REGTRIG) || \ + IS_ADC_TRIG2(REGTRIG) || \ + IS_ADC_TRIG3(REGTRIG) || \ + IS_ADC_TRIG4(REGTRIG) || \ + IS_ADC_TRIG5(REGTRIG) || \ + IS_ADC_TRIG6(REGTRIG) || \ + IS_ADC_TRIG7(REGTRIG)) + +#define IS_ADC_HPTRIG(REGTRIG) (IS_ADC_TRIG1(REGTRIG) || \ + IS_ADC_TRIG2(REGTRIG) || \ + IS_ADC_TRIG3(REGTRIG) || \ + IS_ADC_TRIG4(REGTRIG) || \ + IS_ADC_TRIG5(REGTRIG) || \ + IS_ADC_TRIG6(REGTRIG) || \ + IS_ADC_HPTRIG7(REGTRIG)) + +#define IS_ADC_TRIG1(REGTRIG) (((REGTRIG) == ADC_TRIG_GPTM0_MTO) || \ + ((REGTRIG) == ADC_TRIG_GPTM0_CH0O) || \ + ((REGTRIG) == ADC_TRIG_GPTM0_CH1O) || \ + ((REGTRIG) == ADC_TRIG_GPTM0_CH2O) || \ + ((REGTRIG) == ADC_TRIG_GPTM0_CH3O) || \ + ((REGTRIG) == ADC_TRIG_BFTM0) || \ + ((REGTRIG) == ADC_TRIG_EXTI_0) || \ + ((REGTRIG) == ADC_TRIG_EXTI_1) || \ + ((REGTRIG) == ADC_TRIG_EXTI_2) || \ + ((REGTRIG) == ADC_TRIG_EXTI_3) || \ + ((REGTRIG) == ADC_TRIG_EXTI_4) || \ + ((REGTRIG) == ADC_TRIG_EXTI_5) || \ + ((REGTRIG) == ADC_TRIG_EXTI_6) || \ + ((REGTRIG) == ADC_TRIG_EXTI_7) || \ + ((REGTRIG) == ADC_TRIG_EXTI_8) || \ + ((REGTRIG) == ADC_TRIG_EXTI_9) || \ + ((REGTRIG) == ADC_TRIG_EXTI_10) || \ + ((REGTRIG) == ADC_TRIG_EXTI_11) || \ + ((REGTRIG) == ADC_TRIG_EXTI_12) || \ + ((REGTRIG) == ADC_TRIG_EXTI_13) || \ + ((REGTRIG) == ADC_TRIG_EXTI_14) || \ + ((REGTRIG) == ADC_TRIG_EXTI_15) || \ + ((REGTRIG) == ADC_TRIG_SOFTWARE)) + +#define IS_ADC_TRIG2(REGTRIG) ((REGTRIG) == ADC_TRIG_BFTM1) + +#if (!LIBCFG_NO_MCTM0) +#define IS_ADC_TRIG3(REGTRIG) (((REGTRIG) == ADC_TRIG_MCTM0_MTO) || \ + ((REGTRIG) == ADC_TRIG_MCTM0_CH0O) || \ + ((REGTRIG) == ADC_TRIG_MCTM0_CH1O) || \ + ((REGTRIG) == ADC_TRIG_MCTM0_CH2O) || \ + ((REGTRIG) == ADC_TRIG_MCTM0_CH3O) || \ + ((REGTRIG) == ADC_TRIG_BFTM1)) +#else +#define IS_ADC_TRIG3(REGTRIG) (0) +#endif + +#if (!LIBCFG_NO_MCTM1) +#define IS_ADC_TRIG4(REGTRIG) (((REGTRIG) == ADC_TRIG_GPTM1_MTO) || \ + ((REGTRIG) == ADC_TRIG_GPTM1_CH0O) || \ + ((REGTRIG) == ADC_TRIG_GPTM1_CH1O) || \ + ((REGTRIG) == ADC_TRIG_GPTM1_CH2O) || \ + ((REGTRIG) == ADC_TRIG_GPTM1_CH3O)) +#else +#define IS_ADC_TRIG4(REGTRIG) (0) +#endif + +#if (LIBCFG_PWM0) +#define IS_ADC_TRIG5(REGTRIG) (((REGTRIG) == ADC_TRIG_PWM0_MTO) || \ + ((REGTRIG) == ADC_TRIG_PWM0_CH0O) || \ + ((REGTRIG) == ADC_TRIG_PWM0_CH1O) || \ + ((REGTRIG) == ADC_TRIG_PWM0_CH2O) || \ + ((REGTRIG) == ADC_TRIG_PWM0_CH3O)) +#else +#define IS_ADC_TRIG5(REGTRIG) (0) +#endif + +#if (LIBCFG_PWM1) +#define IS_ADC_TRIG6(REGTRIG) (((REGTRIG) == ADC_TRIG_PWM1_MTO) || \ + ((REGTRIG) == ADC_TRIG_PWM1_CH0O) || \ + ((REGTRIG) == ADC_TRIG_PWM1_CH1O) || \ + ((REGTRIG) == ADC_TRIG_PWM1_CH2O) || \ + ((REGTRIG) == ADC_TRIG_PWM1_CH3O)) +#else +#define IS_ADC_TRIG6(REGTRIG) (0) +#endif + +#if (!LIBCFG_NO_CMP_TRIG_ADC) +#define IS_ADC_TRIG7(REGTRIG) (((REGTRIG) == ADC_TRIG_CMP0) || \ + ((REGTRIG) == ADC_TRIG_CMP1)) +#else +#define IS_ADC_TRIG7(REGTRIG) (0) +#endif + +#if (!LIBCFG_NO_CMP_HPTRIG_ADC) +#define IS_ADC_HPTRIG7(REGTRIG) (((REGTRIG) == ADC_HPTRIG_CMP0) || \ + ((REGTRIG) == ADC_HPTRIG_CMP1)) +#else +#define IS_ADC_HPTRIG7(REGTRIG) (0) +#endif + + +#define ADC_INT_SINGLE_EOC (0x00000001) +#define ADC_INT_SUB_GROUP_EOC (0x00000002) +#define ADC_INT_CYCLE_EOC (0x00000004) +#define ADC_INT_HP_SINGLE_EOC (0x00000100) +#define ADC_INT_HP_SUB_GROUP_EOC (0x00000200) +#define ADC_INT_HP_CYCLE_EOC (0x00000400) +#define ADC_INT_AWD_LOWER (0x00010000) +#define ADC_INT_AWD_UPPER (0x00020000) +#define ADC_INT_DATA_OVERWRITE (0x01000000) +#define ADC_INT_HP_DATA_OVERWRITE (0x02000000) + +#define IS_ADC_INT(INT) ((((INT) & 0xFCFCF8F8) == 0) && ((INT) != 0)) + + +#define ADC_FLAG_SINGLE_EOC (0x00000001) +#define ADC_FLAG_SUB_GROUP_EOC (0x00000002) +#define ADC_FLAG_CYCLE_EOC (0x00000004) +#define ADC_FLAG_HP_SINGLE_EOC (0x00000100) +#define ADC_FLAG_HP_SUB_GROUP_EOC (0x00000200) +#define ADC_FLAG_HP_CYCLE_EOC (0x00000400) +#define ADC_FLAG_AWD_LOWER (0x00010000) +#define ADC_FLAG_AWD_UPPER (0x00020000) +#define ADC_FLAG_DATA_OVERWRITE (0x01000000) +#define ADC_FLAG_HP_DATA_OVERWRITE (0x02000000) + +#define IS_ADC_FLAG(FLAG) ((((FLAG) & 0xFCFCF8F8) == 0) && ((FLAG) != 0)) + + +#define ADC_REGULAR_DATA0 (0) +#define ADC_REGULAR_DATA1 (1) +#define ADC_REGULAR_DATA2 (2) +#define ADC_REGULAR_DATA3 (3) +#define ADC_REGULAR_DATA4 (4) +#define ADC_REGULAR_DATA5 (5) +#define ADC_REGULAR_DATA6 (6) +#define ADC_REGULAR_DATA7 (7) +#define ADC_REGULAR_DATA8 (8) +#define ADC_REGULAR_DATA9 (9) +#define ADC_REGULAR_DATA10 (10) +#define ADC_REGULAR_DATA11 (11) +#define ADC_REGULAR_DATA12 (12) +#define ADC_REGULAR_DATA13 (13) +#define ADC_REGULAR_DATA14 (14) +#define ADC_REGULAR_DATA15 (15) + +#define IS_ADC_REGULAR_DATA(DATA) ((DATA) < 16) + + +#define ADC_HP_DATA0 (0) +#define ADC_HP_DATA1 (1) +#define ADC_HP_DATA2 (2) +#define ADC_HP_DATA3 (3) + +#define IS_ADC_HP_DATA(DATA) ((DATA) < 4) + + +#define ADC_AWD_DISABLE (u8)0x00 +#define ADC_AWD_ALL_LOWER (u8)0x05 +#define ADC_AWD_ALL_UPPER (u8)0x06 +#define ADC_AWD_ALL_LOWER_UPPER (u8)0x07 +#define ADC_AWD_SINGLE_LOWER (u8)0x01 +#define ADC_AWD_SINGLE_UPPER (u8)0x02 +#define ADC_AWD_SINGLE_LOWER_UPPER (u8)0x03 + +#define IS_ADC_AWD(AWD) (((AWD) == ADC_AWD_DISABLE) || \ + ((AWD) == ADC_AWD_ALL_LOWER) || \ + ((AWD) == ADC_AWD_ALL_UPPER) || \ + ((AWD) == ADC_AWD_ALL_LOWER_UPPER) || \ + ((AWD) == ADC_AWD_SINGLE_LOWER) || \ + ((AWD) == ADC_AWD_SINGLE_UPPER) || \ + ((AWD) == ADC_AWD_SINGLE_LOWER_UPPER)) + +#define IS_ADC_THRESHOLD(THRESHOLD) ((THRESHOLD) < 4096) + +#define ADC_PDMA_REGULAR_SINGLE (0x00000001) +#define ADC_PDMA_REGULAR_SUBGROUP (0x00000002) +#define ADC_PDMA_REGULAR_CYCLE (0x00000004) + +#define ADC_PDMA_HP_SINGLE (0x00000100) +#define ADC_PDMA_HP_SUBGROUP (0x00000200) +#define ADC_PDMA_HP_CYCLE (0x00000400) + +#define IS_ADC_PDMA(PDMA) (((PDMA) == ADC_PDMA_REGULAR_SINGLE) || \ + ((PDMA) == ADC_PDMA_REGULAR_SUBGROUP) || \ + ((PDMA) == ADC_PDMA_REGULAR_CYCLE) || \ + ((PDMA) == ADC_PDMA_HP_SINGLE) || \ + ((PDMA) == ADC_PDMA_HP_SUBGROUP) || \ + ((PDMA) == ADC_PDMA_HP_CYCLE)) + + +#define IS_ADC_INPUT_SAMPLING_TIME(TIME) ((TIME) <= 255) + +#define IS_ADC_OFFSET(OFFSET) ((OFFSET) < 4096) + +#define IS_ADC_REGULAR_RANK(RANK) ((RANK) < 16) + +#define IS_ADC_HP_RANK(RANK) ((RANK) < 4) + +#define IS_ADC_REGULAR_LENGTH(LENGTH) (((LENGTH) >= 1) && ((LENGTH) <= 16)) +#define IS_ADC_REGULAR_SUB_LENGTH(SUB_LENGTH) (((SUB_LENGTH) >= 1) && ((SUB_LENGTH) <= 16)) + +#define IS_ADC_HP_LENGTH(LENGTH) (((LENGTH) >= 1) && ((LENGTH) <= 4)) +#define IS_ADC_HP_SUB_LENGTH(SUB_LENGTH) (((SUB_LENGTH) >= 1) && ((SUB_LENGTH) <= 4)) + +#define ADC_VREF_1V215 (0ul << 4) +#define ADC_VREF_2V0 (1ul << 4) +#define ADC_VREF_2V5 (2ul << 4) +#define ADC_VREF_2V7 (3ul << 4) + +#define IS_ADC_VREF_SEL(SEL) ((SEL == ADC_VREF_1V215) || \ + (SEL == ADC_VREF_2V0) || \ + (SEL == ADC_VREF_2V5) || \ + (SEL == ADC_VREF_2V7)) + +typedef enum +{ + ADC_ALIGN_RIGHT = (0 << 14), + ADC_ALIGN_LEFT = (1 << 14), +} ADC_ALIGN_Enum; + +#define IS_ADC_ALIGN(ALIGN) (((ALIGN) == ADC_ALIGN_RIGHT) || ((ALIGN) == ADC_ALIGN_LEFT)) +/** + * @} + */ + +/* Exported functions --------------------------------------------------------------------------------------*/ +/** @defgroup ADC_Exported_Functions ADC exported functions + * @{ + */ +void ADC_DeInit(HT_ADC_TypeDef* HT_ADCn); +void ADC_Reset(HT_ADC_TypeDef* HT_ADCn); +void ADC_Cmd(HT_ADC_TypeDef* HT_ADCn, ControlStatus NewState); + +void ADC_SamplingTimeConfig(HT_ADC_TypeDef* HT_ADCn, u8 SampleClock); // Apply for the specific model only +void ADC_RegularChannelConfig(HT_ADC_TypeDef* HT_ADCn, u8 ADC_CH_n, u8 Rank, u8 SampleClock); +void ADC_RegularGroupConfig(HT_ADC_TypeDef* HT_ADCn, u8 ADC_MODE, u8 Length, u8 SubLength); +void ADC_RegularTrigConfig(HT_ADC_TypeDef* HT_ADCn, u32 ADC_TRIG_x); + +void ADC_HPChannelConfig(HT_ADC_TypeDef* HT_ADCn, u8 ADC_CH_n, u8 Rank, u8 SampleClock); +void ADC_HPGroupConfig(HT_ADC_TypeDef* HT_ADCn, u8 ADC_MODE, u8 Length, u8 SubLength); +void ADC_HPTrigConfig(HT_ADC_TypeDef* HT_ADCn, u32 ADC_TRIG_x); + +void ADC_ChannelDataAlign(HT_ADC_TypeDef* HT_ADCn, u8 ADC_CH_n, ADC_ALIGN_Enum ADC_ALIGN_x); +void ADC_ChannelOffsetValue(HT_ADC_TypeDef* HT_ADCn, u8 ADC_CH_n, u16 OffsetValue); +void ADC_ChannelOffsetCmd(HT_ADC_TypeDef* HT_ADCn, u8 ADC_CH_n, ControlStatus NewState); + +void ADC_SoftwareStartConvCmd(HT_ADC_TypeDef* HT_ADCn, ControlStatus NewState); +void ADC_HPSoftwareStartConvCmd(HT_ADC_TypeDef* HT_ADCn, ControlStatus NewState); + +u16 ADC_GetConversionData(HT_ADC_TypeDef* HT_ADCn, u8 ADC_REGULAR_DATAn); +u16 ADC_GetHPConversionData(HT_ADC_TypeDef* HT_ADCn, u8 ADC_HP_DATAn); + +void ADC_IntConfig(HT_ADC_TypeDef* HT_ADCn, u32 ADC_INT_x, ControlStatus NewState); +FlagStatus ADC_GetIntStatus(HT_ADC_TypeDef* HT_ADCn, u32 ADC_INT_x); +void ADC_ClearIntPendingBit(HT_ADC_TypeDef* HT_ADCn, u32 ADC_INT_x); +FlagStatus ADC_GetFlagStatus(HT_ADC_TypeDef* HT_ADCn, u32 ADC_FLAG_x); + +void ADC_AWDConfig(HT_ADC_TypeDef* HT_ADCn, u32 ADC_AWD_x); +void ADC_AWDSingleChannelConfig(HT_ADC_TypeDef* HT_ADCn, u8 ADC_CH_n); +void ADC_AWDThresholdsConfig(HT_ADC_TypeDef* HT_ADCn, u16 UPPER, u16 LOWER); + +void ADC_PDMAConfig(HT_ADC_TypeDef* HT_ADCn, u32 ADC_PDMA_x, ControlStatus NewState); + +void ADC_VREFCmd(HT_ADC_TypeDef* HT_ADCn, ControlStatus NewState); +void ADC_VREFConfig(HT_ADC_TypeDef* HT_ADCn, u32 ADC_VREF_x); +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/inc/ht32f1xxxx_aes.h b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/inc/ht32f1xxxx_aes.h new file mode 100644 index 0000000000..176bf19e72 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/inc/ht32f1xxxx_aes.h @@ -0,0 +1,202 @@ +/*********************************************************************************************************//** + * @file ht32f1xxxx_aes.h + * @version $Rev:: 2022 $ + * @date $Date:: 2020-02-03 #$ + * @brief The header file of the ADC library. + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------------------------------------*/ +#ifndef __HT32F1XXXX_AES_H +#define __HT32F1XXXX_AES_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------------------------------------*/ +#include "ht32.h" + +/** @addtogroup HT32F1xxxx_Peripheral_Driver HT32F1xxxx Peripheral Driver + * @{ + */ + +/** @addtogroup AES + * @{ + */ + + +/* Exported types ------------------------------------------------------------------------------------------*/ +/** @defgroup AES_Exported_Types AES exported types + * @{ + */ + +/** + * @brief Definition of AES Init Structure + */ +typedef struct +{ + u16 AES_KeySize; + u16 AES_Dir; + u16 AES_Mode; + u16 AES_Swap; +} AES_InitTypeDef; +/** + * @} + */ + +/* Exported constants --------------------------------------------------------------------------------------*/ +/** @defgroup AES_Exported_Constants AES exported constants + * @{ + */ + +#define IS_AES(AES) (AES == HT_AES) + +/* Definitions of AES key size */ +#define AES_KEYSIZE_128B ((u32)0x00000000) +#define AES_KEYSIZE_192B ((u32)0x00000020) +#define AES_KEYSIZE_256B ((u32)0x00000040) + +#define IS_AES_KEY_SIZE(SIZE) ((SIZE == AES_KEYSIZE_128B) || (SIZE == AES_KEYSIZE_192B) || (SIZE == AES_KEYSIZE_256B)) + +/* Definitions of AES direction */ +typedef enum +{ + AES_DIR_ENCRYPT =0, + AES_DIR_DECRYPT =2 +} AES_DIR_Enum; + +#define IS_AES_DIR(DIR) ((DIR == AES_DIR_ENCRYPT) || (DIR == AES_DIR_DECRYPT)) + +/* Definitions of AES mode */ +#define AES_MODE_ECB ((u32)0x00000000) +#define AES_MODE_CBC ((u32)0x00000004) +#define AES_MODE_CTR ((u32)0x00000008) + +#define IS_AES_MODE(MODE) ((MODE == AES_MODE_ECB) || (MODE == AES_MODE_CBC) || (MODE == AES_MODE_CTR)) + +/* Definitions of AES key start */ +#define AES_KEYSTART_DISABLE ((u32)0x00000000) +#define AES_KEYSTART_ENABLE ((u32)0x00000010) + +#define IS_AES_KEYSTART(KEYSTART) ((KEYSTART == AES_KEYSTART_DISABLE) || (KEYSTART == AES_KEYSTART_ENABLE)) + +/* Definitions of AES swap */ +#define AES_SWAP_DISABLE ((u32)0x00000000) +#define AES_SWAP_ENABLE ((u32)0x00000100) + +#define IS_AES_SWAP(SWAP) ((SWAP == AES_SWAP_DISABLE) || (SWAP == AES_SWAP_ENABLE)) + +/* Definitions of AES flush */ +#define AES_FLUSH_DISABLE ((u32)0x00000000) +#define AES_FLUSH_ENABLE ((u32)0x00000400) + +#define IS_AES_FLUSH(FLUSH) ((FLUSH == AES_FLUSH_DISABLE) || (FLUSH == AES_FLUSH_ENABLE)) + +/* Definitions of AES Enable */ +#define AES_DISABLE ((u32)0x00000000) +#define AES_ENABLE ((u32)0x00000001) + +#define IS_AES_CMD(CMD) ((CMD == AES_DISABLE) || (CMD == AES_ENABLE)) + +/* Definitions of AES status */ +#define AES_SR_IFEMPTY ((u32)0x00000001) +#define AES_SR_IFNFULL ((u32)0x00000002) +#define AES_SR_OFNEMPTY ((u32)0x00000004) +#define AES_SR_OFFULL ((u32)0x00000008) +#define AES_SR_BUSY ((u32)0x00000010) + +#define IS_AES_STATUS(STATUS) ((STATUS == AES_SR_IFEMPTY) || \ + (STATUS == AES_SR_IFNFULL) || \ + (STATUS == AES_SR_OFNEMPTY) || \ + (STATUS == AES_SR_OFFULL) || \ + (STATUS == AES_SR_BUSY)) + +/* Definitions of AES PDMA */ +#define AES_PDMA_IFDMAEN ((u32)0x00000001) +#define AES_PDMA_OFDMAEN ((u32)0x00000002) + +#define IS_AES_PDMA(AES_PDMA) ((AES_PDMA == AES_PDMA_IFDMAEN) || (AES_PDMA == AES_PDMA_OFDMAEN)) + +/* Definitions of AES Interrupt Status */ +#define AES_INTSR_IFINT ((u32)0x00000001) +#define AES_INTSR_OFINT ((u32)0x00000002) + +#define IS_AES_INTSR(AES_INSR) ((AES_INSR == AES_INTSR_IFINT) || (AES_INSR == AES_INTSR_OFINT)) + +/* Definitions of AES interrupt enable */ +#define AES_IER_IFINTEN ((u32)0x00000001) +#define AES_IER_OFINTEN ((u32)0x00000002) + +#define IS_AES_IER(ARS_IER) ((ARS_IER == AES_IER_IFINTEN) || (ARS_IER == AES_IER_OFINTEN)) +/** + * @} + */ + +/* Exported functions --------------------------------------------------------------------------------------*/ +/** @defgroup AES_Exported_Functions AES exported functions + * @{ + */ +void AES_ECB_Init(HT_AES_TypeDef* HT_AESn, AES_InitTypeDef* AES_InitStruct); +void AES_CBC_Init(HT_AES_TypeDef* HT_AESn, AES_InitTypeDef* AES_InitStruct); +void AES_CTR_Init(HT_AES_TypeDef* HT_AESn, AES_InitTypeDef* AES_InitStruct); +void AES_SetKeyTable(HT_AES_TypeDef* HT_AESn, uc8* Key, u32 keySize); +ErrStatus _AES_CryptData(HT_AES_TypeDef* HT_AESn, AES_DIR_Enum dir, uc8 *iv, u32 length, uc8 *inputData, u8 *outputData); +#define AES_ECB_CryptData(a, b, c, d, e) _AES_CryptData(a, b, NULL, c, d, e) +#define AES_CBC_CryptData _AES_CryptData +#define AES_CTR_CryptData(a, b, c, d, e) _AES_CryptData(a, AES_DIR_ENCRYPT, b, c, d, e) +#if 0 +ErrStatus AES_ECB_CryptData(HT_AES_TypeDef* HT_AESn, AES_DIR_Enum mode, u32 length, uc8 *inputData, u8 *outputData); +ErrStatus AES_CBC_CryptData(HT_AES_TypeDef* HT_AESn, AES_DIR_Enum mode, uc8 *iv, u32 length, uc8 *inputData, u8 *outputData); +ErrStatus AES_CTR_CryptData(HT_AES_TypeDef* HT_AESn, uc8 *iv, u32 length, uc8 *inputData, u8 *outputData); +#endif + +void AES_StartKey(HT_AES_TypeDef* HT_AESn); +void AES_DeInit(HT_AES_TypeDef* HT_AESn); +void AES_FIFOFlush(HT_AES_TypeDef* HT_AESn); +void AES_Cmd(HT_AES_TypeDef* HT_AESn, ControlStatus NewState); +FlagStatus AES_GetStatus(HT_AES_TypeDef* HT_AESn, u32 AES_Status); +void AES_PDMACmd(HT_AES_TypeDef* HT_AESn, u32 AES_PDMA_xFDMAEN, ControlStatus NewState); +FlagStatus AES_GetIntStatus(HT_AES_TypeDef* HT_AESn, u32 AES_INTSR_x); +void AES_IntConfig(HT_AES_TypeDef* HT_AESn, u32 AES_IER_x, ControlStatus NewState); +void AES_SetInputData(HT_AES_TypeDef* HT_AESn, uc32 AES_Data); +u32 AES_GetOutputData(HT_AES_TypeDef* HT_AESn); +void AES_SetVectorTable(HT_AES_TypeDef* HT_AESn, uc8* Vector); +void AESCore_IRQHandler(HT_AES_TypeDef* HT_AESn); +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/inc/ht32f1xxxx_bftm.h b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/inc/ht32f1xxxx_bftm.h new file mode 100644 index 0000000000..091cc6dd77 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/inc/ht32f1xxxx_bftm.h @@ -0,0 +1,99 @@ +/*********************************************************************************************************//** + * @file ht32f1xxxx_bftm.h + * @version $Rev:: 2971 $ + * @date $Date:: 2023-10-25 #$ + * @brief The header file of the BFTM library. + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------------------------------------*/ +#ifndef __HT32F1XXXX_BFTM_H +#define __HT32F1XXXX_BFTM_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------------------------------------*/ +#include "ht32.h" + +/** @addtogroup HT32F1xxxx_Peripheral_Driver HT32F1xxxx Peripheral Driver + * @{ + */ + +/** @addtogroup BFTM + * @{ + */ + +/* Exported types ------------------------------------------------------------------------------------------*/ +/** @defgroup BFTM_Exported_Types BFTM exported types + * @{ + */ +typedef u32 BFTM_DataTypeDef; +/** + * @} + */ + +/* Exported constants --------------------------------------------------------------------------------------*/ +/** @defgroup BFTM_Exported_Constants BFTM exported constants + * @{ + */ +#define IS_BFTM(x) ((x == HT_BFTM0) || (x == HT_BFTM1)) + +#define BFTM_FLAG_MATCH (1UL << 0) +#define BFTM_INT_MATCH (1UL << 0) +/** + * @} + */ + +/* Exported functions --------------------------------------------------------------------------------------*/ +/** @defgroup BFTM_Exported_Functions BFTM exported functions + * @{ + */ +void BFTM_DeInit(HT_BFTM_TypeDef* HT_BFTMn); +void BFTM_EnaCmd(HT_BFTM_TypeDef* HT_BFTMn, ControlStatus NewState); +void BFTM_SetCompare(HT_BFTM_TypeDef* HT_BFTMn, BFTM_DataTypeDef uCompare); +u32 BFTM_GetCompare(HT_BFTM_TypeDef* HT_BFTMn); +void BFTM_SetCounter(HT_BFTM_TypeDef* HT_BFTMn, BFTM_DataTypeDef uCounter); +u32 BFTM_GetCounter(HT_BFTM_TypeDef* HT_BFTMn); +void BFTM_OneShotModeCmd(HT_BFTM_TypeDef* HT_BFTMn, ControlStatus NewState); +void BFTM_IntConfig(HT_BFTM_TypeDef* HT_BFTMn, ControlStatus NewState); +FlagStatus BFTM_GetFlagStatus(HT_BFTM_TypeDef* HT_BFTMn); +void BFTM_ClearFlag(HT_BFTM_TypeDef* HT_BFTMn); +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/inc/ht32f1xxxx_ckcu.h b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/inc/ht32f1xxxx_ckcu.h new file mode 100644 index 0000000000..11369ee4d0 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/inc/ht32f1xxxx_ckcu.h @@ -0,0 +1,734 @@ +/*********************************************************************************************************//** + * @file ht32f1xxxx_ckcu.h + * @version $Rev:: 2974 $ + * @date $Date:: 2023-10-30 #$ + * @brief The header file of the Clock Control Unit library. + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------------------------------------*/ +#ifndef __HT32F1XXXX_CKCU_H +#define __HT32F1XXXX_CKCU_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------------------------------------*/ +#include "ht32.h" + +/** @addtogroup HT32F1xxxx_Peripheral_Driver HT32F1xxxx Peripheral Driver + * @{ + */ + +/** @addtogroup CKCU + * @{ + */ + + +/* Exported types ------------------------------------------------------------------------------------------*/ +/** @defgroup CKCU_Exported_Types CKCU exported types + * @{ + */ + +/** + * @brief Enumeration of APB peripheral prescaler. + */ +typedef enum +{ + CKCU_APBCLKPRE_DIV1 = 0, + CKCU_APBCLKPRE_DIV2, + CKCU_APBCLKPRE_DIV4, + CKCU_APBCLKPRE_DIV8, + CKCU_APBCLKPRE_DIV16, + CKCU_APBCLKPRE_DIV32 +} CKCU_APBCLKPRE_TypeDef; + +/** + * @brief Enumeration of CK_REF prescaler. + */ +typedef enum +{ + CKCU_CKREFPRE_DIV2 = 0, + CKCU_CKREFPRE_DIV4, + CKCU_CKREFPRE_DIV6, + CKCU_CKREFPRE_DIV8, + CKCU_CKREFPRE_DIV10, + CKCU_CKREFPRE_DIV12, + CKCU_CKREFPRE_DIV14, + CKCU_CKREFPRE_DIV16, + CKCU_CKREFPRE_DIV18, + CKCU_CKREFPRE_DIV20, + CKCU_CKREFPRE_DIV22, + CKCU_CKREFPRE_DIV24, + CKCU_CKREFPRE_DIV26, + CKCU_CKREFPRE_DIV28, + CKCU_CKREFPRE_DIV30, + CKCU_CKREFPRE_DIV32, + CKCU_CKREFPRE_DIV34, + CKCU_CKREFPRE_DIV36, + CKCU_CKREFPRE_DIV38, + CKCU_CKREFPRE_DIV40, + CKCU_CKREFPRE_DIV42, + CKCU_CKREFPRE_DIV44, + CKCU_CKREFPRE_DIV46, + CKCU_CKREFPRE_DIV48, + CKCU_CKREFPRE_DIV50, + CKCU_CKREFPRE_DIV52, + CKCU_CKREFPRE_DIV54, + CKCU_CKREFPRE_DIV56, + CKCU_CKREFPRE_DIV58, + CKCU_CKREFPRE_DIV60, + CKCU_CKREFPRE_DIV62, + CKCU_CKREFPRE_DIV64 +} CKCU_CKREFPRE_TypeDef; + +/** + * @brief Enumeration of PLL clock source. + */ +typedef enum +{ + CKCU_PLLSRC_HSE = 0, + CKCU_PLLSRC_HSI +} CKCU_PLLSRC_TypeDef; + +#if (LIBCFG_CKCU_USART_PRESCALER) +/** + * @brief Enumeration of CK_USART prescaler. + */ +typedef enum +{ + CKCU_URPRE_DIV1 = 0, + CKCU_URPRE_DIV2 +} CKCU_URPRE_TypeDef; +#endif + +#if (!LIBCFG_NO_CKCU_USBPRE) +/** + * @brief Enumeration of CK_USB prescaler. + */ +typedef enum +{ + CKCU_USBPRE_DIV1 = 0, + CKCU_USBPRE_DIV2, +#if (LIBCFG_CKCU_USB_DIV3) + CKCU_USBPRE_DIV3 +#endif +} CKCU_USBPRE_TypeDef; +#endif + +#if (LIBCFG_CKCU_USB_PLL) +/** + * @brief Enumeration of CK_USB clock source. + */ +typedef enum +{ + CKCU_CKPLL = 0, + CKCU_CKUSBPLL +} CKCU_USBSRC_TypeDef; +#endif + +/** + * @brief Enumeration of WDT clock source. + */ +typedef enum +{ + CKCU_WDTSRC_LSI = 0, + CKCU_WDTSRC_LSE +} CKCU_WDTSRC_TypeDef; + + + +#if (!LIBCFG_CKCU_HSI_NO_AUTOTRIM) +/** + * @brief Enumeration of HSI auto-trim clock source. + */ +typedef enum +{ + CKCU_ATC_LSE = 0, + CKCU_ATC_USB = 1, +#if (LIBCFG_CKCU_AUTOTRIM_NOCKIN) +#else + CKCU_ATC_CKIN = 2, +#endif +} CKCU_ATC_TypeDef; + +#endif + +#if (LIBCFG_CKCU_ATM_V01) +/** + * @brief Enumeration of ATC search algorithm. + */ +typedef enum +{ + CKCU_ATC_BINARY_SEARCH = 0, + CKCU_ATC_LINEAR_SEARCH = 8 +} CKCU_ATCSearchAlgorithm_TypeDef; + +/** + * @brief Enumeration of ATC frequency tolerance. + */ +typedef enum +{ + CKCU_ATC_DOUBLE_PRECISION = 0, + CKCU_ATC_SINGLE_PRECISION = 4 +} CKCU_ATCFrqTolerance_TypeDef; +#endif + +/** + * @brief Enumeration of CK_AHB prescaler. + */ +typedef enum +{ + CKCU_SYSCLK_DIV1 = 0, + CKCU_SYSCLK_DIV2, + CKCU_SYSCLK_DIV4, + CKCU_SYSCLK_DIV8, +#if (LIBCFG_CKCU_SYSCLK_DIV8_ONLY) +#else + CKCU_SYSCLK_DIV16, + CKCU_SYSCLK_DIV32 +#endif +} CKCU_SYSCLKDIV_TypeDef; + +/** + * @brief Enumeration of CK_ADC prescaler. + */ +typedef enum +{ + #if (LIBCFG_CKCU_NO_ADCPRE_DIV1) + #else + CKCU_ADCPRE_DIV1 = 0, + #endif + CKCU_ADCPRE_DIV2 = 1, + CKCU_ADCPRE_DIV4, + CKCU_ADCPRE_DIV8, + CKCU_ADCPRE_DIV16, + CKCU_ADCPRE_DIV32, + CKCU_ADCPRE_DIV64, +#if (LIBCFG_CKCU_ADCPRE_DIV5) + CKCU_ADCPRE_DIV5 +#else + CKCU_ADCPRE_DIV6 +#endif +} CKCU_ADCPRE_TypeDef; + +/** + * @brief Enumeration of CK_ADCn. + */ +typedef enum +{ + CKCU_ADCPRE_ADC0 = 16, +} CKCU_ADCPRE_ADCn_TypeDef; + +/** + * @brief Enumeration of System clock source. + */ +typedef enum +{ + CKCU_SW_PLL = 1, + CKCU_SW_HSE = 2, + CKCU_SW_HSI = 3, +#if (LIBCFG_CKCU_NO_HCLK_LOW_SPEED) +#else + CKCU_SW_LSE = 6, + CKCU_SW_LSI = 7 +#endif +} CKCU_SW_TypeDef; + +/** + * @brief Enumeration of CKOUT clock source. + */ +typedef enum +{ + CKCU_CKOUTSRC_REFCK = 0, + CKCU_CKOUTSRC_HCLK_DIV16 = 1, + CKCU_CKOUTSRC_SYSCK_DIV16 = 2, + CKCU_CKOUTSRC_HSECK_DIV16 = 3, + CKCU_CKOUTSRC_HSICK_DIV16 = 4, + CKCU_CKOUTSRC_LSECK = 5, + CKCU_CKOUTSRC_LSICK = 6 +} CKCU_CKOUTSRC_TypeDef; + +/** + * @brief Enumeration of PLL clock source status. + */ +typedef enum +{ + CKCU_PLLST_SYSCK = 1, + CKCU_PLLST_USB = 4, + CKCU_PLLST_REFCK = 8 +} CKCU_PLLST_TypeDef; + +/** + * @brief Enumeration of HSI clock source status. + */ +typedef enum +{ + CKCU_HSIST_SYSCK = 1, + CKCU_HSIST_PLL = 2, + CKCU_HSIST_CKM = 4 +} CKCU_HSIST_TypeDef; + +/** + * @brief Enumeration of HSE clock source status. + */ +typedef enum +{ + CKCU_HSEST_SYSCK = 1, + CKCU_HSEST_PLL +} CKCU_HSEST_TypeDef; + +/** + * @brief Definition of CKOUT Init Structure. + */ +typedef struct +{ + CKCU_CKOUTSRC_TypeDef CKOUTSRC; +} CKCU_CKOUTInitTypeDef; + +/** + * @brief Definition of PLL Init Structure. + */ +typedef struct +{ + u32 CFG; + CKCU_PLLSRC_TypeDef ClockSource; + ControlStatus BYPASSCmd; +} CKCU_PLLInitTypeDef; + +/** + * @brief Definition of structure for clock frequency. + */ +typedef struct +{ + u32 PLL_Freq; + u32 SYSCK_Freq; + u32 HCLK_Freq; +#if (LIBCFG_CKCU_USART_PRESCALER) + u32 USART_Freq; +#endif + u32 ADC0_Freq; +} CKCU_ClocksTypeDef; + +#if (LIBCFG_CKCU_ATM_V01) +/** + * @brief Definition of ATC Init Structure. + */ +typedef struct +{ + CKCU_ATCSearchAlgorithm_TypeDef SearchAlgorithm; + CKCU_ATCFrqTolerance_TypeDef FrqTolerance; +} CKCU_ATCInitTypeDef; +#endif + +/** + * @brief Definition of initial structure of peripheral clock control. + */ +typedef union +{ + struct + { + /* Definitions of AHB clock control */ + unsigned long FMC :1; // Bit 0 + unsigned long :1; // Bit 1 + unsigned long SRAM :1; // Bit 2 + unsigned long :1; // Bit 3 + unsigned long PDMA :1; // Bit 4 + unsigned long BM :1; // Bit 5 + unsigned long APB0 :1; // Bit 6 + unsigned long APB1 :1; // Bit 7 + + unsigned long CSIF :1; // Bit 8 + unsigned long CSIFMCLK :1; // Bit 9 + unsigned long USBD :1; // Bit 10 + unsigned long CKREF :1; // Bit 11 + unsigned long EBI :1; // Bit 12 + unsigned long CRC :1; // Bit 13 + unsigned long SDIO :1; // Bit 14 + unsigned long AES :1; // Bit 15 + + unsigned long PA :1; // Bit 16 + unsigned long PB :1; // Bit 17 + unsigned long PC :1; // Bit 18 + unsigned long PD :1; // Bit 19 + unsigned long PE :1; // Bit 20 + unsigned long PF :1; // Bit 21 + unsigned long :1; // Bit 22 + unsigned long :1; // Bit 23 + + unsigned long :1; // Bit 24 + unsigned long :1; // Bit 25 + unsigned long :1; // Bit 26 + unsigned long :1; // Bit 27 + unsigned long :1; // Bit 28 + unsigned long :1; // Bit 29 + unsigned long :1; // Bit 30 + unsigned long :1; // Bit 31 + + /* Definitions of APB0 clock control */ + unsigned long I2C0 :1; // Bit 0 + unsigned long I2C1 :1; // Bit 1 + unsigned long :1; // Bit 2 + unsigned long :1; // Bit 3 + unsigned long SPI0 :1; // Bit 4 + unsigned long SPI1 :1; // Bit 5 + unsigned long :1; // Bit 6 + unsigned long :1; // Bit 7 + + unsigned long USART0 :1; // Bit 8 + unsigned long USART1 :1; // Bit 9 + unsigned long UART0 :1; // Bit 10 + unsigned long UART1 :1; // Bit 11 + unsigned long :1; // Bit 12 + unsigned long :1; // Bit 13 + unsigned long AFIO :1; // Bit 14 + unsigned long EXTI :1; // Bit 15 + + unsigned long :1; // Bit 16 + unsigned long :1; // Bit 17 + unsigned long :1; // Bit 18 + unsigned long :1; // Bit 19 + unsigned long :1; // Bit 20 + unsigned long :1; // Bit 21 + unsigned long :1; // Bit 22 + unsigned long :1; // Bit 23 + + unsigned long SCI0 :1; // Bit 24 + unsigned long I2S :1; // Bit 25 + unsigned long :1; // Bit 26 + unsigned long SCI1 :1; // Bit 27 + unsigned long :1; // Bit 28 + unsigned long :1; // Bit 29 + unsigned long :1; // Bit 30 + unsigned long :1; // Bit 31 + + /* Definitions of APB1 clock control */ + unsigned long MCTM0 :1; // Bit 0 + unsigned long MCTM1 :1; // Bit 1 + unsigned long :1; // Bit 2 + unsigned long :1; // Bit 3 + unsigned long WDT :1; // Bit 4 + unsigned long :1; // Bit 5 + unsigned long BKP :1; // Bit 6 + unsigned long :1; // Bit 7 + + unsigned long GPTM0 :1; // Bit 8 + unsigned long GPTM1 :1; // Bit 9 + unsigned long :1; // Bit 10 + unsigned long :1; // Bit 11 + unsigned long PWM0 :1; // Bit 12 + unsigned long :1; // Bit 13 + unsigned long :1; // Bit 14 + unsigned long :1; // Bit 15 + + unsigned long BFTM0 :1; // Bit 16 + unsigned long BFTM1 :1; // Bit 17 + unsigned long :1; // Bit 18 + unsigned long :1; // Bit 19 + unsigned long :1; // Bit 20 + unsigned long :1; // Bit 21 +#if (LIBCFG_CMP_OPA) + unsigned long OPA0 :1; // Bit 22 +#else + unsigned long CMP :1; // Bit 22 +#endif + unsigned long OPA1 :1; // Bit 23 + + unsigned long ADC0 :1; // Bit 24 + unsigned long :1; // Bit 25 + unsigned long :1; // Bit 26 + unsigned long :1; // Bit 27 + unsigned long SCTM0 :1; // Bit 28 + unsigned long SCTM1 :1; // Bit 29 + unsigned long :1; // Bit 30 + unsigned long :1; // Bit 31 + } Bit; + u32 Reg[3]; +} CKCU_PeripClockConfig_TypeDef; + +#define CKCU_APBPCSR_OFFSET (5) +#define CKCU_APBPCSR0 (0 << CKCU_APBPCSR_OFFSET) +#define CKCU_APBPCSR1 (1 << CKCU_APBPCSR_OFFSET) +#define CKCU_APBPCSR2 (4 << CKCU_APBPCSR_OFFSET) +typedef enum +{ + CKCU_PCLK_I2C0 = (CKCU_APBPCSR0 | 0), + CKCU_PCLK_I2C1 = (CKCU_APBPCSR0 | 2), + CKCU_PCLK_SPI0 = (CKCU_APBPCSR0 | 4), + CKCU_PCLK_SPI1 = (CKCU_APBPCSR0 | 6), + CKCU_PCLK_BFTM0 = (CKCU_APBPCSR0 | 12), + CKCU_PCLK_BFTM1 = (CKCU_APBPCSR0 | 14), + CKCU_PCLK_MCTM0 = (CKCU_APBPCSR0 | 16), + CKCU_PCLK_MCTM1 = (CKCU_APBPCSR0 | 18), + CKCU_PCLK_GPTM0 = (CKCU_APBPCSR0 | 20), + CKCU_PCLK_GPTM1 = (CKCU_APBPCSR0 | 22), + CKCU_PCLK_USART0 = (CKCU_APBPCSR0 | 24), + CKCU_PCLK_USART1 = (CKCU_APBPCSR0 | 26), + CKCU_PCLK_UART0 = (CKCU_APBPCSR0 | 28), + CKCU_PCLK_UART1 = (CKCU_APBPCSR0 | 30), + CKCU_PCLK_AFIO = (CKCU_APBPCSR1 | 0), + CKCU_PCLK_EXTI = (CKCU_APBPCSR1 | 2), + CKCU_PCLK_ADC = (CKCU_APBPCSR1 | 4), + CKCU_PCLK_CMP = (CKCU_APBPCSR1 | 8), + CKCU_PCLK_WDTR = (CKCU_APBPCSR1 | 12), + CKCU_PCLK_BKPR = (CKCU_APBPCSR1 | 14), +#if (LIBCFG_SCI0) + CKCU_PCLK_SCI0 = (CKCU_APBPCSR1 | 16), +#endif +#if (LIBCFG_SCI1) + CKCU_PCLK_SCI1 = (CKCU_APBPCSR1 | 18), +#endif + CKCU_PCLK_I2S = (CKCU_APBPCSR1 | 20), + CKCU_PCLK_SCTM0 = (CKCU_APBPCSR1 | 24), + CKCU_PCLK_SCTM1 = (CKCU_APBPCSR1 | 26), + CKCU_PCLK_PWM0 = (CKCU_APBPCSR2 | 16), +} CKCU_PeripPrescaler_TypeDef; + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------------------------------------*/ +/** @defgroup CKCU_Exported_Constants CKCU exported constants + * @{ + */ + +/* Definitions of clock ready flag */ +#define CKCU_FLAG_PLLRDY (1UL << 1) +#define CKCU_FLAG_HSERDY (1UL << 2) +#define CKCU_FLAG_HSIRDY (1UL << 3) +#define CKCU_FLAG_LSERDY (1UL << 4) +#define CKCU_FLAG_LSIRDY (1UL << 5) +#if (LIBCFG_CKCU_USB_PLL) +#define CKCU_FLAG_USBPLLRDY (1UL) +#define IS_CKCU_FLAG(FLAG) (((FLAG & 0xFFFFFFC0) == 0) && (FLAG != 0)) +#else +#define IS_CKCU_FLAG(FLAG) (((FLAG & 0xFFFFFFC1) == 0) && (FLAG != 0)) +#endif +/* Definitions of clock interrupt & flag */ +#define CKCU_INT_CKS (1UL) +#define CKCU_INT_PLLRDY (1UL << 2) +#define CKCU_INT_HSERDY (1UL << 3) +#define CKCU_INT_HSIRDY (1UL << 4) +#define CKCU_INT_LSERDY (1UL << 5) +#define CKCU_INT_LSIRDY (1UL << 6) + +#if (LIBCFG_CKCU_USB_PLL) +#define CKCU_INT_USBPLLRDY (1UL << 1) +#define IS_CKCU_INT_FLAG(FLAG) (((FLAG & 0xFFFFFF80) == 0) && (FLAG != 0)) +#else +#define IS_CKCU_INT_FLAG(FLAG) (((FLAG & 0xFFFFFF82) == 0) && (FLAG != 0)) +#endif + +#define CKCU_INT_CKSIE (1UL << 16) +#if (LIBCFG_CKCU_USB_PLL) +#define CKCU_INT_USBPLLRDYIE (1UL << 17) +#endif +#define CKCU_INT_PLLRDYIE (1UL << 18) +#define CKCU_INT_HSERDYIE (1UL << 19) +#define CKCU_INT_HSIRDYIE (1UL << 20) +#define CKCU_INT_LSERDYIE (1UL << 21) +#define CKCU_INT_LSIRDYIE (1UL << 22) + +#if (LIBCFG_CKCU_USB_PLL) +#define IS_CKCU_INT(IT) (((IT & 0xFF80FFFF) == 0) && (IT != 0)) +#else +#define IS_CKCU_INT(IT) (((IT & 0xFF82FFFF) == 0) && (IT != 0)) +#endif + +#define IS_PLL_CLKSRC(SRC) ((SRC == CKCU_PLLSRC_HSE) || \ + (SRC == CKCU_PLLSRC_HSI)) + +/* Definitions of PLL frequency */ +#if (LIBCDG_CKCU_PLL_144M) +#define CKCU_PLL_4M_144M ((36UL << 23) | (0UL << 21)) +#define CKCU_PLL_8M_144M ((18UL << 23) | (0UL << 21)) +#define CKCU_PLL_12M_144M ((12UL << 23) | (0UL << 21)) +#define CKCU_PLL_16M_144M (( 9UL << 23) | (0UL << 21)) +#endif + +#define CKCU_PLL_4M_48M ((12UL << 23) | (0UL << 21)) +#define CKCU_PLL_4M_72M ((18UL << 23) | (0UL << 21)) +#define CKCU_PLL_4M_96M ((24UL << 23) | (0UL << 21)) +#define CKCU_PLL_8M_48M (( 6UL << 23) | (0UL << 21)) +#define CKCU_PLL_8M_64M (( 8UL << 23) | (0UL << 21)) +#define CKCU_PLL_8M_72M (( 9UL << 23) | (0UL << 21)) +#define CKCU_PLL_8M_80M ((10UL << 23) | (0UL << 21)) +#define CKCU_PLL_8M_96M ((12UL << 23) | (0UL << 21)) +#define CKCU_PLL_12M_48M (( 4UL << 23) | (0UL << 21)) +#define CKCU_PLL_12M_72M (( 6UL << 23) | (0UL << 21)) +#define CKCU_PLL_12M_96M (( 8UL << 23) | (0UL << 21)) +#define CKCU_PLL_16M_80M (( 5UL << 23) | (0UL << 21)) +#define CKCU_PLL_16M_96M (( 6UL << 23) | (0UL << 21)) + +#if (LIBCDG_CKCU_PLL_144M) +#define IS_PLL_CFG(CFG) (((CFG & 0xE01FFFFF) == 0x0)) +#else +#define IS_PLL_CFG(CFG) (((CFG & 0xF01FFFFF) == 0x0)) +#endif + +#if (LIBCFG_CKCU_USB_PLL) +/* Definitions of USBPLL frequency */ +#define CKCU_USBPLL_4M_48M ((12UL << 7) | (0UL << 5)) +#define CKCU_USBPLL_8M_48M (( 6UL << 7) | (0UL << 5)) +#define CKCU_USBPLL_12M_48M (( 4UL << 7) | (0UL << 5)) +#define CKCU_USBPLL_16M_48M (( 3UL << 7) | (0UL << 5)) + +#define IS_USBPLL_CFG(CFG) (((CFG & 0xFFFFF81F) == 0x0)) +#endif + +/* Definitions of MCU debug control */ +#define CKCU_DBG_SLEEP (1UL) +#define CKCU_DBG_DEEPSLEEP1 (1UL << 1) +#define CKCU_DBG_POWERDOWN (1UL << 2) +#define CKCU_DBG_WDT_HALT (1UL << 3) +#define CKCU_DBG_MCTM0_HALT (1UL << 4) +#define CKCU_DBG_MCTM1_HALT (1UL << 5) +#define CKCU_DBG_GPTM0_HALT (1UL << 6) +#define CKCU_DBG_GPTM1_HALT (1UL << 7) +#define CKCU_DBG_USART0_HALT (1UL << 8) +#define CKCU_DBG_USART1_HALT (1UL << 9) +#define CKCU_DBG_SPI0_HALT (1UL << 10) +#define CKCU_DBG_SPI1_HALT (1UL << 11) +#define CKCU_DBG_I2C0_HALT (1UL << 12) +#define CKCU_DBG_I2C1_HALT (1UL << 13) +#define CKCU_DBG_DEEPSLEEP2 (1UL << 14) +#define CKCU_DBG_SCI_HALT (1UL << 15) +#define CKCU_DBG_BFTM0_HALT (1UL << 16) +#define CKCU_DBG_BFTM1_HALT (1UL << 17) +#define CKCU_DBG_UART0_HALT (1UL << 18) +#define CKCU_DBG_UART1_HALT (1UL << 19) +#define CKCU_DBG_TRACE_ON (1UL << 20) + +#if (LIBCFG_SCI0) +#define CKCU_DBG_SCI0_HALT (1UL << 15) +#endif +#if (LIBCFG_SCI1) +#define CKCU_DBG_SCI1_HALT (1UL << 21) +#endif + +#define IS_CKCU_DBG(MODE) (((MODE & 0xBF200000) == 0) && (MODE != 0)) + +/* Definitions of AHB clock control */ +#define CKCU_AHBEN_SLEEP_FMC (1UL) +#define CKCU_AHBEN_SLEEP_SRAM (1UL << 2) +#define CKCU_AHBEN_SLEEP_BM (1UL << 5) +#define CKCU_AHBEN_SLEEP_APB0 (1UL << 6) +#define CKCU_AHBEN_SLEEP_APB1 (1UL << 7) + +#define IS_CKCU_SLEEP_AHB(PERIPH) (((PERIPH & 0xFFFFFF1A) == 0) && (PERIPH != 0)) + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------------------------------------*/ +/** @defgroup CKCU_Exported_Functions CKCU exported functions + * @{ + */ +void CKCU_DeInit(void); + +void CKCU_HSICmd(ControlStatus Cmd); +void CKCU_HSECmd(ControlStatus Cmd); +bool CKCU_IS_HSI_USED(CKCU_HSIST_TypeDef Target); +bool CKCU_IS_HSE_USED(CKCU_HSEST_TypeDef Target); +FlagStatus CKCU_GetClockReadyStatus(u32 CKCU_FLAG); +ErrStatus CKCU_WaitHSEReady(void); + +ErrStatus CKCU_SysClockConfig(CKCU_SW_TypeDef CLKSRC); +u32 CKCU_GetSysClockSource(void); + +void CKCU_PeripClockConfig(CKCU_PeripClockConfig_TypeDef Clock, ControlStatus Cmd); + +void CKCU_PLLInit(CKCU_PLLInitTypeDef *PLL_InitStruct); +void CKCU_PLLCmd(ControlStatus Cmd); +bool CKCU_IS_PLL_USED(CKCU_PLLST_TypeDef Target); + +#if (LIBCFG_CKCU_USB_PLL) +void CKCU_USBPLLInit(CKCU_PLLInitTypeDef *USBPLL_InitStruct); +void CKCU_USBPLLCmd(ControlStatus Cmd); +void CKCU_USBClockConfig(CKCU_USBSRC_TypeDef USBSRC); +#endif + +void CKCU_SleepClockConfig(u32 CKCU_CLK, ControlStatus Cmd); + +void CKCU_SetHCLKPrescaler(CKCU_SYSCLKDIV_TypeDef HCLKPRE); +void CKCU_SetCKREFPrescaler(CKCU_CKREFPRE_TypeDef CKREFPRE); +void CKCU_SetADCnPrescaler(CKCU_ADCPRE_ADCn_TypeDef CKCU_ADCPRE_ADCn, CKCU_ADCPRE_TypeDef CKCU_ADCPRE_DIVn); +#define CKCU_SetADCPrescaler(DIV) CKCU_SetADCnPrescaler(CKCU_ADCPRE_ADC0, DIV) + +#if (LIBCFG_CKCU_USART_PRESCALER) +void CKCU_SetUSARTPrescaler(CKCU_URPRE_TypeDef URPRE); +#endif + +#if (!LIBCFG_NO_CKCU_USBPRE) +void CKCU_SetUSBPrescaler(CKCU_USBPRE_TypeDef USBPRE); +#endif + +#if (LIBCFG_CKCU_NO_APB_PRESCALER) +#else +void CKCU_SetPeripPrescaler(CKCU_PeripPrescaler_TypeDef Perip, CKCU_APBCLKPRE_TypeDef PCLKPRE); +#endif + +void CKCU_GetClocksFrequency(CKCU_ClocksTypeDef* CKCU_Clk); +u32 CKCU_GetPLLFrequency(void); +u32 CKCU_GetPeripFrequency(CKCU_PeripPrescaler_TypeDef Perip); + +void CKCU_CKMCmd(ControlStatus Cmd); +void CKCU_PSRCWKUPCmd(ControlStatus Cmd); +void CKCU_BKISOCmd(ControlStatus Cmd); +void CKCU_CKOUTConfig(CKCU_CKOUTInitTypeDef *CKOUTInit); +void CKCU_MCUDBGConfig(u32 CKCU_DBGx, ControlStatus Cmd); + +void CKCU_IntConfig(u32 CKCU_INT, ControlStatus Cmd); +FlagStatus CKCU_GetIntStatus(u32 CKCU_INT); +void CKCU_ClearIntFlag(u32 CKCU_INT); + +#if (!LIBCFG_CKCU_HSI_NO_AUTOTRIM) +#if (LIBCFG_CKCU_ATM_V01) +void CKCU_ATCInit(CKCU_ATCInitTypeDef* ATC_InitStruct); +void CKCU_HSIAutoTrimAlgorithm(u32 Algo); +void CKCU_HSIAutoTrimFreqTolerance(u32 Tolerance); +#endif +void CKCU_HSIAutoTrimClkConfig(CKCU_ATC_TypeDef CLKSRC); +void CKCU_HSIAutoTrimCmd(ControlStatus Cmd); +bool CKCU_HSIAutoTrimIsReady(void); +#endif +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/inc/ht32f1xxxx_cmp.h b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/inc/ht32f1xxxx_cmp.h new file mode 100644 index 0000000000..7650247fb4 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/inc/ht32f1xxxx_cmp.h @@ -0,0 +1,230 @@ +/*********************************************************************************************************//** + * @file ht32f1xxxx_cmp.h + * @version $Rev:: 2971 $ + * @date $Date:: 2023-10-25 #$ + * @brief The header file of the CMP library. + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------------------------------------*/ +#ifndef __HT32F1XXXX_CMP_H +#define __HT32F1XXXX_CMP_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------------------------------------*/ +#include "ht32.h" + +/** @addtogroup HT32F1xxxx_Peripheral_Driver HT32F1xxxx Peripheral Driver + * @{ + */ + +/** @addtogroup CMP + * @{ + */ + + +/* Exported types ------------------------------------------------------------------------------------------*/ +/** @defgroup CMP_Exported_Types CMP exported types + * @{ + */ + +typedef struct +{ + u32 CMP_Wakeup; + u32 CMP_OutputSelection; + u32 CMP_ScalerSource; + u32 CMP_ScalerOutputBuf; + u32 CMP_ScalerEnable; + u32 CMP_CoutSync; + u32 CMP_OutputPol; + u32 CMP_InvInputSelection; + u32 CMP_Hysteresis; + u32 CMP_Speed; +} CMP_InitTypeDef; + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------------------------------------*/ +/** @defgroup CMP_Exported_Constants CMP exported constants + * @{ + */ + +/* Definitions of CMP Protection Key */ +#define CMP_PROTECT_KEY ((u32)0x9C3A0000) + + +/* Definitions of CMP Output Status */ +#define CMP_OUTPUT_HIGH ((u32)0x00008000) +#define CMP_OUTPUT_LOW ((u32)0x00000000) + + +/* Definitions of CMP Wakeup Control Bit */ +#define CMP_WUP_ENABLE ((u32)0x00004000) +#define CMP_WUP_DISABLE ((u32)0x00000000) + +#define IS_CMP_Wakeup_Set(x) ((x == CMP_WUP_ENABLE) || (x == CMP_WUP_DISABLE)) + + +/* Definitions of CMP Output Selection for IP Trigger Source */ +#define CMP_TRIG_NONE ((u32)0x00000000) +#define CMP_TRIG_GPTM_CH3 ((u32)0x00000800) +#define CMP_TRIG_MCTM_CH3 ((u32)0x00001000) +#define CMP_TRIG_MCTM_BK1 ((u32)0x00001800) +#define CMP_TRIG_ADC ((u32)0x00002000) + +#define IS_CMP_OutputSelection(x) ((x == CMP_TRIG_NONE) || (x == CMP_TRIG_GPTM_CH3) || (x == CMP_TRIG_MCTM_CH3) || \ + (x == CMP_TRIG_MCTM_BK1) || (x == CMP_TRIG_ADC)) + +/* Definitions of CMP Scaler Source Selection */ +#define CMP_SCALER_SRC_VDDA ((u32)0x00000000) +#define CMP_SCALER_SRC_VREF ((u32)0x00000400) + +#define IS_CMP_ScalerSource(x) ((x == CMP_SCALER_SRC_VDDA) || (x == CMP_SCALER_SRC_VREF)) + + +/* Definitions of CMP Scaler Output Enable Bit */ +#define CMP_SCALER_OBUF_DISABLE ((u32)0x00000000) +#define CMP_SCALER_OBUF_ENABLE ((u32)0x00000200) + +#define IS_CMP_ScalerOutputBuf(x) ((x == CMP_SCALER_OBUF_DISABLE) || (x == CMP_SCALER_OBUF_ENABLE)) + + +/* Definitions of CMP Scaler Enable Bit */ +#define CMP_SCALER_DISABLE ((u32)0x00000000) +#define CMP_SCALER_ENABLE ((u32)0x00000100) + +#define IS_CMP_ScalerEnable(x) ((x == CMP_SCALER_DISABLE) || (x == CMP_SCALER_ENABLE)) + + +/* Definitions of CMP Sync Output Enable bit */ +#define CMP_ASYNC_OUTPUT ((u32)0x00000000) +#define CMP_SYNC_OUTPUT ((u32)0x00000080) + +#define IS_CMP_CoutSynchronized(x) ((x == CMP_ASYNC_OUTPUT) || (x == CMP_SYNC_OUTPUT)) + + +/* Definitions of CMP Output Polarity Selection */ +#define CMP_NONINV_OUTPUT ((u32)0x00000000) +#define CMP_INV_OUTPUT ((u32)0x00000040) + +#define IS_CMP_OutputPol_Set(x) ((x == CMP_NONINV_OUTPUT) || (x == CMP_INV_OUTPUT)) + + +/* Definitions of CMP Inverted Input Source Selection */ +#define CMP_EXTERNAL_CN_IN ((u32)0x00000000) +#define CMP_SCALER_CN_IN ((u32)0x00000010) + +#define IS_CMP_InvInputSelection(x) ((x == CMP_EXTERNAL_CN_IN) || (x == CMP_SCALER_CN_IN)) + + +/* Definitions of CMP Hysteresis Level Selection */ +#define CMP_NO_HYSTERESIS ((u32)0x00000000) +#define CMP_LOW_HYSTERESIS ((u32)0x00000004) +#define CMP_MID_HYSTERESIS ((u32)0x00000008) +#define CMP_HIGH_HYSTERESIS ((u32)0x0000000C) + +#define IS_CMP_Hysteresis_Set(x) ((x == CMP_NO_HYSTERESIS) || (x == CMP_LOW_HYSTERESIS) || (x == CMP_MID_HYSTERESIS) || \ + (x == CMP_HIGH_HYSTERESIS)) + +/* Definitions of CMP Speed Mode Selection */ +#define CMP_HIGH_SPEED ((u32)0x00000002) +#define CMP_LOW_SPEED ((u32)0x00000000) + +#define IS_CMP_Speed_Set(x) ((x == CMP_HIGH_SPEED) || (x == CMP_LOW_SPEED)) + + +/* Definitions of CMP Enable bit */ +#define CMP_ENABLE ((u32)0x00000001) + + +/* Definitions of CMP Output Edge Interrupt Enable bit */ +#define CMP_INT_RE ((u32)0x00000002) +#define CMP_INT_FE ((u32)0x00000001) + +/* Check the CMP Interrupt Parameter */ +#define IS_CMP_INT(x) ((x & 0xFFFFFF00) != 0x0) + + +/* Definitions of CMP Output Edge Detection Enable bit */ +#define CMP_RE_Detect ((u32)0x00000200) +#define CMP_FE_Detect ((u32)0x00000100) + +#define IS_CMP_EdgeDetect(x) ((x == CMP_RE_Detect) || (x == CMP_FE_Detect)) + + +/* Definitions of CMP Output Edge Flag */ +#define CMP_FLAG_RE ((u32)0x00000002) +#define CMP_FLAG_FE ((u32)0x00000001) + +/* Check the CMP flag Parameter */ +#define IS_CMP_FLAG(x) ((x & 0xFFFFFF00) != 0x0) + + +/* Check the CMPx Parameter */ +#define IS_CMP(x) ((x == HT_CMP0) || (x == HT_CMP1)) + + +/* Check the Scaler Value */ +#define IS_SCALER_VALUE(x) (x <= 0x3F) + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------------------------------------*/ +/** @defgroup CMP_Exported_Functions CMP exported functions + * @{ + */ +void CMP_DeInit(HT_CMP_TypeDef* HT_CMPn); +void CMP_UnprotectConfig(HT_CMP_TypeDef* HT_CMPn); +void CMP_Init(HT_CMP_TypeDef* HT_CMPn, CMP_InitTypeDef* CMP_InitStruct); +void CMP_StructInit(CMP_InitTypeDef* CMP_InitStruct); +void CMP_Cmd(HT_CMP_TypeDef* HT_CMPn, ControlStatus NewState); +void CMP_IntConfig(HT_CMP_TypeDef* HT_CMPn, u32 CMP_INT_x, ControlStatus NewState); +void CMP_EdgeDetectConfig(HT_CMP_TypeDef* HT_CMPn, u32 CMP_xE_Detect, ControlStatus NewState); +FlagStatus CMP_GetFlagStatus(HT_CMP_TypeDef* HT_CMPn, u32 CMP_FLAG_x); +void CMP_ClearFlag(HT_CMP_TypeDef* HT_CMPn, u32 CMP_FLAG_x); +FlagStatus CMP_GetOutputStatus(HT_CMP_TypeDef* HT_CMPn); +void CMP_SetScalerValue(HT_CMP_TypeDef* HT_CMPn, u8 Scaler_Value); +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/inc/ht32f1xxxx_cmp_op.h b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/inc/ht32f1xxxx_cmp_op.h new file mode 100644 index 0000000000..bcfb5d82ff --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/inc/ht32f1xxxx_cmp_op.h @@ -0,0 +1,124 @@ +/*********************************************************************************************************//** + * @file ht32f1xxxx_cmp_op.h + * @version $Rev:: 122 $ + * @date $Date:: 2017-06-13 #$ + * @brief The header file of the CMP_OP library. + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------------------------------------*/ +#ifndef __HT32F1XXXX_CMP_OP_H +#define __HT32F1XXXX_CMP_OP_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------------------------------------*/ +#include "ht32.h" + +/** @addtogroup HT32F1xxxx_Peripheral_Driver HT32F1xxxx Peripheral Driver + * @{ + */ + +/** @addtogroup CMP_OP + * @{ + */ + + +/* Exported constants --------------------------------------------------------------------------------------*/ +/** @defgroup CMP_OP_Exported_Constants CMP_OP exported constants + * @{ + */ + +/* Definitions of CMP_OP modes */ +#define OP_MODE (0x00000000ul) +#define CMP_MODE (0x00000002ul) + +#define IS_CMP_OP_MODE(MODE) ((MODE == OP_MODE) || (MODE == CMP_MODE)) + +/* Definitions the cancelation reference input of CMP_OP */ +#define CMP_OP_NEGATIVE_INPUT (0x00000000ul) +#define CMP_OP_POSITIVE_INPUT (0x00000008ul) + +#define IS_CMP_OP_REF(REF) ((REF == CMP_OP_NEGATIVE_INPUT ) || (REF == CMP_OP_POSITIVE_INPUT)) + +/* Definitions of CMP_OP input offset */ +#define CMP_OP_IOVC_MIN (0x00000000ul) +#define CMP_OP_IOVC_CENTER (0x00000020ul) +#define CMP_OP_IOVC_MAX (0x0000003Ful) + +#define IS_CMP_OP_IOVC(IOVC) (IOVC <= 63 ) + +/* Definitions of CMP_OP interrupts */ +#define CMP_OP_INT_FALLING (0x00000001ul) +#define CMP_OP_INT_RISING (0x00000002ul) + +#define IS_CMP_OP_INT(CMP_OP_INT) (((CMP_OP_INT & 0xFFFFFFFC) == 0x0) && \ + (CMP_OP_INT != 0x0)) + +/* Definitions of CMP_OP interrupt flags */ +#define CMP_OP_FLAG_FALLING (0x00000001ul) +#define CMP_OP_FLAG_RISING (0x00000002ul) + +#define IS_CMP_OP_FLAG(FLAG) (((FLAG & 0xFFFFFFFC) == 0x0) && \ + (FLAG != 0x0)) + +/* check parameter of the CMP_OPx */ +#define IS_CMP_OP_ALL_PERIPH(PERIPH) ((PERIPH == HT_CMP_OP0) || (PERIPH == HT_CMP_OP1)) +/** + * @} + */ + +/* Exported functions --------------------------------------------------------------------------------------*/ +/** @defgroup CMP_OP_Exported_Functions CMP_OP exported functions + * @{ + */ +void CMP_OP_DeInit(HT_CMP_OP_TypeDef* CMP_OPx); +void CMP_OP_Config(HT_CMP_OP_TypeDef* CMP_OPx, u32 mode, u32 cancellation); +void CMP_OP_Cmd(HT_CMP_OP_TypeDef* CMP_OPx, ControlStatus NewState); +void CMP_OP_CancellationModeConfig(HT_CMP_OP_TypeDef* CMP_OPx, u16 CMP_OP_REF_INPUT); +void CMP_OP_SetCancellationVaule(HT_CMP_OP_TypeDef* CMP_OPx, u32 cancellation); +u32 CMP_OP_GetCancellationVaule(HT_CMP_OP_TypeDef* CMP_OPx); +void CMP_OP_IntConfig(HT_CMP_OP_TypeDef* CMP_OPx, u32 CMP_OP_INT, ControlStatus NewState); +FlagStatus CMP_OP_GetIntStatus(HT_CMP_OP_TypeDef* CMP_OPx, u32 CMP_OP_INT); +FlagStatus CMP_OP_GetFlagStatus(HT_CMP_OP_TypeDef* CMP_OPx, u32 CMP_OP_FLAG); +void CMP_OP_ClearIntPendingBit(HT_CMP_OP_TypeDef* CMP_OPx, u32 CMP_OP_INT); +FlagStatus CMP_OP_GetOutputStatus(HT_CMP_OP_TypeDef* CMP_OPx); +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/inc/ht32f1xxxx_crc.h b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/inc/ht32f1xxxx_crc.h new file mode 100644 index 0000000000..0247ced9ca --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/inc/ht32f1xxxx_crc.h @@ -0,0 +1,124 @@ +/*********************************************************************************************************//** + * @file ht32f1xxxx_crc.h + * @version $Rev:: 2787 $ + * @date $Date:: 2022-11-23 #$ + * @brief The header file of the CRC library. + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------------------------------------*/ +#ifndef __HT32F1XXXX_CRC_H +#define __HT32F1XXXX_CRC_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------------------------------------*/ +#include "ht32.h" + +/** @addtogroup HT32F1xxxx_Peripheral_Driver HT32F1xxxx Peripheral Driver + * @{ + */ + +/** @addtogroup CRC + * @{ + */ + + +/* Exported types ------------------------------------------------------------------------------------------*/ +/** @defgroup CRC_Exported_Types CRC exported types + * @{ + */ + +/* Definition of CRC Init Structure */ +typedef enum +{ + CRC_CCITT_POLY = 0, + CRC_16_POLY = 1, + CRC_32_POLY = 2, + CRC_USER_DEFINE = 0xF +} CRC_Mode; + +typedef struct +{ + CRC_Mode Mode; + u32 uSeed; + u32 uCR; +} CRC_InitTypeDef; +/** + * @} + */ + +/* Exported constants --------------------------------------------------------------------------------------*/ +/** @defgroup CRC_Exported_Constants CRC exported constants + * @{ + */ +#define IS_CRC_POLY(POLY) ((POLY == CRC_CCITT_POLY) || \ + (POLY == CRC_16_POLY) || \ + (POLY == CRC_32_POLY) || \ + (POLY == CRC_USER_DEFINE)) + +#define CRC_NORMAL_WR (0) +#define CRC_BIT_RVS_WR (1UL << 2) +#define CRC_BYTE_RVS_WR (1UL << 3) +#define CRC_CMPL_WR (1UL << 4) + +#define CRC_NORMAL_SUM (0) +#define CRC_BIT_RVS_SUM (1UL << 5) +#define CRC_BYTE_RVS_SUM (1UL << 6) +#define CRC_CMPL_SUM (1UL << 7) + +#define IS_CRC_MOD(MOD) ((MOD & 0xFFFFFF00) == 0) +/** + * @} + */ + +/* Exported functions --------------------------------------------------------------------------------------*/ +/** @defgroup CRC_Exported_Functions CRC exported functions + * @{ + */ +void CRC_DeInit(HT_CRC_TypeDef* HT_CRCn); +void CRC_Init(HT_CRC_TypeDef* HT_CRCn, CRC_InitTypeDef* CRC_InitStruct); +u32 CRC_Process(HT_CRC_TypeDef* HT_CRCn, u8 *buffer, u32 length); + +u16 CRC_CCITT(u16 seed, u8 *buffer, u32 length); +u16 CRC_16(u16 seed, u8 *buffer, u32 length); +u32 CRC_32(u32 seed, u8 *buffer, u32 length); +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/inc/ht32f1xxxx_ebi.h b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/inc/ht32f1xxxx_ebi.h new file mode 100644 index 0000000000..b09ba30b77 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/inc/ht32f1xxxx_ebi.h @@ -0,0 +1,289 @@ +/*********************************************************************************************************//** + * @file ht32f1xxxx_ebi.h + * @version $Rev:: 2788 $ + * @date $Date:: 2022-11-24 #$ + * @brief The header file of the EBI library. + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------------------------------------*/ +#ifndef __HT32F1XXXX_EBI_H +#define __HT32F1XXXX_EBI_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------------------------------------*/ +#include "ht32.h" + +/** @addtogroup HT32F1xxxx_Peripheral_Driver HT32F1xxxx Peripheral Driver + * @{ + */ + +/** @addtogroup EBI + * @{ + */ + + +/* Exported types ------------------------------------------------------------------------------------------*/ +/** @defgroup EBI_Exported_Types EBI exported types + * @{ + */ +typedef struct +{ + u32 EBI_Bank; + u32 EBI_Mode; + #if (LIBCFG_EBI_BYTELAND_ASYNCREADY) + u32 EBI_ByteLane; + u32 EBI_AsynchronousReady; + u32 EBI_ARDYTimeOut; + u32 EBI_ByteLanePolarity; + u32 EBI_ReadySignalPolarity; + #endif + u32 EBI_IdleCycle; + u32 EBI_ChipSelectPolarity; + u32 EBI_AddressLatchPolarity; + u32 EBI_WriteEnablePolarity; + u32 EBI_ReadEnablePolarity; + u32 EBI_IdleCycleTime; + u32 EBI_AddressSetupTime; + u32 EBI_AddressHoldTime; + u32 EBI_WriteSetupTime; + u32 EBI_WriteStrobeTime; + u32 EBI_WriteHoldTime; + u32 EBI_ReadSetupTime; + u32 EBI_ReadStrobeTime; + u32 EBI_ReadHoldTime; + #if !(LIBCFG_EBI_V01) + u32 EBI_PageMode; + u32 EBI_PageLength; + u32 EBI_PageHitMode; + u32 EBI_PageAccessTime; + u32 EBI_PageOpenTime; + #endif +} EBI_InitTypeDef; +/** + * @} + */ + +/* Exported constants --------------------------------------------------------------------------------------*/ +/** @defgroup EBI_Exported_Constants EBI exported constants + * @{ + */ +#define EBI_BANK_0 ((u32)0x00000000) +#define EBI_BANK_1 ((u32)0x00000001) +#define EBI_BANK_2 ((u32)0x00000002) +#define EBI_BANK_3 ((u32)0x00000003) + +#define IS_EBI_BANK(BANK) ((BANK == EBI_BANK_0) || \ + (BANK == EBI_BANK_1) || \ + (BANK == EBI_BANK_2) || \ + (BANK == EBI_BANK_3)) + + +#define EBI_MODE_D8A8 ((u32)0x00000000) +#define EBI_MODE_D16A16ALE ((u32)0x00000001) +#define EBI_MODE_D8A24ALE ((u32)0x00000002) +#define EBI_MODE_D16 ((u32)0x00000003) + +#define IS_EBI_MODE(MODE) ((MODE == EBI_MODE_D8A8) || \ + (MODE == EBI_MODE_D16A16ALE) || \ + (MODE == EBI_MODE_D8A24ALE) || \ + (MODE == EBI_MODE_D16)) + + +#if (LIBCFG_EBI_BYTELAND_ASYNCREADY) +#define EBI_BYTELANE_ENABLE ((u32)0x01000000) +#define EBI_BYTELANE_DISABLE ((u32)0x00000000) + +#define IS_EBI_BYTELANE(BYTELANE) ((BYTELANE == EBI_BYTELANE_ENABLE) || \ + (BYTELANE == EBI_BYTELANE_DISABLE)) +#endif + + +#define EBI_IDLECYCLE_ENABLE ((u32)0x00000000) +#define EBI_IDLECYCLE_DISABLE ((u32)0x00001000) + +#define IS_EBI_IDLECYCLE(IDLECYCLE) ((IDLECYCLE == EBI_IDLECYCLE_ENABLE) || \ + (IDLECYCLE == EBI_IDLECYCLE_DISABLE)) + + +#if (LIBCFG_EBI_BYTELAND_ASYNCREADY) +#define EBI_ASYNCHRONOUSREADY_ENABLE ((u32)0x00010000) +#define EBI_ASYNCHRONOUSREADY_DISABLE ((u32)0x00000000) + +#define IS_EBI_ARDY(ARDY) ((ARDY == EBI_ASYNCHRONOUSREADY_ENABLE) || \ + (ARDY == EBI_ASYNCHRONOUSREADY_DISABLE)) + + +#define EBI_ARDYTIMEOUT_ENABLE ((u32)0x00000000) +#define EBI_ARDYTIMEOUT_DISABLE ((u32)0x00020000) + +#define IS_EBI_ARDY_TIMEOUT(TIMEOUT) ((TIMEOUT == EBI_ARDYTIMEOUT_ENABLE) || \ + (TIMEOUT == EBI_ARDYTIMEOUT_DISABLE)) +#endif + + +#define EBI_CHIPSELECTPOLARITY_LOW ((u32)0x00000000) +#define EBI_CHIPSELECTPOLARITY_HIGH ((u32)0x00000001) + +#define IS_EBI_CS_POLARITY(POLARITY) ((POLARITY == EBI_CHIPSELECTPOLARITY_LOW) || \ + (POLARITY == EBI_CHIPSELECTPOLARITY_HIGH)) + + +#define EBI_ADDRESSLATCHPOLARITY_LOW ((u32)0x00000000) +#define EBI_ADDRESSLATCHPOLARITY_HIGH ((u32)0x00000001) + +#define IS_EBI_ALE_POLARITY(POLARITY) ((POLARITY == EBI_ADDRESSLATCHPOLARITY_LOW) || \ + (POLARITY == EBI_ADDRESSLATCHPOLARITY_HIGH)) + + +#define EBI_WRITEENABLEPOLARITY_LOW ((u32)0x00000000) +#define EBI_WRITEENABLEPOLARITY_HIGH ((u32)0x00000001) + +#define IS_EBI_WE_POLARITY(POLARITY) ((POLARITY == EBI_WRITEENABLEPOLARITY_LOW) || \ + (POLARITY == EBI_WRITEENABLEPOLARITY_HIGH)) + + +#define EBI_READENABLEPOLARITY_LOW ((u32)0x00000000) +#define EBI_READENABLEPOLARITY_HIGH ((u32)0x00000001) + +#define IS_EBI_RE_POLARITY(POLARITY) ((POLARITY == EBI_READENABLEPOLARITY_LOW) || \ + (POLARITY == EBI_READENABLEPOLARITY_HIGH)) + + +#if (LIBCFG_EBI_BYTELAND_ASYNCREADY) +#define EBI_BYTELANEPOLARITY_LOW ((u32)0x00000000) +#define EBI_BYTELANEPOLARITY_HIGH ((u32)0x00000001) + +#define IS_EBI_BL_POLARITY(POLARITY) ((POLARITY == EBI_BYTELANEPOLARITY_LOW) || \ + (POLARITY == EBI_BYTELANEPOLARITY_HIGH)) + + +#define EBI_READYSIGNALPOLARITY_LOW ((u32)0x00000000) +#define EBI_READYSIGNALPOLARITY_HIGH ((u32)0x00000001) + +#define IS_EBI_ARDY_POLARITY(POLARITY) ((POLARITY == EBI_READYSIGNALPOLARITY_LOW) || \ + (POLARITY == EBI_READYSIGNALPOLARITY_HIGH)) +#endif + +#if !(LIBCFG_EBI_V01) +#define EBI_PAGEMODE_ENABLE ((u32)0x01000000) +#define EBI_PAGEMODE_DISABLE ((u32)0x00000000) + +#define IS_EBI_PAGE_MODE(MODE) ((MODE == EBI_PAGEMODE_ENABLE) || \ + (MODE == EBI_PAGEMODE_DISABLE)) + + +#define EBI_PAGELENGTH_4 ((u32)0x00000000) +#define EBI_PAGELENGTH_8 ((u32)0x00000001) +#define EBI_PAGELENGTH_16 ((u32)0x00000002) +#define EBI_PAGELENGTH_32 ((u32)0x00000003) + +#define IS_EBI_PAGE_LENGTH(LENGTH) ((LENGTH == EBI_PAGELENGTH_4) || \ + (LENGTH == EBI_PAGELENGTH_8) || \ + (LENGTH == EBI_PAGELENGTH_16) || \ + (LENGTH == EBI_PAGELENGTH_32)) + + +#define EBI_PAGEHITMODE_ADDINC ((u32)0x00000010) +#define EBI_PAGEHITMODE_INTRPAGE ((u32)0x00000000) + +#define IS_EBI_PAGE_HIT_MODE(MODE) ((MODE == EBI_PAGEHITMODE_ADDINC) || \ + (MODE == EBI_PAGEHITMODE_INTRPAGE)) +#endif + + +#if !(LIBCFG_EBI_V01) +#if (LIBCFG_EBI_BYTELAND_ASYNCREADY) +#define EBI_INT_TOUT ((u32)0x00000001) +#endif +#define EBI_INT_ACCDIS ((u32)0x00000002) +#define EBI_INT_ACCERR ((u32)0x00000002) +#define EBI_INT_ACCRES ((u32)0x00000004) +#define EBI_INT_ALL ((u32)0x00000007) + +#define IS_EBI_INT(INT) (((INT & 0xFFFFFFF8) == 0x0) && (INT != 0x0)) + +#define IS_EBI_INT_FLAG(FLAG) (((FLAG & 0xFFFFFFFC) == 0x0) && (FLAG != 0x0)) +#endif + + +#define IS_EBI_IDLE_CYCLE_TIME(TIME) (TIME < 0x10) + +#define IS_EBI_ADDRESS_SETUP_TIME(TIME) (TIME < 0x10) + +#define IS_EBI_ADDRESS_HOLD_TIME(TIME) (TIME < 0x10) + +#define IS_EBI_WRITE_SETUP_TIME(TIME) (TIME < 0x10) + +#define IS_EBI_WRITE_STROBE_TIME(TIME) (TIME < 0x40) + +#define IS_EBI_WRITE_HOLD_TIME(TIME) (TIME < 0x10) + +#define IS_EBI_READ_SETUP_TIME(TIME) (TIME < 0x10) + +#define IS_EBI_READ_STROBE_TIME(TIME) (TIME < 0x40) + +#define IS_EBI_READ_HOLD_TIME(TIME) (TIME < 0x10) + +#if !(LIBCFG_EBI_V01) +#define IS_EBI_PAGE_ACCESS_TIME(TIME) (TIME < 0x10) + +#define IS_EBI_PAGE_OPEN_TIME(TIME) (TIME < 0x100) +#endif +/** + * @} + */ + +/* Exported functions --------------------------------------------------------------------------------------*/ +/** @defgroup EBI_Exported_Functions EBI exported functions + * @{ + */ +void EBI_DeInit(void); +void EBI_Init(EBI_InitTypeDef* EBI_InitStruct); +void EBI_StructInit(EBI_InitTypeDef* EBI_InitStruct); +void EBI_Cmd(u32 EBI_Bank, ControlStatus NewState); +void EBI_IntConfig(u32 EBI_Int, ControlStatus NewState); +FlagStatus EBI_GetIntStatus(u32 EBI_Int); +void EBI_ClearIntFlag(u32 EBI_Int); +FlagStatus EBI_GetBusyStatus(void); +FlagStatus EBI_GetARDYStatus(void); +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/inc/ht32f1xxxx_exti.h b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/inc/ht32f1xxxx_exti.h new file mode 100644 index 0000000000..ad34ac56bc --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/inc/ht32f1xxxx_exti.h @@ -0,0 +1,208 @@ +/*********************************************************************************************************//** + * @file ht32f1xxxx_exti.h + * @version $Rev:: 2971 $ + * @date $Date:: 2023-10-25 #$ + * @brief The header file of the EXTI library. + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------------------------------------*/ +#ifndef __HT32F1XXXX_EXTI_H +#define __HT32F1XXXX_EXTI_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------------------------------------*/ +#include "ht32.h" + +/** @addtogroup HT32F1xxxx_Peripheral_Driver HT32F1xxxx Peripheral Driver + * @{ + */ + +/** @addtogroup EXTI + * @{ + */ + +/* Exported macro ------------------------------------------------------------------------------------------*/ +/** @defgroup EXTI_Exported_Macro EXTI exported macros + * @{ + */ +/*********************************************************************************************************//** + * @brief Convert the pin number of GPIO to the channel of EXTI. + * @param n: can be 0, 1 to 15 to select the pin number of GPIO. + ************************************************************************************************************/ +#define GPIO2EXTI(n) (n) +#define EXTI_GetIRQn(ch) gEXTIn_IRQn[ch] +/** + * @} + */ + +/* Exported types ------------------------------------------------------------------------------------------*/ +/** @defgroup EXTI_Exported_Types EXTI exported types + * @{ + */ + +/* Definitions of EXTI interrupt line */ +typedef enum +{ + EXTI_CHANNEL_0 = 0, + EXTI_CHANNEL_1, + EXTI_CHANNEL_2, + EXTI_CHANNEL_3, + EXTI_CHANNEL_4, + EXTI_CHANNEL_5, + EXTI_CHANNEL_6, + EXTI_CHANNEL_7, + EXTI_CHANNEL_8, + EXTI_CHANNEL_9, + EXTI_CHANNEL_10, + EXTI_CHANNEL_11, + EXTI_CHANNEL_12, + EXTI_CHANNEL_13, + EXTI_CHANNEL_14, + EXTI_CHANNEL_15, +} EXTI_Channel_TypeDef; + +#define IS_EXTI_CHANNEL(CHANNEL) ((CHANNEL == EXTI_CHANNEL_0) || \ + (CHANNEL == EXTI_CHANNEL_1) || \ + (CHANNEL == EXTI_CHANNEL_2) || \ + (CHANNEL == EXTI_CHANNEL_3) || \ + (CHANNEL == EXTI_CHANNEL_4) || \ + (CHANNEL == EXTI_CHANNEL_5) || \ + (CHANNEL == EXTI_CHANNEL_6) || \ + (CHANNEL == EXTI_CHANNEL_7) || \ + (CHANNEL == EXTI_CHANNEL_8) || \ + (CHANNEL == EXTI_CHANNEL_9) || \ + (CHANNEL == EXTI_CHANNEL_10) || \ + (CHANNEL == EXTI_CHANNEL_11) || \ + (CHANNEL == EXTI_CHANNEL_12) || \ + (CHANNEL == EXTI_CHANNEL_13) || \ + (CHANNEL == EXTI_CHANNEL_14) || \ + (CHANNEL == EXTI_CHANNEL_15)) + +/* Definitions of EXTI init structure */ +typedef enum +{ + EXTI_LOW_LEVEL = 0x0, + EXTI_HIGH_LEVEL = 0x1, + EXTI_NEGATIVE_EDGE = 0x2, + EXTI_POSITIVE_EDGE = 0x3, + EXTI_BOTH_EDGE = 0x4 +} EXTI_Interrupt_TypeDef; + +#define IS_EXTI_INT_TYPE(TYPE) ((TYPE == EXTI_LOW_LEVEL) || \ + (TYPE == EXTI_HIGH_LEVEL) || \ + (TYPE == EXTI_NEGATIVE_EDGE) || \ + (TYPE == EXTI_POSITIVE_EDGE) || \ + (TYPE == EXTI_BOTH_EDGE)) + +typedef enum +{ + EXTI_DEBOUNCE_DISABLE = 0x0, + EXTI_DEBOUNCE_ENABLE = 0x1 +} EXTI_Deb_TypeDef; + +#define IS_EXTI_DEBOUNCE_TYPE(TYPE) ((TYPE == EXTI_DEBOUNCE_DISABLE) || \ + (TYPE == EXTI_DEBOUNCE_ENABLE)) + +typedef struct +{ + u32 EXTI_Channel; + EXTI_Deb_TypeDef EXTI_Debounce; + #if (LIBCFG_EXTI_8BIT_DEBOUNCE_COUNTER) + u8 EXTI_DebounceCnt; + #else + u16 EXTI_DebounceCnt; + #endif + EXTI_Interrupt_TypeDef EXTI_IntType; +} EXTI_InitTypeDef; +/** + * @} + */ + +/* Exported constants --------------------------------------------------------------------------------------*/ +/** @defgroup EXTI_Exported_Constants EXTI exported constants + * @{ + */ + +/* Definitions of EXTI wake up polarity */ +#define EXTI_WAKEUP_HIGH_LEVEL ((u8)0x0) +#define EXTI_WAKEUP_LOW_LEVEL ((u8)0x1) + +#define IS_EXTI_WAKEUP_TYPE(TYPE) ((TYPE == EXTI_WAKEUP_HIGH_LEVEL) || \ + (TYPE == EXTI_WAKEUP_LOW_LEVEL)) + + +#define EXTI_EDGE_POSITIVE ((u8)0x0) +#define EXTI_EDGE_NEGATIVE ((u8)0x1) + +#define IS_EXTI_EDGE(EDGE) ((EDGE == EXTI_EDGE_POSITIVE) || \ + (EDGE == EXTI_EDGE_NEGATIVE)) + +#if (LIBCFG_EXTI_8BIT_DEBOUNCE_COUNTER) +#define IS_EXTI_DEBOUNCE_SIZE(SIZE) (SIZE <= 0xFF) +#else +#define IS_EXTI_DEBOUNCE_SIZE(SIZE) (SIZE <= 0xFFFF) +#endif + +extern const IRQn_Type gEXTIn_IRQn[16]; + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------------------------------------*/ +/** @defgroup EXTI_Exported_Functions EXTI exported functions + * @{ + */ +void EXTI_DeInit(u32 EXTI_Channel); +void EXTI_Init(EXTI_InitTypeDef* EXTI_InitStruct); +void EXTI_IntConfig(u32 EXTI_Channel, ControlStatus NewState); +void EXTI_WakeupEventConfig(u32 EXTI_Channel, u8 EXTI_WakeUpType, ControlStatus NewState); +void EXTI_WakeupEventIntConfig(ControlStatus NewState); +void EXTI_ClearEdgeFlag(u32 EXTI_Channel); +void EXTI_ClearWakeupFlag(u32 EXTI_Channel); +FlagStatus EXTI_GetEdgeFlag(u32 EXTI_Channel); +FlagStatus EXTI_GetEdgeStatus(u32 EXTI_Channel, u32 EXTI_Edge); +FlagStatus EXTI_GetWakeupFlagStatus(u32 EXTI_Channel); +void EXTI_SWIntCmd(u32 EXTI_Channel, ControlStatus NewState); +FlagStatus EXTI_GetSWCmdStatus(u32 EXTI_Channel); +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/inc/ht32f1xxxx_flash.h b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/inc/ht32f1xxxx_flash.h new file mode 100644 index 0000000000..cb194268c0 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/inc/ht32f1xxxx_flash.h @@ -0,0 +1,191 @@ +/*********************************************************************************************************//** + * @file ht32f1xxxx_flash.h + * @version $Rev:: 2971 $ + * @date $Date:: 2023-10-25 #$ + * @brief The header file of the FLASH library. + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------------------------------------*/ +#ifndef __HT32F1XXXX_FLASH_H +#define __HT32F1XXXX_FLASH_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------------------------------------*/ +#include "ht32.h" + +/** @addtogroup HT32F1xxxx_Peripheral_Driver HT32F1xxxx Peripheral Driver + * @{ + */ + +/** @addtogroup FLASH + * @{ + */ + + +/* Exported types ------------------------------------------------------------------------------------------*/ +/** @defgroup FLASH_Exported_Types FLASH exported types + * @{ + */ + +/** + * @brief Enumeration of FLASH return status. + */ +typedef enum +{ + FLASH_COMPLETE = 0, + FLASH_ERR_ADDR_OUT_OF_RANGE, + FLASH_ERR_WRITE_PROTECTED, + FLASH_TIME_OUT +} FLASH_State; + +/** + * @brief Enumeration of FLASH boot mode. + */ +typedef enum +{ + FLASH_BOOT_SRAM = 0, + FLASH_BOOT_LOADER = 1, + FLASH_BOOT_MAIN = 2 +} FLASH_Vector; + +typedef struct +{ + u32 WriteProtect[4]; + u32 MainSecurity; + u32 OptionProtect; +} FLASH_OptionByte; + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------------------------------------*/ +/** @defgroup FLASH_Exported_Constants FLASH exported constants + * @{ + */ + +/* Flash Information */ +#define FLASH_PAGE_SIZE (LIBCFG_FLASH_PAGESIZE) /* Flash page size */ + +/* Flash Wait State */ +#define FLASH_WAITSTATE_0 (0x00000001) /* FLASH zero wait state */ +#define FLASH_WAITSTATE_1 (0x00000002) /* FLASH one wait state */ +#define FLASH_WAITSTATE_2 (0x00000003) /* FLASH two wait state */ +#if (LIBCFG_FMC_WAIT_STATE_3) +#define FLASH_WAITSTATE_3 (0x00000004) /* FLASH three wait state */ +#endif + +#if (LIBCFG_FMC_WAIT_STATE_3) +#define FLASH_WAITSTATE_MAX (FLASH_WAITSTATE_3) +#else +#define FLASH_WAITSTATE_MAX (FLASH_WAITSTATE_2) +#endif + +/* FLASH OISR Flags */ +#define FLASH_FLAG_ORFF (0x00000001) /* Operation Finished Flag */ +#define FLASH_FLAG_ITADF (0x00000002) /* Invalid Target Address Flag */ +#define FLASH_FLAG_OBEF (0x00000004) /* Option Byte Check Sum Error Flag */ +#define FLASH_FLAG_IOCMF (0x00000008) /* Invalid Operation Command Flag */ +#define FLASH_FLAG_OREF (0x00000010) /* Operation Error Flag */ +#define FLASH_FLAG_RORFF (0x00010000) /* Raw Operation Finished Flag */ +#define FLASH_FLAG_PPEF (0x00020000) /* Page Erase/Program Protected Error Flag */ + +/* FLASH OIER */ +#define FLASH_INT_ORFIEN (0x00000001) /* Flash Operation Finished Interrupt Enable */ +#define FLASH_INT_ITADIEN (0x00000002) /* Invalid Target Address Interrupt Enable */ +#define FLASH_INT_OBEIEN (0x00000004) /* Option Byte Checksum Error Interrupt Enable */ +#define FLASH_INT_IOCMIEN (0x00000008) /* Invalid Operation Command Interrupt Enable */ +#define FLASH_INT_OREIEN (0x00000010) /* Operation Error Interrupt Enable */ +#define FLASH_INT_ALL (0x0000001F) /* Flash all Interrupt Enable */ + +/* Option Bytes Address */ +#define OPTION_BYTE_BASE (0x1FF00000) /* Option Byte Base Address */ +#define OB_PP0 (0x1FF00000) /* Option Byte: Write Protection 0 */ +#define OB_PP1 (0x1FF00004) /* Option Byte: Write Protection 1 */ +#define OB_PP2 (0x1FF00008) /* Option Byte: Write Protection 2 */ +#define OB_PP3 (0x1FF0000C) /* Option Byte: Write Protection 3 */ +#define OB_CP (0x1FF00010) /* Option Byte: Security Protection */ +#define OB_CHECKSUM (0x1FF00020) /* Option Byte: Checksum */ + +/* Flash Write Protection Page Mask */ +#if (LIBCFG_FLASH_2PAGE_PER_WPBIT) + #define FLASH_WP_PAGE_SET(OP, PAGE) (OP.WriteProtect[PAGE / 64] |= 1 << ((PAGE % 64) / 2)) + #define FLASH_WP_PAGE_CLEAR(OP, PAGE) (OP.WriteProtect[PAGE / 64] &= ~(1 << ((PAGE % 64) / 2))) + #define FLASH_IS_WP_PAGE(OP, PAGE) (OP.WriteProtect[PAGE / 64] & (1 << ((PAGE % 64) / 2))) +#else + #define FLASH_WP_PAGE_SET(OP, PAGE) (OP.WriteProtect[PAGE / 32] |= 1 << (PAGE % 32)) + #define FLASH_WP_PAGE_CLEAR(OP, PAGE) (OP.WriteProtect[PAGE / 32] &= ~(1 << (PAGE % 32))) + #define FLASH_IS_WP_PAGE(OP, PAGE) (OP.WriteProtect[PAGE / 32] & (1 << (PAGE % 32))) +#endif +#define FLASH_WP_ALLPAGE_SET(OP) {u32 i; for (i = 0; i < 4; i++) { OP.WriteProtect[i] = 0xFFFFFFFF; } } + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------------------------------------*/ +/** @defgroup FLASH_Exported_Functions FLASH exported functions + * @{ + */ +void FLASH_SetWaitState(u32 FLASH_WAITSTATE_n); +void FLASH_PrefetchBufferCmd(ControlStatus NewState); +void FLASH_DcodeCacheCmd(ControlStatus NewState); +void FLASH_BranchCacheCmd(ControlStatus NewState); +#if (LIBCFG_FLASH_HALFCYCYLE) +ErrStatus FLASH_FlashHalfCycleCmd(ControlStatus NewState); +#endif +#if (LIBCFG_FLASH_ZWPWESAVING) +ErrStatus FLASH_FlashZwPwrSavingCmd(ControlStatus NewState); +#endif +void FLASH_SetRemappingMode(FLASH_Vector RemapMode); +FLASH_State FLASH_ErasePage(u32 PageAddress); +FLASH_State FLASH_EraseOptionByte(void); +FLASH_State FLASH_MassErase(void); +FLASH_State FLASH_ProgramWordData(u32 Address, u32 Data); +FLASH_State FLASH_ProgramOptionByte(FLASH_OptionByte *Option); +void FLASH_GetOptionByteStatus(FLASH_OptionByte *Option); +void FLASH_IntConfig(u32 FLASH_INT, ControlStatus Cmd); +FlagStatus FLASH_GetIntStatus(u32 FLASH_FLAG_x); +void FLASH_ClearIntFlag(u32 FLASH_FLAG_x); +FLASH_State FLASH_WaitForOperationEnd(void); +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/inc/ht32f1xxxx_gpio.h b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/inc/ht32f1xxxx_gpio.h new file mode 100644 index 0000000000..30e360baf5 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/inc/ht32f1xxxx_gpio.h @@ -0,0 +1,426 @@ +/*********************************************************************************************************//** + * @file ht32f1xxxx_gpio.h + * @version $Rev:: 2971 $ + * @date $Date:: 2023-10-25 #$ + * @brief The header file of the GPIO and AFIO library. + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------------------------------------*/ +#ifndef __HT32F1XXXX_GPIO_H +#define __HT32F1XXXX_GPIO_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------------------------------------*/ +#include "ht32.h" + +/** @addtogroup HT32F1xxxx_Peripheral_Driver HT32F1xxxx Peripheral Driver + * @{ + */ + +/** @addtogroup GPIO + * @{ + */ + + +/* Settings ------------------------------------------------------------------------------------------------*/ +/** @defgroup GPIO_Settings GPIO settings + * @{ + */ +#ifndef AUTO_CK_CONTROL +#define AUTO_CK_CONTROL (0) +#endif +/** + * @} + */ + +/* Exported types ------------------------------------------------------------------------------------------*/ +/** @defgroup GPIO_Exported_Types GPIO exported types + * @{ + */ + +/** + * @brief Enumeration of GPIO pull resistor. + */ +typedef enum +{ + GPIO_PR_UP = 0, /*!< weak pull-up resistor */ + GPIO_PR_DOWN, /*!< weak pull-down resistor */ + GPIO_PR_DISABLE /*!< Tri-state */ +} GPIO_PR_Enum; +/** + * @brief Enumeration of GPIO output drive current. + */ +typedef enum +{ + GPIO_DV_4MA = 0, /*!< 4mA source/sink current */ + GPIO_DV_8MA, /*!< 8mA source/sink current */ + #if (LIBCFG_GPIO_DV_4_8MA_ONLY) + #else + GPIO_DV_12MA, /*!< 12mA source/sink current */ + GPIO_DV_16MA /*!< 16mA source/sink current */ + #endif +} GPIO_DV_Enum; +/** + * @brief Enumeration of GPIO direction. + */ +typedef enum +{ + GPIO_DIR_IN = 0, /*!< input mode */ + GPIO_DIR_OUT /*!< output mode */ +} GPIO_DIR_Enum; +/** + * @brief Enumeration of GPIO port source for EXTI channel. + */ +typedef enum +{ + AFIO_ESS_PA = 0, /*!< EXTI channel x source come from GPIO Port A */ + AFIO_ESS_PB = 1, /*!< EXTI channel x source come from GPIO Port B */ + AFIO_ESS_PC = 2, /*!< EXTI channel x source come from GPIO Port C */ + AFIO_ESS_PD = 3, /*!< EXTI channel x source come from GPIO Port D */ +#if (LIBCFG_GPIOE) + AFIO_ESS_PE = 4, /*!< EXTI channel x source come from GPIO Port E */ +#endif +#if (LIBCFG_GPIOF) + AFIO_ESS_PF = 5 /*!< EXTI channel x source come from GPIO Port F */ +#endif +} AFIO_ESS_Enum; +/** + * @brief Enumeration of AFIO for EXTI channel. + */ +typedef enum +{ + AFIO_EXTI_CH_0 = 0, /*!< GPIO pin 0 */ + AFIO_EXTI_CH_1, /*!< GPIO pin 1 */ + AFIO_EXTI_CH_2, /*!< GPIO pin 2 */ + AFIO_EXTI_CH_3, /*!< GPIO pin 3 */ + AFIO_EXTI_CH_4, /*!< GPIO pin 4 */ + AFIO_EXTI_CH_5, /*!< GPIO pin 5 */ + AFIO_EXTI_CH_6, /*!< GPIO pin 6 */ + AFIO_EXTI_CH_7, /*!< GPIO pin 7 */ + AFIO_EXTI_CH_8, /*!< GPIO pin 8 */ + AFIO_EXTI_CH_9, /*!< GPIO pin 9 */ + AFIO_EXTI_CH_10, /*!< GPIO pin 10 */ + AFIO_EXTI_CH_11, /*!< GPIO pin 11 */ + AFIO_EXTI_CH_12, /*!< GPIO pin 12 */ + AFIO_EXTI_CH_13, /*!< GPIO pin 13 */ + AFIO_EXTI_CH_14, /*!< GPIO pin 14 */ + AFIO_EXTI_CH_15 /*!< GPIO pin 15 */ +} AFIO_EXTI_CH_Enum; +/** + * @brief Enumeration of AFIO_MODE. + */ +typedef enum +{ + AFIO_MODE_DEFAULT = 0, /*!< Default AFIO mode */ + AFIO_MODE_1, /*!< AFIO mode 1 */ + AFIO_MODE_2, /*!< AFIO mode 2 */ + AFIO_MODE_3, /*!< AFIO mode 3 */ + AFIO_MODE_4, /*!< AFIO mode 4 */ + AFIO_MODE_5, /*!< AFIO mode 5 */ + AFIO_MODE_6, /*!< AFIO mode 6 */ + AFIO_MODE_7, /*!< AFIO mode 7 */ + AFIO_MODE_8, /*!< AFIO mode 8 */ + AFIO_MODE_9, /*!< AFIO mode 9 */ + AFIO_MODE_10, /*!< AFIO mode 10 */ + AFIO_MODE_11, /*!< AFIO mode 11 */ + AFIO_MODE_12, /*!< AFIO mode 12 */ + AFIO_MODE_13, /*!< AFIO mode 13 */ + AFIO_MODE_14, /*!< AFIO mode 14 */ + AFIO_MODE_15 /*!< AFIO mode 15 */ +} AFIO_MODE_Enum; +/** + * @} + */ + +/* Exported constants --------------------------------------------------------------------------------------*/ +/** @defgroup GPIO_Exported_Constants GPIO exported constants + * @{ + */ + +/* Definitions of AFIO_FUN */ +#define AFIO_FUN_DEFAULT AFIO_MODE_DEFAULT /*!< Default AFIO mode */ +#define AFIO_FUN_GPIO AFIO_MODE_1 /*!< AFIO mode GPIO */ +#define AFIO_FUN_ADC0 AFIO_MODE_2 /*!< AFIO mode ADC0 */ +#define AFIO_FUN_CMP AFIO_MODE_3 /*!< AFIO mode CMP */ +#define AFIO_FUN_MCTM_GPTM AFIO_MODE_4 /*!< AFIO mode MCTM/GPTM */ +#define AFIO_FUN_SPI AFIO_MODE_5 /*!< AFIO mode SPI */ +#define AFIO_FUN_USART_UART AFIO_MODE_6 /*!< AFIO mode USART/UART */ +#define AFIO_FUN_I2C AFIO_MODE_7 /*!< AFIO mode I2C */ +#define AFIO_FUN_SCI AFIO_MODE_8 /*!< AFIO mode SCI */ +#define AFIO_FUN_EBI AFIO_MODE_9 /*!< AFIO mode EBI */ +#define AFIO_FUN_I2S AFIO_MODE_10 /*!< AFIO mode I2S */ +#define AFIO_FUN_SDIO AFIO_MODE_11 /*!< AFIO mode SDIO */ +#define AFIO_FUN_CSIF AFIO_MODE_12 /*!< AFIO mode CSIF */ +#define AFIO_FUN_SCTM AFIO_MODE_13 /*!< AFIO mode SCTM */ +#define AFIO_FUN_PWM AFIO_MODE_13 /*!< AFIO mode PWM */ +#define AFIO_FUN_SYSTEM AFIO_MODE_15 /*!< AFIO mode System */ + +/* Definitions of AFIO_FUN alias */ +#define AFIO_FUN_MCTM0 AFIO_FUN_MCTM_GPTM +#define AFIO_FUN_MCTM1 AFIO_FUN_MCTM_GPTM + +#define AFIO_FUN_GPTM0 AFIO_FUN_MCTM_GPTM +#define AFIO_FUN_GPTM1 AFIO_FUN_MCTM_GPTM +#define AFIO_FUN_GPTM2 AFIO_FUN_MCTM_GPTM +#define AFIO_FUN_GPTM3 AFIO_FUN_MCTM_GPTM + +#define AFIO_FUN_PWM0 AFIO_FUN_PWM +#define AFIO_FUN_PWM1 AFIO_FUN_PWM +#define AFIO_FUN_PWM2 AFIO_FUN_PWM +#define AFIO_FUN_PWM3 AFIO_FUN_PWM + +#define AFIO_FUN_SCTM0 AFIO_FUN_SCTM +#define AFIO_FUN_SCTM1 AFIO_FUN_SCTM + +#define AFIO_FUN_ADC AFIO_FUN_ADC0 +#define AFIO_FUN_PWM_SCTM AFIO_MODE_13 + +/* Definitions of GPIO_Px */ +#define GPIO_PORT_NUM (6) +#define GPIO_PIN_NUM (16) +#define GPIO_PA (0) +#define GPIO_PB (1) +#define GPIO_PC (2) +#define GPIO_PD (3) +#if (LIBCFG_GPIOE) +#define GPIO_PE (4) +#endif +#if (LIBCFG_GPIOF) +#define GPIO_PF (5) +#endif + +/* Definitions of GPIO port source for EXTI channel */ +#define AFIO_ESS_PA GPIO_PA /*!< EXTI channel x source come from GPIO Port A */ +#define AFIO_ESS_PB GPIO_PB /*!< EXTI channel x source come from GPIO Port B */ +#define AFIO_ESS_PC GPIO_PC /*!< EXTI channel x source come from GPIO Port C */ +#define AFIO_ESS_PD GPIO_PD /*!< EXTI channel x source come from GPIO Port D */ +#if (LIBCFG_GPIOE) +#define AFIO_ESS_PE GPIO_PE /*!< EXTI channel x source come from GPIO Port E */ +#endif +#if (LIBCFG_GPIOF) +#define AFIO_ESS_PF GPIO_PF /*!< EXTI channel x source come from GPIO Port F */ +#endif + +/* Definitions of GPIO_PIN */ +#define GPIO_PIN_0 0x0001 /*!< GPIO pin 0 selected */ +#define GPIO_PIN_1 0x0002 /*!< GPIO pin 1 selected */ +#define GPIO_PIN_2 0x0004 /*!< GPIO pin 2 selected */ +#define GPIO_PIN_3 0x0008 /*!< GPIO pin 3 selected */ +#define GPIO_PIN_4 0x0010 /*!< GPIO pin 4 selected */ +#define GPIO_PIN_5 0x0020 /*!< GPIO pin 5 selected */ +#define GPIO_PIN_6 0x0040 /*!< GPIO pin 6 selected */ +#define GPIO_PIN_7 0x0080 /*!< GPIO pin 7 selected */ +#define GPIO_PIN_8 0x0100 /*!< GPIO pin 8 selected */ +#define GPIO_PIN_9 0x0200 /*!< GPIO pin 9 selected */ +#define GPIO_PIN_10 0x0400 /*!< GPIO pin 10 selected */ +#define GPIO_PIN_11 0x0800 /*!< GPIO pin 11 selected */ +#define GPIO_PIN_12 0x1000 /*!< GPIO pin 12 selected */ +#define GPIO_PIN_13 0x2000 /*!< GPIO pin 13 selected */ +#define GPIO_PIN_14 0x4000 /*!< GPIO pin 14 selected */ +#define GPIO_PIN_15 0x8000 /*!< GPIO pin 15 selected */ +#define GPIO_PIN_ALL 0xFFFF /*!< GPIO all pins selected */ + +/* Definitions of AFIO_PIN */ +#define AFIO_PIN_0 0x0001 /*!< AFIO pin 0 selected */ +#define AFIO_PIN_1 0x0002 /*!< AFIO pin 1 selected */ +#define AFIO_PIN_2 0x0004 /*!< AFIO pin 2 selected */ +#define AFIO_PIN_3 0x0008 /*!< AFIO pin 3 selected */ +#define AFIO_PIN_4 0x0010 /*!< AFIO pin 4 selected */ +#define AFIO_PIN_5 0x0020 /*!< AFIO pin 5 selected */ +#define AFIO_PIN_6 0x0040 /*!< AFIO pin 6 selected */ +#define AFIO_PIN_7 0x0080 /*!< AFIO pin 7 selected */ +#define AFIO_PIN_8 0x0100 /*!< AFIO pin 8 selected */ +#define AFIO_PIN_9 0x0200 /*!< AFIO pin 9 selected */ +#define AFIO_PIN_10 0x0400 /*!< AFIO pin 10 selected */ +#define AFIO_PIN_11 0x0800 /*!< AFIO pin 11 selected */ +#define AFIO_PIN_12 0x1000 /*!< AFIO pin 12 selected */ +#define AFIO_PIN_13 0x2000 /*!< AFIO pin 13 selected */ +#define AFIO_PIN_14 0x4000 /*!< AFIO pin 14 selected */ +#define AFIO_PIN_15 0x8000 /*!< AFIO pin 15 selected */ +#define AFIO_PIN_ALL 0xFFFF /*!< All AFIO pins selected */ + +/* Definitions of GPIO_PIN_NUM */ +#define GPIO_PIN_NUM_0 0x00 /*!< GPIO pin number 0 selected */ +#define GPIO_PIN_NUM_1 0x01 /*!< GPIO pin number 1 selected */ +#define GPIO_PIN_NUM_2 0x02 /*!< GPIO pin number 2 selected */ +#define GPIO_PIN_NUM_3 0x03 /*!< GPIO pin number 3 selected */ +#define GPIO_PIN_NUM_4 0x04 /*!< GPIO pin number 4 selected */ +#define GPIO_PIN_NUM_5 0x05 /*!< GPIO pin number 5 selected */ +#define GPIO_PIN_NUM_6 0x06 /*!< GPIO pin number 6 selected */ +#define GPIO_PIN_NUM_7 0x07 /*!< GPIO pin number 7 selected */ +#define GPIO_PIN_NUM_8 0x08 /*!< GPIO pin number 8 selected */ +#define GPIO_PIN_NUM_9 0x09 /*!< GPIO pin number 9 selected */ +#define GPIO_PIN_NUM_10 0x0A /*!< GPIO pin number 10 selected */ +#define GPIO_PIN_NUM_11 0x0B /*!< GPIO pin number 11 selected */ +#define GPIO_PIN_NUM_12 0x0C /*!< GPIO pin number 12 selected */ +#define GPIO_PIN_NUM_13 0x0D /*!< GPIO pin number 13 selected */ +#define GPIO_PIN_NUM_14 0x0E /*!< GPIO pin number 14 selected */ +#define GPIO_PIN_NUM_15 0x0F /*!< GPIO pin number 15 selected */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------------------------------------*/ +/** @defgroup GPIO_Exported_Macro GPIO exported macro + * @{ + */ +/* check parameter of the GPIOx */ +#define IS_GPIO(x) (IS_GPIOABCD(x) || IS_GPIOE(x) || IS_GPIOF(x)) +#define IS_GPIOABCD(x) ((x==HT_GPIOA) || (x==HT_GPIOB) || (x==HT_GPIOC) || (x==HT_GPIOD)) +#if (LIBCFG_GPIOE) +#define IS_GPIOE(x) (x == HT_GPIOE) +#else +#define IS_GPIOE(x) (0) +#endif +#if (LIBCFG_GPIOF) +#define IS_GPIOF(x) (x == HT_GPIOF) +#else +#define IS_GPIOF(x) (0) +#endif + +/* check parameter of the GPIO_Px */ +#define IS_GPIO_PORT(x) (IS_GPIO_PORT1(x) || IS_GPIO_PORT2(x) || IS_GPIO_PORT3(x) || IS_GPIO_PORT4(x) || IS_GPIO_PORT5(x)) + +#define IS_GPIO_PORT1(x) ((x == GPIO_PA) || (x == GPIO_PB) ) + +#define IS_GPIO_PORT2(x) (x == GPIO_PC) + +#define IS_GPIO_PORT3(x) (x == GPIO_PD) + +#if (LIBCFG_GPIOE) +#define IS_GPIO_PORT4(x) (x == GPIO_PE) +#else +#define IS_GPIO_PORT4(x) (0) +#endif +#if (LIBCFG_GPIOF) +#define IS_GPIO_PORT5(x) (x == GPIO_PF) +#else +#define IS_GPIO_PORT5(x) (0) +#endif + +/* check parameter of the GPIO_PIN_NUM */ +#define IS_GPIO_PIN_NUM(x) (x < 16) + +/* check parameter of the GPIOx pull resistor */ +#define IS_GPIO_PR(x) (((x) == GPIO_PR_UP) || ((x) == GPIO_PR_DOWN) || ((x) == GPIO_PR_DISABLE)) + +/* check parameter of the GPIOx driving current */ +#if (LIBCFG_GPIO_DV_4_8MA_ONLY) +#define IS_GPIO_DV_12_16MA(x) (0) +#else +#define IS_GPIO_DV_12_16MA(x) (((x) == GPIO_DV_12MA) || ((x) == GPIO_DV_16MA)) +#endif +#define IS_GPIO_DV(x) (((x) == GPIO_DV_4MA) || ((x) == GPIO_DV_8MA) || IS_GPIO_DV_12_16MA(x)) + +/* check parameter of the GPIOx input/output direction */ +#define IS_GPIO_DIR(x) (((x) == GPIO_DIR_IN) || ((x) == GPIO_DIR_OUT) ) + +/* check parameter of the EXTI source port */ +#if (LIBCFG_GPIOE) +#define IS_ESSE(x) (x == AFIO_ESS_PE) +#else +#define IS_ESSE(x) (0) +#endif +#if (LIBCFG_GPIOF) +#define IS_ESSF(x) (x == AFIO_ESS_PF) +#else +#define IS_ESSF(x) (0) +#endif + +#define IS_AFIO_ESS(x) ((x == AFIO_ESS_PA) || (x == AFIO_ESS_PB) || (x == AFIO_ESS_PC) || (x == AFIO_ESS_PD) || IS_ESSE(x) || IS_ESSF(x)) + +/* check parameter of the EXTI channel */ +#define IS_AFIO_EXTI_CH(x) ((x == AFIO_EXTI_CH_0) || (x == AFIO_EXTI_CH_1) || \ + (x == AFIO_EXTI_CH_2) || (x == AFIO_EXTI_CH_3) || \ + (x == AFIO_EXTI_CH_4) || (x == AFIO_EXTI_CH_5) || \ + (x == AFIO_EXTI_CH_6) || (x == AFIO_EXTI_CH_7) || \ + (x == AFIO_EXTI_CH_8) || (x == AFIO_EXTI_CH_9) || \ + (x == AFIO_EXTI_CH_10) || (x == AFIO_EXTI_CH_11) || \ + (x == AFIO_EXTI_CH_12) || (x == AFIO_EXTI_CH_13) || \ + (x == AFIO_EXTI_CH_14) || (x == AFIO_EXTI_CH_15)) + +/* check parameter of the AFIO mode */ +#define IS_AFIO_MODE(x) ((x == AFIO_MODE_DEFAULT) || (x == AFIO_MODE_1) || \ + (x == AFIO_MODE_2) || (x == AFIO_MODE_3) || \ + (x == AFIO_MODE_4) || (x == AFIO_MODE_5) || \ + (x == AFIO_MODE_6) || (x == AFIO_MODE_7) || \ + (x == AFIO_MODE_8) || (x == AFIO_MODE_9) || \ + (x == AFIO_MODE_10) || (x == AFIO_MODE_11) || \ + (x == AFIO_MODE_12) || (x == AFIO_MODE_13) || \ + (x == AFIO_MODE_14) || (x == AFIO_MODE_15)) +/** + * @} + */ + +/* Exported functions --------------------------------------------------------------------------------------*/ +/** @defgroup GPIO_Exported_Functions GPIO exported functions + * @{ + */ + +/* Prototype of related GPIO function */ +void GPIO_DeInit(HT_GPIO_TypeDef* HT_GPIOx); +void GPIO_DirectionConfig(HT_GPIO_TypeDef* HT_GPIOx, u16 GPIO_PIN_nBITMAP, GPIO_DIR_Enum GPIO_DIR_INorOUT); +void GPIO_PullResistorConfig(HT_GPIO_TypeDef* HT_GPIOx, u16 GPIO_PIN_nBITMAP, GPIO_PR_Enum GPIO_PR_x); +void GPIO_InputConfig(HT_GPIO_TypeDef* HT_GPIOx, u16 GPIO_PIN_nBITMAP, ControlStatus Cmd); +void GPIO_DriveConfig(HT_GPIO_TypeDef* HT_GPIOx, u16 GPIO_PIN_nBITMAP, GPIO_DV_Enum GPIO_DV_nMA); +void GPIO_OpenDrainConfig(HT_GPIO_TypeDef* HT_GPIOx, u16 GPIO_PIN_nBITMAP, ControlStatus Cmd); +FlagStatus GPIO_ReadInBit(HT_GPIO_TypeDef* HT_GPIOx, u16 GPIO_PIN_n); +FlagStatus GPIO_ReadOutBit(HT_GPIO_TypeDef* HT_GPIOx, u16 GPIO_PIN_n); +u16 GPIO_ReadInData(HT_GPIO_TypeDef* HT_GPIOx); +u16 GPIO_ReadOutData(HT_GPIO_TypeDef* HT_GPIOx); +void GPIO_SetOutBits(HT_GPIO_TypeDef* HT_GPIOx, u16 GPIO_PIN_nBITMAP); +void GPIO_ClearOutBits(HT_GPIO_TypeDef* HT_GPIOx, u16 GPIO_PIN_nBITMAP); +void GPIO_WriteOutBits(HT_GPIO_TypeDef* HT_GPIOx, u16 GPIO_PIN_nBITMAP, FlagStatus Status); +void GPIO_WriteOutData(HT_GPIO_TypeDef* HT_GPIOx, u16 Data); +void GPIO_PinLock(HT_GPIO_TypeDef* HT_GPIOx, u16 GPIO_PIN_nBITMAP); +bool GPIO_IsPortLocked(HT_GPIO_TypeDef* HT_GPIOx); +bool GPIO_IsPinLocked(HT_GPIO_TypeDef* HT_GPIOx, u16 GPIO_PIN_n); +void GPIO_DisableDebugPort(void); +u32 GPIO_GetID(HT_GPIO_TypeDef* HT_GPIOx); + +/* Prototype of related AFIO function */ +void AFIO_DeInit(void); +void AFIO_GPxConfig(u32 GPIO_Px, u32 AFIO_PIN_n, AFIO_MODE_Enum AFIO_MODE_n); +void AFIO_EXTISourceConfig(u32 GPIO_PIN_NUM_n, u32 GPIO_Px); +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/inc/ht32f1xxxx_i2c.h b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/inc/ht32f1xxxx_i2c.h new file mode 100644 index 0000000000..7d1c314490 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/inc/ht32f1xxxx_i2c.h @@ -0,0 +1,325 @@ +/*********************************************************************************************************//** + * @file ht32f1xxxx_i2c.h + * @version $Rev:: 2971 $ + * @date $Date:: 2023-10-25 #$ + * @brief The header file of the I2C library. + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------------------------------------*/ +#ifndef __HT32F1XXXX_I2C_H +#define __HT32F1XXXX_I2C_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------------------------------------*/ +#include "ht32.h" + +/** @addtogroup HT32F1xxxx_Peripheral_Driver HT32F1xxxx Peripheral Driver + * @{ + */ + +/** @addtogroup I2C + * @{ + */ + + +/* Exported types ------------------------------------------------------------------------------------------*/ +/** @defgroup I2C_Exported_Types I2C exported types + * @{ + */ + +typedef u16 I2C_AddressTypeDef; + +typedef struct +{ + u8 I2C_GeneralCall; + u8 I2C_AddressingMode; + u8 I2C_Acknowledge; + u8 I2C_SpeedOffset; /* Offset value to reach real speed, recommended I2C_SpeedOffset = I2C PCLK/8000000 */ + /* which based on 4.7K Pull up */ + u32 I2C_Speed; + u16 I2C_OwnAddress; +} I2C_InitTypeDef; +/** + * @} + */ + +/* Exported constants --------------------------------------------------------------------------------------*/ +/** @defgroup I2C_Exported_Constants I2C exported constants + * @{ + */ +#define I2C_GENERALCALL_ENABLE ((u32)0x00000004) +#define I2C_GENERALCALL_DISABLE ((u32)0x00000000) + +#define IS_I2C_GENERAL_CALL(CALL) ((CALL == I2C_GENERALCALL_ENABLE) || \ + (CALL == I2C_GENERALCALL_DISABLE)) + +#define I2C_ADDRESSING_7BIT ((u32)0x00000000) +#define I2C_ADDRESSING_10BIT ((u32)0x00000080) + +#define IS_I2C_ACKNOWLEDGE_ADDRESS(ADDRESS) ((ADDRESS == I2C_ADDRESSING_7BIT) || \ + (ADDRESS == I2C_ADDRESSING_10BIT)) + +#define I2C_ACK_ENABLE ((u32)0x00000001) +#define I2C_ACK_DISABLE ((u32)0x00000000) + +#define IS_I2C_ACKNOWLEDGE(ACKNOWLEDGE) ((ACKNOWLEDGE == I2C_ACK_ENABLE) || \ + (ACKNOWLEDGE == I2C_ACK_DISABLE)) + + +#define I2C_INT_STA ((u32)0x00000001) +#define I2C_INT_STO ((u32)0x00000002) +#define I2C_INT_ADRS ((u32)0x00000004) +#define I2C_INT_GCS ((u32)0x00000008) +#define I2C_INT_ARBLOS ((u32)0x00000100) +#define I2C_INT_RXNACK ((u32)0x00000200) +#define I2C_INT_BUSERR ((u32)0x00000400) +#define I2C_INT_TOUT ((u32)0x00000800) +#define I2C_INT_RXDNE ((u32)0x00010000) +#define I2C_INT_TXDE ((u32)0x00020000) +#define I2C_INT_RXBF ((u32)0x00040000) +#define I2C_INT_ALL ((u32)0x00070F0F) + +#define IS_I2C_INT(int) (((int & 0xFFF8F0F0) == 0x0) && (int != 0x0)) + +#define I2C_MASTER_READ ((u32)0x00000400) +#define I2C_MASTER_WRITE ((u32)0x00000000) + +#define IS_I2C_DIRECTION(DIRECTION) ((DIRECTION == I2C_MASTER_READ) || \ + (DIRECTION == I2C_MASTER_WRITE)) + + +#define I2C_REGISTER_CR ((u8)0x00) +#define I2C_REGISTER_IER ((u8)0x04) +#define I2C_REGISTER_ADDR ((u8)0x08) +#define I2C_REGISTER_SR ((u8)0x0C) +#define I2C_REGISTER_SHPGR ((u8)0x10) +#define I2C_REGISTER_SLPGR ((u8)0x14) +#define I2C_REGISTER_DR ((u8)0x18) +#define I2C_REGISTER_BFCLR ((u8)0x1C) +#define I2C_REGISTER_TAR ((u8)0x20) + +#define IS_I2C_REGISTER(REGISTER) ((REGISTER == I2C_REGISTER_CR) || \ + (REGISTER == I2C_REGISTER_IER) || \ + (REGISTER == I2C_REGISTER_ADDR) || \ + (REGISTER == I2C_REGISTER_SR) || \ + (REGISTER == I2C_REGISTER_SHPGR) || \ + (REGISTER == I2C_REGISTER_SLPGR) || \ + (REGISTER == I2C_REGISTER_DR) || \ + (REGISTER == I2C_REGISTER_BFCLR) || \ + (REGISTER == I2C_REGISTER_TAR)) + + +#define I2C_FLAG_STA ((u32)0x00000001) +#define I2C_FLAG_STO ((u32)0x00000002) +#define I2C_FLAG_ADRS ((u32)0x00000004) +#define I2C_FLAG_GCS ((u32)0x00000008) +#define I2C_FLAG_ARBLOS ((u32)0x00000100) +#define I2C_FLAG_RXNACK ((u32)0x00000200) +#define I2C_FLAG_BUSERR ((u32)0x00000400) +#define I2C_FLAG_TOUTF ((u32)0x00000800) +#define I2C_FLAG_RXDNE ((u32)0x00010000) +#define I2C_FLAG_TXDE ((u32)0x00020000) +#define I2C_FLAG_RXBF ((u32)0x00040000) +#define I2C_FLAG_BUSBUSY ((u32)0x00080000) +#define I2C_FLAG_MASTER ((u32)0x00100000) +#define I2C_FLAG_TXNRX ((u32)0x00200000) + +#define IS_I2C_FLAG(FLAG) ((FLAG == I2C_FLAG_STA) || \ + (FLAG == I2C_FLAG_STO) || \ + (FLAG == I2C_FLAG_ADRS) || \ + (FLAG == I2C_FLAG_GCS) || \ + (FLAG == I2C_FLAG_ARBLOS) || \ + (FLAG == I2C_FLAG_RXNACK) || \ + (FLAG == I2C_FLAG_BUSERR) || \ + (FLAG == I2C_FLAG_TOUTF) || \ + (FLAG == I2C_FLAG_RXDNE) || \ + (FLAG == I2C_FLAG_TXDE) || \ + (FLAG == I2C_FLAG_RXBF) || \ + (FLAG == I2C_FLAG_BUSBUSY)|| \ + (FLAG == I2C_FLAG_MASTER) || \ + (FLAG == I2C_FLAG_TXNRX)) + +#define IS_I2C_CLEAR_FLAG(FLAG) ((FLAG == I2C_FLAG_ARBLOS) || \ + (FLAG == I2C_FLAG_RXNACK) || \ + (FLAG == I2C_FLAG_BUSERR) || \ + (FLAG == I2C_FLAG_TOUTF)) + +#define I2C_MASTER_SEND_START ((u32)0x00180001) +#define I2C_MASTER_RECEIVER_MODE ((u32)0x00180004) +#define I2C_MASTER_TRANSMITTER_MODE ((u32)0x003A0004) +#define I2C_MASTER_RX_NOT_EMPTY ((u32)0x00190000) +#define I2C_MASTER_RX_NOT_EMPTY_NOBUSY ((u32)0x00010000) +#define I2C_MASTER_TX_EMPTY ((u32)0x003A0000) +#define I2C_MASTER_RX_BUFFER_FULL ((u32)0x001D0000) +#define I2C_SLAVE_ACK_TRANSMITTER_ADDRESS ((u32)0x002A0004) +#define I2C_SLAVE_ACK_RECEIVER_ADDRESS ((u32)0x00080004) +#define I2C_SLAVE_ACK_GCALL_ADDRESS ((u32)0x00080008) +#define I2C_SLAVE_RX_NOT_EMPTY ((u32)0x00090000) +#define I2C_SLAVE_RX_NOT_EMPTY_STOP ((u32)0x00010002) +#define I2C_SLAVE_TX_EMPTY ((u32)0x002A0000) +#define I2C_SLAVE_RX_BUFFER_FULL ((u32)0x000D0000) +#define I2C_SLAVE_RECEIVED_NACK ((u32)0x00080200) +#define I2C_SLAVE_RECEIVED_NACK_STOP ((u32)0x00000202) +#define I2C_SLAVE_STOP_DETECTED ((u32)0x00000002) + + +#define IS_I2C_STATUS(STATUS) ((STATUS == I2C_MASTER_SEND_START) || \ + (STATUS == I2C_MASTER_RECEIVER_MODE) || \ + (STATUS == I2C_MASTER_TRANSMITTER_MODE) || \ + (STATUS == I2C_MASTER_RX_NOT_EMPTY) || \ + (STATUS == I2C_MASTER_RX_NOT_EMPTY_NOBUSY) || \ + (STATUS == I2C_MASTER_TX_EMPTY) || \ + (STATUS == I2C_MASTER_RX_BUFFER_FULL) || \ + (STATUS == I2C_SLAVE_ACK_TRANSMITTER_ADDRESS) || \ + (STATUS == I2C_SLAVE_ACK_RECEIVER_ADDRESS) || \ + (STATUS == I2C_SLAVE_ACK_GCALL_ADDRESS) || \ + (STATUS == I2C_SLAVE_RX_NOT_EMPTY) || \ + (STATUS == I2C_SLAVE_RX_NOT_EMPTY_STOP) || \ + (STATUS == I2C_SLAVE_TX_EMPTY) || \ + (STATUS == I2C_SLAVE_RX_BUFFER_FULL) || \ + (STATUS == I2C_SLAVE_RECEIVED_NACK) || \ + (STATUS == I2C_SLAVE_RECEIVED_NACK_STOP) || \ + (STATUS == I2C_SLAVE_STOP_DETECTED)) + +#define I2C_PDMAREQ_TX ((u32)0x00000100) +#define I2C_PDMAREQ_RX ((u32)0x00000200) + +#define IS_I2C_PDMA_REQ(REQ) (((REQ & 0xFFFFFCFF) == 0x0) && (REQ != 0x0)) + +#define I2C_PRESCALER_1 ((u32)0x00000000) +#define I2C_PRESCALER_2 ((u32)0x00010000) +#define I2C_PRESCALER_4 ((u32)0x00020000) +#define I2C_PRESCALER_8 ((u32)0x00030000) +#define I2C_PRESCALER_16 ((u32)0x00040000) +#define I2C_PRESCALER_32 ((u32)0x00050000) +#define I2C_PRESCALER_64 ((u32)0x00060000) +#define I2C_PRESCALER_128 ((u32)0x00070000) + +#define IS_I2C_PRESCALER(PRESCALER) ((PRESCALER == I2C_PRESCALER_1) || \ + (PRESCALER == I2C_PRESCALER_2) || \ + (PRESCALER == I2C_PRESCALER_4) || \ + (PRESCALER == I2C_PRESCALER_8) || \ + (PRESCALER == I2C_PRESCALER_16) || \ + (PRESCALER == I2C_PRESCALER_32) || \ + (PRESCALER == I2C_PRESCALER_64) || \ + (PRESCALER == I2C_PRESCALER_128)) + +#define I2C_MASKBIT_0 ((u32)0x00000001) +#define I2C_MASKBIT_1 ((u32)0x00000002) +#define I2C_MASKBIT_2 ((u32)0x00000004) +#define I2C_MASKBIT_3 ((u32)0x00000008) +#define I2C_MASKBIT_4 ((u32)0x00000010) +#define I2C_MASKBIT_5 ((u32)0x00000020) +#define I2C_MASKBIT_6 ((u32)0x00000040) +#define I2C_MASKBIT_7 ((u32)0x00000080) +#define I2C_MASKBIT_8 ((u32)0x00000100) +#define I2C_MASKBIT_9 ((u32)0x00000200) + + +#define IS_I2C_ADDRESS_MASK(MASK) ((MASK == I2C_MASKBIT_0) || \ + (MASK == I2C_MASKBIT_1) || \ + (MASK == I2C_MASKBIT_2) || \ + (MASK == I2C_MASKBIT_3) || \ + (MASK == I2C_MASKBIT_4) || \ + (MASK == I2C_MASKBIT_5) || \ + (MASK == I2C_MASKBIT_6) || \ + (MASK == I2C_MASKBIT_7) || \ + (MASK == I2C_MASKBIT_8) || \ + (MASK == I2C_MASKBIT_9)) + + +#define IS_I2C(I2C) ((I2C == HT_I2C0) || (I2C == HT_I2C1)) + +#define IS_I2C_ADDRESS(ADDRESS) (ADDRESS <= 0x3FF) + +#define IS_I2C_SPEED(SPEED) ((SPEED >= 1) && (SPEED <= 1000000)) + +#define IS_I2C_SCL_HIGH(HIGH) (HIGH <= 0xFFFF) + +#define IS_I2C_SCL_LOW(LOW) (LOW <= 0xFFFF) + +#define IS_I2C_TIMEOUT(TIMEOUT) (TIMEOUT <= 0xFFFF) + +#define SEQ_FILTER_DISABLE ((u32)0x00000000) +#define SEQ_FILTER_1_PCLK ((u32)0x00004000) +#define SEQ_FILTER_2_PCLK ((u32)0x00008000) + +#define IS_I2C_SEQ_FILTER_MASK(CONFIG) ((CONFIG == SEQ_FILTER_DISABLE) || \ + (CONFIG == SEQ_FILTER_1_PCLK) || \ + (CONFIG == SEQ_FILTER_2_PCLK)) +/** + * @} + */ + +/* Exported functions --------------------------------------------------------------------------------------*/ +/** @defgroup I2C_Exported_Functions I2C exported functions + * @{ + */ +void I2C_DeInit(HT_I2C_TypeDef* I2Cx); +void I2C_Init(HT_I2C_TypeDef* I2Cx, I2C_InitTypeDef* I2C_InitStructure); +void I2C_StructInit(I2C_InitTypeDef* I2C_InitStructure); +void I2C_Cmd(HT_I2C_TypeDef* I2Cx, ControlStatus NewState); +void I2C_GenerateSTOP(HT_I2C_TypeDef* I2Cx); +void I2C_IntConfig(HT_I2C_TypeDef* I2Cx, u32 I2C_Int, ControlStatus NewState); +void I2C_GeneralCallCmd(HT_I2C_TypeDef* I2Cx, ControlStatus NewState); +void I2C_AckCmd(HT_I2C_TypeDef* I2Cx, ControlStatus NewState); +void I2C_SetOwnAddress(HT_I2C_TypeDef* I2Cx, I2C_AddressTypeDef I2C_Address); +void I2C_TargetAddressConfig(HT_I2C_TypeDef* I2Cx, I2C_AddressTypeDef I2C_Address, u32 I2C_Direction); +void I2C_SendData(HT_I2C_TypeDef* I2Cx, u8 I2C_Data); +u8 I2C_ReceiveData(HT_I2C_TypeDef* I2Cx); +u32 I2C_ReadRegister(HT_I2C_TypeDef* I2Cx, u8 I2C_Register); +FlagStatus I2C_GetFlagStatus(HT_I2C_TypeDef* I2Cx, u32 I2C_Flag); +ErrStatus I2C_CheckStatus(HT_I2C_TypeDef* I2Cx, u32 I2C_Status); +void I2C_ClearFlag(HT_I2C_TypeDef* I2Cx, u32 I2C_Flag); +void I2C_SetSCLHighPeriod(HT_I2C_TypeDef* I2Cx, u32 I2C_HighPeriod); +void I2C_SetSCLLowPeriod(HT_I2C_TypeDef* I2Cx, u32 I2C_LowPeriod); +void I2C_PDMACmd(HT_I2C_TypeDef* I2Cx, u32 I2C_PDMAREQ, ControlStatus NewState); +void I2C_PDMANACKCmd(HT_I2C_TypeDef* I2Cx, ControlStatus NewState); +void I2C_TimeOutCmd(HT_I2C_TypeDef* I2Cx, ControlStatus NewState); +void I2C_SetTimeOutValue(HT_I2C_TypeDef* I2Cx, u32 I2C_Timeout); +void I2C_SetTimeOutPrescaler(HT_I2C_TypeDef* I2Cx, u32 I2C_Prescaler); +void I2C_AddressMaskConfig(HT_I2C_TypeDef* I2Cx, u32 I2C_Mask); +u16 I2C_GetAddressBuffer(HT_I2C_TypeDef* I2Cx); +void I2C_CombFilterCmd(HT_I2C_TypeDef* I2Cx, ControlStatus NewState); +void I2C_SequentialFilterConfig(HT_I2C_TypeDef* I2Cx, u32 Seq_Filter_Select); +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/inc/ht32f1xxxx_i2s.h b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/inc/ht32f1xxxx_i2s.h new file mode 100644 index 0000000000..4a63e99458 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/inc/ht32f1xxxx_i2s.h @@ -0,0 +1,240 @@ +/*********************************************************************************************************//** + * @file ht32f1xxxx_i2s.h + * @version $Rev:: 1364 $ + * @date $Date:: 2018-08-02 #$ + * @brief The header file of the I2S library. + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------------------------------------*/ +#ifndef __HT32F1XXXX_I2S_H +#define __HT32F1XXXX_I2S_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------------------------------------*/ +#include "ht32.h" + +/** @addtogroup HT32F1xxxx_Peripheral_Driver HT32F1xxxx Peripheral Driver + * @{ + */ + +/** @addtogroup I2S + * @{ + */ + + +/* Exported types ------------------------------------------------------------------------------------------*/ +/** @defgroup I2S_Exported_Types I2S exported types + * @{ + */ +typedef struct +{ + u32 I2S_Mode; + u32 I2S_Format; + u32 I2S_WordWidth; + u32 I2S_MclkOut; + u32 I2S_MclkInv; + u32 I2S_BclkInv; + u32 I2S_X_Div; + u32 I2S_Y_Div; + u32 I2S_N_Div; +} I2S_InitTypeDef; +/** + * @} + */ + +/* Exported constants --------------------------------------------------------------------------------------*/ +/** @defgroup I2S_Exported_Constants I2S exported constants + * @{ + */ +/* mode */ +#define I2S_MASTER_TX (1UL << 1) +#define I2S_MASTER_RX (1UL << 2) +#define I2S_MASTER_TX_RX ((1UL << 1) | (1UL << 2)) + +#define I2S_SLAVE_TX ((1UL << 3) | (1UL << 1)) +#define I2S_SLAVE_RX ((1UL << 3) | (1UL << 2)) +#define I2S_SLAVE_TX_RX ((1UL << 3) | (1UL << 1) | (1UL << 2)) + +#define IS_I2S_MODE(MOD) ((MOD == I2S_MASTER_TX) || \ + (MOD == I2S_MASTER_RX) || \ + (MOD == I2S_MASTER_TX_RX) || \ + (MOD == I2S_SLAVE_TX) || \ + (MOD == I2S_SLAVE_RX) || \ + (MOD == I2S_SLAVE_TX_RX)) + + +/* format */ +#define I2S_JUSTIFIED_STEREO (0) +#define LEFT_JUSTIFIED_STEREO (1UL << 6) +#define RIGHT_JUSTIFIED_STEREO (2UL << 6) +#define I2S_JUSTIFIED_REPEAT (1UL << 10) + +#define I2S_JUSTIFIED_STEREO_EXT (1UL << 8) +#define LEFT_JUSTIFIED_STEREO_EXT ((1UL << 8) | (1UL << 6)) +#define RIGHT_JUSTIFIED_STEREO_EXT ((1UL << 8) | (2UL << 6)) +#define I2S_JUSTIFIED_REPEAT_EXT ((1UL << 8) | (1UL << 10)) + +#define I2S_JUSTIFIED_MONO (1UL << 11) +#define LEFT_JUSTIFIED_MONO ((1UL << 11) | (1UL << 6)) +#define RIGHT_JUSTIFIED_MONO ((1UL << 11) | (2UL << 6)) + +#define I2S_JUSTIFIED_MONO_EXT ((1UL << 8) | (1UL << 11)) +#define LEFT_JUSTIFIED_MONO_EXT ((1UL << 8) | (1UL << 11) | (1UL << 6)) +#define RIGHT_JUSTIFIED_MONO_EXT ((1UL << 8) | (1UL << 11) | (2UL << 6)) + +#define IS_I2S_FORMAT(FMT) ((FMT == I2S_JUSTIFIED_STEREO) || \ + (FMT == LEFT_JUSTIFIED_STEREO) || \ + (FMT == RIGHT_JUSTIFIED_STEREO) || \ + (FMT == I2S_JUSTIFIED_REPEAT) || \ + (FMT == I2S_JUSTIFIED_STEREO_EXT) || \ + (FMT == LEFT_JUSTIFIED_STEREO_EXT) || \ + (FMT == RIGHT_JUSTIFIED_STEREO_EXT) || \ + (FMT == I2S_JUSTIFIED_REPEAT_EXT) || \ + (FMT == I2S_JUSTIFIED_MONO) || \ + (FMT == LEFT_JUSTIFIED_MONO) || \ + (FMT == RIGHT_JUSTIFIED_MONO) || \ + (FMT == I2S_JUSTIFIED_MONO_EXT) || \ + (FMT == LEFT_JUSTIFIED_MONO_EXT) || \ + (FMT == RIGHT_JUSTIFIED_MONO_EXT)) + + +/* word width */ +#define I2S_WORDWIDTH_8 (0) +#define I2S_WORDWIDTH_16 (1UL << 4) +#define I2S_WORDWIDTH_24 (2UL << 4) +#define I2S_WORDWIDTH_32 (3UL << 4) + +#define IS_I2S_WORD_WIDTH(WIDTH) ((WIDTH == I2S_WORDWIDTH_8) || \ + (WIDTH == I2S_WORDWIDTH_16) || \ + (WIDTH == I2S_WORDWIDTH_24) || \ + (WIDTH == I2S_WORDWIDTH_32)) + + +/* clock divider */ +#define IS_I2S_MCLK_DIV(X, Y) ((X > 0) && (X < 256) && (Y > 0) && (Y < 256) && (X <= Y)) + +#define IS_I2S_BCLK_DIV(N) (N < 256) + + +/* FIFO */ +#define I2S_TX_FIFO (1UL << 8) +#define I2S_RX_FIFO (2UL << 8) + +#define IS_I2S_ONE_FIFO(FIFO) ((FIFO == I2S_TX_FIFO) || (FIFO == I2S_RX_FIFO)) + +#define IS_I2S_TWO_FIFO(FIFO) (((FIFO & 0xFFFFFCFF) == 0) && (FIFO != 0)) + +#define IS_I2S_FIFO_LEVEL(LEVEL) ((LEVEL & 0x0000000F) < 9) + + +/* interrupt */ +#define I2S_INT_TXFIFO_TRI (1UL) +#define I2S_INT_TXFIFO_UDF (1UL << 1) +#define I2S_INT_TXFIFO_OVF (1UL << 2) + +#define I2S_INT_RXFIFO_TRI (1UL << 4) +#define I2S_INT_RXFIFO_UDF (1UL << 5) +#define I2S_INT_RXFIFO_OVF (1UL << 6) + +#define IS_I2S_INT(INT) (((INT & 0xFFFFFF88) == 0) && (INT != 0)) + + +/* flag */ +#define I2S_FLAG_TXFIFO_TRI (1UL) +#define I2S_FLAG_TXFIFO_UDF (1UL << 1) +#define I2S_FLAG_TXFIFO_OVF (1UL << 2) +#define I2S_FLAG_RXFIFO_TRI (1UL << 8) +#define I2S_FLAG_RXFIFO_UDF (1UL << 9) +#define I2S_FLAG_RXFIFO_OVF (1UL << 10) + +#define I2S_FLAG_TXFIFO_EMP (1UL << 3) +#define I2S_FLAG_TXFIFO_FUL (1UL << 4) +#define I2S_FLAG_RXFIFO_EMP (1UL << 11) +#define I2S_FLAG_RXFIFO_FUL (1UL << 12) +#define I2S_FLAG_RIGHT_CH (1UL << 16) +#define I2S_FLAG_TX_BUSY (1UL << 17) +#define I2S_FLAG_CLK_RDY (1UL << 18) + +#define IS_I2S_FLAG_CLEAR(FLAG) (((FLAG & 0xFFFFF8F8) == 0) && (FLAG != 0)) + +#define IS_I2S_FLAG(FLAG) ((FLAG == I2S_FLAG_TXFIFO_TRI) || \ + (FLAG == I2S_FLAG_TXFIFO_UDF) || \ + (FLAG == I2S_FLAG_TXFIFO_OVF) || \ + (FLAG == I2S_FLAG_TXFIFO_EMP) || \ + (FLAG == I2S_FLAG_TXFIFO_FUL) || \ + (FLAG == I2S_FLAG_RXFIFO_TRI) || \ + (FLAG == I2S_FLAG_RXFIFO_UDF) || \ + (FLAG == I2S_FLAG_RXFIFO_OVF) || \ + (FLAG == I2S_FLAG_RXFIFO_EMP) || \ + (FLAG == I2S_FLAG_RXFIFO_FUL) || \ + (FLAG == I2S_FLAG_RIGHT_CH) || \ + (FLAG == I2S_FLAG_TX_BUSY) || \ + (FLAG == I2S_FLAG_CLK_RDY)) + + +/* PDMA request */ +#define I2S_PDMAREQ_TX (1UL << 13) +#define I2S_PDMAREQ_RX (1UL << 14) + +#define IS_I2S_PDMA_REQ(REQ) (((REQ & 0xFFFF9FFF) == 0) && (REQ != 0)) +/** + * @} + */ + +/* Exported functions --------------------------------------------------------------------------------------*/ +/** @defgroup I2S_Exported_Functions I2S exported functions + * @{ + */ +void I2S_DeInit(void); +void I2S_Init(I2S_InitTypeDef* I2S_InitStruct); +void I2S_Cmd(ControlStatus NewState); +void I2S_MclkOutputCmd(ControlStatus NewState); +void I2S_TxMuteCmd(ControlStatus NewState); +void I2S_PDMACmd(u32 I2S_PDMAREQ, ControlStatus NewState); +void I2S_FIFOReset(u32 I2S_FIFO); +void I2S_FIFOTrigLevelConfig(u32 I2S_FIFO, u32 I2S_FIFOLevel); +u8 I2S_GetFIFOStatus(u32 I2S_FIFO); +void I2S_IntConfig(u32 I2S_Int, ControlStatus NewState); +FlagStatus I2S_GetFlagStatus(u32 I2S_Flag); +void I2S_ClearFlag(u32 I2S_Flag); +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/inc/ht32f1xxxx_lib.h b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/inc/ht32f1xxxx_lib.h new file mode 100644 index 0000000000..f3c09ec6c0 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/inc/ht32f1xxxx_lib.h @@ -0,0 +1,223 @@ +/*********************************************************************************************************//** + * @file ht32f1xxxx_lib.h + * @version $Rev:: 2971 $ + * @date $Date:: 2023-10-25 #$ + * @brief The header file includes all the header files of the libraries. + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------------------------------------*/ +#ifndef __HT32F1XXXX_LIB_H +#define __HT32F1XXXX_LIB_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Settings ------------------------------------------------------------------------------------------------*/ +#define HT32_FWLIB_VER (0x01004001) +#define HT32_FWLIB_SVN (0x2982) + +#if defined(USE_HT32F1653_54) + #include "ht32f1653_54_libcfg.h" +#endif +#if defined(USE_HT32F1655_56) + #include "ht32f1655_56_libcfg.h" +#endif +#if defined(USE_HT32F12365_66) + #include "ht32f12365_66_libcfg.h" +#endif +#if defined(USE_HT32F12345) + #include "ht32f12345_libcfg.h" +#endif +#if defined(USE_HT32F12364) + #include "ht32f12364_libcfg.h" +#endif + +/* Includes ------------------------------------------------------------------------------------------------*/ +#include +#include "ht32f1xxxx_conf.h" + +#if (HT32_LIB_DEBUG == 1) +/** + * @brief The assert_param macro is used for function's parameters check. + * @param expr: If expr is false, it calls assert_failed function + * which reports the name of the source file and the source + * line number of the call that failed. + * If expr is true, it returns no value. + * @retval None + */ +#define Assert_Param(expr) ((expr) ? (void)0 : assert_error((u8 *)__FILE__, __LINE__)) +/* Exported functions ------------------------------------------------------- ------------------------------*/ +void assert_error(u8* file, u32 line); +#else + +#define Assert_Param(expr) ((void)0) + +#endif /* DEBUG --------------------------------------------------------------------------------------------*/ + + +#if _ADC + #include "ht32f1xxxx_adc.h" +#endif + +#if _AES && LIBCFG_AES + #include "ht32f1xxxx_aes.h" +#endif + +#if _BFTM + #include "ht32f1xxxx_bftm.h" +#endif + +#if _CKCU + #include "ht32f1xxxx_ckcu.h" +#endif + +#if _CMP_OPA && LIBCFG_CMP_OPA + #include "ht32f1xxxx_cmp_op.h" +#endif + +#if _CMP && (!LIBCFG_CMP_OPA) + #include "ht32f1xxxx_cmp.h" +#endif + +#if _CRC + #include "ht32f1xxxx_crc.h" +#endif + +#if _CSIF && LIBCFG_CSIF + #include "ht32f2xxxx_csif.h" +#endif + +#if _EBI + #include "ht32f1xxxx_ebi.h" +#endif + +#if _EXTI + #include "ht32f1xxxx_exti.h" +#endif + +#if _FLASH + #include "ht32f1xxxx_flash.h" +#endif + +#if _GPIO + #include "ht32f1xxxx_gpio.h" +#endif + +#if _GPTM + #include "ht32f1xxxx_tm_type.h" + #include "ht32f1xxxx_tm.h" +#endif + +#if _I2C + #include "ht32f1xxxx_i2c.h" +#endif + +#if _I2S + #include "ht32f1xxxx_i2s.h" +#endif + +#if _MCTM && (!LIBCFG_NO_MCTM0) + #include "ht32f1xxxx_tm_type.h" + #include "ht32f1xxxx_tm.h" + #include "ht32f1xxxx_mctm.h" +#endif + +#if _PDMA + #include "ht32f1xxxx_pdma.h" +#endif + +#if _PWRCU + #include "ht32f1xxxx_pwrcu.h" +#endif + +#if _PWM + #include "ht32f1xxxx_tm_type.h" + #include "ht32f1xxxx_tm.h" +#endif + +#if _RSTCU + #include "ht32f1xxxx_rstcu.h" +#endif + +#if _RTC + #include "ht32f1xxxx_rtc.h" +#endif + +#if _SCI && LIBCFG_SCI0 + #include "ht32f1xxxx_sci.h" +#endif + +#if _SDIO && LIBCFG_SDIO + #include "ht32f1xxxx_sdio.h" +#endif + +#if _SPI + #include "ht32f1xxxx_spi.h" +#endif + +#if _SCTM + #include "ht32f1xxxx_tm_type.h" + #include "ht32f1xxxx_tm.h" +#endif + +#if _USART + #include "ht32f1xxxx_usart.h" +#endif + +#if _USB + #include "ht32f1xxxx_usbd.h" +#endif + +#if _WDT + #include "ht32f1xxxx_wdt.h" +#endif + +#if _MISC + #include "ht32_cm3_misc.h" +#endif + +#if _SERIAL + #include "ht32_serial.h" +#endif + +#if _SWRAND + #include "ht32_rand.h" +#endif + +#if (_RETARGET) + #if defined (__GNUC__) + #undef getchar + #define getchar SERIAL_GetChar + #endif +#endif + +#ifdef HTCFG_TIME_IPSEL +#include "ht32_time.h" +#endif + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/inc/ht32f1xxxx_mctm.h b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/inc/ht32f1xxxx_mctm.h new file mode 100644 index 0000000000..e99cfa0f30 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/inc/ht32f1xxxx_mctm.h @@ -0,0 +1,237 @@ +/*********************************************************************************************************//** + * @file ht32f1xxxx_mctm.h + * @version $Rev:: 122 $ + * @date $Date:: 2017-06-13 #$ + * @brief The header file of the MCTM library. + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------------------------------------*/ +#ifndef __HT32F1XXXX_MCTM_H +#define __HT32F1XXXX_MCTM_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------------------------------------*/ +#include "ht32f1xxxx_tm.h" +#include "ht32.h" + +/** @addtogroup HT32F1xxxx_Peripheral_Driver HT32F1xxxx Peripheral Driver + * @{ + */ + +/** @addtogroup MCTM + * @{ + */ + + +/* Exported types ------------------------------------------------------------------------------------------*/ +/** @defgroup MCTM_Exported_Types MCTM exported types + * @{ + */ +/** + * @brief Enumeration of MCTM channel output idle state. + */ +/** + * @brief Definition of Break & DeadTime init structure. + */ +typedef struct +{ + u32 OSSRState; + u32 OSSIState; + u32 LockLevel; + u32 Break0; + u32 Break0Polarity; + u32 Break1; + u32 Break1Polarity; + u32 AutomaticOutput; + u8 DeadTime; + u8 BreakFilter; +} MCTM_CHBRKCTRInitTypeDef; +/** + * @} + */ + +/* Exported constants --------------------------------------------------------------------------------------*/ +/** @defgroup MCTM_Exported_Constants MCTM exported constants + * @{ + */ + +/** @defgroup MCTM_BKE Definitions of MCTM break control + * @{ + */ +#define MCTM_BREAK_ENABLE 0x00000001 /*!< Break enable */ +#define MCTM_BREAK_DISABLE 0x00000000 /*!< Break disable */ +/** + * @} + */ + +/** @defgroup MCTM_BKP Definitions of MCTM break polarity + * @{ + */ +#define MCTM_BREAK_POLARITY_LOW 0x00000000 /*!< Break input pin active low level */ +#define MCTM_BREAK_POLARITY_HIGH 0x00000002 /*!< Break input pin active high level */ +/** + * @} + */ + +/** @defgroup MCTM_CHMOE Definitions of MCTM main output enable function state + * @{ + */ +#define MCTM_CHMOE_DISABLE 0x00000000 /*!< main output disable */ +#define MCTM_CHMOE_ENABLE 0x00000010 /*!< Main output enable */ +/** + * @} + */ + +/** @defgroup MCTM_CHAOE Definitions of MCTM automatic output enable function state + * @{ + */ +#define MCTM_CHAOE_DISABLE 0x00000000 /*!< Automatic output enable function disable */ +#define MCTM_CHAOE_ENABLE 0x00000020 /*!< Automatic output enable function enable */ +/** + * @} + */ + +/** @defgroup MCTM_LOCK_LEVEL Definitions of MCTM lock level selection + * @{ + */ +#define MCTM_LOCK_LEVEL_OFF 0x00000000 /*!< Lock Off */ +#define MCTM_LOCK_LEVEL_1 0x00010000 /*!< Lock level 1 */ +#define MCTM_LOCK_LEVEL_2 0x00020000 /*!< Lock level 2 */ +#define MCTM_LOCK_LEVEL_3 0x00030000 /*!< Lock level 3 */ +/** + * @} + */ + +/** @defgroup MCTM_OSSI Definitions of Off-State Selection for Idle mode states + * @{ + */ +#define MCTM_OSSI_STATE_ENABLE 0x00100000 +#define MCTM_OSSI_STATE_DISABLE 0x00000000 +/** + * @} + */ + +/** @defgroup MCTM_OSSR Definitions of Off-State Selection for Run mode states + * @{ + */ +#define MCTM_OSSR_STATE_ENABLE 0x00200000 +#define MCTM_OSSR_STATE_DISABLE 0x00000000 +/** + * @} + */ + +/** @defgroup MCTM_Check_Parameter Check parameter + * @{ + */ + +/** + * @brief Used to check parameter of the MCTMx. + */ +#define IS_MCTM(x) ((x == HT_MCTM0) || (x == HT_MCTM1)) +/** + * @brief Used to check parameter of the complementary output channel. + */ +#define IS_MCTM_COMPLEMENTARY_CH(x) (((x) == TM_CH_0) || ((x) == TM_CH_1) || \ + ((x) == TM_CH_2)) +/** + * @brief Used to check parameter of the COMUS. + */ +#define IS_MCTM_COMUS(x) ((x == MCTM_COMUS_STIOFF) || (x == MCTM_COMUS_STION)) +/** + * @brief Used to check parameter of the channel output idle state. + */ +#define IS_MCTM_OIS(x) ((x == MCTM_OIS_LOW) || (x == MCTM_OIS_HIGH)) +/** + * @brief Used to check value of MCTM break control state. + */ +#define IS_MCTM_BREAK_STATE(STATE) (((STATE) == MCTM_BREAK_ENABLE) || \ + ((STATE) == MCTM_BREAK_DISABLE)) +/** + * @brief Used to check value of MCTM break polarity. + */ +#define IS_MCTM_BREAK_POLARITY(POLARITY) (((POLARITY) == MCTM_BREAK_POLARITY_LOW) || \ + ((POLARITY) == MCTM_BREAK_POLARITY_HIGH)) +/** + * @brief Used to check value of MCTM automatic output enable control state. + */ +#define IS_MCTM_CHAOE_STATE(STATE) (((STATE) == MCTM_CHAOE_ENABLE) || \ + ((STATE) == MCTM_CHAOE_DISABLE)) +/** + * @brief Used to check value of MCTM lock level. + */ +#define IS_MCTM_LOCK_LEVEL(LEVEL) (((LEVEL) == MCTM_LOCK_LEVEL_OFF) || \ + ((LEVEL) == MCTM_LOCK_LEVEL_1) || \ + ((LEVEL) == MCTM_LOCK_LEVEL_2) || \ + ((LEVEL) == MCTM_LOCK_LEVEL_3)) +/** + * @brief Used to check value of MCTM OSSI state. + */ +#define IS_MCTM_OSSI_STATE(STATE) (((STATE) == MCTM_OSSI_STATE_ENABLE) || \ + ((STATE) == MCTM_OSSI_STATE_DISABLE)) +/** + * @brief Used to check value of MCTM OSSR state. + */ +#define IS_MCTM_OSSR_STATE(STATE) (((STATE) == MCTM_OSSR_STATE_ENABLE) || \ + ((STATE) == MCTM_OSSR_STATE_DISABLE)) +/** + * @} + */ + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------------------------------------*/ +/** @defgroup MCTM_Exported_Functions MCTM exported functions + * @{ + */ +void MCTM_ChNPolarityConfig(HT_TM_TypeDef* MCTMx, TM_CH_Enum Channel, TM_CHP_Enum Pol); +void MCTM_ChannelNConfig(HT_TM_TypeDef* MCTMx, TM_CH_Enum Channel, TM_CHCTL_Enum Control); + +void MCTM_CHMOECmd(HT_TM_TypeDef* MCTMx, ControlStatus NewState); +void MCTM_CHBRKCTRConfig(HT_TM_TypeDef* MCTMx, MCTM_CHBRKCTRInitTypeDef *CHBRKCTRInit); +void MCTM_CHBRKCTRStructInit(MCTM_CHBRKCTRInitTypeDef* CHBRKCTRInit); +void MCTM_COMPRECmd(HT_TM_TypeDef* MCTMx, ControlStatus NewState); +void MCTM_COMUSConfig(HT_TM_TypeDef* MCTMx, MCTM_COMUS_Enum Sel); + +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/inc/ht32f1xxxx_pdma.h b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/inc/ht32f1xxxx_pdma.h new file mode 100644 index 0000000000..fbb2259615 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/inc/ht32f1xxxx_pdma.h @@ -0,0 +1,344 @@ +/*********************************************************************************************************//** + * @file ht32f1xxxx_pdma.h + * @version $Rev:: 2971 $ + * @date $Date:: 2023-10-25 #$ + * @brief The header file of the PDMA library. + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------------------------------------*/ +#ifndef __HT32F1XXXX_PDMA_H +#define __HT32F1XXXX_PDMA_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------------------------------------*/ +#include "ht32.h" + +/** @addtogroup HT32F1xxxx_Peripheral_Driver HT32F1xxxx Peripheral Driver + * @{ + */ + +/** @addtogroup PDMA + * @{ + */ + + +/* Exported types ------------------------------------------------------------------------------------------*/ +/** @defgroup PDMA_Exported_Types PDMA exported types + * @{ + */ + +/** + * @brief Definition of PDMA channel Init Structure + */ +typedef struct +{ + u32 PDMACH_SrcAddr; /*!< source address */ + u32 PDMACH_DstAddr; /*!< destination address */ + u16 PDMACH_BlkCnt; /*!< number of blocks for a PDMA transfer (1 ~ 65,535) */ + u16 PDMACH_BlkLen; /*!< number of data for a block (1 ~ 65,535) */ + u8 PDMACH_DataSize; /*!< number of bits for a data (8-bit/16-bit/32-bit) */ + u16 PDMACH_Priority; /*!< software priority for a PDMA transfer (L/M/H/VH) */ + u16 PDMACH_AdrMod; /*!< address mode (LIN_INC/LIN_DEC/CIR_INC/CIR_DEC/FIX/AUTO_RELOAD) */ +} PDMACH_InitTypeDef; +/** + * @} + */ + +/* Exported constants --------------------------------------------------------------------------------------*/ +/** @defgroup PDMA_Exported_Constants PDMA exported constants + * @{ + */ +/* priority */ +#define L_PRIO (0) /*!< low priority */ +#define M_PRIO (1UL << 8) /*!< medium priority */ +#define H_PRIO (2UL << 8) /*!< high priority */ +#define VH_PRIO (3UL << 8) /*!< very high priority */ + +#define IS_PDMA_PRIO(PRIO) ((PRIO >> 8) < 4) /*!< check channel priority parameter */ + +/* address mode */ +#define AUTO_RELOAD (1UL << 11) /*!< enable auto reload */ +#define ADR_FIX (1UL << 10) /*!< enable address fix */ + +#define SRC_ADR_LIN_INC (0) /*!< source address linear increment */ +#define SRC_ADR_LIN_DEC (1UL << 6) /*!< source address linear decrement */ +#define SRC_ADR_CIR_INC (2UL << 6) /*!< source address circular increment */ +#define SRC_ADR_CIR_DEC (3UL << 6) /*!< source address circular decrement */ +#define SRC_ADR_FIX (ADR_FIX | SRC_ADR_CIR_INC) /*!< source address fix */ + +#define DST_ADR_LIN_INC (0) /*!< destination address linear increment */ +#define DST_ADR_LIN_DEC (1UL << 4) /*!< destination address linear decrement */ +#define DST_ADR_CIR_INC (2UL << 4) /*!< destination address circular increment */ +#define DST_ADR_CIR_DEC (3UL << 4) /*!< destination address circular decrement */ +#define DST_ADR_FIX (ADR_FIX | DST_ADR_CIR_INC) /*!< destination address fix */ + +#define IS_PDMA_ADR_MOD(MOD) ((MOD & 0xFFFFF30F) == 0) /*!< check address mode parameters */ + +/* transfer size */ +#if (LIBCFG_PDMA_BLKLEN65536) +#define _PDMA_BLK_LEN (65535) +#else +#define _PDMA_BLK_LEN (255) +#endif +#define IS_PDMA_BLK_CNT(CNT) ((CNT > 0) && (CNT <= 65535)) /*!< block count per transfer */ +#define IS_PDMA_BLK_LEN(LEN) ((LEN > 0) && (LEN <= _PDMA_BLK_LEN)) /*!< block size per block count */ + +/* transfer width */ +#define WIDTH_8BIT (0) /*!< 8-bit transfer width */ +#define WIDTH_16BIT (1UL << 2) /*!< 16-bit transfer width */ +#define WIDTH_32BIT (2UL << 2) /*!< 32-bit transfer width */ + +#define IS_PDMA_WIDTH(WIDTH) ((WIDTH >> 2) < 3) /*!< check transfer width parameter */ + +/* channel number */ +#define PDMA_CH0 (0) /*!< channel 0 number */ +#define PDMA_CH1 (1UL) /*!< channel 1 number */ +#define PDMA_CH2 (2UL) /*!< channel 2 number */ +#define PDMA_CH3 (3UL) /*!< channel 3 number */ +#define PDMA_CH4 (4UL) /*!< channel 4 number */ +#define PDMA_CH5 (5UL) /*!< channel 5 number */ +#if !(LIBCFG_NO_PDMA_CH6_11) +#define PDMA_CH6 (6UL) /*!< channel 6 number */ +#define PDMA_CH7 (7UL) /*!< channel 7 number */ +#if (LIBCFG_PDMA_CH8_11) +#define PDMA_CH8 (8UL) /*!< channel 8 number */ +#define PDMA_CH9 (9UL) /*!< channel 9 number */ +#define PDMA_CH10 (10UL) /*!< channel 10 number */ +#define PDMA_CH11 (11UL) /*!< channel 11 number */ +#endif +#endif + +#if (LIBCFG_NO_PDMA_CH6_11) +#define _PDMA_CH_NUM (6) +#elif (LIBCFG_PDMA_CH8_11) +#define _PDMA_CH_NUM (12) +#else +#define _PDMA_CH_NUM (8) +#endif + +#define IS_PDMA_CH(CH) (CH < _PDMA_CH_NUM) /*!< check channel number parameter */ + +#define PDMA_ADC0 PDMA_CH0 /*!< ADC PDMA channel number */ +#define PDMA_ADC PDMA_ADC0 + +#define PDMA_SPI0_RX PDMA_CH0 /*!< SPI0_RX PDMA channel number */ +#define PDMA_SPI0_TX PDMA_CH1 /*!< SPI0_TX PDMA channel number */ +#define PDMA_SPI1_RX PDMA_CH4 /*!< SPI1_RX PDMA channel number */ +#define PDMA_SPI1_TX PDMA_CH5 /*!< SPI1_TX PDMA channel number */ + +#if defined(USE_HT32F12364) +#define PDMA_USART0_RX PDMA_CH0 /*!< USART_RX PDMA channel number */ +#define PDMA_USART0_TX PDMA_CH1 /*!< USART_TX PDMA channel number */ +#else +#define PDMA_USART0_RX PDMA_CH2 /*!< USART0_RX PDMA channel number */ +#define PDMA_USART0_TX PDMA_CH3 /*!< USART0_TX PDMA channel number */ +#endif +#if defined(USE_HT32F1653_54) || defined(USE_HT32F1655_56) +#define PDMA_USART1_TX PDMA_CH6 /*!< USART1_TX PDMA channel number */ +#define PDMA_USART1_RX PDMA_CH7 /*!< USART1_RX PDMA channel number */ +#endif +#if defined(USE_HT32F12365_66) || defined(USE_HT32F12345) +#define PDMA_USART1_RX PDMA_CH8 /*!< USART1_RX PDMA channel number */ +#define PDMA_USART1_TX PDMA_CH9 /*!< USART1_TX PDMA channel number */ +#endif +#if defined(USE_HT32F12364) +#define PDMA_UART0_RX PDMA_CH2 /*!< UART0_RX PDMA channel number */ +#define PDMA_UART0_TX PDMA_CH3 /*!< UART0_TX PDMA channel number */ +#else +#define PDMA_UART0_RX PDMA_CH0 /*!< UART0_RX PDMA channel number */ +#define PDMA_UART0_TX PDMA_CH1 /*!< UART0_TX PDMA channel number */ +#endif +#define PDMA_UART1_RX PDMA_CH4 /*!< UART1_RX PDMA channel number */ +#define PDMA_UART1_TX PDMA_CH5 /*!< UART1_TX PDMA channel number */ + +#if defined(USE_HT32F1653_54) || defined(USE_HT32F1655_56) +#define PDMA_SCI0_RX PDMA_CH6 /*!< SCI_RX PDMA channel number */ +#define PDMA_SCI0_TX PDMA_CH7 /*!< SCI_TX PDMA channel number */ +#endif +#if defined(USE_HT32F12364) +#define PDMA_SCI0_RX PDMA_CH4 /*!< SCI_RX PDMA channel number */ +#define PDMA_SCI0_TX PDMA_CH5 /*!< SCI_TX PDMA channel number */ +#endif +#if defined(USE_HT32F12365_66) +#define PDMA_SCI0_RX PDMA_CH8 /*!< SCI0_RX PDMA channel number */ +#define PDMA_SCI0_TX PDMA_CH9 /*!< SCI0_TX PDMA channel number */ +#define PDMA_SCI1_RX PDMA_CH10 /*!< SCI1_RX PDMA channel number */ +#define PDMA_SCI1_TX PDMA_CH11 /*!< SCI1_TX PDMA channel number */ +#endif + +#if defined(USE_HT32F1653_54) || defined(USE_HT32F1655_56) || defined(USE_HT32F12364) +#define PDMA_I2C0_RX PDMA_CH2 /*!< I2C0_RX PDMA channel number */ +#define PDMA_I2C0_TX PDMA_CH4 /*!< I2C0_TX PDMA channel number */ +#elif defined(USE_HT32F12365_66) || defined(USE_HT32F12345) +#define PDMA_I2C0_RX PDMA_CH10 /*!< I2C0_RX PDMA channel number */ +#define PDMA_I2C0_TX PDMA_CH11 /*!< I2C0_TX PDMA channel number */ +#endif +#if defined(USE_HT32F12364) +#define PDMA_I2C1_RX PDMA_CH3 /*!< I2C1_RX PDMA channel number */ +#define PDMA_I2C1_TX PDMA_CH5 /*!< I2C1_TX PDMA channel number */ +#else +#define PDMA_I2C1_RX PDMA_CH6 /*!< I2C1_RX PDMA channel number */ +#define PDMA_I2C1_TX PDMA_CH7 /*!< I2C1_TX PDMA channel number */ +#endif + +#if !(LIBCFG_NO_MCTM0) +#define PDMA_MCTM0_CH0 PDMA_CH0 /*!< MCTM0_CH0 PDMA channel number */ +#define PDMA_MCTM0_TRIG PDMA_CH1 /*!< MCTM0_TRIG PDMA channel number */ +#define PDMA_MCTM0_CH1 PDMA_CH2 /*!< MCTM0_CH1 PDMA channel number */ +#define PDMA_MCTM0_CH3 PDMA_CH3 /*!< MCTM0_CH3 PDMA channel number */ +#define PDMA_MCTM0_CH2 PDMA_CH4 /*!< MCTM0_CH2 PDMA channel number */ +#define PDMA_MCTM0_UEV1 PDMA_CH5 /*!< MCTM0_UEV1 PDMA channel number */ +#define PDMA_MCTM0_UEV2 PDMA_CH7 /*!< MCTM0_UEV2 PDMA channel number */ + +#define PDMA_MCTM1_CH0 PDMA_CH1 /*!< MCTM1_CH0 PDMA channel number */ +#define PDMA_MCTM1_CH2 PDMA_CH2 /*!< MCTM1_CH2 PDMA channel number */ +#define PDMA_MCTM1_UEV1 PDMA_CH3 /*!< MCTM1_UEV1 PDMA channel number */ +#define PDMA_MCTM1_CH1 PDMA_CH4 /*!< MCTM1_CH1 PDMA channel number */ +#define PDMA_MCTM1_CH3 PDMA_CH5 /*!< MCTM1_CH3 PDMA channel number */ +#define PDMA_MCTM1_UEV2 PDMA_CH6 /*!< MCTM1_UEV2 PDMA channel number */ +#define PDMA_MCTM1_TRIG PDMA_CH7 /*!< MCTM1_TRIG PDMA channel number */ +#endif + +#if defined(USE_HT32F12364) +#define PDMA_GPTM0_CH0 PDMA_CH2 /*!< GPTM0_CH0 PDMA channel number */ +#define PDMA_GPTM0_CH1 PDMA_CH0 /*!< GPTM0_CH1 PDMA channel number */ +#define PDMA_GPTM0_CH2 PDMA_CH1 /*!< GPTM0_CH2 PDMA channel number */ +#define PDMA_GPTM0_CH3 PDMA_CH0 /*!< GPTM0_CH3 PDMA channel number */ +#define PDMA_GPTM0_TRIG PDMA_CH2 /*!< GPTM0_TRIG PDMA channel number */ +#define PDMA_GPTM0_UEV PDMA_CH1 /*!< GPTM0_UEV PDMA channel number */ +#else +#define PDMA_GPTM0_CH1 PDMA_CH0 /*!< GPTM0_CH1 PDMA channel number */ +#define PDMA_GPTM0_CH3 PDMA_CH0 /*!< GPTM0_CH3 PDMA channel number */ +#define PDMA_GPTM0_UEV PDMA_CH1 /*!< GPTM0_UEV PDMA channel number */ +#define PDMA_GPTM0_CH2 PDMA_CH2 /*!< GPTM0_CH2 PDMA channel number */ +#define PDMA_GPTM0_CH0 PDMA_CH3 /*!< GPTM0_CH0 PDMA channel number */ +#define PDMA_GPTM0_TRIG PDMA_CH3 /*!< GPTM0_TRIG PDMA channel number */ +#endif + +#if defined(USE_HT32F1653_54) || defined(USE_HT32F1655_56) +#define PDMA_GPTM1_CH0 PDMA_CH4 /*!< GPTM1_CH0 PDMA channel number */ +#define PDMA_GPTM1_CH1 PDMA_CH5 /*!< GPTM1_CH1 PDMA channel number */ +#define PDMA_GPTM1_UEV PDMA_CH5 /*!< GPTM1_UEV PDMA channel number */ +#define PDMA_GPTM1_CH2 PDMA_CH6 /*!< GPTM1_CH2 PDMA channel number */ +#define PDMA_GPTM1_TRIG PDMA_CH6 /*!< GPTM1_TRIG PDMA channel number */ +#define PDMA_GPTM1_CH3 PDMA_CH7 /*!< GPTM1_CH3 PDMA channel number */ +#endif +#if defined(USE_HT32F12365_66) || defined(USE_HT32F12345) +#define PDMA_GPTM1_CH0 PDMA_CH8 /*!< GPTM1_CH0 PDMA channel number */ +#define PDMA_GPTM1_CH1 PDMA_CH9 /*!< GPTM1_CH1 PDMA channel number */ +#define PDMA_GPTM1_UEV PDMA_CH9 /*!< GPTM1_UEV PDMA channel number */ +#define PDMA_GPTM1_CH2 PDMA_CH10 /*!< GPTM1_CH2 PDMA channel number */ +#define PDMA_GPTM1_TRIG PDMA_CH10 /*!< GPTM1_TRIG PDMA channel number */ +#define PDMA_GPTM1_CH3 PDMA_CH11 /*!< GPTM1_CH3 PDMA channel number */ +#endif + +#if (LIBCFG_PWM0) +#define PDMA_PWM0_CH0 PDMA_CH5 /*!< PWM0_CH0 PDMA channel number */ +#define PDMA_PWM0_CH1 PDMA_CH3 /*!< PWM0_CH1 PDMA channel number */ +#define PDMA_PWM0_CH2 PDMA_CH4 /*!< PWM0_CH2 PDMA channel number */ +#define PDMA_PWM0_CH3 PDMA_CH3 /*!< PWM0_CH3 PDMA channel number */ +#define PDMA_PWM0_TRIG PDMA_CH5 /*!< PWM0_TRIG PDMA channel number */ +#define PDMA_PWM0_UEV PDMA_CH4 /*!< PWM0_UEV PDMA channel number */ +#endif + + +#define PDMA_I2S_RX PDMA_CH2 /*!< I2S_RX PDMA channel number */ +#define PDMA_I2S_TX PDMA_CH3 /*!< I2S_TX PDMA channel number */ + +#if defined(USE_HT32F12365_66) +#define PDMA_CSIF PDMA_CH0 /*!< CSIF PDMA channel number */ +#endif + +#if defined(USE_HT32F12365_66) || defined(USE_HT32F12345) +#define PDMA_SDIO_RX PDMA_CH6 /*!< SDIO_RX PDMA channel number */ +#define PDMA_SDIO_TX PDMA_CH7 /*!< SDIO_TX PDMA channel number */ +#endif + +#if defined(USE_HT32F12364) +#define PDMA_AES_OUT PDMA_CH4 /*!< AES_OUT PDMA channel number */ +#define PDMA_AES_IN PDMA_CH5 /*!< AES_IN PDMA channel number */ +#elif defined(USE_HT32F12365_66) +#define PDMA_AES_OUT PDMA_CH10 /*!< AES_OUT PDMA channel number */ +#define PDMA_AES_IN PDMA_CH11 /*!< AES_IN PDMA channel number */ +#endif + +/* flag */ +#define PDMA_FLAG_GE (1UL << 0) /*!< PDMA channel global event flag */ +#define PDMA_FLAG_BE (1UL << 1) /*!< PDMA channel block end flag */ +#define PDMA_FLAG_HT (1UL << 2) /*!< PDMA channel half transfer flag */ +#define PDMA_FLAG_TC (1UL << 3) /*!< PDMA channel transfer complete flag */ +#define PDMA_FLAG_TE (1UL << 4) /*!< PDMA channel transfer error flag */ + +#define IS_PDMA_FLAG(FLAG) (((FLAG & 0xFFFFFFE0) == 0) && (FLAG != 0)) +#define IS_PDMA_CLEAR_FLAG(FLAG) (((FLAG & 0xFFFFFFE0) == 0) && (FLAG != 0)) + +/* interrupt */ +#define PDMA_INT_GE (1UL << 0) /*!< PDMA channel global event interrupt */ +#define PDMA_INT_BE (1UL << 1) /*!< PDMA channel block end interrupt */ +#define PDMA_INT_HT (1UL << 2) /*!< PDMA channel half transfer interrupt */ +#define PDMA_INT_TC (1UL << 3) /*!< PDMA channel transfer complete interrupt */ +#define PDMA_INT_TE (1UL << 4) /*!< PDMA channel transfer error interrupt */ + +#define IS_PDMA_INT(INT) (((INT & 0xFFFFFFE0) == 0) && (INT != 0)) +/** + * @} + */ + +/* Exported functions --------------------------------------------------------------------------------------*/ +/** @defgroup PDMA_Exported_Functions PDMA exported functions + * @{ + */ +void PDMA_DeInit(void); +void PDMA_Config(u32 PDMA_CHn, PDMACH_InitTypeDef *PDMACH_InitStruct); +void PDMA_AddrConfig(u32 PDMA_CHn, u32 SrcAddr, u32 DstAddr); +void PDMA_SrcAddrConfig(u32 PDMA_CHn, u32 SrcAddr); +void PDMA_DstAddrConfig(u32 PDMA_CHn, u32 DstAddr); +void PDMA_TranSizeConfig(u32 PDMA_CHn, u16 BlkCnt, u16 BlkLen); +void PDMA_EnaCmd(u32 PDMA_CHn, ControlStatus NewState); +void PDMA_SwTrigCmd(u32 PDMA_CHn, ControlStatus NewState); + +void PDMA_IntConfig(u32 PDMA_CHn, u32 PDMA_INT_x, ControlStatus NewState); +FlagStatus PDMA_GetFlagStatus(u32 PDMA_CHn, u32 PDMA_FLAG_x); +void PDMA_ClearFlag(u32 PDMA_CHn, u32 PDMA_FLAG_x); +u16 PDMA_GetRemainBlkCnt(u32 PDMA_CHn); +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/inc/ht32f1xxxx_pwrcu.h b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/inc/ht32f1xxxx_pwrcu.h new file mode 100644 index 0000000000..267e7be448 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/inc/ht32f1xxxx_pwrcu.h @@ -0,0 +1,285 @@ +/*********************************************************************************************************//** + * @file ht32f1xxxx_pwrcu.h + * @version $Rev:: 2971 $ + * @date $Date:: 2023-10-25 #$ + * @brief The header file of the Power Control Unit library. + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------------------------------------*/ +#ifndef __HT32F1XXXX_PWRCU_H +#define __HT32F1XXXX_PWRCU_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------------------------------------*/ +#include "ht32.h" + +/** @addtogroup HT32F1xxxx_Peripheral_Driver HT32F1xxxx Peripheral Driver + * @{ + */ + +/** @addtogroup PWRCU + * @{ + */ + + +/* Exported types ------------------------------------------------------------------------------------------*/ +/** @defgroup PWRCU_Exported_Types PWRCU exported types + * @{ + */ + +/** + * @brief Status of Power control unit + */ +typedef enum +{ + PWRCU_OK = 0, /*!< Ready for access or backup domain power-on reset is released */ + PWRCU_TIMEOUT, /*!< Time out */ + PWRCU_ERROR /*!< Error */ +} PWRCU_Status; +/** + * @brief DMOS status + */ +typedef enum +{ + PWRCU_DMOS_STS_ON = 0, /*!< DMOS on */ + PWRCU_DMOS_STS_OFF, /*!< DMOS off */ + PWRCU_DMOS_STS_OFF_BY_BODRESET /*!< DMOS off caused by brow out reset */ +} PWRCU_DMOSStatus; +/** + * @brief LVD level selection + */ +typedef enum +{ + PWRCU_LVDS_LV1 = 0x00000000, /*!< LVD level 1 */ + PWRCU_LVDS_LV2 = 0x00020000, /*!< LVD level 2 */ + PWRCU_LVDS_LV3 = 0x00040000, /*!< LVD level 3 */ + PWRCU_LVDS_LV4 = 0x00060000, /*!< LVD level 4 */ + PWRCU_LVDS_LV5 = 0x00400000, /*!< LVD level 5 */ + PWRCU_LVDS_LV6 = 0x00420000, /*!< LVD level 6 */ + PWRCU_LVDS_LV7 = 0x00440000, /*!< LVD level 7 */ + PWRCU_LVDS_LV8 = 0x00460000 /*!< LVD level 8 */ +} PWRCU_LVDS_Enum; +#if (LIBCFG_PWRCU_LVDS_27_35) + #define PWRCU_LVDS_2V7 PWRCU_LVDS_LV1 + #define PWRCU_LVDS_2V8 PWRCU_LVDS_LV2 + #define PWRCU_LVDS_2V9 PWRCU_LVDS_LV3 + #define PWRCU_LVDS_3V PWRCU_LVDS_LV4 + #define PWRCU_LVDS_3V1 PWRCU_LVDS_LV5 + #define PWRCU_LVDS_3V2 PWRCU_LVDS_LV6 + #define PWRCU_LVDS_3V4 PWRCU_LVDS_LV7 + #define PWRCU_LVDS_3V5 PWRCU_LVDS_LV8 +#elif (LIBCFG_PWRCU_LVDS_17_31) + #define PWRCU_LVDS_1V75 PWRCU_LVDS_LV1 + #define PWRCU_LVDS_1V95 PWRCU_LVDS_LV2 + #define PWRCU_LVDS_2V15 PWRCU_LVDS_LV3 + #define PWRCU_LVDS_2V35 PWRCU_LVDS_LV4 + #define PWRCU_LVDS_2V55 PWRCU_LVDS_LV5 + #define PWRCU_LVDS_2V75 PWRCU_LVDS_LV6 + #define PWRCU_LVDS_2V95 PWRCU_LVDS_LV7 + #define PWRCU_LVDS_3V15 PWRCU_LVDS_LV8 +#else + #define PWRCU_LVDS_2V25 PWRCU_LVDS_LV1 + #define PWRCU_LVDS_2V4 PWRCU_LVDS_LV2 + #define PWRCU_LVDS_2V55 PWRCU_LVDS_LV3 + #define PWRCU_LVDS_2V7 PWRCU_LVDS_LV4 + #define PWRCU_LVDS_2V85 PWRCU_LVDS_LV5 + #define PWRCU_LVDS_3V PWRCU_LVDS_LV6 + #define PWRCU_LVDS_3V15 PWRCU_LVDS_LV7 + #define PWRCU_LVDS_3V3 PWRCU_LVDS_LV8 +#endif +/** + * @brief BOD reset or interrupt selection + */ +typedef enum +{ + PWRCU_BODRIS_RESET = 0, /*!< Reset the whole chip */ + PWRCU_BODRIS_INT = 1, /*!< Assert interrupt */ +} PWRCU_BODRIS_Enum; +/** + * @brief Sleep entry instruction selection + */ +typedef enum +{ + PWRCU_SLEEP_ENTRY_WFE = 0, /*!< Sleep then wait for event */ + PWRCU_SLEEP_ENTRY_WFI /*!< Sleep then wait for interrupt */ +} PWRCU_SLEEP_ENTRY_Enum; +#if (!LIBCFG_NO_BACK_DOMAIN) +/** + * @brief Backup register selection + */ +typedef enum +{ + PWRCU_BAKREG_0 = 0, + PWRCU_BAKREG_1, + PWRCU_BAKREG_2, + PWRCU_BAKREG_3, + PWRCU_BAKREG_4, + PWRCU_BAKREG_5, + PWRCU_BAKREG_6, + PWRCU_BAKREG_7, + PWRCU_BAKREG_8, + PWRCU_BAKREG_9 +} PWRCU_BAKREG_Enum; +#endif +/** + * @brief Vdd18/Vdd15 power good source selection + */ +typedef enum +{ + PWRCU_VRDYSC_BKISO = 0, /*!< Vdd18/Vdd15 power good source come from BK_ISO bit in CKCU unit */ + PWRCU_VRDYSC_VPOR /*!< Vdd18/Vdd15 power good source come from Vdd18 power on reset */ +} PWRCU_VRDYSC_Enum; +#if (!LIBCFG_PWRCU_LDO_LEGACY) +/** + * @brief LDO operation mode selection + */ +typedef enum +{ + PWRCU_LDO_NORMAL = 0, /*!< The LDO is operated in normal current mode */ + PWRCU_LDO_LOWCURRENT /*!< The LDO is operated in low current mode */ +} PWRCU_LDOMODE_Enum; +/** + * @brief LDO output offset selection + */ +typedef enum +{ + PWRCU_LDO_DEFAULT = 0x00000000, /*!< The LDO default output voltage */ + PWRCU_LDO_OFFSET_DEC5P = 0x00000010, /*!< The LDO default output voltage offset -5% */ + PWRCU_LDO_OFFSET_ADD3P = 0x00000020, /*!< The LDO default output voltage offset +3% */ + PWRCU_LDO_OFFSET_ADD7P = 0x00000030, /*!< The LDO default output voltage offset +7% */ +} PWRCU_LDOFTRM_Enum; +#endif +/** + * @brief HSI ready counter bit length selection + */ +typedef enum +{ + PWRCU_HSIRCBL_4 = 0, /*!< 4 bits */ + PWRCU_HSIRCBL_5, /*!< 5 bits */ + PWRCU_HSIRCBL_6, /*!< 5 bits */ + PWRCU_HSIRCBL_7 /*!< 7 bits (Default) */ +} PWRCU_HSIRCBL_Enum; +/** + * @} + */ + +/* Exported constants --------------------------------------------------------------------------------------*/ +/** @defgroup PWRCU_Exported_Constants PWRCU exported constants + * @{ + */ + +/* Definitions of PWRCU_FLAG */ +#define PWRCU_FLAG_PWRPOR 0x0001 /*!< Backup domain power-on reset flag */ +#define PWRCU_FLAG_PD 0x0002 /*!< Power-Down flag */ +#define PWRCU_FLAG_WUP 0x0100 /*!< External WAKEUP pin flag */ + +#define PWRCU_FLAG_BAKPOR PWRCU_FLAG_PWRPOR + +/* check PWRCU_LVDS parameter */ +#define IS_PWRCU_LVDS(x) ((x == PWRCU_LVDS_LV1) || (x == PWRCU_LVDS_LV2) || \ + (x == PWRCU_LVDS_LV3) || (x == PWRCU_LVDS_LV4) || \ + (x == PWRCU_LVDS_LV5) || (x == PWRCU_LVDS_LV6) || \ + (x == PWRCU_LVDS_LV7) || (x == PWRCU_LVDS_LV8)) + +/* check PWRCU_BODRIS parameter */ +#define IS_PWRCU_BODRIS(x) ((x == PWRCU_BODRIS_RESET) || (x == PWRCU_BODRIS_INT)) + +/* check PWRCU_HSIRCBL parameter */ +#define IS_PWRCU_HSIRCBL(x) (x <= 3) + +/* check PWRCU_SLEEP_ENTRY parameter */ +#define IS_PWRCU_SLEEP_ENTRY(x) ((x == PWRCU_SLEEP_ENTRY_WFI) || (x == PWRCU_SLEEP_ENTRY_WFE)) + +/* check PWRCU_BAKREG parameter */ +#define IS_PWRCU_BAKREG(x) (x < 10) + +/* check PWRCU_VRDY_SRC parameter */ +#define IS_PWRCU_VRDYSC(x) ((x == PWRCU_VRDYSC_BKISO) || (x == PWRCU_VRDYSC_VPOR)) + +#if (!LIBCFG_PWRCU_LDO_LEGACY) +/* check PWRCU_LDOMODE parameter */ +#define IS_PWRCU_LDOMODE(x) ((x == PWRCU_LDO_NORMAL) || (x == PWRCU_LDO_LOWCURRENT)) +#if (!LIBCFG_NO_PWRCU_LDO_CFG_VOLTAGE) +/* check PWRCU_LDOFTRM parameter */ +#define IS_PWRCU_LDOFTRM(x) ((x == PWRCU_LDO_DEFAULT) || (x == PWRCU_LDO_OFFSET_DEC5P) || \ + (x == PWRCU_LDO_OFFSET_ADD3P) || (x == PWRCU_LDO_OFFSET_ADD7P)) +#endif +#endif +/** + * @} + */ + +/* Exported functions --------------------------------------------------------------------------------------*/ +/** @defgroup PWRCU_Exported_Functions PWRCU exported functions + * @{ + */ +void PWRCU_DeInit(void); +PWRCU_Status PWRCU_CheckReadyAccessed(void); +u16 PWRCU_GetFlagStatus(void); +#if (!LIBCFG_NO_BACK_DOMAIN) +u32 PWRCU_ReadBackupRegister(PWRCU_BAKREG_Enum BAKREGx); +void PWRCU_WriteBackupRegister(PWRCU_BAKREG_Enum BAKREGx, u32 DATA); +#endif +void PWRCU_Sleep(PWRCU_SLEEP_ENTRY_Enum SleepEntry); +void PWRCU_DeepSleep1(PWRCU_SLEEP_ENTRY_Enum SleepEntry); +void PWRCU_DeepSleep2(PWRCU_SLEEP_ENTRY_Enum SleepEntry); +void PWRCU_PowerDown(void); +void PWRCU_SetLVDS(PWRCU_LVDS_Enum Level); +#if (!LIBCFG_PWRCU_LDO_LEGACY) +void PWRCU_SetLDOFTRM(PWRCU_LDOFTRM_Enum VolOffset); +void PWRCU_LDOConfig(PWRCU_LDOMODE_Enum Sel); +#endif +void PWRCU_LVDCmd(ControlStatus NewState); +void PWRCU_BODCmd(ControlStatus NewState); +void PWRCU_BODRISConfig(PWRCU_BODRIS_Enum Selection); +FlagStatus PWRCU_GetLVDFlagStatus(void); +FlagStatus PWRCU_GetBODFlagStatus(void); +PWRCU_DMOSStatus PWRCU_GetDMOSStatus(void); +void PWRCU_DMOSCmd(ControlStatus NewState); +void PWRCU_VRDYSourceConfig(PWRCU_VRDYSC_Enum Sel); +void PWRCU_LVDIntWakeupConfig(ControlStatus NewState); +void PWRCU_LVDEventWakeupConfig(ControlStatus NewState); +void PWRCU_WakeupPinCmd(ControlStatus NewState); +void PWRCU_WakeupPinIntConfig(ControlStatus NewState); +void PWRCU_HSIReadyCounterBitLengthConfig(PWRCU_HSIRCBL_Enum BitLength); +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/inc/ht32f1xxxx_rstcu.h b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/inc/ht32f1xxxx_rstcu.h new file mode 100644 index 0000000000..c6870ab8bf --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/inc/ht32f1xxxx_rstcu.h @@ -0,0 +1,266 @@ +/*********************************************************************************************************//** + * @file ht32f1xxxx_rstcu.h + * @version $Rev:: 2973 $ + * @date $Date:: 2023-10-30 #$ + * @brief The header file of the Reset Control Unit library. + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------------------------------------*/ +#ifndef __HT32F1XXXX_RSTCU_H +#define __HT32F1XXXX_RSTCU_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------------------------------------*/ +#include "ht32.h" + +/** @addtogroup HT32F1xxxx_Peripheral_Driver HT32F1xxxx Peripheral Driver + * @{ + */ + +/** @addtogroup RSTCU + * @{ + */ + + +/* Exported types ------------------------------------------------------------------------------------------*/ +/** @defgroup RSTCU_Exported_Types RSTCU exported types + * @{ + */ + +/** + * @brief Enumeration of Global reset status. + */ +typedef enum +{ + RSTCU_FLAG_SYSRST = 0, + RSTCU_FLAG_EXTRST, + RSTCU_FLAG_WDTRST, + RSTCU_FLAG_PORST +} RSTCU_RSTF_TypeDef; + +/** + * @brief Definition of initial structure of peripheral reset. + */ +typedef union +{ + struct + { + /* Definitions of AHB peripheral reset */ + unsigned long PDMA :1; // Bit 0 + unsigned long :1; // Bit 1 + unsigned long :1; // Bit 2 + unsigned long :1; // Bit 3 +#if (LIBCFG_CSIF) + unsigned long CSIF :1; // Bit 4 +#else + unsigned long :1; // Bit 4 +#endif + unsigned long USBD :1; // Bit 5 + unsigned long EBI :1; // Bit 6 + unsigned long CRC :1; // Bit 7 + + unsigned long PA :1; // Bit 8 + unsigned long PB :1; // Bit 9 + unsigned long PC :1; // Bit 10 + unsigned long PD :1; // Bit 11 +#if (LIBCFG_GPIOE) + unsigned long PE :1; // Bit 12 +#else + unsigned long :1; // Bit 12 +#endif +#if (LIBCFG_GPIOF) + unsigned long PF :1; // Bit 13 +#else + unsigned long :1; // Bit 13 +#endif +#if (LIBCFG_SDIO) + unsigned long SDIO :1; // Bit 14 +#else + unsigned long :1; // Bit 14 +#endif +#if (LIBCFG_AES) + unsigned long AES :1; // Bit 15 +#else + unsigned long :1; // Bit 15 +#endif + + unsigned long :1; // Bit 16 + unsigned long :1; // Bit 17 + unsigned long :1; // Bit 18 + unsigned long :1; // Bit 19 + unsigned long :1; // Bit 20 + unsigned long :1; // Bit 21 + unsigned long :1; // Bit 22 + unsigned long :1; // Bit 23 + + unsigned long :1; // Bit 24 + unsigned long :1; // Bit 25 + unsigned long :1; // Bit 26 + unsigned long :1; // Bit 27 + unsigned long :1; // Bit 28 + unsigned long :1; // Bit 29 + unsigned long :1; // Bit 30 + unsigned long :1; // Bit 31 + + /* Definitions of APB peripheral 0 reset */ + unsigned long I2C0 :1; // Bit 0 + unsigned long I2C1 :1; // Bit 1 + unsigned long :1; // Bit 2 + unsigned long :1; // Bit 3 + unsigned long SPI0 :1; // Bit 4 + unsigned long SPI1 :1; // Bit 5 + unsigned long :1; // Bit 6 + unsigned long :1; // Bit 7 + + unsigned long USART0 :1; // Bit 8 + unsigned long USART1 :1; // Bit 9 + unsigned long UART0 :1; // Bit 10 + unsigned long UART1 :1; // Bit 11 + unsigned long :1; // Bit 12 + unsigned long :1; // Bit 13 + unsigned long AFIO :1; // Bit 14 + unsigned long EXTI :1; // Bit 15 + + unsigned long :1; // Bit 16 + unsigned long :1; // Bit 17 + unsigned long :1; // Bit 18 + unsigned long :1; // Bit 19 + unsigned long :1; // Bit 20 + unsigned long :1; // Bit 21 + unsigned long :1; // Bit 22 + unsigned long :1; // Bit 23 + +#if (LIBCFG_SCI0) + unsigned long SCI0 :1; // Bit 24 +#else + unsigned long :1; // Bit 24 +#endif + unsigned long I2S :1; // Bit 25 + unsigned long :1; // Bit 26 +#if (LIBCFG_SCI1) + unsigned long SCI1 :1; // Bit 27 +#else + unsigned long :1; // Bit 27 +#endif + unsigned long :1; // Bit 28 + unsigned long :1; // Bit 29 + unsigned long :1; // Bit 30 + unsigned long :1; // Bit 31 + + /* Definitions of APB peripheral 1 reset */ + unsigned long MCTM0 :1; // Bit 0 + unsigned long MCTM1 :1; // Bit 1 + unsigned long :1; // Bit 2 + unsigned long :1; // Bit 3 + unsigned long WDT :1; // Bit 4 + unsigned long :1; // Bit 5 + unsigned long :1; // Bit 6 + unsigned long :1; // Bit 7 + + unsigned long GPTM0 :1; // Bit 8 + unsigned long GPTM1 :1; // Bit 9 + unsigned long :1; // Bit 10 + unsigned long :1; // Bit 11 + unsigned long PWM0 :1; // Bit 12 + unsigned long :1; // Bit 13 + unsigned long :1; // Bit 14 + unsigned long :1; // Bit 15 + + unsigned long BFTM0 :1; // Bit 16 + unsigned long BFTM1 :1; // Bit 17 + unsigned long :1; // Bit 18 + unsigned long :1; // Bit 19 + unsigned long :1; // Bit 20 + unsigned long :1; // Bit 21 +#if (LIBCFG_CMP_OPA) + unsigned long OPA0 :1; // Bit 22 +#else + unsigned long CMP :1; // Bit 22 +#endif +#if (LIBCFG_CMP_OPA) + unsigned long OPA1 :1; // Bit 23 +#else + unsigned long :1; // Bit 23 +#endif + + unsigned long ADC0 :1; // Bit 24 + unsigned long :1; // Bit 25 + unsigned long :1; // Bit 26 + unsigned long :1; // Bit 27 + unsigned long SCTM0 :1; // Bit 28 + unsigned long SCTM1 :1; // Bit 29 + unsigned long :1; // Bit 30 + unsigned long :1; // Bit 31 + } Bit; + u32 Reg[3]; +} RSTCU_PeripReset_TypeDef; + +/** + * @} + */ + + +/* Exported constants --------------------------------------------------------------------------------------*/ +/** @defgroup RSTCU_Exported_Constants RSTCU exported constants + * @{ + */ + +/* Other definitions */ +#define IS_RSTCU_FLAG(FLAG) ((FLAG == RSTCU_FLAG_SYSRST) || \ + (FLAG == RSTCU_FLAG_EXTRST) || \ + (FLAG == RSTCU_FLAG_WDTRST) || \ + (FLAG == RSTCU_FLAG_PORST)) +/** + * @} + */ + +/* Exported functions --------------------------------------------------------------------------------------*/ +/** @defgroup RSTCU_Exported_Functions RSTCU exported functions + * @{ + */ +FlagStatus RSTCU_GetResetFlagStatus(RSTCU_RSTF_TypeDef RSTCU_RSTF); +void RSTCU_ClearResetFlag(RSTCU_RSTF_TypeDef RSTCU_RSTF); +void RSTCU_ClearAllResetFlag(void); +void RSTCU_PeripReset(RSTCU_PeripReset_TypeDef Reset, ControlStatus Cmd); + +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/inc/ht32f1xxxx_rtc.h b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/inc/ht32f1xxxx_rtc.h new file mode 100644 index 0000000000..f2e50b49f9 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/inc/ht32f1xxxx_rtc.h @@ -0,0 +1,245 @@ +/*********************************************************************************************************//** + * @file ht32f1xxxx_rtc.h + * @version $Rev:: 2971 $ + * @date $Date:: 2023-10-25 #$ + * @brief The header file of the RTC library. + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------------------------------------*/ +#ifndef __HT32F1XXXX_RTC_H +#define __HT32F1XXXX_RTC_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------------------------------------*/ +#include "ht32.h" + +/** @addtogroup HT32F1xxxx_Peripheral_Driver HT32F1xxxx Peripheral Driver + * @{ + */ + +/** @addtogroup RTC + * @{ + */ + + +/* Exported types ------------------------------------------------------------------------------------------*/ +/** @defgroup RTC_Exported_Types RTC exported types + * @{ + */ + +/** + * @brief Selection of RTC clock source + */ +typedef enum +{ + RTC_SRC_LSI = 0, /*!< Low speed internal clock, about 32 kHz */ + RTC_SRC_LSE /*!< Low speed external 32768 Hz clock */ +} RTC_SRC_Enum; +/** + * @brief Selection of RTC LSE startup mode + */ +typedef enum +{ + RTC_LSESM_NORMAL = 0, /*!< Little power consumption but longer startup time. */ + RTC_LSESM_FAST /*!< Shortly startup time but higher power consumption. */ +} RTC_LSESM_Enum; +/** + * @brief Selection of RTC prescaler + */ +typedef enum +{ + RTC_RPRE_1 = 0x0000, /*!< CK_SECOND = CK_RTC */ + RTC_RPRE_2 = 0x0100, /*!< CK_SECOND = CK_RTC / 2 */ + RTC_RPRE_4 = 0x0200, /*!< CK_SECOND = CK_RTC / 4 */ + RTC_RPRE_8 = 0x0300, /*!< CK_SECOND = CK_RTC / 8 */ + RTC_RPRE_16 = 0x0400, /*!< CK_SECOND = CK_RTC / 16 */ + RTC_RPRE_32 = 0x0500, /*!< CK_SECOND = CK_RTC / 32 */ + RTC_RPRE_64 = 0x0600, /*!< CK_SECOND = CK_RTC / 64 */ + RTC_RPRE_128 = 0x0700, /*!< CK_SECOND = CK_RTC / 128 */ + RTC_RPRE_256 = 0x0800, /*!< CK_SECOND = CK_RTC / 256 */ + RTC_RPRE_512 = 0x0900, /*!< CK_SECOND = CK_RTC / 512 */ + RTC_RPRE_1024 = 0x0A00, /*!< CK_SECOND = CK_RTC / 1024 */ + RTC_RPRE_2048 = 0x0B00, /*!< CK_SECOND = CK_RTC / 2048 */ + RTC_RPRE_4096 = 0x0C00, /*!< CK_SECOND = CK_RTC / 4096 */ + RTC_RPRE_8192 = 0x0D00, /*!< CK_SECOND = CK_RTC / 8192 */ + RTC_RPRE_16384 = 0x0E00, /*!< CK_SECOND = CK_RTC / 16384 */ + RTC_RPRE_32768 = 0x0F00 /*!< CK_SECOND = CK_RTC / 32768 */ +} RTC_RPRE_Enum; +/** + * @brief Active polarity of RTC output + */ +typedef enum +{ + RTC_ROAP_HIGH = 0, /*!< Active level is high */ + RTC_ROAP_LOW /*!< Active level is low */ +} RTC_ROAP_Enum; +/** + * @brief Waveform mode of RTC output + */ +typedef enum +{ + RTC_ROWM_PULSE = 0, /*!< Pulse mode. */ + RTC_ROWM_LEVEL /*!< Level mode. */ +} RTC_ROWM_Enum; +/** + * @brief Waveform mode of RTC output + */ +typedef enum +{ + RTC_ROES_MATCH = 0, /*!< Selected RTC compare match. */ + RTC_ROES_SECOND /*!< Selected RTC second clock. */ +} RTC_ROES_Enum; +/** + * @} + */ + +/* Exported constants --------------------------------------------------------------------------------------*/ +/** @defgroup RTC_Exported_Constants RTC exported constants + * @{ + */ + +/** @defgroup RTC_WAKEUP Selection of RTC wakeup source + * @{ + */ +#define RTC_WAKEUP_CSEC 0x00000100 +#define RTC_WAKEUP_CM 0x00000200 +#define RTC_WAKEUP_OV 0x00000400 +/** + * @} + */ + +/** @defgroup RTC_IT RTC Selection of interrupt source + * @{ + */ +#define RTC_INT_CSEC 0x00000001 +#define RTC_INT_CM 0x00000002 +#define RTC_INT_OV 0x00000004 +/** + * @} + */ + +/** @defgroup RTC_FLAG RTC Definitions of flags + * @{ + */ +#define RTC_FLAG_CSEC 0x00000001 +#define RTC_FLAG_CM 0x00000002 +#define RTC_FLAG_OV 0x00000004 +/** + * @} + */ + +/** @defgroup RTC_Check_Parameter Selection of Vdd18 power good + * @{ + */ + +/** + * @brief Used to check RTC_SRC_Enum parameter + */ +#define IS_RTC_SRC(x) ((x == RTC_SRC_LSI) || (x == RTC_SRC_LSE)) +/** + * @brief Used to check RTC_LSESM_Enum parameter + */ +#define IS_RTC_LSESM(x) ((x == RTC_LSESM_NORMAL) || (x == RTC_LSESM_FAST)) +/** + * @brief Used to check RTC_RPRE_Enum parameter + */ +#define IS_RTC_PSC(x) ((x == RTC_RPRE_1) || (x == RTC_RPRE_2) || (x == RTC_RPRE_4) ||\ + (x == RTC_RPRE_8) || (x == RTC_RPRE_16) || (x == RTC_RPRE_32) ||\ + (x == RTC_RPRE_64) || (x == RTC_RPRE_128) || (x == RTC_RPRE_256) ||\ + (x == RTC_RPRE_512) || (x == RTC_RPRE_1024) || (x == RTC_RPRE_2048) ||\ + (x == RTC_RPRE_4096) || (x == RTC_RPRE_8192) || (x == RTC_RPRE_16384) ||\ + (x == RTC_RPRE_32768)) +/** + * @brief Used to check RTC_ROAP_Enum parameter + */ +#define IS_RTC_ROAP(x) ((x == RTC_ROAP_HIGH) || (x == RTC_ROAP_LOW)) +/** + * @brief Used to check RTC_ROWM_Enum parameter + */ +#define IS_RTC_ROWM(x) ((x == RTC_ROWM_PULSE) || (x == RTC_ROWM_LEVEL)) +/** + * @brief Used to check RTC_ROES_Enum parameter + */ +#define IS_RTC_ROES(x) ((x == RTC_ROES_MATCH) || (x == RTC_ROES_SECOND)) +/** + * @brief Used to check RTC_WAKEUP parameter + */ +#define IS_RTC_WAKEUP(x) ((((x) & (u32)0xFFFFF8FF) == 0x00) && ((x) != 0x00)) +/** + * @brief Used to check RTC_INT parameter + */ +#define IS_RTC_INT(x) ((((x) & (u32)0xFFFFFFF8) == 0x00) && ((x) != 0x00)) +/** + * @brief Used to check RTC_FLAG parameter + */ +#define IS_RTC_FLAG(x) ((((x) & (u32)0xFFFFFFF8) == 0x00) && ((x) != 0x00)) +/** + * @} + */ + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------------------------------------*/ +/** @defgroup RTC_Exported_Functions RTC exported functions + * @{ + */ +void RTC_DeInit(void); +void RTC_ClockSourceConfig(RTC_SRC_Enum Source); +void RTC_LSESMConfig(RTC_LSESM_Enum Mode); +void RTC_LSECmd(ControlStatus NewState); +void RTC_CMPCLRCmd(ControlStatus NewState); +void RTC_SetPrescaler(RTC_RPRE_Enum Psc); +u16 RTC_GetPrescaler(void); +void RTC_Cmd(ControlStatus NewState); +u32 RTC_GetCounter(void); +void RTC_SetCompare(u32 Compare); +u32 RTC_GetCompare(void); +void RTC_WakeupConfig(u32 RTC_WAKEUP, ControlStatus NewState); +void RTC_IntConfig(u32 RTC_INT, ControlStatus NewState); +u8 RTC_GetFlagStatus(void); +void RTC_OutConfig(RTC_ROWM_Enum WMode, RTC_ROES_Enum EventSel, RTC_ROAP_Enum Pol); +void RTC_OutCmd(ControlStatus NewState); +FlagStatus RTC_GetOutStatus(void); +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/inc/ht32f1xxxx_sci.h b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/inc/ht32f1xxxx_sci.h new file mode 100644 index 0000000000..7118c1c42c --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/inc/ht32f1xxxx_sci.h @@ -0,0 +1,278 @@ +/*********************************************************************************************************//** + * @file ht32f1xxxx_sci.h + * @version $Rev:: 122 $ + * @date $Date:: 2017-06-13 #$ + * @brief The header file of the SCI library. + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------------------------------------*/ +#ifndef __HT32F1XXXX_SCI_H +#define __HT32F1XXXX_SCI_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------------------------------------*/ +#include "ht32.h" + +/** @addtogroup HT32F1xxxx_Peripheral_Driver HT32F1xxxx Peripheral Driver + * @{ + */ + +/** @addtogroup SCI + * @{ + */ + + +/* Exported types ------------------------------------------------------------------------------------------*/ +/** @defgroup SCI_Exported_Types SCI exported types + * @{ + */ +typedef struct +{ + u32 SCI_Mode; + u32 SCI_Retry; + u32 SCI_Convention; + u32 SCI_CardPolarity; + u32 SCI_ClockPrescale; +} SCI_InitTypeDef; +/** + * @} + */ + +/* Exported constants --------------------------------------------------------------------------------------*/ +/** @defgroup SCI_Exported_Constants SCI exported constants + * @{ + */ +#define SCI_MODE_MANUAL ((u32)0x00000000) +#define SCI_MODE_SCI ((u32)0x00000008) + +#define IS_SCI_MODE(MODE) ((MODE == SCI_MODE_MANUAL) || \ + (MODE == SCI_MODE_SCI)) + + +#define SCI_RETRY_NO ((u32)0x00000000) +#define SCI_RETRY_4 ((u32)0x00000012) +#define SCI_RETRY_5 ((u32)0x00000002) + +#define IS_SCI_RETRY(RETRY) ((RETRY == SCI_RETRY_NO) || \ + (RETRY == SCI_RETRY_4) || \ + (RETRY == SCI_RETRY_5)) + + +#define SCI_CONVENTION_DIRECT ((u32)0x00000000) +#define SCI_CONVENTION_INVERSE ((u32)0x00000001) + +#define IS_SCI_CONVENTION(CONVENTION) ((CONVENTION == SCI_CONVENTION_DIRECT) || \ + (CONVENTION == SCI_CONVENTION_INVERSE)) + + +#define SCI_CARDPOLARITY_LOW ((u32)0x00000000) +#define SCI_CARDPOLARITY_HIGH ((u32)0x00000040) + +#define IS_SCI_CARD_POLARITY(POLARITY) ((POLARITY == SCI_CARDPOLARITY_LOW) || \ + (POLARITY == SCI_CARDPOLARITY_HIGH)) + + +#define SCI_CLKPRESCALER_1 ((u32)0x00000000) +#define SCI_CLKPRESCALER_2 ((u32)0x00000001) +#define SCI_CLKPRESCALER_4 ((u32)0x00000002) +#define SCI_CLKPRESCALER_6 ((u32)0x00000003) +#define SCI_CLKPRESCALER_8 ((u32)0x00000004) +#define SCI_CLKPRESCALER_10 ((u32)0x00000005) +#define SCI_CLKPRESCALER_12 ((u32)0x00000006) +#define SCI_CLKPRESCALER_14 ((u32)0x00000007) +#define SCI_CLKPRESCALER_16 ((u32)0x00000008) +#define SCI_CLKPRESCALER_18 ((u32)0x00000009) +#define SCI_CLKPRESCALER_20 ((u32)0x0000000A) +#define SCI_CLKPRESCALER_22 ((u32)0x0000000B) +#define SCI_CLKPRESCALER_24 ((u32)0x0000000C) +#define SCI_CLKPRESCALER_26 ((u32)0x0000000D) +#define SCI_CLKPRESCALER_28 ((u32)0x0000000E) +#define SCI_CLKPRESCALER_30 ((u32)0x0000000F) +#define SCI_CLKPRESCALER_32 ((u32)0x00000010) +#define SCI_CLKPRESCALER_34 ((u32)0x00000011) +#define SCI_CLKPRESCALER_36 ((u32)0x00000012) +#define SCI_CLKPRESCALER_38 ((u32)0x00000013) +#define SCI_CLKPRESCALER_40 ((u32)0x00000014) +#define SCI_CLKPRESCALER_42 ((u32)0x00000015) +#define SCI_CLKPRESCALER_44 ((u32)0x00000016) +#define SCI_CLKPRESCALER_46 ((u32)0x00000017) +#define SCI_CLKPRESCALER_48 ((u32)0x00000018) +#define SCI_CLKPRESCALER_50 ((u32)0x00000019) +#define SCI_CLKPRESCALER_52 ((u32)0x0000001A) +#define SCI_CLKPRESCALER_54 ((u32)0x0000001B) +#define SCI_CLKPRESCALER_56 ((u32)0x0000001C) +#define SCI_CLKPRESCALER_58 ((u32)0x0000001D) +#define SCI_CLKPRESCALER_60 ((u32)0x0000001E) +#define SCI_CLKPRESCALER_62 ((u32)0x0000001F) +#define SCI_CLKPRESCALER_64 ((u32)0x00000020) +#define SCI_CLKPRESCALER_66 ((u32)0x00000021) +#define SCI_CLKPRESCALER_68 ((u32)0x00000022) +#define SCI_CLKPRESCALER_70 ((u32)0x00000023) +#define SCI_CLKPRESCALER_72 ((u32)0x00000024) +#define SCI_CLKPRESCALER_74 ((u32)0x00000025) +#define SCI_CLKPRESCALER_76 ((u32)0x00000026) +#define SCI_CLKPRESCALER_78 ((u32)0x00000027) +#define SCI_CLKPRESCALER_80 ((u32)0x00000028) +#define SCI_CLKPRESCALER_82 ((u32)0x00000029) +#define SCI_CLKPRESCALER_84 ((u32)0x0000002A) +#define SCI_CLKPRESCALER_86 ((u32)0x0000002B) +#define SCI_CLKPRESCALER_88 ((u32)0x0000002C) +#define SCI_CLKPRESCALER_90 ((u32)0x0000002D) +#define SCI_CLKPRESCALER_92 ((u32)0x0000002E) +#define SCI_CLKPRESCALER_94 ((u32)0x0000002F) +#define SCI_CLKPRESCALER_96 ((u32)0x00000030) +#define SCI_CLKPRESCALER_98 ((u32)0x00000031) +#define SCI_CLKPRESCALER_100 ((u32)0x00000032) +#define SCI_CLKPRESCALER_102 ((u32)0x00000033) +#define SCI_CLKPRESCALER_104 ((u32)0x00000034) +#define SCI_CLKPRESCALER_106 ((u32)0x00000035) +#define SCI_CLKPRESCALER_108 ((u32)0x00000036) +#define SCI_CLKPRESCALER_110 ((u32)0x00000037) +#define SCI_CLKPRESCALER_112 ((u32)0x00000038) +#define SCI_CLKPRESCALER_114 ((u32)0x00000039) +#define SCI_CLKPRESCALER_116 ((u32)0x0000003A) +#define SCI_CLKPRESCALER_118 ((u32)0x0000003B) +#define SCI_CLKPRESCALER_120 ((u32)0x0000003C) +#define SCI_CLKPRESCALER_122 ((u32)0x0000003D) +#define SCI_CLKPRESCALER_124 ((u32)0x0000003E) +#define SCI_CLKPRESCALER_126 ((u32)0x0000003F) + +#define IS_SCI_CLOCK_PRESCALER(PRESCALER) (PRESCALER <= 0x3F) + + +#define SCI_COMPENSATION_ENABLE ((u32)0x00008000) +#define SCI_COMPENSATION_DISABLE ((u32)0x00000000) + +#define IS_SCI_ETU_COMPENSATION(COMPENSATION) ((COMPENSATION == SCI_COMPENSATION_ENABLE) || \ + (COMPENSATION == SCI_COMPENSATION_DISABLE)) + + +#define SCI_CLK_HARDWARE ((u32)0x00000080) +#define SCI_CLK_SOFTWARE ((u32)0xFFFFFF7F) + +#define IS_SCI_CLK_MODE(MODE) ((MODE == SCI_CLK_HARDWARE) || \ + (MODE == SCI_CLK_SOFTWARE)) + + +#define SCI_CLK_HIGH ((u32)0x00000004) +#define SCI_CLK_LOW ((u32)0xFFFFFFFB) + +#define IS_SCI_CLK(CLK) ((CLK == SCI_CLK_HIGH) || \ + (CLK == SCI_CLK_LOW)) + + +#define SCI_DIO_HIGH ((u32)0x00000008) +#define SCI_DIO_LOW ((u32)0xFFFFFFF7) + +#define IS_SCI_DIO(DIO) ((DIO == SCI_DIO_HIGH) || \ + (DIO == SCI_DIO_LOW)) + + +#define SCI_INT_PAR ((u32)0x00000001) +#define SCI_INT_RXC ((u32)0x00000002) +#define SCI_INT_TXC ((u32)0x00000004) +#define SCI_INT_WT ((u32)0x00000008) +#define SCI_INT_CARD ((u32)0x00000040) +#define SCI_INT_TXBE ((u32)0x00000080) +#define SCI_INT_ALL ((u32)0x000000CF) + +#define IS_SCI_INT(INT) (((INT & 0xFFFFFF30) == 0x0) && (INT != 0)) + + + +#define SCI_FLAG_PAR ((u32)0x00000001) +#define SCI_FLAG_RXC ((u32)0x00000002) +#define SCI_FLAG_TXC ((u32)0x00000004) +#define SCI_FLAG_WT ((u32)0x00000008) +#define SCI_FLAG_CARD ((u32)0x00000040) +#define SCI_FLAG_TXBE ((u32)0x00000080) + +#define IS_SCI_FLAG(FLAG) ((FLAG == SCI_FLAG_PAR) || \ + (FLAG == SCI_FLAG_RXC) || \ + (FLAG == SCI_FLAG_TXC) || \ + (FLAG == SCI_FLAG_WT) || \ + (FLAG == SCI_FLAG_CARD) || \ + (FLAG == SCI_FLAG_TXBE)) + +#define IS_SCI_CLEAR_FLAG(FLAG) ((FLAG == SCI_FLAG_PAR) || \ + (FLAG == SCI_FLAG_TXC) || \ + (FLAG == SCI_FLAG_WT)) + + +#define SCI_PDMAREQ_TX ((u32)0x00000100) +#define SCI_PDMAREQ_RX ((u32)0x00000200) + +#define IS_SCI_PDMA_REQ(REQ) (((REQ & 0xFFFFFCFF) == 0x0) && (REQ != 0)) + + +#define IS_SCI_ETU(ETU) ((ETU >= 12) & (ETU <= 2047)) + +#define IS_SCI_GUARDTIME(GUARDTIME) ((GUARDTIME >= 11) & (GUARDTIME <= 511)) + +#define IS_SCI_WAITING_TIME(TIME) ((TIME >= 372) & (TIME <= 16777215)) +/** + * @} + */ + +/* Exported functions --------------------------------------------------------------------------------------*/ +/** @defgroup SCI_Exported_Functions SCI exported functions + * @{ + */ +void SCI_DeInit(HT_SCI_TypeDef* SCIx); +void SCI_Init(HT_SCI_TypeDef* SCIx, SCI_InitTypeDef* SCI_InitStruct); +void SCI_StructInit(SCI_InitTypeDef* SCI_InitStruct); +void SCI_Cmd(HT_SCI_TypeDef* SCIx, ControlStatus NewState); +void SCI_ETUConfig(HT_SCI_TypeDef* SCIx, u32 SCI_ETU, u32 SCI_Compensation); +void SCI_SetGuardTimeValue(HT_SCI_TypeDef* SCIx, u16 SCI_GuardTime); +void SCI_SetWaitingTimeValue(HT_SCI_TypeDef* SCIx, u32 SCI_WaitingTime); +void SCI_WaitingTimeCounterCmd(HT_SCI_TypeDef* SCIx, ControlStatus NewState); +void SCI_SendData(HT_SCI_TypeDef* SCIx, u8 SCI_Data); +u8 SCI_ReceiveData(HT_SCI_TypeDef* SCIx); +void SCI_ClockModeConfig(HT_SCI_TypeDef* SCIx, u32 SCI_CLKMode); +void SCI_SoftwareClockCmd(HT_SCI_TypeDef* SCIx, u32 SCI_CLK); +void SCI_OutputDIO(HT_SCI_TypeDef* SCIx, u32 SCI_DIO); +void SCI_IntConfig(HT_SCI_TypeDef* SCIx, u32 SCI_Int, ControlStatus NewState); +FlagStatus SCI_GetFlagStatus(HT_SCI_TypeDef* SCIx, u32 SCI_Flag); +void SCI_ClearFlag(HT_SCI_TypeDef* SCIx, u32 SCI_Flag); +void SCI_PDMACmd(HT_SCI_TypeDef* SCIx, u32 SCI_PDMAREQ, ControlStatus NewState); +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/inc/ht32f1xxxx_sdio.h b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/inc/ht32f1xxxx_sdio.h new file mode 100644 index 0000000000..4a62ce7db4 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/inc/ht32f1xxxx_sdio.h @@ -0,0 +1,413 @@ +/*********************************************************************************************************//** + * @file ht32f1xxxx_sdio.h + * @version $Rev:: 2458 $ + * @date $Date:: 2021-08-05 #$ + * @brief The header file of the SDIO library. + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------------------------------------*/ +#ifndef __HT32F1XXXX_SDIO_H +#define __HT32F1XXXX_SDIO_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------------------------------------*/ +#include "ht32.h" + +/** @addtogroup HT32F1xxxx_Peripheral_Driver HT32F1xxxx Peripheral Driver + * @{ + */ + +/** @addtogroup SDIO + * @{ + */ + + +/* Exported types ------------------------------------------------------------------------------------------*/ +/** @defgroup SDIO_Exported_Types SDIO exported types + * @{ + */ +typedef struct +{ + u32 SDIO_ClockDiv; /*!< Specify the SDIO clock divider value. + This parameter can be a value between 1 and 256. */ + + u32 SDIO_ClockPeriod; /*!< Specify whether SDIO clock has longer or shorter low period + when the SDIO clock divider value is odd. + This parameter can be a value of @ref SDIO_Clock_Period */ + + u32 SDIO_ClockPowerSave; /*!< Specify whether SDIO clock output is enabled or disabled + when the bus is idle. + This parameter can be a value of @ref SDIO_Clock_Power_Save */ + + u32 SDIO_BusWide; /*!< Specify the SDIO bus width. + This parameter can be a value of @ref SDIO_Bus_Wide */ + + u32 SDIO_BusMode; /*!< Specify the SDIO bus Mode. + This parameter can be a value of @ref SDIO_Bus_Mode */ +} SDIO_InitTypeDef; + + +typedef struct +{ + u32 SDIO_Argument; /*!< Specify the SDIO command argument which is sent + to a card as part of a command message. If a command + contains an argument, it must be loaded into this register + before writing the command to the command register */ + + u32 SDIO_CmdIndex; /*!< Specify the SDIO command index. It must be lower than 0x40. */ + + u32 SDIO_Response; /*!< Specify the SDIO response type. + This parameter can be a value of @ref SDIO_Response_Type */ + + u32 SDIO_DatPresent; /*!< Specify whether data is present on the SDIO data line + after SDIO command or not. + This parameter can be a value of @ref SDIO_Data_Present */ + + u32 SDIO_CmdIdxChk; /*!< Specify whether SDIO command index check function is enabled or not. + This parameter can be a value of @ref SDIO_CmdIdx_Check */ + + u32 SDIO_CmdCrcChk; /*!< Specify whether SDIO command CRC check function is enabled or not. + This parameter can be a value of @ref SDIO_CmdCrc_Check */ +} SDIO_CmdInitTypeDef; + + +typedef struct +{ + u32 SDIO_DataBlockCount; /*!< Specify the number of data block count to be transferred. + This parameter can be a value between 1 and 65535. */ + + u32 SDIO_DataBlockSize; /*!< Specify the data block size for block transfer. + This parameter can be a value between 1 and 2048. */ + + u32 SDIO_TransferDir; /*!< Specify the data transfer direction, whether the transfer + is a read or write. + This parameter can be a value of @ref SDIO_Transfer_Direction */ + + u32 SDIO_TransferMode; /*!< Specify whether data transfer is in single block or multi-block mode. + This parameter can be a value of @ref SDIO_Transfer_Mode */ + + u32 SDIO_DataTimeOut; /*!< Specify the data timeout period in card bus clock periods. + This parameter can be a value between 0x1 and 0x00ffffff. */ + +} SDIO_DataInitTypeDef; +/** + * @} + */ + +/* Exported constants --------------------------------------------------------------------------------------*/ +/** @defgroup SDIO_Exported_Constants SDIO exported constants + * @{ + */ + +/** @defgroup SDIO_Clock_Div SDIO Clock Div + * @{ + */ +#define IS_SDIO_CLOC_DIV(DIV) ((DIV > 0) && (DIV < 256)) +/** + * @} + */ + +/** @defgroup SDIO_Clock_Period SDIO Clock Period + * @{ + */ +#define SDIO_Clock_LowPeriod_Shorter (0x00000000) +#define SDIO_Clock_LowPeriod_Longer (0x00000008) + +#define IS_SDIO_CLOCK_PERIOD(PERIOD) (((PERIOD) == SDIO_Clock_LowPeriod_Shorter) || \ + ((PERIOD) == SDIO_Clock_LowPeriod_Longer)) +/** + * @} + */ + +/** @defgroup SDIO_Clock_Power_Save SDIO Clock Power Save + * @{ + */ +#define SDIO_Clock_PowerSave_Disable (0x00000000) +#define SDIO_Clock_PowerSave_StopLow (0x00000002) +#define SDIO_Clock_PowerSave_StopHigh (0x00000003) + +#define IS_SDIO_CLOCK_POWER_SAVE(SAVE) (((SAVE) == SDIO_Clock_PowerSave_Disable) || \ + ((SAVE) == SDIO_Clock_PowerSave_StopLow) || \ + ((SAVE) == SDIO_Clock_PowerSave_StopHigh)) +/** + * @} + */ + +/** @defgroup SDIO_Bus_Wide SDIO Bus Wide + * @{ + */ +#define SDIO_BusWide_1b (0x00000000) +#define SDIO_BusWide_4b (0x00000002) + +#define IS_SDIO_BUS_WIDE(WIDE) (((WIDE) == SDIO_BusWide_1b) || \ + ((WIDE) == SDIO_BusWide_4b)) +/** + * @} + */ + +/** @defgroup SDIO_Bus_Mode SDIO Bus Mode + * @{ + */ +#define SDIO_BusMode_NormalSpeed (0x00000000) +#define SDIO_BusMode_HighSpeed (0x00000004) + +#define IS_SDIO_BUS_MODE(MODE) (((MODE) == SDIO_BusMode_NormalSpeed) || \ + ((MODE) == SDIO_BusMode_HighSpeed)) +/** + * @} + */ + +/** @defgroup SDIO_Command_Index SDIO Command Index + * @{ + */ +#define IS_SDIO_CMD_INDEX(INDEX) ((INDEX) < 0x40) +/** + * @} + */ + +/** @defgroup SDIO_Response_Type SDIO Response Type + * @{ + */ +#define SDIO_Response_No (0x00000000) +#define SDIO_Response_Long (0x00000001) +#define SDIO_Response_Short (0x00000002) + +#define IS_SDIO_RESPONSE(RESPONSE) (((RESPONSE) == SDIO_Response_No) || \ + ((RESPONSE) == SDIO_Response_Short) || \ + ((RESPONSE) == SDIO_Response_Long)) +/** + * @} + */ + +/** @defgroup SDIO_Data_Present SDIO Data Present + * @{ + */ +#define SDIO_Data_Present_No (0x00000000) +#define SDIO_Data_Present_Yes (0x00000020) + +#define IS_SDIO_DATA_PRESENT(PRESENT) (((PRESENT) == SDIO_Data_Present_No) || \ + ((PRESENT) == SDIO_Data_Present_Yes)) +/** + * @} + */ + +/** @defgroup SDIO_CmdIdx_Check SDIO CmdIdx Check + * @{ + */ +#define SDIO_CmdIdxChk_No (0x00000000) +#define SDIO_CmdIdxChk_Yes (0x00000010) + +#define IS_SDIO_CMD_IDX_CHK(CHK) (((CHK) == SDIO_CmdIdxChk_No) || \ + ((CHK) == SDIO_CmdIdxChk_Yes)) +/** + * @} + */ + +/** @defgroup SDIO_CmdCrc_Check SDIO CmdCrc Check + * @{ + */ +#define SDIO_CmdCrcChk_No (0x00000000) +#define SDIO_CmdCrcChk_Yes (0x00000008) + +#define IS_SDIO_CMD_CRC_CHK(CHK) (((CHK) == SDIO_CmdCrcChk_No) || \ + ((CHK) == SDIO_CmdCrcChk_Yes)) +/** + * @} + */ + +/** @defgroup SDIO_Data_Block_Count SDIO Data Block Count + * @{ + */ +#define IS_SDIO_DATA_BLOCK_COUNT(COUNT) ((COUNT > 0) && (COUNT <= 65535)) +/** + * @} + */ + +/** @defgroup SDIO_Data_Block_Size SDIO Data Block Size + * @{ + */ +#define IS_SDIO_DATA_BLOCK_SIZE(SIZE) ((SIZE > 0) && (SIZE <= 2048)) +/** + * @} + */ + +/** @defgroup SDIO_Transfer_Mode SDIO Transfer Mode + * @{ + */ +#define SDIO_SingleBlock_Transfer (0x00000000) +#define SDIO_MultiBlock_Transfer (0x00000022) +#define SDIO_SingleBlock_DMA_Transfer (0x00000100) +#define SDIO_MultiBlock_DMA_Transfer (0x00000122) + +#define IS_SDIO_TRANSFER_MODE(MODE) (((MODE) == SDIO_SingleBlock_Transfer) || \ + ((MODE) == SDIO_MultiBlock_Transfer) || \ + ((MODE) == SDIO_SingleBlock_DMA_Transfer) || \ + ((MODE) == SDIO_MultiBlock_DMA_Transfer)) +/** + * @} + */ +/** @defgroup SDIO_Transfer_Direction SDIO Transfer Direction + * @{ + */ +#define SDIO_TransferDir_ToCard (0x00000000) +#define SDIO_TransferDir_ToSDIO (0x00000010) + +#define IS_SDIO_TRANSFER_DIR(DIR) (((DIR) == SDIO_TransferDir_ToCard) || \ + ((DIR) == SDIO_TransferDir_ToSDIO)) +/** + * @} + */ + + +/** @defgroup SDIO_Data_TimeOut SDIO Data TimeOut + * @{ + */ +#define IS_SDIO_DATA_TIMEOUT(TIME) ((TIME > 0) && (TIME <= 0x00ffffff)) +/** + * @} + */ + +/** @defgroup SDIO_Flags SDIO Flags + * @{ + */ +#define SDIO_FLAG_CMD_SEND (0x00000001) +#define SDIO_FLAG_TRANS_END (0x00000002) +#define SDIO_FLAG_BUF_OVERFLOW (0x00000008) +#define SDIO_FLAG_BUF_UNDERFLOW (0x00000010) +#define SDIO_FLAG_BUF_HALF (0x00000020) +#define SDIO_FLAG_BUF_FULL (0x00000040) +#define SDIO_FLAG_BUF_EMPTY (0x00000080) +#define SDIO_FLAG_ERR (0x00008000) +#define SDIO_FLAG_CMD_TIMEOUT (0x00010000) +#define SDIO_FLAG_CMD_CRCERR (0x00020000) +#define SDIO_FLAG_CMD_ENDERR (0x00040000) +#define SDIO_FLAG_CMD_IDXERR (0x00080000) +#define SDIO_FLAG_DATA_TIMEOUT (0x00100000) +#define SDIO_FLAG_DATA_CRCERR (0x00200000) +#define SDIO_FLAG_DATA_ENDERR (0x00400000) +#define SDIO_FLAG_CARD_INT (0x01000000) +#define SDIO_FLAG_DAT_ERR (0x02000000) +#define SDIO_FLAG_CMD_ERR (0x04000000) + +#define IS_SDIO_FLAG(FLAG) (((FLAG) != 0) && (((FLAG) & 0x077F80FB) != 0)) +/** + * @} + */ + +/** @defgroup SDIO_Response_Registers SDIO Response Registers + * @{ + */ +#define SDIO_RESP1 (0x00000000) +#define SDIO_RESP2 (0x00000004) +#define SDIO_RESP3 (0x00000008) +#define SDIO_RESP4 (0x0000000C) + +#define IS_SDIO_RESP(RESP) (((RESP) == SDIO_RESP1) || \ + ((RESP) == SDIO_RESP2) || \ + ((RESP) == SDIO_RESP3) || \ + ((RESP) == SDIO_RESP4)) +/** + * @} + */ + +/** @defgroup SDIO_Interrupt_sources SDIO Interrupt sources + * @{ + */ +#define SDIO_INT_CMD_SEND (0x00000001) +#define SDIO_INT_TRANS_END (0x00000002) +#define SDIO_INT_BUF_OVERFLOW (0x00000008) +#define SDIO_INT_BUF_UNDERFLOW (0x00000010) +#define SDIO_INT_BUF_HALF (0x00000020) +#define SDIO_INT_BUF_FULL (0x00000040) +#define SDIO_INT_BUF_EMPTY (0x00000080) +#define SDIO_INT_CMD_TIMEOUT (0x00010000) +#define SDIO_INT_CMD_CRCERR (0x00020000) +#define SDIO_INT_CMD_IDXERR (0x00080000) +#define SDIO_INT_DATA_TIMEOUT (0x00100000) +#define SDIO_INT_DATA_CRCERR (0x00200000) +#define SDIO_INT_CARD_INT (0x01000000) + +#define IS_SDIO_INT(INT) (((INT) != 0) && (((INT) & 0x013B00FB) != 0)) +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------------------------------------*/ +/** @defgroup SDIO_Exported_Macro SDIO exported macro + * @{ + */ +#define RESET_CPSM() {\ + HT_SDIO->SWRST |= (1UL << 1);\ + while (HT_SDIO->SWRST & (1UL << 1));\ + } + +#define RESET_DPSM() {\ + HT_SDIO->SWRST |= (1UL << 2);\ + while (HT_SDIO->SWRST & (1UL << 2));\ + } +/** + * @} + */ + +/* Exported functions --------------------------------------------------------------------------------------*/ +/** @defgroup SDIO_Exported_Functions SDIO exported functions + * @{ + */ +void SDIO_DeInit(void); +void SDIO_Init(SDIO_InitTypeDef* SDIO_InitStruct); +void SDIO_ClockCmd(ControlStatus Cmd); +u32 SDIO_ReadData(void); +void SDIO_WriteData(u32 Data); +u32 SDIO_GetFIFOCount(void); +void SDIO_SendCommand(SDIO_CmdInitTypeDef *SDIO_CmdInitStruct); +u32 SDIO_GetResponse(u32 SDIO_RESP); +void SDIO_DataConfig(SDIO_DataInitTypeDef* SDIO_DataInitStruct); +void SDIO_FlagConfig(u32 SDIO_FLAG, ControlStatus NewState); +FlagStatus SDIO_GetFlagStatus(u32 SDIO_FLAG); +void SDIO_ClearFlag(u32 SDIO_FLAG); +void SDIO_IntConfig(u32 SDIO_INT, ControlStatus NewState); +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/inc/ht32f1xxxx_spi.h b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/inc/ht32f1xxxx_spi.h new file mode 100644 index 0000000000..d69c32afbf --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/inc/ht32f1xxxx_spi.h @@ -0,0 +1,297 @@ +/*********************************************************************************************************//** + * @file ht32f1xxxx_spi.h + * @version $Rev:: 2797 $ + * @date $Date:: 2022-11-28 #$ + * @brief The header file of the SPI library. + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------------------------------------*/ +#ifndef __HT32F1XXXX_SPI_H +#define __HT32F1XXXX_SPI_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------------------------------------*/ +#include "ht32.h" + +/** @addtogroup HT32F1xxxx_Peripheral_Driver HT32F1xxxx Peripheral Driver + * @{ + */ + +/** @addtogroup SPI + * @{ + */ + + +/* Exported types ------------------------------------------------------------------------------------------*/ +/** @defgroup SPI_Exported_Types SPI exported types + * @{ + */ +typedef u16 SPI_DataTypeDef; +typedef u16 SPI_TimeoutTypeDef; + +typedef struct +{ + u32 SPI_Mode; + u32 SPI_FIFO; + u32 SPI_DataLength; + u32 SPI_SELMode; + u32 SPI_SELPolarity; + u32 SPI_CPOL; + u32 SPI_CPHA; + u32 SPI_FirstBit; + u32 SPI_RxFIFOTriggerLevel; + u32 SPI_TxFIFOTriggerLevel; + u32 SPI_ClockPrescaler; +} SPI_InitTypeDef; +/** + * @} + */ + +/* Exported constants --------------------------------------------------------------------------------------*/ +/** @defgroup SPI_Exported_Constants SPI exported constants + * @{ + */ +#define SPI_FIFO_ENABLE ((u32)0x00000400) +#define SPI_FIFO_DISABLE ((u32)0x00000000) + +#define IS_SPI_FIFO_SET(FIFO) ((FIFO == SPI_FIFO_ENABLE) || \ + (FIFO == SPI_FIFO_DISABLE)) + +#define SPI_DATALENGTH_1 ((u32)0x00000001) +#define SPI_DATALENGTH_2 ((u32)0x00000002) +#define SPI_DATALENGTH_3 ((u32)0x00000003) +#define SPI_DATALENGTH_4 ((u32)0x00000004) +#define SPI_DATALENGTH_5 ((u32)0x00000005) +#define SPI_DATALENGTH_6 ((u32)0x00000006) +#define SPI_DATALENGTH_7 ((u32)0x00000007) +#define SPI_DATALENGTH_8 ((u32)0x00000008) +#define SPI_DATALENGTH_9 ((u32)0x00000009) +#define SPI_DATALENGTH_10 ((u32)0x0000000A) +#define SPI_DATALENGTH_11 ((u32)0x0000000B) +#define SPI_DATALENGTH_12 ((u32)0x0000000C) +#define SPI_DATALENGTH_13 ((u32)0x0000000D) +#define SPI_DATALENGTH_14 ((u32)0x0000000E) +#define SPI_DATALENGTH_15 ((u32)0x0000000F) +#define SPI_DATALENGTH_16 ((u32)0x00000000) + +#define IS_SPI_DATALENGTH(DATALENGTH) ((DATALENGTH <= 0xF)) + + +#define SPI_MASTER ((u32)0x00004000) +#define SPI_SLAVE ((u32)0x00000000) + +#define IS_SPI_MODE(MODE) ((MODE == SPI_MASTER) || \ + (MODE == SPI_SLAVE)) + + +#define SPI_SEL_HARDWARE ((u32)0x00002000) +#define SPI_SEL_SOFTWARE ((u32)0x00000000) + +#define IS_SPI_SEL_MODE(SELMODE) ((SELMODE == SPI_SEL_HARDWARE) || \ + (SELMODE == SPI_SEL_SOFTWARE)) + + +#define SPI_SEL_ACTIVE ((u32)0x00000010) +#define SPI_SEL_INACTIVE ((u32)0xFFFFFFEF) + +#define IS_SPI_SOFTWARE_SEL(SEL) ((SEL == SPI_SEL_ACTIVE) || \ + (SEL == SPI_SEL_INACTIVE)) + + +#define SPI_SELPOLARITY_HIGH ((u32)0x00000800) +#define SPI_SELPOLARITY_LOW ((u32)0x00000000) + +#define IS_SPI_SEL_POLARITY(POLARITY) ((POLARITY == SPI_SELPOLARITY_HIGH) || \ + (POLARITY == SPI_SELPOLARITY_LOW)) + + +#define SPI_CPOL_HIGH ((u32)0x00000400) +#define SPI_CPOL_LOW ((u32)0x00000000) + +#define IS_SPI_CPOL(CPOL) ((CPOL == SPI_CPOL_HIGH) || \ + (CPOL == SPI_CPOL_LOW)) + + +#define SPI_CPHA_FIRST ((u32)0x00000000) +#define SPI_CPHA_SECOND ((u32)0x00000001) + +#define IS_SPI_CPHA(CPHA) ((CPHA == SPI_CPHA_FIRST) || \ + (CPHA == SPI_CPHA_SECOND)) + + +#define SPI_FIRSTBIT_LSB ((u32)0x00001000) +#define SPI_FIRSTBIT_MSB ((u32)0x00000000) + +#define IS_SPI_FIRST_BIT(BIT) ((BIT == SPI_FIRSTBIT_LSB) || \ + (BIT == SPI_FIRSTBIT_MSB)) + + +#define SPI_FLAG_TXBE ((u32)0x00000001) +#define SPI_FLAG_TXE ((u32)0x00000002) +#define SPI_FLAG_RXBNE ((u32)0x00000004) +#define SPI_FLAG_WC ((u32)0x00000008) +#define SPI_FLAG_RO ((u32)0x00000010) +#define SPI_FLAG_MF ((u32)0x00000020) +#define SPI_FLAG_SA ((u32)0x00000040) +#define SPI_FLAG_TOUT ((u32)0x00000080) +#define SPI_FLAG_BUSY ((u32)0x00000100) + +#define IS_SPI_FLAG(FLAG) ((FLAG == SPI_FLAG_TXBE) || \ + (FLAG == SPI_FLAG_TXE) || \ + (FLAG == SPI_FLAG_RXBNE) || \ + (FLAG == SPI_FLAG_WC) || \ + (FLAG == SPI_FLAG_RO) || \ + (FLAG == SPI_FLAG_MF) || \ + (FLAG == SPI_FLAG_SA) || \ + (FLAG == SPI_FLAG_TOUT) || \ + (FLAG == SPI_FLAG_BUSY)) + +#define IS_SPI_FLAG_CLEAR(CLEAR) ((CLEAR == SPI_FLAG_WC) || \ + (CLEAR == SPI_FLAG_RO) || \ + (CLEAR == SPI_FLAG_MF) || \ + (CLEAR == SPI_FLAG_SA) || \ + (CLEAR == SPI_FLAG_TOUT)) + + +#define SPI_INT_TXBE ((u32)0x00000001) +#define SPI_INT_TXE ((u32)0x00000002) +#define SPI_INT_RXBNE ((u32)0x00000004) +#define SPI_INT_WC ((u32)0x00000008) +#define SPI_INT_RO ((u32)0x00000010) +#define SPI_INT_MF ((u32)0x00000020) +#define SPI_INT_SA ((u32)0x00000040) +#define SPI_INT_TOUT ((u32)0x00000080) +#define SPI_INT_ALL ((u32)0x000000FF) + +#define IS_SPI_INT(SPI_INT) (((SPI_INT & 0xFFFFFF00) == 0x0) && (SPI_INT != 0x0)) + + +#define SPI_FIFO_TX ((u32)0x00000100) +#define SPI_FIFO_RX ((u32)0x00000200) + +#define IS_SPI_FIFO_DIRECTION(DIRECTION) (((DIRECTION & 0xFFFFFCFF) == 0) && (DIRECTION != 0)) + + +#define SPI_PDMAREQ_TX ((u32)0x00000002) +#define SPI_PDMAREQ_RX ((u32)0x00000004) + +#define IS_SPI_PDMA_REQ(REQ) (((REQ & 0xFFFFFFF9) == 0x0) && (REQ != 0x0)) + + +#define IS_SPI(SPI) ((SPI == HT_SPI0) || (SPI == HT_SPI1)) + +#define IS_SPI_DATA(DATA) (DATA <= 0xffff) + +#define IS_SPI_FIFO_LEVEL(LEVEL) (LEVEL <= 8) + +#define IS_SPI_CLOCK_PRESCALER(PRESCALER) (PRESCALER >= 2) + +#define SPI_GUADTIME_1_SCK ((u16)0x0000) +#define SPI_GUADTIME_2_SCK ((u16)0x0001) +#define SPI_GUADTIME_3_SCK ((u16)0x0002) +#define SPI_GUADTIME_4_SCK ((u16)0x0003) +#define SPI_GUADTIME_5_SCK ((u16)0x0004) +#define SPI_GUADTIME_6_SCK ((u16)0x0005) +#define SPI_GUADTIME_7_SCK ((u16)0x0006) +#define SPI_GUADTIME_8_SCK ((u16)0x0007) +#define SPI_GUADTIME_9_SCK ((u16)0x0008) +#define SPI_GUADTIME_10_SCK ((u16)0x0009) +#define SPI_GUADTIME_11_SCK ((u16)0x000A) +#define SPI_GUADTIME_12_SCK ((u16)0x000B) +#define SPI_GUADTIME_13_SCK ((u16)0x000C) +#define SPI_GUADTIME_14_SCK ((u16)0x000D) +#define SPI_GUADTIME_15_SCK ((u16)0x000E) +#define SPI_GUADTIME_16_SCK ((u16)0x000F) + +#define IS_SPI_GUADTIME(GUADTIMEPERIOD) ((GUADTIMEPERIOD <= 0x000F)) + + +#define SPI_SELHOLDTIME_HALF_SCK ((u16)0x0000) +#define SPI_SELHOLDTIME_1_SCK ((u16)0x0001) +#define SPI_SELHOLDTIME_1_HALF_SCK ((u16)0x0002) +#define SPI_SELHOLDTIME_2_SCK ((u16)0x0003) +#define SPI_SELHOLDTIME_2_HALF_SCK ((u16)0x0004) +#define SPI_SELHOLDTIME_3_SCK ((u16)0x0005) +#define SPI_SELHOLDTIME_3_HALF_SCK ((u16)0x0006) +#define SPI_SELHOLDTIME_4_SCK ((u16)0x0007) +#define SPI_SELHOLDTIME_4_HALF_SCK ((u16)0x0008) +#define SPI_SELHOLDTIME_5_SCK ((u16)0x0009) +#define SPI_SELHOLDTIME_5_HALF_SCK ((u16)0x000A) +#define SPI_SELHOLDTIME_6_SCK ((u16)0x000B) +#define SPI_SELHOLDTIME_6_HALF_SCK ((u16)0x000C) +#define SPI_SELHOLDTIME_7_SCK ((u16)0x000D) +#define SPI_SELHOLDTIME_7_HALF_SCK ((u16)0x000E) +#define SPI_SELHOLDTIME_8_SCK ((u16)0x000F) + +#define IS_SPI_SELHOLDTIME(SELHOLDTIME) ((SELHOLDTIME <= 0x000F)) +/** + * @} + */ + +/* Exported functions --------------------------------------------------------------------------------------*/ +/** @defgroup SPI_Exported_Functions SPI exported functions + * @{ + */ +void SPI_DeInit(HT_SPI_TypeDef* SPIx); +void SPI_Init(HT_SPI_TypeDef* SPIx, SPI_InitTypeDef* SPI_InitStruct); +void SPI_StructInit(SPI_InitTypeDef* SPI_InitStruct); +void SPI_Cmd(HT_SPI_TypeDef* SPIx, ControlStatus NewState); +void SPI_SELOutputCmd(HT_SPI_TypeDef* SPIx, ControlStatus NewState); +void SPI_FIFOCmd(HT_SPI_TypeDef* SPIx, ControlStatus NewState); +void SPI_SetDataLength(HT_SPI_TypeDef* SPIx, u16 SPI_DataLength); +void SPI_SELModeConfig(HT_SPI_TypeDef* SPIx, u32 SPI_SELMode); +void SPI_SoftwareSELCmd(HT_SPI_TypeDef* SPIx, u32 SPI_SoftwareSEL); +void SPI_SendData(HT_SPI_TypeDef* SPIx, SPI_DataTypeDef SPI_Data); +SPI_DataTypeDef SPI_ReceiveData(HT_SPI_TypeDef* SPIx); +void SPI_SetTimeOutValue(HT_SPI_TypeDef* SPIx, SPI_TimeoutTypeDef SPI_Timeout); +void SPI_IntConfig(HT_SPI_TypeDef* SPIx, u32 SPI_Int, ControlStatus NewState); +FlagStatus SPI_GetFlagStatus(HT_SPI_TypeDef* SPIx, u32 SPI_Flag); +u8 SPI_GetFIFOStatus(HT_SPI_TypeDef* SPIx, u32 SPI_FIFODirection); +void SPI_ClearFlag(HT_SPI_TypeDef* SPIx, u32 SPI_FlagClear); +void SPI_FIFOTriggerLevelConfig(HT_SPI_TypeDef* SPIx, u32 SPI_FIFODirection, u8 SPI_FIFOLevel); +void SPI_PDMACmd(HT_SPI_TypeDef* SPIx, u32 SPI_PDMAREQ, ControlStatus NewState); +void SPI_DUALCmd(HT_SPI_TypeDef* SPIx, ControlStatus NewState); +void SPI_GUARDTCmd(HT_SPI_TypeDef* SPIx, ControlStatus NewState); +void SPI_GUARDTConfig(HT_SPI_TypeDef* SPIx, u32 Guard_Time); +void SPI_SELHTConfig(HT_SPI_TypeDef* SPIx, u32 CS_Hold_Time); +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/inc/ht32f1xxxx_tm.h b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/inc/ht32f1xxxx_tm.h new file mode 100644 index 0000000000..b15bbbdbd0 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/inc/ht32f1xxxx_tm.h @@ -0,0 +1,623 @@ +/*********************************************************************************************************//** + * @file ht32f1xxxx_tm.h + * @version $Rev:: 2971 $ + * @date $Date:: 2023-10-25 #$ + * @brief The header file of the TM library. + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------------------------------------*/ +#ifndef __HT32F1XXXX_TM_H +#define __HT32F1XXXX_TM_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------------------------------------*/ +#include "ht32.h" + +/** @addtogroup HT32F1xxxx_Peripheral_Driver HT32F1xxxx Peripheral Driver + * @{ + */ + +/** @addtogroup TM + * @{ + */ + + +/* Exported types ------------------------------------------------------------------------------------------*/ +/** @defgroup TM_Exported_Types TM exported types + * @{ + */ +/** + * @brief Enumeration of TM counter mode. + */ +typedef enum +{ + TM_CNT_MODE_UP = 0x00000000, /*!< Edge up-counting mode */ + TM_CNT_MODE_CA1 = 0x00010000, /*!< Center-align mode 1 */ + TM_CNT_MODE_CA2 = 0x00020000, /*!< Center-align mode 2 */ + TM_CNT_MODE_CA3 = 0x00030000, /*!< Center-align mode 3 */ + TM_CNT_MODE_DOWN = 0x01000000 /*!< Edge down-counting mode */ +} TM_CNT_MODE_Enum; +/** + * @brief Enumeration of TM prescaler reload time. + */ +typedef enum +{ + TM_PSC_RLD_UPDATE = 0x0000, /*!< Reload prescaler at next update event */ + TM_PSC_RLD_IMMEDIATE = 0x0100 /*!< Reload prescaler immediately */ +} TM_PSC_RLD_Enum; +/** + * @brief Enumeration of TM channel output mode. + */ +typedef enum +{ + TM_OM_MATCH_NOCHANGE = 0x0000, /*!< TM channel output no change on match */ + TM_OM_MATCH_INACTIVE = 0x0001, /*!< TM channel output inactive level on match */ + TM_OM_MATCH_ACTIVE = 0x0002, /*!< TM channel output active level on match */ + TM_OM_MATCH_TOGGLE = 0x0003, /*!< TM channel output toggle on match */ + TM_OM_FORCED_INACTIVE = 0x0004, /*!< TM channel output forced inactive level */ + TM_OM_FORCED_ACTIVE = 0x0005, /*!< TM channel output forced active level */ + TM_OM_PWM1 = 0x0006, /*!< TM channel pwm1 output mode */ + TM_OM_PWM2 = 0x0007, /*!< TM channel pwm2 output mode */ + TM_OM_ASYMMETRIC_PWM1 = 0x0106, /*!< TM channel asymmetric pwm1 output mode */ + TM_OM_ASYMMETRIC_PWM2 = 0x0107 /*!< TM channel asymmetric pwm2 output mode */ +} TM_OM_Enum; +/** + * @brief Enumeration of TM channel capture source selection. + */ +typedef enum +{ + TM_CHCCS_DIRECT = 0x00010000, /*!< TM channel capture selection direct input */ + TM_CHCCS_INDIRECT = 0x00020000, /*!< TM channel capture selection indirect input */ + TM_CHCCS_TRCED = 0x00030000 /*!< TM channel capture selection TRCED of trigger control block */ +} TM_CHCCS_Enum; +/** + * @brief Enumeration of TM channel capture prescaler. + */ +typedef enum +{ + TM_CHPSC_OFF = 0x00000000, /*!< TM channel capture no prescaler, capture is done each event */ + TM_CHPSC_2 = 0x00040000, /*!< TM channel capture is done once every 2 event */ + TM_CHPSC_4 = 0x00080000, /*!< TM channel capture is done once every 4 event */ + TM_CHPSC_8 = 0x000C0000 /*!< TM channel capture is done once every 8 event */ +} TM_CHPSC_Enum; +/** + * @brief Enumeration of TM fDTS clock divider. + */ +typedef enum +{ + TM_CKDIV_OFF = 0x0000, /*!< fDTS = fCLKIN */ + TM_CKDIV_2 = 0x0100, /*!< fDTS = fCLKIN / 2 */ + TM_CKDIV_4 = 0x0200 /*!< fDTS = fCLKIN / 4 */ +} TM_CKDIV_Enum; +/** + * @brief Enumeration of TM ETI input prescaler. + */ +typedef enum +{ + TM_ETIPSC_OFF = 0x00000000, /*!< ETI prescaler off */ + TM_ETIPSC_2 = 0x00001000, /*!< ETIP frequency divided by 2 */ + TM_ETIPSC_4 = 0x00002000, /*!< ETIP frequency divided by 4 */ + TM_ETIPSC_8 = 0x00003000 /*!< ETIP frequency divided by 8 */ +} TM_ETIPSC_Enum; +/** + * @brief Enumeration of TM ETI input polarity. + */ +typedef enum +{ + TM_ETIPOL_NONINVERTED = 0x00000000, /*!< TM ETI polarity is active high or rising edge */ + TM_ETIPOL_INVERTED = 0x00010000 /*!< TM ETI polarity is active low or falling edge */ +} TM_ETIPOL_Enum; +/** + * @brief Enumeration of TM slave trigger input selection. + */ +typedef enum +{ + TM_TRSEL_UEVG = 0x0, /*!< Software trigger by setting UEVG bit */ + TM_TRSEL_TI0S0 = 0x1, /*!< Filtered channel 0 input */ + TM_TRSEL_TI1S1 = 0x2, /*!< Filtered channel 1 input */ + TM_TRSEL_ETIF = 0x3, /*!< External Trigger input */ + TM_TRSEL_TI0BED = 0x8, /*!< Trigger input 0 both edge detector */ + TM_TRSEL_ITI0 = 0x9, /*!< Internal trigger input 0 */ + TM_TRSEL_ITI1 = 0xA, /*!< Internal trigger input 1 */ + TM_TRSEL_ITI2 = 0xB /*!< Internal trigger input 2 */ +} TM_TRSEL_Enum; +/** + * @brief Enumeration of TM slave mode selection. + */ +typedef enum +{ + TM_SMSEL_DISABLE = 0x0000, /*!< The prescaler is clocked directly by the internal clock */ + TM_SMSEL_DECODER1 = 0x0100, /*!< Counter counts up/down on CH0 edge depending on CH1 level */ + TM_SMSEL_DECODER2 = 0x0200, /*!< Counter counts up/down on CH1 edge depending on CH0 level */ + TM_SMSEL_DECODER3 = 0x0300, /*!< Counter counts up/down on both CH0 & CH1 edges depending on the + level of the other input */ + TM_SMSEL_RESTART = 0x0400, /*!< Slave restart mode */ + TM_SMSEL_PAUSE = 0x0500, /*!< Slave pause mode */ + TM_SMSEL_TRIGGER = 0x0600, /*!< Slave trigger mode */ + TM_SMSEL_STIED = 0x0700 /*!< Rising edge of the selected trigger(STI) clock the counter */ +} TM_SMSEL_Enum; +/** + * @brief Enumeration of TM master mode selection. + */ +typedef enum +{ + TM_MMSEL_RESET = 0x00000000, /*!< Send trigger signal when S/W setting UEVG or slave restart */ + TM_MMSEL_ENABLE = 0x00010000, /*!< The counter enable signal is used as trigger output. */ + TM_MMSEL_UPDATE = 0x00020000, /*!< The update event is used as trigger output. */ + TM_MMSEL_CH0CC = 0x00030000, /*!< Channel 0 capture or compare match occurred as trigger output. */ + TM_MMSEL_CH0OREF = 0x00040000, /*!< The CH0OREF signal is used as trigger output. */ + TM_MMSEL_CH1OREF = 0x00050000, /*!< The CH1OREF signal is used as trigger output. */ + TM_MMSEL_CH2OREF = 0x00060000, /*!< The CH2OREF signal is used as trigger output. */ + TM_MMSEL_CH3OREF = 0x00070000 /*!< The CH3OREF signal is used as trigger output. */ +} TM_MMSEL_Enum; +/** + * @brief Enumeration of TM channel Capture / Compare PDMA selection. + */ +typedef enum +{ + TM_CHCCDS_CHCCEV = 0, /*!< Send CHx PDMA request when channel capture/compare event occurs */ + TM_CHCCDS_UEV /*!< Send CHx PDMA request when update event occurs */ +} TM_CHCCDS_Enum; +/** + * @brief Definition of TM timebase init structure. + */ +typedef struct +{ + u16 CounterReload; /*!< Period (Value for CRR register) */ + u16 Prescaler; /*!< Prescaler (Value for PSCR register) */ + u8 RepetitionCounter; /*!< Repetition counter */ + TM_CNT_MODE_Enum CounterMode; /*!< Counter mode refer to \ref TM_CNT_MODE_Enum */ + TM_PSC_RLD_Enum PSCReloadTime; /*!< Prescaler reload mode refer to \ref TM_PSC_RLD_Enum */ +} TM_TimeBaseInitTypeDef; +/** + * @brief Definition of TM channel output init structure. + */ +typedef struct +{ + TM_CH_Enum Channel; /*!< Channel selection refer to \ref TM_CH_Enum */ + TM_OM_Enum OutputMode; /*!< Channel output mode selection refer to \ref TM_OM_Enum */ + TM_CHCTL_Enum Control; /*!< CHxO output state refer to \ref TM_CHCTL_Enum */ + TM_CHCTL_Enum ControlN; /*!< CHxO output state refer to \ref TM_CHCTL_Enum */ + TM_CHP_Enum Polarity; /*!< CHxO polarity refer to \ref TM_CHP_Enum */ + TM_CHP_Enum PolarityN; /*!< CHxO polarity refer to \ref TM_CHP_Enum */ + MCTM_OIS_Enum IdleState; /*!< CHxO polarity refer to \ref TM_CHP_Enum */ + MCTM_OIS_Enum IdleStateN; /*!< CHxO polarity refer to \ref TM_CHP_Enum */ + u16 Compare; /*!< Value for CHxCCR register */ + u16 AsymmetricCompare; /*!< Value for CHxACR register */ +} TM_OutputInitTypeDef; +/** + * @brief Definition of TM channel input init structure. + */ +typedef struct +{ + TM_CH_Enum Channel; /*!< Channel selection refer to \ref TM_CH_Enum */ + TM_CHP_Enum Polarity; /*!< Channel input polarity refer to \ref TM_CHP_Enum */ + TM_CHCCS_Enum Selection; /*!< Channel capture source selection refer to \ref TM_CHCCS_Enum */ + TM_CHPSC_Enum Prescaler; /*!< Channel Capture prescaler refer to \ref TM_CHPSC_Enum */ + u8 Filter; /*!< Digital filter Configuration, it must between 0x0 ~ 0xF. */ +} TM_CaptureInitTypeDef; +/** + * @} + */ + +/* Exported constants --------------------------------------------------------------------------------------*/ +/** @defgroup TM_Exported_Constants TM exported constants + * @{ + */ + +/** @defgroup TM_INT Definitions of TM_INT + * @{ + */ +#define TM_INT_CH0CC 0x0001 /*!< Channel 0 capture/compare interrupt */ +#define TM_INT_CH1CC 0x0002 /*!< Channel 1 capture/compare interrupt */ +#define TM_INT_CH2CC 0x0004 /*!< Channel 2 capture/compare interrupt */ +#define TM_INT_CH3CC 0x0008 /*!< Channel 3 capture/compare interrupt */ +#define TM_INT_UEV 0x0100 /*!< Update interrupt */ +#define TM_INT_UEV2 0x0200 /*!< Update interrupt 2 */ +#define TM_INT_TEV 0x0400 /*!< Trigger interrupt */ +#define TM_INT_BRKEV 0x0800 /*!< Break interrupt */ +/** + * @} + */ + +/** @defgroup TM_PDMA Definitions of TM_PDMA + * @{ + */ +#define TM_PDMA_CH0CC 0x00010000 /*!< Channel 0 capture/compare PDMA request */ +#define TM_PDMA_CH1CC 0x00020000 /*!< Channel 1 capture/compare PDMA request */ +#define TM_PDMA_CH2CC 0x00040000 /*!< Channel 2 capture/compare PDMA request */ +#define TM_PDMA_CH3CC 0x00080000 /*!< Channel 3 capture/compare PDMA request */ +#define TM_PDMA_UEV 0x01000000 /*!< Update PDMA request */ +#define TM_PDMA_UEV2 0x02000000 /*!< Update 2 PDMA request */ +#define TM_PDMA_TEV 0x04000000 /*!< Trigger PDMA request */ +/** + * @} + */ + +/** @defgroup TM_EVENT Definitions of TM_EVENT + * @{ + */ +#define TM_EVENT_CH0CC 0x0001 /*!< Channel 0 capture/compare event */ +#define TM_EVENT_CH1CC 0x0002 /*!< Channel 1 capture/compare event */ +#define TM_EVENT_CH2CC 0x0004 /*!< Channel 2 capture/compare event */ +#define TM_EVENT_CH3CC 0x0008 /*!< Channel 3 capture/compare event */ +#define TM_EVENT_UEV 0x0100 /*!< Update event */ +#define TM_EVENT_UEV2 0x0200 /*!< Update event 2 */ +#define TM_EVENT_TEV 0x0400 /*!< Trigger event */ +#define TM_EVENT_BRKEV 0x0800 /*!< Break event */ +/** + * @} + */ + +/** @defgroup TM_FLAG Definitions of TM_FLAG + * @{ + */ +#define TM_FLAG_CH0CC 0x0001 /*!< Channel 0 capture/compare flag */ +#define TM_FLAG_CH1CC 0x0002 /*!< Channel 1 capture/compare flag */ +#define TM_FLAG_CH2CC 0x0004 /*!< Channel 2 capture/compare flag */ +#define TM_FLAG_CH3CC 0x0008 /*!< Channel 3 capture/compare flag */ +#define TM_FLAG_CH0OC 0x0010 /*!< Channel 0 over capture flag */ +#define TM_FLAG_CH1OC 0x0020 /*!< Channel 1 over capture flag */ +#define TM_FLAG_CH2OC 0x0040 /*!< Channel 2 over capture flag */ +#define TM_FLAG_CH3OC 0x0080 /*!< Channel 3 over capture flag */ +#define TM_FLAG_UEV 0x0100 /*!< Update flag */ +#define TM_FLAG_UEV2 0x0200 /*!< Update 2 flag */ +#define TM_FLAG_TEV 0x0400 /*!< Trigger flag */ +#define TM_FLAG_BRK0 0x0800 /*!< Break 0 flag */ +#define TM_FLAG_BRK1 0x1000 /*!< Break 1 flag */ +/** + * @} + */ + +/** @defgroup TM_Check_Parameter Check parameter + * @{ + */ + +/** + * @brief Used to check parameter of the TMx. + */ +#define IS_TM(x) (IS_GPTM0(x) || IS_GPTM1(x) || IS_MCTM0(x) || IS_MCTM1(x) || IS_SCTM(x)) +#define IS_GPTM0(x) (x == HT_GPTM0) + +#define IS_GPTM1(x) (0) +#define IS_MCTM0(x) (0) +#define IS_MCTM1(x) (0) + +#if !(LIBCFG_NO_GPTM1) +#undef IS_GPTM1 +#define IS_GPTM1(x) (x == HT_GPTM1) +#endif + +#if !(LIBCFG_NO_MCTM0) +#undef IS_MCTM0 +#define IS_MCTM0(x) (x == HT_MCTM0) +#endif + +#if !(LIBCFG_NO_MCTM1) +#undef IS_MCTM1 +#define IS_MCTM1(x) (x == HT_MCTM1) +#endif + +#define IS_SCTM(x) (IS_SCTM0(x) || IS_SCTM1(x)) + +#define IS_SCTM0(x) (0) +#define IS_SCTM1(x) (0) + +#if (LIBCFG_SCTM0) +#undef IS_SCTM0 +#define IS_SCTM0(x) (x == HT_SCTM0) +#endif + +#if (LIBCFG_SCTM1) +#undef IS_SCTM1 +#define IS_SCTM1(x) (x == HT_SCTM1) +#endif + + +/** + * @brief Used to check parameter of the output compare mode. + */ +#define IS_TM_OM_CMP(x) (((x) == TM_OM_MATCH_NOCHANGE) || \ + ((x) == TM_OM_MATCH_INACTIVE) || \ + ((x) == TM_OM_MATCH_ACTIVE) || \ + ((x) == TM_OM_MATCH_TOGGLE) || \ + ((x) == TM_OM_PWM1) || \ + ((x) == TM_OM_PWM2)) +/** + * @brief Used to check parameter of the output mode. + */ +#define IS_TM_OM(x) (((x) == TM_OM_MATCH_NOCHANGE) || \ + ((x) == TM_OM_MATCH_INACTIVE) || \ + ((x) == TM_OM_MATCH_ACTIVE) || \ + ((x) == TM_OM_MATCH_TOGGLE) || \ + ((x) == TM_OM_PWM1) || \ + ((x) == TM_OM_PWM2) || \ + ((x) == TM_OM_FORCED_INACTIVE) || \ + ((x) == TM_OM_FORCED_ACTIVE) || \ + ((x) == TM_OM_ASYMMETRIC_PWM1) || \ + ((x) == TM_OM_ASYMMETRIC_PWM2)) +/** + * @brief Used to check parameter of the channel. + */ +#define IS_TM_CH(x) (((x) == TM_CH_0) || ((x) == TM_CH_1) || \ + ((x) == TM_CH_2) || ((x) == TM_CH_3)) +/** + * @brief Used to check parameter of the channel for PWM input function. + */ +#define IS_TM_CH_PWMI(x) (((x) == TM_CH_0) || ((x) == TM_CH_1)) +/** + * @brief Used to check parameter of the clock divider. + */ +#define IS_TM_CKDIV(x) ((x == TM_CKDIV_OFF) || \ + (x == TM_CKDIV_2) || \ + (x == TM_CKDIV_4)) +/** + * @brief Used to check parameter of the counter mode. + */ +#define IS_TM_CNT_MODE(x) ((x == TM_CNT_MODE_UP) || \ + (x == TM_CNT_MODE_CA1) || \ + (x == TM_CNT_MODE_CA2) || \ + (x == TM_CNT_MODE_CA3) || \ + (x == TM_CNT_MODE_DOWN)) +/** + * @brief Used to check parameter of the channel polarity. + */ +#define IS_TM_CHP(x) ((x == TM_CHP_NONINVERTED) || (x == TM_CHP_INVERTED)) +/** + * @brief Used to check parameter of the channel control. + */ +#define IS_TM_CHCTL(x) ((x == TM_CHCTL_DISABLE) || (x == TM_CHCTL_ENABLE)) +/** + * @brief Used to check parameter of the channel capture / compare PDMA selection. + */ +#define IS_TM_CHCCDS(x) ((x == TM_CHCCDS_CHCCEV) || (x == TM_CHCCDS_UEV)) +/** + * @brief Used to check parameter of the channel input selection. + */ +#define IS_TM_CHCCS(x) ((x == TM_CHCCS_DIRECT) || \ + (x == TM_CHCCS_INDIRECT) || \ + (x == TM_CHCCS_TRCED)) +/** + * @brief Used to check parameter of the channel capture prescaler. + */ +#define IS_TM_CHPSC(x) ((x == TM_CHPSC_OFF) || \ + (x == TM_CHPSC_2) || \ + (x == TM_CHPSC_4) || \ + (x == TM_CHPSC_8)) +/** + * @brief Used to check parameter of the ETI prescaler. + */ +#define IS_TM_ETIPSC(x) ((x == TM_ETIPSC_OFF) || \ + (x == TM_ETIPSC_2) || \ + (x == TM_ETIPSC_4) || \ + (x == TM_ETIPSC_8)) +/** + * @brief Used to check parameter of the TM interrupt. + */ +#define IS_TM_INT(x) (((x & 0xFFFFF0F0) == 0x0) && (x != 0)) +/** + * @brief Used to check parameter of the TM PDMA request. + */ +#define IS_TM_PDMA(x) (((x & 0xF8F0FFFF) == 0x0) && (x != 0)) +/** + * @brief Used to check parameter of the TM interrupt for \ref TM_GetIntStatus function. + */ +#define IS_TM_GET_INT(x) ((x == TM_INT_CH0CC) || \ + (x == TM_INT_CH1CC) || \ + (x == TM_INT_CH2CC) || \ + (x == TM_INT_CH3CC) || \ + (x == TM_INT_UEV) || \ + (x == TM_INT_UEV2) || \ + (x == TM_INT_TEV) || \ + (x == TM_INT_BRKEV)) +/** + * @brief Used to check parameter of the TM STI selection. + */ +#define IS_TM_TRSEL(x) ((x == TM_TRSEL_UEVG) || \ + (x == TM_TRSEL_TI0S0) || \ + (x == TM_TRSEL_TI1S1) || \ + (x == TM_TRSEL_ETIF) || \ + (x == TM_TRSEL_TI0BED) || \ + (x == TM_TRSEL_ITI0) || \ + (x == TM_TRSEL_ITI1) || \ + (x == TM_TRSEL_ITI2)) +/** + * @brief Used to check parameter of the ITI. + */ +#define IS_TM_ITI(x) ((x == TM_TRSEL_ITI0) || (x == TM_TRSEL_ITI1) || (x == TM_TRSEL_ITI2)) +/** + * @brief Used to check parameter of the TM_TRSEL for \ref TM_ChExternalClockConfig function. + */ +#define IS_TM_TRSEL_CH(x) ((x == TM_TRSEL_TI0S0) || (x == TM_TRSEL_TI1S1) || \ + (x == TM_TRSEL_TI0BED)) +/** + * @brief Used to check parameter of the TM ETI polarity. + */ +#define IS_TM_ETIPOL(x) ((x == TM_ETIPOL_NONINVERTED) || (x == TM_ETIPOL_INVERTED)) +/** + * @brief Used to check parameter of the TM prescaler reload time. + */ +#define IS_TM_PSC_RLD(x) ((x == TM_PSC_RLD_UPDATE) || (x == TM_PSC_RLD_IMMEDIATE)) +/** + * @brief Used to check parameter of the forced action. + */ +#define IS_TM_OM_FORCED(x) ((x == TM_OM_FORCED_ACTIVE) || (x == TM_OM_FORCED_INACTIVE)) +/** + * @brief Used to check parameter of the decoder mode. + */ +#define IS_TM_SMSEL_DECODER(x) ((x == TM_SMSEL_DECODER1) || (x == TM_SMSEL_DECODER2) || \ + (x == TM_SMSEL_DECODER3)) +/** + * @brief Used to check parameter of the event. + */ +#define IS_TM_EVENT(x) (((x & 0xFFFFF0F0) == 0x0000) && (x != 0x0000)) +/** + * @brief Used to check parameter of the TM master mode selection. + */ +#define IS_TM_MMSEL(x) (((x) == TM_MMSEL_RESET) || \ + ((x) == TM_MMSEL_ENABLE) || \ + ((x) == TM_MMSEL_UPDATE) || \ + ((x) == TM_MMSEL_CH0CC) || \ + ((x) == TM_MMSEL_CH0OREF) || \ + ((x) == TM_MMSEL_CH1OREF) || \ + ((x) == TM_MMSEL_CH2OREF) || \ + ((x) == TM_MMSEL_CH3OREF)) +/** + * @brief Used to check parameter of the TM slave mode. + */ +#define IS_TM_SLAVE_MODE(x) ((x == TM_SMSEL_RESTART) || (x == TM_SMSEL_PAUSE) || \ + (x == TM_SMSEL_TRIGGER) || (x == TM_SMSEL_STIED)) +/** + * @brief Used to check parameter of the TM flag. + */ +#define IS_TM_FLAG(x) ((x == TM_FLAG_CH0CC) || \ + (x == TM_FLAG_CH1CC) || \ + (x == TM_FLAG_CH2CC) || \ + (x == TM_FLAG_CH3CC) || \ + (x == TM_FLAG_CH0OC) || \ + (x == TM_FLAG_CH1OC) || \ + (x == TM_FLAG_CH2OC) || \ + (x == TM_FLAG_CH3OC) || \ + (x == TM_FLAG_UEV) || \ + (x == TM_FLAG_UEV2) || \ + (x == TM_FLAG_TEV) || \ + (x == TM_FLAG_BRK0) || \ + (x == TM_FLAG_BRK1)) + +/** + * @brief Used to check parameter of the TM flag for \ref TM_ClearFlag function. + */ +#define IS_TM_FLAG_CLR(x) (((x & 0xFFFFE000) == 0) && (x != 0)) +/** + * @brief Used to check value of TM digital filter. + */ +#define IS_TM_FILTER(x) (x <= 0xF) + +/** + * @} + */ + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------------------------------------*/ +/** @defgroup TM_Exported_Functions TM exported functions + * @{ + */ +#define TM_SetCaptureCompare0(TMx, Cmp) TM_SetCaptureCompare(TMx, TM_CH_0, Cmp) +#define TM_SetCaptureCompare1(TMx, Cmp) TM_SetCaptureCompare(TMx, TM_CH_1, Cmp) +#define TM_SetCaptureCompare2(TMx, Cmp) TM_SetCaptureCompare(TMx, TM_CH_2, Cmp) +#define TM_SetCaptureCompare3(TMx, Cmp) TM_SetCaptureCompare(TMx, TM_CH_3, Cmp) + +#define TM_ForcedOREF0(TMx, ForcedAction) TM_ForcedOREF(TMx, TM_CH_0, ForcedAction) +#define TM_ForcedOREF1(TMx, ForcedAction) TM_ForcedOREF(TMx, TM_CH_1, ForcedAction) +#define TM_ForcedOREF2(TMx, ForcedAction) TM_ForcedOREF(TMx, TM_CH_2, ForcedAction) +#define TM_ForcedOREF3(TMx, ForcedAction) TM_ForcedOREF(TMx, TM_CH_3, ForcedAction) + +#define TM_SetAsymmetricCompare0(TMx, Cmp) TM_SetAsymmetricCompare(TMx, TM_CH_0, Cmp) +#define TM_SetAsymmetricCompare1(TMx, Cmp) TM_SetAsymmetricCompare(TMx, TM_CH_1, Cmp) +#define TM_SetAsymmetricCompare2(TMx, Cmp) TM_SetAsymmetricCompare(TMx, TM_CH_2, Cmp) +#define TM_SetAsymmetricCompare3(TMx, Cmp) TM_SetAsymmetricCompare(TMx, TM_CH_3, Cmp) + +#define TM_GetCaptureCompare0(TMx) TM_GetCaptureCompare(TMx,TM_CH_0) +#define TM_GetCaptureCompare1(TMx) TM_GetCaptureCompare(TMx,TM_CH_1) +#define TM_GetCaptureCompare2(TMx) TM_GetCaptureCompare(TMx,TM_CH_2) +#define TM_GetCaptureCompare3(TMx) TM_GetCaptureCompare(TMx,TM_CH_3) + +void TM_DeInit(HT_TM_TypeDef* TMx); +void TM_TimeBaseInit(HT_TM_TypeDef* TMx, TM_TimeBaseInitTypeDef* TimeBaseInit); +void TM_OutputInit(HT_TM_TypeDef* TMx, TM_OutputInitTypeDef* OutInit); +void TM_CaptureInit(HT_TM_TypeDef* TMx, TM_CaptureInitTypeDef* CapInit); +void TM_PwmInputInit(HT_TM_TypeDef* TMx, TM_CaptureInitTypeDef* CapInit); +void TM_TimeBaseStructInit(TM_TimeBaseInitTypeDef* TimeBaseInit); +void TM_OutputStructInit(TM_OutputInitTypeDef* OutInit); +void TM_CaptureStructInit(TM_CaptureInitTypeDef* CapInit); +void TM_Cmd(HT_TM_TypeDef* TMx, ControlStatus NewState); +void TM_ItiExternalClockConfig(HT_TM_TypeDef* TMx, TM_TRSEL_Enum Iti); +void TM_ChExternalClockConfig(HT_TM_TypeDef* TMx, TM_TRSEL_Enum Sel, TM_CHP_Enum Pol, u8 Filter); +void TM_EtiExternalClockConfig(HT_TM_TypeDef* TMx, TM_ETIPSC_Enum Psc, TM_ETIPOL_Enum Pol, u8 Filter); +void TM_EtiConfig(HT_TM_TypeDef* TMx, TM_ETIPSC_Enum Psc, TM_ETIPOL_Enum Pol, u8 Filter); +void TM_PrescalerConfig(HT_TM_TypeDef* TMx, u16 Psc, TM_PSC_RLD_Enum PscReloadTime); +void TM_CounterModeConfig(HT_TM_TypeDef* TMx, TM_CNT_MODE_Enum Mod); +void TM_StiConfig(HT_TM_TypeDef* TMx, TM_TRSEL_Enum Sel); +void TM_DecoderConfig(HT_TM_TypeDef* TMx, TM_SMSEL_Enum DecoderMod, TM_CHP_Enum CH0P, TM_CHP_Enum CH1P); + +void TM_ForcedOREF(HT_TM_TypeDef* TMx, TM_CH_Enum TM_CH_n, TM_OM_Enum ForcedAction); +void TM_CRRPreloadCmd(HT_TM_TypeDef* TMx, ControlStatus NewState); +void TM_CHCCRPreloadConfig(HT_TM_TypeDef* TMx, TM_CH_Enum Channel, ControlStatus NewState); +void TM_ClearOREFConfig(HT_TM_TypeDef* TMx, TM_CH_Enum Channel, ControlStatus NewState); +void TM_ChPolarityConfig(HT_TM_TypeDef* TMx, TM_CH_Enum Channel, TM_CHP_Enum Pol); + +void TM_ImmActiveConfig(HT_TM_TypeDef* TMx, TM_CH_Enum Channel, ControlStatus NewState); +void TM_ChannelConfig(HT_TM_TypeDef* TMx, TM_CH_Enum Channel, TM_CHCTL_Enum Control); + +void TM_OutputModeConfig(HT_TM_TypeDef* TMx, TM_CH_Enum Channel, TM_OM_Enum Mod); +void TM_UpdateCmd(HT_TM_TypeDef* TMx, ControlStatus NewState); +void TM_UEVG_IntConfig(HT_TM_TypeDef* TMx, ControlStatus NewState); +void TM_HallInterfaceCmd(HT_TM_TypeDef* TMx, ControlStatus NewState); +void TM_SinglePulseModeCmd(HT_TM_TypeDef* TMx, ControlStatus NewState); +void TM_MMSELConfig(HT_TM_TypeDef* TMx, TM_MMSEL_Enum Sel); +void TM_SlaveModeConfig(HT_TM_TypeDef* TMx, TM_SMSEL_Enum Sel); +void TM_TimSyncCmd(HT_TM_TypeDef* TMx, ControlStatus NewState); +void TM_SetCounter(HT_TM_TypeDef* TMx, u16 Counter); +void TM_SetCounterReload(HT_TM_TypeDef* TMx, u16 Reload); +void TM_SetCaptureCompare(HT_TM_TypeDef* TMx, TM_CH_Enum TM_CH_n, u16 Cmp); +void TM_SetAsymmetricCompare(HT_TM_TypeDef* TMx, TM_CH_Enum TM_CH_n, u16 Cmp); + +void TM_CHPSCConfig(HT_TM_TypeDef* TMx, TM_CH_Enum Channel, TM_CHPSC_Enum Psc); +void TM_CKDIVConfig(HT_TM_TypeDef* TMx, TM_CKDIV_Enum Div); +u32 TM_GetCaptureCompare(HT_TM_TypeDef* TMx, TM_CH_Enum TM_CH_n); +u32 TM_GetCounter(HT_TM_TypeDef* TMx); +u32 TM_GetPrescaler(HT_TM_TypeDef* TMx); +void TM_GenerateEvent(HT_TM_TypeDef* TMx, u32 TM_EVENT); +FlagStatus TM_GetFlagStatus(HT_TM_TypeDef* TMx, u32 TM_FLAG); +void TM_ClearFlag(HT_TM_TypeDef* TMx, u32 TM_FLAG); +void TM_IntConfig(HT_TM_TypeDef* TMx, u32 TM_INT, ControlStatus NewState); +FlagStatus TM_GetIntStatus(HT_TM_TypeDef* TMx, u32 TM_INT); +void TM_ClearIntPendingBit(HT_TM_TypeDef* TMx, u32 TM_INT); +void TM_InternalClockConfig(HT_TM_TypeDef* TMx); + +void TM_CHCCDSConfig(HT_TM_TypeDef* TMx, TM_CHCCDS_Enum Selection); +void TM_PDMAConfig(HT_TM_TypeDef* TMx, u32 TM_PDMA, ControlStatus NewState); +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/inc/ht32f1xxxx_tm_type.h b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/inc/ht32f1xxxx_tm_type.h new file mode 100644 index 0000000000..19cac328c5 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/inc/ht32f1xxxx_tm_type.h @@ -0,0 +1,113 @@ +/*********************************************************************************************************//** + * @file ht32f1xxxx_tm_type.h + * @version $Rev:: 2971 $ + * @date $Date:: 2023-10-25 #$ + * @brief The header file of the TM library. + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------------------------------------*/ +#ifndef __HT32F1XXXX_TM_TYPE_H +#define __HT32F1XXXX_TM_TYPE_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------------------------------------*/ +#include "ht32.h" + +/** @addtogroup HT32F1xxxx_Peripheral_Driver HT32F1xxxx Peripheral Driver + * @{ + */ + +/** @addtogroup TM + * @{ + */ + + +/* Exported types ------------------------------------------------------------------------------------------*/ +/** @defgroup TM_Exported_Types TM exported types + * @{ + */ +/** + * @brief Enumeration of TM channel. + */ +typedef enum +{ + TM_CH_0 = 0, /*!< TM channel 0 */ + TM_CH_1, /*!< TM channel 1 */ + TM_CH_2, /*!< TM channel 2 */ + TM_CH_3 /*!< TM channel 3 */ +} TM_CH_Enum; +/** + * @brief Enumeration of TM channel control. + */ +typedef enum +{ + TM_CHCTL_DISABLE = 0, /*!< TM channel disable */ + TM_CHCTL_ENABLE /*!< TM channel enable */ +} TM_CHCTL_Enum; +/** + * @brief Enumeration of TM channel polarity. + */ +typedef enum +{ + TM_CHP_NONINVERTED = 0, /*!< TM channel polarity is active high or rising edge */ + TM_CHP_INVERTED /*!< TM channel polarity is active low or falling edge */ +} TM_CHP_Enum; +/** + * @brief Enumeration of MCTM channel output idle state. + */ +typedef enum +{ + MCTM_OIS_LOW = 0, /*!< MCTM channel output low when CHMOE equal to 0 */ + MCTM_OIS_HIGH /*!< MCTM channel output high when CHMOE equal to 0 */ +} MCTM_OIS_Enum; +/** + * @brief Enumeration of MCTM COMUS. + */ +typedef enum +{ + MCTM_COMUS_STIOFF = 0, /*!< MCTM capture/compare control bits are updated by + setting the UEV2G bit only */ + MCTM_COMUS_STION /*!< MCTM capture/compare control bits are updated by both + setting the UEV2G bit or when a rising edge occurs on STI */ +} MCTM_COMUS_Enum; +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/inc/ht32f1xxxx_usart.h b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/inc/ht32f1xxxx_usart.h new file mode 100644 index 0000000000..6e0c5332b2 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/inc/ht32f1xxxx_usart.h @@ -0,0 +1,585 @@ +/*********************************************************************************************************//** + * @file ht32f1xxxx_usart.h + * @version $Rev:: 2797 $ + * @date $Date:: 2022-11-28 #$ + * @brief The header file of the USART library. + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------------------------------------*/ +#ifndef __HT32F1XXXX_USART_H +#define __HT32F1XXXX_USART_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------------------------------------*/ +#include "ht32.h" + +/** @addtogroup HT32F1xxxx_Peripheral_Driver HT32F1xxxx Peripheral Driver + * @{ + */ + +/** @addtogroup USART + * @{ + */ + + +#define LIBCFG_USART_V01_LEGACY (0) + +/* Exported types ------------------------------------------------------------------------------------------*/ +/** @defgroup USART_Exported_Types USART exported types + * @{ + */ +/* Definition of USART Init Structure ---------------------------------------------------------------------*/ +typedef struct +{ + u32 USART_BaudRate; + u16 USART_WordLength; + u16 USART_StopBits; + u16 USART_Parity; + u16 USART_Mode; +} USART_InitTypeDef; + +typedef struct +{ + u16 USART_ClockEnable; + u16 USART_ClockPhase; + u16 USART_ClockPolarity; + u16 USART_TransferSelectMode; +} USART_SynClock_InitTypeDef; +/** + * @} + */ + +/* Exported constants --------------------------------------------------------------------------------------*/ +/** @defgroup USART_Exported_Constants USART exported constants + * @{ + */ + +#define USART_CMD_TX (0) +#define USART_CMD_RX (1) + +#define USART_CMD_OUT (0) +#define USART_CMD_IN (1) + +/* USART Word Length ---------------------------------------------------------------------------------------*/ +/** @defgroup USART_Word_Length Definitions of USART word length + * @{ + */ +#if (LIBCFG_USART_V01) +#define USART_WORDLENGTH_7B ((u32)0x00000000) +#define USART_WORDLENGTH_8B ((u32)0x00000001) +#define USART_WORDLENGTH_9B ((u32)0x00000002) +#else +#define USART_WORDLENGTH_7B ((u32)0x00000000) +#define USART_WORDLENGTH_8B ((u32)0x00000100) +#define USART_WORDLENGTH_9B ((u32)0x00000200) +#endif + +#define IS_USART_WORD_LENGTH(LENGTH) ((LENGTH == USART_WORDLENGTH_9B) || \ + (LENGTH == USART_WORDLENGTH_8B) || \ + (LENGTH == USART_WORDLENGTH_7B)) +/** + * @} + */ + +/* USART Stop Bits -----------------------------------------------------------------------------------------*/ +/** @defgroup USART_Stop_Bit Definitions of USART stop bit + * @{ + */ +#if (LIBCFG_USART_V01) +#define USART_STOPBITS_1 ((u32)0x00000000) +#define USART_STOPBITS_2 ((u32)0x00000004) +#else +#define USART_STOPBITS_1 ((u32)0x00000000) +#define USART_STOPBITS_2 ((u32)0x00000400) +#endif + + +#define IS_USART_STOPBITS(STOPBITS) ((STOPBITS == USART_STOPBITS_1) || \ + (STOPBITS == USART_STOPBITS_2)) +/** + * @} + */ + +/* USART Parity --------------------------------------------------------------------------------------------*/ +/** @defgroup USART_Parity Definitions of USART parity + * @{ + */ +#if (LIBCFG_USART_V01) +#define USART_PARITY_NO ((u32)0x00000000) +#define USART_PARITY_EVEN ((u32)0x00000018) +#define USART_PARITY_ODD ((u32)0x00000008) +#else +#define USART_PARITY_NO ((u32)0x00000000) +#define USART_PARITY_EVEN ((u32)0x00001800) +#define USART_PARITY_ODD ((u32)0x00000800) +#define USART_PARITY_MARK ((u32)0x00002800) +#define USART_PARITY_SPACE ((u32)0x00003800) +#endif + +#define IS_USART_PARITY(PARITY) ((PARITY == USART_PARITY_NO) || \ + (PARITY == USART_PARITY_EVEN) || \ + (PARITY == USART_PARITY_ODD)) +/** + * @} + */ + +/* USART Mode ----------------------------------------------------------------------------------------------*/ +/** @defgroup USART_Mode Definitions of USART mode + * @{ + */ +#define USART_MODE_NORMAL ((u32)0x00000000) +#define USART_MODE_IRDA ((u32)0x00000001) +#define USART_MODE_RS485 ((u32)0x00000002) +#define USART_MODE_SYNCHRONOUS ((u32)0x00000003) + +#define IS_USART_MODE(MODE) ((MODE == USART_MODE_NORMAL) || \ + (MODE == USART_MODE_IRDA) || \ + (MODE == USART_MODE_RS485) || \ + (MODE == USART_MODE_SYNCHRONOUS)) +/** + * @} + */ + +/* USART Transfer Select Mode ------------------------------------------------------------------------------*/ +/** @defgroup USART_LSB Definitions of USART LSB + * @{ + */ +#define USART_LSB_FIRST ((u32)0x00000000) +#define USART_MSB_FIRST ((u32)0x00000004) + +#define IS_USART_TRANSFER_MODE(TMODE) ((TMODE == USART_LSB_FIRST) || \ + (TMODE == USART_MSB_FIRST)) +/** + * @} + */ + + +/* USART Synchronous Clock ---------------------------------------------------------------------------------*/ +/** @defgroup USART_Synchronous_Clock Definitions of USART synchronous clock + * @{ + */ +#define USART_SYN_CLOCK_DISABLE ((u32)0x00000000) +#define USART_SYN_CLOCK_ENABLE ((u32)0x00000001) + +#define IS_USART_SYNCHRONOUS_CLOCK(SYNCLOCK) ((SYNCLOCK == USART_SYN_CLOCK_DISABLE) || \ + (SYNCLOCK == USART_SYN_CLOCK_ENABLE)) +/** + * @} + */ + +/* USART Synchronous Clock Phase ---------------------------------------------------------------------------*/ +/** @defgroup USART_Synchronous_Clock_Phase Definitions of USART Synchronous clock phase + * @{ + */ +#define USART_SYN_CLOCK_PHASE_FIRST ((u32)0x00000000) +#define USART_SYN_CLOCK_PHASE_SECOND ((u32)0x00000004) + +#define IS_USART_SYNCHRONOUS_PHASE(PHASE) ((PHASE == USART_SYN_CLOCK_PHASE_FIRST) || \ + (PHASE == USART_SYN_CLOCK_PHASE_SECOND)) +/** + * @} + */ + +/* USART Clock Polarity ------------------------------------------------------------------------------------*/ +/** @defgroup USART_Clock_Polarity Definitions of USART clock polarity + * @{ + */ +#define USART_SYN_CLOCK_POLARITY_LOW ((u32)0x00000000) +#define USART_SYN_CLOCK_POLARITY_HIGH ((u32)0x00000008) + +#define IS_USART_SYNCHRONOUS_POLARITY(POLARITY) ((POLARITY == USART_SYN_CLOCK_POLARITY_LOW) || \ + (POLARITY == USART_SYN_CLOCK_POLARITY_HIGH)) +/** + * @} + */ + +/* USART IrDA ---------------------------------------------------------------------------------------------*/ +/** @defgroup USART_IrDA Definitions of USART IrDA + * @{ + */ +#define USART_IRDA_LOWPOWER ((u32)0x00000002) +#define USART_IRDA_NORMAL ((u32)0xFFFFFFFD) + +#define IS_USART_IRDA_MODE(MODE) ((MODE == USART_IRDA_LOWPOWER) || \ + (MODE == USART_IRDA_NORMAL)) + +#define USART_IRDA_TX ((u32)0x00000004) +#define USART_IRDA_RX ((u32)0xFFFFFFFB) + +#define IS_USART_IRDA_DIRECTION(DIRECTION) ((DIRECTION == USART_IRDA_TX) || \ + (DIRECTION == USART_IRDA_RX)) +/** + * @} + */ + +#define IS_USART_TL(x) (IS_USART_RXTL(x) || IS_USART_TXTL(x)) + +/* USART Rx FIFO Interrupt Trigger Level -------------------------------------------------------------------*/ +/** @defgroup USART_RX_FIFO_Trigger_Level Definitions of USART Rx FIFO interrupts + * @{ + */ +#if (LIBCFG_USART_V01) +#define USART_RXTL_01 ((u32)0x00000000) +#define USART_RXTL_04 ((u32)0x00000010) +#define USART_RXTL_08 ((u32)0x00000020) +#define USART_RXTL_14 ((u32)0x00000030) + +#define IS_USART_RXTL(RXTL) ((RXTL == USART_RXTL_01) || \ + (RXTL == USART_RXTL_04) || \ + (RXTL == USART_RXTL_08) || \ + (RXTL == USART_RXTL_14)) +#else +#define USART_RXTL_01 ((u32)0x00000000) +#define USART_RXTL_02 ((u32)0x00000010) +#define USART_RXTL_04 ((u32)0x00000020) +#define USART_RXTL_06 ((u32)0x00000030) + +#define IS_USART_RXTL(RXTL) ((RXTL == USART_RXTL_01) || \ + (RXTL == USART_RXTL_02) || \ + (RXTL == USART_RXTL_04) || \ + (RXTL == USART_RXTL_06)) +#endif +/** + * @} + */ + +/* USART Tx FIFO Interrupt Trigger Level -------------------------------------------------------------------*/ +/** @defgroup USART_TX_FIFO_Trigger_Level Definitions of USART Tx FIFO interrupts + * @{ + */ +#if (LIBCFG_USART_V01) +#define USART_TXTL_00 ((u32)0x00000000) +#define USART_TXTL_02 ((u32)0x00000010) +#define USART_TXTL_04 ((u32)0x00000020) +#define USART_TXTL_08 ((u32)0x00000030) + +#define IS_USART_TXTL(TXTL) ((TXTL == USART_TXTL_00) || \ + (TXTL == USART_TXTL_02) || \ + (TXTL == USART_TXTL_04) || \ + (TXTL == USART_TXTL_08)) +#else +#define USART_TXTL_00 ((u32)0x00000000) +#define USART_TXTL_02 ((u32)0x00000010) +#define USART_TXTL_04 ((u32)0x00000020) +#define USART_TXTL_06 ((u32)0x00000030) + +#define IS_USART_TXTL(TXTL) ((TXTL == USART_TXTL_00) || \ + (TXTL == USART_TXTL_02) || \ + (TXTL == USART_TXTL_04) || \ + (TXTL == USART_TXTL_06)) +#endif +/** + * @} + */ + +/* USART Interrupt definition ------------------------------------------------------------------------------*/ +/** @defgroup USART_Interrupt_Enable Definitions of USART interrupt Enable bits + * @{ + */ +#if (LIBCFG_USART_V01) +#define USART_INT_RXDR ((u32)0x00000001) +#define USART_INT_TXDE ((u32)0x00000002) +#define USART_INT_RLSIE ((u32)0x00000004) +#define USART_INT_MSIE ((u32)0x00000008) +#define USART_INT_TOUT ((u32)0x00000100) + +#if (LIBCFG_USART_V01_LEGACY) +#define USART_IER_RDAIE (USART_INT_RXDR) +#define USART_IER_THREIE (USART_INT_TXDE) +#define USART_IER_RLSIE (USART_INT_RLSIE) +#define USART_IER_MSIE (USART_INT_MSIE) +#endif + +#define IS_USART_INT(INT) ((((INT) & 0xFFFFFFF0) == 0) && ((INT) != 0)) + +#define USART_IID_RLS ((u8)0x06) +#define USART_IID_RDA ((u8)0x04) +#define USART_IID_CTI ((u8)0x0C) +#define USART_IID_THRE ((u8)0x02) +#define USART_IID_MS ((u8)0x00) +#define USART_IID_NON ((u8)0x01) + +#define IS_USART_IID(IID) ((IID == USART_IID_RLS) || \ + (IID == USART_IID_RDA) || \ + (IID == USART_IID_CTI) || \ + (IID == USART_IID_THRE) || \ + (IID == USART_IID_MS) || \ + (IID == USART_IID_NON)) + +#else +#define USART_INT_RXDR ((u32)0x00000001) +#define USART_INT_TXDE ((u32)0x00000002) +#define USART_INT_TXC ((u32)0x00000004) +#define USART_INT_OE ((u32)0x00000008) +#define USART_INT_PE ((u32)0x00000010) +#define USART_INT_FE ((u32)0x00000020) +#define USART_INT_BI ((u32)0x00000040) +#define USART_INT_RSADD ((u32)0x00000080) +#define USART_INT_TOUT ((u32)0x00000100) +#define USART_INT_CTS ((u32)0x00000200) + +#define IS_USART_INT(INT) ((((INT) & 0xFFFFFC00) == 0) && ((INT) != 0)) +#endif +/** + * @} + */ + +/* USART Flags ---------------------------------------------------------------------------------------------*/ +/** @defgroup USART_Flag Definitions of USART flags + * @{ + */ +#if (LIBCFG_USART_V01) +#define USART_FLAG_RXDNE ((u32)0x00000001) +#define USART_FLAG_THRE ((u32)0x00000020) +#define USART_FLAG_TXC ((u32)0x00000040) +#define USART_FLAG_ERR ((u32)0x00000080) + +#define USART_FLAG_FROM_IIR ((u32)0x00000800) +#define USART_FLAG_MODIS ((u32)0x00000800) +#define USART_FLAG_TXDE ((u32)0x00000802) +#define USART_FLAG_RXDR ((u32)0x00000804) +#define USART_FLAG_RLSI ((u32)0x00000806) +#define USART_FLAG_TOUT ((u32)0x0000080C) + +#if (LIBCFG_USART_V01_LEGACY) +#define USART_LSR_RFDR (USART_FLAG_RXDNE) +#define USART_LSR_THRE (USART_FLAG_THRE) +#define USART_LSR_TE (USART_FLAG_TXC) +#define USART_LSR_ERR (USART_FLAG_ERR) +#endif + +#define IS_USART_FLAG(FLAG) ((FLAG == USART_FLAG_RXDNE) || \ + (FLAG == USART_FLAG_THRE) || \ + (FLAG == USART_FLAG_TXC) || \ + (FLAG == USART_FLAG_ERR) || \ + (FLAG == USART_FLAG_TXDE) || \ + (FLAG == USART_FLAG_RXDR) || \ + (FLAG == USART_FLAG_TOUT)) + +#define USART_LSR_OE ((u32)0x00000002) +#define USART_LSR_PE ((u32)0x00000004) +#define USART_LSR_FE ((u32)0x00000008) +#define USART_LSR_BI ((u32)0x00000010) +#define USART_LSR_RSADD ((u32)0x00000100) + +#else +#define USART_FLAG_RXDNE ((u32)0x00000001) +#define USART_FLAG_OE ((u32)0x00000002) +#define USART_FLAG_PE ((u32)0x00000004) +#define USART_FLAG_FE ((u32)0x00000008) +#define USART_FLAG_BI ((u32)0x00000010) +#define USART_FLAG_RXDR ((u32)0x00000020) +#define USART_FLAG_TOUT ((u32)0x00000040) +#define USART_FLAG_TXDE ((u32)0x00000080) +#define USART_FLAG_TXC ((u32)0x00000100) +#define USART_FLAG_RSADD ((u32)0x00000200) +#define USART_FLAG_CTSC ((u32)0x00000400) +#define USART_FLAG_CTSS ((u32)0x00000800) + +#define IS_USART_FLAG(FLAG) ((FLAG == USART_FLAG_RXDNE) || (FLAG == USART_FLAG_OE) || \ + (FLAG == USART_FLAG_PE) || (FLAG == USART_FLAG_FE) || \ + (FLAG == USART_FLAG_BI) || (FLAG == USART_FLAG_RXDR) || \ + (FLAG == USART_FLAG_TOUT) || (FLAG == USART_FLAG_TXDE) || \ + (FLAG == USART_FLAG_TXC) || (FLAG == USART_FLAG_RSADD) || \ + (FLAG == USART_FLAG_CTSC) || (FLAG == USART_FLAG_CTSS)) + +#define IS_USART_CLEAR_FLAG(FLAG) ((FLAG == USART_FLAG_OE) || (FLAG == USART_FLAG_PE) || \ + (FLAG == USART_FLAG_FE) || (FLAG == USART_FLAG_BI) || \ + (FLAG == USART_FLAG_TOUT) || (FLAG == USART_FLAG_RSADD) || \ + (FLAG == USART_FLAG_CTSC)) +#endif +/** + * @} + */ + +/* USART RS485 definition ----------------------------------------------------------------------------------*/ +/** @defgroup USART_RS485 Definitions of USART RS485 + * @{ + */ +#define USART_RS485POLARITY_LOW ((u32)0x00000001) +#define USART_RS485POLARITY_HIGH ((u32)0xFFFFFFFE) + +#define IS_USART_RS485_POLARITY(POLARITY) ((POLARITY == USART_RS485POLARITY_LOW) || \ + (POLARITY == USART_RS485POLARITY_HIGH)) +/** + * @} + */ +#if (LIBCFG_USART_V01) +#define USART_FIFO_TX ((u32)0x00000004) +#define USART_FIFO_RX ((u32)0x00000002) +#else +#define USART_FIFO_TX ((u32)0x00000001) +#define USART_FIFO_RX ((u32)0x00000002) +#endif + +#define IS_USART_FIFO_DIRECTION(DIRECTION) ((DIRECTION == USART_FIFO_TX) || \ + (DIRECTION == USART_FIFO_RX)) + +#if (LIBCFG_USART_V01) +#define USART_STICK_LOW ((u32)0x00000010) +#define USART_STICK_HIGH ((u32)0xFFFFFFEF) +#else +#define USART_STICK_LOW ((u32)0x00001000) +#define USART_STICK_HIGH ((u32)0xFFFFEFFF) +#endif + +#define IS_USART_STICK_PARITY(PARITY) ((PARITY == USART_STICK_LOW) || (PARITY == USART_STICK_HIGH)) + +#if (LIBCFG_USART_V01) +#define USART_PDMAREQ_TX ((u32)0x00000010) +#define USART_PDMAREQ_RX ((u32)0x00000020) +#else +#define USART_PDMAREQ_TX ((u32)0x00000040) +#define USART_PDMAREQ_RX ((u32)0x00000080) +#endif + +#define IS_USART_PDMA_REQ(REQ) ((REQ == USART_PDMAREQ_TX) || (REQ == USART_PDMAREQ_RX)) + +#define IS_USART(USART) ((USART == HT_USART0) || \ + (IS_USART1(USART)) || \ + (USART == HT_UART0) || \ + (USART == HT_UART1)) + +#if (LIBCFG_NO_USART1) +#define IS_USART1(x) (0) +#else +#define IS_USART1(x) (x == HT_USART1) +#endif + +#define IS_USART_BAUDRATE(BAUDRATE) ((BAUDRATE > 0) && (BAUDRATE < 0x0044AA21)) +#define IS_USART_DATA(DATA) (DATA <= 0x1FF) +#define IS_USART_GUARD_TIME(TIME) (TIME <= 0xFF) +#define IS_USART_IRDA_PRESCALER(PRESCALER) (PRESCALER <= 0xFF) +#define IS_USART_TIMEOUT(TIMEOUT) (TIMEOUT <= 0x7F) +#define IS_USART_ADDRESS_MATCH_VALUE(VALUE) (VALUE <= 0xFF) +/** + * @} + */ + +#if (LIBCFG_USART_V01) +/* USART Modem definition ----------------------------------------------------------------------------------*/ +/** @defgroup USART_MODEM Definitions of USART Modem + * @{ + */ +#define USART_MODEM_DTR ((u32)0x00000000) +#define USART_MODEM_RTS ((u32)0x00000001) + +#define IS_USART_MODEM_PIN(PIN) ((PIN == USART_MODEM_DTR) || (PIN == USART_MODEM_RTS)) + +#define USART_MODEMSTATE_HIGH ((u32)0x00000000) +#define USART_MODEMSTATE_LOW ((u32)0x00000001) + +#define IS_USART_MODEM_STATE(STATE) ((STATE == USART_MODEMSTATE_HIGH) || (STATE == USART_MODEMSTATE_LOW)) +/** + * @} + */ +#endif + +/* Exported functions --------------------------------------------------------------------------------------*/ +/** @defgroup USART_Exported_Functions USART exported functions + * @{ + */ +#define USART_TxCmd(USARTx, NewState) USART_TxRxCmd(USARTx, USART_CMD_TX, NewState) +#define USART_RxCmd(USARTx, NewState) USART_TxRxCmd(USARTx, USART_CMD_RX, NewState) + +#define USART_TxPDMACmd(USARTx, NewState) USART_PDMACmd(USARTx, USART_PDMAREQ_TX, NewState) +#define USART_RxPDMACmd(USARTx, NewState) USART_PDMACmd(USARTx, USART_PDMAREQ_RX, NewState) + +#define USART_RXTLConfig(USARTx, USART_tl) USART_TXRXTLConfig(USARTx, USART_CMD_RX, USART_tl) +#define USART_TXTLConfig(USARTx, USART_tl) USART_TXRXTLConfig(USARTx, USART_CMD_TX, USART_tl) + +#define USART_IrDAInvtOutputCmd(USARTx, NewState) USART_IrDAInvtCmd(USARTx, USART_CMD_OUT, NewState) +#define USART_IrDAInvtInputCmd(USARTx, NewState) USART_IrDAInvtCmd(USARTx, USART_CMD_IN, NewState) + +void USART_DeInit(HT_USART_TypeDef* USARTx); +void USART_Init(HT_USART_TypeDef* USARTx, USART_InitTypeDef* USART_InitStructure); +void USART_StructInit(USART_InitTypeDef* USART_InitStructure); +void USART_SendData(HT_USART_TypeDef* USARTx, u16 Data); +u16 USART_ReceiveData(HT_USART_TypeDef* USARTx); +FlagStatus USART_GetFlagStatus(HT_USART_TypeDef* USARTx, u32 USART_FLAG_x); +#if (LIBCFG_USART_V01) +#else +FlagStatus USART_GetIntStatus(HT_USART_TypeDef* USARTx, u32 USART_FLAG_x); +void USART_ClearFlag(HT_USART_TypeDef* USARTx, u32 USART_Flag); +#endif +void USART_IntConfig(HT_USART_TypeDef* USARTx, u32 USART_INT_x, ControlStatus NewState); +void USART_TxRxCmd(HT_USART_TypeDef* USARTx,u32 TxRx, ControlStatus NewState); +void USART_PDMACmd(HT_USART_TypeDef* USARTx, u32 USART_PDMAREQ, ControlStatus NewState); +void USART_ForceBreakCmd(HT_USART_TypeDef* USARTx, ControlStatus NewState); +void USART_StickParityCmd(HT_USART_TypeDef* USARTx, ControlStatus NewState); +void USART_StickParityConfig(HT_USART_TypeDef* USARTx, u32 USART_StickParity); + +void USART_SetGuardTime(HT_USART_TypeDef* USARTx, u32 USART_GuardTime); +void USART_TXRXTLConfig(HT_USART_TypeDef* USARTx, u32 TxRx, u32 USART_tl); +void USART_SetTimeOutValue(HT_USART_TypeDef* USARTx, u32 USART_TimeOut); +void USART_FIFOReset(HT_USART_TypeDef* USARTx, u32 USART_FIFODirection); +u8 USART_GetFIFOStatus(HT_USART_TypeDef* USARTx, u32 USART_FIFODirection); +void USART_HardwareFlowControlCmd(HT_USART_TypeDef* USARTx, ControlStatus NewState); + +void USART_IrDACmd(HT_USART_TypeDef* USARTx, ControlStatus NewState); +void USART_IrDAConfig(HT_USART_TypeDef* USARTx, u32 USART_IrDAMode); +void USART_SetIrDAPrescaler(HT_USART_TypeDef* USARTx, u32 USART_IrDAPrescaler); +void USART_IrDADirectionConfig(HT_USART_TypeDef* USARTx, u32 USART_IrDADirection); +void USART_IrDAInvtCmd(HT_USART_TypeDef* USARTx, u32 inout, ControlStatus NewState); + +void USART_RS485TxEnablePolarityConfig(HT_USART_TypeDef* USARTx, u32 USART_RS485Polarity); +void USART_RS485NMMCmd(HT_USART_TypeDef* USARTx, ControlStatus NewState); +void USART_RS485AADCmd(HT_USART_TypeDef* USARTx, ControlStatus NewState); +void USART_SetAddressMatchValue(HT_USART_TypeDef* USARTx, u32 USART_AddressMatchValue); + +void USART_SynClockInit(HT_USART_TypeDef* USARTx, USART_SynClock_InitTypeDef* USART_SynClock_InitStruct); +void USART_SynClockStructInit(USART_SynClock_InitTypeDef* USART_SynClock_InitStruct); + +#if (LIBCFG_USART_V01) +#if (LIBCFG_USART_V01_LEGACY) +#define USART_GetLineStatus USART_GetFlagStatus +#endif + +void USART_ForceModemPinState(HT_USART_TypeDef* USARTx, u32 USART_ModemPin, u32 USART_ModemState); +u8 USART_GetModemStatus(HT_USART_TypeDef* USARTx); +#define USART_TimeOutIntConfig(USARTx, NewState) USART_IntConfig(USARTx, USART_INT_TOUT, NewState) +//void USART_TimeOutIntConfig(HT_USART_TypeDef* USARTx, ControlStatus NewState); +u8 USART_GetIntID(HT_USART_TypeDef* USARTx); +u32 USART_GetLineStatusValue(HT_USART_TypeDef* USARTx); +#endif +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/inc/ht32f1xxxx_usbd.h b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/inc/ht32f1xxxx_usbd.h new file mode 100644 index 0000000000..8f616a245b --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/inc/ht32f1xxxx_usbd.h @@ -0,0 +1,325 @@ +/*********************************************************************************************************//** + * @file ht32f1xxxx_usbd.h + * @version $Rev:: 1670 $ + * @date $Date:: 2019-04-09 #$ + * @brief The header file of the USB Device Driver. + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------------------------------------*/ +#ifndef __HT32F1XXXX_USBD_H +#define __HT32F1XXXX_USBD_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------------------------------------*/ +#include "ht32f1xxxx_01_usbdconf.h" +#include "ht32f1xxxx_usbdinit.h" + +/** @addtogroup HT32F1xxxx_Peripheral_Driver HT32F1xxxx Peripheral Driver + * @{ + */ + +/** @defgroup USBDevice USB Device + * @brief USB Device driver modules + * @{ + */ + + +/* Settings ------------------------------------------------------------------------------------------------*/ +/** @defgroup USBDevice_Settings USB Device settings + * @{ + */ +#define MAX_EP_NUM (8) +/** + * @} + */ + +/* Exported types ------------------------------------------------------------------------------------------*/ +/** @defgroup USBDevice_Exported_Types USB Device exported types + * @{ + */ +/* USB Endpoint number */ +typedef enum +{ + USBD_EPT0 = 0, + USBD_EPT1 = 1, + USBD_EPT2 = 2, + USBD_EPT3 = 3, + USBD_EPT4 = 4, + USBD_EPT5 = 5, + USBD_EPT6 = 6, + USBD_EPT7 = 7, + USBD_NOEPT = -1, +} USBD_EPTn_Enum; + +typedef enum +{ + USBD_TCR_0 = 0, + USBD_TCR_1 = 16, +} USBD_TCR_Enum; + +typedef enum +{ + USBD_NAK = 0, + USBD_ACK = 1 +} USBD_Handshake_Enum; + +/* Endpoint CFGR Register */ +typedef struct _EPTCFGR_BIT +{ + vu32 EPBUFA: 10; + vu32 EPLEN : 10; + vu32 _RES0 : 3; + vu32 SDBS : 1; + vu32 EPADR : 4; + vu32 EPDIR : 1; + vu32 EPTYPE: 1; + vu32 _RES1 : 1; + vu32 EPEN : 1; +} USBD_EPTCFGR_Bit; + +typedef union _EPTCFGR_TYPEDEF +{ + USBD_EPTCFGR_Bit bits; + u32 word; +} USBD_EPTCFGR_TypeDef; + +/* Endpoint CFGR and IER Register */ +typedef struct +{ + USBD_EPTCFGR_TypeDef CFGR; + u32 IER; +} USBD_EPTInit_TypeDef; + +/* Endpoint 0 ~ MAX_EP_NUM */ +typedef struct +{ + u32 uInterruptMask; + USBD_EPTInit_TypeDef ept[MAX_EP_NUM]; +} USBD_Driver_TypeDef; +/** + * @} + */ + +/* Exported constants --------------------------------------------------------------------------------------*/ +/** @defgroup USBDevice_Exported_Constants USB Device exported constants + * @{ + */ + +/* USB Interrupt Enable Register (USBIER) */ +#define UGIE ((u32)0x00000001) /*!< USB global Interrupt Enable */ +#define SOFIE ((u32)0x00000002) /*!< Start Of Frame Interrupt Enable */ +#define URSTIE ((u32)0x00000004) /*!< USB Reset Interrupt Enable */ +#define RSMIE ((u32)0x00000008) /*!< Resume Interrupt Enable */ +#define SUSPIE ((u32)0x00000010) /*!< Suspend Interrupt Enable */ +#define ESOFIE ((u32)0x00000020) /*!< Expected Start Of Frame Interrupt Enable */ +#define FRESIE ((u32)0x00000040) /*!< Force USB Reset Control Interrupt Enable */ +#define EP0IE ((u32)0x00000100) /*!< Endpoint 0 Interrupt Enable */ +#define EP1IE ((u32)0x00000200) /*!< Endpoint 1 Interrupt Enable */ +#define EP2IE ((u32)0x00000400) /*!< Endpoint 2 Interrupt Enable */ +#define EP3IE ((u32)0x00000800) /*!< Endpoint 3 Interrupt Enable */ +#define EP4IE ((u32)0x00001000) /*!< Endpoint 4 Interrupt Enable */ +#define EP5IE ((u32)0x00002000) /*!< Endpoint 5 Interrupt Enable */ +#define EP6IE ((u32)0x00004000) /*!< Endpoint 6 Interrupt Enable */ +#define EP7IE ((u32)0x00008000) /*!< Endpoint 7 Interrupt Enable */ + +/* USB Interrupt Status Register (USBISR) */ +#define SOFIF ((u32)0x00000002) /*!< Start Of Frame Interrupt Flag */ +#define URSTIF ((u32)0x00000004) /*!< USB Reset Interrupt Flag */ +#define RSMIF ((u32)0x00000008) /*!< Resume Interrupt Flag */ +#define SUSPIF ((u32)0x00000010) /*!< Suspend Interrupt Flag */ +#define ESOFIF ((u32)0x00000020) /*!< Expected Start Of Frame Interrupt Flag */ +#define FRESIF ((u32)0x00000040) /*!< Force USB Reset Control Interrupt Flag */ +#define EP0IF ((u32)0x00000100) /*!< Endpoint 0 Interrupt flag */ +#define EP1IF ((u32)0x00000200) /*!< Endpoint 1 Interrupt flag */ +#define EP2IF ((u32)0x00000400) /*!< Endpoint 2 Interrupt flag */ +#define EP3IF ((u32)0x00000800) /*!< Endpoint 3 Interrupt flag */ +#define EP4IF ((u32)0x00001000) /*!< Endpoint 4 Interrupt flag */ +#define EP5IF ((u32)0x00002000) /*!< Endpoint 5 Interrupt flag */ +#define EP6IF ((u32)0x00004000) /*!< Endpoint 6 Interrupt flag */ +#define EP7IF ((u32)0x00008000) /*!< Endpoint 7 Interrupt flag */ +#define EPnIF ((u32)0x0000FF00) /*!< Endpoint n Interrupt flag */ + +/* USB Endpoint n Interrupt Enable Register (USBEPnIER) */ +#define OTRXIE ((u32)0x00000001) /*!< OUT Token Received Interrupt Enable */ +#define ODRXIE ((u32)0x00000002) /*!< OUT Data Received Interrupt Enable */ +#define ODOVIE ((u32)0x00000004) /*!< OUT Data Buffer Overrun Interrupt Enable */ +#define ITRXIE ((u32)0x00000008) /*!< IN Token Received Interrupt Enable */ +#define IDTXIE ((u32)0x00000010) /*!< IN Data Transmitted Interrupt Enable */ +#define NAKIE ((u32)0x00000020) /*!< NAK Transmitted Interrupt Enable */ +#define STLIE ((u32)0x00000040) /*!< STALL Transmitted Interrupt Enable */ +#define UERIE ((u32)0x00000080) /*!< USB Error Interrupt Enable */ +#define STRXIE ((u32)0x00000100) /*!< SETUP Token Received Interrupt Enable */ +#define SDRXIE ((u32)0x00000200) /*!< SETUP Data Received Interrupt Enable */ +#define SDERIE ((u32)0x00000400) /*!< SETUP Data Error Interrupt Enable */ +#define ZLRXIE ((u32)0x00000800) /*!< Zero Length Data Received Interrupt Enable */ + +/* USB Endpoint n Interrupt Status Register (USBEPnISR) */ +#define OTRXIF ((u32)0x00000001) /*!< OUT Token Received Interrupt Flag */ +#define ODRXIF ((u32)0x00000002) /*!< OUT Data Received Interrupt Flag */ +#define ODOVIF ((u32)0x00000004) /*!< OUT Data Buffer Overrun Interrupt Flag */ +#define ITRXIF ((u32)0x00000008) /*!< IN Token Received Interrupt Flag */ +#define IDTXIF ((u32)0x00000010) /*!< IN Data Transmitted Interrupt Flag */ +#define NAKIF ((u32)0x00000020) /*!< NAK Transmitted Interrupt Flag */ +#define STLIF ((u32)0x00000040) /*!< STALL Transmitted Interrupt Flag */ +#define UERIF ((u32)0x00000080) /*!< USB Error Interrupt Flag */ +#define STRXIF ((u32)0x00000100) /*!< SETUP Token Received Interrupt Flag */ +#define SDRXIF ((u32)0x00000200) /*!< SETUP Data Received Interrupt Flag */ +#define SDERIF ((u32)0x00000400) /*!< SETUP Data Error Interrupt Flag */ +#define ZLRXIF ((u32)0x00000800) /*!< Zero Length Data Received Interrupt Flag */ + +/* USB Endpoint n Control and Status Register (USBEPnCSR) */ +#define DTGTX ((u32)0x00000001) /*!< Data Toggle Status, for IN transfer */ +#define NAKTX ((u32)0x00000002) /*!< NAK Status, for IN transfer */ +#define STLTX ((u32)0x00000004) /*!< STALL Status, for IN transfer */ +#define DTGRX ((u32)0x00000008) /*!< Data Toggle Status, for OUT transfer */ +#define NAKRX ((u32)0x00000010) /*!< NAK Status, for OUT transfer */ +#define STLRX ((u32)0x00000020) /*!< STALL Status, for OUT transfer */ + +/* For USBD_EPTGetTranssferCount function */ +#define USBD_CNTB0 (USBD_TCR_0) +#define USBD_CNTB1 (USBD_TCR_1) +#define USBD_CNTIN (USBD_TCR_0) +#define USBD_CNTOUT (USBD_TCR_1) +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------------------------------------*/ +/** @defgroup USBDevice_Exported_Macro USB Device exported macro + * @{ + */ +/* API macro for USB Core - Global event and operation */ +#define API_USB_INIT(driver) (USBD_Init(driver)) +#define API_USB_DEINIT() (USBD_DeInit()) +#define API_USB_POWER_UP(driver, power) (USBD_PowerUp(driver, power)) +#define API_USB_POWER_OFF() (USBD_PowerOff()) +#define API_USB_POWER_ON() (USBD_PowerOn()) +#define API_USB_REMOTE_WAKEUP() (USBD_RemoteWakeup()) +#define API_USB_READ_SETUP(buffer) (USBD_ReadSETUPData((u32 *)(buffer))) +#define API_USB_SET_ADDR(addr) (USBD_SetAddress(addr)) +#define API_USB_GET_CTRL_IN_LEN() (USBD_EPTGetBufferLen(USBD_EPT0)) +#define API_USB_ENABLE_INT(flag) (USBD_EnableINT(flag)) +#define API_USB_GET_INT() (USBD_GetINT()) +#define API_USB_GET_EPT_NUM(flag) (USBD_GetEPTnINTNumber(flag)) +#define API_USB_IS_SETUP_INT(flag) (flag & SDRXIF) +#define API_USB_CLR_SETUP_INT() (USBD_EPTClearINT(USBD_EPT0, SDRXIF)) +#define API_USB_IS_RESET_INT(flag) (flag & URSTIF) +#define API_USB_CLR_RESET_INT() (USBD_ClearINT(URSTIF)) +#define API_USB_IS_SOF_INT(flag) (flag & SOFIF) +#define API_USB_CLR_SOF_INT() (USBD_ClearINT(SOFIF)) +#define API_USB_IS_FRES_INT(flag) (flag & FRESIF) +#define API_USB_CLR_FRES_INT() (USBD_ClearINT(FRESIF)) +#define API_USB_IS_RESUME_INT(flag) (flag & RSMIF) +#define API_USB_CLR_RESUME_INT() (USBD_ClearINT(RSMIF)) +#define API_USB_IS_SUSPEND_INT(flag) (flag & SUSPIF) +#define API_USB_CLR_SUSPEND_INT() (USBD_ClearINT(SUSPIF)) +#define API_USB_IS_EPTn_INT(flag, EPTn) (flag & (EP0IF << EPTn)) +#define API_USB_CLR_EPTn_INT(EPTn) (USBD_ClearINT(EP0IF << EPTn)) + +/* API macro for USB Core - Endpoint event and operation */ +#define API_USB_EPTn_INIT(EPTn, driver) (USBD_EPTInit(EPTn, driver)) +#define API_USB_EPTn_RESET(EPTn) (USBD_EPTReset(EPTn)) +#define API_USB_EPTn_SEND_STALL(EPTn) (USBD_EPTSendSTALL(EPTn)) +#define API_USB_EPTn_GET_INT(EPTn) (USBD_EPTGetINT(EPTn)) +#define API_USB_EPTn_IS_IN_INT(flag) (flag & IDTXIF) +#define API_USB_EPTn_CLR_IN_INT(EPTn) (USBD_EPTClearINT(EPTn, IDTXIF)) +#define API_USB_EPTn_IS_OUT_INT(flag) (flag & ODRXIF) +#define API_USB_EPTn_CLR_OUT_INT(EPTn) (USBD_EPTClearINT(EPTn, ODRXIF)) +#define API_USB_EPTn_IS_INT(flag) (flag & (ODRXIF | IDTXIF)) +#define API_USB_EPTn_CLR_INT(EPTn) (USBD_EPTClearINT(EPTn, (ODRXIF | IDTXIF))) +#define API_USB_EPTn_GET_HALT(EPTn) (USBD_EPTGetHalt(EPTn)) +#define API_USB_EPTn_SET_HALT(EPTn) (USBD_EPTSetHalt(EPTn)) +#define API_USB_EPTn_CLR_HALT(EPTn) (USBD_EPTClearHalt(EPTn)) +#define API_USB_EPTn_WAIT_STALL_SENT(EPTn) (USBD_EPTWaitSTALLSent(EPTn)) +#define API_USB_EPTn_CLR_DTG(EPTn) (USBD_EPTClearDTG(EPTn)) +#define API_USB_EPTn_GET_BUFFLEN(EPTn) (USBD_EPTGetBufferLen(EPTn)) +#define API_USB_EPTn_GET_CNT(EPTn, type) (USBD_EPTGetTransferCount(EPTn, type)) +#define API_USB_EPTn_WRITE_IN(EPTn, from, len) (USBD_EPTWriteINData(EPTn, from, len)) +#define API_USB_EPTn_READ_OUT(EPTn, to, len) (USBD_EPTReadOUTData(EPTn, to, len)) +#define API_USB_EPTn_READ_MEM(EPTn, to, len) (USBD_EPTReadMemory(EPTn, to, len)) +/** + * @} + */ + +/* Exported functions --------------------------------------------------------------------------------------*/ +/** @defgroup USBDevice_Exported_Functions USB Device exported functions + * @{ + */ +void USBD_Init(u32 *pDriver); +void USBD_PreInit(USBD_Driver_TypeDef *pDriver); +void USBD_DPpullupCmd(ControlStatus NewState); +void USBD_DPWakeUpCmd(ControlStatus NewState); +void USBD_DeInit(void); +void USBD_PowerUp(u32 *pDriver, u32 uIsSelfPowered); +void USBD_PowerOff(void); +void USBD_PowerOn(void); +void USBD_SRAMResetConditionCmd(ControlStatus NewState); +void USBD_DisableDefaultPull(void); +void USBD_RemoteWakeup(void); +void USBD_ReadSETUPData(u32 *pBuffer); +void USBD_SetAddress(u32 address); +void USBD_EnableINT(u32 INTFlag); +void USBD_DisableINT(u32 INTFlag); +u32 USBD_GetINT(void); +void USBD_ClearINT(u32 INTFlag); +USBD_EPTn_Enum USBD_GetEPTnINTNumber(u32 INTFlag); + +void USBD_EPTInit(USBD_EPTn_Enum USBD_EPTn, u32 *pDriver); +void USBD_EPTReset(USBD_EPTn_Enum USBD_EPTn); +void USBD_EPTEnableINT(USBD_EPTn_Enum USBD_EPTn, u32 INTFlag); +u32 USBD_EPTGetINT(USBD_EPTn_Enum USBD_EPTn); +void USBD_EPTClearINT(USBD_EPTn_Enum USBD_EPTn, u32 INTFlag); +void USBD_EPTSendSTALL(USBD_EPTn_Enum USBD_EPTn); +u32 USBD_EPTGetHalt(USBD_EPTn_Enum USBD_EPTn); +void USBD_EPTSetHalt(USBD_EPTn_Enum USBD_EPTn); +void USBD_EPTClearHalt(USBD_EPTn_Enum USBD_EPTn); +void USBD_EPTWaitSTALLSent(USBD_EPTn_Enum USBD_EPTn); +void USBD_EPTClearDTG(USBD_EPTn_Enum USBD_EPTn); +u32 USBD_EPTGetBuffer0Addr(USBD_EPTn_Enum USBD_EPTn); +u32 USBD_EPTGetBuffer1Addr(USBD_EPTn_Enum USBD_EPTn); +u32 USBD_EPTGetBufferLen(USBD_EPTn_Enum USBD_EPTn); +u32 USBD_EPTGetTransferCount(USBD_EPTn_Enum USBD_EPTn, USBD_TCR_Enum USBD_TCR_0or1); +u32 USBD_EPTWriteINData(USBD_EPTn_Enum USBD_EPTn, u32 *pFrom, u32 len); +u32 USBD_EPTReadOUTData(USBD_EPTn_Enum USBD_EPTn, u32 *pTo, u32 len); +u32 USBD_EPTReadMemory(USBD_EPTn_Enum USBD_EPTn, u32 *pTo, u32 len); +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/inc/ht32f1xxxx_usbdchk.h b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/inc/ht32f1xxxx_usbdchk.h new file mode 100644 index 0000000000..0109747eb3 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/inc/ht32f1xxxx_usbdchk.h @@ -0,0 +1,504 @@ +/*********************************************************************************************************//** + * @file ht32f1xxxx_usbdchk.h + * @version $Rev:: 122 $ + * @date $Date:: 2017-06-13 #$ + * @brief The header file of the USB Device Driver. + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------------------------------------*/ +#ifndef __HT32F1XXXX_USBDCHK_H +#define __HT32F1XXXX_USBDCHK_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------------------------------------*/ + +/** @addtogroup HT32F1xxxx_Peripheral_Driver HT32F1xxxx Peripheral Driver + * @{ + */ + +/** @addtogroup USBDevice + * @{ + */ + + +/*----------------------------------------------------------------------------------------------------------*/ +/* Endpoint 0 ~ 7 and checking */ +/* !!! DO NOT MODIFY !!! */ +/*----------------------------------------------------------------------------------------------------------*/ + +/*----------------------------------------------------------------------------------------------------------*/ +/* Endpoint0 checking */ +/*----------------------------------------------------------------------------------------------------------*/ +#if (_EP0LEN != 8 && _EP0LEN != 16 && _EP0LEN != 32 && _EP0LEN != 64) + #error "USB Buffer Length (EPLEN) of Control Endpoint0 must be 8, 16, 32, or 64 bytes." +#endif + +/*----------------------------------------------------------------------------------------------------------*/ +/* Endpoint1 Configuration and checking */ +/*----------------------------------------------------------------------------------------------------------*/ +#if (_EP1_ENABLE == 1) + #if (_EP1_TYPR == EP_TYPE_BULK) + #if (_EP1LEN != 8 && _EP1LEN != 16 && _EP1LEN != 32 && _EP1LEN != 64) + #error "USB Buffer Length (EPLEN) of Endpoint1 must be 8, 16, 32, or 64 bytes under Bulk transfer." + #endif + #endif + #if (_EP1LEN > 64) + #error "USB Buffer Length (EPLEN) of Endpoint1 must be less than 64 bytes." + #endif + #if (_EP1LEN == 0) + #error "USB Buffer Length (EPLEN) of Endpoint1 cannot be 0 byte." + #endif + #if ((_EP1LEN & 0x3) != 0x0) + #error "USB Buffer Length (EPLEN) of Endpoint1 must be a multiple of 4 (word-aligned)." + #endif +#endif + +/*----------------------------------------------------------------------------------------------------------*/ +/* Endpoint2 checking */ +/*----------------------------------------------------------------------------------------------------------*/ +#if (_EP2_ENABLE == 1) + #if (_EP2_TYPR == EP_TYPE_BULK) + #if (_EP2LEN != 8 && _EP2LEN != 16 && _EP2LEN != 32 && _EP2LEN != 64) + #error "USB Buffer Length (EPLEN) of Endpoint2 must be 8, 16, 32, or 64 bytes under Bulk transfer." + #endif + #endif + #if (_EP2LEN > 64) + #error "USB Buffer Length (EPLEN) of Endpoint2 must be less than 64 bytes." + #endif + #if (_EP2LEN == 0) + #error "USB Buffer Length (EPLEN) of Endpoint2 cannot be 0 byte." + #endif + #if ((_EP2LEN & 0x3) != 0x0) + #error "USB Buffer Length (EPLEN) of Endpoint2 must be a multiple of 4 (word-aligned)." + #endif +#endif + +/*----------------------------------------------------------------------------------------------------------*/ +/* Endpoint3 checking */ +/*----------------------------------------------------------------------------------------------------------*/ +#if (_EP3_ENABLE == 1) + #if (_EP3_TYPR == EP_TYPE_BULK) + #if (_EP3LEN != 8 && _EP3LEN != 16 && _EP3LEN != 32 && _EP3LEN != 64) + #error "USB Buffer Length (EPLEN) of Endpoint3 must be 8, 16, 32, or 64 bytes under Bulk transfer." + #endif + #endif + #if (_EP3LEN > 64) + #error "USB Buffer Length (EPLEN) of Endpoint3 must be less than 64 bytes." + #endif + #if (_EP3LEN == 0) + #error "USB Buffer Length (EPLEN) of Endpoint3 cannot be 0 byte." + #endif + #if ((_EP3LEN & 0x3) != 0x0) + #error "USB Buffer Length (EPLEN) of Endpoint3 must be a multiple of 4 (word-aligned)." + #endif +#endif + +/*----------------------------------------------------------------------------------------------------------*/ +/* Endpoint4 checking */ +/*----------------------------------------------------------------------------------------------------------*/ +#if (_EP4_ENABLE == 1) + #if (_EP4_TYPR == EP_TYPE_BULK) + #if (_EP4LEN != 8 && _EP4LEN != 16 && _EP4LEN != 32 && _EP4LEN != 64) + #error "USB Buffer Length (EPLEN) of Endpoint4 must be 8, 16, 32, or 64 bytes under Bulk transfer." + #endif + #endif + #if (_EP4_TYPR == EP_TYPE_INT) + #if (_EP4LEN > 64) + #error "USB Buffer Length (EPLEN) of Endpoint4 must be less than 64 bytes under Interrupt transfer." + #endif + #endif + #if (_EP4_TYPR == EP_TYPE_ISO) + #if (_EP4LEN > 1023) + #error "USB Buffer Length (EPLEN) of Endpoint4 must be less than 1023 bytes under Isochronous transfer." + #endif + #endif + #if (_EP4LEN == 0) + #error "USB Buffer Length (EPLEN) of Endpoint4 cannot be 0 byte." + #endif + #if ((_EP4LEN & 0x3) != 0x0) + #error "USB Buffer Length (EPLEN) of Endpoint4 must be a multiple of 4 (word-aligned)." + #endif +#endif + +/*----------------------------------------------------------------------------------------------------------*/ +/* Endpoint5 checking */ +/*----------------------------------------------------------------------------------------------------------*/ +#if (_EP5_ENABLE == 1) + #if (_EP5_TYPR == EP_TYPE_BULK) + #if (_EP5LEN != 8 && _EP5LEN != 16 && _EP5LEN != 32 && _EP5LEN != 64) + #error "USB Buffer Length (EPLEN) of Endpoint5 must be 8, 16, 32, or 64 bytes under Bulk transfer." + #endif + #endif + #if (_EP5_TYPR == EP_TYPE_INT) + #if (_EP5LEN > 64) + #error "USB Buffer Length (EPLEN) of Endpoint5 must be less than 64 bytes under Interrupt transfer." + #endif + #endif + #if (_EP5_TYPR == EP_TYPE_ISO) + #if (_EP5LEN > 1023) + #error "USB Buffer Length (EPLEN) of Endpoint5 must be less than 1023 bytes under Isochronous transfer." + #endif + #endif + #if (_EP5LEN == 0) + #error "USB Buffer Length (EPLEN) of Endpoint5 cannot be 0 byte." + #endif + #if ((_EP5LEN & 0x3) != 0x0) + #error "USB Buffer Length (EPLEN) of Endpoint5 must be a multiple of 4 (word-aligned)." + #endif +#endif + +/*----------------------------------------------------------------------------------------------------------*/ +/* Endpoint6 checking */ +/*----------------------------------------------------------------------------------------------------------*/ +#if (_EP6_ENABLE == 1) + #if (_EP6_TYPR == EP_TYPE_BULK) + #if (_EP6LEN != 8 && _EP6LEN != 16 && _EP6LEN != 32 && _EP6LEN != 64) + #error "USB Buffer Length (EPLEN) of Endpoint6 must be 8, 16, 32, or 64 bytes under Bulk transfer." + #endif + #endif + #if (_EP6_TYPR == EP_TYPE_INT) + #if (_EP6LEN > 64) + #error "USB Buffer Length (EPLEN) of Endpoint6 must be less than 64 bytes under Interrupt transfer." + #endif + #endif + #if (_EP6_TYPR == EP_TYPE_ISO) + #if (_EP6LEN > 1023) + #error "USB Buffer Length (EPLEN) of Endpoint6 must be less than 1023 bytes under Isochronous transfer." + #endif + #endif + #if (_EP6LEN == 0) + #error "USB Buffer Length (EPLEN) of Endpoint6 cannot be 0 byte." + #endif + #if ((_EP6LEN & 0x3) != 0x0) + #error "USB Buffer Length (EPLEN) of Endpoint6 must be a multiple of 4 (word-aligned)." + #endif +#endif + +/*----------------------------------------------------------------------------------------------------------*/ +/* Endpoint7 checking */ +/*----------------------------------------------------------------------------------------------------------*/ +#if (_EP7_ENABLE == 1) + #if (_EP7_TYPR == EP_TYPE_BULK) + #if (_EP7LEN != 8 && _EP7LEN != 16 && _EP7LEN != 32 && _EP7LEN != 64) + #error "USB Buffer Length (EPLEN) of Endpoint7 must be 8, 16, 32, or 64 bytes under Bulk transfer." + #endif + #endif + #if (_EP7_TYPR == EP_TYPE_INT) + #if (_EP7LEN > 64) + #error "USB Buffer Length (EPLEN) of Endpoint7 must be less than 64 bytes under Interrupt transfer." + #endif + #endif + #if (_EP7_TYPR == EP_TYPE_ISO) + #if (_EP7LEN > 1023) + #error "USB Buffer Length (EPLEN) of Endpoint7 must be less than 1023 bytes under Isochronous transfer." + #endif + #endif + #if (_EP7LEN == 0) + #error "USB Buffer Length (EPLEN) of Endpoint7 cannot be 0 byte." + #endif + #if ((_EP7LEN & 0x3) != 0x0) + #error "USB Buffer Length (EPLEN) of Endpoint7 must be a multiple of 4 (word-aligned)." + #endif +#endif + + +/*----------------------------------------------------------------------------------------------------------*/ +/* Check the endpoint address */ +/*----------------------------------------------------------------------------------------------------------*/ +#if (_EP1_ENABLE == 1) + #if (_EP1_CFG_EPADR == 0) + #error "The address of Endpoint1 (EPADR) cannot be 0." + #endif + #if (_EP2_ENABLE == 1) + #if (_EP1_CFG_EPADR == _EP2_CFG_EPADR) + #error "The address of Endpoint1 (EPADR) conflicts with Endpoint2." + #endif + #endif + #if (_EP3_ENABLE == 1) + #if (_EP1_CFG_EPADR == _EP3_CFG_EPADR) + #error "The address of Endpoint1 (EPADR) conflicts with Endpoint3." + #endif + #endif + #if (_EP4_ENABLE == 1) + #if (_EP1_CFG_EPADR == _EP4_CFG_EPADR) + #error "The address of Endpoint1 (EPADR) conflicts with Endpoint4." + #endif + #endif + #if (_EP5_ENABLE == 1) + #if (_EP1_CFG_EPADR == _EP5_CFG_EPADR) + #error "The address of Endpoint1 (EPADR) conflicts with Endpoint5." + #endif + #endif + #if (_EP6_ENABLE == 1) + #if (_EP1_CFG_EPADR == _EP6_CFG_EPADR) + #error "The address of Endpoint1 (EPADR) conflicts with Endpoint6." + #endif + #endif + #if (_EP7_ENABLE == 1) + #if (_EP1_CFG_EPADR == _EP7_CFG_EPADR) + #error "The address of Endpoint1 (EPADR) conflicts with Endpoint7." + #endif + #endif +#endif + +#if (_EP2_ENABLE == 1) + #if (_EP2_CFG_EPADR == 0) + #error "The address of Endpoint2 (EPADR) cannot be 0." + #endif + #if (_EP1_ENABLE == 1) + #if (_EP2_CFG_EPADR == _EP1_CFG_EPADR) + #error "The address of Endpoint2 (EPADR) conflicts with Endpoint1." + #endif + #endif + #if (_EP3_ENABLE == 1) + #if (_EP2_CFG_EPADR == _EP3_CFG_EPADR) + #error "The address of Endpoint2 (EPADR) conflicts with Endpoint3." + #endif + #endif + #if (_EP4_ENABLE == 1) + #if (_EP2_CFG_EPADR == _EP4_CFG_EPADR) + #error "The address of Endpoint2 (EPADR) conflicts with Endpoint4." + #endif + #endif + #if (_EP5_ENABLE == 1) + #if (_EP2_CFG_EPADR == _EP5_CFG_EPADR) + #error "The address of Endpoint2 (EPADR) conflicts with Endpoint5." + #endif + #endif + #if (_EP6_ENABLE == 1) + #if (_EP2_CFG_EPADR == _EP6_CFG_EPADR) + #error "The address of Endpoint2 (EPADR) conflicts with Endpoint6." + #endif + #endif + #if (_EP7_ENABLE == 1) + #if (_EP2_CFG_EPADR == _EP7_CFG_EPADR) + #error "The address of Endpoint2 (EPADR) conflicts with Endpoint7." + #endif + #endif +#endif + +#if (_EP3_ENABLE == 1) + #if (_EP3_CFG_EPADR == 0) + #error "The address of Endpoint3 (EPADR) cannot be 0." + #endif + #if (_EP1_ENABLE == 1) + #if (_EP3_CFG_EPADR == _EP1_CFG_EPADR) + #error "The address of Endpoint3 (EPADR) conflicts with Endpoint1." + #endif + #endif + #if (_EP2_ENABLE == 1) + #if (_EP3_CFG_EPADR == _EP2_CFG_EPADR) + #error "The address of Endpoint3 (EPADR) conflicts with Endpoint2." + #endif + #endif + #if (_EP4_ENABLE == 1) + #if (_EP3_CFG_EPADR == _EP4_CFG_EPADR) + #error "The address of Endpoint3 (EPADR) conflicts with Endpoint4." + #endif + #endif + #if (_EP5_ENABLE == 1) + #if (_EP3_CFG_EPADR == _EP5_CFG_EPADR) + #error "The address of Endpoint3 (EPADR) conflicts with Endpoint5." + #endif + #endif + #if (_EP6_ENABLE == 1) + #if (_EP3_CFG_EPADR == _EP6_CFG_EPADR) + #error "The address of Endpoint3 (EPADR) conflicts with Endpoint6." + #endif + #endif + #if (_EP7_ENABLE == 1) + #if (_EP3_CFG_EPADR == _EP7_CFG_EPADR) + #error "The address of Endpoint3 (EPADR) conflicts with Endpoint7." + #endif + #endif +#endif + +#if (_EP4_ENABLE == 1) + #if (_EP4_CFG_EPADR == 0) + #error "The address of Endpoint4 (EPADR) cannot be 0." + #endif + #if (_EP1_ENABLE == 1) + #if (_EP4_CFG_EPADR == _EP1_CFG_EPADR) + #error "The address of Endpoint4 (EPADR) conflicts with Endpoint1." + #endif + #endif + #if (_EP2_ENABLE == 1) + #if (_EP4_CFG_EPADR == _EP2_CFG_EPADR) + #error "The address of Endpoint4 (EPADR) conflicts with Endpoint2." + #endif + #endif + #if (_EP3_ENABLE == 1) + #if (_EP4_CFG_EPADR == _EP3_CFG_EPADR) + #error "The address of Endpoint4 (EPADR) conflicts with Endpoint3." + #endif + #endif + #if (_EP5_ENABLE == 1) + #if (_EP4_CFG_EPADR == _EP5_CFG_EPADR) + #error "The address of Endpoint4 (EPADR) conflicts with Endpoint5." + #endif + #endif + #if (_EP6_ENABLE == 1) + #if (_EP4_CFG_EPADR == _EP6_CFG_EPADR) + #error "The address of Endpoint4 (EPADR) conflicts with Endpoint6." + #endif + #endif + #if (_EP7_ENABLE == 1) + #if (_EP4_CFG_EPADR == _EP7_CFG_EPADR) + #error "The address of Endpoint4 (EPADR) conflicts with Endpoint7." + #endif + #endif +#endif + +#if (_EP5_ENABLE == 1) + #if (_EP5_CFG_EPADR == 0) + #error "The address of Endpoint5 (EPADR) cannot be 0." + #endif + #if (_EP1_ENABLE == 1) + #if (_EP5_CFG_EPADR == _EP1_CFG_EPADR) + #error "The address of Endpoint5 (EPADR) conflicts with Endpoint1." + #endif + #endif + #if (_EP2_ENABLE == 1) + #if (_EP5_CFG_EPADR == _EP2_CFG_EPADR) + #error "The address of Endpoint5 (EPADR) conflicts with Endpoint2." + #endif + #endif + #if (_EP3_ENABLE == 1) + #if (_EP5_CFG_EPADR == _EP3_CFG_EPADR) + #error "The address of Endpoint5 (EPADR) conflicts with Endpoint3." + #endif + #endif + #if (_EP4_ENABLE == 1) + #if (_EP5_CFG_EPADR == _EP4_CFG_EPADR) + #error "The address of Endpoint5 (EPADR) conflicts with Endpoint4." + #endif + #endif + #if (_EP6_ENABLE == 1) + #if (_EP5_CFG_EPADR == _EP6_CFG_EPADR) + #error "The address of Endpoint5 (EPADR) conflicts with Endpoint6." + #endif + #endif + #if (_EP7_ENABLE == 1) + #if (_EP5_CFG_EPADR == _EP7_CFG_EPADR) + #error "The address of Endpoint5 (EPADR) conflicts with Endpoint7." + #endif + #endif +#endif + +#if (_EP6_ENABLE == 1) + #if (_EP6_CFG_EPADR == 0) + #error "The address of Endpoint6 (EPADR) cannot be 0." + #endif + #if (_EP1_ENABLE == 1) + #if (_EP6_CFG_EPADR == _EP1_CFG_EPADR) + #error "The address of Endpoint6 (EPADR) conflicts with Endpoint1." + #endif + #endif + #if (_EP2_ENABLE == 1) + #if (_EP6_CFG_EPADR == _EP2_CFG_EPADR) + #error "The address of Endpoint6 (EPADR) conflicts with Endpoint2." + #endif + #endif + #if (_EP3_ENABLE == 1) + #if (_EP6_CFG_EPADR == _EP3_CFG_EPADR) + #error "The address of Endpoint6 (EPADR) conflicts with Endpoint3." + #endif + #endif + #if (_EP4_ENABLE == 1) + #if (_EP6_CFG_EPADR == _EP4_CFG_EPADR) + #error "The address of Endpoint6 (EPADR) conflicts with Endpoint4." + #endif + #endif + #if (_EP5_ENABLE == 1) + #if (_EP6_CFG_EPADR == _EP5_CFG_EPADR) + #error "The address of Endpoint6 (EPADR) conflicts with Endpoint5." + #endif + #endif + #if (_EP7_ENABLE == 1) + #if (_EP6_CFG_EPADR == _EP7_CFG_EPADR) + #error "The address of Endpoint6 (EPADR) conflicts with Endpoint7." + #endif + #endif +#endif + +#if (_EP7_ENABLE == 1) + #if (_EP7_CFG_EPADR == 0) + #error "The address of Endpoint1 (EPADR) cannot be 0." + #endif + #if (_EP1_ENABLE == 1) + #if (_EP7_CFG_EPADR == _EP1_CFG_EPADR) + #error "The address of Endpoint7 (EPADR) conflicts with Endpoint1." + #endif + #endif + #if (_EP2_ENABLE == 1) + #if (_EP7_CFG_EPADR == _EP2_CFG_EPADR) + #error "The address of Endpoint7 (EPADR) conflicts with Endpoint2." + #endif + #endif + #if (_EP3_ENABLE == 1) + #if (_EP7_CFG_EPADR == _EP3_CFG_EPADR) + #error "The address of Endpoint7 (EPADR) conflicts with Endpoint3." + #endif + #endif + #if (_EP4_ENABLE == 1) + #if (_EP7_CFG_EPADR == _EP4_CFG_EPADR) + #error "The address of Endpoint7 (EPADR) conflicts with Endpoint4." + #endif + #endif + #if (_EP5_ENABLE == 1) + #if (_EP7_CFG_EPADR == _EP5_CFG_EPADR) + #error "The address of Endpoint7 (EPADR) conflicts with Endpoint5." + #endif + #endif + #if (_EP6_ENABLE == 1) + #if (_EP7_CFG_EPADR == _EP6_CFG_EPADR) + #error "The address of Endpoint7 (EPADR) conflicts with Endpoint6." + #endif + #endif +#endif + + +/*----------------------------------------------------------------------------------------------------------*/ +/* Check Buffer size */ +/*----------------------------------------------------------------------------------------------------------*/ +#if ((_EP0LEN_T + _EP1LEN + _EP2LEN + _EP3LEN + _EP4LEN_T + _EP5LEN_T + _EP6LEN_T + _EP7LEN_T) > 1024) + #error "Total buffer size of Endpoint 0 ~ 7 must be less than 1024 bytes." +#endif + + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/inc/ht32f1xxxx_usbdinit.h b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/inc/ht32f1xxxx_usbdinit.h new file mode 100644 index 0000000000..b0cd17e96f --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/inc/ht32f1xxxx_usbdinit.h @@ -0,0 +1,283 @@ +/*********************************************************************************************************//** + * @file ht32f1xxxx_usbdinit.h + * @version $Rev:: 2971 $ + * @date $Date:: 2023-10-25 #$ + * @brief The header file of the USB Device Driver. + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------------------------------------*/ +#ifndef __HT32F1XXXX_USBDINIT_H +#define __HT32F1XXXX_USBDINIT_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------------------------------------*/ +#include "ht32_retarget_usbdconf.h" + +/** @addtogroup HT32F1xxxx_Peripheral_Driver HT32F1xxxx Peripheral Driver + * @{ + */ + +/** @addtogroup USBDevice + * @{ + */ + + +/*----------------------------------------------------------------------------------------------------------*/ +/* Endpoint 0 ~ 7 Configuration */ +/* !!! DO NOT MODIFY !!! */ +/*----------------------------------------------------------------------------------------------------------*/ + +#define EP_TYPE_ISO (1) +#define EP_TYPE_BULK (2) +#define EP_TYPE_INT (3) + +#ifndef _UIER_ALL + #define _UIER_ALL _UIER +#endif + +/*----------------------------------------------------------------------------------------------------------*/ +/* Endpoint0 Configuration */ +/*----------------------------------------------------------------------------------------------------------*/ +#define _EP0_CFG_EPEN (1UL) +#define _EP0STADR (HT_USB_SRAM_BASE + 0x8) +#define _EP0INTADR (_EP0STADR) +#define _EP0OUTTADR (_EP0STADR + _EP0LEN) +#define _EP0_CFG ((_EP0_CFG_EPEN << 31) | \ + (_EP0LEN << 10) | \ + (_EP0STADR & EPBUFA_MASK)) +#define _EP0LEN_T (_EP0LEN * 2) + +/*----------------------------------------------------------------------------------------------------------*/ +/* Endpoint1 Configuration */ +/*----------------------------------------------------------------------------------------------------------*/ +#define _EP1STADR (_EP0STADR + (_EP0LEN * 2)) + +#if (_EP1_ENABLE == 1) + #define _EP1LEN (_EP1LEN_TMP) +#else + #define _EP1LEN (0) +#endif + +#if (_EP1_CFG_EPEN_TMP == 1) + #define _EP1_CFG_EPEN (1UL) +#else + #define _EP1_CFG_EPEN (0UL) +#endif + +#define _EP1_CFG ((_EP1_CFG_EPEN << 31) | \ + (_EP1_CFG_EPDIR << 28) | \ + (_EP1_CFG_EPADR << 24) | \ + (_EP1LEN << 10) | \ + (_EP1STADR & EPBUFA_MASK)) + +/*----------------------------------------------------------------------------------------------------------*/ +/* Endpoint2 Configuration */ +/*----------------------------------------------------------------------------------------------------------*/ +#define _EP2STADR (_EP1STADR + _EP1LEN) + +#if (_EP2_ENABLE == 1) + #define _EP2LEN (_EP2LEN_TMP) +#else + #define _EP2LEN (0) +#endif + +#if (_EP2_CFG_EPEN_TMP == 1) + #define _EP2_CFG_EPEN (1UL) +#else + #define _EP2_CFG_EPEN (0UL) +#endif + +#define _EP2_CFG ((_EP2_CFG_EPEN << 31) | \ + (_EP2_CFG_EPDIR << 28) | \ + (_EP2_CFG_EPADR << 24) | \ + (_EP2LEN << 10) | \ + (_EP2STADR & EPBUFA_MASK)) + +/*----------------------------------------------------------------------------------------------------------*/ +/* Endpoint3 Configuration */ +/*----------------------------------------------------------------------------------------------------------*/ +#define _EP3STADR (_EP2STADR + _EP2LEN) + +#if (_EP3_ENABLE == 1) + #define _EP3LEN (_EP3LEN_TMP) +#else + #define _EP3LEN (0) +#endif + +#if (_EP3_CFG_EPEN_TMP == 1) + #define _EP3_CFG_EPEN (1UL) +#else + #define _EP3_CFG_EPEN (0UL) +#endif + +#define _EP3_CFG ((_EP3_CFG_EPEN << 31) | \ + (_EP3_CFG_EPDIR << 28) | \ + (_EP3_CFG_EPADR << 24) | \ + (_EP3LEN << 10) | \ + (_EP3STADR & EPBUFA_MASK)) + +/*----------------------------------------------------------------------------------------------------------*/ +/* Endpoint4 Configuration */ +/*----------------------------------------------------------------------------------------------------------*/ +#define _EP4STADR (_EP3STADR + _EP3LEN) + +#if (_EP4_ENABLE == 1) + #define _EP4LEN (_EP4LEN_TMP) + #define _EP4LEN_T (_EP4LEN_TMP * (_EP4_CFG_SDBS + 1)) +#else + #define _EP4LEN (0) + #define _EP4LEN_T (0) +#endif +#if (_EP4_TYPR == EP_TYPE_ISO) + #define _EP4_CFG_EPTYPE (1) +#else + #define _EP4_CFG_EPTYPE (0) +#endif + +#if (_EP4_CFG_EPEN_TMP == 1) + #define _EP4_CFG_EPEN (1UL) +#else + #define _EP4_CFG_EPEN (0UL) +#endif + +#define _EP4_CFG ((_EP4_CFG_EPEN << 31) | \ + (_EP4_CFG_EPTYPE << 29) | \ + (_EP4_CFG_EPDIR << 28) | \ + (_EP4_CFG_EPADR << 24) | \ + (_EP4_CFG_SDBS << 23) | \ + (_EP4LEN << 10) | \ + (_EP4STADR & EPBUFA_MASK)) + +/*----------------------------------------------------------------------------------------------------------*/ +/* Endpoint5 Configuration */ +/*----------------------------------------------------------------------------------------------------------*/ +#define _EP5STADR (_EP4STADR + _EP4LEN_T) + +#if (_EP5_ENABLE == 1) + #define _EP5LEN (_EP5LEN_TMP) + #define _EP5LEN_T (_EP5LEN_TMP * (_EP5_CFG_SDBS + 1)) +#else + #define _EP5LEN (0) + #define _EP5LEN_T (0) +#endif +#if (_EP5_TYPR == EP_TYPE_ISO) + #define _EP5_CFG_EPTYPE (1) +#else + #define _EP5_CFG_EPTYPE (0) +#endif + +#if (_EP5_CFG_EPEN_TMP == 1) + #define _EP5_CFG_EPEN (1UL) +#else + #define _EP5_CFG_EPEN (0UL) +#endif + +#define _EP5_CFG ((_EP5_CFG_EPEN << 31) | \ + (_EP5_CFG_EPTYPE << 29) | \ + (_EP5_CFG_EPDIR << 28) | \ + (_EP5_CFG_EPADR << 24) | \ + (_EP5_CFG_SDBS << 23) | \ + (_EP5LEN << 10) | \ + (_EP5STADR & EPBUFA_MASK)) + +/*----------------------------------------------------------------------------------------------------------*/ +/* Endpoint6 Configuration */ +/*----------------------------------------------------------------------------------------------------------*/ +#define _EP6STADR (_EP5STADR + _EP5LEN_T) + +#if (_EP6_ENABLE == 1) + #define _EP6LEN (_EP6LEN_TMP) + #define _EP6LEN_T (_EP6LEN_TMP * (_EP6_CFG_SDBS + 1)) +#else + #define _EP6LEN (0) + #define _EP6LEN_T (0) +#endif +#if (_EP6_TYPR == EP_TYPE_ISO) + #define _EP6_CFG_EPTYPE (1) +#else + #define _EP6_CFG_EPTYPE (0) +#endif + +#if (_EP6_CFG_EPEN_TMP == 1) + #define _EP6_CFG_EPEN (1UL) +#else + #define _EP6_CFG_EPEN (0UL) +#endif + +#define _EP6_CFG ((_EP6_CFG_EPEN << 31) | \ + (_EP6_CFG_EPTYPE << 29) | \ + (_EP6_CFG_EPDIR << 28) | \ + (_EP6_CFG_EPADR << 24) | \ + (_EP6_CFG_SDBS << 23) | \ + (_EP6LEN << 10) | \ + (_EP6STADR & EPBUFA_MASK)) + +/*----------------------------------------------------------------------------------------------------------*/ +/* Endpoint7 Configuration */ +/*----------------------------------------------------------------------------------------------------------*/ +#define _EP7STADR (_EP6STADR + _EP6LEN_T) + +#if (_EP7_ENABLE == 1) + #define _EP7LEN (_EP7LEN_TMP) + #define _EP7LEN_T (_EP7LEN_TMP * (_EP7_CFG_SDBS + 1)) +#else + #define _EP7LEN (0) + #define _EP7LEN_T (0) +#endif +#if (_EP7_TYPR == EP_TYPE_ISO) + #define _EP7_CFG_EPTYPE (1) +#else + #define _EP7_CFG_EPTYPE (0) +#endif + +#if (_EP7_CFG_EPEN_TMP == 1) + #define _EP7_CFG_EPEN (1UL) +#else + #define _EP7_CFG_EPEN (0UL) +#endif + +#define _EP7_CFG ((_EP7_CFG_EPEN << 31) | \ + (_EP7_CFG_EPTYPE << 29) | \ + (_EP7_CFG_EPDIR << 28) | \ + (_EP7_CFG_EPADR << 24) | \ + (_EP7_CFG_SDBS << 23) | \ + (_EP7LEN << 10) | \ + (_EP7STADR & EPBUFA_MASK)) + + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/inc/ht32f1xxxx_wdt.h b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/inc/ht32f1xxxx_wdt.h new file mode 100644 index 0000000000..c0a9c03951 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/inc/ht32f1xxxx_wdt.h @@ -0,0 +1,148 @@ +/*********************************************************************************************************//** + * @file ht32f1xxxx_wdt.h + * @version $Rev:: 122 $ + * @date $Date:: 2017-06-13 #$ + * @brief The header file of the WDT library. + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------------------------------------*/ +#ifndef __HT32F1XXXX_WDT_H +#define __HT32F1XXXX_WDT_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------------------------------------*/ +#include "ht32.h" + +/** @addtogroup HT32F1xxxx_Peripheral_Driver HT32F1xxxx Peripheral Driver + * @{ + */ + +/** @addtogroup WDT + * @{ + */ + + +/* Exported constants --------------------------------------------------------------------------------------*/ +/** @defgroup WDT_Exported_Constants WDT exported constants + * @{ + */ + +/* WDT prescaler */ +#define WDT_PRESCALER_1 ((u16)0x0000) +#define WDT_PRESCALER_2 ((u16)0x1000) +#define WDT_PRESCALER_4 ((u16)0x2000) +#define WDT_PRESCALER_8 ((u16)0x3000) +#define WDT_PRESCALER_16 ((u16)0x4000) +#define WDT_PRESCALER_32 ((u16)0x5000) +#define WDT_PRESCALER_64 ((u16)0x6000) +#define WDT_PRESCALER_128 ((u16)0x7000) + +#define IS_WDT_PRESCALER(PRESCALER) ((PRESCALER == WDT_PRESCALER_1) || \ + (PRESCALER == WDT_PRESCALER_2) || \ + (PRESCALER == WDT_PRESCALER_4) || \ + (PRESCALER == WDT_PRESCALER_8) || \ + (PRESCALER == WDT_PRESCALER_16) || \ + (PRESCALER == WDT_PRESCALER_32) || \ + (PRESCALER == WDT_PRESCALER_64) || \ + (PRESCALER == WDT_PRESCALER_128)) + + +/* WDT runs or halts in sleep and deep sleep1 mode */ +/* WDT WDTSHLT mask */ +#define MODE0_WDTSHLT_BOTH ((u32)0x00000000) +#define MODE0_WDTSHLT_SLEEP ((u32)0x00004000) +#define MODE0_WDTSHLT_HALT ((u32)0x00008000) + +#define IS_WDT_WDTSHLT_MODE(WDT_Mode) ((WDT_Mode == MODE0_WDTSHLT_BOTH) || \ + (WDT_Mode == MODE0_WDTSHLT_SLEEP) || \ + (WDT_Mode == MODE0_WDTSHLT_HALT)) + + + +/* WDT Flag */ +#define WDT_FLAG_UNDERFLOW ((u32)0x00000001) +#define WDT_FLAG_ERROR ((u32)0x00000002) + + +#define IS_WDT_FLAG(WDT_FLAG) ((WDT_FLAG == WDT_FLAG_UNDERFLOW) || \ + (WDT_FLAG == WDT_FLAG_ERROR)) + + +#define IS_WDT_RELOAD(WDTV) ((WDTV <= 0xFFF)) + +#define IS_WDT_DELTA(WDTD) ((WDTD <= 0xFFF)) + +/* WDT Source Select */ +#define WDT_SOURCE_LSI ((u32)0x00000000) +#define WDT_SOURCE_LSE ((u32)0x00000001) + + +#define IS_WDT_SOURCE_SELECT(WDT_SOURCE) ((WDT_SOURCE == WDT_SOURCE_LSI) || \ + (WDT_SOURCE == WDT_SOURCE_LSE)) +/** + * @} + */ + +/* Exported functions --------------------------------------------------------------------------------------*/ +/** @defgroup WDT_Exported_Functions WDT exported functions + * @{ + */ +void WDT_DeInit(void); +void WDT_Cmd(ControlStatus NewState); +#if (LIBCFG_WDT_INT) +void WDT_IntConfig(ControlStatus NewState); +#endif +void WDT_HaltConfig(u32 WDT_Mode); +void WDT_ResetCmd(ControlStatus NewState); +void WDT_ProtectCmd(ControlStatus NewState); +void WDT_SetReloadValue(u16 WDTV); +u16 WDT_GetReloadValue(void); +void WDT_SetDeltaValue(u16 WDTD); +u16 WDT_GetDeltaValue(void); +void WDT_SetPrescaler(u16 WDT_PRESCALER); +u8 WDT_GetPrescaler(void); +void WDT_Restart(void); +FlagStatus WDT_GetFlagStatus (u32 WDT_FLAG); +void WDT_LockCmd(ControlStatus NewState); +void WDT_SourceConfig(u32 WDT_SOURCE); +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/inc/ht32f2xxxx_csif.h b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/inc/ht32f2xxxx_csif.h new file mode 100644 index 0000000000..2460b561ba --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/inc/ht32f2xxxx_csif.h @@ -0,0 +1,302 @@ +/*********************************************************************************************************//** + * @file ht32f2xxxx_csif.h + * @version $Rev:: 122 $ + * @date $Date:: 2017-06-13 #$ + * @brief The header file of the CSIF library. + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------------------------------------*/ +#ifndef __HT32F2XXXX_CSIF_H +#define __HT32F2XXXX_CSIF_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------------------------------------*/ +#include "ht32.h" + +/** @addtogroup HT32F1xxxx_Peripheral_Driver HT32F1xxxx Peripheral Driver + * @{ + */ + +/** @addtogroup CSIF + * @{ + */ + +/* Exported types ------------------------------------------------------------------------------------------*/ + +/** @defgroup CSIF_Exported_Types CSIF exported types + * @{ + */ + +typedef struct +{ + u32 CSIF_Format; + u32 CSIF_VSYNCType; + u32 CSIF_HSYNCType; + u32 CSIF_SampleEdge; + u32 CSIF_VSYNCPolarity; + u32 CSIF_HSYNCPolarity; + u32 CSIF_LineDelay; + u32 CSIF_FrameDelay; + u32 CSIF_ImageWidth; + u32 CSIF_ImageHeight; +}CSIF_BasicInitTypeDef; + + +typedef struct +{ + u32 CSIF_Window; + u32 CSIF_HorizontalStartPoint; + u32 CSIF_VerticalStartPoint; + u32 CSIF_WindowWidth; + u32 CSIF_WindowHeight; +}CSIF_WindowInitTypeDef; + + +typedef struct +{ + u32 CSIF_SubSample; + u32 CSIF_ColumnSkipMaskLength; + u32 CSIF_RowSkipMaskLength; + u32 CSIF_ColumnSkipMask; + u32 CSIF_RowSkipMask; +}CSIF_SubSampleInitTypeDef; + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------------------------------------*/ +/** @defgroup CSIF_Exported_Constants CSIF exported constants + * @{ + */ + +#define CSIF_FORMAT_RAWRGB ((u32)0x00000000) +#define CSIF_FORMAT_YUV422 ((u32)0x00000010) + +#define IS_CSIF_FORMAT(FORMAT) ((FORMAT == CSIF_FORMAT_RAWRGB) || \ + (FORMAT == CSIF_FORMAT_YUV422)) + + +#define CSIF_VSYNCTYPE_PULSE ((u32)0x00000000) +#define CSIF_VSYNCTYPE_OVERLAP ((u32)0x00000002) + +#define IS_CSIF_VSYNC_TYPE(TYPE) ((TYPE == CSIF_VSYNCTYPE_PULSE) || \ + (TYPE == CSIF_VSYNCTYPE_OVERLAP)) + + +#define CSIF_HSYNCTYPE_CONTINUOUS ((u32)0x00000000) +#define CSIF_HSYNCTYPE_DISCONTINUOUS ((u32)0x00000004) + +#define IS_CSIF_HSYNC_TYPE(TYPE) ((TYPE == CSIF_HSYNCTYPE_CONTINUOUS) || \ + (TYPE == CSIF_HSYNCTYPE_DISCONTINUOUS)) + + +#define CSIF_SAMPLEEDGE_FALLING ((u32)0x00000000) +#define CSIF_SAMPLEEDGE_RISING ((u32)0x00000008) + +#define IS_CSIF_SAMPLE_EDGE(EDGE) ((EDGE == CSIF_SAMPLEEDGE_FALLING) || \ + (EDGE == CSIF_SAMPLEEDGE_RISING)) + + +#define CSIF_VSYNCPOLARITY_HIGH ((u32)0x00000000) +#define CSIF_VSYNCPOLARITY_LOW ((u32)0x00000040) + +#define IS_CSIF_VSYNC_POLARITY(POLARITY) ((POLARITY == CSIF_VSYNCPOLARITY_HIGH) || \ + (POLARITY == CSIF_VSYNCPOLARITY_LOW)) + + +#define CSIF_HSYNCPOLARITY_HIGH ((u32)0x00000000) +#define CSIF_HSYNCPOLARITY_LOW ((u32)0x00000080) + +#define IS_CSIF_HSYNC_POLARITY(POLARITY) ((POLARITY == CSIF_HSYNCPOLARITY_HIGH) || \ + (POLARITY == CSIF_HSYNCPOLARITY_LOW)) + + +#define CSIF_WINDOW_ENABLE ((u32)0x80000000) +#define CSIF_WINDOW_DISABLE ((u32)0x00000000) + +#define IS_CSIF_WINDOW(WINDOW) ((WINDOW == CSIF_WINDOW_ENABLE) || \ + (WINDOW == CSIF_WINDOW_DISABLE)) + + +#define CSIF_SUBSAMPLE_ENABLE ((u32)0x80000000) +#define CSIF_SUBSAMPLE_DISABLE ((u32)0x00000000) + +#define IS_CSIF_SUB_SAMPLE(SAMPLE) ((SAMPLE == CSIF_SUBSAMPLE_ENABLE) || \ + (SAMPLE == CSIF_SUBSAMPLE_DISABLE)) + + +#define CSIF_MASKLENGTH_1B ((u32)0x00000000) +#define CSIF_MASKLENGTH_2B ((u32)0x00000001) +#define CSIF_MASKLENGTH_3B ((u32)0x00000002) +#define CSIF_MASKLENGTH_4B ((u32)0x00000003) +#define CSIF_MASKLENGTH_5B ((u32)0x00000004) +#define CSIF_MASKLENGTH_6B ((u32)0x00000005) +#define CSIF_MASKLENGTH_7B ((u32)0x00000006) +#define CSIF_MASKLENGTH_8B ((u32)0x00000007) +#define CSIF_MASKLENGTH_9B ((u32)0x00000008) +#define CSIF_MASKLENGTH_10B ((u32)0x00000009) +#define CSIF_MASKLENGTH_11B ((u32)0x0000000A) +#define CSIF_MASKLENGTH_12B ((u32)0x0000000B) +#define CSIF_MASKLENGTH_13B ((u32)0x0000000C) +#define CSIF_MASKLENGTH_14B ((u32)0x0000000D) +#define CSIF_MASKLENGTH_15B ((u32)0x0000000E) +#define CSIF_MASKLENGTH_16B ((u32)0x0000000F) +#define CSIF_MASKLENGTH_17B ((u32)0x00000010) +#define CSIF_MASKLENGTH_18B ((u32)0x00000011) +#define CSIF_MASKLENGTH_19B ((u32)0x00000012) +#define CSIF_MASKLENGTH_20B ((u32)0x00000013) +#define CSIF_MASKLENGTH_21B ((u32)0x00000014) +#define CSIF_MASKLENGTH_22B ((u32)0x00000015) +#define CSIF_MASKLENGTH_23B ((u32)0x00000016) +#define CSIF_MASKLENGTH_24B ((u32)0x00000017) +#define CSIF_MASKLENGTH_25B ((u32)0x00000018) +#define CSIF_MASKLENGTH_26B ((u32)0x00000019) +#define CSIF_MASKLENGTH_27B ((u32)0x0000001A) +#define CSIF_MASKLENGTH_28B ((u32)0x0000001B) +#define CSIF_MASKLENGTH_29B ((u32)0x0000001C) +#define CSIF_MASKLENGTH_30B ((u32)0x0000001D) +#define CSIF_MASKLENGTH_31B ((u32)0x0000001E) +#define CSIF_MASKLENGTH_32B ((u32)0x0000001F) + +#define IS_CSIF_MASK_LENGTH(LENGTH) (LENGTH <= 0x1F) + + +#define CSIF_FIFO_0 ((u8)0x20) +#define CSIF_FIFO_1 ((u8)0x24) +#define CSIF_FIFO_2 ((u8)0x28) +#define CSIF_FIFO_3 ((u8)0x2C) +#define CSIF_FIFO_4 ((u8)0x30) +#define CSIF_FIFO_5 ((u8)0x34) +#define CSIF_FIFO_6 ((u8)0x38) +#define CSIF_FIFO_7 ((u8)0x3C) + +#define IS_CSIF_FIFO(FIFO) ((FIFO == CSIF_FIFO_0) || \ + (FIFO == CSIF_FIFO_1) || \ + (FIFO == CSIF_FIFO_2) || \ + (FIFO == CSIF_FIFO_3) || \ + (FIFO == CSIF_FIFO_4) || \ + (FIFO == CSIF_FIFO_5) || \ + (FIFO == CSIF_FIFO_6) || \ + (FIFO == CSIF_FIFO_7)) + +#define CSIF_INT_SOFFLG ((u32)0x00000001) +#define CSIF_INT_EOFFLG ((u32)0x00000002) +#define CSIF_INT_CAPSTA ((u32)0x00000004) +#define CSIF_INT_CAPSTS ((u32)0x00000008) +#define CSIF_INT_BADFRAME ((u32)0x00000010) +#define CSIF_INT_FIFOOVR ((u32)0x00000100) +#define CSIF_INT_FIFOEMP ((u32)0x00000200) +#define CSIF_INT_FIFOFUL ((u32)0x00000400) +#define CSIF_INT_ALL ((u32)0x0000071F) + +#define IS_CSIF_INT(INT) (((INT & 0xFFFFF8E0) == 0x0) && (INT != 0x0)) + + + +#define CSIF_FLAG_SOFFLG ((u32)0x00000001) +#define CSIF_FLAG_EOFFLG ((u32)0x00000002) +#define CSIF_FLAG_CAPSTA ((u32)0x00000004) +#define CSIF_FLAG_CAPSTS ((u32)0x00000008) +#define CSIF_FLAG_BADFRAME ((u32)0x00000010) +#define CSIF_FLAG_FIFOOVR ((u32)0x00000100) +#define CSIF_FLAG_FIFOEMP ((u32)0x00000200) +#define CSIF_FLAG_FIFOFUL ((u32)0x00000400) + +#define IS_CSIF_FLAG(FLAG) ((FLAG == CSIF_FLAG_SOFFLG) || \ + (FLAG == CSIF_FLAG_EOFFLG) || \ + (FLAG == CSIF_FLAG_CAPSTA) || \ + (FLAG == CSIF_FLAG_CAPSTS) || \ + (FLAG == CSIF_FLAG_BADFRAME) || \ + (FLAG == CSIF_FLAG_FIFOOVR) || \ + (FLAG == CSIF_FLAG_FIFOEMP) || \ + (FLAG == CSIF_FLAG_FIFOFUL)) + +#define IS_CSIF_CLEAR_FLAG(FLAG) ((FLAG == CSIF_FLAG_SOFFLG) || \ + (FLAG == CSIF_FLAG_EOFFLG) || \ + (FLAG == CSIF_FLAG_CAPSTA) || \ + (FLAG == CSIF_FLAG_CAPSTS) || \ + (FLAG == CSIF_FLAG_BADFRAME)) + + +#define IS_CSIF_LINE_DELAY(DELAY) (DELAY <= 0xFF) + +#define IS_CSIF_FRAME_DELAY(DELAY) (DELAY <= 0xFF) + +#define IS_CSIF_IMAGE_WIDTH(WIDTH) (WIDTH <= 0x800) + +#define IS_CSIF_IMAGE_HEIGHT(HEIGHT) (HEIGHT <= 0x800) + +#define IS_CSIF_HORSTART_POINT(POINT) (POINT <= 0x7FF) + +#define IS_CSIF_VERSTART_POINT(POINT) (POINT <= 0x7FF) + +#define IS_CSIF_WINDOW_WIDTH(WIDTH) (WIDTH <= 0x800) + +#define IS_CSIF_WINDOW_HEIGHT(HEIGHT) (HEIGHT <= 0x800) + +#define IS_CSIF_PRESCALER(PRESCALER) ((PRESCALER%2 == 0) && (PRESCALER != 0)) + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------------------------------------*/ +/** @defgroup CSIF_Exported_Functions CSIF exported functions + * @{ + */ +void CSIF_DeInit(void); +void CSIF_BasicInit(CSIF_BasicInitTypeDef* CSIF_BasicInitStruct); +void CSIF_BasicStructInit(CSIF_BasicInitTypeDef* CSIF_BasicInitStruct); +void CSIF_WindowInit(CSIF_WindowInitTypeDef* CSIF_WindowInitStruct); +void CSIF_WindowStructInit(CSIF_WindowInitTypeDef* CSIF_WindowInitStruct); +void CSIF_SubSampleInit(CSIF_SubSampleInitTypeDef* CSIF_SubSampleInitStruct); +void CSIF_SunSampleStructInit(CSIF_SubSampleInitTypeDef* CSIF_SubSampleInitStruct); +void CSIF_Cmd(ControlStatus NewState); +void CSIF_IntConfig(u32 CSIF_Int, ControlStatus NewState); +FlagStatus CSIF_GetFlagStatus(u32 CSIF_Flag); +void CSIF_ClearFlag(u32 CSIF_Flag); +u32 CSIF_ReceiveData(u8 CSIF_FIFO); +void CSIF_MasterClockCmd(ControlStatus NewState); +void CSIF_SetMasterClockPrescaler(u8 CSIF_Prescaler); +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/src/ht32_cm3_misc.c b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/src/ht32_cm3_misc.c new file mode 100644 index 0000000000..c9632a267d --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/src/ht32_cm3_misc.c @@ -0,0 +1,232 @@ +/*********************************************************************************************************//** + * @file ht32_cm3_misc.c + * @version $Rev:: 2437 $ + * @date $Date:: 2021-06-01 #$ + * @brief This file provides all the miscellaneous firmware functions. + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ + +/* Includes ------------------------------------------------------------------------------------------------*/ +#include "ht32_cm3_misc.h" +#include "ht32_rand.c" +#ifdef HTCFG_TIME_IPSEL +#include "ht32_time.c" +#endif + +/** @addtogroup HT32_Peripheral_Driver HT32 Peripheral Driver + * @{ + */ + +/** @defgroup MISC MISC + * @brief MISC driver modules + * @{ + */ + + +/* Private definitions -------------------------------------------------------------------------------------*/ +/** @defgroup MISC_Private_Define MISC private definitions + * @{ + */ +#define AIRCR_VECTKEY_MASK ((u32)0x05FA0000) +#define CTRL_TICKINT_SET ((u32)0x00000002) +#define CTRL_TICKINT_RESET ((u32)0xFFFFFFFD) +/** + * @} + */ + +/* Global functions ----------------------------------------------------------------------------------------*/ +/** @defgroup MISC_Exported_Functions MISC exported functions + * @{ + */ +/*********************************************************************************************************//** + * @brief Set the vector table location and Offset. + * @param NVIC_VectTable: Specify if the vector table is in FLASH or RAM. + * This parameter can be one of the following values: + * @arg NVIC_VECTTABLE_RAM + * @arg NVIC_VECTTABLE_FLASH + * @param NVIC_Offset: Vector Table base offset field. + * This value must be a multiple of 0x100. + * @retval None + ***********************************************************************************************************/ +void NVIC_SetVectorTable(u32 NVIC_VectTable, u32 NVIC_Offset) +{ + /* Check the parameters */ + Assert_Param(IS_NVIC_VECTTABLE(NVIC_VectTable)); + Assert_Param(IS_NVIC_OFFSET(NVIC_Offset)); + + SCB->VTOR = NVIC_VectTable | (NVIC_Offset & (u32)0x1FFFFF80); +} + +/*********************************************************************************************************//** + * @brief Select which low power mode to execute to the system. + * @param NVIC_LowPowerMode: Specify the new low power mode to execute to the system. + * This parameter can be one of the following values: + * @arg NVIC_LOWPOWER_SEVONPEND + * @arg NVIC_LOWPOWER_SLEEPDEEP + * @arg NVIC_LOWPOWER_SLEEPONEXIT + * @param NewState: new state of low power condition. + * This parameter can be: ENABLE or DISABLE. + * @retval None + ***********************************************************************************************************/ +void NVIC_LowPowerConfig(u8 NVIC_LowPowerMode, ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_NVIC_LOWPOWER(NVIC_LowPowerMode)); + Assert_Param(IS_CONTROL_STATUS(NewState)); + + if (NewState != DISABLE) + { + SCB->SCR |= NVIC_LowPowerMode; + } + else + { + SCB->SCR &= (u32)(~(u32)NVIC_LowPowerMode); + } +} + +/*********************************************************************************************************//** + * @brief Generate a Core (Core + NVIC) reset. + * @retval None + ***********************************************************************************************************/ +void NVIC_CoreReset(void) +{ + SCB->AIRCR = AIRCR_VECTKEY_MASK | (u32)0x01; +} + +/*********************************************************************************************************//** + * @brief Set the pending bit for a system handler. + * @param SystemHandler: Specify the system handler pending bit to be set. + * This parameter can be one of the following values: + * @arg SYSTEMHANDLER_NMI + * @arg SYSTEMHANDLER_PSV + * @arg SYSTEMHANDLER_SYSTICK + * @retval None + ***********************************************************************************************************/ +void NVIC_SetPendingSystemHandler(u32 SystemHandler) +{ + /* Check the parameters */ + Assert_Param(IS_NVIC_SYSTEMHANDLER(SystemHandler)); + + /* Set the corresponding System Handler pending bit */ + SCB->ICSR |= SystemHandler; +} + +/*********************************************************************************************************//** + * @brief Configure the SysTick clock source. + * @param SysTick_ClockSource: Specify the SysTick clock source. + * This parameter can be one of the following values: + * @arg SYSTICK_SRC_STCLK : External reference clock is selected as SysTick clock source. + * @arg SYSTICK_SRC_FCLK : AHB clock is selected as SysTick clock source. + * @retval None + ***********************************************************************************************************/ +void SYSTICK_ClockSourceConfig(u32 SysTick_ClockSource) +{ + /* Check the parameters */ + Assert_Param(IS_SYSTICK_CLOCK_SOURCE(SysTick_ClockSource)); + + if (SysTick_ClockSource == SYSTICK_SRC_FCLK) + { + SysTick->CTRL |= SYSTICK_SRC_FCLK; + } + else + { + SysTick->CTRL &= SYSTICK_SRC_STCLK; + } +} + +/*********************************************************************************************************//** + * @brief Enable or Disable the SysTick counter. + * @param SysTick_Counter: new state of the SysTick counter. + * This parameter can be one of the following values: + * @arg SYSTICK_COUNTER_DISABLE : Disable counter + * @arg SYSTICK_COUNTER_ENABLE : Enable counter + * @arg SYSTICK_COUNTER_CLEAR : Clear counter value to 0 + * @retval None + ***********************************************************************************************************/ +void SYSTICK_CounterCmd(u32 SysTick_Counter) +{ + /* Check the parameters */ + Assert_Param(IS_SYSTICK_COUNTER(SysTick_Counter)); + + if (SysTick_Counter == SYSTICK_COUNTER_CLEAR) + { + SysTick->VAL = SYSTICK_COUNTER_CLEAR; + } + else + { + if (SysTick_Counter == SYSTICK_COUNTER_ENABLE) + { + SysTick->CTRL |= SYSTICK_COUNTER_ENABLE; + } + else + { + SysTick->CTRL &= SYSTICK_COUNTER_DISABLE; + } + } +} + +/*********************************************************************************************************//** + * @brief Enable or Disable the SysTick Interrupt. + * @param NewState: new state of the SysTick Interrupt. + * This parameter can be: ENABLE or DISABLE. + * @retval None + ***********************************************************************************************************/ +void SYSTICK_IntConfig(ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_CONTROL_STATUS(NewState)); + + if (NewState != DISABLE) + { + SysTick->CTRL |= CTRL_TICKINT_SET; + } + else + { + SysTick->CTRL &= CTRL_TICKINT_RESET; + } +} + +/*********************************************************************************************************//** + * @brief Set SysTick counter reload value. + * @param SysTick_Reload: SysTick reload new value. + * This parameter must be a number between 1 and 0xFFFFFF. + * @retval None + ***********************************************************************************************************/ +void SYSTICK_SetReloadValue(u32 SysTick_Reload) +{ + /* Check the parameters */ + Assert_Param(IS_SYSTICK_RELOAD(SysTick_Reload)); + + SysTick->LOAD = SysTick_Reload; +} +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ diff --git a/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/src/ht32_rand.c b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/src/ht32_rand.c new file mode 100644 index 0000000000..5b47d8884f --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/src/ht32_rand.c @@ -0,0 +1,106 @@ +/*********************************************************************************************************//** + * @file ht32_rand.c + * @version $Rev:: 1736 $ + * @date $Date:: 2019-06-25 #$ + * @brief The rundom number function. + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ + +/* Includes ------------------------------------------------------------------------------------------------*/ +#include "ht32.h" +#include + +/* Global variables ----------------------------------------------------------------------------------------*/ +#if !(LIBCFG_ADC_V01) +__ALIGN4 static uc32 RandData[] = +{ + 0x4fffe92d, 0xb0844948, 0x94016a4c, 0x94006b0c, + 0xf4446a4c, 0x624c3440, 0x4d446b0c, 0x630c432c, + 0x2135ea4f, 0xf004688c, 0xf5a40480, 0x608c4479, + 0x2403ea42, 0x4402ea44, 0x6403ea44, 0xea42610c, + 0xea442402, 0xea444403, 0x614c6403, 0x0282eb01, + 0x67142417, 0x0283eb01, 0x22016714, 0x2100f8c1, + 0xf042688a, 0x608a0280, 0x90c4f8df, 0x2004f8d9, + 0x4a309202, 0x93036853, 0x73fff64f, 0x3004f8c9, + 0xf8d96053, 0x69d7601c, 0x2104f8d1, 0x0201f042, + 0x2104f8c1, 0x2134f8d1, 0xd5fb0752, 0x2fb0f851, + 0x0b0ff002, 0xf002684a, 0x688a0e0f, 0x0a0ff002, + 0xf00268ca, 0x690a050f, 0x040ff002, 0xf002694a, + 0x698a030f, 0xf00269c9, 0xf8d0020f, 0xf8d9c000, + 0x44c4801c, 0xeb064466, 0x4f164607, 0xf8d76006, + 0xea4bc01c, 0xeb06180e, 0xea4f460c, 0xea4c2c0a, + 0xea483505, 0xea480805, 0xea444404, 0xea435303, + 0xea426202, 0x9a057101, 0x44114431, 0x98026001, + 0x0004f8c9, 0x60789803, 0x99014803, 0x99006241, + 0xb0086301, 0x8ff0e8bd, 0x40088000, 0x01000040, + 0x400b0000, 0x400b2000 +}; +#else +__ALIGN4 static uc32 RandData[] = +{ + 0x4946b5ff, 0x6a4cb087, 0x6b0c9404, 0x6a4c9403, + 0x042d2503, 0x624c432c, 0x4d416b0c, 0x630c432c, + 0x68394f40, 0x2580463c, 0x402926f9, 0x1b890236, + 0x021e6039, 0x04114316, 0x0619430e, 0x607e430e, + 0x43160216, 0x4316041a, 0x60a6430e, 0x62212117, + 0x22014934, 0x630a3140, 0x432b6823, 0x4e326023, + 0x93056873, 0x685c4b31, 0x4c319406, 0x605c6074, + 0x69dd69f4, 0x43136b4b, 0x4a2a634b, 0x68533280, + 0xd5fc075b, 0x463a6b3b, 0x0f1b071b, 0x6b7b9302, + 0x071b6bbf, 0x073f0f1b, 0x97010f3f, 0x07176bd2, + 0x680a0f3f, 0x071746bc, 0x97000f3f, 0x0717684a, + 0x688a0f3f, 0x071246be, 0x0f1268c9, 0x68074e1a, + 0x042d69f6, 0x193419be, 0x4d181964, 0x69ed6004, + 0x011b9e02, 0x431e9f01, 0x023b042d, 0x46671964, + 0x432b033d, 0x431e9f00, 0x431e043b, 0x053b4677, + 0x0612431e, 0x07094316, 0x9a08430e, 0x18891931, + 0x48096001, 0x60419905, 0x99064808, 0x48036041, + 0x62419904, 0x63019903, 0xbdf0b00b, 0x40088000, + 0x01000040, 0x40010000, 0x400b0000, 0x400b2000, + 0x0000ffff +}; +#endif +__ALIGN4 static uc32 RandData2[] = +{ + 0x4604b510, 0x18406800, 0x46216020, 0x68084a03, + 0x4a034350, 0x60081880, 0xbd100840, 0x41c64e6d, + 0x00003039 +}; + +typedef void (*Randinit_TypeDef) (u32 *, u32, u32, u32); +u32 (*Rand_Get)(u32 *, u32); + +/* Global functions ----------------------------------------------------------------------------------------*/ +/*********************************************************************************************************//** + * @brief Rand init. + * @param uSeed + * @param uCount + * @param a + * @param b + * @retval none + ***********************************************************************************************************/ +void Rand_Init(u32 *uSeed, u32 uCount, u32 a, u32 b) +{ + Randinit_TypeDef Randinit = (Randinit_TypeDef)((u32)RandData | 0x1); + Rand_Get = (u32 (*)(u32 *, u32))((u32)RandData2 | 0x1); + Randinit(uSeed, uCount, a, b); +} diff --git a/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/src/ht32_retarget.c b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/src/ht32_retarget.c new file mode 100644 index 0000000000..27ea3a0dfd --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/src/ht32_retarget.c @@ -0,0 +1,413 @@ +/*********************************************************************************************************//** + * @file ht32_retarget.c + * @version $Rev:: 2922 $ + * @date $Date:: 2023-06-07 #$ + * @brief Retarget layer for target-dependent low level functions. + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ + +/* Includes ------------------------------------------------------------------------------------------------*/ +#include "ht32.h" +#include "ht32_board.h" + +#if defined (__CC_ARM) + #pragma import(__use_no_semihosting_swi) +#endif + +#if defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #ifndef __MICROLIB + __asm(".global __use_no_semihosting"); + #endif +#endif + +#if (_RETARGET == 1) +#include + +#if defined (__CC_ARM) + #include +#endif + +/** @addtogroup HT32_Peripheral_Driver HT32 Peripheral Driver + * @{ + */ + +/** @defgroup RETARGET Retarget + * @brief Retarget related functions + * @{ + */ + + +/* Private constants ---------------------------------------------------------------------------------------*/ +/** @defgroup RETARGET_Private_Define Retarget private definitions + * @{ + */ + +#if (RETARGET_PORT == RETARGET_ITM) +#define ITM_PORT8(n) (*((vu8 *)(0xE0000000 + 4 * n))) +#define ITM_PORT16(n) (*((vu16 *)(0xE0000000 + 4 * n))) +#define ITM_PORT32(n) (*((vu32 *)(0xE0000000 + 4 * n))) + +#define DEMCR (*((vu32 *)(0xE000EDFC))) +#define TRCENA (0x01000000) +volatile int32_t ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* For Keil MDK-ARM only */ +#endif +/** + * @} + */ + +/* Global variables ----------------------------------------------------------------------------------------*/ +/** @defgroup RETARGET_Global_Variable Retarget global variables + * @{ + */ +#if defined (__CC_ARM) +struct __FILE { int handle; /* Add whatever you need here */ }; +FILE __stdout; +FILE __stdin; +#endif + +#if defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #ifndef __MICROLIB + FILE __stdout; + FILE __stdin; + FILE __stderr; + #endif +#endif + +#if defined (__SES_ARM) && defined(__SEGGER_RTL_VERSION) +struct __SEGGER_RTL_FILE_impl { // NOTE: Provides implementation for FILE + int stub; // only needed so impl has size != 0. +}; +static FILE __SEGGER_RTL_stdin_file = { 0 }; // stdin reads from UART +static FILE __SEGGER_RTL_stdout_file = { 0 }; // stdout writes to UART +static FILE __SEGGER_RTL_stderr_file = { 0 }; // stderr writes to UART + +FILE *stdin = &__SEGGER_RTL_stdin_file; // NOTE: Provide implementation of stdin for RTL. +FILE *stdout = &__SEGGER_RTL_stdout_file; // NOTE: Provide implementation of stdout for RTL. +FILE *stderr = &__SEGGER_RTL_stderr_file; // NOTE: Provide implementation of stderr for RTL. + +static int _stdin_ungot = EOF; +#endif +/** + * @} + */ + +/* Global functions ----------------------------------------------------------------------------------------*/ +/** @defgroup RETARGET_Exported_Functions Retarget exported functions + * @{ + */ + +void RETARGET_Configuration(void) +{ +#ifdef RETARGET_IS_UART + /* !!! NOTICE !!! + Notice that the local variable (structure) did not have an initial value. + Please confirm that there are no missing members in the parameter settings below in this function. + */ + USART_InitTypeDef USART_InitStructure; + #ifdef RETARGET_UxART_BAUDRATE + USART_InitStructure.USART_BaudRate = RETARGET_UxART_BAUDRATE; + #else + USART_InitStructure.USART_BaudRate = 115200; + #endif + USART_InitStructure.USART_WordLength = USART_WORDLENGTH_8B; + USART_InitStructure.USART_StopBits = USART_STOPBITS_1; + USART_InitStructure.USART_Parity = USART_PARITY_NO; + USART_InitStructure.USART_Mode = USART_MODE_NORMAL; + + #ifdef RETARGET_COM_PORT + HT32F_DVB_COMInit(RETARGET_COM_PORT, &USART_InitStructure); + #else + { /* Enable peripheral clock of UxART */ + CKCU_PeripClockConfig_TypeDef CKCUClock = {{0}}; + CKCUClock.Bit.RETARGET_UxART_IPN = 1; + CKCU_PeripClockConfig(CKCUClock, ENABLE); + } + + USART_Init(RETARGET_USART_PORT, &USART_InitStructure); + USART_TxCmd(RETARGET_USART_PORT, ENABLE); + USART_RxCmd(RETARGET_USART_PORT, ENABLE); + #if (RETARGET_INT_MODE == 1) + NVIC_EnableIRQ(RETARGET_UART_IRQn); + #endif + #endif +#endif + +#if (RETARGET_PORT == RETARGET_ITM) + CKCU_PeripClockConfig_TypeDef CKCUClock = {{ 0 }}; + CKCUClock.Bit.AFIO = 1; + CKCU_PeripClockConfig(CKCUClock, ENABLE); + + CKCU_MCUDBGConfig(CKCU_DBG_TRACE_ON, ENABLE); + AFIO_GPxConfig(TRACESWO_GPIO_ID, TRACESWO_AFIO_PIN, TRACESWO_AFIO_MODE); +#endif + +#ifdef NON_USB_IN_APP + SERIAL_USBDInit(); +#endif +} + +int __backspace(FILE *stream) +{ + if (stream == 0) // Remove the compiler warning + { + } + return 0; +} + +/* + Keil and IAR before 9.20 share fputc() to implement printf +*/ +int fputc (int ch, FILE *f) +{ + #if 0 + if (f == 0) // Remove the compiler warning + { + } + #endif + #if (RETARGET_PORT == RETARGET_ITM) + if (DEMCR & TRCENA) + { + while (ITM_PORT32(0) == 0); + ITM_PORT8(0) = ch; + } + return (ch); + #else + #ifdef AUTO_RETURN + if (ch == '\n') + { + SERIAL_PutChar('\r'); + } + #endif + return (SERIAL_PutChar(ch)); + #endif +} + +#if defined (__ICCARM__) +#if (__VER__ > 9010000) +/* + IAR's version after 9.20 use write to implement printf +*/ +int __write(int Handle, + const unsigned char * Buf, + int Bufsize) +{ + size_t nChars = 0; + if (Handle == -1) + { + return 0; + } + /* Check for stdout and stderr + (only necessary if FILE descriptors are enabled.) */ + if (Handle != 1 && Handle != 2) + { + return -1; + } + for (/*Empty */; Bufsize > 0; --Bufsize) + { + SERIAL_PutChar(*Buf++); + ++nChars; + } + return nChars; +} +#endif +int __read(int Handle, unsigned char *Buf, size_t BufSize) +{ + #if (RETARGET_PORT != RETARGET_ITM) + int nChars = 0; + + if (Handle != 0) + { + return -1; + } + + for (/* Empty */; BufSize > 0; --BufSize) + { + unsigned char c = NULL; + c = SERIAL_GetChar(); + if (c == 0) + break; + *Buf++ = c; + ++nChars; + } + #endif + return nChars; +} + +#elif defined(__SES_ARM) +#if defined(__SEGGER_RTL_VERSION) +/* + SES's version after 6.20 use RTL to implement printf. +*/ +/*********************************************************************************************************//** + * @brief Get character from standard input.. + * @retval Character received. + ************************************************************************************************************/ +static char _stdin_getc(void) { + unsigned char c; + + if (_stdin_ungot != EOF) { + c = _stdin_ungot; + _stdin_ungot = EOF; + } else { + c = SERIAL_GetChar(); + } + return c; +} + +/*********************************************************************************************************//** + * @brief Get file status. + * @param Pointer to file. + * @retval -1: Failure, stream is not a valid file. 0: Success, stream is a valid file. + ***********************************************************************************************************/ +int __SEGGER_RTL_X_file_stat(FILE *stream) { + if (stream == stdin || stream == stdout || stream == stderr) { + return 0; // NOTE: stdin, stdout, and stderr are assumed to be valid. + } else { + return EOF; + } +} + +/*********************************************************************************************************//** + * @brief Get stream buffer size. + * @param stream: Pointer to file. + * @retval Nonzero number of characters to use for buffered I/O; for unbuffered I/O, return 1. + ***********************************************************************************************************/ +int __SEGGER_RTL_X_file_bufsize(FILE *stream) { + (void)stream; + return 1; +} + +/*********************************************************************************************************//** + * @brief Read data from file. + * @param stream: Pointer to file to read from. + * @param s: Pointer to object that receives the input. + * @param len: Number of characters to read from file. + * @retval -1: Failure, stream is not a valid file. >0: Success, stream is a valid file. + ***********************************************************************************************************/ +int __SEGGER_RTL_X_file_read(FILE *stream, char *s, unsigned len) { + int c; + + if (stream == stdin) { + c = 0; + while (len > 0) { + *s = _stdin_getc(); + ++s; + ++c; + --len; + } + } else { + c = EOF; + } + return c; +} + +/*********************************************************************************************************//** + * @brief Write data to file. + * @param stream: Pointer to file to write to. + * @param s:Pointer to object to write to file. + * @param len:Number of characters to write to the file. + * @retval -1: Failure, stream is not a valid file. >0: Success, stream is a valid file. + ***********************************************************************************************************/ +int __SEGGER_RTL_X_file_write(FILE *stream, const char *s, unsigned len) { + if ((stream == stdout) || (stream == stderr)) { + //BSP_UART_WriteBlocking(_UART_Port, (const unsigned char*) s, len); + for (/*Empty */; len > 0; --len) + { + SERIAL_PutChar(*s++); + } + return len; + } else { + return EOF; + } +} + +/*********************************************************************************************************//** + * @brief ush character back to stream. + * @param stream: Pointer to file to push back to. + * @param c: Character to push back. + * @retval -1: Failure, stream is not a valid file. >0: Success, stream is a valid file. + ***********************************************************************************************************/ +int __SEGGER_RTL_X_file_unget(FILE *stream, int c) { + if (stream == stdin) { + if (c != EOF && _stdin_ungot == EOF) { + _stdin_ungot = c; + } else { + c = EOF; + } + } else { + c = EOF; + } + return c; +} +#endif +#else +int fgetc (FILE *f) +{ + #if 0 + if (f == 0) // Remove the compiler warning + { + } + #endif + #if (RETARGET_PORT == RETARGET_ITM) + /* For Keil MDK-ARM only */ + while (ITM_CheckChar() == 0); + return (ITM_ReceiveChar()); + #else + return (SERIAL_GetChar()); + #endif +} +#endif + +void _ttywrch(int ch) +{ + #if (RETARGET_PORT == RETARGET_ITM) + if (DEMCR & TRCENA) + { + while (ITM_PORT32(0) == 0); + ITM_PORT8(0) = ch; + } + #else + SERIAL_PutChar(ch); + #endif +} +#endif + +void _sys_exit(int return_code) +{ + if (return_code == 0) // Remove the compiler warning + { + } + +label: goto label; /* endless loop */ +} +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ diff --git a/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/src/ht32_retarget_desc.c b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/src/ht32_retarget_desc.c new file mode 100644 index 0000000000..2b955b173d --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/src/ht32_retarget_desc.c @@ -0,0 +1,272 @@ +/*********************************************************************************************************//** + * @file ht32_retarget_desc.c + * @version $Rev:: 41 $ + * @date $Date:: 2017-05-23 #$ + * @brief The The USB Descriptor of retarget. + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ +// <<< Use Configuration Wizard in Context Menu >>> + +/* Includes ------------------------------------------------------------------------------------------------*/ + +#define DESC_LEN_CONFN_T (u16)(DESC_LEN_CONFN) + +/*----------------------------------------------------------------------------------------------------------*/ +/* USB Device descriptor setting */ +/*----------------------------------------------------------------------------------------------------------*/ +// USB Device descriptor setting +// USB Specification Release number (bcdUSB) +// <0x0200=> USB 2.0 +// <0x0110=> USB 1.1 +// <0x0100=> USB 1.0 +// USB Class code (assigned by the USB-IF) +// <0x00=> Use class information in the Interface Descriptors (0x00) +// <0x02=> Communications and CDC Control (CDC, 0x02) +// <0xDC=> Diagnostic Device (0xDC) +// <0xEF=> Miscellaneous (0xEF) +// <0xFF=> Vendor Specific (0xFF) +// USB Subclass code (assigned by the USB-IF) <0x0-0xFF:1> +// USB Protocol code (assigned by the USB-IF) <0x0-0xFF:1> +// USB Vendor ID <0x0-0xFFFF:1> +// USB Product ID <0x0-0xFFFF:1> +// USB Device Version <0x0-0xFFFF:1> +// USB String descriptor - Manufacturer +// USB String descriptor - Product +// USB String descriptor - Device serial number +// USB Number of possible configurations <0-255:1> +#define DESC_BCDUSB (0x0110) +#define DESC_BDEVCLASS (0x00) +#define DESC_BDEVSUBCLASS (0x00) +#define DESC_BDEVPROTOCOL (0x00) +#define DESC_IDVENDOR (0x04D9) +#define DESC_IDPRODUCT (0x8008) +#define DESC_BCDDEVICE (0x0100) +#define DESC_IMANUFACTURE (1) +#define DESC_IPRODUCT (1) +#define DESC_ISERIALNUM (1) +#define DESC_INUMCONFN (1) +// + +/*----------------------------------------------------------------------------------------------------------*/ +/* USB Device Descriptor definition. DO NOT MODIFY. */ +/*----------------------------------------------------------------------------------------------------------*/ +#if (DESC_BDEVCLASS == 0x0 & DESC_BDEVSUBCLASS != 0x0) +#error "DESC_BDEVSUBCLASS must be reset to zero when the DESC_BDEVCLASS is equal to zero." +#endif +#define DESC_WMAXPACKETSIZE0 (_EP0LEN) +#define DESC_STR_MAN (1 * DESC_IMANUFACTURE) +#define DESC_STR_PRD (2 * DESC_IPRODUCT) +#define DESC_STR_SER (3 * DESC_ISERIALNUM) +#define DESC_NUM_STRING (1 + 3) + +/*----------------------------------------------------------------------------------------------------------*/ +/* USB Device descriptor */ +/*----------------------------------------------------------------------------------------------------------*/ +__ALIGN4 static uc8 guUSB_DeviceDesc[] = +{ + /*--------------------------------------------------------------------------------------------------------*/ + /* Device descriptor */ + /*--------------------------------------------------------------------------------------------------------*/ + /* Field Size Description */ + /*----------------------------------------------------------------------------*/ + DESC_LEN_DEV, // bLength 1 Size of this descriptor in bytes + DESC_TYPE_01_DEV, // bDescriptorType 1 DEVICE Descriptor Type + DESC_H2B(DESC_BCDUSB), // bcdUSB 2 USB Specification Release Number + DESC_BDEVCLASS, // bDeviceClass 1 Class code (assigned by the USB-IF) + DESC_BDEVSUBCLASS, // bDeviceSubClass 1 Subclass code (assigned by the USB-IF) + DESC_BDEVPROTOCOL, // bDeviceProtocol 1 Protocol code (assigned by the USB-IF) + DESC_WMAXPACKETSIZE0, // wMaxPacketSize0 1 Maximum packet size for endpoint zero + DESC_H2B(DESC_IDVENDOR), // idVendor 2 Vendor ID (assigned by USB-IF) + DESC_H2B(DESC_IDPRODUCT), // idProduct 2 Product ID (assigned by manufacturer) + DESC_H2B(DESC_BCDDEVICE), // bcdDevice 2 Device release number + DESC_STR_MAN, // iManufacturer 1 Index of string descriptor (Manufacturer) + DESC_STR_PRD, // iProduct 1 Index of string descriptor (Product) + DESC_STR_SER, // iSerialNumber 1 Index of string descriptor (Serial Number) + DESC_INUMCONFN, // iNumConfigurations 1 Number of possible configuration +}; + + +/*----------------------------------------------------------------------------------------------------------*/ +/* USB Configuration descriptor setting */ +/*----------------------------------------------------------------------------------------------------------*/ +// USB Configuration descriptor setting +// Self-powered +// Bit 6 of bmAttributes +// Remote Wakeup +// Bit 5 of bmAttributes +// USB Device maximum power (mA) < 2-512:2> +#define DESC_BMATTR_SELF_POWER (0) +#define DESC_BMATTR_REMOTE_WAKEUP (0) +#define DESC_BMAXPOWER (100) +// + +/*----------------------------------------------------------------------------------------------------------*/ +/* USB Configuration Descriptor definition. DO NOT MODIFY. */ +/*----------------------------------------------------------------------------------------------------------*/ +#define DESC_BMATTRIBUTES (0x80 | (DESC_BMATTR_SELF_POWER << 6) | (DESC_BMATTR_REMOTE_WAKEUP << 5)) +#define DESC_TOTAL_LEN DESC_H2B((DESC_LEN_CONFN_T + RETARGET_DLEN)) + +/*----------------------------------------------------------------------------------------------------------*/ +/* USB Configuration Descriptor */ +/*----------------------------------------------------------------------------------------------------------*/ +__ALIGN4 static uc8 guUSB_ConfnDesc[] = +{ + /*--------------------------------------------------------------------------------------------------------*/ + /* Configuration descriptor */ + /*--------------------------------------------------------------------------------------------------------*/ + /* Field Size Description */ + /*----------------------------------------------------------------------------*/ + DESC_LEN_CONFN, // bLength 1 Size of this descriptor in bytes + DESC_TYPE_02_CONFN, // bDescriptorType 1 CONFIGURATION Descriptor Type + DESC_TOTAL_LEN, // wTotalLength 2 Total length of data returned for this configuration + RETARGET_INF, // bNumberInterface 1 Number of interfaces supported by this configuration + 0x01, // bConfigurationValue 1 Value to use as an argument to the SetConfiguration() + 0x00, // iConfiguration 1 Index of string descriptor describing this configuration + DESC_BMATTRIBUTES, // bmAttributes 1 Configuration characteristics + // D6: Self-powered, D5: RemoteWakeup + DESC_POWER(DESC_BMAXPOWER), // bMaxPower 1 Maximum power consumption of the USB device (2 mA units) + + #ifdef RETARGET_IS_USB + #include "ht32_retarget_desc.h" + #endif + +}; + +/*----------------------------------------------------------------------------------------------------------*/ +/* USB String Descriptor */ +/*----------------------------------------------------------------------------------------------------------*/ +__ALIGN4 static uc8 guUSB_StringDescLANGID[] = +{ + /*--------------------------------------------------------------------------------------------------------*/ + /* LANGID (Index = 0) */ + /*--------------------------------------------------------------------------------------------------------*/ + /* Field Size Description */ + /*----------------------------------------------------------------------------*/ + DESC_STRLEN(1), // bLength 1 Size of this descriptor in bytes + DESC_TYPE_03_STR, // bDescriptorType 1 STRING Descriptor Type + DESC_H2B(0x0409), // wLANGID[0] 2 LANGID code zero +}; + +#if (DESC_IMANUFACTURE == 1) +__ALIGN4 static uc8 guUSB_StringDescManufacture[] = +{ + /*--------------------------------------------------------------------------------------------------------*/ + /* Manufacture (Index = 1) */ + /*--------------------------------------------------------------------------------------------------------*/ + /* Field Size Description */ + /*----------------------------------------------------------------------------*/ + DESC_STRLEN(6), // bLength 1 Size of this descriptor in bytes + DESC_TYPE_03_STR, // bDescriptorType 1 STRING Descriptor Type + DESC_CHAR('H'), // bString N UNICODE encoded string + DESC_CHAR('O'), + DESC_CHAR('L'), + DESC_CHAR('T'), + DESC_CHAR('E'), + DESC_CHAR('K'), +}; +#endif + +#if (DESC_IPRODUCT == 1) +__ALIGN4 static uc8 guUSB_StringDescProduct[] = +{ + /*--------------------------------------------------------------------------------------------------------*/ + /* Product (Index = 2) */ + /*--------------------------------------------------------------------------------------------------------*/ + /* Field Size Description */ + /*----------------------------------------------------------------------------*/ + DESC_STRLEN(7), // bLength 1 Size of this descriptor in bytes + DESC_TYPE_03_STR, // bDescriptorType 1 STRING Descriptor Type + DESC_CHAR('U'), // bString N UNICODE encoded string + DESC_CHAR('S'), + DESC_CHAR('B'), + DESC_CHAR('-'), + DESC_CHAR('V'), + DESC_CHAR('C'), + DESC_CHAR('P'), +}; +#endif + + +#if (DESC_ISERIALNUM == 1) +__ALIGN4 static uc8 guUSB_StringDescSerialNum[] = +{ + /*--------------------------------------------------------------------------------------------------------*/ + /* Serial Number (Index = 3) */ + /*--------------------------------------------------------------------------------------------------------*/ + /* Field Size Description */ + /*----------------------------------------------------------------------------*/ + DESC_STRLEN(12), // bLength 1 Size of this descriptor in bytes + DESC_TYPE_03_STR, // bDescriptorType 1 STRING Descriptor Type + DESC_CHAR('S'), // bString N UNICODE encoded string + DESC_CHAR('N'), + DESC_CHAR('0'), + DESC_CHAR('0'), + DESC_CHAR('0'), + DESC_CHAR('0'), + DESC_CHAR('0'), + DESC_CHAR('0'), + DESC_CHAR('1'), + DESC_CHAR('0'), + DESC_CHAR('0'), + DESC_CHAR('0'), +}; +#endif + +uc8 *gpStringDesc[DESC_NUM_STRING] = +{ + + guUSB_StringDescLANGID, + + #if (DESC_IMANUFACTURE == 1) + guUSB_StringDescManufacture, + #else + NULL, + #endif + + #if (DESC_IPRODUCT == 1) + guUSB_StringDescProduct, + #else + NULL, + #endif + + #if (DESC_ISERIALNUM == 1) + guUSB_StringDescSerialNum + #else + NULL, + #endif + +}; + +/*********************************************************************************************************//** + * @brief USB Descriptor pointer initialization. + * @param pDesc: pointer of USBDCore_Desc_TypeDef + * @retval None + ***********************************************************************************************************/ +void USBDDesc_Init(USBDCore_Desc_TypeDef *pDesc) +{ + pDesc->pDeviceDesc = guUSB_DeviceDesc; + pDesc->pConfnDesc = guUSB_ConfnDesc; + pDesc->ppStringDesc = gpStringDesc; + pDesc->uStringDescNumber = DESC_NUM_STRING; + + return; +} diff --git a/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/src/ht32_serial.c b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/src/ht32_serial.c new file mode 100644 index 0000000000..7eded142f3 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/src/ht32_serial.c @@ -0,0 +1,549 @@ +/*********************************************************************************************************//** + * @file ht32_serial.c + * @version $Rev:: 2794 $ + * @date $Date:: 2022-11-25 #$ + * @brief This file provides all the Low level serial routines for HT32. + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ + +/* Includes ------------------------------------------------------------------------------------------------*/ +#include "ht32.h" +#include "ht32_board.h" + +#if (_RETARGET == 1) + +/** @addtogroup HT32_Peripheral_Driver HT32 Peripheral Driver + * @{ + */ + +/** @defgroup SERIAL SERIAL + * @brief Serial related functions + * @{ + */ + + +/* Global functions ----------------------------------------------------------------------------------------*/ +/** @defgroup SERIAL_Exported_Functions Serial exported functions + * @{ + */ + +#ifdef RETARGET_IS_UART + +#if (RETARGET_INT_MODE == 1) +__ALIGN4 static u8 uSerialBuffer[RETARGET_INT_BUFFER_SIZE]; +static vu32 uReadIndex; +static vu32 uWriteIndex; + +#define IS_BUFFER_FULL(LEN) (((uWriteIndex + LEN) >= RETARGET_INT_BUFFER_SIZE) ? ((uWriteIndex + LEN - RETARGET_INT_BUFFER_SIZE) == uReadIndex) : ((uWriteIndex + LEN) == uReadIndex)) +#define IS_BUFFER_EMPTY() (uReadIndex == uWriteIndex) +#define BUFFER_FREE_LEN() ((uWriteIndex >= uReadIndex) ? (RETARGET_INT_BUFFER_SIZE - uWriteIndex + uReadIndex - 1) : (uReadIndex - uWriteIndex - 1)) + +/*********************************************************************************************************//** + * @brief UART IRQ handler. + * @retval None + ************************************************************************************************************/ +void RETARGET_UART_IRQHandler(void) +{ + if (((RETARGET_USART_PORT->SR) & USART_FLAG_TXDE)) + { + if (IS_BUFFER_EMPTY()) + { + RETARGET_USART_PORT->IER &= ~USART_INT_TXDE; + } + else + { + RETARGET_USART_PORT->DR = uSerialBuffer[uReadIndex++]; + if (uReadIndex == RETARGET_INT_BUFFER_SIZE) + { + uReadIndex = 0; + } + } + } + +} +#endif + +/*********************************************************************************************************//** + * @brief Put char to USART. + * @param ch: The char put to USART. + * @retval The char put to USART. + ************************************************************************************************************/ +u32 SERIAL_PutChar(u32 ch) +{ +#if (RETARGET_INT_MODE == 1) + + while (IS_BUFFER_FULL(1)); + + uSerialBuffer[uWriteIndex++] = ch; + if (uWriteIndex == RETARGET_INT_BUFFER_SIZE) + { + uWriteIndex = 0; + } + RETARGET_USART_PORT->IER |= USART_INT_TXDE; + +#else + + USART_SendData(RETARGET_USART_PORT, (u8)ch); + while (USART_GetFlagStatus(RETARGET_USART_PORT, USART_FLAG_TXC) == RESET) + { + } + +#endif + + return ch; +} + +/*********************************************************************************************************//** + * @brief Get char from USART. + * @retval The char got from USART. + ************************************************************************************************************/ +u32 SERIAL_GetChar(void) +{ + #if (LIBCFG_USART_V01) + while (USART_GetFlagStatus(RETARGET_USART_PORT, USART_FLAG_RXDNE) == RESET) + { + } + #else + while (USART_GetFlagStatus(RETARGET_USART_PORT, USART_FLAG_RXDR) == RESET) + { + } + #endif + return USART_ReceiveData(RETARGET_USART_PORT); +} +#endif + + +#ifdef RETARGET_IS_USB +/* Private types -------------------------------------------------------------------------------------------*/ +/** @defgroup SERIAL_Private_TypesDefinitions Serial private types definitions + * @{ + */ +typedef struct _VCP_LINE_CODING +{ + u32 dwDTERate; //Bit rate; + u8 bCharFormat; //Stop bits: + //0 = 1 Stop bit + //1 = 1.5 Stop bit + //2 = 2 Stop bit + u8 bParityType; //parity: + //0 = None + //1 = Odd + //2 = Even + //3 = Mark + //4 = Space + u8 bDataBits; //Number of data bits (7, 8, 9) +} USBDClass_VCP_LINE_CODING; +/** + * @} + */ + +/* Private constants ---------------------------------------------------------------------------------------*/ +/** @defgroup SERIAL_Private_Define Serial private definitions + * @{ + */ +#define CLASS_REQ_20_SET_LINE_CODING (0x20) +#define CLASS_REQ_21_GET_LINE_CODING (0x21) +#define CLASS_REQ_22_SET_CONTROL_LINE_STATE (0x22) + +#ifndef RETARGET_TXBUFFER_SIZE + #define RETARGET_TXBUFFER_SIZE (1) +#endif + +#define RETARGET_USB_MODE_BLOCK (0) +#define RETARGET_USB_MODE_NONBLOCK (1) +/** + * @} + */ + +/* Private macro -------------------------------------------------------------------------------------------*/ +/** @defgroup SERIAL_Private_Macro Serial private macros + * @{ + */ +#define IS_BUFFER_FULL(LEN) (((uWriteIndex + LEN) >= RETARGET_BUFFER_SIZE) ? ((uWriteIndex + LEN - RETARGET_BUFFER_SIZE) == uReadIndex) : ((uWriteIndex + LEN) == uReadIndex)) +#define IS_BUFFER_EMPTY() (uReadIndex == uWriteIndex) +#define BUFFER_FREE_LEN() ((uWriteIndex >= uReadIndex) ? (RETARGET_BUFFER_SIZE - uWriteIndex + uReadIndex - 1) : (uReadIndex - uWriteIndex - 1)) +/** + * @} + */ + +/* Private variables ---------------------------------------------------------------------------------------*/ +/** @defgroup SERIAL_Private_Variable Serial private variables + * @{ + */ +static USBDClass_VCP_LINE_CODING USBDClassVCPLineCoding; +__ALIGN4 static u8 uSerialBuffer[RETARGET_BUFFER_SIZE]; +static vu32 uReadIndex; +static vu32 uWriteIndex; +static vu32 uDTRState = 0; +static vu32 gIsINEmpty = TRUE; + +static u32 TxCount = 0; +__ALIGN4 static u8 TxBuffer[RETARGET_TXBUFFER_SIZE]; +/** + * @} + */ + +#if (RETARGET_RX_EPT == RETARGET_TX_EPT) + #error USB Endpoint of retarget Rx and Tx must different. Please check RETARGET_RX_EPT/RETARGET_TX_EPT "ht32_retarget_usbdconf.h". +#endif + +#if (RETARGET_CTRL_EPT == RETARGET_TX_EPT) + #error USB Endpoint of retarget Control and Tx must different. Please check RETARGET_CTRL_EPT/RETARGET_TX_EPT "ht32_retarget_usbdconf.h". +#endif + +#if (RETARGET_CTRL_EPT == RETARGET_RX_EPT) + #error USB Endpoint of retarget Control and Rx must different. Please check RETARGET_CTRL_EPT/RETARGET_RX_EPT "ht32_retarget_usbdconf.h". +#endif + +#ifdef _RERATGET1_ERR + #error Endpoint 1 already used by other USB class. Retarget can not overwrite it. +#endif + +#ifdef _RERATGET2_ERR + #error Endpoint 2 already used by other USB class. Retarget can not overwrite it. +#endif + +#ifdef _RERATGET3_ERR + #error Endpoint 3 already used by other USB class. Retarget can not overwrite it. +#endif + +#ifdef _RERATGET4_ERR + #error Endpoint 4 already used by other USB class. Retarget can not overwrite it. +#endif + +#ifdef _RERATGET5_ERR + #error Endpoint 5 already used by other USB class. Retarget can not overwrite it. +#endif + +#ifdef _RERATGET6_ERR + #error Endpoint 6 already used by other USB class. Retarget can not overwrite it. +#endif + +#ifdef _RERATGET7_ERR + #error Endpoint 7 already used by other USB class. Retarget can not overwrite it. +#endif + +/*********************************************************************************************************//** + * @brief Put char to USB. + * @param ch: The char put to USB. + * @retval The char put to USB. + ************************************************************************************************************/ +u32 SERIAL_PutChar(u32 ch) +{ + #if (RETARGET_TXBUFFER_SIZE > 63) + #error RETARGET_TXBUFFER_SIZE shall less than 63 (define in ht32fxxxxx_conf.h). + #endif + + #if (RETARGET_USB_MODE == RETARGET_USB_MODE_BLOCK) + while (uDTRState == 0); /* Wait until user open the virtual COM port by PC UI such as Hyper Terminal */ + #elif (RETARGET_USB_MODE == RETARGET_USB_MODE_NONBLOCK) + if (uDTRState == 0) /* Drop data if USB or terminal software is not ready */ + { + return ch; + } + #endif + + TxBuffer[TxCount++] = ch; + + if (TxCount == RETARGET_TXBUFFER_SIZE) + { + TxCount = 0; + + while (gIsINEmpty == FALSE) + { + #if (RETARGET_USB_MODE == RETARGET_USB_MODE_NONBLOCK) + if (uDTRState == 0) + { + return ch; + } + #endif + } + + gIsINEmpty = FALSE; + USBDCore_EPTWriteINData((USBD_EPTn_Enum)RETARGET_TX_EPT, (u32 *)&TxBuffer, RETARGET_TXBUFFER_SIZE); + } + + return ch; +} + +/*********************************************************************************************************//** + * @brief Get char from USB. + * @retval The char got from USB. + ************************************************************************************************************/ +u32 SERIAL_GetChar(void) +{ + u32 value = 0; + + while (IS_BUFFER_EMPTY()); + value = uSerialBuffer[uReadIndex++]; + if (uReadIndex == RETARGET_BUFFER_SIZE) + { + uReadIndex = 0; + } + + return value; +} + +/*********************************************************************************************************//** + * @brief Flush the Tx Buffer + * @retval None + ************************************************************************************************************/ +void SERIAL_Flush(void) +{ + do + { + #if (RETARGET_USB_MODE == RETARGET_USB_MODE_NONBLOCK) + if (uDTRState == 0) + { + return; + } + #endif + } while (USBDCore_EPTGetTransferCount((USBD_EPTn_Enum)RETARGET_TX_EPT, USBD_TCR_0)); + + gIsINEmpty = FALSE; + USBDCore_EPTWriteINData((USBD_EPTn_Enum)RETARGET_TX_EPT, (u32 *)&TxBuffer, TxCount); + TxCount = 0; +} + +#ifdef NON_USB_IN_APP +#include "ht32_retarget_desc.c" +__ALIGN4 USBDCore_TypeDef gUSBCore; +USBD_Driver_TypeDef gUSBDriver; + +/*********************************************************************************************************//** + * @brief This function handles USB interrupt. + * @retval None + ************************************************************************************************************/ +void USB_IRQHandler(void) +{ + USBDCore_IRQHandler(&gUSBCore); +} + +/*********************************************************************************************************//** + * @brief USB Class initialization. + * @param pClass: pointer of USBDCore_Class_TypeDef + * @retval None + ************************************************************************************************************/ +void USBDClass_Init(USBDCore_Class_TypeDef *pClass) +{ + pClass->CallBack_ClassRequest = SERIAL_USBDClass_Request; + pClass->CallBack_EPTn[RETARGET_RX_EPT] = SERIAL_USBDClass_RXHandler; + pClass->CallBack_EPTn[RETARGET_TX_EPT] = SERIAL_USBDClass_TXHandler; + return; +} + +#if (LIBCFG_CKCU_USB_PLL) +/*********************************************************************************************************//** + * @brief Configure USB PLL + * @retval None + ************************************************************************************************************/ +void USBPLL_Configuration(void) +{ + if ((HT_CKCU->GCCR & (1 << 11)) == 0) + { + CKCU_HSICmd(ENABLE); + } + + { /* USB PLL configuration */ + + /* !!! NOTICE !!! + Notice that the local variable (structure) did not have an initial value. + Please confirm that there are no missing members in the parameter settings below in this function. + */ + CKCU_PLLInitTypeDef PLLInit; + + PLLInit.ClockSource = CKCU_PLLSRC_HSI; + #if (LIBCFG_CKCU_USB_PLL_96M) + PLLInit.CFG = CKCU_USBPLL_8M_96M; + #else + PLLInit.CFG = CKCU_USBPLL_8M_48M; + #endif + PLLInit.BYPASSCmd = DISABLE; + CKCU_USBPLLInit(&PLLInit); + } + + CKCU_USBPLLCmd(ENABLE); + + while (CKCU_GetClockReadyStatus(CKCU_FLAG_USBPLLRDY) == RESET); + CKCU_USBClockConfig(CKCU_CKUSBPLL); +} +#endif + +/*********************************************************************************************************//** + * @brief Configure USB for retarget. + * @retval None + ************************************************************************************************************/ +void SERIAL_USBDInit(void) +{ + CKCU_PeripClockConfig_TypeDef CKCUClock = {{0}}; + CKCUClock.Bit.USBD = 1; + CKCU_PeripClockConfig(CKCUClock, ENABLE); + + #if (LIBCFG_CKCU_USB_PLL) + USBPLL_Configuration(); + #else + { + u32 uPLL; + uPLL = CKCU_GetPLLFrequency(); + // uPLL=48000000, CKCU_USBPRE_DIV1 + // uPLL=96000000, CKCU_USBPRE_DIV2 + // uPLL=144000000, CKCU_USBPRE_DIV3 + CKCU_SetUSBPrescaler((CKCU_USBPRE_TypeDef)((uPLL / 48000000) - 1)); + #endif + +#if (LIBCFG_CKCU_HSI_NO_AUTOTRIM) +#else + /* !!! NOTICE !!! + Must turn on if the USB clock source is from HSI (PLL clock Source) + */ + #if (RETARGET_HSI_ATM) + CKCU_HSIAutoTrimClkConfig(CKCU_ATC_USB); + CKCU_HSIAutoTrimCmd(ENABLE); + #endif +#endif + + gUSBCore.pDriver = (u32 *)&gUSBDriver; /* Initiate memory pointer of USB driver */ + USBDDesc_Init(&gUSBCore.Device.Desc); /* Initiate memory pointer of descriptor */ + USBDClass_Init(&gUSBCore.Class); /* Initiate USB Class layer */ + USBDCore_Init(&gUSBCore); /* Initiate USB Core layer */ + NVIC_EnableIRQ(USB_IRQn); /* Enable USB device interrupt */ + USBD_DPpullupCmd(ENABLE); + + #if (RETARGET_USB_MODE == RETARGET_USB_MODE_BLOCK) + USBDCore_MainRoutine(&gUSBCore); /* USB core main routine */ + while (USBDCore_GetStatus() != USB_STATE_CONFIGURED); + #else + gUSBCore.Info.CurrentFeature.Bits.bSelfPowered = TRUE; + USBDCore_MainRoutine(&gUSBCore); /* USB core main routine */ + #endif +} +#endif + +/*********************************************************************************************************//** + * @brief USB Device Class Request for USB retarget + * @param pDev: pointer of USB Device + * @retval None + ************************************************************************************************************/ +void SERIAL_USBDClass_Request(USBDCore_Device_TypeDef *pDev) +{ + u8 USBCmd = *((u8 *)(&(pDev->Request.bRequest))); + u16 len = *((u16 *)(&(pDev->Request.wLength))); + u32 inf = pDev->Request.wIndex; + u32 uIsCmdOK = 0; + + if (inf != 11) + { + return; + } + + if (USBCmd == CLASS_REQ_22_SET_CONTROL_LINE_STATE) + { + if (len == 0) + { + uDTRState = pDev->Request.wValueL & 0x1; + pDev->Transfer.pData = 0; + pDev->Transfer.sByteLength = 0; + pDev->Transfer.Action = USB_ACTION_DATAOUT; + } + } + else + { + if (USBCmd == CLASS_REQ_20_SET_LINE_CODING) + { + pDev->Transfer.Action = USB_ACTION_DATAOUT; + uIsCmdOK = 1; + } + else if (USBCmd == CLASS_REQ_21_GET_LINE_CODING) + { + pDev->Transfer.Action = USB_ACTION_DATAIN; + uIsCmdOK = 1; + } + + if (uIsCmdOK == 1) + { + pDev->Transfer.pData = (uc8*)&USBDClassVCPLineCoding; + pDev->Transfer.sByteLength = (sizeof(USBDClassVCPLineCoding) > pDev->Request.wLength) ? (pDev->Request.wLength) : (sizeof(USBDClassVCPLineCoding)); + } + } + + return; +} + +/*********************************************************************************************************//** + * @brief USB Class Received handler + * @param EPTn: USB Endpoint number + * @arg USBD_EPT0 ~ USBD_EPT7 + * @retval None +************************************************************************************************************/ +void SERIAL_USBDClass_RXHandler(USBD_EPTn_Enum EPTn) +{ + u32 uLen; + u32 uFreeLen = BUFFER_FREE_LEN(); + u8 uTempBuffer[64]; + u32 i; + + /* Read Receive data */ + uLen = USBDCore_EPTReadOUTData(EPTn, (u32*)uTempBuffer, 64); + + if (uLen > uFreeLen) + { + uLen = uFreeLen; + } + + for (i = 0; i < uLen; i++) + { + uSerialBuffer[uWriteIndex++] = uTempBuffer[i]; + if (uWriteIndex == RETARGET_BUFFER_SIZE) + { + uWriteIndex = 0; + } + } + + return; +} + +/*********************************************************************************************************//** + * @brief USB Class Tx handler + * @param EPTn: USB Endpoint number + * @arg USBD_EPT0 ~ USBD_EPT7 + * @retval None +************************************************************************************************************/ +void SERIAL_USBDClass_TXHandler(USBD_EPTn_Enum EPTn) +{ + gIsINEmpty = TRUE; + return; +} + +#endif +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ +#endif diff --git a/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/src/ht32_time.c b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/src/ht32_time.c new file mode 100644 index 0000000000..ff50187484 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/src/ht32_time.c @@ -0,0 +1,185 @@ +/*********************************************************************************************************//** + * @file ht32_time.c + * @version $Rev:: 2888 $ + * @date $Date:: 2023-03-03 #$ + * @brief The time functions. + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ + +/* Includes ------------------------------------------------------------------------------------------------*/ +#include "ht32.h" +#include "ht32_time.h" + +/* + Tick Range: 0 ~ 2^32 / HTCFG_TIME_TICKHZ (maximum tick time) + Interrupt Time: _HTCFG_TIME_OVERFLOW_VALUE / (HTCFG_TIME_TICKHZ * HTCFG_TIME_MULTIPLE) Second (not apply for BFTM) + + Example: 32-bit BFTM with 48 MHz Timer Clock + HTCFG_TIME_TICKHZ = HTCFG_TIME_CLKSRC = 48000000 + Tick Range: 0 ~ 2^32 / 48000000 = 0 ~ 89.478485 Second (maximum tick time, return to 0 every 89.478485 Second) + BFTM do not use interrupt + + Example: 16-bit SCTM with 1 us tick + HTCFG_TIME_TICKHZ = 1000000 (Hz) + HTCFG_TIME_MULTIPLE = 1 (1 Timer Count = 1 Tick) + Tick Range: 0 ~ 2^32 / 1000000 = 0 ~ 4294 Second = 0 ~ 71.58 Minute (maximum tick time, return to 0 every 71.58 Minute) + Interrupt Time: 65536 / (1000000 * 1) = 65.536 ms (Trigger interrupt every 65.536 ms) + + Example: 16-bit SCTM with 10 us tick + HTCFG_TIME_TICKHZ = 100000 (Hz) + HTCFG_TIME_MULTIPLE = 4 (4 Timer Count = 1 Tick) + Tick Range: 0 ~ 2^32 / 100000 = 0 ~ 42949 Second = 0 ~ 715.82 Minute = 11.93 Hour (maximum tick time, return to 0 every 11.93 Hour) + Interrupt Time: 65536 / (100000 * 4) = 163.84 ms (Trigger interrupt every 163.84 ms) + + Example: 16-bit GPTM with 1 ms tick + HTCFG_TIME_TICKHZ = 1000 (Hz) + HTCFG_TIME_MULTIPLE = 4 (4 Timer Count = 1 Tick) + Tick Range: 0 ~ 2^32 / 1000 = 0 ~ 4294967 Second = 0 ~ 49.7 Day (maximum tick time, return to 0 every 49.7 Day) + Interrupt Time: 65536 / (1000 * 4) = 16.384 Second (Trigger interrupt every 16.384 Second) +*/ + +/* Private constants ---------------------------------------------------------------------------------------*/ +#define _HTCFG_TIME_CKCU_PCLK STRCAT2(CKCU_PCLK_, HTCFG_TIME_IPN) + +#if (IS_IPN_TM(HTCFG_TIME_IPN)) +// SCTM/PWM/GPTM/MCTM +#define _HTCFG_TIME_IRQn STRCAT2(HTCFG_TIME_IPN, _IRQn) +#define _HTCFG_TIME_IRQHandler STRCAT2(HTCFG_TIME_IPN, _IRQHandler) +#define _HTCFG_TIME_CLKDIV (HTCFG_TIME_CLKSRC / HTCFG_TIME_TICKHZ / HTCFG_TIME_MULTIPLE) +#define _HTCFG_TIME_OVERFLOW_VALUE (65536) // 16-bit = 2^16 + +#if (_HTCFG_TIME_CLKDIV <= 0) + #error "_HTCFG_TIME_CLKDIV is not correct (must >= 1)!" +#endif + +#if (_HTCFG_TIME_CLKDIV > 65536) + #error "_HTCFG_TIME_CLKDIV is not correct (must <= 65536)!" +#endif + +#if ((_HTCFG_TIME_CLKDIV * HTCFG_TIME_MULTIPLE) != (HTCFG_TIME_CLKSRC / HTCFG_TIME_TICKHZ)) + #error "_HTCFG_TIME_CLKDIV is not correct (must be integer)!" +#endif +#endif + +/* Private variables ---------------------------------------------------------------------------------------*/ +#if (IS_IPN_TM(HTCFG_TIME_IPN)) +u32 gTotalTick = 0x00000000; +u8 gIsTimeInt = FALSE; +#endif + +/* Global functions ----------------------------------------------------------------------------------------*/ +/*********************************************************************************************************//** + * @brief Time Init function. + * @retval None + ***********************************************************************************************************/ +void Time_Init(void) +{ + { /* Enable peripheral clock */ + CKCU_PeripClockConfig_TypeDef CKCUClock = {{ 0 }}; + CKCUClock.Bit.HTCFG_TIME_IPN = 1; + CKCU_PeripClockConfig(CKCUClock, ENABLE); + } + + #if (LIBCFG_CKCU_NO_APB_PRESCALER == 0) + CKCU_SetPeripPrescaler(_HTCFG_TIME_CKCU_PCLK, (CKCU_APBCLKPRE_TypeDef)HTCFG_TIME_PCLK_DIV); + #endif + + #if (IS_IPN_TM(HTCFG_TIME_IPN)) + + { /* Time base configuration */ + /* !!! NOTICE !!! + Notice that the local variable (structure) did not have an initial value. + Please confirm that there are no missing members in the parameter settings below in this function. + */ + TM_TimeBaseInitTypeDef TimeBaseInit; + + TimeBaseInit.Prescaler = _HTCFG_TIME_CLKDIV - 1; + TimeBaseInit.CounterReload = _HTCFG_TIME_OVERFLOW_VALUE -1; + TimeBaseInit.RepetitionCounter = 0; + TimeBaseInit.CounterMode = TM_CNT_MODE_UP; + TimeBaseInit.PSCReloadTime = TM_PSC_RLD_IMMEDIATE; + TM_TimeBaseInit(_HTCFG_TIME_PORT, &TimeBaseInit); + + /* Clear Update Event Interrupt flag since the "TM_TimeBaseInit()" writes the UEV1G bit */ + TM_ClearFlag(_HTCFG_TIME_PORT, TM_FLAG_UEV); + } + + /* Enable Update Event interrupt */ + TM_IntConfig(_HTCFG_TIME_PORT, TM_INT_UEV, ENABLE); + NVIC_EnableIRQ(_HTCFG_TIME_IRQn); + + TM_SetCounter(_HTCFG_TIME_PORT, 0x0000); + TM_Cmd(_HTCFG_TIME_PORT, ENABLE); + + #else + + BFTM_SetCounter(_HTCFG_TIME_PORT, 0x00000000); + BFTM_EnaCmd(_HTCFG_TIME_PORT, ENABLE); + #endif +} + +/*********************************************************************************************************//** + * @brief Time delay function. + * @param uDelayTick: Delay count based on tick. + * @retval None + ***********************************************************************************************************/ +void Time_Delay(u32 uDelayTick) +{ + u32 uCurrent; + u32 uStart = Time_GetTick(); + + do + { + uCurrent = Time_GetTick(); + } while (TIME_TICKDIFF(uStart, uCurrent) < uDelayTick); +} + +#if (IS_IPN_TM(HTCFG_TIME_IPN)) +/*********************************************************************************************************//** + * @brief Gets the current time tick. + * @retval Time Tick + ***********************************************************************************************************/ +u32 Time_GetTick(void) +{ + u32 uCount = GET_CNT(); + + if (gIsTimeInt == TRUE) + { + gIsTimeInt = FALSE; + uCount = GET_CNT(); + gTotalTick += (_HTCFG_TIME_OVERFLOW_VALUE / HTCFG_TIME_MULTIPLE); + } + + return (gTotalTick + (uCount / HTCFG_TIME_MULTIPLE)); +} + +/*********************************************************************************************************//** + * @brief This function handles Timer interrupt. + * @retval None + ************************************************************************************************************/ +void _HTCFG_TIME_IRQHandler(void) +{ + TM_ClearFlag(_HTCFG_TIME_PORT, TM_INT_UEV); + + gIsTimeInt = TRUE; +} +#endif diff --git a/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/src/ht32f1xxxx_adc.c b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/src/ht32f1xxxx_adc.c new file mode 100644 index 0000000000..501d394756 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/src/ht32f1xxxx_adc.c @@ -0,0 +1,724 @@ +/*********************************************************************************************************//** + * @file ht32f1xxxx_adc.c + * @version $Rev:: 2972 $ + * @date $Date:: 2023-10-28 #$ + * @brief This file provides all the ADC firmware functions. + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ + +/* Includes ------------------------------------------------------------------------------------------------*/ +#include "ht32f1xxxx_adc.h" + +/** @addtogroup HT32F1xxxx_Peripheral_Driver HT32F1xxxx Peripheral Driver + * @{ + */ + +/** @defgroup ADC ADC + * @brief ADC driver modules + * @{ + */ + + +/* Private constants ---------------------------------------------------------------------------------------*/ +/** @defgroup ADC_Private_Define ADC private definitions + * @{ + */ +#define ADC_ENABLE_BIT (0x00000080) +#define ADC_SOFTWARE_RESET (0x00000001) +#define LST_SEQ_SET (0x0000001F) +#define TCR_SC_SET (0x00000001) + +#define HLST_SEQ_SET (0x0000001F) +#define HTCR_SC_SET (0x00000001) + +#define OFR_ADOF_MASK (0x00000FFF) +#define OFR_ADAL (1 << 14) +#define OFR_ADOFE (1 << 15) +/** + * @} + */ + +/* Global functions ----------------------------------------------------------------------------------------*/ +/** @addtogroup ADC_Exported_Functions ADC exported functions + * @{ + */ +/*********************************************************************************************************//** + * @brief Deinitialize the HT_ADCn peripheral registers to their default reset values. + * @param HT_ADCn: where HT_ADCn is the selected ADC from the ADC peripherals. + * @retval None + ************************************************************************************************************/ +void ADC_DeInit(HT_ADC_TypeDef* HT_ADCn) +{ + RSTCU_PeripReset_TypeDef RSTCUReset = {{0}}; + + /* Check the parameters */ + Assert_Param(IS_ADC(HT_ADCn)); + + if (HT_ADCn == NULL) // Remove the compiler warning + { + } + + RSTCUReset.Bit.ADC0 = 1; + RSTCU_PeripReset(RSTCUReset, ENABLE); +} + +/*********************************************************************************************************//** + * @brief Reset ADC. + * @param HT_ADCn: is the selected ADC from the ADC peripherals. + * @retval None + ************************************************************************************************************/ +void ADC_Reset(HT_ADC_TypeDef* HT_ADCn) +{ + /* Check the parameters */ + Assert_Param(IS_ADC(HT_ADCn)); + + HT_ADCn->RST |= ADC_SOFTWARE_RESET; +} + +/*********************************************************************************************************//** + * @brief Enable or Disable the specified ADC. + * @param HT_ADCn: where HT_ADCn is the selected ADC from the ADC peripherals. + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void ADC_Cmd(HT_ADC_TypeDef* HT_ADCn, ControlStatus NewState) +{ + #if (LIBCFG_ADC_NOENBIT) + #else + /* Check the parameters */ + Assert_Param(IS_ADC(HT_ADCn)); + Assert_Param(IS_CONTROL_STATUS(NewState)); + + if (NewState != DISABLE) + { + HT_ADCn->CONV |= ADC_ENABLE_BIT; + ADC_Reset(HT_ADCn); + } + else + { + HT_ADCn->CONV &= ~(ADC_ENABLE_BIT); + } + #endif +} + +/*********************************************************************************************************//** + * @brief Configure conversion mode and length of list queue for regular group. + * @param HT_ADCn: where HT_ADCn is the selected ADC from the ADC peripherals. + * @param ADC_MODE: ADC Cyclic Conversion Mode. + * This parameter can be one of the following values: + * @arg ONE_SHOT_MODE : + * @arg CONTINUOUS_MODE : + * @arg DISCONTINUOUS_MODE : + * @param Length: must between 1 ~ 16 + * @param SubLength: must between 1 ~ 16, only valid for DISCONTINUOUS_MODE. + * @retval None + ************************************************************************************************************/ +void ADC_RegularGroupConfig(HT_ADC_TypeDef* HT_ADCn, u8 ADC_MODE, u8 Length, u8 SubLength) +{ + /* Check the parameters */ + Assert_Param(IS_ADC(HT_ADCn)); + Assert_Param(IS_ADC_CONVERSION_MODE(ADC_MODE)); + Assert_Param(IS_ADC_REGULAR_LENGTH(Length)); + if (ADC_MODE == DISCONTINUOUS_MODE) + { + Assert_Param(IS_ADC_REGULAR_SUB_LENGTH(SubLength)); + } + + /* Config cyclic conversion mode and length of list queue and sub length for regular group */ + #if (LIBCFG_ADC_NOENBIT) + HT_ADCn->CONV = ((u32)(SubLength - 1) << 16) | ((u32)(Length - 1) << 8) | ADC_MODE; + #else + HT_ADCn->CONV = ((u32)(SubLength - 1) << 16) | ((u32)(Length - 1) << 8) | ADC_MODE | (HT_ADCn->CONV & ADC_ENABLE_BIT); + #endif +} + +/*********************************************************************************************************//** + * @brief Configure conversion mode and length of list queue for high priority group. + * @param HT_ADCn: where HT_ADCn is the selected ADC from the ADC peripherals. + * @param ADC_MODE: ADC Cyclic Conversion Mode. + * This parameter can be one of the following values: + * @arg ONE_SHOT_MODE : + * @arg CONTINUOUS_MODE : + * @arg DISCONTINUOUS_MODE : + * @param Length: must between 1 ~ 4 + * @param SubLength: must between 1 ~ 4 + * @retval None + ************************************************************************************************************/ +void ADC_HPGroupConfig(HT_ADC_TypeDef* HT_ADCn, u8 ADC_MODE, u8 Length, u8 SubLength) +{ + /* Check the parameters */ + Assert_Param(IS_ADC(HT_ADCn)); + Assert_Param(IS_ADC_CONVERSION_MODE(ADC_MODE)); + Assert_Param(IS_ADC_HP_LENGTH(Length)); + Assert_Param(IS_ADC_HP_SUB_LENGTH(SubLength)); + + /* Config cyclic conversion mode and length of list queue and sub length for regular group */ + HT_ADCn->HCONV = ((u32)(SubLength - 1) << 16) | ((u32)(Length - 1) << 8) | ADC_MODE; +} + +/*********************************************************************************************************//** + * @brief Configure the corresponding rank in the sequencer and the sampling time for the regular channel + * @param HT_ADCn: where HT_ADCn is the selected ADC from the ADC peripherals. + * @param ADC_CH_n: the ADC channel to configure + * This parameter can be one of the following values: + * @arg ADC_CH_n : ADC Channel x selected, x must between 0 ~ 11 + * @arg ADC_CH_GND_VREF : ADC GND VREF selected + * @arg ADC_CH_VDD_VREF : ADC VDD VREF selected + * @param Rank: The rank in the regular group sequencer. + * This parameter must be between 0 to 15. + * @param SampleClock: Number of sampling clocks. + * This parameter must be between 0x00 to 0xFF. + * @retval None + ************************************************************************************************************/ +void ADC_RegularChannelConfig(HT_ADC_TypeDef* HT_ADCn, u8 ADC_CH_n, u8 Rank, u8 SampleClock) +{ + u32 tmpreg1, tmpreg2; + + /* Check the parameters */ + Assert_Param(IS_ADC(HT_ADCn)); + Assert_Param(IS_ADC_CHANNEL(ADC_CH_n)); + Assert_Param(IS_ADC_REGULAR_RANK(Rank)); + Assert_Param(IS_ADC_INPUT_SAMPLING_TIME(SampleClock)); + + /* config sampling clock of correspond ADC input channel */ + HT_ADCn->STR[ADC_CH_n] = SampleClock; + + /* Get the old register value */ + tmpreg1 = HT_ADCn->LST[Rank >> 2]; + /* Calculate the mask to clear */ + tmpreg2 = LST_SEQ_SET << (8 * (Rank & 0x3)); + /* Clear the old SEQx bits for the selected rank */ + tmpreg1 &= ~tmpreg2; + /* Calculate the mask to set */ + tmpreg2 = (u32)ADC_CH_n << (8 * (Rank & 0x3)); + /* Set the SEQx bits for the selected rank */ + tmpreg1 |= tmpreg2; + /* Store the new register value */ + HT_ADCn->LST[Rank >> 2] = tmpreg1; +} + +/*********************************************************************************************************//** + * @brief Configure the corresponding rank in the sequencer and the sample time for the High Priority channel + * @param HT_ADCn: where HT_ADCn is the selected ADC from the ADC peripherals. + * @param ADC_CH_n: the ADC channel to configure + * This parameter can be one of the following values: + * @arg ADC_CH_n : ADC Channel x selected, x must between 0 ~ 11 + * @arg ADC_CH_GND_VREF : ADC GND VREF selected + * @arg ADC_CH_VDD_VREF : ADC VDD VREF selected + * @param Rank: The rank in the high priority group sequencer. + * This parameter must be between 0 to 3. + * @param SampleClock: Number of sampling clocks. + * This parameter must be between 0x00 to 0xFF. + * @retval None + ************************************************************************************************************/ +void ADC_HPChannelConfig(HT_ADC_TypeDef* HT_ADCn, u8 ADC_CH_n, u8 Rank, u8 SampleClock) +{ + u32 tmpreg1, tmpreg2; + + /* Check the parameters */ + Assert_Param(IS_ADC(HT_ADCn)); + Assert_Param(IS_ADC_CHANNEL(ADC_CH_n)); + Assert_Param(IS_ADC_HP_RANK(Rank)); + Assert_Param(IS_ADC_INPUT_SAMPLING_TIME(SampleClock)); + + /* config sampling clock of correspond ADC input channel */ + HT_ADCn->STR[ADC_CH_n] = SampleClock; + + /* Get the old register value */ + tmpreg1 = HT_ADCn->HLST; + /* Calculate the mask to clear */ + tmpreg2 = HLST_SEQ_SET << (8 * (Rank & 0x3)); + /* Clear the old SEQx bits for the selected rank */ + tmpreg1 &= ~tmpreg2; + /* Calculate the mask to set */ + tmpreg2 = (u32)ADC_CH_n << (8 * (Rank & 0x3)); + /* Set the SEQx bits for the selected rank */ + tmpreg1 |= tmpreg2; + /* Store the new register value */ + HT_ADCn->HLST = tmpreg1; +} + +/*********************************************************************************************************//** + * @brief Configure the ADC trigger source for regular channels conversion. + * @param HT_ADCn: where HT_ADCn is the selected ADC from the ADC peripherals. + * @param ADC_TRIG_x: + * This parameter can be one of the following values: + * @arg ADC_TRIG_SOFTWARE : S/W trigger + * @arg ADC_TRIG_EXTI_n : where n can be 0 ~ 15 + * @arg ADC_TRIG_MCTMn_MTO : where n can be 0 + * @arg ADC_TRIG_MCTMn_CH0O : where n can be 0 + * @arg ADC_TRIG_MCTMn_CH1O : where n can be 0 + * @arg ADC_TRIG_MCTMn_CH2O : where n can be 0 + * @arg ADC_TRIG_MCTMn_CH3O : where n can be 0 + * @arg ADC_TRIG_GPTMn_MTO : where n can be 0 ~ 1 + * @arg ADC_TRIG_GPTMn_CH0O : where n can be 0 ~ 1 + * @arg ADC_TRIG_GPTMn_CH1O : where n can be 0 ~ 1 + * @arg ADC_TRIG_GPTMn_CH2O : where n can be 0 ~ 1 + * @arg ADC_TRIG_GPTMn_CH3O : where n can be 0 ~ 1 + * @arg ADC_TRIG_BFTMn : where n can be 0 ~ 1 + * @arg ADC_TRIG_PWMn_MTO : where n can be 0 ~ 1 + * @arg ADC_TRIG_PWMn_CH0O : where n can be 0 ~ 1 + * @arg ADC_TRIG_PWMn_CH1O : where n can be 0 ~ 1 + * @arg ADC_TRIG_PWMn_CH2O : where n can be 0 ~ 1 + * @arg ADC_TRIG_PWMn_CH3O : where n can be 0 ~ 1 + * @arg ADC_TRIG_CMPn : where n can be 0 ~ 1 + * @retval None + ************************************************************************************************************/ +void ADC_RegularTrigConfig(HT_ADC_TypeDef* HT_ADCn, u32 ADC_TRIG_x) +{ + /* Check the parameters */ + Assert_Param(IS_ADC(HT_ADCn)); + Assert_Param(IS_ADC_TRIG(ADC_TRIG_x)); + + /* Config external trigger conversion source of regular group */ + HT_ADCn->TCR = ADC_TRIG_x & 0x0000001F; + HT_ADCn->TSR = ADC_TRIG_x & (~0x0000001F); +} + +/*********************************************************************************************************//** + * @brief Configure the ADC trigger source for high priority channels conversion. + * @param HT_ADCn: where HT_ADCn is the selected ADC from the ADC peripherals. + * @param ADC_TRIG_x: + * This parameter can be one of the following values: + * @arg ADC_TRIG_EXTI_n : where n can be 0 ~ 15 + * @arg ADC_TRIG_MCTMn_MTO : where n can be 0 + * @arg ADC_TRIG_MCTMn_CH0O : where n can be 0 + * @arg ADC_TRIG_MCTMn_CH1O : where n can be 0 + * @arg ADC_TRIG_MCTMn_CH2O : where n can be 0 + * @arg ADC_TRIG_MCTMn_CH3O : where n can be 0 + * @arg ADC_TRIG_GPTMn_MTO : where n can be 0 ~ 1 + * @arg ADC_TRIG_GPTMn_CH0O : where n can be 0 ~ 1 + * @arg ADC_TRIG_GPTMn_CH1O : where n can be 0 ~ 1 + * @arg ADC_TRIG_GPTMn_CH2O : where n can be 0 ~ 1 + * @arg ADC_TRIG_GPTMn_CH3O : where n can be 0 ~ 1 + * @arg ADC_TRIG_BFTMn : where n can be 0 ~ 1 + * @arg ADC_TRIG_PWMn_MTO : where n can be 0 ~ 1 + * @arg ADC_TRIG_PWMn_CH0O : where n can be 0 ~ 1 + * @arg ADC_TRIG_PWMn_CH1O : where n can be 0 ~ 1 + * @arg ADC_TRIG_PWMn_CH2O : where n can be 0 ~ 1 + * @arg ADC_TRIG_PWMn_CH3O : where n can be 0 ~ 1 + * @arg ADC_HPTRIG_CMPn : where n can be 0 ~ 1 + * @retval None + ************************************************************************************************************/ +void ADC_HPTrigConfig(HT_ADC_TypeDef* HT_ADCn, u32 ADC_TRIG_x) +{ + /* Check the parameters */ + Assert_Param(IS_ADC(HT_ADCn)); + Assert_Param(IS_ADC_HPTRIG(ADC_TRIG_x)); + + HT_ADCn->HTCR = ADC_TRIG_x & 0x0000001F; + HT_ADCn->HTSR = ADC_TRIG_x & (~0x0000001F); +} + +/*********************************************************************************************************//** + * @brief Configure the channel data alignment format. + * @param HT_ADCn: where HT_ADCn is the selected ADC from the ADC peripherals. + * @param ADC_CH_n: the ADC channel to configure + * This parameter can be one of the following values: + * @arg ADC_CH_n : ADC Channel x selected + * @arg ADC_CH_OPAn : ADC channel for OPAn + * @arg ADC_CH_GND_VREF : ADC GND VREF selected + * @arg ADC_CH_VDD_VREF : ADC VDD VREF selected + * @param ADC_ALIGN_x: ADC_ALIGN_RIGHT or ADC_ALIGN_LEFT + * @retval None + ************************************************************************************************************/ +void ADC_ChannelDataAlign(HT_ADC_TypeDef* HT_ADCn, u8 ADC_CH_n, ADC_ALIGN_Enum ADC_ALIGN_x) +{ + u32 OFRValue; + + /* Check the parameters */ + Assert_Param(IS_ADC(HT_ADCn)); + Assert_Param(IS_ADC_CHANNEL(ADC_CH_n)); + Assert_Param(IS_ADC_ALIGN(ADC_ALIGN_x)); + + OFRValue = HT_ADCn->OFR[ADC_CH_n] & (~(OFR_ADAL)); + OFRValue |= ADC_ALIGN_x; + + HT_ADCn->OFR[ADC_CH_n] = OFRValue; +} + +/*********************************************************************************************************//** + * @brief Configure the offset value for channel offset cancellation. + * @param HT_ADCn: where HT_ADCn is the selected ADC from the ADC peripherals. + * @param ADC_CH_n: the ADC channel to configure + * This parameter can be one of the following values: + * @arg ADC_CH_n : ADC Channel x selected + * @arg ADC_CH_OPAn : ADC channel for OPAn + * @arg ADC_CH_GND_VREF : ADC GND VREF selected + * @arg ADC_CH_VDD_VREF : ADC VDD VREF selected + * @param OffsetValue: The offset value + * @retval None + ************************************************************************************************************/ +void ADC_ChannelOffsetValue(HT_ADC_TypeDef* HT_ADCn, u8 ADC_CH_n, u16 OffsetValue) +{ + u32 OFRValue; + + /* Check the parameters */ + Assert_Param(IS_ADC(HT_ADCn)); + Assert_Param(IS_ADC_CHANNEL(ADC_CH_n)); + Assert_Param(IS_ADC_OFFSET(OffsetValue)); + + OFRValue = HT_ADCn->OFR[ADC_CH_n] & (~OFR_ADOF_MASK); + OFRValue |= (OffsetValue & 0xFFF); + HT_ADCn->OFR[ADC_CH_n] = OFRValue; +} + +/*********************************************************************************************************//** + * @brief Enable or Disable the channel offset cancellation function. + * @param HT_ADCn: where HT_ADCn is the selected ADC from the ADC peripherals. + * @param ADC_CH_n: the ADC channel to configure + * This parameter can be one of the following values: + * @arg ADC_CH_n : ADC Channel x selected + * @arg ADC_CH_OPAn : ADC channel for OPAn + * @arg ADC_CH_GND_VREF : ADC GND VREF selected + * @arg ADC_CH_VDD_VREF : ADC VDD VREF selected + * @param NewState: ENABLE DISABLE + * @retval None + ************************************************************************************************************/ +void ADC_ChannelOffsetCmd(HT_ADC_TypeDef* HT_ADCn, u8 ADC_CH_n, ControlStatus NewState) +{ + u32 OFRValue; + + /* Check the parameters */ + Assert_Param(IS_ADC(HT_ADCn)); + Assert_Param(IS_ADC_CHANNEL(ADC_CH_n)); + Assert_Param(IS_CONTROL_STATUS(NewState)); + + OFRValue = HT_ADCn->OFR[ADC_CH_n] & (~(OFR_ADOFE)); + + if (NewState == ENABLE) + { + OFRValue |= OFR_ADOFE; + } + + HT_ADCn->OFR[ADC_CH_n] = OFRValue; +} + +/*********************************************************************************************************//** + * @brief Enable or Disable software start of the regular channel conversion of the selected ADC. + * @param HT_ADCn: where HT_ADCn is the selected ADC from the ADC peripherals. + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void ADC_SoftwareStartConvCmd(HT_ADC_TypeDef* HT_ADCn, ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_ADC(HT_ADCn)); + Assert_Param(IS_CONTROL_STATUS(NewState)); + + /* Start Conversion */ + if (NewState != DISABLE) + { + HT_ADCn->TSR |= TCR_SC_SET; + } + else + { + HT_ADCn->TSR &= ~TCR_SC_SET; + } +} + +/*********************************************************************************************************//** + * @brief Enable or Disable software start of the high priority channel conversion of the selected ADC. + * @param HT_ADCn: where HT_ADCn is the selected ADC from the ADC peripherals. + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void ADC_HPSoftwareStartConvCmd(HT_ADC_TypeDef* HT_ADCn, ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_ADC(HT_ADCn)); + Assert_Param(IS_CONTROL_STATUS(NewState)); + + /* Start Conversion */ + if (NewState != DISABLE) + { + HT_ADCn->HTSR |= HTCR_SC_SET; + } + else + { + HT_ADCn->HTSR &= ~HTCR_SC_SET; + } +} + +/*********************************************************************************************************//** + * @brief Return the result of ADC regular channel conversion. + * @param HT_ADCn: where HT_ADCn is the selected ADC from the ADC peripherals. + * @param ADC_REGULAR_DATAn: where n can be 0 ~ 15 + * @retval The Value of data conversion. + ************************************************************************************************************/ +u16 ADC_GetConversionData(HT_ADC_TypeDef* HT_ADCn, u8 ADC_REGULAR_DATAn) +{ + /* Check the parameters */ + Assert_Param(IS_ADC(HT_ADCn)); + Assert_Param(IS_ADC_REGULAR_DATA(ADC_REGULAR_DATAn)); + + return ((u16)HT_ADCn->DR[ADC_REGULAR_DATAn]); +} + +/*********************************************************************************************************//** + * @brief Return the result of ADC high priority channel conversion. + * @param HT_ADCn: where HT_ADCn is the selected ADC from the ADC peripherals. + * @param ADC_HP_DATAn: where x can be 0 ~ 3 + * @retval The Value of data conversion. + ************************************************************************************************************/ +u16 ADC_GetHPConversionData(HT_ADC_TypeDef* HT_ADCn, u8 ADC_HP_DATAn) +{ + /* Check the parameters */ + Assert_Param(IS_ADC(HT_ADCn)); + Assert_Param(IS_ADC_HP_DATA(ADC_HP_DATAn)); + + return ((u16)HT_ADCn->HDR[ADC_HP_DATAn]); +} + +/*********************************************************************************************************//** + * @brief Enable or Disable the specified ADC interrupts. + * @param HT_ADCn: where HT_ADCn is the selected ADC from the ADC peripherals. + * @param ADC_INT_x: Specify the ADC interrupt sources that is to be enabled or disabled. + * This parameter can be any combination of the following values: + * @arg ADC_INT_SINGLE_EOC : + * @arg ADC_INT_SUB_GROUP_EOC : + * @arg ADC_INT_CYCLE_EOC : + * @arg ADC_INT_HP_SINGLE_EOC : + * @arg ADC_INT_HP_SUB_GROUP_EOC : + * @arg ADC_INT_HP_CYCLE_EOC : + * @arg ADC_INT_DATA_OVERWRITE : + * @arg ADC_INT_HP_DATA_OVERWRITE : + * @arg ADC_INT_AWD_LOWER : + * @arg ADC_INT_AWD_UPPER : + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void ADC_IntConfig(HT_ADC_TypeDef* HT_ADCn, u32 ADC_INT_x, ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_ADC(HT_ADCn)); + Assert_Param(IS_ADC_INT(ADC_INT_x)); + Assert_Param(IS_CONTROL_STATUS(NewState)); + + if (NewState != DISABLE) + { + HT_ADCn->IER |= ADC_INT_x; + } + else + { + HT_ADCn->IER &= ~ADC_INT_x; + } +} + +/*********************************************************************************************************//** + * @brief Check whether the specified ADC interrupt has occurred. + * @param HT_ADCn: where HT_ADCn is the selected ADC from the ADC peripherals. + * @param ADC_INT_x: Specify the interrupt status to check. + * This parameter can be any combination of the following values: + * @arg ADC_INT_SINGLE_EOC : + * @arg ADC_INT_SUB_GROUP_EOC : + * @arg ADC_INT_CYCLE_EOC : + * @arg ADC_INT_HP_SINGLE_EOC : + * @arg ADC_INT_HP_SUB_GROUP_EOC : + * @arg ADC_INT_HP_CYCLE_EOC : + * @arg ADC_INT_DATA_OVERWRITE : + * @arg ADC_INT_HP_DATA_OVERWRITE : + * @arg ADC_INT_AWD_LOWER : + * @arg ADC_INT_AWD_UPPER : + * @retval SET or RESET + ************************************************************************************************************/ +FlagStatus ADC_GetIntStatus(HT_ADC_TypeDef* HT_ADCn, u32 ADC_INT_x) +{ + FlagStatus Status; + + /* Check the parameters */ + Assert_Param(IS_ADC(HT_ADCn)); + Assert_Param(IS_ADC_INT(ADC_INT_x)); + + if ((HT_ADCn->ISR & ADC_INT_x) != RESET) + { + Status = SET; + } + else + { + Status = RESET; + } + + return Status; +} + +/*********************************************************************************************************//** + * @brief Clear the ADC interrupt pending bits. + * @param HT_ADCn: where HT_ADCn is the selected ADC from the ADC peripherals. + * @param ADC_INT_x: Specify the interrupt pending bits to be cleared. + * This parameter can be any combination of the following values: + * @arg ADC_INT_SINGLE_EOC : + * @arg ADC_INT_SUB_GROUP_EOC : + * @arg ADC_INT_CYCLE_EOC : + * @arg ADC_INT_HP_SINGLE_EOC : + * @arg ADC_INT_HP_SUB_GROUP_EOC : + * @arg ADC_INT_HP_CYCLE_EOC : + * @arg ADC_INT_DATA_OVERWRITE : + * @arg ADC_INT_HP_DATA_OVERWRITE : + * @arg ADC_INT_AWD_LOWER : + * @arg ADC_INT_AWD_UPPER : + * @retval None + ************************************************************************************************************/ +void ADC_ClearIntPendingBit(HT_ADC_TypeDef* HT_ADCn, u32 ADC_INT_x) +{ + /* Check the parameters */ + Assert_Param(IS_ADC(HT_ADCn)); + Assert_Param(IS_ADC_INT(ADC_INT_x)); + + HT_ADCn->ICLR = ADC_INT_x; +} + +/*********************************************************************************************************//** + * @brief Check whether the specified ADC flag has been set. + * @param HT_ADCn: where HT_ADCn is the selected ADC from the ADC peripherals. + * @param ADC_FLAG_x: Specify the flag to check. + * This parameter can be any combination of the following values: + * @arg ADC_FLAG_SINGLE_EOC : + * @arg ADC_FLAG_SUB_GROUP_EOC : + * @arg ADC_FLAG_CYCLE_EOC : + * @arg ADC_FLAG_HP_SINGLE_EOC : + * @arg ADC_FLAG_HP_SUB_GROUP_EOC : + * @arg ADC_FLAG_HP_CYCLE_EOC : + * @arg ADC_FLAG_DATA_OVERWRITE : + * @arg ADC_FLAG_HP_DATA_OVERWRITE : + * @arg ADC_FLAG_AWD_LOWER : + * @arg ADC_FLAG_AWD_UPPER : + * @retval SET or RESET + ************************************************************************************************************/ +FlagStatus ADC_GetFlagStatus(HT_ADC_TypeDef* HT_ADCn, u32 ADC_FLAG_x) +{ + FlagStatus Status; + + /* Check the parameters */ + Assert_Param(IS_ADC(HT_ADCn)); + Assert_Param(IS_ADC_FLAG(ADC_FLAG_x)); + + if ((HT_ADCn->IRAW & ADC_FLAG_x) != RESET) + { + Status = SET; + } + else + { + Status = RESET; + } + + return Status; +} + +/*********************************************************************************************************//** + * @brief Enable or Disable Lower/Upper threshold warning of the analog watchdog on single/all channels. + * @param HT_ADCn: where HT_ADCn is the selected ADC from the ADC peripherals. + * @param ADC_AWD_x: + * This parameter can be any combination of the following values: + * @arg ADC_AWD_DISABLE : + * @arg ADC_AWD_ALL_LOWER : + * @arg ADC_AWD_ALL_UPPER : + * @arg ADC_AWD_ALL_LOWER_UPPER : + * @arg ADC_AWD_SINGLE_LOWER : + * @arg ADC_AWD_SINGLE_UPPER : + * @arg ADC_AWD_SINGLE_LOWER_UPPER : + * @retval None + ************************************************************************************************************/ +void ADC_AWDConfig(HT_ADC_TypeDef* HT_ADCn, u32 ADC_AWD_x) +{ + /* Check the parameters */ + Assert_Param(IS_ADC(HT_ADCn)); + Assert_Param(IS_ADC_AWD(ADC_AWD_x)); + + HT_ADCn->WCR = (HT_ADCn->WCR & 0xFFFFFFF8) | ADC_AWD_x; +} + +/*********************************************************************************************************//** + * @brief Configure the analog watchdog that guards single channel. + * @param HT_ADCn: where HT_ADCn is the selected ADC from the ADC peripherals. + * @param ADC_CH_n: where n must between 0 ~ 11 + * @retval None + ************************************************************************************************************/ +void ADC_AWDSingleChannelConfig(HT_ADC_TypeDef* HT_ADCn, u8 ADC_CH_n) +{ + /* Check the parameters */ + Assert_Param(IS_ADC(HT_ADCn)); + Assert_Param(IS_ADC_INPUT_CHANNEL(ADC_CH_n)); + + HT_ADCn->WCR = (HT_ADCn->WCR & 0xFFFFF0FF) | ((u32)ADC_CH_n << 8); +} + +/*********************************************************************************************************//** + * @brief Configure the high and low thresholds of the analog watchdog. + * @param HT_ADCn: where HT_ADCn is the selected ADC from the ADC peripherals. + * @param UPPER: must between 0x0000 ~ 0x0FFF + * @param LOWER: must between 0x0000 ~ 0x0FFF + * @retval None + ************************************************************************************************************/ +void ADC_AWDThresholdsConfig(HT_ADC_TypeDef* HT_ADCn, u16 UPPER, u16 LOWER) +{ + /* Check the parameters */ + Assert_Param(IS_ADC(HT_ADCn)); + Assert_Param(IS_ADC_THRESHOLD(UPPER)); + Assert_Param(IS_ADC_THRESHOLD(LOWER)); + + HT_ADCn->LTR = LOWER; + HT_ADCn->UTR = UPPER; +} + +/*********************************************************************************************************//** + * @brief Enable or Disable the specified PDMA request. + * @param HT_ADCn: where HT_ADCn is the selected ADC from the ADC peripherals. + * @param ADC_PDMA_x: Specify the ADC PDMA request that is to be enabled or disabled. + * This parameter can be any combination of the following values: + * @arg ADC_PDMA_REGULAR_SINGLE : + * @arg ADC_PDMA_REGULAR_SUBGROUP : + * @arg ADC_PDMA_REGULAR_CYCLE : + * @arg ADC_PDMA_HP_SINGLE : + * @arg ADC_PDMA_HP_SUBGROUP : + * @arg ADC_PDMA_HP_CYCLE : + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void ADC_PDMAConfig(HT_ADC_TypeDef* HT_ADCn, u32 ADC_PDMA_x, ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_ADC(HT_ADCn)); + Assert_Param(IS_ADC_PDMA(ADC_PDMA_x)); + Assert_Param(IS_CONTROL_STATUS(NewState)); + + if (NewState != DISABLE) + { + HT_ADCn->PDMAR |= ADC_PDMA_x; + } + else + { + HT_ADCn->PDMAR &= ~ADC_PDMA_x; + } +} +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ diff --git a/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/src/ht32f1xxxx_adc_02.c b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/src/ht32f1xxxx_adc_02.c new file mode 100644 index 0000000000..8d22863d7b --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/src/ht32f1xxxx_adc_02.c @@ -0,0 +1,559 @@ +/*********************************************************************************************************//** + * @file ht32f1xxxx_adc_02.c + * @version $Rev:: 2972 $ + * @date $Date:: 2023-10-28 #$ + * @brief This file provides all the ADC firmware functions. + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ + +/* Includes ------------------------------------------------------------------------------------------------*/ +#include "ht32f1xxxx_adc.h" + +/** @addtogroup HT32F1xxxx_Peripheral_Driver HT32F1xxxx Peripheral Driver + * @{ + */ + +/** @defgroup ADC ADC + * @brief ADC driver modules + * @{ + */ + + +/* Private constants ---------------------------------------------------------------------------------------*/ +/** @defgroup ADC_Private_Define ADC private definitions + * @{ + */ +#define ADC_ENABLE_BIT (0x00000080) +#define ADC_SOFTWARE_RESET (0x00000040) +#define LST_SEQ_SET (0x0000001F) +#define TCR_SC_SET (0x00000001) + +#define HLST_SEQ_SET (0x0000001F) +#define HTCR_SC_SET (0x00000001) + +#if (LIBCFG_ADC_IVREF) +#define ADC_VREF_MVDDAEN (0x00000100) +#endif +/** + * @} + */ + +/* Global functions ----------------------------------------------------------------------------------------*/ +/** @addtogroup ADC_Exported_Functions ADC exported functions + * @{ + */ +/*********************************************************************************************************//** + * @brief Deinitialize the HT_ADCn peripheral registers to their default reset values. + * @param HT_ADCn: where HT_ADCn is the selected ADC from the ADC peripherals. + * @retval None + ************************************************************************************************************/ +void ADC_DeInit(HT_ADC_TypeDef* HT_ADCn) +{ + RSTCU_PeripReset_TypeDef RSTCUReset = {{0}}; + + /* Check the parameters */ + Assert_Param(IS_ADC(HT_ADCn)); + + if (HT_ADCn == NULL) // Remove the compiler warning + { + } + + RSTCUReset.Bit.ADC0 = 1; + RSTCU_PeripReset(RSTCUReset, ENABLE); +} + +/*********************************************************************************************************//** + * @brief Reset ADC. + * @param HT_ADCn: is the selected ADC from the ADC peripherals. + * @retval None + ************************************************************************************************************/ +void ADC_Reset(HT_ADC_TypeDef* HT_ADCn) +{ + /* Check the parameters */ + Assert_Param(IS_ADC(HT_ADCn)); + + HT_ADCn->CR |= ADC_SOFTWARE_RESET; +} + +/*********************************************************************************************************//** + * @brief Enable or Disable the specified ADC. + * @param HT_ADCn: where HT_ADCn is the selected ADC from the ADC peripherals. + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void ADC_Cmd(HT_ADC_TypeDef* HT_ADCn, ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_ADC(HT_ADCn)); + Assert_Param(IS_CONTROL_STATUS(NewState)); + + if (NewState != DISABLE) + { + HT_ADCn->CR |= ADC_ENABLE_BIT; + ADC_Reset(HT_ADCn); + } + else + { + HT_ADCn->CR &= ~(ADC_ENABLE_BIT); + } +} + +/*********************************************************************************************************//** + * @brief Configure conversion mode and length of list queue for regular group. + * @param HT_ADCn: where HT_ADCn is the selected ADC from the ADC peripherals. + * @param ADC_MODE: ADC Cyclic Conversion Mode. + * This parameter can be one of the following values: + * @arg ONE_SHOT_MODE : + * @arg CONTINUOUS_MODE : + * @arg DISCONTINUOUS_MODE : + * @param Length: must between 1 ~ 8 + * @param SubLength: must between 1 ~ 8, only valid for DISCONTINUOUS_MODE. + * @retval None + ************************************************************************************************************/ +void ADC_RegularGroupConfig(HT_ADC_TypeDef* HT_ADCn, u8 ADC_MODE, u8 Length, u8 SubLength) +{ + /* Check the parameters */ + Assert_Param(IS_ADC(HT_ADCn)); + Assert_Param(IS_ADC_CONVERSION_MODE(ADC_MODE)); + Assert_Param(IS_ADC_REGULAR_LENGTH(Length)); + if (ADC_MODE == DISCONTINUOUS_MODE) + { + Assert_Param(IS_ADC_REGULAR_SUB_LENGTH(SubLength)); + } + + /* Config cyclic conversion mode and length of list queue and sub length for regular group */ + HT_ADCn->CR = ((u32)(SubLength - 1) << 16) | ((u32)(Length - 1) << 8) | ADC_MODE | (HT_ADCn->CR & ADC_ENABLE_BIT); +} + +/*********************************************************************************************************//** + * @brief Configure the corresponding rank in the sequencer and the sampling time for the regular channel + * @param HT_ADCn: where HT_ADCn is the selected ADC from the ADC peripherals. + * @param ADC_CH_n: the ADC channel to configure + * This parameter can be one of the following values: + * @arg ADC_CH_n : ADC Channel n selected, n must between 0 ~ m (m represent the maximum external ADC input channel). + * @arg ADC_CH_DAC1 : ADC DAC1 selected + * @arg ADC_CH_DAC0 : ADC DAC0 selected + * @arg ADC_CH_IVREF : ADC Internal VREF selected + * @arg ADC_CH_GND_VREF : ADC GND VREF selected + * @arg ADC_CH_VDD_VREF : ADC VDD VREF selected + * @arg ADC_CH_MVDDA : ADC MVDDA selected + * @param Rank: The rank in the regular group sequencer. + * This parameter must be between 0 to 7. + * @param SampleClock: must between 0 ~ 255. + * @retval None + ************************************************************************************************************/ +void ADC_RegularChannelConfig(HT_ADC_TypeDef* HT_ADCn, u8 ADC_CH_n, u8 Rank, u8 SampleClock) +{ + u32 tmpreg1, tmpreg2; + + /* Check the parameters */ + Assert_Param(IS_ADC(HT_ADCn)); + Assert_Param(IS_ADC_CHANNEL(ADC_CH_n)); + Assert_Param(IS_ADC_REGULAR_RANK(Rank)); + Assert_Param(IS_ADC_INPUT_SAMPLING_TIME(SampleClock)); + + /* config sampling clock of ADC input channel */ + HT_ADCn->STR = SampleClock; + /* Get the old register value */ + tmpreg1 = HT_ADCn->LST[Rank >> 2]; + /* Calculate the mask to clear */ + tmpreg2 = LST_SEQ_SET << (8 * (Rank & 0x3)); + /* Clear the old SEQx bits for the selected rank */ + tmpreg1 &= ~tmpreg2; + /* Calculate the mask to set */ + tmpreg2 = (u32)ADC_CH_n << (8 * (Rank & 0x3)); + /* Set the SEQx bits for the selected rank */ + tmpreg1 |= tmpreg2; + /* Store the new register value */ + HT_ADCn->LST[Rank >> 2] = tmpreg1; +} + +/*********************************************************************************************************//** + * @brief Configure the ADC trigger source for regular channels conversion. + * @param HT_ADCn: where HT_ADCn is the selected ADC from the ADC peripherals. + * @param ADC_TRIG_x: + * This parameter can be one of the following values: + * @arg ADC_TRIG_SOFTWARE : S/W trigger + * @arg ADC_TRIG_EXTI_n : where n can be 0 ~ 15 + * @arg ADC_TRIG_MCTMn_MTO : where n can be 0 + * @arg ADC_TRIG_MCTMn_CH0O : where n can be 0 + * @arg ADC_TRIG_MCTMn_CH1O : where n can be 0 + * @arg ADC_TRIG_MCTMn_CH2O : where n can be 0 + * @arg ADC_TRIG_MCTMn_CH3O : where n can be 0 + * @arg ADC_TRIG_GPTMn_MTO : where n can be 0 ~ 1 + * @arg ADC_TRIG_GPTMn_CH0O : where n can be 0 ~ 1 + * @arg ADC_TRIG_GPTMn_CH1O : where n can be 0 ~ 1 + * @arg ADC_TRIG_GPTMn_CH2O : where n can be 0 ~ 1 + * @arg ADC_TRIG_GPTMn_CH3O : where n can be 0 ~ 1 + * @arg ADC_TRIG_BFTMn : where n can be 0 ~ 1 + * @arg ADC_TRIG_PWMn_MTO : where n can be 0 ~ 1 + * @arg ADC_TRIG_PWMn_CH0O : where n can be 0 ~ 1 + * @arg ADC_TRIG_PWMn_CH1O : where n can be 0 ~ 1 + * @arg ADC_TRIG_PWMn_CH2O : where n can be 0 ~ 1 + * @arg ADC_TRIG_PWMn_CH3O : where n can be 0 ~ 1 + * @arg ADC_TRIG_CMPn : where n can be 0 ~ 1 + * @retval None + ************************************************************************************************************/ +void ADC_RegularTrigConfig(HT_ADC_TypeDef* HT_ADCn, u32 ADC_TRIG_x) +{ + /* Check the parameters */ + Assert_Param(IS_ADC(HT_ADCn)); + Assert_Param(IS_ADC_TRIG(ADC_TRIG_x)); + + /* Config external trigger conversion source of regular group */ + HT_ADCn->TCR = ADC_TRIG_x & 0x0000001F; + HT_ADCn->TSR = ADC_TRIG_x & (~0x0000001F); +} + +/*********************************************************************************************************//** + * @brief Configure the sampling time for the ADC input channel. + * @param HT_ADCn: where HT_ADCn is the selected ADC from the ADC peripherals. + * @param SampleClock: must between 0 ~ 255. + * @retval None + ************************************************************************************************************/ +void ADC_SamplingTimeConfig(HT_ADC_TypeDef* HT_ADCn, u8 SampleClock) +{ + /* Check the parameters */ + Assert_Param(IS_ADC(HT_ADCn)); + + /* config sampling clock of ADC input channel */ + HT_ADCn->STR = SampleClock; +} + +/*********************************************************************************************************//** + * @brief Enable or Disable software start of the regular channel conversion of the selected ADC. + * @param HT_ADCn: where HT_ADCn is the selected ADC from the ADC peripherals. + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void ADC_SoftwareStartConvCmd(HT_ADC_TypeDef* HT_ADCn, ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_ADC(HT_ADCn)); + Assert_Param(IS_CONTROL_STATUS(NewState)); + + /* Start Conversion */ + if (NewState != DISABLE) + { + HT_ADCn->TSR |= TCR_SC_SET; + } + else + { + HT_ADCn->TSR &= ~TCR_SC_SET; + } +} + +/*********************************************************************************************************//** + * @brief Return the result of ADC regular channel conversion. + * @param HT_ADCn: where HT_ADCn is the selected ADC from the ADC peripherals. + * @param ADC_REGULAR_DATAn: where n can be 0 ~ 7 + * @retval The Value of data conversion. + ************************************************************************************************************/ +u16 ADC_GetConversionData(HT_ADC_TypeDef* HT_ADCn, u8 ADC_REGULAR_DATAn) +{ + /* Check the parameters */ + Assert_Param(IS_ADC(HT_ADCn)); + Assert_Param(IS_ADC_REGULAR_DATA(ADC_REGULAR_DATAn)); + + return ((u16)HT_ADCn->DR[ADC_REGULAR_DATAn]); +} + +/*********************************************************************************************************//** + * @brief Enable or Disable the specified ADC interrupts. + * @param HT_ADCn: where HT_ADCn is the selected ADC from the ADC peripherals. + * @param ADC_INT_x: Specify the ADC interrupt sources that is to be enabled or disabled. + * This parameter can be any combination of the following values: + * @arg ADC_INT_SINGLE_EOC : + * @arg ADC_INT_SUB_GROUP_EOC : + * @arg ADC_INT_CYCLE_EOC : + * @arg ADC_INT_DATA_OVERWRITE : + * @arg ADC_INT_AWD_LOWER : + * @arg ADC_INT_AWD_UPPER : + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void ADC_IntConfig(HT_ADC_TypeDef* HT_ADCn, u32 ADC_INT_x, ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_ADC(HT_ADCn)); + Assert_Param(IS_ADC_INT(ADC_INT_x)); + Assert_Param(IS_CONTROL_STATUS(NewState)); + + if (NewState != DISABLE) + { + HT_ADCn->IER |= ADC_INT_x; + } + else + { + HT_ADCn->IER &= ~ADC_INT_x; + } +} + +/*********************************************************************************************************//** + * @brief Check whether the specified ADC interrupt has occurred. + * @param HT_ADCn: where HT_ADCn is the selected ADC from the ADC peripherals. + * @param ADC_INT_x: Specify the interrupt status to check. + * This parameter can be any combination of the following values: + * @arg ADC_INT_SINGLE_EOC : + * @arg ADC_INT_SUB_GROUP_EOC : + * @arg ADC_INT_CYCLE_EOC : + * @arg ADC_INT_DATA_OVERWRITE : + * @arg ADC_INT_AWD_LOWER : + * @arg ADC_INT_AWD_UPPER : + * @retval SET or RESET + ************************************************************************************************************/ +FlagStatus ADC_GetIntStatus(HT_ADC_TypeDef* HT_ADCn, u32 ADC_INT_x) +{ + FlagStatus Status; + + /* Check the parameters */ + Assert_Param(IS_ADC(HT_ADCn)); + Assert_Param(IS_ADC_INT(ADC_INT_x)); + + if ((HT_ADCn->ISR & ADC_INT_x) != RESET) + { + Status = SET; + } + else + { + Status = RESET; + } + + return Status; +} + +/*********************************************************************************************************//** + * @brief Clear the ADC interrupt pending bits. + * @param HT_ADCn: where HT_ADCn is the selected ADC from the ADC peripherals. + * @param ADC_INT_x: Specify the interrupt pending bits to be cleared. + * This parameter can be any combination of the following values: + * @arg ADC_INT_SINGLE_EOC : + * @arg ADC_INT_SUB_GROUP_EOC : + * @arg ADC_INT_CYCLE_EOC : + * @arg ADC_INT_DATA_OVERWRITE : + * @arg ADC_INT_AWD_LOWER : + * @arg ADC_INT_AWD_UPPER : + * @retval None + ************************************************************************************************************/ +void ADC_ClearIntPendingBit(HT_ADC_TypeDef* HT_ADCn, u32 ADC_INT_x) +{ + /* Check the parameters */ + Assert_Param(IS_ADC(HT_ADCn)); + Assert_Param(IS_ADC_INT(ADC_INT_x)); + + HT_ADCn->ICLR = ADC_INT_x; +} + +/*********************************************************************************************************//** + * @brief Check whether the specified ADC flag has been set. + * @param HT_ADCn: where HT_ADCn is the selected ADC from the ADC peripherals. + * @param ADC_FLAG_x: Specify the flag to check. + * This parameter can be any combination of the following values: + * @arg ADC_FLAG_SINGLE_EOC : + * @arg ADC_FLAG_SUB_GROUP_EOC : + * @arg ADC_FLAG_CYCLE_EOC : + * @arg ADC_FLAG_DATA_OVERWRITE : + * @arg ADC_FLAG_AWD_LOWER : + * @arg ADC_FLAG_AWD_UPPER : + * @retval SET or RESET + ************************************************************************************************************/ +FlagStatus ADC_GetFlagStatus(HT_ADC_TypeDef* HT_ADCn, u32 ADC_FLAG_x) +{ + FlagStatus Status; + + /* Check the parameters */ + Assert_Param(IS_ADC(HT_ADCn)); + Assert_Param(IS_ADC_FLAG(ADC_FLAG_x)); + + if ((HT_ADCn->IRAW & ADC_FLAG_x) != RESET) + { + Status = SET; + } + else + { + Status = RESET; + } + + return Status; +} + +/*********************************************************************************************************//** + * @brief Enable or Disable Lower/Upper threshold warning of the analog watchdog on single/all channels. + * @param HT_ADCn: where HT_ADCn is the selected ADC from the ADC peripherals. + * @param ADC_AWD_x: + * This parameter can be any combination of the following values: + * @arg ADC_AWD_DISABLE : + * @arg ADC_AWD_ALL_LOWER : + * @arg ADC_AWD_ALL_UPPER : + * @arg ADC_AWD_ALL_LOWER_UPPER : + * @arg ADC_AWD_SINGLE_LOWER : + * @arg ADC_AWD_SINGLE_UPPER : + * @arg ADC_AWD_SINGLE_LOWER_UPPER : + * @retval None + ************************************************************************************************************/ +void ADC_AWDConfig(HT_ADC_TypeDef* HT_ADCn, u32 ADC_AWD_x) +{ + /* Check the parameters */ + Assert_Param(IS_ADC(HT_ADCn)); + Assert_Param(IS_ADC_AWD(ADC_AWD_x)); + + HT_ADCn->WCR = (HT_ADCn->WCR & 0xFFFFFFF8) | ADC_AWD_x; +} + +/*********************************************************************************************************//** + * @brief Configure the analog watchdog that guards single channel. + * @param HT_ADCn: where HT_ADCn is the selected ADC from the ADC peripherals. + * @param ADC_CH_n: where n must between 0 ~ m (m represent the maximum external ADC input channel). + * @retval None + ************************************************************************************************************/ +void ADC_AWDSingleChannelConfig(HT_ADC_TypeDef* HT_ADCn, u8 ADC_CH_n) +{ + /* Check the parameters */ + Assert_Param(IS_ADC(HT_ADCn)); + Assert_Param(IS_ADC_INPUT_CHANNEL(ADC_CH_n)); + + HT_ADCn->WCR = (HT_ADCn->WCR & 0xFFFFF0FF) | ((u32)ADC_CH_n << 8); +} + +/*********************************************************************************************************//** + * @brief Configure the high and low thresholds of the analog watchdog. + * @param HT_ADCn: where HT_ADCn is the selected ADC from the ADC peripherals. + * @param UPPER: must between 0x0000 ~ 0x0FFF + * @param LOWER: must between 0x0000 ~ 0x0FFF + * @retval None + ************************************************************************************************************/ +void ADC_AWDThresholdsConfig(HT_ADC_TypeDef* HT_ADCn, u16 UPPER, u16 LOWER) +{ + /* Check the parameters */ + Assert_Param(IS_ADC(HT_ADCn)); + Assert_Param(IS_ADC_THRESHOLD(UPPER)); + Assert_Param(IS_ADC_THRESHOLD(LOWER)); + + HT_ADCn->WTR = (UPPER << 16) | LOWER; +} + +/*********************************************************************************************************//** + * @brief Enable or Disable the specified PDMA request. + * @param HT_ADCn: where HT_ADCn is the selected ADC from the ADC peripherals. + * @param ADC_PDMA_x: Specify the ADC PDMA request that is to be enabled or disabled. + * This parameter can be any combination of the following values: + * @arg ADC_PDMA_REGULAR_SINGLE : + * @arg ADC_PDMA_REGULAR_SUBGROUP : + * @arg ADC_PDMA_REGULAR_CYCLE : + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void ADC_PDMAConfig(HT_ADC_TypeDef* HT_ADCn, u32 ADC_PDMA_x, ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_ADC(HT_ADCn)); + Assert_Param(IS_ADC_PDMA(ADC_PDMA_x)); + Assert_Param(IS_CONTROL_STATUS(NewState)); + + if (NewState != DISABLE) + { + HT_ADCn->PDMAR |= ADC_PDMA_x; + } + else + { + HT_ADCn->PDMAR &= ~ADC_PDMA_x; + } +} + +#if (LIBCFG_ADC_IVREF) +/*********************************************************************************************************//** + * @brief Enable or Disable the VREF. + * @param HT_ADCn: where HT_ADCn is the selected ADC from the ADC peripherals. + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void ADC_VREFCmd(HT_ADC_TypeDef* HT_ADCn, ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_ADC(HT_ADCn)); + Assert_Param(IS_CONTROL_STATUS(NewState)); + + if (NewState != DISABLE) + { + HT_ADCn->VREFCR |= 0x00000001; + } + else + { + HT_ADCn->VREFCR &= ~(0x00000001); + } +} + +/*********************************************************************************************************//** + * @brief Configure the VREF output voltage. + * @param HT_ADCn: where HT_ADCn is the selected ADC from the ADC peripherals. + * @param ADC_VREF_x: + * This parameter can be one of the following value: + * @arg ADC_VREF_1V215 : + * @arg ADC_VREF_2V0 : + * @arg ADC_VREF_2V5 : + * @arg ADC_VREF_2V7 : + * @retval None + ************************************************************************************************************/ +void ADC_VREFConfig(HT_ADC_TypeDef* HT_ADCn, u32 ADC_VREF_x) +{ + /* Check the parameters */ + Assert_Param(IS_ADC(HT_ADCn)); + Assert_Param(IS_ADC_VREF_SEL(ADC_VREF_x)); + + HT_ADCn->VREFCR = (HT_ADCn->VREFCR & ~(3ul << 4)) | (ADC_VREF_x); +} + +/*********************************************************************************************************//** + * @brief Enable or Disable the power of MVDDA (VDDA/2) + * @param HT_ADCn: where HT_ADCn is the selected ADC from the ADC peripherals. + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void ADC_MVDDACmd(HT_ADC_TypeDef* HT_ADCn, ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_ADC(HT_ADCn)); + Assert_Param(IS_CONTROL_STATUS(NewState)); + + if (NewState != DISABLE) + { + HT_ADCn->VREFCR |= ADC_VREF_MVDDAEN; + } + else + { + HT_ADCn->VREFCR &= ~(ADC_VREF_MVDDAEN); + } +} + +#endif +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ diff --git a/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/src/ht32f1xxxx_aes.c b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/src/ht32f1xxxx_aes.c new file mode 100644 index 0000000000..c6e8ea2a5b --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/src/ht32f1xxxx_aes.c @@ -0,0 +1,550 @@ +/*********************************************************************************************************//** + * @file ht32f1xxxx_aes.c + * @version $Rev:: 2788 $ + * @date $Date:: 2022-11-24 #$ + * @brief This file provides all the AES firmware functions. + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ + +/* Includes ------------------------------------------------------------------------------------------------*/ +#include "ht32f1xxxx_aes.h" + +/** @addtogroup HT32F1xxxx_Peripheral_Driver HT32F1xxxx Peripheral Driver + * @{ + */ + +/** @defgroup AES AES + * @brief AES driver modules + * @{ + */ + + +/* Global variables ----------------------------------------------------------------------------------------*/ +u32 *gpu32OutputBuff; +u32 gu32OutputIndex = 0; + +u32 *gpu32InputBuff; +u32 gu32InputSize = 0; +u32 gu32InputIndex = 0; + +/* Private functions ---------------------------------------------------------------------------------------*/ +static void _AES_Init(HT_AES_TypeDef* HT_AESn, AES_InitTypeDef* AES_InitStruct); + +/* Global functions ----------------------------------------------------------------------------------------*/ +/** @defgroup AES_Exported_Functions AES exported functions + * @{ + */ +/*********************************************************************************************************//** + * @brief Deinitialize the AES peripheral registers to their default reset values. + * @param HT_AESn: where HT_AESn is the selected AES from the AES peripherals. + * @retval None + ************************************************************************************************************/ +void AES_DeInit(HT_AES_TypeDef* HT_AESn) +{ + RSTCU_PeripReset_TypeDef RSTCUReset = {{0}}; + + if (HT_AESn == NULL) // Remove the compiler warning + { + } + + RSTCUReset.Bit.AES = 1; + RSTCU_PeripReset(RSTCUReset, ENABLE); +} + +/*********************************************************************************************************//** + * @brief Flush the FIFO. + * @param HT_AESn: where HT_AESn is the selected AES from the AES peripherals. + * @retval None + ************************************************************************************************************/ +void AES_FIFOFlush(HT_AES_TypeDef* HT_AESn) +{ + AES_Cmd(HT_AESn, DISABLE); + HT_AESn->CR |= AES_FLUSH_ENABLE; + AES_Cmd(HT_AESn, ENABLE); +} + +/*********************************************************************************************************//** + * @brief Enable or Disable the specified AES. + * @param HT_AESn: where HT_AESn is the selected AES from the AES peripherals. + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void AES_Cmd(HT_AES_TypeDef* HT_AESn, ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_AES(HT_AESn)); + Assert_Param(IS_CONTROL_STATUS(NewState)); + + if (NewState != DISABLE) + { + HT_AESn->CR |= AES_ENABLE; + } + else + { + HT_AESn->CR &= ~AES_ENABLE; + } +} + +/*********************************************************************************************************//** + * @brief Start the AES key. + * @param HT_AESn: where HT_AESn is the selected AES from the AES peripherals. + * @retval None + ************************************************************************************************************/ +void AES_StartKey(HT_AES_TypeDef* HT_AESn) +{ + HT_AESn->CR |= (1 << 4); +} + +/*********************************************************************************************************//** + * @brief Initialize the AES peripheral according to the specified parameters in the AES_InitStruct. + * @param HT_AESn: where AES is the selected AES peripheral. + * @param AES_InitStruct: pointer to a AES_InitTypeDef structure. + * @retval None + ************************************************************************************************************/ +void _AES_Init(HT_AES_TypeDef* HT_AESn, AES_InitTypeDef* AES_InitStruct) +{ + /* Check the parameters */ + Assert_Param(IS_AES(HT_AESn)); + Assert_Param(IS_AES_KEY_SIZE(AES_InitStruct->AES_KeySize)); + Assert_Param(IS_AES_DIR(AES_InitStruct->AES_Dir)); + Assert_Param(IS_AES_MODE(AES_InitStruct->AES_Mode)); + Assert_Param(IS_AES_SWAP(AES_InitStruct->AES_Swap)); + + HT_AESn->CR = (HT_AESn->CR & 0xFFFFFE81) | AES_InitStruct->AES_KeySize | + AES_InitStruct->AES_Dir | AES_InitStruct->AES_Mode | + AES_InitStruct->AES_Swap; + + AES_Cmd(HT_AESn, ENABLE); +} + +/*********************************************************************************************************//** + * @brief Initialize the AES peripheral on ECB mode according to the specified parameters in the AES_InitStruct. + * @param HT_AESn: where AES is the selected AES peripheral. + * @param AES_InitStruct: pointer to a AES_InitTypeDef structure. + * @retval None + ************************************************************************************************************/ +void AES_ECB_Init(HT_AES_TypeDef* HT_AESn, AES_InitTypeDef* AES_InitStruct) +{ + AES_InitStruct->AES_Mode = AES_MODE_ECB; + _AES_Init(HT_AESn, AES_InitStruct); + + AES_IntConfig(HT_AESn, AES_IER_OFINTEN, ENABLE); + NVIC_EnableIRQ(AES_IRQn); +} + +/*********************************************************************************************************//** + * @brief Initialize the AES peripheral on CBC mode according to the specified parameters in the AES_InitStruct. + * @param HT_AESn: where AES is the selected AES peripheral. + * @param AES_InitStruct: pointer to a AES_InitTypeDef structure. + * @retval None + ************************************************************************************************************/ +void AES_CBC_Init(HT_AES_TypeDef* HT_AESn, AES_InitTypeDef* AES_InitStruct) +{ + AES_InitStruct->AES_Mode = AES_MODE_CBC; + _AES_Init(HT_AESn, AES_InitStruct); + + AES_IntConfig(HT_AESn, AES_IER_OFINTEN, ENABLE); + NVIC_EnableIRQ(AES_IRQn); +} + +/*********************************************************************************************************//** + * @brief Initialize the AES peripheral on CTR mode according to the specified parameters in the AES_InitStruct. + * @param HT_AESn: where HT_AESn is the selected AES peripheral. + * @param AES_InitStruct: pointer to a AES_InitTypeDef structure. + * @retval None + ************************************************************************************************************/ +void AES_CTR_Init(HT_AES_TypeDef* HT_AESn, AES_InitTypeDef* AES_InitStruct) +{ + AES_InitStruct->AES_Mode = AES_MODE_CTR; + _AES_Init(HT_AESn, AES_InitStruct); + + AES_IntConfig(HT_AESn, AES_IER_OFINTEN, ENABLE); + NVIC_EnableIRQ(AES_IRQn); +} + +/*********************************************************************************************************//** + * @brief Check whether the specified AES status has been set. + * @param HT_AESn: where HT_AESn is the selected AES peripheral. + * @param AES_SR_x: specify the flag to be check. + * This parameter can be one of the following values: + * @arg AES_SR_IFEMPTY : AES Input FIFO is Empty + * @arg AES_SR_IFNFULL : AES Input FIFO is not Full + * @arg AES_SR_OFNEMPTY : AES Output FIFO is not Empty + * @arg AES_SR_OFFULL : AES Output FIFO is Full + * @arg AES_SR_BUSY : AES is busy when AES is in encrypt/decrypt action and key expansion + * @retval SET or RESET + ************************************************************************************************************/ +FlagStatus AES_GetStatus(HT_AES_TypeDef* HT_AESn, u32 AES_SR_x) +{ + Assert_Param(IS_AES(HT_AESn)); + Assert_Param(IS_AES_STATUS(AES_SR_x)); + + if ((HT_AESn->SR & AES_SR_x) != (u32)RESET) + { + return (SET); + } + else + { + return (RESET); + } +} + +/*********************************************************************************************************//** + * @brief Enable or Disable the AES PDMA interface. + * @param HT_AESn: where HT_AESn is the selected HT_AESn peripheral. + * @param AES_PDMA_xFDMAEN: specify the AES FIFO DMA to be enabled or disabled. + * This parameter can be any combination of the following values: + * @arg AES_PDMA_IFDMAEN : input FIFO PDMA + * @arg AES_PDMA_OFDMAEN : Output FIFO PDMA + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void AES_PDMACmd(HT_AES_TypeDef* HT_AESn, u32 AES_PDMA_xFDMAEN, ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_AES(HT_AESn)); + Assert_Param(IS_CONTROL_STATUS(NewState)); + + if (NewState != DISABLE) + { + HT_AESn->PDMAR |= AES_PDMA_xFDMAEN; + } + else + { + HT_AESn->PDMAR &= ~AES_PDMA_xFDMAEN; + } +} + +/*********************************************************************************************************//** + * @brief Check whether the specified AES interrupt has occurred. + * @param HT_AESn: where HT_AESn is the selected AES from the AES peripherals. + * @param AES_INTSR_x: Specify the interrupt status to check. + * This parameter can be any combination of the following values: + * @arg AES_INTSR_IFINT : + * @arg AES_INTSR_OFINT : + * @return SET or RESET + ************************************************************************************************************/ +FlagStatus AES_GetIntStatus(HT_AES_TypeDef* HT_AESn, u32 AES_INTSR_x) +{ + FlagStatus Status; + u32 aes_isr = HT_AESn->ISR; + u32 aes_ier = HT_AESn->IER; + + /* Check the parameters */ + Assert_Param(IS_AES(HT_AESn)); + Assert_Param(IS_AES_INTSR(AES_INTSR_x)); + + Status = (FlagStatus)(aes_isr & aes_ier); + if ((Status & AES_INTSR_x) != RESET) + { + Status = SET; + } + else + { + Status = RESET; + } + + return Status; +} + +/*********************************************************************************************************//** + * @brief Enable or Disable the specified AES interrupts. + * @param HT_AESn: where HT_AESn is the selected AES from the AES peripherals. + * @param AES_IER_x: Specify the AES interrupt sources that is to be enabled or disabled. + * This parameter can be any combination of the following values: + * @arg AES_IER_IFINTEN : + * @arg AES_IER_OFINTEN : + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void AES_IntConfig(HT_AES_TypeDef* HT_AESn, u32 AES_IER_x, ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_AES(HT_AESn)); + Assert_Param(IS_AES_IER(AES_IER_x)); + Assert_Param(IS_CONTROL_STATUS(NewState)); + + if (NewState != DISABLE) + { + HT_AESn->IER |= AES_IER_x; + } + else + { + HT_AESn->IER &= ~AES_IER_x; + } +} + +/*********************************************************************************************************//** + * @brief Set the specified AES Input data. + * @param HT_AESn: where HT_AESn is the selected AES from the AES peripherals + * @param AES_Data: Data input + * @retval None + ************************************************************************************************************/ +void AES_SetInputData(HT_AES_TypeDef* HT_AESn, uc32 AES_Data) +{ + Assert_Param(IS_AES(HT_AESn)); + #if (LIBCFG_AES_SWAP) + HT_AESn->DINR = __REV(AES_Data); + #else + HT_AESn->DINR = AES_Data; + #endif +} + +/*********************************************************************************************************//** + * @brief Get the specified AES output data. + * @param HT_AESn: where HT_AESn is the selected AES from the AES peripherals + * @retval Output Data + ************************************************************************************************************/ +u32 AES_GetOutputData(HT_AES_TypeDef* HT_AESn) +{ + Assert_Param(IS_AES(HT_AESn)); + #if (LIBCFG_AES_SWAP) + return __REV(HT_AESn->DOUTR); + #else + return HT_AESn->DOUTR; + #endif +} + +/*********************************************************************************************************//** + * @brief Set the specified AES key table. + * @param HT_AESn: where HT_AESn is the selected AES from the AES peripherals. + * @param Key: Key table + * @param keySize: Key table's size + * @retval None + ************************************************************************************************************/ +void AES_SetKeyTable(HT_AES_TypeDef* HT_AESn, uc8* Key, u32 keySize) +{ + u32 i; + u32 uCRTemp = HT_AESn->CR & (~(0x00000060UL)); + if (keySize == 128/8) + { + uCRTemp |= AES_KEYSIZE_128B; + } + else if (keySize == 192/8) + { + uCRTemp |= AES_KEYSIZE_192B; + } + else if (keySize == 256/8) + { + uCRTemp |= AES_KEYSIZE_256B; + } + else + { + return; + } + HT_AESn->CR = uCRTemp; + + for (i = 0; i < keySize; i += 4) + { + #if (LIBCFG_AES_SWAP) + HT_AESn->KEYR[i >> 2] = __REV(*(u32*)&Key[i]); + #else + HT_AESn->KEYR[i >> 2] = *(u32*)&Key[i]; + #endif + } + + AES_StartKey(HT_AES); +} + +/*********************************************************************************************************//** + * @brief Set the specified AES Vector table. + * @param HT_AESn: where HT_AESn is the selected AES from the AES peripherals. + * @param Vector: + * @retval None + ************************************************************************************************************/ +void AES_SetVectorTable(HT_AES_TypeDef* HT_AESn, uc8* Vector) +{ + int i; + Assert_Param(IS_AES(HT_AESn)); + + for (i = 0; i < 16; i += 4) + { + #if (LIBCFG_AES_SWAP) + HT_AESn->IVR[i >> 2] = __REV(*(u32*)&Vector[i]); + #else + HT_AESn->IVR[i >> 2] = *(u32*)&Vector[i]; + #endif + } +} + +/*********************************************************************************************************//** + * @brief AES Crypt Data + * @param HT_AESn: where HT_AESn is the selected AES from the AES peripherals + * @param dir: Crypt Data's direction + * @param iv: initial vector table + * @param length: data size + * @param inputData: InputData + * @param outputData: Output Data + * @retval SUCCESS or ERROR + ************************************************************************************************************/ +ErrStatus _AES_CryptData(HT_AES_TypeDef* HT_AESn, + AES_DIR_Enum dir, + uc8 *iv, + u32 length, + uc8 *inputData, + u8 *outputData) +{ + /*AES Data blocks 16 byte */ + if ((length % 16) != 0) + { + /* Data size can not be divisible by 16. */ + return ERROR; + } + + /*Set inital Vector */ + if (iv != NULL) + { + AES_SetVectorTable(HT_AESn, iv); + } + + /*FIFO Flush */ + AES_FIFOFlush(HT_AES); + + /*Set direction */ + HT_AESn->CR = (HT_AESn->CR & 0xFFFFFFFD) | dir; + + /*Create input/output data */ + gpu32InputBuff = (u32*)inputData; + gpu32OutputBuff = (u32*)outputData; + + /*Init Index */ + gu32OutputIndex = 0; + gu32InputSize = length/4; + + /*Set input data */ + AES_IntConfig(HT_AES, AES_IER_IFINTEN, ENABLE); + + /*Waitting for conversion */ + while (AES_GetStatus(HT_AES, AES_SR_OFNEMPTY)); + return SUCCESS; +} + +#if 0 +/*********************************************************************************************************//** + * @brief AES Crypt Data on ECB mode + * @param HT_AESn: where HT_AESn is the selected AES from the AES peripherals + * @param dir: Crypt Data's direction + * @param length: data size + * @param inputData: InputData + * @param outputData: Output Data + * @retval SUCCESS or ERROR + ************************************************************************************************************/ +ErrStatus AES_ECB_CryptData(HT_AES_TypeDef* HT_AESn, + AES_DIR_Enum dir, + u32 length, + uc8 *inputData, + u8 *outputData) +{ + return _AES_CryptData(HT_AESn, + dir, + NULL, + length, + inputData, + outputData); +} + +/*********************************************************************************************************//** + * @brief AES Crypt Data on CBC mode + * @param HT_AESn: where HT_AESn is the selected AES from the AES peripherals + * @param dir: Crypt Data's direction + * @param iv: initial vector table + * @param length: data size + * @param inputData: InputData + * @param outputData: Output Data + * @retval SUCCESS or ERROR + ************************************************************************************************************/ +ErrStatus AES_CBC_CryptData(HT_AES_TypeDef* HT_AESn, + AES_DIR_Enum dir, + uc8 *iv, + u32 length, + uc8 *inputData, + u8 *outputData) +{ + return _AES_CryptData(HT_AESn, + dir, + iv, + length, + inputData, + outputData); +} + +/*********************************************************************************************************//** + * @brief AES Crypt Data on CTR mode + * @param HT_AESn: where HT_AESn is the selected AES from the AES peripherals + * @param iv: initial vector table + * @param length: data size + * @param inputData: InputData + * @param outputData: Output Data + * @retval SUCCESS or ERROR + ************************************************************************************************************/ +ErrStatus AES_CTR_CryptData(HT_AES_TypeDef* HT_AESn, + uc8 *iv, + u32 length, + uc8 *inputData, + u8 *outputData) +{ + return _AES_CryptData(HT_AESn, + AES_DIR_ENCRYPT, + iv, + length, + inputData, + outputData); +} +#endif + +/*********************************************************************************************************//** + * @brief This function handles AES Core interrupt. + * @param HT_AESn: where HT_AESn is the selected AES from the AES peripherals. + * @retval None + ************************************************************************************************************/ +void AESCore_IRQHandler(HT_AES_TypeDef* HT_AESn) +{ + if (AES_GetIntStatus(HT_AES, AES_INTSR_OFINT)) + { + gpu32OutputBuff[gu32OutputIndex++] = AES_GetOutputData(HT_AES); + } + if (AES_GetIntStatus(HT_AES, AES_INTSR_IFINT)) + { + if (gu32InputIndex < gu32InputSize) + { + AES_SetInputData(HT_AES, gpu32InputBuff[gu32InputIndex]); + gu32InputIndex++; + } + else + { + AES_IntConfig(HT_AES, AES_IER_IFINTEN, DISABLE); + gu32InputIndex = 0; + } + } +} +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ diff --git a/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/src/ht32f1xxxx_bftm.c b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/src/ht32f1xxxx_bftm.c new file mode 100644 index 0000000000..c38bebac7e --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/src/ht32f1xxxx_bftm.c @@ -0,0 +1,240 @@ +/*********************************************************************************************************//** + * @file ht32f1xxxx_bftm.c + * @version $Rev:: 2789 $ + * @date $Date:: 2022-11-24 #$ + * @brief This file provides all the BFTM firmware functions. + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ + +/* Includes ------------------------------------------------------------------------------------------------*/ +#include "ht32f1xxxx_bftm.h" + +/** @addtogroup HT32F1xxxx_Peripheral_Driver HT32F1xxxx Peripheral Driver + * @{ + */ + +/** @defgroup BFTM BFTM + * @brief BFTM driver modules + * @{ + */ + + +/* Global functions ----------------------------------------------------------------------------------------*/ +/** @defgroup BFTM_Exported_Functions BFTM exported functions + * @{ + */ +/*********************************************************************************************************//** + * @brief Deinitialize the specified BFTM registers to their default values. + * @param HT_BFTMn: where the HT_BFTMn is the selected BFTM from the BFTM peripherals. + * @retval None + ************************************************************************************************************/ +void BFTM_DeInit(HT_BFTM_TypeDef* HT_BFTMn) +{ + RSTCU_PeripReset_TypeDef RSTCUReset = {{0}}; + + /* Check the parameters */ + Assert_Param(IS_BFTM(HT_BFTMn)); + + if (HT_BFTMn == HT_BFTM0) + { + RSTCUReset.Bit.BFTM0 = 1; + } + else if (HT_BFTMn == HT_BFTM1) + { + RSTCUReset.Bit.BFTM1 = 1; + } + RSTCU_PeripReset(RSTCUReset, ENABLE); +} + +/*********************************************************************************************************//** + * @brief Enable or Disable the specified BFTM. + * @param HT_BFTMn: where the HT_BFTMn is the selected BFTM from the BFTM peripherals. + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void BFTM_EnaCmd(HT_BFTM_TypeDef* HT_BFTMn, ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_BFTM(HT_BFTMn)); + Assert_Param(IS_CONTROL_STATUS(NewState)); + + if (NewState != DISABLE) + { + HT_BFTMn->CR |= (1UL << 2); + } + else + { + HT_BFTMn->CR &= ~(1UL << 2); + } +} + +/*********************************************************************************************************//** + * @brief Configure the CMP register value of the specified BFTM. + * @param HT_BFTMn: where the HT_BFTMn is the selected BFTM from the BFTM peripherals. + * @param uCompare: Specify a value to the CMP register. + * @retval None + ************************************************************************************************************/ +void BFTM_SetCompare(HT_BFTM_TypeDef* HT_BFTMn, BFTM_DataTypeDef uCompare) +{ + /* Check the parameters */ + Assert_Param(IS_BFTM(HT_BFTMn)); + + HT_BFTMn->CMP = uCompare; +} + +/*********************************************************************************************************//** + * @brief Get the CMP register value of the specified BFTM. + * @param HT_BFTMn: where the HT_BFTMn is the selected BFTM from the BFTM peripherals. + * @retval The value of the CMP register + ************************************************************************************************************/ +u32 BFTM_GetCompare(HT_BFTM_TypeDef* HT_BFTMn) +{ + /* Check the parameters */ + Assert_Param(IS_BFTM(HT_BFTMn)); + + return HT_BFTMn->CMP; +} + +/*********************************************************************************************************//** + * @brief Set the CNTR register value of the specified BFTM. + * @param HT_BFTMn: where the HT_BFTMn is the selected BFTM from the BFTM peripherals. + * @param uCounter: Specify a new value to the CNTR register. + * @retval None + ************************************************************************************************************/ +void BFTM_SetCounter(HT_BFTM_TypeDef* HT_BFTMn, BFTM_DataTypeDef uCounter) +{ + /* Check the parameters */ + Assert_Param(IS_BFTM(HT_BFTMn)); + + HT_BFTMn->CNTR = uCounter; +} + +/*********************************************************************************************************//** + * @brief Get the CNTR register value of the specified BFTM. + * @param HT_BFTMn: where the HT_BFTMn is the selected BFTM from the BFTM peripherals. + * @retval The value of the CNTR register + ************************************************************************************************************/ +u32 BFTM_GetCounter(HT_BFTM_TypeDef* HT_BFTMn) +{ + /* Check the parameters */ + Assert_Param(IS_BFTM(HT_BFTMn)); + + return HT_BFTMn->CNTR; +} + +/*********************************************************************************************************//** + * @brief Enable or Disable the one shot mode of the specified BFTM. + * @param HT_BFTMn: where the HT_BFTMn is the selected BFTM from the BFTM peripherals. + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void BFTM_OneShotModeCmd(HT_BFTM_TypeDef* HT_BFTMn, ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_BFTM(HT_BFTMn)); + Assert_Param(IS_CONTROL_STATUS(NewState)); + + if (NewState != DISABLE) + { + HT_BFTMn->CR |= (1UL << 1); + } + else + { + HT_BFTMn->CR &= ~(1UL << 1); + } +} + +/*********************************************************************************************************//** + * @brief Enable or Disable the specified BFTM interrupt. + * @param HT_BFTMn: where the HT_BFTMn is the selected BFTM from the BFTM peripherals. + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void BFTM_IntConfig(HT_BFTM_TypeDef* HT_BFTMn, ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_BFTM(HT_BFTMn)); + Assert_Param(IS_CONTROL_STATUS(NewState)); + + if (NewState != DISABLE) + { + HT_BFTMn->CR |= BFTM_INT_MATCH; + } + else + { + HT_BFTMn->CR &= ~BFTM_INT_MATCH; + } +} + +/*********************************************************************************************************//** + * @brief Get the flag status of the specified BFTM. + * @param HT_BFTMn: where the HT_BFTMn is the selected BFTM from the BFTM peripherals. + * @retval SET or RESET + ************************************************************************************************************/ +FlagStatus BFTM_GetFlagStatus(HT_BFTM_TypeDef* HT_BFTMn) +{ + /* Check the parameters */ + Assert_Param(IS_BFTM(HT_BFTMn)); + + if (HT_BFTMn->SR & BFTM_FLAG_MATCH) + { + return SET; + } + else + { + return RESET; + } +} + +/*********************************************************************************************************//** + * @brief Clear the interrupt flag of the specified BFTM. + * @param HT_BFTMn: where the HT_BFTMn is the selected BFTM from the BFTM peripherals. + * @retval None + ************************************************************************************************************/ +void BFTM_ClearFlag(HT_BFTM_TypeDef* HT_BFTMn) +{ + /* Check the parameters */ + Assert_Param(IS_BFTM(HT_BFTMn)); + + HT_BFTMn->SR &= ~BFTM_FLAG_MATCH; + + /*--------------------------------------------------------------------------------------------------------*/ + /* DSB instruction is added in this function to ensure the write operation which is for clearing interrupt*/ + /* flag is actually completed before exiting ISR. It prevents the NVIC from detecting the interrupt again */ + /* since the write register operation may be pended in the internal write buffer of Cortex-Mx when program*/ + /* has exited interrupt routine. This DSB instruction may be masked if this function is called in the */ + /* beginning of ISR and there are still some instructions before exiting ISR. */ + /*--------------------------------------------------------------------------------------------------------*/ + __DSB(); +} +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ diff --git a/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/src/ht32f1xxxx_ckcu.c b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/src/ht32f1xxxx_ckcu.c new file mode 100644 index 0000000000..81e7f8f143 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/src/ht32f1xxxx_ckcu.c @@ -0,0 +1,1076 @@ +/*********************************************************************************************************//** + * @file ht32f1xxxx_ckcu.c + * @version $Rev:: 2972 $ + * @date $Date:: 2023-10-28 #$ + * @brief This file provides all the Clock Control Unit firmware functions. + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ + +/* Includes ------------------------------------------------------------------------------------------------*/ +#include "ht32f1xxxx_ckcu.h" + +/** @addtogroup HT32F1xxxx_Peripheral_Driver HT32F1xxxx Peripheral Driver + * @{ + */ + +/** @defgroup CKCU CKCU + * @brief CKCU driver modules + * @{ + */ + + +/* Private constants ---------------------------------------------------------------------------------------*/ +/** @defgroup CKCU_Private_Define CKCU private definitions + * @{ + */ + +/* GCFGR bit field definition */ +#define CKCU_POS_CKOUTSRC 0 +#define CKCU_MASK_CKOUTSRC ((u32)0x7 << CKCU_POS_CKOUTSRC) + +#if (LIBCFG_CKCU_USB_PLL) +#define CKCU_POS_USBSRC 10 +#define CKCU_MASK_USBSRC ((u32)0x1 << CKCU_POS_USBSRC) +#endif + +#define CKCU_POS_CKREFPRE 11 +#define CKCU_MASK_CKREFPRE ((u32)0x1F << CKCU_POS_CKREFPRE) + +#if (LIBCFG_CKCU_USART_PRESCALER) +#define CKCU_POS_URPRE 20 +#define CKCU_MASK_URPRE ((u32)0x3 << CKCU_POS_URPRE) +#endif + +#if (!LIBCFG_NO_CKCU_USBPRE) +#define CKCU_POS_USBPRE 22 +#define CKCU_MASK_USBPRE ((u32)0x3 << CKCU_POS_USBPRE) +#endif + +/* GCCR bit field definition */ +#define CKCU_POS_SW 0 +#if (LIBCFG_CKCU_NO_HCLK_LOW_SPEED) +#define CKCU_MASK_SW ((u32)0x3 << CKCU_POS_SW) +#else +#define CKCU_MASK_SW ((u32)0x7 << CKCU_POS_SW) +#endif + +/* PLLCFGR bit field definition */ +#define CKCU_POS_POTD 21 +#define CKCU_MASK_POTD ((u32)0x3 << CKCU_POS_POTD) + +#define CKCU_POS_PFBD 23 +#if (LIBCDG_CKCU_PLL_144M) +#define CKCU_MASK_PFBD ((u32)0x3F << CKCU_POS_PFBD) +#else +#define CKCU_MASK_PFBD ((u32)0x1F << CKCU_POS_PFBD) +#endif + +/* APBCFGR bit field definition */ +#define CKCU_POS_ADCDIV 16 +#define CKCU_MASK_ADCDIV ((u32)0x7 << CKCU_POS_ADCDIV) + +/* CKST bit field definition */ +#define CKCU_POS_PLLST 8 +#define CKCU_MASK_PLLST ((u32)0xF << CKCU_POS_PLLST) + +#define CKCU_POS_HSEST 16 +#define CKCU_MASK_HSEST ((u32)0x3 << CKCU_POS_HSEST) + +#define CKCU_POS_HSIST 24 +#define CKCU_MASK_HSIST ((u32)0x7 << CKCU_POS_HSIST) + +#if (LIBCFG_CKCU_CKSWST_LEGACY) +#define CKCU_POS_CKSWST 30 +#define CKCU_MASK_CKSWST ((u32)0x3 << CKCU_POS_CKSWST) +#else +#define CKCU_POS_CKSWST 0 +#define CKCU_MASK_CKSWST ((u32)0x7 << CKCU_POS_CKSWST) +#endif + +/* GCFGR Bit Band Alias */ +#define CKCU_BB_PLLSRC BitBand((u32)&HT_CKCU->GCFGR, 8) +#if (LIBCFG_CKCU_USB_PLL) +#define CKCU_BB_USBPLLSRC BitBand((u32)&HT_CKCU->GCFGR, 9) +#endif + +/* GCCR Bit Band Alias */ +#if (LIBCFG_CKCU_USB_PLL) +#define CKCU_BB_USBPLLEN BitBand((u32)&HT_CKCU->GCCR, 3) +#endif +#define CKCU_BB_PLLEN BitBand((u32)&HT_CKCU->GCCR, 9) +#define CKCU_BB_HSEEN BitBand((u32)&HT_CKCU->GCCR, 10) +#define CKCU_BB_HSIEN BitBand((u32)&HT_CKCU->GCCR, 11) +#define CKCU_BB_CKMEN BitBand((u32)&HT_CKCU->GCCR, 16) +#define CKCU_BB_PSRCEN BitBand((u32)&HT_CKCU->GCCR, 17) + +/* GCIR Bit Band Alias */ +#define CKCU_BB_CKSF BitBand((u32)&HT_CKCU->GCIR, 0) +#define CKCU_BB_CKSIE BitBand((u32)&HT_CKCU->GCIR, 16) + +/* PLLCR Bit Band Alias */ +#define CKCU_BB_PLLBYPASS BitBand((u32)&HT_CKCU->PLLCR, 31) + +#if (!LIBCFG_NO_BACK_DOMAIN) +/* LPCR Bit Band Alias */ +#define CKCU_BB_BKISO BitBand((u32)&HT_CKCU->LPCR, 0) +#endif + +#if (!LIBCFG_CKCU_HSI_NO_AUTOTRIM) +/* HSICR Bit Band Alias */ +#define CKCU_BB_TRIMEN BitBand((u32)&HT_CKCU->HSICR, 0) +#define CKCU_BB_ATCEN BitBand((u32)&HT_CKCU->HSICR, 1) +#define CKCU_BB_REFCLKSEL0 BitBand((u32)&HT_CKCU->HSICR, 5) +#define CKCU_BB_REFCLKSEL1 BitBand((u32)&HT_CKCU->HSICR, 6) +#endif + +/** + * @} + */ + +/* Private macro -------------------------------------------------------------------------------------------*/ +/** @defgroup CKCU_Private_Macro CKCU private macros + * @{ + */ +#define CKCU_BF_WRITE(Reg, Mask, Pos, WriteValue) (Reg = ((Reg & ~((u32)Mask)) | ((u32)WriteValue << Pos))) +#define CKCU_BF_READ(Reg, Mask, Pos) ((Reg & (u32)Mask) >> Pos) +/** + * @} + */ + +/* Global functions ----------------------------------------------------------------------------------------*/ +/** @addtogroup CKCU_Exported_Functions CKCU exported functions + * @{ + */ +/*********************************************************************************************************//** + * @brief Deinitialize the CKCU registers to the reset values. + * @retval None + ************************************************************************************************************/ +void CKCU_DeInit(void) +{ + /* Reset system clock */ + CKCU_HSICmd(ENABLE); + while (CKCU_GetClockReadyStatus(CKCU_FLAG_HSIRDY) == RESET); + CKCU_SysClockConfig(CKCU_SW_HSI); + +#if (LIBCFG_CKCU_USB_PLL) + HT_CKCU->GCFGR = 0x00000302; /* Reset value of GCFGR */ +#else + HT_CKCU->GCFGR = 0x00000102; /* Reset value of GCFGR */ +#endif + HT_CKCU->GCCR = 0x00000803; /* Reset value of GCCR */ +#if (LIBCFG_CKCU_USB_PLL) + HT_CKCU->GCIR = 0x0000007F; /* Clear all interrupt flags */ +#else + HT_CKCU->GCIR = 0x0000007D; /* Clear all interrupt flags */ +#endif + + HT_CKCU->PLLCR = 0; /* Reset value of PLLCR */ + HT_CKCU->AHBCFGR = 0; /* Reset value of AHBCFGR */ + HT_CKCU->AHBCCR = 0x000000E5; /* Reset value of AHBCCR */ + HT_CKCU->APBCFGR = 0x00010000; /* Reset value of APBCFGR */ + HT_CKCU->APBCCR0 = 0; /* Reset value of APBCCR0 */ + HT_CKCU->APBCCR1 = 0; /* Reset value of APBCCR1 */ +#if (LIBCFG_CKCU_NO_APB_PRESCALER) +#else + HT_CKCU->APBPCSR0 = 0; /* Reset value of APBPCSR0 */ + HT_CKCU->APBPCSR1 = 0; /* Reset value of APBPCSR1 */ +#endif +#if (LIBCFG_CKCU_APBPCSR2) + HT_CKCU->APBPCSR2 = 0; /* Reset value of APBPCSR2 */ +#endif +#if (LIBCFG_CKCU_HSI_NO_AUTOTRIM) +#else + HT_CKCU->HSICR = 0; /* Reset value of HSICR */ + HT_CKCU->HSIATCR = 0; /* Reset value of HSIATCR */ +#endif + HT_CKCU->LPCR = 0; /* Reset value of LPCR */ + HT_CKCU->MCUDBGCR = 0; /* Reset value of MCUDBGCR */ +} + +/*********************************************************************************************************//** + * @brief Enable or Disable the external high speed oscillator (HSE). + * @note HSE can not be stopped if it is used by system clock or PLL. + * @param Cmd: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void CKCU_HSECmd(ControlStatus Cmd) +{ + /* Check the parameters */ + Assert_Param(IS_CONTROL_STATUS(Cmd)); + + CKCU_BB_HSEEN = Cmd; +} + +/*********************************************************************************************************//** + * @brief Enable or Disable the internal high speed oscillator (HSI). + * @note HSI can not be stopped if it is used by system clock or PLL. + * @param Cmd: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void CKCU_HSICmd(ControlStatus Cmd) +{ + /* Check the parameters */ + Assert_Param(IS_CONTROL_STATUS(Cmd)); + + CKCU_BB_HSIEN = Cmd; +} + +/*********************************************************************************************************//** + * @brief Enable or Disable the PLL clock. + * @note PLL can not be stopped if it is used by system clock or CK_REF. + * @param Cmd: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void CKCU_PLLCmd(ControlStatus Cmd) +{ + /* Check the parameters */ + Assert_Param(IS_CONTROL_STATUS(Cmd)); + + CKCU_BB_PLLEN = Cmd; +} + +#if (LIBCFG_CKCU_USB_PLL) +/*********************************************************************************************************//** + * @brief Enable or Disable the USBPLL clock. + * @param Cmd: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void CKCU_USBPLLCmd(ControlStatus Cmd) +{ + /* Check the parameters */ + Assert_Param(IS_CONTROL_STATUS(Cmd)); + + CKCU_BB_USBPLLEN = Cmd; +} +#endif + +/*********************************************************************************************************//** + * @brief Wait for HSE is ready to be used. + * @retval SUCCESS or ERROR + ************************************************************************************************************/ +ErrStatus CKCU_WaitHSEReady(void) +{ + u32 ReadyCnt = 0; + + /* Wait until HSE is ready or time-out occurred */ + while (CKCU_GetClockReadyStatus(CKCU_FLAG_HSERDY) != SET) + { + if (++ReadyCnt >= HSE_READY_TIME) + { + return ERROR; + } + } + + return SUCCESS; +} + +/*********************************************************************************************************//** + * @brief Check whether the specific clock ready flag is set or not. + * @param CKCU_FLAG: specify the clock ready flag. + * This parameter can be one of the following values: + * @arg CKCU_FLAG_USBPLLRDY : USB PLL ready flag + * @arg CKCU_FLAG_PLLRDY : PLL ready flag + * @arg CKCU_FLAG_HSERDY : HSE ready flag + * @arg CKCU_FLAG_HSIRDY : HSI ready flag + * @arg CKCU_FLAG_LSERDY : LSE ready flag + * @arg CKCU_FLAG_LSIRDY : LSI ready flag + * @retval SET or RESET + ************************************************************************************************************/ +FlagStatus CKCU_GetClockReadyStatus(u32 CKCU_FLAG) +{ + /* Check the parameters */ + Assert_Param(IS_CKCU_FLAG(CKCU_FLAG)); + + if (HT_CKCU->GCSR & CKCU_FLAG) + { + return SET; + } + else + { + return RESET; + } +} + +/*********************************************************************************************************//** + * @brief This function is used to configure PLL. + * @param PLL_InitStruct: pointer to CKCU_PLLInitTypeDef structure. + * @retval None + ************************************************************************************************************/ +void CKCU_PLLInit(CKCU_PLLInitTypeDef *PLL_InitStruct) +{ + /* Check the parameters */ + Assert_Param(IS_PLL_CLKSRC(PLL_InitStruct->ClockSource)); + Assert_Param(IS_CONTROL_STATUS(PLL_InitStruct->BYPASSCmd)); + Assert_Param(IS_PLL_CFG(PLL_InitStruct->CFG)); + + CKCU_BB_PLLSRC = PLL_InitStruct->ClockSource; + CKCU_BB_PLLBYPASS = PLL_InitStruct->BYPASSCmd; + HT_CKCU->PLLCFGR = (HT_CKCU->PLLCFGR & 0x0000FFFF) | PLL_InitStruct->CFG; +} + +#if (LIBCFG_CKCU_USB_PLL) +/*********************************************************************************************************//** + * @brief This function is used to configure USBPLL. + * @param USBPLL_InitStruct: pointer to CKCU_PLLInitTypeDef structure. + * @retval None + ************************************************************************************************************/ +void CKCU_USBPLLInit(CKCU_PLLInitTypeDef *USBPLL_InitStruct) +{ + /* Check the parameters */ + Assert_Param(IS_PLL_CLKSRC(USBPLL_InitStruct->ClockSource)); + Assert_Param(IS_USBPLL_CFG(USBPLL_InitStruct->CFG)); + + CKCU_BB_USBPLLSRC = USBPLL_InitStruct->ClockSource; + HT_CKCU->PLLCFGR = (HT_CKCU->PLLCFGR & 0xFFFF0000) | USBPLL_InitStruct->CFG; +} + +/*********************************************************************************************************//** + * @brief Configure the CK_USB clock source. + * @param USBSRC: specify the USB clock source. + * This parameter can be one of the following values: + * @arg CKCU_CKPLL : CK_USB = CK_PLL + * @arg CKCU_CKUSBPLL : CK_USB = CK_USBPLL + * @retval None + ************************************************************************************************************/ +void CKCU_USBClockConfig(CKCU_USBSRC_TypeDef USBSRC) +{ + CKCU_BF_WRITE(HT_CKCU->GCFGR, CKCU_MASK_USBSRC, CKCU_POS_USBSRC, USBSRC); +} +#endif + +/*********************************************************************************************************//** + * @brief Configure the CK_SYS source. + * @param CLKSRC: specify the system clock source. + * This parameter can be one of the following values: + * @arg CKCU_SW_PLL : PLL is selected as CK_SYS + * @arg CKCU_SW_HSE : HSE is selected as CK_SYS + * @arg CKCU_SW_HSI : HSI is selected as CK_SYS + * @arg CKCU_SW_LSE : LSE is selected as CK_SYS + * @arg CKCU_SW_LSI : LSI is selected as CK_SYS + * @retval None + ************************************************************************************************************/ +ErrStatus CKCU_SysClockConfig(CKCU_SW_TypeDef CLKSRC) +{ + u32 cnt = 0xFF; + + CKCU_BF_WRITE(HT_CKCU->GCCR, CKCU_MASK_SW, CKCU_POS_SW, CLKSRC); + + /* Wait until new system clock source is applied or time-out */ + while (--cnt) + { + if (CKCU_GetSysClockSource() == (u32)CLKSRC) + { + return SUCCESS; + } + } + + return ERROR; +} + +/*********************************************************************************************************//** + * @brief Return the source clock which is used as system clock. + * @retval The source clock used as system clock. + * 0x01: PLL is selected as system clock + * 0x02: HSE is selected as system clock + * 0x03: HSI is selected as system clock + * 0x06: LSE is selected as system clock + * 0x07: LSI is selected as system clock + ************************************************************************************************************/ +u32 CKCU_GetSysClockSource(void) +{ + return ((u32)CKCU_BF_READ(HT_CKCU->CKST, CKCU_MASK_CKSWST, CKCU_POS_CKSWST)); +} + +/*********************************************************************************************************//** + * @brief Configure the CK_AHB prescaler. + * @param HCLKPRE: specify the value of divider. + * This parameter can be one of the following values: + * @arg CKCU_SYSCLK_DIV1 : HCLK = CK_SYS + * @arg CKCU_SYSCLK_DIV2 : HCLK = CK_SYS / 2 + * @arg CKCU_SYSCLK_DIV4 : HCLK = CK_SYS / 4 + * @arg CKCU_SYSCLK_DIV8 : HCLK = CK_SYS / 8 + * @arg CKCU_SYSCLK_DIV16 : HCLK = CK_SYS / 16 + * @arg CKCU_SYSCLK_DIV32 : HCLK = CK_SYS / 32 + * @retval None + ************************************************************************************************************/ +void CKCU_SetHCLKPrescaler(CKCU_SYSCLKDIV_TypeDef HCLKPRE) +{ + HT_CKCU->AHBCFGR = HCLKPRE; +} + +/*********************************************************************************************************//** + * @brief Configure the CK_REF prescaler. + * @param CKREFPRE: specify the value of divider. + * This parameter can be: CKCU_CKREFPRE_DIV2 to CKCU_CKREFPRE_DIV64 (CK_REF = CK_PLL / (2 * (N + 1)), N = 0 ~ 31) + * @retval None + ************************************************************************************************************/ +void CKCU_SetCKREFPrescaler(CKCU_CKREFPRE_TypeDef CKREFPRE) +{ + CKCU_BF_WRITE(HT_CKCU->GCFGR, CKCU_MASK_CKREFPRE, CKCU_POS_CKREFPRE, CKREFPRE); +} + +#if (LIBCFG_CKCU_USART_PRESCALER) +/********************************************************************************************************//** + * @brief Configure the CK_USART prescaler. + * @param URPRE: specify the prescaler value. + * This parameter can be: + * @arg CKCU_URPRE_DIV1: USART clock divided by 1 + * @arg CKCU_URPRE_DIV2: USART clock divided by 2 + * @retval None + ************************************************************************************************************/ +void CKCU_SetUSARTPrescaler(CKCU_URPRE_TypeDef URPRE) +{ + CKCU_BF_WRITE(HT_CKCU->GCFGR, CKCU_MASK_URPRE, CKCU_POS_URPRE, URPRE); +} +#endif + +#if (!LIBCFG_NO_CKCU_USBPRE) +/*********************************************************************************************************//** + * @brief Configure the CK_USB prescaler. + * @param USBPRE: specify the value of divider. + * This parameter can be one of the following values: + * @arg CKCU_USBPRE_DIV1 : CK_USB = CK_PLL / 1 + * @arg CKCU_USBPRE_DIV2 : CK_USB = CK_PLL / 2 + * @arg CKCU_USBPRE_DIV3 : CK_USB = CK_PLL / 3 (For HT32F165x only) + * @retval None + ************************************************************************************************************/ +void CKCU_SetUSBPrescaler(CKCU_USBPRE_TypeDef USBPRE) +{ + CKCU_BF_WRITE(HT_CKCU->GCFGR, CKCU_MASK_USBPRE, CKCU_POS_USBPRE, USBPRE); +} +#endif + +/*********************************************************************************************************//** + * @brief Configure the CK_ADC prescaler. + * @param CKCU_ADCPRE_ADCn: specify the ADCn. + * @param CKCU_ADCPRE_DIVn: specify the prescaler value. + * This parameter can be one of the following values: + * @arg CKCU_ADCPRE_DIV1 : CK_ADC = HCLK / 1 (HT32F12364 Only) + * @arg CKCU_ADCPRE_DIV2 : CK_ADC = HCLK / 2 + * @arg CKCU_ADCPRE_DIV4 : CK_ADC = HCLK / 4 + * @arg CKCU_ADCPRE_DIV5 : CK_ADC = HCLK / 5 (HT32F12364 Only) + * @arg CKCU_ADCPRE_DIV6 : CK_ADC = HCLK / 6 + * @arg CKCU_ADCPRE_DIV8 : CK_ADC = HCLK / 8 + * @arg CKCU_ADCPRE_DIV16 : CK_ADC = HCLK / 16 + * @arg CKCU_ADCPRE_DIV32 : CK_ADC = HCLK / 32 + * @arg CKCU_ADCPRE_DIV64 : CK_ADC = HCLK / 64 + * @retval None + ************************************************************************************************************/ +void CKCU_SetADCnPrescaler(CKCU_ADCPRE_ADCn_TypeDef CKCU_ADCPRE_ADCn, CKCU_ADCPRE_TypeDef CKCU_ADCPRE_DIVn) +{ + HT_CKCU->APBCFGR = (HT_CKCU->APBCFGR & (~(0x07 << CKCU_ADCPRE_ADCn))) | (CKCU_ADCPRE_DIVn << CKCU_ADCPRE_ADCn); +} + +/*********************************************************************************************************//** + * @brief Return the frequency of the different clocks. + * @param CKCU_Clk: pointer to CKCU_ClocksTypeDef structure to get the clocks frequency. + * @retval None + ************************************************************************************************************/ +void CKCU_GetClocksFrequency(CKCU_ClocksTypeDef* CKCU_Clk) +{ + u32 div; + #if (LIBCFG_CKCU_CKSWST_LEGACY) + u32 SystemCoreClockSrc = (HT_CKCU->CKST >> 30) & 3UL; + #else + u32 SystemCoreClockSrc = (HT_CKCU->CKST >> 0) & 7UL; + #endif + + CKCU_Clk->PLL_Freq = CKCU_GetPLLFrequency(); + + /* Get system frequency */ + switch (SystemCoreClockSrc) + { + case CKCU_SW_PLL: + CKCU_Clk->SYSCK_Freq = CKCU_Clk->PLL_Freq; + break; + case CKCU_SW_HSE: + CKCU_Clk->SYSCK_Freq = HSE_VALUE; + break; + case CKCU_SW_HSI: + CKCU_Clk->SYSCK_Freq = HSI_VALUE; + break; + #if (LIBCFG_CKCU_NO_HCLK_LOW_SPEED) + #else + case CKCU_SW_LSE: + CKCU_Clk->SYSCK_Freq = LSE_VALUE; + break; + case CKCU_SW_LSI: + CKCU_Clk->SYSCK_Freq = LSI_VALUE; + break; + #endif + default: + CKCU_Clk->SYSCK_Freq = 0; + break; + } + + /* Get HCLK frequency */ + CKCU_Clk->HCLK_Freq = (CKCU_Clk->SYSCK_Freq) >> (HT_CKCU->AHBCFGR); + + #if (LIBCFG_CKCU_USART_PRESCALER) + /* Get USART frequency */ + { + u32 urpre; + urpre = CKCU_BF_READ(HT_CKCU->GCFGR, CKCU_MASK_URPRE, CKCU_POS_URPRE); + CKCU_Clk->USART_Freq = (CKCU_Clk->HCLK_Freq) >> urpre; + } + #endif + + /* Get ADC frequency */ + div = CKCU_BF_READ(HT_CKCU->APBCFGR, CKCU_MASK_ADCDIV, CKCU_POS_ADCDIV); + CKCU_Clk->ADC0_Freq = (div == 7) ? ((CKCU_Clk->HCLK_Freq) / 6) : ((CKCU_Clk->HCLK_Freq) >> div); +} + +/*********************************************************************************************************//** + * @brief Return the frequency of the PLL. + * @retval PLL Frequency + ************************************************************************************************************/ +u32 CKCU_GetPLLFrequency(void) +{ + u32 pllNO, pllNF, ClockSrc; + + /* Get PLL frequency */ + if (CKCU_BB_PLLEN == DISABLE) + { + return 0; + } + + ClockSrc = (CKCU_BB_PLLSRC == CKCU_PLLSRC_HSE) ? HSE_VALUE : HSI_VALUE; + + if (CKCU_BB_PLLBYPASS == ENABLE) + { + return ClockSrc; + } + + pllNF = CKCU_BF_READ(HT_CKCU->PLLCFGR, CKCU_MASK_PFBD, CKCU_POS_PFBD); + if (pllNF == 0) + pllNF = 64; + + pllNO = CKCU_BF_READ(HT_CKCU->PLLCFGR, CKCU_MASK_POTD, CKCU_POS_POTD); + pllNO = (u8)0x1 << pllNO; + + return ((ClockSrc / pllNO) * pllNF); +} + +#if (LIBCFG_CKCU_NO_APB_PRESCALER == 0) +/*********************************************************************************************************//** + * @brief Configure the APB peripheral prescaler. + * @param Perip: specify the APB peripheral. + * This parameter can be: + * @arg CKCU_PCLK_I2C0, CKCU_PCLK_I2C1, + * CKCU_PCLK_SPI0, CKCU_PCLK_SPI1, + * CKCU_PCLK_BFTM0, CKCU_PCLK_BFTM1, + * CKCU_PCLK_MCTM0, CKCU_PCLK_MCTM1, + * CKCU_PCLK_GPTM0, CKCU_PCLK_GPTM1, + * CKCU_PCLK_USART0, CKCU_PCLK_USART1, + * CKCU_PCLK_UART0, CKCU_PCLK_UART1, + * CKCU_PCLK_AFIO, CKCU_PCLK_EXTI, CKCU_PCLK_ADC, CKCU_PCLK_CMP, + * CKCU_PCLK_WDTR, CKCU_PCLK_BKPR, + * CKCU_PCLK_SCI0, CKCU_PCLK_SCI1, + * CKCU_PCLK_I2S, + * CKCU_PCLK_SCTM0, CKCU_PCLK_SCTM1, + * CKCU_PCLK_PWM0 + * @param PCLKPrescaler: specify the value of prescaler. + * This parameter can be: + * @arg CKCU_APBCLKPRE_DIV1: specific peripheral clock = PCLK / 1 (inapplicable to BKPRCLK) + * @arg CKCU_APBCLKPRE_DIV2: specific peripheral clock = PCLK / 2 (inapplicable to BKPRCLK) + * @arg CKCU_APBCLKPRE_DIV4: specific peripheral clock = PCLK / 4 + * @arg CKCU_APBCLKPRE_DIV8: specific peripheral clock = PCLK / 8 + * @arg CKCU_APBCLKPRE_DIV16: specific peripheral clock = PCLK / 16 (BKPRCLK only) + * @arg CKCU_APBCLKPRE_DIV32: specific peripheral clock = PCLK / 32 (BKPRCLK only) + * @retval None + ************************************************************************************************************/ +void CKCU_SetPeripPrescaler(CKCU_PeripPrescaler_TypeDef Perip, CKCU_APBCLKPRE_TypeDef PCLKPrescaler) +{ + u32 *PCSR = (u32 *)((&HT_CKCU->APBPCSR0) + (Perip >> CKCU_APBPCSR_OFFSET)); + u32 Prescaler = PCLKPrescaler; + if (Perip == CKCU_PCLK_BKPR) + { + Prescaler -= 2; + } + Perip &= 0x0000001F; + CKCU_BF_WRITE(*PCSR, (3UL << Perip), Perip, Prescaler); +} +#endif + +/*********************************************************************************************************//** + * @brief Return the operating frequency of the specific APB peripheral. + * @param Perip: specify the APB peripheral. + * This parameter can be: + * @arg CKCU_PCLK_I2C0, CKCU_PCLK_I2C1, + * CKCU_PCLK_SPI0, CKCU_PCLK_SPI1, + * CKCU_PCLK_BFTM0, CKCU_PCLK_BFTM1, + * CKCU_PCLK_MCTM0, CKCU_PCLK_MCTM1, + * CKCU_PCLK_GPTM0, CKCU_PCLK_GPTM1, + * CKCU_PCLK_USART0, CKCU_PCLK_USART1, + * CKCU_PCLK_UART0, CKCU_PCLK_UART1, + * CKCU_PCLK_AFIO, CKCU_PCLK_EXTI, CKCU_PCLK_ADC, CKCU_PCLK_CMP, + * CKCU_PCLK_WDTR, CKCU_PCLK_BKPR, + * CKCU_PCLK_SCI0, CKCU_PCLK_SCI1, + * CKCU_PCLK_I2S, + * CKCU_PCLK_I2S, + * CKCU_PCLK_SCTM0, CKCU_PCLK_SCTM1, + * CKCU_PCLK_PWM0 + * @retval Frequency in Hz + ************************************************************************************************************/ +u32 CKCU_GetPeripFrequency(CKCU_PeripPrescaler_TypeDef Perip) +{ + CKCU_ClocksTypeDef Clock; + + #if (LIBCFG_CKCU_NO_APB_PRESCALER) + CKCU_GetClocksFrequency(&Clock); + return Clock.HCLK_Freq; + #else + u32 *PCSR = (u32 *)(&HT_CKCU->APBPCSR0 + (Perip >> CKCU_APBPCSR_OFFSET)); + u32 PCLKPrescaler = 0; + + if (Perip == CKCU_PCLK_BKPR) + { + PCLKPrescaler = 2; + } + + Perip &= 0x0000001F; + PCLKPrescaler += CKCU_BF_READ(*PCSR, (3UL << Perip), Perip); + + CKCU_GetClocksFrequency(&Clock); + return (Clock.HCLK_Freq >> (PCLKPrescaler)); + #endif +} + +/*********************************************************************************************************//** + * @brief Enable or Disable the HSE Clock Monitor function. + * @param Cmd: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void CKCU_CKMCmd(ControlStatus Cmd) +{ + /* Check the parameters */ + Assert_Param(IS_CONTROL_STATUS(Cmd)); + + CKCU_BB_CKMEN = Cmd; +} + +/*********************************************************************************************************//** + * @brief Enable or Disable the power saving wakeup RC clock. + * @param Cmd: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void CKCU_PSRCWKUPCmd(ControlStatus Cmd) +{ + /* Check the parameters */ + Assert_Param(IS_CONTROL_STATUS(Cmd)); + + CKCU_BB_PSRCEN = Cmd; +} + +/*********************************************************************************************************//** + * @brief Select the output clock source through the CKOUT pin. + * @param CKOUTInit: pointer to CKCU_CKOUTInitTypeDef structure. + * @retval None + ************************************************************************************************************/ +void CKCU_CKOUTConfig(CKCU_CKOUTInitTypeDef *CKOUTInit) +{ + CKCU_BF_WRITE(HT_CKCU->GCFGR, CKCU_MASK_CKOUTSRC, CKCU_POS_CKOUTSRC, CKOUTInit->CKOUTSRC); +} + +/*********************************************************************************************************//** + * @brief Check whether the specific CKCU interrupt has occurred or not. + * @param CKCU_INT: specify the CKCU interrupt source. + * This parameter can be any combination of the following values: + * @arg CKCU_INT_CKS, CKCU_INT_PLLRDY, CKCU_INT_HSERDY, CKCU_INT_HSIRDY, CKCU_INT_LSERDY, CKCU_INT_LSIRDY + * @retval SET or RESET + ************************************************************************************************************/ +FlagStatus CKCU_GetIntStatus(u32 CKCU_INT) +{ + /* Check the parameters */ + Assert_Param(IS_CKCU_INT_FLAG(CKCU_INT)); + + if (HT_CKCU->GCIR & CKCU_INT) + { + return SET; + } + else + { + return RESET; + } +} + +/*********************************************************************************************************//** + * @brief Clear the CKCU interrupt flag. + * @param CKCU_INT: specify the CKCU interrupt flag to clear. + * This parameter can be any combination of the following values: + * @arg CKCU_INT_CKS : HSE clock failure interrupt flag (NMI) + * @arg CKCU_INT_USBPLLRDY : USB PLL ready interrupt flag + * @arg CKCU_INT_PLLRDY : PLL ready interrupt flag + * @arg CKCU_INT_HSERDY : HSE ready interrupt flag + * @arg CKCU_INT_HSIRDY : HSI ready interrupt flag + * @arg CKCU_INT_LSERDY : LSE ready interrupt flag + * @arg CKCU_INT_LSIRDY : LSI ready interrupt flag + * @retval None + ************************************************************************************************************/ +void CKCU_ClearIntFlag(u32 CKCU_INT) +{ + /* Check the parameters */ + Assert_Param(IS_CKCU_INT_FLAG(CKCU_INT)); + + HT_CKCU->GCIR |= CKCU_INT; +} + +/*********************************************************************************************************//** + * @brief Enable or Disable the specific CKCU interrupts. + * @param CKCU_INT: specify the CKCU interrupt source which is enabled or disabled. + * This parameter can be any combination of the following values: + * @arg CKCU_INT_CKSIE : HSE clock failure interrupt (NMI) + * @arg CKCU_INT_USBPLLRDYIE : USB PLL ready interrupt + * @arg CKCU_INT_PLLRDYIE : PLL ready interrupt + * @arg CKCU_INT_HSERDYIE : HSE ready interrupt + * @arg CKCU_INT_HSIRDYIE : HSI ready interrupt + * @arg CKCU_INT_LSERDYIE : LSE ready interrupt + * @arg CKCU_INT_LSIRDYIE : LSI ready interrupt + * @param Cmd: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void CKCU_IntConfig(u32 CKCU_INT, ControlStatus Cmd) +{ + u32 tmp1 = HT_CKCU->GCIR; + + /* Check the parameters */ + Assert_Param(IS_CKCU_INT(CKCU_INT)); + Assert_Param(IS_CONTROL_STATUS(Cmd)); + + if (Cmd != DISABLE) + { + tmp1 |= CKCU_INT; + } + else + { + tmp1 &= ~CKCU_INT; + } + + /* Note: CKCU interrupt flags will be cleared by writing "1" */ +#if (LIBCFG_CKCU_USB_PLL) + tmp1 &= ~0x0000007F; +#else + tmp1 &= ~0x0000007D; +#endif + HT_CKCU->GCIR = tmp1; +} + +/*********************************************************************************************************//** + * @brief Enable or Disable the AHB peripheral clock during SLEEP mode. + * @param CKCU_CLK: specify the clock which is enabled or disabled. + * This parameter can be any combination of the following values: + * @arg CKCU_AHBEN_SLEEP_FMC, CKCU_AHBEN_SLEEP_SRAM, CKCU_AHBEN_SLEEP_BM, CKCU_AHBEN_SLEEP_APB0, + * CKCU_AHBEN_SLEEP_APB1 + * @param Cmd: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void CKCU_SleepClockConfig(u32 CKCU_CLK, ControlStatus Cmd) +{ + /* Check the parameters */ + Assert_Param(IS_CKCU_SLEEP_AHB(CKCU_CLK)); + Assert_Param(IS_CONTROL_STATUS(Cmd)); + + if (Cmd != DISABLE) + { + HT_CKCU->AHBCCR |= CKCU_CLK; + } + else + { + HT_CKCU->AHBCCR &= ~CKCU_CLK; + } +} + +/*********************************************************************************************************//** + * @brief Check if PLL clock used by the specific target source or not. + * @param Target: specify the target clock. + * This parameter can be one of the following values: + * @arg CKCU_PLLST_SYSCK : Is PLL used by system clock + * @arg CKCU_PLLST_USB : Is PLL used by USB + * @arg CKCU_PLLST_REFCK : Is PLL used by CK_REF + * @retval TRUE or FALSE + ************************************************************************************************************/ +bool CKCU_IS_PLL_USED(CKCU_PLLST_TypeDef Target) +{ + if ((HT_CKCU->CKST >> CKCU_POS_PLLST) & (u32)Target) + { + return TRUE; + } + else + { + return FALSE; + } +} + +/*********************************************************************************************************//** + * @brief Check HSI clock used by the specific target source or not. + * @param Target: specify the target clock. + * This parameter can be one of the following values: + * @arg CKCU_HSIST_SYSCK : Is HSI used by system clock + * @arg CKCU_HSIST_PLL : Is HSI used by PLL + * @arg CKCU_HSIST_CKM : Is HSI used by clock monitor + * @retval TRUE or FALSE + ************************************************************************************************************/ +bool CKCU_IS_HSI_USED(CKCU_HSIST_TypeDef Target) +{ + if ((HT_CKCU->CKST >> CKCU_POS_HSIST) & (u32)Target) + { + return TRUE; + } + else + { + return FALSE; + } +} + +/*********************************************************************************************************//** + * @brief Check HSE clock used by the specific target source or not. + * @param Target: specify the target clock. + * This parameter can be one of the following values: + * @arg CKCU_HSEST_SYSCK : Is HSE used by system clock + * @arg CKCU_HSEST_PLL : Is HSE used by PLL + * @retval TRUE or FALSE + ************************************************************************************************************/ +bool CKCU_IS_HSE_USED(CKCU_HSEST_TypeDef Target) +{ + if ((HT_CKCU->CKST >> CKCU_POS_HSEST) & (u32)Target) + { + return TRUE; + } + else + { + return FALSE; + } +} + +/*********************************************************************************************************//** + * @brief Enable or Disable the specific debug function. + * @param CKCU_DBGx: specify the debug functions to be enabled or disabled. + * This parameter can be any combination of the following values: + * @arg CKCU_DBG_SLEEP, CKCU_DBG_DEEPSLEEP1, CKCU_DBG_DEEPSLEEP2, CKCU_DBG_POWERDOWN, + * CKCU_DBG_MCTM0_HALT, CKCU_DBG_MCTM1_HALT, + * CKCU_DBG_GPTM0_HALT, CKCU_DBG_GPTM1_HALT, + * CKCU_DBG_PWM_HALT, CKCU_DBG_SCTM0_HALT, CKCU_DBG_SCTM1_HALT, + * CKCU_DBG_BFTM0_HALT, CKCU_DBG_BFTM1_HALT, + * CKCU_DBG_USART0_HALT, CKCU_DBG_USART1_HALT, + * CKCU_DBG_UART0_HALT, CKCU_DBG_UART1_HALT, + * CKCU_DBG_SPI0_HALT, CKCU_DBG_SPI1_HALT, + * CKCU_DBG_I2C0_HALT, CKCU_DBG_I2C1_HALT, + * CKCU_DBG_SCI0_HALT, CKCU_DBG_SCI1_HALT, + * CKCU_DBG_WDT_HALT, CKCU_DBG_TRACE_ON + * @param Cmd: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void CKCU_MCUDBGConfig(u32 CKCU_DBGx, ControlStatus Cmd) +{ + /* Check the parameters */ + Assert_Param(IS_CKCU_DBG(CKCU_DBGx)); + Assert_Param(IS_CONTROL_STATUS(Cmd)); + + if (Cmd != DISABLE) + { + HT_CKCU->MCUDBGCR |= CKCU_DBGx; + } + else + { + HT_CKCU->MCUDBGCR &= ~CKCU_DBGx; + } +} + +#if (!LIBCFG_NO_BACK_DOMAIN) +/*********************************************************************************************************//** + * @brief Enable or Disable the Backup domain isolation control. + * @param Cmd: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void CKCU_BKISOCmd(ControlStatus Cmd) +{ + /* Check the parameters */ + Assert_Param(IS_CONTROL_STATUS(Cmd)); + + if (Cmd != DISABLE) + { + CKCU_BB_BKISO = 0; /* Backup domain is isolated */ + } + else + { + CKCU_BB_BKISO = 1; /* Backup domain is accessible */ + } +} +#endif + +/*********************************************************************************************************//** + * @brief Enable or Disable the peripheral clock. + * @param Clock: specify the peripheral clock enable bits. + * @param Cmd: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void CKCU_PeripClockConfig(CKCU_PeripClockConfig_TypeDef Clock, ControlStatus Cmd) +{ + u32 uAHBCCR; + u32 uAPBCCR0; + u32 uAPBCCR1; + + uAHBCCR = HT_CKCU->AHBCCR; + uAPBCCR0 = HT_CKCU->APBCCR0; + uAPBCCR1 = HT_CKCU->APBCCR1; + + uAHBCCR &= ~(Clock.Reg[0]); + uAPBCCR0 &= ~(Clock.Reg[1]); + uAPBCCR1 &= ~(Clock.Reg[2]); + + if (Cmd != DISABLE) + { + uAHBCCR |= Clock.Reg[0]; + uAPBCCR0 |= Clock.Reg[1]; + uAPBCCR1 |= Clock.Reg[2]; + } + + HT_CKCU->AHBCCR = uAHBCCR; + HT_CKCU->APBCCR0 = uAPBCCR0; + HT_CKCU->APBCCR1 = uAPBCCR1; +} + +#if (!LIBCFG_CKCU_HSI_NO_AUTOTRIM) +/*********************************************************************************************************//** + * @brief Configure the reference clock of HSI auto-trim function. + * @param CLKSRC: specify the clock source. + * This parameter can be: + * @arg CKCU_ATC_LSE: LSE is selected as reference clock + * @arg CKCU_ATC_USB: USB is selected as reference clock + * @arg CKCU_ATC_CKIN: External pin (CKIN) is selected as reference clock + * @retval None + ************************************************************************************************************/ +void CKCU_HSIAutoTrimClkConfig(CKCU_ATC_TypeDef CLKSRC) +{ + #if (LIBCFG_CKCU_AUTOTRIM_NOCKIN==1) + HT_CKCU->HSICR = (HT_CKCU->HSICR & (~(0x1 << 5))) | (CLKSRC << 5); + #else + HT_CKCU->HSICR = (HT_CKCU->HSICR & (~(0x3 << 5))) | (CLKSRC << 5); + #endif +} + +#if (LIBCFG_CKCU_ATM_V01) +/*********************************************************************************************************//** + * @brief Initialize the ATC according to the specified parameters in the ATC_InitStruct. + * @param ATC_InitStruct: pointer to a CKCU_ATCInitTypeDef structure. + * @retval None + ************************************************************************************************************/ +void CKCU_ATCInit(CKCU_ATCInitTypeDef* ATC_InitStruct) +{ + HT_CKCU->HSICR &= 0xFFFFFFF3; + HT_CKCU->HSICR |= (u32)ATC_InitStruct->SearchAlgorithm | (u32)ATC_InitStruct->FrqTolerance; +} + +/*********************************************************************************************************//** + * @brief Automatic Trimming Algorithm Mode Selection. + * @param Algo: Search Algorithm. + * This parameter can be: + * @arg CKCU_ATC_BINARY_SEARCH: Auto Trimming Controller is used binary search to approach the target range + * @arg CKCU_ATC_LINEAR_SEARCH: Auto Trimming Controller is used linear search to approach the target range + * @retval None + ***********************************************************************************************************/ +void CKCU_HSIAutoTrimAlgorithm(u32 Algo) +{ + HT_CKCU->HSICR = (HT_CKCU->HSICR & (~(0x1 << 3))) | Algo; +} + +/*********************************************************************************************************//** + * @brief Lock Target Range Selection. + * @param Tolerance: Variation Tolerance. + * This parameter can be: + * @arg CKCU_ATC_DOUBLE_PRECISION: 0.2 % variation + * @arg CKCU_ATC_SINGLE_PRECISION: 0.1 % variation + * @retval None + ***********************************************************************************************************/ +void CKCU_HSIAutoTrimFreqTolerance(u32 Tolerance) +{ + HT_CKCU->HSICR = (HT_CKCU->HSICR & (~(0x1 << 2))) | Tolerance; +} +#endif + +/*********************************************************************************************************//** + * @brief Enable or Disable the HSI auto-trim function. + * @param Cmd: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void CKCU_HSIAutoTrimCmd(ControlStatus Cmd) +{ + /* Check the parameters */ + Assert_Param(IS_CONTROL_STATUS(Cmd)); + + CKCU_BB_TRIMEN = Cmd; + CKCU_BB_ATCEN = Cmd; +} + +/*********************************************************************************************************//** + * @brief Check Auto Trim is ready or not. + * @retval TRUE or FALSE + ************************************************************************************************************/ +bool CKCU_HSIAutoTrimIsReady(void) +{ +#if (LIBCFG_CKCU_AUTO_TRIM_LEGACY) + u32 lower_bound, upper_bound, i; + static u32 ATCR = 0; + + if ((HT_CKCU->HSICR & (3ul << 5)) == 0) + { + lower_bound = 7812 - 19; + upper_bound = 7812 + 19; + } + else + { + lower_bound = 8000 - 20; + upper_bound = 8000 + 20; + } + + SystemCoreClockUpdate(); + for (i = SystemCoreClock / 8000; i > 0; i--){}; + ATCR += HT_CKCU->HSIATCR; + ATCR /= 2; + + if ((ATCR >= lower_bound) && (ATCR <= upper_bound)) + { + ATCR = 0; + return TRUE; + } + else + { + return FALSE; + } + +#else + return (HT_CKCU->HSICR & 0x80) ? TRUE : FALSE; +#endif +} +#endif +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ diff --git a/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/src/ht32f1xxxx_cmp.c b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/src/ht32f1xxxx_cmp.c new file mode 100644 index 0000000000..ec0688153b --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/src/ht32f1xxxx_cmp.c @@ -0,0 +1,298 @@ +/*********************************************************************************************************//** + * @file ht32f1xxxx_cmp.c + * @version $Rev:: 2794 $ + * @date $Date:: 2022-11-25 #$ + * @brief This file provides all the CMP firmware functions. + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ + +/* Includes ------------------------------------------------------------------------------------------------*/ +#include "ht32f1xxxx_cmp.h" + +/** @addtogroup HT32F1xxxx_Peripheral_Driver HT32F1xxxx Peripheral Driver + * @{ + */ + +/** @defgroup CMP CMP + * @brief CMP driver modules + * @{ + */ + + +/* Global functions ----------------------------------------------------------------------------------------*/ +/** @defgroup CMP_Exported_Functions CMP exported functions + * @{ + */ +/*********************************************************************************************************//** + * @brief Deinitialize the CMP0 and CMP1 peripheral registers to their default reset values. + * @param HT_CMPn: where HT_CMPn is the selected CMP from the CMP peripherals. + * @retval None + ************************************************************************************************************/ +void CMP_DeInit(HT_CMP_TypeDef* HT_CMPn) +{ + RSTCU_PeripReset_TypeDef RSTCUReset = {{0}}; + + if (HT_CMPn == NULL) // Remove the compiler warning + { + } + + RSTCUReset.Bit.CMP = 1; + RSTCU_PeripReset(RSTCUReset, ENABLE); +} + +/*********************************************************************************************************//** + * @brief Unprotect the selected comparator configuration before setting the Comparator Control Register. + * @param HT_CMPn: where HT_CMPn is the selected CMP from the CMP peripherals. + * @retval None + ************************************************************************************************************/ +void CMP_UnprotectConfig(HT_CMP_TypeDef* HT_CMPn) +{ + /* Check the parameters */ + Assert_Param(IS_CMP(HT_CMPn)); + + /* Set the unlock code corresponding to selected comparator */ + HT_CMPn->CR = CMP_PROTECT_KEY; +} + +/*********************************************************************************************************//** + * @brief Initialize the CMP peripheral according to the specified parameters in the CMP_InitStruct. + * @param HT_CMPn: where HT_CMPn is the selected CMP from the CMP peripherals. + * @param CMP_InitStruct: pointer to a CMP_InitTypeDef structure. + * @retval None + ************************************************************************************************************/ +void CMP_Init(HT_CMP_TypeDef* HT_CMPn, CMP_InitTypeDef* CMP_InitStruct) +{ + /* Check the parameters */ + Assert_Param(IS_CMP(HT_CMPn)); + Assert_Param(IS_CMP_Wakeup_Set(CMP_InitStruct->CMP_Wakeup)); + Assert_Param(IS_CMP_OutputSelection(CMP_InitStruct->CMP_OutputSelection)); + Assert_Param(IS_CMP_ScalerSource(CMP_InitStruct->CMP_ScalerSource)); + Assert_Param(IS_CMP_ScalerOutputBuf(CMP_InitStruct->CMP_ScalerOutputBuf)); + Assert_Param(IS_CMP_ScalerEnable(CMP_InitStruct->CMP_ScalerEnable)); + Assert_Param(IS_CMP_CoutSynchronized(CMP_InitStruct->CMP_CoutSync)); + Assert_Param(IS_CMP_OutputPol_Set(CMP_InitStruct->CMP_OutputPol)); + Assert_Param(IS_CMP_InvInputSelection(CMP_InitStruct->CMP_InvInputSelection)); + Assert_Param(IS_CMP_Hysteresis_Set(CMP_InitStruct->CMP_Hysteresis)); + Assert_Param(IS_CMP_Speed_Set(CMP_InitStruct->CMP_Speed)); + + HT_CMPn->CR |= CMP_InitStruct->CMP_Wakeup | CMP_InitStruct->CMP_OutputSelection | CMP_InitStruct->CMP_ScalerSource | \ + CMP_InitStruct->CMP_ScalerOutputBuf | CMP_InitStruct->CMP_ScalerEnable | CMP_InitStruct->CMP_CoutSync | \ + CMP_InitStruct->CMP_OutputPol | CMP_InitStruct->CMP_InvInputSelection | CMP_InitStruct->CMP_Hysteresis | \ + CMP_InitStruct->CMP_Speed; +} + +/*********************************************************************************************************//** + * @brief Fill each CMP_InitStruct member with its default value. + * @param CMP_InitStruct: pointer to an CMP_InitTypeDef structure. + * @retval None + ************************************************************************************************************/ +void CMP_StructInit(CMP_InitTypeDef* CMP_InitStruct) +{ + /* CMP_InitStruct members default value */ + CMP_InitStruct->CMP_Wakeup = CMP_WUP_DISABLE; + CMP_InitStruct->CMP_OutputSelection = CMP_TRIG_NONE; + CMP_InitStruct->CMP_ScalerSource = CMP_SCALER_SRC_VDDA; + CMP_InitStruct->CMP_ScalerOutputBuf = CMP_SCALER_OBUF_DISABLE; + CMP_InitStruct->CMP_ScalerEnable = CMP_SCALER_DISABLE; + CMP_InitStruct->CMP_CoutSync = CMP_ASYNC_OUTPUT; + CMP_InitStruct->CMP_OutputPol = CMP_NONINV_OUTPUT; + CMP_InitStruct->CMP_InvInputSelection = CMP_EXTERNAL_CN_IN; + CMP_InitStruct->CMP_Hysteresis = CMP_NO_HYSTERESIS; + CMP_InitStruct->CMP_Speed = CMP_LOW_SPEED; +} + +/*********************************************************************************************************//** + * @brief Enable or Disable the specified CMP peripheral. + * @param HT_CMPn: where HT_CMPn is the selected CMP from the CMP peripherals. + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void CMP_Cmd(HT_CMP_TypeDef* HT_CMPn, ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_CMP(HT_CMPn)); + Assert_Param(IS_CONTROL_STATUS(NewState)); + + if (NewState != DISABLE) + { + HT_CMPn->CR |= CMP_ENABLE; + } + else + { + HT_CMPn->CR &= ~(u32)CMP_ENABLE; + } +} + +/*********************************************************************************************************//** + * @brief Enable or Disable the specified CMP interrupts. + * @param HT_CMPn: where HT_CMPn is the selected CMP from the CMP peripherals. + * @param CMP_INT_x: specify the CMP interrupt sources that is to be enabled or disabled. + * This parameter can be any combination of the following values: + * @arg CMP_INT_RE : CMP rising edge interrupt + * @arg CMP_INT_FE : CMP falling edge interrupt + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void CMP_IntConfig(HT_CMP_TypeDef* HT_CMPn, u32 CMP_INT_x, ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_CMP(HT_CMPn)); + Assert_Param(IS_CMP_INT(CMP_INT_x)); + Assert_Param(IS_CONTROL_STATUS(NewState)); + + if (NewState != DISABLE) + { + HT_CMPn->IER |= CMP_INT_x; + } + else + { + HT_CMPn->IER &= ~CMP_INT_x; + } +} + +/*********************************************************************************************************//** + * @brief Enable or Disable the specified CMP edge detection. + * @param HT_CMPn: where HT_CMPn is the selected CMP from the CMP peripherals. + * @param CMP_xE_Detect: specify the CMP edge detection that is to be enabled or disabled. + * This parameter can be any combination of the following values: + * @arg CMP_RE_Detect : CMP rising edge detection + * @arg CMP_FE_Detect : CMP falling edge detection + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void CMP_EdgeDetectConfig(HT_CMP_TypeDef* HT_CMPn, u32 CMP_xE_Detect, ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_CMP(HT_CMPn)); + Assert_Param(IS_CMP_EdgeDetect(CMP_xE_Detect)); + Assert_Param(IS_CONTROL_STATUS(NewState)); + + if (NewState != DISABLE) + { + HT_CMPn->TFR = (HT_CMPn->TFR | CMP_xE_Detect) & 0xfffffffc; + } + else + { + HT_CMPn->TFR = (HT_CMPn->TFR & (~CMP_xE_Detect)) & 0xfffffffc; + } +} + +/*********************************************************************************************************//** + * @brief Check whether the specified CM flag has been set. + * @param HT_CMPn: where HT_CMPn is the selected CMP from the CMP peripherals. + * @param CMP_FLAG_x: specify the flag to be checked. + * This parameter can be any combination of the following values: + * @arg CMP_FLAG_RE : CMP rising edge flag + * @arg CMP_FLAG_FE : CMP falling edge flag + * @retval SET or RESET + ************************************************************************************************************/ +FlagStatus CMP_GetFlagStatus(HT_CMP_TypeDef* HT_CMPn, u32 CMP_FLAG_x) +{ + /* Check the parameters */ + Assert_Param(IS_CMP(HT_CMPn)); + Assert_Param(IS_CMP_FLAG(CMP_FLAG_x)); + + if ((HT_CMPn->TFR & CMP_FLAG_x) != 0) + { + return SET; + } + else + { + return RESET; + } +} + +/*********************************************************************************************************//** + * @brief Clear flags of the specified CMP. + * @param HT_CMPn: where HT_CMPn is the selected CMP from the CMP peripherals. + * @param CMP_FLAG_x: specify the flag to be checked. + * This parameter can be any combination of the following values: + * @arg CMP_FLAG_RE : CMP rising edge flag + * @arg CMP_FLAG_FE : CMP falling edge flag + * @retval None + ************************************************************************************************************/ +void CMP_ClearFlag(HT_CMP_TypeDef* HT_CMPn, u32 CMP_FLAG_x) +{ + /* Check the parameters */ + Assert_Param(IS_CMP(HT_CMPn)); + Assert_Param(IS_CMP_FLAG(CMP_FLAG_x)); + + /* Clear the flags */ + HT_CMPn->TFR = (HT_CMPn->TFR & 0xfffffffc) | CMP_FLAG_x; + + /*--------------------------------------------------------------------------------------------------------*/ + /* DSB instruction is added in this function to ensure the write operation which is for clearing interrupt*/ + /* flag is actually completed before exiting ISR. It prevents the NVIC from detecting the interrupt again */ + /* since the write register operation may be pended in the internal write buffer of Cortex-Mx when program*/ + /* has exited interrupt routine. This DSB instruction may be masked if this function is called in the */ + /* beginning of ISR and there are still some instructions before exiting ISR. */ + /*--------------------------------------------------------------------------------------------------------*/ + __DSB(); +} + +/*********************************************************************************************************//** + * @brief Get the output status of the specified CMP. + * @param HT_CMPn: where HT_CMPn is the selected CMP from the CMP peripherals. + * @retval SET or RESET + ************************************************************************************************************/ +FlagStatus CMP_GetOutputStatus(HT_CMP_TypeDef* HT_CMPn) +{ + /* Check the parameters */ + Assert_Param(IS_CMP(HT_CMPn)); + + if ((HT_CMPn-> CR & CMP_OUTPUT_HIGH) != 0) + { + return SET; + } + else + { + return RESET; + } +} + +/*********************************************************************************************************//** + * @brief Set the specified reference value in the data register of the scaler. + * @param HT_CMPn: where HT_CMPn is the selected CMP from the CMP peripherals. + * @param Scaler_Value: value to be loaded in the selected data register + * @retval None + ************************************************************************************************************/ +void CMP_SetScalerValue(HT_CMP_TypeDef* HT_CMPn, u8 Scaler_Value) +{ + /* Check the parameters */ + Assert_Param(IS_CMP(HT_CMPn)); + Assert_Param(IS_SCALER_VALUE(Scaler_Value)); + + /* Set the scaler reference value register */ + HT_CMPn->VALR = (u32)Scaler_Value; +} +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ diff --git a/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/src/ht32f1xxxx_cmp_op.c b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/src/ht32f1xxxx_cmp_op.c new file mode 100644 index 0000000000..cd26f7a5d8 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/src/ht32f1xxxx_cmp_op.c @@ -0,0 +1,307 @@ +/*********************************************************************************************************//** + * @file ht32f1xxxx_cmp_op.c + * @version $Rev:: 129 $ + * @date $Date:: 2017-06-14 #$ + * @brief This file provides all the CMP_OP firmware functions. + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ + +/* Includes ------------------------------------------------------------------------------------------------*/ +#include "ht32f1xxxx_cmp_op.h" + +/** @addtogroup HT32F1xxxx_Peripheral_Driver HT32F1xxxx Peripheral Driver + * @{ + */ + +/** @defgroup CMP_OP CMP_OP + * @brief CMP_OP driver modules + * @{ + */ + + +/* Private constants ---------------------------------------------------------------------------------------*/ +/** @defgroup CMP_OP_Private_Define CMP_OP private definitions + * @{ + */ +#define CMP_OP_ENABLE (0x00000001ul) +#define CMP_OP_CANCELLATION_MODE (0x00000004ul) +/** + * @} + */ + + +/* Global functions ----------------------------------------------------------------------------------------*/ +/** @defgroup CMP_OP_Exported_Functions CMP_OP exported functions + * @{ + */ +/*********************************************************************************************************//** + * @brief Deinitialize the CMP_OP peripheral registers to their default reset values. + * @param CMP_OPx: where x can be 0 or 1 to select the CMP_OP peripheral. + * @retval None + ************************************************************************************************************/ +void CMP_OP_DeInit(HT_CMP_OP_TypeDef* CMP_OPx) +{ + RSTCU_PeripReset_TypeDef RSTCUReset = {{0}}; + + /* Check the parameters */ + Assert_Param(IS_CMP_OP_ALL_PERIPH(CMP_OPx)); + + if (CMP_OPx == HT_CMP_OP0) + { + RSTCUReset.Bit.OPA0 = 1; + } + else + { + RSTCUReset.Bit.OPA1 = 1; + } + + RSTCU_PeripReset(RSTCUReset, ENABLE); +} + +/*********************************************************************************************************//** + * @brief Configure the CMP_OP peripheral as OPA or CMP mode and fill the cancellation value. + * @param CMP_OPx: where CMP_OP is the selected CMP_OP from the CMP_OP peripherals, x can be 0 or 1. + * @param mode: Specify the CMP_OPx peripheral mode + * This parameter can be any combination of the following values: + * @arg OP_MODE : Operational Amplifier mode + * @arg CMP_MODE : Comparator Mode Selection + * @param cancellation: Specify the input offset voltage cancellation value. + * @retval None +************************************************************************************************************/ +void CMP_OP_Config(HT_CMP_OP_TypeDef* CMP_OPx, u32 mode, u32 cancellation) +{ + /* Check the parameters */ + Assert_Param(IS_CMP_OP_ALL_PERIPH(CMP_OPx)); + Assert_Param(IS_CMP_OP_MODE(mode)); + Assert_Param(IS_CMP_OP_IOVC(cancellation)); + + CMP_OPx->OPACR = (CMP_OPx->OPACR & CMP_OP_ENABLE) | mode; + CMP_OPx->OFVCR = cancellation; +} + +/*********************************************************************************************************//** + * @brief Enable or Disable the specified CMP_OP peripheral. + * @param CMP_OPx: where CMP_OPx is the selected CMP_OP from the CMP_OP peripherals, x can be 0 or 1. + * @param NewState: new state of the CMP_OPx peripheral. + * This parameter can be: ENABLE or DISABLE. + * @retval None +************************************************************************************************************/ +void CMP_OP_Cmd(HT_CMP_OP_TypeDef* CMP_OPx, ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_CMP_OP_ALL_PERIPH(CMP_OPx)); + Assert_Param(IS_CONTROL_STATUS(NewState)); + + if (NewState != DISABLE) + { + /* Enable the selected CMP_OPx peripheral */ + CMP_OPx->OPACR |= CMP_OP_ENABLE; + } + else + { + /* Disable the selected CMP_OPx peripheral */ + CMP_OPx->OPACR &= ~(u32)CMP_OP_ENABLE; + } +} + +/*********************************************************************************************************//** + * @brief Configure the CMP_OP peripheral as cancellation mode and select the source of reference input. + * @param CMP_OPx: where CMP_OPx is the selected CMP_OP from the CMP_OP peripherals, x can be 0 or 1. + * @param CMP_OP_REF_INPUT: Specify the the source of reference input. + * This parameter can be any combination of the following values: + * @arg CMP_OP_NEGATIVE_INPUT + * @arg CMP_OP_POSITIVE_INPUT + * @retval None +************************************************************************************************************/ +void CMP_OP_CancellationModeConfig(HT_CMP_OP_TypeDef* CMP_OPx, u16 CMP_OP_REF_INPUT) +{ + /* Check the parameters */ + Assert_Param(IS_CMP_OP_ALL_PERIPH(CMP_OPx)); + Assert_Param(IS_CMP_OP_REF(CMP_OP_REF_INPUT)); + + CMP_OPx->OPACR = (CMP_OPx->OPACR & CMP_OP_ENABLE) | CMP_OP_CANCELLATION_MODE | CMP_OP_REF_INPUT; +} + +/*********************************************************************************************************//** + * @brief Set input offset voltage cancellation value. + * @param CMP_OPx: where CMP_OPx is the selected CMP_OP from the CMP_OP peripherals, x can be 0 or 1. + * @param cancellation: Specify the input offset voltage cancellation value. + * @retval None +************************************************************************************************************/ +void CMP_OP_SetCancellationVaule(HT_CMP_OP_TypeDef* CMP_OPx, u32 cancellation) +{ + /* Check the parameters */ + Assert_Param(IS_CMP_OP_ALL_PERIPH(CMP_OPx)); + Assert_Param(IS_CMP_OP_IOVC(cancellation)); + + CMP_OPx->OFVCR = cancellation; +} + +/*********************************************************************************************************//** + * @brief Get input offset voltage cancellation value. + * @param CMP_OPx: where CMP_OPx is the selected CMP_OP from the CMP_OP peripherals, x can be 0 or 1. + * @retval The input offset voltage cancellation value. +************************************************************************************************************/ +u32 CMP_OP_GetCancellationVaule(HT_CMP_OP_TypeDef* CMP_OPx) +{ + /* Check the parameters */ + Assert_Param(IS_CMP_OP_ALL_PERIPH(CMP_OPx)); + + return CMP_OPx->OFVCR; +} + +/*********************************************************************************************************//** + * @brief Enable or Disable the specified CMP_OP interrupts. + * @param CMP_OPx: where CMP_OPx is the selected CMP_OP from the CMP_OP peripherals, x can be 0 or 1. + * @param CMP_OP_INT: Specify the CMP_OP interrupt sources that is to be enabled or disabled. + * This parameter can be any combination of the following values: + * - CMP_OP_INT_FALLING: + * - CMP_OP_INT_RISING: + * @param NewState new state of the specified ADC interrupts. + * This parameter can be: ENABLE or DISABLE. + * @retval None +************************************************************************************************************/ +void CMP_OP_IntConfig(HT_CMP_OP_TypeDef* CMP_OPx, u32 CMP_OP_INT, ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_CMP_OP_ALL_PERIPH(CMP_OPx)); + Assert_Param(IS_CMP_OP_INT(CMP_OP_INT)); + Assert_Param(IS_CONTROL_STATUS(NewState)); + + if (NewState != DISABLE) + { + CMP_OPx->CMPIER |= CMP_OP_INT; + } + else + { + CMP_OPx->CMPIER &= ~CMP_OP_INT; + } +} + +/*********************************************************************************************************//** + * @brief Check whether the specified ADC interrupt has occurred. + * @param CMP_OPx: where CMP_OPx is the selected CMP_OP from the CMP_OP peripherals, x can be 0 or 1. + * @param CMP_OP_INT: Specify the interrupt status to check. + * This parameter can be any combination of the following values: + * - CMP_OP_INT_FALLING: + * - CMP_OP_INT_RISING: + * @retval SET or RESET +************************************************************************************************************/ +FlagStatus CMP_OP_GetIntStatus(HT_CMP_OP_TypeDef* CMP_OPx, u32 CMP_OP_INT) +{ + FlagStatus Status; + + /* Check the parameters */ + Assert_Param(IS_CMP_OP_ALL_PERIPH(CMP_OPx)); + Assert_Param(IS_CMP_OP_INT(CMP_OP_INT)); + + if ((CMP_OPx->CMPISR & CMP_OP_INT) != 0x0) + { + Status = SET; + } + else + { + Status = RESET; + } + + return Status; +} + +/*********************************************************************************************************//** + * @brief Check whether the specified CMP_OP flag has been set. + * @param CMP_OPx: where CMP_OPx is the selected CMP_OP from the CMP_OP peripherals, x can be 0 or 1. + * @param CMP_OP_FLAG: Specify the flag to check. + * This parameter can be any combination of the following values: + * - CMP_OP_FLAG_FALLING: + * - CMP_OP_FLAG_RISING: + * @retval SET or RESET +************************************************************************************************************/ +FlagStatus CMP_OP_GetFlagStatus(HT_CMP_OP_TypeDef* CMP_OPx, u32 CMP_OP_FLAG) +{ + FlagStatus Status; + + /* Check the parameters */ + Assert_Param(IS_CMP_OP_ALL_PERIPH(CMP_OPx)); + Assert_Param(IS_CMP_OP_FLAG(CMP_OP_FLAG)); + + if ((CMP_OPx->CMPRSR & CMP_OP_FLAG) != 0x0) + { + Status = SET; + } + else + { + Status = RESET; + } + + return Status; +} + + +/*********************************************************************************************************//** + * @brief Clear the CMP_OPx interrupt pending bits. + * @param CMP_OPx: where CMP_OPx is the selected CMP_OP from the CMP_OP peripherals, x can be 0 or 1. + * @param CMP_OP_INT: specifies the interrupt pending bits to be cleared. + * This parameter can be any combination of the following values: + * - CMP_OP_INT_FALLING: + * - CMP_OP_INT_RISING: + * @retval None +************************************************************************************************************/ +void CMP_OP_ClearIntPendingBit(HT_CMP_OP_TypeDef* CMP_OPx, u32 CMP_OP_INT) +{ + /* Check the parameters */ + Assert_Param(IS_CMP_OP_ALL_PERIPH(CMP_OPx)); + Assert_Param(IS_CMP_OP_INT(CMP_OP_INT)); + + CMP_OPx->CMPICLR = CMP_OP_INT; +} + +/*********************************************************************************************************//** + * @brief Get the output status of CMP_OPx. + * @param CMP_OPx: where CMP_OPx is the selected CMP_OP from the CMP_OP peripherals, x can be 0 or 1. + * @retval SET or RESET +************************************************************************************************************/ +FlagStatus CMP_OP_GetOutputStatus(HT_CMP_OP_TypeDef* CMP_OPx) +{ + /* Check the parameters */ + Assert_Param(IS_CMP_OP_ALL_PERIPH(CMP_OPx)); + + if ((CMP_OPx->OPACR & 0x00000100) != 0x0) + { + return SET; + } + else + { + return RESET; + } +} +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ diff --git a/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/src/ht32f1xxxx_crc.c b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/src/ht32f1xxxx_crc.c new file mode 100644 index 0000000000..6630ae3023 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/src/ht32f1xxxx_crc.c @@ -0,0 +1,190 @@ +/*********************************************************************************************************//** + * @file ht32f1xxxx_crc.c + * @version $Rev:: 2787 $ + * @date $Date:: 2022-11-23 #$ + * @brief This file provides all the CRC firmware functions. + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ + +/* Includes ------------------------------------------------------------------------------------------------*/ +#include "ht32f1xxxx_crc.h" + +/** @addtogroup HT32F1xxxx_Peripheral_Driver HT32F1xxxx Peripheral Driver + * @{ + */ + +/** @defgroup CRC CRC + * @brief CRC driver modules + * @{ + */ + + +/* Global functions ----------------------------------------------------------------------------------------*/ +/** @defgroup CRC_Exported_Functions CRC exported functions + * @{ + */ +/*********************************************************************************************************//** + * @brief Deinitialize the CRC peripheral registers to their default reset values. + * @param HT_CRCn: where CRC is the selected CRC peripheral. + * @retval None + ************************************************************************************************************/ +void CRC_DeInit(HT_CRC_TypeDef* HT_CRCn) +{ + RSTCU_PeripReset_TypeDef RSTCUReset = {{0}}; + + if (HT_CRCn == NULL) // Remove the compiler warning + { + } + + RSTCUReset.Bit.CRC = 1; + RSTCU_PeripReset(RSTCUReset, ENABLE); +} + +/*********************************************************************************************************//** + * @brief Initialize the CRC peripheral according to the specified parameters in the CRC_InitStruct. + * @param HT_CRCn: Selected CRC peripheral. + * @param CRC_InitStruct: pointer to a CRC_InitTypeDef structure. + * @retval None + ************************************************************************************************************/ +void CRC_Init(HT_CRC_TypeDef* HT_CRCn, CRC_InitTypeDef* CRC_InitStruct) +{ + u32 uCRValue; + HT_CRCn->SDR = CRC_InitStruct->uSeed; + switch (CRC_InitStruct->Mode) + { + case CRC_CCITT_POLY: + { + uCRValue = CRC_CCITT_POLY | CRC_NORMAL_WR | CRC_NORMAL_SUM; + break; + } + case CRC_16_POLY: + { + uCRValue = CRC_16_POLY | CRC_BIT_RVS_WR | CRC_BIT_RVS_SUM | CRC_BYTE_RVS_SUM; + break; + } + case CRC_32_POLY: + { + uCRValue = CRC_32_POLY | CRC_BIT_RVS_WR | CRC_BIT_RVS_SUM | CRC_BYTE_RVS_SUM | CRC_CMPL_SUM; + break; + } + case CRC_USER_DEFINE: + default: + { + uCRValue = CRC_InitStruct->uCR; + break; + } + } + + HT_CRCn->CR = uCRValue; +} + +/*********************************************************************************************************//** + * @brief Get the CRC checksum from the given data + * @param HT_CRCn: Selected CRC peripheral. + * @param buffer: pointer to the given data to be calculated + * @param length: data length in byte + * @retval The checksum value + ***********************************************************************************************************/ +u32 CRC_Process(HT_CRC_TypeDef* HT_CRCn, u8 *buffer, u32 length) +{ + while (length--) + { + wb(&HT_CRCn->DR, *buffer++); // byte write + } + + return (HT_CRCn->CSR); +} + +/*********************************************************************************************************//** + * @brief Get the CRC-CCITT checksum from the given data + * @param seed: CRC initial data + * @param buffer: pointer to the given data to be calculated + * @param length: data length in byte + * @retval The checksum value + ************************************************************************************************************/ +u16 CRC_CCITT(u16 seed, u8 *buffer, u32 length) +{ + /* CRC-CCITT poly: 0x1021 */ + HT_CRC->SDR = seed; + HT_CRC->CR = CRC_CCITT_POLY | CRC_NORMAL_WR | CRC_NORMAL_SUM; + + while (length--) + { + wb(&HT_CRC->DR, *buffer++); // byte write + } + + return (u16)(HT_CRC->CSR); +} + +/*********************************************************************************************************//** + * @brief Get the CRC-16 checksum from the given data + * @param seed: CRC initial data + * @param buffer: pointer to the given data to be calculated + * @param length: data length in byte + * @retval The checksum value + ************************************************************************************************************/ +u16 CRC_16(u16 seed, u8 *buffer, u32 length) +{ + /* CRC-16 poly: 0x8005 */ + HT_CRC->SDR = seed; + HT_CRC->CR = CRC_16_POLY | CRC_BIT_RVS_WR | CRC_BIT_RVS_SUM | CRC_BYTE_RVS_SUM; + + while (length--) + { + wb(&HT_CRC->DR, *buffer++); // byte write + } + + return (u16)(HT_CRC->CSR); +} + +/*********************************************************************************************************//** + * @brief Get the CRC-32 checksum from the given data + * @param seed: CRC initial data + * @param buffer: pointer to the given data to be calculated + * @param length: data length in byte + * @retval The checksum value + ************************************************************************************************************/ +u32 CRC_32(u32 seed, u8 *buffer, u32 length) +{ + /* CRC-32 poly: 0x04C11DB7 */ + HT_CRC->SDR = seed; + HT_CRC->CR = CRC_32_POLY | CRC_BIT_RVS_WR | CRC_BIT_RVS_SUM | CRC_BYTE_RVS_SUM | CRC_CMPL_SUM; + + while (length--) + { + wb(&HT_CRC->DR, *buffer++); // byte write + } + + return (HT_CRC->CSR); +} +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ diff --git a/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/src/ht32f1xxxx_ebi.c b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/src/ht32f1xxxx_ebi.c new file mode 100644 index 0000000000..55be3bc8dd --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/src/ht32f1xxxx_ebi.c @@ -0,0 +1,339 @@ +/********************************************************************************************************//** + * @file ht32f1xxxx_ebi.c + * @version $Rev:: 2788 $ + * @date $Date:: 2022-11-24 #$ + * @brief This file provides all the EBI firmware functions. + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ + +/* Includes ------------------------------------------------------------------------------------------------*/ +#include "ht32f1xxxx_ebi.h" + +/** @addtogroup HT32F1xxxx_Peripheral_Driver HT32F1xxxx Peripheral Driver + * @{ + */ + +/** @defgroup EBI EBI + * @brief EBI driver modules + * @{ + */ + + +/* Global functions ----------------------------------------------------------------------------------------*/ +/** @defgroup EBI_Exported_Functions EBI exported functions + * @{ + */ +/*********************************************************************************************************//** + * @brief Deinitializes the EBI peripheral registers to their default reset values. + * @retval None + ************************************************************************************************************/ +void EBI_DeInit(void) +{ + RSTCU_PeripReset_TypeDef RSTCUReset = {{0}}; + + RSTCUReset.Bit.EBI = 1; + RSTCU_PeripReset(RSTCUReset, ENABLE); +} + +/*********************************************************************************************************//** + * @brief Initializes the EBI peripheral according to the specified parameters in the EBI_InitStruct. + * @param EBI_InitStruct: pointer to a EBI_InitTypeDef structure. + * @retval None + ************************************************************************************************************/ +void EBI_Init(EBI_InitTypeDef* EBI_InitStruct) +{ + u32 tmp; + u32 bank = EBI_InitStruct->EBI_Bank; + u32 offset = EBI_InitStruct->EBI_Bank * 0x10; + + /* Check the parameters */ + Assert_Param(IS_EBI_BANK(EBI_InitStruct->EBI_Bank)); + Assert_Param(IS_EBI_MODE(EBI_InitStruct->EBI_Mode)); + #if (LIBCFG_EBI_BYTELAND_ASYNCREADY) + Assert_Param(IS_EBI_BYTELANE(EBI_InitStruct->EBI_ByteLane)); + Assert_Param(IS_EBI_ARDY(EBI_InitStruct->EBI_AsynchronousReady)); + Assert_Param(IS_EBI_ARDY_TIMEOUT(EBI_InitStruct->EBI_ARDYTimeOut)); + Assert_Param(IS_EBI_BL_POLARITY(EBI_InitStruct->EBI_ByteLanePolarity)); + Assert_Param(IS_EBI_ARDY_POLARITY(EBI_InitStruct->EBI_ReadySignalPolarity)); + #endif + Assert_Param(IS_EBI_IDLECYCLE(EBI_InitStruct->EBI_IdleCycle)); + Assert_Param(IS_EBI_CS_POLARITY(EBI_InitStruct->EBI_ChipSelectPolarity)); + Assert_Param(IS_EBI_ALE_POLARITY(EBI_InitStruct->EBI_AddressLatchPolarity)); + Assert_Param(IS_EBI_WE_POLARITY(EBI_InitStruct->EBI_WriteEnablePolarity)); + Assert_Param(IS_EBI_RE_POLARITY(EBI_InitStruct->EBI_ReadEnablePolarity)); + Assert_Param(IS_EBI_IDLE_CYCLE_TIME(EBI_InitStruct->EBI_IdleCycleTime)); + Assert_Param(IS_EBI_ADDRESS_SETUP_TIME(EBI_InitStruct->EBI_AddressSetupTime)); + Assert_Param(IS_EBI_ADDRESS_HOLD_TIME(EBI_InitStruct->EBI_AddressHoldTime)); + Assert_Param(IS_EBI_WRITE_SETUP_TIME(EBI_InitStruct->EBI_WriteSetupTime)); + Assert_Param(IS_EBI_WRITE_STROBE_TIME(EBI_InitStruct->EBI_WriteStrobeTime)); + Assert_Param(IS_EBI_WRITE_HOLD_TIME(EBI_InitStruct->EBI_WriteHoldTime)); + Assert_Param(IS_EBI_READ_SETUP_TIME(EBI_InitStruct->EBI_ReadSetupTime)); + Assert_Param(IS_EBI_READ_STROBE_TIME(EBI_InitStruct->EBI_ReadStrobeTime)); + #if !(LIBCFG_EBI_V01) + Assert_Param(IS_EBI_PAGE_MODE(EBI_InitStruct->EBI_PageMode)); + Assert_Param(IS_EBI_PAGE_LENGTH(EBI_InitStruct->EBI_PageLength)); + Assert_Param(IS_EBI_PAGE_HIT_MODE(EBI_InitStruct->EBI_PageHitMode)); + Assert_Param(IS_EBI_PAGE_ACCESS_TIME(EBI_InitStruct->EBI_PageAccessTime)); + Assert_Param(IS_EBI_PAGE_OPEN_TIME(EBI_InitStruct->EBI_PageOpenTime)); + #endif + + + *((u32 *)((u32)&HT_EBI->ATR0 + offset)) = EBI_InitStruct->EBI_AddressSetupTime | + (EBI_InitStruct->EBI_AddressHoldTime << 8); +#if (LIBCFG_EBI_V01) +*((u32 *)((u32)&HT_EBI->RTR0 + offset)) = EBI_InitStruct->EBI_ReadSetupTime | + (EBI_InitStruct->EBI_ReadStrobeTime << 8) | + (EBI_InitStruct->EBI_ReadHoldTime << 16); +#else +*((u32 *)((u32)&HT_EBI->RTR0 + offset)) = EBI_InitStruct->EBI_ReadSetupTime | + (EBI_InitStruct->EBI_ReadStrobeTime << 8) | + (EBI_InitStruct->EBI_ReadHoldTime << 16) | + EBI_InitStruct->EBI_PageMode; +#endif + *((u32 *)((u32)&HT_EBI->WTR0 + offset)) = EBI_InitStruct->EBI_WriteSetupTime | + (EBI_InitStruct->EBI_WriteStrobeTime << 8) | + (EBI_InitStruct->EBI_WriteHoldTime << 16); + *((u32 *)((u32)&HT_EBI->PR0 + offset)) = EBI_InitStruct->EBI_ChipSelectPolarity | + (EBI_InitStruct->EBI_ReadEnablePolarity << 1) | + (EBI_InitStruct->EBI_AddressLatchPolarity << 3) | + #if (LIBCFG_EBI_BYTELAND_ASYNCREADY) + (EBI_InitStruct->EBI_ReadySignalPolarity << 4) | + (EBI_InitStruct->EBI_ByteLanePolarity << 5) | + #endif + (EBI_InitStruct->EBI_WriteEnablePolarity << 2); + + + /*------------------------- EBI Control Register Configuration -------------------------------------------*/ + tmp = (3 << (bank * 2)) | (0x00001000 << bank) | + (0x00010000 << (bank * 2)) | (0x00020000 << (bank * 2)) | + (0x01000000 << bank); + tmp = HT_EBI->CR & (~tmp); + HT_EBI->CR = (EBI_InitStruct->EBI_Mode << (bank * 2)) | + (EBI_InitStruct->EBI_IdleCycle << bank) | + #if (LIBCFG_EBI_BYTELAND_ASYNCREADY) + (EBI_InitStruct->EBI_AsynchronousReady << (bank * 2)) | + (EBI_InitStruct->EBI_ARDYTimeOut << (bank * 2)) | + (EBI_InitStruct->EBI_ByteLane << bank) | + #endif + (EBI_InitStruct->EBI_IdleCycleTime << 28) | tmp; + + #if !(LIBCFG_EBI_V01) + if (EBI_InitStruct->EBI_PageMode) + { + Assert_Param(IS_EBI_PAGE_LENGTH(EBI_InitStruct->EBI_PageLength)); + Assert_Param(IS_EBI_PAGE_HIT_MODE(EBI_InitStruct->EBI_PageHitMode)); + Assert_Param(IS_EBI_PAGE_ACCESS_TIME(EBI_InitStruct->EBI_PageAccessTime)); + Assert_Param(IS_EBI_PAGE_OPEN_TIME(EBI_InitStruct->EBI_PageOpenTime)); + + HT_EBI->PCR = EBI_InitStruct->EBI_PageLength | EBI_InitStruct->EBI_PageHitMode | + (EBI_InitStruct->EBI_PageAccessTime << 8) | (EBI_InitStruct->EBI_PageOpenTime << 16); + } + #endif +} + +/*********************************************************************************************************//** + * @brief Fills each EBI_InitStruct member with its default value. + * @param EBI_InitStruct: pointer to an EBI_InitTypeDef structure. + * @retval None + ************************************************************************************************************/ +void EBI_StructInit(EBI_InitTypeDef* EBI_InitStruct) +{ + /* Initialize the EBI structure parameters values */ + EBI_InitStruct->EBI_Bank = EBI_BANK_0; + EBI_InitStruct->EBI_Mode = EBI_MODE_D8A8; + #if (LIBCFG_EBI_BYTELAND_ASYNCREADY) + EBI_InitStruct->EBI_ByteLane = EBI_BYTELANE_DISABLE; + EBI_InitStruct->EBI_AsynchronousReady = EBI_ASYNCHRONOUSREADY_DISABLE; + EBI_InitStruct->EBI_ARDYTimeOut = EBI_ARDYTIMEOUT_DISABLE; + EBI_InitStruct->EBI_ByteLanePolarity = EBI_BYTELANEPOLARITY_LOW; + EBI_InitStruct->EBI_ReadySignalPolarity = EBI_READYSIGNALPOLARITY_LOW; + #endif + EBI_InitStruct->EBI_IdleCycle = EBI_IDLECYCLE_DISABLE; + EBI_InitStruct->EBI_ChipSelectPolarity = EBI_CHIPSELECTPOLARITY_LOW; + EBI_InitStruct->EBI_AddressLatchPolarity = EBI_ADDRESSLATCHPOLARITY_LOW; + EBI_InitStruct->EBI_WriteEnablePolarity = EBI_WRITEENABLEPOLARITY_LOW; + EBI_InitStruct->EBI_ReadEnablePolarity = EBI_READENABLEPOLARITY_LOW; + EBI_InitStruct->EBI_IdleCycleTime = 0xF; + EBI_InitStruct->EBI_AddressSetupTime = 0xF; + EBI_InitStruct->EBI_AddressHoldTime = 0xF; + EBI_InitStruct->EBI_WriteSetupTime = 0xF; + EBI_InitStruct->EBI_WriteStrobeTime = 0x3F; + EBI_InitStruct->EBI_WriteHoldTime = 0xF; + EBI_InitStruct->EBI_ReadSetupTime = 0xF; + EBI_InitStruct->EBI_ReadStrobeTime = 0x3F; + EBI_InitStruct->EBI_ReadHoldTime = 0xF; + #if !(LIBCFG_EBI_V01) + EBI_InitStruct->EBI_PageMode = EBI_PAGEMODE_DISABLE; + EBI_InitStruct->EBI_PageLength = EBI_PAGELENGTH_4; + EBI_InitStruct->EBI_PageHitMode = EBI_PAGEHITMODE_ADDINC; + EBI_InitStruct->EBI_PageAccessTime = 0xF; + EBI_InitStruct->EBI_PageOpenTime = 0xFF; + #endif +} + +/*********************************************************************************************************//** + * @brief Enable or Disable the EBI peripheral. + * @param EBI_Bank: EBI Bank. + * This parameter can be one of the following values: + * @arg EBI_BANK_0 : EBI Bank 0 + * @arg EBI_BANK_1 : EBI Bank 1 + * @arg EBI_BANK_2 : EBI Bank 2 + * @arg EBI_BANK_3 : EBI Bank 3 + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void EBI_Cmd(u32 EBI_Bank, ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_EBI_BANK(EBI_Bank)); + Assert_Param(IS_CONTROL_STATUS(NewState)); + + if (NewState != DISABLE) + { + HT_EBI->CR |= (0x100 << EBI_Bank); + } + else + { + HT_EBI->CR &= ~(0x100 << EBI_Bank); + } +} + +#if !(LIBCFG_EBI_V01) +/*********************************************************************************************************//** + * @brief Enable or Disable the specified EBI interrupt. + * @param EBI_Int: specify the EBI interrupt source to be enabled or disabled. + * This parameter can be any combination of the following values: + * @arg EBI_INT_TOUT : ARDY time out interrupt + * @arg EBI_INT_ACCDIS : Access disabled bank interrupt + * @arg EBI_INT_ACCRES : Access under software reset interrupt + * @arg EBI_INT_ALL : All EBI interrupt + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ***********************************************************************************************************/ +void EBI_IntConfig(u32 EBI_Int, ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_EBI_INT(EBI_Int)); + Assert_Param(IS_CONTROL_STATUS(NewState)); + + if (NewState != DISABLE) + { + HT_EBI->IEN |= EBI_Int; + } + else + { + HT_EBI->IEN &= (u32)~EBI_Int; + } +} + +/*********************************************************************************************************//** + * @brief Check whether the specified EBI interrupt has been occurred. + * @param EBI_IntFlag: specify the EBI interrupt to be check. + * This parameter can be one of the following values: + * @arg EBI_INT_TOUT : ARDY time out interrupt + * @arg EBI_INT_ACCERR : Access disabled bank or under software reset interrupt + * @retval SET or RESET + ***********************************************************************************************************/ +FlagStatus EBI_GetIntStatus(u32 EBI_IntFlag) +{ + u32 status = 0; + FlagStatus bitstatus = RESET; + + /* Check the parameters */ + Assert_Param(IS_EBI_INT_FLAG(EBI_IntFlag)); + + status = HT_EBI->IF; + + if ((status & EBI_IntFlag) != (u32)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + return bitstatus; +} + +/*********************************************************************************************************//** + * @brief Clear the specified EBI interrupt flag. + * @param EBI_IntFlag: specify the interrupt flag that is to be cleared. + * This parameter can be any combination of the following values: + * @arg EBI_INT_TOUT : ARDY time out interrupt flag + * @arg EBI_INT_ACCERR : Access disabled bank or under software reset interrupt flag + * @retval None + ***********************************************************************************************************/ +void EBI_ClearIntFlag(u32 EBI_IntFlag) +{ + /* Check the parameters */ + Assert_Param(IS_EBI_INT_FLAG(EBI_IntFlag)); + + HT_EBI->IFC = EBI_IntFlag; +} +#endif + +/*********************************************************************************************************//** + * @brief Check whether the specified EBI busy flag has been set. + * @retval SET or RESET + ************************************************************************************************************/ +FlagStatus EBI_GetBusyStatus(void) +{ + if (HT_EBI->SR & 0x1) + { + return SET; + } + else + { + return RESET; + } +} + +#if (LIBCFG_EBI_BYTELAND_ASYNCREADY) +/*********************************************************************************************************//** + * @brief Check whether the specified EBI ARDY flag has been set. + * @retval SET or RESET + ************************************************************************************************************/ +FlagStatus EBI_GetARDYStatus(void) +{ + if (HT_EBI->SR & 0x10) + { + return SET; + } + else + { + return RESET; + } +} +#endif +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ diff --git a/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/src/ht32f1xxxx_exti.c b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/src/ht32f1xxxx_exti.c new file mode 100644 index 0000000000..de263a613a --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/src/ht32f1xxxx_exti.c @@ -0,0 +1,516 @@ +/*********************************************************************************************************//** + * @file ht32f1xxxx_exti.c + * @version $Rev:: 2873 $ + * @date $Date:: 2023-02-23 #$ + * @brief This file provides all the EXTI firmware functions. + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ + +/* Includes ------------------------------------------------------------------------------------------------*/ +#include "ht32f1xxxx_exti.h" + +/** @addtogroup HT32F1xxxx_Peripheral_Driver HT32F1xxxx Peripheral Driver + * @{ + */ + +/** @defgroup EXTI EXTI + * @brief EXTI driver modules + * @{ + */ + + +/* Private constants ---------------------------------------------------------------------------------------*/ +/** @defgroup EXTI_Private_Define EXTI private definitions + * @{ + */ +/* EXTI EVWUPIEN mask */ +#define WAKUPCR_EVWUPIEN_SET ((u32)0x80000000) +#define WAKUPCR_EVWUPIEN_RESET ((u32)0x7FFFFFFF) + +const IRQn_Type gEXTIn_IRQn[16] = { + EXTI0_IRQn, EXTI1_IRQn, EXTI2_IRQn, EXTI3_IRQn, + EXTI4_IRQn, EXTI5_IRQn, EXTI6_IRQn, EXTI7_IRQn, + EXTI8_IRQn, EXTI9_IRQn, EXTI10_IRQn, EXTI11_IRQn, + EXTI12_IRQn, EXTI13_IRQn, EXTI14_IRQn, EXTI15_IRQn, +}; + +/** + * @} + */ + +/* Global functions ----------------------------------------------------------------------------------------*/ +/** @defgroup EXTI_Exported_Functions EXTI exported functions + * @{ + */ +/*********************************************************************************************************//** + * @brief Deinitialize the EXTI peripheral registers. + * @param EXTI_Channel: can be 0, 1 to 15 to select the EXTI Channel. + * This parameter can be one of the following values: + * @arg EXTI_CHANNEL_0 + * @arg EXTI_CHANNEL_1 + * @arg EXTI_CHANNEL_2 + * @arg EXTI_CHANNEL_3 + * @arg EXTI_CHANNEL_4 + * @arg EXTI_CHANNEL_5 + * @arg EXTI_CHANNEL_6 + * @arg EXTI_CHANNEL_7 + * @arg EXTI_CHANNEL_8 + * @arg EXTI_CHANNEL_9 + * @arg EXTI_CHANNEL_10 + * @arg EXTI_CHANNEL_11 + * @arg EXTI_CHANNEL_12 + * @arg EXTI_CHANNEL_13 + * @arg EXTI_CHANNEL_14 + * @arg EXTI_CHANNEL_15 + * @retval None + ************************************************************************************************************/ +void EXTI_DeInit(u32 EXTI_Channel) +{ + u32 tmp; + + /* Check the parameters */ + Assert_Param(IS_EXTI_CHANNEL(EXTI_Channel)); + + tmp = 1 << EXTI_Channel; + + *((u32 *) HT_EXTI + EXTI_Channel) = 0x0; + HT_EXTI->CR &= (~tmp); + HT_EXTI->EDGEFLGR = tmp; + HT_EXTI->EDGESR = tmp; + HT_EXTI->SSCR &= (~tmp); + HT_EXTI->WAKUPCR &= (~tmp); + HT_EXTI->WAKUPPOLR &= (~tmp); + HT_EXTI->WAKUPFLG = tmp; +} + +/*********************************************************************************************************//** + * @brief Initialize the EXTI peripheral. + * @param EXTI_InitStruct: pointer to a EXTI_InitTypeDef structure. + * @retval None + ************************************************************************************************************/ +void EXTI_Init(EXTI_InitTypeDef* EXTI_InitStruct) +{ + u32 regval; + + /* Check the parameters */ + Assert_Param(IS_EXTI_CHANNEL(EXTI_InitStruct->EXTI_Channel)); + Assert_Param(IS_EXTI_DEBOUNCE_TYPE(EXTI_InitStruct->EXTI_Debounce)); + Assert_Param(IS_EXTI_DEBOUNCE_SIZE(EXTI_InitStruct->EXTI_DebounceCnt)); + Assert_Param(IS_EXTI_INT_TYPE(EXTI_InitStruct->EXTI_IntType)); + + /* Set EXTI interrupt configuration */ + regval = (EXTI_InitStruct->EXTI_Debounce << 31) | (EXTI_InitStruct->EXTI_IntType << 28) | (EXTI_InitStruct->EXTI_DebounceCnt); + *((u32 *) HT_EXTI + EXTI_InitStruct->EXTI_Channel) = regval; +} + +/*********************************************************************************************************//** + * @brief Enable or Disable the specified EXTI channelx interrupts. + * @param EXTI_Channel: specify the EXTI channel. + * This parameter can be one of the following values: + * @arg EXTI_CHANNEL_0 + * @arg EXTI_CHANNEL_1 + * @arg EXTI_CHANNEL_2 + * @arg EXTI_CHANNEL_3 + * @arg EXTI_CHANNEL_4 + * @arg EXTI_CHANNEL_5 + * @arg EXTI_CHANNEL_6 + * @arg EXTI_CHANNEL_7 + * @arg EXTI_CHANNEL_8 + * @arg EXTI_CHANNEL_9 + * @arg EXTI_CHANNEL_10 + * @arg EXTI_CHANNEL_11 + * @arg EXTI_CHANNEL_12 + * @arg EXTI_CHANNEL_13 + * @arg EXTI_CHANNEL_14 + * @arg EXTI_CHANNEL_15 + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void EXTI_IntConfig(u32 EXTI_Channel, ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_EXTI_CHANNEL(EXTI_Channel)); + Assert_Param(IS_CONTROL_STATUS(NewState)); + + /* Configure EXTI interrupt */ + if (NewState == ENABLE) + { + HT_EXTI->CR |= (1 << EXTI_Channel); + } + else + { + HT_EXTI->CR &= ~(1 << EXTI_Channel); + } +} + +/*********************************************************************************************************//** + * @brief Configure the EXTI channelx event wakeup function. + * @param EXTI_Channel: specify the EXTI channel. + * This parameter can be one of the following values: + * @arg EXTI_CHANNEL_0 + * @arg EXTI_CHANNEL_1 + * @arg EXTI_CHANNEL_2 + * @arg EXTI_CHANNEL_3 + * @arg EXTI_CHANNEL_4 + * @arg EXTI_CHANNEL_5 + * @arg EXTI_CHANNEL_6 + * @arg EXTI_CHANNEL_7 + * @arg EXTI_CHANNEL_8 + * @arg EXTI_CHANNEL_9 + * @arg EXTI_CHANNEL_10 + * @arg EXTI_CHANNEL_11 + * @arg EXTI_CHANNEL_12 + * @arg EXTI_CHANNEL_13 + * @arg EXTI_CHANNEL_14 + * @arg EXTI_CHANNEL_15 + * @param EXTI_WakeUpType: determines the type of signal to trigger EXTI interrupt. + * This parameter can be one of the following values: + * @arg EXTI_WAKEUP_HIGH_LEVEL + * @arg EXTI_WAKEUP_LOW_LEVEL + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void EXTI_WakeupEventConfig(u32 EXTI_Channel, u8 EXTI_WakeUpType, ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_EXTI_CHANNEL(EXTI_Channel)); + Assert_Param(IS_EXTI_WAKEUP_TYPE(EXTI_WakeUpType)); + Assert_Param(IS_CONTROL_STATUS(NewState)); + + if (NewState == ENABLE) + { + if (EXTI_WakeUpType == EXTI_WAKEUP_HIGH_LEVEL) + { + HT_EXTI->WAKUPPOLR &= ~(1 << EXTI_Channel); + } + else + { + HT_EXTI->WAKUPPOLR |= (1 << EXTI_Channel); + } + + HT_EXTI->WAKUPCR |= (1 << EXTI_Channel); + } + else + { + HT_EXTI->WAKUPCR &= ~(1 << EXTI_Channel); + } +} + +/*********************************************************************************************************//** + * @brief Enable or Disable the EXTI channelx event wakeup interrupt. + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void EXTI_WakeupEventIntConfig(ControlStatus NewState) +{ + if (NewState == ENABLE) + { + /* Set EVWUPIEN bit */ + HT_EXTI->WAKUPCR |= WAKUPCR_EVWUPIEN_SET; + } + else + { + /* Clear EVWUPIEN bit */ + HT_EXTI->WAKUPCR &= WAKUPCR_EVWUPIEN_RESET; + } +} + +/*********************************************************************************************************//** + * @brief Clear the specified EXTI channelx edge flag. + * @param EXTI_Channel: specify the EXTI channel. + * This parameter can be one of the following values: + * @arg EXTI_CHANNEL_0 + * @arg EXTI_CHANNEL_1 + * @arg EXTI_CHANNEL_2 + * @arg EXTI_CHANNEL_3 + * @arg EXTI_CHANNEL_4 + * @arg EXTI_CHANNEL_5 + * @arg EXTI_CHANNEL_6 + * @arg EXTI_CHANNEL_7 + * @arg EXTI_CHANNEL_8 + * @arg EXTI_CHANNEL_9 + * @arg EXTI_CHANNEL_10 + * @arg EXTI_CHANNEL_11 + * @arg EXTI_CHANNEL_12 + * @arg EXTI_CHANNEL_13 + * @arg EXTI_CHANNEL_14 + * @arg EXTI_CHANNEL_15 + * @retval None + ************************************************************************************************************/ +void EXTI_ClearEdgeFlag(u32 EXTI_Channel) +{ + u32 tmp; + + /* Check the parameters */ + Assert_Param(IS_EXTI_CHANNEL(EXTI_Channel)); + + tmp = 1 << EXTI_Channel; + + /* Write 1 to clear both edge detection flag */ + HT_EXTI->EDGEFLGR = tmp; + /* Write 1 to clear positive edge detection flag */ + HT_EXTI->EDGESR = tmp; +} + +/*********************************************************************************************************//** + * @brief Clear the specified EXTI channelx wakeup flag. + * @param EXTI_Channel: specify the EXTI channel. + * This parameter can be one of the following values: + * @arg EXTI_CHANNEL_0 + * @arg EXTI_CHANNEL_1 + * @arg EXTI_CHANNEL_2 + * @arg EXTI_CHANNEL_3 + * @arg EXTI_CHANNEL_4 + * @arg EXTI_CHANNEL_5 + * @arg EXTI_CHANNEL_6 + * @arg EXTI_CHANNEL_7 + * @arg EXTI_CHANNEL_8 + * @arg EXTI_CHANNEL_9 + * @arg EXTI_CHANNEL_10 + * @arg EXTI_CHANNEL_11 + * @arg EXTI_CHANNEL_12 + * @arg EXTI_CHANNEL_13 + * @arg EXTI_CHANNEL_14 + * @arg EXTI_CHANNEL_15 + * @retval None + ************************************************************************************************************/ +void EXTI_ClearWakeupFlag(u32 EXTI_Channel) +{ + /* Check the parameters */ + Assert_Param(IS_EXTI_CHANNEL(EXTI_Channel)); + + /* Write 1 to clear wake up flag */ + HT_EXTI->WAKUPFLG = 1 << EXTI_Channel; + + /*--------------------------------------------------------------------------------------------------------*/ + /* DSB instruction is added in this function to ensure the write operation which is for clearing interrupt*/ + /* flag is actually completed before exiting ISR. It prevents the NVIC from detecting the interrupt again */ + /* since the write register operation may be pended in the internal write buffer of Cortex-Mx when program*/ + /* has exited interrupt routine. This DSB instruction may be masked if this function is called in the */ + /* beginning of ISR and there are still some instructions before exiting ISR. */ + /*--------------------------------------------------------------------------------------------------------*/ + __DSB(); +} + +/*********************************************************************************************************//** + * @brief Get the specified EXTI channelx edge flag. + * @param EXTI_Channel: specify the EXTI channel. + * This parameter can be one of the following values: + * @arg EXTI_CHANNEL_0 + * @arg EXTI_CHANNEL_1 + * @arg EXTI_CHANNEL_2 + * @arg EXTI_CHANNEL_3 + * @arg EXTI_CHANNEL_4 + * @arg EXTI_CHANNEL_5 + * @arg EXTI_CHANNEL_6 + * @arg EXTI_CHANNEL_7 + * @arg EXTI_CHANNEL_8 + * @arg EXTI_CHANNEL_9 + * @arg EXTI_CHANNEL_10 + * @arg EXTI_CHANNEL_11 + * @arg EXTI_CHANNEL_12 + * @arg EXTI_CHANNEL_13 + * @arg EXTI_CHANNEL_14 + * @arg EXTI_CHANNEL_15 + * @retval SET or RESET + ************************************************************************************************************/ +FlagStatus EXTI_GetEdgeFlag(u32 EXTI_Channel) +{ + /* Check the parameters */ + Assert_Param(IS_EXTI_CHANNEL(EXTI_Channel)); + + return ((HT_EXTI->EDGEFLGR & (1UL << EXTI_Channel)) ? SET : RESET); +} + +/*********************************************************************************************************//** + * @brief Get the specified EXTI channelx edge status. + * @param EXTI_Channel: specify the EXTI channel. + * This parameter can be one of the following values: + * @arg EXTI_CHANNEL_0 + * @arg EXTI_CHANNEL_1 + * @arg EXTI_CHANNEL_2 + * @arg EXTI_CHANNEL_3 + * @arg EXTI_CHANNEL_4 + * @arg EXTI_CHANNEL_5 + * @arg EXTI_CHANNEL_6 + * @arg EXTI_CHANNEL_7 + * @arg EXTI_CHANNEL_8 + * @arg EXTI_CHANNEL_9 + * @arg EXTI_CHANNEL_10 + * @arg EXTI_CHANNEL_11 + * @arg EXTI_CHANNEL_12 + * @arg EXTI_CHANNEL_13 + * @arg EXTI_CHANNEL_14 + * @arg EXTI_CHANNEL_15 + * @param EXTI_Edge: can be status of edge that user want to monitor. + * This parameter can be one of the following values: + * @arg EXTI_EDGE_POSITIVE + * @arg EXTI_EDGE_NEGATIVE + * @retval SET or RESET + ************************************************************************************************************/ +FlagStatus EXTI_GetEdgeStatus(u32 EXTI_Channel, u32 EXTI_Edge) +{ + /* Check the parameters */ + Assert_Param(IS_EXTI_CHANNEL(EXTI_Channel)); + Assert_Param(IS_EXTI_EDGE(EXTI_Edge)); + + if (HT_EXTI->EDGEFLGR & (1UL << EXTI_Channel)) + { + if (((HT_EXTI->EDGESR >> EXTI_Channel) & 1UL) ^ EXTI_Edge) + { + return SET; + } + else + { + return RESET; + } + } + else + { + return RESET; + } +} + +/*********************************************************************************************************//** + * @brief Get the specified EXTI channelx wakeup flag. + * @param EXTI_Channel: specify the EXTI channel. + * This parameter can be one of the following values: + * @arg EXTI_CHANNEL_0 + * @arg EXTI_CHANNEL_1 + * @arg EXTI_CHANNEL_2 + * @arg EXTI_CHANNEL_3 + * @arg EXTI_CHANNEL_4 + * @arg EXTI_CHANNEL_5 + * @arg EXTI_CHANNEL_6 + * @arg EXTI_CHANNEL_7 + * @arg EXTI_CHANNEL_8 + * @arg EXTI_CHANNEL_9 + * @arg EXTI_CHANNEL_10 + * @arg EXTI_CHANNEL_11 + * @arg EXTI_CHANNEL_12 + * @arg EXTI_CHANNEL_13 + * @arg EXTI_CHANNEL_14 + * @arg EXTI_CHANNEL_15 + * @retval SET or RESET + ************************************************************************************************************/ +FlagStatus EXTI_GetWakeupFlagStatus(u32 EXTI_Channel) +{ + /* Check the parameters */ + Assert_Param(IS_EXTI_CHANNEL(EXTI_Channel)); + + if (HT_EXTI->WAKUPFLG & (1 << EXTI_Channel)) + { + return SET; + } + else + { + return RESET; + } +} + +/*********************************************************************************************************//** + * @brief Activate or Deactivate an EXTI channelx interrupt by software. + * @param EXTI_Channel: specify the EXTI channel. + * This parameter can be one of the following values: + * @arg EXTI_CHANNEL_0 + * @arg EXTI_CHANNEL_1 + * @arg EXTI_CHANNEL_2 + * @arg EXTI_CHANNEL_3 + * @arg EXTI_CHANNEL_4 + * @arg EXTI_CHANNEL_5 + * @arg EXTI_CHANNEL_6 + * @arg EXTI_CHANNEL_7 + * @arg EXTI_CHANNEL_8 + * @arg EXTI_CHANNEL_9 + * @arg EXTI_CHANNEL_10 + * @arg EXTI_CHANNEL_11 + * @arg EXTI_CHANNEL_12 + * @arg EXTI_CHANNEL_13 + * @arg EXTI_CHANNEL_14 + * @arg EXTI_CHANNEL_15 + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void EXTI_SWIntCmd(u32 EXTI_Channel, ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_EXTI_CHANNEL(EXTI_Channel)); + Assert_Param(IS_CONTROL_STATUS(NewState)); + + if (NewState == ENABLE) + { + HT_EXTI->SSCR = 1 << EXTI_Channel; + } + else + { + HT_EXTI->SSCR &= ~(1 << EXTI_Channel); + } +} + +/*********************************************************************************************************//** + * @brief Get the specified EXTI channelx software command register bit. + * @param EXTI_Channel: specify the EXTI channel. + * This parameter can be one of the following values: + * @arg EXTI_CHANNEL_0 + * @arg EXTI_CHANNEL_1 + * @arg EXTI_CHANNEL_2 + * @arg EXTI_CHANNEL_3 + * @arg EXTI_CHANNEL_4 + * @arg EXTI_CHANNEL_5 + * @arg EXTI_CHANNEL_6 + * @arg EXTI_CHANNEL_7 + * @arg EXTI_CHANNEL_8 + * @arg EXTI_CHANNEL_9 + * @arg EXTI_CHANNEL_10 + * @arg EXTI_CHANNEL_11 + * @arg EXTI_CHANNEL_12 + * @arg EXTI_CHANNEL_13 + * @arg EXTI_CHANNEL_14 + * @arg EXTI_CHANNEL_15 + * @retval SET or RESET + ************************************************************************************************************/ +FlagStatus EXTI_GetSWCmdStatus(u32 EXTI_Channel) +{ + /* Check the parameters */ + Assert_Param(IS_EXTI_CHANNEL(EXTI_Channel)); + + if (HT_EXTI->SSCR & (1 << EXTI_Channel)) + { + return SET; + } + else + { + return RESET; + } +} +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ diff --git a/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/src/ht32f1xxxx_flash.c b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/src/ht32f1xxxx_flash.c new file mode 100644 index 0000000000..301920da1d --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/src/ht32f1xxxx_flash.c @@ -0,0 +1,603 @@ +/*********************************************************************************************************//** + * @file ht32f1xxxx_flash.c + * @version $Rev:: 2972 $ + * @date $Date:: 2023-10-28 #$ + * @brief This file provides all the FLASH firmware functions. + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ + +/* Includes ------------------------------------------------------------------------------------------------*/ +#include "ht32f1xxxx_flash.h" + +/** @addtogroup HT32F1xxxx_Peripheral_Driver HT32F1xxxx Peripheral Driver + * @{ + */ + +/** @defgroup FLASH FLASH + * @brief FLASH driver modules + * @{ + */ + + +/* Private constants ---------------------------------------------------------------------------------------*/ +/** @defgroup FLASH_Private_Define FLASH private definitions + * @{ + */ + +/* Delay definition */ +#define FLASH_TIMEOUT (0x000FFFFF) + +/* FLASH OCMR */ +#define FLASH_CMD_STADNBY (0x00000000) +#define FLASH_CMD_PROGRAM (0x00000004) +#define FLASH_CMD_PAGEERASE (0x00000008) +#define FLASH_CMD_MASSERASE (0x0000000A) + +/* FLASH OPCR */ +#define FLASH_READY (0x6UL << 1) +#define FLASH_SEND_MAIN (0x00000014) + +/* FLASH CFCR */ +#define CFCR_WAIT_MASK (0xFFFFFFF8) + +#define FLASH_PREFETCHBUF_ON (0x00000010) +#define FLASH_PREFETCHBUF_OFF (0xFFFFFFEF) + +#define FLASH_BRANCHCACHE_ON (0x00001000) +#define FLASH_BRANCHCACHE_OFF (0xFFFFEFFF) + +#define FLASH_DCODECACHE_ON (0xFFFFFF7F) +#define FLASH_DCODECACHE_OFF (0x00000080) + +#define FLASH_CFCR_MASK (0xFFFFEFE8) +#define FLASH_PREFETCHBUF_AND_BRANCHCACHE_ON (0x00001010) +#define FLASH_PREFETCHBUF_AND_BRANCHCACHE_OFF (0xFFFFEFEF) + +#if (LIBCFG_FLASH_HALFCYCYLE) +#define FLASH_HALFCYCLE_ON (0x00008000) +#define FLASH_HALFCYCLE_OFF (0xFFFF7FFF) +#endif +#if (LIBCFG_FLASH_ZWPWESAVING) +#define FLASH_ZWPWRSAVING_ON (0x00010000) +#define FLASH_ZWPWRSAVING_OFF (0xFFFEFFFF) +#endif +/** + * @} + */ + +/* Private macro -------------------------------------------------------------------------------------------*/ +/** @defgroup FLASH_Private_Macro FLASH private macros + * @{ + */ + +/** + * @brief Check parameter of the FLASH wait state. + */ + +#if (LIBCFG_FMC_WAIT_STATE_3) +#define IS_WAIT_STATE3(x) (x == FLASH_WAITSTATE_3) +#else +#define IS_WAIT_STATE3(x) (0) +#endif + +#define IS_FLASH_WAITSTATE(WAIT) ((WAIT == FLASH_WAITSTATE_0) || \ + (WAIT == FLASH_WAITSTATE_1) || \ + (WAIT == FLASH_WAITSTATE_2) || \ + (IS_WAIT_STATE3(WAIT))) + +/** + * @brief Check parameter of the FLASH vector mapping. + */ +#define IS_FLASH_VECTOR_MODE(MODE) ((MODE == FLASH_BOOT_LOADER) || \ + (MODE == FLASH_BOOT_SRAM) || \ + (MODE == FLASH_BOOT_MAIN)) +/** + * @brief Check parameter of the FLASH address. + */ +#define IS_FLASH_ADDRESS(ADDRESS) (ADDRESS < 0x20000000) /* Code 0.5GB Area */ + +/** + * @brief Check parameter of the FLASH interrupt status. + */ +#define IS_FLASH_WC_FLAG(FLAG) ((FLAG & 0x0000001F) != 0) + +/** + * @brief Check parameter of the FLASH interrupt flag. + */ +#define IS_FLASH_FLAG(FLAG) ((FLAG & 0x0003001F) != 0) + +/** + * @brief Check parameter of the FLASH interrupt. + */ +#define IS_FLASH_INT(IT) ((IT & 0x0000001F) != 0) + +/** + * @} + */ + +/* Global functions ----------------------------------------------------------------------------------------*/ +/** @defgroup FLASH_Exported_Functions FLASH exported functions + * @{ + */ +/*********************************************************************************************************//** + * @brief Configure the FLASH wait state. + * @param FLASH_WAITSTATE_n: Setting of FLASH wait state. + * This parameter can be one of the following values: + * @arg \ref FLASH_WAITSTATE_0 : zero wait state + * @arg \ref FLASH_WAITSTATE_1 : one wait state + * @arg \ref FLASH_WAITSTATE_2 : two wait state + * @arg \ref FLASH_WAITSTATE_3 : three wait state (For HT32F1xxxx only) + * @retval None + ************************************************************************************************************/ +void FLASH_SetWaitState(u32 FLASH_WAITSTATE_n) +{ + u32 uCFCR; + /* Check the parameters */ + Assert_Param(IS_FLASH_WAITSTATE(FLASH_WAITSTATE_n)); + + /* !!! NOTICE !!! + Before changing wait state, both Pre-fetch function and Branch Cache function must be disabled. + */ + uCFCR = HT_FLASH->CFCR; /* Backup previous settings. */ + + /* Disable Pre-fetch function and Branch Cache. */ + HT_FLASH->CFCR = uCFCR & FLASH_PREFETCHBUF_AND_BRANCHCACHE_OFF; + /* Change wait state. */ + HT_FLASH->CFCR = (uCFCR & FLASH_CFCR_MASK) | FLASH_WAITSTATE_n; + /* Restore previous settings. */ + HT_FLASH->CFCR |= uCFCR & (FLASH_PREFETCHBUF_AND_BRANCHCACHE_ON); +} + +/*********************************************************************************************************//** + * @brief Enable or Disable FLASH pre-fetch buffer. + * @param NewState: This parameter can be ENABLE or DISABLE + * @retval None + ************************************************************************************************************/ +void FLASH_PrefetchBufferCmd(ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_CONTROL_STATUS(NewState)); + + if (NewState != DISABLE) + { + HT_FLASH->CFCR |= FLASH_PREFETCHBUF_ON; + } + else + { + HT_FLASH->CFCR &= FLASH_PREFETCHBUF_OFF; + } +} + +/*********************************************************************************************************//** + * @brief Enable or Disable FLASH DCODE cache mode. + * @param NewState: This parameter can be ENABLE or DISABLE + * @retval None + ************************************************************************************************************/ +void FLASH_DcodeCacheCmd(ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_CONTROL_STATUS(NewState)); + + if (NewState != DISABLE) + { + HT_FLASH->CFCR &= FLASH_DCODECACHE_ON; + } + else + { + HT_FLASH->CFCR |= FLASH_DCODECACHE_OFF; + } +} + +/*********************************************************************************************************//** + * @brief Enable or Disable FLASH branch cache. + * @param NewState: This parameter can be ENABLE or DISABLE + * @retval None + ************************************************************************************************************/ +void FLASH_BranchCacheCmd(ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_CONTROL_STATUS(NewState)); + + if (NewState != DISABLE) + { + HT_FLASH->CFCR |= FLASH_BRANCHCACHE_ON; + } + else + { + HT_FLASH->CFCR &= FLASH_BRANCHCACHE_OFF; + } +} + +#if (LIBCFG_FLASH_HALFCYCYLE) +/*********************************************************************************************************//** + * @brief Enable or Disable FLASH half cycle access. + * @param NewState: new state of the FLASH half cycle access. + * This parameter can be: ENABLE or DISABLE + * @retval ERROR or SUCCESS + ************************************************************************************************************/ +ErrStatus FLASH_FlashHalfCycleCmd(ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_CONTROL_STATUS(NewState)); + + if ((HT_FLASH->CFCR & ~CFCR_WAIT_MASK) == FLASH_WAITSTATE_0) + { + if (NewState != DISABLE) + { + HT_FLASH->CFCR |= FLASH_HALFCYCLE_ON; + } + else + { + HT_FLASH->CFCR &= FLASH_HALFCYCLE_OFF; + } + + return SUCCESS; + } + + return ERROR; +} +#endif + +#if (LIBCFG_FLASH_ZWPWESAVING) +/*********************************************************************************************************//** + * @brief Enable or Disable FLASH zero wait state power saving. + * @param NewState: new state of the FLASH zero wait state power saving. + * This parameter can be: ENABLE or DISABLE + * @retval ERROR or SUCCESS + ************************************************************************************************************/ +ErrStatus FLASH_FlashZwPwrSavingCmd(ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_CONTROL_STATUS(NewState)); + + if ((HT_FLASH->CFCR & ~CFCR_WAIT_MASK) == FLASH_WAITSTATE_0) + { + if (NewState != DISABLE) + { + HT_FLASH->CFCR |= FLASH_ZWPWRSAVING_ON; + } + else + { + HT_FLASH->CFCR &= FLASH_ZWPWRSAVING_OFF; + } + + return SUCCESS; + } + + return ERROR; +} +#endif + +/*********************************************************************************************************//** + * @brief Set vector remapping mode. + * @param FLASH_BOOT_x: Booting mode. + * This parameter can be one of the following values: + * @arg \ref FLASH_BOOT_LOADER : Boot loader mode + * @arg \ref FLASH_BOOT_SRAM : SRAM booting mode + * @arg \ref FLASH_BOOT_MAIN : Main FLASH mode + * @retval None + ************************************************************************************************************/ +void FLASH_SetRemappingMode(FLASH_Vector FLASH_BOOT_x) +{ + /* Check the parameters */ + Assert_Param(IS_FLASH_VECTOR_MODE(FLASH_BOOT_x)); + + HT_FLASH->VMCR = FLASH_BOOT_x; +} + +/*********************************************************************************************************//** + * @brief Erase a specific FLASH page. + * @param PageAddress: Address of the erased page. + * @retval FLASH_State + * - \ref FLASH_COMPLETE + * - \ref FLASH_TIME_OUT + * - \ref FLASH_ERR_WRITE_PROTECTED + * - \ref FLASH_ERR_ADDR_OUT_OF_RANGE + * @note HSI must keep turn on when doing the Flash operation (Erase/Program). + ************************************************************************************************************/ +FLASH_State FLASH_ErasePage(u32 PageAddress) +{ + FLASH_State status; + #if (AUTO_CMDVERIFY == 1) + u32 uData; + u32 uAddress; + PageAddress &= (~(FLASH_PAGE_SIZE - 1)); + uAddress = PageAddress; + #endif + + /* Check the parameters */ + Assert_Param(IS_FLASH_ADDRESS(PageAddress)); + + #if (AUTO_CMDVERIFY == 1) + do + { + if (uAddress - PageAddress == FLASH_PAGE_SIZE) + { + return FLASH_COMPLETE; + } + + uData = rw(uAddress); + uAddress += 4; + } while (uData == 0xFFFFFFFF); + #endif + + HT_FLASH->TADR = PageAddress; + HT_FLASH->OCMR = FLASH_CMD_PAGEERASE; + + #if (AUTO_CMDVERIFY == 1) + do { + #endif + status = FLASH_WaitForOperationEnd(); + #if (AUTO_CMDVERIFY == 1) + if (status != FLASH_COMPLETE) + break; + } while (rw(uAddress - 4) != 0xFFFFFFFF); + #endif + + return status; +} + +/*********************************************************************************************************//** + * @brief Erase FLASH Option Byte page. + * @retval FLASH_State + * - \ref FLASH_COMPLETE + * - \ref FLASH_TIME_OUT + * - \ref FLASH_ERR_WRITE_PROTECTED + * @note HSI must keep turn on when doing the Flash operation (Erase/Program). + ************************************************************************************************************/ +FLASH_State FLASH_EraseOptionByte(void) +{ + return FLASH_ErasePage(OPTION_BYTE_BASE); +} + +/*********************************************************************************************************//** + * @brief Erase the entire FLASH. + * @retval FLASH_State + * - \ref FLASH_COMPLETE + * - \ref FLASH_TIME_OUT + * @note HSI must keep turn on when doing the Flash operation (Erase/Program). + ************************************************************************************************************/ +FLASH_State FLASH_MassErase(void) +{ + HT_FLASH->OCMR = FLASH_CMD_MASSERASE; + + return FLASH_WaitForOperationEnd(); +} + +/*********************************************************************************************************//** + * @brief Program one word data. + * @param Address: The specific FLASH address to be programmed. + * @param Data: The specific FLASH data to be programmed. + * @retval FLASH_State + * - \ref FLASH_COMPLETE + * - \ref FLASH_TIME_OUT + * - \ref FLASH_ERR_WRITE_PROTECTED + * - \ref FLASH_ERR_ADDR_OUT_OF_RANGE + * @note HSI must keep turn on when doing the Flash operation (Erase/Program). + ************************************************************************************************************/ +FLASH_State FLASH_ProgramWordData(u32 Address, u32 Data) +{ + FLASH_State status; + + /* Check the parameters */ + Assert_Param(IS_FLASH_ADDRESS(Address)); + + HT_FLASH->TADR = Address; + HT_FLASH->WRDR = Data; + HT_FLASH->OCMR = FLASH_CMD_PROGRAM; + + if (Data == 0xFFFFFFFF) + { + return FLASH_COMPLETE; + } + + #if (AUTO_CMDVERIFY == 1) + do { + #endif + status = FLASH_WaitForOperationEnd(); + #if (AUTO_CMDVERIFY == 1) + if (status != FLASH_COMPLETE) + break; + } while (rw(Address) == 0xFFFFFFFF); + #endif + + return status; +} + +/*********************************************************************************************************//** + * @brief Program FLASH Option Byte page. + * @param Option: Struct pointer of Option Bytes. + * @retval FLASH_State + * - \ref FLASH_COMPLETE + * @note HSI must keep turn on when doing the Flash operation (Erase/Program). + ************************************************************************************************************/ +FLASH_State FLASH_ProgramOptionByte(FLASH_OptionByte *Option) +{ + s32 i; + u32 CP = ~(Option->MainSecurity | Option->OptionProtect << 1); + u32 checksum = 0; + + for (i = 3; i >= 0; i--) + { + FLASH_ProgramWordData(OB_PP0 + i * 4, ~(Option->WriteProtect[i])); + checksum += ~(Option->WriteProtect[i]); + } + + FLASH_ProgramWordData(OB_CP, CP); + checksum += CP; + + FLASH_ProgramWordData(OB_CHECKSUM, checksum); + + return FLASH_COMPLETE; +} + +/*********************************************************************************************************//** + * @brief Return security status of the FLASH. + * @param Option: Struct pointer of Option Bytes. + * @retval None + ************************************************************************************************************/ +void FLASH_GetOptionByteStatus(FLASH_OptionByte *Option) +{ + s32 i; + + for (i = 3; i >= 0; i--) + { + Option->WriteProtect[i] = ~HT_FLASH->PPSR[i]; + } + + Option->MainSecurity = !(HT_FLASH->CPSR & 1); + Option->OptionProtect = !((HT_FLASH->CPSR >> 1) & 1); +} + +/*********************************************************************************************************//** + * @brief Enable or Disable the specific FLASH interrupts. + * @param FLASH_INT_x: The specific FLASH interrupt. + * This parameter can be any combination (|) of the following values: + * @arg \ref FLASH_INT_ORFIEN + * @arg \ref FLASH_INT_ITADIEN + * @arg \ref FLASH_INT_OBEIEN + * @arg \ref FLASH_INT_IOCMIEN + * @arg \ref FLASH_INT_OREIEN + * @arg \ref FLASH_INT_ALL + * @param Cmd: This parameter can be ENABLE or DISABLE + * @retval None + ************************************************************************************************************/ +void FLASH_IntConfig(u32 FLASH_INT_x, ControlStatus Cmd) +{ + /* Check the parameters */ + Assert_Param(IS_FLASH_INT(FLASH_INT_x)); + Assert_Param(IS_CONTROL_STATUS(Cmd)); + + if (Cmd != DISABLE) + { + HT_FLASH->OIER |= FLASH_INT_x; + } + else + { + HT_FLASH->OIER &= ~FLASH_INT_x; + } +} + +/*********************************************************************************************************//** + * @brief Return flag status of the FLASH interrupt. + * @param FLASH_FLAG_x: Flag of the FLASH interrupt. + * This parameter can be any combination (|) of the following values: + * @arg \ref FLASH_FLAG_OREF + * @arg \ref FLASH_FLAG_IOCMF + * @arg \ref FLASH_FLAG_OBEF + * @arg \ref FLASH_FLAG_ITADF + * @arg \ref FLASH_FLAG_ORFF + * @arg \ref FLASH_FLAG_PPEF + * @arg \ref FLASH_FLAG_RORFF + * @retval FlagStatus + * - \ref SET + * - \ref RESET + ************************************************************************************************************/ +FlagStatus FLASH_GetIntStatus(u32 FLASH_FLAG_x) +{ + /* Check the parameters */ + Assert_Param(IS_FLASH_FLAG(FLASH_FLAG_x)); + + if ((HT_FLASH->OISR & FLASH_FLAG_x) != (u32)RESET) + { + return SET; + } + else + { + return RESET; + } +} + +/*********************************************************************************************************//** + * @brief Clear specific interrupt flags of FLASH. + * @param FLASH_FLAG_x: interrupt flag of FLASH. + * This parameter can be any combination (|) of the following values: + * @arg \ref FLASH_FLAG_OREF + * @arg \ref FLASH_FLAG_IOCMF + * @arg \ref FLASH_FLAG_OBEF + * @arg \ref FLASH_FLAG_ITADF + * @arg \ref FLASH_FLAG_ORFF + * @retval None + ************************************************************************************************************/ +void FLASH_ClearIntFlag(u32 FLASH_FLAG_x) +{ + /* Check the parameters */ + Assert_Param(IS_FLASH_WC_FLAG(FLASH_FLAG_x)); + + HT_FLASH->OISR = FLASH_FLAG_x; +} + +/*********************************************************************************************************//** + * @brief Wait untill the FLASH operation has finished or time-out has occurred. + * @retval FLASH_State + * - \ref FLASH_COMPLETE + * - \ref FLASH_TIME_OUT + * - \ref FLASH_ERR_WRITE_PROTECTED + * - \ref FLASH_ERR_ADDR_OUT_OF_RANGE + * @note HSI must keep turn on when doing the Flash operation (Erase/Program). + ************************************************************************************************************/ +FLASH_State FLASH_WaitForOperationEnd(void) +{ + u32 Timeout = FLASH_TIMEOUT; + u32 Status; + + HT_FLASH->OIER |= (FLASH_INT_ITADIEN); + HT_FLASH->OPCR = FLASH_SEND_MAIN; + + /* Waits till the FLASH operation has finished or time-out has occurred */ + while (Timeout--) + { + if ((HT_FLASH->OPCR & FLASH_READY) == FLASH_READY) + { + break; + } + } + Status = HT_FLASH->OISR; + HT_FLASH->OISR &= ~(FLASH_INT_ITADIEN); + + if (Status & FLASH_FLAG_PPEF) + { + return FLASH_ERR_WRITE_PROTECTED; + } + if (Status & FLASH_FLAG_ITADF) + { + return FLASH_ERR_ADDR_OUT_OF_RANGE; + } + if (Timeout == 0) + { + return FLASH_TIME_OUT; + } + + return FLASH_COMPLETE; +} +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ diff --git a/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/src/ht32f1xxxx_gpio.c b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/src/ht32f1xxxx_gpio.c new file mode 100644 index 0000000000..572d61055c --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/src/ht32f1xxxx_gpio.c @@ -0,0 +1,730 @@ +/*********************************************************************************************************//** + * @file ht32f1xxxx_gpio.c + * @version $Rev:: 2797 $ + * @date $Date:: 2022-11-28 #$ + * @brief This file provides all the GPIO and AFIO firmware functions. + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ + +/* Includes ------------------------------------------------------------------------------------------------*/ +#include "ht32f1xxxx_gpio.h" + +/** @addtogroup HT32F1xxxx_Peripheral_Driver HT32F1xxxx Peripheral Driver + * @{ + */ + +/** @defgroup GPIO GPIO + * @brief GPIO driver modules + * @{ + */ + + +/* Private function prototypes -----------------------------------------------------------------------------*/ +u32 _GPIO_ClockControl(HT_GPIO_TypeDef* HT_GPIOx, ControlStatus Cmd); +u32 _AFIO_ClockControl(ControlStatus Cmd); + +/* Private macro -------------------------------------------------------------------------------------------*/ +/** @defgroup GPIO_Private_Macro GPIO private macros + * @{ + */ +#if (AUTO_CK_CONTROL == 1) + #define GPIO_CK_ST u32 isAlreadyOn + #define GPIO_CK_ON() (isAlreadyOn = _GPIO_ClockControl(HT_GPIOx, ENABLE)) + #define GPIO_CK_OFF() if (isAlreadyOn == FALSE) _GPIO_ClockControl(HT_GPIOx, DISABLE) + #define AFIO_CK_ST u32 isAlreadyOn + #define AFIO_CK_ON() (isAlreadyOn = _AFIO_ClockControl(ENABLE)) + #define AFIO_CK_OFF() if (isAlreadyOn == FALSE) _AFIO_ClockControl(DISABLE) +#else + #define GPIO_CK_ST + #define GPIO_CK_ON(...) + #define GPIO_CK_OFF(...) + #define AFIO_CK_ST + #define AFIO_CK_ON(...) + #define AFIO_CK_OFF(...) +#endif +/** + * @} + */ + +/* Global functions ----------------------------------------------------------------------------------------*/ +/** @addtogroup GPIO_Exported_Functions GPIO exported functions + * @{ + */ +/*********************************************************************************************************//** + * @brief Deinitializes the GPIO peripheral registers to their default reset values. + * @param HT_GPIOx: where HT_GPIOx is the selected GPIO from the GPIO peripherals. + * @retval None + ************************************************************************************************************/ +void GPIO_DeInit(HT_GPIO_TypeDef* HT_GPIOx) +{ + RSTCU_PeripReset_TypeDef RSTCUReset = {{0}}; + + /* Check the parameters */ + Assert_Param(IS_GPIO(HT_GPIOx)); + + if (HT_GPIOx == HT_GPIOA) + { + RSTCUReset.Bit.PA = 1; + } + else if (HT_GPIOx == HT_GPIOB) + { + RSTCUReset.Bit.PB = 1; + } + else if (HT_GPIOx == HT_GPIOC) + { + RSTCUReset.Bit.PC = 1; + } + else if (HT_GPIOx == HT_GPIOD) + { + RSTCUReset.Bit.PD = 1; + } + #if (LIBCFG_GPIOE) + else if (HT_GPIOx == HT_GPIOE) + { + RSTCUReset.Bit.PE = 1; + } + #endif + #if (LIBCFG_GPIOF) + else if (HT_GPIOx == HT_GPIOF) + { + RSTCUReset.Bit.PF = 1; + } + #endif + + RSTCU_PeripReset(RSTCUReset, ENABLE); +} + +/*********************************************************************************************************//** + * @brief Configure the direction of specified GPIO pins. + * @param HT_GPIOx: where HT_GPIOx is the selected GPIO from the GPIO peripherals. + * @param GPIO_PIN_nBITMAP: The port pins. + * This parameter can be any combination of GPIO_PIN_x. + * @param GPIO_DIR_INorOUT: + * This parameter can be one of below: + * @arg GPIO_DIR_IN : The pins are input mode + * @arg GPIO_DIR_OUT : The pins are output mode + * @retval None + ************************************************************************************************************/ +void GPIO_DirectionConfig(HT_GPIO_TypeDef* HT_GPIOx, u16 GPIO_PIN_nBITMAP, GPIO_DIR_Enum GPIO_DIR_INorOUT) +{ + GPIO_CK_ST; + + /* Check the parameters */ + Assert_Param(IS_GPIO(HT_GPIOx)); + Assert_Param(IS_GPIO_DIR(GPIO_DIR_INorOUT)); + + GPIO_CK_ON(); + + if (GPIO_DIR_INorOUT != GPIO_DIR_IN) + HT_GPIOx->DIRCR |= GPIO_PIN_nBITMAP; + else + HT_GPIOx->DIRCR &= ~GPIO_PIN_nBITMAP; + + GPIO_CK_OFF(); +} + +/*********************************************************************************************************//** + * @brief Configure the pull resistor of specified GPIO pins. + * @param HT_GPIOx: where HT_GPIOx is the selected GPIO from the GPIO peripherals. + * @param GPIO_PIN_nBITMAP: The port pins. + * This parameter can be any combination of GPIO_PIN_x. + * @param GPIO_PR_x: Selection of Pull resistor. + * This parameter can be one of below: + * @arg GPIO_PR_UP : The pins with internal pull-up resistor + * @arg GPIO_PR_DOWN : The pins with internal pull-down resistor + * @arg GPIO_PR_DISABLE : The pins without pull resistor + * @retval None + ************************************************************************************************************/ +void GPIO_PullResistorConfig(HT_GPIO_TypeDef* HT_GPIOx, u16 GPIO_PIN_nBITMAP, GPIO_PR_Enum GPIO_PR_x) +{ + u32 temp_up, temp_down; + GPIO_CK_ST; + + /* Check the parameters */ + Assert_Param(IS_GPIO(HT_GPIOx)); + Assert_Param(IS_GPIO_PR(GPIO_PR_x)); + + GPIO_CK_ON(); + temp_up = HT_GPIOx->PUR; + temp_down = HT_GPIOx->PDR; + + temp_up &= ~GPIO_PIN_nBITMAP; + temp_down &= ~GPIO_PIN_nBITMAP; + + switch (GPIO_PR_x) + { + case GPIO_PR_UP: + temp_up |= GPIO_PIN_nBITMAP; + break; + case GPIO_PR_DOWN: + temp_down |= GPIO_PIN_nBITMAP; + break; + case GPIO_PR_DISABLE: + break; + default: + break; + } + + HT_GPIOx->PUR = temp_up; + HT_GPIOx->PDR = temp_down; + + GPIO_CK_OFF(); +} + +/*********************************************************************************************************//** + * @brief Enable or Disable the input control of specified GPIO pins. + * @param HT_GPIOx: where HT_GPIOx is the selected GPIO from the GPIO peripherals. + * @param GPIO_PIN_nBITMAP: The port pins. + * This parameter can be any combination of GPIO_PIN_x. + * @param Cmd: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void GPIO_InputConfig(HT_GPIO_TypeDef* HT_GPIOx, u16 GPIO_PIN_nBITMAP, ControlStatus Cmd) +{ + GPIO_CK_ST; + + /* Check the parameters */ + Assert_Param(IS_GPIO(HT_GPIOx)); + Assert_Param(IS_CONTROL_STATUS(Cmd)); + + GPIO_CK_ON(); + if (Cmd != DISABLE) + HT_GPIOx->INER |= GPIO_PIN_nBITMAP; + else + HT_GPIOx->INER &= ~GPIO_PIN_nBITMAP; + GPIO_CK_OFF(); +} + +/*********************************************************************************************************//** + * @brief Select the driving current of specified GPIO pins. + * @param HT_GPIOx: where HT_GPIOx is the selected GPIO from the GPIO peripherals. + * @param GPIO_PIN_nBITMAP: The port pins. + * This parameter can be any combination of GPIO_PIN_x. + * @param GPIO_DV_nMA: + * This parameter can be one of below: + * @arg GPIO_DV_4MA : Select output driving current as 4 mA + * @arg GPIO_DV_8MA : Select output driving current as 8 mA + * @arg GPIO_DV_12MA : Select output driving current as 12 mA (For HT32F1xxxx only) + * @arg GPIO_DV_16MA : Select output driving current as 16 mA (For HT32F1xxxx only) + * @retval None + ************************************************************************************************************/ +void GPIO_DriveConfig(HT_GPIO_TypeDef* HT_GPIOx, u16 GPIO_PIN_nBITMAP, GPIO_DV_Enum GPIO_DV_nMA) +{ + GPIO_CK_ST; + + /* Check the parameters */ + Assert_Param(IS_GPIO(HT_GPIOx)); + Assert_Param(IS_GPIO_DV(GPIO_DV_nMA)); + + GPIO_CK_ON(); +#if (LIBCFG_GPIO_DV_4_8MA_ONLY) + if (GPIO_DV_nMA != GPIO_DV_4MA) + HT_GPIOx->DRVR |= GPIO_PIN_nBITMAP; + else + HT_GPIOx->DRVR &= ~GPIO_PIN_nBITMAP; +#else +{ + u8 index = 0, temp = 0; + u32 CurrentMode = 0, PinPosition = 0; + for (index = 0; index < 16; index++) + { + if ((GPIO_PIN_nBITMAP & 0x0001) == 1) + { + temp = index << 1; + CurrentMode |= ((u32) GPIO_DV_nMA << temp); + PinPosition |= ((u32) 0x03 << temp); + } + GPIO_PIN_nBITMAP >>= 1; + } + + HT_GPIOx->DRVR &= ~PinPosition; + HT_GPIOx->DRVR |= CurrentMode; +} +#endif + GPIO_CK_OFF(); +} + +/*********************************************************************************************************//** + * @brief Enable or Disable the open drain function of specified GPIO pins. + * @param HT_GPIOx: where HT_GPIOx is the selected GPIO from the GPIO peripherals. + * @param GPIO_PIN_nBITMAP: The port pins. + * This parameter can be any combination of GPIO_PIN_x. + * @param Cmd: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void GPIO_OpenDrainConfig(HT_GPIO_TypeDef* HT_GPIOx, u16 GPIO_PIN_nBITMAP, ControlStatus Cmd) +{ + GPIO_CK_ST; + + /* Check the parameters */ + Assert_Param(IS_GPIO(HT_GPIOx)); + Assert_Param(IS_CONTROL_STATUS(Cmd)); + + GPIO_CK_ON(); + if (Cmd != DISABLE) + HT_GPIOx->ODR |= GPIO_PIN_nBITMAP; + else + HT_GPIOx->ODR &= ~GPIO_PIN_nBITMAP; + GPIO_CK_OFF(); +} + +/*********************************************************************************************************//** + * @brief Get the input data of specified port pin. + * @param HT_GPIOx: where HT_GPIOx is the selected GPIO from the GPIO peripherals. + * @param GPIO_PIN_n: This parameter can be GPIO_PIN_x. + * @retval SET or RESET + ************************************************************************************************************/ +FlagStatus GPIO_ReadInBit(HT_GPIO_TypeDef* HT_GPIOx, u16 GPIO_PIN_n) +{ + FlagStatus result; + GPIO_CK_ST; + + /* Check the parameters */ + Assert_Param(IS_GPIO(HT_GPIOx)); + + GPIO_CK_ON(); + if ((HT_GPIOx->DINR & GPIO_PIN_n) != RESET) + result = SET; + else + result = RESET; + + GPIO_CK_OFF(); + return result; +} + +/*********************************************************************************************************//** + * @brief Get the input data of specified GPIO port. + * @param HT_GPIOx: where HT_GPIOx is the selected GPIO from the GPIO peripherals. + * @retval The value of input data register. + ************************************************************************************************************/ +u16 GPIO_ReadInData(HT_GPIO_TypeDef* HT_GPIOx) +{ + u16 uValue; + GPIO_CK_ST; + + /* Check the parameters */ + Assert_Param(IS_GPIO(HT_GPIOx)); + + GPIO_CK_ON(); + uValue = (u16)HT_GPIOx->DINR; + GPIO_CK_OFF(); + return (uValue); +} + +/*********************************************************************************************************//** + * @brief Get the output data of specified port pin. + * @param HT_GPIOx: where HT_GPIOx is the selected GPIO from the GPIO peripherals. + * @param GPIO_PIN_n: This parameter can be GPIO_PIN_x. + * @retval SET or RESET + ************************************************************************************************************/ +FlagStatus GPIO_ReadOutBit(HT_GPIO_TypeDef* HT_GPIOx, u16 GPIO_PIN_n) +{ + FlagStatus result; + GPIO_CK_ST; + /* Check the parameters */ + Assert_Param(IS_GPIO(HT_GPIOx)); + + GPIO_CK_ON(); + if ((HT_GPIOx->DOUTR & GPIO_PIN_n) != RESET) + result = SET; + else + result = RESET; + + GPIO_CK_OFF(); + return result; +} + +/*********************************************************************************************************//** + * @brief Get the output data of specified GPIO port. + * @param HT_GPIOx: where HT_GPIOx is the selected GPIO from the GPIO peripherals. + * @retval The value of output data register. + ************************************************************************************************************/ +u16 GPIO_ReadOutData(HT_GPIO_TypeDef* HT_GPIOx) +{ + u32 uValue; + GPIO_CK_ST; + + /* Check the parameters */ + Assert_Param(IS_GPIO(HT_GPIOx)); + + GPIO_CK_ON(); + uValue = (u16)HT_GPIOx->DOUTR; + GPIO_CK_OFF(); + return uValue; +} + +/*********************************************************************************************************//** + * @brief Set the selected port bits of output data. + * @param HT_GPIOx: where HT_GPIOx is the selected GPIO from the GPIO peripherals. + * @param GPIO_PIN_nBITMAP: Specify the port bit to be set. + * This parameter can be any combination of GPIO_PIN_x. + * @retval None + ************************************************************************************************************/ +void GPIO_SetOutBits(HT_GPIO_TypeDef* HT_GPIOx, u16 GPIO_PIN_nBITMAP) +{ + GPIO_CK_ST; + + /* Check the parameters */ + Assert_Param(IS_GPIO(HT_GPIOx)); + + GPIO_CK_ON(); + HT_GPIOx->SRR = GPIO_PIN_nBITMAP; + GPIO_CK_OFF(); +} + +/*********************************************************************************************************//** + * @brief Clear the selected port bits of output data. + * @param HT_GPIOx: where HT_GPIOx is the selected GPIO from the GPIO peripherals. + * @param GPIO_PIN_nBITMAP: Specify the port bit to be clear. + * This parameter can be any combination of GPIO_PIN_x. + * @retval None + ************************************************************************************************************/ +void GPIO_ClearOutBits(HT_GPIO_TypeDef* HT_GPIOx, u16 GPIO_PIN_nBITMAP) +{ + GPIO_CK_ST; + + /* Check the parameters */ + Assert_Param(IS_GPIO(HT_GPIOx)); + + GPIO_CK_ON(); + HT_GPIOx->RR = GPIO_PIN_nBITMAP; + GPIO_CK_OFF(); +} + +/*********************************************************************************************************//** + * @brief Set or Clear the selected port bits of data. + * @param HT_GPIOx: where HT_GPIOx is the selected GPIO from the GPIO peripherals. + * @param GPIO_PIN_nBITMAP: Specify the port bits. + * This parameter can be any combination of GPIO_PIN_x. + * @param Status: This parameter can be SET or RESET. + * @retval None + ************************************************************************************************************/ +void GPIO_WriteOutBits(HT_GPIO_TypeDef* HT_GPIOx, u16 GPIO_PIN_nBITMAP, FlagStatus Status) +{ + GPIO_CK_ST; + + /* Check the parameters */ + Assert_Param(IS_GPIO(HT_GPIOx)); + + GPIO_CK_ON(); + if (Status != RESET) + HT_GPIOx->SRR = GPIO_PIN_nBITMAP; + else + HT_GPIOx->RR = GPIO_PIN_nBITMAP; + GPIO_CK_OFF(); +} + +/*********************************************************************************************************//** + * @brief Put data to the specified GPIO data port. + * @param HT_GPIOx: where HT_GPIOx is the selected GPIO from the GPIO peripherals. + * @param Data: Specify the data to be written to the port data register. + * @retval None + ************************************************************************************************************/ +void GPIO_WriteOutData(HT_GPIO_TypeDef* HT_GPIOx, u16 Data) +{ + GPIO_CK_ST; + + /* Check the parameters */ + Assert_Param(IS_GPIO(HT_GPIOx)); + + GPIO_CK_ON(); + HT_GPIOx->DOUTR = Data; + GPIO_CK_OFF(); +} + +/*********************************************************************************************************//** + * @brief Lock configuration of GPIO pins. + * @param HT_GPIOx: where HT_GPIOx is the selected GPIO from the GPIO peripherals. + * @param GPIO_PIN_nBITMAP: Specify the port bits. + * This parameter can be any combination of GPIO_PIN_x. + * @retval None + ************************************************************************************************************/ +void GPIO_PinLock(HT_GPIO_TypeDef* HT_GPIOx, u16 GPIO_PIN_nBITMAP) +{ + GPIO_CK_ST; + + /* Check the parameters */ + Assert_Param(IS_GPIO(HT_GPIOx)); + + GPIO_CK_ON(); + HT_GPIOx->LOCKR = (u32)0x5FA00000 | GPIO_PIN_nBITMAP; + GPIO_CK_OFF(); +} + +/*********************************************************************************************************//** + * @brief Get the lock state of specified GPIO port. + * @param HT_GPIOx: where HT_GPIOx is the selected GPIO from the GPIO peripherals. + * @retval TRUE or FALSE + ************************************************************************************************************/ +bool GPIO_IsPortLocked(HT_GPIO_TypeDef* HT_GPIOx) +{ + bool result; + GPIO_CK_ST; + + /* Check the parameters */ + Assert_Param(IS_GPIO(HT_GPIOx)); + + GPIO_CK_ON(); + if ((HT_GPIOx->LOCKR >> 16) == 0) + result = FALSE; + else + result = TRUE; + GPIO_CK_OFF(); + return result; +} + +/*********************************************************************************************************//** + * @brief Get the lock state of specified GPIO port pin. + * @param HT_GPIOx: where HT_GPIOx is the selected GPIO from the GPIO peripherals. + * @param GPIO_PIN_n: This parameter can be GPIO_PIN_x. + * @retval TRUE or FALSE + ************************************************************************************************************/ +bool GPIO_IsPinLocked(HT_GPIO_TypeDef* HT_GPIOx, u16 GPIO_PIN_n) +{ + bool result; + GPIO_CK_ST; + + /* Check the parameters */ + Assert_Param(IS_GPIO(HT_GPIOx)); + + GPIO_CK_ON(); + if ((HT_GPIOx->LOCKR & GPIO_PIN_n) == 0) + result = FALSE; + else + result = TRUE; + GPIO_CK_OFF(); + return result; +} + +/*********************************************************************************************************//** + * @brief Disable DEBUG port to prevent unexpected security lock. + * @retval None + ************************************************************************************************************/ +void GPIO_DisableDebugPort(void) +{ + CKCU_PeripClockConfig_TypeDef CKCUClock = {{ 0 }}; + CKCUClock.Bit.PA = 1; + CKCUClock.Bit.AFIO = 1; + CKCU_PeripClockConfig(CKCUClock, ENABLE); + + AFIO_GPxConfig(GPIO_PA, GPIO_PIN_13, AFIO_FUN_GPIO); + GPIO_PullResistorConfig(HT_GPIOA, GPIO_PIN_13, GPIO_PR_DOWN); + GPIO_InputConfig(HT_GPIOA, GPIO_PIN_13, DISABLE); + + #if 0 + GPIO_PullResistorConfig(HT_GPIOA, GPIO_PIN_12, GPIO_PR_DOWN); + GPIO_PullResistorConfig(HT_GPIOA, GPIO_PIN_12, GPIO_PR_UP); + GPIO_PullResistorConfig(HT_GPIOA, GPIO_PIN_12, GPIO_PR_DOWN); + GPIO_PullResistorConfig(HT_GPIOA, GPIO_PIN_12, GPIO_PR_UP); + GPIO_PullResistorConfig(HT_GPIOA, GPIO_PIN_12, GPIO_PR_DOWN); + GPIO_PullResistorConfig(HT_GPIOA, GPIO_PIN_12, GPIO_PR_UP); + GPIO_PullResistorConfig(HT_GPIOA, GPIO_PIN_12, GPIO_PR_DOWN); + GPIO_PullResistorConfig(HT_GPIOA, GPIO_PIN_12, GPIO_PR_UP); + AFIO_GPxConfig(GPIO_PA, GPIO_PIN_12, AFIO_FUN_GPIO); + #endif +} + +/*********************************************************************************************************//** + * @brief Convert HT_GPIOx to GPIO_Px + * @param HT_GPIOx: where HT_GPIOx is the selected GPIO from the GPIO peripherals. + * @retval GPIO_Px: GPIO ID + ************************************************************************************************************/ +u32 GPIO_GetID(HT_GPIO_TypeDef* HT_GPIOx) +{ + // Convert 0x400B0000 ~ 0x400C6000 to 0 ~ 11 + u32 GPIO_Px = (((u32)HT_GPIOx) >> (12 + 1)) & 0x7F; + GPIO_Px -= 0x58; // 0xB0000 >> 13 = 0x58 + + return GPIO_Px; +} + +/*********************************************************************************************************//** + * @brief Deinitialize the AFIO peripheral registers to their default reset values. + * @retval None + ************************************************************************************************************/ +void AFIO_DeInit(void) +{ + RSTCU_PeripReset_TypeDef RSTCUReset = {{0}}; + + RSTCUReset.Bit.AFIO = 1; + RSTCU_PeripReset(RSTCUReset, ENABLE); +} + +/*********************************************************************************************************//** + * @brief Configure alternated mode of GPIO with specified pins. + * @param GPIO_Px: GPIO_PA ~ GPIO_PE. + * @param AFIO_PIN_n: This parameter can be any combination of AFIO_PIN_x. + * @param AFIO_MODE_n: This parameter can be one of the following values: + * @arg AFIO_MODE_DEFAULT : The default I/O function + * @arg AFIO_MODE_1 : Alternated mode 1 + * @arg AFIO_MODE_2 : Alternated mode 2 + * @arg AFIO_MODE_3 : Alternated mode 3 + * @arg AFIO_MODE_4 : Alternated mode 4 + * @arg AFIO_MODE_5 : Alternated mode 5 + * @arg AFIO_MODE_6 : Alternated mode 6 + * @arg AFIO_MODE_7 : Alternated mode 7 + * @arg AFIO_MODE_8 : Alternated mode 8 + * @arg AFIO_MODE_9 : Alternated mode 9 + * @arg AFIO_MODE_10 : Alternated mode 10 + * @arg AFIO_MODE_11 : Alternated mode 11 + * @arg AFIO_MODE_12 : Alternated mode 12 + * @arg AFIO_MODE_13 : Alternated mode 13 + * @arg AFIO_MODE_14 : Alternated mode 14 + * @arg AFIO_MODE_15 : Alternated mode 15 + * @retval None + ************************************************************************************************************/ +void AFIO_GPxConfig(u32 GPIO_Px, u32 AFIO_PIN_n, AFIO_MODE_Enum AFIO_MODE_n) +{ + vu32* pGPxCFGR = ((vu32*)&HT_AFIO->GPACFGR[0]) + GPIO_Px * 2; + u32 index = 0; + u32 Mask = 0, PinMode = 0; + s32 i; + AFIO_CK_ST; + + Assert_Param(IS_AFIO_MODE(AFIO_MODE_n)); + AFIO_CK_ON(); + + for (i = 0; i <= 8; i += 8) + { + Mask = 0; + PinMode = 0; + if (AFIO_PIN_n & (0x00FF << i)) + { + for (index = 0; index < 8; index++) + { + if ((AFIO_PIN_n >> index) & (0x0001 << i)) + { + Mask |= (0xF << (index * 4)); + PinMode |= (AFIO_MODE_n << (index * 4)); + } + } + *pGPxCFGR = (*pGPxCFGR & (~Mask)) | PinMode; + } + pGPxCFGR++; + } + + AFIO_CK_OFF(); +} + +/*********************************************************************************************************//** + * @brief Select the GPIO pin to be used as EXTI channel. + * @param GPIO_PIN_NUM_n: Specify the GPIO pin number to be configured. + * @param GPIO_Px: GPIO_PA ~ GPIO_PF. + * @retval None + ************************************************************************************************************/ +void AFIO_EXTISourceConfig(u32 GPIO_PIN_NUM_n, u32 GPIO_Px) +{ + u8 index = 0; + u32 tmp = 0; + AFIO_CK_ST; + + /* Check the parameters */ + Assert_Param(IS_GPIO_PORT(GPIO_Px)); + Assert_Param(IS_GPIO_PIN_NUM(GPIO_PIN_NUM_n)); + + AFIO_CK_ON(); + + if (GPIO_PIN_NUM_n > 7) + { + index = 1; + GPIO_PIN_NUM_n -= 8; + } + + tmp = HT_AFIO->ESSR[index]; + tmp &= ~((u32)0x0F << (GPIO_PIN_NUM_n * 4)); + tmp |= (u32)GPIO_Px << (GPIO_PIN_NUM_n * 4); + HT_AFIO->ESSR[index] = tmp; + AFIO_CK_OFF(); +} +/** + * @} + */ + +/* Private functions ---------------------------------------------------------------------------------------*/ +/** @defgroup GPIO_Private_Functions GPIO private functions + * @{ + */ +/*********************************************************************************************************//** + * @brief Turn on/Turn off specify GPIO clock. + * @param HT_GPIOx: where HT_GPIOx is the selected GPIO from the GPIO peripherals. + * @param Cmd: This parameter can be ENABLE or DISABLE. + * @retval TRUE or FALSE (TRUE: already turn on, FALSE, Turn on by this call) + ***********************************************************************************************************/ +u32 _GPIO_ClockControl(HT_GPIO_TypeDef* HT_GPIOx, ControlStatus Cmd) +{ + u32 PxENStatus; + /*--------------------------------------------------------------------------------------------------------*/ + /* ((0x400Bx000 & 0x0000F000) >> 12 ) / 2 + 16 = */ + /* (0x0 ~ 0x4) + 16 = 16 ~ 20 for AHBCCR PAEN ~ PEEN bit offset */ + /*--------------------------------------------------------------------------------------------------------*/ + u32 offset = ((((u32)HT_GPIOx) & 0x0000F000) >> 12) / 2 + 16; + + PxENStatus = HT_CKCU->AHBCCR & (1 << offset); + + if (PxENStatus != 0) + { + if (Cmd == DISABLE) + { + HT_CKCU->AHBCCR &= (~(1 << offset)); + } + return TRUE; + } + + HT_CKCU->AHBCCR |= (1 << offset); + return FALSE; +} + +/*********************************************************************************************************//** + * @brief Turn on/Turn off AFIO clock. + * @param Cmd: This parameter can be ENABLE or DISABLE. + * @retval TRUE or FALSE (TRUE: already turn on, FALSE, Turn on by this call) + ***********************************************************************************************************/ +u32 _AFIO_ClockControl(ControlStatus Cmd) +{ + u32 AFIOENStatus; + + AFIOENStatus = HT_CKCU->APBCCR0 & (1 << 14); + + if (AFIOENStatus != 0) + { + if (Cmd == DISABLE) + { + HT_CKCU->APBCCR0 &= (~(1 << 14)); + } + return TRUE; + } + + HT_CKCU->APBCCR0 |= (1 << 14); + return FALSE; +} +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ diff --git a/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/src/ht32f1xxxx_gptm.c b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/src/ht32f1xxxx_gptm.c new file mode 100644 index 0000000000..b824c72b16 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/src/ht32f1xxxx_gptm.c @@ -0,0 +1,2 @@ +The SCTM, PWM, GPTM, and MCTM timer have similar architecture. They use the same driver, +"ht32fxxxxx_tm.c/.h" to save the code size. For those timers, please refet to the TM driver/example. diff --git a/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/src/ht32f1xxxx_i2c.c b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/src/ht32f1xxxx_i2c.c new file mode 100644 index 0000000000..81ea72bc65 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/src/ht32f1xxxx_i2c.c @@ -0,0 +1,773 @@ +/*********************************************************************************************************//** + * @file ht32f1xxxx_i2c.c + * @version $Rev:: 2787 $ + * @date $Date:: 2022-11-23 #$ + * @brief This file provides all the I2C firmware functions. + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ + +/* Includes ------------------------------------------------------------------------------------------------*/ +#include "ht32f1xxxx_i2c.h" + +/** @addtogroup HT32F1xxxx_Peripheral_Driver HT32F1xxxx Peripheral Driver + * @{ + */ + +/** @defgroup I2C I2C + * @brief I2C driver modules + * @{ + */ + + +/* Private constants ---------------------------------------------------------------------------------------*/ +/** @defgroup I2C_Private_Define I2C private definitions + * @{ + */ +/* I2C ENI2C mask */ +#define CR_ENI2C_SET ((u32)0x00000008) +#define CR_ENI2C_RESET ((u32)0xFFFFFFF7) + +/* I2C ENGC mask */ +#define CR_ENGC_SET ((u32)0x00000004) +#define CR_ENGC_RESET ((u32)0xFFFFFFFB) + +/* I2C AA mask */ +#define CR_ACK_SET ((u32)0x00000001) +#define CR_ACK_RESET ((u32)0xFFFFFFFE) + +/* I2C PDMANACK mask */ +#define CR_PDMANACK_SET ((u32)0x00000400) +#define CR_PDMANACK_RESET ((u32)0xFFFFFBFF) + +/* I2C ENTOUT mask */ +#define CR_ENTOUT_SET ((u32)0x00001000) +#define CR_ENTOUT_RESET ((u32)0xFFFFEFFF) + +/* I2C COMBFILT mask */ +#define CR_COMBFILTER_SET ((u32)0x00002000) +#define CR_COMBFILTER_RESET ((u32)0xFFFFDFFF) +/** + * @} + */ + +/* Global functions ----------------------------------------------------------------------------------------*/ +/** @defgroup I2C_Exported_Functions I2C exported functions + * @{ + */ +/*********************************************************************************************************//** + * @brief Deinitialize the I2C peripheral registers to their default reset values. + * @param I2Cx: where I2Cx is the selected I2C from the I2C peripherals. + * @retval None + ************************************************************************************************************/ +void I2C_DeInit(HT_I2C_TypeDef* I2Cx) +{ + RSTCU_PeripReset_TypeDef RSTCUReset = {{0}}; + + /* Check the parameters */ + Assert_Param(IS_I2C(I2Cx)); + + if (I2Cx == HT_I2C0) + { + RSTCUReset.Bit.I2C0 = 1; + } + else if (I2Cx == HT_I2C1) + { + RSTCUReset.Bit.I2C1 = 1; + } + + RSTCU_PeripReset(RSTCUReset, ENABLE); +} + +/*********************************************************************************************************//** + * @brief Initialize the I2Cx peripheral according to the specified parameters in the I2C_InitStruct. + * @param I2Cx: where I2Cx is the selected I2C from the I2C peripherals. + * @param I2C_InitStruct: pointer to a I2C_InitTypeDef structure. + * @retval None + ************************************************************************************************************/ +void I2C_Init(HT_I2C_TypeDef* I2Cx, I2C_InitTypeDef* I2C_InitStruct) +{ + u32 PCLK_Freq = 0; + s32 sTmp = 0; + s32 SHPGR = 0; + s32 SLPGR = 0; + + /* Check the parameters */ + Assert_Param(IS_I2C(I2Cx)); + Assert_Param(IS_I2C_GENERAL_CALL(I2C_InitStruct->I2C_GeneralCall)); + Assert_Param(IS_I2C_ACKNOWLEDGE_ADDRESS(I2C_InitStruct->I2C_AddressingMode)); + Assert_Param(IS_I2C_ACKNOWLEDGE(I2C_InitStruct->I2C_Acknowledge)); + Assert_Param(IS_I2C_ADDRESS(I2C_InitStruct->I2C_OwnAddress)); + Assert_Param(IS_I2C_SPEED(I2C_InitStruct->I2C_Speed)); + + I2Cx->CR = (I2Cx->CR & 0xFFFFFF7A) | I2C_InitStruct->I2C_GeneralCall | + I2C_InitStruct->I2C_AddressingMode | I2C_InitStruct->I2C_Acknowledge; + + I2Cx->ADDR = I2C_InitStruct->I2C_OwnAddress; + + if (I2Cx == HT_I2C0) + PCLK_Freq = CKCU_GetPeripFrequency(CKCU_PCLK_I2C0); + else if (I2Cx == HT_I2C1) + PCLK_Freq = CKCU_GetPeripFrequency(CKCU_PCLK_I2C1); + + switch (I2Cx->CR & 0xC000) + { + case 0: + { + sTmp = 6; + break; + } + case 0x4000: + { + sTmp = 8; + break; + } + case 0x8000: + { + sTmp = 9; + break; + } + } + + SHPGR = (PCLK_Freq * 9)/(I2C_InitStruct->I2C_Speed * 20) - sTmp - I2C_InitStruct->I2C_SpeedOffset; + SLPGR = (PCLK_Freq * 11)/(I2C_InitStruct->I2C_Speed * 20) - sTmp - I2C_InitStruct->I2C_SpeedOffset; + + SHPGR = (SHPGR < 0) ? 0 : SHPGR; + SLPGR = (SLPGR < 0) ? 0 : SLPGR; + + I2Cx->SHPGR = SHPGR; + I2Cx->SLPGR = SLPGR; +} + +/*********************************************************************************************************//** + * @brief Fill each I2C_InitStruct member with its default value. + * @param I2C_InitStruct: pointer to an I2C_InitTypeDef structure. + * @retval None + ************************************************************************************************************/ +void I2C_StructInit(I2C_InitTypeDef* I2C_InitStruct) +{ + I2C_InitStruct->I2C_GeneralCall = I2C_GENERALCALL_DISABLE; + I2C_InitStruct->I2C_AddressingMode = I2C_ADDRESSING_7BIT; + I2C_InitStruct->I2C_Acknowledge = I2C_ACK_DISABLE; + I2C_InitStruct->I2C_OwnAddress = 0; + I2C_InitStruct->I2C_Speed = 1000000; + I2C_InitStruct->I2C_SpeedOffset = 0; +} + +/*********************************************************************************************************//** + * @brief Enable or Disable the specified I2C peripheral. + * @param I2Cx: where I2Cx is the selected I2C from the I2C peripherals. + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void I2C_Cmd(HT_I2C_TypeDef* I2Cx, ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_I2C(I2Cx)); + Assert_Param(IS_CONTROL_STATUS(NewState)); + + if (NewState != DISABLE) + { + I2Cx->CR |= CR_ENI2C_SET; + } + else + { + I2Cx->CR &= CR_ENI2C_RESET; + } +} + +/*********************************************************************************************************//** + * @brief Generate STOP condition of I2C communication. + * @param I2Cx: where I2Cx is the selected I2C from the I2C peripherals. + * @retval None + ************************************************************************************************************/ +void I2C_GenerateSTOP(HT_I2C_TypeDef* I2Cx) +{ + /* Check the parameters */ + Assert_Param(IS_I2C(I2Cx)); + + I2Cx->CR |= 0x2; +} + +/*********************************************************************************************************//** + * @brief Enable or Disable I2C interrupts. + * @param I2Cx: where I2Cx is the selected I2C from the I2C peripherals. + * @param I2C_Int: specify if the I2C interrupt source to be enabled or disabled. + * This parameter can be any combination of the following values: + * @arg I2C_INT_STA + * @arg I2C_INT_STO + * @arg I2C_INT_ADRS + * @arg I2C_INT_GCS + * @arg I2C_INT_ARBLOS + * @arg I2C_INT_RXNACK + * @arg I2C_INT_BUSERR + * @arg I2C_INT_TOUT + * @arg I2C_INT_RXDNE + * @arg I2C_INT_TXDE + * @arg I2C_INT_RXBF + * @arg I2C_INT_ALL + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void I2C_IntConfig(HT_I2C_TypeDef* I2Cx, u32 I2C_Int, ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_I2C(I2Cx)); + Assert_Param(IS_I2C_INT(I2C_Int)); + Assert_Param(IS_CONTROL_STATUS(NewState)); + + if (NewState != DISABLE) + { + I2Cx->IER |= I2C_Int; + } + else + { + I2Cx->IER &= (u32)~I2C_Int; + } +} + +/*********************************************************************************************************//** + * @brief Enable or Disable I2C General Call. + * @param I2Cx: where I2Cx is the selected I2C from the I2C peripherals. + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void I2C_GeneralCallCmd(HT_I2C_TypeDef* I2Cx, ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_I2C(I2Cx)); + Assert_Param(IS_CONTROL_STATUS(NewState)); + + if (NewState != DISABLE) + { + I2Cx->CR |= CR_ENGC_SET; + } + else + { + I2Cx->CR &= CR_ENGC_RESET; + } +} + +/*********************************************************************************************************//** + * @brief Enable or Disable I2C sending acknowledgement. + * @param I2Cx: where I2Cx is the selected I2C from the I2C peripherals. + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void I2C_AckCmd(HT_I2C_TypeDef* I2Cx, ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_I2C(I2Cx)); + Assert_Param(IS_CONTROL_STATUS(NewState)); + + if (NewState != DISABLE) + { + I2Cx->CR |= CR_ACK_SET; + } + else + { + I2Cx->CR &= CR_ACK_RESET; + } +} + +/*********************************************************************************************************//** + * @brief Configure own address of the specified I2C. + * @param I2Cx: where I2Cx is the selected I2C from the I2C peripherals. + * @param I2C_Address: specify own address of I2C. + * @retval None + ************************************************************************************************************/ +void I2C_SetOwnAddress(HT_I2C_TypeDef* I2Cx, I2C_AddressTypeDef I2C_Address) +{ + /* Check the parameters */ + Assert_Param(IS_I2C(I2Cx)); + Assert_Param(IS_I2C_ADDRESS(I2C_Address)); + + I2Cx->ADDR = I2C_Address; +} + +/*********************************************************************************************************//** + * @brief Start transmitting to target slave address. + * @param I2Cx: where I2Cx is the selected I2C from the I2C peripherals. + * @param I2C_Address: specify the slave address which will be transmitted. + * @param I2C_Direction: This parameter can be I2C_MASTER_READ or I2C_MASTER_WRITE. + * @retval None + ************************************************************************************************************/ +void I2C_TargetAddressConfig(HT_I2C_TypeDef* I2Cx, I2C_AddressTypeDef I2C_Address, u32 I2C_Direction) +{ + /* Check the parameters */ + Assert_Param(IS_I2C(I2Cx)); + Assert_Param(IS_I2C_ADDRESS(I2C_Address)); + Assert_Param(IS_I2C_DIRECTION(I2C_Direction)); + + /* Make sure the prior stop command has been finished */ + while (I2Cx->CR & 0x2); + + if (I2C_Direction != I2C_MASTER_WRITE) + { + I2Cx->TAR = I2C_Address | I2C_MASTER_READ; + } + else + { + I2Cx->TAR = I2C_Address | I2C_MASTER_WRITE; + } +} + +/*********************************************************************************************************//** + * @brief Send a data word through the I2Cx peripheral. + * @param I2Cx: where I2Cx is the selected I2C from the I2C peripherals. + * @param I2C_Data: Byte to be transmitted. + * @retval None + ************************************************************************************************************/ +void I2C_SendData(HT_I2C_TypeDef* I2Cx, u8 I2C_Data) +{ + /* Check the parameters */ + Assert_Param(IS_I2C(I2Cx)); + + I2Cx->DR = I2C_Data; +} + +/*********************************************************************************************************//** + * @brief Return the received data by the I2Cx peripheral. + * @param I2Cx: where I2Cx is the selected I2C from the I2C peripherals. + * @retval The value of the received data. + ************************************************************************************************************/ +u8 I2C_ReceiveData(HT_I2C_TypeDef* I2Cx) +{ + /* Check the parameters */ + Assert_Param(IS_I2C(I2Cx)); + + return (u8)I2Cx->DR; +} + +/*********************************************************************************************************//** + * @brief Read the specified I2C register and returns its value. + * @param I2Cx: where I2Cx is the selected I2C from the I2C peripherals. + * @param I2C_Register: specify the register to read. + * This parameter can be one of the following values: + * @arg I2C_REGISTER_CR : Control Register + * @arg I2C_REGISTER_IER : Interrupt Enable Register + * @arg I2C_REGISTER_ADDR : Address Register + * @arg I2C_REGISTER_SR : Status Register + * @arg I2C_REGISTER_SHPGR : SCL High Period Generation Register + * @arg I2C_REGISTER_SLPGR : SCL Low Period Generation Register + * @arg I2C_REGISTER_DR : Data Register + * @arg I2C_REGISTER_TAR : Target Register + * @retval None + ************************************************************************************************************/ +u32 I2C_ReadRegister(HT_I2C_TypeDef* I2Cx, u8 I2C_Register) +{ + vu32 tmp = 0; + + /* Check the parameters */ + Assert_Param(IS_I2C(I2Cx)); + Assert_Param(IS_I2C_REGISTER(I2C_Register)); + + tmp = (u32)I2Cx; + tmp += I2C_Register; + return (*(u32 *)tmp); +} + +/*********************************************************************************************************//** + * @brief Check whether the specified I2C flag has been set. + * @param I2Cx: where I2Cx is the selected I2C from the I2C peripherals. + * @param I2C_Flag: specify the flag to be check. + * This parameter can be one of the following values: + * @arg I2C_FLAG_STA : I2C start condition transmitted flag (Master mode) + * @arg I2C_FLAG_STO : I2C stop condition detected flag (Slave flag) + * @arg I2C_FLAG_ADRS : I2C address flag + * @arg I2C_FLAG_GCS : I2C general call flag (Slave mode) + * @arg I2C_FLAG_ARBLOS : I2C arbitration loss flag (Master mode) + * @arg I2C_FLAG_RXNACK : I2C received not acknowledge flag + * @arg I2C_FLAG_BUSERR : I2C bus error flag + * @arg I2C_FLAG_RXDNE : I2C Rx data not empty flag + * @arg I2C_FLAG_TXDE : I2C Tx data empty flag + * @arg I2C_FLAG_RXBF : I2C RX buffer full flag + * @arg I2C_FLAG_BUSBUSY : I2C bus busy flag + * @arg I2C_FLAG_MASTER : I2C master mode flag (Master flag) + * @arg I2C_FLAG_TXNRX : I2C transmitter mode flag + * @retval SET or RESET + ************************************************************************************************************/ +FlagStatus I2C_GetFlagStatus(HT_I2C_TypeDef* I2Cx, u32 I2C_Flag) +{ + /* Check the parameters */ + Assert_Param(IS_I2C(I2Cx)); + Assert_Param(IS_I2C_FLAG(I2C_Flag)); + + if ((I2Cx->SR & I2C_Flag) != (u32)RESET) + { + return (SET); + } + else + { + return (RESET); + } +} + +/*********************************************************************************************************//** + * @brief Check whether the specified I2C status has been active. + * @param I2Cx: where I2Cx is the selected I2C from the I2C peripherals. + * @param I2C_Status: specify the flag that is to be check. + * This parameter can be one of the following values: + * @arg I2C_MASTER_SEND_START + * @arg I2C_MASTER_RECEIVER_MODE + * @arg I2C_MASTER_TRANSMITTER_MODE + * @arg I2C_MASTER_RX_NOT_EMPTY + * @arg I2C_MASTER_RX_NOT_EMPTY_NOBUSY + * @arg I2C_MASTER_TX_EMPTY + * @arg I2C_MASTER_RX_BUFFER_FULL + * @arg I2C_SLAVE_ACK_TRANSMITTER_ADDRESS + * @arg I2C_SLAVE_ACK_RECEIVER_ADDRESS + * @arg I2C_SLAVE_ACK_GCALL_ADDRESS + * @arg I2C_SLAVE_RX_NOT_EMPTY + * @arg I2C_SLAVE_RX_NOT_EMPTY_STOP + * @arg I2C_SLAVE_TX_EMPTY + * @arg I2C_SLAVE_RX_BUFFER_FULL + * @arg I2C_SLAVE_RECEIVED_NACK + * @arg I2C_SLAVE_RECEIVED_NACK_STOP + * @arg I2C_SLAVE_STOP_DETECTED + * @retval SUCCESS or ERROR + ************************************************************************************************************/ +ErrStatus I2C_CheckStatus(HT_I2C_TypeDef* I2Cx, u32 I2C_Status) +{ + /* Check the parameters */ + Assert_Param(IS_I2C(I2Cx)); + Assert_Param(IS_I2C_STATUS(I2C_Status)); + + if (I2Cx->SR == I2C_Status) + { + return (SUCCESS); + } + else + { + return (ERROR); + } +} + +/*********************************************************************************************************//** + * @brief Clear the specified I2C flag. + * @param I2Cx: where I2Cx is the selected I2C from the I2C peripherals. + * @param I2C_Flag: specify the flag that is to be cleared. + * This parameter can be one of the following values: + * @arg I2C_FLAG_ARBLOS : I2C arbitration flag + * @arg I2C_FLAG_RXNACK : I2C receive not acknowledge flag + * @arg I2C_FLAG_BUSERR : I2C Bus error flag + * @retval None + ************************************************************************************************************/ +void I2C_ClearFlag(HT_I2C_TypeDef* I2Cx, u32 I2C_Flag) +{ + /* Check the parameters */ + Assert_Param(IS_I2C(I2Cx)); + Assert_Param(IS_I2C_CLEAR_FLAG(I2C_Flag)); + + I2Cx->SR = I2C_Flag; +} + +/*********************************************************************************************************//** + * @brief Set the interval timing of the high period of the I2C clock. + * @param I2Cx: where I2Cx is the selected I2C from the I2C peripherals. + * @param I2C_HighPeriod: specify the high period that is to be set. + * This parameter must be a number between 0 and 0xFFFF. + * @retval None + ************************************************************************************************************/ +void I2C_SetSCLHighPeriod(HT_I2C_TypeDef* I2Cx, u32 I2C_HighPeriod) +{ + /* Check the parameters */ + Assert_Param(IS_I2C(I2Cx)); + Assert_Param(IS_I2C_SCL_HIGH(I2C_HighPeriod)); + + I2Cx->SHPGR = I2C_HighPeriod; +} + +/*********************************************************************************************************//** + * @brief Set the interval timing of low period of the I2C clock. + * @param I2Cx: where I2Cx is the selected I2C from the I2C peripherals. + * @param I2C_LowPeriod: specify the low period that is to be set. + * This parameter must be a number between 0 and 0xFFFF. + * @retval None + ************************************************************************************************************/ +void I2C_SetSCLLowPeriod(HT_I2C_TypeDef* I2Cx, u32 I2C_LowPeriod) +{ + /* Check the parameters */ + Assert_Param(IS_I2C(I2Cx)); + Assert_Param(IS_I2C_SCL_LOW(I2C_LowPeriod)); + + I2Cx->SLPGR = I2C_LowPeriod; +} + +/*********************************************************************************************************//** + * @brief Enable or Disable the I2Cx PDMA interface. + * @param I2Cx: where I2Cx is the selected I2C from the I2C peripherals. + * @param I2C_PDMAREQ: specify the I2C PDMA transfer request to be enabled or disabled. + * This parameter can be any combination of the following values: + * @arg I2C_PDMAREQ_TX: Tx PDMA transfer request + * @arg I2C_PDMAREQ_RX: Rx PDMA transfer request + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void I2C_PDMACmd(HT_I2C_TypeDef* I2Cx, u32 I2C_PDMAREQ, ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_I2C(I2Cx)); + Assert_Param(IS_I2C_PDMA_REQ(I2C_PDMAREQ)); + Assert_Param(IS_CONTROL_STATUS(NewState)); + + if (NewState != DISABLE) + { + I2Cx->CR |= I2C_PDMAREQ; + } + else + { + I2Cx->CR &= ~I2C_PDMAREQ; + } +} + +/*********************************************************************************************************//** + * @brief Specify that the next PDMA transfer is the last one. + * @param I2Cx: where I2Cx is the selected I2C from the I2C peripherals. + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void I2C_PDMANACKCmd(HT_I2C_TypeDef* I2Cx, ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_I2C(I2Cx)); + Assert_Param(IS_CONTROL_STATUS(NewState)); + + if (NewState != DISABLE) + { + I2Cx->CR |= CR_PDMANACK_SET; + } + else + { + I2Cx->CR &= CR_PDMANACK_RESET; + } +} + +/*********************************************************************************************************//** + * @brief Enable or Disable the specified I2C time out function. + * @param I2Cx: where I2Cx is the selected I2C from the I2C peripherals. + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void I2C_TimeOutCmd(HT_I2C_TypeDef* I2Cx, ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_I2C(I2Cx)); + Assert_Param(IS_CONTROL_STATUS(NewState)); + + if (NewState != DISABLE) + { + I2Cx->CR |= CR_ENTOUT_SET; + } + else + { + I2Cx->CR &= CR_ENTOUT_RESET; + } +} + +/*********************************************************************************************************//** + * @brief This function is used to set the I2C timeout value. + * @param I2Cx: where I2Cx is the selected I2C from the I2C peripherals. + * @param I2C_Timeout: specify the timeout value. + * @retval None + ************************************************************************************************************/ +void I2C_SetTimeOutValue(HT_I2C_TypeDef* I2Cx, u32 I2C_Timeout) +{ + /* Check the parameters */ + Assert_Param(IS_I2C(I2Cx)); + Assert_Param(IS_I2C_TIMEOUT(I2C_Timeout)); + + I2Cx->TOUT = (I2C_Timeout | (I2Cx->TOUT & 0xFFFF0000)); +} + +/*********************************************************************************************************//** + * @brief This function is used to set the prescaler of I2C timeout value. + * @param I2Cx: where I2Cx is the selected I2C from the I2C peripherals. + * @param I2C_Prescaler: specify the I2C time out prescaler value. + * This parameter can be one of the following values: + * @arg I2C_PRESCALER_1 : I2C prescaler set to 1 + * @arg I2C_PRESCALER_2 : I2C prescaler set to 2 + * @arg I2C_PRESCALER_4 : I2C prescaler set to 4 + * @arg I2C_PRESCALER_16 : I2C prescaler set to 16 + * @arg I2C_PRESCALER_32 : I2C prescaler set to 32 + * @arg I2C_PRESCALER_64 : I2C prescaler set to 64 + * @arg I2C_PRESCALER_128 : I2C prescaler set to 128 + * @retval None + ************************************************************************************************************/ +void I2C_SetTimeOutPrescaler(HT_I2C_TypeDef* I2Cx, u32 I2C_Prescaler) +{ + /* Check the parameters */ + Assert_Param(IS_I2C(I2Cx)); + Assert_Param(IS_I2C_PRESCALER(I2C_Prescaler)); + + I2Cx->TOUT = (I2C_Prescaler | (I2Cx->TOUT & 0x0000FFFF)); +} + +/*********************************************************************************************************//** + * @brief This function is used to determine the prescaler of I2C timeout value. + * @param I2Cx: where I2Cx is the selected I2C from the I2C peripherals. + * @param I2C_Mask: specify the bit position of I2C slave address to be masked. + * This parameter can be any combination of the following values: + * @arg I2C_MASKBIT_0 : Bit 0 of I2C slave address is masked + * @arg I2C_MASKBIT_1 : Bit 1 of I2C slave address is masked + * @arg I2C_MASKBIT_2 : Bit 2 of I2C slave address is masked + * @arg I2C_MASKBIT_3 : Bit 3 of I2C slave address is masked + * @arg I2C_MASKBIT_4 : Bit 4 of I2C slave address is masked + * @arg I2C_MASKBIT_5 : Bit 5 of I2C slave address is masked + * @arg I2C_MASKBIT_6 : Bit 6 of I2C slave address is masked + * @arg I2C_MASKBIT_7 : Bit 7 of I2C slave address is masked + * @arg I2C_MASKBIT_8 : Bit 8 of I2C slave address is masked + * @arg I2C_MASKBIT_9 : Bit 9 of I2C slave address is masked + * @retval None + ************************************************************************************************************/ +void I2C_AddressMaskConfig(HT_I2C_TypeDef* I2Cx, u32 I2C_Mask) +{ + /* Check the parameters */ + Assert_Param(IS_I2C(I2Cx)); + Assert_Param(IS_I2C_ADDRESS_MASK(I2C_Mask)); + + I2Cx->ADDMR = I2C_Mask; +} + +/*********************************************************************************************************//** + * @brief Return the received address by the I2Cx peripheral. + * @param I2Cx: where I2Cx is the selected I2C from the I2C peripherals. + * @retval The value of the received address. + ************************************************************************************************************/ +u16 I2C_GetAddressBuffer(HT_I2C_TypeDef* I2Cx) +{ + /* Check the parameters */ + Assert_Param(IS_I2C(I2Cx)); + + return ((u16)I2Cx->ADDSR); +} + +/*********************************************************************************************************//** + * @brief Enable or Disable the combinational filter. + * @param I2Cx: where I2Cx is the selected I2C from the I2C peripherals. + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void I2C_CombFilterCmd(HT_I2C_TypeDef* I2Cx, ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_I2C(I2Cx)); + Assert_Param(IS_CONTROL_STATUS(NewState)); + + if (NewState != DISABLE) + { + I2Cx->CR |= CR_COMBFILTER_SET; + } + else + { + I2Cx->CR &= CR_COMBFILTER_RESET; + } +} + +/*********************************************************************************************************//** + * @brief This function is used to determine the filter glitch width of 0~2 PCLK. + * @param I2Cx: where I2Cx is the selected I2C from the I2C peripherals. + * @param Seq_Filter_Select: specify the glitch width of 0~2 PCLK. + * This parameter can be any combination of the following values: + * @arg SEQ_FILTER_DISABLE : sequential filter is disabled + * @arg SEQ_FILTER_1_PCLK : filter glitch width of 1 PCLK + * @arg SEQ_FILTER_2_PCLK : filter glitch width of 2 PCLK + * @retval None + ************************************************************************************************************/ +void I2C_SequentialFilterConfig(HT_I2C_TypeDef* I2Cx, u32 Seq_Filter_Select) +{ + u32 SHPGR = I2Cx->SHPGR; + u32 SLPGR = I2Cx->SLPGR; + + /* Check the parameters */ + Assert_Param(IS_I2C(I2Cx)); + Assert_Param(IS_I2C_SEQ_FILTER_MASK(Seq_Filter_Select)); + + switch (I2Cx->CR & 0xC000) + { + case 0: + if (Seq_Filter_Select == SEQ_FILTER_1_PCLK) + { + if (SHPGR >= 2) + { + SHPGR -= 2; + SLPGR -= 2; + } + } + else if (Seq_Filter_Select == SEQ_FILTER_2_PCLK) + { + if (SHPGR >= 2) + { + SHPGR -= 3; + SLPGR -= 3; + } + } + break; + + case 0x4000: + if (Seq_Filter_Select == SEQ_FILTER_DISABLE) + { + SHPGR += 2; + SLPGR += 2; + } + else if (Seq_Filter_Select == SEQ_FILTER_2_PCLK) + { + if (SHPGR >= 1) + { + SHPGR -= 1; + SLPGR -= 1; + } + } + break; + + case 0x8000: + if (Seq_Filter_Select == SEQ_FILTER_DISABLE) + { + SHPGR += 3; + SLPGR += 3; + } + else if (Seq_Filter_Select == SEQ_FILTER_1_PCLK) + { + SHPGR += 1; + SLPGR += 1; + } + break; + + default: + break; + } + + I2Cx->SHPGR = SHPGR; + I2Cx->SLPGR = SLPGR; + I2Cx->CR = (I2Cx->CR & 0x3FFF) | Seq_Filter_Select; +} +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ diff --git a/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/src/ht32f1xxxx_i2s.c b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/src/ht32f1xxxx_i2s.c new file mode 100644 index 0000000000..b269844127 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/src/ht32f1xxxx_i2s.c @@ -0,0 +1,336 @@ +/*********************************************************************************************************//** + * @file ht32f1xxxx_i2s.c + * @version $Rev:: 2140 $ + * @date $Date:: 2020-07-23 #$ + * @brief This file provides all the I2S firmware functions. + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ + +/* Includes ------------------------------------------------------------------------------------------------*/ +#include "ht32f1xxxx_i2s.h" + +/** @addtogroup HT32F1xxxx_Peripheral_Driver HT32F1xxxx Peripheral Driver + * @{ + */ + +/** @defgroup I2S I2S + * @brief I2S driver modules + * @{ + */ + + +/* Private constants ---------------------------------------------------------------------------------------*/ +/** @defgroup I2S_Private_Define I2S private definitions + * @{ + */ +#define I2S_EN (1UL) +#define MCLK_OP_EN (1UL << 9) +#define TX_MUTE_EN (1UL << 12) +#define CLK_DIV_EN (1UL << 15) +#define BCLK_INV_EN (1UL << 18) +#define MCLK_INV_EN (1UL << 19) + +#define I2S_SLAVE (1UL << 3) +/** + * @} + */ + + +/* Global functions ----------------------------------------------------------------------------------------*/ +/** @defgroup I2S_Exported_Functions I2S exported functions + * @{ + */ +/*********************************************************************************************************//** + * @brief Deinitialize the I2S peripheral registers to their default reset values. + * @retval None + ************************************************************************************************************/ +void I2S_DeInit(void) +{ + RSTCU_PeripReset_TypeDef RSTCUReset = {{0}}; + + RSTCUReset.Bit.I2S = 1; + RSTCU_PeripReset(RSTCUReset, ENABLE); +} + +/*********************************************************************************************************//** + * @brief Initialize the I2S peripheral according to the specified parameters in the I2S_InitStruct. + * @param I2S_InitStruct: pointer to a I2S_InitTypeDef structure. + * @retval None + ************************************************************************************************************/ +void I2S_Init(I2S_InitTypeDef* I2S_InitStruct) +{ + /* Check the parameters */ + Assert_Param(IS_I2S_MODE(I2S_InitStruct->I2S_Mode)); + Assert_Param(IS_I2S_FORMAT(I2S_InitStruct->I2S_Format)); + Assert_Param(IS_I2S_WORD_WIDTH(I2S_InitStruct->I2S_WordWidth)); + Assert_Param(IS_I2S_MCLK_DIV(I2S_InitStruct->I2S_X_Div, I2S_InitStruct->I2S_Y_Div)); + Assert_Param(IS_I2S_BCLK_DIV(I2S_InitStruct->I2S_N_Div)); + + HT_I2S->CR = I2S_InitStruct->I2S_Mode | I2S_InitStruct->I2S_Format | I2S_InitStruct->I2S_WordWidth; + + if (I2S_InitStruct->I2S_BclkInv == ENABLE) + { + HT_I2S->CR |= BCLK_INV_EN; + } + + if (I2S_InitStruct->I2S_MclkInv == ENABLE) + { + HT_I2S->CR |= MCLK_INV_EN; + } + + if ((I2S_InitStruct->I2S_Mode & I2S_SLAVE) == RESET) + { + HT_I2S->CDR = (I2S_InitStruct->I2S_N_Div << 16) | (I2S_InitStruct->I2S_X_Div << 8) | + (I2S_InitStruct->I2S_Y_Div); + HT_I2S->CR |= CLK_DIV_EN; + while (I2S_GetFlagStatus(I2S_FLAG_CLK_RDY) == RESET); + + if (I2S_InitStruct->I2S_MclkOut == ENABLE) + { + HT_I2S->CR |= MCLK_OP_EN; + } + } +} + +/*********************************************************************************************************//** + * @brief Enable or Disable the I2S peripheral. + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void I2S_Cmd(ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_CONTROL_STATUS(NewState)); + + if (NewState != DISABLE) + { + HT_I2S->CR |= I2S_EN; + } + else + { + HT_I2S->CR &= ~I2S_EN; + } +} + +/*********************************************************************************************************//** + * @brief Enable or Disable the Tx mute for the I2S peripheral. + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void I2S_TxMuteCmd(ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_CONTROL_STATUS(NewState)); + + if (NewState != DISABLE) + { + HT_I2S->CR |= TX_MUTE_EN; + } + else + { + HT_I2S->CR &= ~TX_MUTE_EN; + } +} + +/*********************************************************************************************************//** + * @brief Enable or Disable the I2S PDMA interface. + * @param I2S_PDMAREQ: specify the I2S PDMA transfer request to be enabled or disabled. + * This parameter can be any combination of the following values: + * @arg I2S_PDMAREQ_TX : Tx PDMA transfer request + * @arg I2S_PDMAREQ_RX : Rx PDMA transfer request + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void I2S_PDMACmd(u32 I2S_PDMAREQ, ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_I2S_PDMA_REQ(I2S_PDMAREQ)); + Assert_Param(IS_CONTROL_STATUS(NewState)); + + if (NewState != DISABLE) + { + HT_I2S->CR |= I2S_PDMAREQ; + } + else + { + HT_I2S->CR &= I2S_PDMAREQ; + } +} + +/*********************************************************************************************************//** + * @brief Reset the specified I2S FIFO. + * @param I2S_FIFO: specify the FIFO that is to be reset. + * This parameter can be any combination of the following values: + * @arg I2S_TX_FIFO : I2S Tx FIFO + * @arg I2S_RX_FIFO : I2S Rx FIFO + * @retval None + ************************************************************************************************************/ +void I2S_FIFOReset(u32 I2S_FIFO) +{ + /* Check the parameters */ + Assert_Param(IS_I2S_TWO_FIFO(I2S_FIFO)); + + HT_I2S->FCR |= I2S_FIFO; +} + +/*********************************************************************************************************//** + * @brief Set the trigger level of specified I2S FIFO. + * @param I2S_FIFO: specify the FIFO that is to be set. + * This parameter can be any combination of the following values: + * @arg I2S_TX_FIFO : I2S Tx FIFO + * @arg I2S_RX_FIFO : I2S Rx FIFO + * @param I2S_FIFOLevel: Specify the FIFO trigger level. + * @retval None + ************************************************************************************************************/ +void I2S_FIFOTrigLevelConfig(u32 I2S_FIFO, u32 I2S_FIFOLevel) +{ + /* Check the parameters */ + Assert_Param(IS_I2S_TWO_FIFO(I2S_FIFO)); + Assert_Param(IS_I2S_FIFO_LEVEL(I2S_FIFOLevel)); + + if (I2S_FIFO == I2S_TX_FIFO) + { + HT_I2S->FCR = ((HT_I2S->FCR & (~0x0000000F)) | I2S_FIFOLevel); + } + else + { + HT_I2S->FCR = ((HT_I2S->FCR & (~0x000000F0)) | (I2S_FIFOLevel << 4)); + } +} + +/*********************************************************************************************************//** + * @brief Return the status of specified I2S FIFO. + * @param I2S_FIFO: specify the FIFO that is to be checked. + * This parameter can be one of the following values: + * @arg I2S_TX_FIFO : I2S Tx FIFO + * @arg I2S_RX_FIFO : I2S Rx FIFO + * @retval The number of data in specified I2S FIFO. + ************************************************************************************************************/ +u8 I2S_GetFIFOStatus(u32 I2S_FIFO) +{ + /* Check the parameters */ + Assert_Param(IS_I2S_ONE_FIFO(I2S_FIFO)); + + if (I2S_FIFO == I2S_TX_FIFO) + { + return (u8)((HT_I2S->SR >> 24) & 0x0F); + } + else + { + return (u8)(HT_I2S->SR >> 28); + } +} + +/*********************************************************************************************************//** + * @brief Enable or Disable the I2S interrupt. + * @param I2S_Int: specify if the I2S interrupt source to be enabled or disabled. + * This parameter can be any combination of the following values: + * @arg I2S_INT_TXFIFO_TRI : I2S Tx FIFO trigger level interrupt + * @arg I2S_INT_TXFIFO_UF : I2S Rx FIFO underflow interrupt + * @arg I2S_INT_TXFIFO_OV : I2S Tx FIFO overflow interrupt + * @arg I2S_INT_RXFIFO_TRI : I2S Rx FIFO trigger level interrupt + * @arg I2S_INT_RXFIFO_UV : I2S Rx FIFO underflow interrupt + * @arg I2S_INT_RXFIFO_OV : I2S Rx FIFO overflow interrupt + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void I2S_IntConfig(u32 I2S_Int, ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_I2S_INT(I2S_Int)); + Assert_Param(IS_CONTROL_STATUS(NewState)); + + if (NewState != DISABLE) + { + HT_I2S->IER |= I2S_Int; + } + else + { + HT_I2S->IER &= ~I2S_Int; + } +} + +/*********************************************************************************************************//** + * @brief Check whether the specified I2S flag has been set or not. + * @param I2S_Flag: specify the flag that is to be check. + * This parameter can be one of the following values: + * @arg I2S_FLAG_TXFIFO_TRI : I2S Tx FIFO trigger level flag + * @arg I2S_FLAG_TXFIFO_UDF : I2S Tx FIFO underflow flag + * @arg I2S_FLAG_TXFIFO_OVF : I2S Tx FIFO overflow flag + * @arg I2S_FLAG_TXFIFO_EMP : I2S Tx FIFO empty flag + * @arg I2S_FLAG_TXFIFO_FUL : I2S Tx FIFO full flag + * @arg I2S_FLAG_RXFIFO_TRI : I2S Rx FIFO trigger level flag + * @arg I2S_FLAG_RXFIFO_UDF : I2S Rx FIFO underflow flag + * @arg I2S_FLAG_RXFIFO_OVF : I2S Rx FIFO overflow flag + * @arg I2S_FLAG_RXFIFO_EMP : I2S Rx FIFO empty flag + * @arg I2S_FLAG_RXFIFO_FUL : I2S Rx FIFO full flag + * @arg I2S_FLAG_RIGHT_CH : I2S right channel flag + * @arg I2S_FLAG_TX_BUSY : I2S Tx busy flag + * @arg I2S_FLAG_CLK_RDY : I2S clock ready flag + * @retval SET or RESET + ************************************************************************************************************/ +FlagStatus I2S_GetFlagStatus(u32 I2S_Flag) +{ + /* Check the parameters */ + Assert_Param(IS_I2S_FLAG(I2S_Flag)); + + if (HT_I2S->SR & I2S_Flag) + { + return SET; + } + else + { + return RESET; + } +} + +/*********************************************************************************************************//** + * @brief Clear the specified I2S flag. + * @param I2S_Flag: specify the flag that is to be cleared. + * This parameter can be any combination of the following values: + * @arg I2S_FLAG_TXFIFO_TRI : I2S Tx FIFO trigger level flag + * @arg I2S_FLAG_TXFIFO_UV : I2S Tx FIFO underflow flag + * @arg I2S_FLAG_TXFIFO_OV : I2S Tx FIFO overflow flag + * @arg I2S_FLAG_RXFIFO_TRI : I2S Rx FIFO trigger level flag + * @arg I2S_FLAG_RXFIFO_UV : I2S Rx FIFO underflow flag + * @arg I2S_FLAG_RXFIFO_OV : I2S Rx FIFO overflow flag + * @retval None + ************************************************************************************************************/ +void I2S_ClearFlag(u32 I2S_Flag) +{ + /* Check the parameters */ + Assert_Param(IS_I2S_FLAG_CLEAR(I2S_Flag)); + + HT_I2S->SR = I2S_Flag; +} +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ diff --git a/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/src/ht32f1xxxx_mctm.c b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/src/ht32f1xxxx_mctm.c new file mode 100644 index 0000000000..a77c3858b2 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/src/ht32f1xxxx_mctm.c @@ -0,0 +1,253 @@ +/*********************************************************************************************************//** + * @file ht32f1xxxx_mctm.c + * @version $Rev:: 2797 $ + * @date $Date:: 2022-11-28 #$ + * @brief This file provides all the MCTM firmware functions. + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ + +/* Includes ------------------------------------------------------------------------------------------------*/ +#include "ht32f1xxxx_mctm.h" + +/** @addtogroup HT32F1xxxx_Peripheral_Driver HT32F1xxxx Peripheral Driver + * @{ + */ + +/** @defgroup MCTM MCTM + * @brief MCTM driver modules + * @{ + */ + + +/* Private constants ---------------------------------------------------------------------------------------*/ +/** @defgroup MCTM_Private_Define MCTM private definitions + * @{ + */ +#define CTR_COMPRE 0x00000100ul +#define CTR_COMUS 0x00000200ul + +#define CHBRKCTR_CHMOE 0x00000010ul +/** + * @} + */ + + +/* Global functions ----------------------------------------------------------------------------------------*/ +/** @defgroup MCTM_Exported_Functions MCTM exported functions + * @{ + */ + +/*********************************************************************************************************//** + * @brief Configure polarity of the MCTMx channel N. + * @param MCTMx: where MCTMx is the selected MCTM from the MCTM peripheral. + * @param Channel: Specify the MCTM channel. + * This parameter can be one of the following values: + * @arg MCTM_CH_0 : MCTM channel 0 + * @arg MCTM_CH_1 : MCTM channel 1 + * @arg MCTM_CH_2 : MCTM channel 2 + * @arg MCTM_CH_3 : MCTM channel 3 + * @param Pol: Specify the polarity of channel N. + * This parameter can be one of the following values: + * @arg MCTM_CHP_NONINVERTED : active high + * @arg MCTM_CHP_INVERTED : active low + * @retval None + ************************************************************************************************************/ +void MCTM_ChNPolarityConfig(HT_TM_TypeDef* MCTMx, TM_CH_Enum Channel, TM_CHP_Enum Pol) +{ + u32 wChpolr; + + /* Check the parameters */ + Assert_Param(IS_MCTM(MCTMx)); + Assert_Param(IS_MCTM_COMPLEMENTARY_CH(Channel)); + Assert_Param(IS_TM_CHP(Pol)); + + /* Set or reset the CHxN polarity */ + wChpolr = MCTMx->CHPOLR & (~(u32)(0x2 << (Channel << 1))); + MCTMx->CHPOLR = wChpolr | ((Pol << 1) << (Channel << 1)); +} + +/*********************************************************************************************************//** + * @brief Enable or Disable the MCTMx channel N. + * @param MCTMx: where MCTMx is the selected MCTM from the MCTM peripheral. + * @param Channel: Specify the MCTM channel. + * This parameter can be one of the following values: + * @arg MCTM_CH_0 : MCTM channel 0 + * @arg MCTM_CH_1 : MCTM channel 1 + * @arg MCTM_CH_2 : MCTM channel 2 + * @arg MCTM_CH_3 : MCTM channel 3 + * @param Control: This parameter can be TM_CHCTL_ENABLE or TM_CHCTL_DISABLE. + * @retval None + ************************************************************************************************************/ +void MCTM_ChannelNConfig(HT_TM_TypeDef* MCTMx, TM_CH_Enum Channel, TM_CHCTL_Enum Control) +{ + /* Check the parameters */ + Assert_Param(IS_MCTM(MCTMx)); + Assert_Param(IS_MCTM_COMPLEMENTARY_CH(Channel)); + Assert_Param(IS_TM_CHCTL(Control)); + + /* Reset the CHxNE Bit */ + MCTMx->CHCTR &= ~(u32)(0x2 << (Channel << 1)); + + /* Set or reset the CHxNE Bit */ + MCTMx->CHCTR |= (u32)(Control << 1) << (Channel << 1); +} + +/*********************************************************************************************************//** + * @brief Enable or Disable the channels main output of the MCTMx. + * @param MCTMx: where MCTMx is the selected MCTM from the MCTM peripherals. + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void MCTM_CHMOECmd(HT_TM_TypeDef* MCTMx, ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_MCTM(MCTMx)); + Assert_Param(IS_CONTROL_STATUS(NewState)); + + if (NewState != DISABLE) + { + /* Enable the MCTM Main Output */ + MCTMx->CHBRKCTR |= CHBRKCTR_CHMOE; + } + else + { + /* Disable the MCTM Main Output */ + MCTMx->CHBRKCTR &= ~CHBRKCTR_CHMOE; + } +} + +/*********************************************************************************************************//** + * @brief Configure the break feature, dead time, Lock level, the OSSI, the OSSR State + * and the CHAOE(automatic output enable). + * @param MCTMx: where MCTMx is the selected MCTM from the MCTM peripherals. + * @param CHBRKCTRInit: Point to a MCTM_CHBRKCTRInitTypeDef structure. + * @retval None + ************************************************************************************************************/ +void MCTM_CHBRKCTRConfig(HT_TM_TypeDef* MCTMx, MCTM_CHBRKCTRInitTypeDef *CHBRKCTRInit) +{ + u32 wTmpReg; + + /* Check the parameters */ + Assert_Param(IS_MCTM(MCTMx)); + Assert_Param(IS_MCTM_OSSR_STATE(CHBRKCTRInit->OSSRState)); + Assert_Param(IS_MCTM_OSSI_STATE(CHBRKCTRInit->OSSIState)); + Assert_Param(IS_MCTM_LOCK_LEVEL(CHBRKCTRInit->LockLevel)); + Assert_Param(IS_MCTM_BREAK_STATE(CHBRKCTRInit->Break0)); + Assert_Param(IS_MCTM_BREAK_POLARITY(CHBRKCTRInit->Break0Polarity)); + Assert_Param(IS_MCTM_BREAK_STATE(CHBRKCTRInit->Break1)); + Assert_Param(IS_MCTM_BREAK_POLARITY(CHBRKCTRInit->Break1Polarity)); + Assert_Param(IS_MCTM_CHAOE_STATE(CHBRKCTRInit->AutomaticOutput)); + Assert_Param(IS_TM_FILTER(CHBRKCTRInit->BreakFilter)); + + wTmpReg = MCTMx->CHBRKCTR & 0x00000010; // Keep CHMOE + wTmpReg |= (u32)CHBRKCTRInit->BreakFilter << 8; + wTmpReg |= (u32)CHBRKCTRInit->DeadTime << 24; + wTmpReg |= CHBRKCTRInit->LockLevel | CHBRKCTRInit->OSSRState | CHBRKCTRInit->OSSIState; + wTmpReg |= CHBRKCTRInit->Break0 | CHBRKCTRInit->Break0Polarity | CHBRKCTRInit->AutomaticOutput; + wTmpReg |= (CHBRKCTRInit->Break1 << 2) | (CHBRKCTRInit->Break1Polarity << 2); + + MCTMx->CHBRKCTR = wTmpReg; +} + +/*********************************************************************************************************//** + * @brief Fill each CHBRKCTRInitStruct member with its default value. + * @param CHBRKCTRInitStruct: Point to a MCTM_CHBRKCTRInitTypeDef structure. + * @retval None + ************************************************************************************************************/ +void MCTM_CHBRKCTRStructInit(MCTM_CHBRKCTRInitTypeDef* CHBRKCTRInitStruct) +{ + /* Set the default configuration */ + CHBRKCTRInitStruct->OSSRState = MCTM_OSSR_STATE_DISABLE; + CHBRKCTRInitStruct->OSSIState = MCTM_OSSI_STATE_DISABLE; + CHBRKCTRInitStruct->LockLevel = MCTM_LOCK_LEVEL_OFF; + CHBRKCTRInitStruct->DeadTime = 0x00; + CHBRKCTRInitStruct->Break0 = MCTM_BREAK_DISABLE; + CHBRKCTRInitStruct->Break0Polarity = MCTM_BREAK_POLARITY_LOW; + CHBRKCTRInitStruct->Break1 = MCTM_BREAK_DISABLE; + CHBRKCTRInitStruct->Break1Polarity = MCTM_BREAK_POLARITY_LOW; + CHBRKCTRInitStruct->BreakFilter = 0; + CHBRKCTRInitStruct->AutomaticOutput = MCTM_CHAOE_DISABLE; +} + +/*********************************************************************************************************//** + * @brief Enable or Disable MCTMx COMPRE function. + * @param MCTMx: where MCTMx is the selected MCTM from the MCTM peripherals. + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void MCTM_COMPRECmd(HT_TM_TypeDef* MCTMx, ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_MCTM(MCTMx)); + Assert_Param(IS_CONTROL_STATUS(NewState)); + + if (NewState != DISABLE) + { + /* Enable the MCTM COMPRE */ + MCTMx->CTR |= CTR_COMPRE; + } + else + { + /* Disable the MCTM COMPRE */ + MCTMx->CTR &= ~CTR_COMPRE; + } +} + +/*********************************************************************************************************//** + * @brief Configure the MCTMx COMUS function. + * @param MCTMx: where MCTMx is the selected MCTM from the MCTM peripherals. + * @param Sel: Specify the COMUS value. + * This parameter can be one of the following values: + * @arg MCTM_COMUS_STIOFF : MCTM capture/compare control bits are updated by setting the UEV2G bit only + * @arg MCTM_COMUS_STION : MCTM capture/compare control bits are updated by both setting the UEV2G bit + * or when a rising edge occurs on STI + * @retval None + ************************************************************************************************************/ +void MCTM_COMUSConfig(HT_TM_TypeDef* MCTMx, MCTM_COMUS_Enum Sel) +{ + /* Check the parameters */ + Assert_Param(IS_MCTM(MCTMx)); + Assert_Param(IS_MCTM_COMUS(Sel)); + + if (Sel != MCTM_COMUS_STIOFF) + { + /* Set the MCTM COMUS bit */ + MCTMx->CTR |= CTR_COMUS; + } + else + { + /* Clear the MCTM COMUS bit */ + MCTMx->CTR &= ~CTR_COMUS; + } +} +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ diff --git a/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/src/ht32f1xxxx_pdma.c b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/src/ht32f1xxxx_pdma.c new file mode 100644 index 0000000000..8a816d946f --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/src/ht32f1xxxx_pdma.c @@ -0,0 +1,341 @@ +/*********************************************************************************************************//** + * @file ht32f1xxxx_pdma.c + * @version $Rev:: 2717 $ + * @date $Date:: 2022-08-20 #$ + * @brief This file provides all the PDMA firmware functions. + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ + +/* Includes ------------------------------------------------------------------------------------------------*/ +#include "ht32f1xxxx_pdma.h" + +/** @addtogroup HT32F1xxxx_Peripheral_Driver HT32F1xxxx Peripheral Driver + * @{ + */ + +/** @defgroup PDMA PDMA + * @brief PDMA driver modules + * @{ + */ + + +/* Global functions ----------------------------------------------------------------------------------------*/ +/** @defgroup PDMA_Exported_Functions PDMA exported functions + * @{ + */ +/*********************************************************************************************************//** + * @brief Deinitialize the PDMA peripheral registers to their default reset values. + * @retval None + ************************************************************************************************************/ +void PDMA_DeInit(void) +{ + RSTCU_PeripReset_TypeDef RSTCUReset = {{0}}; + + RSTCUReset.Bit.PDMA = 1; + RSTCU_PeripReset(RSTCUReset, ENABLE); +} + +/*********************************************************************************************************//** + * @brief Configure specific PDMA channel + * @param PDMA_CHn: PDMA_CH0 ~ PDMA_CH5 + * PDMA_CH0 ~ PDMA_CH7 + * PDMA_CH8 ~ PDMA_CH11 (For specific models only) + * @param PDMACH_InitStruct: pointer to a PDMACH_InitTypeDef structure. + * @retval None + ************************************************************************************************************/ +void PDMA_Config(u32 PDMA_CHn, PDMACH_InitTypeDef *PDMACH_InitStruct) +{ + HT_PDMACH_TypeDef *PDMACHx = (HT_PDMACH_TypeDef *)(HT_PDMA_BASE + PDMA_CHn * 6 * 4); + + /* Check the parameters */ + Assert_Param(IS_PDMA_CH(PDMA_CHn)); + Assert_Param(IS_PDMA_WIDTH(PDMACH_InitStruct->PDMACH_DataSize)); + Assert_Param(IS_PDMA_PRIO(PDMACH_InitStruct->PDMACH_Priority)); + Assert_Param(IS_PDMA_ADR_MOD(PDMACH_InitStruct->PDMACH_AdrMod)); + Assert_Param(IS_PDMA_BLK_CNT(PDMACH_InitStruct->PDMACH_BlkCnt)); + Assert_Param(IS_PDMA_BLK_LEN(PDMACH_InitStruct->PDMACH_BlkLen)); + + /* PDMA channel x configuration */ + PDMACHx->CR = (PDMACH_InitStruct->PDMACH_DataSize | PDMACH_InitStruct->PDMACH_Priority | PDMACH_InitStruct->PDMACH_AdrMod); + + PDMACHx->SADR = PDMACH_InitStruct->PDMACH_SrcAddr; + + PDMACHx->DADR = PDMACH_InitStruct->PDMACH_DstAddr; + + PDMACHx->TSR = (PDMACH_InitStruct->PDMACH_BlkCnt << 16) | PDMACH_InitStruct->PDMACH_BlkLen; +} + +/*********************************************************************************************************//** + * @brief PDMA_AddrConfig + * @param PDMA_CHn: PDMA_CH0 ~ PDMA_CH5 + * @param SrcAddr: Source address + * @param DstAddr: Destination address + * @retval None + ************************************************************************************************************/ +void PDMA_AddrConfig(u32 PDMA_CHn, u32 SrcAddr, u32 DstAddr) +{ + HT_PDMACH_TypeDef *PDMACHx = (HT_PDMACH_TypeDef *)(HT_PDMA_BASE + PDMA_CHn * 6 * 4); + + /* Check the parameters */ + Assert_Param(IS_PDMA_CH(PDMA_CHn)); + + /* transfer address configuration */ + PDMACHx->SADR = SrcAddr; + PDMACHx->DADR = DstAddr; +} + +/*********************************************************************************************************//** + * @brief PDMA_SrcAddrConfig + * @param PDMA_CHn: PDMA_CH0 ~ PDMA_CH5 + * @param SrcAddr: Source address + * @retval None + ************************************************************************************************************/ +void PDMA_SrcAddrConfig(u32 PDMA_CHn, u32 SrcAddr) +{ + HT_PDMACH_TypeDef *PDMACHx = (HT_PDMACH_TypeDef *)(HT_PDMA_BASE + PDMA_CHn * 6 * 4); + + /* Check the parameters */ + Assert_Param(IS_PDMA_CH(PDMA_CHn)); + + /* transfer address configuration */ + PDMACHx->SADR = SrcAddr; +} + +/*********************************************************************************************************//** + * @brief PDMA_DstAddrConfig + * @param PDMA_CHn: PDMA_CH0 ~ PDMA_CH5 + * @param DstAddr: Destination address + * @retval None + ************************************************************************************************************/ +void PDMA_DstAddrConfig(u32 PDMA_CHn, u32 DstAddr) +{ + HT_PDMACH_TypeDef *PDMACHx = (HT_PDMACH_TypeDef *)(HT_PDMA_BASE + PDMA_CHn * 6 * 4); + + /* Check the parameters */ + Assert_Param(IS_PDMA_CH(PDMA_CHn)); + + /* transfer address configuration */ + PDMACHx->DADR = DstAddr; +} + +/*********************************************************************************************************//** + * @brief PDMA_TranSizeConfig + * @param PDMA_CHn: PDMA_CH0 ~ PDMA_CH5 + * PDMA_CH0 ~ PDMA_CH7 + * PDMA_CH8 ~ PDMA_CH11 (For specific models only) + * @param BlkCnt: Number of blocks for a transfer + * @param BlkLen: Number of data for a block + * @retval None + ************************************************************************************************************/ +void PDMA_TranSizeConfig(u32 PDMA_CHn, u16 BlkCnt, u16 BlkLen) +{ + HT_PDMACH_TypeDef *PDMACHx = (HT_PDMACH_TypeDef *)(HT_PDMA_BASE + PDMA_CHn * 6 * 4); + + /* Check the parameters */ + Assert_Param(IS_PDMA_CH(PDMA_CHn)); + Assert_Param(IS_PDMA_BLK_CNT(BlkCnt)); + Assert_Param(IS_PDMA_BLK_LEN(BlkLen)); + + /* transfer size configuration */ + PDMACHx->TSR = ((BlkCnt << 16) | BlkLen); +} + +/*********************************************************************************************************//** + * @brief Enable the specific PDMA channel interrupts + * @param PDMA_CHn: PDMA_CH0 ~ PDMA_CH5 + * PDMA_CH0 ~ PDMA_CH7 + * PDMA_CH8 ~ PDMA_CH11 (For specific models only) + * @param PDMA_INT_x: PDMA_INT_GE, PDMA_INT_BE, PDMA_INT_HT, PDMA_INT_TC, PDMA_INT_TE + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void PDMA_IntConfig(u32 PDMA_CHn, u32 PDMA_INT_x, ControlStatus NewState) +{ + #if (LIBCFG_PDMA_V01) + u32 *PdmaIntEnReg = ((u32 *)(&HT_PDMA->IER0)); + #else + u32 *PdmaIntEnReg = (PDMA_CHn < 6) ? ((u32 *)(&HT_PDMA->IER0)) : ((u32 *)(&HT_PDMA->IER1)); + #endif + u32 BitShift = (PDMA_CHn < 6) ? (PDMA_CHn * 5) : ((PDMA_CHn - 6) * 5); + u32 uRegTmp = 0; + + /* Check the parameters */ + Assert_Param(IS_PDMA_CH(PDMA_CHn)); + Assert_Param(IS_PDMA_INT(PDMA_INT_x)); + Assert_Param(IS_CONTROL_STATUS(NewState)); + + #if (LIBCFG_PDMA_CH3FIX) + if (PDMA_CHn == PDMA_CH3) + { + if (PDMA_INT_x & PDMA_INT_BE) + { + uRegTmp |= (PDMA_INT_BE << (PDMA_CH2 * 5)); + } + if (PDMA_INT_x & PDMA_INT_HT) + { + uRegTmp |= (PDMA_INT_HT << (PDMA_CH2 * 5)); + } + } + #endif + + if (NewState != DISABLE) + { + *PdmaIntEnReg |= ((PDMA_INT_x << BitShift) | uRegTmp); + } + else + { + *PdmaIntEnReg &= ~(PDMA_INT_x << BitShift); + } +} + +/*********************************************************************************************************//** + * @brief Enable a specific PDMA channel + * @param PDMA_CHn: PDMA_CH0 ~ PDMA_CH5 + * PDMA_CH0 ~ PDMA_CH7 + * PDMA_CH8 ~ PDMA_CH11 (For specific models only) + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void PDMA_EnaCmd(u32 PDMA_CHn, ControlStatus NewState) +{ + HT_PDMACH_TypeDef *PDMACHx = (HT_PDMACH_TypeDef *)(HT_PDMA_BASE + PDMA_CHn * 6 * 4); + + /* Check the parameters */ + Assert_Param(IS_PDMA_CH(PDMA_CHn)); + Assert_Param(IS_CONTROL_STATUS(NewState)); + + if (NewState != DISABLE) + { + SetBit_BB((u32)(&PDMACHx->CR), 0); + } + else + { + ResetBit_BB((u32)(&PDMACHx->CR), 0); + } +} + +/*********************************************************************************************************//** + * @brief Software trigger a specific PDMA channel + * @param PDMA_CHn: PDMA_CH0 ~ PDMA_CH5 + * PDMA_CH0 ~ PDMA_CH7 + * PDMA_CH8 ~ PDMA_CH11 (For specific models only) + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void PDMA_SwTrigCmd(u32 PDMA_CHn, ControlStatus NewState) +{ + HT_PDMACH_TypeDef *PDMACHx = (HT_PDMACH_TypeDef *)(HT_PDMA_BASE + PDMA_CHn * 6 * 4); + + /* Check the parameters */ + Assert_Param(IS_PDMA_CH(PDMA_CHn)); + Assert_Param(IS_CONTROL_STATUS(NewState)); + + if (NewState != DISABLE) + { + SetBit_BB((u32)(&PDMACHx->CR), 1); + } + else + { + ResetBit_BB((u32)(&PDMACHx->CR), 1); + } +} + +/*********************************************************************************************************//** + * @brief Get the specific PDMA channel interrupt flag + * @param PDMA_CHn: PDMA_CH0 ~ PDMA_CH5 + * PDMA_CH0 ~ PDMA_CH7 + * PDMA_CH8 ~ PDMA_CH11 (For specific models only) + * @param PDMA_FLAG_x: PDMA_FLAG_GE, PDMA_FLAG_BE, PDMA_FLAG_HT, PDMA_FLAG_TC, PDMA_FLAG_TE + * @retval SET or RESET + ************************************************************************************************************/ +FlagStatus PDMA_GetFlagStatus(u32 PDMA_CHn, u32 PDMA_FLAG_x) +{ + #if (LIBCFG_PDMA_V01) + u32 *PdmaIntStatReg = ((u32 *)(&HT_PDMA->ISR0)); + #else + u32 *PdmaIntStatReg = (PDMA_CHn < 6) ? ((u32 *)(&HT_PDMA->ISR0)) : ((u32 *)(&HT_PDMA->ISR1)); + #endif + u32 BitShift = (PDMA_CHn < 6) ? (PDMA_CHn * 5) : ((PDMA_CHn - 6) * 5); + + /* Check the parameters */ + Assert_Param(IS_PDMA_CH(PDMA_CHn)); + Assert_Param(IS_PDMA_FLAG(PDMA_FLAG_x)); + + if ((*PdmaIntStatReg & (PDMA_FLAG_x << BitShift)) != RESET) + { + return SET; + } + else + { + return RESET; + } +} + +/*********************************************************************************************************//** + * @brief Clear the specific PDMA channel interrupt flags + * @param PDMA_CHn: PDMA_CH0 ~ PDMA_CH5 + * PDMA_CH0 ~ PDMA_CH7 + * PDMA_CH8 ~ PDMA_CH11 (For specific models only) + * @param PDMA_FLAG_x: PDMA_FLAG_GE, PDMA_FLAG_BE, PDMA_FLAG_HT, PDMA_FLAG_TC, PDMA_FLAG_TE + * @retval None + ************************************************************************************************************/ +void PDMA_ClearFlag(u32 PDMA_CHn, u32 PDMA_FLAG_x) +{ + #if (LIBCFG_PDMA_V01) + u32 *PdmaIntStatClrReg = ((u32 *)(&HT_PDMA->ISCR0)); + #else + u32 *PdmaIntStatClrReg = (PDMA_CHn < 6) ? ((u32 *)(&HT_PDMA->ISCR0)) : ((u32 *)(&HT_PDMA->ISCR1)); + #endif + u32 BitShift = (PDMA_CHn < 6) ? (PDMA_CHn * 5) : ((PDMA_CHn - 6) * 5); + + /* Check the parameters */ + Assert_Param(IS_PDMA_CH(PDMA_CHn)); + Assert_Param(IS_PDMA_CLEAR_FLAG(PDMA_FLAG_x)); + + *PdmaIntStatClrReg |= (PDMA_FLAG_x << BitShift); +} + +/*********************************************************************************************************//** + * @brief Get remain block count of the specific PDMA channel + * @retval CBLKCNT + ************************************************************************************************************/ +u16 PDMA_GetRemainBlkCnt(u32 PDMA_CHn) +{ + HT_PDMACH_TypeDef *PDMACHx = (HT_PDMACH_TypeDef *)(HT_PDMA_BASE + PDMA_CHn * 6 * 4); + + /* Check the parameters */ + Assert_Param(IS_PDMA_CH(PDMA_CHn)); + + return ((PDMACHx->CTSR) >> 16); +} +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ diff --git a/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/src/ht32f1xxxx_pwm.c b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/src/ht32f1xxxx_pwm.c new file mode 100644 index 0000000000..b824c72b16 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/src/ht32f1xxxx_pwm.c @@ -0,0 +1,2 @@ +The SCTM, PWM, GPTM, and MCTM timer have similar architecture. They use the same driver, +"ht32fxxxxx_tm.c/.h" to save the code size. For those timers, please refet to the TM driver/example. diff --git a/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/src/ht32f1xxxx_pwrcu.c b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/src/ht32f1xxxx_pwrcu.c new file mode 100644 index 0000000000..82f0fdb62a --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/src/ht32f1xxxx_pwrcu.c @@ -0,0 +1,665 @@ +/*********************************************************************************************************//** + * @file ht32f1xxxx_pwrcu.c + * @version $Rev:: 2970 $ + * @date $Date:: 2023-10-25 #$ + * @brief This file provides all the Power Control Unit firmware functions. + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ + +/* Includes ------------------------------------------------------------------------------------------------*/ +#include "ht32f1xxxx_pwrcu.h" + +/** @addtogroup HT32F1xxxx_Peripheral_Driver HT32F1xxxx Peripheral Driver + * @{ + */ + +/** @defgroup PWRCU PWRCU + * @brief PWRCU driver modules + * @{ + */ + + +/* Private constants ---------------------------------------------------------------------------------------*/ +/** @defgroup PWRCU_Private_Define PWRCU private definitions + * @{ + */ +#define APBCCR1_ADDR (HT_CKCU_BASE + 0x30) +#define BAKCR_ADDR (HT_PWRCU_BASE + 0x04) +#define LVDCSR_ADDR (HT_PWRCU_BASE + 0x10) + +#define BB_ADCEN BitBand(APBCCR1_ADDR, 24) +#define BB_RTCEN BitBand(APBCCR1_ADDR, 6) + +#define BB_LDOLCM BitBand(BAKCR_ADDR, 2) +#define BB_LDOOFF BitBand(BAKCR_ADDR, 3) +#define BB_DMOSON BitBand(BAKCR_ADDR, 7) +#define BB_WUPEN BitBand(BAKCR_ADDR, 8) +#define BB_WUPIEN BitBand(BAKCR_ADDR, 9) +#define BB_VRDYSC BitBand(BAKCR_ADDR, 12) +#define BB_DMOSSTS BitBand(BAKCR_ADDR, 15) + +#define BB_BODEN BitBand(LVDCSR_ADDR, 0) +#define BB_BODRIS BitBand(LVDCSR_ADDR, 1) +#define BB_BODF BitBand(LVDCSR_ADDR, 3) +#define BB_LVDEN BitBand(LVDCSR_ADDR, 16) +#define BB_LVDF BitBand(LVDCSR_ADDR, 19) +#define BB_LVDIWEN BitBand(LVDCSR_ADDR, 20) +#define BB_LVDEWEN BitBand(LVDCSR_ADDR, 21) + +#define LDOFTRM_MASK 0xFFFFFFCF +#define LVDS_MASK 0xFFB9FFFF +#define BAKRST_SET 0x1 +#define BAKTEST_READY 0x27 +#define TIME_OUT 48000000 + +#define SLEEPDEEP_SET 0x04 /*!< Cortex SLEEPDEEP bit */ +/** + * @} + */ + +/* Global functions ----------------------------------------------------------------------------------------*/ +/** @defgroup PWRCU_Exported_Functions PWRCU exported functions + * @{ + */ +/*********************************************************************************************************//** + * @brief Deinitialize Backup domain which contains PWRCU and RTC units. + * @retval None + ************************************************************************************************************/ +void PWRCU_DeInit(void) +{ + HT_PWRCU->CR = BAKRST_SET; + while(HT_PWRCU->CR & 0xFFFFEFFF); /* Skip Bit 12 when wait RESET finish. */ + while (HT_PWRCU->SR); /* Waits until the BAKPORF be cleared by read */ +} + +/*********************************************************************************************************//** + * @brief Waits, until the PWRCU can be accessed. + * @retval PWRCU_TIMEOUT or PWRCU_OK + ************************************************************************************************************/ +PWRCU_Status PWRCU_CheckReadyAccessed(void) +{ + u32 wTimeOutCnt = TIME_OUT; + +#if (!LIBCFG_NO_BACK_DOMAIN) + /* Set the ISO control bit */ + HT_CKCU->LPCR = 0x1; +#endif + + while (--wTimeOutCnt) + { + if (HT_PWRCU->TEST == BAKTEST_READY) + { + #if (!LIBCFG_NO_BACK_DOMAIN) + u32 write = ~HT_PWRCU->BAKREG[9]; + u32 backup = HT_PWRCU->BAKREG[9]; + while (1) + { + HT_PWRCU->BAKREG[9] = write; + if (HT_PWRCU->BAKREG[9] == write) break; + } + HT_PWRCU->BAKREG[9] = backup; + #endif + return PWRCU_OK; + } + } + return PWRCU_TIMEOUT; +} + +/*********************************************************************************************************//** + * @brief Return the flags of PWRCU. + * @retval This function will return one of the following: + * - 0x0000 : There is no flag is set. + * - 0x0001 (PWRCU_FLAG_PWRPOR) : Backup domain power-on reset flag has been set. + * - 0x0002 (PWRCU_FLAG_PD) : Power-Down flag has been set. + * - 0x0100 (PWRCU_FLAG_WUP) : External WAKEUP pin flag has been set. + * - 0x0102 (PWRCU_FLAG_PD | PWRCU_FLAG_WUP) : Both PDF and WUPF flags have been set. + ************************************************************************************************************/ +u16 PWRCU_GetFlagStatus(void) +{ + u32 uRTCStatus = 0; + u32 uStatus; + uRTCStatus = BB_RTCEN; + + BB_RTCEN = 1; + + uStatus = HT_PWRCU->SR; + BB_RTCEN = uRTCStatus; + + return uStatus; +} + +#if (!LIBCFG_NO_BACK_DOMAIN) +/*********************************************************************************************************//** + * @brief Return the value of specified backup register. + * @param BAKREGx: Number of backup register. Where x can be 0 ~ 9. + * @return Between 0x0 ~ 0xFFFFFFFF. + ************************************************************************************************************/ +u32 PWRCU_ReadBackupRegister(PWRCU_BAKREG_Enum BAKREGx) +{ + /* Check the parameters */ + Assert_Param(IS_PWRCU_BAKREG(BAKREGx)); + + return HT_PWRCU->BAKREG[BAKREGx]; +} + +/*********************************************************************************************************//** + * @brief Write the DATA to specified backup register. + * @param BAKREGx : Number of backup registers. Where x can be 0 ~ 9. + * @param DATA : Must between 0x0 ~ 0xFFFFFFFF. + * @retval None + ************************************************************************************************************/ +void PWRCU_WriteBackupRegister(PWRCU_BAKREG_Enum BAKREGx, u32 DATA) +{ + /* Check the parameters */ + Assert_Param(IS_PWRCU_BAKREG(BAKREGx)); + + HT_PWRCU->BAKREG[BAKREGx] = DATA; +} +#endif + +/*********************************************************************************************************//** + * @brief Enter SLEEP mode. + * @param SleepEntry : Enters sleep mode instruction that is used to WFI or WFE. + * This parameter can be one of the following values: + * @arg PWRCU_SLEEP_ENTRY_WFE : Enters SLEEP mode via WFE instruction + * @arg PWRCU_SLEEP_ENTRY_WFI : Enters SLEEP mode via WFI instruction + * @retval None + ************************************************************************************************************/ +void PWRCU_Sleep(PWRCU_SLEEP_ENTRY_Enum SleepEntry) +{ + /* Check the parameters */ + Assert_Param(IS_PWRCU_SLEEP_ENTRY(SleepEntry)); + + /* Clear SLEEPDEEP bit of Cortex System Control Register */ + SCB->SCR &= ~(u32)SLEEPDEEP_SET; + + if (SleepEntry == PWRCU_SLEEP_ENTRY_WFE) + { + /* Wait for event */ + __WFE(); + } + else + { + /* Wait for interrupt */ + __WFI(); + } +} + +/*********************************************************************************************************//** + * @brief Enter DEEP-SLEEP Mode 1. + * @param SleepEntry : Enters sleep mode instruction that is used to WFI or WFE. + * This parameter can be one of the following values: + * @arg PWRCU_SLEEP_ENTRY_WFE : Enters SLEEP mode via WFE instruction + * @arg PWRCU_SLEEP_ENTRY_WFI : Enters SLEEP mode via WFI instruction + * @retval None + ************************************************************************************************************/ +void PWRCU_DeepSleep1(PWRCU_SLEEP_ENTRY_Enum SleepEntry) +{ + u32 uRTCStatus = 0; + u32 uADCStatus = 0; + + /* Check the parameters */ + Assert_Param(IS_PWRCU_SLEEP_ENTRY(SleepEntry)); + + uRTCStatus = BB_RTCEN; + uADCStatus = BB_ADCEN; + + BB_RTCEN = 1; + BB_ADCEN = 0; + + BB_DMOSON = 0; + BB_LDOOFF = 0; + + BB_RTCEN = uRTCStatus; + /* Sets SLEEPDEEP bit of Cortex System Control Register */ + SCB->SCR |= SLEEPDEEP_SET; + + if (SleepEntry == PWRCU_SLEEP_ENTRY_WFE) + { + /* Wait for event */ + __WFE(); + } + else + { + /* Wait for interrupt */ + __WFI(); + } + BB_ADCEN = uADCStatus; +} + +/*********************************************************************************************************//** + * @brief Enter DEEP-SLEEP Mode 2. + * @param SleepEntry : Enters sleep mode instruction that is used to WFI or WFE. + * This parameter can be one of the following values: + * @arg PWRCU_SLEEP_ENTRY_WFE : Enters SLEEP mode via WFE instruction + * @arg PWRCU_SLEEP_ENTRY_WFI : Enters SLEEP mode via WFI instruction + * @retval None + ************************************************************************************************************/ +void PWRCU_DeepSleep2(PWRCU_SLEEP_ENTRY_Enum SleepEntry) +{ + u32 uRTCStatus = 0; + u32 uADCStatus = 0; + #if (!LIBCFG_PWRCU_LDO_LEGACY) + u32 uLDOStatus = 0; + #endif + + /* Check the parameters */ + Assert_Param(IS_PWRCU_SLEEP_ENTRY(SleepEntry)); + + uRTCStatus = BB_RTCEN; + uADCStatus = BB_ADCEN; + + BB_RTCEN = 1; + BB_ADCEN = 0; + + if (BB_DMOSSTS == 0) + { + BB_DMOSON = 0; + BB_DMOSON = 1; + } + BB_LDOOFF = 0; + + BB_RTCEN = uRTCStatus; + + #if (!LIBCFG_PWRCU_LDO_LEGACY) + uLDOStatus = HT_PWRCU->CR & ~LDOFTRM_MASK; + if (uLDOStatus >= PWRCU_LDO_OFFSET_ADD3P) + { + CKCU_PSRCWKUPCmd(ENABLE); + } + #endif + + /* Sets SLEEPDEEP bit of Cortex System Control Register */ + SCB->SCR |= SLEEPDEEP_SET; + + if (SleepEntry == PWRCU_SLEEP_ENTRY_WFE) + { + /* Wait for event */ + __WFE(); + } + else + { + /* Wait for interrupt */ + __WFI(); + } + + #if (!LIBCFG_PWRCU_LDO_LEGACY) + if (uLDOStatus >= PWRCU_LDO_OFFSET_ADD3P) + { + PWRCU_SetLDOFTRM((PWRCU_LDOFTRM_Enum)uLDOStatus); + CKCU_PSRCWKUPCmd(DISABLE); + + if ((HT_CKCU->GCCR >> 9) & 1) + { + while (CKCU_GetClockReadyStatus(CKCU_FLAG_PLLRDY) != SET); + } + } + #endif + + BB_ADCEN = uADCStatus; +} + +/*********************************************************************************************************//** + * @brief Enter POWER-DOWN Mode. + * @retval None + ************************************************************************************************************/ +void PWRCU_PowerDown(void) +{ + u32 uRTCStatus = 0; + u32 uADCStatus = 0; + + uRTCStatus = BB_RTCEN; + uADCStatus = BB_ADCEN; + + BB_RTCEN = 1; + BB_ADCEN = 0; + + #if (LIBCFG_RTC_LSI_LOAD_TRIM) + { + static u8 isLSITrimLoaded = FALSE; + if (isLSITrimLoaded == FALSE) + { + u32 i = 9600; + isLSITrimLoaded = TRUE; + HT_RTC->CR &= ~(1UL << 2); + /* Insert a delay must > 1 CK_RTC */ + while (i--); + HT_RTC->CR |= (1UL << 2); + while ((HT_CKCU->GCSR & 0x20) == 0); + } + } + #endif + + BB_DMOSON = 0; + BB_LDOOFF = 1; + + BB_RTCEN = uRTCStatus; + + /* Sets SLEEPDEEP bit of Cortex System Control Register */ + SCB->SCR |= SLEEPDEEP_SET; + + /* Enters power-down mode */ + __WFE(); + + BB_ADCEN = uADCStatus; +} + +#if (LIBCFG_PWRCU_LDO_LEGACY) +#else +/*********************************************************************************************************//** + * @brief Configure LDO output voltage fine trim. + * @param VolOffset: LDO default output voltage offset. + * This parameter can be one of following: + * @arg PWRCU_LDO_DEFAULT : default output voltage + * @arg PWRCU_LDO_OFFSET_DEC5P : default output voltage offset -5% + * @arg PWRCU_LDO_OFFSET_ADD3P : default output voltage offset +3% + * @arg PWRCU_LDO_OFFSET_ADD7P : default output voltage offset +7% + * @retval None + ************************************************************************************************************/ +void PWRCU_SetLDOFTRM(PWRCU_LDOFTRM_Enum VolOffset) +{ + /* Check the parameters */ + Assert_Param(IS_PWRCU_LDOFTRM(VolOffset)); + + do { + HT_PWRCU->CR = (HT_PWRCU->CR & LDOFTRM_MASK) | VolOffset; + } while ((HT_PWRCU->CR & ~LDOFTRM_MASK) != VolOffset); +} +#endif + +/*********************************************************************************************************//** + * @brief Configure LVD voltage level. + * @param Level: Low voltage detect level. + * This parameter can be one of the following: + * HT32F165x: + * @arg PWRCU_LVDS_2V7 : 2.7 V + * @arg PWRCU_LVDS_2V8 : 2.9 V + * @arg PWRCU_LVDS_2V9 : 2.9 V + * @arg PWRCU_LVDS_3V : 3.0 V + * @arg PWRCU_LVDS_3V1 : 3.1 V + * @arg PWRCU_LVDS_3V2 : 3.2 V + * @arg PWRCU_LVDS_3V4 : 3.4 V + * @arg PWRCU_LVDS_3V5 : 3.5 V + * HT32F123xx: + * @arg PWRCU_LVDS_2V25 : 2.25 V + * @arg PWRCU_LVDS_2V4 : 2.40 V + * @arg PWRCU_LVDS_2V55 : 2.55 V + * @arg PWRCU_LVDS_2V7 : 2.70 V + * @arg PWRCU_LVDS_2V85 : 2.85 V + * @arg PWRCU_LVDS_3V : 3.00 V + * @arg PWRCU_LVDS_3V15 : 3.15 V + * @arg PWRCU_LVDS_3V3 : 3.30 V + * HT32F12364: + * @arg PWRCU_LVDS_1V75 : 1.75 V + * @arg PWRCU_LVDS_1V95 : 1.95 V + * @arg PWRCU_LVDS_2V15 : 2.15 V + * @arg PWRCU_LVDS_2V35 : 2.35 V + * @arg PWRCU_LVDS_2V55 : 2.55 V + * @arg PWRCU_LVDS_2V75 : 2.75 V + * @arg PWRCU_LVDS_2V95 : 2.95 V + * @arg PWRCU_LVDS_3V15 : 3.15 V + * @retval None + ************************************************************************************************************/ +void PWRCU_SetLVDS(PWRCU_LVDS_Enum Level) +{ + /* Check the parameters */ + Assert_Param(IS_PWRCU_LVDS(Level)); + + HT_PWRCU->LVDCSR = (HT_PWRCU->LVDCSR & LVDS_MASK) | Level; +} + +/*********************************************************************************************************//** + * @brief Enable or Disable LVD function. + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void PWRCU_LVDCmd(ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_CONTROL_STATUS(NewState)); + + BB_LVDEN = NewState; +} + +/*********************************************************************************************************//** + * @brief Enable or Disable BOD reset function. + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void PWRCU_BODCmd(ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_CONTROL_STATUS(NewState)); + + BB_BODEN = NewState; +} + +/*********************************************************************************************************//** + * @brief Select when the BOD occurs, the action for the cause Reset or Interrupt. + * @param Selection: BOD reset or interrupt selection. + * This parameter can be one of the following values: + * @arg PWRCU_BODRIS_RESET : Reset the whole chip + * @arg PWRCU_BODRIS_INT : Assert interrupt + * @retval None + ************************************************************************************************************/ +void PWRCU_BODRISConfig(PWRCU_BODRIS_Enum Selection) +{ + /* Check the parameters */ + Assert_Param(IS_PWRCU_BODRIS(Selection)); + + BB_BODRIS = Selection; +} + +/*********************************************************************************************************//** + * @brief Return the flag status of LVD. + * @retval SET or RESET + ************************************************************************************************************/ +FlagStatus PWRCU_GetLVDFlagStatus(void) +{ + return (FlagStatus)BB_LVDF; +} + +/*********************************************************************************************************//** + * @brief Return the flag status of BOD. + * @retval SET or RESET + ************************************************************************************************************/ +FlagStatus PWRCU_GetBODFlagStatus(void) +{ + return (FlagStatus)BB_BODF; +} + +/*********************************************************************************************************//** + * @brief Return the DMOS status. + * @retval This function will return one of the following values: + * - PWRCU_DMOS_STS_ON : DMOS on + * - PWRCU_DMOS_STS_OFF : DMOS off + * - PWRCU_DMOS_STS_OFF_BY_BODRESET : DMOS off caused by brow out reset + ************************************************************************************************************/ +PWRCU_DMOSStatus PWRCU_GetDMOSStatus(void) +{ + u32 wDmosStatus = HT_PWRCU->CR & 0x8080; + + if (wDmosStatus == 0x0) + { + return PWRCU_DMOS_STS_OFF; + } + else if (wDmosStatus == 0x8080) + { + return PWRCU_DMOS_STS_ON; + } + else + { + return PWRCU_DMOS_STS_OFF_BY_BODRESET; + } +} + +/*********************************************************************************************************//** + * @brief Enable or Disable DMOS function. + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void PWRCU_DMOSCmd(ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_CONTROL_STATUS(NewState)); + + if (BB_DMOSSTS == 0) + { + BB_DMOSON = 0; + } + + BB_DMOSON = NewState; +} + +#if (LIBCFG_PWRCU_LDO_LEGACY) +#else +/*********************************************************************************************************//** + * @brief Configure the LDO operation mode. + * @param Sel: Specify the LDO mode. + * This parameter can be one of the following values: + * @arg PWRCU_LDO_NORMAL : The LDO is operated in normal current mode + * @arg PWRCU_LDO_LOWCURRENT : The LDO is operated in low current mode + * @retval None + ************************************************************************************************************/ +void PWRCU_LDOConfig(PWRCU_LDOMODE_Enum Sel) +{ + /* Check the parameters */ + Assert_Param(IS_PWRCU_LDOMODE(Sel)); + + if (Sel == PWRCU_LDO_NORMAL) + { + BB_LDOLCM = 0; + } + else + { + BB_LDOLCM = 1; + } +} +#endif + +/*********************************************************************************************************//** + * @brief Configure VDD18/VDD15 power good source. + * @param Sel: Specify VDD18/VDD15 power good source. + * This parameter can be one of the following values: + * @arg PWRCU_VRDYSC_BKISO : Vdd18/Vdd15 power good source come from BK_ISO bit in CKCU unit + * @arg PWRCU_VRDYSC_VPOR : Vdd18/Vdd15 power good source come from Vdd18/Vdd15 power on reset + * @retval None + ************************************************************************************************************/ +void PWRCU_VRDYSourceConfig(PWRCU_VRDYSC_Enum Sel) +{ + /* Check the parameters */ + Assert_Param(IS_PWRCU_VRDYSC(Sel)); + + BB_VRDYSC = Sel; +} + +/*********************************************************************************************************//** + * @brief Enable or Disable the LVD interrupt wakeup function. + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void PWRCU_LVDIntWakeupConfig(ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_CONTROL_STATUS(NewState)); + + BB_LVDIWEN = NewState; +} + +/*********************************************************************************************************//** + * @brief Enable or Disable the LVD event wakeup function. + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void PWRCU_LVDEventWakeupConfig(ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_CONTROL_STATUS(NewState)); + + BB_LVDEWEN = NewState; +} + +/*********************************************************************************************************//** + * @brief Enable or Disable the external WAKEUP pin function. + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void PWRCU_WakeupPinCmd(ControlStatus NewState) +{ + u32 uRTCStatus = 0; + + /* Check the parameters */ + Assert_Param(IS_CONTROL_STATUS(NewState)); + + uRTCStatus = BB_RTCEN; + + BB_RTCEN = 1; + + BB_WUPEN = NewState; + + BB_RTCEN = uRTCStatus; +} + +/*********************************************************************************************************//** + * @brief Enable or Disable the external WAKEUP pin interrupt function. + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void PWRCU_WakeupPinIntConfig(ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_CONTROL_STATUS(NewState)); + + BB_WUPIEN = NewState; +} + +#if (LIBCFG_PWRCU_HSI_READY_COUNTER) +/*********************************************************************************************************//** + * @brief Configure HSI ready counter bit length. + * @param BitLength: HSI ready counter bit length. + * This parameter can be one of following: + * @arg PWRCU_HSIRCBL_4 : 4 bits + * @arg PWRCU_HSIRCBL_5 : 5 bits + * @arg PWRCU_HSIRCBL_6 : 6 bits + * @arg PWRCU_HSIRCBL_7 : 7 bits (Default) + * @retval None + ************************************************************************************************************/ +void PWRCU_HSIReadyCounterBitLengthConfig(PWRCU_HSIRCBL_Enum BitLength) +{ + /* Check the parameters */ + Assert_Param(IS_PWRCU_HSIRCBL(BitLength)); + + HT_PWRCU->HSIRCR = BitLength; +} +#endif +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ diff --git a/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/src/ht32f1xxxx_rstcu.c b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/src/ht32f1xxxx_rstcu.c new file mode 100644 index 0000000000..e4ac9f5b9d --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/src/ht32f1xxxx_rstcu.c @@ -0,0 +1,142 @@ +/*********************************************************************************************************//** + * @file ht32f1xxxx_rstcu.c + * @version $Rev:: 2787 $ + * @date $Date:: 2022-11-23 #$ + * @brief This file provides all the Reset Control Unit firmware functions. + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ + +/* Includes ------------------------------------------------------------------------------------------------*/ +#include "ht32f1xxxx_rstcu.h" + +/** @addtogroup HT32F1xxxx_Peripheral_Driver HT32F1xxxx Peripheral Driver + * @{ + */ + +/** @defgroup RSTCU RSTCU + * @brief RSTCU driver modules + * @{ + */ + + +/* Global functions ----------------------------------------------------------------------------------------*/ +/** @defgroup RSTCU_Exported_Functions RSTCU exported functions + * @{ + */ +/*********************************************************************************************************//** + * @brief Check whether the specific global reset flag is set or not. + * @param RSTCU_RSTF: specify the reset flag. + * This parameter can be one of the following values: + * @arg RSTCU_FLAG_SYSRST : Get system reset flag + * @arg RSTCU_FLAG_EXTRST : Get external pin reset flag + * @arg RSTCU_FLAG_WDTRST : Get WDT reset flag + * @arg RSTCU_FLAG_PORST : Get power on reset flag + * @retval SET or RESET + ************************************************************************************************************/ +FlagStatus RSTCU_GetResetFlagStatus(RSTCU_RSTF_TypeDef RSTCU_RSTF) +{ + u32 tmp; + + /* Check the parameters */ + Assert_Param(IS_RSTCU_FLAG(RSTCU_RSTF)); + + tmp = (HT_RSTCU->GRSR & ((u32)0x1 << RSTCU_RSTF)); + if (tmp != RESET) + { + return SET; + } + else + { + return RESET; + } +} + +/*********************************************************************************************************//** + * @brief Clear the specific global reset flag. + * @param RSTCU_RSTF: specify the reset flag. + * This parameter can be one of the following values: + * @arg RSTCU_FLAG_SYSRST : Clear system reset flag + * @arg RSTCU_FLAG_EXTRST : Clear external pin reset flag + * @arg RSTCU_FLAG_WDTRST : Clear WDT reset flag + * @arg RSTCU_FLAG_PORST : Clear power on reset flag + * @retval None + ************************************************************************************************************/ +void RSTCU_ClearResetFlag(RSTCU_RSTF_TypeDef RSTCU_RSTF) +{ + /* Check the parameters */ + Assert_Param(IS_RSTCU_FLAG(RSTCU_RSTF)); + + HT_RSTCU->GRSR = (u32)0x1 << RSTCU_RSTF; /* Write 1 to clear */ +} + +/*********************************************************************************************************//** + * @brief Clear all of the global reset flag. + * @retval None + ************************************************************************************************************/ +void RSTCU_ClearAllResetFlag(void) +{ + HT_RSTCU->GRSR = (u32)0xF; /* Write 1 to clear */ +} + +/*********************************************************************************************************//** + * @brief Peripheral reset function. + * @param Reset: specify the peripheral clock enable bits. + * @param Cmd: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void RSTCU_PeripReset(RSTCU_PeripReset_TypeDef Reset, ControlStatus Cmd) +{ + u32 uAHBPRST; + u32 uAPBPRST0; + u32 uAPBPRST1; + + uAHBPRST = HT_RSTCU->AHBPRST; + uAPBPRST0 = HT_RSTCU->APBPRST0; + uAPBPRST1 = HT_RSTCU->APBPRST1; + + uAHBPRST &= ~(Reset.Reg[0]); + uAPBPRST0 &= ~(Reset.Reg[1]); + uAPBPRST1 &= ~(Reset.Reg[2]); + + if (Cmd != DISABLE) + { + uAHBPRST |= Reset.Reg[0]; + uAPBPRST0 |= Reset.Reg[1]; + uAPBPRST1 |= Reset.Reg[2]; + } + + HT_RSTCU->AHBPRST = uAHBPRST; + HT_RSTCU->APBPRST0 = uAPBPRST0; + HT_RSTCU->APBPRST1 = uAPBPRST1; +} +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ diff --git a/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/src/ht32f1xxxx_rtc.c b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/src/ht32f1xxxx_rtc.c new file mode 100644 index 0000000000..6c8a2638a7 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/src/ht32f1xxxx_rtc.c @@ -0,0 +1,372 @@ +/*********************************************************************************************************//** + * @file ht32f1xxxx_rtc.c + * @version $Rev:: 2233 $ + * @date $Date:: 2020-10-13 #$ + * @brief This file provides all the RTC firmware functions. + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ + +/* Includes ------------------------------------------------------------------------------------------------*/ +#include "ht32f1xxxx_rtc.h" + +/** @addtogroup HT32F1xxxx_Peripheral_Driver HT32F1xxxx Peripheral Driver + * @{ + */ + +/** @defgroup RTC RTC + * @brief RTC driver modules + * @{ + */ + + +/* Private constants ---------------------------------------------------------------------------------------*/ +/** @defgroup RTC_Private_Define RTC private definitions + * @{ + */ +#define RTC_CR_ADDR (HT_RTC_BASE + 0x008) +#define BB_RTCEN BitBand(RTC_CR_ADDR, 0) +#define BB_RTCSRC BitBand(RTC_CR_ADDR, 1) +#define BB_LSI_EN BitBand(RTC_CR_ADDR, 2) +#define BB_LSE_EN BitBand(RTC_CR_ADDR, 3) +#define BB_CMPCLR BitBand(RTC_CR_ADDR, 4) +#define BB_SOP BitBand(RTC_CR_ADDR, 5) +#define BB_ROEN BitBand(RTC_CR_ADDR, 16) +#define BB_ROES BitBand(RTC_CR_ADDR, 17) +#define BB_ROWM BitBand(RTC_CR_ADDR, 18) +#define BB_ROAP BitBand(RTC_CR_ADDR, 19) +#define BB_ROLF BitBand(RTC_CR_ADDR, 20) +#define RPRE_MASK (0xFFFFF0FF) + +/** + * @} + */ + +/* Global functions ----------------------------------------------------------------------------------------*/ +/** @defgroup RTC_Exported_Functions RTC exported functions + * @{ + */ +/*********************************************************************************************************//** + * @brief Deinitialize the RTC peripheral registers to their default reset values. + * @retval None + ************************************************************************************************************/ +void RTC_DeInit(void) +{ + HT_RTC->CR = 0x00000004; + HT_RTC->CMP = 0x0; + HT_RTC->IWEN = 0x0; + HT_RTC->CR |= 0x00000005; + while (HT_RTC->CNT); + HT_RTC->CR = 0x00000F04; + /* Read the RTC_SR register to clear it */ + HT_RTC->SR; +} + +/*********************************************************************************************************//** + * @brief Select the RTC timer clock source. + * @param Source: specify the clock source of RTC and backup domain. + * @arg RTC_SRC_LSI : Low speed internal clock. + * @arg RTC_SRC_LSE : Low speed external clock. + * @retval None + ************************************************************************************************************/ +void RTC_ClockSourceConfig(RTC_SRC_Enum Source) +{ + Assert_Param(IS_RTC_SRC(Source)); + + BB_RTCSRC = Source; +} + +#if (LIBCFG_RTC_LSI_LOAD_TRIM) +/*********************************************************************************************************//** + * @brief Loads the LSI trim data. + * @retval None + ************************************************************************************************************/ +void RTC_LSILoadTrimData(void) +{ + u32 i = 9600; + + HT_RTC->CR &= ~(1UL << 2); + /* Insert a delay must > 1 CK_RTC */ + while (i--); + HT_RTC->CR |= (1UL << 2); + while ((HT_CKCU->GCSR & 0x20) == 0); +} +#endif + +/*********************************************************************************************************//** + * @brief Select the LSE startup mode. + * @param Mode: specify the LSE startup mode. + * This parameter can be one of the following values: + * @arg RTC_LSESM_NORMAL : Little power consumption but longer startup time. + * @arg RTC_LSESM_FAST : Shortly startup time but higher power consumption. + * @retval None + ************************************************************************************************************/ +void RTC_LSESMConfig(RTC_LSESM_Enum Mode) +{ + Assert_Param(IS_RTC_LSESM(Mode)); + + BB_SOP = Mode; +} + +/*********************************************************************************************************//** + * @brief Enable or Disable the LSE clock. + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void RTC_LSECmd(ControlStatus NewState) +{ + Assert_Param(IS_CONTROL_STATUS(NewState)); + + if (NewState == DISABLE) + { + BB_LSE_EN = 0; + while (HT_CKCU->GCSR & 0x10); + } + else + { + BB_LSE_EN = 1; + while ((HT_CKCU->GCSR & 0x10) == 0); + } +} + +/*********************************************************************************************************//** + * @brief Enable or Disable the compare match function. + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void RTC_CMPCLRCmd(ControlStatus NewState) +{ + Assert_Param(IS_CONTROL_STATUS(NewState)); + + BB_CMPCLR = NewState; +} + +/*********************************************************************************************************//** + * @brief Configure the RTC prescaler. + * @param Psc: Value of RTC prescaler. + * This parameter can be one of following values: + * @arg RTC_RPRE_1 + * @arg RTC_RPRE_2 + * @arg RTC_RPRE_4 + * @arg RTC_RPRE_8 + * @arg RTC_RPRE_16 + * @arg RTC_RPRE_32 + * @arg RTC_RPRE_64 + * @arg RTC_RPRE_128 + * @arg RTC_RPRE_256 + * @arg RTC_RPRE_512 + * @arg RTC_RPRE_1024 + * @arg RTC_RPRE_2048 + * @arg RTC_RPRE_4096 + * @arg RTC_RPRE_8192 + * @arg RTC_RPRE_16384 + * @arg RTC_RPRE_32768 + * @retval None + ************************************************************************************************************/ +void RTC_SetPrescaler(RTC_RPRE_Enum Psc) +{ + Assert_Param(IS_RTC_PSC(Psc)); + + HT_RTC->CR = (HT_RTC->CR & RPRE_MASK) | Psc; +} + +/*********************************************************************************************************//** + * @brief Return the RTC prescaler setting. + * @retval The prescaler value. It is powered by 2 and max.is 32768. + ************************************************************************************************************/ +u16 RTC_GetPrescaler(void) +{ + u32 prescaler; + + prescaler = HT_RTC->CR >> 8; + + return ((u16)0x1 << prescaler); +} + +/*********************************************************************************************************//** + * @brief Enable or Disable the RTC timer. + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void RTC_Cmd(ControlStatus NewState) +{ + BB_RTCEN = NewState; +} + +/*********************************************************************************************************//** + * @brief Return the counter value. + * @retval Between 0x0 ~ 0xFFFFFFFF. + ************************************************************************************************************/ +u32 RTC_GetCounter(void) +{ + /* !!! NOTICE !!! + A 1/CK_RTC delay time is required if you read the RTC CNT count immediately when the RTC compare match + occurred (in the RTC ISR or the system is wakeup from the DeepSleep1/2). + The CK_RTC can be configured from the LSI or LSE. + */ + return (HT_RTC->CNT); +} + +/*********************************************************************************************************//** + * @brief Configure the compare match value. + * @param Compare: Between 0x0 ~ 0xFFFFFFFF + * @retval None + ************************************************************************************************************/ +void RTC_SetCompare(u32 Compare) +{ + HT_RTC->CMP = Compare; +} + +/*********************************************************************************************************//** + * @brief Return the compare match value. + * @retval Between 0x0 ~ 0xFFFFFFFF. + ************************************************************************************************************/ +u32 RTC_GetCompare(void) +{ + return (HT_RTC->CMP); +} + +/*********************************************************************************************************//** + * @brief Enable or Disable the specified wakeup source. + * @param RTC_WAKEUP Selection of Wakeup source. + * This parameter can be any combination of the following values: + * @arg RTC_WAKEUP_CSEC : Waken up by counter counting. + * @arg RTC_WAKEUP_CM : Waken up by counter compare match with CMP register. + * @arg RTC_WAKEUP_OV : Waken up by counter overflow. + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void RTC_WakeupConfig(u32 RTC_WAKEUP, ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_RTC_WAKEUP(RTC_WAKEUP)); + + if (NewState != DISABLE) + { + HT_RTC->IWEN |= RTC_WAKEUP; + } + else + { + HT_RTC->IWEN &= ~RTC_WAKEUP; + } +} + +/*********************************************************************************************************//** + * @brief Enable or Disable the specified interrupt source. + * @param RTC_INT: Selection of Wakeup source. + * This parameter can be any combination of the following values: + * @arg RTC_INT_CSEC : Assert interrupt at counter counting + * @arg RTC_INT_CM : Assert interrupt at counter compare match with CMP register + * @arg RTC_INT_OV : Assert interrupt at counter overflow + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void RTC_IntConfig(u32 RTC_INT, ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_RTC_INT(RTC_INT)); + + if (NewState != DISABLE) + { + HT_RTC->IWEN |= RTC_INT; + } + else + { + HT_RTC->IWEN &= ~RTC_INT; + } +} + +/*********************************************************************************************************//** + * @brief Return the RTC flags. + * @retval RTC_STS register value. + * This parameter can be any combination of following: + * - 0x0 : No flag set + * - 0x1 : Count flag + * - 0x2 : Match flag + * - 0x4 : Overflow flag + * @note RTC_SR is read clear. + ************************************************************************************************************/ +u8 RTC_GetFlagStatus(void) +{ + return ((u8)HT_RTC->SR); +} + +/*********************************************************************************************************//** + * @brief Configure the RTC output function. + * @param WMode: specify the RTC output waveform mode + * This parameter can be one of the following values: + * @arg RTC_ROWM_PULSE : Pulse mode + * @arg RTC_ROWM_LEVEL : Level mode + * @param EventSel: specify the RTC output event selection + * This parameter can be one of the following values: + * @arg RTC_ROES_MATCH : Compare match selected + * @arg RTC_ROES_SECOND : Second clock selected + * @param Pol: specify the RTC output active polarity + * This parameter can be one of the following values: + * @arg RTC_ROAP_HIGH : Active level is high + * @arg RTC_ROAP_LOW : Active level is low + * @note This function will disable RTC output first. + ************************************************************************************************************/ +void RTC_OutConfig(RTC_ROWM_Enum WMode, RTC_ROES_Enum EventSel, RTC_ROAP_Enum Pol) +{ + Assert_Param(IS_RTC_ROWM(WMode)); + Assert_Param(IS_RTC_ROES(EventSel)); + Assert_Param(IS_RTC_ROAP(Pol)); + + BB_ROEN = 0; + BB_ROWM = WMode; + BB_ROES = EventSel; + BB_ROAP = Pol; +} + +/*********************************************************************************************************//** + * @brief Enable or Disable the RTC output. + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void RTC_OutCmd(ControlStatus NewState) +{ + Assert_Param(IS_CONTROL_STATUS(NewState)); + + BB_ROEN = NewState; +} + +/*********************************************************************************************************//** + * @brief Return the RTCOUT level mode flag. + * @retval SET or RESET + * @note Reads RTC_CR action will clear ROLF flag. + ************************************************************************************************************/ +FlagStatus RTC_GetOutStatus(void) +{ + return (FlagStatus)BB_ROLF; +} +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ diff --git a/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/src/ht32f1xxxx_sci.c b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/src/ht32f1xxxx_sci.c new file mode 100644 index 0000000000..f3c826ae15 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/src/ht32f1xxxx_sci.c @@ -0,0 +1,444 @@ +/*********************************************************************************************************//** + * @file ht32f1xxxx_sci.c + * @version $Rev:: 2797 $ + * @date $Date:: 2022-11-28 #$ + * @brief This file provides all the SCI firmware functions. + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ + +/* Includes ------------------------------------------------------------------------------------------------*/ +#include "ht32f1xxxx_sci.h" + +/** @addtogroup HT32F1xxxx_Peripheral_Driver HT32F1xxxx Peripheral Driver + * @{ + */ + +/** @defgroup SCI SCI + * @brief SCI driver modules + * @{ + */ + + +/* Private constants ---------------------------------------------------------------------------------------*/ +/** @defgroup SCI_Private_Define SCI private definitions + * @{ + */ +/* SCI ENSCI mask */ +#define CR_ENSCI_SET ((u32)0x00000020) +#define CR_ENSCI_RESET ((u32)0xFFFFFFDF) + +/* SCI WTEN mask */ +#define CR_WTEN_SET ((u32)0x00000004) +#define CR_WTEN_RESET ((u32)0xFFFFFFFB) +/** + * @} + */ + +/* Global functions ----------------------------------------------------------------------------------------*/ +/** @defgroup SCI_Exported_Functions SCI exported functions + * @{ + */ +/*********************************************************************************************************//** + * @brief Deinitialize the SCI peripheral registers to their default reset values. + * @param SCIx: where SCIx is the selected SCI from the SCI peripherals. + * @retval None + ************************************************************************************************************/ +void SCI_DeInit(HT_SCI_TypeDef* SCIx) +{ + RSTCU_PeripReset_TypeDef RSTCUReset = {{0}}; + if (SCIx == HT_SCI0) + { + RSTCUReset.Bit.SCI0 = 1; + } + #if (LIBCFG_SCI1) + else + { + RSTCUReset.Bit.SCI1 = 1; + } + #endif + RSTCU_PeripReset(RSTCUReset, ENABLE); +} + +/*********************************************************************************************************//** + * @brief Initialize the SCI peripheral according to the specified parameters in the SCI_InitStruct. + * @param SCIx: where SCIx is the selected SCI from the SCI peripherals. + * @param SCI_InitStruct: pointer to a SCI_InitTypeDef structure. + * @retval None + ************************************************************************************************************/ +void SCI_Init(HT_SCI_TypeDef* SCIx, SCI_InitTypeDef* SCI_InitStruct) +{ + u32 tmpreg; + + /* Check the parameters */ + Assert_Param(IS_SCI_MODE(SCI_InitStruct->SCI_Mode)); + Assert_Param(IS_SCI_RETRY(SCI_InitStruct->SCI_Retry)); + Assert_Param(IS_SCI_CONVENTION(SCI_InitStruct->SCI_Convention)); + Assert_Param(IS_SCI_CARD_POLARITY(SCI_InitStruct->SCI_CardPolarity)); + Assert_Param(IS_SCI_CLOCK_PRESCALER(SCI_InitStruct->SCI_ClockPrescale)); + + + /*------------------------- SCI Control Register Configuration -------------------------------------------*/ + tmpreg = SCIx->CR; + tmpreg &= 0xFFFFFFA4; + + tmpreg |= SCI_InitStruct->SCI_Mode | SCI_InitStruct->SCI_Retry | SCI_InitStruct->SCI_Convention | + SCI_InitStruct->SCI_CardPolarity; + + SCIx->CR = tmpreg; + + /*------------------------- SCI Prescaler Register Configuration -----------------------------------------*/ + SCIx->PSC = SCI_InitStruct->SCI_ClockPrescale; +} + +/*********************************************************************************************************//** + * @brief Initialize the SCI peripheral according to the specified parameters in the SCI_InitStruct. + * @param SCI_InitStruct: pointer to a SCI_InitTypeDef structure. + * @retval None + ************************************************************************************************************/ +void SCI_StructInit(SCI_InitTypeDef* SCI_InitStruct) +{ + /* Initialize the SCI_Mode member */ + SCI_InitStruct->SCI_Mode = SCI_MODE_MANUAL; + + /* Initialize the SCI_Retry member */ + SCI_InitStruct->SCI_Retry = SCI_RETRY_NO; + + /* Initialize the SCI_Convention member */ + SCI_InitStruct->SCI_Convention = SCI_CONVENTION_DIRECT; + + /* Initialize the SCI_CardPolarity member */ + SCI_InitStruct->SCI_CardPolarity = SCI_CARDPOLARITY_LOW; + + /* Initialize the SCI_ClockPrescale member */ + SCI_InitStruct->SCI_ClockPrescale = SCI_CLKPRESCALER_1; +} + +/*********************************************************************************************************//** + * @brief Enable or Disable the specified SCI peripheral. + * @param SCIx: where SCIx is the selected SCI from the SCI peripherals. + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void SCI_Cmd(HT_SCI_TypeDef* SCIx, ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_CONTROL_STATUS(NewState)); + + if (NewState != DISABLE) + { + SCIx->CR |= CR_ENSCI_SET; + } + else + { + SCIx->CR &= CR_ENSCI_RESET; + } +} + +/*********************************************************************************************************//** + * @brief This function is used to configure the Elementary Time Unit. + * @param SCIx: where SCIx is the selected SCI from the SCI peripherals. + * @param SCI_ETU: specify the SCI Elementary Time Unit. + * @param SCI_Compensation: Enable or Disable the Compensation mode. + * This parameter can be one of the following values: + * @arg SCI_COMPENSATION_ENABLE : Compensation mode enabled + * @arg SCI_COMPENSATION_DISABLE : Compensation mode disabled + * @retval None + ************************************************************************************************************/ +void SCI_ETUConfig(HT_SCI_TypeDef* SCIx, u32 SCI_ETU, u32 SCI_Compensation) +{ + /* Check the parameters */ + Assert_Param(IS_SCI_ETU(SCI_ETU)); + Assert_Param(IS_SCI_ETU_COMPENSATION(SCI_Compensation)); + + SCIx->ETU = SCI_ETU | SCI_Compensation; +} + +/*********************************************************************************************************//** + * @brief This function is used to set the value of SCI GuardTime. + * @param SCIx: where SCIx is the selected SCI from the SCI peripherals. + * @param SCI_GuardTime: specify the value of SCI GuardTime value. + * @retval None + ************************************************************************************************************/ +void SCI_SetGuardTimeValue(HT_SCI_TypeDef* SCIx, u16 SCI_GuardTime) +{ + /* Check the parameters */ + Assert_Param(IS_SCI_GUARDTIME(SCI_GuardTime)); + + SCIx->GT = SCI_GuardTime; +} + +/*********************************************************************************************************//** + * @brief This function is used to set the value of SCI Waiting Time. + * @param SCIx: where SCIx is the selected SCI from the SCI peripherals. + * @param SCI_WaitingTime: specify the value of SCI Waiting Time value. + * @retval None + ************************************************************************************************************/ +void SCI_SetWaitingTimeValue(HT_SCI_TypeDef* SCIx, u32 SCI_WaitingTime) +{ + /* Check the parameters */ + Assert_Param(IS_SCI_WAITING_TIME(SCI_WaitingTime)); + + SCIx->WT = SCI_WaitingTime; +} + +/*********************************************************************************************************//** + * @brief Enable or Disable the Waiting Time Counter. + * @param SCIx: where SCIx is the selected SCI from the SCI peripherals. + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void SCI_WaitingTimeCounterCmd(HT_SCI_TypeDef* SCIx, ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_CONTROL_STATUS(NewState)); + + if (NewState != DISABLE) + { + SCIx->CR |= CR_WTEN_SET; + } + else + { + SCIx->CR &= CR_WTEN_RESET; + } +} + +/*********************************************************************************************************//** + * @brief Sends a data byte through the SCI peripheral. + * @param SCIx: where SCIx is the selected SCI from the SCI peripherals. + * @param SCI_Data: byte to be transmitted. + * @retval None + ************************************************************************************************************/ +void SCI_SendData(HT_SCI_TypeDef* SCIx, u8 SCI_Data) +{ + SCIx->TXB = SCI_Data; +} + +/*********************************************************************************************************//** + * @brief Returns the received data through the SCI peripheral. + * @param SCIx: where SCIx is the selected SCI from the SCI peripherals. + * @retval The value of the received data. + ************************************************************************************************************/ +u8 SCI_ReceiveData(HT_SCI_TypeDef* SCIx) +{ + return ((u8)SCIx->RXB); +} + +/*********************************************************************************************************//** + * @brief Determines the SCI output clock signal is driven by hardware or software. + * @param SCIx: where SCIx is the selected SCI from the SCI peripherals. + * @param SCI_CLKMode: specify the SCI clock pin mode. + * This parameter can be one of the following values: + * @arg SCI_CLK_SOFTWARE : SCI output clock is controlled by software + * @arg SCI_CLK_HARDWARE : SCI output clock is controlled by hardware + * @retval None + ************************************************************************************************************/ +void SCI_ClockModeConfig(HT_SCI_TypeDef* SCIx, u32 SCI_CLKMode) +{ + /* Check the parameters */ + Assert_Param(IS_SCI_CLK_MODE(SCI_CLKMode)); + + if (SCI_CLKMode != SCI_CLK_SOFTWARE) + { + SCIx->CCR |= SCI_CLK_HARDWARE; + } + else + { + SCIx->CCR &= SCI_CLK_SOFTWARE; + } +} + +/*********************************************************************************************************//** + * @brief Output the SCI clock pin low or high by software. + * @param SCIx: where SCIx is the selected SCI from the SCI peripherals. + * @param SCI_CLK: specify if the SCI clock pin to be high or low. + * This parameter can be one of the following values: + * @arg SCI_CLK_HIGH : Software drive SCI output clock high + * @arg SCI_CLK_LOW : Software drive SCI output clock low + * @retval None + ************************************************************************************************************/ +void SCI_SoftwareClockCmd(HT_SCI_TypeDef* SCIx, u32 SCI_CLK) +{ + /* Check the parameters */ + Assert_Param(IS_SCI_CLK(SCI_CLK)); + + if (SCI_CLK != SCI_CLK_LOW) + { + SCIx->CCR |= SCI_CLK_HIGH; + } + else + { + SCIx->CCR &= SCI_CLK_LOW; + } +} + +/*********************************************************************************************************//** + * @brief Output the SCI DIO pin low or high by software. + * @param SCIx: where SCIx is the selected SCI from the SCI peripherals. + * @param SCI_DIO: specify if the SCI DIO pin to be high or low. + * This parameter can be one of the following values: + * @arg SCI_DIO_HIGH : Drive SCI DIO signal high + * @arg SCI_DIO_LOW : Drive SCI DIO signal low + * @retval None + ************************************************************************************************************/ +void SCI_OutputDIO(HT_SCI_TypeDef* SCIx, u32 SCI_DIO) +{ + /* Check the parameters */ + Assert_Param(IS_SCI_DIO(SCI_DIO)); + + if (SCI_DIO != SCI_DIO_LOW) + { + SCIx->CCR |= SCI_DIO_HIGH; + } + else + { + SCIx->CCR &= SCI_DIO_LOW; + } +} + +/*********************************************************************************************************//** + * @brief Enable or Disable the specified SCI interrupt. + * @param SCIx: where SCIx is the selected SCI from the SCI peripherals. + * @param SCI_Int: specify the SCI interrupt source to be enabled or disable. + * This parameter can be any combination of the following values: + * @arg SCI_INT_PAR : SCI parity error interrupt + * @arg SCI_INT_RXC : SCI received character interrupt + * @arg SCI_INT_TXC : SCI transmitted character interrupt + * @arg SCI_INT_WT : SCI waiting timer interrupt + * @arg SCI_INT_CARD : SCI card insert/remove interrupt + * @arg SCI_INT_TXBE : SCI transmit buffer empty interrupt + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void SCI_IntConfig(HT_SCI_TypeDef* SCIx, u32 SCI_Int, ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_SCI_INT(SCI_Int)); + Assert_Param(IS_CONTROL_STATUS(NewState)); + + if (NewState != DISABLE) + { + SCIx->IER |= SCI_Int; + } + else + { + SCIx->IER &= ~SCI_Int; + } +} + +/*********************************************************************************************************//** + * @brief Get the status of specified SCI flag. + * @param SCIx: where SCIx is the selected SCI from the SCI peripherals. + * @param SCI_Flag: specify the flag that is to be check. + * This parameter can be one of the following values: + * @arg SCI_FLAG_PAR : SCI parity error flag + * @arg SCI_FLAG_RXC : SCI received character flag + * @arg SCI_FLAG_TXC : SCI transmitted character flag + * @arg SCI_FLAG_WT : SCI waiting timer flag + * @arg SCI_FLAG_CARD : SCI card insert/remove flag + * @arg SCI_FLAG_TXBE : SCI transmit buffer empty flag + * @retval SET or RESET + ************************************************************************************************************/ +FlagStatus SCI_GetFlagStatus(HT_SCI_TypeDef* SCIx, u32 SCI_Flag) +{ + u32 statusreg = 0; + FlagStatus bitstatus = RESET; + + /* Check the parameters */ + Assert_Param(IS_SCI_FLAG(SCI_Flag)); + + statusreg = SCIx->SR; + + if ((statusreg & SCI_Flag) != (u32)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + return bitstatus; +} + +/*********************************************************************************************************//** + * @brief Clears the flag status of specified SCI flag. + * @param SCIx: where SCIx is the selected SCI from the SCI peripherals. + * @param SCI_Flag: specify the flag to be cleared. + * This parameter can be one of the following values: + * @arg SCI_FLAG_PAR : SCI parity error flag + * @arg SCI_FLAG_TXC : SCI transmitted character flag + * @arg SCI_FLAG_WT : SCI waiting timer flag + * @retval None + ************************************************************************************************************/ +void SCI_ClearFlag(HT_SCI_TypeDef* SCIx, u32 SCI_Flag) +{ + /* Check the parameters */ + Assert_Param(IS_SCI_CLEAR_FLAG(SCI_Flag)); + + if (SCI_Flag != SCI_FLAG_WT) + { + SCIx->SR &= ~SCI_Flag; + } + else + { + SCIx->CR &= CR_WTEN_RESET; + SCIx->CR |= CR_WTEN_SET; + } +} + +/*********************************************************************************************************//** + * @brief Enable or disables the SCI PDMA interface. + * @param SCIx: where SCIx is the selected SCI from the SCI peripherals. + * @param SCI_PDMAREQ: specify the SCI PDMA transfer request to be enabled or disabled. + * This parameter can be any combination of the following values: + * @arg SCI_PDMAREQ_TX : Tx PDMA transfer request + * @arg SCI_PDMAREQ_RX : Rx PDMA transfer request + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void SCI_PDMACmd(HT_SCI_TypeDef* SCIx, u32 SCI_PDMAREQ, ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_SCI_PDMA_REQ(SCI_PDMAREQ)); + Assert_Param(IS_CONTROL_STATUS(NewState)); + + if (NewState != DISABLE) + { + SCIx->CR |= SCI_PDMAREQ; + } + else + { + SCIx->CR &= ~SCI_PDMAREQ; + } +} +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ diff --git a/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/src/ht32f1xxxx_sctm.c b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/src/ht32f1xxxx_sctm.c new file mode 100644 index 0000000000..b824c72b16 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/src/ht32f1xxxx_sctm.c @@ -0,0 +1,2 @@ +The SCTM, PWM, GPTM, and MCTM timer have similar architecture. They use the same driver, +"ht32fxxxxx_tm.c/.h" to save the code size. For those timers, please refet to the TM driver/example. diff --git a/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/src/ht32f1xxxx_sdio.c b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/src/ht32f1xxxx_sdio.c new file mode 100644 index 0000000000..f596560451 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/src/ht32f1xxxx_sdio.c @@ -0,0 +1,355 @@ +/*********************************************************************************************************//** + * @file ht32f1xxxx_sdio.c + * @version $Rev:: 2459 $ + * @date $Date:: 2021-08-13 #$ + * @brief This file provides all the SDIO firmware functions. + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ + +/* Includes ------------------------------------------------------------------------------------------------*/ +#include "ht32f1xxxx_sdio.h" + +/** @addtogroup HT32F1xxxx_Peripheral_Driver HT32F1xxxx Peripheral Driver + * @{ + */ + +/** @defgroup SDIO SDIO + * @brief SDIO driver modules + * @{ + */ + + +/* Global functions ----------------------------------------------------------------------------------------*/ +/** @defgroup SDIO_Exported_Functions SDIO exported functions + * @{ + */ +/*********************************************************************************************************//** + * @brief Deinitialize the SDIO peripheral registers to their default reset values. + * @retval None + ************************************************************************************************************/ +void SDIO_DeInit(void) +{ + RSTCU_PeripReset_TypeDef RSTCUReset = {{0}}; + + RSTCUReset.Bit.SDIO = 1; + RSTCU_PeripReset(RSTCUReset, ENABLE); +} + +/*********************************************************************************************************//** + * @brief Initialize the SDIO peripheral according to the specified parameters in the SDIO_InitStruct. + * @param SDIO_InitStruct: pointer to a SDIO_InitTypeDef structure. + * @retval None + ************************************************************************************************************/ +void SDIO_Init(SDIO_InitTypeDef* SDIO_InitStruct) +{ + u32 t; + + /* Check the parameters */ + Assert_Param(IS_SDIO_CLOC_DIV(SDIO_InitStruct->SDIO_ClockDiv)); + Assert_Param(IS_SDIO_CLOCK_PERIOD(SDIO_InitStruct->SDIO_ClockPeriod)); + Assert_Param(IS_SDIO_CLOCK_POWER_SAVE(SDIO_InitStruct->SDIO_ClockPowerSave)); + Assert_Param(IS_SDIO_BUS_WIDE(SDIO_InitStruct->SDIO_BusWide)); + Assert_Param(IS_SDIO_BUS_MODE(SDIO_InitStruct->SDIO_BusMode)); + + /* Disable the SDIO clock and wait for a while */ + SDIO_ClockCmd(DISABLE); + for (t = 500; t > 0; t--); + + /* Configure SDIO bus and clock */ + HT_SDIO->CR = SDIO_InitStruct->SDIO_BusWide | SDIO_InitStruct->SDIO_BusMode; + + HT_SDIO->CLKCR = SDIO_InitStruct->SDIO_ClockPeriod | SDIO_InitStruct->SDIO_ClockPowerSave | + ((SDIO_InitStruct->SDIO_ClockDiv - 1) << 8); + + /* Enable SDIO bus clock */ + SDIO_ClockCmd(ENABLE); +} + +/*********************************************************************************************************//** + * @brief Enable or disable the SDIO Clock. + * @param Cmd: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void SDIO_ClockCmd(ControlStatus Cmd) +{ + /* Check the parameters */ + Assert_Param(IS_CONTROL_STATUS(Cmd)); + + if (Cmd != DISABLE) + { + BitBand((u32)&HT_SDIO->CLKCR, 2) = Cmd; + } + else + { + BitBand((u32)&HT_SDIO->CLKCR, 2) = Cmd; + } +} + +/*********************************************************************************************************//** + * @brief Initialize the SDIO command according to the specified parameters in the SDIO_CmdInitStruct. + * @param SDIO_CmdInitStruct: pointer to a SDIO_CmdInitTypeDef structure. + * @retval None + ************************************************************************************************************/ +void SDIO_SendCommand(SDIO_CmdInitTypeDef *SDIO_CmdInitStruct) +{ + /* Check the parameters */ + Assert_Param(IS_SDIO_CMD_INDEX(SDIO_CmdInitStruct->SDIO_CmdIndex)); + Assert_Param(IS_SDIO_RESPONSE(SDIO_CmdInitStruct->SDIO_Response)); + Assert_Param(IS_SDIO_DATA_PRESENT(SDIO_CmdInitStruct->SDIO_DatPresent)); + Assert_Param(IS_SDIO_CMD_IDX_CHK(SDIO_CmdInitStruct->SDIO_CmdIdxChk)); + Assert_Param(IS_SDIO_CMD_CRC_CHK(SDIO_CmdInitStruct->SDIO_CmdCrcChk)); + + HT_SDIO->ARG = SDIO_CmdInitStruct->SDIO_Argument; + + HT_SDIO->CMD = SDIO_CmdInitStruct->SDIO_CmdIndex | SDIO_CmdInitStruct->SDIO_Response | + SDIO_CmdInitStruct->SDIO_DatPresent | SDIO_CmdInitStruct->SDIO_CmdIdxChk | + SDIO_CmdInitStruct->SDIO_CmdCrcChk; +} + +/*********************************************************************************************************//** + * @brief Return response received from the card for the last command. + * @param SDIO_RESP: Specify the SDIO response register. + * This parameter can be one of the following values: + * @arg SDIO_RESP1 : Response Register 1 + * @arg SDIO_RESP2 : Response Register 2 + * @arg SDIO_RESP3 : Response Register 3 + * @arg SDIO_RESP4 : Response Register 4 + * @retval The Corresponding response register value. + ************************************************************************************************************/ +u32 SDIO_GetResponse(u32 SDIO_RESP) +{ + /* Check the parameters */ + Assert_Param(IS_SDIO_RESP(SDIO_RESP)); + + return(rw((u32)&HT_SDIO->RESP0 + SDIO_RESP)); +} + +/*********************************************************************************************************//** + * @brief Initialize the SDIO data path according to the specified parameters in the SDIO_DataInitStruct. + * @param SDIO_DataInitStruct: pointer to a SDIO_DataInitTypeDef structure. + * @retval None + ************************************************************************************************************/ +void SDIO_DataConfig(SDIO_DataInitTypeDef* SDIO_DataInitStruct) +{ + /* Check the parameters */ + Assert_Param(IS_SDIO_DATA_BLOCK_COUNT(SDIO_DataInitStruct->SDIO_DataBlockCount)); + Assert_Param(IS_SDIO_DATA_BLOCK_SIZE(SDIO_DataInitStruct->SDIO_DataBlockSize)); + Assert_Param(IS_SDIO_TRANSFER_MODE(SDIO_DataInitStruct->SDIO_TransferMode)); + Assert_Param(IS_SDIO_TRANSFER_DIR(SDIO_DataInitStruct->SDIO_TransferDir)); + Assert_Param(IS_SDIO_DATA_TIMEOUT(SDIO_DataInitStruct->SDIO_DataTimeOut)); + + /* configure DPSM */ + RESET_DPSM(); + HT_SDIO->BLKCNT = SDIO_DataInitStruct->SDIO_DataBlockCount; + HT_SDIO->BLKSIZE = SDIO_DataInitStruct->SDIO_DataBlockSize; + HT_SDIO->TMR = SDIO_DataInitStruct->SDIO_TransferMode | SDIO_DataInitStruct->SDIO_TransferDir; + HT_SDIO->TMOCR = SDIO_DataInitStruct->SDIO_DataTimeOut; +} + +/*********************************************************************************************************//** + * @brief Read one data word from FIFO. + * @return Data received + ************************************************************************************************************/ +u32 SDIO_ReadData(void) +{ + return HT_SDIO->DR; +} + +/*********************************************************************************************************//** + * @brief Write one data word to FIFO. + * @param Data: 32-bit data word to write. + * @retval None + ************************************************************************************************************/ +void SDIO_WriteData(u32 Data) +{ + HT_SDIO->DR = Data; +} + +/*********************************************************************************************************//** + * @brief Return the number of words left to be written to or read from FIFO. + * @return Remaining number of words. + ************************************************************************************************************/ +u32 SDIO_GetFIFOCount(void) +{ + return (HT_SDIO->PSR >> 20); +} + +/*********************************************************************************************************//** + * @brief Enable the SDIO's flag. + * @param SDIO_FLAG: specify the flag to enable. + * This parameter can be one of the following values: + * @arg SDIO_FLAG_CMD_SEND : + * @arg SDIO_FLAG_TRANS_END : + * @arg SDIO_FLAG_BUF_OVERFLOW : + * @arg SDIO_FLAG_BUF_UNDERFLOW : + * @arg SDIO_FLAG_BUF_HALF : + * @arg SDIO_FLAG_BUF_FULL : + * @arg SDIO_FLAG_BUF_EMPTY : + * @arg SDIO_FLAG_CMD_TIMEOUT : + * @arg SDIO_FLAG_CMD_CRCERR : + * @arg SDIO_FLAG_CMD_IDXERR : + * @arg SDIO_FLAG_DATA_TIMEOUT : + * @arg SDIO_FLAG_DATA_CRCERR : + * @arg SDIO_FLAG_CARD_INT : + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void SDIO_FlagConfig(u32 SDIO_FLAG, ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_SDIO_FLAG(SDIO_FLAG)); + Assert_Param(IS_CONTROL_STATUS(NewState)); + + if (NewState != DISABLE) + { + HT_SDIO->SER |= (SDIO_FLAG); + } + else + { + HT_SDIO->SER &= ~(SDIO_FLAG); + } +} + +/*********************************************************************************************************//** + * @brief Check whether the specified SDIO flag is set or not. + * @param SDIO_FLAG: specify the flag to check. + * This parameter can be one of the following values: + * @arg SDIO_FLAG_CMD_SEND : + * @arg SDIO_FLAG_TRANS_END : + * @arg SDIO_FLAG_BUF_OVERFLOW : + * @arg SDIO_FLAG_BUF_UNDERFLOW : + * @arg SDIO_FLAG_BUF_HALF : + * @arg SDIO_FLAG_BUF_FULL : + * @arg SDIO_FLAG_BUF_EMPTY : + * @arg SDIO_FLAG_CMD_TIMEOUT : + * @arg SDIO_FLAG_CMD_CRCERR : + * @arg SDIO_FLAG_CMD_IDXERR : + * @arg SDIO_FLAG_DATA_TIMEOUT : + * @arg SDIO_FLAG_DATA_CRCERR : + * @arg SDIO_FLAG_CARD_INT : + * @retval SET or RESET + ************************************************************************************************************/ +FlagStatus SDIO_GetFlagStatus(u32 SDIO_FLAG) +{ + /* Check the parameters */ + Assert_Param(IS_SDIO_FLAG(SDIO_FLAG)); + + if (HT_SDIO->SR & (SDIO_FLAG)) + { + return SET; + } + else + { + return RESET; + } +} + +/*********************************************************************************************************//** + * @brief Clear the SDIO's pending flags. + * @param SDIO_FLAG: specify the flag to clear. + * This parameter can be one of the following values: + * @arg SDIO_FLAG_CMD_SEND : + * @arg SDIO_FLAG_TRANS_END : + * @arg SDIO_FLAG_BUF_OVERFLOW : + * @arg SDIO_FLAG_BUF_UNDERFLOW : + * @arg SDIO_FLAG_BUF_HALF : + * @arg SDIO_FLAG_BUF_FULL : + * @arg SDIO_FLAG_BUF_EMPTY : + * @arg SDIO_FLAG_ERR : + * @arg SDIO_FLAG_CMD_TIMEOUT : + * @arg SDIO_FLAG_CMD_CRCERR : + * @arg SDIO_FLAG_CMD_ENDERR : + * @arg SDIO_FLAG_CMD_IDXERR : + * @arg SDIO_FLAG_DATA_TIMEOUT : + * @arg SDIO_FLAG_DATA_CRCERR : + * @arg SDIO_FLAG_DATA_ENDERR : + * @arg SDIO_FLAG_CARD_INT : + * @arg SDIO_FLAG_DAT_ERR : + * @arg SDIO_FLAG_CMD_ERR : + * @retval SET or RESET + ************************************************************************************************************/ +void SDIO_ClearFlag(u32 SDIO_FLAG) +{ + /* Check the parameters */ + Assert_Param(IS_SDIO_FLAG(SDIO_FLAG)); + + HT_SDIO->SR = (SDIO_FLAG); + + if (SDIO_FLAG & SDIO_FLAG_BUF_OVERFLOW) + { + HT_SDIO->SER &= ~(SDIO_FLAG_BUF_OVERFLOW); + HT_SDIO->SER |= (SDIO_FLAG_BUF_OVERFLOW); + } + if (SDIO_FLAG & SDIO_FLAG_BUF_UNDERFLOW) + { + HT_SDIO->SER &= ~(SDIO_FLAG_BUF_UNDERFLOW); + HT_SDIO->SER |= (SDIO_FLAG_BUF_UNDERFLOW); + } +} + +/*********************************************************************************************************//** + * @brief Clear the SDIO's pending flags. + * @param SDIO_INT: specify the flag to clear. + * This parameter can be one of the following values: + * @arg SDIO_INT_CMD_SEND : + * @arg SDIO_INT_TRANS_END : + * @arg SDIO_INT_BUF_OVERFLOW : + * @arg SDIO_INT_BUF_UNDERFLOW : + * @arg SDIO_INT_BUF_HALF : + * @arg SDIO_INT_BUF_FULL : + * @arg SDIO_INT_BUF_EMPTY : + * @arg SDIO_INT_CMD_TIMEOUT : + * @arg SDIO_INT_CMD_CRCERR : + * @arg SDIO_INT_CMD_IDXERR : + * @arg SDIO_INT_DATA_TIMEOUT : + * @arg SDIO_INT_DATA_CRCERR : + * @arg SDIO_INT_CARD_INT : + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval SET or RESET + ************************************************************************************************************/ +void SDIO_IntConfig(u32 SDIO_INT, ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_SDIO_INT(SDIO_INT)); + Assert_Param(IS_CONTROL_STATUS(NewState)); + + if (NewState != DISABLE) + { + HT_SDIO->IER |= (SDIO_INT); + } + else + { + HT_SDIO->IER &= ~(SDIO_INT); + } +} +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ diff --git a/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/src/ht32f1xxxx_spi.c b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/src/ht32f1xxxx_spi.c new file mode 100644 index 0000000000..c0e8face8c --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/src/ht32f1xxxx_spi.c @@ -0,0 +1,623 @@ +/*********************************************************************************************************//** + * @file ht32f1xxxx_spi.c + * @version $Rev:: 2797 $ + * @date $Date:: 2022-11-28 #$ + * @brief This file provides all the SPI firmware functions. + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ + +/* Includes ------------------------------------------------------------------------------------------------*/ +#include "ht32f1xxxx_spi.h" + +/** @addtogroup HT32F1xxxx_Peripheral_Driver HT32F1xxxx Peripheral Driver + * @{ + */ + +/** @defgroup SPI SPI + * @brief SPI driver modules + * @{ + */ + + +/* Private constants ---------------------------------------------------------------------------------------*/ +/** @defgroup SPI_Private_Define SPI private definitions + * @{ + */ +/* SPI SPIEN Mask */ +#define CR0_SPIEN_SET (u32)0x00000001 +#define CR0_SPIEN_RESET (u32)0xFFFFFFFE + +/* SPI SELOEN Mask */ +#define CR0_SELOEN_SET (u32)0x00000008 +#define CR0_SELOEN_RESET (u32)0xFFFFFFF7 + +/* SPI SPI DUALEN Mask */ +#define CR0_DUALEN_SET (u32)0x00000040 +#define CR0_DUALEN_RESET (u32)0xFFFFFFBF + +/* SPI SPI GUADTEN Mask */ +#define CR0_GUADTEN_SET (u32)0x00000080 +#define CR0_GUADTEN_RESET (u32)0xFFFFFF7F + +/* SPI FIFOEN Mask */ +#define FCR_FIFOEN_SET (u32)0x00000400 +#define FCR_FIFOEN_RESET (u32)0xFFFFFBFF + +/* SPI DFL Mask */ +#define CR1_DFL_MASK (u32)0x0000000F + +/* SPI FIFO Mask */ +#define FCR_FIFO_MASK (u32)0x0000000F +/** + * @} + */ + + +/* Global functions ----------------------------------------------------------------------------------------*/ +/** @defgroup SPI_Exported_Functions SPI exported functions + * @{ + */ +/*********************************************************************************************************//** + * @brief Deinitialize the SPI peripheral registers to their default reset values. + * @param SPIx: where SPIx is the selected SPI from the SPI peripherals. + * @retval None + ************************************************************************************************************/ +void SPI_DeInit(HT_SPI_TypeDef* SPIx) +{ + RSTCU_PeripReset_TypeDef RSTCUReset = {{0}}; + + /* Check the parameters */ + Assert_Param(IS_SPI(SPIx)); + + if (SPIx == HT_SPI0) + { + RSTCUReset.Bit.SPI0 = 1; + } + else if (SPIx == HT_SPI1) + { + RSTCUReset.Bit.SPI1 = 1; + } + + RSTCU_PeripReset(RSTCUReset, ENABLE); +} + +/*********************************************************************************************************//** + * @brief Initialize the SPIx peripheral according to the specified parameters in the SPI_InitStruct. + * @param SPIx: where SPIx is the selected SPI from the SPI peripherals. + * @param SPI_InitStruct: pointer to a SPI_InitTypeDef structure. + * @retval None + ************************************************************************************************************/ +void SPI_Init(HT_SPI_TypeDef* SPIx, SPI_InitTypeDef* SPI_InitStruct) +{ + u32 tmp; + + /* Check the parameters */ + Assert_Param(IS_SPI(SPIx)); + Assert_Param(IS_SPI_MODE(SPI_InitStruct->SPI_Mode)); + Assert_Param(IS_SPI_FIFO_SET(SPI_InitStruct->SPI_FIFO)); + Assert_Param(IS_SPI_DATALENGTH(SPI_InitStruct->SPI_DataLength)); + Assert_Param(IS_SPI_SEL_MODE(SPI_InitStruct->SPI_SELMode)); + Assert_Param(IS_SPI_SEL_POLARITY(SPI_InitStruct->SPI_SELPolarity)); + Assert_Param(IS_SPI_CPOL(SPI_InitStruct->SPI_CPOL)); + Assert_Param(IS_SPI_CPHA(SPI_InitStruct->SPI_CPHA)); + Assert_Param(IS_SPI_FIRST_BIT(SPI_InitStruct->SPI_FirstBit)); + Assert_Param(IS_SPI_FIFO_LEVEL(SPI_InitStruct->SPI_RxFIFOTriggerLevel)); + Assert_Param(IS_SPI_FIFO_LEVEL(SPI_InitStruct->SPI_TxFIFOTriggerLevel)); + Assert_Param(IS_SPI_CLOCK_PRESCALER(SPI_InitStruct->SPI_ClockPrescaler)); + + /*---------------------------- SPIx Control Register 2 Configuration -------------------------------------*/ + tmp = SPI_InitStruct->SPI_CPOL; + if (tmp == SPI_CPOL_LOW) + { + tmp |= (0x100 << SPI_InitStruct->SPI_CPHA); + } + else + { + tmp |= (0x200 >> SPI_InitStruct->SPI_CPHA); + } + + SPIx->CR1 = SPI_InitStruct->SPI_Mode | SPI_InitStruct->SPI_DataLength | + SPI_InitStruct->SPI_SELMode | SPI_InitStruct->SPI_SELPolarity | + SPI_InitStruct->SPI_FirstBit | tmp; + + /*---------------------------- SPIx FIFO Control Register Configuration ----------------------------------*/ + SPIx->FCR = SPI_InitStruct->SPI_FIFO | SPI_InitStruct->SPI_TxFIFOTriggerLevel | + (SPI_InitStruct->SPI_RxFIFOTriggerLevel << 4); + + /*---------------------------- SPIx Clock Prescaler Register Configuration -------------------------------*/ + #if (LIBCFG_SPI_CLK_PRE_V01) + SPIx->CPR = (SPI_InitStruct->SPI_ClockPrescaler - 1); + #else + SPIx->CPR = (SPI_InitStruct->SPI_ClockPrescaler / 2) - 1; + #endif +} + +/*********************************************************************************************************//** + * @brief Fill each SPI_InitStruct member with its default value. + * @param SPI_InitStruct: pointer to an SPI_InitTypeDef structure. + * @retval None + ************************************************************************************************************/ +void SPI_StructInit(SPI_InitTypeDef* SPI_InitStruct) +{ + /* Initialize the SPI_Mode member */ + SPI_InitStruct->SPI_Mode = SPI_SLAVE; + + /* Initialize the SPI_FIFO member */ + SPI_InitStruct->SPI_FIFO = SPI_FIFO_DISABLE; + + /* Initialize the SPI_DataLength member */ + SPI_InitStruct->SPI_DataLength = SPI_DATALENGTH_16; + + /* Initialize the SPI_SELMode member */ + SPI_InitStruct->SPI_SELMode = SPI_SEL_SOFTWARE; + + /* Initialize the SPI_SELPolarity member */ + SPI_InitStruct->SPI_SELPolarity = SPI_SELPOLARITY_LOW; + + /* Initialize the SPI_CPOL member */ + SPI_InitStruct->SPI_CPOL = SPI_CPOL_LOW; + + /* Initialize the SPI_CPHA member */ + SPI_InitStruct->SPI_CPHA = SPI_CPHA_FIRST; + + /* Initialize the SPI_FirstBit member */ + SPI_InitStruct->SPI_FirstBit = SPI_FIRSTBIT_MSB; + + /* Initialize the SPI_RxFIFOTriggerLevel member */ + SPI_InitStruct->SPI_RxFIFOTriggerLevel = 0; + + /* Initialize the SPI_TxFIFOTriggerLevel member */ + SPI_InitStruct->SPI_TxFIFOTriggerLevel = 0; + + /* Initialize the SPI_ClockPrescaler member */ + SPI_InitStruct->SPI_ClockPrescaler = 2; +} + +/*********************************************************************************************************//** + * @brief Enable or Disable the specified SPI peripheral. + * @param SPIx: where SPIx is the selected SPI from the SPI peripherals. + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void SPI_Cmd(HT_SPI_TypeDef* SPIx, ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_SPI(SPIx)); + Assert_Param(IS_CONTROL_STATUS(NewState)); + + if (NewState != DISABLE) + { + /* Enable the selected SPI peripheral */ + SPIx->CR0 |= CR0_SPIEN_SET; + } + else + { + /* Disable the selected SPI peripheral */ + SPIx->CR0 &= CR0_SPIEN_RESET; + } +} + +/*********************************************************************************************************//** + * @brief Enable or Disable the SEL output for the specified SPI peripheral. + * @param SPIx: where SPIx is the selected SPI from the SPI peripherals. + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void SPI_SELOutputCmd(HT_SPI_TypeDef* SPIx, ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_SPI(SPIx)); + Assert_Param(IS_CONTROL_STATUS(NewState)); + + if (NewState != DISABLE) + { + SPIx->CR0 |= CR0_SELOEN_SET; + } + else + { + SPIx->CR0 &= CR0_SELOEN_RESET; + } +} + +/*********************************************************************************************************//** + * @brief Enable or Disable SPI FIFO. + * @param SPIx: where SPIx is the selected SPI from the SPI peripherals. + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void SPI_FIFOCmd(HT_SPI_TypeDef* SPIx, ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_SPI(SPIx)); + Assert_Param(IS_CONTROL_STATUS(NewState)); + + if (NewState != DISABLE) + { + SPIx->FCR |= FCR_FIFOEN_SET; + } + else + { + SPIx->FCR &= FCR_FIFOEN_RESET; + } +} + +/*********************************************************************************************************//** + * @brief Configure the data length for the selected SPI. + * @param SPIx: where SPIx is the selected SPI from the SPI peripherals. + * @param SPI_DataLength: specify data length of the SPI. + * @retval None + ************************************************************************************************************/ +void SPI_SetDataLength(HT_SPI_TypeDef* SPIx, u16 SPI_DataLength) +{ + /* Check the parameters */ + Assert_Param(IS_SPI(SPIx)); + Assert_Param(IS_SPI_DATALENGTH(SPI_DataLength)); + + /* Clear DFL[3:0] in CR1 */ + SPIx->CR1 &= (u32)~CR1_DFL_MASK; + + /* Set new DFL[3:0] in CR1 */ + SPIx->CR1 |= SPI_DataLength; +} + +/*********************************************************************************************************//** + * @brief SEL pin is configured to be driven by hardware or software. + * @param SPIx: where SPIx is the selected SPI from the SPI peripherals. + * @param SPI_SEL: specify the SPI SEL pin mode. + * This parameter can be one of the following values: + * @arg SPI_SEL_HARDWARE : SEL is driven by hardware + * @arg SPI_SEL_SOFTWARE : SEL is driven by software + * @retval None + ************************************************************************************************************/ +void SPI_SELModeConfig(HT_SPI_TypeDef* SPIx, u32 SPI_SEL) +{ + /* Check the parameters */ + Assert_Param(IS_SPI(SPIx)); + Assert_Param(IS_SPI_SEL_MODE(SPI_SEL)); + + if (SPI_SEL != SPI_SEL_SOFTWARE) + { + SPIx->CR1 |= SPI_SEL_HARDWARE; + } + else + { + SPIx->CR1 &= ~SPI_SEL_HARDWARE; + } +} + +/*********************************************************************************************************//** + * @brief Configure the SEL state by software. + * @param SPIx: where SPIx is the selected SPI from the SPI peripherals. + * @param SPI_SoftwareSEL: specify if the SPI SEL to be active or inactive. + * This parameter can be one of the following values: + * @arg SPI_SEL_ACTIVE : activate SEL signal + * @arg SPI_SEL_INACTIVE : deactivate SEL signal + * @retval None + ************************************************************************************************************/ +void SPI_SoftwareSELCmd(HT_SPI_TypeDef* SPIx, u32 SPI_SoftwareSEL) +{ + /* Check the parameters */ + Assert_Param(IS_SPI(SPIx)); + Assert_Param(IS_SPI_SOFTWARE_SEL(SPI_SoftwareSEL)); + + if (SPI_SoftwareSEL != SPI_SEL_INACTIVE) + { + SPIx->CR0 |= SPI_SEL_ACTIVE; + } + else + { + SPIx->CR0 &= SPI_SEL_INACTIVE; + } +} + +/*********************************************************************************************************//** + * @brief Send a data through the SPIx peripheral. + * @param SPIx: where SPIx is the selected SPI from the SPI peripherals. + * @param SPI_Data: the data to be transmitted. + * @retval None + ************************************************************************************************************/ +void SPI_SendData(HT_SPI_TypeDef* SPIx, SPI_DataTypeDef SPI_Data) +{ + /* Check the parameters */ + Assert_Param(IS_SPI(SPIx)); + Assert_Param(IS_SPI_DATA(SPI_Data)); + + SPIx->DR = SPI_Data; +} + +/*********************************************************************************************************//** + * @brief Return the received data through the SPIx peripheral + * @param SPIx: where SPIx is the selected SPI from the SPI peripherals. + * @retval The value of the received data. + ************************************************************************************************************/ +SPI_DataTypeDef SPI_ReceiveData(HT_SPI_TypeDef* SPIx) +{ + /* Check the parameters */ + Assert_Param(IS_SPI(SPIx)); + + return (SPI_DataTypeDef)SPIx->DR; +} + +/*********************************************************************************************************//** + * @brief Set the value of SPI FIFO Time Out. + * @param SPIx: where SPIx is the selected SPI from the SPI peripherals. + * @param SPI_Timeout: specify the value of Time Out. + * @retval None + ************************************************************************************************************/ +void SPI_SetTimeOutValue(HT_SPI_TypeDef* SPIx, SPI_TimeoutTypeDef SPI_Timeout) +{ + /* Check the parameters */ + Assert_Param(IS_SPI(SPIx)); + + SPIx->FTOCR = SPI_Timeout; +} + +/*********************************************************************************************************//** + * @brief Enable or Disable the specified SPI interrupt. + * @param SPIx: where SPIx is the selected SPI from the SPI peripherals. + * @param SPI_Int: specify if the SPI interrupt source to be enabled or disabled. + * This parameter can be any combination of the following values: + * @arg SPI_INT_TXBE : SPI Tx buffer empty interrupt + * @arg SPI_INT_TXE : SPI Tx empty interrupt + * @arg SPI_INT_RXBNE : SPI Rx buffer not empty interrupt + * @arg SPI_INT_WC : SPI write collision interrupt + * @arg SPI_INT_RO : SPI read overrun interrupt + * @arg SPI_INT_MF : SPI mode fault interrupt + * @arg SPI_INT_SA : SPI slave abort interrupt + * @arg SPI_INT_TO : SPI time out interrupt + * @arg SPI_INT_ALL : All SPI interrupt + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void SPI_IntConfig(HT_SPI_TypeDef* SPIx, u32 SPI_Int, ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_SPI(SPIx)); + Assert_Param(IS_SPI_INT(SPI_Int)); + Assert_Param(IS_CONTROL_STATUS(NewState)); + + if (NewState != DISABLE) + { + SPIx->IER |= SPI_Int; + } + else + { + SPIx->IER &= (u32)~SPI_Int; + } +} + +/*********************************************************************************************************//** + * @brief Check whether the specified SPI flag has been set or not. + * @param SPIx: where SPIx is the selected SPI from the SPI peripherals. + * @param SPI_Flag: specify the flag that is to be check. + * This parameter can be one of the following values: + * @arg SPI_FLAG_TXBE : SPI Tx buffer empty flag + * @arg SPI_FLAG_TXE : SPI Tx empty flag + * @arg SPI_FLAG_RXBNE : SPI Rx buffer not empty flag + * @arg SPI_FLAG_WC : SPI write collision flag + * @arg SPI_FLAG_RO : SPI read overrun flag + * @arg SPI_FLAG_MF : SPI mode fault flag + * @arg SPI_FLAG_SA : SPI slave abort flag + * @arg SPI_FLAG_TOUT : SPI time out flag + * @arg SPI_FLAG_BUSY : SPI busy flag + * @retval SET or RESET + ************************************************************************************************************/ +FlagStatus SPI_GetFlagStatus(HT_SPI_TypeDef* SPIx, u32 SPI_Flag) +{ + FlagStatus bitstatus = RESET; + u32 statusreg = 0; + + /* Check the parameters */ + Assert_Param(IS_SPI(SPIx)); + Assert_Param(IS_SPI_FLAG(SPI_Flag)); + + statusreg = SPIx->SR; + + if ((statusreg & SPI_Flag) != (u32)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + return bitstatus; +} + +/*********************************************************************************************************//** + * @brief Return the status of specified SPI FIFO. + * @param SPIx: where SPIx is the selected SPI from the SPI peripherals. + * @param SPI_FIFODirection: specify the FIFO that is to be checked. + * This parameter can be one of the following values: + * @arg SPI_FIFO_TX : + * @arg SPI_FIFO_RX : + * @retval The number of data in Tx FIFO or Rx FIFO. + ************************************************************************************************************/ +u8 SPI_GetFIFOStatus(HT_SPI_TypeDef* SPIx, u32 SPI_FIFODirection) +{ + u32 tmpreg; + + /* Check the parameters */ + Assert_Param(IS_SPI(SPIx)); + Assert_Param(IS_SPI_FIFO_DIRECTION(SPI_FIFODirection)); + + if (SPI_FIFODirection == SPI_FIFO_TX) + { + tmpreg = SPIx->FSR & FCR_FIFO_MASK; + } + else + { + tmpreg = (SPIx->FSR & (FCR_FIFO_MASK << 4)) >> 4; + } + + return (u8)tmpreg; +} + +/*********************************************************************************************************//** + * @brief Clear the specified SPI flag. + * @param SPIx: where SPIx is the selected SPI from the SPI peripherals. + * @param SPI_Flag: specify the flag that is to be cleared. + * This parameter can be one of the following values: + * @arg SPI_FLAG_WC : SPI write collision flag + * @arg SPI_FLAG_RO : SPI read overrun flag + * @arg SPI_FLAG_MF : SPI mode fault flag + * @arg SPI_FLAG_SA : SPI slave abort flag + * @arg SPI_FLAG_TOUT : SPI time out flag + * @retval None + ************************************************************************************************************/ +void SPI_ClearFlag(HT_SPI_TypeDef* SPIx, u32 SPI_Flag) +{ + /* Check the parameters */ + Assert_Param(IS_SPI(SPIx)); + Assert_Param(IS_SPI_FLAG_CLEAR(SPI_Flag)); + + SPIx->SR = SPI_Flag; +} + +/*********************************************************************************************************//** + * @brief Set the trigger level of SPI FIFO. + * @param SPIx: where SPIx is the selected SPI from the SPI peripherals. + * @param SPI_FIFODirection: specify the FIFO that is to be set. + * This parameter can be one of the following values: + * @arg SPI_FIFO_TX : + * @arg SPI_FIFO_RX : + * @param SPI_FIFOLevel: Specify the FIFO trigger level. + * @retval None + ************************************************************************************************************/ +void SPI_FIFOTriggerLevelConfig(HT_SPI_TypeDef* SPIx, u32 SPI_FIFODirection, u8 SPI_FIFOLevel) +{ + /* Check the parameters */ + Assert_Param(IS_SPI(SPIx)); + Assert_Param(IS_SPI_FIFO_DIRECTION(SPI_FIFODirection)); + Assert_Param(IS_SPI_FIFO_LEVEL(SPI_FIFOLevel)); + + if (SPI_FIFODirection == SPI_FIFO_TX) + { + SPIx->FCR = ((SPIx->FCR & (0x00000400 | (FCR_FIFO_MASK << 4))) | SPI_FIFOLevel); + } + else + { + SPIx->FCR = ((SPIx->FCR & (0x00000400 | FCR_FIFO_MASK)) | (SPI_FIFOLevel << 4)); + } +} + +/*********************************************************************************************************//** + * @brief Enable or Disable the SPIx PDMA interface. + * @param SPIx: where SPIx is the selected SPI from the SPI peripherals. + * @param SPI_PDMAREQ: specify the SPI PDMA transfer request to be enabled or disabled. + * This parameter can be any combination of the following values: + * @arg SPI_PDMAREQ_TX : Tx PDMA transfer request + * @arg SPI_PDMAREQ_RX : Rx PDMA transfer request + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void SPI_PDMACmd(HT_SPI_TypeDef* SPIx, u32 SPI_PDMAREQ, ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_SPI(SPIx)); + Assert_Param(IS_SPI_PDMA_REQ(SPI_PDMAREQ)); + Assert_Param(IS_CONTROL_STATUS(NewState)); + + if (NewState != DISABLE) + { + SPIx->CR0 |= SPI_PDMAREQ; + } + else + { + SPIx->CR0 &= ~SPI_PDMAREQ; + } +} + +/*********************************************************************************************************//** + * @brief Enable or Disable the SPIx dual port read interface. + * @param SPIx: where SPIx is the selected SPI from the SPI peripherals. + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void SPI_DUALCmd(HT_SPI_TypeDef* SPIx, ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_SPI(SPIx)); + Assert_Param(IS_CONTROL_STATUS(NewState)); + + (NewState == ENABLE)?(SPIx->CR0 |= CR0_DUALEN_SET):(SPIx->CR0 &= CR0_DUALEN_RESET); +} + +/*********************************************************************************************************//** + * @brief Enable or Disable the SPIx guard time selection function. + * @param SPIx: where SPIx is the selected SPI from the SPI peripherals. + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void SPI_GUARDTCmd(HT_SPI_TypeDef* SPIx, ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_SPI(SPIx)); + Assert_Param(IS_CONTROL_STATUS(NewState)); + + (NewState == ENABLE) ? (SPIx->CR0 |= CR0_GUADTEN_SET) : (SPIx->CR0 &= CR0_GUADTEN_RESET); +} + +/*********************************************************************************************************//** + * @brief Set the SPIx guard time length. + * @param SPIx: where SPIx is the selected SPI from the SPI peripherals. + * @param Guard_Time: number of SCK to be the guard time length. + * This parameter can be: SPI_GUADTIME_1_SCK to SPI_GUADTIME_16_SCK. + * @retval None + ************************************************************************************************************/ +void SPI_GUARDTConfig(HT_SPI_TypeDef* SPIx, u32 Guard_Time) +{ + /* Check the parameters */ + Assert_Param(IS_SPI(SPIx)); + Assert_Param(IS_SPI_GUADTIME(Guard_Time)); + + SPIx->CR0 = (SPIx->CR0 & 0xF0FF) | (Guard_Time << 8); +} + +/*********************************************************************************************************//** + * @brief Set the SPIx chip select hold time. + * @param SPIx: where SPIx is the selected SPI from the SPI peripherals. + * @param CS_Hold_Time: number of SCK to be the hold time length. + * This parameter can be: 0 ~ 15 + * @retval None + ************************************************************************************************************/ +void SPI_SELHTConfig(HT_SPI_TypeDef* SPIx, u32 CS_Hold_Time) +{ + /* Check the parameters */ + Assert_Param(IS_SPI(SPIx)); + Assert_Param(IS_SPI_SELHOLDTIME(CS_Hold_Time)); + + SPIx->CR0 = (SPIx->CR0 & 0x0FFF) | (CS_Hold_Time << 12); +} +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ diff --git a/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/src/ht32f1xxxx_tm.c b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/src/ht32f1xxxx_tm.c new file mode 100644 index 0000000000..df486b5523 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/src/ht32f1xxxx_tm.c @@ -0,0 +1,1656 @@ +/*********************************************************************************************************//** + * @file ht32f1xxxx_tm.c + * @version $Rev:: 2973 $ + * @date $Date:: 2023-10-30 #$ + * @brief This file provides all the TM firmware functions. + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ + +/* Includes ------------------------------------------------------------------------------------------------*/ +#include "ht32f1xxxx_tm.h" + +/** @addtogroup HT32F1xxxx_Peripheral_Driver HT32F1xxxx Peripheral Driver + * @{ + */ + +/** @defgroup TM TM + * @brief TM driver modules + * @{ + */ + + +/* Private constants ---------------------------------------------------------------------------------------*/ +/** @defgroup TM_Private_Define TM private definitions + * @{ + */ +#define CNTCFR_UEVDIS 0x00000001ul +#define CNTCFR_UGDIS 0x00000002ul +#define CNTCFR_DIR 0x01000000ul +#define CNTCFR_CMSEL_MASK ~0x00030000ul +#define CNTCFR_CKDIV_MASK ~0x00000300ul + +#define MDCFR_SPMSET 0x01000000ul +#define MDCFR_TSE 0x00000001ul +#define MDCFR_SMSEL_MASK ~0x00000700ul +#define MDCFR_MMSEL_MASK ~0x00070000ul + +#define TRCFR_ECME 0x01000000ul +#define TRCFR_ETI_POL 0x00010000ul +#define TRCFR_ETI_PSC_MASK ~0x00003000ul +#define TRCFR_ETIF_MASK ~0x00000F00ul +#define TRCFR_TRSEL_MASK ~0x0000000Ful +#define TRCFR_ETI_CONF_MASK ~0x00013F00ul + +#define CTR_TME 0x00000001ul +#define CTR_CRBE 0x00000002ul +#define CTR_CHCCDS 0x00010000ul + +#define CH0ICFR_CH0SRC 0x80000000ul +#define CHICFR_CHF_MASK ~0x0000000Ful +#define CHICFR_CHCCS_MASK ~0x00030000ul +#define CHICFR_CHPSC_MASK ~0x000C0000ul + +#define CHOCFR_REFCE 0x00000008ul +#define CHOCFR_CHPRE 0x00000010ul +#define CHOCFR_IMAE 0x00000020ul +#define CHOCFR_CHOM_MASK ~0x00000107ul + +#define CHPOLR_CH0P 0x00000001ul +#define CHPOLR_CH1P 0x00000004ul +/** + * @} + */ + +/* Private function prototypes -----------------------------------------------------------------------------*/ +static void _TM_CHx_Config(HT_TM_TypeDef* TMx, TM_CH_Enum Ch, TM_CHP_Enum Pol, TM_CHCCS_Enum Sel, u8 Filter); + +/* Global functions ----------------------------------------------------------------------------------------*/ +/** @defgroup TM_Exported_Functions TM exported functions + * @{ + */ +/*********************************************************************************************************//** + * @brief Deinitialize the TMx peripheral registers to their default reset values. + * @param TMx: where TMx is the selected TM from the TM peripherals. + * @retval None + ************************************************************************************************************/ +void TM_DeInit(HT_TM_TypeDef* TMx) +{ + RSTCU_PeripReset_TypeDef RSTCUReset = {{0}}; + + /* Check the parameters */ + Assert_Param(IS_TM(TMx)); + + if (TMx == HT_GPTM0) + { + RSTCUReset.Bit.GPTM0 = 1; + } + #if (!LIBCFG_NO_GPTM1) + else if (TMx == HT_GPTM1) + { + RSTCUReset.Bit.GPTM1 = 1; + } + #endif + #if (!LIBCFG_NO_MCTM0) + else if (TMx == HT_MCTM0) + { + RSTCUReset.Bit.MCTM0 = 1; + } + #endif + #if (!LIBCFG_NO_MCTM1) + else if (TMx == HT_MCTM1) + { + RSTCUReset.Bit.MCTM1 = 1; + } + #endif + #if (LIBCFG_PWM0) + else if (TMx == HT_PWM0) + { + RSTCUReset.Bit.PWM0 = 1; + } + #endif + #if (LIBCFG_SCTM0) + else if (TMx == HT_SCTM0) + { + RSTCUReset.Bit.SCTM0 = 1; + } + #endif + #if (LIBCFG_SCTM1) + else if (TMx == HT_SCTM1) + { + RSTCUReset.Bit.SCTM1 = 1; + } + #endif + + RSTCU_PeripReset(RSTCUReset, ENABLE); +} + +/*********************************************************************************************************//** + * @brief Initialize the TMx counter to reload, prescaler, counter mode and repetition counter. + * @param TMx: where TMx is the selected TM from the TM peripheral. + * @param TimeBaseInit: Point to a \ref TM_TimeBaseInitTypeDef that contains the configuration information. + * @retval None + ************************************************************************************************************/ +void TM_TimeBaseInit(HT_TM_TypeDef* TMx, TM_TimeBaseInitTypeDef* TimeBaseInit) +{ + /* Check the parameters */ + Assert_Param(IS_TM(TMx)); + Assert_Param(IS_TM_CNT_MODE(TimeBaseInit->CounterMode)); + Assert_Param(IS_TM_PSC_RLD(TimeBaseInit->PSCReloadTime)); + + /* Set the counter reload value */ + TMx->CRR = TimeBaseInit->CounterReload; + + /* Set the Prescaler value */ + TMx->PSCR = TimeBaseInit->Prescaler; + + /* Select the Counter Mode */ + TMx->CNTCFR &= CNTCFR_CMSEL_MASK; /* CNTCFR_DIR is read only when the timer configured as */ + TMx->CNTCFR &= ~(u32)CNTCFR_DIR; /* Center-aligned mode. Reset mode first and then reset the */ + /* CNTCFR_DIR bit (separate as two steps). */ + + TMx->CNTCFR |= TimeBaseInit->CounterMode; + + #if (!LIBCFG_NO_MCTM0) + if ((TMx == HT_MCTM0) || (TMx == HT_MCTM1)) + { + /* Set the Repetition value */ + TMx->REPR = TimeBaseInit->RepetitionCounter; + } + #endif + + /* To reload the Prescaler value immediatly or next update event */ + TMx->EVGR = TimeBaseInit->PSCReloadTime; +} + +/*********************************************************************************************************//** + * @brief Initialize the TMx channel N output. + * @param TMx: where TMx is the selected TM from the TM peripherals. + * @param OutInit: Point to a \ref TM_OutputInitTypeDef structure that contains + the configuration information. + * @retval None + ************************************************************************************************************/ +void TM_OutputInit(HT_TM_TypeDef* TMx, TM_OutputInitTypeDef* OutInit) +{ + vu32 *pOcfr = (vu32*)&TMx->CH0OCFR + OutInit->Channel; + vu32 *pCcr = (vu32*)&TMx->CH0CCR + OutInit->Channel; + vu32 *pAcr = (vu32*)&TMx->CH0ACR + OutInit->Channel; + u8 bChPos = OutInit->Channel << 1; + u32 wTmpMask; + u32 wTmpReg; + u32 uIsMCTM = 0; + + #if (!LIBCFG_NO_MCTM0) + if ((TMx == HT_MCTM0) || (TMx == HT_MCTM1)) + { + uIsMCTM = 1; + } + #endif + if (uIsMCTM) + { + wTmpMask = ~(0x3ul << bChPos); + } + else + { + wTmpMask = ~(0x1ul << bChPos); + } + + /* Check the parameters */ + Assert_Param(IS_TM(TMx)); + Assert_Param(IS_TM_CH(OutInit->Channel)); + Assert_Param(IS_TM_OM(OutInit->OutputMode)); + Assert_Param(IS_TM_CHCTL(OutInit->Control)); + Assert_Param(IS_TM_CHP(OutInit->Polarity)); + + #if (!LIBCFG_NO_MCTM0) + if (uIsMCTM) + { + Assert_Param(IS_TM_CHCTL(OutInit->ControlN)); + Assert_Param(IS_TM_CHP(OutInit->PolarityN)); + Assert_Param(IS_MCTM_OIS(OutInit->IdleState)); + Assert_Param(IS_MCTM_OIS(OutInit->IdleStateN)); + } + #endif + + + /* Disable the Channel */ + TMx->CHCTR &= wTmpMask; + + /* Set the Output Compare Polarity */ + wTmpReg = TMx->CHPOLR & wTmpMask; + + if (uIsMCTM) + { + wTmpReg |= (u32)(OutInit->Polarity | (OutInit->PolarityN << 1)) << bChPos; + } + else + { + wTmpReg |= (u32)(OutInit->Polarity) << bChPos; + } + + TMx->CHPOLR = wTmpReg; + + /* Set the Output Idle State */ + if (uIsMCTM) + { + wTmpReg = TMx->CHBRKCFR & wTmpMask; + wTmpReg |= (u32)(OutInit->IdleState | (OutInit->IdleStateN << 1)) << bChPos; + TMx->CHBRKCFR = wTmpReg; + } + + /* Select the Output Compare Mode */ + *pOcfr &= CHOCFR_CHOM_MASK; + *pOcfr |= OutInit->OutputMode; + + /* Set the Capture Compare Register value */ + *pCcr = OutInit->Compare; + + /* Set the Asymmetric Compare Register value */ + *pAcr = OutInit->AsymmetricCompare; + + /* Set the channel state */ + if (uIsMCTM) + { + TMx->CHCTR |= (u32)(OutInit->Control | (OutInit->ControlN << 1)) << bChPos; + } + else + { + TMx->CHCTR |= (u32)(OutInit->Control) << bChPos; + } +} + +/*********************************************************************************************************//** + * @brief Initialize input capture of the TMx channel. + * @param TMx: where TMx is the selected TM from the TM peripherals. + * @param CapInit: Point to a \ref TM_CaptureInitTypeDef structure that contains the configuration + * information. + * @retval None + ************************************************************************************************************/ +void TM_CaptureInit(HT_TM_TypeDef* TMx, TM_CaptureInitTypeDef* CapInit) +{ + /* Check the parameters */ + Assert_Param(IS_TM(TMx)); + Assert_Param(IS_TM_CH(CapInit->Channel)); + Assert_Param(IS_TM_CHP(CapInit->Polarity)); + Assert_Param(IS_TM_CHCCS(CapInit->Selection)); + Assert_Param(IS_TM_CHPSC(CapInit->Prescaler)); + Assert_Param(IS_TM_FILTER(CapInit->Filter)); + + _TM_CHx_Config(TMx, CapInit->Channel, CapInit->Polarity, CapInit->Selection, CapInit->Filter); + + /* Set the Input Capture Prescaler value */ + TM_CHPSCConfig(TMx, CapInit->Channel, CapInit->Prescaler); +} + +/*********************************************************************************************************//** + * @brief Configure the TMx to measure an external PWM signal. + * @param TMx: where TMx is the selected TM from the TM peripherals. + * @param CapInit: Point to a \ref TM_CaptureInitTypeDef structure that contains the configuration + * information. + * @retval None + ************************************************************************************************************/ +void TM_PwmInputInit(HT_TM_TypeDef* TMx, TM_CaptureInitTypeDef* CapInit) +{ + TM_CHP_Enum OppositePol; + TM_CHCCS_Enum OppositeSel; + TM_CH_Enum OppositeChannel; + + /* Check the parameters */ + Assert_Param(IS_TM(TMx)); + Assert_Param(IS_TM_CH_PWMI(CapInit->Channel)); + Assert_Param(IS_TM_CHP(CapInit->Polarity)); + Assert_Param(IS_TM_CHCCS(CapInit->Selection)); + Assert_Param(IS_TM_CHPSC(CapInit->Prescaler)); + Assert_Param(IS_TM_FILTER(CapInit->Filter)); + + /* Select the Opposite Input Polarity */ + if (CapInit->Polarity == TM_CHP_NONINVERTED) + { + OppositePol = TM_CHP_INVERTED; + } + else + { + OppositePol = TM_CHP_NONINVERTED; + } + + /* Select the Opposite Input */ + if (CapInit->Selection == TM_CHCCS_DIRECT) + { + OppositeSel = TM_CHCCS_INDIRECT; + } + else + { + OppositeSel = TM_CHCCS_DIRECT; + } + + if (CapInit->Channel == TM_CH_0) + { + OppositeChannel = TM_CH_1; + } + else + { + OppositeChannel = TM_CH_0; + } + + /* Capture Channel Configuration */ + _TM_CHx_Config(TMx, CapInit->Channel, CapInit->Polarity, CapInit->Selection, CapInit->Filter); + + /* Set the Input Capture Prescaler value */ + TM_CHPSCConfig(TMx, CapInit->Channel, CapInit->Prescaler); + + /* Opposite Channel Configuration */ + _TM_CHx_Config(TMx, OppositeChannel, OppositePol, OppositeSel, CapInit->Filter); + + /* Set the Input Capture Prescaler value */ + TM_CHPSCConfig(TMx, OppositeChannel, CapInit->Prescaler); +} + +/*********************************************************************************************************//** + * @brief Fill each TimeBaseInit member with its default value. + * @param TimeBaseInit: Point to a \ref TM_TimeBaseInitTypeDef structure. + * @retval None + ************************************************************************************************************/ +void TM_TimeBaseStructInit(TM_TimeBaseInitTypeDef* TimeBaseInit) +{ + /* Set the default configuration */ + TimeBaseInit->CounterMode = TM_CNT_MODE_UP; + TimeBaseInit->CounterReload = 0xFFFF; + TimeBaseInit->Prescaler = 0x0000; + TimeBaseInit->PSCReloadTime = TM_PSC_RLD_IMMEDIATE; + TimeBaseInit->RepetitionCounter = 0; +} + +/*********************************************************************************************************//** + * @brief Fill each OutInit member with its default value. + * @param OutInit: Point to a \ref TM_OutputInitTypeDef structure. + * @retval None + ************************************************************************************************************/ +void TM_OutputStructInit(TM_OutputInitTypeDef* OutInit) +{ + /* Set the default configuration */ + OutInit->Channel = TM_CH_0; + OutInit->OutputMode = TM_OM_MATCH_NOCHANGE; + OutInit->Control = TM_CHCTL_DISABLE; + OutInit->ControlN = TM_CHCTL_DISABLE; + OutInit->Polarity = TM_CHP_NONINVERTED; + OutInit->PolarityN = TM_CHP_NONINVERTED; + OutInit->IdleState = MCTM_OIS_LOW; + OutInit->IdleStateN = MCTM_OIS_LOW; + OutInit->Compare = 0x0000; + OutInit->AsymmetricCompare = 0x0000; +} + +/*********************************************************************************************************//** + * @brief Fill each CapInit member with its default value. + * @param CapInit: Point to a \ref TM_CaptureInitTypeDef structure. + * @retval None + ************************************************************************************************************/ +void TM_CaptureStructInit(TM_CaptureInitTypeDef* CapInit) +{ + /* Set the default configuration */ + CapInit->Channel = TM_CH_0; + CapInit->Polarity = TM_CHP_NONINVERTED; + CapInit->Selection = TM_CHCCS_DIRECT; + CapInit->Prescaler = TM_CHPSC_OFF; + CapInit->Filter = 0x00; +} + +/*********************************************************************************************************//** + * @brief Enable or Disable TMx counter. + * @param TMx: where TMx is the selected TM from the TM peripherals. + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void TM_Cmd(HT_TM_TypeDef* TMx, ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_TM(TMx)); + Assert_Param(IS_CONTROL_STATUS(NewState)); + + if (NewState != DISABLE) + { + /* Enable the TM Counter */ + TMx->CTR |= CTR_TME; + } + else + { + /* Disable the TM Counter */ + TMx->CTR &= ~CTR_TME; + } +} + +/*********************************************************************************************************//** + * @brief Configure external clock mode of the TMx. Used ITIx as the clock source. + * @param TMx: where TMx is the selected TM from the TM peripherals. + * @param Iti: Trigger source. + * This parameter can be one of the following values: + * @arg TM_TRSEL_ITI0: Internal trigger 0 + * @arg TM_TRSEL_ITI1: Internal trigger 1 + * @arg TM_TRSEL_ITI2: Internal trigger 2 + * @retval None + ************************************************************************************************************/ +void TM_ItiExternalClockConfig(HT_TM_TypeDef* TMx, TM_TRSEL_Enum Iti) +{ + /* Check the parameters */ + Assert_Param(IS_TM(TMx)); + Assert_Param(IS_TM_ITI(Iti)); + + /* Select the Internal Trigger. Slave mode will be disable in this function */ + TM_StiConfig(TMx, Iti); + + /* Select the STIED as external clock source */ + TMx->MDCFR |= TM_SMSEL_STIED; +} + +/*********************************************************************************************************//** + * @brief Configure external clock mode of the TMx. Used CHx as the clock source. + * @param TMx: where TMx is the selected TM from the TM peripherals. + * @param Sel: Specify the channel source. + * This parameter can be one of the following values: + * @arg TM_TRSEL_TI0BED : TI0 both edge detector + * @arg TM_TRSEL_TI0S0 : Filtered timer input 0 + * @arg TM_TRSEL_TI1S1 : Filtered timer input 1 + * @param Pol: Specify the CHx Polarity. + * This parameter can be one of the following values: + * @arg TM_CHP_NONINVERTED : active high. + * @arg TM_CHP_INVERTED : active low. + * @param Filter: Specify the filter value. + * This parameter must be a value between 0x0 and 0xF. + * @retval None + ************************************************************************************************************/ +void TM_ChExternalClockConfig(HT_TM_TypeDef* TMx, TM_TRSEL_Enum Sel, TM_CHP_Enum Pol, u8 Filter) +{ + /* Check the parameters */ + Assert_Param(IS_TM(TMx)); + Assert_Param(IS_TM_TRSEL_CH(Sel)); + Assert_Param(IS_TM_CHP(Pol)); + Assert_Param(IS_TM_FILTER(Filter)); + + /* Configure the Timer Input Clock Source */ + if (Sel == TM_TRSEL_TI1S1) + { + _TM_CHx_Config(TMx, TM_CH_1, Pol, TM_CHCCS_DIRECT, Filter); + } + else + { + _TM_CHx_Config(TMx, TM_CH_0, Pol, TM_CHCCS_DIRECT, Filter); + } + + /* Select the external clock source. Slave mode will be disable in this function */ + TM_StiConfig(TMx, Sel); + + /* Select the STIED as external clock source */ + TMx->MDCFR |= TM_SMSEL_STIED; +} + +/*********************************************************************************************************//** + * @brief Configure external clock mode of the TMx. Used ETI as the clock source. + * @param TMx: where TMx is the selected TM from the TM peripheral. + * @param Psc: The external Trigger Prescaler. + * It can be one of the following values: + * @arg TM_ETIPSC_OFF : ETI prescaler off + * @arg TM_ETIPSC_2 : ETIP frequency divided by 2 + * @arg TM_ETIPSC_4 : ETIP frequency divided by 4 + * @arg TM_ETIPSC_8 : ETIP frequency divided by 8 + * @param Pol: The external trigger input polarity. + * It can be one of the following values: + * @arg TM_ETIPOL_NONINVERTED : Active high level or rising edge + * @arg TM_ETIPOL_INVERTED : Active low level or falling edge + * @param Filter: Filter for ETI input. + * This parameter must be a value between 0x00 and 0x0F + * @retval None + ************************************************************************************************************/ +void TM_EtiExternalClockConfig(HT_TM_TypeDef* TMx, TM_ETIPSC_Enum Psc, TM_ETIPOL_Enum Pol, u8 Filter) +{ + /* Check the parameters */ + Assert_Param(IS_TM(TMx)); + Assert_Param(IS_TM_ETIPSC(Psc)); + Assert_Param(IS_TM_ETIPOL(Pol)); + Assert_Param(IS_TM_FILTER(Filter)); + + /* Configure the ETI Clock source */ + TM_EtiConfig(TMx, Psc, Pol, Filter); + + /* Enable the external clock mode */ + TMx->TRCFR |= TRCFR_ECME; +} + +/*********************************************************************************************************//** + * @brief Configure external trigger input (ETI) of the TMx. + * @param TMx: where TMx is the selected TM from the TM peripheral. + * @param Psc: The external Trigger Prescaler. + * It can be one of the following values: + * @arg TM_ETIPSC_OFF : ETI prescaler off + * @arg TM_ETIPSC_2 : ETIP frequency divided by 2 + * @arg TM_ETIPSC_4 : ETIP frequency divided by 4 + * @arg TM_ETIPSC_8 : ETIP frequency divided by 8 + * @param Pol: The external trigger input polarity. + * It can be one of the following values: + * @arg TM_ETIPOL_NONINVERTED : Active high level or rising edge + * @arg TM_ETIPOL_INVERTED : Active low level or falling edge + * @param Filter: Filter for ETI input. + * This parameter must be a value between 0x00 and 0x0F + * @retval None + ************************************************************************************************************/ +void TM_EtiConfig(HT_TM_TypeDef* TMx, TM_ETIPSC_Enum Psc, TM_ETIPOL_Enum Pol, u8 Filter) +{ + u32 wTrcfr; + + /* Check the parameters */ + Assert_Param(IS_TM(TMx)); + Assert_Param(IS_TM_ETIPSC(Psc)); + Assert_Param(IS_TM_ETIPOL(Pol)); + Assert_Param(IS_TM_FILTER(Filter)); + + /* Get TRCFR value with cleared ETI configuration bits */ + wTrcfr = TMx->TRCFR & TRCFR_ETI_CONF_MASK; + + /* Set the prescaler, filter and polarity for ETI input */ + wTrcfr |= (u32)Psc | Pol | ((u32)Filter << 8); + + /* Write to TMx TRCFR */ + TMx->TRCFR = wTrcfr; +} + +/*********************************************************************************************************//** + * @brief Configure prescaler of the TMx. + * @param TMx: where TMx is the selected TM from the TM peripherals. + * @param Psc: Specify the prescaler value. + * @param PscReloadTime: Specify the TM prescaler reload time. + * This parameter can be one of the following values: + * @arg TM_PSC_RLD_UPDATE : The prescaler is loaded at the next update event. + * @arg TM_PSC_RLD_IMMEDIATE : The prescaler is loaded immediatly. + * @retval None + ************************************************************************************************************/ +void TM_PrescalerConfig(HT_TM_TypeDef* TMx, u16 Psc, TM_PSC_RLD_Enum PscReloadTime) +{ + /* Check the parameters */ + Assert_Param(IS_TM(TMx)); + Assert_Param(IS_TM_PSC_RLD(PscReloadTime)); + + /* Set the prescaler value */ + TMx->PSCR = Psc; + + /* Set the UEVG bit or not */ + TMx->EVGR = PscReloadTime; +} + +/*********************************************************************************************************//** + * @brief Configure counter mode of the TMx. + * @param TMx: where TMx is the selected TM from the TM peripherals. + * @param Mod: Specify the counter mode to be used. + * This parameter can be one of the following values: + * @arg TM_CNT_MODE_UP : TM up counting mode. + * @arg TM_CNT_MODE_DOWN : TM down counting mode. + * @arg TM_CNT_MODE_CA1 : TM center aligned mode 1. + * @arg TM_CNT_MODE_CA2 : TM center aligned mode 2. + * @arg TM_CNT_MODE_CA3 : TM center aligned mode 3. + * @retval None + ************************************************************************************************************/ +void TM_CounterModeConfig(HT_TM_TypeDef* TMx, TM_CNT_MODE_Enum Mod) +{ + /* Check the parameters */ + Assert_Param(IS_TM(TMx)); + Assert_Param(IS_TM_CNT_MODE(Mod)); + + /* Reset the CMSEL and DIR Bits */ + TMx->CNTCFR &= CNTCFR_CMSEL_MASK; /* CNTCFR_DIR is read only when the timer configured as */ + TMx->CNTCFR &= ~(u32)CNTCFR_DIR; /* Center-aligned mode. Reset mode first and then reset the */ + /* CNTCFR_DIR bit (separate as two steps). */ + + /* Set the Counter Mode */ + TMx->CNTCFR |= Mod; +} + +/*********************************************************************************************************//** + * @brief Select the STI source. + * @param TMx: where TMx is the selected TM from the TM peripherals. + * @param Sel: Specify the STI source. + * This parameter can be one of the following: + * @arg TM_TRSEL_ITI0 : Internal trigger 0. + * @arg TM_TRSEL_ITI1 : Internal trigger 1. + * @arg TM_TRSEL_ITI2 : Internal trigger 2. + * @arg TM_TRSEL_TI0BED : TI0 both edge detector. + * @arg TM_TRSEL_TI0S0 : Filtered channel 0 input. + * @arg TM_TRSEL_TI1S1 : Filtered channel 1 input. + * @arg TM_TRSEL_ETIF : External trigger input. + * @arg TM_TRSEL_UEVG : Trigger by setting UEVG bit. + * @retval None + ************************************************************************************************************/ +void TM_StiConfig(HT_TM_TypeDef* TMx, TM_TRSEL_Enum Sel) +{ + u32 wTrcfr; + + /* Check the parameters */ + Assert_Param(IS_TM(TMx)); + Assert_Param(IS_TM_TRSEL(Sel)); + + /* Disable slave mode */ + TMx->MDCFR &= MDCFR_SMSEL_MASK; + + /* Get the TRCFR value with cleared TRSEL */ + wTrcfr = TMx->TRCFR & TRCFR_TRSEL_MASK; + + /* Set the STI source */ + TMx->TRCFR |= wTrcfr | Sel; +} + +/*********************************************************************************************************//** + * @brief Configure encoder interface of the TMx. + * @param TMx: where TMx is the selected TM from the TM peripherals. + * @param DecoderMod: Specify the TMx decoder mode. + * This parameter can be one of the following values: + * @arg TM_SMSEL_DECODER1 : Counter counts on CH0 edge depending on CH1 level. + * @arg TM_SMSEL_DECODER2 : Counter counts on CH1 edge depending on CH0 level. + * @arg TM_SMSEL_DECODER3 : Counter counts on both CH0 and CH1 edges depending on + * the level of the other input. + * @param CH0P: Specify the CH0 polarity. + * This parameter can be one of the following values: + * @arg TM_CHP_NONINVERTED : Active high level or rising edge + * @arg TM_CHP_INVERTED : Active low level or falling edge + * @param CH1P: Specify the CH1 polarity. + * This parameter can be one of the following values: + * @arg TM_CHP_NONINVERTED : Active high level or rising edge + * @arg TM_CHP_INVERTED : Active low level or falling edge + * @retval None + ************************************************************************************************************/ +void TM_DecoderConfig(HT_TM_TypeDef* TMx, TM_SMSEL_Enum DecoderMod, TM_CHP_Enum CH0P, TM_CHP_Enum CH1P) +{ + u32 wMdcfr, wCh0Icfr, wCh1Icfr, wChpolr; + + /* Check the parameters */ + Assert_Param(IS_TM(TMx)); + Assert_Param(IS_TM_SMSEL_DECODER(DecoderMod)); + Assert_Param(IS_TM_CHP(CH0P)); + Assert_Param(IS_TM_CHP(CH1P)); + + /* Get the TMx MDCFR register value */ + wMdcfr = TMx->MDCFR; + + /* Get the TMx CH0ICFR & CH1ICFR register value */ + wCh0Icfr = TMx->CH0ICFR; + wCh1Icfr = TMx->CH1ICFR; + + /* Get the TMx CHPOLR register value */ + wChpolr = TMx->CHPOLR; + + /* Set the decoder mode */ + wMdcfr &= MDCFR_SMSEL_MASK; + wMdcfr |= DecoderMod; + + /* Select the channel 0 and the channel 1 as input and clear CH0SRC */ + wCh0Icfr &= CHICFR_CHCCS_MASK & (~CH0ICFR_CH0SRC); + wCh1Icfr &= CHICFR_CHCCS_MASK; + wCh0Icfr |= TM_CHCCS_DIRECT; + wCh1Icfr |= TM_CHCCS_DIRECT; + + /* Set the CH0 and the CH1 polarities */ + wChpolr &= ~(CHPOLR_CH0P | CHPOLR_CH1P); + wChpolr |= (CH0P | (CH1P << 2)); + + /* Write to TMx MDCFR */ + TMx->MDCFR = wMdcfr; + + /* Write to TMx CH0ICFR & CH1ICFR */ + TMx->CH0ICFR = wCh0Icfr; + TMx->CH1ICFR = wCh1Icfr; + + /* Write to TMx CHPOLR */ + TMx->CHPOLR = wChpolr; +} + +/*********************************************************************************************************//** + * @brief Force the TMx CHnOREF waveform to active or inactive level. + * @param TMx: where TMx is the selected TM from the TM peripherals. + * @param TM_CH_n: Specify the TM channel. + * This parameter can be one of the following values: + * @arg TM_CH_0 : TM channel 0 + * @arg TM_CH_1 : TM channel 1 + * @arg TM_CH_2 : TM channel 2 + * @arg TM_CH_3 : TM channel 3 + * @param ForcedAction: Specify the forced action to be set to the output waveform. + * This parameter can be one of the following values: + * @arg TM_OM_FORCED_ACTIVE : Forced active level on CH0OREF + * @arg TM_OM_FORCED_INACTIVE : Forced inactive level on CH0OREF. + * @retval None + ************************************************************************************************************/ +void TM_ForcedOREF(HT_TM_TypeDef* TMx, TM_CH_Enum TM_CH_n, TM_OM_Enum ForcedAction) +{ + vu32* pCHnOCFR = ((vu32*)&TMx->CH0OCFR) + (TM_CH_n * 1); + + /* Check the parameters */ + Assert_Param(IS_TM(TMx)); + Assert_Param(IS_TM_CH(TM_CH_n)); + Assert_Param(IS_TM_OM_FORCED(ForcedAction)); + + /* Configure The forced output mode */ + *pCHnOCFR = (*pCHnOCFR & CHOCFR_CHOM_MASK) | ForcedAction; +} + +/*********************************************************************************************************//** + * @brief Enable or Disable the TMx CRR preload function. + * @param TMx: where TMx is the selected TM from the TM peripheral. + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void TM_CRRPreloadCmd(HT_TM_TypeDef* TMx, ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_TM(TMx)); + Assert_Param(IS_CONTROL_STATUS(NewState)); + + if (NewState != DISABLE) + { + /* Set the CRR preload control bit */ + TMx->CTR |= CTR_CRBE; + } + else + { + /* Reset the CRR preload control bit */ + TMx->CTR &= ~CTR_CRBE; + } +} + +/*********************************************************************************************************//** + * @brief Enable or Disable the TMx CHxCCR preload function. + * @param TMx: where TMx is the selected TM from the TM peripherals. + * @param Channel: Specify the TM channel. + * This parameter can be one of the following values: + * @arg TM_CH_0 : TM channel 0 + * @arg TM_CH_1 : TM channel 1 + * @arg TM_CH_2 : TM channel 2 + * @arg TM_CH_3 : TM channel 3 + * @param NewState This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void TM_CHCCRPreloadConfig(HT_TM_TypeDef* TMx, TM_CH_Enum Channel, ControlStatus NewState) +{ + vu32 *pOcfr = (vu32*)&TMx->CH0OCFR + Channel; + + /* Check the parameters */ + Assert_Param(IS_TM(TMx)); + Assert_Param(IS_TM_CH(Channel)); + Assert_Param(IS_CONTROL_STATUS(NewState)); + + /* Enable or disable the channel N CCR preload feature */ + if (NewState != DISABLE) + { + *pOcfr |= CHOCFR_CHPRE; + } + else + { + *pOcfr &= ~CHOCFR_CHPRE; + } +} + +/*********************************************************************************************************//** + * @brief Clear or Safeguard the CHxOREF signal when ETI is active. + * @param TMx: where TMx is the selected TM from the TM peripheral. + * @param Channel: Specify the TM channel. + * This parameter can be one of the following values: + * @arg TM_CH_0 : TM channel 0 + * @arg TM_CH_1 : TM channel 1 + * @arg TM_CH_2 : TM channel 2 + * @arg TM_CH_3 : TM channel 3 + * @param NewState This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void TM_ClearOREFConfig(HT_TM_TypeDef* TMx, TM_CH_Enum Channel, ControlStatus NewState) +{ + vu32 *pOcfr = (vu32*)&TMx->CH0OCFR + Channel; + + /* Check the parameters */ + Assert_Param(IS_TM(TMx)); + Assert_Param(IS_TM_CH(Channel)); + Assert_Param(IS_CONTROL_STATUS(NewState)); + + /* Enable or Disable the channel N clear Oref at ETI active function */ + if (NewState != DISABLE) + { + *pOcfr |= CHOCFR_REFCE; + } + else + { + *pOcfr &= ~CHOCFR_REFCE; + } +} + +/*********************************************************************************************************//** + * @brief Configure polarity of the TMx channel N. + * @param TMx: where TMx is the selected TM from the TM peripherals. + * @param Channel: Specify the TM channel. + * This parameter can be one of the following values: + * @arg TM_CH_0 : TM channel 0 + * @arg TM_CH_1 : TM channel 1 + * @arg TM_CH_2 : TM channel 2 + * @arg TM_CH_3 : TM channel 3 + * @param Pol: Specify the polarity of channel N. + * This parameter can be one of the following values: + * @arg TM_CHP_NONINVERTED : active high + * @arg TM_CHP_INVERTED : active low + * @retval None + ************************************************************************************************************/ +void TM_ChPolarityConfig(HT_TM_TypeDef* TMx, TM_CH_Enum Channel, TM_CHP_Enum Pol) +{ + u32 wChpolr; + + /* Check the parameters */ + Assert_Param(IS_TM(TMx)); + Assert_Param(IS_TM_CH(Channel)); + Assert_Param(IS_TM_CHP(Pol)); + + /* Set or reset the CHx polarity */ + wChpolr = TMx->CHPOLR & (~(u32)(0x1 << (Channel << 1))); + TMx->CHPOLR = wChpolr | (Pol << (Channel << 1)); +} + +/*********************************************************************************************************//** + * @brief Enable or Disable the single pulse immediate active function. + * @param TMx: where TMx is the selected TM from the TM peripherals. + * @param Channel: Specify the TM channel. + * This parameter can be one of the following values: + * @arg TM_CH_0 : TM channel 0 + * @arg TM_CH_1 : TM channel 1 + * @arg TM_CH_2 : TM channel 2 + * @arg TM_CH_3 : TM channel 3 + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + * @note Must configure output mode to PWM1 or PWM2 before invoke this function. + ************************************************************************************************************/ +void TM_ImmActiveConfig(HT_TM_TypeDef* TMx, TM_CH_Enum Channel, ControlStatus NewState) +{ + vu32 *pOcfr = (vu32*)&TMx->CH0OCFR + Channel; + + /* Check the parameters */ + Assert_Param(IS_TM(TMx)); + Assert_Param(IS_TM_CH(Channel)); + Assert_Param(IS_CONTROL_STATUS(NewState)); + + /* Enable or disable the channel N clear CHxOREF at ETI active function */ + if (NewState != DISABLE) + { + *pOcfr |= CHOCFR_IMAE; + } + else + { + *pOcfr &= ~CHOCFR_IMAE; + } +} + +/*********************************************************************************************************//** + * @brief Enable or Disable the TMx channel N. + * @param TMx: where TMx is the selected TM from the TM peripherals. + * @param Channel: Specify the TM channel. + * This parameter can be one of the following values: + * @arg TM_CH_0 : TM channel 0 + * @arg TM_CH_1 : TM channel 1 + * @arg TM_CH_2 : TM channel 2 + * @arg TM_CH_3 : TM channel 3 + * @param Control: This parameter can be TM_CHCTL_ENABLE or TM_CHCTL_DISABLE. + * @retval None + ************************************************************************************************************/ +void TM_ChannelConfig(HT_TM_TypeDef* TMx, TM_CH_Enum Channel, TM_CHCTL_Enum Control) +{ + /* Check the parameters */ + Assert_Param(IS_TM(TMx)); + Assert_Param(IS_TM_CH(Channel)); + Assert_Param(IS_TM_CHCTL(Control)); + + /* Reset the CHxE Bit */ + TMx->CHCTR &= ~(u32)(0x1 << (Channel << 1)); + + /* Set or reset the CHxE Bit */ + TMx->CHCTR |= (u32)Control << (Channel << 1); +} + +/*********************************************************************************************************//** + * @brief Configure output mode of the TMx. + * @param TMx: where TMx is the selected TM from the TM peripherals. + * @param Channel: Specify the TM channel. + * This parameter can be one of the following values: + * @arg TM_CH_0 : TM channel 0 + * @arg TM_CH_1 : TM channel 1 + * @arg TM_CH_2 : TM channel 2 + * @arg TM_CH_3 : TM channel 3 + * @param Mod: Specify the TM output mode. + * This parameter can be one of the following values: + * @arg TM_OM_MATCH_NOCHANGE : Output dont change on match + * @arg TM_OM_MATCH_INACTIVE : Output inactive on compare match + * @arg TM_OM_MATCH_ACTIVE : Output active on compare match + * @arg TM_OM_MATCH_TOGGLE : Output toggle on compare match + * @arg TM_OM_FORCED_INACTIVE : Output forced inactive + * @arg TM_OM_FORCED_ACTIVE : Output forced active + * @arg TM_OM_PWM1 : PWM1 mode + * @arg TM_OM_PWM2 : PWM2 mode + * @arg TM_OM_ASYMMETRIC_PWM1 : Asymmetric PWM1 mode + * @arg TM_OM_ASYMMETRIC_PWM2 : Asymmetric PWM2 mode + * @retval None + * @note This function disables the selected channel before changing the output mode. + ************************************************************************************************************/ +void TM_OutputModeConfig(HT_TM_TypeDef* TMx, TM_CH_Enum Channel, TM_OM_Enum Mod) +{ + vu32 *pOcfr = (vu32*)&TMx->CH0OCFR + Channel; + + /* Check the parameters */ + Assert_Param(IS_TM(TMx)); + Assert_Param(IS_TM_CH(Channel)); + Assert_Param(IS_TM_OM(Mod)); + + /* Disable the channel: Reset the CHxE Bit */ + TMx->CHCTR &= ~(u32)(0x1 << (Channel << 1)); + + /* Selects the TM output mode */ + *pOcfr = (*pOcfr & CHOCFR_CHOM_MASK) | Mod; +} + +/*********************************************************************************************************//** + * @brief Enable or Disable update event of the TMx. + * @param TMx: where TMx is the selected TM from the TM peripherals. + * @param NewState: This parameter can be ENABLE (default) or DISABLE. + * @retval None + ************************************************************************************************************/ +void TM_UpdateCmd(HT_TM_TypeDef* TMx, ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_TM(TMx)); + Assert_Param(IS_CONTROL_STATUS(NewState)); + + if (NewState == DISABLE) + { + /* Set the update disable bit */ + TMx->CNTCFR |= CNTCFR_UEVDIS; + } + else + { + /* Reset the update disable bit */ + TMx->CNTCFR &= ~CNTCFR_UEVDIS; + } +} + +/*********************************************************************************************************//** + * @brief Configure UEVG interrupt function of the TMx. + * @param TMx: where TMx is the selected TM from the TM peripherals. + * @param NewState: This parameter can be one of the following value: + * @arg ENABLE : Default value. Any of the following events will generate an update event interrupt: + * - Counter overflow/underflow + * - Setting the UEVG bit + * - Update generation through the slave restart mode + * @arg DISABLE : Only counter overflow/underflow generations an update event interrupt. + * @retval None + ************************************************************************************************************/ +void TM_UEVG_IntConfig(HT_TM_TypeDef* TMx, ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_TM(TMx)); + Assert_Param(IS_CONTROL_STATUS(NewState)); + + if (NewState == DISABLE) + { + /* Set the UEVG interrupt disable bit */ + TMx->CNTCFR |= CNTCFR_UGDIS; + } + else + { + /* Reset the UEVG interrupt disable bit */ + TMx->CNTCFR &= ~CNTCFR_UGDIS; + } +} + +/*********************************************************************************************************//** + * @brief Enable or Disable hall sensor interface of the TMx. + * @param TMx: where TMx is the selected TM from the TM peripherals. + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void TM_HallInterfaceCmd(HT_TM_TypeDef* TMx, ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_TM(TMx)); + Assert_Param(IS_CONTROL_STATUS(NewState)); + + if (NewState != DISABLE) + { + /* Set the CH0SRC Bit */ + TMx->CH0ICFR |= CH0ICFR_CH0SRC; + } + else + { + /* Reset the CH0SRC Bit */ + TMx->CH0ICFR &= ~CH0ICFR_CH0SRC; + } +} + +/*********************************************************************************************************//** + * @brief Select single pulse mode of the TMx. + * @param TMx: where TMx is the selected TM from the TM peripherals. + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void TM_SinglePulseModeCmd(HT_TM_TypeDef* TMx, ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_TM(TMx)); + Assert_Param(IS_CONTROL_STATUS(NewState)); + + if (NewState != DISABLE) + { + TMx->MDCFR |= MDCFR_SPMSET; + } + else + { + TMx->MDCFR &= ~MDCFR_SPMSET; + } +} + +/*********************************************************************************************************//** + * @brief Select master trigger output source of the TMx. + * @param TMx: where TMx is the selected TM from the TM peripherals. + * @param Sel: Specify the master trigger output source. + * This parameter can be as follow: + * @arg TM_MMSEL_RESET : Send trigger signal when S/W setting UEVG or slave restart + * @arg TM_MMSEL_ENABLE : The counter enable signal is used as trigger output. + * @arg TM_MMSEL_UPDATE : The update event is used as trigger output. + * @arg TM_MMSEL_CH0CC : Channel 0 capture or compare match occurred as trigger output. + * @arg TM_MMSEL_CH0OREF : The CH0OREF signal is used as trigger output. + * @arg TM_MMSEL_CH1OREF : The CH1OREF signal is used as trigger output. + * @arg TM_MMSEL_CH2OREF : The CH2OREF signal is used as trigger output. + * @arg TM_MMSEL_CH3OREF : The CH3OREF signal is used as trigger output. + * @retval None + ************************************************************************************************************/ +void TM_MMSELConfig(HT_TM_TypeDef* TMx, TM_MMSEL_Enum Sel) +{ + /* Check the parameters */ + Assert_Param(IS_TM(TMx)); + Assert_Param(IS_TM_MMSEL(Sel)); + + /* Select the MTO source */ + TMx->MDCFR = (TMx->MDCFR & MDCFR_MMSEL_MASK) | Sel; +} + +/*********************************************************************************************************//** + * @brief Select slave mode of the TMx. + * @param TMx: where TMx is the selected TM from the TM peripherals. + * @param Sel: Specify the timer slave mode. + * This parameter can be one of the following values: + * @arg TM_SMSEL_RESTART : Slave restart counter mode. + * @arg TM_SMSEL_PAUSE : Slave pause counter mode. + * @arg TM_SMSEL_TRIGGER : Slave trigger counter start mode. + * @arg TM_SMSEL_STIED : Used rising edge of STI as prescaler clock source. + * @retval None + ************************************************************************************************************/ +void TM_SlaveModeConfig(HT_TM_TypeDef* TMx, TM_SMSEL_Enum Sel) +{ + /* Check the parameters */ + Assert_Param(IS_TM(TMx)); + Assert_Param(IS_TM_SLAVE_MODE(Sel)); + + /* Select the slave mode */ + TMx->MDCFR = (TMx->MDCFR & MDCFR_SMSEL_MASK) | Sel; +} + +/*********************************************************************************************************//** + * @brief Enable or Disable the master & slave TMx synchronous function. + * @param TMx: where TMx is the selected TM from the TM peripherals. + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void TM_TimSyncCmd(HT_TM_TypeDef* TMx, ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_TM(TMx)); + Assert_Param(IS_CONTROL_STATUS(NewState)); + + if (NewState != DISABLE) + { + /* Set the TSE Bit */ + TMx->MDCFR |= MDCFR_TSE; + } + else + { + /* Reset the TSE Bit */ + TMx->MDCFR &= ~MDCFR_TSE; + } +} + +/*********************************************************************************************************//** + * @brief Set counter register value of the TMx. + * @param TMx: where TMx is the selected TM from the TM peripherals. + * @param Counter: Specify the counter register new value. + * @retval None + ************************************************************************************************************/ +void TM_SetCounter(HT_TM_TypeDef* TMx, u16 Counter) +{ + /* Check the parameters */ + Assert_Param(IS_TM(TMx)); + + /* Set the Counter Register value */ + TMx->CNTR = Counter; +} + +/*********************************************************************************************************//** + * @brief Set counter reload register value of the TMx. + * @param TMx: where TMx is the selected TM from the TM peripherals. + * @param Reload: Specify the counter reload register new value. + * @retval None + ************************************************************************************************************/ +void TM_SetCounterReload(HT_TM_TypeDef* TMx, u16 Reload) +{ + /* Check the parameters */ + Assert_Param(IS_TM(TMx)); + + /* Set the counter reload register value */ + TMx->CRR = Reload; +} + +/*********************************************************************************************************//** + * @brief Set channel n capture/compare register value of the TMx. + * @param TMx: where TMx is the selected TM from the TM peripherals. + * @param TM_CH_n: Specify the TM channel. + * This parameter can be one of the following values: + * @arg TM_CH_0 : TM channel 0 + * @arg TM_CH_1 : TM channel 1 + * @arg TM_CH_2 : TM channel 2 + * @arg TM_CH_3 : TM channel 3 + * @param Cmp: Specify the CH0CCR register new value. + * @retval None + ************************************************************************************************************/ +void TM_SetCaptureCompare(HT_TM_TypeDef* TMx, TM_CH_Enum TM_CH_n, u16 Cmp) +{ + vu32* pCHnCCR = ((vu32*)&TMx->CH0CCR) + (TM_CH_n * 1); + /* Check the parameters */ + Assert_Param(IS_TM(TMx)); + Assert_Param(IS_TM_CH(TM_CH_n)); + + /* Set the CHnCCR register new value */ + *pCHnCCR = Cmp; +} + +/*********************************************************************************************************//** + * @brief Set channel n asymmetric compare register value of the TMx. + * @param TMx: where TMx is the selected TM from the TM peripherals. + * @param TM_CH_n: Specify the TM channel. + * This parameter can be one of the following values: + * @arg TM_CH_0 : TM channel 0 + * @arg TM_CH_1 : TM channel 1 + * @arg TM_CH_2 : TM channel 2 + * @arg TM_CH_3 : TM channel 3 + * @param Cmp: Specify the CH0ACR register new value. + * @retval None + ************************************************************************************************************/ +void TM_SetAsymmetricCompare(HT_TM_TypeDef* TMx, TM_CH_Enum TM_CH_n, u16 Cmp) +{ + vu32* pCHnACR = ((vu32*)&TMx->CH0ACR) + (TM_CH_n * 1); + + /* Check the parameters */ + Assert_Param(IS_TM(TMx)); + Assert_Param(IS_TM_CH(TM_CH_n)); + + /* Set the CHnACR register new value */ + *pCHnACR = Cmp; +} + +/*********************************************************************************************************//** + * @brief Configure input capture prescaler. + * @param TMx: where TMx is the selected TM from the TM peripherals. + * @param Channel: Specify the TM channel. + * This parameter can be one of the following values: + * @arg TM_CH_0 : TM channel 0 + * @arg TM_CH_1 : TM channel 1 + * @arg TM_CH_2 : TM channel 2 + * @arg TM_CH_3 : TM channel 3 + * @param Psc: Specify the input capture prescaler new value. + * This parameter can be one of the following values: + * @arg TM_CHPSC_OFF : No prescaler + * @arg TM_CHPSC_2 : Capture is done once every 2 events + * @arg TM_CHPSC_4 : Capture is done once every 4 events + * @arg TM_CHPSC_8 : Capture is done once every 8 events + * @retval None + ************************************************************************************************************/ +void TM_CHPSCConfig(HT_TM_TypeDef* TMx, TM_CH_Enum Channel, TM_CHPSC_Enum Psc) +{ + vu32 *pIcfr = (vu32*)&TMx->CH0ICFR + Channel; + + /* Check the parameters */ + Assert_Param(IS_TM(TMx)); + Assert_Param(IS_TM_CH(Channel)); + Assert_Param(IS_TM_CHPSC(Psc)); + + /* Reset the CHxPSC bits */ + *pIcfr &= CHICFR_CHPSC_MASK; + + /* Set the capture input prescaler value */ + *pIcfr |= Psc; +} + +/*********************************************************************************************************//** + * @brief Set clock division value of the TMx. + * @param TMx: where TMx is the selected TM from the TM peripherals. + * @param Div: Specify the clock division value. + * This parameter can be one of the following value: + * @arg TM_CKDIV_OFF : fDTS = fCLKIN + * @arg TM_CKDIV_2 : fDTS = fCLKIN / 2 + * @arg TM_CKDIV_4 : fDTS = fCLKIN / 4 + * @retval None + ************************************************************************************************************/ +void TM_CKDIVConfig(HT_TM_TypeDef* TMx, TM_CKDIV_Enum Div) +{ + /* Check the parameters */ + Assert_Param(IS_TM(TMx)); + Assert_Param(IS_TM_CKDIV(Div)); + + /* Reset the CKDIV Bits */ + TMx->CNTCFR &= CNTCFR_CKDIV_MASK; + + /* Set the CKDIV value */ + TMx->CNTCFR |= Div; +} + +/*********************************************************************************************************//** + * @brief Get channel n capture/compare register value of the TMx. + * @param TMx: where TMx is the selected TM from the TM peripherals. + * @param TM_CH_n: Specify the TM channel. + * This parameter can be one of the following values: + * @arg TM_CH_0 : TM channel 0 + * @arg TM_CH_1 : TM channel 1 + * @arg TM_CH_2 : TM channel 2 + * @arg TM_CH_3 : TM channel 3 + * @retval Value of CH0CCR register + ************************************************************************************************************/ +u32 TM_GetCaptureCompare(HT_TM_TypeDef* TMx, TM_CH_Enum TM_CH_n) +{ + vu32* pCHnCCR = ((vu32*)&TMx->CH0CCR) + (TM_CH_n * 1); + + /* Check the parameters */ + Assert_Param(IS_TM(TMx)); + Assert_Param(IS_TM_CH(TM_CH_n)); + + /* Get the CHnCCR register value */ + return (*pCHnCCR); +} + +/*********************************************************************************************************//** + * @brief Get counter value of the TMx. + * @param TMx: where TMx is the selected TM from the TM peripherals. + * @retval Value of Counter register + ************************************************************************************************************/ +u32 TM_GetCounter(HT_TM_TypeDef* TMx) +{ + /* Check the parameters */ + Assert_Param(IS_TM(TMx)); + + /* Get the Counter Register value */ + return TMx->CNTR; +} + +/*********************************************************************************************************//** + * @brief Get prescaler value of the TMx. + * @param TMx: where TMx is the selected TM from the TM peripherals. + * @retval Value of Prescaler register + ************************************************************************************************************/ +u32 TM_GetPrescaler(HT_TM_TypeDef* TMx) +{ + /* Check the parameters */ + Assert_Param(IS_TM(TMx)); + + /* Get the Prescaler Register value */ + return TMx->PSCR; +} + +/*********************************************************************************************************//** + * @brief Generate TMx events. + * @param TMx: where TMx is the selected TM from the TM peripherals. + * @param TM_EVENT: Stores the event source. + * This parameter can be any combination of following: + * @arg TM_EVENT_CH0CC : Timer Capture/compare 0 event + * @arg TM_EVENT_CH1CC : Timer Capture/compare 1 event + * @arg TM_EVENT_CH2CC : Timer Capture/compare 2 event + * @arg TM_EVENT_CH3CC : Timer Capture/compare 3 event + * @arg TM_EVENT_UEV : Timer update event + * @arg TM_EVENT_UEV2 : Timer update event 2 + * @arg TM_EVENT_TEV : Timer trigger event + * @arg TM_EVENT_BRKEV : Timer break event + * @retval None + ************************************************************************************************************/ +void TM_GenerateEvent(HT_TM_TypeDef* TMx, u32 TM_EVENT) +{ + /* Check the parameters */ + Assert_Param(IS_TM(TMx)); + Assert_Param(IS_TM_EVENT(TM_EVENT)); + + /* Set the event sources */ + TMx->EVGR = TM_EVENT; +} + +/*********************************************************************************************************//** + * @brief Check whether the specified TMx flag has been set. + * @param TMx: where TMx is the selected TM from the TM peripherals. + * @param TM_FLAG: Specify the flag to be checked. + * This parameter can be one of the following values: + * @arg TM_FLAG_CH0CC : TM Capture/compare 0 flag + * @arg TM_FLAG_CH1CC : TM Capture/compare 1 flag + * @arg TM_FLAG_CH2CC : TM Capture/compare 2 flag + * @arg TM_FLAG_CH3CC : TM Capture/compare 3 flag + * @arg TM_FLAG_CH0OC : TM channel 0 overcapture flag + * @arg TM_FLAG_CH1OC : TM channel 1 overcapture flag + * @arg TM_FLAG_CH2OC : TM channel 2 overcapture flag + * @arg TM_FLAG_CH3OC : TM channel 3 overcapture flag + * @arg TM_FLAG_UEV : TM update flag + * @arg TM_FLAG_UEV2 : TM update 2 flag + * @arg TM_FLAG_TEV : TM trigger flag + * @arg TM_FLAG_BRK0 : TM break 0 flag + * @arg TM_FLAG_BRK1 : TM break 1 flag + * @retval The new state of TM_FLAG (SET or RESET). + ************************************************************************************************************/ +FlagStatus TM_GetFlagStatus(HT_TM_TypeDef* TMx, u32 TM_FLAG) +{ + /* Check the parameters */ + Assert_Param(IS_TM(TMx)); + Assert_Param(IS_TM_FLAG(TM_FLAG)); + + if ((TMx->INTSR & TM_FLAG) != 0) + { + return SET; + } + else + { + return RESET; + } +} + +/*********************************************************************************************************//** + * @brief Clear flags of the TMx. + * @param TMx: where TMx is the selected TM from the TM peripherals. + * @param TM_FLAG: Specify the flag to be cleared. + * This parameter can be any combination of the following values: + * @arg TM_FLAG_CH0CC : TM Capture/compare 0 flag + * @arg TM_FLAG_CH1CC : TM Capture/compare 1 flag + * @arg TM_FLAG_CH2CC : TM Capture/compare 2 flag + * @arg TM_FLAG_CH3CC : TM Capture/compare 3 flag + * @arg TM_FLAG_CH0OC : TM channel 0 overcapture flag + * @arg TM_FLAG_CH1OC : TM channel 1 overcapture flag + * @arg TM_FLAG_CH2OC : TM channel 2 overcapture flag + * @arg TM_FLAG_CH3OC : TM channel 3 overcapture flag + * @arg TM_FLAG_UEV : TM update flag + * @arg TM_FLAG_UEV2 : TM update 2 flag + * @arg TM_FLAG_TEV : TM trigger flag + * @arg TM_FLAG_BRK0 : TM break 0 flag + * @arg TM_FLAG_BRK1 : TM break 1 flag + * @retval None + ************************************************************************************************************/ +void TM_ClearFlag(HT_TM_TypeDef* TMx, u32 TM_FLAG) +{ + /* Check the parameters */ + Assert_Param(IS_TM(TMx)); + Assert_Param(IS_TM_FLAG_CLR(TM_FLAG)); + + /* Clear the flags */ + TMx->INTSR = ~TM_FLAG; + + /*--------------------------------------------------------------------------------------------------------*/ + /* DSB instruction is added in this function to ensure the write operation which is for clearing interrupt*/ + /* flag is actually completed before exiting ISR. It prevents the NVIC from detecting the interrupt again */ + /* since the write register operation may be pended in the internal write buffer of Cortex-Mx when program*/ + /* has exited interrupt routine. This DSB instruction may be masked if this function is called in the */ + /* beginning of ISR and there are still some instructions before exiting ISR. */ + /*--------------------------------------------------------------------------------------------------------*/ + __DSB(); +} + +/*********************************************************************************************************//** + * @brief Enable or Disable the specified interrupts of the TMx. + * @param TMx: where TMx is the selected TM from the TM peripherals. + * @param TM_INT: Specify the TM interrupts sources to be enabled or disabled. + * This parameter can be any combination of the following values: + * @arg TM_INT_CH0CC : TM Capture/compare 0 interrupt + * @arg TM_INT_CH1CC : TM Capture/compare 1 interrupt + * @arg TM_INT_CH2CC : TM Capture/compare 2 interrupt + * @arg TM_INT_CH3CC : TM Capture/compare 3 interrupt + * @arg TM_INT_UEV : TM update interrupt + * @arg TM_INT_UEV2 : TM update 2 interrupt + * @arg TM_INT_TEV : TM trigger interrupt + * @arg TM_INT_BRKEV : TM break interrupt + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void TM_IntConfig(HT_TM_TypeDef* TMx, u32 TM_INT, ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_TM(TMx)); + Assert_Param(IS_TM_INT(TM_INT)); + Assert_Param(IS_CONTROL_STATUS(NewState)); + + if (NewState != DISABLE) + { + /* Enable the interrupt sources */ + TMx->DICTR |= TM_INT; + } + else + { + /* Disable the interrupt sources */ + TMx->DICTR &= ~TM_INT; + } +} + +/*********************************************************************************************************//** + * @brief Check whether the TMx interrupt has occurred. + * @param TMx: where TMx is the selected TM from the TM peripherals. + * @param TM_INT: Specify the TM interrupt source to be checked. + * This parameter can be one of the following values: + * @arg TM_INT_CH0CC : TM Capture/compare 0 interrupt + * @arg TM_INT_CH1CC : TM Capture/compare 1 interrupt + * @arg TM_INT_CH2CC : TM Capture/compare 2 interrupt + * @arg TM_INT_CH3CC : TM Capture/compare 3 interrupt + * @arg TM_INT_UEV : TM update interrupt + * @arg TM_INT_UEV2 : TM update 2 interrupt + * @arg TM_INT_TEV : TM trigger interrupt + * @arg TM_INT_BRKEV : TM break interrupt + * @retval The new state of the TM_INT(SET or RESET) + ************************************************************************************************************/ +FlagStatus TM_GetIntStatus(HT_TM_TypeDef* TMx, u32 TM_INT) +{ + u32 itstatus, itenable; + + /* Check the parameters */ + Assert_Param(IS_TM(TMx)); + Assert_Param(IS_TM_GET_INT(TM_INT)); + + itstatus = TMx->INTSR & TM_INT; + itenable = TMx->DICTR & TM_INT; + + if ((itstatus != 0) && (itenable != 0)) + { + return SET; + } + else + { + return RESET; + } +} + +/*********************************************************************************************************//** + * @brief Clear interrupt pending bits of the TMx. + * @param TMx: where TMx is the selected TM from the TM peripherals. + * @param TM_INT: Specify the TM interrupt to be cleared. + * This parameter can be any combination of the following values: + * @arg TM_INT_CH0CC : TM Capture/compare 0 interrupt + * @arg TM_INT_CH1CC : TM Capture/compare 1 interrupt + * @arg TM_INT_CH2CC : TM Capture/compare 2 interrupt + * @arg TM_INT_CH3CC : TM Capture/compare 3 interrupt + * @arg TM_INT_UEV : TM update interrupt + * @arg TM_INT_UEV2 : TM update 2 interrupt + * @arg TM_INT_TEV : TM trigger interrupt + * @arg TM_INT_BRKEV : TM break interrupt + * @retval None + ************************************************************************************************************/ +void TM_ClearIntPendingBit(HT_TM_TypeDef* TMx, u32 TM_INT) +{ + /* Check the parameters */ + Assert_Param(IS_TM(TMx)); + Assert_Param(IS_TM_INT(TM_INT)); + + /* Clear the interrupt pending Bit */ + TMx->INTSR = ~TM_INT; + + /*--------------------------------------------------------------------------------------------------------*/ + /* DSB instruction is added in this function to ensure the write operation which is for clearing interrupt*/ + /* flag is actually completed before exiting ISR. It prevents the NVIC from detecting the interrupt again */ + /* since the write register operation may be pended in the internal write buffer of Cortex-Mx when program*/ + /* has exited interrupt routine. This DSB instruction may be masked if this function is called in the */ + /* beginning of ISR and there are still some instructions before exiting ISR. */ + /*--------------------------------------------------------------------------------------------------------*/ + __DSB(); +} + +/*********************************************************************************************************//** + * @brief Disable slave mode to clock the prescaler directly with the internal clock. + * @param TMx: where TMx is the selected TM from the TM peripherals. + * @retval None + ************************************************************************************************************/ +void TM_InternalClockConfig(HT_TM_TypeDef* TMx) +{ + /* Check the parameters */ + Assert_Param(IS_TM(TMx)); + + /* Disable slave mode to clock the prescaler directly with the internal clock */ + TMx->MDCFR &= MDCFR_SMSEL_MASK; +} + +/*********************************************************************************************************//** + * @brief Select Channel Capture/Compare PDMA event of the TMx. + * @param TMx: where TMx is the selected TM from the TM peripherals. + * @param Selection: This parameter can be TM_CHCCDS_CHCCEV or TM_CHCCDS_UEV. + * @retval None + ************************************************************************************************************/ +void TM_CHCCDSConfig(HT_TM_TypeDef* TMx, TM_CHCCDS_Enum Selection) +{ + /* Check the parameters */ + Assert_Param(IS_TM(TMx)); + Assert_Param(IS_TM_CHCCDS(Selection)); + + if (Selection != TM_CHCCDS_CHCCEV) + { + TMx->CTR |= CTR_CHCCDS; + } + else + { + TMx->CTR &= ~CTR_CHCCDS; + } +} + +/*********************************************************************************************************//** + * @brief Enable or Disable the specified PDMA requests of the TMx. + * @param TMx: where TMx is the selected TM from the TM peripherals. + * @param TM_PDMA: Specify the TM PDMA requests to be enabled or disabled. + * This parameter can be any combination of the following values: + * @arg TM_PDMA_CH0CC : TM Capture/compare 0 PDMA request + * @arg TM_PDMA_CH1CC : TM Capture/compare 1 PDMA request + * @arg TM_PDMA_CH2CC : TM Capture/compare 2 PDMA request + * @arg TM_PDMA_CH3CC : TM Capture/compare 3 PDMA request + * @arg TM_PDMA_UEV : TM update PDMA request + * @arg TM_PDMA_UEV2 : TM update 2 PDMA request + * @arg TM_PDMA_TEV : TM trigger PDMA request + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void TM_PDMAConfig(HT_TM_TypeDef* TMx, u32 TM_PDMA, ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_TM(TMx)); + Assert_Param(IS_TM_PDMA(TM_PDMA)); + Assert_Param(IS_CONTROL_STATUS(NewState)); + + if (NewState != DISABLE) + { + /* Enable the PDMA request */ + TMx->DICTR |= TM_PDMA; + } + else + { + /* Disable the PDMA request */ + TMx->DICTR &= ~TM_PDMA; + } +} +/** + * @} + */ + +/* Private functions ---------------------------------------------------------------------------------------*/ +/** @defgroup TM_Private_Functions TM private functions + * @{ + */ +/*********************************************************************************************************//** + * @brief Configure the CHx as input. + * @param TMx: where TMx is the selected TM from the TM peripherals. + * @param Ch: Specify the TM Channel. + * This parameter can be one of the following values: + * @arg TM_CH_0 : TM channel 0 + * @arg TM_CH_1 : TM channel 1 + * @arg TM_CH_2 : TM channel 2 + * @arg TM_CH_3 : TM channel 3 + * @param Pol: The input polarity. + * This parameter can be one of the following values: + * @arg TM_CHP_NONINVERTED : Active high level or rising edge + * @arg TM_CHP_INVERTED : Active low level or falling edge + * @param Sel: Specify the input to be used. + * This parameter can be one of the following values: + * @arg TM_CHCCS_DIRECT : TM CHxI is mapped on CHx. + * @arg TM_CHCCS_INDIRECT : TM CH1I is mapped on CH0 (or CH0I->CH1 or CH2I->CH3 or CH3I->CH2). + * @arg TM_CHCCS_TRCED : TM CHx is mapped on TRC. + * @param Filter: Specify the input capture filter. + * This parameter must be a value between 0x00 and 0x0F. + * @retval None + ************************************************************************************************************/ +static void _TM_CHx_Config(HT_TM_TypeDef* TMx, TM_CH_Enum Ch, TM_CHP_Enum Pol, TM_CHCCS_Enum Sel, u8 Filter) +{ + vu32* pIcfr = (vu32*)&TMx->CH0ICFR + Ch; + u32 wIcfr, wChpolr; + + /* Disable the channel N: reset the CHxE bit */ + TMx->CHCTR &= ~((u32)0x1 << (Ch << 1)); + + wIcfr = *pIcfr; + wChpolr = TMx->CHPOLR; + + /* Select the input and set the filter */ + wIcfr &= CHICFR_CHCCS_MASK & CHICFR_CHF_MASK; + wIcfr |= Sel | Filter; + *pIcfr = wIcfr; + + /* Select the polarity bit */ + wChpolr &= ~((u32)0x1 << (Ch << 1)); + wChpolr |= (u32)Pol << (Ch << 1); + TMx->CHPOLR = wChpolr; + + /* Set the CHxE Bit */ + TMx->CHCTR |= (u32)0x1 << (Ch << 1); +} +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ diff --git a/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/src/ht32f1xxxx_usart.c b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/src/ht32f1xxxx_usart.c new file mode 100644 index 0000000000..93ccffa0bf --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/src/ht32f1xxxx_usart.c @@ -0,0 +1,1105 @@ +/*********************************************************************************************************//** + * @file ht32f1xxxx_usart.c + * @version $Rev:: 2972 $ + * @date $Date:: 2023-10-28 #$ + * @brief This file provides all the USART firmware functions. + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ + +/* Includes ------------------------------------------------------------------------------------------------*/ +#include "ht32f1xxxx_usart.h" + +/** @addtogroup HT32F1xxxx_Peripheral_Driver HT32F1xxxx Peripheral Driver + * @{ + */ + +/** @defgroup USART USART + * @brief USART driver modules + * @{ + */ + + +/* Private constants ---------------------------------------------------------------------------------------*/ +/** @defgroup USART_Private_Define USART private definitions + * @{ + */ +#if (LIBCFG_USART_V01) +#define MDR_CLEAR_Mask ((u32)0xFFFFFFFC) +#define LCR_CLEAR_Mask ((u32)0xFFFFFFE0) + +#define USART_TIMEOUT_ON ((u32)0x00000080) +#define USART_TIMEOUT_OFF ((u32)0xFFFFFF7F) + +#define USART_BREAK_ON ((u32)0x00000040) +#define USART_BREAK_OFF ((u32)0xFFFFFFBF) + +#define USART_SPE_ON ((u32)0x00000020) +#define USART_SPE_OFF ((u32)0xFFFFFFDF) + +#define USART_EN_ON ((u32)0x00000100) + +#define USART_HFCEN_ON ((u32)0x00000004) +#define USART_HFCEN_OFF ((u32)0xFFFFFFFB) +#else +#define CR_CLEAR_Mask ((u32)0xFFFFE0FC) + +#define USART_BREAK_ON ((u32)0x00004000) +#define USART_BREAK_OFF ((u32)0xFFFFBFFF) + +#define USART_PBE_ON ((u32)0x00000800) +#define USART_SPE_ON ((u32)0x00002000) +#define USART_SPE_OFF ((u32)0xFFFFDFFF) + +#define USART_EN_ON ((u32)0x00000010) + +#define USART_HFCEN_ON ((u32)0x00000008) +#define USART_HFCEN_OFF ((u32)0xFFFFFFF7) + +#define USART_RXTOEN_ON ((u32)0x00000080) +#endif + +#define FCR_TL_Mask ((u32)0x00000030) + +#define TRSM_CLEAR_Mask ((u32)0xFFFFFFFB) +#define TPR_TG_Mask ((u32)0xFFFF00FF) +#define ICR_IRDAPSC_Mask ((u32)0xFFFF00FF) +#define TPR_RXTOIC_Mask ((u32)0xFFFFFF80) +#define RS485CR_ADDM_Mask ((u32)0xFFFF00FF) + +#define USART_IRDA_ON ((u32)0x00000001) +#define USART_IRDA_OFF ((u32)0xFFFFFFFE) + +#define USART_INV_ON ((u32)0x00000010) + +#define USART_RS485NMM_ON ((u32)0x00000002) +#define USART_RS485NMM_OFF ((u32)0xFFFFFFFD) + +#define USART_RS485AAD_ON ((u32)0x00000004) +#define USART_RS485AAD_OFF ((u32)0xFFFFFFFB) +/** + * @} + */ + +/* Global functions ----------------------------------------------------------------------------------------*/ +/** @defgroup USART_Exported_Functions USART exported functions + * @{ + */ +/*********************************************************************************************************//** + * @brief Deinitialize the USART/UART peripheral registers to their default reset values. + * @param USARTx: Parameter to select the UxART peripheral. + * @retval None + ************************************************************************************************************/ +void USART_DeInit(HT_USART_TypeDef* USARTx) +{ + RSTCU_PeripReset_TypeDef RSTCUReset = {{0}}; + u32 uIPAddr = (u32)USARTx; + + /* Check the parameters */ + Assert_Param(IS_USART(USARTx)); + + switch (uIPAddr) + { + case HT_USART0_BASE: + { + RSTCUReset.Bit.USART0 = 1; + break; + } + #if !(LIBCFG_NO_USART1) + case HT_USART1_BASE: + { + RSTCUReset.Bit.USART1 = 1; + break; + } + #endif + case HT_UART0_BASE: + { + RSTCUReset.Bit.UART0 = 1; + break; + } + case HT_UART1_BASE: + { + RSTCUReset.Bit.UART1 = 1; + break; + } + } + + RSTCU_PeripReset(RSTCUReset, ENABLE); +} + +/*********************************************************************************************************//** + * @brief Initialize the USART/UART peripheral according to the specified parameters in the USART_InitStruct. + * @param USARTx: Parameter to select the UxART peripheral. + * @param USART_InitStruct: pointer to a USART_InitTypeDef structure. + * @retval None + ************************************************************************************************************/ +void USART_Init(HT_USART_TypeDef* USARTx, USART_InitTypeDef* USART_InitStruct) +{ + u32 uIPClock = 0; + u32 uIPAddr = (u32)USARTx; + + /* Check the parameters */ + Assert_Param(IS_USART(USARTx)); + Assert_Param(IS_USART_BAUDRATE(USART_InitStruct->USART_BaudRate)); + Assert_Param(IS_USART_WORD_LENGTH(USART_InitStruct->USART_WordLength)); + Assert_Param(IS_USART_STOPBITS(USART_InitStruct->USART_StopBits)); + Assert_Param(IS_USART_PARITY(USART_InitStruct->USART_Parity)); + Assert_Param(IS_USART_MODE(USART_InitStruct->USART_Mode)); + + #if (LIBCFG_USART_V01) + USARTx->LCR = (USARTx->LCR & LCR_CLEAR_Mask) | USART_InitStruct->USART_StopBits | + USART_InitStruct->USART_WordLength | USART_InitStruct->USART_Parity; + + USARTx->MDR = (USARTx->MDR & MDR_CLEAR_Mask) | USART_InitStruct->USART_Mode; + #else + USARTx->CR = (USARTx->CR & CR_CLEAR_Mask) | USART_InitStruct->USART_StopBits | + USART_InitStruct->USART_WordLength | USART_InitStruct->USART_Parity | + USART_InitStruct->USART_Mode; + #endif + + switch (uIPAddr) + { + case HT_USART0_BASE: + { + uIPClock = CKCU_GetPeripFrequency(CKCU_PCLK_USART0); + break; + } + #if !(LIBCFG_NO_USART1) + case HT_USART1_BASE: + { + uIPClock = CKCU_GetPeripFrequency(CKCU_PCLK_USART1); + break; + } + #endif + case HT_UART0_BASE: + { + uIPClock = CKCU_GetPeripFrequency(CKCU_PCLK_UART0); + break; + } + case HT_UART1_BASE: + { + uIPClock = CKCU_GetPeripFrequency(CKCU_PCLK_UART1); + break; + } + } + + USARTx->DLR = uIPClock / (u32)USART_InitStruct->USART_BaudRate; +} + +/*********************************************************************************************************//** + * @brief Fill each USART_InitStruct member with its default value. + * @param USART_InitStruct: pointer to a USART_InitTypeDef structure. + * @retval None + ************************************************************************************************************/ +void USART_StructInit(USART_InitTypeDef* USART_InitStruct) +{ + /* USART_InitStruct members default value */ + USART_InitStruct->USART_BaudRate = 9600; + USART_InitStruct->USART_WordLength = USART_WORDLENGTH_8B; + USART_InitStruct->USART_StopBits = USART_STOPBITS_1; + USART_InitStruct->USART_Parity = USART_PARITY_NO; + USART_InitStruct->USART_Mode = USART_MODE_NORMAL; +} + +/*********************************************************************************************************//** + * @brief USART/UART send data to Tx. + * @param USARTx: Parameter to select the UxART peripheral. + * @param Data: the data to be transmitted. + * @retval None + ************************************************************************************************************/ +void USART_SendData(HT_USART_TypeDef* USARTx, u16 Data) +{ + /* Check the parameters */ + Assert_Param(IS_USART(USARTx)); + Assert_Param(IS_USART_DATA(Data)); + + USARTx->DR = Data; +} + +/*********************************************************************************************************//** + * @brief USART/UART receive data from Rx. + * @param USARTx: Parameter to select the UxART peripheral. + * @retval The received data. + ************************************************************************************************************/ +u16 USART_ReceiveData(HT_USART_TypeDef* USARTx) +{ + /* Check the parameters */ + Assert_Param(IS_USART(USARTx)); + + return (u16)(USARTx->DR); +} + +/*********************************************************************************************************//** + * @brief Get the specified USART/UART status flags. + * @param USARTx: Parameter to select the UxART peripheral. + * @param USART_FLAG_x: Specify the flag to be check. + * This parameter can be one of the following values: + * LIBCFG_USART_V01 / LIBCFG_USART_V01_LEGACY: + * @arg USART_FLAG_RXDNE / USART_LSR_RFDR + * @arg USART_FLAG_THRE / USART_LSR_THRE + * @arg USART_FLAG_TXC / USART_LSR_TE + * @arg USART_FLAG_ERR / USART_LSR_ERR + * @arg USART_FLAG_MODIS + * @arg USART_FLAG_TXDE + * @arg USART_FLAG_RXDR + * @arg USART_FLAG_RLSI + * @arg USART_FLAG_TOUT + * HT32F1xxxx: + * @arg USART_FLAG_RXDNE : + * @arg USART_FLAG_OE : + * @arg USART_FLAG_PE : + * @arg USART_FLAG_FE : + * @arg USART_FLAG_BI : + * @arg USART_FLAG_RXDR : + * @arg USART_FLAG_TOUT : + * @arg USART_FLAG_TXDE : + * @arg USART_FLAG_TXC : + * @arg USART_FLAG_RSADD : + * @arg USART_FLAG_CTSC : + * @arg USART_FLAG_CTSS : + * @retval SET or RESET + ************************************************************************************************************/ +FlagStatus USART_GetFlagStatus(HT_USART_TypeDef* USARTx, u32 USART_FLAG_x) +{ + /* Check the parameters */ + Assert_Param(IS_USART(USARTx)); + Assert_Param(IS_USART_FLAG(USART_FLAG_x)); + + #if (LIBCFG_USART_V01) + if (USART_FLAG_x & USART_FLAG_FROM_IIR) + { + if (USARTx->IIR == (USART_FLAG_x & (~(USART_FLAG_FROM_IIR)))) + { + return (SET); + } + else + { + return (RESET); + } + } + else + { + #endif + + if ((USARTx->SR & USART_FLAG_x) != (u32)RESET) + { + return (SET); + } + else + { + return (RESET); + } + + #if (LIBCFG_USART_V01) + } + #endif +} + +#if (LIBCFG_USART_V01) +#else +/*********************************************************************************************************//** + * @brief Get the specified USART/UART INT status. + * @param USARTx: Parameter to select the UxART peripheral. + * @param USART_INT_x: Specify if the USART/UART interrupt source. + * This parameter can be one of the following values: + * @arg USART_INT_RXDR : + * @arg USART_INT_TXDE : + * @arg USART_INT_TXC : + * @arg USART_INT_OE : + * @arg USART_INT_PE : + * @arg USART_INT_FE : + * @arg USART_INT_BI : + * @arg USART_INT_RSADD : + * @arg USART_INT_TOUT : + * @arg USART_INT_CTS : + * @retval SET or RESET + ************************************************************************************************************/ +FlagStatus USART_GetIntStatus(HT_USART_TypeDef* USARTx, u32 USART_INT_x) +{ + /* Check the parameters */ + Assert_Param(IS_USART(USARTx)); + Assert_Param(IS_USART_INT(USART_INT_x)); + + if ((USARTx->IER & USART_INT_x) != (u32)RESET) + { + return (SET); + } + else + { + return (RESET); + } +} + +/*********************************************************************************************************//** + * @brief Clear the specified USART/UART flags. + * @param USARTx: where USARTx is the selected USART/UART from the USART/UART peripherals. + * @param USART_Flag: Specify the flag to check. + * This parameter can be any combination of the following values: + * @arg USART_FLAG_OE : + * @arg USART_FLAG_PE : + * @arg USART_FLAG_FE : + * @arg USART_FLAG_BI : + * @arg USART_FLAG_TOUT : + * @arg USART_FLAG_RSADD : + * @arg USART_FLAG_CTSC : + * @retval SET or RESET + ************************************************************************************************************/ +void USART_ClearFlag(HT_USART_TypeDef* USARTx, u32 USART_Flag) +{ + /* Check the parameters */ + Assert_Param(IS_USART(USARTx)); + Assert_Param(IS_USART_CLEAR_FLAG(USART_Flag)); + + USARTx->SR &= USART_Flag; +} +#endif + +/*********************************************************************************************************//** + * @brief Enable or Disable the USART/UART interrupts. + * @param USARTx: Parameter to select the UxART peripheral. + * @param USART_INT_x: Specify if the USART/UART interrupt source to be enabled or disabled. + * This parameter can be one of the following values: + * LIBCFG_USART_V01 / LIBCFG_USART_V01_LEGACY + * @arg USART_INT_RXDR / USART_IER_RDAIE : + * @arg USART_INT_TXDE / USART_IER_THREIE : + * @arg USART_INT_RLSIE / USART_IER_RLSIE : TXC, OE, PE, FE, BI, RSADD + * @arg USART_INT_MSIE / USART_IER_MSIE : + * HT32F1xxxx: + * @arg USART_INT_RXDR : + * @arg USART_INT_TXDE : + * @arg USART_INT_TXC : + * @arg USART_INT_OE : + * @arg USART_INT_PE : + * @arg USART_INT_FE : + * @arg USART_INT_BI : + * @arg USART_INT_RSADD : + * @arg USART_INT_TOUT : + * @arg USART_INT_CTS : + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void USART_IntConfig(HT_USART_TypeDef* USARTx, u32 USART_INT_x, ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_USART(USARTx)); + Assert_Param(IS_USART_INT(USART_INT_x)); + Assert_Param(IS_CONTROL_STATUS(NewState)); + + #if (LIBCFG_USART_V01) + if (USART_INT_x & USART_INT_TOUT) + { + if (NewState != DISABLE) + { + USARTx->TPR |= USART_TIMEOUT_ON; + } + else + { + USARTx->TPR &= USART_TIMEOUT_OFF; + } + } + #endif + + if (NewState != DISABLE) + { + USARTx->IER |= USART_INT_x; + } + else + { + USARTx->IER &= ~USART_INT_x; + } +} + +/*********************************************************************************************************//** + * @brief Enable or Disable the USART Tx/Rx. + * @param USARTx: Parameter to select the USART peripheral. + * @param TxRx: This parameter can be USART_CMD_TX or USART_CMD_RX. + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void USART_TxRxCmd(HT_USART_TypeDef* USARTx, u32 TxRx, ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_USART(USARTx)); + Assert_Param(IS_CONTROL_STATUS(NewState)); + + #if (LIBCFG_USART_V01) + if (NewState != DISABLE) + { + USARTx->FCR |= (USART_EN_ON << TxRx); + } + else + { + USARTx->FCR &= ~(USART_EN_ON << TxRx); + } + #else + if (NewState != DISABLE) + { + USARTx->CR |= (USART_EN_ON << TxRx); + } + else + { + USARTx->CR &= ~(USART_EN_ON << TxRx); + } + #endif +} + +/*********************************************************************************************************//** + * @brief Enable or Disable the USART/UART PDMA interface. + * @param USARTx: Parameter to select the UxART peripheral. + * @param USART_PDMAREQ: specify the USART/UART PDMA transfer request to be enabled or disabled. + * This parameter can be any combination of the following values: + * @arg USART_PDMAREQ_TX + * @arg USART_PDMAREQ_RX + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void USART_PDMACmd(HT_USART_TypeDef* USARTx, u32 USART_PDMAREQ, ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_USART(USARTx)); + Assert_Param(IS_USART_PDMA_REQ(USART_PDMAREQ)); + Assert_Param(IS_CONTROL_STATUS(NewState)); + + #if (LIBCFG_USART_V01) + if (NewState != DISABLE) + { + USARTx->MDR |= USART_PDMAREQ; + } + else + { + USARTx->MDR &= ~USART_PDMAREQ; + } + #else + if (NewState != DISABLE) + { + USARTx->CR |= USART_PDMAREQ; + } + else + { + USARTx->CR &= ~USART_PDMAREQ; + } + #endif +} + +/*********************************************************************************************************//** + * @brief Enable or Disable the USART/UART break control function. + * @param USARTx: Parameter to select the USART peripheral. + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void USART_ForceBreakCmd(HT_USART_TypeDef* USARTx, ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_USART(USARTx)); + Assert_Param(IS_CONTROL_STATUS(NewState)); + + #if (LIBCFG_USART_V01) + if (NewState != DISABLE) + { + USARTx->LCR |= USART_BREAK_ON; + } + else + { + USARTx->LCR &= USART_BREAK_OFF; + } + #else + if (NewState != DISABLE) + { + USARTx->CR |= USART_BREAK_ON; + } + else + { + USARTx->CR &= USART_BREAK_OFF; + } + #endif +} + +/*********************************************************************************************************//** + * @brief Enable or Disable the USART/UART stick parity function. + * @param USARTx: Parameter to select the UxART peripheral. + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void USART_StickParityCmd(HT_USART_TypeDef* USARTx, ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_USART(USARTx)); + Assert_Param(IS_CONTROL_STATUS(NewState)); + + #if (LIBCFG_USART_V01) + if (NewState != DISABLE) + { + USARTx->LCR |= USART_SPE_ON; + } + else + { + USARTx->LCR &= USART_SPE_OFF; + } + #else + if (NewState != DISABLE) + { + USARTx->CR |= USART_SPE_ON | USART_PBE_ON; + } + else + { + USARTx->CR &= USART_SPE_OFF; + } + #endif +} + +/*********************************************************************************************************//** + * @brief Configure the stick parity value of the USART/UART. + * @param USARTx: Parameter to select the UxART peripheral. + * @param USART_StickParity: Specify the stick parity of the USART/UART. + * This parameter can be one of the following values: + * @arg USART_STICK_LOW + * @arg USART_STICK_HIGH + * @retval None + ************************************************************************************************************/ +void USART_StickParityConfig(HT_USART_TypeDef * USARTx, u32 USART_StickParity) +{ + /* Check the parameters */ + Assert_Param(IS_USART(USARTx)); + Assert_Param(IS_USART_STICK_PARITY(USART_StickParity)); + + #if (LIBCFG_USART_V01) + if (USART_StickParity != USART_STICK_HIGH) + { + USARTx->LCR |= USART_STICK_LOW; + } + else + { + USARTx->LCR &= USART_STICK_HIGH; + } + #else + if (USART_StickParity != USART_STICK_HIGH) + { + USARTx->CR |= USART_STICK_LOW; + } + else + { + USARTx->CR &= USART_STICK_HIGH; + } + #endif +} + +/*********************************************************************************************************//** + * @brief Set the specified USART guard time. + * @param USARTx: Parameter to select the USART peripheral. + * @param USART_GuardTime: Specify the guard time. + * @retval None + ************************************************************************************************************/ +void USART_SetGuardTime(HT_USART_TypeDef* USARTx, u32 USART_GuardTime) +{ + /* Check the parameters */ + Assert_Param(IS_USART(USARTx)); + Assert_Param(IS_USART_GUARD_TIME(USART_GuardTime)); + + USARTx->TPR = (USARTx->TPR & TPR_TG_Mask) | (USART_GuardTime << 0x08); +} + +/*********************************************************************************************************//** + * @brief Configure the Tx/Rx FIFO Interrupt Trigger Level. + * @param USARTx: Parameter to select the USART peripheral. + * @param TxRx: This parameter can be USART_CMD_TX or USART_CMD_RX. + * @param USART_tl: Specify the USART Tx/Rx FIFO interrupt trigger level. + * This parameter can be one of the following values: + * For LIBCFG_USART_V01: + * @arg USART_RXTL_01 + * @arg USART_RXTL_04 + * @arg USART_RXTL_08 + * @arg USART_RXTL_14 + * @arg USART_TXTL_00 + * @arg USART_TXTL_02 + * @arg USART_TXTL_04 + * @arg USART_TXTL_08 + * For HT32F1xxxx: + * @arg USART_RXTL_01 + * @arg USART_RXTL_02 + * @arg USART_RXTL_04 + * @arg USART_RXTL_06 + * @arg USART_TXTL_00 + * @arg USART_TXTL_02 + * @arg USART_TXTL_04 + * @arg USART_TXTL_06 + * @retval None + ************************************************************************************************************/ +void USART_TXRXTLConfig(HT_USART_TypeDef* USARTx, u32 TxRx, u32 USART_tl) +{ + /* Check the parameters */ + Assert_Param(IS_USART(USARTx)); + Assert_Param(IS_USART_TL(USART_tl)); + + USARTx->FCR = (USARTx->FCR & ~(FCR_TL_Mask << (TxRx * 2))) | (USART_tl << (TxRx * 2)); +} + +/*********************************************************************************************************//** + * @brief Set the USART FIFO time-out value. + * @param USARTx: Parameter to select the USART peripheral. + * @param USART_TimeOut: Specify the time-out value. + * @retval None + ************************************************************************************************************/ +void USART_SetTimeOutValue(HT_USART_TypeDef* USARTx, u32 USART_TimeOut) +{ + /* Check the parameters */ + Assert_Param(IS_USART(USARTx)); + Assert_Param(IS_USART_TIMEOUT(USART_TimeOut)); + + #if (LIBCFG_USART_V01) + USARTx->TPR = (USARTx->TPR & TPR_RXTOIC_Mask) | USART_TimeOut; + #else + USARTx->TPR = (USARTx->TPR & TPR_RXTOIC_Mask) | USART_TimeOut | USART_RXTOEN_ON; + #endif +} + +/*********************************************************************************************************//** + * @brief Clear both the write and read point in USART Tx FIFO or Rx FIFO. + * @param USARTx: Parameter to select the USART peripheral. + * @param USART_FIFODirection: Determine TX FIFO or Rx FIFO that is to be reset. + * This parameter can be any combination of the following values: + * @arg USART_FIFO_TX + * @arg USART_FIFO_RX + * @retval None + ************************************************************************************************************/ +void USART_FIFOReset(HT_USART_TypeDef* USARTx, u32 USART_FIFODirection) +{ + /* Check the parameters */ + Assert_Param(IS_USART(USARTx)); + Assert_Param(IS_USART_FIFO_DIRECTION(USART_FIFODirection)); + + USARTx->FCR |= USART_FIFODirection; +} + +/*********************************************************************************************************//** + * @brief Return the status of specified USART FIFO. + * @param USARTx: Parameter to select the USART peripheral. + * @param USART_FIFODirection: specify the FIFO that is to be check. + * This parameter can be one of the following values: + * @arg USART_FIFO_TX + * @arg USART_FIFO_RX + * @retval The number of data in Tx FIFO or Rx FIFO. + ************************************************************************************************************/ +u8 USART_GetFIFOStatus(HT_USART_TypeDef* USARTx, u32 USART_FIFODirection) +{ + /* Check the parameters */ + Assert_Param(IS_USART(USARTx)); + Assert_Param(IS_USART_FIFO_DIRECTION(USART_FIFODirection)); + + #if (LIBCFG_USART_V01) + if (USART_FIFODirection == USART_FIFO_TX) + { + return (u8)(USARTx->FSR & 0x1F); + } + else + { + return (u8)((USARTx->FSR & 0x1F00) >> 8); + } + #else + if (USART_FIFODirection == USART_FIFO_TX) + { + return (u8)((USARTx->FCR & 0xF0000) >> 16); + } + else + { + return (u8)((USARTx->FCR & 0xF000000) >> 24); + } + #endif +} + +/*********************************************************************************************************//** + * @brief Enable or Disable the USART hardware flow control. + * @param USARTx: Parameter to select the USART peripheral. + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void USART_HardwareFlowControlCmd(HT_USART_TypeDef* USARTx, ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_USART(USARTx)); + Assert_Param(IS_CONTROL_STATUS(NewState)); + + #if (LIBCFG_USART_V01) + if (NewState != DISABLE) + { + USARTx->MCR |= USART_HFCEN_ON; + } + else + { + USARTx->MCR &= USART_HFCEN_OFF; + } + #else + if (NewState != DISABLE) + { + USARTx->CR |= USART_HFCEN_ON; + } + else + { + USARTx->CR &= USART_HFCEN_OFF; + } + #endif +} + +/*********************************************************************************************************//** + * @brief Enable or Disable the USART IrDA interface. + * @param USARTx: Parameter to select the USART peripheral. + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void USART_IrDACmd(HT_USART_TypeDef* USARTx, ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_USART(USARTx)); + Assert_Param(IS_CONTROL_STATUS(NewState)); + + if (NewState != DISABLE) + { + USARTx->ICR |= USART_IRDA_ON; + } + else + { + USARTx->ICR &= USART_IRDA_OFF; + } +} + +/*********************************************************************************************************//** + * @brief Configure the USART IrDA interface. + * @param USARTx: Parameter to select the USART peripheral. + * @param USART_IrDAMode: Specify the USART IrDA mode. + * This parameter can be one of the following values: + * @arg USART_IRDA_LOWPOWER + * @arg USART_IRDA_NORMAL + * @retval None + ************************************************************************************************************/ +void USART_IrDAConfig(HT_USART_TypeDef* USARTx, u32 USART_IrDAMode) +{ + /* Check the parameters */ + Assert_Param(IS_USART(USARTx)); + Assert_Param(IS_USART_IRDA_MODE(USART_IrDAMode)); + + if (USART_IrDAMode != USART_IRDA_NORMAL) + { + USARTx->ICR |= USART_IRDA_LOWPOWER; + } + else + { + USARTx->ICR &= USART_IRDA_NORMAL; + } +} + +/*********************************************************************************************************//** + * @brief Set the specified USART IrDA prescaler. + * @param USARTx: Parameter to select the USART peripheral. + * @param USART_IrDAPrescaler: Specify the USART IrDA prescaler. + * @retval None + ************************************************************************************************************/ +void USART_SetIrDAPrescaler(HT_USART_TypeDef* USARTx, u32 USART_IrDAPrescaler) +{ + /* Check the parameters */ + Assert_Param(IS_USART(USARTx)); + Assert_Param(IS_USART_IRDA_PRESCALER(USART_IrDAPrescaler)); + + USARTx->ICR = (USARTx->ICR & ICR_IRDAPSC_Mask) | (USART_IrDAPrescaler << 0x08); +} + +/*********************************************************************************************************//** + * @brief Enable the IrDA transmitter or receiver. + * @param USARTx: Parameter to select the USART peripheral, x can be 0 or 1. + * @param USART_IrDADirection: Specify the USART IrDA direction select. + * This parameter can be one of the following values: + * @arg USART_IRDA_TX + * @arg USART_IRDA_RX + * @retval None + ************************************************************************************************************/ +void USART_IrDADirectionConfig(HT_USART_TypeDef* USARTx, u32 USART_IrDADirection) +{ + /* Check the parameters */ + Assert_Param(IS_USART(USARTx)); + Assert_Param(IS_USART_IRDA_DIRECTION(USART_IrDADirection)); + + if (USART_IrDADirection != USART_IRDA_RX) + { + USARTx->ICR |= USART_IRDA_TX; + } + else + { + USARTx->ICR &= USART_IRDA_RX; + } +} + +/*********************************************************************************************************//** + * @brief Enable or Disable inverting serial output/input function of IrDA on the specified USART. + * @param USARTx: Parameter to select the USART peripheral. + * @param inout: This parameter can be USART_CMD_OUT or USART_CMD_IN. + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void USART_IrDAInvtCmd(HT_USART_TypeDef* USARTx, u32 inout, ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_USART(USARTx)); + Assert_Param(IS_CONTROL_STATUS(NewState)); + + if (NewState != DISABLE) + { + USARTx->ICR |= (USART_INV_ON << inout); + } + else + { + USARTx->ICR &= ~(USART_INV_ON << inout); + } +} + +/*********************************************************************************************************//** + * @brief Configure the polarity of USART RS485 transmitter enable signal. + * @param USARTx: Parameter to select the USART peripheral. + * @param USART_RS485Polarity: Specify the polarity of USART RS485 Tx enable signal. + * This parameter can be one of the following values: + * @arg USART_RS485POL_LOW + * @arg USART_RS485POL_HIGH + * @retval None + ************************************************************************************************************/ +void USART_RS485TxEnablePolarityConfig(HT_USART_TypeDef* USARTx, u32 USART_RS485Polarity) +{ + /* Check the parameters */ + Assert_Param(IS_USART(USARTx)); + Assert_Param(IS_USART_RS485_POLARITY(USART_RS485Polarity)); + + if (USART_RS485Polarity != USART_RS485POLARITY_HIGH) + { + USARTx->RCR |= USART_RS485POLARITY_LOW; + } + else + { + USARTx->RCR &= USART_RS485POLARITY_HIGH; + } +} + +/*********************************************************************************************************//** + * @brief Enable or Disable the USART RS485 normal multi-drop operation mode. + * @param USARTx: Parameter to select the USART peripheral. + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void USART_RS485NMMCmd(HT_USART_TypeDef* USARTx, ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_USART(USARTx)); + Assert_Param(IS_CONTROL_STATUS(NewState)); + + if (NewState != DISABLE) + { + USARTx->RCR |= USART_RS485NMM_ON; + } + else + { + USARTx->RCR &= USART_RS485NMM_OFF; + } +} + +/*********************************************************************************************************//** + * @brief Enable or Disable the USART RS485 normal multi-drop operation mode. + * @param USARTx: Parameter to select the USART peripheral. + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void USART_RS485AADCmd(HT_USART_TypeDef* USARTx, ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_USART(USARTx)); + Assert_Param(IS_CONTROL_STATUS(NewState)); + + if (NewState != DISABLE) + { + USARTx->RCR |= USART_RS485AAD_ON; + } + else + { + USARTx->RCR &= USART_RS485AAD_OFF; + } +} + +/*********************************************************************************************************//** + * @brief Set the specified USART RS485 address match value. + * @param USARTx: Parameter to select the USART peripheral. + * @param USART_AddressMatchValue: specify the USART RS485 address match value. + * @retval None + ************************************************************************************************************/ +void USART_SetAddressMatchValue(HT_USART_TypeDef* USARTx, u32 USART_AddressMatchValue) +{ + /* Check the parameters */ + Assert_Param(IS_USART(USARTx)); + Assert_Param(IS_USART_ADDRESS_MATCH_VALUE(USART_AddressMatchValue)); + + USARTx->RCR = (USARTx->RCR & RS485CR_ADDM_Mask) | (u32)(USART_AddressMatchValue << 0x08); +} + +/*********************************************************************************************************//** + * @brief Initialize the clock of the USART peripheral according to the specified parameters + * in the USART_ClockInitStruct. + * @param USARTx: Parameter to select the USART peripheral. + * @param USART_SynClock_InitStruct: pointer to a USART_SynClock_InitTypeDef structure. + * @retval None + ************************************************************************************************************/ +void USART_SynClockInit(HT_USART_TypeDef* USARTx, USART_SynClock_InitTypeDef* USART_SynClock_InitStruct) +{ + /* Check the parameters */ + Assert_Param(IS_USART(USARTx)); + Assert_Param(IS_USART_SYNCHRONOUS_CLOCK(USART_SynClock_InitStruct->USART_ClockEnable)); + Assert_Param(IS_USART_SYNCHRONOUS_PHASE(USART_SynClock_InitStruct->USART_ClockPhase)); + Assert_Param(IS_USART_SYNCHRONOUS_POLARITY(USART_SynClock_InitStruct->USART_ClockPolarity)); + Assert_Param(IS_USART_TRANSFER_MODE(USART_SynClock_InitStruct->USART_TransferSelectMode)); + + USARTx->SCR = USART_SynClock_InitStruct->USART_ClockEnable | USART_SynClock_InitStruct->USART_ClockPhase | + USART_SynClock_InitStruct->USART_ClockPolarity; + + #if (LIBCFG_USART_V01) + USARTx->MDR = (USARTx->MDR & TRSM_CLEAR_Mask) | USART_SynClock_InitStruct->USART_TransferSelectMode; + #else + USARTx->CR = (USARTx->CR & TRSM_CLEAR_Mask) | USART_SynClock_InitStruct->USART_TransferSelectMode; + #endif +} + +/*********************************************************************************************************//** + * @brief Fill each USART_SynClockInitStruct member with its default value. + * @param USART_SynClock_InitStruct: pointer to a USART_SynClock_InitTypeDef structure. + * @retval None + ************************************************************************************************************/ +void USART_SynClockStructInit(USART_SynClock_InitTypeDef* USART_SynClock_InitStruct) +{ + /* USART_ClockInitStruct members default value */ + USART_SynClock_InitStruct->USART_ClockEnable = USART_SYN_CLOCK_DISABLE; + USART_SynClock_InitStruct->USART_ClockPhase = USART_SYN_CLOCK_PHASE_FIRST; + USART_SynClock_InitStruct->USART_ClockPolarity = USART_SYN_CLOCK_POLARITY_LOW; + USART_SynClock_InitStruct->USART_TransferSelectMode = USART_LSB_FIRST; +} + +#if (LIBCFG_USART_V01) +/*********************************************************************************************************//** + * @brief Force pin DTR/RTS to low or high state. + * @param USARTx: Parameter to select the USART peripheral. + * @param USART_ModemPin: Specify the USART modem pin to be forced. + * This parameter can be one of the following values: + * @arg USART_MODEM_DTR + * @arg USART_MODEM_RTS + * @param USART_ModemState: the USART modem pin state. + * This parameter can be one of the following values: + * @arg USART_MODEMSTATE_HIGH + * @arg USART_MODEMSTATE_LOW + * @retval None + ************************************************************************************************************/ +void USART_ForceModemPinState(HT_USART_TypeDef* USARTx, u32 USART_ModemPin, u32 USART_ModemState) +{ + /* Check the parameters */ + Assert_Param(IS_USART(USARTx)); + Assert_Param(IS_USART_MODEM_PIN(USART_ModemPin)); + Assert_Param(IS_USART_MODEM_STATE(USART_ModemState)); + + if (USART_ModemState != USART_MODEMSTATE_HIGH) + { + USARTx->MCR |= USART_MODEMSTATE_LOW << USART_ModemPin; + } + else + { + USARTx->MCR &= ~(USART_MODEMSTATE_HIGH << USART_ModemPin); + } +} + +/*********************************************************************************************************//** + * @brief Get Modem status. + * @param USARTx: Parameter to select the USART peripheral. + * @retval The current status of Modem Status Register. + ************************************************************************************************************/ +u8 USART_GetModemStatus(HT_USART_TypeDef* USARTx) +{ + /* Check the parameters */ + Assert_Param(IS_USART(USARTx)); + + return (u8)(USARTx->MSR); +} + +#if 0 +/*********************************************************************************************************//** + * @brief Enable or Disable time out interrupt of the USART. + * @param USARTx: Parameter to select the USART peripheral. + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void USART_TimeOutIntConfig(HT_USART_TypeDef* USARTx, ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_USART(USARTx)); + Assert_Param(IS_CONTROL_STATUS(NewState)); + + if (NewState != DISABLE) + { + USARTx->TPR |= USART_TIMEOUT_ON; + } + else + { + USARTx->TPR &= USART_TIMEOUT_OFF; + } +} +#endif + +/*********************************************************************************************************//** + * @brief Get Interrupt ID value. + * @param USARTx: Parameter to select the USART peripheral. + * @retval The interrupt ID of USART. + * @arg USART_IID_RLS + * @arg USART_IID_RDA + * @arg USART_IID_CTI + * @arg USART_IID_THRE + * @arg USART_IID_MS + * @arg USART_IID_NON + ************************************************************************************************************/ +u8 USART_GetIntID(HT_USART_TypeDef* USARTx) +{ + /* Check the parameters */ + Assert_Param(IS_USART(USARTx)); + + return (u8)(USARTx->IIR); +} + +/*********************************************************************************************************//** + * @brief Get Line Status Value. + * @param USARTx: Parameter to select the USART peripheral. + * @retval The vlaue of LSR. + ************************************************************************************************************/ +u32 USART_GetLineStatusValue(HT_USART_TypeDef* USARTx) +{ + /* Check the parameters */ + Assert_Param(IS_USART(USARTx)); + + return (u8)(USARTx->LSR); +} +#endif +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ diff --git a/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/src/ht32f1xxxx_usbd.c b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/src/ht32f1xxxx_usbd.c new file mode 100644 index 0000000000..307c5f3d2c --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/src/ht32f1xxxx_usbd.c @@ -0,0 +1,796 @@ +/*********************************************************************************************************//** + * @file ht32f1xxxx_usbd.c + * @version $Rev:: 1670 $ + * @date $Date:: 2019-04-09 #$ + * @brief The USB Device Peripheral Driver. + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ + +/* Includes ------------------------------------------------------------------------------------------------*/ +#include "ht32.h" +#include "ht32f1xxxx_usbdchk.h" + +/** @addtogroup HT32F1xxxx_Peripheral_Driver HT32F1xxxx Peripheral Driver + * @{ + */ + +/** @defgroup USBDevice USB Device + * @brief USB Device driver modules + * @{ + */ + + +/* Private constants ---------------------------------------------------------------------------------------*/ +/** @defgroup USBDevice_Private_Constant USB Device private constants + * @{ + */ +#define TCR_MASK (0x1FF) +#define EPLEN_MASK ((u32)0x000FFC00) +#define EPBUFA_MASK ((u32)0x000003FF) +#define ISR_EPn_OFFSET (8) + +/* USB Control and Status Register (USBCSR) */ +#define FRES ((u32)0x00000002) /* Force USB Reset */ +#define PDWN ((u32)0x00000004) /* Power Down */ +#define LPMODE ((u32)0x00000008) /* Low-power Mode */ +#define GENRSM ((u32)0x00000020) /* Generate Resume */ +#define ADRSET ((u32)0x00000100) /* Device Address Setting */ +#define SRAMRSTC ((u32)0x00000200) /* USB SRAM reset condition */ +#define DPPUEN ((u32)0x00000400) /* DP Pull Up Enable */ +#define DPWKEN ((u32)0x00000800) /* DP Wake Up Enable */ + +#define EPDIR_IN (1) +#define EPDIR_OUT (0) +/** + * @} + */ + +/* Private variables ---------------------------------------------------------------------------------------*/ +/** @defgroup USBDevice_Private_Variable USB Device private variables + * @{ + */ +static u32 gIsFirstPowered = TRUE; +/** + * @} + */ + +/* Private macro -------------------------------------------------------------------------------------------*/ +/** @defgroup USBDevice_Private_Macro USB Device private macros + * @{ + */ +#ifndef USBDCore_LowPower + #define USBDCore_LowPower() PWRCU_DeepSleep1(PWRCU_SLEEP_ENTRY_WFE) +#endif +/** + * @brief Convert Byte length to Word length + */ +#define ByteLen2WordLen(n) ((n + 3) >> 2) +/** + * @} + */ + +/* Private function prototypes -----------------------------------------------------------------------------*/ +static void _USBD_CopyMemory(u32 *pFrom, u32 *pTo, u32 len); +static HT_USBEP_TypeDef * _USBD_GetEPTnAddr(USBD_EPTn_Enum USBD_EPTn); +static void _delay(u32 nCount); + +/* Global functions ----------------------------------------------------------------------------------------*/ +/** @defgroup USBDevice_Exported_Functions USB Device exported functions + * @{ + */ +/*********************************************************************************************************//** + * @brief Pre initialization for USBD_Init function. + * @param pDriver: USB initialization structure + * @retval None + ***********************************************************************************************************/ +void USBD_PreInit(USBD_Driver_TypeDef *pDriver) +{ + pDriver->uInterruptMask = _UIER_ALL; + + pDriver->ept[USBD_EPT0].CFGR.word = _EP0_CFG; + pDriver->ept[USBD_EPT0].IER = _EP0_IER; + + #if (_EP1_ENABLE == 1) + pDriver->ept[USBD_EPT1].CFGR.word = _EP1_CFG; + pDriver->ept[USBD_EPT1].IER = _EP1_IER; + #endif + + #if (_EP2_ENABLE == 1) + pDriver->ept[USBD_EPT2].CFGR.word = _EP2_CFG; + pDriver->ept[USBD_EPT2].IER = _EP2_IER; + #endif + + #if (_EP3_ENABLE == 1) + pDriver->ept[USBD_EPT3].CFGR.word = _EP3_CFG; + pDriver->ept[USBD_EPT3].IER = _EP3_IER; + #endif + + #if (_EP4_ENABLE == 1) + pDriver->ept[USBD_EPT4].CFGR.word = _EP4_CFG; + pDriver->ept[USBD_EPT4].IER = _EP4_IER; + #endif + + #if (_EP5_ENABLE == 1) + pDriver->ept[USBD_EPT5].CFGR.word = _EP5_CFG; + pDriver->ept[USBD_EPT5].IER = _EP5_IER; + #endif + + #if (_EP6_ENABLE == 1) + pDriver->ept[USBD_EPT6].CFGR.word = _EP6_CFG; + pDriver->ept[USBD_EPT6].IER = _EP6_IER; + #endif + + #if (_EP7_ENABLE == 1) + pDriver->ept[USBD_EPT7].CFGR.word = _EP7_CFG; + pDriver->ept[USBD_EPT7].IER = _EP7_IER; + #endif + + return; +} + +/*********************************************************************************************************//** + * @brief USB Device Peripheral initialization. + * @param pDriver: USB initialization structure + * @retval None + ***********************************************************************************************************/ +void USBD_Init(u32 *pDriver) +{ + USBD_Driver_TypeDef *pDrv = (USBD_Driver_TypeDef *)pDriver; + + /* Init USB Device Driver struct */ + USBD_PreInit(pDrv); + + return; +} + +/*********************************************************************************************************//** + * @brief USB Device Internal DP pull up. + * @param NewState: ENABLE or DISABLE + * @retval None + ***********************************************************************************************************/ +void USBD_DPpullupCmd(ControlStatus NewState) +{ + (NewState == ENABLE)?(HT_USB->CSR |= DPPUEN):(HT_USB->CSR &= ~DPPUEN); +} + +/*********************************************************************************************************//** + * @brief USB Device Wake Up when DP is high level. + * @param NewState: ENABLE or DISABLE + * @retval None + ***********************************************************************************************************/ +void USBD_DPWakeUpCmd(ControlStatus NewState) +{ + (NewState == ENABLE)?(HT_USB->CSR |= DPWKEN):(HT_USB->CSR &= ~DPWKEN); +} + +/*********************************************************************************************************//** + * @brief USB Device Peripheral deinitialization. + * @retval None + ***********************************************************************************************************/ +void USBD_DeInit(void) +{ + RSTCU_PeripReset_TypeDef RSTCUReset = {{0}}; + + RSTCUReset.Bit.USBD = 1; + RSTCU_PeripReset(RSTCUReset, ENABLE); + + return; +} + +/*********************************************************************************************************//** + * @brief USB power up procedure. + * @retval None + ***********************************************************************************************************/ +void USBD_PowerUp(u32 *pDriver, u32 uIsSelfPowered) +{ + USBD_Driver_TypeDef *pDrv = (USBD_Driver_TypeDef *)pDriver; + + if (gIsFirstPowered == TRUE) + { + gIsFirstPowered = FALSE; + + if (HT_USB->CSR & 0x40) + { + HT_USB->CSR = (DPPUEN | LPMODE | PDWN); + while((HT_USB->ISR & URSTIE) == 0); + HT_USB->ISR = 0xFFFFFFFF; + if (uIsSelfPowered == FALSE) + { + USBDCore_LowPower(); + } + USBD_EnableINT(pDrv->uInterruptMask); + } + else + { + HT_USB->CSR = (DPWKEN | DPPUEN | LPMODE | PDWN); + while((HT_USB->ISR & URSTIE) == 0); + HT_USB->ISR = 0xFFFFFFFF; + if (uIsSelfPowered == FALSE) + { + USBDCore_LowPower(); + } + USBD_DPWakeUpCmd(DISABLE); + USBD_EnableINT(pDrv->uInterruptMask); + USBD_DPpullupCmd(DISABLE); + _delay(200); + USBD_DPpullupCmd(ENABLE); + } + } + + return; +} + +/*********************************************************************************************************//** + * @brief Enter USB Device Power Down mode. + * @retval None + ***********************************************************************************************************/ +void USBD_PowerOff(void) +{ + HT_USB->CSR |= (LPMODE | PDWN); + return; +} + +/*********************************************************************************************************//** + * @brief Exit USB Device Power Down mode. + * @retval None + ***********************************************************************************************************/ +void USBD_PowerOn(void) +{ + HT_USB->CSR |= 0x00001000; + HT_USB->CSR &= 0x00001400; + return; +} + +/*********************************************************************************************************//** + * @brief USB SRAM reset condition. + * @param NewState: ENABLE or DISABLE + * @retval None + ***********************************************************************************************************/ +void USBD_SRAMResetConditionCmd(ControlStatus NewState) +{ + (NewState == ENABLE)?(HT_USB->CSR |= SRAMRSTC):(HT_USB->CSR &= ~SRAMRSTC); +} + +/*********************************************************************************************************//** + * @brief Disable Default pull resistance of D+ and D-. + * @retval None + ***********************************************************************************************************/ +void USBD_DisableDefaultPull(void) +{ + HT_USB->CSR = FRES; // Clear PDWN and keep FRES = 1 +} + +/*********************************************************************************************************//** + * @brief Generate a resume request to USB Host for Remote Wakeup function. + * @retval None + ***********************************************************************************************************/ +void USBD_RemoteWakeup(void) +{ + HT_USB->CSR |= GENRSM; + return; +} + +/*********************************************************************************************************//** + * @brief Read Endpoint0 SETUP data from USB Buffer. + * @param pBuffer: Buffer for save SETUP data + * @retval None + ***********************************************************************************************************/ +void USBD_ReadSETUPData(u32 *pBuffer) +{ + u32 *pSrc = (u32 *)HT_USB_SRAM_BASE; + + *pBuffer = *pSrc; + *(pBuffer + 1) = *(pSrc + 1); + return; +} + +/*********************************************************************************************************//** + * @brief Set USB Device address. + * @param address: USB address which specified by Host + * @retval None + ***********************************************************************************************************/ +void USBD_SetAddress(u32 address) +{ + HT_USB->CSR |= ADRSET; + HT_USB->DEVAR = address; + return; +} + +/*********************************************************************************************************//** + * @brief Enable USB Device interrupt. + * @param INTFlag: USB Device global interrupt flag + * @arg UGIE | SOFIE | URSTIE | RSMIE | SUSPIE | ESOFIE + * EP0IE | EP1IE | EP2IE | EP3IE | EP4IE | EP5IE | EP6IE | EP7IE + * @retval None + ***********************************************************************************************************/ +void USBD_EnableINT(u32 INTFlag) +{ + HT_USB->IER |= INTFlag; + return; +} + +/*********************************************************************************************************//** + * @brief Disable USB Device interrupt. + * @param INTFlag: USB Device global interrupt flag + * @arg UGIE | SOFIE | URSTIE | RSMIE | SUSPIE | ESOFIE + * EP0IE | EP1IE | EP2IE | EP3IE | EP4IE | EP5IE | EP6IE | EP7IE + * @retval None + ***********************************************************************************************************/ +void USBD_DisableINT(u32 INTFlag) +{ + HT_USB->IER &= (~INTFlag); + return; +} + +/*********************************************************************************************************//** + * @brief Get active USB Device interrupt flag. + * @retval USB ISR Flag + ***********************************************************************************************************/ +u32 USBD_GetINT(void) +{ + u32 IER = HT_USB->IER | FRESIE; + return (HT_USB->ISR & IER); +} + +/*********************************************************************************************************//** + * @brief Clear USB Device interrupt flag. + * @param INTFlag: USB Device global interrupt flag + * @arg SOFIF | URSTIF | RSMIF | SUSPIF | ESOFIF + * EP0IF | EP1IF | EP2IF | EP3IF | EP4IF | EP5IF | EP6IF | EP7IF + * @retval None + ***********************************************************************************************************/ +void USBD_ClearINT(u32 INTFlag) +{ + HT_USB->ISR = INTFlag; + return; +} + +/*********************************************************************************************************//** + * @brief Get USB Endpoint number by interrupt flag. + * @param INTFlag: USB Device global interrupt flag + * @arg SOFIF | URSTIF | RSMIF | SUSPIF | ESOFIF + * EP0IF | EP1IF | EP2IF | EP3IF | EP4IF | EP5IF | EP6IF | EP7IF + * @retval USB Endpoint number from USBD_EPT1 ~ USBD_EPT7 + ***********************************************************************************************************/ +USBD_EPTn_Enum USBD_GetEPTnINTNumber(u32 INTFlag) +{ + s32 i; + for (i = MAX_EP_NUM - 1; i > 0; i--) + { + if ((INTFlag >> (i + ISR_EPn_OFFSET)) & SET) + { + return (USBD_EPTn_Enum)i; + } + } + + return USBD_NOEPT; +} + +/*********************************************************************************************************//** + * @brief USB Device Peripheral initialization for Endpoint. + * @param USBD_EPTn: USB Endpoint number + * @arg USBD_EPT0 ~ USBD_EPT7 + * @param pDriver: USB initialization structure + * @retval None + ***********************************************************************************************************/ +void USBD_EPTInit(USBD_EPTn_Enum USBD_EPTn, u32 *pDriver) +{ + USBD_Driver_TypeDef *pDrv = (USBD_Driver_TypeDef *)pDriver; + HT_USBEP_TypeDef *USBEPn = _USBD_GetEPTnAddr(USBD_EPTn); + + USBEPn->CFGR = pDrv->ept[USBD_EPTn].CFGR.word; + USBEPn->IER = pDrv->ept[USBD_EPTn].IER; + + USBEPn->ISR = 0xFFFFFFFF; + + USBD_EPTReset(USBD_EPTn); + + return; +} + +/*********************************************************************************************************//** + * @brief Reset Endpoint Status. + * @param USBD_EPTn: USB Endpoint number + * @arg USBD_EPT0 ~ USBD_EPT7 + * @retval None + ***********************************************************************************************************/ +void USBD_EPTReset(USBD_EPTn_Enum USBD_EPTn) +{ + HT_USBEP_TypeDef *USBEPn = _USBD_GetEPTnAddr(USBD_EPTn); + USBEPn->CSR = (USBEPn->CSR) & (DTGTX | DTGRX | NAKRX); + return; +} + +/*********************************************************************************************************//** + * @brief Enable Interrupt for Endpoint. + * @param USBD_EPTn: USB Endpoint number + * @arg USBD_EPT0 ~ USBD_EPT7 + * @param INTFlag: Interrupt flag + * @arg OTRXIE | ODRXIE | ODOVIE | ITRXIE | IDTXIE | NAKIE | STLIE | UERIE | + * STRXIE | SDRXIE | SDERIE | ZLRXIE + * @retval None + ***********************************************************************************************************/ +void USBD_EPTEnableINT(USBD_EPTn_Enum USBD_EPTn, u32 INTFlag) +{ + _USBD_GetEPTnAddr(USBD_EPTn)->IER = INTFlag; + return; +} + +/*********************************************************************************************************//** + * @brief Get active USB Device Endpoint interrupt. + * @param USBD_EPTn: USB Endpoint number + * @arg USBD_EPT0 ~ USBD_EPT7 + * @retval USB Endpoint ISR Flag + ***********************************************************************************************************/ +u32 USBD_EPTGetINT(USBD_EPTn_Enum USBD_EPTn) +{ + HT_USBEP_TypeDef *USBEPn = _USBD_GetEPTnAddr(USBD_EPTn); + u32 IER = USBEPn->IER; + return (USBEPn->ISR & IER); +} + +/*********************************************************************************************************//** + * @brief Clear Interrupt for Endpoint. + * @param USBD_EPTn: USB Endpoint number + * @arg USBD_EPT0 ~ USBD_EPT7 + * @param INTFlag: Interrupt flag + * @arg OTRXIF | ODRXIF | ODOVIF | ITRXIF | IDTXIF | NAKIF | STLIF | UERIF | + * STRXIF | SDRXIF | SDERIF | ZLRXIF + * @retval None + ***********************************************************************************************************/ +void USBD_EPTClearINT(USBD_EPTn_Enum USBD_EPTn, u32 INTFlag) +{ + _USBD_GetEPTnAddr(USBD_EPTn)->ISR = INTFlag; + return; +} + +/*********************************************************************************************************//** + * @brief Get Endpoint n Halt status (STLTX or STLRX). + * @param USBD_EPTn: USB Endpoint number + * @arg USBD_EPT0 ~ USBD_EPT7 + * @retval Endpoint Halt Status (1: Endpoint is Halt, 0: Endpoint is not Halt) + ***********************************************************************************************************/ +u32 USBD_EPTGetHalt(USBD_EPTn_Enum USBD_EPTn) +{ + HT_USBEP_TypeDef *USBEPn = _USBD_GetEPTnAddr(USBD_EPTn); + USBD_EPTCFGR_Bit *CFGR = (USBD_EPTCFGR_Bit *)(&(USBEPn->CFGR)); + if (CFGR->EPDIR == EPDIR_IN) + { + return (((USBEPn->CSR) & STLTX) ? 1 : 0); + } + else + { + return (((USBEPn->CSR) & STLRX) ? 1 : 0); + } +} + +/*********************************************************************************************************//** + * @brief Send STALL on Endpoint n. + * @param USBD_EPTn: USB Endpoint number + * @arg USBD_EPT0 ~ USBD_EPT7 + * @retval None + ***********************************************************************************************************/ +void USBD_EPTSendSTALL(USBD_EPTn_Enum USBD_EPTn) +{ + _USBD_GetEPTnAddr(USBD_EPTn)->CSR = STLTX; + return; +} + +/*********************************************************************************************************//** + * @brief Set Endpoint n Halt status (STLTX or STLRX). + * @param USBD_EPTn: USB Endpoint number + * @arg USBD_EPT0 ~ USBD_EPT7 + * @retval None + ***********************************************************************************************************/ +void USBD_EPTSetHalt(USBD_EPTn_Enum USBD_EPTn) +{ + HT_USBEP_TypeDef *USBEPn = _USBD_GetEPTnAddr(USBD_EPTn); + +#if 1 + /* Clean STLIF flag, for USBD_EPTWaitSTALLSent function */ + USBEPn->ISR = STLIF; + USBEPn->CSR = (~(USBEPn->CSR)) & (STLTX | STLRX); +#else + USBD_EPTCFGR_Bit *CFGR = (USBD_EPTCFGR_Bit *)(&(USBEPn->CFGR)); + if (CFGR->EPDIR == EPDIR_IN) + { + /* Clean STLIF flag, for USBD_EPTWaitSTALLSent function */ + USBEPn->ISR = STLIF; + /* Set only when STLTX = 0 */ + USBEPn->CSR = (~(USBEPn->CSR)) & STLTX; + } + else + { + /* Set only when STLRX = 0 */ + USBEPn->CSR = (~(USBEPn->CSR)) & STLRX; + } +#endif + + return; +} + +/*********************************************************************************************************//** + * @brief Clear Endpoint n Halt status (STLTX or STLRX). + * @param USBD_EPTn: USB Endpoint number + * @arg USBD_EPT0 ~ USBD_EPT7 + * @retval None + ***********************************************************************************************************/ +void USBD_EPTClearHalt(USBD_EPTn_Enum USBD_EPTn) +{ + HT_USBEP_TypeDef *USBEPn = _USBD_GetEPTnAddr(USBD_EPTn); + +#if 1 + USBEPn->CSR = (USBEPn->CSR) & (STLTX | STLRX); +#else + USBD_EPTCFGR_Bit *CFGR = (USBD_EPTCFGR_Bit *)(&(USBEPn->CFGR)); + if (CFGR->EPDIR == EPDIR_IN) + { + /* Clear only when STLTX = 1 */ + USBEPn->CSR = (USBEPn->CSR) & STLTX; + } + else + { + /* Clear only when STLRX = 1 */ + USBEPn->CSR = (USBEPn->CSR) & STLRX; + } +#endif + + return; +} + +/*********************************************************************************************************//** + * @brief Wait until STALL transmission is finished + * @param USBD_EPTn: USB Endpoint number + * @arg USBD_EPT0 ~ USBD_EPT7 + * @retval None + ***********************************************************************************************************/ +void USBD_EPTWaitSTALLSent(USBD_EPTn_Enum USBD_EPTn) +{ + HT_USBEP_TypeDef *USBEPn = _USBD_GetEPTnAddr(USBD_EPTn); + USBD_EPTCFGR_Bit *CFGR = (USBD_EPTCFGR_Bit *)(&(USBEPn->CFGR)); + u32 uSTALLState = (CFGR->EPDIR == EPDIR_IN) ? ((USBEPn->CSR) & STLTX) : ((USBEPn->CSR) & STLRX); + + if (uSTALLState) + { + while ((USBEPn->ISR & STLIF) == 0); + } + + return; +} + +/*********************************************************************************************************//** + * @brief Clear Endpoint n Data toggle bit (DTGTX or DTGRX). + * @param USBD_EPTn: USB Endpoint number + * @arg USBD_EPT0 ~ USBD_EPT7 + * @retval None + ***********************************************************************************************************/ +void USBD_EPTClearDTG(USBD_EPTn_Enum USBD_EPTn) +{ + HT_USBEP_TypeDef *USBEPn = _USBD_GetEPTnAddr(USBD_EPTn); + +#if 1 + USBEPn->CSR = (USBEPn->CSR) & (DTGTX | DTGRX); +#else + USBD_EPTCFGR_Bit *CFGR = (USBD_EPTCFGR_Bit *)(&(USBEPn->CFGR)); + if (CFGR->EPDIR == EPDIR_IN) + { + /* Clear only when DTGTX = 1 */ + USBEPn->CSR = (USBEPn->CSR) & DTGTX; + } + else + { + /* Clear only when DTGRX = 1 */ + USBEPn->CSR = (USBEPn->CSR) & DTGRX; + } +#endif + return; +} + +/*********************************************************************************************************//** + * @brief Get Endpoint n buffer 0 address. + * @param USBD_EPTn: USB Endpoint number + * @arg USBD_EPT0 ~ USBD_EPT7 + * @retval USB Endpoint buffer 0 address + ***********************************************************************************************************/ +u32 USBD_EPTGetBuffer0Addr(USBD_EPTn_Enum USBD_EPTn) +{ + HT_USBEP_TypeDef *USBEPn = _USBD_GetEPTnAddr(USBD_EPTn); + return (HT_USB_SRAM_BASE + (USBEPn->CFGR & EPBUFA_MASK)); +} + +/*********************************************************************************************************//** + * @brief Get Endpoint n buffer 1 address. + * @param USBD_EPTn: USB Endpoint number + * @arg USBD_EPT0 ~ USBD_EPT7 + * @retval USB Endpoint buffer 1 address + ***********************************************************************************************************/ +u32 USBD_EPTGetBuffer1Addr(USBD_EPTn_Enum USBD_EPTn) +{ + HT_USBEP_TypeDef *USBEPn = _USBD_GetEPTnAddr(USBD_EPTn); + return (HT_USB_SRAM_BASE + (USBEPn->CFGR & EPBUFA_MASK) + USBD_EPTGetBufferLen(USBD_EPTn)); +} + +/*********************************************************************************************************//** + * @brief Get Endpoint n buffer length. + * @param USBD_EPTn: USB Endpoint number + * @arg USBD_EPT0 ~ USBD_EPT7 + * @retval USB Endpoint buffer length + ***********************************************************************************************************/ +u32 USBD_EPTGetBufferLen(USBD_EPTn_Enum USBD_EPTn) +{ + return ((_USBD_GetEPTnAddr(USBD_EPTn)->CFGR & EPLEN_MASK) >> 10); +} + +/*********************************************************************************************************//** + * @brief Get Endpoint n Transfer Count. + * @param USBD_EPTn: USB Endpoint number + * @arg USBD_EPT0 ~ USBD_EPT7 + * @param USBD_TCR_n: USBD_TCR_0 or USBD_TCR_1 + * @retval Endpoint Transfer Count + ***********************************************************************************************************/ +u32 USBD_EPTGetTransferCount(USBD_EPTn_Enum USBD_EPTn, USBD_TCR_Enum USBD_TCR_n) +{ + return (((_USBD_GetEPTnAddr(USBD_EPTn)->TCR) >> USBD_TCR_n) & TCR_MASK); +} + +/*********************************************************************************************************//** + * @brief Write IN Data from User buffer to USB buffer. + * @param USBD_EPTn: USB Endpoint number + * @arg USBD_EPT0 ~ USBD_EPT7 + * @param pFrom: Source buffer + * @param len: Length for write IN data + * @retval Total length written by this function + ***********************************************************************************************************/ +u32 USBD_EPTWriteINData(USBD_EPTn_Enum USBD_EPTn, u32 *pFrom, u32 len) +{ + u32 bufferlen = USBD_EPTGetBufferLen(USBD_EPTn); + HT_USBEP_TypeDef *USBEPn = _USBD_GetEPTnAddr(USBD_EPTn); + u32 EPTnLen; + u32 *pTo; + + EPTnLen = (USBD_EPTn == USBD_EPT0) ? USBD_EPTGetTransferCount(USBD_EPTn, USBD_CNTIN):USBD_EPTGetTransferCount(USBD_EPTn, USBD_CNTB0); + + if (len <= bufferlen && EPTnLen == 0) + { + pTo = (u32 *)USBD_EPTGetBuffer0Addr(USBD_EPTn); + _USBD_CopyMemory(pFrom, pTo, ByteLen2WordLen(len)); + USBEPn->TCR = len; + USBEPn->CSR = NAKTX; + return len; + } + else + { + return 0; + } +} + +/*********************************************************************************************************//** + * @brief Read OUT Data from USB buffer to User buffer. + * @param USBD_EPTn: USB Endpoint number + * @arg USBD_EPT0 ~ USBD_EPT7 + * @param pTo: Destination memory + * @param len: Length for read OUT data, set as 0 for discard current OUT data in the USB buffer + * @retval Total length read by this function + ***********************************************************************************************************/ +u32 USBD_EPTReadOUTData(USBD_EPTn_Enum USBD_EPTn, u32 *pTo, u32 len) +{ + HT_USBEP_TypeDef *USBEPn = _USBD_GetEPTnAddr(USBD_EPTn); + u32 EPTnLen = 0; + + if (len != 0) + { + EPTnLen = USBD_EPTReadMemory(USBD_EPTn, pTo, len); + } + + if (EPTnLen != 0 || len == 0) + { + USBEPn->CSR = (USBEPn->CSR & NAKRX); + } + + return EPTnLen; +} + +/*********************************************************************************************************//** + * @brief Read memory from endpoint buffer. + * @param USBD_EPTn: USB Endpoint number + * @arg USBD_EPT0 ~ USBD_EPT7 + * @param pTo: Destination buffer + * @param len: Length for read OUT data + * @retval Total length read by this function + ***********************************************************************************************************/ +u32 USBD_EPTReadMemory(USBD_EPTn_Enum USBD_EPTn, u32 *pTo, u32 len) +{ + u32 EPTnLen = 0; + u32 *pFrom; + + EPTnLen = (USBD_EPTn == USBD_EPT0) ? USBD_EPTGetTransferCount(USBD_EPTn, USBD_CNTOUT):USBD_EPTGetTransferCount(USBD_EPTn, USBD_CNTB0); + + if (EPTnLen <= len) + { + pFrom = (USBD_EPTn == USBD_EPT0) ? (u32 *)USBD_EPTGetBuffer1Addr(USBD_EPTn):(u32 *)USBD_EPTGetBuffer0Addr(USBD_EPTn); + _USBD_CopyMemory(pFrom, pTo, ByteLen2WordLen(EPTnLen)); + } + + return EPTnLen; +} +/** + * @} + */ + +/* Private functions ---------------------------------------------------------------------------------------*/ +/** @defgroup USBDevice_Private_Function USB Device private functions + * @{ + */ +/*********************************************************************************************************//** + * @brief Copy 32 bits memory from pFrom to pTo. + * @param pFrom: Source buffer + * @param pTo: Destination buffer + * @param len: Copy length + * @retval None + ***********************************************************************************************************/ +static void _USBD_CopyMemory(u32 *pFrom, u32 *pTo, u32 len) +{ + s32 i; + for (i = len - 1; i >= 0; i--) + { + pTo[i] = pFrom[i]; + } + + return; +} + +/*********************************************************************************************************//** + * @brief Convent USBD_EPTn_Enum to USBEP_TypeDef. + * @param USBD_EPTn: USB Endpoint number + * @arg USBD_EPT0 ~ USBD_EPT7 + * @retval USBEP0 ~ USBEP7 + ***********************************************************************************************************/ +static HT_USBEP_TypeDef * _USBD_GetEPTnAddr(USBD_EPTn_Enum USBD_EPTn) +{ + return ((HT_USBEP_TypeDef *)(HT_USBEP0 + USBD_EPTn)); +} + +/*********************************************************************************************************//** + * @brief Inserts a delay time. + * @param nCount: specifies the delay time length. + * @retval None + ***********************************************************************************************************/ +static void _delay(u32 nCount) +{ + u32 i; + + for (i = 0; i < nCount; i++) + { + } +} +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ diff --git a/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/src/ht32f1xxxx_wdt.c b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/src/ht32f1xxxx_wdt.c new file mode 100644 index 0000000000..5bd9a98e77 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/src/ht32f1xxxx_wdt.c @@ -0,0 +1,363 @@ +/*********************************************************************************************************//** + * @file ht32f1xxxx_wdt.c + * @version $Rev:: 2797 $ + * @date $Date:: 2022-11-28 #$ + * @brief This file provides all the WDT firmware functions. + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ + +/* Includes ------------------------------------------------------------------------------------------------*/ +#include "ht32f1xxxx_wdt.h" + +/** @addtogroup HT32F1xxxx_Peripheral_Driver HT32F1xxxx Peripheral Driver + * @{ + */ + +/** @defgroup WDT WDT + * @brief WDT driver modules + * @{ + */ + + +/* Private constants ---------------------------------------------------------------------------------------*/ +/** @defgroup WDT_Private_Define WDT private definitions + * @{ + */ + +/* WDT Restart Key */ +#define RESTART_KEY ((u32)0x5FA00000) + +/* WDT Protect mask */ +#define PRCT_SET ((u32)0x0000CA35) +#define PRCT_RESET ((u32)0x000035CA) + +/* WDT WDTFIEN mask */ +#define MODE0_WDTFIEN_SET ((u32)0x00001000) +#define MODE0_WDTFIEN_RESET ((u32)0xFFFFEFFF) + +/* WDT WDTRSTEN mask */ +#define MODE0_WDTRETEN_SET ((u32)0x00002000) +#define MODE0_WDTRETEN_RESET ((u32)0xFFFFDFFF) + +/* WDT WDTEN mask */ +#define MODE0_WDTEN_SET ((u32)0x00010000) +#define MODE0_WDTEN_RESET ((u32)0xFFFEFFFF) + +/* WDT WDTLOCK mask */ +#define MODE0_WDTLOCK_SET ((u32)0x00000010) +#define MODE0_WDTLOCK_RESET ((u32)0x00000000) +/** + * @} + */ + +/* Global functions ----------------------------------------------------------------------------------------*/ +/** @defgroup WDT_Exported_Functions WDT exported functions + * @{ + */ +/*********************************************************************************************************//** + * @brief Deinitialize the WDT peripheral registers to their default reset values. + * @retval None + ************************************************************************************************************/ +void WDT_DeInit(void) +{ + RSTCU_PeripReset_TypeDef RSTCUReset = {{0}}; + + RSTCUReset.Bit.WDT = 1; + RSTCU_PeripReset(RSTCUReset, ENABLE); +} + +/*********************************************************************************************************//** + * @brief Enable or Disable the WDT. + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void WDT_Cmd(ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_CONTROL_STATUS(NewState)); + + if (NewState != DISABLE) + { + HT_WDT->MR0 |= MODE0_WDTEN_SET; + } + else + { + HT_WDT->MR0 &= MODE0_WDTEN_RESET; + } +} + +/*********************************************************************************************************//** + * @brief Configure the WDT to run or halt in sleep and deep sleep1 mode. + * @param WDT_Mode: + * This parameter can be one of the following values: + * @arg MODE0_WDTSHLT_BOTH : WDT runs in sleep and deep sleep1 mode + * @arg MODE0_WDTSHLT_SLEEP : WDT runs in sleep mode + * @arg MODE0_WDTSHLT_HALT : WDT halts in sleep and deep sleep1 mode + * @retval None + ************************************************************************************************************/ +void WDT_HaltConfig(u32 WDT_Mode) +{ + /* Check the parameters */ + Assert_Param(IS_WDT_WDTSHLT_MODE(WDT_Mode)); + + HT_WDT->MR0 = ((WDT_Mode) | (HT_WDT->MR0 & 0x00013FFF)); +} + +#if (LIBCFG_WDT_INT) +/*********************************************************************************************************//** + * @brief Enable or Disable the WDT interrupt when WDT meets underflow or error. + * @param NewState: This parameter can be: ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void WDT_IntConfig(ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_CONTROL_STATUS(NewState)); + + if (NewState != DISABLE) + { + HT_WDT->MR0 |= MODE0_WDTFIEN_SET; + } + else + { + HT_WDT->MR0 &= MODE0_WDTFIEN_RESET; + } +} +#endif + +/*********************************************************************************************************//** + * @brief Enable or Disable the WDT Reset when WDT meets underflow or error. + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void WDT_ResetCmd(ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_CONTROL_STATUS(NewState)); + + if (NewState != DISABLE) + { + HT_WDT->MR0 |= MODE0_WDTRETEN_SET; + } + else + { + HT_WDT->MR0 &= MODE0_WDTRETEN_RESET; + } +} + +/*********************************************************************************************************//** + * @brief Enable or Disable protection mechanism of the WDT. + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void WDT_ProtectCmd(ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_CONTROL_STATUS(NewState)); + + if (NewState != DISABLE) + { + HT_WDT->PR = PRCT_SET; + } + else + { + HT_WDT->PR = PRCT_RESET; + } +} + +/*********************************************************************************************************//** + * @brief Set reload value of the WDT. + * @param WDT_WDTV : specify the WDT Reload value. + * This parameter must be a number between 0 and 0x0FFF + * @retval None + ************************************************************************************************************/ +void WDT_SetReloadValue(u16 WDT_WDTV) +{ + /* Check the parameters */ + Assert_Param(IS_WDT_RELOAD(WDT_WDTV)); + + HT_WDT->MR0 = WDT_WDTV | (HT_WDT->MR0 & 0x0000F000); +} + +/*********************************************************************************************************//** + * @brief Get the current reload value of the WDT. + * @retval WDT reload value between 0 and 0x0FFF + ************************************************************************************************************/ +u16 WDT_GetReloadValue(void) +{ + return ((u16)(HT_WDT->MR0 & 0xFFF)); +} + +/*********************************************************************************************************//** + * @brief Set delta value of the WDT. + * @param WDT_WDTD : specify the WDT Delta value. + * This parameter must be a number between 0 and 0x0FFF + * @retval None + ************************************************************************************************************/ +void WDT_SetDeltaValue(u16 WDT_WDTD) +{ + /* Check the parameters */ + Assert_Param(IS_WDT_DELTA(WDT_WDTD)); + + HT_WDT->MR1 = (WDT_WDTD | (HT_WDT->MR1 & 0x00007000)); +} + +/*********************************************************************************************************//** + * @brief Get current delta value of the WDT. + * @retval WDT delta value between 0 and 0x0FFF + ************************************************************************************************************/ +u16 WDT_GetDeltaValue(void) +{ + return ((u16)(HT_WDT->MR1 & 0xFFF)); +} + +/*********************************************************************************************************//** + * @brief Set prescaler value of the WDT. + * @param WDT_PRESCALER: specify the WDT Prescaler value. + * This parameter can be one of the following values: + * @arg WDT_PRESCALER_1 : WDT prescaler set to 1 + * @arg WDT_PRESCALER_2 : WDT prescaler set to 2 + * @arg WDT_PRESCALER_4 : WDT prescaler set to 4 + * @arg WDT_PRESCALER_8 : WDT prescaler set to 8 + * @arg WDT_PRESCALER_16 : WDT prescaler set to 16 + * @arg WDT_PRESCALER_32 : WDT prescaler set to 32 + * @arg WDT_PRESCALER_64 : WDT prescaler set to 64 + * @arg WDT_PRESCALER_128 : WDT prescaler set to 128 + * @retval None + ************************************************************************************************************/ +void WDT_SetPrescaler(u16 WDT_PRESCALER) +{ + /* Check the parameters */ + Assert_Param(IS_WDT_PRESCALER(WDT_PRESCALER)); + + HT_WDT->MR1 = (WDT_PRESCALER | (HT_WDT->MR1 & 0x00000FFF)); +} + +/*********************************************************************************************************//** + * @brief Get the current prescaler value of the WDT. + * @retval WDT prescaler value + ************************************************************************************************************/ +u8 WDT_GetPrescaler(void) +{ + u32 tmp; + + tmp = HT_WDT->MR1 & 0x7000; + tmp >>= 12; + return ((u8)0x1 << tmp); +} + +/*********************************************************************************************************//** + * @brief WDT Restart (Reload WDT Counter) + * @retval None + ************************************************************************************************************/ +void WDT_Restart(void) +{ + HT_WDT->CR = RESTART_KEY | 0x1; +} + +/*********************************************************************************************************//** + * @brief Check whether the specified WDT flag has been set. + * @param WDT_FLAG: specify the flag to be check. + * This parameter can be one of the following values: + * @arg WDT_FLAG_UNDERFLOW : WDT underflow active + * @arg WDT_FLAG_ERROR : WDT error active + * @retval SET or RESET + ************************************************************************************************************/ +FlagStatus WDT_GetFlagStatus(u32 WDT_FLAG) +{ + u32 statusreg = 0; + FlagStatus bitstatus = RESET; + + /* Check the parameters */ + Assert_Param(IS_WDT_FLAG(WDT_FLAG)); + + statusreg = HT_WDT->SR; + + if (statusreg != WDT_FLAG) + { + bitstatus = RESET; + } + else + { + bitstatus = SET; + } + + return bitstatus; +} + +/*********************************************************************************************************//** + * @brief Enable or Disable the WDTLOCK. + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void WDT_LockCmd(ControlStatus NewState) +{ + u32 uRegVale; + + /* Check the parameters */ + Assert_Param(IS_CONTROL_STATUS(NewState)); + + uRegVale = HT_WDT->CSR; + if (NewState != DISABLE) + { + HT_WDT->CSR |= (MODE0_WDTLOCK_SET | (uRegVale & 0x00000001)); + } + else + { + HT_WDT->CSR &= (MODE0_WDTLOCK_RESET | (uRegVale & 0x00000001)); + } +} + +/*********************************************************************************************************//** + * @brief WDT source select. + * @param WDT_SOURCE: LSI or LSE of the WDT source. + * This parameter can be one of the following values: + * @arg WDT_SOURCE_LSI : + * @arg WDT_SOURCE_LSE : + * @retval None + ************************************************************************************************************/ +void WDT_SourceConfig(u32 WDT_SOURCE) +{ + /* Check the parameters */ + Assert_Param(IS_WDT_SOURCE_SELECT(WDT_SOURCE)); + + if (WDT_SOURCE != WDT_SOURCE_LSE) + { + HT_WDT->CSR = WDT_SOURCE_LSI; + } + else + { + HT_WDT->CSR = WDT_SOURCE_LSE; + } +} +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ diff --git a/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/src/ht32f2xxxx_csif.c b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/src/ht32f2xxxx_csif.c new file mode 100644 index 0000000000..fed68afd33 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/src/ht32f2xxxx_csif.c @@ -0,0 +1,386 @@ +/*********************************************************************************************************//** + * @file ht32f2xxxx_csif.c + * @version $Rev:: 118 $ + * @date $Date:: 2017-06-02 #$ + * @brief This file provides all the CSIF firmware functions. + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ + +/* Includes ------------------------------------------------------------------------------------------------*/ +#include "ht32f2xxxx_csif.h" + +/** @addtogroup HT32F1xxxx_Peripheral_Driver HT32F1xxxx Peripheral Driver + * @{ + */ + +/** @defgroup CSIF CSIF + * @brief CSIF driver modules + * @{ + */ + + +/* Private constants ---------------------------------------------------------------------------------------*/ +/** @defgroup CSIF_Private_Define CSIF private definitions + * @{ + */ +/* CSIF CSIFEN mask */ +#define ENR_CSIFEN_SET ((u32)0x80000000) +#define ENR_CSIFEN_RESET ((u32)0x00000000) +/** + * @} + */ + +/* Global functions ----------------------------------------------------------------------------------------*/ +/** @defgroup CSIF_Exported_Functions CSIF exported functions + * @{ + */ +/*********************************************************************************************************//** + * @brief Deinitialize the CSIF peripheral registers to their default reset values. + * @retval None + ***********************************************************************************************************/ +void CSIF_DeInit(void) +{ + RSTCU_PeripReset_TypeDef RSTCUReset = {{0}}; + + RSTCUReset.Bit.CSIF = 1; + RSTCU_PeripReset(RSTCUReset, ENABLE); +} + +/*********************************************************************************************************//** + * @brief Initializes the CSIF peripheral according to the specified parameters in the CSIF_BasicInitStruct. + * @param CSIF_BasicInitStruct: pointer to a CSIF_BasicInitTypeDef structure that contains the configuration + * information for the specified CSIF peripheral. + * @retval None + ***********************************************************************************************************/ +void CSIF_BasicInit(CSIF_BasicInitTypeDef* CSIF_BasicInitStruct) +{ + /* Check the parameters */ + Assert_Param(IS_CSIF_FORMAT(CSIF_BasicInitStruct->CSIF_Format)); + Assert_Param(IS_CSIF_VSYNC_TYPE(CSIF_BasicInitStruct->CSIF_VSYNCType)); + Assert_Param(IS_CSIF_HSYNC_TYPE(CSIF_BasicInitStruct->CSIF_HSYNCType)); + Assert_Param(IS_CSIF_SAMPLE_EDGE(CSIF_BasicInitStruct->CSIF_SampleEdge)); + Assert_Param(IS_CSIF_VSYNC_POLARITY(CSIF_BasicInitStruct->CSIF_VSYNCPolarity)); + Assert_Param(IS_CSIF_HSYNC_POLARITY(CSIF_BasicInitStruct->CSIF_HSYNCPolarity)); + Assert_Param(IS_CSIF_LINE_DELAY(CSIF_BasicInitStruct->CSIF_LineDelay)); + Assert_Param(IS_CSIF_FRAME_DELAY(CSIF_BasicInitStruct->CSIF_FrameDelay)); + Assert_Param(IS_CSIF_IMAGE_WIDTH(CSIF_BasicInitStruct->CSIF_ImageWidth)); + Assert_Param(IS_CSIF_IMAGE_HEIGHT(CSIF_BasicInitStruct->CSIF_ImageHeight)); + + /*------------------------ CSIF Control Register Configuration -------------------------------------------*/ + HT_CSIF->CR = CSIF_BasicInitStruct->CSIF_Format | CSIF_BasicInitStruct->CSIF_VSYNCType | CSIF_BasicInitStruct->CSIF_HSYNCType | + CSIF_BasicInitStruct->CSIF_SampleEdge | CSIF_BasicInitStruct->CSIF_VSYNCPolarity | + CSIF_BasicInitStruct->CSIF_HSYNCPolarity | (CSIF_BasicInitStruct->CSIF_LineDelay << 8) | + (CSIF_BasicInitStruct->CSIF_FrameDelay << 16); + + /*------------------------ CSIF Image Width/Height Register Configuration --------------------------------*/ + HT_CSIF->IMGWH = (CSIF_BasicInitStruct->CSIF_ImageWidth-1) | ((CSIF_BasicInitStruct->CSIF_ImageHeight-1) << 16); +} + +/*********************************************************************************************************//** + * @brief Fills each CSIF_BasicInitStruct member with its default value. + * @param CSIF_BasicInitStruct: pointer to an CSIF_BasicInitTypeDef structure which will be initialized. + * @retval None + ***********************************************************************************************************/ +void CSIF_BasicStructInit(CSIF_BasicInitTypeDef* CSIF_BasicInitStruct) +{ + /* Initialize the CSIF_Format member */ + CSIF_BasicInitStruct->CSIF_Format = CSIF_FORMAT_RAWRGB; + + /* Initialize the CSIF_VSYNCType member */ + CSIF_BasicInitStruct->CSIF_VSYNCType = CSIF_VSYNCTYPE_PULSE; + + /* Initialize the CSIF_HSYNCType member */ + CSIF_BasicInitStruct->CSIF_HSYNCType = CSIF_HSYNCTYPE_CONTINUOUS; + + /* Initialize the CSIF_SampleEdge member */ + CSIF_BasicInitStruct->CSIF_SampleEdge = CSIF_SAMPLEEDGE_FALLING; + + /* Initialize the CSIF_VSYNCPolarity member */ + CSIF_BasicInitStruct->CSIF_VSYNCPolarity = CSIF_VSYNCPOLARITY_HIGH; + + /* Initialize the CSIF_HSYNCPolarity member */ + CSIF_BasicInitStruct->CSIF_HSYNCPolarity = CSIF_HSYNCPOLARITY_HIGH; + + /* Initialize the CSIF_LineDelay member */ + CSIF_BasicInitStruct->CSIF_LineDelay = 0; + + /* Initialize the CSIF_FrameDelay member */ + CSIF_BasicInitStruct->CSIF_FrameDelay = 0; + + /* Initialize the CSIF_ImageWidth member */ + CSIF_BasicInitStruct->CSIF_ImageWidth = 0; + + /* Initialize the CSIF_ImageHeight member */ + CSIF_BasicInitStruct->CSIF_ImageHeight = 0; + +} + +/*********************************************************************************************************//** + * @brief Initializes the CSIF peripheral according to the specified parameters in the CSIF_WindowInitStruct. + * @param CSIF_WindowInitStruct: pointer to a CSIF_WindowInitTypeDef structure that contains the configuration + * information for the specified CSIF peripheral. + * @retval None + ***********************************************************************************************************/ +void CSIF_WindowInit(CSIF_WindowInitTypeDef* CSIF_WindowInitStruct) +{ + /* Check the parameters */ + Assert_Param(IS_CSIF_WINDOW(CSIF_WindowInitStruct->CSIF_Window)); + Assert_Param(IS_CSIF_HORSTART_POINT(CSIF_WindowInitStruct->CSIF_HorizontalStartPoint)); + Assert_Param(IS_CSIF_VERSTART_POINT(CSIF_WindowInitStruct->CSIF_VerticalStartPoint)); + Assert_Param(IS_CSIF_WINDOW_WIDTH(CSIF_WindowInitStruct->CSIF_WindowWidth)); + Assert_Param(IS_CSIF_WINDOW_HEIGHT(CSIF_WindowInitStruct->CSIF_WindowHeight)); + + /*------------------------ CSIF Window Capture Register 0 Configuration ----------------------------------*/ + HT_CSIF->WCR0 = CSIF_WindowInitStruct->CSIF_Window | CSIF_WindowInitStruct->CSIF_HorizontalStartPoint | + (CSIF_WindowInitStruct->CSIF_VerticalStartPoint << 16); + + /*------------------------ CSIF Window Capture Register 1 Configuration ----------------------------------*/ + HT_CSIF->WCR1 = (CSIF_WindowInitStruct->CSIF_WindowWidth-1) | ((CSIF_WindowInitStruct->CSIF_WindowHeight-1) << 16); +} + +/*********************************************************************************************************//** + * @brief Fills each CSIF_WindowStructInit member with its default value. + * @param CSIF_WindowInitStruct: pointer to an CSIF_WindowInitTypeDef structure which will be initialized. + * @retval None + ***********************************************************************************************************/ +void CSIF_WindowStructInit(CSIF_WindowInitTypeDef* CSIF_WindowInitStruct) +{ + /* Initialize the CSIF_Window member */ + CSIF_WindowInitStruct->CSIF_Window = CSIF_WINDOW_DISABLE; + + /* Initialize the CSIF_HorizontalStartPoint member */ + CSIF_WindowInitStruct->CSIF_HorizontalStartPoint = 0; + + /* Initialize the CSIF_VerticalStartPoint member */ + CSIF_WindowInitStruct->CSIF_VerticalStartPoint = 0; + + /* Initialize the CSIF_WindowWidth member */ + CSIF_WindowInitStruct->CSIF_WindowWidth = 0; + + /* Initialize the CSIF_WindowHeight member */ + CSIF_WindowInitStruct->CSIF_WindowHeight = 0; +} + +/*********************************************************************************************************//** + * @brief Initializes the CSIF peripheral according to the specified parameters in the CSIF_SubSampleInitStruct. + * @param CSIF_SubSampleInitStruct: pointer to a CSIF_SubSampleInitTypeDef structure that contains the configuration + * information for the specified CSIF peripheral. + * @retval None + ***********************************************************************************************************/ +void CSIF_SubSampleInit(CSIF_SubSampleInitTypeDef* CSIF_SubSampleInitStruct) +{ + /* Check the parameters */ + Assert_Param(IS_CSIF_SUB_SAMPLE(CSIF_SubSampleInitStruct->CSIF_SubSample)); + Assert_Param(IS_CSIF_MASK_LENGTH(CSIF_SubSampleInitStruct->CSIF_ColumnSkipMaskLength)); + Assert_Param(IS_CSIF_MASK_LENGTH(CSIF_SubSampleInitStruct->CSIF_RowSkipMaskLength)); + + /*------------------------ CSIF Row & Column Sub-Sample RegisterConfiguration ----------------------------*/ + HT_CSIF->SMP = CSIF_SubSampleInitStruct->CSIF_SubSample | (CSIF_SubSampleInitStruct->CSIF_ColumnSkipMaskLength << 8) | + (CSIF_SubSampleInitStruct->CSIF_RowSkipMaskLength << 16); + + /*------------------------ CSIF Column Sub-Sample Register Configuration ---------------------------------*/ + HT_CSIF->SMPCOL = CSIF_SubSampleInitStruct->CSIF_ColumnSkipMask; + + /*------------------------ CSIF Row Sub-Sample Register Configuration ------------------------------------*/ + HT_CSIF->SMPROW = CSIF_SubSampleInitStruct->CSIF_RowSkipMask; +} + +/*********************************************************************************************************//** + * @brief Fills each CSIF_SubSampleInitStruct member with its default value + * @param CSIF_SubSampleInitStruct: pointer to an CSIF_SubSampleInitTypeDef structurewhich will be initialized. + * @retval None + ***********************************************************************************************************/ +void CSIF_SunSampleStructInit(CSIF_SubSampleInitTypeDef* CSIF_SubSampleInitStruct) +{ + /* Initialize the CSIF_SubSample member */ + CSIF_SubSampleInitStruct->CSIF_SubSample = CSIF_SUBSAMPLE_DISABLE; + + /* Initialize the CSIF_ColumnSkipMaskLength member */ + CSIF_SubSampleInitStruct->CSIF_ColumnSkipMaskLength = CSIF_MASKLENGTH_32B; + + /* Initialize the CSIF_RowSkipMaskLength member */ + CSIF_SubSampleInitStruct->CSIF_RowSkipMaskLength = CSIF_MASKLENGTH_32B; + + /* Initialize the CSIF_ColumnSkipMask member */ + CSIF_SubSampleInitStruct->CSIF_ColumnSkipMask = 0; + + /* Initialize the CSIF_RowSkipMask member */ + CSIF_SubSampleInitStruct->CSIF_RowSkipMask = 0; +} + +/*********************************************************************************************************//** + * @brief Enables or Disables the CSIF peripheral. + * @param NewState: new state of the CSIF peripheral. + * This parameter can be: ENABLE or DISABLE. + * @retval None + ***********************************************************************************************************/ +void CSIF_Cmd(ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_CONTROL_STATUS(NewState)); + + if (NewState != DISABLE) + { + /* Enable CSIF peripheral */ + HT_CSIF->ENR = ENR_CSIFEN_SET; + } + else + { + /* Disable CSIF peripheral */ + HT_CSIF->ENR = ENR_CSIFEN_RESET; + } +} + +/*********************************************************************************************************//** + * @brief Enables or Disables the specified CSIF interrupt. + * @param CSIF_Int: specifies if the CSIF interrupt source to be enabled or disabled. + * This parameter can be any combination of the following values: + * @arg CSIF_INT_SOFFLG : CSIF start of frame interrupt + * @arg CSIF_INT_EOFFLG : CSIF end of frame interrupt + * @arg CSIF_INT_CAPSTA : CSIF cpature start interrupt + * @arg CSIF_INT_CAPSTS : CSIF capture status interrupt + * @arg CSIF_INT_BADFRAME : CSIF bad frame interrupt + * @arg CSIF_INT_FIFOOVR : CSIF FIFO overrun interrupt + * @arg CSIF_INT_FIFOEMP : CSIF FIFO empty interrupt + * @arg CSIF_INT_FIFOFUL : CSIF FIFO full interrupt + * @arg CSIF_INT_ALL : All CSIF interrupt + * @param NewState: new state of the CSIF interrupts. + * This parameter can be: ENABLE or DISABLE. + * @retval None + ***********************************************************************************************************/ +void CSIF_IntConfig(u32 CSIF_Int, ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_CSIF_INT(CSIF_Int)); + Assert_Param(IS_CONTROL_STATUS(NewState)); + + if (NewState != DISABLE) + { + HT_CSIF->IER |= CSIF_Int; + } + else + { + HT_CSIF->IER &= (u32)~CSIF_Int; + } +} + +/*********************************************************************************************************//** + * @brief Check whether the specified CSIF flag has been set. + * @param CSIF_Flag: specifies the flag that is to be check. + * This parameter can be one of the following values: + * @arg CSIF_FLAG_SOFFLG : CSIF start of frame flag + * @arg CSIF_FLAG_EOFFLG : CSIF end of frame flag + * @arg CSIF_FLAG_CAPSTA : CSIF cpature start flag + * @arg CSIF_FLAG_CAPSTS : CSIF capture status flag + * @arg CSIF_FLAG_BADFRAME : CSIF bad frame fla + * @arg CSIF_FLAG_FIFOOVR : CSIF FIFO overrun flag + * @arg CSIF_FLAG_FIFOEMP : CSIF FIFO empty flag + * @arg CSIF_FLAG_FIFOFUL : CSIF FIFO full flag + * @retval The new state of CSIF_Flag (SET or RESET). + ***********************************************************************************************************/ +FlagStatus CSIF_GetFlagStatus(u32 CSIF_Flag) +{ + u32 statusreg = 0; + FlagStatus bitstatus = RESET; + + /* Check the parameters */ + Assert_Param(IS_CSIF_FLAG(CSIF_Flag)); + + statusreg = HT_CSIF->SR; + + if ((statusreg & CSIF_Flag) != (u32)RESET ) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + return bitstatus; +} + +/*********************************************************************************************************//** + * @brief Clear the specified CSIF flag. + * @param CSIF_Flag: specifies the flag to be cleared. + * This parameter can be one of the following values: + * @arg CSIF_FLAG_SOFFLG : CSIF start of frame flag + * @arg CSIF_FLAG_EOFFLG : CSIF end of frame flag + * @arg CSIF_FLAGT_CAPSTA : CSIF cpature start flag + * @arg CSIF_FLAG_CAPSTS : CSIF capture status flag + * @arg CSIF_FLAG_BADFRAME : CSIF bad frame flag + * @retval None + ***********************************************************************************************************/ +void CSIF_ClearFlag(u32 CSIF_Flag) +{ + /* Check the parameters */ + Assert_Param(IS_CSIF_CLEAR_FLAG(CSIF_Flag)); + + HT_CSIF->SR = CSIF_Flag; +} + +/*********************************************************************************************************//** + * @brief Enables or Disables the CSIF Master Clock. + * @param NewState: new state of the CSIF Master Clock. + * This parameter can be: ENABLE or DISABLE. + * @retval None + ***********************************************************************************************************/ +void CSIF_MasterClockCmd(ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_CONTROL_STATUS(NewState)); + + if (NewState != DISABLE) + { + HT_CKCU->AHBCCR |= 0x00000200; + } + else + { + HT_CKCU->AHBCCR &= 0xFFFFFDFF; + } +} + +/*********************************************************************************************************//** + * @brief Sets the CSIF Master Clock Prescaler. + * @param CSIF_Prescaler: specifies the CSIF Master Clock Prescaler value. + * This parameter must be even. + * @retval None + ***********************************************************************************************************/ +void CSIF_SetMasterClockPrescaler(u8 CSIF_Prescaler) +{ + /* Check the parameters */ + Assert_Param(IS_CSIF_PRESCALER(CSIF_Prescaler)); + + HT_CKCU->GCFGR |= (CSIF_Prescaler/2-1) << 24; +} +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ diff --git a/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/src/printf.c b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/src/printf.c new file mode 100644 index 0000000000..7b4f905013 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/src/printf.c @@ -0,0 +1,390 @@ +/*********************************************************************************************************//** + * @file printf.c + * @version $Rev:: 5 $ + * @date $Date:: 2017-05-11 #$ + * @brief Print functions. + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ + +/* Includes ------------------------------------------------------------------------------------------------*/ +#include "ht32.h" +#include + +/** @addtogroup HT32_Peripheral_Driver HT32 Peripheral Driver + * @{ + */ + +/** @defgroup PRINTF printf re-implementation + * @brief printf related functions + * @{ + */ + + +/* Private macro -------------------------------------------------------------------------------------------*/ +/** @defgroup PRINTF_Private_Macro printf private macros + * @{ + */ +#define vaStart(list, param) list = (char*)((int)¶m + sizeof(param)) +#define vaArg(list, type) ((type *)(list += sizeof(type)))[-1] +/** + * @} + */ + +/* Private function prototypes -----------------------------------------------------------------------------*/ +static const char *FormatItem(const char *f, int a); +static void PutRepChar(const char c, int count); +static int PutString(const char *pString); +static int PutStringReverse(const char *pString, int index); +static void PutNumber(int value, int radix, int width, char fill); + +/* Global functions ----------------------------------------------------------------------------------------*/ +/** @defgroup PRINTF_Exported_Functions printf exported functions + * @{ + */ +/*********************************************************************************************************//** + * @brief Print function. + * @param f: Format string. + * @retval String length. + ************************************************************************************************************/ +signed int printf(const char *f, ...) +{ + char *argP; + int i = 0; + + vaStart(argP, f); + while (*f) + { + if (*f == '%') + { + f = FormatItem(f + 1, vaArg(argP, int)); + } + else + { + fputc(*f++, (FILE *)1); + } + i++; + } + return i; +} + +/*********************************************************************************************************//** + * @brief Put string. + * @param pString: String. + * @retval String length. + ************************************************************************************************************/ +signed int puts(const char *pString) +{ + int i; + i = PutString(pString); + fputc('\n', (FILE *)1); + return i; +} +/** + * @} + */ + +/* Private functions ---------------------------------------------------------------------------------------*/ +/** @defgroup PRINTF_Private_Function printf private functions + * @{ + */ +/*********************************************************************************************************//** + * @brief Format item for print function. + * @param f: Format string. + * @param a: Length of format string. + * @retval Point of string. + ************************************************************************************************************/ +static const char *FormatItem(const char *f, int a) +{ + char c; + int fieldwidth = 0; + int leftjust = FALSE; + int radix = 0; + char fill = ' '; + int i; + + if (*f == '0') + { + fill = '0'; + } + + while ((c = *f++) != 0) + { + if (c >= '0' && c <= '9') + { + fieldwidth = (fieldwidth * 10) + (c - '0'); + } + else + { + switch (c) + { + case '\000': + { + return (--f); + } + case '%': + { + fputc('%', (FILE *)1); + return (f); + } + case '-': + { + leftjust = TRUE; + break; + } + case 'c': + { + if (leftjust) + { + fputc(a & 0x7f, (FILE *)f); + } + if (fieldwidth > 0) + { + PutRepChar(fill, fieldwidth - 1); + } + if (!leftjust) + { + fputc(a & 0x7f, (FILE *)f); + return (f); + } + } + case 's': + { + i = 0; + while (*((char *)(a + i)) !='\0' ) + { + i++; + } + + if (leftjust) + { + PutString((char *)a); + } + + if (fieldwidth > i ) + { + PutRepChar(fill, fieldwidth - i); + } + + if (!leftjust) + { + PutString((char *)a); + } + return (f); + } + case 'l': + { + radix = -10; + f++; + break; + } + case 'd': + case 'i': + { + radix = -10; + break; + } + case 'u': + { + radix = 10; + break; + } + case 'x': + case 'X': + { + radix = 16; + break; + } + case 'o': + { + radix = 8; + break; + } + default: + { + radix = 3; + break; + } + } + } + if (radix) + { + break; + } + } + + if (leftjust) + { + fieldwidth = -fieldwidth; + } + + PutNumber(a, radix, fieldwidth, fill); + + return (f); +} + +/*********************************************************************************************************//** + * @brief Put repeat character. + * @param c: Character. + * @param count: Repeat count + ************************************************************************************************************/ +static void PutRepChar(const char c, int count) +{ + while (count--) + { + fputc(c, (FILE *)1); + } +} + +/*********************************************************************************************************//** + * @brief Put string. + * @param pString: String. + * @retval String length. + ************************************************************************************************************/ +static int PutString(const char *pString) +{ + int i = 0; + while (*pString != '\0') + { + fputc(*pString, (FILE *)1); + pString++; + i++; + } + + return i; +} + +/*********************************************************************************************************//** + * @brief Put string in reversed order. + * @param pString: String. + * @param index: String length + * @retval String length. + ************************************************************************************************************/ +static int PutStringReverse(const char *pString, int index) +{ + int i = 0; + while ((index--) > 0) + { + fputc(pString[index], (FILE *)1); + i++; + } + return i; +} + +/*********************************************************************************************************//** + * @brief Put number. + * @param value: Value of number. + * @param radix: Radix of number. + * @param width: Width of number. + * @param fill: fill character. + ************************************************************************************************************/ +static void PutNumber(int value, int radix, int width, char fill) +{ + char buffer[8]; + int bi = 0; + unsigned int uvalue; + unsigned short digit; + unsigned short left = FALSE; + unsigned short negative = FALSE; + + if (fill == 0) + { + fill = ' '; + } + + if (width < 0) + { + width = -width; + left = TRUE; + } + + if (width < 0 || width > 80) + { + width = 0; + } + + if (radix < 0) + { + radix = -radix; + if (value < 0) + { + negative = TRUE; + value = -value; + } + } + + uvalue = value; + + do + { + if (radix != 16) + { + digit = uvalue % radix; + uvalue = uvalue / radix; + } + else + { + digit = uvalue & 0xf; + uvalue = uvalue >> 4; + } + buffer[bi] = digit + ((digit <= 9) ? '0' : ('A' - 10)); + bi++; + } + while (uvalue != 0); + + if (negative) + { + buffer[bi] = '-'; + bi += 1; + } + + if (width <= bi) + { + PutStringReverse(buffer, bi); + } + else + { + width -= bi; + if (!left) + { + PutRepChar(fill, width); + } + + PutStringReverse(buffer, bi); + + if (left) + { + PutRepChar(fill, width); + } + } +} +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ diff --git a/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/src/syscalls.c b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/src/syscalls.c new file mode 100644 index 0000000000..b78500264e --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/src/syscalls.c @@ -0,0 +1,127 @@ +/*********************************************************************************************************//** + * @file syscalls.c + * @version $Rev:: 2904 $ + * @date $Date:: 2023-03-27 #$ + * @brief Implementation of system call related functions. + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ + +/* Includes ------------------------------------------------------------------------------------------------*/ +#include +#include +#include +#include + +/** @addtogroup HT32_Peripheral_Driver HT32 Peripheral Driver + * @{ + */ + +/** @defgroup SYSCALLS System call functions + * @brief System call functions for GNU toolchain + * @{ + */ + + +/* Global variables ----------------------------------------------------------------------------------------*/ +/** @defgroup SYSCALLS_Global_Variable System call global variables + * @{ + */ +#undef errno +extern int errno; +extern int _end; +/** + * @} + */ + +/* Global functions ----------------------------------------------------------------------------------------*/ +/** @defgroup SYSCALLS_Exported_Functions System call exported functions + * @{ + */ +caddr_t _sbrk(int incr) +{ + static unsigned char *heap = NULL; + unsigned char *prev_heap; + + if (heap == NULL) + { + heap = (unsigned char *)&_end; + } + prev_heap = heap; + + heap += incr; + + return (caddr_t) prev_heap; +} + +int link(char *old, char *new) { +return -1; +} + +int _close(int fd) +{ + return -1; +} + +int _fstat(int fd, struct stat *st) +{ + st->st_mode = S_IFCHR; + return 0; +} + +int _isatty(int fd) +{ + return 1; +} + +int _lseek(int fd, int ptr, int dir) +{ + return 0; +} + +int _read(int fd, char *ptr, int len) +{ + return 0; +} + +int _write(int fd, char *ptr, int len) +{ + return len; +} + +void abort(void) +{ + /* Abort called */ + while (1); +} + +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ diff --git a/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32_USBD_Library/example/ht32_usbd_class.c b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32_USBD_Library/example/ht32_usbd_class.c new file mode 100644 index 0000000000..a90caeb986 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32_USBD_Library/example/ht32_usbd_class.c @@ -0,0 +1,426 @@ +/*********************************************************************************************************//** + * @file example/ht32_usbd_class.c + * @version $Rev:: 11 $ + * @date $Date:: 2017-05-15 #$ + * @brief The USB Device Class. + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ + +/* Includes ------------------------------------------------------------------------------------------------*/ +#include "ht32.h" +#include "ht32_usbd_core.h" +#include "ht32_usbd_class.h" + +/** @addtogroup HT32_USBD_Library HT32 USB Device Library + * @{ + */ + +/** @defgroup USBDClass USB Device Class + * @brief USB Device Class + * @{ + */ + +/* Exported constants --------------------------------------------------------------------------------------*/ +/** @defgroup USBDClass_Private_Define USB Device Class private definitions + * @{ + */ +#define CLASS_REQ_01_CMD1 (u16)(0x1 << 8) +#define CLASS_REQ_02_CMD2 (u16)(0x2 << 8) +/** + * @} + */ + +/* Private function prototypes -----------------------------------------------------------------------------*/ +static void USBDClass_MainRoutine(u32 uPara); +static void USBDClass_ClassProcess(void); +static void USBDClass_EPT1Process(void); +static void USBDClass_EPT2Process(void); + +static void USBDClass_Reset(u32 uPara); +static void USBDClass_StartOfFrame(u32 uPara); + +static void USBDClass_Standard_GetDescriptor(USBDCore_Device_TypeDef *pDev); +static void USBDClass_Standard_SetInterface(USBDCore_Device_TypeDef *pDev); +static void USBDClass_Standard_GetInterface(USBDCore_Device_TypeDef *pDev); + +static void USBDClass_Request(USBDCore_Device_TypeDef *pDev); + +static void USBDClass_CMD1(USBDCore_Device_TypeDef *pDev); +static void USBDClass_CMD2(USBDCore_Device_TypeDef *pDev); + +static void USBDClass_Endpoint1(USBD_EPTn_Enum EPTn); +static void USBDClass_Endpoint2(USBD_EPTn_Enum EPTn); +static void USBDClass_Endpoint3(USBD_EPTn_Enum EPTn); +static void USBDClass_Endpoint4(USBD_EPTn_Enum EPTn); +static void USBDClass_Endpoint5(USBD_EPTn_Enum EPTn); +static void USBDClass_Endpoint6(USBD_EPTn_Enum EPTn); +static void USBDClass_Endpoint7(USBD_EPTn_Enum EPTn); + +/* Global Function -----------------------------------------------------------------------------------------*/ +/** @defgroup USBDClass_Exported_Functions USB Device Class exported functions + * @{ + */ +/*********************************************************************************************************//** + * @brief USB Class initialization. + * @param pClass: pointer of USBDCore_Class_TypeDef + * @retval None + ***********************************************************************************************************/ +void USBDClass_Init(USBDCore_Class_TypeDef *pClass) +{ + pClass->CallBack_MainRoutine.func = USBDClass_MainRoutine; + //pClass->CallBack_MainRoutine.uPara = (u32)NULL; + + pClass->CallBack_Reset.func = USBDClass_Reset; + pClass->CallBack_Reset.uPara = (u32)NULL; + + pClass->CallBack_StartOfFrame.func = USBDClass_StartOfFrame; + pClass->CallBack_StartOfFrame.uPara = (u32)NULL; + + pClass->CallBack_ClassGetDescriptor = USBDClass_Standard_GetDescriptor; + pClass->CallBack_ClassSetInterface = USBDClass_Standard_SetInterface; + pClass->CallBack_ClassGetInterface = USBDClass_Standard_GetInterface; + + pClass->CallBack_ClassRequest = USBDClass_Request; + pClass->CallBack_EPTn[1] = USBDClass_Endpoint1; + pClass->CallBack_EPTn[2] = USBDClass_Endpoint2; + pClass->CallBack_EPTn[3] = USBDClass_Endpoint3; + pClass->CallBack_EPTn[4] = USBDClass_Endpoint4; + pClass->CallBack_EPTn[5] = USBDClass_Endpoint5; + pClass->CallBack_EPTn[6] = USBDClass_Endpoint6; + pClass->CallBack_EPTn[7] = USBDClass_Endpoint7; + + #ifdef RETARGET_IS_USB + pClass->CallBack_EPTn[RETARGET_RX_EPT] = SERIAL_USBDClass_RXHandler; + #endif + + return; +} +/** + * @} + */ + +/* Private functions ---------------------------------------------------------------------------------------*/ +/** @defgroup USBDClass_Private_Functions USB Device Class private functions + * @{ + */ +/*********************************************************************************************************//** + * @brief USB Class main routine. + * @param uPara: Parameter for Class main routine + * @retval None + ***********************************************************************************************************/ +static void USBDClass_MainRoutine(u32 uPara) +{ + USBDClass_ClassProcess(); + USBDClass_EPT1INProcess(); + USBDClass_EPT2OUTProcess(); + + return; +} + +/*********************************************************************************************************//** + * @brief USB Class Process for application. + * @retval None + ***********************************************************************************************************/ +static void USBDClass_ClassProcess(void) +{ + return; +} + +/*********************************************************************************************************//** + * @brief USB Class Endpoint 1 Process for application. + * @retval None + ***********************************************************************************************************/ +static void USBDClass_EPT1Process(void) +{ + if (gIsEP1 == TRUE) + { + gIsEP1 = FALSE; + } + + return; +} + +/*********************************************************************************************************//** + * @brief USB Class Endpoint 2 Process for application. + * @retval None + ***********************************************************************************************************/ +static void USBDClass_EPT2Process(void) +{ + if (gIsEP2 == TRUE) + { + gIsEP2 = FALSE; + } + + return; +} + +/*********************************************************************************************************//** + * @brief USB Class Reset. + * @param uPara: Parameter for Class Reset. + * @retval None + ***********************************************************************************************************/ +static void USBDClass_Reset(u32 uPara) +{ + +} + +/*********************************************************************************************************//** + * @brief USB Class Start of Frame. + * @param uPara: Parameter for Class Start of Frame. + * @retval None + ***********************************************************************************************************/ +static void USBDClass_StartOfFrame(u32 uPara) +{ + +} + +/*********************************************************************************************************//** + * @brief USB Device Class Request + * @param pDev: pointer of USB Device + * @retval None + ***********************************************************************************************************/ +static void USBDClass_Request(USBDCore_Device_TypeDef *pDev) +{ + u16 uUSBCmd = *((u16 *)(&(pDev->Request))); + +#ifdef RETARGET_IS_USB + SERIAL_USBDClass_Request(pDev); +#endif + + switch (uUSBCmd) + { + /*------------------------------------------------------------------------------------------------------*/ + /* | bRequest | Data transfer direction | Type | Recipient | Data */ + /*------------------------------------------------------------------------------------------------------*/ + + /*------------------------------------------------------------------------------------------------------*/ + /* | 01_CMD1 | 80_Device-to-Host | 20_Class Request | 1_Interface | 01A1h */ + /*------------------------------------------------------------------------------------------------------*/ + case (CLASS_REQ_01_CMDID0 | REQ_DIR_01_D2H | REQ_TYPE_01_CLS | REQ_REC_01_INF): + { + __DBG_USBPrintf("%06ld CMD0\t[%02d][%02d]\r\n", __DBG_USBCount, pDev->Request.wValueH, pDev->Request.wLength ); + USBDClass_RequestCMD1(pDev); + break; + } + /*------------------------------------------------------------------------------------------------------*/ + /* | 02_CMD2 | 00_Host-to-Device | 20_Class Request | 1_Interface | 0221h */ + /*------------------------------------------------------------------------------------------------------*/ + case (CLASS_REQ_02_GET_IDLE | REQ_DIR_00_H2D | REQ_TYPE_01_CLS | REQ_REC_01_INF): + { + __DBG_USBPrintf("%06ld CMD1\t[%02d][%02d]\r\n", __DBG_USBCount, pDev->Request.wValueH, pDev->Request.wLength ); + USBDClass_RequestCMD2(pDev); + break; + } + } + + return; +} + +/*********************************************************************************************************//** + * @brief USB Device Class Standard Request - GET_DESCRIPTOR + * @param pDev: pointer of USB Device + * @retval None + ***********************************************************************************************************/ +static void USBDClass_Standard_GetDescriptor(USBDCore_Device_TypeDef *pDev) +{ + u32 type = pDev->Request.wValueH; + + switch (type) + { + case DESC_TYPE_01_XXX + { + pDev->Transfer.pData = (uc8 *)(__BUFFER_POINTER__); + pDev->Transfer.sByteLength = DESC_LEN_XXX; + pDev->Transfer.Action = USB_ACTION_DATAIN; + break; + } + case DESC_TYPE_02_XXX: + { + pDev->Transfer.pData = (uc8 *)(__BUFFER_POINTER__); + pDev->Transfer.sByteLength = DESC_LEN_XXX; + pDev->Transfer.Action = USB_ACTION_DATAIN; + break; + } + } /* switch (type) */ + + return; +} + +/*********************************************************************************************************//** + * @brief USB Device Class Standard Request - SET_INTERFACE + * @param pDev: pointer of USB Device + * @retval None + ***********************************************************************************************************/ +static void USBDClass_Standard_SetInterface(USBDCore_Device_TypeDef *pDev) +{ + +} + +/*********************************************************************************************************//** + * @brief USB Device Class Standard Request - GET_INTERFACE + * @param pDev: pointer of USB Device + * @retval None + ***********************************************************************************************************/ +static void USBDClass_Standard_GetInterface(USBDCore_Device_TypeDef *pDev) +{ + +} + + + +/*********************************************************************************************************//** + * @brief USB Device Class Request - CMD1 + * @param pDev: pointer of USB Device + * @retval None + ***********************************************************************************************************/ +static void USBDClass_CMD1(USBDCore_Device_TypeDef *pDev) +{ + /* Add your own Class request function here.... + For example.... + + u32 uReportID = pDev->Request.wValueL; + u32 uInterface = pDev->Request.wIndex; + + pDev->Transfer.pData = (uc8 *)&(__IDLE_DURATION_BUFFER[uReportID]); + pDev->Transfer.sByteLength = 1; + pDev->Transfer.Action= USB_ACTION_DATAIN; + + */ + return; +} + +/*********************************************************************************************************//** + * @brief USB Device Class Request - CMD2 + * @param pDev: pointer of USB Device + * @retval None + ***********************************************************************************************************/ +static void USBDClass_CMD2(USBDCore_Device_TypeDef *pDev) +{ + /* Add your own Class request function here.... + For example.... + + u32 uReportID = pDev->Request.wValueL; + u32 uInterface = pDev->Request.wIndex; + + pDev->Transfer.pData = (uc8 *)&(__IDLE_DURATION_BUFFER[uReportID]); + pDev->Transfer.sByteLength = 1; + pDev->Transfer.Action= USB_ACTION_DATAIN; + + */ + return; +} + +/*********************************************************************************************************//** + * @brief USB Class Endpoint handler + * @param EPTn: USB Endpoint number + * @arg USBD_EPT0 ~ USBD_EPT7 + * @retval None + ***********************************************************************************************************/ +static void USBDClass_Endpoint1(USBD_EPTn_Enum EPTn) +{ + gIsEP1 = TRUE; + + __DBG_USBPrintf("%06ld EP1\t[%02d]", ++__DBG_USBCount, (int)USBDCore_EPTGetBufferLen(EPTn)); + + return; +} + +/*********************************************************************************************************//** + * @brief USB Class Endpoint handler + * @param EPTn: USB Endpoint number + * @arg USBD_EPT0 ~ USBD_EPT7 + * @retval None + ***********************************************************************************************************/ +static void USBDClass_Endpoint2(USBD_EPTn_Enum EPTn) +{ + gIsEP2 = TRUE; + __DBG_USBPrintf("%06ld EP2\t[%02d]", ++__DBG_USBCount, (int)USBDCore_EPTGetBufferLen(EPTn)); + + return; +} + +/*********************************************************************************************************//** + * @brief USB Class Endpoint handler + * @param EPTn: USB Endpoint number + * @arg USBD_EPT0 ~ USBD_EPT7 + * @retval None + ***********************************************************************************************************/ +static void USBDClass_Endpoint3(USBD_EPTn_Enum EPTn) +{ + return; +} + +/*********************************************************************************************************//** + * @brief USB Class Endpoint handler + * @param EPTn: USB Endpoint number + * @arg USBD_EPT0 ~ USBD_EPT7 + * @retval None + ***********************************************************************************************************/ +static void USBDClass_Endpoint4(USBD_EPTn_Enum EPTn) +{ + return; +} + +/*********************************************************************************************************//** + * @brief USB Class Endpoint handler + * @param EPTn: USB Endpoint number + * @arg USBD_EPT0 ~ USBD_EPT7 + * @retval None + ***********************************************************************************************************/ +static void USBDClass_Endpoint5(USBD_EPTn_Enum EPTn) +{ + return; +} + +/*********************************************************************************************************//** + * @brief USB Class Endpoint handler + * @param EPTn: USB Endpoint number + * @arg USBD_EPT0 ~ USBD_EPT7 + * @retval None + ***********************************************************************************************************/ +static void USBDClass_Endpoint6(USBD_EPTn_Enum EPTn) +{ + return; +} + +/*********************************************************************************************************//** + * @brief USB Class Endpoint handler + * @param EPTn: USB Endpoint number + * @arg USBD_EPT0 ~ USBD_EPT7 + * @retval None + ***********************************************************************************************************/ +static void USBDClass_Endpoint7(USBD_EPTn_Enum EPTn) +{ + return; +} +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ diff --git a/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32_USBD_Library/example/ht32_usbd_class.h b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32_USBD_Library/example/ht32_usbd_class.h new file mode 100644 index 0000000000..c674de9ce6 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32_USBD_Library/example/ht32_usbd_class.h @@ -0,0 +1,87 @@ +/*********************************************************************************************************//** + * @file example/ht32_usbd_class.h + * @version $Rev:: 5 $ + * @date $Date:: 2017-05-11 #$ + * @brief The header file of USB Device Class. + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------------------------------------*/ +#ifndef __HT32_USBD_CLASS_H +#define __HT32_USBD_CLASS_H + +/* Includes ------------------------------------------------------------------------------------------------*/ + +/** @addtogroup HT32_USBD_Library HT32 USB Device Library + * @{ + */ + +/** @defgroup USBDClass USB Device Class + * @brief USB Device Class + * @{ + */ + + +/* Exported constants --------------------------------------------------------------------------------------*/ +/** @defgroup USBDClass_Private_Define USB Device Class private definitions + * @{ + */ +/* For ht32_usbd_descriptor.c */ +#define CLASS_INF_CLASS (DESC_CLASS_03_XXX) +#define CLASS_INF_SUBCLASS (HID_SUBCLASS_00_NONE) +#define CLASS_INF_PTCO (HID_PROTOCOL_00_NONE) + +/* HID related definition */ +#define DESC_LEN_XXX ((u32)(9)) +#define DESC_LEN_XXX ((u16)(47)) + +#define DESC_TYPE_01_XXX (0x01) +#define DESC_TYPE_02_XXX (0x02) + +#define HID_SUBCLASS_00_NONE (0x00) +#define HID_SUBCLASS_01_BOOT (0x01) + +#define HID_PROTOCOL_00_NONE (0x00) +/** + * @} + */ + + +/* Exported functions --------------------------------------------------------------------------------------*/ +/** @defgroup USBDClass_Exported_Functions USB Device Class exported functions + * @{ + */ +void USBDClass_Init(USBDCore_Class_TypeDef *pClass); +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ + +#endif /* __HT32_USBD_CLASS_H ------------------------------------------------------------------------------*/ diff --git a/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32_USBD_Library/example/ht32_usbd_descriptor.c b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32_USBD_Library/example/ht32_usbd_descriptor.c new file mode 100644 index 0000000000..a4432bf192 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32_USBD_Library/example/ht32_usbd_descriptor.c @@ -0,0 +1,368 @@ +/*********************************************************************************************************//** + * @file example/ht32_usbd_descriptor.c + * @version $Rev:: 5 $ + * @date $Date:: 2017-05-11 #$ + * @brief The USB Descriptor. + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ +// <<< Use Configuration Wizard in Context Menu >>> + +/* Includes ------------------------------------------------------------------------------------------------*/ +#include "ht32.h" +#include "ht32_usbd_core.h" +#include "ht32_usbd_class.h" +#include "ht32_usbd_descriptor.h" + +/** @addtogroup HT32_USBD_Library HT32 USB Device Library + * @{ + */ + +/** @defgroup USBDDescriptor USB Descriptor + * @brief USB descriptor + * @{ + */ + + +/*----------------------------------------------------------------------------------------------------------*/ +/* USB Device descriptor setting */ +/*----------------------------------------------------------------------------------------------------------*/ +// USB Device descriptor setting +// USB Specification Release number (bcdUSB) +// <0x0200=> USB 2.0 +// <0x0110=> USB 1.1 +// <0x0100=> USB 1.0 +// USB Class code (assigned by the USB-IF) +// <0x00=> Use class information in the Interface Descriptors (0x00) +// <0x02=> Communications and CDC Control (CDC, 0x02) +// <0xDC=> Diagnostic Device (0xDC) +// <0xEF=> Miscellaneous (0xEF) +// <0xFF=> Vendor Specific (0xFF) +// USB Subclass code (assigned by the USB-IF) <0x0-0xFF:1> +// USB Protocol code (assigned by the USB-IF) <0x0-0xFF:1> +// USB Vendor ID <0x0-0xFFFF:1> +// USB Product ID <0x0-0xFFFF:1> +// USB Device Version <0x0-0xFFFF:1> +// USB String descriptor - Manufacturer +// USB String descriptor - Product +// USB String descriptor - Device serial number +// USB Number of possible configurations <0-255:1> +#define DESC_BCDUSB (0x0110) +#define DESC_BDEVCLASS (0x00) +#define DESC_BDEVSUBCLASS (0x00) +#define DESC_BDEVPROTOCOL (0x00) +#define DESC_IDVENDOR (0x04D9) +#define DESC_IDPRODUCT (0x8008) +#define DESC_BCDDEVICE (0x0100) +#define DESC_IMANUFACTURE (1) +#define DESC_IPRODUCT (1) +#define DESC_ISERIALNUM (1) +#define DESC_INUMCONFN (1) +// + +/*----------------------------------------------------------------------------------------------------------*/ +/* USB Device Descriptor definition. DO NOT MODIFY. */ +/*----------------------------------------------------------------------------------------------------------*/ +#if (DESC_BDEVCLASS == 0x0 & DESC_BDEVSUBCLASS != 0x0) +#error "DESC_BDEVSUBCLASS must be reset to zero when the DESC_BDEVCLASS is equal to zero." +#endif +#define DESC_WMAXPACKETSIZE0 (_EP0LEN) +#define DESC_STR_MAN (1 * DESC_IMANUFACTURE) +#define DESC_STR_PRD (2 * DESC_IPRODUCT) +#define DESC_STR_SER (3 * DESC_ISERIALNUM) +#define DESC_NUM_STRING (1 + 3) + +/*----------------------------------------------------------------------------------------------------------*/ +/* USB Device descriptor */ +/*----------------------------------------------------------------------------------------------------------*/ +__ALIGN4 static uc8 guUSB_DeviceDesc[] = +{ + /*--------------------------------------------------------------------------------------------------------*/ + /* Device descriptor */ + /*--------------------------------------------------------------------------------------------------------*/ + /* Field Size Description */ + /*----------------------------------------------------------------------------*/ + DESC_LEN_DEV, // bLength 1 Size of this descriptor in bytes + DESC_TYPE_01_DEV, // bDescriptorType 1 DEVICE Descriptor Type + DESC_H2B(DESC_BCDUSB), // bcdUSB 2 USB Specification Release Number + DESC_BDEVCLASS, // bDeviceClass 1 Class code (assigned by the USB-IF) + DESC_BDEVSUBCLASS, // bDeviceSubClass 1 Subclass code (assigned by the USB-IF) + DESC_BDEVPROTOCOL, // bDeviceProtocol 1 Protocol code (assigned by the USB-IF) + DESC_WMAXPACKETSIZE0, // wMaxPacketSize0 1 Maximum packet size for endpoint zero + DESC_H2B(DESC_IDVENDOR), // idVendor 2 Vendor ID (assigned by USB-IF) + DESC_H2B(DESC_IDPRODUCT), // idProduct 2 Product ID (assigned by manufacturer) + DESC_H2B(DESC_BCDDEVICE), // bcdDevice 2 Device release number + DESC_STR_MAN, // iManufacturer 1 Index of string descriptor (Manufacturer) + DESC_STR_PRD, // iProduct 1 Index of string descriptor (Product) + DESC_STR_SER, // iSerialNumber 1 Index of string descriptor (Serial Number) + DESC_INUMCONFN, // iNumConfigurations 1 Number of possible configuration +}; + + +/*----------------------------------------------------------------------------------------------------------*/ +/* USB Configuration descriptor setting */ +/*----------------------------------------------------------------------------------------------------------*/ +// USB Configuration descriptor setting +// Self-powered +// Bit 6 of bmAttributes +// Remote Wakeup +// Bit 5 of bmAttributes +// USB Device maximum power (mA) < 2-512:2> +#define DESC_BMATTR_SELF_POWER (0) +#define DESC_BMATTR_REMOTE_WAKEUP (1) +#define DESC_BMAXPOWER (100) +// + +/*----------------------------------------------------------------------------------------------------------*/ +/* USB Configuration Descriptor definition. DO NOT MODIFY. */ +/*----------------------------------------------------------------------------------------------------------*/ +#define DESC_BMATTRIBUTES (0x80 | (DESC_BMATTR_SELF_POWER << 6) | (DESC_BMATTR_REMOTE_WAKEUP << 5)) +#define DESC_TOTAL_LEN DESC_H2B((DESC_LEN_CONFN_T + RETARGET_DLEN)) + +/*----------------------------------------------------------------------------------------------------------*/ +/* USB Configuration Descriptor */ +/*----------------------------------------------------------------------------------------------------------*/ +__ALIGN4 static uc8 guUSB_ConfnDesc[] = +{ + /*--------------------------------------------------------------------------------------------------------*/ + /* Configuration descriptor */ + /*--------------------------------------------------------------------------------------------------------*/ + /* Field Size Description */ + /*----------------------------------------------------------------------------*/ + DESC_LEN_CONFN, // bLength 1 Size of this descriptor in bytes + DESC_TYPE_02_CONFN, // bDescriptorType 1 CONFIGURATION Descriptor Type + DESC_TOTAL_LEN, // wTotalLength 2 Total length of data returned for this configuration + 0x01 + RETARGET_INF, // bNumberInterface 1 Number of interfaces supported by this configuration + 0x01, // bConfigurationValue 1 Value to use as an argument to the SetConfiguration() + 0x00, // iConfiguration 1 Index of string descriptor describing this configuration + DESC_BMATTRIBUTES, // bmAttributes 1 Configuration characteristics + // D6: Self-powered, D5: RemoteWakeup + DESC_POWER(DESC_BMAXPOWER), // bMaxPower 1 Maximum power consumption of the USB device (2 mA units) + + /*--------------------------------------------------------------------------------------------------------*/ + /* Interface descriptor */ + /*--------------------------------------------------------------------------------------------------------*/ + /* Field Size Description */ + /*----------------------------------------------------------------------------*/ + DESC_LEN_INF, // bLength 1 Size of this descriptor in bytes + DESC_TYPE_04_INF, // bDescriptorType 1 INTERFACE Descriptor Type + 0x00, // bInterfaceNumber 1 Number of this interface (Zero-based 0) + 0x00, // bAlternateSetting 1 Value used to select this alternate setting + 2, // bNumEndpoints 1 Number of endpoints used by this interface + CLASS_INF_CLASS, // bInterfaceClass 1 Class code (assigned by USB-IF) + CLASS_INF_SUBCLASS, // bInterfaceSubClass 1 Subclass code (assigned by USB-IF) + CLASS_INF_PTCO, // bInterfaceProtocol 1 Protocol code (assigned by USB) + 0x00, // iInterface 1 Index of string descriptor describing this interface + + /*--------------------------------------------------------------------------------------------------------*/ + /* XXX descriptor */ + /*--------------------------------------------------------------------------------------------------------*/ + /* Field Size Description */ + /*----------------------------------------------------------------------------*/ + DESC_LEN_XXX, // bLength 1 Size of this descriptor in bytes + DESC_TYPE_01_XXX, // bDescriptorType 1 XXX Descriptor type + DESC_H2B(0x0110), // bcdXXX 2 XXX Specification Release Number + 0x21, // bCountryCode 1 Country code of the localized hardware + 0x01, // bNumDescriptors 1 Number of class descriptors (at least 1) + DESC_TYPE_02_XXX, // bDescriptorType 1 REPORT Descriptor Type + DESC_H2B(DESC_LEN_XXXX), // bDescriptorLength 2 Total size of the Report descriptor + + /*--------------------------------------------------------------------------------------------------------*/ + /* Endpoint */ + /*--------------------------------------------------------------------------------------------------------*/ + /* Field Size Description */ + /*----------------------------------------------------------------------------*/ + DESC_LEN_EPT, // bLength 1 Size of this descriptor in bytes + DESC_TYPE_05_EPT, // bDescriptorType 1 ENDPOINT Descriptor Type + 0x81, // bEndpointAddress 1 The address of the endpoint + // Bit 3..0: The endpoint number + // Bit 6..4: Reserved + // Bit 7 : Direction (0 = Out/1 = In) + 0x03, // bmAttribute 1 Endpoint Attribute + // Bit 1..0: Transfer type + // 00 = Control + // 01 = Isochronous + // 10 = Bulk + // 11 = Interrupt + // All other reserved + DESC_H2B(_EP1LEN), // wMaxPacketSize 2 Maximum packet size + 0x01, // bInterval 1 Interval for polling endpoint + + /*--------------------------------------------------------------------------------------------------------*/ + /* Endpoint */ + /*--------------------------------------------------------------------------------------------------------*/ + /* Field Size Description */ + /*----------------------------------------------------------------------------*/ + DESC_LEN_EPT, // bLength 1 Size of this descriptor in bytes + DESC_TYPE_05_EPT, // bDescriptorType 1 ENDPOINT Descriptor Type + 0x02, // bEndpointAddress 1 The address of the endpoint + // Bit 3..0: The endpoint number + // Bit 6..4: Reserved + // Bit 7 : Direction (0 = Out/1 = In) + 0x03, // bmAttribute 1 Endpoint Attribute + // Bit 1..0: Transfer type + // 00 = Control + // 01 = Isochronous + // 10 = Bulk + // 11 = Interrupt + // All other reserved + DESC_H2B(_EP2LEN), // wMaxPacketSize 2 Maximum packet size + 0x01, // bInterval 1 Interval for polling endpoint + + #ifdef RETARGET_IS_USB + #include "ht32_retarget_desc.h" + #endif + +}; + +/*----------------------------------------------------------------------------------------------------------*/ +/* USB String Descriptor */ +/*----------------------------------------------------------------------------------------------------------*/ +__ALIGN4 static uc8 guUSB_StringDescLANGID[] = +{ + /*--------------------------------------------------------------------------------------------------------*/ + /* LANGID (Index = 0) */ + /*--------------------------------------------------------------------------------------------------------*/ + /* Field Size Description */ + /*----------------------------------------------------------------------------*/ + DESC_STRLEN(1), // bLength 1 Size of this descriptor in bytes + DESC_TYPE_03_STR, // bDescriptorType 1 STRING Descriptor Type + DESC_H2B(0x0409), // wLANGID[0] 2 LANGID code zero +}; + +#if (DESC_IMANUFACTURE == 1) +__ALIGN4 static uc8 guUSB_StringDescManufacture[] = +{ + /*--------------------------------------------------------------------------------------------------------*/ + /* Manufacture (Index = 1) */ + /*--------------------------------------------------------------------------------------------------------*/ + /* Field Size Description */ + /*----------------------------------------------------------------------------*/ + DESC_STRLEN(6), // bLength 1 Size of this descriptor in bytes + DESC_TYPE_03_STR, // bDescriptorType 1 STRING Descriptor Type + DESC_CHAR('H'), // bString N UNICODE encoded string + DESC_CHAR('O'), + DESC_CHAR('L'), + DESC_CHAR('T'), + DESC_CHAR('E'), + DESC_CHAR('K'), +}; +#endif + +#if (DESC_IPRODUCT == 1) +__ALIGN4 static uc8 guUSB_StringDescProduct[] = +{ + /*--------------------------------------------------------------------------------------------------------*/ + /* Product (Index = 2) */ + /*--------------------------------------------------------------------------------------------------------*/ + /* Field Size Description */ + /*----------------------------------------------------------------------------*/ + DESC_STRLEN(12), // bLength 1 Size of this descriptor in bytes + DESC_TYPE_03_STR, // bDescriptorType 1 STRING Descriptor Type + DESC_CHAR('U'), // bString N UNICODE encoded string + DESC_CHAR('S'), + DESC_CHAR('B'), + DESC_CHAR('-'), + DESC_CHAR('X'), + DESC_CHAR('X'), + DESC_CHAR('X'), + DESC_CHAR(' '), + DESC_CHAR('D'), + DESC_CHAR('E'), + DESC_CHAR('M'), + DESC_CHAR('O'), +}; +#endif + + +#if (DESC_ISERIALNUM == 1) +__ALIGN4 static u8 guUSB_StringDescSerialNum[] = +{ + /*--------------------------------------------------------------------------------------------------------*/ + /* Serial Number (Index = 3) */ + /*--------------------------------------------------------------------------------------------------------*/ + /* Field Size Description */ + /*----------------------------------------------------------------------------*/ + DESC_STRLEN(12), // bLength 1 Size of this descriptor in bytes + DESC_TYPE_03_STR, // bDescriptorType 1 STRING Descriptor Type + DESC_CHAR('S'), // bString N UNICODE encoded string + DESC_CHAR('N'), + DESC_CHAR('0'), + DESC_CHAR('0'), + DESC_CHAR('0'), + DESC_CHAR('0'), + DESC_CHAR('0'), + DESC_CHAR('0'), + DESC_CHAR('0'), + DESC_CHAR('0'), + DESC_CHAR('0'), + DESC_CHAR('0'), +}; +#endif + +uc8 *gpStringDesc[DESC_NUM_STRING] = +{ + + guUSB_StringDescLANGID, + + #if (DESC_IMANUFACTURE == 1) + guUSB_StringDescManufacture, + #else + NULL, + #endif + + #if (DESC_IPRODUCT == 1) + guUSB_StringDescProduct, + #else + NULL, + #endif + + #if (DESC_ISERIALNUM == 1) + guUSB_StringDescSerialNum + #else + NULL, + #endif + +}; + +/*********************************************************************************************************//** + * @brief USB Descriptor pointer initialization. + * @param pDesc: pointer of USBDCore_Desc_TypeDef + * @retval None + ***********************************************************************************************************/ +void USBDDesc_Init(USBDCore_Desc_TypeDef *pDesc) +{ + pDesc->pDeviceDesc = guUSB_DeviceDesc; + pDesc->pConfnDesc = guUSB_ConfnDesc; + pDesc->ppStringDesc = gpStringDesc; + pDesc->uStringDescNumber = DESC_NUM_STRING; + + return; +} + + +/** + * @} + */ + +/** + * @} + */ diff --git a/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32_USBD_Library/example/ht32_usbd_descriptor.h b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32_USBD_Library/example/ht32_usbd_descriptor.h new file mode 100644 index 0000000000..1f0dee2e81 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32_USBD_Library/example/ht32_usbd_descriptor.h @@ -0,0 +1,59 @@ +/*********************************************************************************************************//** + * @file example/ht32_usbd_descriptor.h + * @version $Rev:: 5 $ + * @date $Date:: 2017-05-11 #$ + * @brief The USB descriptor. + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------------------------------------*/ +#ifndef __HT32_USBD_DESCRIPTOR_H +#define __HT32_USBD_DESCRIPTOR_H + +/* Includes ------------------------------------------------------------------------------------------------*/ + +/** @addtogroup HT32_USBD_Library HT32 USB Device Library + * @{ + */ + +/** @defgroup USBDDescriptor USB Descriptor + * @brief USB descriptor + * @{ + */ + + +/* Exported constants --------------------------------------------------------------------------------------*/ +#define DESC_LEN_CONFN_T (u16)(DESC_LEN_CONFN + DESC_LEN_INF + DESC_LEN_XXX + DESC_LEN_EPT * 2) + +/* Exported functions --------------------------------------------------------------------------------------*/ +void USBDDesc_Init(USBDCore_Desc_TypeDef *pDesc); + + +/** + * @} + */ + +/** + * @} + */ + +#endif /* __HT32_USBD_DESCRIPTOR_H -------------------------------------------------------------------------*/ diff --git a/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32_USBD_Library/example/ht32fxxxxx_usbdconf.h b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32_USBD_Library/example/ht32fxxxxx_usbdconf.h new file mode 100644 index 0000000000..73cdd54b0a --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32_USBD_Library/example/ht32fxxxxx_usbdconf.h @@ -0,0 +1,453 @@ +/*********************************************************************************************************//** + * @file example/ht32fxxxxx_usbdconf.h + * @version $Rev:: 5 $ + * @date $Date:: 2017-05-11 #$ + * @brief The configuration file of USB Device Driver. + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ +// <<< Use Configuration Wizard in Context Menu >>> + +/* Define to prevent recursive inclusion -------------------------------------------------------------------*/ +#ifndef __HT32FXXXX_USBDCONF_H +#define __HT32FXXXX_USBDCONF_H + +// Enter Low Power mode when Suspended +#define USBDCORE_ENABLE_LOW_POWER (0) +// + +#if (USBDCORE_ENABLE_LOW_POWER == 1) + #define USBDCore_LowPower() PWRCU_DeepSleep1(PWRCU_SLEEP_ENTRY_WFE) +#else + #define USBDCore_LowPower(...) +#endif + +/*----------------------------------------------------------------------------------------------------------*/ +/* USB Interrupt Enable */ +/*----------------------------------------------------------------------------------------------------------*/ +// USB Interrupt Setting (UIER) +// USB Global Interrupt Enable (UGIE) (Default) +// Start Of Frame Interrupt Enable (SOFIE) +// USB Reset Interrupt Enable (URSTIE) (Default) +// Resume Interrupt Enable (RSMIE) (Default) +// Suspend Interrupt Enable (SUSPIE) (Default) +// Expected Start of Frame Interrupt Enable (ESOFE) +// Control Endpoint Interrupt Enable (EP0IE) (Default) +// Endpoint1 Interrupt Enable (EP1IE) +// Endpoint2 Interrupt Enable (EP2IE) +// Endpoint3 Interrupt Enable (EP3IE) +// Endpoint4 Interrupt Enable (EP4IE) +// Endpoint5 Interrupt Enable (EP5IE) +// Endpoint6 Interrupt Enable (EP6IE) +// Endpoint7 Interrupt Enable (EP7IE) +#define _UIER (0x071D) +// + + +/*----------------------------------------------------------------------------------------------------------*/ +/* Endpoint0 Configuration Setting */ +/*----------------------------------------------------------------------------------------------------------*/ +// Control Endpoint0 Configuration +// Endpoint Buffer Length (EPLEN) +// <8=> 8 bytes +// <16=> 16 bytes +// <32=> 32 bytes +// <64=> 64 bytes + /* Maximum: 64 Bytes */ +#define _EP0LEN (64) + + +// Control Endpoint0 Interrupt Enable Settings (EP0IER) +// OUT Token Packet Received Interrupt Enable (OTRXIE) +// OUT Data Packet Received Interrupt Enable (ODRXIE) (Default) +// OUT Data Buffer Overrun Interrupt Enable (ODOVIE) +// IN Token Packet Received Interrupt Enable (ITRXIE) +// IN Data Packet Transmitted Interrupt Enable (IDTXIE) (Default) +// NAK Transmitted Interrupt Enable (NAKIE) +// STALL Transmitted Interrupt Enable (STLIE) +// USB Error Interrupt Enable (UERIE) +// SETUP Token Packet Received Interrupt Enable (STRXIE) +// SETUP Data Packet Received Interrupt Enable (SDRXIE) (Default) +// SETUP Data Error Interrupt Enable (SDERIE) +// Zero Length Data Packet Received Interrupt Enable (ZLRXIE) +#define _EP0_IER (0x212) +// +// + +/*----------------------------------------------------------------------------------------------------------*/ +/* Endpoint1 Configuration Setting */ +/*----------------------------------------------------------------------------------------------------------*/ +// Endpoint1 Configuration +#define _EP1_ENABLE (1) + +// Endpoint Address (EPADR) +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 +#define _EP1_CFG_EPADR (1) + +// Endpoint Enable (EPEN) +#define _EP1_CFG_EPEN_TMP (1) + +// Endpoint Transfer Type +// <2=> Bulk +// <3=> Interrupt +#define _EP1_TYPR (3) + +// Endpoint Direction (EPDIR) +// <1=> IN +// <0=> OUT +#define _EP1_CFG_EPDIR (1) + +// Endpoint Buffer Length (EPLEN) (in byte) <4-64:4> + /* Maximum: 64 Bytes */ +#define _EP1LEN_TMP (64) + +// Endpoint Interrupt Enable Settings (EPIER) +// Endpoint Interrupt Enable Settings (EPIER) <0x0-0xFF:1> +// OUT Token Packet Received Interrupt Enable (OTRXIE) +// OUT Data Packet Received Interrupt Enable (ODRXIE) +// OUT Data Buffer Overrun Interrupt Enable (ODOVIE) +// IN Token Packet Received Interrupt Enable (ITRXIE) +// IN Data Packet Transmitted Interrupt Enable (IDTXIE) +// NAK Transmitted Interrupt Enable (NAKIE) +// STALL Transmitted Interrupt Enable (STLIE) +// USB Error Interrupt Enable (UERIE) +#define _EP1_IER (0x10) +// +// + + +/*----------------------------------------------------------------------------------------------------------*/ +/* Endpoint2 Configuration Setting */ +/*----------------------------------------------------------------------------------------------------------*/ +// Endpoint2 Configuration +#define _EP2_ENABLE (1) + +// Endpoint Address (EPADR) +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 +#define _EP2_CFG_EPADR (2) + +// Endpoint Enable (EPEN) +#define _EP2_CFG_EPEN_TMP (1) + +// Endpoint Transfer Type +// <2=> Bulk +// <3=> Interrupt +#define _EP2_TYPR (3) + +// Endpoint Direction (EPDIR) +// <1=> IN +// <0=> OUT +#define _EP2_CFG_EPDIR (0) + +// Endpoint Buffer Length (EPLEN) (in byte) <4-64:4> + /* Maximum: 64 Bytes */ +#define _EP2LEN_TMP (64) + +// Endpoint Interrupt Enable Settings (EPIER) +// Endpoint Interrupt Enable Settings (EPIER) <0x0-0xFF:1> +// OUT Token Packet Received Interrupt Enable (OTRXIE) +// OUT Data Packet Received Interrupt Enable (ODRXIE) +// OUT Data Buffer Overrun Interrupt Enable (ODOVIE) +// IN Token Packet Received Interrupt Enable (ITRXIE) +// IN Data Packet Transmitted Interrupt Enable (IDTXIE) +// NAK Transmitted Interrupt Enable (NAKIE) +// STALL Transmitted Interrupt Enable (STLIE) +// USB Error Interrupt Enable (UERIE) +#define _EP2_IER (0x002) +// +// + +/*----------------------------------------------------------------------------------------------------------*/ +/* Endpoint3 Configuration Setting */ +/*----------------------------------------------------------------------------------------------------------*/ +// Endpoint3 Configuration +#define _EP3_ENABLE (0) + +// Endpoint Address (EPADR) +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 +#define _EP3_CFG_EPADR (3) + +// Endpoint Enable (EPEN) +#define _EP3_CFG_EPEN_TMP (1) + +// Endpoint Transfer Type +// <2=> Bulk +// <3=> Interrupt +#define _EP3_TYPR (3) + +// Endpoint Direction (EPDIR) +// <1=> IN +// <0=> OUT +#define _EP3_CFG_EPDIR (1) + +// Endpoint Buffer Length (EPLEN) (in byte) <4-64:4> + /* Maximum: 64 Bytes */ +#define _EP3LEN_TMP (8) + +// Endpoint Interrupt Enable Settings (EPIER) +// Endpoint Interrupt Enable Settings (EPIER) <0x0-0xFF:1> +// OUT Token Packet Received Interrupt Enable (OTRXIE) +// OUT Data Packet Received Interrupt Enable (ODRXIE) +// OUT Data Buffer Overrun Interrupt Enable (ODOVIE) +// IN Token Packet Received Interrupt Enable (ITRXIE) +// IN Data Packet Transmitted Interrupt Enable (IDTXIE) +// NAK Transmitted Interrupt Enable (NAKIE) +// STALL Transmitted Interrupt Enable (STLIE) +// USB Error Interrupt Enable (UERIE) +#define _EP3_IER (0x10) +// +// + +/*----------------------------------------------------------------------------------------------------------*/ +/* Endpoint4 Configuration Setting */ +/*----------------------------------------------------------------------------------------------------------*/ +// Endpoint4 Configuration +#define _EP4_ENABLE (0) + +// Endpoint Address (EPADR) +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 +#define _EP4_CFG_EPADR (4) + +// Endpoint Enable (EPEN) +#define _EP4_CFG_EPEN_TMP (1) + +// Endpoint Transfer Type +// <1=> Isochronous +// <2=> Bulk +// <3=> Interrupt +#define _EP4_TYPR (3) + +// Endpoint Direction (EPDIR) +// <1=> IN +// <0=> OUT +#define _EP4_CFG_EPDIR (0) + +// Endpoint Buffer Length (EPLEN) (in byte) <4-1000:4> + /* Maximum: 1000 Bytes */ +#define _EP4LEN_TMP (8) + +// Single/Double Buffer Selection (SDBS) +// <0=> Single Buffer +// <1=> Double Buffer +#define _EP4_CFG_SDBS (0) + +// Endpoint Interrupt Enable Settings (EPIER) +// Endpoint Interrupt Enable Settings (EPIER) <0x0-0xFF:1> +// OUT Token Packet Received Interrupt Enable (OTRXIE) +// OUT Data Packet Received Interrupt Enable (ODRXIE) +// OUT Data Buffer Overrun Interrupt Enable (ODOVIE) +// IN Token Packet Received Interrupt Enable (ITRXIE) +// IN Data Packet Transmitted Interrupt Enable (IDTXIE) +// NAK Transmitted Interrupt Enable (NAKIE) +// STALL Transmitted Interrupt Enable (STLIE) +// USB Error Interrupt Enable (UERIE) +#define _EP4_IER (0x02) +// +// + + +/*----------------------------------------------------------------------------------------------------------*/ +/* Endpoint5 Configuration Setting */ +/*----------------------------------------------------------------------------------------------------------*/ +// Endpoint5 Configuration +#define _EP5_ENABLE (0) + +// Endpoint Address (EPADR) +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 +#define _EP5_CFG_EPADR (5) + +// Endpoint Enable (EPEN) +#define _EP5_CFG_EPEN_TMP (1) + +// Endpoint Transfer Type +// <1=> Isochronous +// <2=> Bulk +// <3=> Interrupt +#define _EP5_TYPR (3) + +// Endpoint Direction (EPDIR) +// <1=> IN +// <0=> OUT +#define _EP5_CFG_EPDIR (1) + +// Endpoint Buffer Length (EPLEN) (in byte) <4-1000:4> + /* Maximum: 1000 Bytes */ +#define _EP5LEN_TMP (8) + + +// Single/Double Buffer Selection (SDBS) +// <0=> Single Buffer +// <1=> Double Buffer +#define _EP5_CFG_SDBS (0) + +// Endpoint Interrupt Enable Settings (EPIER) +// Endpoint Interrupt Enable Settings (EPIER) <0x0-0xFF:1> +// OUT Token Packet Received Interrupt Enable (OTRXIE) +// OUT Data Packet Received Interrupt Enable (ODRXIE) +// OUT Data Buffer Overrun Interrupt Enable (ODOVIE) +// IN Token Packet Received Interrupt Enable (ITRXIE) +// IN Data Packet Transmitted Interrupt Enable (IDTXIE) +// NAK Transmitted Interrupt Enable (NAKIE) +// STALL Transmitted Interrupt Enable (STLIE) +// USB Error Interrupt Enable (UERIE) +#define _EP5_IER (0x10) +// +// + + +/*----------------------------------------------------------------------------------------------------------*/ +/* Endpoint6 Configuration Setting */ +/*----------------------------------------------------------------------------------------------------------*/ +// Endpoint6 Configuration +#define _EP6_ENABLE (0) + +// Endpoint Address (EPADR) +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 +#define _EP6_CFG_EPADR (6) + +// Endpoint Enable (EPEN) +#define _EP6_CFG_EPEN_TMP (1) + +// Endpoint Transfer Type +// <1=> Isochronous +// <2=> Bulk +// <3=> Interrupt +#define _EP6_TYPR (3) + +// Endpoint Direction (EPDIR) +// <1=> IN +// <0=> OUT +#define _EP6_CFG_EPDIR (0) + +// Endpoint Buffer Length (EPLEN) (in byte) <4-1000:4> + /* Maximum: 1000 Bytes */ +#define _EP6LEN_TMP (8) + +// Single/Double Buffer Selection (SDBS) +// <0=> Single Buffer +// <1=> Double Buffer +#define _EP6_CFG_SDBS (0) + +// Endpoint Interrupt Enable Settings (EPIER) +// Endpoint Interrupt Enable Settings (EPIER) <0x0-0xFF:1> +// OUT Token Packet Received Interrupt Enable (OTRXIE) +// OUT Data Packet Received Interrupt Enable (ODRXIE) +// OUT Data Buffer Overrun Interrupt Enable (ODOVIE) +// IN Token Packet Received Interrupt Enable (ITRXIE) +// IN Data Packet Transmitted Interrupt Enable (IDTXIE) +// NAK Transmitted Interrupt Enable (NAKIE) +// STALL Transmitted Interrupt Enable (STLIE) +// USB Error Interrupt Enable (UERIE) +#define _EP6_IER (0x02) +// +// + + +/*----------------------------------------------------------------------------------------------------------*/ +/* Endpoint7 Configuration Setting */ +/*----------------------------------------------------------------------------------------------------------*/ +// Endpoint7 Configuration +#define _EP7_ENABLE (0) + +// Endpoint Address (EPADR) +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 +#define _EP7_CFG_EPADR (7) + +// Endpoint Enable (EPEN) +#define _EP7_CFG_EPEN_TMP (1) + +// Endpoint Transfer Type +// <1=> Isochronous +// <2=> Bulk +// <3=> Interrupt +#define _EP7_TYPR (3) + +// Endpoint Direction (EPDIR) +// <1=> IN +// <0=> OUT +#define _EP7_CFG_EPDIR (1) + +// Endpoint Buffer Length (EPLEN) (in byte) <4-1000:4> + /* Maximum: 1000 Bytes */ +#define _EP7LEN_TMP (8) + +// Single/Double Buffer Selection (SDBS) +// <0=> Single Buffer +// <1=> Double Buffer +#define _EP7_CFG_SDBS (0) + +// Endpoint Interrupt Enable Settings (EPIER) +// Endpoint Interrupt Enable Settings (EPIER) <0x0-0xFF:1> +// OUT Token Packet Received Interrupt Enable (OTRXIE) +// OUT Data Packet Received Interrupt Enable (ODRXIE) +// OUT Data Buffer Overrun Interrupt Enable (ODOVIE) +// IN Token Packet Received Interrupt Enable (ITRXIE) +// IN Data Packet Transmitted Interrupt Enable (IDTXIE) +// NAK Transmitted Interrupt Enable (NAKIE) +// STALL Transmitted Interrupt Enable (STLIE) +// USB Error Interrupt Enable (UERIE) +#define _EP7_IER (0x10) +// +// + +#endif diff --git a/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32_USBD_Library/inc/ht32_usbd_core.h b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32_USBD_Library/inc/ht32_usbd_core.h new file mode 100644 index 0000000000..a30f749d10 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32_USBD_Library/inc/ht32_usbd_core.h @@ -0,0 +1,435 @@ +/*********************************************************************************************************//** + * @file ht32_usbd_core.h + * @version $Rev:: 2555 $ + * @date $Date:: 2022-03-15 #$ + * @brief The header file of standard protocol related function for HT32 USB Device Library. + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ +// <<< Use Configuration Wizard in Context Menu >>> + +/* Define to prevent recursive inclusion -------------------------------------------------------------------*/ +#ifndef __HT32_USBD_CORE_H +#define __HT32_USBD_CORE_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------------------------------------*/ + +/** @addtogroup HT32_USBD_Library + * @{ + */ + +/** @addtogroup USBDCore + * @{ + */ + + +/* Settings ------------------------------------------------------------------------------------------------*/ +/** @defgroup USBDCore_Settings USB Device Core settings + * @{ + */ +/* USBD Debug mode */ +// Enable USB Debug mode +// Dump USB Debug data +#ifndef USBDCORE_DEBUG + #define USBDCORE_DEBUG (0) /*!< Enable USB Debug mode */ + #define USBDCORE_DEBUG_DATA (0) /*!< Dump USB Debug data */ +#endif +/** + * @} + */ + +/* Exported types ------------------------------------------------------------------------------------------*/ +/** @defgroup USBDCore_Exported_Type USB Device Core exported types + * @{ + */ +/** + * @brief USB Device Request. + */ +typedef __PACKED_H struct +{ + uc8 bmRequestType; + uc8 bRequest; + uc8 wValueL; + uc8 wValueH; + uc16 wIndex; + uc16 wLength; +} __PACKED_F USBDCore_Request_TypeDef; + +/** + * @brief USB Descriptor. + */ +typedef struct +{ + uc8 *pDeviceDesc; /*!< Device Descriptor */ + uc8 *pConfnDesc; /*!< Configuration Descriptor */ + uc8 **ppStringDesc; /*!< String Descriptor */ + u32 uStringDescNumber; /*!< Count of String Descriptor */ +} USBDCore_Desc_TypeDef; + +/** + * @brief STALL, control IN or control OUT. + */ +typedef enum +{ + USB_ACTION_STALL = 0, + USB_ACTION_DATAIN = 1, + USB_ACTION_DATAOUT = 2, +} USBDCore_Action_Enum; + +/** + * @brief Call back function. + */ +typedef struct +{ + void (*func) (u32 uPara); /*!< Call back function pointer */ + u32 uPara; /*!< Parameter of call back function */ +} USBDCore_CallBack_TypeDef; + +/** + * @brief Parameter for control IN/OUT Transfer. + */ +typedef struct +{ + u8 uBuffer[2]; /*!< Temporary buffer */ + uc8 *pData; /*!< Pointer of control IN/OUT Data */ + s32 sByteLength; /*!< Total length for control IN/OUT Transfer */ + USBDCore_Action_Enum Action; /*!< STALL, control IN or control OUT */ + USBDCore_CallBack_TypeDef CallBack_OUT; /*!< Call back function pointer for Control OUT */ +} USBDCore_Transfer_TypeDef; + +/** + * @brief USB Device. + */ +typedef struct +{ + USBDCore_Request_TypeDef Request; /*!< USB Device Request */ + USBDCore_Desc_TypeDef Desc; /*!< USB Descriptor */ + USBDCore_Transfer_TypeDef Transfer; /*!< Parameter for control IN/OUT Transfer */ +} USBDCore_Device_TypeDef; + +/** + * @brief Bit access for CurrentFeature. + */ +typedef __PACKED_H struct _FEATURE_TYPEBIT +{ + unsigned bSelfPowered :1; /*!< Remote Wakeup feature */ + unsigned bRemoteWakeup :1; /*!< Self Powered */ +} __PACKED_F USBDCore_Feature_TypeBit; + +/** + * @brief For Set/ClearFeature and GetStatus request. + */ +typedef __PACKED_H union _FEATURE_TYPEDEF +{ + u8 uByte; /*!< Byte access for CurrentFeature */ + USBDCore_Feature_TypeBit Bits; /*!< Bit access for CurrentFeature */ +} __PACKED_F USBDCore_Feature_TypeDef; + +/** + * @brief Device State. + */ +typedef enum +{ + USB_STATE_UNCONNECTED = 0, + USB_STATE_ATTACHED = 1, + USB_STATE_POWERED = 2, + USB_STATE_SUSPENDED = 3, + USB_STATE_DEFAULT = 4, + USB_STATE_ADDRESS = 5, + USB_STATE_CONFIGURED = 6, +} USBDCore_Status_Enum; + +/** + * @brief USB Device information. + */ +typedef struct +{ + u8 uCurrentConfiguration; /*!< For Set/GetConfiguration request */ + u8 uCurrentInterface; /*!< For Set/GetInterface request */ + volatile USBDCore_Status_Enum CurrentStatus; /*!< Device State */ + USBDCore_Status_Enum LastStatus; /*!< Device State before SUSPEND */ + USBDCore_Feature_TypeDef CurrentFeature; /*!< For Set/ClearFeature and GetStatus request */ + u32 uIsDiscardClearFeature; /*!< Discard ClearFeature flag for Mass Storage */ +} USBDCore_Info_TypeDef; + +typedef void (*USBDCore_CallBackClass_Typedef) (USBDCore_Device_TypeDef *pDev); +typedef void (*USBDCore_CallBackVendor_Typedef) (USBDCore_Device_TypeDef *pDev); +typedef void (*USBDCore_CallBackEPTn_Typedef) (USBD_EPTn_Enum EPTn); + +/** + * @brief USB Class call back function. + */ +typedef struct +{ + USBDCore_CallBack_TypeDef CallBack_MainRoutine; /*!< Class main routine call back function */ + USBDCore_CallBack_TypeDef CallBack_Reset; /*!< Class RESET call back function */ + USBDCore_CallBack_TypeDef CallBack_StartOfFrame; /*!< Class SOF call back function */ + USBDCore_CallBackClass_Typedef CallBack_ClassGetDescriptor; /*!< Class Get Descriptor call back function */ + USBDCore_CallBackClass_Typedef CallBack_ClassSetInterface; /*!< Set Interface call back function */ + USBDCore_CallBackClass_Typedef CallBack_ClassGetInterface; /*!< Get Interface call back function */ + USBDCore_CallBackClass_Typedef CallBack_ClassRequest; /*!< Class Request call back function */ + USBDCore_CallBackVendor_Typedef CallBack_VendorRequest; /*!< Vendor Request call back function */ + USBDCore_CallBackEPTn_Typedef CallBack_EPTn[MAX_EP_NUM]; /*!< Endpoint n call back function */ +} USBDCore_Class_TypeDef; + +/** + * @brief USB Device Power related call back function. + */ +typedef struct +{ + USBDCore_CallBack_TypeDef CallBack_Suspend; +} USBDCore_Power_TypeDef; + +/** + * @brief Major structure of USB Library. + */ +typedef struct +{ + USBDCore_Device_TypeDef Device; /*!< USB Device */ + USBDCore_Info_TypeDef Info; /*!< USB Device information */ + USBDCore_Class_TypeDef Class; /*!< USB Class call back function */ + u32 *pDriver; /*!< USB Device Driver initialization structure */ + USBDCore_Power_TypeDef Power; /*!< USB Device Power related call back function */ +} USBDCore_TypeDef; + +/*----------------------------------------------------------------------------------------------------------*/ +/* Variable architecture of USB Library */ +/*----------------------------------------------------------------------------------------------------------*/ +/* USBCore - USBDCore_TypeDef Major structure of USB Library */ +/* USBCore.Device - USBDCore_Device_TypeDef USB Device */ +/* USBCore.Device.Request - USBDCore_Request_TypeDef USB Device Request */ +/* USBCore.Device.Request.bmRequestType */ +/* USBCore.Device.Request.bRequest */ +/* USBCore.Device.Request.wValueL */ +/* USBCore.Device.Request.wValueH */ +/* USBCore.Device.Request.wIndex */ +/* USBCore.Device.Request.wLength */ +/* USBCore.Device.Desc - USBDCore_Desc_TypeDef USB Descriptor */ +/* USBCore.Device.Desc.pDeviceDesc Device Descriptor */ +/* USBCore.Device.Desc.pConfnDesc Configuration Descriptor */ +/* USBCore.Device.Desc.pStringDesc[DESC_NUM_STRING] String Descriptor */ +/* USBCore.Device.Desc.uStringDescNumber Count of String Descriptor */ +/* USBCore.Device.Transfer - USBDCore_Transfer_TypeDef Parameter for control IN/OUT Transfer */ +/* USBCore.Device.Transfer.uBuffer[2] Temporary buffer */ +/* USBCore.Device.Transfer.pData Pointer of control IN/OUT Data */ +/* USBCore.Device.Transfer.sByteLength Total length for control IN/OUT Transfer */ +/* USBCore.Device.Transfer.Action - USBDCore_Action_Enum STALL, control IN or control OUT */ +/* USBCore.Device.Transfer.CallBack_OUT.func(uPara) Call back function pointer for Control OUT */ +/* USBCore.Device.Transfer.CallBack_OUT.uPara Parameter of Control OUT call back function */ +/* */ +/* USBCore.Info - USBDCore_Info_TypeDef USB Device information */ +/* USBCore.Info.uCurrentConfiguration For Set/GetConfiguration request */ +/* USBCore.Info.uCurrentInterface For Set/GetInterface request */ +/* USBCore.Info.CurrentStatus - USBDCore_Status_Enum Device State */ +/* USBCore.Info.LastStatus - USBDCore_Status_Enum Device State before SUSPEND */ +/* USBCore.Info.CurrentFeature - USBDCore_Feature_TypeDef For Set/ClearFeature and GetStatus request */ +/* USBCore.Info.CurrentFeature.uByte Byte access for CurrentFeature */ +/* USBCore.Info.CurrentFeature.Bits.bRemoteWakeup Remote Wakeup feature */ +/* USBCore.Info.CurrentFeature.Bits.bSelfPowered Self Powered */ +/* USBCore.Info.uIsDiscardClearFeature Discard ClearFeature flag for Mass Storage */ +/* */ +/* USBCore.Class - USBDCore_Class_TypeDef USB Class call back function */ +/* USBCore.Class.CallBack_MainRoutine.func(uPara) Class main routine call back function */ +/* USBCore.Class.CallBack_MainRoutine.uPara Parameter of class main routine */ +/* USBCore.Class.CallBack_Reset.func(uPara) Class RESET call back function */ +/* USBCore.Class.CallBack_Reset.uPara Parameter of RESET call back function */ +/* USBCore.Class.CallBack_StartOfFrame.func(uPara) Class SOF call back function */ +/* USBCore.Class.CallBack_StartOfFrame.uPara Parameter of SOF call back function */ +/* USBCore.Class.CallBack_ClassGetDescriptor(pDev) Class Get Descriptor call back function */ +/* USBCore.Class.CallBack_ClassSetInterface(pDev) Set Interface call back function */ +/* USBCore.Class.CallBack_ClassGetInterface(pDev) Get Interface call back function */ +/* USBCore.Class.CallBack_ClassRequest(pDev) Class Request call back function */ +/* USBCore.Class.CallBack_EPTn[MAX_EP_NUM](EPTn) Endpoint n call back function */ +/* */ +/* USBCore.pDriver USB Device Driver initialization structure */ +/* */ +/* USBCore.Power - USBDCore_Power_TypeDef USB Device Power related call back function */ +/* USBCore.Power.CallBack_Suspend.func(uPara) System low power function for SUSPEND */ +/* USBCore.Power.CallBack_Suspend.uPara Parameter of system low power function */ +/*----------------------------------------------------------------------------------------------------------*/ + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------------------------------------*/ +/** @defgroup USBDCore_Exported_Constant USB Device Core exported constants + * @{ + */ + +/** @defgroup USBDCore_Descriptor Definitions for USB descriptor + * @{ + */ +#define DESC_TYPE_01_DEV (0x1) +#define DESC_TYPE_02_CONFN (0x2) +#define DESC_TYPE_03_STR (0x3) +#define DESC_TYPE_04_INF (0x4) +#define DESC_TYPE_05_EPT (0x5) +#define DESC_TYPE_06_DEV_QLF (0x6) +#define DESC_TYPE_08_INF_PWR (0x8) + +#define DESC_CLASS_00_BY_INF (0x00) +#define DESC_CLASS_01_AUDIO (0x01) +#define DESC_CLASS_02_CDC_CTRL (0x02) +#define DESC_CLASS_03_HID (0x03) +#define DESC_CLASS_05_PHY (0x05) +#define DESC_CLASS_06_STILL_IMG (0x06) +#define DESC_CLASS_07_PRINTER (0x07) +#define DESC_CLASS_08_MASS_STORAGE (0x08) +#define DESC_CLASS_09_HUB (0x09) +#define DESC_CLASS_0A_CDC_DATA (0x0A) +#define DESC_CLASS_0B_SMART_CARD (0x0B) +#define DESC_CLASS_0E_VIDEO (0x0E) +#define DESC_CLASS_0F_PHD (0x0F) +#define DESC_CLASS_FF_VENDOR (0xFF) + +#define DESC_LEN_DEV ((u32)(18)) +#define DESC_LEN_CONFN ((u32)(9)) +#define DESC_LEN_INF ((u32)(9)) +#define DESC_LEN_EPT ((u32)(7)) +/** + * @} + */ + +/** @defgroup USBDCore_Request Definitions for USB Request + * @{ + */ +#define REQ_DIR_00_H2D (0 << 7) +#define REQ_DIR_01_D2H (1 << 7) + +#define REQ_TYPE_00_STD (0 << 5) +#define REQ_TYPE_01_CLS (1 << 5) +#define REQ_TYPE_02_VND (2 << 5) + +#define REQ_REC_00_DEV (0) +#define REQ_REC_01_INF (1) +#define REQ_REC_02_EPT (2) +/** + * @} + */ + +/** + * @brief For USBDCore_EPTReadOUTData function. + */ +#define USB_DISCARD_OUT_DATA (0) + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------------------------------------*/ +/** @defgroup USBDCore_Exported_Macro USB Device Core exported macros + * @{ + */ +#define __DBG_USBPrintf(...) +#define __DBG_USBDump(a, b) + +#if (USBDCORE_DEBUG == 1) + #ifndef RETARGET_IS_USB + extern u32 __DBG_USBCount; + #undef __DBG_USBPrintf + #define __DBG_USBPrintf printf + #if (USBDCORE_DEBUG_DATA == 1) + #undef __DBG_USBDump + void __DBG_USBDump(uc8 *memory, u32 len); + #endif + #endif +#endif + +/** + * @brief Convert Half-Word to Byte for descriptor. + */ +#define DESC_H2B(Val) ((u8)(Val & 0x00FF)), ((u8)((Val & 0xFF00) >> 8)) + +/** + * @brief Padding 0 automatically for String descriptor. + */ +#define DESC_CHAR(c) (c), (0) + +/** + * @brief Calculate String length for String descriptor. + */ +#define DESC_STRLEN(n) (n * 2 + 2) + +/** + * @brief Calculate power for Configuration descriptor. + */ +#define DESC_POWER(mA) (mA / 2) +/** + * @} + */ + +/* Exported functions --------------------------------------------------------------------------------------*/ +/** @defgroup USBDCore_Exported_Functions USB Device Core exported functions + * @{ + */ +#define USBDCore_DeInit API_USB_DEINIT +#define USBDCore_EPTReset API_USB_EPTn_RESET +#define USBDCore_EPTGetBufferLen API_USB_EPTn_GET_BUFFLEN +#define USBDCore_EPTGetTransferCount API_USB_EPTn_GET_CNT +#define USBDCore_EPTSetSTALL API_USB_EPTn_SET_HALT +#define USBDCore_EPTWaitSTALLSent API_USB_EPTn_WAIT_STALL_SENT +#define USBDCore_EPTClearDataToggle API_USB_EPTn_CLR_DTG + +#define USBDCore_EPTWriteINData API_USB_EPTn_WRITE_IN +#define USBDCore_EPTReadOUTData API_USB_EPTn_READ_OUT +#define USBDCore_EPTReadMemory API_USB_EPTn_READ_MEM + +void USBDCore_Init(USBDCore_TypeDef *pCore); +void USBDCore_IRQHandler(USBDCore_TypeDef *pCore); +void USBDCore_MainRoutine(USBDCore_TypeDef *pCore); +u32 USBDCore_IsSuspend(USBDCore_TypeDef *pCore); +u32 USBDCore_GetRemoteWakeUpFeature(USBDCore_TypeDef *pCore); +void USBDCore_TriggerRemoteWakeup(void); +USBDCore_Status_Enum USBDCore_GetStatus(void); + +void USBDCore_EPTReset(USBD_EPTn_Enum USBD_EPTn); +u32 USBDCore_EPTGetBufferLen(USBD_EPTn_Enum USBD_EPTn); +u32 USBDCore_EPTGetTransferCount(USBD_EPTn_Enum USBD_EPTn, USBD_TCR_Enum type); +void USBDCore_EPTSetSTALL(USBD_EPTn_Enum USBD_EPTn); +void USBDCore_EPTWaitSTALLSent(USBD_EPTn_Enum USBD_EPTn); +void USBDCore_EPTClearDataToggle(USBD_EPTn_Enum USBD_EPTn); + +u32 USBDCore_EPTWriteINData(USBD_EPTn_Enum USBD_EPTn, u32 *pFrom, u32 len); +u32 USBDCore_EPTReadOUTData(USBD_EPTn_Enum USBD_EPTn, u32 *pTo, u32 len); +u32 USBDCore_EPTReadMemory(USBD_EPTn_Enum USBD_EPTn, u32 *pTo, u32 len); +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __HT32_USBD_CORE_H -------------------------------------------------------------------------------*/ diff --git a/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32_USBD_Library/src/ht32_usbd_core.c b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32_USBD_Library/src/ht32_usbd_core.c new file mode 100644 index 0000000000..0a7bc4c20c --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32_USBD_Library/src/ht32_usbd_core.c @@ -0,0 +1,1037 @@ +/*********************************************************************************************************//** + * @file ht32_usbd_core.c + * @version $Rev:: 1684 $ + * @date $Date:: 2019-05-07 #$ + * @brief The standard protocol related function of HT32 USB Device Library. + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ + +/* Includes ------------------------------------------------------------------------------------------------*/ +#include "ht32.h" +#include "ht32_usbd_core.h" + +#ifdef USBD_VENDOR_SUPPORT +#include "ht32_usbd_vendor.c" +#endif + +/** @addtogroup HT32_USBD_Library HT32 USB Device Library + * @{ + */ + +/** @defgroup USBDCore USB Device Core + * @brief USB Device Core standard protocol related function + * @{ + */ + + +/* Private types -------------------------------------------------------------------------------------------*/ +/** @defgroup USBDCore_Private_TypesDefinitions USB Device Core private types definitions + * @{ + */ +typedef enum +{ + Device = 0, + Interface = 1, + Endpoint = 2, + Other = 3, +} USBDCore_Recipient_Enum; + +typedef enum +{ + ClearFeature = 0, + SetFeature = 1, +} USBDCore_SetClearFeature_Enum; +/** + * @} + */ + +/* Private constants ---------------------------------------------------------------------------------------*/ +/** @defgroup USBDCore_Private_Define USB Device Core private definitions + * @{ + */ +/* USBD Debug mode */ +#if (USBDCORE_DEBUG == 1) + #ifdef RETARGET_IS_USB + #warning "USB debug mode can not work when retaget to USB Virtual COM. Turn off automatically." + #undef USBDCORE_DEBUG + #define USBDCORE_DEBUG 0 + #else + u32 __DBG_USBCount; + #warning "USB debug mode has been enabled which degrade the performance." + #warning "After the debug operation, please remember to turn off USB debug mode." + #endif +#endif + +/** @defgroup USBDCore_STD Definition for standard request + * @{ + */ +#define REQ_00_GET_STAT ((u16)(0 << 8)) +#define REQ_01_CLR_FETU ((u16)(1 << 8)) +#define REQ_03_SET_FETU ((u16)(3 << 8)) +#define REQ_05_SET_ADDR ((u16)(5 << 8)) +#define REQ_06_GET_DESC ((u16)(6 << 8)) +#define REQ_07_SET_DESC ((u16)(7 << 8)) +#define REQ_08_GET_CONF ((u16)(8 << 8)) +#define REQ_09_SET_CONF ((u16)(9 << 8)) +#define REQ_10_GET_INF ((u16)(10 << 8)) +#define REQ_11_SET_INF ((u16)(11 << 8)) +#define REQ_12_SYN_FRME ((u16)(12 << 8)) +/** + * @} + */ + +#define DESC_TYPE_01_DEV (0x1) +#define DESC_TYPE_02_CONFN (0x2) +#define DESC_TYPE_03_STR (0x3) +#define USB_NO_DATA (-1) /*!< For Device.Transfer.sByteLength */ +#define BMREQUEST_TYPE_MASK (0x6 << 4) /*!< bmRequestType[6:5] */ +#define USB_FEATURE_REMOTE_WAKEUP (1) + +#define MAX_CONTROL_OUT_SIZE (64) +/** + * @} + */ + +/* Private function prototypes -----------------------------------------------------------------------------*/ +static void _USBDCore_PowerHandler(USBDCore_TypeDef *pCore); +static void _USBDCore_Reset(USBDCore_TypeDef *pCore); +static void _USBDCore_Resume(USBDCore_TypeDef *pCore); +static void _USBDCore_Suspend(USBDCore_TypeDef *pCore); +static void _USBDCore_Setup(USBDCore_TypeDef *pCore); +static void _USBDCore_Standard_Request(USBDCore_TypeDef *pCore); +static void _USBDCore_Standard_GetStatus(USBDCore_TypeDef *pCore, USBDCore_Recipient_Enum recipient); +static void _USBDCore_Standard_SetClearFeature(USBDCore_TypeDef *pCore, USBDCore_Recipient_Enum recipient, USBDCore_SetClearFeature_Enum type); +static void _USBDCore_Standard_SetAddress(USBDCore_TypeDef *pCore); +static void _USBDCore_Standard_GetDescriptor(USBDCore_TypeDef *pCore); +static void _USBDCore_Standard_GetConfiguration(USBDCore_TypeDef *pCore); +static void _USBDCore_Standard_SetConfiguration(USBDCore_TypeDef *pCore); +static void _USBDCore_ControlIN(USBDCore_TypeDef *pCore); +static void _USBDCore_ControlOUT(USBDCore_TypeDef *pCore); + +/* Private macro -------------------------------------------------------------------------------------------*/ +/** @defgroup USBDCore_Private_Macro USB Device Core private macros + * @{ + */ +/** + * @brief Get self powered bit from Device descriptor + */ +#define _GET_SELFPOWERED_FROM_DESC() (((pCore->Device.Desc.pConfnDesc[7]) >> 6) & 0x01) +/** + * @} + */ + +/* Private variables ---------------------------------------------------------------------------------------*/ +/** @defgroup USBDCore_Private_Variable USB Device Core private variables + * @{ + */ +USBDCore_TypeDef *pUSBCore; +/** + * @} + */ + + +/* Global Function -----------------------------------------------------------------------------------------*/ +/** @defgroup USBDCore_Exported_Functions USB Device Core exported functions + * @{ + */ +/*********************************************************************************************************//** + * @brief USB Core initialization. + * @param pCore: pointer of USB Device + * @retval None + ***********************************************************************************************************/ +void USBDCore_Init(USBDCore_TypeDef *pCore) +{ + pUSBCore = pCore; + pCore->Info.CurrentStatus = USB_STATE_POWERED; + API_USB_INIT(pCore->pDriver); + __DBG_USBPrintf("\r\n%06ld \r\n", ++__DBG_USBCount); + return; +} + +/*********************************************************************************************************//** + * @brief USB Interrupt Service Routine. + * @param pCore: pointer of USB Device + * @retval None + ***********************************************************************************************************/ +void USBDCore_IRQHandler(USBDCore_TypeDef *pCore) +{ + u32 USBISRFlag = API_USB_GET_INT(); + u32 USBEPTISRFlag; + USBD_EPTn_Enum EPTn; + + #if (USBDCORE_DEBUG == 1) + u32 USBAddr = HT_USB->DEVAR; + #endif + + /*--------------------------------------------------------------------------------------------------------*/ + /* USB SOF Interrupt */ + /*--------------------------------------------------------------------------------------------------------*/ + if (API_USB_IS_SOF_INT(USBISRFlag)) + { + __DBG_USBPrintf("%06ld SOF[%02d][%02lX]\r\n", ++__DBG_USBCount, pCore->Info.CurrentStatus, USBAddr); + if (pCore->Class.CallBack_StartOfFrame.func != NULL) + { + pCore->Class.CallBack_StartOfFrame.func(pCore->Class.CallBack_StartOfFrame.uPara); + } + API_USB_CLR_SOF_INT(); + } + + /*--------------------------------------------------------------------------------------------------------*/ + /* USB SUSPEND Interrupt */ + /*--------------------------------------------------------------------------------------------------------*/ + if (API_USB_IS_SUSPEND_INT(USBISRFlag)) + { + __DBG_USBPrintf("%06ld SUSPEND[%02d]\r\n", ++__DBG_USBCount, pCore->Info.CurrentStatus); + API_USB_CLR_SUSPEND_INT(); + _USBDCore_Suspend(pCore); + } + + /*--------------------------------------------------------------------------------------------------------*/ + /* USB RESET Interrupt */ + /*--------------------------------------------------------------------------------------------------------*/ + if (API_USB_IS_RESET_INT(USBISRFlag)) + { + if (API_USB_IS_FRES_INT(USBISRFlag)) + { + API_USB_CLR_FRES_INT(); + } + else + { + __DBG_USBPrintf("%06ld RESET[%02d][%02lX]\r\n", ++__DBG_USBCount, pCore->Info.CurrentStatus, USBAddr); + _USBDCore_Reset(pCore); + if (pCore->Class.CallBack_Reset.func != NULL) + { + pCore->Class.CallBack_Reset.func(pCore->Class.CallBack_Reset.uPara); + } + } + API_USB_CLR_RESET_INT(); + } + + /*--------------------------------------------------------------------------------------------------------*/ + /* USB RESUME Interrupt */ + /*--------------------------------------------------------------------------------------------------------*/ + if (API_USB_IS_RESUME_INT(USBISRFlag)) + { + __DBG_USBPrintf("%06ld RESUME\r\n", ++__DBG_USBCount); + _USBDCore_Resume(pCore); + API_USB_CLR_RESUME_INT(); + } + + /*--------------------------------------------------------------------------------------------------------*/ + /* USB Endpoint 0 interrupt */ + /*--------------------------------------------------------------------------------------------------------*/ + if (API_USB_IS_EPTn_INT(USBISRFlag, USBD_EPT0)) + { + USBEPTISRFlag = API_USB_EPTn_GET_INT(USBD_EPT0); + + /*------------------------------------------------------------------------------------------------------*/ + /* Control SETUP Stage */ + /*------------------------------------------------------------------------------------------------------*/ + if (API_USB_IS_SETUP_INT(USBEPTISRFlag)) + { + API_USB_READ_SETUP(&(pCore->Device.Request)); /* Read SETUP Command data from USB Buffer*/ + + __DBG_USBPrintf("%06ld SETUP\t[08]\r\n", ++__DBG_USBCount); + __DBG_USBDump((uc8 *)&(pCore->Device.Request), 8); + + _USBDCore_Setup(pCore); + API_USB_CLR_SETUP_INT(); /* Clear SETUP Interrupt */ + } + + /*------------------------------------------------------------------------------------------------------*/ + /* Control Endpoint 0 IN */ + /*------------------------------------------------------------------------------------------------------*/ + if (API_USB_EPTn_IS_IN_INT(USBEPTISRFlag)) + { + __DBG_USBPrintf("%06ld EP0IN\t[%02ld]", ++__DBG_USBCount, pCore->Device.Transfer.sByteLength); + + _USBDCore_ControlIN(pCore); + API_USB_EPTn_CLR_IN_INT(USBD_EPT0); + } + + /*------------------------------------------------------------------------------------------------------*/ + /* Control Endpoint 0 OUT */ + /*------------------------------------------------------------------------------------------------------*/ + if (API_USB_EPTn_IS_OUT_INT(USBEPTISRFlag)) + { + __DBG_USBPrintf("%06ld EP0OUT\t[%02ld]", ++__DBG_USBCount, pCore->Device.Transfer.sByteLength); + + /*----------------------------------------------------------------------------------------------------*/ + /* Clear interrupt flag before USBDCore_ControlOUT is meaning since USBDCore_ControlOUT clear NAKRX */ + /* bit which will cause another interrupt occur. */ + /*----------------------------------------------------------------------------------------------------*/ + API_USB_EPTn_CLR_OUT_INT(USBD_EPT0); + _USBDCore_ControlOUT(pCore); + } + + /*------------------------------------------------------------------------------------------------------*/ + /* Clear Control Endpoint 0 global interrupt */ + /*------------------------------------------------------------------------------------------------------*/ + API_USB_CLR_EPTn_INT(USBD_EPT0); + + } /* if (API_USB_IS_EP_INT(USBISRFlag, USBD_EPT0)) */ + + + /*--------------------------------------------------------------------------------------------------------*/ + /* USB Endpoint n call back function */ + /*--------------------------------------------------------------------------------------------------------*/ + while ((EPTn = API_USB_GET_EPT_NUM(API_USB_GET_INT())) != USBD_NOEPT) + { + USBEPTISRFlag = API_USB_EPTn_GET_INT((USBD_EPTn_Enum)EPTn); + + if (API_USB_EPTn_IS_INT(USBEPTISRFlag)) + { + API_USB_EPTn_CLR_INT(EPTn); + API_USB_CLR_EPTn_INT(EPTn); + + if (pCore->Class.CallBack_EPTn[EPTn] != NULL) + { + pCore->Class.CallBack_EPTn[EPTn](EPTn); + } + } + } /* while ((EPTn = API_USB_GET_EPTn_NUM(API_USB_GET_INT())) != USBD_NOEPT) */ + + return; +} + +/*********************************************************************************************************//** + * @brief USB Core Main Routine for application. + * @param pCore: pointer of USB Device + * @retval None + ***********************************************************************************************************/ +void USBDCore_MainRoutine(USBDCore_TypeDef *pCore) +{ + _USBDCore_PowerHandler(pCore); + + /*--------------------------------------------------------------------------------------------------------*/ + /* Class main routine call back function */ + /*--------------------------------------------------------------------------------------------------------*/ + if ((pCore->Class.CallBack_MainRoutine.func != NULL) && (pCore->Info.CurrentStatus == USB_STATE_CONFIGURED)) + { + pCore->Class.CallBack_MainRoutine.func(pCore->Class.CallBack_MainRoutine.uPara); + } + + return; +} + +/*********************************************************************************************************//** + * @brief Return Suspend status + * @param pCore: pointer of USB Device + * @retval TRUE or FALSE + ***********************************************************************************************************/ +u32 USBDCore_IsSuspend(USBDCore_TypeDef *pCore) +{ + return ((pCore->Info.CurrentStatus == USB_STATE_SUSPENDED) ? TRUE : FALSE); +} + +/*********************************************************************************************************//** + * @brief Return remote wake status which set by SET FEATURE standard command + * @param pCore: pointer of USB Device + * @retval TRUE or FALSE + ***********************************************************************************************************/ +u32 USBDCore_GetRemoteWakeUpFeature(USBDCore_TypeDef *pCore) +{ + return (pCore->Info.CurrentFeature.Bits.bRemoteWakeup); +} + +/*********************************************************************************************************//** + * @brief Turn on USB power and remote wakeup the Host + * @retval None + ***********************************************************************************************************/ +void USBDCore_TriggerRemoteWakeup(void) +{ + API_USB_POWER_ON(); /* Turn on USB Power */ + API_USB_REMOTE_WAKEUP(); /* Generate Remote Wakeup request to Host (RESUME) */ + return; +} + +/*********************************************************************************************************//** + * @brief Get USB Device status + * @retval USBDCore_Status_Enum + ***********************************************************************************************************/ +USBDCore_Status_Enum USBDCore_GetStatus(void) +{ + return pUSBCore->Info.CurrentStatus; +} + +/*********************************************************************************************************//** + * @brief Dump memory data for debug purpose. + * @param memory: buffer pointer to dump + * @param len: dump length + * @retval None + ***********************************************************************************************************/ +#if (USBDCORE_DEBUG == 1 && USBDCORE_DEBUG_DATA == 1) +void __DBG_USBDump(uc8 *memory, u32 len) +{ + u32 i; + for (i = 0; i < len; i++) + { + if (i % 8 == 0) + { + if (i != 0) + { + __DBG_USBPrintf("\r\n"); + } + __DBG_USBPrintf("\t\t"); + } + __DBG_USBPrintf("%02X ", *((u8 *)(memory + i))); + } + __DBG_USBPrintf("\r\n"); + + return; +} +#endif +/** + * @} + */ + +/* Private functions ---------------------------------------------------------------------------------------*/ +/** @defgroup USBDCore_Private_Function USB Device Core private functions + * @{ + */ +/*********************************************************************************************************//** + * @brief USB Core Power handler for application. + * @param pCore: pointer of USB Device + * @retval None + ***********************************************************************************************************/ +static void _USBDCore_PowerHandler(USBDCore_TypeDef *pCore) +{ + API_USB_POWER_UP(pCore->pDriver, pCore->Info.CurrentFeature.Bits.bSelfPowered); + + if (pCore->Info.CurrentStatus == USB_STATE_SUSPENDED) + { + /*------------------------------------------------------------------------------------------------------*/ + /* System Low Power call back function */ + /*------------------------------------------------------------------------------------------------------*/ + if (pCore->Power.CallBack_Suspend.func != NULL) + { + __DBG_USBPrintf("%06ld >LOWPOWER\r\n", ++__DBG_USBCount); + + pCore->Power.CallBack_Suspend.func(pCore->Power.CallBack_Suspend.uPara); + + __DBG_USBPrintf("%06ld pDriver; + + pCore->Device.Transfer.sByteLength = USB_NO_DATA; + pCore->Info.uCurrentConfiguration = 0; + pCore->Info.uCurrentInterface = 0; + pCore->Info.CurrentFeature.Bits.bRemoteWakeup = 0; + pCore->Info.CurrentStatus = USB_STATE_DEFAULT; + pCore->Info.uIsDiscardClearFeature = FALSE; + + API_USB_DEINIT(); + + API_USB_POWER_ON(); + + /* Endpoint 0 initialization */ + API_USB_EPTn_INIT(USBD_EPT0, pCore->pDriver); // To be modify, init from desc + + /* Enable USB interrupt */ + API_USB_ENABLE_INT(pDrv->uInterruptMask); + + return; +} + +/*********************************************************************************************************//** + * @brief USB Resume + * @param pCore: pointer of USB Device + * @retval None + ***********************************************************************************************************/ +static void _USBDCore_Resume(USBDCore_TypeDef *pCore) +{ + API_USB_POWER_ON(); + pCore->Info.CurrentStatus = pCore->Info.LastStatus; + return; +} + +/*********************************************************************************************************//** + * @brief USB Suspend + * @param pCore: pointer of USB Device + * @retval None + ***********************************************************************************************************/ +static void _USBDCore_Suspend(USBDCore_TypeDef *pCore) +{ + /*--------------------------------------------------------------------------------------------------------*/ + /* When Device has been suspended, Change CurrentStatus as SUSPEND and then USBDCore_PowerHandler will */ + /* turn off chip power. */ + /*--------------------------------------------------------------------------------------------------------*/ + if (pCore->Info.CurrentStatus >= USB_STATE_POWERED) + { + API_USB_POWER_OFF(); + pCore->Info.LastStatus = pCore->Info.CurrentStatus; + pCore->Info.CurrentStatus = USB_STATE_SUSPENDED; + } + + return; +} + +/*********************************************************************************************************//** + * @brief USB Setup Stage + * @param pCore: pointer of USB Device + * @retval None + ***********************************************************************************************************/ +static void _USBDCore_Setup(USBDCore_TypeDef *pCore) +{ + pCore->Device.Transfer.Action = USB_ACTION_STALL; + pCore->Device.Transfer.sByteLength = 0; + + switch (pCore->Device.Request.bmRequestType & BMREQUEST_TYPE_MASK) + { + /*------------------------------------------------------------------------------------------------------*/ + /* Standard requests */ + /*------------------------------------------------------------------------------------------------------*/ + case REQ_TYPE_00_STD: + { + _USBDCore_Standard_Request(pCore); + break; + } + /*------------------------------------------------------------------------------------------------------*/ + /* Class requests */ + /*------------------------------------------------------------------------------------------------------*/ + case REQ_TYPE_01_CLS: + { + if (pCore->Class.CallBack_ClassRequest != NULL) + { + pCore->Class.CallBack_ClassRequest(&(pCore->Device)); + } + break; + } + /*------------------------------------------------------------------------------------------------------*/ + /* Vendor requests */ + /*------------------------------------------------------------------------------------------------------*/ + case REQ_TYPE_02_VND: + { + if (pCore->Class.CallBack_VendorRequest != NULL) + { + pCore->Class.CallBack_VendorRequest(&(pCore->Device)); + } + /* Add Vendor requests handler here.... */ + #ifdef USBD_VENDOR_SUPPORT + USBDVendor_Request(pCore); + #endif + break; + } + } /* switch (gUSBReq.bmRequestType.byte) */ + + switch (pCore->Device.Transfer.Action) + { + /*------------------------------------------------------------------------------------------------------*/ + /* Control IN */ + /*------------------------------------------------------------------------------------------------------*/ + case USB_ACTION_DATAIN: + { + /*----------------------------------------------------------------------------------------------------*/ + /* When the Control IN length is large than the Host required, transfer the length which specified */ + /* by SETUP Data Packet. */ + /*----------------------------------------------------------------------------------------------------*/ + if (pCore->Device.Transfer.sByteLength > pCore->Device.Request.wLength) + { + pCore->Device.Transfer.sByteLength = pCore->Device.Request.wLength; + } + __DBG_USBPrintf("%06ld EP0IN\t[%02ld]", __DBG_USBCount, pCore->Device.Transfer.sByteLength); + + _USBDCore_ControlIN(pCore); + break; + } + /*------------------------------------------------------------------------------------------------------*/ + /* Control OUT */ + /*------------------------------------------------------------------------------------------------------*/ + case USB_ACTION_DATAOUT: + { + if (pCore->Device.Transfer.sByteLength == 0) + { + API_USB_EPTn_WRITE_IN(USBD_EPT0, (u32 *)0, 0); /* Prepare ZLP ack for Control OUT */ + } + break; + } + /*------------------------------------------------------------------------------------------------------*/ + /* STALL */ + /*------------------------------------------------------------------------------------------------------*/ + default: + { + __DBG_USBPrintf("%06ld EP0 STALL\r\n", __DBG_USBCount); + + API_USB_EPTn_SEND_STALL(USBD_EPT0); + break; + } + } + + return; +} + +/*********************************************************************************************************//** + * @brief USB Stand Request. + * @param pCore: pointer of USB Device + * @retval None + ***********************************************************************************************************/ +static void _USBDCore_Standard_Request(USBDCore_TypeDef *pCore) +{ + u16 USBCmd = *((u16 *)(&(pCore->Device.Request))); + + switch (USBCmd) + { + /*------------------------------------------------------------------------------------------------------*/ + /* | bRequest | Data transfer direction | Type | Recipient | Data */ + /*------------------------------------------------------------------------------------------------------*/ + + /*------------------------------------------------------------------------------------------------------*/ + /* | 00_Get Status | 80_Device-to-Host | 00_Standard Request | 0_Device | 0080h */ + /*------------------------------------------------------------------------------------------------------*/ + case (REQ_00_GET_STAT | REQ_DIR_01_D2H | REQ_TYPE_00_STD | REQ_REC_00_DEV): + { + __DBG_USBPrintf("%06ld GET DST\t[%02d]\r\n", __DBG_USBCount, pCore->Info.CurrentFeature.uByte); + _USBDCore_Standard_GetStatus(pCore, Device); + break; + } + /*------------------------------------------------------------------------------------------------------*/ + /* | 00_Get Status | 80_Device-to-Host | 00_Standard Request | 1_Interface | 0081h */ + /*------------------------------------------------------------------------------------------------------*/ + case (REQ_00_GET_STAT | REQ_DIR_01_D2H | REQ_TYPE_00_STD | REQ_REC_01_INF): + { + __DBG_USBPrintf("%06ld GET IST\t[%02d]\r\n", __DBG_USBCount, 0); + _USBDCore_Standard_GetStatus(pCore, Interface); + break; + } + /*------------------------------------------------------------------------------------------------------*/ + /* | 00_Get Status | 80_Device-to-Host | 00_Standard Request | 2_Endpoint | 0082h */ + /*------------------------------------------------------------------------------------------------------*/ + case (REQ_00_GET_STAT | REQ_DIR_01_D2H | REQ_TYPE_00_STD | REQ_REC_02_EPT): + { + __DBG_USBPrintf("%06ld GET EST\t[%02d]\r\n", __DBG_USBCount, pCore->Device.Request.wIndex); + _USBDCore_Standard_GetStatus(pCore, Endpoint); + break; + } + /*------------------------------------------------------------------------------------------------------*/ + /* | 01_Clear Feature | 00_Host-to-Device | 00_Standard Request | 0_Device | 0100h */ + /*------------------------------------------------------------------------------------------------------*/ + case (REQ_01_CLR_FETU | REQ_DIR_00_H2D | REQ_TYPE_00_STD | REQ_REC_00_DEV): + { + __DBG_USBPrintf("%06ld CLR DFEA\t[%02d]\r\n", __DBG_USBCount, pCore->Device.Request.wValueL); + _USBDCore_Standard_SetClearFeature(pCore, Device, ClearFeature); + break; + } + /*------------------------------------------------------------------------------------------------------*/ + /* | 01_Clear Feature | 00_Host-to-Device | 00_Standard Request | 2_Endpoint | 0102h */ + /*------------------------------------------------------------------------------------------------------*/ + case (REQ_01_CLR_FETU | REQ_DIR_00_H2D | REQ_TYPE_00_STD | REQ_REC_02_EPT): + { + __DBG_USBPrintf("%06ld CLR EFEA\t[0x%02x]\r\n", __DBG_USBCount, pCore->Device.Request.wIndex); + _USBDCore_Standard_SetClearFeature(pCore, Endpoint, ClearFeature); + break; + } + /*------------------------------------------------------------------------------------------------------*/ + /* | 03_Set Feature | 00_Host-to-Device | 00_Standard Request | 0_Device | 0300h */ + /*------------------------------------------------------------------------------------------------------*/ + case (REQ_03_SET_FETU | REQ_DIR_00_H2D | REQ_TYPE_00_STD | REQ_REC_00_DEV): + { + __DBG_USBPrintf("%06ld SET DFEA\t[%02d]\r\n", __DBG_USBCount, pCore->Device.Request.wValueL); + _USBDCore_Standard_SetClearFeature(pCore, Device, SetFeature); + break; + } + /*------------------------------------------------------------------------------------------------------*/ + /* | 03_Set Feature | 00_Host-to-Device | 00_Standard Request | 2_Endpoint | 0302h */ + /*------------------------------------------------------------------------------------------------------*/ + case (REQ_03_SET_FETU | REQ_DIR_00_H2D | REQ_TYPE_00_STD | REQ_REC_02_EPT): + { + __DBG_USBPrintf("%06ld SET EFEA\t[%02d]\r\n", __DBG_USBCount, pCore->Device.Request.wIndex); + _USBDCore_Standard_SetClearFeature(pCore, Endpoint, SetFeature); + break; + } + /*------------------------------------------------------------------------------------------------------*/ + /* | 05_Set Address | 00_Host-to-Device | 00_Standard Request | 0_Device | 0500h */ + /*------------------------------------------------------------------------------------------------------*/ + case (REQ_05_SET_ADDR | REQ_DIR_00_H2D | REQ_TYPE_00_STD | REQ_REC_00_DEV): + { + __DBG_USBPrintf("%06ld SET ADDR\t[%02d]\r\n", __DBG_USBCount, pCore->Device.Request.wValueL); + _USBDCore_Standard_SetAddress(pCore); + break; + } + /*------------------------------------------------------------------------------------------------------*/ + /* | 06_Get Descriptor | 80_Device-to-Host | 00_Standard Request | 0_Device | 0680h */ + /*------------------------------------------------------------------------------------------------------*/ + case (REQ_06_GET_DESC | REQ_DIR_01_D2H | REQ_TYPE_00_STD | REQ_REC_00_DEV): + { + __DBG_USBPrintf("%06ld GET DDESC\t[%02X]\r\n", __DBG_USBCount, pCore->Device.Request.wValueH); + _USBDCore_Standard_GetDescriptor(pCore); + break; + } + /*------------------------------------------------------------------------------------------------------*/ + /* | 06_Get Descriptor | 80_Device-to-Host | 00_Standard Request | 1_Interface | 0681h */ + /*------------------------------------------------------------------------------------------------------*/ + case (REQ_06_GET_DESC | REQ_DIR_01_D2H | REQ_TYPE_00_STD | REQ_REC_01_INF): + { + __DBG_USBPrintf("%06ld GET IDESC\t[%02X]\r\n", __DBG_USBCount, pCore->Device.Request.wValueH); + if (pCore->Class.CallBack_ClassGetDescriptor != NULL) + { + pCore->Class.CallBack_ClassGetDescriptor((USBDCore_Device_TypeDef *)&(pCore->Device)); + } + break; + } + /*------------------------------------------------------------------------------------------------------*/ + /* | 08_Get Configuration | 80_Host-to-Device | 00_Standard Request | 0_Device | 0880h */ + /*------------------------------------------------------------------------------------------------------*/ + case (REQ_08_GET_CONF | REQ_DIR_01_D2H | REQ_TYPE_00_STD | REQ_REC_00_DEV): + { + __DBG_USBPrintf("%06ld GET CONF\t[%02X]\r\n", __DBG_USBCount, pCore->Info.uCurrentConfiguration); + _USBDCore_Standard_GetConfiguration(pCore); + break; + } + /*------------------------------------------------------------------------------------------------------*/ + /* | 09_Set Configuration | 00_Host-to-Device | 00_Standard Request | 0_Device | 0900h */ + /*------------------------------------------------------------------------------------------------------*/ + case (REQ_09_SET_CONF | REQ_DIR_00_H2D | REQ_TYPE_00_STD | REQ_REC_00_DEV): + { + __DBG_USBPrintf("%06ld SET CONF\t[%02X]\r\n", __DBG_USBCount, pCore->Device.Request.wValueL); + _USBDCore_Standard_SetConfiguration(pCore); + break; + } + /*------------------------------------------------------------------------------------------------------*/ + /* | 11_Set Interface | 00_Host-to-Device | 00_Standard Request | 1_Interface | 0B01h */ + /*------------------------------------------------------------------------------------------------------*/ + case (REQ_11_SET_INF | REQ_DIR_00_H2D | REQ_TYPE_00_STD | REQ_REC_01_INF): + { + __DBG_USBPrintf("%06ld SET INF\t[%02X]\r\n", __DBG_USBCount, pCore->Device.Request.wValueL); + if (pCore->Class.CallBack_ClassSetInterface != NULL) + { + pCore->Class.CallBack_ClassSetInterface((USBDCore_Device_TypeDef *)&(pCore->Device)); + } + break; + } + /*------------------------------------------------------------------------------------------------------*/ + /* | 10_Get Interface | 80_Device-to-Host | 00_Standard Request | 1_Interface | 0A81h */ + /*------------------------------------------------------------------------------------------------------*/ + case (REQ_10_GET_INF | REQ_DIR_01_D2H | REQ_TYPE_00_STD | REQ_REC_01_INF): + { + __DBG_USBPrintf("%06ld GET INF\t[%02X]\r\n", __DBG_USBCount, pCore->Device.Request.wValueL); + if (pCore->Class.CallBack_ClassGetInterface != NULL) + { + pCore->Class.CallBack_ClassGetInterface((USBDCore_Device_TypeDef *)&(pCore->Device)); + } + break; + } + } + + return; +} + +/*********************************************************************************************************//** + * @brief USB Standard Request - GET_STATUS. + * @param pCore: pointer of USB Device + * @param recipient: Recipient + * @arg Device: 0 + * @arg Interface: 1 + * @arg Endpoint: 2 + * @retval None + ***********************************************************************************************************/ +static void _USBDCore_Standard_GetStatus(USBDCore_TypeDef *pCore, USBDCore_Recipient_Enum recipient) +{ + pCore->Device.Transfer.uBuffer[1] = 0; + switch (recipient) + { + case Device: + { + pCore->Device.Transfer.uBuffer[0] = pCore->Info.CurrentFeature.uByte; + break; + } + case Interface: + { + pCore->Device.Transfer.uBuffer[0] = 0; + break; + } + case Endpoint: + { + pCore->Device.Transfer.uBuffer[0] = API_USB_EPTn_GET_HALT((USBD_EPTn_Enum)(pCore->Device.Request.wIndex & 0xF)); + break; + } + default: + { + return; + } + } + + pCore->Device.Transfer.pData = (uc8 *)&(pCore->Device.Transfer.uBuffer); + pCore->Device.Transfer.sByteLength = 2; + pCore->Device.Transfer.Action = USB_ACTION_DATAIN; + + return; +} + +/*********************************************************************************************************//** + * @brief USB Standard Request - SET_FEATURE / CLEAR_FEATURE. + * @param pCore: pointer of USB Device + * @param recipient: Recipient + * @arg Device: 0 + * @arg Interface: 1 + * @arg Endpoint: 2 + * @param type: + * @arg ClearFeature: 0 + @arg SerFeature: 1 + * @retval None + ***********************************************************************************************************/ +static void _USBDCore_Standard_SetClearFeature(USBDCore_TypeDef *pCore, + USBDCore_Recipient_Enum recipient, + USBDCore_SetClearFeature_Enum type) +{ + u32 i; + switch (recipient) + { + case Device: + { + if (pCore->Device.Request.wValueL == USB_FEATURE_REMOTE_WAKEUP) + { + pCore->Info.CurrentFeature.Bits.bRemoteWakeup = type; + pCore->Device.Transfer.Action = USB_ACTION_DATAIN; + } + break; + } + case Endpoint: + { + i = pCore->Device.Request.wIndex & 0xF; + if (i != 0) + { + if (type == ClearFeature) + { + if (pCore->Info.uIsDiscardClearFeature == FALSE) + { + API_USB_EPTn_CLR_HALT((USBD_EPTn_Enum)i); + API_USB_EPTn_CLR_DTG((USBD_EPTn_Enum)i); + } + } + else + { + API_USB_EPTn_SET_HALT((USBD_EPTn_Enum)i); + } + } + pCore->Device.Transfer.Action = USB_ACTION_DATAIN; + break; + } + default: + { + break; + } + } + + return; +} + +/*********************************************************************************************************//** + * @brief USB Standard Request - SET_ADDRESS. + * @param pCore: pointer of USB Device + * @retval None + ***********************************************************************************************************/ +static void _USBDCore_Standard_SetAddress(USBDCore_TypeDef *pCore) +{ + API_USB_SET_ADDR(pCore->Device.Request.wValueL); + pCore->Device.Transfer.Action = USB_ACTION_DATAIN; + pCore->Info.CurrentStatus = USB_STATE_ADDRESS; + + return; +} + +/*********************************************************************************************************//** + * @brief USB Standard Request - GET_DESCRIPTOR. + * @param pCore: pointer of USB Device + * @retval None + ***********************************************************************************************************/ +static void _USBDCore_Standard_GetDescriptor(USBDCore_TypeDef *pCore) +{ + u32 value = pCore->Device.Request.wValueH; + uc8 *pTemp; + + switch (value) + { + case DESC_TYPE_01_DEV: + { + pCore->Device.Transfer.pData = pCore->Device.Desc.pDeviceDesc; + pCore->Device.Transfer.sByteLength = *(pCore->Device.Desc.pDeviceDesc); + pCore->Device.Transfer.Action= USB_ACTION_DATAIN; + break; + } + case DESC_TYPE_02_CONFN: + { + pCore->Device.Transfer.pData = pCore->Device.Desc.pConfnDesc; + pCore->Device.Transfer.sByteLength = *(u16 *)((pCore->Device.Desc.pConfnDesc) + 2); + pCore->Device.Transfer.Action = USB_ACTION_DATAIN; + break; + } + case DESC_TYPE_03_STR: + { + value = pCore->Device.Request.wValueL; + if (value < pCore->Device.Desc.uStringDescNumber) + { + if (*(pCore->Device.Desc.ppStringDesc + value) != NULL) + { + pTemp = *(pCore->Device.Desc.ppStringDesc + value); + pCore->Device.Transfer.pData = (uc8 *)(pTemp); + pCore->Device.Transfer.sByteLength = *(pTemp); + pCore->Device.Transfer.Action = USB_ACTION_DATAIN; + } + } + break; + } + } + + #ifdef USBD_VENDOR_SUPPORT + USBDVendor_StandardGetDescriptor(pCore); + #endif + + return; +} + +/*********************************************************************************************************//** + * @brief USB Standard Request - GET_CONFIGURATION. + * @param pCore: pointer of USB Device + * @retval None + ***********************************************************************************************************/ +static void _USBDCore_Standard_GetConfiguration(USBDCore_TypeDef *pCore) +{ + pCore->Device.Transfer.pData = &(pCore->Info.uCurrentConfiguration); + pCore->Device.Transfer.sByteLength = 1; + pCore->Device.Transfer.Action= USB_ACTION_DATAIN; + + return; +} + +/*********************************************************************************************************//** + * @brief USB Standard Request - SET_CONFIGURATION. + * @param pCore: pointer of USB Device + * @retval None + ***********************************************************************************************************/ +static void _USBDCore_Standard_SetConfiguration(USBDCore_TypeDef *pCore) +{ + u32 i; + + pCore->Info.uCurrentConfiguration = pCore->Device.Request.wValueL; + pCore->Device.Transfer.Action= USB_ACTION_DATAIN; + + /* Endpoint n settings */ + for (i = 1; i < MAX_EP_NUM; i++) + { + API_USB_EPTn_INIT((USBD_EPTn_Enum)i, pCore->pDriver); // To be modify, init from desc + } + + pCore->Info.CurrentStatus = USB_STATE_CONFIGURED; + + return; +} + +/*********************************************************************************************************//** + * @brief USB Control IN transfer. + * @param pCore: pointer of USB Device + * @retval None + ***********************************************************************************************************/ +static void _USBDCore_ControlIN(USBDCore_TypeDef *pCore) +{ + s32 EP0INLen = API_USB_GET_CTRL_IN_LEN(); + u32 len; + + if (pCore->Device.Transfer.sByteLength != USB_NO_DATA && pCore->Device.Transfer.Action == USB_ACTION_DATAIN) + { + if (pCore->Device.Transfer.sByteLength >= EP0INLen) + { + len = EP0INLen; + pCore->Device.Transfer.sByteLength -= len; + } + else + { + len = pCore->Device.Transfer.sByteLength; + pCore->Device.Transfer.sByteLength = USB_NO_DATA; + pCore->Device.Transfer.Action = USB_ACTION_DATAOUT; + } + + __DBG_USBPrintf("[%02ld]\r\n", len); + __DBG_USBDump((uc8 *)pCore->Device.Transfer.pData, len); + + API_USB_EPTn_WRITE_IN(USBD_EPT0, (u32 *)pCore->Device.Transfer.pData, len); + pCore->Device.Transfer.pData = pCore->Device.Transfer.pData + len; + } + else + { + __DBG_USBPrintf("[-1]\r\n"); + } + + return; +} + +/*********************************************************************************************************//** + * @brief USB Control OUT transfer. + * @param pCore: pointer of USB Device + * @retval None + ***********************************************************************************************************/ +static void _USBDCore_ControlOUT(USBDCore_TypeDef *pCore) +{ + u32 len; + + if (pCore->Device.Transfer.sByteLength != USB_NO_DATA && pCore->Device.Transfer.Action == USB_ACTION_DATAOUT) + { + len = API_USB_EPTn_READ_OUT(USBD_EPT0, (u32 *)pCore->Device.Transfer.pData, MAX_CONTROL_OUT_SIZE); + + __DBG_USBPrintf("[%02ld]\r\n", len); + __DBG_USBDump((uc8 *)pCore->Device.Transfer.pData, len); + + pCore->Device.Transfer.pData = pCore->Device.Transfer.pData + len; + pCore->Device.Transfer.sByteLength -= len; + + if (pCore->Device.Transfer.sByteLength == 0) + { + pCore->Device.Transfer.Action = USB_ACTION_DATAIN; + if (pCore->Device.Transfer.CallBack_OUT.func != NULL) + { + pCore->Device.Transfer.CallBack_OUT.func(pCore->Device.Transfer.CallBack_OUT.uPara); + pCore->Device.Transfer.CallBack_OUT.func = NULL; + } + pCore->Device.Transfer.sByteLength = USB_NO_DATA; + API_USB_EPTn_WRITE_IN(USBD_EPT0, (u32 *)0, 0); + } + } + else + { + __DBG_USBPrintf("[-1]\r\n"); + } + + return; +} +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/Release_Notes.txt b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/Release_Notes.txt new file mode 100644 index 0000000000..948233eafc --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/Release_Notes.txt @@ -0,0 +1,1674 @@ +/*********************************************************************************************************//** + * @file Release_Notes.txt + * @version V1.9.1 + * @date 2023-12-22 + * @brief The Release notes of HT32 Firmware Library. + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ + +// Supported Device +// ======================================== +// HT32F50020, HT32F50030 +// HT32F50220, HT32F50230 +// HT32F50231, HT32F50241 +// HT32F50343 +// HT32F50431, HT32F50441 +// HT32F50442, HT32F50452 +// HT32F52220, HT32F52230 +// HT32F52231, HT32F52241 +// HT32F52234, HT32F52244 +// HT32F52243, HT32F52253 +// HT32F52331, HT32F52341 +// HT32F52342, HT32F52352 +// HT32F52344, HT32F52354 +// HT32F52357, HT32F52367 +// HT32F53231, HT32F53241 +// HT32F53242, HT32F53252 +// HT32F54231, HT32F54241 +// HT32F54243, HT32F54253 +// HT32F57331, HT32F57341 +// HT32F57342, HT32F57352 +// HT32F59041, HT32F59741 +// HT32F59046, HT32F59746 +// HT32F5826, HT32F5828 +// HT32F0006 +// HT32F0008 +// HT32F52142 +// HT32F61030, HT32F61041 +// HT32F61141 +// HT32F61244, HT32F61245 +// HT32F61352 +// HT32F61355, HT32F61356, HT32F61357 +// HT32F61630, HT32F61641 +// HT32F62030, HT32F62040, HT32F62050 +// HT32F65230, HT32F65240 +// HT32F65232 +// HT32F67041, HT32F67051 +// HT32F67232 +// HT32F67233 +// HT32F67741 +// HT32F67742 +// HT50F32002, HT50F32003 +// HT50F3200S, HT50F3200T +// HF5032 +// MXTX6306 + +/*----------------------------------------------------------------------------------------------------------*/ +/* HT32_STD_5xxxx_FWLib_V1.9.1_7446 */ +/*----------------------------------------------------------------------------------------------------------*/ + Release Date: 2023-12-22 + Main Changes + + Add example support of BM18B367A DVB. + + Add "system_ht32f5xxxx_18.c" for BM18B367A DVB. + + Update "ht32f5xxxx_aes.c/h", changed API parameter 4 bytes to remove type conversion at driver layer. + + Update example, add "__ALIGN4" to variables and enforced type conversion for 4 bytes read/write API calls. + - "AES/CBC" + - "AES/CTR" + - "AES/ECB" + + Update USB example, add the process of detecting USB bus status before USBDCore_LowPower(). + - "CKCU/HSI_AutoTrim_By_USB" + - "USBD/*" + + Update USART example for BM18B367A DVB, add the HSI auto trim by LSE related flow. + - "USART/Interrupt" + - "USART/Interrupt_FIFO" + - "USART/PDMA" + - "USART/Polling" + - "USART/Retarget" + - "USART/RS485_NMM_Slave" + + Others + + Update comment, format, typing error, and coding style. + +/*----------------------------------------------------------------------------------------------------------*/ +/* HT32_STD_5xxxx_FWLib_V1.8.1_7371 */ +/*----------------------------------------------------------------------------------------------------------*/ + Release Date: 2023-12-06 + Main Changes + + Update "ht32f5xxxx_usbd.c", fix the USB buffer unaligned handling mechanism. + + Update "ht32f5xxxx_rtc.c", modify the RTC_LSECmd() related flow. + + Fix example IO define error of BM53A367A DVB. + - "I2C/PDMA" + + Update example IO define for the latest version of BM53A367A DVB. + - "TM/MatchOutputToggle" + - "TM/PWM" + + Update "ht32f5xxxx_adc.c" and "ht32f65xxx_66xxx_adc.c" to modify the ADC enable related flow. + + Others + + Update comment, format, typing error, and coding style. + +/*----------------------------------------------------------------------------------------------------------*/ +/* HT32_STD_5xxxx_FWLib_V1.7.1_7327 */ +/*----------------------------------------------------------------------------------------------------------*/ + Release Date: 2023-11-01 + Main Changes + + Fix example IO define conflict with LED1 of HT32F57352 Starter Kit. + - "CMP/ComparatorInterrupt" + + Fix example IO define error of HT32F50441. + - "MCTM/ComplementaryOutput" + + Update "ht32f5xxxx_ckcu.c", modify the HSI Auto Trim initial function related flow. + + Update "ht32f5xxxx_adc.c" and "ht32f65xxx_66xxx_adc.c", modify the ADC enable related flow. + + Update "ht32_op.c" and "ht32_op.s" to support new version of bootloader waiting time setting address. + (The setting address is changed from 0x1FF0002C to 0x1FF0004C) + + Add "ht32_op_V107.c" and "ht32_op_V107.s" to support the use of older versions of bootloader. + + Others + + Update comment, format, typing error, and coding style. + + Modify and check the example supportability of each IC. + + Add the below file, for the BMduino shield. + - "ht32_undef_IP.h" + +/*----------------------------------------------------------------------------------------------------------*/ +/* HT32_STD_5xxxx_FWLib_V1.6.2_7271 */ +/*----------------------------------------------------------------------------------------------------------*/ + Release Date: 2023-10-03 + Main Changes + + Add example support. + - HT32F53231/41, HT32F53242/52 + - HT32F50431/41, HT32F50442/52 + - HT32F52234/44 + + Fix example IO define error of HT32F52367. + - "USBD/Mass_Storage" + + Modify the example below, add volatile qualifier on some variables (in the for loop usage) + to fix the Arm Compiler Version 6 optimization issue. + ("u32" to "vu32", unsigned int to volatile unsigned int). + - "FMC/FLASH_Security" + + Modify the example below, change the timer used from GPTM to BFTM to increase support. + - "PDMA/SoftwareTrigger" + + Add the below folder, For the BMduino shield/module Keil Driver. + - "BestModules" + + Others + + Update comment, format, typing error, and coding style. + + Adjust "LIBCFG_xxxxx" definition below. + New: + "LIBCFG_ADC_IVREF_DEFAULT_08V" + +/*----------------------------------------------------------------------------------------------------------*/ +/* HT32_STD_5xxxx_FWLib_V1.6.1_7190 */ +/*----------------------------------------------------------------------------------------------------------*/ + Release Date: 2023-08-31 + Main Changes + + Add new device support. + - HT32F61030, HT32F61041 + - HT32F50431, HT32F50441, HT32F50442, HT32F50452 + - HT32F53231, HT32F53241, HT32F53242, HT32F53252 + + Add Controller Area Network driver, "ht32f5xxxx_can.c/h". + + Add new "CAN/FIFO" example. + + Others + + Update comment, format, typing error, and coding style. + + Update "project_template/Script" for adding project C++ source files and setting the chip model mechanism. + - The updated files are as follows: + "Script/_ProjectSource.bat" + "Script/_ProjectSource.ini" + + Update "project_template/Script" for improving script mechanism. + - The updated files are as follows: + "Script/_CreateProjectConfScript.bat" + "Script/_CreateProjectScript.bat" + "Script/_ht32_ic_name.ini" + +/*----------------------------------------------------------------------------------------------------------*/ +/* HT32_STD_5xxxx_FWLib_V1.5.1_7084 */ +/*----------------------------------------------------------------------------------------------------------*/ + Release Date: 2023-08-01 + Main Changes + + Add new device support. + - HT32F52234, HT32F52244 + + Modify DAC related define (The left side old one is still kept for backward compatible). + - HT_DAC -> HT_DAC0 + - AFIO_FUN_DAC -> AFIO_FUN_DAC0 + - CKCU_PCLK_DAC -> CKCU_PCLK_DAC0 + + Modify API as below, add parameter "HT_DAC_TypeDef* HT_DACn" to select DAC engine from the DAC peripherals. + Old API + - DAC_DeInit(void) + - DAC_ModeConfig(u8 ModeSel) + - DAC_ReferenceConfig(u8 DAC_Ch, u32 RefSel) + - DAC_ResolutionConfig(u8 DAC_Ch, u32 ResoSel) + - DAC_OutBufCmd(u8 DAC_Ch, ControlStatus NewState) + - DAC_Cmd(u8 DAC_Ch, ControlStatus NewState) + - DAC_SetData(u8 DAC_Ch, u32 Data) + - DAC_GetOutData(u8 DAC_Ch) + New API + - DAC_DeInit(HT_DAC_TypeDef* HT_DACn) + - DAC_ModeConfig(HT_DAC_TypeDef* HT_DACn, u8 ModeSel) + - DAC_ReferenceConfig(HT_DAC_TypeDef* HT_DACn, u8 DAC_Ch, u32 RefSel) + - DAC_ResolutionConfig(HT_DAC_TypeDef* HT_DACn, u8 DAC_Ch, u32 ResoSel) + - DAC_OutBufCmd(HT_DAC_TypeDef* HT_DACn, u8 DAC_Ch, ControlStatus NewState) + - DAC_Cmd(HT_DAC_TypeDef* HT_DACn, u8 DAC_Ch, ControlStatus NewState) + - DAC_SetData(HT_DAC_TypeDef* HT_DACn, u8 DAC_Ch, u32 Data) + - DAC_GetOutData(HT_DAC_TypeDef* HT_DACn, u8 DAC_Ch) + + Add API as below. + - "USART_LIN_SendBreak()" API for the USART/UART LIN mode send break to Tx. + - "USART_LIN_LengthSelect()" API for the USART/UART LIN mode configure the break detection length. + - "CKCU_Set_HSIReadyCounter" API for set HSI ready counter value. + + Others + + Update comment, format, typing error, and coding style. + + Rename "LIBCFG_xxxxx" definition below. + - "LIBCFG_DAC" to "LIBCFG_DAC0" + + Add HT32F61630/HT32F61641 related files for Create Project. + +/*----------------------------------------------------------------------------------------------------------*/ +/* HT32_STD_5xxxx_FWLib_V1.4.3_7026 */ +/*----------------------------------------------------------------------------------------------------------*/ + Release Date: 2023-07-17 + + Main Changes + + Add new device support. + - HT32F59046, HT32F59746 + + Others + + Update comment, format, typing error, and coding style. + + Update and sync startup.s/system.c files. + +/*----------------------------------------------------------------------------------------------------------*/ +/* HT32_STD_5xxxx_FWLib_V1.4.2_6992 */ +/*----------------------------------------------------------------------------------------------------------*/ + Release Date: 2023-06-20 + + Main Changes + + Add new device support. + - HT32F61630, HT32F61641 + - HT32F62030, HT32F62040, HT32F62050 + - HT32F67742 + + Modify "RETARGET_Configuration()", add the operation of UxARTn peripheral clock enable. + + Update and sync "ht32f5xxxx_conf.h", modify related define of UxARTn retarget port. + + Others + + Update comment, format, typing error, and coding style. + +/*----------------------------------------------------------------------------------------------------------*/ +/* HT32_STD_5xxxx_FWLib_V1.4.1_6948 */ +/*----------------------------------------------------------------------------------------------------------*/ + Release Date: 2023-05-19 + + Main Changes + + Add new device support. + - HT50F3200S, HT50F3200T + + Add example support of HT32F67233. + + Add new "GPIO/PinLock" example. + + Add "Project or Target File Clearing" functions ("_ClearProject.bat" and "_ClearTarget.bat"). + + Rename "ht32f652xx_opa.c/h" to "ht32f65xxx_66xxx_opa.c/h". + + Rename "ht32f652xx_adc.c/h" to "ht32f65xxx_66xxx_adc.c/h". + + Add "ht32f652xx_opa.c/h" and "ht32f652xx_adc.c/h" for backward compatible. + + Modify "ht32_time.h", "ht32f5xxxx_conf.h" and "ht32_time_conf.h" for "LIBCFG_CKCU_NO_APB_PRESCALER" series. + - To ensure the correct configuration of the timer clock, the "HTCFG_TIME_PCLK_DIV" is redefined as 0. + + Modify "syscall.c" to prevent redundant initialization of the heap index. + + Modify the examples below, use separate "if" statements instead of "if-else" to avoid double-entry ISR. + - "PWRCU/DeepSleepMode1" + - "PWRCU/DeepSleepMode2" + + Modify "ht32f5xxxx_01.h" below, ensure the defined register naming to be consistent with the document. + Old New + ----- ----- + - HT_OPA_TypeDef + "OFR" to "VOS" + "VALR" to "DAC" + - HT_CMP_TypeDef + "ICR" to "CI" + "OCR" to "CO" + + Others + + Update comment, format, typing error, and coding style. + + Update e-Link32 Pro/Lite Command line tool as "V1.19" ("utilities/elink32pro/eLink32pro.exe"). + + Update the LVDS setting method of "example\PWRCU\BOD_LVD" example ht32_board_config.h file. + + Update "system_ht32f5xxxx_nn.c" and "startup_ht32f5xxxx_nn.s" files. + + Modify "_ProjectConfigScript.bat" to prevent the creation of project that copy unused system/startup files. + + Modify the Sourcery G++ Lite toolchain project. + - Set C99 mode to fix issues after updating CMSIS v5.9.0 ("for" loop initial declarations). + + Modify and check the startup_ht32fxxxxx_nn files, fix _HT32FWID more than one digit problem. + + Adjust "LIBCFG_xxxxx" definition below. + New: + "LIBCFG_ADC_NO_OFFSET_REG" + Rename: + "LIBCFG_CMP_OCR" to "LIBCFG_CMP_CO" + +/*----------------------------------------------------------------------------------------------------------*/ +/* HT32_STD_5xxxx_FWLib_V1.3.4_6737 */ +/*----------------------------------------------------------------------------------------------------------*/ + Release Date: 2023-02-17 + + Main Changes + + Add example support of HT32F61244, HT32F61245. + + Modify the example below, add volatile qualifier on some variables (in the for loop usage) + to fix the Arm Compiler Version 6 optimization issue. + ("u32" to "vu32", unsigned int to volatile unsigned int). + - "PWRCU/PowerDown_WAKEUPPin" + - "PWRCU/PowerDown_RTC" + - "TM/PWM" + + Others + + Update comment, format, typing error, and coding style. + + Change the default RTC clock as LSI for the "PWRCU/PowerDownMode" example. + + Add the pin group of QSPI in "ht32f61245_sk.h". + + Add "ht32_board_config.h" for the "SYSTICK/DelayMicrosecond" example. + +/*----------------------------------------------------------------------------------------------------------*/ +/* HT32_STD_5xxxx_FWLib_V1.3.3_6685 */ +/*----------------------------------------------------------------------------------------------------------*/ + Release Date: 2023-01-18 + + Main Changes + + Add new device support. + - HT32F61244, HT32F61245, HT32F67233 + + Add new examples: + - "SRAM_Overwrite/Watchpoint_Heap" + - "SRAM_Overwrite/Watchpoint_Stack" + + Update "ht32f5xxxx_conf.h" for user layer HSE_VALUE setting. + + Update "ht32f5xxxx_midi.c/.h" for HT32F0006/61355/61356/61357/61244/61245. + + Add "PDMA_MIDI_IN", "PDMA_MIDI_OUT" define. + + Fix "MAX_EP_NUM" define error of HT32F61141. + + Update "SPI/PDMA" example, fix the function call order as below. The "SPI_SELOutputCmd()" shall be called + before the "SPI_Cmd()", to prevent SPI Master Mode Fault (MF) error if Chip Select pin did not have + an external pull-up. + "SPI_SELOutputCmd(HTCFG_SPIS_PORT, ENABLE);" + "SPI_Cmd(HTCFG_SPIS_PORT, ENABLE);" + + Others + + Update comment, format, typing error, and coding style. + + Update and sync startup.s/system.c files. + + Modify "system_ht32fxxxxx_nn.c", add HSE_VALUE notice and update PLL Out formula. + + Update EEPROM Emulation middleware, improve efficacy and reduce resource usage. + "utilities/middleware/eeprom_emulation.c" + "utilities/middleware/ht32_eeprom_config_templet.h" + + Update I2C Master middleware, improve setting way and fix minor errors. + "utilities/middleware/i2c_master.c/.h" + "utilities/middleware/i2c_master_config_templet.h" + +/*----------------------------------------------------------------------------------------------------------*/ +/* HT32_STD_5xxxx_FWLib_V1.3.2_6448 */ +/*----------------------------------------------------------------------------------------------------------*/ + Release Date: 2022-11-15 + + Main Changes + + Add new examples: + - "ADC/ADC_InternalReferenceVoltage_SWTriggerr" + + Add "LIBCFG_ADC_TRIG_DELAY" define to support "ADC_TrigDelayConfig" function for HT32F65230/65240. + + Update "ADC_24bit/Convert_Interrupt" example, fix "I2CMaster_Typedef" structure variable error (correct + "uTimeout_ms" to "uTimeout_us") of "ADC24_WriteRegNonBlock()" and "ADC24_ReadRegNonBlock()". + + Update "ht32_time.h", fix a formula error of "TIME_TICK2US()" and "TIME_TICK2MS()" macro. + + Modify "ht32_retarget.c", fix retarget can't work when the MicroLIB is not used in Keil's V6 compiler. + + Others + + Upgrade CMSIS to v5.9.0. + + Update "ht32_op.s/c", allow "Bootloader Waiting Time" function for all series. + + Modify "HT32F5xxxx_01_DebugSupport.ini" content. + +/*----------------------------------------------------------------------------------------------------------*/ +/* HT32_STD_5xxxx_FWLib_V1.3.1_6405 */ +/*----------------------------------------------------------------------------------------------------------*/ + Release Date: 2022-10-28 + + Main Changes + + Add new device support. + - HT32F50020, HT32F50030 + + GPIO + - Add new define "GPIO_PIN_NUM_n" for GPIO pin number (n = 0 ~ 15). + + EXTI + - Add "gEXTIn_IRQn[]" and "EXTI_GetIRQn()"" macro to map GPIO pin number (0 ~ 15) to "EXTIn_IRQn". + - Add "GPIO2EXTI()"" macro to map GPIO pin to EXTI Channel. + - Change "AFIO_EXTISourceConfig()"" API, remove "AFIO_EXTI_CH_Enum" and "AFIO_ESS_Enum". + Old: "void AFIO_EXTISourceConfig(AFIO_EXTI_CH_Enum AFIO_EXTI_CH_n, AFIO_ESS_Enum AFIO_ESS_Px);" + New: "void AFIO_EXTISourceConfig(u32 GPIO_PIN_NUM_n, u32 GPIO_Px);" + + LEDC + - Fix typing error of the following define. + Old New + ------------- ---------------- + LEDC_FLAG_FEAME LEDC_FLAG_FRAME + LEDC_INT_FEAME LEDC_INT_FRAME + + Fix the error that "TM_DeInit(HT_PWM2)" not works. + + Add new examples: + - "ADC/OneShot_SWTrigger" + + Rename examples as below. + IP Old Name New Name + -------- -------- -------- + ADC InternalReferenceVoltage InternalReferenceVoltage_PWMTrigger + + Modify "EXTI/WakeUp_SleepMode" example, fix "EXTIn_IRQHandler()" ISR naming error of "ht32f5xxxx_01_it.c" + (HT32F652xx). + + Others + + Update comment, format, typing error, and coding style. + + Update and sync startup.s/system.c files. + + Modify API parameter check macro of Library Debug Mode, fix parameter check error. + + Modify variable declaration of "PDMACH_InitTypeDef" to reduce memory size. + + Add a setting, "HT32_LIB_ENABLE_GET_CK_ADC" to control "ADC0_Freq/ADC1_Freq" calculation of the + "CKCU_GetClocksFrequency()" function (default off for code size consideration). + +/*----------------------------------------------------------------------------------------------------------*/ +/* HT32_STD_5xxxx_FWLib_V1.2.1_6192 */ +/*----------------------------------------------------------------------------------------------------------*/ + Release Date: 2022-09-30 + + Main Changes + + Add new device support. + - HT32F67232 + - HT32F67041, HT32F67051 + + Add the following API for PDMA. + - "PDMA_DeInit()" + - "PDMA_AddrConfig()" + - "PDMA_SrcAddrConfig()" + - "PDMA_DstAddrConfig()" + - "PDMA_GetRemainBlkCnt()" + + Add the following API for ADC (HT32F652xx only). + - "ADC_ChannelDataAlign()" + - "ADC_ChannelOffsetValue()" + - "ADC_ChannelOffsetCmd()" + + Add the following API for OPA (HT32F652xx only). + - "OPA_SetUnProtectKey()" + - "OPA_ProtectConfig()" + + Update "OPA/OPA_Enable" example, add the un-protect key related functions. + + Update "FLASH_SetWaitState()" function, disable Pre-fetch and Branch Cache function before change + wait state. + + Fix "HT_ADC->OFR" define error of HT32F65232. + + Update "ht32_retarget.c", modify the retarget related functions for SEGGER Embedded Studio. + + Update following middleware. + "utilities/middleware/i2c_master.c/h" + "utilities/middleware/uart_module.c" + + Others + + Update comment, format, typing error, and coding style. + + Update and sync startup.s/system.c files. + + Change "HT_PWRCU->BAKPSR" to "HT_PWRCU->LDOSR" of HT32F57352. + + Fix "HT_AES->KEYR" define error (from KEYR[8] to KEYR[4] for AES128). + + Update "BFTM/OneShot" example, fix the register access sequence and time calculation formula. + + Update "TM/PWM/main.c", add "HTCFG_PWM_TM_RELOAD" check. + + Update "SLED/*" example, for fix error and coding style. + + Update "HT32F_DVB_PBInit()" of "ht32f5xxxx_board_01.c", add "LIBCFG_EXTI_4_7_GROUP" support. + + Update e-Link32 Pro/Lite Command line tool as "V1.18" ("utilities/elink32pro/eLink32pro.exe"). + + Change the project recommended minimum version of SEGGER Embedded Studio from V4.12 to V6.20. + +/*----------------------------------------------------------------------------------------------------------*/ +/* HT32_STD_5xxxx_FWLib_V1.1.1_5938 */ +/*----------------------------------------------------------------------------------------------------------*/ + Release Date: 2022-06-08 + + Main Changes + + Add new "TM/TriggerCounter_FrequencyMeasure" example. + + Add following middleware. + "utilities/middleware/spi_module.c" + "utilities/middleware/spi_module.h" + "utilities/middleware/spi_module_config_templet.h" + + Fixed FW library compatibility with ARM compiler version 6 of MDK-ARM V5.37. + - Add MDK-ARMv537 project template for MDK-ARM V5.37. + - Update "project_template/Script". Those MDK-ARMv537 project templates will be added for use if choose + the target IDE is "Keil MDK-ARMv5". The fixed files are as follows: + "Script/_CreateProjectScript.bat" + "Script/_ProjectConfig.bat" + "Script/_ProjectSource.bat" + - Update "core_cm0plus.h", fix compiler error. + - Update "SLED/ARGB_GetLEDNum", fix compiler warning. + - Update "FMC/FLASH_OperationNoHalt", fix the compiler issue of Arm Compiler Version V6.18 and the + compiler warning of linker script file. The fixed files are as follows: + "FLASH_OperationNoHalt/main.c" + "FLASH_OperationNoHalt/linker.lin" + - Update following middleware, remove STRCAT3 usage to fix compiler error. + "utilities/middleware/uart_module.c" + "utilities/middleware/i2c_master.c" + "utilities/middleware/spi_module.c" + + Update "ht32_retarget.c". Implement __write function to fix compiler error in IAR EWARM Version 9.20 + or later. + + Update GNU Arm makefile in the project_template, fix the compatibility issue that the makefile of GNU Arm + Version 11 cannot be compiled. + + Update EWARM in the project_template, fix the compiler error that header file path doesn't exist in + the file list of Workspace of IAR EWARM Version 7. + + Fix SPI initial PDMA parameter in the "utilities/common/spi_flash.c". + + Others + + Update comment, format, typing error, and coding style. + + Update e-Link32 Pro/Lite Command line tool as "V1.16" ("utilities/elink32pro/eLink32pro.exe"). + + Update the following examples to remove compiler warning of the IAR EWARM. + "BFTM/TimeMeasure" + "TM/PWMOut_PDMA_4CH" + "USBD/HID_Keyboard_Virtual_COM" + "USBD/USB_UAC_Sound" + "USBD/USB_Video" + "USBD/Virtual_COM" + + Update "TM/PWM" example, add the PWM channel initial function to "pwm.c". + + Update "WDT/Period_Reload" example, add WDT_ResetCmd function. + + Update and sync create project related files ("_ProjectConfig.bat", "_ProjectConfig.ini"). + + Update content of "project_template/IP/Example/readme.txt", add MDK-ARM V5.37 related information. + +/*----------------------------------------------------------------------------------------------------------*/ +/* HT32_STD_5xxxx_FWLib_V1.0.25_5831 */ +/*----------------------------------------------------------------------------------------------------------*/ + Release Date: 2022-04-19 + + Main Changes + + Add example support of BM53A367A. + + Add "LIBCFG_ADC_MVDDA" define, fix the issue that "ADC_MVDDACmd()" function is missing of HT32F50343. + + Update EEPROM Basic and EEPROM Emulation middleware, fix the include and define sequence. + "utilities/middleware/eeprom_basic.h" + "utilities/middleware/eeprom_emulation.h" + + Update UART Module middleware, add the "UARTM_IsTxFinished()" API. + "utilities/middleware/uart_module.c" + "utilities/middleware/uart_module.h" + + Others + + Update comment, format, typing error, and coding style. + + Update e-Link32 Pro/Lite Command line tool as "V1.0.15" ("utilities/elink32pro/eLink32pro.exe"). + +/*----------------------------------------------------------------------------------------------------------*/ +/* HT32_STD_5xxxx_FWLib_V1.0.24_5762 */ +/*----------------------------------------------------------------------------------------------------------*/ + Release Date: 2022-03-08 + + Main Changes + + Change to the new Holtek version format (Vm.n.r). + + Add following middleware. + "utilities/middleware/uart_module.c" + "utilities/middleware/uart_module.h" + + Add new "FMC/FLASH_OperationNoHalt" example. + + Modify "utilities/common/ring_buffer.c", fix the thread-safe issue of "Buffer_GetLength()". + + Others + + Update comment, format, typing error, and coding style. + + Update "startup_ht32fxxxxx_nn.s", support "USE_HT32_CHIP" define exist at startup.s and project Asm + setting in the same time (project's Asm Define has the higher priority). + +/*----------------------------------------------------------------------------------------------------------*/ +/* HT32_STD_5xxxx_FWLib_v023_5734 */ +/*----------------------------------------------------------------------------------------------------------*/ + Release Date: 2022-02-10 + + Main Changes + + Add new device support. + - MXTX6306 + + Rename previously "EXTI/GPIO_Interrupt" example to "EXTI/EXTI_Key_LED". + + Add new "EXTI/GPIO_Interrupt" example. + + Update the internal VREF level driver, add the missing voltage level setting/define for the HT32F542xx + series. + ADC_VREF_2V5 + ADC_VREF_3V0 + ADC_VREF_4V0 + ADC_VREF_4V5 + + Others + + Update comment, format, typing error, and coding style. + + Modify "bool, TRUE, FALSE" define way for C++/.cpp applications. + + Add warning message for the HT32F54241 SK ("ht32f54241_sk.h" and "ht32_board_config.h" of the related + examples). + + Simplify the following examples to use less IO/LED/KEY. + - "GPIO/InputOutput" + - "EXTI/EXTI_Key_LED" + + Update "utilities/common/spi_flash.c and spi_lcd.c", change the SPI Clock prescaler from 2 to 4 when the + Core clock is large than 48 MHz. + + Update "eLink32pro.exe" from v1.1.2 to v1.1.3. + + Update related middleware (eeprom_basic and eeprom_emulation). + + Update "ADC/InternalReferenceVoltage" example, add the voltage level setting of the internal VREF for + the 5V MCU. + +/*----------------------------------------------------------------------------------------------------------*/ +/* HT32_STD_5xxxx_FWLib_v022_5673 */ +/*----------------------------------------------------------------------------------------------------------*/ + Release Date: 2021-12-09 + + Main Changes + + Add new device support. + HT32F61141 + + Add new board support. + HT32F54241 DVB + HT32F54253 DVB + + Add new examples: + - "SYSTICK/DelayMicrosecond" + + Update "ht32fxxxxx_sk.h", "spi_lcd.c/.h", fix the GPIO Chip SEL define mistake which cause the H/W SPI SEL + not work of the following SK model. + HT32F50230, HT32F50241, HT32F52241, HT32F52253, HT32F52341, HT32F54241, HT32F65232, HT32F65240 + + Update "ht32f54241_sk.h" and "ht32f54253_sh.h", fix the COM port UART/Pin and SPI LCD BL typing error. + + Update "GNU_ARM/linker.ld", fix the heap/stack area overlap problem. + + Fix the following library configuration error of HT32F54241/54253. + Add: "LIBCFG_CKCU_PLLSRCDIV", "LIBCFG_PWRCU_PORF". + Remove: "LIBCFG_CMP" (HT32F54241 only, not support). + + Update "example/I2C/TouchKey/ht32_board_config.h", fix the typing error of I2C Port. + + Others + + Rename "LIBCFG_NO_PWRCU_PORF" to "LIBCFG_NO_PWRCU_VDDPORF". + + Update comment, format, typing error, and coding style. + + Update "example/LEDC/7-SegmentDigitalDisplay/main.c", change the frame rate from 40 Hz to 50 Hz. + +/*----------------------------------------------------------------------------------------------------------*/ +/* HT32_STD_5xxxx_FWLib_v021_5582 */ +/*----------------------------------------------------------------------------------------------------------*/ + Release Date: 2021-08-19 + + Main Changes + + Add example support of HT32F54241/54253. + + Update "SPI/Slave" example of HT32F52253, modify the SPI port and pin assignment from SPI1 to SPI0. + + Update "SPI/SEL_Software" example of HT32F52253, fix the typing error of SEL GPIO clock. + + Update "SPI/Master" example of HT32F52253. + - Fix the configuration typing error of "ht32_board_config.h". + - Modify the SPI port and pin assignment from SPI1 to SPI0. + + Others + + Update comment, format, typing error, and coding style. + + Update "_ProjectConfig*.bat" files. + + Update "RSTCU/Peripheral_Reset_Function" example, modify "HTCFG_LED0_RST" to "HTCFG_LED1_RST". + + Update "SPI/Slave" example, move the IRQHandler define from "ht32f5xxxx_01_it.c" to "ht32_board_config.h" + to reduce maintenance time. + + Add "LCD_SPI_RST_UNUSE" define for "ht32fxxxxx_sk.h" and "spi_lcd.c", to decide the "spi_lcd.c" controls + the LCD_RST pin or not. + + Update e-Link32 Pro Commander to V1.10. + +/*----------------------------------------------------------------------------------------------------------*/ +/* HT32_STD_5xxxx_FWLib_v020_5545 */ +/*----------------------------------------------------------------------------------------------------------*/ + Release Date: 2021-07-23 + + Main Changes + + Add new device support. + HT32F54231, HT32F54241 + HT32F54243, HT32F54253 + HT32F67741 + + Add "ht32_time.c/.h" to support following new functions for delay, time measure, and timeout. + "Time_Init()" + "Time_Delay()" + "Time_GetTick()" + + Add new examples: + - "GPIO/Input" + - "GPIO/Output" + - "Time/TimeFun" + - "Time/TimeFun_UserConf" + - "TM/PWMOut_PDMA_4CH" + - "USART/RS485_NMM_Slave" + + Add new definition, "FLASH_WAITSTATE_MAX". + + Fix the problem that "FLASH_BranchCacheCmd()" is not exist of HT32F0006, HT32F61352, and HT32F6135x. + + Fix the problem that "PWRCU_WakeupMultiPinCmd()", "PWRCU_WAKEUP_PIN_1" are not exist of HT32F50343. + + Fix typing error which cause the "I2C2_IRQn" missing (from "USE_HT32F2243_53" to "USE_HT32F52243_53"). + + Modify the following definition (CH4 to CH7 usually have the compare function only but the "TM_FLAG_CHnC" + definition is not compatible with the "TM_FLAG_CHnCC"). + "TM_FLAG_CH4C" to "TM_FLAG_CH4CC" + "TM_FLAG_CH5C" to "TM_FLAG_CH5CC" + "TM_FLAG_CH6C" to "TM_FLAG_CH6CC" + "TM_FLAG_CH7C" to "TM_FLAG_CH7CC" + + Modify "TM_GetCaptureCompare()" to support TM_CH4 ~ TM_CH7 for 8 channel PWM timer. + + Add "TM_GetCaptureCompare4()" ~ "TM_GetCaptureCompare7()" functions. + + Add "USART_PARITY_MARK" and "USART_PARITY_SPACE" for the UART parity mode. + + Update "example/I2C/Interrupt/main.c", fix the configuration error of I2C slave. + + Update following example, modify the default value of "gIsINEmpty" from TRUE to FALSE. The default value + TRUE may cause the F/W to not send CSW after the first Inquiry CBW Command in a specific condition. + "example/USBD/HID_Keyboard_Mass_Storage" + "example/USBD/Mass_Storage" + "example/USBD/Mass_Storage_IAP" + + Others + + Update comment, format, typing error, and coding style. + + Adjust and fix error of "LIBCFG_xxxxx" definition. + New: + "LIBCFG_FMC_PREFETCH", + Rename: + "LIBCFG_SINK_CURRENT_ENHANCED" to "LIBCFG_GPIO_SINK_CURRENT_ENHANCED" + "LIBCFG_WAKEUP_V01" to "LIBCFG_PWRCU_WAKEUP_V01" + "LIBCFG_CACHE" to "LIBCFG_FMC_BRANCHCACHE" + Remove: + "LIBCFG_ADC_INTERNAL_CH_V02", "LIBCFG_NO_FMC_PRE_FETCH", "LIBCFG_NO_FMC_WAIT_STATUS", + "LIBCFG_ADC_INTERNAL_CH_V03", "LIBCFG_ADC_INTERNAL_CH_DAC" + + Remove unnecessary functions, "PWRCU_WakeupPinIntConfig()" and "PWRCU_WakeupMultiPinIntConfig()". + + Remove unuse global variable "DelayTime" of "ebi_lcd.c" and "spi_lcd.c". + + Change the member order of the "I2C_InitTypeDef". + + Modify the "USART_StickParityCmd()" function to set the PBE bit by default when the command is ENABLE. + + Remove compiler warning of GNU by adding the dummy "if" usage of the unused parameter. + + Fix the case error of "HT32_Board" include path. + +/*----------------------------------------------------------------------------------------------------------*/ +/* HT32_STD_5xxxx_FWLib_v019_5358 */ +/*----------------------------------------------------------------------------------------------------------*/ + Release Date: 2021-05-11 + + Main Changes + + Add new examples: + - "ADC/OneShot_SWTrigger_ByTM" + - "CKCU/HSI_AutoTrim_By_LSE" + + Update startup/system files supported of specific MCU projects. + Old New + ------------------------- ------------------------- + - HT32F0006/HT32F61352 + system_ht32f0006.c to system_ht32f5xxxx_07.c + startup_ht32f5xxxx_xxx_01.s to startup_ht32f5xxxx_xxx_07.s + - HT32F52344/HT32F52354 + startup_ht32f5xxxx_01.s to startup_ht32f5xxxx_03.s + + Fix the problem of Flash API of HT32F50343 that the AHB clock of the GPIO port was not enable ,but the + drive current of SPI_MOSI is adjusted. The fixed item is as follows: + - The function "SPI_FLASH_Init()", It is in the "utilities/common/spi_flash.c". + - Add new define "#define FLASH_SPI_MOSI_CLK(CK) (CK.Bit.PB)", It is in the + "utilities/HT32_Board/ht32f50343_sk.h". + + Fixed the system was stuck in CKCU_HSIAutoTrimCmd() because of the misjudgment of CKCU_HSIAutoTrimIsReady(). + + Fixed the problem that the example CKCU/HSI_AUTO_Trim_BY_USB uses HSE(CKCU_PLLSRC_HSE) as the USB PLL + clock source. Change the USB PLL Clock source to HSI(CKCU_PLLSRC_HSI). + + Fix the CHIP ID error in all HT32F6135x projects. Fixed "USE_HT32_CHIP=10" to "USE_HT32_CHIP=17". + + Remove the interrupt capability of the DAC. Modify the file as follows: + - "example/DAC/Async_2CH/ht32f5xxxx_01_it.c"" + - "example/DAC/Async_2CH/main.c" + - "example/DAC/Sync_12bit_2CH/ht32f5xxxx_01_it.c" + - "example/DAC/Sync_12bit_2CH/main.c" + - "trunk/library/Device/Holtek/HT32F5xxxx/Include/ht32f5xxxx_01.h" + - "library/HT32F5xxxx_Driver/inc/ht32f5xxxx_dac.h" + - "library/HT32F5xxxx_Driver/src/ht32f5xxxx_dac.c" + + Others + + Update comment, format, typing error, and coding style. + + Update LIBCFG of SCTM. + - Add the new definition of LIBCFG for a specific MCU: + "#define LIBCFG_SCTM0 (1)" + "#define LIBCFG_SCTM1 (1)" + - Remove the definition of LIBCFG for a specific MCU: + "#define LIBCFG_NO_SCTM (1)" + - Update ht325xxxx_tm.c to depend on the new definitions LIBCFG_SCTM0 and LIBCFG_SCTM1. + + Update the version of eLink32pro.exe to 1.0.1.1. + + Update the following project setting: + - IAR EWARM v6/v7: Modify "_ht32_project_source.c" to "_ht32_project_source.h". + - SEGGER Embedded Studio: Add the new definition "arm_compiler_variant="SEGGER"". + + Remove redundant SCTM definition of 57331/57341. + +/*----------------------------------------------------------------------------------------------------------*/ +/* HT32_STD_5xxxx_FWLib_v018_5303 */ +/*----------------------------------------------------------------------------------------------------------*/ + Release Date: 2021-02-26 + + Main Changes + + Add "Create Project Configuration Menu" to choose the target IDE and Device when the first time to do the + create project operation of the example. The configuration file, "_CreateProjectConfig.bat" is saved to + the root path of the HT32 Firmware Library. You can reset the create project IDE/IC configuration anytime + by deleting the configuration file. + Target IDE/Compiler: + - Keil MDK-ARM v5 + - Keil MDK-ARM v4 + - IAR EWARM v8 + - IAR EWARM v6/v7 + - SEGGER Embedded Studio + - GNU [with Keil and GNU make] + - SourceryG++Lite [with Keil] + Target Device: + - xxxxx: Single Device + - xxx*: Series + + Add new examples: + - "ADC_24bit/Convert_Interrupt" + - "NVIC/Disable_Interrupt" + - "TM/InternalTrigger" + - "WDT/Auto_Enable" + + Add Flash programming function of GNU Maker (via e-Link32 Pro/Lite Commander). + "make IC=xxxxx eraseall" + "make IC=xxxxx program" + "make IC=xxxxx run" + + Update "CKCU_HSIAutoTrimCmd()" and "CKCU_HSIAutoTrimIsReady()" function to improve clock stability. + + Fix the cache address problem of "SDDISK_Read()" function. + "USBD/Mass_Storage/sd_disk.c" + + Update GNU project (*.uvprojx), fix the compile error when use new GNU Arm version + ("gcc-arm-none-eabi-10-2020-q2-preview-win32" or above). + + Fix Keil compiling error when disable both retarget and MicroLib. + + Update "ht32f1xxxx_01.h", fix the compatibility issue when user include "stdbool.h". + + Modify GNU compiler settings, output text file (disassembly) after building the code. + + Change the startup/system supporting files of specify MCU device. + Old New + ------------------------- ------------------------- + - HT32F0006/HT32F61352 + system_ht32f0006.c to system_ht32f5xxxx_07.c + startup_ht32f5xxxx_xxx_01.s to startup_ht32f5xxxx_xxx_07.s + - HT32F52344/HT32F52354 + startup_ht32f5xxxx_01.s to startup_ht32f5xxxx_03.s + + Add "HT32_FWLIB_VER" and "HT32_FWLIB_SVN" in "ht32f1xxxx_lib.h" for the version information of + HT32 Firmware Library. + Example: + "#define HT32_FWLIB_VER (018)" + "#define HT32_FWLIB_VER (5303)" + + Add new AFIO define in "ht32f1xxxx_gpio.h". + - "AFIO_FUN_MCTM0", "AFIO_FUN_MCTM1" + - "AFIO_FUN_GPTM0", "AFIO_FUN_GPTM1", "AFIO_FUN_GPTM2", "AFIO_FUN_GPTM3" + - "AFIO_FUN_PWM0", "AFIO_FUN_PWM1", "AFIO_FUN_PWM2", "AFIO_FUN_PWM3" + + Add following alias of MCTM IRQ handler + "#define MCTM0_IRQn MCTM0UP_IRQn" + "#define MCTM0_IRQHandler MCTM0UP_IRQHandler" + "#define MCTM1_IRQn MCTM1UP_IRQn" + "#define MCTM1_IRQHandler MCTM1UP_IRQHandler" + + Others + + Update comment, format, typing error, and coding style. + + Update "TM/PWM_Buzzer" example, move the buzzer function to "buzzer_pwm.c/.h". + + Update "_ProjectConfig*.bat" files. + + Add "Project Source File Setting" functions ("_ProjectSource.ini" and "_ProjectSource.bat"). + + Rename "_CreateProjectUSB.bat" as "_CreateProject.bat". + + Add dummy xxTM C files, to notify the user that SCTM/PWM/GPTM/MCTM timer use the "ht32f5xxxx_tm.c" driver. + "ht32f5xxxx_gptm.c", "ht32f5xxxx_pwm.c", "ht32f5xxxx_sctm.c" + + Add "IS_IPN_MCTM()" and "IS_IPN_GPTM" macro, for use to confirm the xxTMn is GPTM or MCTM. + + Update comment and board/pin configuration of "ADC/OneShot_TMTrigger_PDMA" example. + + Update and sync startup.s/system.c files. + +/*----------------------------------------------------------------------------------------------------------*/ +/* HT32_STD_5xxxx_FWLib_v017_5137 */ +/*----------------------------------------------------------------------------------------------------------*/ + Release Date: 2020-12-31 + + Main Changes + + Update IAR linker.icf, modify the ROM/RAM size. + + Add "LCDENS" related notice of "ht32f5xxxx_lcd.c/.h". + + Fix Keil compiling error when disable both retarget and MicroLib. + + Update "ht32f5xxxx_flash.c", fix the flash erase/program related flow. + + Others + + Update comment, format, typing error, and coding style. + + Update SPI chip select define and SPI configuration of "utilities/common/spi_lcd.c & spi_lcd.h". + + Add "BOARD_DISABLE_EEPROM" define of "utilities/common/i2c_eeprom.c". + + Add notice of VREF stable time and output function. + + Update create project script. + +/*----------------------------------------------------------------------------------------------------------*/ +/* HT32_STD_5xxxx_FWLib_v017_5074 */ +/*----------------------------------------------------------------------------------------------------------*/ + Release Date: 2020-11-08 + + Main Changes + + Add new device and example support. + HT32F65232, HT32F5828 + + Add "ADC_DualModeConfig()" API for the dual ADC mode of HT32F65230/65240. + + Add "ADC/OneShot_PWMTrigger_Dual_ADC" example. + + Update "startup_ht32f5xxxx_*_05.s" to support HT32F5828. + + Add "system_ht32f5xxxx_08.c" and "startup_ht32f5xxxx_*_08.s" for HT32F652xx series. + + Fix the FIFF/TIFN(Fsampling/Event) setting error of the following function and typedef of the + HT32F65230/65240. + "TM_CaptureInit()" + "TM_PwmInputInit()" + "TM_CHFDIV_Enum" + + Modify the function "MCTM_UpdateDisable()" to "MCTM_UpdateEventDisable" and add "MCTM_UEV1UD/MCTM_UEV1OD" + enum for HT32F65230/65240. + + Add OCR support and update CMP_INPUT_x define for HT32F65232. + + Rename "startup_ht32f65230_40.s" to "startup_ht32fxxxx_08.s" for HT32F652xx series. + + Rename "ht32f65230_40_opa.c/h" to "ht32f652xx_opa.c/h". + + Rename "ht32f65230_40_adc.c/h" to "ht32f652xx_adc.c/h". + + Add missing define of ADC_TRIG_XXXX and modify "ht32f652xx_adc.c/h" for support HT32F652xx series. + + Modify "ht32f5xxxx_rtc.c/h", use LIBCFG_LSE to disable "RTC_SRC_LSE", "RTC_LSECmd()", and + "RTC_LSESMConfig()". + + Remove un-support functions of HT32F5xxxx series. + "TM_EtiExternalClockConfig()" + "TM_EtiConfig()" + + Add missing enum, "TM_CKDIV_8" for HT32F652xx series. + + Add "MCTM_CHBRKCTRConfig2()" MCTM to support Break2 of HT32F652xx series. + + Add missing MCTM interrupt define of HT32F652xx series. + "MCTM_INT_CH0CD" + "MCTM_INT_CH1CD" + "MCTM_INT_CH2CD" + "MCTM_INT_CH3CD" + "MCTM_INT_OVER" + "MCTM_INT_UNDER" + + Others + + Update "system_ht32f5xxxx_04.c", remove unnecessary define. + + Update comment, format, typing error, and coding style. + + Add below notice of examples to inform the user to check the local structure variable without a + default value. + "Notice that the local variable (structure) did not have an initial value. + Please confirm that there are no missing members in the parameter settings below this function." + + Add "LIBCFG_EXTI_4_9_GROUP" define for the chip who supported extra EXTI interrupt channel. + + Update "MCTM_CHBRKCTRConfig()" function to keep "CHMOE" value. + +/*----------------------------------------------------------------------------------------------------------*/ +/* HT32_STD_5xxxx_FWLib_v016_4983 */ +/*----------------------------------------------------------------------------------------------------------*/ + Release Date: 2020-10-16 + + Main Changes + + Add new device and example support. + HT32F61355, HT32F61356, HT32F61357 + + Add new board support. + HT32F65240 Starter Kit + + Add more example support for HT32F65240 DVB. + + Add a new example. + "OPA/OPA_Enable" + + Change the default USB LDO setting from the enable mode to bypass mode. + + Update "SPI/FIFO_SEL_Hardware" example. Use timeout interrupt and RX_FIFO length to read the + corresponding data (Previously, it was fixed to read 4 bytes which may cause the data loss problem in + specific conditions). + + Update "CKCU/Clock_Configuration_LSI" example. Add wait for LSI clock ready before the system clock + source switches to LSI (Otherwise, the switching may fail). + + Update "SPI/Slave" example to fix missing EXTI interrupt service routine of HT32F52354. + + Modify "TM/PWM" example to output the complete PWM signal before stopping it. + + Update CMP driver, "ht32f5xxxx_cmp.c/h" and "ht32f65230_40_libcfg.h". Support new CMP function of + HT32F65230/65240. + + Update CMP example "CMP/ComparatorInterrupt" to support HT32F65230/65240 and improve readability. + + Remove "OFVCR" parameter of "HT_OPA_TypeDef" struct in the "ht32f5xxx_01.h". This register is not + supported by the HT32F65230/65240. + + Remove the following unnecessary API in the "ht32f65230_40_opa.c" and "ht32f65230_40_opa.h". + "void OPA_Config(HT_OPA_TypeDef* HT_OPAn, u32 mode, u32 cancellation)" + "void OPA_CancellationModeConfig(HT_OPA_TypeDef* HT_OPAn, u16 OPA_REF_INPUT)" + "void OPA_SetCancellationVaule(HT_OPA_TypeDef* HT_OPAn, u32 cancellation)" + "u32 OPA_GetCancellationVaule(HT_OPA_TypeDef* HT_OPAn)" + + Others + + Update comment, format, typing error, and coding style. + + Update "I2C/Interrupt/main.c" to improve readability. + + Add below notice into USB examples to inform the user turn on the HSI Auto Trim function when the PLL + clock source is HSI (PLL for USB 48 MHz clock). + "Msut turn on if the USB clock source is from HSI (PLL clock Source)" + + Remove the following unnecessary files. + "WDT/Period_Reload/ht32_board_config.h" + "FMC/FLASH_Write_Protection/ht32_board_config.h" + + Remove the remote wake-up function in the "USB_Video/main.c". + +/*----------------------------------------------------------------------------------------------------------*/ +/* HT32_STD_5xxxx_FWLib_v015_4909 */ +/*----------------------------------------------------------------------------------------------------------*/ + Release Date: 2020-08-11 + + Main Changes + + Add the following files to use e-Link32 Pro with SEGGER Embedded Studio. Refer to the + "readme e-Link32 Pro.txt" for how to use it. + "emStudiov4/readme e-Link32 Pro.txt" + "emStudiov4/Project_xxxxx.bat" + "emStudiov4/_MassErase.bat" + + Add QSPI support. + "ht32f5xxxx_spi.c". + "QSPI_QuadCmd()" + "QSPI_DirectionConfig()" + "utilities/common/spi_flash.c" + "SPI_FLASH_WriteStatus2()" + "QSPI_FLASH_BufferQuadRead()" + "QSPI_FLASH_BufferQuadReadByDMA()" + "QSPI_FLASH_BufferWrite()" + "QSPI_FLASH_BufferWriteByDMA()" + "utilities/HT32_Board" + "ht32f52367_sk.h" + "ht32f0006_dvb.h" + + Add new examples. + "TM/PWM" + "TM/UpdateEvent" + "QSPI/Flash_Quad_Mode_PDMA" + + Change the USB LDO default state from ON (PWRCU_VREG_ENABLE) to OFF (PWRCU_VREG_BYPASS) and + add below notice description. + "USB LDO Should be enabled (PWRCU_VREG_ENABLE) if the MCU VDD > 3.6 V." + + Change the driving current as 8 mA of LCD/SPI Flash utilities driver SPI pins for HT32F50343 (since the + default operation voltage of Starter Kit is 3.3 V). + + Add "SPI_FLASH_WaitForWriteEnd()" function in the end of the write status operation + ("SPI_FLASH_WriteStatus()"). + + Fix typing error of the define, "LIBCFG_MAX_SPEED" for HT32F52220/52230/52231/52241/52243/52253. + There are a few examples that refer to this value to set the IP-related frequency. + + Fix the I2S clock setting error of the following example. + "I2S/CodecLoopback_PDMA" + "USBD/USB_UAC_Sound" + "USBD/USB_UAC_Sound_RateControl" + + Add below notice of examples to inform the user to check the local structure variable without a + default value. + "Notice that the local variable (structure) did not have an initial value. + Please confirm that there are no missing members in the parameter settings below this function." + + Fix defined problem of "utilities/common/ebi_lcd.c". Change "EBI_FUN_BYTELAND" / "EBI_FUN_ASYNCREADY" to + "LIBCFG_EBI_BYTELAND_ASYNCREADY". + + Fix the "I2S_FIFOTrigLevelConfig()" error which did not clear the field of I2S FCR correctly. + + Fix "RPRE_MASK" define error for "RTC_SetPrescaler()" function. + + Add utilities drivers into HT32F0006/HT32F61352 project. + "i2c_eeprom.c" + "spi_flash.c" + "spi_lcd.c" + + Others + + Update comment, format, typing error, and coding style. + + Add below notice in the "FMC/FLASH_Security" example. + "The Option Byte will be write protected (cannot be changed again) after the + Security Protection is enabled. Refer to the user manual for details." + + Update and modify naming rule of the "HTCFG_xxxx" configuration define in the "ht32_board_config.h". + "I2S/CodecLoopback_PDMA" + + Update the following examples to remove compiler warning of the GNU compiler. + "SLED/ARGB_GetLEDNum" + "USART/PDMA" + + Add "-Waddress-of-packed-member" #pragma of below examples to remove compiler warning of the + GNU compiler. + "USBD/Mass_Storage" + "USBD/HID_Keyboard_Mass_Storage" + + Add the following notice in the Program/Erase related function. + "HSI must keep turn on when doing the Flash operation (Erase/Program)." + + Remove HSI disable setting of Configuration Wizard and add notice in the "system_xxxxx_nn.c". + +/*----------------------------------------------------------------------------------------------------------*/ +/* HT32_STD_5xxxx_FWLib_v014_4736 */ +/*----------------------------------------------------------------------------------------------------------*/ + Release Date: 2020-04-08 + + Main Changes - Modification & Improvement + + Add "USBDClass_Reset()" into the "USBD/*" example to reset related flag for the self-power application. + + Modify "ht32f5xxxx_aes.c", fix "AES_SetKeyTable()" and "_AES_CryptData()" functions who did not clear + related fields before set it. + + Update UxART related example, turn on internal pull up to prevent unknown state. + + Remove unnecessary RTC compare match restart setting of the "RTC/Calendar_BackupDomain" example. + (which cause the time not correct after entering the low power mode). + + Make up the init structure member when the XXXXX_InitTypeDef is a local variable (which without the + default value). For example, add the following code. + "MCTM_OutputInitStructure.AsymmetricCompare = 0;" + "OutInit.ControlN = TM_CHCTL_DISABLE;" + + Update "TM/InputCapture" example, fix the Pulse Width Count formula (shall be plus with 1). + + Fix RAM size from 8K to 16K of HT32F0006 (LIBCFG_RAM_SIZE). + + Update the following example to improve readability. + "ADC/AnalogWatchdog" + "ADC/Continuous_Potentiometer" + "ADC/Discontinuous_EXTITrigger" + "ADC/InternalReferenceVoltage" + "ADC/OneShot_PWMTrigger" + "ADC/OneShot_PWMTrigger_with_Delay" + "ADC/OneShot_TMTrigger_PDMA" + "ADC/Two_Group_MaxCH" + "EXTI/GPIO_Interrupt" + "HWDIV/DIV32" + "TM/InputCapture" + "TM/MatchOutputActive" + "TM/MatchOutputToggle" + "TM/PWM_Buzzer" + "TM/PWMInput" + "TM/PWMOut_PDMA" + "TM/SinglePulseMode" + "TM/TriggerCounter" + "USART/Interrupt" + "USART/Interrupt_FIFO" + "USART/PDMA" + "USART/Polling" + "USART/Retarget" + "USBD/HID_Demo" + "USBD/HID_DemoVendorReport" + + Main Changes - API Function & Compatibility + + Add "USART_GetIntStatus()" function to get the both enabled and occurred interrupt source. + + Remove the "I2C_Cmd()" in the "I2C_Init()" function since it shall be called after the I2C related + settings. User shall call the "I2C_Cmd()" by themself after the "I2C_Init()". + + Add "DR_8BIT", "DR_16BIT", and "DR_32BIT" define for the "HT_SLEDn" structure. + + Modify "ADC_RegularChannelConfig()", add the last variable-length argument for the code compatibility + between the general HT32 model and the specific model (with the independent sample & hold function of each + ADC channel). + "ADC_RegularChannelConfig(HT_ADC_TypeDef* HT_ADCn, u8 ADC_CH_n, u8 Rank, ...)" + + Modify the following MCTM IRQ define for compatibility. + Old New + ------------- ---------------- + MCTM_BRK_IRQn MCTM0_BRK_IRQn + MCTM_UP_IRQn MCTM0_UP_IRQn + MCTM_TR_UP2_IRQn MCTM0_TR_UP2_IRQn + MCTM_CC_IRQn MCTM0_CC_IRQn + GPTM_G_IRQn GPTM0_G_IRQn + GPTM_VCLK_IRQn GPTM0_VCLK_IRQn + + Modify "AFIO_FUN_ADC" as AFIO_FUN_ADC0. + + Add the following functions of "ht32f5xxxx_div.c". + "DIV_IsDivByZero()": Return the division by zero flag. + "DIV_uDiv32()": Do the 32-bit unsigned division. + "DIV_uGetLastRemainder()": Get remainder of last 32-bit unsigned division. + + Add "u64" definition. + + Add the following definition for convenience. + PDMACH0_IRQn ~ PDMACH5_IRQn + AFIO_FUN_MCTM0 + AFIO_FUN_GPTM0 ~ AFIO_FUN_GPTM3 + AFIO_FUN_PWM0 ~ AFIO_FUN_PWM3 + AFIO_FUN_SCTM0 ~ AFIO_FUN_SCTM3 + + Add "LIBCFG_MAX_SPEED" in the file "ht32fxxxxx_libcfg.h" which indicate the maximum core speed. + + Main Changes - New Example & Supporting + + Add new examples. + "BFTM/OneShot" + "BFTM/TimeMeasure" + "Mono_LCD/LCD_module" (for ESK32-A3A31 mono LCD module) + "SLED/ARGB_GetLEDNum" + "USBD/HID_DemoVendorReport" + + Add example support of HT32F65230/65240 + ADC, BFTM, CRC, EXTI, FMC, GPIO, HWDIV, NVIC, PDMA, PWRCU, RSTCU, RTC, SWDIV, SYSTICK, TM, WDT + + Rename examples as below. + IP Old Name New Name + -------- -------- -------- + ADC EXTITrigger_DiscontinuousMode Discontinuous_EXTITrigger + ADC PDMA_ADCResult OneShot_TMTrigger_PDMA + ADC Potentiometer_ContinuousMode Continuous_Potentiometer + ADC TM_Trigger OneShot_PWMTrigger + ADC TM_Trigger_with_Delay OneShot_PWMTrigger_with_Delay + QSPI Flash Flash_Quad_Mode + TM PWMOutput PWM_Buzzer + USART HyperTerminal_TxRx Retarget + USART HyperTerminal_TxRx_Interrupt Interrupt + USART HyperTerminal_TxRx_Interrupt_FIFO Interrupt_FIFO + Mono_LCD 8CHAR_14SEG_Demo Demo + + Others + + Update comment, format, typing error, and coding style. + + Update and modify naming rule of the "HTCFG_xxxx" configuration define in the "ht32_board_config.h". + + Update "ht32_series.c/h" and "ht32_retarget_usbdconf.h" to improve the compatibly of the + terminal software. + + Add ring buffer support of the "Virtual_COM" and "HID_Keyboard_Virtual_COM" examples. + + Fix interrupt mode of UxART retarget, remove unnecessary FIFO/interrupt configuration of the + retarget function. + + Update "system_ht32fxxxxx_nn.c" (coding style only). + +/*----------------------------------------------------------------------------------------------------------*/ +/* HT32_STD_5xxxx_FWLib_v013_4429 */ +/*----------------------------------------------------------------------------------------------------------*/ + Release Date: 2019-12-05 + + Main Changes + + Update "USBD/Virtual_COM" example, add ZLP process for BULK transfer. + + Fix memory size error of HT32F65230. + + Modify "ht32f65230_40_libcfg.h", fix the "USE_MEM_HT32F65230" define problem of HT32F65230. + + Others + + Fix typing error of ""USBD/HID_Keyboard_Virtual_COM" example. + +/*----------------------------------------------------------------------------------------------------------*/ +/* HT32_STD_5xxxx_FWLib_v013_4425 */ +/*----------------------------------------------------------------------------------------------------------*/ + Release Date: 2019-11-29 + + Main Changes + + Add new device support. + HT32F65230 + + Changes for HT32F65230 and HT32F65240 + Change USE_HT32F65240 to USE_HT32F65230_40. + Rename "startup_ht3265240_xxx.s" to "startup_ht3265230_40_xxx.s". + + Update "HID_Demo_UI.exe" to support HID Report ID. + + Add "USBD/HID_DemoVendorReport" example. + + Add UART0_IRQn ~ UART3_IRQn define for HT32F52357/52367 (map to UART0_UART2_IRQn and UART1_UART3_IRQn). + + Add "RETARGET_UxART_BAUDRATE" setting to change the retarget UART baudrate in "ht32f5xxxx_conf.h". + + Add "RETARGET_HSI_ATM" setting to turn on/off the auto-trim function of HSI. + + Add "RETARGET_DEFINE_HANDLER" setting to remove the UxARTn_IRQHandler() define of the retarget. + This setting is used for the model who grouping two UART Interrupt into one vector. + + Add non-block mode of USB Virtual-COM retarget function ((Drop data if USB or terminal software is + not ready). + + Fix EXTI4_IRQn ~ EXTI15_IRQn define error of HT32F65230/65240. + + Add SWCLK toggle of "GPIO_DisableDebugPort()" function. + + Others + + Add "USAGE_PAGE_L" define of "USB/HID_Demo" example. + + Add "UART0_UART2_IRQHandler()" and "UART1_UART3_IRQHandler" example in the file "ht32f5xxxx_01_it.c" for + HT32F52357/52367. + + Update format and coding style. + +/*----------------------------------------------------------------------------------------------------------*/ +/* HT32_STD_5xxxx_FWLib_v012_4285 */ +/*----------------------------------------------------------------------------------------------------------*/ + Release Date: 2019-10-18 + + Main Changes + + Add new device support. + HT32F50343, HT32F59041, HT32F59741, HF5032 + + Fix HT32F65240 IRQ number error of "USART0_IRQn" and "UART0_IRQn". + + Fix "ADC_CH_GND_VREF" and "ADC_CH_VDD_VREF" define error of HT32F65240. + + Add "GPIO_GetID()" function to convert the HT_GPIOx to GPIO_Px. + + Add "LIBCFG_PWRCU_NO_PORF" define of HT32F65240 to fix the "PWRCU_DeInit()" function not work. + + Update "system_ht32fxxxxx.c" and "startup_ht32fxxxxx_xx_nn.s". + + Rename "startup_ht32f5xxxx_01/02.s" of IAR as "startup_ht32f5xxxx_iar_01/02.s". + + Move the "common/*.h" include from the begin to the end (after the pin define) in the file + "HT32_Board/ht32fxxxx_sk/dvb.h". The original include way leads to the pin define lost when you + use the EBI_LCD->EBI_LCD_RAM outside the "ebi_lcd.c". + + Update "ebi_lcd.c", fix LCD_SPI_BL_GPIO_XXX define error (shall be LCD_EBI_BL_GPIO_XXX). + + Fix error of "_CreateProjectScript.bat" which cause the stack size and RW base can not be set by the + "_ProjectConfig.bat" of the emStudiov4 project. + + Others + + Remove the wrong define, "LIBCFG_CKCU_USB_PLL_96M" of HT32F52367. + + Add calculation method of PLL clock in the file, "system_ht32f5xxxx_nn.c". + + Add "utilities/common/lcd.h" to put the lcd related register together. + + Update example to improve readability. + +/*----------------------------------------------------------------------------------------------------------*/ +/* HT32_STD_5xxxx_FWLib_v011_4188 */ +/*----------------------------------------------------------------------------------------------------------*/ + Release Date: 2019-08-05 + + Main Changes + + Add new device support. + HT32F57331, HT32F57341, HT32F57342, HT32F57352, HT32F52357, HT32F52367, HT32F52142, + HT32F65240, HT32F61352, HT50F32002, HT50F32003 + + Fix define error of "ht32fxxxxx_libcfg.h". + + Update "system_ht32fxxxxx.c" and "startup_ht32fxxxxx_xx_nn.s". + + Rename "startup_ht32f5xxxx_nn.s" of IAR as "startup_ht32f5xxxx_iar_nn.s". + + Modify ADC related define (The left side old one is still kept for backward compatible). + HT_ADC -> HT_ADC0 + ADC -> ADC0 + ADC_IRQn -> ADC0_IRQn + + Fix typing error of the function name below. + SPI_GUARDTCmd(), SPI_GUARDTConfig() + + Others + + Update content of "readme.txt". + + Add s64 ("typedef signed long long s64;"). + + Update comment and coding style. + + Update and sync "ht32f5xxxx_conf.h". + + Update and sync create project related files ("_ProjectConfig.bat", "_CreateProjectScript.bat"). + + Update "HT32F5xxxx_01_DebugSupport.ini". + + Update "ht32_op.s" and "ht32_op.c". + +/*----------------------------------------------------------------------------------------------------------*/ +/* HT32_STD_5xxxx_FWLib_v010_3748 */ +/*----------------------------------------------------------------------------------------------------------*/ + Release Date: 2019-04-09 + + Main Changes + + Update functions of "ht32f5xxxx_dac_dual16.c". + + Update Create Project script, add Script folder in project_template. + + Fix VREFCR/VREFVALR register address error of HT_ADC_TypeDef. + + Fix "ADC_VREFConfig()" error (ADC_VREF_x shift error). + + Add "ADC_MVDDACmd()" function. + + Add "PWRCU_DeepSleep2Ex()" function for the case which wakeup by EXTI in the short time or the wakeup + source keeps active. + Notice: PWRCU_DeepSleep2Ex() function will affect the accuracy of RTC for the date/time application. + + Add "TM/TriggerCounter" example. + + Add "ADC/InternalReferenceVoltage" example. + + Update "ADC/Potentiometer_ContinuousMode" example, remove division in the ISR of ADC. + + Others + + Update "ht32f5xxxx_usbd.c" and "ht32_usbd_core.c", add Force USB Reset Control function (apply to specific + model only). + + Update/sync startup.s/system.c files, fix PLL range and content errors. + + Update "BootProcess" function. + + Update/sync "ht32_op.s" and "ht32_op.c". + + Update "PWRCU/DeepSleepMode1" examples, fix compile error when set "DISABLE_DEBUG_PIN" = 1. + + Update "PWRCU/PowerDownMode" examples + - Update EXTI ISR to reduce maintenance time. + - Add "DISABLE_DEBUG_PIN" function. + + Update/sync "FlashMacro.mac". + + Update Keil after build setting + - Add double quotes (") in the command. + - Change filename keyword from "#L" to "!L" (relative path specification to the current folder). + - Update "fromelf.txt" and "objcopy.txt" + +/*----------------------------------------------------------------------------------------------------------*/ +/* HT32_STD_5xxxx_FWLib_v009_3383 */ +/*----------------------------------------------------------------------------------------------------------*/ + Release Date: 2019-02-12 + + Main Changes + + Add SEGGER Embedded Studio IDE support (beta version). + + Update "EXTI/WakeUp_DeepSleepMode1" Example, fix channel error of EXTI clear wakeup flag and add LED3 + (for some SK have only LED2 and LED3 on board). + + Others + + Update comment and coding style. + + Add "USBD/USB_UAC_Sound_RateControl" Example. + + Add "USBD/HID_Keyboard_Mass_Storage" Example. + + Update utilities/common/spi_flash.c/h", change the way of HT_PDMA define. + + Update HT32F0006 MDK-ARM project related files (uvproj*). fix SRAM size. + + Update "LIBCFG_DAC" as "LIBCFG_DACDUAL16" for HT32F0006. + + Add "LIBCFG_DACDUAL16" define for "ht32f5xxxx_dac_dual16.h" of "ht32f5xxxx_lib.h". + + Fix missed "I2C2_IRQHandler" and "AES_IRQHandler" in "startup_ht32f5xxxx_01.s" files (both MDK-ARM and + EWARM). + +/*----------------------------------------------------------------------------------------------------------*/ +/* HT32_STD_5xxxx_FWLib_v008_3322 */ +/*----------------------------------------------------------------------------------------------------------*/ + Release Date: 2018-12-17 + + Main Changes + + Fix filename error of IAR EWARM and GNU make file ("ht32f5xxxx_dac_dual16.c"). + + Others + + Update "startup_ht32f5xxxx_xxxx.s". + +/*----------------------------------------------------------------------------------------------------------*/ +/* HT32_STD_5xxxx_FWLib_v008_3314 */ +/*----------------------------------------------------------------------------------------------------------*/ + Release Date: 2018-12-12 + + Main Changes + + Add new device support. + HT32F0006 + + Modify Control IN/OUT method of USB Core, to fix USB transfer problem when CPU in the lower speed or late + USB interrupt case. + + Add workaround for PDMA CH3 issue (Interrupt Enable bit of CH3 is not work). + + Modify "CKCU_ATC_EXT_PIN" as "CKCU_ATC_CKIN". + + Others + + Fix typing error of MCTM. + + Add "LIBCFG_ipname" define to the IP channel of "ht32f5xxxx_pdma.h". + + Add "USBD_DisableDefaultPull()" function to disable pull resistance when the USB is not use. + + Update comment and coding style. + + Rename RTC example as below. + "Calendar" -> "Time" + "Calendar_backup_Domain" -> "Time_BackupDomain" + + Add new example, "RTC/Calendar_BackupDomain". + + Update "EXTI/WakeUp_DeepSleepMode1" example. + +/*----------------------------------------------------------------------------------------------------------*/ +/* HT32_STD_5xxxx_FWLib_v007_3076 */ +/*----------------------------------------------------------------------------------------------------------*/ + Release Date: 2018-09-30 + + Main Changes + + Update HardFault_Handler of "ht32f5xxxx_01_it.c",add the debug instruction and system reset. + + Update AES examples, add zero init of local Struct (AES_InitTypeDef AES_InitStruct). + + Add "__HT_check_sp" and "__HT_check_heap" symbol into startup.s and watchpoint command into + "HT32F5xxxx_01_DebugSupport.ini" for debug stack/heap underflow, overflow, and overwrite. + + Add GNU Make support of GNU Arm compiler. + + Add 52354 IAR project files into "project_template/IP/Template_USB". + + Add "LIBCFG_ADC_INTERNAL_CH_V02" define to fix the "ADC_CH_GNDREF/ADC_CH_VREF" mismatch of HT32F502xx + Series (The ADC input channel number of analog ground/power is different between HT32F502xx and other + series). + + Update "USBD/HID_Keyboard_Joystick" and "USBD/HID_Mouse" example, change the set flag sequence + (before USBDCore_EPTWriteINData). + + Others + + Add "objcooy.txt" which shows how to use obj tools of GNU Arm compiler. + + Update format and coding style. + +/*----------------------------------------------------------------------------------------------------------*/ +/* HT32_STD_5xxxx_FWLib_v007_2962 */ +/*----------------------------------------------------------------------------------------------------------*/ + Release Date: 2018-08-02 + + Main Changes + + Add GNU Arm compiler support. + - Add project_template related files + - "startup_ht32f5xxxx_gcc_nn.s" + - "linker.ld" (link script) + + Fix typing error of "ht32f52230_sk.h" file. + "COM1_IRQHandler" shall be "UART0_IRQHandler". + + Fix startup.s error of IAP example which cause UART not work. + + Rename "CreatProject.bat" to "_CreateProject.bat" and update its content. + + Update "ht32f5xxxx_tm.c/.h", add following functions which have TM_CH_n parameter. + void TM_ForcedOREF(HT_TM_TypeDef* TMx, TM_CH_Enum TM_CH_n, TM_OM_Enum ForcedAction) + void TM_SetCaptureCompare(HT_TM_TypeDef* TMx, TM_CH_Enum TM_CH_n, u16 Cmp) + void TM_SetAsymmetricCompare(HT_TM_TypeDef* TMx, TM_CH_Enum TM_CH_n, u16 Cmp) + u32 TM_GetCaptureCompare(HT_TM_TypeDef* TMx, TM_CH_Enum TM_CH_n) + + Others + + Fix compile error when turn on Library debug mode (HT32_LIB_DEBUG = 1). + + Fix compile warning/error of GNU Arm compiler. + +/*----------------------------------------------------------------------------------------------------------*/ +/* HT32_STD_5xxxx_FWLib_v006_2891 */ +/*----------------------------------------------------------------------------------------------------------*/ + Release Date: 2018-07-14 + + Main Changes + + None + + Others + + Add "USBD/HID_Keyboard_Virtual_COM" example. + + Add "ADC/Two_Group_MaxCH" example. + +/*----------------------------------------------------------------------------------------------------------*/ +/* HT32_STD_5xxxx_FWLib_v006_2863 */ +/*----------------------------------------------------------------------------------------------------------*/ + Release Date: 2018-06-11 + + Main Changes + + Add new device support. + HT32F52344, HT32F52354 + + Add DMA support of "utilities/common/spi_flash.c". + + Add missed function prototype declaration of "GPIO_SinkConfig()" in "ht32f5xxxx_gpio.h". + + Add "EXTI_GetEdgeFlag()" function. + + Add LIBCFG_AES_SWAP function to process endian issue of AES. + + Others + + Update project and "ht32f5826_libcfg.h" typing error of HT32F5826. + + Fix "LIBCFC_CKCU_USB_PLL" typing error of ht32fxxxx_libcfg.h and example code (shall be LIBCFG_CKCU_USB_PLL). + + Add LED3 toggle of "//project_template/IP/Example" since HT32F52253 Starter Kit using LED2 and LED3. + + Fix compiler error of "USBD/USB_UAC_Sound" Example. + + Remove unnecessary define "LIBCFG_CKCU_INTERRUPT_FLAG_V01". + + Update ht32_op.s and ht32_op.c (improve readability). + + FIx memory size typing error of HT32F0008 project. + + Add LIBCFG_FMC_CMD_READY_WAIT define to insert NOP after ISP command for specific model. + + Update USB's example, driver, an setting related to the LIBCFG_CKCU_USB_PLL_96M. + + Update comment and coding style. + + Add MDK_ARMv5 project of IAP example. + + Fix HT32F52352 IAP_PPBIT define error of "IAP/IAP_UI" example. + + Change buffer size of "IAP/IAP_UI" example for the MCU runs on the slower speed. + + Update "USBD/Mass_Storage" example. + + Update "ht32f5xxxx_ckcu.c" to remove unnecessary register write of PLL. + + Update "EXTI/GPIO_Interrupt" example to reduce maintenance effort. + + Update "ht32f52352_sk.h", "ht32f52354_sk.h", and "ebi_lcd.h" to support EBI 8-bit mode with SPI dual output. + +/*----------------------------------------------------------------------------------------------------------*/ +/* HT32_STD_5xxxx_FWLib_v006_2687 */ +/*----------------------------------------------------------------------------------------------------------*/ + Release Date: 2018-04-12 + + Main Changes + + Add SourceryG++Lite compiler support. + - Add project_template related files + - "startup_ht32f5xxxx_cs3_nn.s" + - "linker.ld" (link script) + + Fix typing error of "Project_50241.uvproj" files. + + Others + + Update "ht32f5xxxx_conf.h" for AUTO_RETURN (\r) option. + + Update "ht32f5xxxx_div.h" to remove compiler error of SourceryG++Lite compiler. + +/*----------------------------------------------------------------------------------------------------------*/ +/* HT32_STD_5xxxx_FWLib_v005_2639 */ +/*----------------------------------------------------------------------------------------------------------*/ + Release Date: 2018-02-28 + + Main Changes + + Add "I2C_SpeedOffset" parameter of "I2C_InitTypeDef" struct to reach real I2C speed. + + Add "CKCU/HSI_AutoTrim_By_USB" Example. + + Add "USBD/HID_Keyboard_Joystick" Example. + + Update "CKCU_HSIAutoTrimIsReady" function of "ht32f5xxxx_ckcu.c". + + Others + + Update SPI/PDMA example to support HT32F52243/52253. + + Add "I2C_SpeedOffset" parameter of I2C related examples. + + Update "i2c_eeprom.c" to remove warning on specify compiler. + + Modify EXTI related code of "USBD/HID_Keyboard" Example to reduce maintenance effort. + +/*----------------------------------------------------------------------------------------------------------*/ +/* HT32_STD_5xxxx_FWLib_v005_2481 */ +/*----------------------------------------------------------------------------------------------------------*/ + Release Date: 2017-12-30 + + Main Changes + + None + + Others + + Update I2S and USB UAC related examples (Coding style and remove unuse define). + + Fix I2S setting of "USB_UAC_Sound" example. + + Fix define error of "PWRCU/DeepSleepMode1" example. + +/*----------------------------------------------------------------------------------------------------------*/ +/* HT32_STD_5xxxx_FWLib_v005_2470 */ +/*----------------------------------------------------------------------------------------------------------*/ + Release Date: 2017-12-29 + + Main Changes + + Add new device support. + HT32F50231, HT32F50241 + Note: The examples of HT32F50220, HT32F50230, HT32F50231, HT32F50241 are under test. Please contact us if + any question. Thanks. + + Update boot related functions of "startup_ht32f5xxxx_nn.s" and "system_ht32f5xxxx_nn.c". + + Fix USB example code which forget to turn on USB PLL of HT32F0008. + + Update IAP example to support HT32F0008. + + Add "GPIO_DisableDebugPort()"" function to disable SWD function. + + Add "GPIO_SinkConfig()" function for sink current configuration (Apply to specific model only). + + Update "ht32_op.c" and "ht32_op.s" to support enable WDT function by Flash Option byte (Apply to specific + model only). + + Add "Clock_Configuration_LSI" example to show how to configure the system clock between High Speed + (PLL, HSI, or HSE) and LSI. + + Others + + Fix errors of following examples (related to the MCU we added recently). + "EXTI/GPIO_Interrupt" + "PWRCU/BOD_LVD" + "PWRCU/PowerDownMode" + "RAND/Random_Number" + "SPI/Slave" + "TM/MatchOutputToggle" + "TM/PWMOut_PDMA" + "TM/PWMOutput" + "TM/SinglePulseMode" + "USART/HyperTerminal_TxRx_Interrupt_FIFO" + "USART/PDMA" + + Fix "LIBCFG_CHIPNAME" typing error of HT32F50220/50230. + + Remove useless "RTC_LSICmd()"" function. + + Update "RTC_LSILoadTrimData()" to prevent hardfault if RTC clock is not enabled when calling this function. + + Update typing error and coding style of "ht32f5xxxx_ckcu.h". + + Change pin assignment of HT32F0008's example. + +/*----------------------------------------------------------------------------------------------------------*/ +/* HT32_STD_5xxxx_FWLib_v005_2267 */ +/*----------------------------------------------------------------------------------------------------------*/ + Release Date: 2017-11-30 + + Main Changes + + Add new device support. + HT32F0008 + HT32F50220, HT32F50230 + + Others + + Update "ht32_virtual_com.inf" file, add Digital Signature. + + Update "ht32_usbd_core.c/.h", add vendor request call back capability. + + Fix compiler warning when turn on library debug mode. + + Fix IAR project setting of IAP related examples (Output format). + +/*----------------------------------------------------------------------------------------------------------*/ +/* HT32_STD_5xxxx_FWLib_v004_1996 */ +/*----------------------------------------------------------------------------------------------------------*/ + Release Date: 2017-10-19 + + Main Changes + + Update "system_ht32F5xxxx_03.c", modify PLL related setting. + + Change "LIBCFG_WP_2PAGE_PER_BIT" to "LIBCFG_FLASH_2PAGE_PER_WPBIT". + + Others + + Update "PWRCU/DeepSleepMode2" example, fix compiler error when DISABLE_DEBUG_PIN = 1. + + Update "WDT/Period_Reload" example, fix comment typing error. + + Add "LIBCFG_CHIPNAME" define. + + Update project setting. + + Update "NVIC/External_Interrupt" example, remove unuse define. + +/*----------------------------------------------------------------------------------------------------------*/ +/* HT32_STD_5xxxx_FWLib_v004_1790 */ +/*----------------------------------------------------------------------------------------------------------*/ + Release Date: 2017-09-05 + + Main Changes + + Fix vector table error ("startup_ht32f5xxxx_01.s"). + + Others + + Update "system_ht32f5xxxx_xx.c". + + Update Keil project setting, enable "User->After Build Run #1" as default value to output Binary file. + +/*----------------------------------------------------------------------------------------------------------*/ +/* HT32_STD_5xxxx_FWLib_v004_1753 */ +/*----------------------------------------------------------------------------------------------------------*/ + Release Date: 2017-08-31 + + Main Changes + + Rename "HT32F520xx_FWLib" to "HT32_STD_5xxxx_FWLib" and "520xx" to "5xxxx". + The following files are also renamed. + Old New + ====================================== ====================================== + startup_ht32f520xx_01.s startup_ht32f5xxxx_01.s + system_ht32f520xx_01.c system_ht32f5xxxx_01.c + system_ht32f5xxxx_02.c system_ht32f5xxxx_02.c + ht32f520xx_01_it.c ht32f5xxxx_01_it.c + ht32f523xx_01_usbdconf.h ht32f5xxxx_01_usbdconf.h + ht32f520xx_01_conf.h ht32f5xxxx_conf.h + HT32F520xx_01_DebugSupport.ini HT32F5xxxx_01_DebugSupport.ini + ht32f520xx_sk.c ht32f5xxxx_board_01.c + ht32f520xx_01.h ht32f5xxxx_01.h + + Others + + Update "ht32_usbd_core.c" to support vendor function. + + Add "USE_MEM_HT32F5xxxx" define into project. + + Add "USE_MEM_HT32F5xxxx" default define into "ht32f5xxxx_xx_libcfg.h". + + Update the IAP Example. Change IAP loader size from 3 KBytes to 4 KBytes (Since the code size of IAP + example for IAR EWARM is large than 3 KB). + + Add new device support + HT32F5826 + +/*----------------------------------------------------------------------------------------------------------*/ +/* HT32F520xx_FWLib_v003_1661 */ +/*----------------------------------------------------------------------------------------------------------*/ + Release Date: 2017-07-27 + + Main Changes + + Add hardware divider driver, "ht32f520xx_div.c/h" + + Update following example to support HT32F52243 and HT32F52253. + DIV, IAP, SPI, TM + Note: The code size of IAP example for IAR EWARM is large than 3 KB. It over Reserved size of the IAP + area. We will update it in the next version. + + Others + + Update project related file and setting. + + Modify USB/Mass_Storage example for WIN10 compatibility issue. + + Update "ht32_op.c" and "ht32_op.s", add CK_CODE/CK_DATA/CK_CODEOP in Option Bytes (same format with e-Writer32). + +/*----------------------------------------------------------------------------------------------------------*/ +/* HT32F520xx_FWLib_v003_1566 */ +/*----------------------------------------------------------------------------------------------------------*/ + Release Date: 2017-07-17 + + Main Changes + + Fix COM1 & BUZZER setting error of "ht32f52253_sk.h". + + Update following example to support HT32F52243 and HT32F52253. + ADC, I2C + + Others + + Update ht32_op.s and ht32_op.c + +/*----------------------------------------------------------------------------------------------------------*/ +/* HT32F520xx_FWLib_v003_1534 */ +/*----------------------------------------------------------------------------------------------------------*/ + Release Date: 2017-07-03 + + Main Changes + + Add new device support + HT32F52243, HT32F52253 + Note: The following example is not supported yet for the HT32F52243 and HT32F52253. + ADC, DIV, I2C, IAP, SPI, TM + + Add IAR EWARMv8 project template (create by IAR EWARM v8.11). + + Update "system_ht32f520xx_01.c" and "system_ht32f520xx_02.c" to support different setting between + IAP and AP. + + Fix "ht32_retarget.c" error (UxART Rx interrupt is no need to turn on). + + Update UxART driver to sync with HT32_STD_1xxxx FW Library. + + Modify following variable name of "MCTM_CHBRKCTRInitTypeDef". + Break -> Break0 + BreakPolarity -> Break0Polarity + + Others + + Update project related file and setting. + + Upgrade the version of IAR EWARM project template from v6.20 to v6.50. + Note: + 1. Supported CMSIS-DAP: IAR EWARM v6.50 and above. + 2. RDI/e-Link32 is not supported anymore from the v8.xx of IAR EWARM. + 3. For the Cortex-M0+, you must use IAR EWARM v6.40 and above. + + Update file format and coding style. + + Modify "EXTI_DebounceCnt" of "EXTI_InitTypeDef" from u32 to u16, to prevent count setting over range. + +/*----------------------------------------------------------------------------------------------------------*/ +/* HT32F520xx_FWLib_v002_1320 */ +/*----------------------------------------------------------------------------------------------------------*/ + Release Date: 2017-05-04 + + Main Changes + + Fix IAR compiler failed issue of "ht32_cm0plus_misc.c" (Tool Internal Error with Access violation error). + + Others + + Fix config error of ADC example, "PWMTrigger_OneShotMode". + + Rename ADC example "PWMTrigger_OneShotMode" as "TM_Trigger". + + Add ADC example, "TM_Trigger_with_Delay". + + Fix I2C register naming (ADDBR to ADDSR). + + Fix build error when Library Debug mode enable. + + Fix IAP example, add "USART_ClearFlag(HTCFG_UART_PORT, USART_FLAG_TOUT)" in the UART ISR. + + Fix SPI Flash dual read, enable dual read function (SPI_DUALCmd()) before send dummy bytes. + +/*----------------------------------------------------------------------------------------------------------*/ +/* HT32F520xx_FWLib_v002_1143 */ +/*----------------------------------------------------------------------------------------------------------*/ + Release Date: 2016-10-11 + + Main Changes + + Fix FLASH_WP_ALLPAGE_SET macro error. + + Add memory footprint information (ht32fxxxxx_xx_libcfg.h). + + Others + + Update typing error and naming rule. + + Update "ht32f520xx_02.h" variable data type define to prevent data type confusion (such as const s32 not + equal to sc32). + + Modify Re-target to USB Tx buffer size from 63 to 1. Add notice message for SERIAL_Flush() when Tx buffer + size is lager than 1. + + Update MDK_ARMv5 project setting. + +/*----------------------------------------------------------------------------------------------------------*/ +/* HT32F520xx_FWLib_v002_966 */ +/*----------------------------------------------------------------------------------------------------------*/ + Release Date: 2016-08-17 + + Main Changes + + Add "CKCU_HSIAutoTrimIsReady()" functions. + + Fix Re-target USB virtual bug (Bulk out 64 Bytes without zero length OUT is not allow). + + Add example code. + + Update IAR EWARM project of example codes. + + Add random number function/example. + + Others + + Rename and update "HT32_Virtual_COM.inf". Add VID/PID for e-Link32Pro USB to UART function. + + Update pin assignment of HT32F52341 SPI/Master example. + + Fix "CKCU_GetClocksFrequency()" and "CKCU_GetPLLFrequency()" error. + + Update typing error and naming rule. + + Fix USB descriptor error of "ht32_retarget_desc.h". + + Fix CKCU/Clock_Configuration example error (CKOUT pin). + +/*----------------------------------------------------------------------------------------------------------*/ +/* HT32F520xx_FWLib_v002_820 */ +/*----------------------------------------------------------------------------------------------------------*/ + Release Date: 2016-06-20 + + Main Changes + + Fix IAP_Text_RAM example setting error. + + Fix "_USBD_CopyMemory()" error. + + Fix EXTI init sequence of HT32F_DVB_PBInit() which may cause unexpect EXTI interrupt. + + Fix LIBCFG_WP_2PAGE_PER_BIT define error of HT32F52331/41. + + Add project files of MDK_ARMv5 (*.uvprojx), select CMSIS-DAP debug adapter as default setting. + + Others + + Fix IAR scanf not work issue + + Add UART interrupt mode for Re-target. + + Improve efficiency of USB re-target (USB IN). + + Modify uIsTerminalOpened check method. + + Fix Re-target to USB bug (OUT data overrun the Rx buffer). + + Remove unnecessary divide/mod operation ("ring_buffer.c", "ht32_serial.c"). + + Remove unnecessary code of "ht32f520xx_tm.c". + + Fix Buffer_GetLength error of "ring_buffer.c". + + Modify __RBIT as RBIT of "ht32_cm0plus_misc.c" (__RBIT is keyword of IAR). diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/SConscript b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/SConscript new file mode 100644 index 0000000000..b673b24b8f --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/SConscript @@ -0,0 +1,49 @@ +import rtconfig +from building import * +Import('rtconfig') + +cwd = GetCurrentDir() +src = [] + +if GetDepend(['SOC_HT32F52352']): + src = Split(""" + library/HT32F5xxxx_Driver/src/ht32_cm0plus_misc.c + library/HT32F5xxxx_Driver/src/ht32f5xxxx_adc.c + library/HT32F5xxxx_Driver/src/ht32f5xxxx_bftm.c + library/HT32F5xxxx_Driver/src/ht32f5xxxx_ckcu.c + library/HT32F5xxxx_Driver/src/ht32f5xxxx_cmp.c + library/HT32F5xxxx_Driver/src/ht32f5xxxx_crc.c + library/HT32F5xxxx_Driver/src/ht32f5xxxx_ebi.c + library/HT32F5xxxx_Driver/src/ht32f5xxxx_exti.c + library/HT32F5xxxx_Driver/src/ht32f5xxxx_flash.c + library/HT32F5xxxx_Driver/src/ht32f5xxxx_gpio.c + library/HT32F5xxxx_Driver/src/ht32f5xxxx_i2c.c + library/HT32F5xxxx_Driver/src/ht32f5xxxx_i2s.c + library/HT32F5xxxx_Driver/src/ht32f5xxxx_mctm.c + library/HT32F5xxxx_Driver/src/ht32f5xxxx_pdma.c + library/HT32F5xxxx_Driver/src/ht32f5xxxx_pwrcu.c + library/HT32F5xxxx_Driver/src/ht32f5xxxx_rstcu.c + library/HT32F5xxxx_Driver/src/ht32f5xxxx_rtc.c + library/HT32F5xxxx_Driver/src/ht32f5xxxx_sci.c + library/HT32F5xxxx_Driver/src/ht32f5xxxx_spi.c + library/HT32F5xxxx_Driver/src/ht32f5xxxx_tm.c + library/HT32F5xxxx_Driver/src/ht32f5xxxx_usart.c + library/HT32F5xxxx_Driver/src/ht32f5xxxx_usbd.c + library/HT32F5xxxx_Driver/src/ht32f5xxxx_wdt.c + library/Device/Holtek/HT32F5xxxx/Source/system_ht32f5xxxx_01.c + """) + + + +path = [ + cwd + '/library/HT32F5xxxx_Driver/inc', + cwd + '/library/CMSIS/Include', + cwd + '/library/Device/Holtek/HT32F5xxxx/Include' +] + +CPPDEFINES = ['USE_HT32_DRIVER'] + +group = DefineGroup('Libraries', src, depend = [''], CPPPATH = path, CPPDEFINES = CPPDEFINES) + +Return('group') + diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/CMSIS/ARM.CMSIS.pdsc b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/CMSIS/ARM.CMSIS.pdsc new file mode 100644 index 0000000000..96775d502a --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/CMSIS/ARM.CMSIS.pdsc @@ -0,0 +1,3271 @@ + + + + CMSIS + CMSIS (Common Microcontroller Software Interface Standard) + ARM + + http://www.keil.com/pack/ + + + + CMSIS-Core(M): 5.6.0 + - Arm Cortex-M85 cpu support + - Arm China STAR-MC1 cpu support + - Updated system_ARMCM55.c + CMSIS-DSP: 1.10.0 (see revision history for details) + CMSIS-NN: 3.1.0 (see revision history for details) + - Support for int16 convolution and fully connected for reference implementation + - Support for DSP extension optimization for int16 convolution and fully connected + - Support dilation for int8 convolution + - Support dilation for int8 depthwise convolution + - Support for int16 depthwise conv for reference implementation including dilation + - Support for int16 average and max pooling for reference implementation + - Support for elementwise add and mul int16 scalar version + - Support for softmax int16 scalar version + - Support for SVDF with 8 bit state tensor + CMSIS-RTOS2: 2.1.3 (unchanged) + - RTX 5.5.4 (see revision history for details) + CMSIS-Pack: deprecated (moved to Open-CMSIS-Pack) + CMSIS-SVD: 1.3.9 (see revision history for details) + CMSIS-DAP: 2.1.1 (see revision history for details) + - Allow default clock frequency to use fast clock mode + Devices + - Support for Cortex-M85 + Utilities + - SVDConv 3.3.42 + - PackChk 1.3.95 + + + CMSIS-Core(M): 5.5.0 (see revision history for details) + - Updated GCC LinkerDescription, GCC Assembler startup + - Added Armv8-M Stack Sealing (to linker, startup) for toolchain ARM, GCC + - Changed C-Startup to default Startup. + - Updated Armv8-M Assembler startup to use GAS syntax + Note: Updating existing projects may need manual user interaction! + CMSIS-Core(A): 1.2.1 (see revision history for details) + - Bugfixes for Cortex-A32 + CMSIS-DAP: 2.1.0 (see revision history for details) + - Enhanced DAP_Info + - Added extra UART support + CMSIS-DSP: 1.9.0 (see revision history for details) + - Purged pre-built libs from Git + - Enhanced support for f16 datatype + - Fixed couple of GCC issues + CMSIS-NN: 3.0.0 (see revision history for details including version 2.0.0) + - Major interface change for functions compatible with TensorFlow Lite for Microcontroller + - Added optimization for SVDF kernel + - Improved MVE performance for fully Connected and max pool operator + - NULL bias support for fully connected operator in non-MVE case(Can affect performance) + - Expanded existing unit test suite along with support for FVP + - Removed Examples folder + CMSIS-RTOS2: + - RTX 5.5.3 (see revision history for details) + - CVE-2021-27431 vulnerability mitigation. + - Enhanced stack overrun checking. + - Various bug fixes and improvements. + CMSIS-Pack: 1.7.2 (see revision history for details) + - Support for Microchip XC32 compiler + - Support for Custom Datapath Extension + + + CMSIS-Build: 0.9.0 (beta) + - Draft for CMSIS Project description (CPRJ) + CMSIS-Core(M): 5.4.0 (see revision history for details) + - Cortex-M55 cpu support + - Enhanced MVE support for Armv8.1-MML + - Fixed device config define checks. + - L1 Cache functions for Armv7-M and later + CMSIS-Core(A): 1.2.0 (see revision history for details) + - Fixed GIC_SetPendingIRQ to use GICD_SGIR + - Added missing DSP intrinsics + - Reworked assembly intrinsics: volatile, barriers and clobber + CMSIS-DSP: 1.8.0 (see revision history for details) + - Added new functions and function groups + - Added MVE support + CMSIS-NN: 1.3.0 (see revision history for details) + - Added MVE support + - Further optimizations for kernels using DSP extension + CMSIS-RTOS2: + - RTX 5.5.2 (see revision history for details) + CMSIS-Driver: 2.8.0 + - Added VIO API 0.1.0 (Preview) + - removed volatile from status related typedefs in APIs + - enhanced WiFi Interface API with support for polling Socket Receive/Send + CMSIS-Pack: 1.6.3 (see revision history for details) + - deprecating all types specific to cpdsc format. Cpdsc is replaced by Cprj with dedicated schema. + Devices: + - ARMCM55 device + - ARMv81MML startup code recognizing __MVE_USED macro + - Refactored vector table references for all Cortex-M devices + - Reworked ARMCM* C-StartUp files. + - Include L1 Cache functions in ARMv8MML/ARMv81MML devices + Utilities: + Attention: Linux binaries moved to Linux64 folder! + - SVDConv 3.3.35 + - PackChk 1.3.89 + + + CMSIS-Core(M): 5.3.0 (see revision history for details) + - Added provisions for compiler-independent C startup code. + CMSIS-Core(A): 1.1.4 (see revision history for details) + - Fixed __FPU_Enable. + CMSIS-DSP: 1.7.0 (see revision history for details) + - New Neon versions of f32 functions + - Python wrapper + - Preliminary cmake build + - Compilation flags for FFTs + - Changes to arm_math.h + CMSIS-NN: 1.2.0 (see revision history for details) + - New function for depthwise convolution with asymmetric quantization. + - New support functions for requantization. + CMSIS-RTOS: + - RTX 4.82.0 (updated provisions for Arm Compiler 6 when using Cortex-M0/M0+) + CMSIS-RTOS2: + - RTX 5.5.1 (see revision history for details) + CMSIS-Driver: 2.7.1 + - WiFi Interface API 1.0.0 + Devices: + - Generalized C startup code for all Cortex-M family devices. + - Updated Cortex-A default memory regions and MMU configurations + - Moved Cortex-A memory and system config files to avoid include path issues + + + The following folders are deprecated + - CMSIS/Include/ (superseded by CMSIS/DSP/Include/ and CMSIS/Core/Include/) + + CMSIS-Core(M): 5.2.1 (see revision history for details) + - Fixed compilation issue in cmsis_armclang_ltm.h + + + The following folders have been removed: + - CMSIS/Lib/ (superseded by CMSIS/DSP/Lib/) + - CMSIS/DSP_Lib/ (superseded by CMSIS/DSP/) + The following folders are deprecated + - CMSIS/Include/ (superseded by CMSIS/DSP/Include/ and CMSIS/Core/Include/) + + CMSIS-Core(M): 5.2.0 (see revision history for details) + - Reworked Stack/Heap configuration for ARM startup files. + - Added Cortex-M35P device support. + - Added generic Armv8.1-M Mainline device support. + CMSIS-Core(A): 1.1.3 (see revision history for details) + CMSIS-DSP: 1.6.0 (see revision history for details) + - reworked DSP library source files + - reworked DSP library documentation + - Changed DSP folder structure + - moved DSP libraries to folder ./DSP/Lib + - ARM DSP Libraries are built with ARMCLANG + - Added DSP Libraries Source variant + CMSIS-RTOS2: + - RTX 5.5.0 (see revision history for details) + CMSIS-Driver: 2.7.0 + - Added WiFi Interface API 1.0.0-beta + - Added components for project specific driver implementations + CMSIS-Pack: 1.6.0 (see revision history for details) + Devices: + - Added Cortex-M35P and ARMv81MML device templates. + - Fixed C-Startup Code for GCC (aligned with other compilers) + Utilities: + - SVDConv 3.3.25 + - PackChk 1.3.82 + + + Aligned pack structure with repository. + The following folders are deprecated: + - CMSIS/Include/ + - CMSIS/DSP_Lib/ + + CMSIS-Core(M): 5.1.2 (see revision history for details) + - Added Cortex-M1 support (beta). + CMSIS-Core(A): 1.1.2 (see revision history for details) + CMSIS-NN: 1.1.0 + - Added new math functions. + CMSIS-RTOS2: + - API 2.1.3 (see revision history for details) + - RTX 5.4.0 (see revision history for details) + * Updated exception handling on Cortex-A + CMSIS-Driver: + - Flash Driver API V2.2.0 + Utilities: + - SVDConv 3.3.21 + - PackChk 1.3.71 + + + Updated Arm company brand. + CMSIS-Core(M): 5.1.1 (see revision history for details) + CMSIS-Core(A): 1.1.1 (see revision history for details) + CMSIS-DAP: 2.0.0 (see revision history for details) + CMSIS-NN: 1.0.0 + - Initial contribution of the bare metal Neural Network Library. + CMSIS-RTOS2: + - RTX 5.3.0 (see revision history for details) + - OS Tick API 1.0.1 + + + CMSIS-Core(M): 5.1.0 (see revision history for details) + - Added MPU Functions for ARMv8-M for Cortex-M23/M33. + - Added compiler_iccarm.h to replace compiler_iar.h shipped with the compiler. + CMSIS-Core(A): 1.1.0 (see revision history for details) + - Added compiler_iccarm.h. + - Added additional access functions for physical timer. + CMSIS-DAP: 1.2.0 (see revision history for details) + CMSIS-DSP: 1.5.2 (see revision history for details) + CMSIS-Driver: 2.6.0 (see revision history for details) + - CAN Driver API V1.2.0 + - NAND Driver API V2.3.0 + CMSIS-RTOS: + - RTX: added variant for Infineon XMC4 series affected by PMU_CM.001 errata. + CMSIS-RTOS2: + - API 2.1.2 (see revision history for details) + - RTX 5.2.3 (see revision history for details) + Devices: + - Added GCC startup and linker script for Cortex-A9. + - Added device ARMCM0plus_MPU for Cortex-M0+ with MPU. + - Added IAR startup code for Cortex-A9 + + + CMSIS-RTOS2: + - RTX 5.2.1 (see revision history for details) + + + CMSIS-Core(M): 5.0.2 (see revision history for details) + - Changed Version Control macros to be core agnostic. + - Added MPU Functions for ARMv7-M for Cortex-M0+/M3/M4/M7. + CMSIS-Core(A): 1.0.0 (see revision history for details) + - Initial release + - IRQ Controller API 1.0.0 + CMSIS-Driver: 2.05 (see revision history for details) + - All typedefs related to status have been made volatile. + CMSIS-RTOS2: + - API 2.1.1 (see revision history for details) + - RTX 5.2.0 (see revision history for details) + - OS Tick API 1.0.0 + CMSIS-DSP: 1.5.2 (see revision history for details) + - Fixed GNU Compiler specific diagnostics. + CMSIS-Pack: 1.5.0 (see revision history for details) + - added System Description File (*.SDF) Format + CMSIS-Zone: 0.0.1 (Preview) + - Initial specification draft + + + Package Description: + - added taxonomy for Cclass RTOS + CMSIS-RTOS2: + - API 2.1 (see revision history for details) + - RTX 5.1.0 (see revision history for details) + CMSIS-Core: 5.0.1 (see revision history for details) + - Added __PACKED_STRUCT macro + - Added uVisior support + - Updated cmsis_armcc.h: corrected macro __ARM_ARCH_6M__ + - Updated template for secure main function (main_s.c) + - Updated template for Context Management for ARMv8-M TrustZone (tz_context.c) + CMSIS-DSP: 1.5.1 (see revision history for details) + - added ARMv8M DSP libraries. + CMSIS-Pack:1.4.9 (see revision history for details) + - added Pack Index File specification and schema file + + + Changed open source license to Apache 2.0 + CMSIS_Core: + - Added support for Cortex-M23 and Cortex-M33. + - Added ARMv8-M device configurations for mainline and baseline. + - Added CMSE support and thread context management for TrustZone for ARMv8-M + - Added cmsis_compiler.h to unify compiler behaviour. + - Updated function SCB_EnableICache (for Cortex-M7). + - Added functions: NVIC_GetEnableIRQ, SCB_GetFPUType + CMSIS-RTOS: + - bug fix in RTX 4.82 (see revision history for details) + CMSIS-RTOS2: + - new API including compatibility layer to CMSIS-RTOS + - reference implementation based on RTX5 + - supports all Cortex-M variants including TrustZone for ARMv8-M + CMSIS-SVD: + - reworked SVD format documentation + - removed SVD file database documentation as SVD files are distributed in packs + - updated SVDConv for Win32 and Linux + CMSIS-DSP: + - Moved DSP libraries from CMSIS/DSP/Lib to CMSIS/Lib. + - Added DSP libraries build projects to CMSIS pack. + + + - CMSIS-Core 4.30.0 (see revision history for details) + - CMSIS-DAP 1.1.0 (unchanged) + - CMSIS-Driver 2.04.0 (see revision history for details) + - CMSIS-DSP 1.4.7 (no source code change [still labeled 1.4.5], see revision history for details) + - CMSIS-Pack 1.4.1 (see revision history for details) + - CMSIS-RTOS 4.80.0 Restored time delay parameter 'millisec' old behavior (prior V4.79) for software compatibility. (see revision history for details) + - CMSIS-SVD 1.3.1 (see revision history for details) + + + - CMSIS-Core 4.20 (see revision history for details) + - CMSIS-DSP 1.4.6 (no source code change [still labeled 1.4.5], see revision history for details) + - CMSIS-Pack 1.4.0 (adding memory attributes, algorithm style) + - CMSIS-Driver 2.03.0 (adding CAN [Controller Area Network] API) + - CMSIS-RTOS + -- API 1.02 (unchanged) + -- RTX 4.79 (see revision history for details) + - CMSIS-SVD 1.3.0 (see revision history for details) + - CMSIS-DAP 1.1.0 (extended with SWO support) + + + - CMSIS-Core 4.10 (Cortex-M7 extended Cache Maintenance functions) + - CMSIS-DSP 1.4.5 (see revision history for details) + - CMSIS-Driver 2.02 (adding SAI (Serial Audio Interface) API) + - CMSIS-Pack 1.3.3 (Semantic Versioning, Generator extensions) + - CMSIS-RTOS + -- API 1.02 (unchanged) + -- RTX 4.78 (see revision history for details) + - CMSIS-SVD 1.2 (unchanged) + + + Adding Cortex-M7 support + - CMSIS-Core 4.00 (Cortex-M7 support, corrected C++ include guards in core header files) + - CMSIS-DSP 1.4.4 (Cortex-M7 support and corrected out of bound issues) + - CMSIS-Pack 1.3.1 (Cortex-M7 updates, clarification, corrected batch files in Tutorial) + - CMSIS-SVD 1.2 (Cortex-M7 extensions) + - CMSIS-RTOS RTX 4.75 (see revision history for details) + + + - fixed conditions preventing the inclusion of the DSP library in projects for Infineon XMC4000 series devices + + + - CMSIS-Driver 2.02 (incompatible update) + - CMSIS-Pack 1.3 (see revision history for details) + - CMSIS-DSP 1.4.2 (unchanged) + - CMSIS-Core 3.30 (unchanged) + - CMSIS-RTOS RTX 4.74 (unchanged) + - CMSIS-RTOS API 1.02 (unchanged) + - CMSIS-SVD 1.10 (unchanged) + PACK: + - removed G++ specific files from PACK + - added Component Startup variant "C Startup" + - added Pack Checking Utility + - updated conditions to reflect tool-chain dependency + - added Taxonomy for Graphics + - updated Taxonomy for unified drivers from "Drivers" to "CMSIS Drivers" + + + + - CMSIS-RTOS 4.74 (see revision history for details) + - PACK Extensions (Boards, Device Features, Flash Programming, Generators, Configuration Wizard). Schema version 1.1. + + + + + + + + + Software components for audio processing + Generic Interfaces for Evaluation and Development Boards + Drivers that support an external component available on an evaluation board + Compiler Software Extensions + Cortex Microcontroller Software Interface Components + Unified Device Drivers compliant to CMSIS-Driver Specifications + Startup, System Setup + Data exchange or data formatter + Drivers that support an extension board or shield + File Drive Support and File System + IoT cloud client connector + IoT specific services + IoT specific software utility + Graphical User Interface + Network Stack using Internet Protocols + Real-time Operating System + Encryption for secure communication or storage + Universal Serial Bus Stack + Generic software utility components + + + + + + + +The Cortex-M0 processor is an entry-level 32-bit Arm Cortex processor designed for a broad range of embedded applications. It offers significant benefits to developers, including: +- simple, easy-to-use programmers model +- highly efficient ultra-low power operation +- excellent code density +- deterministic, high-performance interrupt handling +- upward compatibility with the rest of the Cortex-M processor family. + + + + + + + + + + + + + + + + +The Cortex-M0+ processor is an entry-level 32-bit Arm Cortex processor designed for a broad range of embedded applications. It offers significant benefits to developers, including: +- simple, easy-to-use programmers model +- highly efficient ultra-low power operation +- excellent code density +- deterministic, high-performance interrupt handling +- upward compatibility with the rest of the Cortex-M processor family. + + + + + + + + + + + + + + + + + + + + + +The ARM Cortex-M1 FPGA processor is intended for deeply embedded applications that require a small processor integrated into an FPGA. +The ARM Cortex-M1 processor implements the ARMv6-M architecture profile. + + + + + + + + + + + + + + + + +The Cortex-M3 processor is an entry-level 32-bit Arm Cortex processor designed for a broad range of embedded applications. It offers significant benefits to developers, including: +- simple, easy-to-use programmers model +- highly efficient ultra-low power operation +- excellent code density +- deterministic, high-performance interrupt handling +- upward compatibility with the rest of the Cortex-M processor family. + + + + + + + + + + + + + + + + +The Cortex-M4 processor is an entry-level 32-bit Arm Cortex processor designed for a broad range of embedded applications. It offers significant benefits to developers, including: +- simple, easy-to-use programmers model +- highly efficient ultra-low power operation +- excellent code density +- deterministic, high-performance interrupt handling +- upward compatibility with the rest of the Cortex-M processor family. + + + + + + + + + + + + + + + + + + + + + +The Cortex-M7 processor is an entry-level 32-bit Arm Cortex processor designed for a broad range of embedded applications. It offers significant benefits to developers, including: +- simple, easy-to-use programmers model +- highly efficient ultra-low power operation +- excellent code density +- deterministic, high-performance interrupt handling +- upward compatibility with the rest of the Cortex-M processor family. + + + + + + + + + + + + + + + + + + + + + + + + + + +The Arm Cortex-M23 is based on the Armv8-M baseline architecture. +It is the smallest and most energy efficient Arm processor with Arm TrustZone technology. +Cortex-M23 is the ideal processor for constrained embedded applications requiring efficient security. + + + + + + + + + + + + + + + + + + + + + + + +The Arm Cortex-M33 is the most configurable of all Cortex-M processors. It is a full featured microcontroller +class processor based on the Armv8-M mainline architecture with Arm TrustZone security. + + + + + + + + + + + + no DSP Instructions, no Floating Point Unit, no TrustZone + + + + + + + + no DSP Instructions, no Floating Point Unit, TrustZone + + + + + + + + DSP Instructions, Single Precision Floating Point Unit, no TrustZone + + + + + + + + DSP Instructions, Single Precision Floating Point Unit, TrustZone + + + + + + + + + +The Arm Cortex-M35P is the most configurable of all Cortex-M processors. It is a full featured microcontroller +class processor based on the Armv8-M mainline architecture with Arm TrustZone security designed for a broad range of secure embedded applications. + + + + + + + + + + + + + no DSP Instructions, no Floating Point Unit, no TrustZone + + + + + + + + no DSP Instructions, no Floating Point Unit, TrustZone + + + + + + + + DSP Instructions, Single Precision Floating Point Unit, no TrustZone + + + + + + + + DSP Instructions, Single Precision Floating Point Unit, TrustZone + + + + + + + + + +The Arm Cortex-M55 processor is a fully synthesizable, mid-range, microcontroller-class processor that implements the Armv8.1-M mainline architecture and includes support for the M-profile Vector Extension (MVE), also known as Arm Helium technology. +It is Arm's most AI-capable Cortex-M processor, delivering enhanced, energy-efficient digital signal processing (DSP) and machine learning (ML) performance. +The Cortex-M55 processor achieves high compute performance across scalar and vector operations, while maintaining low energy consumption. + + + + + + + + + + + + + Floating Point Vector Extensions, DSP Instructions, Double Precision Floating Point Unit, TrustZone + + + + + + + + + +The Arm Cortex-M85 processor is a fully synthesizable high-performance microcontroller class processor that implements the Armv8.1-M Mainline architecture which includes support for the M-profile Vector Extension (MVE). +The processor also supports previous Armv8-M architectural features. +The design is focused on compute applications such as Digital Signal Processing (DSP) and machine learning. +The Arm Cortex-M85 processor is energy efficient and achieves high compute performance across scalar and vector operations while maintaining low power consumption. + + + + + + + + + + + + + Floating Point Vector Extensions, DSP Instructions, Double Precision Floating Point Unit, TrustZone, PACBTI + + + + + + + + +The Arm SC000 processor is an entry-level 32-bit Arm Cortex processor designed for a broad range of secure embedded applications. It offers significant benefits to developers, including: +- simple, easy-to-use programmers model +- highly efficient ultra-low power operation +- excellent code density +- deterministic, high-performance interrupt handling + + + + + + + + + + + + + + + +The ARM SC300 processor is an entry-level 32-bit ARM Cortex processor designed for a broad range of secure embedded applications. It offers significant benefits to developers, including: +- simple, easy-to-use programmers model +- highly efficient ultra-low power operation +- excellent code density +- deterministic, high-performance interrupt handling + + + + + + + + + + + + + + + + +Armv8-M Baseline based device with TrustZone + + + + + + + + + + + + + + + + + + +Armv8-M Mainline based device with TrustZone + + + + + + + + + + + + no DSP Instructions, no Floating Point Unit, TrustZone + + + + + + + + DSP Instructions, no Floating Point Unit, TrustZone + + + + + + + + no DSP Instructions, Single Precision Floating Point Unit, TrustZone + + + + + + + + DSP Instructions, Single Precision Floating Point Unit, TrustZone + + + + + + + + no DSP Instructions, Double Precision Floating Point Unit, TrustZone + + + + + + + + DSP Instructions, Double Precision Floating Point Unit, TrustZone + + + + + + + + + +Armv8.1-M Mainline based device with TrustZone and MVE + + + + + + + + + + + + + Double Precision Vector Extensions, DSP Instructions, Double Precision Floating Point Unit, TrustZone + + + + + + + + + +The Arm Cortex-A5 processor is a high-performance, low-power, Arm macrocell with an L1 cache subsystem that provides full +virtual memory capabilities. The Cortex-A5 processor implements the Armv7-A architecture profile and can execute 32-bit +Arm instructions and 16-bit and 32-bit Thumb instructions. The Cortex-A5 is the smallest member of the Cortex-A processor family. + + + + + + + + + + + + + + + + + +The Cortex-A7 MPCore processor is a high-performance, low-power processor that implements the Armv7-A architecture. +The Cortex-A7 MPCore processor has one to four processors in a single multiprocessor device with a L1 cache subsystem, +an optional integrated GIC, and an optional L2 cache controller. + + + + + + + + + + + + + + + + + +The Cortex-A9 processor is a high-performance, low-power, Arm macrocell with an L1 cache subsystem that provides full virtual memory capabilities. +The Cortex-A9 processor implements the Armv7-A architecture and runs 32-bit Arm instructions, 16-bit and 32-bit Thumb instructions, +and 8-bit Java bytecodes in Jazelle state. + + + + + + + + + + + + + + + + + + + Device interrupt controller interface + + + + + + RTOS Kernel system tick timer interface + + + + + + + CMSIS-RTOS API for Cortex-M, SC000, and SC300 + + + + + + CMSIS-RTOS API for Cortex-M, SC000, and SC300 + + + + + + + + USART Driver API for Cortex-M + + + + + + + SPI Driver API for Cortex-M + + + + + + + SAI Driver API for Cortex-M + + + + + + + I2C Driver API for Cortex-M + + + + + + + CAN Driver API for Cortex-M + + + + + + + Flash Driver API for Cortex-M + + + + + + + MCI Driver API for Cortex-M + + + + + + + NAND Flash Driver API for Cortex-M + + + + + + + Ethernet MAC and PHY Driver API for Cortex-M + + + + + + + + Ethernet MAC Driver API for Cortex-M + + + + + + + Ethernet PHY Driver API for Cortex-M + + + + + + + USB Device Driver API for Cortex-M + + + + + + + USB Host Driver API for Cortex-M + + + + + + + WiFi driver + + + + + + + Virtual I/O + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Armv6-M architecture based device + + + + + + + Armv7-M architecture based device + + + + + + + Armv8-M base line architecture based device + + + + + Armv8-M main line architecture based device + + + + + + + Armv8.1-M main line architecture based device + + + + + + Armv8-M/Armv8.1-M architecture based device + + + + + Armv8-M architecture based device + + + + + + Armv6_7-M architecture based device + + + + + Armv6_7_8-M architecture based device + + + + + + Armv7-A architecture based device + + + + + + + TrustZone + + + + TrustZone (Secure) + + + + + TrustZone (Non-secure) + + + + + + + + Startup files for Arm Compiler 6 targeting TrustZone secure mode + + + + + Startup files for Arm Compiler 6 targeting non-TrustZone or TrustZone non-secure mode + + + + + + + Generic Arm Cortex-M0 device startup and depends on CMSIS Core + + + + + + Generic Arm Cortex-M0+ device startup and depends on CMSIS Core + + + + + + Generic Arm Cortex-M1 device startup and depends on CMSIS Core + + + + + + Generic Arm Cortex-M3 device startup and depends on CMSIS Core + + + + + + Generic Arm Cortex-M4 device startup and depends on CMSIS Core + + + + + + Generic Arm Cortex-M7 device startup and depends on CMSIS Core + + + + + + Generic Arm Cortex-M23 device startup and depends on CMSIS Core + + + + + + Generic Arm Cortex-M33 device startup and depends on CMSIS Core + + + + + + Generic Arm Cortex-M35P device startup and depends on CMSIS Core + + + + + + Generic Arm Cortex-M55 device startup and depends on CMSIS Core + + + + + + Generic Arm Cortex-M85 device startup and depends on CMSIS Core + + + + + + Generic Arm SC000 device startup and depends on CMSIS Core + + + + + + Generic Arm SC300 device startup and depends on CMSIS Core + + + + + + Generic Armv8-M Baseline device startup and depends on CMSIS Core + + + + + + Generic Armv8-M Mainline device startup and depends on CMSIS Core + + + + + + Generic Armv8.1-M Mainline device startup and depends on CMSIS Core + + + + + + Generic Arm Cortex-A5 device startup and depends on CMSIS Core + + + + + + Generic Arm Cortex-A7 device startup and depends on CMSIS Core + + + + + + Generic Arm Cortex-A9 device startup and depends on CMSIS Core + + + + + + + Components required for DSP + + + + + + + + Components required for NN + + + + + + Components required for RTOS RTX + + + + + + + Components required for RTOS RTX IFX + + + + + + + + Components required for RTOS RTX5 + + + + + + Components required for RTOS2 RTX5 + + + + + + + Components required for RTOS2 RTX5 on Armv7-A + + + + + + + + + Components required for RTOS2 RTX5 in Non-Secure Domain + + + + + + + + + Arm Compiler for Armv6-M architecture (little endian) + + + + + + Arm Compiler for Armv6-M architecture (big endian) + + + + + + Arm Compiler for Armv7-M architecture without FPU (little endian) + + + + + + + Arm Compiler for Armv7-M architecture without FPU (big endian) + + + + + + + Arm Compiler for Armv7-M architecture with FPU (little endian) + + + + + + + + Arm Compiler for Armv7-M architecture with FPU (big endian) + + + + + + + + Arm Compiler for Armv8-M base line architecture (little endian) + + + + + + Arm Compiler for Armv8-M/Armv8.1-M main line architecture without FPU/MVE (little endian) + + + + + + + + Arm Compiler for Armv8-M/Armv8.1-M main line architecture with FPU/MVE (little endian) + + + + + + + + + + + GNU Compiler for Armv6-M architecture (little endian) + + + + + + GNU Compiler for Armv6-M architecture (big endian) + + + + + + GNU Compiler for Armv7-M architecture without FPU (little endian) + + + + + + + GNU Compiler for Armv7-M architecture without FPU (big endian) + + + + + + + GNU Compiler for Armv7-M architecture with FPU (little endian) + + + + + + + + GNU Compiler for Armv7-M architecture with FPU (big endian) + + + + + + + + GNU Compiler for Armv8-M base line architecture (little endian) + + + + + + GNU Compiler for Armv8-M/Armv8.1-M main line architecture without FPU/MVE (little endian) + + + + + + + + GNU Compiler for Armv8-M/Armv8.1-M main line architecture with FPU/MVE (little endian) + + + + + + + + + + + IAR Compiler for Armv6-M architecture (little endian) + + + + + + IAR Compiler for Armv6-M architecture (big endian) + + + + + + IAR Compiler for Armv7-M architecture without FPU (little endian) + + + + + + + IAR Compiler for Armv7-M architecture without FPU (big endian) + + + + + + + IAR Compiler for Armv7-M architecture with FPU (little endian) + + + + + + + + IAR Compiler for Armv7-M architecture with FPU (big endian) + + + + + + + + IAR Compiler for Armv8-M base line architecture (little endian) + + + + + + IAR Compiler for Armv8-M main line architecture without FPU (little endian) + + + + + + + IAR Compiler for Armv8-M main line architecture with FPU (little endian) + + + + + + + + IAR Compiler for Armv8.1-M main line architecture without FPU/MVE (little endian) + + + + + + + + IAR Compiler for Armv8.1-M main line architecture with FPU/MVE (little endian) + + + + + + + + + + + Arm Assembler for Armv6-M architecture + + + + + GNU Assembler for Armv6-M architecture + + + + + + IAR Assembler for Armv6-M architecture + + + + + + Arm Assembler for Armv7-M architecture + + + + + GNU Assembler for Armv7-M architecture + + + + + + IAR Assembler for Armv7-M architecture + + + + + + GNU Assembler for Armv8-M base line architecture + + + + + GNU Assembler for Armv8-M/Armv8.1-M main line architecture + + + + + IAR Assembler for Armv8-M base line architecture + + + + + IAR Assembler for Armv8-M main line architecture + + + + + + Arm Assembler for Armv7-A architecture + + + + + GNU Assembler for Armv7-A architecture + + + + + + IAR Assembler for Armv7-A architecture + + + + + + + Components required for OS Tick Private Timer + + + + + + + Components required for OS Tick Generic Physical Timer + + + + + + + + + + CMSIS-CORE for Cortex-M, SC000, SC300, Star-MC1, ARMv8-M, ARMv8.1-M + + + + + + + + + + + + + CMSIS-CORE for Cortex-A + + + + + + + + + + + System and Startup for Generic Arm Cortex-M0 device + + + + + + + + + + + + + DEPRECATED: System and Startup for Generic Arm Cortex-M0 device + + + + + + + + + + + + + + + System and Startup for Generic Arm Cortex-M0+ device + + + + + + + + + + + + + DEPRECATED: System and Startup for Generic Arm Cortex-M0+ device + + + + + + + + + + + + + + + System and Startup for Generic Arm Cortex-M1 device + + + + + + + + + + + + + DEPRECATED: System and Startup for Generic Arm Cortex-M1 device + + + + + + + + + + + + + + + System and Startup for Generic Arm Cortex-M3 device + + + + + + + + + + + + + DEPRECATED: System and Startup for Generic Arm Cortex-M3 device + + + + + + + + + + + + + + + System and Startup for Generic Arm Cortex-M4 device + + + + + + + + + + + + + DEPRECATED: System and Startup for Generic Arm Cortex-M4 device + + + + + + + + + + + + + + + System and Startup for Generic Arm Cortex-M7 device + + + + + + + + + + + + + DEPRECATED: System and Startup for Generic Arm Cortex-M7 device + + + + + + + + + + + + + + + System and Startup for Generic Arm Cortex-M23 device + + + + + + + + + + + + + + + DEPRECATED: System and Startup for Generic Arm Cortex-M23 device + + + + + + + + + + + + + + + + + + + System and Startup for Generic Arm Cortex-M33 device + + + + + + + + + + + + + + + DEPRECATED: System and Startup for Generic Arm Cortex-M33 device + + + + + + + + + + + + + + + + + + + System and Startup for Generic Arm Cortex-M35P device + + + + + + + + + + + + + + + DEPRECATED: System and Startup for Generic Arm Cortex-M35P device + + + + + + + + + + + + + + + + + + + System and Startup for Generic Cortex-M55 device + + + + + + + + + + + + + + + + + System and Startup for Generic Cortex-M85 device + + + + + + + + + + + + + + + + + System and Startup for Generic Arm SC000 device + + + + + + + + + + + + + DEPRECATED: System and Startup for Generic Arm SC000 device + + + + + + + + + + + + + + + System and Startup for Generic Arm SC300 device + + + + + + + + + + + + + DEPRECATED: System and Startup for Generic Arm SC300 device + + + + + + + + + + + + + + + System and Startup for Generic Armv8-M Baseline device + + + + + + + + + + + + + + + DEPRECATED: System and Startup for Generic Armv8-M Baseline device + + + + + + + + + + + + + + + + + + System and Startup for Generic Armv8-M Mainline device + + + + + + + + + + + + + + + DEPRECATED: System and Startup for Generic Armv8-M Mainline device + + + + + + + + + + + + + + + + + + System and Startup for Generic Armv8.1-M Mainline device + + + + + + + + + + + + + + + + + System and Startup for Generic Arm Cortex-A5 device + + + + + + + + + + + + + + + + + + + + + + + System and Startup for Generic Arm Cortex-A7 device + + + + + + + + + + + + + + + + + + + + + + System and Startup for Generic Arm Cortex-A9 device + + + + + + + + + + + + + + + + + + + + + + IRQ Controller implementation using GIC + + + + + + + + OS Tick implementation using Private Timer + + + + + + + OS Tick implementation using Generic Physical Timer + + + + + + + + CMSIS-DSP Library for Cortex-M, SC000, and SC300 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + CMSIS-NN Neural Network Library + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + CMSIS-RTOS RTX implementation for Cortex-M, SC000, and SC300 + + + #define RTE_CMSIS_RTOS /* CMSIS-RTOS */ + #define RTE_CMSIS_RTOS_RTX /* CMSIS-RTOS Keil RTX */ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + CMSIS-RTOS RTX implementation for Infineon XMC4 series affected by PMU_CM.001 errata + + + #define RTE_CMSIS_RTOS /* CMSIS-RTOS */ + #define RTE_CMSIS_RTOS_RTX /* CMSIS-RTOS Keil RTX */ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + CMSIS-RTOS RTX5 implementation for Cortex-M, SC000, and SC300 + + + #define RTE_CMSIS_RTOS /* CMSIS-RTOS */ + #define RTE_CMSIS_RTOS_RTX5 /* CMSIS-RTOS Keil RTX5 */ + + + + + + + + + + + + CMSIS-RTOS2 RTX5 for Cortex-M, SC000, SC300, ARMv8-M, ARMv8.1-M (Library) + + + #define RTE_CMSIS_RTOS2 /* CMSIS-RTOS2 */ + #define RTE_CMSIS_RTOS2_RTX5 /* CMSIS-RTOS2 Keil RTX5 */ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + CMSIS-RTOS2 RTX5 for Armv8-M/Armv8.1-M Non-Secure Domain (Library) + + + #define RTE_CMSIS_RTOS2 /* CMSIS-RTOS2 */ + #define RTE_CMSIS_RTOS2_RTX5 /* CMSIS-RTOS2 Keil RTX5 */ + #define RTE_CMSIS_RTOS2_RTX5_ARMV8M_NS /* CMSIS-RTOS2 Keil RTX5 Armv8-M Non-secure domain */ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + CMSIS-RTOS2 RTX5 for Cortex-M, SC000, SC300, ARMv8-M, ARMv8.1-M (Source) + + + #define RTE_CMSIS_RTOS2 /* CMSIS-RTOS2 */ + #define RTE_CMSIS_RTOS2_RTX5 /* CMSIS-RTOS2 Keil RTX5 */ + #define RTE_CMSIS_RTOS2_RTX5_SOURCE /* CMSIS-RTOS2 Keil RTX5 Source */ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + CMSIS-RTOS2 RTX5 for Armv7-A (Source) + + + #define RTE_CMSIS_RTOS2 /* CMSIS-RTOS2 */ + #define RTE_CMSIS_RTOS2_RTX5 /* CMSIS-RTOS2 Keil RTX5 */ + #define RTE_CMSIS_RTOS2_RTX5_SOURCE /* CMSIS-RTOS2 Keil RTX5 Source */ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + CMSIS-RTOS2 RTX5 for Armv8-M/Armv8.1-M Non-Secure Domain (Source) + + + #define RTE_CMSIS_RTOS2 /* CMSIS-RTOS2 */ + #define RTE_CMSIS_RTOS2_RTX5 /* CMSIS-RTOS2 Keil RTX5 */ + #define RTE_CMSIS_RTOS2_RTX5_SOURCE /* CMSIS-RTOS2 Keil RTX5 Source */ + #define RTE_CMSIS_RTOS2_RTX5_ARMV8M_NS /* CMSIS-RTOS2 Keil RTX5 Armv8-M Non-secure domain */ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Access to #include Driver_USART.h file and code template for custom implementation + + + + + + + Access to #include Driver_SPI.h file and code template for custom implementation + + + + + + + Access to #include Driver_SAI.h file and code template for custom implementation + + + + + + + Access to #include Driver_I2C.h file and code template for custom implementation + + + + + + + Access to #include Driver_CAN.h file and code template for custom implementation + + + + + + + Access to #include Driver_Flash.h file and code template for custom implementation + + + + + + + Access to #include Driver_MCI.h file and code template for custom implementation + + + + + + + Access to #include Driver_NAND.h file and code template for custom implementation + + + + + + + Access to #include Driver_ETH_PHY/MAC.h files and code templates for custom implementation + + + + + + + + + Access to #include Driver_ETH_MAC.h file and code template for custom implementation + + + + + + + Access to #include Driver_ETH_PHY.h file and code template for custom implementation + + + + + + + Access to #include Driver_USBD.h file and code template for custom implementation + + + + + + + Access to #include Driver_USBH.h file and code template for custom implementation + + + + + + + Access to #include Driver_WiFi.h file + + + + + + + + + Virtual I/O custom implementation template + + + + + + Virtual I/O implementation using memory only + + + + + + + + + + uVision Simulator + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + EWARM Simulator + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + DSP_Lib Bayes example + + + + + + + + + Getting Started + + + + + DSP_Lib Class Marks example + + + + + + + + + Getting Started + + + + + DSP_Lib Convolution example + + + + + + + + + Getting Started + + + + + DSP_Lib Dotproduct example + + + + + + + + + Getting Started + + + + + DSP_Lib FFT Bin example + + + + + + + + + Getting Started + + + + + DSP_Lib FIR example + + + + + + + + + Getting Started + + + + + DSP_Lib Graphic Equalizer example + + + + + + + + + Getting Started + + + + + DSP_Lib Linear Interpolation example + + + + + + + + + Getting Started + + + + + DSP_Lib Matrix example + + + + + + + + + Getting Started + + + + + DSP_Lib Signal Convergence example + + + + + + + + + Getting Started + + + + + DSP_Lib Sinus/Cosinus example + + + + + + + + + Getting Started + + + + + DSP_Lib SVM example + + + + + + + + + Getting Started + + + + + DSP_Lib Variance example + + + + + + + + + Getting Started + + + + + CMSIS-RTOS2 Blinky example + + + + + + + + + Getting Started + + + + + CMSIS-RTOS2 mixed API v1 and v2 + + + + + + + + + Getting Started + + + + + CMSIS-RTOS2 Message Queue Example + + + + + + + + + + Getting Started + + + + + CMSIS-RTOS2 Memory Pool Example + + + + + + + + + + Getting Started + + + + + Bare-metal secure/non-secure example without RTOS + + + + + + + + + Getting Started + + + + + Secure/non-secure RTOS example with thread context management + + + + + + + + + Getting Started + + + + + Secure/non-secure RTOS example with security test cases and system recovery + + + + + + + + + Getting Started + + + + + CMSIS-RTOS2 Blinky example + + + + + + + + + Getting Started + + + + + CMSIS-RTOS2 Message Queue Example + + + + + + + + + Getting Started + + + + + + diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/CMSIS/Core/Include/cachel1_armv7.h b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/CMSIS/Core/Include/cachel1_armv7.h new file mode 100644 index 0000000000..abebc95f94 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/CMSIS/Core/Include/cachel1_armv7.h @@ -0,0 +1,411 @@ +/****************************************************************************** + * @file cachel1_armv7.h + * @brief CMSIS Level 1 Cache API for Armv7-M and later + * @version V1.0.1 + * @date 19. April 2021 + ******************************************************************************/ +/* + * Copyright (c) 2020-2021 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef ARM_CACHEL1_ARMV7_H +#define ARM_CACHEL1_ARMV7_H + +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_CacheFunctions Cache Functions + \brief Functions that configure Instruction and Data cache. + @{ + */ + +/* Cache Size ID Register Macros */ +#define CCSIDR_WAYS(x) (((x) & SCB_CCSIDR_ASSOCIATIVITY_Msk) >> SCB_CCSIDR_ASSOCIATIVITY_Pos) +#define CCSIDR_SETS(x) (((x) & SCB_CCSIDR_NUMSETS_Msk ) >> SCB_CCSIDR_NUMSETS_Pos ) + +#ifndef __SCB_DCACHE_LINE_SIZE +#define __SCB_DCACHE_LINE_SIZE 32U /*!< Cortex-M7 cache line size is fixed to 32 bytes (8 words). See also register SCB_CCSIDR */ +#endif + +#ifndef __SCB_ICACHE_LINE_SIZE +#define __SCB_ICACHE_LINE_SIZE 32U /*!< Cortex-M7 cache line size is fixed to 32 bytes (8 words). See also register SCB_CCSIDR */ +#endif + +/** + \brief Enable I-Cache + \details Turns on I-Cache + */ +__STATIC_FORCEINLINE void SCB_EnableICache (void) +{ + #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) + if (SCB->CCR & SCB_CCR_IC_Msk) return; /* return if ICache is already enabled */ + + __DSB(); + __ISB(); + SCB->ICIALLU = 0UL; /* invalidate I-Cache */ + __DSB(); + __ISB(); + SCB->CCR |= (uint32_t)SCB_CCR_IC_Msk; /* enable I-Cache */ + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Disable I-Cache + \details Turns off I-Cache + */ +__STATIC_FORCEINLINE void SCB_DisableICache (void) +{ + #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) + __DSB(); + __ISB(); + SCB->CCR &= ~(uint32_t)SCB_CCR_IC_Msk; /* disable I-Cache */ + SCB->ICIALLU = 0UL; /* invalidate I-Cache */ + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Invalidate I-Cache + \details Invalidates I-Cache + */ +__STATIC_FORCEINLINE void SCB_InvalidateICache (void) +{ + #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) + __DSB(); + __ISB(); + SCB->ICIALLU = 0UL; + __DSB(); + __ISB(); + #endif +} + + +/** + \brief I-Cache Invalidate by address + \details Invalidates I-Cache for the given address. + I-Cache is invalidated starting from a 32 byte aligned address in 32 byte granularity. + I-Cache memory blocks which are part of given address + given size are invalidated. + \param[in] addr address + \param[in] isize size of memory block (in number of bytes) +*/ +__STATIC_FORCEINLINE void SCB_InvalidateICache_by_Addr (volatile void *addr, int32_t isize) +{ + #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) + if ( isize > 0 ) { + int32_t op_size = isize + (((uint32_t)addr) & (__SCB_ICACHE_LINE_SIZE - 1U)); + uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_ICACHE_LINE_SIZE - 1U) */; + + __DSB(); + + do { + SCB->ICIMVAU = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */ + op_addr += __SCB_ICACHE_LINE_SIZE; + op_size -= __SCB_ICACHE_LINE_SIZE; + } while ( op_size > 0 ); + + __DSB(); + __ISB(); + } + #endif +} + + +/** + \brief Enable D-Cache + \details Turns on D-Cache + */ +__STATIC_FORCEINLINE void SCB_EnableDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + if (SCB->CCR & SCB_CCR_DC_Msk) return; /* return if DCache is already enabled */ + + SCB->CSSELR = 0U; /* select Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) | + ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + __DSB(); + + SCB->CCR |= (uint32_t)SCB_CCR_DC_Msk; /* enable D-Cache */ + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Disable D-Cache + \details Turns off D-Cache + */ +__STATIC_FORCEINLINE void SCB_DisableDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /* select Level 1 data cache */ + __DSB(); + + SCB->CCR &= ~(uint32_t)SCB_CCR_DC_Msk; /* disable D-Cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* clean & invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) | + ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Invalidate D-Cache + \details Invalidates D-Cache + */ +__STATIC_FORCEINLINE void SCB_InvalidateDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /* select Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) | + ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Clean D-Cache + \details Cleans D-Cache + */ +__STATIC_FORCEINLINE void SCB_CleanDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /* select Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* clean D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCCSW = (((sets << SCB_DCCSW_SET_Pos) & SCB_DCCSW_SET_Msk) | + ((ways << SCB_DCCSW_WAY_Pos) & SCB_DCCSW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Clean & Invalidate D-Cache + \details Cleans and Invalidates D-Cache + */ +__STATIC_FORCEINLINE void SCB_CleanInvalidateDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /* select Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* clean & invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) | + ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief D-Cache Invalidate by address + \details Invalidates D-Cache for the given address. + D-Cache is invalidated starting from a 32 byte aligned address in 32 byte granularity. + D-Cache memory blocks which are part of given address + given size are invalidated. + \param[in] addr address + \param[in] dsize size of memory block (in number of bytes) +*/ +__STATIC_FORCEINLINE void SCB_InvalidateDCache_by_Addr (volatile void *addr, int32_t dsize) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + if ( dsize > 0 ) { + int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U)); + uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */; + + __DSB(); + + do { + SCB->DCIMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */ + op_addr += __SCB_DCACHE_LINE_SIZE; + op_size -= __SCB_DCACHE_LINE_SIZE; + } while ( op_size > 0 ); + + __DSB(); + __ISB(); + } + #endif +} + + +/** + \brief D-Cache Clean by address + \details Cleans D-Cache for the given address + D-Cache is cleaned starting from a 32 byte aligned address in 32 byte granularity. + D-Cache memory blocks which are part of given address + given size are cleaned. + \param[in] addr address + \param[in] dsize size of memory block (in number of bytes) +*/ +__STATIC_FORCEINLINE void SCB_CleanDCache_by_Addr (volatile void *addr, int32_t dsize) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + if ( dsize > 0 ) { + int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U)); + uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */; + + __DSB(); + + do { + SCB->DCCMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */ + op_addr += __SCB_DCACHE_LINE_SIZE; + op_size -= __SCB_DCACHE_LINE_SIZE; + } while ( op_size > 0 ); + + __DSB(); + __ISB(); + } + #endif +} + + +/** + \brief D-Cache Clean and Invalidate by address + \details Cleans and invalidates D_Cache for the given address + D-Cache is cleaned and invalidated starting from a 32 byte aligned address in 32 byte granularity. + D-Cache memory blocks which are part of given address + given size are cleaned and invalidated. + \param[in] addr address (aligned to 32-byte boundary) + \param[in] dsize size of memory block (in number of bytes) +*/ +__STATIC_FORCEINLINE void SCB_CleanInvalidateDCache_by_Addr (volatile void *addr, int32_t dsize) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + if ( dsize > 0 ) { + int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U)); + uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */; + + __DSB(); + + do { + SCB->DCCIMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */ + op_addr += __SCB_DCACHE_LINE_SIZE; + op_size -= __SCB_DCACHE_LINE_SIZE; + } while ( op_size > 0 ); + + __DSB(); + __ISB(); + } + #endif +} + +/*@} end of CMSIS_Core_CacheFunctions */ + +#endif /* ARM_CACHEL1_ARMV7_H */ diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/CMSIS/Core/Include/cmsis_armcc.h b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/CMSIS/Core/Include/cmsis_armcc.h new file mode 100644 index 0000000000..a955d47139 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/CMSIS/Core/Include/cmsis_armcc.h @@ -0,0 +1,888 @@ +/**************************************************************************//** + * @file cmsis_armcc.h + * @brief CMSIS compiler ARMCC (Arm Compiler 5) header file + * @version V5.3.2 + * @date 27. May 2021 + ******************************************************************************/ +/* + * Copyright (c) 2009-2021 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_ARMCC_H +#define __CMSIS_ARMCC_H + + +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 400677) + #error "Please use Arm Compiler Toolchain V4.0.677 or later!" +#endif + +/* CMSIS compiler control architecture macros */ +#if ((defined (__TARGET_ARCH_6_M ) && (__TARGET_ARCH_6_M == 1)) || \ + (defined (__TARGET_ARCH_6S_M ) && (__TARGET_ARCH_6S_M == 1)) ) + #define __ARM_ARCH_6M__ 1 +#endif + +#if (defined (__TARGET_ARCH_7_M ) && (__TARGET_ARCH_7_M == 1)) + #define __ARM_ARCH_7M__ 1 +#endif + +#if (defined (__TARGET_ARCH_7E_M) && (__TARGET_ARCH_7E_M == 1)) + #define __ARM_ARCH_7EM__ 1 +#endif + + /* __ARM_ARCH_8M_BASE__ not applicable */ + /* __ARM_ARCH_8M_MAIN__ not applicable */ + /* __ARM_ARCH_8_1M_MAIN__ not applicable */ + +/* CMSIS compiler control DSP macros */ +#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + #define __ARM_FEATURE_DSP 1 +#endif + +/* CMSIS compiler specific defines */ +#ifndef __ASM + #define __ASM __asm +#endif +#ifndef __INLINE + #define __INLINE __inline +#endif +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static __inline +#endif +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE static __forceinline +#endif +#ifndef __NO_RETURN + #define __NO_RETURN __declspec(noreturn) +#endif +#ifndef __USED + #define __USED __attribute__((used)) +#endif +#ifndef __WEAK + #define __WEAK __attribute__((weak)) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed)) +#endif +#ifndef __PACKED_STRUCT + #define __PACKED_STRUCT __packed struct +#endif +#ifndef __PACKED_UNION + #define __PACKED_UNION __packed union +#endif +#ifndef __UNALIGNED_UINT32 /* deprecated */ + #define __UNALIGNED_UINT32(x) (*((__packed uint32_t *)(x))) +#endif +#ifndef __UNALIGNED_UINT16_WRITE + #define __UNALIGNED_UINT16_WRITE(addr, val) ((*((__packed uint16_t *)(addr))) = (val)) +#endif +#ifndef __UNALIGNED_UINT16_READ + #define __UNALIGNED_UINT16_READ(addr) (*((const __packed uint16_t *)(addr))) +#endif +#ifndef __UNALIGNED_UINT32_WRITE + #define __UNALIGNED_UINT32_WRITE(addr, val) ((*((__packed uint32_t *)(addr))) = (val)) +#endif +#ifndef __UNALIGNED_UINT32_READ + #define __UNALIGNED_UINT32_READ(addr) (*((const __packed uint32_t *)(addr))) +#endif +#ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __RESTRICT + #define __RESTRICT __restrict +#endif +#ifndef __COMPILER_BARRIER + #define __COMPILER_BARRIER() __memory_changed() +#endif + +/* ######################### Startup and Lowlevel Init ######################## */ + +#ifndef __PROGRAM_START +#define __PROGRAM_START __main +#endif + +#ifndef __INITIAL_SP +#define __INITIAL_SP Image$$ARM_LIB_STACK$$ZI$$Limit +#endif + +#ifndef __STACK_LIMIT +#define __STACK_LIMIT Image$$ARM_LIB_STACK$$ZI$$Base +#endif + +#ifndef __VECTOR_TABLE +#define __VECTOR_TABLE __Vectors +#endif + +#ifndef __VECTOR_TABLE_ATTRIBUTE +#define __VECTOR_TABLE_ATTRIBUTE __attribute__((used, section("RESET"))) +#endif + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP __nop + + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +#define __WFI __wfi + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE __wfe + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV __sev + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +#define __ISB() __isb(0xF) + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +#define __DSB() __dsb(0xF) + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +#define __DMB() __dmb(0xF) + + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV __rev + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. + \param [in] value Value to reverse + \return Reversed value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value) +{ + rev16 r0, r0 + bx lr +} +#endif + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. + \param [in] value Value to reverse + \return Reversed value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int16_t __REVSH(int16_t value) +{ + revsh r0, r0 + bx lr +} +#endif + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +#define __ROR __ror + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __breakpoint(value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + #define __RBIT __rbit +#else +__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value) +{ + uint32_t result; + uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */ + + result = value; /* r will be reversed bits of v; first get LSB of v */ + for (value >>= 1U; value != 0U; value >>= 1U) + { + result <<= 1U; + result |= value & 1U; + s--; + } + result <<= s; /* shift when v's highest bits are zero */ + return result; +} +#endif + + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +#define __CLZ __clz + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr)) +#else + #define __LDREXB(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint8_t ) __ldrex(ptr)) _Pragma("pop") +#endif + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __LDREXH(ptr) ((uint16_t) __ldrex(ptr)) +#else + #define __LDREXH(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint16_t) __ldrex(ptr)) _Pragma("pop") +#endif + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr)) +#else + #define __LDREXW(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex(ptr)) _Pragma("pop") +#endif + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __STREXB(value, ptr) __strex(value, ptr) +#else + #define __STREXB(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") +#endif + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __STREXH(value, ptr) __strex(value, ptr) +#else + #define __STREXH(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") +#endif + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __STREXW(value, ptr) __strex(value, ptr) +#else + #define __STREXW(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") +#endif + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +#define __CLREX __clrex + + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT __ssat + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT __usat + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value) +{ + rrx r0, r0 + bx lr +} +#endif + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDRBT(ptr) ((uint8_t ) __ldrt(ptr)) + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDRHT(ptr) ((uint16_t) __ldrt(ptr)) + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDRT(ptr) ((uint32_t ) __ldrt(ptr)) + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +#define __STRBT(value, ptr) __strt(value, ptr) + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +#define __STRHT(value, ptr) __strt(value, ptr) + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +#define __STRT(value, ptr) __strt(value, ptr) + +#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +__attribute__((always_inline)) __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat) +{ + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; +} + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat) +{ + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing special-purpose register PRIMASK. + Can only be executed in Privileged modes. + */ +/* intrinsic void __enable_irq(); */ + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting special-purpose register PRIMASK. + Can only be executed in Privileged modes. + */ +/* intrinsic void __disable_irq(); */ + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__STATIC_INLINE uint32_t __get_CONTROL(void) +{ + register uint32_t __regControl __ASM("control"); + return(__regControl); +} + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__STATIC_INLINE void __set_CONTROL(uint32_t control) +{ + register uint32_t __regControl __ASM("control"); + __regControl = control; + __ISB(); +} + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__STATIC_INLINE uint32_t __get_IPSR(void) +{ + register uint32_t __regIPSR __ASM("ipsr"); + return(__regIPSR); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__STATIC_INLINE uint32_t __get_APSR(void) +{ + register uint32_t __regAPSR __ASM("apsr"); + return(__regAPSR); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__STATIC_INLINE uint32_t __get_xPSR(void) +{ + register uint32_t __regXPSR __ASM("xpsr"); + return(__regXPSR); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__STATIC_INLINE uint32_t __get_PSP(void) +{ + register uint32_t __regProcessStackPointer __ASM("psp"); + return(__regProcessStackPointer); +} + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) +{ + register uint32_t __regProcessStackPointer __ASM("psp"); + __regProcessStackPointer = topOfProcStack; +} + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__STATIC_INLINE uint32_t __get_MSP(void) +{ + register uint32_t __regMainStackPointer __ASM("msp"); + return(__regMainStackPointer); +} + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) +{ + register uint32_t __regMainStackPointer __ASM("msp"); + __regMainStackPointer = topOfMainStack; +} + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__STATIC_INLINE uint32_t __get_PRIMASK(void) +{ + register uint32_t __regPriMask __ASM("primask"); + return(__regPriMask); +} + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__STATIC_INLINE void __set_PRIMASK(uint32_t priMask) +{ + register uint32_t __regPriMask __ASM("primask"); + __regPriMask = (priMask); +} + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing special-purpose register FAULTMASK. + Can only be executed in Privileged modes. + */ +#define __enable_fault_irq __enable_fiq + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting special-purpose register FAULTMASK. + Can only be executed in Privileged modes. + */ +#define __disable_fault_irq __disable_fiq + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__STATIC_INLINE uint32_t __get_BASEPRI(void) +{ + register uint32_t __regBasePri __ASM("basepri"); + return(__regBasePri); +} + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__STATIC_INLINE void __set_BASEPRI(uint32_t basePri) +{ + register uint32_t __regBasePri __ASM("basepri"); + __regBasePri = (basePri & 0xFFU); +} + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + register uint32_t __regBasePriMax __ASM("basepri_max"); + __regBasePriMax = (basePri & 0xFFU); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__STATIC_INLINE uint32_t __get_FAULTMASK(void) +{ + register uint32_t __regFaultMask __ASM("faultmask"); + return(__regFaultMask); +} + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) +{ + register uint32_t __regFaultMask __ASM("faultmask"); + __regFaultMask = (faultMask & (uint32_t)1U); +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ + + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +__STATIC_INLINE uint32_t __get_FPSCR(void) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) + register uint32_t __regfpscr __ASM("fpscr"); + return(__regfpscr); +#else + return(0U); +#endif +} + + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +__STATIC_INLINE void __set_FPSCR(uint32_t fpscr) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) + register uint32_t __regfpscr __ASM("fpscr"); + __regfpscr = (fpscr); +#else + (void)fpscr; +#endif +} + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + +#define __SADD8 __sadd8 +#define __QADD8 __qadd8 +#define __SHADD8 __shadd8 +#define __UADD8 __uadd8 +#define __UQADD8 __uqadd8 +#define __UHADD8 __uhadd8 +#define __SSUB8 __ssub8 +#define __QSUB8 __qsub8 +#define __SHSUB8 __shsub8 +#define __USUB8 __usub8 +#define __UQSUB8 __uqsub8 +#define __UHSUB8 __uhsub8 +#define __SADD16 __sadd16 +#define __QADD16 __qadd16 +#define __SHADD16 __shadd16 +#define __UADD16 __uadd16 +#define __UQADD16 __uqadd16 +#define __UHADD16 __uhadd16 +#define __SSUB16 __ssub16 +#define __QSUB16 __qsub16 +#define __SHSUB16 __shsub16 +#define __USUB16 __usub16 +#define __UQSUB16 __uqsub16 +#define __UHSUB16 __uhsub16 +#define __SASX __sasx +#define __QASX __qasx +#define __SHASX __shasx +#define __UASX __uasx +#define __UQASX __uqasx +#define __UHASX __uhasx +#define __SSAX __ssax +#define __QSAX __qsax +#define __SHSAX __shsax +#define __USAX __usax +#define __UQSAX __uqsax +#define __UHSAX __uhsax +#define __USAD8 __usad8 +#define __USADA8 __usada8 +#define __SSAT16 __ssat16 +#define __USAT16 __usat16 +#define __UXTB16 __uxtb16 +#define __UXTAB16 __uxtab16 +#define __SXTB16 __sxtb16 +#define __SXTAB16 __sxtab16 +#define __SMUAD __smuad +#define __SMUADX __smuadx +#define __SMLAD __smlad +#define __SMLADX __smladx +#define __SMLALD __smlald +#define __SMLALDX __smlaldx +#define __SMUSD __smusd +#define __SMUSDX __smusdx +#define __SMLSD __smlsd +#define __SMLSDX __smlsdx +#define __SMLSLD __smlsld +#define __SMLSLDX __smlsldx +#define __SEL __sel +#define __QADD __qadd +#define __QSUB __qsub + +#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ + ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) + +#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ + ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) + +#define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \ + ((int64_t)(ARG3) << 32U) ) >> 32U)) + +#define __SXTB16_RORn(ARG1, ARG2) __SXTB16(__ROR(ARG1, ARG2)) + +#define __SXTAB16_RORn(ARG1, ARG2, ARG3) __SXTAB16(ARG1, __ROR(ARG2, ARG3)) + +#endif /* ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#endif /* __CMSIS_ARMCC_H */ diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/CMSIS/Core/Include/cmsis_armclang.h b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/CMSIS/Core/Include/cmsis_armclang.h new file mode 100644 index 0000000000..6911417747 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/CMSIS/Core/Include/cmsis_armclang.h @@ -0,0 +1,1503 @@ +/**************************************************************************//** + * @file cmsis_armclang.h + * @brief CMSIS compiler armclang (Arm Compiler 6) header file + * @version V5.4.3 + * @date 27. May 2021 + ******************************************************************************/ +/* + * Copyright (c) 2009-2021 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/*lint -esym(9058, IRQn)*/ /* disable MISRA 2012 Rule 2.4 for IRQn */ + +#ifndef __CMSIS_ARMCLANG_H +#define __CMSIS_ARMCLANG_H + +#pragma clang system_header /* treat file as system include file */ + +/* CMSIS compiler specific defines */ +#ifndef __ASM + #define __ASM __asm +#endif +#ifndef __INLINE + #define __INLINE __inline +#endif +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static __inline +#endif +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __attribute__((always_inline)) static __inline +#endif +#ifndef __NO_RETURN + #define __NO_RETURN __attribute__((__noreturn__)) +#endif +#ifndef __USED + #define __USED __attribute__((used)) +#endif +#ifndef __WEAK + #define __WEAK __attribute__((weak)) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_UNION + #define __PACKED_UNION union __attribute__((packed, aligned(1))) +#endif +#ifndef __UNALIGNED_UINT32 /* deprecated */ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32 */ + struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) +#endif +#ifndef __UNALIGNED_UINT16_WRITE + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT16_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_WRITE */ + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT16_READ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT16_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_READ */ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) +#endif +#ifndef __UNALIGNED_UINT32_WRITE + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_WRITE */ + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT32_READ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_READ */ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) +#endif +#ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __RESTRICT + #define __RESTRICT __restrict +#endif +#ifndef __COMPILER_BARRIER + #define __COMPILER_BARRIER() __ASM volatile("":::"memory") +#endif + +/* ######################### Startup and Lowlevel Init ######################## */ + +#ifndef __PROGRAM_START +#define __PROGRAM_START __main +#endif + +#ifndef __INITIAL_SP +#define __INITIAL_SP Image$$ARM_LIB_STACK$$ZI$$Limit +#endif + +#ifndef __STACK_LIMIT +#define __STACK_LIMIT Image$$ARM_LIB_STACK$$ZI$$Base +#endif + +#ifndef __VECTOR_TABLE +#define __VECTOR_TABLE __Vectors +#endif + +#ifndef __VECTOR_TABLE_ATTRIBUTE +#define __VECTOR_TABLE_ATTRIBUTE __attribute__((used, section("RESET"))) +#endif + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +#ifndef __STACK_SEAL +#define __STACK_SEAL Image$$STACKSEAL$$ZI$$Base +#endif + +#ifndef __TZ_STACK_SEAL_SIZE +#define __TZ_STACK_SEAL_SIZE 8U +#endif + +#ifndef __TZ_STACK_SEAL_VALUE +#define __TZ_STACK_SEAL_VALUE 0xFEF5EDA5FEF5EDA5ULL +#endif + + +__STATIC_FORCEINLINE void __TZ_set_STACKSEAL_S (uint32_t* stackTop) { + *((uint64_t *)stackTop) = __TZ_STACK_SEAL_VALUE; +} +#endif + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/* Define macros for porting to both thumb1 and thumb2. + * For thumb1, use low register (r0-r7), specified by constraint "l" + * Otherwise, use general registers, specified by constraint "r" */ +#if defined (__thumb__) && !defined (__thumb2__) +#define __CMSIS_GCC_OUT_REG(r) "=l" (r) +#define __CMSIS_GCC_RW_REG(r) "+l" (r) +#define __CMSIS_GCC_USE_REG(r) "l" (r) +#else +#define __CMSIS_GCC_OUT_REG(r) "=r" (r) +#define __CMSIS_GCC_RW_REG(r) "+r" (r) +#define __CMSIS_GCC_USE_REG(r) "r" (r) +#endif + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP __builtin_arm_nop + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +#define __WFI __builtin_arm_wfi + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE __builtin_arm_wfe + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV __builtin_arm_sev + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +#define __ISB() __builtin_arm_isb(0xF) + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +#define __DSB() __builtin_arm_dsb(0xF) + + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +#define __DMB() __builtin_arm_dmb(0xF) + + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV(value) __builtin_bswap32(value) + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV16(value) __ROR(__REV(value), 16) + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REVSH(value) (int16_t)__builtin_bswap16(value) + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) +{ + op2 %= 32U; + if (op2 == 0U) + { + return op1; + } + return (op1 >> op2) | (op1 << (32U - op2)); +} + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __ASM volatile ("bkpt "#value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +#define __RBIT __builtin_arm_rbit + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +__STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value) +{ + /* Even though __builtin_clz produces a CLZ instruction on ARM, formally + __builtin_clz(0) is undefined behaviour, so handle this case specially. + This guarantees ARM-compatible results if happening to compile on a non-ARM + target, and ensures the compiler doesn't decide to activate any + optimisations using the logic "value was passed to __builtin_clz, so it + is non-zero". + ARM Compiler 6.10 and possibly earlier will optimise this test away, leaving a + single CLZ instruction. + */ + if (value == 0U) + { + return 32U; + } + return __builtin_clz(value); +} + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) + +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDREXB (uint8_t)__builtin_arm_ldrex + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDREXH (uint16_t)__builtin_arm_ldrex + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDREXW (uint32_t)__builtin_arm_ldrex + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXB (uint32_t)__builtin_arm_strex + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXH (uint32_t)__builtin_arm_strex + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXW (uint32_t)__builtin_arm_strex + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +#define __CLREX __builtin_arm_clrex + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT __builtin_arm_ssat + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT __builtin_arm_usat + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) ); +} + +#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) */ + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat) +{ + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; +} + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat) +{ + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) + +/** + \brief Load-Acquire (8 bit) + \details Executes a LDAB instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return ((uint8_t) result); +} + + +/** + \brief Load-Acquire (16 bit) + \details Executes a LDAH instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return ((uint16_t) result); +} + + +/** + \brief Load-Acquire (32 bit) + \details Executes a LDA instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return(result); +} + + +/** + \brief Store-Release (8 bit) + \details Executes a STLB instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Store-Release (16 bit) + \details Executes a STLH instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Store-Release (32 bit) + \details Executes a STL instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Load-Acquire Exclusive (8 bit) + \details Executes a LDAB exclusive instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDAEXB (uint8_t)__builtin_arm_ldaex + + +/** + \brief Load-Acquire Exclusive (16 bit) + \details Executes a LDAH exclusive instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDAEXH (uint16_t)__builtin_arm_ldaex + + +/** + \brief Load-Acquire Exclusive (32 bit) + \details Executes a LDA exclusive instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDAEX (uint32_t)__builtin_arm_ldaex + + +/** + \brief Store-Release Exclusive (8 bit) + \details Executes a STLB exclusive instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEXB (uint32_t)__builtin_arm_stlex + + +/** + \brief Store-Release Exclusive (16 bit) + \details Executes a STLH exclusive instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEXH (uint32_t)__builtin_arm_stlex + + +/** + \brief Store-Release Exclusive (32 bit) + \details Executes a STL exclusive instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEX (uint32_t)__builtin_arm_stlex + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing special-purpose register PRIMASK. + Can only be executed in Privileged modes. + */ +#ifndef __ARM_COMPAT_H +__STATIC_FORCEINLINE void __enable_irq(void) +{ + __ASM volatile ("cpsie i" : : : "memory"); +} +#endif + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting special-purpose register PRIMASK. + Can only be executed in Privileged modes. + */ +#ifndef __ARM_COMPAT_H +__STATIC_FORCEINLINE void __disable_irq(void) +{ + __ASM volatile ("cpsid i" : : : "memory"); +} +#endif + + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CONTROL(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Control Register (non-secure) + \details Returns the content of the non-secure Control Register when in secure mode. + \return non-secure Control Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) +{ + __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); + __ISB(); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Control Register (non-secure) + \details Writes the given value to the non-secure Control Register when in secure state. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) +{ + __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); + __ISB(); +} +#endif + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_IPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_APSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_xPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer (non-secure) + \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state. + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state. + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); +} +#endif + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer (non-secure) + \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state. + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); +} +#endif + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Stack Pointer (non-secure) + \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state. + \return SP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, sp_ns" : "=r" (result) ); + return(result); +} + + +/** + \brief Set Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state. + \param [in] topOfStack Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack) +{ + __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : ); +} +#endif + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Priority Mask (non-secure) + \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Priority Mask (non-secure) + \details Assigns the given value to the non-secure Priority Mask Register when in secure state. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) +{ + __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); +} +#endif + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing special-purpose register FAULTMASK. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __enable_fault_irq(void) +{ + __ASM volatile ("cpsie f" : : : "memory"); +} + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting special-purpose register FAULTMASK. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __disable_fault_irq(void) +{ + __ASM volatile ("cpsid f" : : : "memory"); +} + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Base Priority (non-secure) + \details Returns the current value of the non-secure Base Priority register when in secure state. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri) +{ + __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Base Priority (non-secure) + \details Assigns the given value to the non-secure Base Priority register when in secure state. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); +} +#endif + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Fault Mask (non-secure) + \details Returns the current value of the non-secure Fault Mask register when in secure state. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Fault Mask (non-secure) + \details Assigns the given value to the non-secure Fault Mask register when in secure state. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); +} +#endif + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) + +/** + \brief Get Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void) +{ +#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim" : "=r" (result) ); + return result; +#endif +} + +#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) +{ +#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) ) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) +{ +#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) +{ +#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) ) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); +#endif +} +#endif + + +/** + \brief Get Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void) +{ +#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim" : "=r" (result) ); + return result; +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state. + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void) +{ +#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) ) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). + \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) +{ +#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state. + \param [in] MainStackPtrLimit Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) +{ +#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) ) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); +#endif +} +#endif + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) */ + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#define __get_FPSCR (uint32_t)__builtin_arm_get_fpscr +#else +#define __get_FPSCR() ((uint32_t)0U) +#endif + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#define __set_FPSCR __builtin_arm_set_fpscr +#else +#define __set_FPSCR(x) ((void)(x)) +#endif + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) + +#define __SADD8 __builtin_arm_sadd8 +#define __QADD8 __builtin_arm_qadd8 +#define __SHADD8 __builtin_arm_shadd8 +#define __UADD8 __builtin_arm_uadd8 +#define __UQADD8 __builtin_arm_uqadd8 +#define __UHADD8 __builtin_arm_uhadd8 +#define __SSUB8 __builtin_arm_ssub8 +#define __QSUB8 __builtin_arm_qsub8 +#define __SHSUB8 __builtin_arm_shsub8 +#define __USUB8 __builtin_arm_usub8 +#define __UQSUB8 __builtin_arm_uqsub8 +#define __UHSUB8 __builtin_arm_uhsub8 +#define __SADD16 __builtin_arm_sadd16 +#define __QADD16 __builtin_arm_qadd16 +#define __SHADD16 __builtin_arm_shadd16 +#define __UADD16 __builtin_arm_uadd16 +#define __UQADD16 __builtin_arm_uqadd16 +#define __UHADD16 __builtin_arm_uhadd16 +#define __SSUB16 __builtin_arm_ssub16 +#define __QSUB16 __builtin_arm_qsub16 +#define __SHSUB16 __builtin_arm_shsub16 +#define __USUB16 __builtin_arm_usub16 +#define __UQSUB16 __builtin_arm_uqsub16 +#define __UHSUB16 __builtin_arm_uhsub16 +#define __SASX __builtin_arm_sasx +#define __QASX __builtin_arm_qasx +#define __SHASX __builtin_arm_shasx +#define __UASX __builtin_arm_uasx +#define __UQASX __builtin_arm_uqasx +#define __UHASX __builtin_arm_uhasx +#define __SSAX __builtin_arm_ssax +#define __QSAX __builtin_arm_qsax +#define __SHSAX __builtin_arm_shsax +#define __USAX __builtin_arm_usax +#define __UQSAX __builtin_arm_uqsax +#define __UHSAX __builtin_arm_uhsax +#define __USAD8 __builtin_arm_usad8 +#define __USADA8 __builtin_arm_usada8 +#define __SSAT16 __builtin_arm_ssat16 +#define __USAT16 __builtin_arm_usat16 +#define __UXTB16 __builtin_arm_uxtb16 +#define __UXTAB16 __builtin_arm_uxtab16 +#define __SXTB16 __builtin_arm_sxtb16 +#define __SXTAB16 __builtin_arm_sxtab16 +#define __SMUAD __builtin_arm_smuad +#define __SMUADX __builtin_arm_smuadx +#define __SMLAD __builtin_arm_smlad +#define __SMLADX __builtin_arm_smladx +#define __SMLALD __builtin_arm_smlald +#define __SMLALDX __builtin_arm_smlaldx +#define __SMUSD __builtin_arm_smusd +#define __SMUSDX __builtin_arm_smusdx +#define __SMLSD __builtin_arm_smlsd +#define __SMLSDX __builtin_arm_smlsdx +#define __SMLSLD __builtin_arm_smlsld +#define __SMLSLDX __builtin_arm_smlsldx +#define __SEL __builtin_arm_sel +#define __QADD __builtin_arm_qadd +#define __QSUB __builtin_arm_qsub + +#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ + ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) + +#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ + ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) + +#define __SXTB16_RORn(ARG1, ARG2) __SXTB16(__ROR(ARG1, ARG2)) + +#define __SXTAB16_RORn(ARG1, ARG2, ARG3) __SXTAB16(ARG1, __ROR(ARG2, ARG3)) + +__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) +{ + int32_t result; + + __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#endif /* (__ARM_FEATURE_DSP == 1) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#endif /* __CMSIS_ARMCLANG_H */ diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/CMSIS/Core/Include/cmsis_armclang_ltm.h b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/CMSIS/Core/Include/cmsis_armclang_ltm.h new file mode 100644 index 0000000000..1e255d5907 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/CMSIS/Core/Include/cmsis_armclang_ltm.h @@ -0,0 +1,1928 @@ +/**************************************************************************//** + * @file cmsis_armclang_ltm.h + * @brief CMSIS compiler armclang (Arm Compiler 6) header file + * @version V1.5.3 + * @date 27. May 2021 + ******************************************************************************/ +/* + * Copyright (c) 2018-2021 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/*lint -esym(9058, IRQn)*/ /* disable MISRA 2012 Rule 2.4 for IRQn */ + +#ifndef __CMSIS_ARMCLANG_H +#define __CMSIS_ARMCLANG_H + +#pragma clang system_header /* treat file as system include file */ + +/* CMSIS compiler specific defines */ +#ifndef __ASM + #define __ASM __asm +#endif +#ifndef __INLINE + #define __INLINE __inline +#endif +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static __inline +#endif +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __attribute__((always_inline)) static __inline +#endif +#ifndef __NO_RETURN + #define __NO_RETURN __attribute__((__noreturn__)) +#endif +#ifndef __USED + #define __USED __attribute__((used)) +#endif +#ifndef __WEAK + #define __WEAK __attribute__((weak)) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_UNION + #define __PACKED_UNION union __attribute__((packed, aligned(1))) +#endif +#ifndef __UNALIGNED_UINT32 /* deprecated */ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32 */ + struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) +#endif +#ifndef __UNALIGNED_UINT16_WRITE + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT16_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_WRITE */ + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT16_READ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT16_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_READ */ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) +#endif +#ifndef __UNALIGNED_UINT32_WRITE + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_WRITE */ + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT32_READ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_READ */ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) +#endif +#ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __RESTRICT + #define __RESTRICT __restrict +#endif +#ifndef __COMPILER_BARRIER + #define __COMPILER_BARRIER() __ASM volatile("":::"memory") +#endif + +/* ######################### Startup and Lowlevel Init ######################## */ + +#ifndef __PROGRAM_START +#define __PROGRAM_START __main +#endif + +#ifndef __INITIAL_SP +#define __INITIAL_SP Image$$ARM_LIB_STACK$$ZI$$Limit +#endif + +#ifndef __STACK_LIMIT +#define __STACK_LIMIT Image$$ARM_LIB_STACK$$ZI$$Base +#endif + +#ifndef __VECTOR_TABLE +#define __VECTOR_TABLE __Vectors +#endif + +#ifndef __VECTOR_TABLE_ATTRIBUTE +#define __VECTOR_TABLE_ATTRIBUTE __attribute__((used, section("RESET"))) +#endif + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +#ifndef __STACK_SEAL +#define __STACK_SEAL Image$$STACKSEAL$$ZI$$Base +#endif + +#ifndef __TZ_STACK_SEAL_SIZE +#define __TZ_STACK_SEAL_SIZE 8U +#endif + +#ifndef __TZ_STACK_SEAL_VALUE +#define __TZ_STACK_SEAL_VALUE 0xFEF5EDA5FEF5EDA5ULL +#endif + + +__STATIC_FORCEINLINE void __TZ_set_STACKSEAL_S (uint32_t* stackTop) { + *((uint64_t *)stackTop) = __TZ_STACK_SEAL_VALUE; +} +#endif + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/* Define macros for porting to both thumb1 and thumb2. + * For thumb1, use low register (r0-r7), specified by constraint "l" + * Otherwise, use general registers, specified by constraint "r" */ +#if defined (__thumb__) && !defined (__thumb2__) +#define __CMSIS_GCC_OUT_REG(r) "=l" (r) +#define __CMSIS_GCC_USE_REG(r) "l" (r) +#else +#define __CMSIS_GCC_OUT_REG(r) "=r" (r) +#define __CMSIS_GCC_USE_REG(r) "r" (r) +#endif + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP __builtin_arm_nop + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +#define __WFI __builtin_arm_wfi + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE __builtin_arm_wfe + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV __builtin_arm_sev + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +#define __ISB() __builtin_arm_isb(0xF) + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +#define __DSB() __builtin_arm_dsb(0xF) + + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +#define __DMB() __builtin_arm_dmb(0xF) + + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV(value) __builtin_bswap32(value) + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV16(value) __ROR(__REV(value), 16) + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REVSH(value) (int16_t)__builtin_bswap16(value) + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) +{ + op2 %= 32U; + if (op2 == 0U) + { + return op1; + } + return (op1 >> op2) | (op1 << (32U - op2)); +} + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __ASM volatile ("bkpt "#value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +#define __RBIT __builtin_arm_rbit + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +__STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value) +{ + /* Even though __builtin_clz produces a CLZ instruction on ARM, formally + __builtin_clz(0) is undefined behaviour, so handle this case specially. + This guarantees ARM-compatible results if happening to compile on a non-ARM + target, and ensures the compiler doesn't decide to activate any + optimisations using the logic "value was passed to __builtin_clz, so it + is non-zero". + ARM Compiler 6.10 and possibly earlier will optimise this test away, leaving a + single CLZ instruction. + */ + if (value == 0U) + { + return 32U; + } + return __builtin_clz(value); +} + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDREXB (uint8_t)__builtin_arm_ldrex + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDREXH (uint16_t)__builtin_arm_ldrex + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDREXW (uint32_t)__builtin_arm_ldrex + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXB (uint32_t)__builtin_arm_strex + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXH (uint32_t)__builtin_arm_strex + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXW (uint32_t)__builtin_arm_strex + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +#define __CLREX __builtin_arm_clrex + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT __builtin_arm_ssat + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT __builtin_arm_usat + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) ); +} + +#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat) +{ + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; +} + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat) +{ + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief Load-Acquire (8 bit) + \details Executes a LDAB instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return ((uint8_t) result); +} + + +/** + \brief Load-Acquire (16 bit) + \details Executes a LDAH instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return ((uint16_t) result); +} + + +/** + \brief Load-Acquire (32 bit) + \details Executes a LDA instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return(result); +} + + +/** + \brief Store-Release (8 bit) + \details Executes a STLB instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Store-Release (16 bit) + \details Executes a STLH instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Store-Release (32 bit) + \details Executes a STL instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Load-Acquire Exclusive (8 bit) + \details Executes a LDAB exclusive instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDAEXB (uint8_t)__builtin_arm_ldaex + + +/** + \brief Load-Acquire Exclusive (16 bit) + \details Executes a LDAH exclusive instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDAEXH (uint16_t)__builtin_arm_ldaex + + +/** + \brief Load-Acquire Exclusive (32 bit) + \details Executes a LDA exclusive instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDAEX (uint32_t)__builtin_arm_ldaex + + +/** + \brief Store-Release Exclusive (8 bit) + \details Executes a STLB exclusive instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEXB (uint32_t)__builtin_arm_stlex + + +/** + \brief Store-Release Exclusive (16 bit) + \details Executes a STLH exclusive instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEXH (uint32_t)__builtin_arm_stlex + + +/** + \brief Store-Release Exclusive (32 bit) + \details Executes a STL exclusive instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEX (uint32_t)__builtin_arm_stlex + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing special-purpose register PRIMASK. + Can only be executed in Privileged modes. + */ +#ifndef __ARM_COMPAT_H +__STATIC_FORCEINLINE void __enable_irq(void) +{ + __ASM volatile ("cpsie i" : : : "memory"); +} +#endif + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting special-purpose register PRIMASK. + Can only be executed in Privileged modes. + */ +#ifndef __ARM_COMPAT_H +__STATIC_FORCEINLINE void __disable_irq(void) +{ + __ASM volatile ("cpsid i" : : : "memory"); +} +#endif + + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CONTROL(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Control Register (non-secure) + \details Returns the content of the non-secure Control Register when in secure mode. + \return non-secure Control Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) +{ + __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); + __ISB(); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Control Register (non-secure) + \details Writes the given value to the non-secure Control Register when in secure state. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) +{ + __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); + __ISB(); +} +#endif + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_IPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_APSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_xPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer (non-secure) + \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state. + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state. + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); +} +#endif + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer (non-secure) + \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state. + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); +} +#endif + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Stack Pointer (non-secure) + \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state. + \return SP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, sp_ns" : "=r" (result) ); + return(result); +} + + +/** + \brief Set Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state. + \param [in] topOfStack Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack) +{ + __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : ); +} +#endif + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Priority Mask (non-secure) + \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Priority Mask (non-secure) + \details Assigns the given value to the non-secure Priority Mask Register when in secure state. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) +{ + __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); +} +#endif + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing special-purpose register FAULTMASK. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __enable_fault_irq(void) +{ + __ASM volatile ("cpsie f" : : : "memory"); +} + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting special-purpose register FAULTMASK. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __disable_fault_irq(void) +{ + __ASM volatile ("cpsid f" : : : "memory"); +} + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Base Priority (non-secure) + \details Returns the current value of the non-secure Base Priority register when in secure state. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri) +{ + __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Base Priority (non-secure) + \details Assigns the given value to the non-secure Base Priority register when in secure state. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); +} +#endif + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Fault Mask (non-secure) + \details Returns the current value of the non-secure Fault Mask register when in secure state. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Fault Mask (non-secure) + \details Assigns the given value to the non-secure Fault Mask register when in secure state. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); +} +#endif + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + +/** + \brief Get Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim" : "=r" (result) ); + return result; +#endif +} + +#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); +#endif +} +#endif + + +/** + \brief Get Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim" : "=r" (result) ); + return result; +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state. + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). + \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state. + \param [in] MainStackPtrLimit Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); +#endif +} +#endif + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#define __get_FPSCR (uint32_t)__builtin_arm_get_fpscr +#else +#define __get_FPSCR() ((uint32_t)0U) +#endif + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#define __set_FPSCR __builtin_arm_set_fpscr +#else +#define __set_FPSCR(x) ((void)(x)) +#endif + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) + +__STATIC_FORCEINLINE uint32_t __SADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__STATIC_FORCEINLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__STATIC_FORCEINLINE uint32_t __SADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USAD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#define __SSAT16(ARG1,ARG2) \ +({ \ + int32_t __RES, __ARG1 = (ARG1); \ + __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +#define __USAT16(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +__STATIC_FORCEINLINE uint32_t __UXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint32_t __SEL (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE int32_t __QADD( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE int32_t __QSUB( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ + ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) + +#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ + ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) + +#define __SXTB16_RORn(ARG1, ARG2) __SXTB16(__ROR(ARG1, ARG2)) + +#define __SXTAB16_RORn(ARG1, ARG2, ARG3) __SXTAB16(ARG1, __ROR(ARG2, ARG3)) + +__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) +{ + int32_t result; + + __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#endif /* (__ARM_FEATURE_DSP == 1) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#endif /* __CMSIS_ARMCLANG_H */ diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/CMSIS/Core/Include/cmsis_compiler.h b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/CMSIS/Core/Include/cmsis_compiler.h new file mode 100644 index 0000000000..adbf296f15 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/CMSIS/Core/Include/cmsis_compiler.h @@ -0,0 +1,283 @@ +/**************************************************************************//** + * @file cmsis_compiler.h + * @brief CMSIS compiler generic header file + * @version V5.1.0 + * @date 09. October 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_COMPILER_H +#define __CMSIS_COMPILER_H + +#include + +/* + * Arm Compiler 4/5 + */ +#if defined ( __CC_ARM ) + #include "cmsis_armcc.h" + + +/* + * Arm Compiler 6.6 LTM (armclang) + */ +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) && (__ARMCC_VERSION < 6100100) + #include "cmsis_armclang_ltm.h" + + /* + * Arm Compiler above 6.10.1 (armclang) + */ +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6100100) + #include "cmsis_armclang.h" + + +/* + * GNU Compiler + */ +#elif defined ( __GNUC__ ) + #include "cmsis_gcc.h" + + +/* + * IAR Compiler + */ +#elif defined ( __ICCARM__ ) + #include + + +/* + * TI Arm Compiler + */ +#elif defined ( __TI_ARM__ ) + #include + + #ifndef __ASM + #define __ASM __asm + #endif + #ifndef __INLINE + #define __INLINE inline + #endif + #ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline + #endif + #ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __STATIC_INLINE + #endif + #ifndef __NO_RETURN + #define __NO_RETURN __attribute__((noreturn)) + #endif + #ifndef __USED + #define __USED __attribute__((used)) + #endif + #ifndef __WEAK + #define __WEAK __attribute__((weak)) + #endif + #ifndef __PACKED + #define __PACKED __attribute__((packed)) + #endif + #ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed)) + #endif + #ifndef __PACKED_UNION + #define __PACKED_UNION union __attribute__((packed)) + #endif + #ifndef __UNALIGNED_UINT32 /* deprecated */ + struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + #endif + #ifndef __UNALIGNED_UINT16_WRITE + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void*)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT16_READ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) + #endif + #ifndef __UNALIGNED_UINT32_WRITE + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT32_READ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) + #endif + #ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) + #endif + #ifndef __RESTRICT + #define __RESTRICT __restrict + #endif + #ifndef __COMPILER_BARRIER + #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored. + #define __COMPILER_BARRIER() (void)0 + #endif + + +/* + * TASKING Compiler + */ +#elif defined ( __TASKING__ ) + /* + * The CMSIS functions have been implemented as intrinsics in the compiler. + * Please use "carm -?i" to get an up to date list of all intrinsics, + * Including the CMSIS ones. + */ + + #ifndef __ASM + #define __ASM __asm + #endif + #ifndef __INLINE + #define __INLINE inline + #endif + #ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline + #endif + #ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __STATIC_INLINE + #endif + #ifndef __NO_RETURN + #define __NO_RETURN __attribute__((noreturn)) + #endif + #ifndef __USED + #define __USED __attribute__((used)) + #endif + #ifndef __WEAK + #define __WEAK __attribute__((weak)) + #endif + #ifndef __PACKED + #define __PACKED __packed__ + #endif + #ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __packed__ + #endif + #ifndef __PACKED_UNION + #define __PACKED_UNION union __packed__ + #endif + #ifndef __UNALIGNED_UINT32 /* deprecated */ + struct __packed__ T_UINT32 { uint32_t v; }; + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + #endif + #ifndef __UNALIGNED_UINT16_WRITE + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT16_READ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) + #endif + #ifndef __UNALIGNED_UINT32_WRITE + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT32_READ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) + #endif + #ifndef __ALIGNED + #define __ALIGNED(x) __align(x) + #endif + #ifndef __RESTRICT + #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. + #define __RESTRICT + #endif + #ifndef __COMPILER_BARRIER + #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored. + #define __COMPILER_BARRIER() (void)0 + #endif + + +/* + * COSMIC Compiler + */ +#elif defined ( __CSMC__ ) + #include + + #ifndef __ASM + #define __ASM _asm + #endif + #ifndef __INLINE + #define __INLINE inline + #endif + #ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline + #endif + #ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __STATIC_INLINE + #endif + #ifndef __NO_RETURN + // NO RETURN is automatically detected hence no warning here + #define __NO_RETURN + #endif + #ifndef __USED + #warning No compiler specific solution for __USED. __USED is ignored. + #define __USED + #endif + #ifndef __WEAK + #define __WEAK __weak + #endif + #ifndef __PACKED + #define __PACKED @packed + #endif + #ifndef __PACKED_STRUCT + #define __PACKED_STRUCT @packed struct + #endif + #ifndef __PACKED_UNION + #define __PACKED_UNION @packed union + #endif + #ifndef __UNALIGNED_UINT32 /* deprecated */ + @packed struct T_UINT32 { uint32_t v; }; + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + #endif + #ifndef __UNALIGNED_UINT16_WRITE + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT16_READ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) + #endif + #ifndef __UNALIGNED_UINT32_WRITE + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT32_READ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) + #endif + #ifndef __ALIGNED + #warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored. + #define __ALIGNED(x) + #endif + #ifndef __RESTRICT + #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. + #define __RESTRICT + #endif + #ifndef __COMPILER_BARRIER + #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored. + #define __COMPILER_BARRIER() (void)0 + #endif + + +#else + #error Unknown compiler. +#endif + + +#endif /* __CMSIS_COMPILER_H */ + diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/CMSIS/Core/Include/cmsis_gcc.h b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/CMSIS/Core/Include/cmsis_gcc.h new file mode 100644 index 0000000000..67bda4ef3c --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/CMSIS/Core/Include/cmsis_gcc.h @@ -0,0 +1,2211 @@ +/**************************************************************************//** + * @file cmsis_gcc.h + * @brief CMSIS compiler GCC header file + * @version V5.4.1 + * @date 27. May 2021 + ******************************************************************************/ +/* + * Copyright (c) 2009-2021 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_GCC_H +#define __CMSIS_GCC_H + +/* ignore some GCC warnings */ +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wsign-conversion" +#pragma GCC diagnostic ignored "-Wconversion" +#pragma GCC diagnostic ignored "-Wunused-parameter" + +/* Fallback for __has_builtin */ +#ifndef __has_builtin + #define __has_builtin(x) (0) +#endif + +/* CMSIS compiler specific defines */ +#ifndef __ASM + #define __ASM __asm +#endif +#ifndef __INLINE + #define __INLINE inline +#endif +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline +#endif +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __attribute__((always_inline)) static inline +#endif +#ifndef __NO_RETURN + #define __NO_RETURN __attribute__((__noreturn__)) +#endif +#ifndef __USED + #define __USED __attribute__((used)) +#endif +#ifndef __WEAK + #define __WEAK __attribute__((weak)) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_UNION + #define __PACKED_UNION union __attribute__((packed, aligned(1))) +#endif +#ifndef __UNALIGNED_UINT32 /* deprecated */ + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) +#endif +#ifndef __UNALIGNED_UINT16_WRITE + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT16_READ + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) +#endif +#ifndef __UNALIGNED_UINT32_WRITE + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT32_READ + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) +#endif +#ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __RESTRICT + #define __RESTRICT __restrict +#endif +#ifndef __COMPILER_BARRIER + #define __COMPILER_BARRIER() __ASM volatile("":::"memory") +#endif + +/* ######################### Startup and Lowlevel Init ######################## */ + +#ifndef __PROGRAM_START + +/** + \brief Initializes data and bss sections + \details This default implementations initialized all data and additional bss + sections relying on .copy.table and .zero.table specified properly + in the used linker script. + + */ +__STATIC_FORCEINLINE __NO_RETURN void __cmsis_start(void) +{ + extern void _start(void) __NO_RETURN; + + typedef struct { + uint32_t const* src; + uint32_t* dest; + uint32_t wlen; + } __copy_table_t; + + typedef struct { + uint32_t* dest; + uint32_t wlen; + } __zero_table_t; + + extern const __copy_table_t __copy_table_start__; + extern const __copy_table_t __copy_table_end__; + extern const __zero_table_t __zero_table_start__; + extern const __zero_table_t __zero_table_end__; + + for (__copy_table_t const* pTable = &__copy_table_start__; pTable < &__copy_table_end__; ++pTable) { + for(uint32_t i=0u; iwlen; ++i) { + pTable->dest[i] = pTable->src[i]; + } + } + + for (__zero_table_t const* pTable = &__zero_table_start__; pTable < &__zero_table_end__; ++pTable) { + for(uint32_t i=0u; iwlen; ++i) { + pTable->dest[i] = 0u; + } + } + + _start(); +} + +#define __PROGRAM_START __cmsis_start +#endif + +#ifndef __INITIAL_SP +#define __INITIAL_SP __StackTop +#endif + +#ifndef __STACK_LIMIT +#define __STACK_LIMIT __StackLimit +#endif + +#ifndef __VECTOR_TABLE +#define __VECTOR_TABLE __Vectors +#endif + +#ifndef __VECTOR_TABLE_ATTRIBUTE +#define __VECTOR_TABLE_ATTRIBUTE __attribute__((used, section(".vectors"))) +#endif + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +#ifndef __STACK_SEAL +#define __STACK_SEAL __StackSeal +#endif + +#ifndef __TZ_STACK_SEAL_SIZE +#define __TZ_STACK_SEAL_SIZE 8U +#endif + +#ifndef __TZ_STACK_SEAL_VALUE +#define __TZ_STACK_SEAL_VALUE 0xFEF5EDA5FEF5EDA5ULL +#endif + + +__STATIC_FORCEINLINE void __TZ_set_STACKSEAL_S (uint32_t* stackTop) { + *((uint64_t *)stackTop) = __TZ_STACK_SEAL_VALUE; +} +#endif + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/* Define macros for porting to both thumb1 and thumb2. + * For thumb1, use low register (r0-r7), specified by constraint "l" + * Otherwise, use general registers, specified by constraint "r" */ +#if defined (__thumb__) && !defined (__thumb2__) +#define __CMSIS_GCC_OUT_REG(r) "=l" (r) +#define __CMSIS_GCC_RW_REG(r) "+l" (r) +#define __CMSIS_GCC_USE_REG(r) "l" (r) +#else +#define __CMSIS_GCC_OUT_REG(r) "=r" (r) +#define __CMSIS_GCC_RW_REG(r) "+r" (r) +#define __CMSIS_GCC_USE_REG(r) "r" (r) +#endif + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP() __ASM volatile ("nop") + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +#define __WFI() __ASM volatile ("wfi":::"memory") + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE() __ASM volatile ("wfe":::"memory") + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV() __ASM volatile ("sev") + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +__STATIC_FORCEINLINE void __ISB(void) +{ + __ASM volatile ("isb 0xF":::"memory"); +} + + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +__STATIC_FORCEINLINE void __DSB(void) +{ + __ASM volatile ("dsb 0xF":::"memory"); +} + + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +__STATIC_FORCEINLINE void __DMB(void) +{ + __ASM volatile ("dmb 0xF":::"memory"); +} + + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE uint32_t __REV(uint32_t value) +{ +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5) + return __builtin_bswap32(value); +#else + uint32_t result; + + __ASM ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return result; +#endif +} + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE uint32_t __REV16(uint32_t value) +{ + uint32_t result; + + __ASM ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return result; +} + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE int16_t __REVSH(int16_t value) +{ +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + return (int16_t)__builtin_bswap16(value); +#else + int16_t result; + + __ASM ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return result; +#endif +} + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) +{ + op2 %= 32U; + if (op2 == 0U) + { + return op1; + } + return (op1 >> op2) | (op1 << (32U - op2)); +} + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __ASM volatile ("bkpt "#value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE uint32_t __RBIT(uint32_t value) +{ + uint32_t result; + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) + __ASM ("rbit %0, %1" : "=r" (result) : "r" (value) ); +#else + uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */ + + result = value; /* r will be reversed bits of v; first get LSB of v */ + for (value >>= 1U; value != 0U; value >>= 1U) + { + result <<= 1U; + result |= value & 1U; + s--; + } + result <<= s; /* shift when v's highest bits are zero */ +#endif + return result; +} + + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +__STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value) +{ + /* Even though __builtin_clz produces a CLZ instruction on ARM, formally + __builtin_clz(0) is undefined behaviour, so handle this case specially. + This guarantees ARM-compatible results if happening to compile on a non-ARM + target, and ensures the compiler doesn't decide to activate any + optimisations using the logic "value was passed to __builtin_clz, so it + is non-zero". + ARM GCC 7.3 and possibly earlier will optimise this test away, leaving a + single CLZ instruction. + */ + if (value == 0U) + { + return 32U; + } + return __builtin_clz(value); +} + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDREXB(volatile uint8_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDREXH(volatile uint16_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDREXW(volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); + return(result); +} + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr) +{ + uint32_t result; + + __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr) +{ + uint32_t result; + + __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); + return(result); +} + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +__STATIC_FORCEINLINE void __CLREX(void) +{ + __ASM volatile ("clrex" ::: "memory"); +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] ARG1 Value to be saturated + \param [in] ARG2 Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT(ARG1, ARG2) \ +__extension__ \ +({ \ + int32_t __RES, __ARG1 = (ARG1); \ + __ASM volatile ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) : "cc" ); \ + __RES; \ + }) + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] ARG1 Value to be saturated + \param [in] ARG2 Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT(ARG1, ARG2) \ +__extension__ \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM volatile ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) : "cc" ); \ + __RES; \ + }) + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" ); +#endif + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" ); +#endif + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) ); +} + +#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat) +{ + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; +} + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat) +{ + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief Load-Acquire (8 bit) + \details Executes a LDAB instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return ((uint8_t) result); +} + + +/** + \brief Load-Acquire (16 bit) + \details Executes a LDAH instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return ((uint16_t) result); +} + + +/** + \brief Load-Acquire (32 bit) + \details Executes a LDA instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return(result); +} + + +/** + \brief Store-Release (8 bit) + \details Executes a STLB instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Store-Release (16 bit) + \details Executes a STLH instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Store-Release (32 bit) + \details Executes a STL instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Load-Acquire Exclusive (8 bit) + \details Executes a LDAB exclusive instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDAEXB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldaexb %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return ((uint8_t) result); +} + + +/** + \brief Load-Acquire Exclusive (16 bit) + \details Executes a LDAH exclusive instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDAEXH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldaexh %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return ((uint16_t) result); +} + + +/** + \brief Load-Acquire Exclusive (32 bit) + \details Executes a LDA exclusive instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDAEX(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldaex %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return(result); +} + + +/** + \brief Store-Release Exclusive (8 bit) + \details Executes a STLB exclusive instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("stlexb %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); + return(result); +} + + +/** + \brief Store-Release Exclusive (16 bit) + \details Executes a STLH exclusive instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("stlexh %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); + return(result); +} + + +/** + \brief Store-Release Exclusive (32 bit) + \details Executes a STL exclusive instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("stlex %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); + return(result); +} + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing special-purpose register PRIMASK. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __enable_irq(void) +{ + __ASM volatile ("cpsie i" : : : "memory"); +} + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting special-purpose register PRIMASK. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __disable_irq(void) +{ + __ASM volatile ("cpsid i" : : : "memory"); +} + + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CONTROL(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Control Register (non-secure) + \details Returns the content of the non-secure Control Register when in secure mode. + \return non-secure Control Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) +{ + __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); + __ISB(); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Control Register (non-secure) + \details Writes the given value to the non-secure Control Register when in secure state. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) +{ + __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); + __ISB(); +} +#endif + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_IPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_APSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_xPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer (non-secure) + \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state. + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state. + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); +} +#endif + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer (non-secure) + \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state. + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); +} +#endif + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Stack Pointer (non-secure) + \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state. + \return SP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, sp_ns" : "=r" (result) ); + return(result); +} + + +/** + \brief Set Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state. + \param [in] topOfStack Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack) +{ + __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : ); +} +#endif + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Priority Mask (non-secure) + \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Priority Mask (non-secure) + \details Assigns the given value to the non-secure Priority Mask Register when in secure state. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) +{ + __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); +} +#endif + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing special-purpose register FAULTMASK. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __enable_fault_irq(void) +{ + __ASM volatile ("cpsie f" : : : "memory"); +} + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting special-purpose register FAULTMASK. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __disable_fault_irq(void) +{ + __ASM volatile ("cpsid f" : : : "memory"); +} + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Base Priority (non-secure) + \details Returns the current value of the non-secure Base Priority register when in secure state. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri) +{ + __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Base Priority (non-secure) + \details Assigns the given value to the non-secure Base Priority register when in secure state. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); +} +#endif + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Fault Mask (non-secure) + \details Returns the current value of the non-secure Fault Mask register when in secure state. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Fault Mask (non-secure) + \details Assigns the given value to the non-secure Fault Mask register when in secure state. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); +} +#endif + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + +/** + \brief Get Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim" : "=r" (result) ); + return result; +#endif +} + +#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); +#endif +} +#endif + + +/** + \brief Get Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim" : "=r" (result) ); + return result; +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state. + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). + \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state. + \param [in] MainStackPtrLimit Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); +#endif +} +#endif + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +__STATIC_FORCEINLINE uint32_t __get_FPSCR(void) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#if __has_builtin(__builtin_arm_get_fpscr) +// Re-enable using built-in when GCC has been fixed +// || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2) + /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */ + return __builtin_arm_get_fpscr(); +#else + uint32_t result; + + __ASM volatile ("VMRS %0, fpscr" : "=r" (result) ); + return(result); +#endif +#else + return(0U); +#endif +} + + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +__STATIC_FORCEINLINE void __set_FPSCR(uint32_t fpscr) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#if __has_builtin(__builtin_arm_set_fpscr) +// Re-enable using built-in when GCC has been fixed +// || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2) + /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */ + __builtin_arm_set_fpscr(fpscr); +#else + __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc", "memory"); +#endif +#else + (void)fpscr; +#endif +} + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) + +__STATIC_FORCEINLINE uint32_t __SADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__STATIC_FORCEINLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__STATIC_FORCEINLINE uint32_t __SADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USAD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#define __SSAT16(ARG1, ARG2) \ +__extension__ \ +({ \ + int32_t __RES, __ARG1 = (ARG1); \ + __ASM volatile ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) : "cc" ); \ + __RES; \ + }) + +#define __USAT16(ARG1, ARG2) \ +__extension__ \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM volatile ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) : "cc" ); \ + __RES; \ + }) + +__STATIC_FORCEINLINE uint32_t __UXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM ("uxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM ("sxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTB16_RORn(uint32_t op1, uint32_t rotate) +{ + uint32_t result; + if (__builtin_constant_p(rotate) && ((rotate == 8U) || (rotate == 16U) || (rotate == 24U))) { + __ASM volatile ("sxtb16 %0, %1, ROR %2" : "=r" (result) : "r" (op1), "i" (rotate) ); + } else { + result = __SXTB16(__ROR(op1, rotate)) ; + } + return result; +} + +__STATIC_FORCEINLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTAB16_RORn(uint32_t op1, uint32_t op2, uint32_t rotate) +{ + uint32_t result; + if (__builtin_constant_p(rotate) && ((rotate == 8U) || (rotate == 16U) || (rotate == 24U))) { + __ASM volatile ("sxtab16 %0, %1, %2, ROR %3" : "=r" (result) : "r" (op1) , "r" (op2) , "i" (rotate)); + } else { + result = __SXTAB16(op1, __ROR(op2, rotate)); + } + return result; +} + + +__STATIC_FORCEINLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint32_t __SEL (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE int32_t __QADD( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE int32_t __QSUB( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +#define __PKHBT(ARG1,ARG2,ARG3) \ +__extension__ \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) + +#define __PKHTB(ARG1,ARG2,ARG3) \ +__extension__ \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + if (ARG3 == 0) \ + __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \ + else \ + __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) + + +__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) +{ + int32_t result; + + __ASM ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#endif /* (__ARM_FEATURE_DSP == 1) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#pragma GCC diagnostic pop + +#endif /* __CMSIS_GCC_H */ diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/CMSIS/Core/Include/cmsis_iccarm.h b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/CMSIS/Core/Include/cmsis_iccarm.h new file mode 100644 index 0000000000..65b824b009 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/CMSIS/Core/Include/cmsis_iccarm.h @@ -0,0 +1,1002 @@ +/**************************************************************************//** + * @file cmsis_iccarm.h + * @brief CMSIS compiler ICCARM (IAR Compiler for Arm) header file + * @version V5.3.0 + * @date 14. April 2021 + ******************************************************************************/ + +//------------------------------------------------------------------------------ +// +// Copyright (c) 2017-2021 IAR Systems +// Copyright (c) 2017-2021 Arm Limited. All rights reserved. +// +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License") +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +//------------------------------------------------------------------------------ + + +#ifndef __CMSIS_ICCARM_H__ +#define __CMSIS_ICCARM_H__ + +#ifndef __ICCARM__ + #error This file should only be compiled by ICCARM +#endif + +#pragma system_include + +#define __IAR_FT _Pragma("inline=forced") __intrinsic + +#if (__VER__ >= 8000000) + #define __ICCARM_V8 1 +#else + #define __ICCARM_V8 0 +#endif + +#ifndef __ALIGNED + #if __ICCARM_V8 + #define __ALIGNED(x) __attribute__((aligned(x))) + #elif (__VER__ >= 7080000) + /* Needs IAR language extensions */ + #define __ALIGNED(x) __attribute__((aligned(x))) + #else + #warning No compiler specific solution for __ALIGNED.__ALIGNED is ignored. + #define __ALIGNED(x) + #endif +#endif + + +/* Define compiler macros for CPU architecture, used in CMSIS 5. + */ +#if __ARM_ARCH_6M__ || __ARM_ARCH_7M__ || __ARM_ARCH_7EM__ || __ARM_ARCH_8M_BASE__ || __ARM_ARCH_8M_MAIN__ +/* Macros already defined */ +#else + #if defined(__ARM8M_MAINLINE__) || defined(__ARM8EM_MAINLINE__) + #define __ARM_ARCH_8M_MAIN__ 1 + #elif defined(__ARM8M_BASELINE__) + #define __ARM_ARCH_8M_BASE__ 1 + #elif defined(__ARM_ARCH_PROFILE) && __ARM_ARCH_PROFILE == 'M' + #if __ARM_ARCH == 6 + #define __ARM_ARCH_6M__ 1 + #elif __ARM_ARCH == 7 + #if __ARM_FEATURE_DSP + #define __ARM_ARCH_7EM__ 1 + #else + #define __ARM_ARCH_7M__ 1 + #endif + #endif /* __ARM_ARCH */ + #endif /* __ARM_ARCH_PROFILE == 'M' */ +#endif + +/* Alternativ core deduction for older ICCARM's */ +#if !defined(__ARM_ARCH_6M__) && !defined(__ARM_ARCH_7M__) && !defined(__ARM_ARCH_7EM__) && \ + !defined(__ARM_ARCH_8M_BASE__) && !defined(__ARM_ARCH_8M_MAIN__) + #if defined(__ARM6M__) && (__CORE__ == __ARM6M__) + #define __ARM_ARCH_6M__ 1 + #elif defined(__ARM7M__) && (__CORE__ == __ARM7M__) + #define __ARM_ARCH_7M__ 1 + #elif defined(__ARM7EM__) && (__CORE__ == __ARM7EM__) + #define __ARM_ARCH_7EM__ 1 + #elif defined(__ARM8M_BASELINE__) && (__CORE == __ARM8M_BASELINE__) + #define __ARM_ARCH_8M_BASE__ 1 + #elif defined(__ARM8M_MAINLINE__) && (__CORE == __ARM8M_MAINLINE__) + #define __ARM_ARCH_8M_MAIN__ 1 + #elif defined(__ARM8EM_MAINLINE__) && (__CORE == __ARM8EM_MAINLINE__) + #define __ARM_ARCH_8M_MAIN__ 1 + #else + #error "Unknown target." + #endif +#endif + + + +#if defined(__ARM_ARCH_6M__) && __ARM_ARCH_6M__==1 + #define __IAR_M0_FAMILY 1 +#elif defined(__ARM_ARCH_8M_BASE__) && __ARM_ARCH_8M_BASE__==1 + #define __IAR_M0_FAMILY 1 +#else + #define __IAR_M0_FAMILY 0 +#endif + + +#ifndef __ASM + #define __ASM __asm +#endif + +#ifndef __COMPILER_BARRIER + #define __COMPILER_BARRIER() __ASM volatile("":::"memory") +#endif + +#ifndef __INLINE + #define __INLINE inline +#endif + +#ifndef __NO_RETURN + #if __ICCARM_V8 + #define __NO_RETURN __attribute__((__noreturn__)) + #else + #define __NO_RETURN _Pragma("object_attribute=__noreturn") + #endif +#endif + +#ifndef __PACKED + #if __ICCARM_V8 + #define __PACKED __attribute__((packed, aligned(1))) + #else + /* Needs IAR language extensions */ + #define __PACKED __packed + #endif +#endif + +#ifndef __PACKED_STRUCT + #if __ICCARM_V8 + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) + #else + /* Needs IAR language extensions */ + #define __PACKED_STRUCT __packed struct + #endif +#endif + +#ifndef __PACKED_UNION + #if __ICCARM_V8 + #define __PACKED_UNION union __attribute__((packed, aligned(1))) + #else + /* Needs IAR language extensions */ + #define __PACKED_UNION __packed union + #endif +#endif + +#ifndef __RESTRICT + #if __ICCARM_V8 + #define __RESTRICT __restrict + #else + /* Needs IAR language extensions */ + #define __RESTRICT restrict + #endif +#endif + +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline +#endif + +#ifndef __FORCEINLINE + #define __FORCEINLINE _Pragma("inline=forced") +#endif + +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __FORCEINLINE __STATIC_INLINE +#endif + +#ifndef __UNALIGNED_UINT16_READ +#pragma language=save +#pragma language=extended +__IAR_FT uint16_t __iar_uint16_read(void const *ptr) +{ + return *(__packed uint16_t*)(ptr); +} +#pragma language=restore +#define __UNALIGNED_UINT16_READ(PTR) __iar_uint16_read(PTR) +#endif + + +#ifndef __UNALIGNED_UINT16_WRITE +#pragma language=save +#pragma language=extended +__IAR_FT void __iar_uint16_write(void const *ptr, uint16_t val) +{ + *(__packed uint16_t*)(ptr) = val;; +} +#pragma language=restore +#define __UNALIGNED_UINT16_WRITE(PTR,VAL) __iar_uint16_write(PTR,VAL) +#endif + +#ifndef __UNALIGNED_UINT32_READ +#pragma language=save +#pragma language=extended +__IAR_FT uint32_t __iar_uint32_read(void const *ptr) +{ + return *(__packed uint32_t*)(ptr); +} +#pragma language=restore +#define __UNALIGNED_UINT32_READ(PTR) __iar_uint32_read(PTR) +#endif + +#ifndef __UNALIGNED_UINT32_WRITE +#pragma language=save +#pragma language=extended +__IAR_FT void __iar_uint32_write(void const *ptr, uint32_t val) +{ + *(__packed uint32_t*)(ptr) = val;; +} +#pragma language=restore +#define __UNALIGNED_UINT32_WRITE(PTR,VAL) __iar_uint32_write(PTR,VAL) +#endif + +#ifndef __UNALIGNED_UINT32 /* deprecated */ +#pragma language=save +#pragma language=extended +__packed struct __iar_u32 { uint32_t v; }; +#pragma language=restore +#define __UNALIGNED_UINT32(PTR) (((struct __iar_u32 *)(PTR))->v) +#endif + +#ifndef __USED + #if __ICCARM_V8 + #define __USED __attribute__((used)) + #else + #define __USED _Pragma("__root") + #endif +#endif + +#undef __WEAK /* undo the definition from DLib_Defaults.h */ +#ifndef __WEAK + #if __ICCARM_V8 + #define __WEAK __attribute__((weak)) + #else + #define __WEAK _Pragma("__weak") + #endif +#endif + +#ifndef __PROGRAM_START +#define __PROGRAM_START __iar_program_start +#endif + +#ifndef __INITIAL_SP +#define __INITIAL_SP CSTACK$$Limit +#endif + +#ifndef __STACK_LIMIT +#define __STACK_LIMIT CSTACK$$Base +#endif + +#ifndef __VECTOR_TABLE +#define __VECTOR_TABLE __vector_table +#endif + +#ifndef __VECTOR_TABLE_ATTRIBUTE +#define __VECTOR_TABLE_ATTRIBUTE @".intvec" +#endif + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +#ifndef __STACK_SEAL +#define __STACK_SEAL STACKSEAL$$Base +#endif + +#ifndef __TZ_STACK_SEAL_SIZE +#define __TZ_STACK_SEAL_SIZE 8U +#endif + +#ifndef __TZ_STACK_SEAL_VALUE +#define __TZ_STACK_SEAL_VALUE 0xFEF5EDA5FEF5EDA5ULL +#endif + +__STATIC_FORCEINLINE void __TZ_set_STACKSEAL_S (uint32_t* stackTop) { + *((uint64_t *)stackTop) = __TZ_STACK_SEAL_VALUE; +} +#endif + +#ifndef __ICCARM_INTRINSICS_VERSION__ + #define __ICCARM_INTRINSICS_VERSION__ 0 +#endif + +#if __ICCARM_INTRINSICS_VERSION__ == 2 + + #if defined(__CLZ) + #undef __CLZ + #endif + #if defined(__REVSH) + #undef __REVSH + #endif + #if defined(__RBIT) + #undef __RBIT + #endif + #if defined(__SSAT) + #undef __SSAT + #endif + #if defined(__USAT) + #undef __USAT + #endif + + #include "iccarm_builtin.h" + + #define __disable_fault_irq __iar_builtin_disable_fiq + #define __disable_irq __iar_builtin_disable_interrupt + #define __enable_fault_irq __iar_builtin_enable_fiq + #define __enable_irq __iar_builtin_enable_interrupt + #define __arm_rsr __iar_builtin_rsr + #define __arm_wsr __iar_builtin_wsr + + + #define __get_APSR() (__arm_rsr("APSR")) + #define __get_BASEPRI() (__arm_rsr("BASEPRI")) + #define __get_CONTROL() (__arm_rsr("CONTROL")) + #define __get_FAULTMASK() (__arm_rsr("FAULTMASK")) + + #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) + #define __get_FPSCR() (__arm_rsr("FPSCR")) + #define __set_FPSCR(VALUE) (__arm_wsr("FPSCR", (VALUE))) + #else + #define __get_FPSCR() ( 0 ) + #define __set_FPSCR(VALUE) ((void)VALUE) + #endif + + #define __get_IPSR() (__arm_rsr("IPSR")) + #define __get_MSP() (__arm_rsr("MSP")) + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + #define __get_MSPLIM() (0U) + #else + #define __get_MSPLIM() (__arm_rsr("MSPLIM")) + #endif + #define __get_PRIMASK() (__arm_rsr("PRIMASK")) + #define __get_PSP() (__arm_rsr("PSP")) + + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + #define __get_PSPLIM() (0U) + #else + #define __get_PSPLIM() (__arm_rsr("PSPLIM")) + #endif + + #define __get_xPSR() (__arm_rsr("xPSR")) + + #define __set_BASEPRI(VALUE) (__arm_wsr("BASEPRI", (VALUE))) + #define __set_BASEPRI_MAX(VALUE) (__arm_wsr("BASEPRI_MAX", (VALUE))) + +__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) +{ + __arm_wsr("CONTROL", control); + __iar_builtin_ISB(); +} + + #define __set_FAULTMASK(VALUE) (__arm_wsr("FAULTMASK", (VALUE))) + #define __set_MSP(VALUE) (__arm_wsr("MSP", (VALUE))) + + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + #define __set_MSPLIM(VALUE) ((void)(VALUE)) + #else + #define __set_MSPLIM(VALUE) (__arm_wsr("MSPLIM", (VALUE))) + #endif + #define __set_PRIMASK(VALUE) (__arm_wsr("PRIMASK", (VALUE))) + #define __set_PSP(VALUE) (__arm_wsr("PSP", (VALUE))) + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + #define __set_PSPLIM(VALUE) ((void)(VALUE)) + #else + #define __set_PSPLIM(VALUE) (__arm_wsr("PSPLIM", (VALUE))) + #endif + + #define __TZ_get_CONTROL_NS() (__arm_rsr("CONTROL_NS")) + +__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) +{ + __arm_wsr("CONTROL_NS", control); + __iar_builtin_ISB(); +} + + #define __TZ_get_PSP_NS() (__arm_rsr("PSP_NS")) + #define __TZ_set_PSP_NS(VALUE) (__arm_wsr("PSP_NS", (VALUE))) + #define __TZ_get_MSP_NS() (__arm_rsr("MSP_NS")) + #define __TZ_set_MSP_NS(VALUE) (__arm_wsr("MSP_NS", (VALUE))) + #define __TZ_get_SP_NS() (__arm_rsr("SP_NS")) + #define __TZ_set_SP_NS(VALUE) (__arm_wsr("SP_NS", (VALUE))) + #define __TZ_get_PRIMASK_NS() (__arm_rsr("PRIMASK_NS")) + #define __TZ_set_PRIMASK_NS(VALUE) (__arm_wsr("PRIMASK_NS", (VALUE))) + #define __TZ_get_BASEPRI_NS() (__arm_rsr("BASEPRI_NS")) + #define __TZ_set_BASEPRI_NS(VALUE) (__arm_wsr("BASEPRI_NS", (VALUE))) + #define __TZ_get_FAULTMASK_NS() (__arm_rsr("FAULTMASK_NS")) + #define __TZ_set_FAULTMASK_NS(VALUE)(__arm_wsr("FAULTMASK_NS", (VALUE))) + + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + #define __TZ_get_PSPLIM_NS() (0U) + #define __TZ_set_PSPLIM_NS(VALUE) ((void)(VALUE)) + #else + #define __TZ_get_PSPLIM_NS() (__arm_rsr("PSPLIM_NS")) + #define __TZ_set_PSPLIM_NS(VALUE) (__arm_wsr("PSPLIM_NS", (VALUE))) + #endif + + #define __TZ_get_MSPLIM_NS() (__arm_rsr("MSPLIM_NS")) + #define __TZ_set_MSPLIM_NS(VALUE) (__arm_wsr("MSPLIM_NS", (VALUE))) + + #define __NOP __iar_builtin_no_operation + + #define __CLZ __iar_builtin_CLZ + #define __CLREX __iar_builtin_CLREX + + #define __DMB __iar_builtin_DMB + #define __DSB __iar_builtin_DSB + #define __ISB __iar_builtin_ISB + + #define __LDREXB __iar_builtin_LDREXB + #define __LDREXH __iar_builtin_LDREXH + #define __LDREXW __iar_builtin_LDREX + + #define __RBIT __iar_builtin_RBIT + #define __REV __iar_builtin_REV + #define __REV16 __iar_builtin_REV16 + + __IAR_FT int16_t __REVSH(int16_t val) + { + return (int16_t) __iar_builtin_REVSH(val); + } + + #define __ROR __iar_builtin_ROR + #define __RRX __iar_builtin_RRX + + #define __SEV __iar_builtin_SEV + + #if !__IAR_M0_FAMILY + #define __SSAT __iar_builtin_SSAT + #endif + + #define __STREXB __iar_builtin_STREXB + #define __STREXH __iar_builtin_STREXH + #define __STREXW __iar_builtin_STREX + + #if !__IAR_M0_FAMILY + #define __USAT __iar_builtin_USAT + #endif + + #define __WFE __iar_builtin_WFE + #define __WFI __iar_builtin_WFI + + #if __ARM_MEDIA__ + #define __SADD8 __iar_builtin_SADD8 + #define __QADD8 __iar_builtin_QADD8 + #define __SHADD8 __iar_builtin_SHADD8 + #define __UADD8 __iar_builtin_UADD8 + #define __UQADD8 __iar_builtin_UQADD8 + #define __UHADD8 __iar_builtin_UHADD8 + #define __SSUB8 __iar_builtin_SSUB8 + #define __QSUB8 __iar_builtin_QSUB8 + #define __SHSUB8 __iar_builtin_SHSUB8 + #define __USUB8 __iar_builtin_USUB8 + #define __UQSUB8 __iar_builtin_UQSUB8 + #define __UHSUB8 __iar_builtin_UHSUB8 + #define __SADD16 __iar_builtin_SADD16 + #define __QADD16 __iar_builtin_QADD16 + #define __SHADD16 __iar_builtin_SHADD16 + #define __UADD16 __iar_builtin_UADD16 + #define __UQADD16 __iar_builtin_UQADD16 + #define __UHADD16 __iar_builtin_UHADD16 + #define __SSUB16 __iar_builtin_SSUB16 + #define __QSUB16 __iar_builtin_QSUB16 + #define __SHSUB16 __iar_builtin_SHSUB16 + #define __USUB16 __iar_builtin_USUB16 + #define __UQSUB16 __iar_builtin_UQSUB16 + #define __UHSUB16 __iar_builtin_UHSUB16 + #define __SASX __iar_builtin_SASX + #define __QASX __iar_builtin_QASX + #define __SHASX __iar_builtin_SHASX + #define __UASX __iar_builtin_UASX + #define __UQASX __iar_builtin_UQASX + #define __UHASX __iar_builtin_UHASX + #define __SSAX __iar_builtin_SSAX + #define __QSAX __iar_builtin_QSAX + #define __SHSAX __iar_builtin_SHSAX + #define __USAX __iar_builtin_USAX + #define __UQSAX __iar_builtin_UQSAX + #define __UHSAX __iar_builtin_UHSAX + #define __USAD8 __iar_builtin_USAD8 + #define __USADA8 __iar_builtin_USADA8 + #define __SSAT16 __iar_builtin_SSAT16 + #define __USAT16 __iar_builtin_USAT16 + #define __UXTB16 __iar_builtin_UXTB16 + #define __UXTAB16 __iar_builtin_UXTAB16 + #define __SXTB16 __iar_builtin_SXTB16 + #define __SXTAB16 __iar_builtin_SXTAB16 + #define __SMUAD __iar_builtin_SMUAD + #define __SMUADX __iar_builtin_SMUADX + #define __SMMLA __iar_builtin_SMMLA + #define __SMLAD __iar_builtin_SMLAD + #define __SMLADX __iar_builtin_SMLADX + #define __SMLALD __iar_builtin_SMLALD + #define __SMLALDX __iar_builtin_SMLALDX + #define __SMUSD __iar_builtin_SMUSD + #define __SMUSDX __iar_builtin_SMUSDX + #define __SMLSD __iar_builtin_SMLSD + #define __SMLSDX __iar_builtin_SMLSDX + #define __SMLSLD __iar_builtin_SMLSLD + #define __SMLSLDX __iar_builtin_SMLSLDX + #define __SEL __iar_builtin_SEL + #define __QADD __iar_builtin_QADD + #define __QSUB __iar_builtin_QSUB + #define __PKHBT __iar_builtin_PKHBT + #define __PKHTB __iar_builtin_PKHTB + #endif + +#else /* __ICCARM_INTRINSICS_VERSION__ == 2 */ + + #if __IAR_M0_FAMILY + /* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */ + #define __CLZ __cmsis_iar_clz_not_active + #define __SSAT __cmsis_iar_ssat_not_active + #define __USAT __cmsis_iar_usat_not_active + #define __RBIT __cmsis_iar_rbit_not_active + #define __get_APSR __cmsis_iar_get_APSR_not_active + #endif + + + #if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) )) + #define __get_FPSCR __cmsis_iar_get_FPSR_not_active + #define __set_FPSCR __cmsis_iar_set_FPSR_not_active + #endif + + #ifdef __INTRINSICS_INCLUDED + #error intrinsics.h is already included previously! + #endif + + #include + + #if __IAR_M0_FAMILY + /* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */ + #undef __CLZ + #undef __SSAT + #undef __USAT + #undef __RBIT + #undef __get_APSR + + __STATIC_INLINE uint8_t __CLZ(uint32_t data) + { + if (data == 0U) { return 32U; } + + uint32_t count = 0U; + uint32_t mask = 0x80000000U; + + while ((data & mask) == 0U) + { + count += 1U; + mask = mask >> 1U; + } + return count; + } + + __STATIC_INLINE uint32_t __RBIT(uint32_t v) + { + uint8_t sc = 31U; + uint32_t r = v; + for (v >>= 1U; v; v >>= 1U) + { + r <<= 1U; + r |= v & 1U; + sc--; + } + return (r << sc); + } + + __STATIC_INLINE uint32_t __get_APSR(void) + { + uint32_t res; + __asm("MRS %0,APSR" : "=r" (res)); + return res; + } + + #endif + + #if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) )) + #undef __get_FPSCR + #undef __set_FPSCR + #define __get_FPSCR() (0) + #define __set_FPSCR(VALUE) ((void)VALUE) + #endif + + #pragma diag_suppress=Pe940 + #pragma diag_suppress=Pe177 + + #define __enable_irq __enable_interrupt + #define __disable_irq __disable_interrupt + #define __NOP __no_operation + + #define __get_xPSR __get_PSR + + #if (!defined(__ARM_ARCH_6M__) || __ARM_ARCH_6M__==0) + + __IAR_FT uint32_t __LDREXW(uint32_t volatile *ptr) + { + return __LDREX((unsigned long *)ptr); + } + + __IAR_FT uint32_t __STREXW(uint32_t value, uint32_t volatile *ptr) + { + return __STREX(value, (unsigned long *)ptr); + } + #endif + + + /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */ + #if (__CORTEX_M >= 0x03) + + __IAR_FT uint32_t __RRX(uint32_t value) + { + uint32_t result; + __ASM volatile("RRX %0, %1" : "=r"(result) : "r" (value)); + return(result); + } + + __IAR_FT void __set_BASEPRI_MAX(uint32_t value) + { + __asm volatile("MSR BASEPRI_MAX,%0"::"r" (value)); + } + + + #define __enable_fault_irq __enable_fiq + #define __disable_fault_irq __disable_fiq + + + #endif /* (__CORTEX_M >= 0x03) */ + + __IAR_FT uint32_t __ROR(uint32_t op1, uint32_t op2) + { + return (op1 >> op2) | (op1 << ((sizeof(op1)*8)-op2)); + } + + #if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + + __IAR_FT uint32_t __get_MSPLIM(void) + { + uint32_t res; + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + res = 0U; + #else + __asm volatile("MRS %0,MSPLIM" : "=r" (res)); + #endif + return res; + } + + __IAR_FT void __set_MSPLIM(uint32_t value) + { + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)value; + #else + __asm volatile("MSR MSPLIM,%0" :: "r" (value)); + #endif + } + + __IAR_FT uint32_t __get_PSPLIM(void) + { + uint32_t res; + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + res = 0U; + #else + __asm volatile("MRS %0,PSPLIM" : "=r" (res)); + #endif + return res; + } + + __IAR_FT void __set_PSPLIM(uint32_t value) + { + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)value; + #else + __asm volatile("MSR PSPLIM,%0" :: "r" (value)); + #endif + } + + __IAR_FT uint32_t __TZ_get_CONTROL_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,CONTROL_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_CONTROL_NS(uint32_t value) + { + __asm volatile("MSR CONTROL_NS,%0" :: "r" (value)); + __iar_builtin_ISB(); + } + + __IAR_FT uint32_t __TZ_get_PSP_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,PSP_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_PSP_NS(uint32_t value) + { + __asm volatile("MSR PSP_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_MSP_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,MSP_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_MSP_NS(uint32_t value) + { + __asm volatile("MSR MSP_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_SP_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,SP_NS" : "=r" (res)); + return res; + } + __IAR_FT void __TZ_set_SP_NS(uint32_t value) + { + __asm volatile("MSR SP_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_PRIMASK_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,PRIMASK_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_PRIMASK_NS(uint32_t value) + { + __asm volatile("MSR PRIMASK_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_BASEPRI_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,BASEPRI_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_BASEPRI_NS(uint32_t value) + { + __asm volatile("MSR BASEPRI_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_FAULTMASK_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,FAULTMASK_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_FAULTMASK_NS(uint32_t value) + { + __asm volatile("MSR FAULTMASK_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_PSPLIM_NS(void) + { + uint32_t res; + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + res = 0U; + #else + __asm volatile("MRS %0,PSPLIM_NS" : "=r" (res)); + #endif + return res; + } + + __IAR_FT void __TZ_set_PSPLIM_NS(uint32_t value) + { + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)value; + #else + __asm volatile("MSR PSPLIM_NS,%0" :: "r" (value)); + #endif + } + + __IAR_FT uint32_t __TZ_get_MSPLIM_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,MSPLIM_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_MSPLIM_NS(uint32_t value) + { + __asm volatile("MSR MSPLIM_NS,%0" :: "r" (value)); + } + + #endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */ + +#endif /* __ICCARM_INTRINSICS_VERSION__ == 2 */ + +#define __BKPT(value) __asm volatile ("BKPT %0" : : "i"(value)) + +#if __IAR_M0_FAMILY + __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat) + { + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; + } + + __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat) + { + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; + } +#endif + +#if (__CORTEX_M >= 0x03) /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */ + + __IAR_FT uint8_t __LDRBT(volatile uint8_t *addr) + { + uint32_t res; + __ASM volatile ("LDRBT %0, [%1]" : "=r" (res) : "r" (addr) : "memory"); + return ((uint8_t)res); + } + + __IAR_FT uint16_t __LDRHT(volatile uint16_t *addr) + { + uint32_t res; + __ASM volatile ("LDRHT %0, [%1]" : "=r" (res) : "r" (addr) : "memory"); + return ((uint16_t)res); + } + + __IAR_FT uint32_t __LDRT(volatile uint32_t *addr) + { + uint32_t res; + __ASM volatile ("LDRT %0, [%1]" : "=r" (res) : "r" (addr) : "memory"); + return res; + } + + __IAR_FT void __STRBT(uint8_t value, volatile uint8_t *addr) + { + __ASM volatile ("STRBT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory"); + } + + __IAR_FT void __STRHT(uint16_t value, volatile uint16_t *addr) + { + __ASM volatile ("STRHT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory"); + } + + __IAR_FT void __STRT(uint32_t value, volatile uint32_t *addr) + { + __ASM volatile ("STRT %1, [%0]" : : "r" (addr), "r" (value) : "memory"); + } + +#endif /* (__CORTEX_M >= 0x03) */ + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + + + __IAR_FT uint8_t __LDAB(volatile uint8_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return ((uint8_t)res); + } + + __IAR_FT uint16_t __LDAH(volatile uint16_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return ((uint16_t)res); + } + + __IAR_FT uint32_t __LDA(volatile uint32_t *ptr) + { + uint32_t res; + __ASM volatile ("LDA %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return res; + } + + __IAR_FT void __STLB(uint8_t value, volatile uint8_t *ptr) + { + __ASM volatile ("STLB %1, [%0]" :: "r" (ptr), "r" (value) : "memory"); + } + + __IAR_FT void __STLH(uint16_t value, volatile uint16_t *ptr) + { + __ASM volatile ("STLH %1, [%0]" :: "r" (ptr), "r" (value) : "memory"); + } + + __IAR_FT void __STL(uint32_t value, volatile uint32_t *ptr) + { + __ASM volatile ("STL %1, [%0]" :: "r" (ptr), "r" (value) : "memory"); + } + + __IAR_FT uint8_t __LDAEXB(volatile uint8_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAEXB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return ((uint8_t)res); + } + + __IAR_FT uint16_t __LDAEXH(volatile uint16_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAEXH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return ((uint16_t)res); + } + + __IAR_FT uint32_t __LDAEX(volatile uint32_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAEX %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return res; + } + + __IAR_FT uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr) + { + uint32_t res; + __ASM volatile ("STLEXB %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory"); + return res; + } + + __IAR_FT uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr) + { + uint32_t res; + __ASM volatile ("STLEXH %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory"); + return res; + } + + __IAR_FT uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr) + { + uint32_t res; + __ASM volatile ("STLEX %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory"); + return res; + } + +#endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */ + +#undef __IAR_FT +#undef __IAR_M0_FAMILY +#undef __ICCARM_V8 + +#pragma diag_default=Pe940 +#pragma diag_default=Pe177 + +#define __SXTB16_RORn(ARG1, ARG2) __SXTB16(__ROR(ARG1, ARG2)) + +#define __SXTAB16_RORn(ARG1, ARG2, ARG3) __SXTAB16(ARG1, __ROR(ARG2, ARG3)) + +#endif /* __CMSIS_ICCARM_H__ */ diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/CMSIS/Core/Include/cmsis_version.h b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/CMSIS/Core/Include/cmsis_version.h new file mode 100644 index 0000000000..8b4765f186 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/CMSIS/Core/Include/cmsis_version.h @@ -0,0 +1,39 @@ +/**************************************************************************//** + * @file cmsis_version.h + * @brief CMSIS Core(M) Version definitions + * @version V5.0.5 + * @date 02. February 2022 + ******************************************************************************/ +/* + * Copyright (c) 2009-2022 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CMSIS_VERSION_H +#define __CMSIS_VERSION_H + +/* CMSIS Version definitions */ +#define __CM_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS Core(M) main version */ +#define __CM_CMSIS_VERSION_SUB ( 6U) /*!< [15:0] CMSIS Core(M) sub version */ +#define __CM_CMSIS_VERSION ((__CM_CMSIS_VERSION_MAIN << 16U) | \ + __CM_CMSIS_VERSION_SUB ) /*!< CMSIS Core(M) version number */ +#endif diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/CMSIS/Core/Include/core_armv81mml.h b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/CMSIS/Core/Include/core_armv81mml.h new file mode 100644 index 0000000000..94128a1a70 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/CMSIS/Core/Include/core_armv81mml.h @@ -0,0 +1,4228 @@ +/**************************************************************************//** + * @file core_armv81mml.h + * @brief CMSIS Armv8.1-M Mainline Core Peripheral Access Layer Header File + * @version V1.4.2 + * @date 13. October 2021 + ******************************************************************************/ +/* + * Copyright (c) 2018-2021 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#elif defined ( __GNUC__ ) + #pragma GCC diagnostic ignored "-Wpedantic" /* disable pedantic warning due to unnamed structs/unions */ +#endif + +#ifndef __CORE_ARMV81MML_H_GENERIC +#define __CORE_ARMV81MML_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_ARMV81MML + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS ARMV81MML definitions */ +#define __ARMv81MML_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __ARMv81MML_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __ARMv81MML_CMSIS_VERSION ((__ARMv81MML_CMSIS_VERSION_MAIN << 16U) | \ + __ARMv81MML_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (81U) /*!< Cortex-M Core */ + +#if defined ( __CC_ARM ) + #error Legacy Arm Compiler does not support Armv8.1-M target architecture. +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_ARMV81MML_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_ARMV81MML_H_DEPENDANT +#define __CORE_ARMV81MML_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __ARMv81MML_REV + #define __ARMv81MML_REV 0x0000U + #warning "__ARMv81MML_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #if __FPU_PRESENT != 0U + #ifndef __FPU_DP + #define __FPU_DP 0U + #warning "__FPU_DP not defined in device header file; using default!" + #endif + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __ICACHE_PRESENT + #define __ICACHE_PRESENT 0U + #warning "__ICACHE_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DCACHE_PRESENT + #define __DCACHE_PRESENT 0U + #warning "__DCACHE_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __PMU_PRESENT + #define __PMU_PRESENT 0U + #warning "__PMU_PRESENT not defined in device header file; using default!" + #endif + + #if __PMU_PRESENT != 0U + #ifndef __PMU_NUM_EVENTCNT + #define __PMU_NUM_EVENTCNT 2U + #warning "__PMU_NUM_EVENTCNT not defined in device header file; using default!" + #elif (__PMU_NUM_EVENTCNT > 31 || __PMU_NUM_EVENTCNT < 2) + #error "__PMU_NUM_EVENTCNT is out of range in device header file!" */ + #endif + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DSP_PRESENT + #define __DSP_PRESENT 0U + #warning "__DSP_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 1U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group ARMv81MML */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core SAU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ +#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */ + uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */ + uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */ +#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */ + +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED6[580U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ + __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ + __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ + __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */ + uint32_t RESERVED7[21U]; + __IOM uint32_t SFSR; /*!< Offset: 0x0E4 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x0E8 (R/W) Secure Fault Address Register */ + uint32_t RESERVED3[69U]; + __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ + __IOM uint32_t RFSR; /*!< Offset: 0x204 (R/W) RAS Fault Status Register */ + uint32_t RESERVED4[14U]; + __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ + uint32_t RESERVED5[1U]; + __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ + uint32_t RESERVED6[1U]; + __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ + __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ + __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ + __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ + __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ + __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ + __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ + __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ + __OM uint32_t BPIALL; /*!< Offset: 0x278 ( /W) Branch Predictor Invalidate All */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ +#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_IESB_Pos 5U /*!< SCB AIRCR: Implicit ESB Enable Position */ +#define SCB_AIRCR_IESB_Msk (1UL << SCB_AIRCR_IESB_Pos) /*!< SCB AIRCR: Implicit ESB Enable Mask */ + +#define SCB_AIRCR_DIT_Pos 4U /*!< SCB AIRCR: Data Independent Timing Position */ +#define SCB_AIRCR_DIT_Msk (1UL << SCB_AIRCR_DIT_Pos) /*!< SCB AIRCR: Data Independent Timing Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_TRD_Pos 20U /*!< SCB CCR: TRD Position */ +#define SCB_CCR_TRD_Msk (1UL << SCB_CCR_TRD_Pos) /*!< SCB CCR: TRD Mask */ + +#define SCB_CCR_LOB_Pos 19U /*!< SCB CCR: LOB Position */ +#define SCB_CCR_LOB_Msk (1UL << SCB_CCR_LOB_Pos) /*!< SCB CCR: LOB Mask */ + +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */ +#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */ +#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */ + +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */ +#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_CFSR_MEMFAULTSR_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */ +#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_PMU_Pos 5U /*!< SCB DFSR: PMU Position */ +#define SCB_DFSR_PMU_Msk (1UL << SCB_DFSR_PMU_Pos) /*!< SCB DFSR: PMU Mask */ + +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/* SCB Non-Secure Access Control Register Definitions */ +#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */ +#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */ + +#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */ +#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */ + +#define SCB_NSACR_CP7_Pos 7U /*!< SCB NSACR: CP7 Position */ +#define SCB_NSACR_CP7_Msk (1UL << SCB_NSACR_CP7_Pos) /*!< SCB NSACR: CP7 Mask */ + +#define SCB_NSACR_CP6_Pos 6U /*!< SCB NSACR: CP6 Position */ +#define SCB_NSACR_CP6_Msk (1UL << SCB_NSACR_CP6_Pos) /*!< SCB NSACR: CP6 Mask */ + +#define SCB_NSACR_CP5_Pos 5U /*!< SCB NSACR: CP5 Position */ +#define SCB_NSACR_CP5_Msk (1UL << SCB_NSACR_CP5_Pos) /*!< SCB NSACR: CP5 Mask */ + +#define SCB_NSACR_CP4_Pos 4U /*!< SCB NSACR: CP4 Position */ +#define SCB_NSACR_CP4_Msk (1UL << SCB_NSACR_CP4_Pos) /*!< SCB NSACR: CP4 Mask */ + +#define SCB_NSACR_CP3_Pos 3U /*!< SCB NSACR: CP3 Position */ +#define SCB_NSACR_CP3_Msk (1UL << SCB_NSACR_CP3_Pos) /*!< SCB NSACR: CP3 Mask */ + +#define SCB_NSACR_CP2_Pos 2U /*!< SCB NSACR: CP2 Position */ +#define SCB_NSACR_CP2_Msk (1UL << SCB_NSACR_CP2_Pos) /*!< SCB NSACR: CP2 Mask */ + +#define SCB_NSACR_CP1_Pos 1U /*!< SCB NSACR: CP1 Position */ +#define SCB_NSACR_CP1_Msk (1UL << SCB_NSACR_CP1_Pos) /*!< SCB NSACR: CP1 Mask */ + +#define SCB_NSACR_CP0_Pos 0U /*!< SCB NSACR: CP0 Position */ +#define SCB_NSACR_CP0_Msk (1UL /*<< SCB_NSACR_CP0_Pos*/) /*!< SCB NSACR: CP0 Mask */ + +/* SCB Debug Feature Register 0 Definitions */ +#define SCB_ID_DFR_UDE_Pos 28U /*!< SCB ID_DFR: UDE Position */ +#define SCB_ID_DFR_UDE_Msk (0xFUL << SCB_ID_DFR_UDE_Pos) /*!< SCB ID_DFR: UDE Mask */ + +#define SCB_ID_DFR_MProfDbg_Pos 20U /*!< SCB ID_DFR: MProfDbg Position */ +#define SCB_ID_DFR_MProfDbg_Msk (0xFUL << SCB_ID_DFR_MProfDbg_Pos) /*!< SCB ID_DFR: MProfDbg Mask */ + +/* SCB Cache Level ID Register Definitions */ +#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ +#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ + +#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ +#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ + +/* SCB Cache Type Register Definitions */ +#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ +#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ + +#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ +#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ + +#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ +#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ + +#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ +#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ + +#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ +#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ + +/* SCB Cache Size ID Register Definitions */ +#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ +#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ + +#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ +#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ + +#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ +#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ + +#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ +#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ + +#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ +#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ + +#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ +#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ + +#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ +#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ + +/* SCB Cache Size Selection Register Definitions */ +#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ +#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ + +#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ +#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ + +/* SCB Software Triggered Interrupt Register Definitions */ +#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ +#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ + +/* SCB RAS Fault Status Register Definitions */ +#define SCB_RFSR_V_Pos 31U /*!< SCB RFSR: V Position */ +#define SCB_RFSR_V_Msk (1UL << SCB_RFSR_V_Pos) /*!< SCB RFSR: V Mask */ + +#define SCB_RFSR_IS_Pos 16U /*!< SCB RFSR: IS Position */ +#define SCB_RFSR_IS_Msk (0x7FFFUL << SCB_RFSR_IS_Pos) /*!< SCB RFSR: IS Mask */ + +#define SCB_RFSR_UET_Pos 0U /*!< SCB RFSR: UET Position */ +#define SCB_RFSR_UET_Msk (3UL /*<< SCB_RFSR_UET_Pos*/) /*!< SCB RFSR: UET Mask */ + +/* SCB D-Cache Invalidate by Set-way Register Definitions */ +#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ +#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ + +#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ +#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ + +/* SCB D-Cache Clean by Set-way Register Definitions */ +#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ +#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ + +#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ +#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ + +/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ +#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ +#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ + +#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ +#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ + __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */ + uint32_t RESERVED6[3U]; + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) ITM Device Type Register */ + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Stimulus Port Register Definitions */ +#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */ +#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */ + +#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */ +#define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */ + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */ +#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */ + +#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */ +#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED14[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED15[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED16[1U]; + __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ + uint32_t RESERVED17[1U]; + __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ + uint32_t RESERVED18[1U]; + __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ + uint32_t RESERVED19[1U]; + __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ + uint32_t RESERVED20[1U]; + __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ + uint32_t RESERVED21[1U]; + __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ + uint32_t RESERVED22[1U]; + __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ + uint32_t RESERVED23[1U]; + __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ + uint32_t RESERVED24[1U]; + __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ + uint32_t RESERVED25[1U]; + __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ + uint32_t RESERVED26[1U]; + __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ + uint32_t RESERVED27[1U]; + __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ + uint32_t RESERVED28[1U]; + __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ + uint32_t RESERVED29[1U]; + __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ + uint32_t RESERVED30[1U]; + __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ + uint32_t RESERVED31[1U]; + __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ + uint32_t RESERVED32[934U]; + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ + uint32_t RESERVED33[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */ +#define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Sizes Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Sizes Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ + uint32_t RESERVED3[809U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) Software Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) Software Lock Status Register */ + uint32_t RESERVED4[4U]; + __IM uint32_t TYPE; /*!< Offset: 0xFC8 (R/ ) Device Identifier Register */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Register */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_SWOSCALER_Pos 0U /*!< TPI ACPR: SWOSCALER Position */ +#define TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/) /*!< TPI ACPR: SWOSCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ +#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ + +#define TPI_FFCR_EnFmt_Pos 0U /*!< TPI FFCR: EnFmt Position */ +#define TPI_FFCR_EnFmt_Msk (0x3UL << /*TPI_FFCR_EnFmt_Pos*/) /*!< TPI FFCR: EnFmt Mask */ + +/* TPI Periodic Synchronization Control Register Definitions */ +#define TPI_PSCR_PSCount_Pos 0U /*!< TPI PSCR: PSCount Position */ +#define TPI_PSCR_PSCount_Msk (0x1FUL /*<< TPI_PSCR_PSCount_Pos*/) /*!< TPI PSCR: TPSCount Mask */ + +/* TPI Software Lock Status Register Definitions */ +#define TPI_LSR_nTT_Pos 1U /*!< TPI LSR: Not thirty-two bit. Position */ +#define TPI_LSR_nTT_Msk (0x1UL << TPI_LSR_nTT_Pos) /*!< TPI LSR: Not thirty-two bit. Mask */ + +#define TPI_LSR_SLK_Pos 1U /*!< TPI LSR: Software Lock status Position */ +#define TPI_LSR_SLK_Msk (0x1UL << TPI_LSR_SLK_Pos) /*!< TPI LSR: Software Lock status Mask */ + +#define TPI_LSR_SLI_Pos 0U /*!< TPI LSR: Software Lock implemented Position */ +#define TPI_LSR_SLI_Msk (0x1UL /*<< TPI_LSR_SLI_Pos*/) /*!< TPI LSR: Software Lock implemented Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFO depth Position */ +#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFO depth Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + +#if defined (__PMU_PRESENT) && (__PMU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_PMU Performance Monitoring Unit (PMU) + \brief Type definitions for the Performance Monitoring Unit (PMU) + @{ + */ + +/** + \brief Structure type to access the Performance Monitoring Unit (PMU). + */ +typedef struct +{ + __IOM uint32_t EVCNTR[__PMU_NUM_EVENTCNT]; /*!< Offset: 0x0 (R/W) PMU Event Counter Registers */ +#if __PMU_NUM_EVENTCNT<31 + uint32_t RESERVED0[31U-__PMU_NUM_EVENTCNT]; +#endif + __IOM uint32_t CCNTR; /*!< Offset: 0x7C (R/W) PMU Cycle Counter Register */ + uint32_t RESERVED1[224]; + __IOM uint32_t EVTYPER[__PMU_NUM_EVENTCNT]; /*!< Offset: 0x400 (R/W) PMU Event Type and Filter Registers */ +#if __PMU_NUM_EVENTCNT<31 + uint32_t RESERVED2[31U-__PMU_NUM_EVENTCNT]; +#endif + __IOM uint32_t CCFILTR; /*!< Offset: 0x47C (R/W) PMU Cycle Counter Filter Register */ + uint32_t RESERVED3[480]; + __IOM uint32_t CNTENSET; /*!< Offset: 0xC00 (R/W) PMU Count Enable Set Register */ + uint32_t RESERVED4[7]; + __IOM uint32_t CNTENCLR; /*!< Offset: 0xC20 (R/W) PMU Count Enable Clear Register */ + uint32_t RESERVED5[7]; + __IOM uint32_t INTENSET; /*!< Offset: 0xC40 (R/W) PMU Interrupt Enable Set Register */ + uint32_t RESERVED6[7]; + __IOM uint32_t INTENCLR; /*!< Offset: 0xC60 (R/W) PMU Interrupt Enable Clear Register */ + uint32_t RESERVED7[7]; + __IOM uint32_t OVSCLR; /*!< Offset: 0xC80 (R/W) PMU Overflow Flag Status Clear Register */ + uint32_t RESERVED8[7]; + __IOM uint32_t SWINC; /*!< Offset: 0xCA0 (R/W) PMU Software Increment Register */ + uint32_t RESERVED9[7]; + __IOM uint32_t OVSSET; /*!< Offset: 0xCC0 (R/W) PMU Overflow Flag Status Set Register */ + uint32_t RESERVED10[79]; + __IOM uint32_t TYPE; /*!< Offset: 0xE00 (R/W) PMU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0xE04 (R/W) PMU Control Register */ + uint32_t RESERVED11[108]; + __IOM uint32_t AUTHSTATUS; /*!< Offset: 0xFB8 (R/W) PMU Authentication Status Register */ + __IOM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/W) PMU Device Architecture Register */ + uint32_t RESERVED12[3]; + __IOM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/W) PMU Device Type Register */ + __IOM uint32_t PIDR4; /*!< Offset: 0xFD0 (R/W) PMU Peripheral Identification Register 4 */ + uint32_t RESERVED13[3]; + __IOM uint32_t PIDR0; /*!< Offset: 0xFE0 (R/W) PMU Peripheral Identification Register 0 */ + __IOM uint32_t PIDR1; /*!< Offset: 0xFE4 (R/W) PMU Peripheral Identification Register 1 */ + __IOM uint32_t PIDR2; /*!< Offset: 0xFE8 (R/W) PMU Peripheral Identification Register 2 */ + __IOM uint32_t PIDR3; /*!< Offset: 0xFEC (R/W) PMU Peripheral Identification Register 3 */ + __IOM uint32_t CIDR0; /*!< Offset: 0xFF0 (R/W) PMU Component Identification Register 0 */ + __IOM uint32_t CIDR1; /*!< Offset: 0xFF4 (R/W) PMU Component Identification Register 1 */ + __IOM uint32_t CIDR2; /*!< Offset: 0xFF8 (R/W) PMU Component Identification Register 2 */ + __IOM uint32_t CIDR3; /*!< Offset: 0xFFC (R/W) PMU Component Identification Register 3 */ +} PMU_Type; + +/** \brief PMU Event Counter Registers (0-30) Definitions */ + +#define PMU_EVCNTR_CNT_Pos 0U /*!< PMU EVCNTR: Counter Position */ +#define PMU_EVCNTR_CNT_Msk (0xFFFFUL /*<< PMU_EVCNTRx_CNT_Pos*/) /*!< PMU EVCNTR: Counter Mask */ + +/** \brief PMU Event Type and Filter Registers (0-30) Definitions */ + +#define PMU_EVTYPER_EVENTTOCNT_Pos 0U /*!< PMU EVTYPER: Event to Count Position */ +#define PMU_EVTYPER_EVENTTOCNT_Msk (0xFFFFUL /*<< EVTYPERx_EVENTTOCNT_Pos*/) /*!< PMU EVTYPER: Event to Count Mask */ + +/** \brief PMU Count Enable Set Register Definitions */ + +#define PMU_CNTENSET_CNT0_ENABLE_Pos 0U /*!< PMU CNTENSET: Event Counter 0 Enable Set Position */ +#define PMU_CNTENSET_CNT0_ENABLE_Msk (1UL /*<< PMU_CNTENSET_CNT0_ENABLE_Pos*/) /*!< PMU CNTENSET: Event Counter 0 Enable Set Mask */ + +#define PMU_CNTENSET_CNT1_ENABLE_Pos 1U /*!< PMU CNTENSET: Event Counter 1 Enable Set Position */ +#define PMU_CNTENSET_CNT1_ENABLE_Msk (1UL << PMU_CNTENSET_CNT1_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 1 Enable Set Mask */ + +#define PMU_CNTENSET_CNT2_ENABLE_Pos 2U /*!< PMU CNTENSET: Event Counter 2 Enable Set Position */ +#define PMU_CNTENSET_CNT2_ENABLE_Msk (1UL << PMU_CNTENSET_CNT2_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 2 Enable Set Mask */ + +#define PMU_CNTENSET_CNT3_ENABLE_Pos 3U /*!< PMU CNTENSET: Event Counter 3 Enable Set Position */ +#define PMU_CNTENSET_CNT3_ENABLE_Msk (1UL << PMU_CNTENSET_CNT3_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 3 Enable Set Mask */ + +#define PMU_CNTENSET_CNT4_ENABLE_Pos 4U /*!< PMU CNTENSET: Event Counter 4 Enable Set Position */ +#define PMU_CNTENSET_CNT4_ENABLE_Msk (1UL << PMU_CNTENSET_CNT4_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 4 Enable Set Mask */ + +#define PMU_CNTENSET_CNT5_ENABLE_Pos 5U /*!< PMU CNTENSET: Event Counter 5 Enable Set Position */ +#define PMU_CNTENSET_CNT5_ENABLE_Msk (1UL << PMU_CNTENSET_CNT5_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 5 Enable Set Mask */ + +#define PMU_CNTENSET_CNT6_ENABLE_Pos 6U /*!< PMU CNTENSET: Event Counter 6 Enable Set Position */ +#define PMU_CNTENSET_CNT6_ENABLE_Msk (1UL << PMU_CNTENSET_CNT6_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 6 Enable Set Mask */ + +#define PMU_CNTENSET_CNT7_ENABLE_Pos 7U /*!< PMU CNTENSET: Event Counter 7 Enable Set Position */ +#define PMU_CNTENSET_CNT7_ENABLE_Msk (1UL << PMU_CNTENSET_CNT7_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 7 Enable Set Mask */ + +#define PMU_CNTENSET_CNT8_ENABLE_Pos 8U /*!< PMU CNTENSET: Event Counter 8 Enable Set Position */ +#define PMU_CNTENSET_CNT8_ENABLE_Msk (1UL << PMU_CNTENSET_CNT8_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 8 Enable Set Mask */ + +#define PMU_CNTENSET_CNT9_ENABLE_Pos 9U /*!< PMU CNTENSET: Event Counter 9 Enable Set Position */ +#define PMU_CNTENSET_CNT9_ENABLE_Msk (1UL << PMU_CNTENSET_CNT9_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 9 Enable Set Mask */ + +#define PMU_CNTENSET_CNT10_ENABLE_Pos 10U /*!< PMU CNTENSET: Event Counter 10 Enable Set Position */ +#define PMU_CNTENSET_CNT10_ENABLE_Msk (1UL << PMU_CNTENSET_CNT10_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 10 Enable Set Mask */ + +#define PMU_CNTENSET_CNT11_ENABLE_Pos 11U /*!< PMU CNTENSET: Event Counter 11 Enable Set Position */ +#define PMU_CNTENSET_CNT11_ENABLE_Msk (1UL << PMU_CNTENSET_CNT11_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 11 Enable Set Mask */ + +#define PMU_CNTENSET_CNT12_ENABLE_Pos 12U /*!< PMU CNTENSET: Event Counter 12 Enable Set Position */ +#define PMU_CNTENSET_CNT12_ENABLE_Msk (1UL << PMU_CNTENSET_CNT12_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 12 Enable Set Mask */ + +#define PMU_CNTENSET_CNT13_ENABLE_Pos 13U /*!< PMU CNTENSET: Event Counter 13 Enable Set Position */ +#define PMU_CNTENSET_CNT13_ENABLE_Msk (1UL << PMU_CNTENSET_CNT13_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 13 Enable Set Mask */ + +#define PMU_CNTENSET_CNT14_ENABLE_Pos 14U /*!< PMU CNTENSET: Event Counter 14 Enable Set Position */ +#define PMU_CNTENSET_CNT14_ENABLE_Msk (1UL << PMU_CNTENSET_CNT14_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 14 Enable Set Mask */ + +#define PMU_CNTENSET_CNT15_ENABLE_Pos 15U /*!< PMU CNTENSET: Event Counter 15 Enable Set Position */ +#define PMU_CNTENSET_CNT15_ENABLE_Msk (1UL << PMU_CNTENSET_CNT15_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 15 Enable Set Mask */ + +#define PMU_CNTENSET_CNT16_ENABLE_Pos 16U /*!< PMU CNTENSET: Event Counter 16 Enable Set Position */ +#define PMU_CNTENSET_CNT16_ENABLE_Msk (1UL << PMU_CNTENSET_CNT16_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 16 Enable Set Mask */ + +#define PMU_CNTENSET_CNT17_ENABLE_Pos 17U /*!< PMU CNTENSET: Event Counter 17 Enable Set Position */ +#define PMU_CNTENSET_CNT17_ENABLE_Msk (1UL << PMU_CNTENSET_CNT17_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 17 Enable Set Mask */ + +#define PMU_CNTENSET_CNT18_ENABLE_Pos 18U /*!< PMU CNTENSET: Event Counter 18 Enable Set Position */ +#define PMU_CNTENSET_CNT18_ENABLE_Msk (1UL << PMU_CNTENSET_CNT18_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 18 Enable Set Mask */ + +#define PMU_CNTENSET_CNT19_ENABLE_Pos 19U /*!< PMU CNTENSET: Event Counter 19 Enable Set Position */ +#define PMU_CNTENSET_CNT19_ENABLE_Msk (1UL << PMU_CNTENSET_CNT19_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 19 Enable Set Mask */ + +#define PMU_CNTENSET_CNT20_ENABLE_Pos 20U /*!< PMU CNTENSET: Event Counter 20 Enable Set Position */ +#define PMU_CNTENSET_CNT20_ENABLE_Msk (1UL << PMU_CNTENSET_CNT20_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 20 Enable Set Mask */ + +#define PMU_CNTENSET_CNT21_ENABLE_Pos 21U /*!< PMU CNTENSET: Event Counter 21 Enable Set Position */ +#define PMU_CNTENSET_CNT21_ENABLE_Msk (1UL << PMU_CNTENSET_CNT21_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 21 Enable Set Mask */ + +#define PMU_CNTENSET_CNT22_ENABLE_Pos 22U /*!< PMU CNTENSET: Event Counter 22 Enable Set Position */ +#define PMU_CNTENSET_CNT22_ENABLE_Msk (1UL << PMU_CNTENSET_CNT22_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 22 Enable Set Mask */ + +#define PMU_CNTENSET_CNT23_ENABLE_Pos 23U /*!< PMU CNTENSET: Event Counter 23 Enable Set Position */ +#define PMU_CNTENSET_CNT23_ENABLE_Msk (1UL << PMU_CNTENSET_CNT23_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 23 Enable Set Mask */ + +#define PMU_CNTENSET_CNT24_ENABLE_Pos 24U /*!< PMU CNTENSET: Event Counter 24 Enable Set Position */ +#define PMU_CNTENSET_CNT24_ENABLE_Msk (1UL << PMU_CNTENSET_CNT24_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 24 Enable Set Mask */ + +#define PMU_CNTENSET_CNT25_ENABLE_Pos 25U /*!< PMU CNTENSET: Event Counter 25 Enable Set Position */ +#define PMU_CNTENSET_CNT25_ENABLE_Msk (1UL << PMU_CNTENSET_CNT25_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 25 Enable Set Mask */ + +#define PMU_CNTENSET_CNT26_ENABLE_Pos 26U /*!< PMU CNTENSET: Event Counter 26 Enable Set Position */ +#define PMU_CNTENSET_CNT26_ENABLE_Msk (1UL << PMU_CNTENSET_CNT26_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 26 Enable Set Mask */ + +#define PMU_CNTENSET_CNT27_ENABLE_Pos 27U /*!< PMU CNTENSET: Event Counter 27 Enable Set Position */ +#define PMU_CNTENSET_CNT27_ENABLE_Msk (1UL << PMU_CNTENSET_CNT27_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 27 Enable Set Mask */ + +#define PMU_CNTENSET_CNT28_ENABLE_Pos 28U /*!< PMU CNTENSET: Event Counter 28 Enable Set Position */ +#define PMU_CNTENSET_CNT28_ENABLE_Msk (1UL << PMU_CNTENSET_CNT28_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 28 Enable Set Mask */ + +#define PMU_CNTENSET_CNT29_ENABLE_Pos 29U /*!< PMU CNTENSET: Event Counter 29 Enable Set Position */ +#define PMU_CNTENSET_CNT29_ENABLE_Msk (1UL << PMU_CNTENSET_CNT29_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 29 Enable Set Mask */ + +#define PMU_CNTENSET_CNT30_ENABLE_Pos 30U /*!< PMU CNTENSET: Event Counter 30 Enable Set Position */ +#define PMU_CNTENSET_CNT30_ENABLE_Msk (1UL << PMU_CNTENSET_CNT30_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 30 Enable Set Mask */ + +#define PMU_CNTENSET_CCNTR_ENABLE_Pos 31U /*!< PMU CNTENSET: Cycle Counter Enable Set Position */ +#define PMU_CNTENSET_CCNTR_ENABLE_Msk (1UL << PMU_CNTENSET_CCNTR_ENABLE_Pos) /*!< PMU CNTENSET: Cycle Counter Enable Set Mask */ + +/** \brief PMU Count Enable Clear Register Definitions */ + +#define PMU_CNTENSET_CNT0_ENABLE_Pos 0U /*!< PMU CNTENCLR: Event Counter 0 Enable Clear Position */ +#define PMU_CNTENCLR_CNT0_ENABLE_Msk (1UL /*<< PMU_CNTENCLR_CNT0_ENABLE_Pos*/) /*!< PMU CNTENCLR: Event Counter 0 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT1_ENABLE_Pos 1U /*!< PMU CNTENCLR: Event Counter 1 Enable Clear Position */ +#define PMU_CNTENCLR_CNT1_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT1_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 1 Enable Clear */ + +#define PMU_CNTENCLR_CNT2_ENABLE_Pos 2U /*!< PMU CNTENCLR: Event Counter 2 Enable Clear Position */ +#define PMU_CNTENCLR_CNT2_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT2_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 2 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT3_ENABLE_Pos 3U /*!< PMU CNTENCLR: Event Counter 3 Enable Clear Position */ +#define PMU_CNTENCLR_CNT3_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT3_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 3 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT4_ENABLE_Pos 4U /*!< PMU CNTENCLR: Event Counter 4 Enable Clear Position */ +#define PMU_CNTENCLR_CNT4_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT4_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 4 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT5_ENABLE_Pos 5U /*!< PMU CNTENCLR: Event Counter 5 Enable Clear Position */ +#define PMU_CNTENCLR_CNT5_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT5_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 5 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT6_ENABLE_Pos 6U /*!< PMU CNTENCLR: Event Counter 6 Enable Clear Position */ +#define PMU_CNTENCLR_CNT6_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT6_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 6 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT7_ENABLE_Pos 7U /*!< PMU CNTENCLR: Event Counter 7 Enable Clear Position */ +#define PMU_CNTENCLR_CNT7_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT7_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 7 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT8_ENABLE_Pos 8U /*!< PMU CNTENCLR: Event Counter 8 Enable Clear Position */ +#define PMU_CNTENCLR_CNT8_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT8_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 8 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT9_ENABLE_Pos 9U /*!< PMU CNTENCLR: Event Counter 9 Enable Clear Position */ +#define PMU_CNTENCLR_CNT9_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT9_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 9 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT10_ENABLE_Pos 10U /*!< PMU CNTENCLR: Event Counter 10 Enable Clear Position */ +#define PMU_CNTENCLR_CNT10_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT10_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 10 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT11_ENABLE_Pos 11U /*!< PMU CNTENCLR: Event Counter 11 Enable Clear Position */ +#define PMU_CNTENCLR_CNT11_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT11_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 11 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT12_ENABLE_Pos 12U /*!< PMU CNTENCLR: Event Counter 12 Enable Clear Position */ +#define PMU_CNTENCLR_CNT12_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT12_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 12 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT13_ENABLE_Pos 13U /*!< PMU CNTENCLR: Event Counter 13 Enable Clear Position */ +#define PMU_CNTENCLR_CNT13_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT13_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 13 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT14_ENABLE_Pos 14U /*!< PMU CNTENCLR: Event Counter 14 Enable Clear Position */ +#define PMU_CNTENCLR_CNT14_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT14_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 14 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT15_ENABLE_Pos 15U /*!< PMU CNTENCLR: Event Counter 15 Enable Clear Position */ +#define PMU_CNTENCLR_CNT15_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT15_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 15 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT16_ENABLE_Pos 16U /*!< PMU CNTENCLR: Event Counter 16 Enable Clear Position */ +#define PMU_CNTENCLR_CNT16_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT16_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 16 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT17_ENABLE_Pos 17U /*!< PMU CNTENCLR: Event Counter 17 Enable Clear Position */ +#define PMU_CNTENCLR_CNT17_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT17_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 17 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT18_ENABLE_Pos 18U /*!< PMU CNTENCLR: Event Counter 18 Enable Clear Position */ +#define PMU_CNTENCLR_CNT18_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT18_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 18 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT19_ENABLE_Pos 19U /*!< PMU CNTENCLR: Event Counter 19 Enable Clear Position */ +#define PMU_CNTENCLR_CNT19_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT19_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 19 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT20_ENABLE_Pos 20U /*!< PMU CNTENCLR: Event Counter 20 Enable Clear Position */ +#define PMU_CNTENCLR_CNT20_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT20_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 20 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT21_ENABLE_Pos 21U /*!< PMU CNTENCLR: Event Counter 21 Enable Clear Position */ +#define PMU_CNTENCLR_CNT21_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT21_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 21 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT22_ENABLE_Pos 22U /*!< PMU CNTENCLR: Event Counter 22 Enable Clear Position */ +#define PMU_CNTENCLR_CNT22_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT22_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 22 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT23_ENABLE_Pos 23U /*!< PMU CNTENCLR: Event Counter 23 Enable Clear Position */ +#define PMU_CNTENCLR_CNT23_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT23_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 23 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT24_ENABLE_Pos 24U /*!< PMU CNTENCLR: Event Counter 24 Enable Clear Position */ +#define PMU_CNTENCLR_CNT24_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT24_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 24 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT25_ENABLE_Pos 25U /*!< PMU CNTENCLR: Event Counter 25 Enable Clear Position */ +#define PMU_CNTENCLR_CNT25_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT25_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 25 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT26_ENABLE_Pos 26U /*!< PMU CNTENCLR: Event Counter 26 Enable Clear Position */ +#define PMU_CNTENCLR_CNT26_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT26_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 26 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT27_ENABLE_Pos 27U /*!< PMU CNTENCLR: Event Counter 27 Enable Clear Position */ +#define PMU_CNTENCLR_CNT27_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT27_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 27 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT28_ENABLE_Pos 28U /*!< PMU CNTENCLR: Event Counter 28 Enable Clear Position */ +#define PMU_CNTENCLR_CNT28_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT28_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 28 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT29_ENABLE_Pos 29U /*!< PMU CNTENCLR: Event Counter 29 Enable Clear Position */ +#define PMU_CNTENCLR_CNT29_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT29_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 29 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT30_ENABLE_Pos 30U /*!< PMU CNTENCLR: Event Counter 30 Enable Clear Position */ +#define PMU_CNTENCLR_CNT30_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT30_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 30 Enable Clear Mask */ + +#define PMU_CNTENCLR_CCNTR_ENABLE_Pos 31U /*!< PMU CNTENCLR: Cycle Counter Enable Clear Position */ +#define PMU_CNTENCLR_CCNTR_ENABLE_Msk (1UL << PMU_CNTENCLR_CCNTR_ENABLE_Pos) /*!< PMU CNTENCLR: Cycle Counter Enable Clear Mask */ + +/** \brief PMU Interrupt Enable Set Register Definitions */ + +#define PMU_INTENSET_CNT0_ENABLE_Pos 0U /*!< PMU INTENSET: Event Counter 0 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT0_ENABLE_Msk (1UL /*<< PMU_INTENSET_CNT0_ENABLE_Pos*/) /*!< PMU INTENSET: Event Counter 0 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT1_ENABLE_Pos 1U /*!< PMU INTENSET: Event Counter 1 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT1_ENABLE_Msk (1UL << PMU_INTENSET_CNT1_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 1 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT2_ENABLE_Pos 2U /*!< PMU INTENSET: Event Counter 2 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT2_ENABLE_Msk (1UL << PMU_INTENSET_CNT2_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 2 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT3_ENABLE_Pos 3U /*!< PMU INTENSET: Event Counter 3 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT3_ENABLE_Msk (1UL << PMU_INTENSET_CNT3_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 3 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT4_ENABLE_Pos 4U /*!< PMU INTENSET: Event Counter 4 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT4_ENABLE_Msk (1UL << PMU_INTENSET_CNT4_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 4 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT5_ENABLE_Pos 5U /*!< PMU INTENSET: Event Counter 5 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT5_ENABLE_Msk (1UL << PMU_INTENSET_CNT5_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 5 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT6_ENABLE_Pos 6U /*!< PMU INTENSET: Event Counter 6 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT6_ENABLE_Msk (1UL << PMU_INTENSET_CNT6_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 6 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT7_ENABLE_Pos 7U /*!< PMU INTENSET: Event Counter 7 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT7_ENABLE_Msk (1UL << PMU_INTENSET_CNT7_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 7 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT8_ENABLE_Pos 8U /*!< PMU INTENSET: Event Counter 8 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT8_ENABLE_Msk (1UL << PMU_INTENSET_CNT8_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 8 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT9_ENABLE_Pos 9U /*!< PMU INTENSET: Event Counter 9 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT9_ENABLE_Msk (1UL << PMU_INTENSET_CNT9_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 9 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT10_ENABLE_Pos 10U /*!< PMU INTENSET: Event Counter 10 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT10_ENABLE_Msk (1UL << PMU_INTENSET_CNT10_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 10 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT11_ENABLE_Pos 11U /*!< PMU INTENSET: Event Counter 11 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT11_ENABLE_Msk (1UL << PMU_INTENSET_CNT11_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 11 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT12_ENABLE_Pos 12U /*!< PMU INTENSET: Event Counter 12 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT12_ENABLE_Msk (1UL << PMU_INTENSET_CNT12_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 12 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT13_ENABLE_Pos 13U /*!< PMU INTENSET: Event Counter 13 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT13_ENABLE_Msk (1UL << PMU_INTENSET_CNT13_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 13 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT14_ENABLE_Pos 14U /*!< PMU INTENSET: Event Counter 14 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT14_ENABLE_Msk (1UL << PMU_INTENSET_CNT14_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 14 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT15_ENABLE_Pos 15U /*!< PMU INTENSET: Event Counter 15 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT15_ENABLE_Msk (1UL << PMU_INTENSET_CNT15_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 15 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT16_ENABLE_Pos 16U /*!< PMU INTENSET: Event Counter 16 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT16_ENABLE_Msk (1UL << PMU_INTENSET_CNT16_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 16 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT17_ENABLE_Pos 17U /*!< PMU INTENSET: Event Counter 17 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT17_ENABLE_Msk (1UL << PMU_INTENSET_CNT17_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 17 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT18_ENABLE_Pos 18U /*!< PMU INTENSET: Event Counter 18 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT18_ENABLE_Msk (1UL << PMU_INTENSET_CNT18_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 18 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT19_ENABLE_Pos 19U /*!< PMU INTENSET: Event Counter 19 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT19_ENABLE_Msk (1UL << PMU_INTENSET_CNT19_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 19 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT20_ENABLE_Pos 20U /*!< PMU INTENSET: Event Counter 20 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT20_ENABLE_Msk (1UL << PMU_INTENSET_CNT20_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 20 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT21_ENABLE_Pos 21U /*!< PMU INTENSET: Event Counter 21 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT21_ENABLE_Msk (1UL << PMU_INTENSET_CNT21_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 21 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT22_ENABLE_Pos 22U /*!< PMU INTENSET: Event Counter 22 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT22_ENABLE_Msk (1UL << PMU_INTENSET_CNT22_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 22 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT23_ENABLE_Pos 23U /*!< PMU INTENSET: Event Counter 23 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT23_ENABLE_Msk (1UL << PMU_INTENSET_CNT23_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 23 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT24_ENABLE_Pos 24U /*!< PMU INTENSET: Event Counter 24 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT24_ENABLE_Msk (1UL << PMU_INTENSET_CNT24_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 24 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT25_ENABLE_Pos 25U /*!< PMU INTENSET: Event Counter 25 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT25_ENABLE_Msk (1UL << PMU_INTENSET_CNT25_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 25 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT26_ENABLE_Pos 26U /*!< PMU INTENSET: Event Counter 26 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT26_ENABLE_Msk (1UL << PMU_INTENSET_CNT26_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 26 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT27_ENABLE_Pos 27U /*!< PMU INTENSET: Event Counter 27 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT27_ENABLE_Msk (1UL << PMU_INTENSET_CNT27_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 27 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT28_ENABLE_Pos 28U /*!< PMU INTENSET: Event Counter 28 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT28_ENABLE_Msk (1UL << PMU_INTENSET_CNT28_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 28 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT29_ENABLE_Pos 29U /*!< PMU INTENSET: Event Counter 29 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT29_ENABLE_Msk (1UL << PMU_INTENSET_CNT29_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 29 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT30_ENABLE_Pos 30U /*!< PMU INTENSET: Event Counter 30 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT30_ENABLE_Msk (1UL << PMU_INTENSET_CNT30_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 30 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CYCCNT_ENABLE_Pos 31U /*!< PMU INTENSET: Cycle Counter Interrupt Enable Set Position */ +#define PMU_INTENSET_CCYCNT_ENABLE_Msk (1UL << PMU_INTENSET_CYCCNT_ENABLE_Pos) /*!< PMU INTENSET: Cycle Counter Interrupt Enable Set Mask */ + +/** \brief PMU Interrupt Enable Clear Register Definitions */ + +#define PMU_INTENSET_CNT0_ENABLE_Pos 0U /*!< PMU INTENCLR: Event Counter 0 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT0_ENABLE_Msk (1UL /*<< PMU_INTENCLR_CNT0_ENABLE_Pos*/) /*!< PMU INTENCLR: Event Counter 0 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT1_ENABLE_Pos 1U /*!< PMU INTENCLR: Event Counter 1 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT1_ENABLE_Msk (1UL << PMU_INTENCLR_CNT1_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 1 Interrupt Enable Clear */ + +#define PMU_INTENCLR_CNT2_ENABLE_Pos 2U /*!< PMU INTENCLR: Event Counter 2 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT2_ENABLE_Msk (1UL << PMU_INTENCLR_CNT2_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 2 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT3_ENABLE_Pos 3U /*!< PMU INTENCLR: Event Counter 3 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT3_ENABLE_Msk (1UL << PMU_INTENCLR_CNT3_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 3 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT4_ENABLE_Pos 4U /*!< PMU INTENCLR: Event Counter 4 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT4_ENABLE_Msk (1UL << PMU_INTENCLR_CNT4_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 4 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT5_ENABLE_Pos 5U /*!< PMU INTENCLR: Event Counter 5 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT5_ENABLE_Msk (1UL << PMU_INTENCLR_CNT5_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 5 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT6_ENABLE_Pos 6U /*!< PMU INTENCLR: Event Counter 6 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT6_ENABLE_Msk (1UL << PMU_INTENCLR_CNT6_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 6 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT7_ENABLE_Pos 7U /*!< PMU INTENCLR: Event Counter 7 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT7_ENABLE_Msk (1UL << PMU_INTENCLR_CNT7_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 7 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT8_ENABLE_Pos 8U /*!< PMU INTENCLR: Event Counter 8 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT8_ENABLE_Msk (1UL << PMU_INTENCLR_CNT8_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 8 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT9_ENABLE_Pos 9U /*!< PMU INTENCLR: Event Counter 9 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT9_ENABLE_Msk (1UL << PMU_INTENCLR_CNT9_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 9 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT10_ENABLE_Pos 10U /*!< PMU INTENCLR: Event Counter 10 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT10_ENABLE_Msk (1UL << PMU_INTENCLR_CNT10_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 10 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT11_ENABLE_Pos 11U /*!< PMU INTENCLR: Event Counter 11 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT11_ENABLE_Msk (1UL << PMU_INTENCLR_CNT11_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 11 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT12_ENABLE_Pos 12U /*!< PMU INTENCLR: Event Counter 12 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT12_ENABLE_Msk (1UL << PMU_INTENCLR_CNT12_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 12 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT13_ENABLE_Pos 13U /*!< PMU INTENCLR: Event Counter 13 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT13_ENABLE_Msk (1UL << PMU_INTENCLR_CNT13_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 13 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT14_ENABLE_Pos 14U /*!< PMU INTENCLR: Event Counter 14 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT14_ENABLE_Msk (1UL << PMU_INTENCLR_CNT14_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 14 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT15_ENABLE_Pos 15U /*!< PMU INTENCLR: Event Counter 15 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT15_ENABLE_Msk (1UL << PMU_INTENCLR_CNT15_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 15 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT16_ENABLE_Pos 16U /*!< PMU INTENCLR: Event Counter 16 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT16_ENABLE_Msk (1UL << PMU_INTENCLR_CNT16_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 16 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT17_ENABLE_Pos 17U /*!< PMU INTENCLR: Event Counter 17 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT17_ENABLE_Msk (1UL << PMU_INTENCLR_CNT17_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 17 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT18_ENABLE_Pos 18U /*!< PMU INTENCLR: Event Counter 18 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT18_ENABLE_Msk (1UL << PMU_INTENCLR_CNT18_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 18 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT19_ENABLE_Pos 19U /*!< PMU INTENCLR: Event Counter 19 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT19_ENABLE_Msk (1UL << PMU_INTENCLR_CNT19_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 19 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT20_ENABLE_Pos 20U /*!< PMU INTENCLR: Event Counter 20 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT20_ENABLE_Msk (1UL << PMU_INTENCLR_CNT20_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 20 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT21_ENABLE_Pos 21U /*!< PMU INTENCLR: Event Counter 21 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT21_ENABLE_Msk (1UL << PMU_INTENCLR_CNT21_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 21 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT22_ENABLE_Pos 22U /*!< PMU INTENCLR: Event Counter 22 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT22_ENABLE_Msk (1UL << PMU_INTENCLR_CNT22_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 22 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT23_ENABLE_Pos 23U /*!< PMU INTENCLR: Event Counter 23 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT23_ENABLE_Msk (1UL << PMU_INTENCLR_CNT23_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 23 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT24_ENABLE_Pos 24U /*!< PMU INTENCLR: Event Counter 24 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT24_ENABLE_Msk (1UL << PMU_INTENCLR_CNT24_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 24 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT25_ENABLE_Pos 25U /*!< PMU INTENCLR: Event Counter 25 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT25_ENABLE_Msk (1UL << PMU_INTENCLR_CNT25_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 25 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT26_ENABLE_Pos 26U /*!< PMU INTENCLR: Event Counter 26 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT26_ENABLE_Msk (1UL << PMU_INTENCLR_CNT26_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 26 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT27_ENABLE_Pos 27U /*!< PMU INTENCLR: Event Counter 27 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT27_ENABLE_Msk (1UL << PMU_INTENCLR_CNT27_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 27 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT28_ENABLE_Pos 28U /*!< PMU INTENCLR: Event Counter 28 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT28_ENABLE_Msk (1UL << PMU_INTENCLR_CNT28_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 28 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT29_ENABLE_Pos 29U /*!< PMU INTENCLR: Event Counter 29 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT29_ENABLE_Msk (1UL << PMU_INTENCLR_CNT29_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 29 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT30_ENABLE_Pos 30U /*!< PMU INTENCLR: Event Counter 30 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT30_ENABLE_Msk (1UL << PMU_INTENCLR_CNT30_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 30 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CYCCNT_ENABLE_Pos 31U /*!< PMU INTENCLR: Cycle Counter Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CYCCNT_ENABLE_Msk (1UL << PMU_INTENCLR_CYCCNT_ENABLE_Pos) /*!< PMU INTENCLR: Cycle Counter Interrupt Enable Clear Mask */ + +/** \brief PMU Overflow Flag Status Set Register Definitions */ + +#define PMU_OVSSET_CNT0_STATUS_Pos 0U /*!< PMU OVSSET: Event Counter 0 Overflow Set Position */ +#define PMU_OVSSET_CNT0_STATUS_Msk (1UL /*<< PMU_OVSSET_CNT0_STATUS_Pos*/) /*!< PMU OVSSET: Event Counter 0 Overflow Set Mask */ + +#define PMU_OVSSET_CNT1_STATUS_Pos 1U /*!< PMU OVSSET: Event Counter 1 Overflow Set Position */ +#define PMU_OVSSET_CNT1_STATUS_Msk (1UL << PMU_OVSSET_CNT1_STATUS_Pos) /*!< PMU OVSSET: Event Counter 1 Overflow Set Mask */ + +#define PMU_OVSSET_CNT2_STATUS_Pos 2U /*!< PMU OVSSET: Event Counter 2 Overflow Set Position */ +#define PMU_OVSSET_CNT2_STATUS_Msk (1UL << PMU_OVSSET_CNT2_STATUS_Pos) /*!< PMU OVSSET: Event Counter 2 Overflow Set Mask */ + +#define PMU_OVSSET_CNT3_STATUS_Pos 3U /*!< PMU OVSSET: Event Counter 3 Overflow Set Position */ +#define PMU_OVSSET_CNT3_STATUS_Msk (1UL << PMU_OVSSET_CNT3_STATUS_Pos) /*!< PMU OVSSET: Event Counter 3 Overflow Set Mask */ + +#define PMU_OVSSET_CNT4_STATUS_Pos 4U /*!< PMU OVSSET: Event Counter 4 Overflow Set Position */ +#define PMU_OVSSET_CNT4_STATUS_Msk (1UL << PMU_OVSSET_CNT4_STATUS_Pos) /*!< PMU OVSSET: Event Counter 4 Overflow Set Mask */ + +#define PMU_OVSSET_CNT5_STATUS_Pos 5U /*!< PMU OVSSET: Event Counter 5 Overflow Set Position */ +#define PMU_OVSSET_CNT5_STATUS_Msk (1UL << PMU_OVSSET_CNT5_STATUS_Pos) /*!< PMU OVSSET: Event Counter 5 Overflow Set Mask */ + +#define PMU_OVSSET_CNT6_STATUS_Pos 6U /*!< PMU OVSSET: Event Counter 6 Overflow Set Position */ +#define PMU_OVSSET_CNT6_STATUS_Msk (1UL << PMU_OVSSET_CNT6_STATUS_Pos) /*!< PMU OVSSET: Event Counter 6 Overflow Set Mask */ + +#define PMU_OVSSET_CNT7_STATUS_Pos 7U /*!< PMU OVSSET: Event Counter 7 Overflow Set Position */ +#define PMU_OVSSET_CNT7_STATUS_Msk (1UL << PMU_OVSSET_CNT7_STATUS_Pos) /*!< PMU OVSSET: Event Counter 7 Overflow Set Mask */ + +#define PMU_OVSSET_CNT8_STATUS_Pos 8U /*!< PMU OVSSET: Event Counter 8 Overflow Set Position */ +#define PMU_OVSSET_CNT8_STATUS_Msk (1UL << PMU_OVSSET_CNT8_STATUS_Pos) /*!< PMU OVSSET: Event Counter 8 Overflow Set Mask */ + +#define PMU_OVSSET_CNT9_STATUS_Pos 9U /*!< PMU OVSSET: Event Counter 9 Overflow Set Position */ +#define PMU_OVSSET_CNT9_STATUS_Msk (1UL << PMU_OVSSET_CNT9_STATUS_Pos) /*!< PMU OVSSET: Event Counter 9 Overflow Set Mask */ + +#define PMU_OVSSET_CNT10_STATUS_Pos 10U /*!< PMU OVSSET: Event Counter 10 Overflow Set Position */ +#define PMU_OVSSET_CNT10_STATUS_Msk (1UL << PMU_OVSSET_CNT10_STATUS_Pos) /*!< PMU OVSSET: Event Counter 10 Overflow Set Mask */ + +#define PMU_OVSSET_CNT11_STATUS_Pos 11U /*!< PMU OVSSET: Event Counter 11 Overflow Set Position */ +#define PMU_OVSSET_CNT11_STATUS_Msk (1UL << PMU_OVSSET_CNT11_STATUS_Pos) /*!< PMU OVSSET: Event Counter 11 Overflow Set Mask */ + +#define PMU_OVSSET_CNT12_STATUS_Pos 12U /*!< PMU OVSSET: Event Counter 12 Overflow Set Position */ +#define PMU_OVSSET_CNT12_STATUS_Msk (1UL << PMU_OVSSET_CNT12_STATUS_Pos) /*!< PMU OVSSET: Event Counter 12 Overflow Set Mask */ + +#define PMU_OVSSET_CNT13_STATUS_Pos 13U /*!< PMU OVSSET: Event Counter 13 Overflow Set Position */ +#define PMU_OVSSET_CNT13_STATUS_Msk (1UL << PMU_OVSSET_CNT13_STATUS_Pos) /*!< PMU OVSSET: Event Counter 13 Overflow Set Mask */ + +#define PMU_OVSSET_CNT14_STATUS_Pos 14U /*!< PMU OVSSET: Event Counter 14 Overflow Set Position */ +#define PMU_OVSSET_CNT14_STATUS_Msk (1UL << PMU_OVSSET_CNT14_STATUS_Pos) /*!< PMU OVSSET: Event Counter 14 Overflow Set Mask */ + +#define PMU_OVSSET_CNT15_STATUS_Pos 15U /*!< PMU OVSSET: Event Counter 15 Overflow Set Position */ +#define PMU_OVSSET_CNT15_STATUS_Msk (1UL << PMU_OVSSET_CNT15_STATUS_Pos) /*!< PMU OVSSET: Event Counter 15 Overflow Set Mask */ + +#define PMU_OVSSET_CNT16_STATUS_Pos 16U /*!< PMU OVSSET: Event Counter 16 Overflow Set Position */ +#define PMU_OVSSET_CNT16_STATUS_Msk (1UL << PMU_OVSSET_CNT16_STATUS_Pos) /*!< PMU OVSSET: Event Counter 16 Overflow Set Mask */ + +#define PMU_OVSSET_CNT17_STATUS_Pos 17U /*!< PMU OVSSET: Event Counter 17 Overflow Set Position */ +#define PMU_OVSSET_CNT17_STATUS_Msk (1UL << PMU_OVSSET_CNT17_STATUS_Pos) /*!< PMU OVSSET: Event Counter 17 Overflow Set Mask */ + +#define PMU_OVSSET_CNT18_STATUS_Pos 18U /*!< PMU OVSSET: Event Counter 18 Overflow Set Position */ +#define PMU_OVSSET_CNT18_STATUS_Msk (1UL << PMU_OVSSET_CNT18_STATUS_Pos) /*!< PMU OVSSET: Event Counter 18 Overflow Set Mask */ + +#define PMU_OVSSET_CNT19_STATUS_Pos 19U /*!< PMU OVSSET: Event Counter 19 Overflow Set Position */ +#define PMU_OVSSET_CNT19_STATUS_Msk (1UL << PMU_OVSSET_CNT19_STATUS_Pos) /*!< PMU OVSSET: Event Counter 19 Overflow Set Mask */ + +#define PMU_OVSSET_CNT20_STATUS_Pos 20U /*!< PMU OVSSET: Event Counter 20 Overflow Set Position */ +#define PMU_OVSSET_CNT20_STATUS_Msk (1UL << PMU_OVSSET_CNT20_STATUS_Pos) /*!< PMU OVSSET: Event Counter 20 Overflow Set Mask */ + +#define PMU_OVSSET_CNT21_STATUS_Pos 21U /*!< PMU OVSSET: Event Counter 21 Overflow Set Position */ +#define PMU_OVSSET_CNT21_STATUS_Msk (1UL << PMU_OVSSET_CNT21_STATUS_Pos) /*!< PMU OVSSET: Event Counter 21 Overflow Set Mask */ + +#define PMU_OVSSET_CNT22_STATUS_Pos 22U /*!< PMU OVSSET: Event Counter 22 Overflow Set Position */ +#define PMU_OVSSET_CNT22_STATUS_Msk (1UL << PMU_OVSSET_CNT22_STATUS_Pos) /*!< PMU OVSSET: Event Counter 22 Overflow Set Mask */ + +#define PMU_OVSSET_CNT23_STATUS_Pos 23U /*!< PMU OVSSET: Event Counter 23 Overflow Set Position */ +#define PMU_OVSSET_CNT23_STATUS_Msk (1UL << PMU_OVSSET_CNT23_STATUS_Pos) /*!< PMU OVSSET: Event Counter 23 Overflow Set Mask */ + +#define PMU_OVSSET_CNT24_STATUS_Pos 24U /*!< PMU OVSSET: Event Counter 24 Overflow Set Position */ +#define PMU_OVSSET_CNT24_STATUS_Msk (1UL << PMU_OVSSET_CNT24_STATUS_Pos) /*!< PMU OVSSET: Event Counter 24 Overflow Set Mask */ + +#define PMU_OVSSET_CNT25_STATUS_Pos 25U /*!< PMU OVSSET: Event Counter 25 Overflow Set Position */ +#define PMU_OVSSET_CNT25_STATUS_Msk (1UL << PMU_OVSSET_CNT25_STATUS_Pos) /*!< PMU OVSSET: Event Counter 25 Overflow Set Mask */ + +#define PMU_OVSSET_CNT26_STATUS_Pos 26U /*!< PMU OVSSET: Event Counter 26 Overflow Set Position */ +#define PMU_OVSSET_CNT26_STATUS_Msk (1UL << PMU_OVSSET_CNT26_STATUS_Pos) /*!< PMU OVSSET: Event Counter 26 Overflow Set Mask */ + +#define PMU_OVSSET_CNT27_STATUS_Pos 27U /*!< PMU OVSSET: Event Counter 27 Overflow Set Position */ +#define PMU_OVSSET_CNT27_STATUS_Msk (1UL << PMU_OVSSET_CNT27_STATUS_Pos) /*!< PMU OVSSET: Event Counter 27 Overflow Set Mask */ + +#define PMU_OVSSET_CNT28_STATUS_Pos 28U /*!< PMU OVSSET: Event Counter 28 Overflow Set Position */ +#define PMU_OVSSET_CNT28_STATUS_Msk (1UL << PMU_OVSSET_CNT28_STATUS_Pos) /*!< PMU OVSSET: Event Counter 28 Overflow Set Mask */ + +#define PMU_OVSSET_CNT29_STATUS_Pos 29U /*!< PMU OVSSET: Event Counter 29 Overflow Set Position */ +#define PMU_OVSSET_CNT29_STATUS_Msk (1UL << PMU_OVSSET_CNT29_STATUS_Pos) /*!< PMU OVSSET: Event Counter 29 Overflow Set Mask */ + +#define PMU_OVSSET_CNT30_STATUS_Pos 30U /*!< PMU OVSSET: Event Counter 30 Overflow Set Position */ +#define PMU_OVSSET_CNT30_STATUS_Msk (1UL << PMU_OVSSET_CNT30_STATUS_Pos) /*!< PMU OVSSET: Event Counter 30 Overflow Set Mask */ + +#define PMU_OVSSET_CYCCNT_STATUS_Pos 31U /*!< PMU OVSSET: Cycle Counter Overflow Set Position */ +#define PMU_OVSSET_CYCCNT_STATUS_Msk (1UL << PMU_OVSSET_CYCCNT_STATUS_Pos) /*!< PMU OVSSET: Cycle Counter Overflow Set Mask */ + +/** \brief PMU Overflow Flag Status Clear Register Definitions */ + +#define PMU_OVSCLR_CNT0_STATUS_Pos 0U /*!< PMU OVSCLR: Event Counter 0 Overflow Clear Position */ +#define PMU_OVSCLR_CNT0_STATUS_Msk (1UL /*<< PMU_OVSCLR_CNT0_STATUS_Pos*/) /*!< PMU OVSCLR: Event Counter 0 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT1_STATUS_Pos 1U /*!< PMU OVSCLR: Event Counter 1 Overflow Clear Position */ +#define PMU_OVSCLR_CNT1_STATUS_Msk (1UL << PMU_OVSCLR_CNT1_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 1 Overflow Clear */ + +#define PMU_OVSCLR_CNT2_STATUS_Pos 2U /*!< PMU OVSCLR: Event Counter 2 Overflow Clear Position */ +#define PMU_OVSCLR_CNT2_STATUS_Msk (1UL << PMU_OVSCLR_CNT2_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 2 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT3_STATUS_Pos 3U /*!< PMU OVSCLR: Event Counter 3 Overflow Clear Position */ +#define PMU_OVSCLR_CNT3_STATUS_Msk (1UL << PMU_OVSCLR_CNT3_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 3 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT4_STATUS_Pos 4U /*!< PMU OVSCLR: Event Counter 4 Overflow Clear Position */ +#define PMU_OVSCLR_CNT4_STATUS_Msk (1UL << PMU_OVSCLR_CNT4_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 4 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT5_STATUS_Pos 5U /*!< PMU OVSCLR: Event Counter 5 Overflow Clear Position */ +#define PMU_OVSCLR_CNT5_STATUS_Msk (1UL << PMU_OVSCLR_CNT5_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 5 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT6_STATUS_Pos 6U /*!< PMU OVSCLR: Event Counter 6 Overflow Clear Position */ +#define PMU_OVSCLR_CNT6_STATUS_Msk (1UL << PMU_OVSCLR_CNT6_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 6 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT7_STATUS_Pos 7U /*!< PMU OVSCLR: Event Counter 7 Overflow Clear Position */ +#define PMU_OVSCLR_CNT7_STATUS_Msk (1UL << PMU_OVSCLR_CNT7_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 7 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT8_STATUS_Pos 8U /*!< PMU OVSCLR: Event Counter 8 Overflow Clear Position */ +#define PMU_OVSCLR_CNT8_STATUS_Msk (1UL << PMU_OVSCLR_CNT8_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 8 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT9_STATUS_Pos 9U /*!< PMU OVSCLR: Event Counter 9 Overflow Clear Position */ +#define PMU_OVSCLR_CNT9_STATUS_Msk (1UL << PMU_OVSCLR_CNT9_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 9 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT10_STATUS_Pos 10U /*!< PMU OVSCLR: Event Counter 10 Overflow Clear Position */ +#define PMU_OVSCLR_CNT10_STATUS_Msk (1UL << PMU_OVSCLR_CNT10_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 10 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT11_STATUS_Pos 11U /*!< PMU OVSCLR: Event Counter 11 Overflow Clear Position */ +#define PMU_OVSCLR_CNT11_STATUS_Msk (1UL << PMU_OVSCLR_CNT11_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 11 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT12_STATUS_Pos 12U /*!< PMU OVSCLR: Event Counter 12 Overflow Clear Position */ +#define PMU_OVSCLR_CNT12_STATUS_Msk (1UL << PMU_OVSCLR_CNT12_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 12 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT13_STATUS_Pos 13U /*!< PMU OVSCLR: Event Counter 13 Overflow Clear Position */ +#define PMU_OVSCLR_CNT13_STATUS_Msk (1UL << PMU_OVSCLR_CNT13_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 13 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT14_STATUS_Pos 14U /*!< PMU OVSCLR: Event Counter 14 Overflow Clear Position */ +#define PMU_OVSCLR_CNT14_STATUS_Msk (1UL << PMU_OVSCLR_CNT14_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 14 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT15_STATUS_Pos 15U /*!< PMU OVSCLR: Event Counter 15 Overflow Clear Position */ +#define PMU_OVSCLR_CNT15_STATUS_Msk (1UL << PMU_OVSCLR_CNT15_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 15 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT16_STATUS_Pos 16U /*!< PMU OVSCLR: Event Counter 16 Overflow Clear Position */ +#define PMU_OVSCLR_CNT16_STATUS_Msk (1UL << PMU_OVSCLR_CNT16_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 16 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT17_STATUS_Pos 17U /*!< PMU OVSCLR: Event Counter 17 Overflow Clear Position */ +#define PMU_OVSCLR_CNT17_STATUS_Msk (1UL << PMU_OVSCLR_CNT17_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 17 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT18_STATUS_Pos 18U /*!< PMU OVSCLR: Event Counter 18 Overflow Clear Position */ +#define PMU_OVSCLR_CNT18_STATUS_Msk (1UL << PMU_OVSCLR_CNT18_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 18 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT19_STATUS_Pos 19U /*!< PMU OVSCLR: Event Counter 19 Overflow Clear Position */ +#define PMU_OVSCLR_CNT19_STATUS_Msk (1UL << PMU_OVSCLR_CNT19_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 19 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT20_STATUS_Pos 20U /*!< PMU OVSCLR: Event Counter 20 Overflow Clear Position */ +#define PMU_OVSCLR_CNT20_STATUS_Msk (1UL << PMU_OVSCLR_CNT20_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 20 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT21_STATUS_Pos 21U /*!< PMU OVSCLR: Event Counter 21 Overflow Clear Position */ +#define PMU_OVSCLR_CNT21_STATUS_Msk (1UL << PMU_OVSCLR_CNT21_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 21 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT22_STATUS_Pos 22U /*!< PMU OVSCLR: Event Counter 22 Overflow Clear Position */ +#define PMU_OVSCLR_CNT22_STATUS_Msk (1UL << PMU_OVSCLR_CNT22_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 22 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT23_STATUS_Pos 23U /*!< PMU OVSCLR: Event Counter 23 Overflow Clear Position */ +#define PMU_OVSCLR_CNT23_STATUS_Msk (1UL << PMU_OVSCLR_CNT23_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 23 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT24_STATUS_Pos 24U /*!< PMU OVSCLR: Event Counter 24 Overflow Clear Position */ +#define PMU_OVSCLR_CNT24_STATUS_Msk (1UL << PMU_OVSCLR_CNT24_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 24 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT25_STATUS_Pos 25U /*!< PMU OVSCLR: Event Counter 25 Overflow Clear Position */ +#define PMU_OVSCLR_CNT25_STATUS_Msk (1UL << PMU_OVSCLR_CNT25_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 25 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT26_STATUS_Pos 26U /*!< PMU OVSCLR: Event Counter 26 Overflow Clear Position */ +#define PMU_OVSCLR_CNT26_STATUS_Msk (1UL << PMU_OVSCLR_CNT26_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 26 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT27_STATUS_Pos 27U /*!< PMU OVSCLR: Event Counter 27 Overflow Clear Position */ +#define PMU_OVSCLR_CNT27_STATUS_Msk (1UL << PMU_OVSCLR_CNT27_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 27 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT28_STATUS_Pos 28U /*!< PMU OVSCLR: Event Counter 28 Overflow Clear Position */ +#define PMU_OVSCLR_CNT28_STATUS_Msk (1UL << PMU_OVSCLR_CNT28_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 28 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT29_STATUS_Pos 29U /*!< PMU OVSCLR: Event Counter 29 Overflow Clear Position */ +#define PMU_OVSCLR_CNT29_STATUS_Msk (1UL << PMU_OVSCLR_CNT29_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 29 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT30_STATUS_Pos 30U /*!< PMU OVSCLR: Event Counter 30 Overflow Clear Position */ +#define PMU_OVSCLR_CNT30_STATUS_Msk (1UL << PMU_OVSCLR_CNT30_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 30 Overflow Clear Mask */ + +#define PMU_OVSCLR_CYCCNT_STATUS_Pos 31U /*!< PMU OVSCLR: Cycle Counter Overflow Clear Position */ +#define PMU_OVSCLR_CYCCNT_STATUS_Msk (1UL << PMU_OVSCLR_CYCCNT_STATUS_Pos) /*!< PMU OVSCLR: Cycle Counter Overflow Clear Mask */ + +/** \brief PMU Software Increment Counter */ + +#define PMU_SWINC_CNT0_Pos 0U /*!< PMU SWINC: Event Counter 0 Software Increment Position */ +#define PMU_SWINC_CNT0_Msk (1UL /*<< PMU_SWINC_CNT0_Pos */) /*!< PMU SWINC: Event Counter 0 Software Increment Mask */ + +#define PMU_SWINC_CNT1_Pos 1U /*!< PMU SWINC: Event Counter 1 Software Increment Position */ +#define PMU_SWINC_CNT1_Msk (1UL << PMU_SWINC_CNT1_Pos) /*!< PMU SWINC: Event Counter 1 Software Increment Mask */ + +#define PMU_SWINC_CNT2_Pos 2U /*!< PMU SWINC: Event Counter 2 Software Increment Position */ +#define PMU_SWINC_CNT2_Msk (1UL << PMU_SWINC_CNT2_Pos) /*!< PMU SWINC: Event Counter 2 Software Increment Mask */ + +#define PMU_SWINC_CNT3_Pos 3U /*!< PMU SWINC: Event Counter 3 Software Increment Position */ +#define PMU_SWINC_CNT3_Msk (1UL << PMU_SWINC_CNT3_Pos) /*!< PMU SWINC: Event Counter 3 Software Increment Mask */ + +#define PMU_SWINC_CNT4_Pos 4U /*!< PMU SWINC: Event Counter 4 Software Increment Position */ +#define PMU_SWINC_CNT4_Msk (1UL << PMU_SWINC_CNT4_Pos) /*!< PMU SWINC: Event Counter 4 Software Increment Mask */ + +#define PMU_SWINC_CNT5_Pos 5U /*!< PMU SWINC: Event Counter 5 Software Increment Position */ +#define PMU_SWINC_CNT5_Msk (1UL << PMU_SWINC_CNT5_Pos) /*!< PMU SWINC: Event Counter 5 Software Increment Mask */ + +#define PMU_SWINC_CNT6_Pos 6U /*!< PMU SWINC: Event Counter 6 Software Increment Position */ +#define PMU_SWINC_CNT6_Msk (1UL << PMU_SWINC_CNT6_Pos) /*!< PMU SWINC: Event Counter 6 Software Increment Mask */ + +#define PMU_SWINC_CNT7_Pos 7U /*!< PMU SWINC: Event Counter 7 Software Increment Position */ +#define PMU_SWINC_CNT7_Msk (1UL << PMU_SWINC_CNT7_Pos) /*!< PMU SWINC: Event Counter 7 Software Increment Mask */ + +#define PMU_SWINC_CNT8_Pos 8U /*!< PMU SWINC: Event Counter 8 Software Increment Position */ +#define PMU_SWINC_CNT8_Msk (1UL << PMU_SWINC_CNT8_Pos) /*!< PMU SWINC: Event Counter 8 Software Increment Mask */ + +#define PMU_SWINC_CNT9_Pos 9U /*!< PMU SWINC: Event Counter 9 Software Increment Position */ +#define PMU_SWINC_CNT9_Msk (1UL << PMU_SWINC_CNT9_Pos) /*!< PMU SWINC: Event Counter 9 Software Increment Mask */ + +#define PMU_SWINC_CNT10_Pos 10U /*!< PMU SWINC: Event Counter 10 Software Increment Position */ +#define PMU_SWINC_CNT10_Msk (1UL << PMU_SWINC_CNT10_Pos) /*!< PMU SWINC: Event Counter 10 Software Increment Mask */ + +#define PMU_SWINC_CNT11_Pos 11U /*!< PMU SWINC: Event Counter 11 Software Increment Position */ +#define PMU_SWINC_CNT11_Msk (1UL << PMU_SWINC_CNT11_Pos) /*!< PMU SWINC: Event Counter 11 Software Increment Mask */ + +#define PMU_SWINC_CNT12_Pos 12U /*!< PMU SWINC: Event Counter 12 Software Increment Position */ +#define PMU_SWINC_CNT12_Msk (1UL << PMU_SWINC_CNT12_Pos) /*!< PMU SWINC: Event Counter 12 Software Increment Mask */ + +#define PMU_SWINC_CNT13_Pos 13U /*!< PMU SWINC: Event Counter 13 Software Increment Position */ +#define PMU_SWINC_CNT13_Msk (1UL << PMU_SWINC_CNT13_Pos) /*!< PMU SWINC: Event Counter 13 Software Increment Mask */ + +#define PMU_SWINC_CNT14_Pos 14U /*!< PMU SWINC: Event Counter 14 Software Increment Position */ +#define PMU_SWINC_CNT14_Msk (1UL << PMU_SWINC_CNT14_Pos) /*!< PMU SWINC: Event Counter 14 Software Increment Mask */ + +#define PMU_SWINC_CNT15_Pos 15U /*!< PMU SWINC: Event Counter 15 Software Increment Position */ +#define PMU_SWINC_CNT15_Msk (1UL << PMU_SWINC_CNT15_Pos) /*!< PMU SWINC: Event Counter 15 Software Increment Mask */ + +#define PMU_SWINC_CNT16_Pos 16U /*!< PMU SWINC: Event Counter 16 Software Increment Position */ +#define PMU_SWINC_CNT16_Msk (1UL << PMU_SWINC_CNT16_Pos) /*!< PMU SWINC: Event Counter 16 Software Increment Mask */ + +#define PMU_SWINC_CNT17_Pos 17U /*!< PMU SWINC: Event Counter 17 Software Increment Position */ +#define PMU_SWINC_CNT17_Msk (1UL << PMU_SWINC_CNT17_Pos) /*!< PMU SWINC: Event Counter 17 Software Increment Mask */ + +#define PMU_SWINC_CNT18_Pos 18U /*!< PMU SWINC: Event Counter 18 Software Increment Position */ +#define PMU_SWINC_CNT18_Msk (1UL << PMU_SWINC_CNT18_Pos) /*!< PMU SWINC: Event Counter 18 Software Increment Mask */ + +#define PMU_SWINC_CNT19_Pos 19U /*!< PMU SWINC: Event Counter 19 Software Increment Position */ +#define PMU_SWINC_CNT19_Msk (1UL << PMU_SWINC_CNT19_Pos) /*!< PMU SWINC: Event Counter 19 Software Increment Mask */ + +#define PMU_SWINC_CNT20_Pos 20U /*!< PMU SWINC: Event Counter 20 Software Increment Position */ +#define PMU_SWINC_CNT20_Msk (1UL << PMU_SWINC_CNT20_Pos) /*!< PMU SWINC: Event Counter 20 Software Increment Mask */ + +#define PMU_SWINC_CNT21_Pos 21U /*!< PMU SWINC: Event Counter 21 Software Increment Position */ +#define PMU_SWINC_CNT21_Msk (1UL << PMU_SWINC_CNT21_Pos) /*!< PMU SWINC: Event Counter 21 Software Increment Mask */ + +#define PMU_SWINC_CNT22_Pos 22U /*!< PMU SWINC: Event Counter 22 Software Increment Position */ +#define PMU_SWINC_CNT22_Msk (1UL << PMU_SWINC_CNT22_Pos) /*!< PMU SWINC: Event Counter 22 Software Increment Mask */ + +#define PMU_SWINC_CNT23_Pos 23U /*!< PMU SWINC: Event Counter 23 Software Increment Position */ +#define PMU_SWINC_CNT23_Msk (1UL << PMU_SWINC_CNT23_Pos) /*!< PMU SWINC: Event Counter 23 Software Increment Mask */ + +#define PMU_SWINC_CNT24_Pos 24U /*!< PMU SWINC: Event Counter 24 Software Increment Position */ +#define PMU_SWINC_CNT24_Msk (1UL << PMU_SWINC_CNT24_Pos) /*!< PMU SWINC: Event Counter 24 Software Increment Mask */ + +#define PMU_SWINC_CNT25_Pos 25U /*!< PMU SWINC: Event Counter 25 Software Increment Position */ +#define PMU_SWINC_CNT25_Msk (1UL << PMU_SWINC_CNT25_Pos) /*!< PMU SWINC: Event Counter 25 Software Increment Mask */ + +#define PMU_SWINC_CNT26_Pos 26U /*!< PMU SWINC: Event Counter 26 Software Increment Position */ +#define PMU_SWINC_CNT26_Msk (1UL << PMU_SWINC_CNT26_Pos) /*!< PMU SWINC: Event Counter 26 Software Increment Mask */ + +#define PMU_SWINC_CNT27_Pos 27U /*!< PMU SWINC: Event Counter 27 Software Increment Position */ +#define PMU_SWINC_CNT27_Msk (1UL << PMU_SWINC_CNT27_Pos) /*!< PMU SWINC: Event Counter 27 Software Increment Mask */ + +#define PMU_SWINC_CNT28_Pos 28U /*!< PMU SWINC: Event Counter 28 Software Increment Position */ +#define PMU_SWINC_CNT28_Msk (1UL << PMU_SWINC_CNT28_Pos) /*!< PMU SWINC: Event Counter 28 Software Increment Mask */ + +#define PMU_SWINC_CNT29_Pos 29U /*!< PMU SWINC: Event Counter 29 Software Increment Position */ +#define PMU_SWINC_CNT29_Msk (1UL << PMU_SWINC_CNT29_Pos) /*!< PMU SWINC: Event Counter 29 Software Increment Mask */ + +#define PMU_SWINC_CNT30_Pos 30U /*!< PMU SWINC: Event Counter 30 Software Increment Position */ +#define PMU_SWINC_CNT30_Msk (1UL << PMU_SWINC_CNT30_Pos) /*!< PMU SWINC: Event Counter 30 Software Increment Mask */ + +/** \brief PMU Control Register Definitions */ + +#define PMU_CTRL_ENABLE_Pos 0U /*!< PMU CTRL: ENABLE Position */ +#define PMU_CTRL_ENABLE_Msk (1UL /*<< PMU_CTRL_ENABLE_Pos*/) /*!< PMU CTRL: ENABLE Mask */ + +#define PMU_CTRL_EVENTCNT_RESET_Pos 1U /*!< PMU CTRL: Event Counter Reset Position */ +#define PMU_CTRL_EVENTCNT_RESET_Msk (1UL << PMU_CTRL_EVENTCNT_RESET_Pos) /*!< PMU CTRL: Event Counter Reset Mask */ + +#define PMU_CTRL_CYCCNT_RESET_Pos 2U /*!< PMU CTRL: Cycle Counter Reset Position */ +#define PMU_CTRL_CYCCNT_RESET_Msk (1UL << PMU_CTRL_CYCCNT_RESET_Pos) /*!< PMU CTRL: Cycle Counter Reset Mask */ + +#define PMU_CTRL_CYCCNT_DISABLE_Pos 5U /*!< PMU CTRL: Disable Cycle Counter Position */ +#define PMU_CTRL_CYCCNT_DISABLE_Msk (1UL << PMU_CTRL_CYCCNT_DISABLE_Pos) /*!< PMU CTRL: Disable Cycle Counter Mask */ + +#define PMU_CTRL_FRZ_ON_OV_Pos 9U /*!< PMU CTRL: Freeze-on-overflow Position */ +#define PMU_CTRL_FRZ_ON_OV_Msk (1UL << PMU_CTRL_FRZ_ON_OVERFLOW_Pos) /*!< PMU CTRL: Freeze-on-overflow Mask */ + +#define PMU_CTRL_TRACE_ON_OV_Pos 11U /*!< PMU CTRL: Trace-on-overflow Position */ +#define PMU_CTRL_TRACE_ON_OV_Msk (1UL << PMU_CTRL_TRACE_ON_OVERFLOW_Pos) /*!< PMU CTRL: Trace-on-overflow Mask */ + +/** \brief PMU Type Register Definitions */ + +#define PMU_TYPE_NUM_CNTS_Pos 0U /*!< PMU TYPE: Number of Counters Position */ +#define PMU_TYPE_NUM_CNTS_Msk (0xFFUL /*<< PMU_TYPE_NUM_CNTS_Pos*/) /*!< PMU TYPE: Number of Counters Mask */ + +#define PMU_TYPE_SIZE_CNTS_Pos 8U /*!< PMU TYPE: Size of Counters Position */ +#define PMU_TYPE_SIZE_CNTS_Msk (0x3FUL << PMU_TYPE_SIZE_CNTS_Pos) /*!< PMU TYPE: Size of Counters Mask */ + +#define PMU_TYPE_CYCCNT_PRESENT_Pos 14U /*!< PMU TYPE: Cycle Counter Present Position */ +#define PMU_TYPE_CYCCNT_PRESENT_Msk (1UL << PMU_TYPE_CYCCNT_PRESENT_Pos) /*!< PMU TYPE: Cycle Counter Present Mask */ + +#define PMU_TYPE_FRZ_OV_SUPPORT_Pos 21U /*!< PMU TYPE: Freeze-on-overflow Support Position */ +#define PMU_TYPE_FRZ_OV_SUPPORT_Msk (1UL << PMU_TYPE_FRZ_OV_SUPPORT_Pos) /*!< PMU TYPE: Freeze-on-overflow Support Mask */ + +#define PMU_TYPE_TRACE_ON_OV_SUPPORT_Pos 23U /*!< PMU TYPE: Trace-on-overflow Support Position */ +#define PMU_TYPE_TRACE_ON_OV_SUPPORT_Msk (1UL << PMU_TYPE_FRZ_OV_SUPPORT_Pos) /*!< PMU TYPE: Trace-on-overflow Support Mask */ + +/** \brief PMU Authentication Status Register Definitions */ + +#define PMU_AUTHSTATUS_NSID_Pos 0U /*!< PMU AUTHSTATUS: Non-secure Invasive Debug Position */ +#define PMU_AUTHSTATUS_NSID_Msk (0x3UL /*<< PMU_AUTHSTATUS_NSID_Pos*/) /*!< PMU AUTHSTATUS: Non-secure Invasive Debug Mask */ + +#define PMU_AUTHSTATUS_NSNID_Pos 2U /*!< PMU AUTHSTATUS: Non-secure Non-invasive Debug Position */ +#define PMU_AUTHSTATUS_NSNID_Msk (0x3UL << PMU_AUTHSTATUS_NSNID_Pos) /*!< PMU AUTHSTATUS: Non-secure Non-invasive Debug Mask */ + +#define PMU_AUTHSTATUS_SID_Pos 4U /*!< PMU AUTHSTATUS: Secure Invasive Debug Position */ +#define PMU_AUTHSTATUS_SID_Msk (0x3UL << PMU_AUTHSTATUS_SID_Pos) /*!< PMU AUTHSTATUS: Secure Invasive Debug Mask */ + +#define PMU_AUTHSTATUS_SNID_Pos 6U /*!< PMU AUTHSTATUS: Secure Non-invasive Debug Position */ +#define PMU_AUTHSTATUS_SNID_Msk (0x3UL << PMU_AUTHSTATUS_SNID_Pos) /*!< PMU AUTHSTATUS: Secure Non-invasive Debug Mask */ + +#define PMU_AUTHSTATUS_NSUID_Pos 16U /*!< PMU AUTHSTATUS: Non-secure Unprivileged Invasive Debug Position */ +#define PMU_AUTHSTATUS_NSUID_Msk (0x3UL << PMU_AUTHSTATUS_NSUID_Pos) /*!< PMU AUTHSTATUS: Non-secure Unprivileged Invasive Debug Mask */ + +#define PMU_AUTHSTATUS_NSUNID_Pos 18U /*!< PMU AUTHSTATUS: Non-secure Unprivileged Non-invasive Debug Position */ +#define PMU_AUTHSTATUS_NSUNID_Msk (0x3UL << PMU_AUTHSTATUS_NSUNID_Pos) /*!< PMU AUTHSTATUS: Non-secure Unprivileged Non-invasive Debug Mask */ + +#define PMU_AUTHSTATUS_SUID_Pos 20U /*!< PMU AUTHSTATUS: Secure Unprivileged Invasive Debug Position */ +#define PMU_AUTHSTATUS_SUID_Msk (0x3UL << PMU_AUTHSTATUS_SUID_Pos) /*!< PMU AUTHSTATUS: Secure Unprivileged Invasive Debug Mask */ + +#define PMU_AUTHSTATUS_SUNID_Pos 22U /*!< PMU AUTHSTATUS: Secure Unprivileged Non-invasive Debug Position */ +#define PMU_AUTHSTATUS_SUNID_Msk (0x3UL << PMU_AUTHSTATUS_SUNID_Pos) /*!< PMU AUTHSTATUS: Secure Unprivileged Non-invasive Debug Mask */ + +/*@} end of group CMSIS_PMU */ +#endif + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */ + __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */ + __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */ + __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */ + uint32_t RESERVED0[1]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ +#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/* MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_PXN_Pos 4U /*!< MPU RLAR: PXN Position */ +#define MPU_RLAR_PXN_Msk (1UL << MPU_RLAR_PXN_Pos) /*!< MPU RLAR: PXN Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */ + +/* MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/* MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#else + uint32_t RESERVED0[3]; +#endif + __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */ +} SAU_Type; + +/* SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/* SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/* SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/* SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/* SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/* Secure Fault Status Register Definitions */ +#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */ +#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */ + +#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */ +#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */ + +#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */ +#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */ + +#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */ +#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */ + +#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */ +#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */ + +#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */ +#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */ + +#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */ +#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */ + +#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */ +#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and VFP Feature Register 2 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */ +#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */ + +#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */ +#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */ + +#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */ +#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */ + +#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */ +#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */ + +#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */ +#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */ + +#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */ +#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */ +#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */ +#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +#define FPU_FPDSCR_FZ16_Pos 19U /*!< FPDSCR: FZ16 bit Position */ +#define FPU_FPDSCR_FZ16_Msk (1UL << FPU_FPDSCR_FZ16_Pos) /*!< FPDSCR: FZ16 bit Mask */ + +#define FPU_FPDSCR_LTPSIZE_Pos 16U /*!< FPDSCR: LTPSIZE bit Position */ +#define FPU_FPDSCR_LTPSIZE_Msk (7UL << FPU_FPDSCR_LTPSIZE_Pos) /*!< FPDSCR: LTPSIZE bit Mask */ + +/* Media and VFP Feature Register 0 Definitions */ +#define FPU_MVFR0_FPRound_Pos 28U /*!< MVFR0: FPRound bits Position */ +#define FPU_MVFR0_FPRound_Msk (0xFUL << FPU_MVFR0_FPRound_Pos) /*!< MVFR0: FPRound bits Mask */ + +#define FPU_MVFR0_FPSqrt_Pos 20U /*!< MVFR0: FPSqrt bits Position */ +#define FPU_MVFR0_FPSqrt_Msk (0xFUL << FPU_MVFR0_FPSqrt_Pos) /*!< MVFR0: FPSqrt bits Mask */ + +#define FPU_MVFR0_FPDivide_Pos 16U /*!< MVFR0: FPDivide bits Position */ +#define FPU_MVFR0_FPDivide_Msk (0xFUL << FPU_MVFR0_FPDivide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FPDP_Pos 8U /*!< MVFR0: FPDP bits Position */ +#define FPU_MVFR0_FPDP_Msk (0xFUL << FPU_MVFR0_FPDP_Pos) /*!< MVFR0: FPDP bits Mask */ + +#define FPU_MVFR0_FPSP_Pos 4U /*!< MVFR0: FPSP bits Position */ +#define FPU_MVFR0_FPSP_Msk (0xFUL << FPU_MVFR0_FPSP_Pos) /*!< MVFR0: FPSP bits Mask */ + +#define FPU_MVFR0_SIMDReg_Pos 0U /*!< MVFR0: SIMDReg bits Position */ +#define FPU_MVFR0_SIMDReg_Msk (0xFUL /*<< FPU_MVFR0_SIMDReg_Pos*/) /*!< MVFR0: SIMDReg bits Mask */ + +/* Media and VFP Feature Register 1 Definitions */ +#define FPU_MVFR1_FMAC_Pos 28U /*!< MVFR1: FMAC bits Position */ +#define FPU_MVFR1_FMAC_Msk (0xFUL << FPU_MVFR1_FMAC_Pos) /*!< MVFR1: FMAC bits Mask */ + +#define FPU_MVFR1_FPHP_Pos 24U /*!< MVFR1: FPHP bits Position */ +#define FPU_MVFR1_FPHP_Msk (0xFUL << FPU_MVFR1_FPHP_Pos) /*!< MVFR1: FPHP bits Mask */ + +#define FPU_MVFR1_FP16_Pos 20U /*!< MVFR1: FP16 bits Position */ +#define FPU_MVFR1_FP16_Msk (0xFUL << FPU_MVFR1_FP16_Pos) /*!< MVFR1: FP16 bits Mask */ + +#define FPU_MVFR1_MVE_Pos 8U /*!< MVFR1: MVE bits Position */ +#define FPU_MVFR1_MVE_Msk (0xFUL << FPU_MVFR1_MVE_Pos) /*!< MVFR1: MVE bits Mask */ + +#define FPU_MVFR1_FPDNaN_Pos 4U /*!< MVFR1: FPDNaN bits Position */ +#define FPU_MVFR1_FPDNaN_Msk (0xFUL << FPU_MVFR1_FPDNaN_Pos) /*!< MVFR1: FPDNaN bits Mask */ + +#define FPU_MVFR1_FPFtZ_Pos 0U /*!< MVFR1: FPFtZ bits Position */ +#define FPU_MVFR1_FPFtZ_Msk (0xFUL /*<< FPU_MVFR1_FPFtZ_Pos*/) /*!< MVFR1: FPFtZ bits Mask */ + +/* Media and VFP Feature Register 2 Definitions */ +#define FPU_MVFR2_FPMisc_Pos 4U /*!< MVFR2: FPMisc bits Position */ +#define FPU_MVFR2_FPMisc_Msk (0xFUL << FPU_MVFR2_FPMisc_Pos) /*!< MVFR2: FPMisc bits Mask */ + +/*@} end of group CMSIS_FPU */ + +/* CoreDebug is deprecated. replaced by DCB (Debug Control Block) */ +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief \deprecated Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + __OM uint32_t DSCEMCR; /*!< Offset: 0x010 ( /W) Debug Set Clear Exception and Monitor Control Register */ + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< \deprecated CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< \deprecated CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Position */ +#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_FPD_Pos 23U /*!< \deprecated CoreDebug DHCSR: S_FPD Position */ +#define CoreDebug_DHCSR_S_FPD_Msk (1UL << CoreDebug_DHCSR_S_FPD_Pos) /*!< \deprecated CoreDebug DHCSR: S_FPD Mask */ + +#define CoreDebug_DHCSR_S_SUIDE_Pos 22U /*!< \deprecated CoreDebug DHCSR: S_SUIDE Position */ +#define CoreDebug_DHCSR_S_SUIDE_Msk (1UL << CoreDebug_DHCSR_S_SUIDE_Pos) /*!< \deprecated CoreDebug DHCSR: S_SUIDE Mask */ + +#define CoreDebug_DHCSR_S_NSUIDE_Pos 21U /*!< \deprecated CoreDebug DHCSR: S_NSUIDE Position */ +#define CoreDebug_DHCSR_S_NSUIDE_Msk (1UL << CoreDebug_DHCSR_S_NSUIDE_Pos) /*!< \deprecated CoreDebug DHCSR: S_NSUIDE Mask */ + +#define CoreDebug_DHCSR_S_SDE_Pos 20U /*!< \deprecated CoreDebug DHCSR: S_SDE Position */ +#define CoreDebug_DHCSR_S_SDE_Msk (1UL << CoreDebug_DHCSR_S_SDE_Pos) /*!< \deprecated CoreDebug DHCSR: S_SDE Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< \deprecated CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< \deprecated CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< \deprecated CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< \deprecated CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< \deprecated CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_PMOV_Pos 6U /*!< \deprecated CoreDebug DHCSR: C_PMOV Position */ +#define CoreDebug_DHCSR_C_PMOV_Msk (1UL << CoreDebug_DHCSR_C_PMOV_Pos) /*!< \deprecated CoreDebug DHCSR: C_PMOV Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< \deprecated CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< \deprecated CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< \deprecated CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< \deprecated CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< \deprecated CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< \deprecated CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< \deprecated CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< \deprecated CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< \deprecated CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< \deprecated CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< \deprecated CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< \deprecated CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< \deprecated CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< \deprecated CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< \deprecated CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< \deprecated CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< \deprecated CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< \deprecated CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< \deprecated CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< \deprecated CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< \deprecated CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< \deprecated CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< \deprecated CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< \deprecated CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< \deprecated CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Mask */ + +/* Debug Set Clear Exception and Monitor Control Register Definitions */ +#define CoreDebug_DSCEMCR_CLR_MON_REQ_Pos 19U /*!< \deprecated CoreDebug DSCEMCR: CLR_MON_REQ, Position */ +#define CoreDebug_DSCEMCR_CLR_MON_REQ_Msk (1UL << CoreDebug_DSCEMCR_CLR_MON_REQ_Pos) /*!< \deprecated CoreDebug DSCEMCR: CLR_MON_REQ, Mask */ + +#define CoreDebug_DSCEMCR_CLR_MON_PEND_Pos 17U /*!< \deprecated CoreDebug DSCEMCR: CLR_MON_PEND, Position */ +#define CoreDebug_DSCEMCR_CLR_MON_PEND_Msk (1UL << CoreDebug_DSCEMCR_CLR_MON_PEND_Pos) /*!< \deprecated CoreDebug DSCEMCR: CLR_MON_PEND, Mask */ + +#define CoreDebug_DSCEMCR_SET_MON_REQ_Pos 3U /*!< \deprecated CoreDebug DSCEMCR: SET_MON_REQ, Position */ +#define CoreDebug_DSCEMCR_SET_MON_REQ_Msk (1UL << CoreDebug_DSCEMCR_SET_MON_REQ_Pos) /*!< \deprecated CoreDebug DSCEMCR: SET_MON_REQ, Mask */ + +#define CoreDebug_DSCEMCR_SET_MON_PEND_Pos 1U /*!< \deprecated CoreDebug DSCEMCR: SET_MON_PEND, Position */ +#define CoreDebug_DSCEMCR_SET_MON_PEND_Msk (1UL << CoreDebug_DSCEMCR_SET_MON_PEND_Pos) /*!< \deprecated CoreDebug DSCEMCR: SET_MON_PEND, Mask */ + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_UIDEN_Pos 10U /*!< \deprecated CoreDebug DAUTHCTRL: UIDEN, Position */ +#define CoreDebug_DAUTHCTRL_UIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_UIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: UIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_UIDAPEN_Pos 9U /*!< \deprecated CoreDebug DAUTHCTRL: UIDAPEN, Position */ +#define CoreDebug_DAUTHCTRL_UIDAPEN_Msk (1UL << CoreDebug_DAUTHCTRL_UIDAPEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: UIDAPEN, Mask */ + +#define CoreDebug_DAUTHCTRL_FSDMA_Pos 8U /*!< \deprecated CoreDebug DAUTHCTRL: FSDMA, Position */ +#define CoreDebug_DAUTHCTRL_FSDMA_Msk (1UL << CoreDebug_DAUTHCTRL_FSDMA_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: FSDMA, Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Position */ +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Mask */ + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Mask */ + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos 16U /*!< \deprecated CoreDebug DSCSR: CDS Position */ +#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< \deprecated CoreDebug DSCSR: CDS Mask */ + +#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< \deprecated CoreDebug DSCSR: SBRSEL Position */ +#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< \deprecated CoreDebug DSCSR: SBRSEL Mask */ + +#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< \deprecated CoreDebug DSCSR: SBRSELEN Position */ +#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< \deprecated CoreDebug DSCSR: SBRSELEN Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DCB Debug Control Block + \brief Type definitions for the Debug Control Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Control Block Registers (DCB). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + __OM uint32_t DSCEMCR; /*!< Offset: 0x010 ( /W) Debug Set Clear Exception and Monitor Control Register */ + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} DCB_Type; + +/* DHCSR, Debug Halting Control and Status Register Definitions */ +#define DCB_DHCSR_DBGKEY_Pos 16U /*!< DCB DHCSR: Debug key Position */ +#define DCB_DHCSR_DBGKEY_Msk (0xFFFFUL << DCB_DHCSR_DBGKEY_Pos) /*!< DCB DHCSR: Debug key Mask */ + +#define DCB_DHCSR_S_RESTART_ST_Pos 26U /*!< DCB DHCSR: Restart sticky status Position */ +#define DCB_DHCSR_S_RESTART_ST_Msk (0x1UL << DCB_DHCSR_S_RESTART_ST_Pos) /*!< DCB DHCSR: Restart sticky status Mask */ + +#define DCB_DHCSR_S_RESET_ST_Pos 25U /*!< DCB DHCSR: Reset sticky status Position */ +#define DCB_DHCSR_S_RESET_ST_Msk (0x1UL << DCB_DHCSR_S_RESET_ST_Pos) /*!< DCB DHCSR: Reset sticky status Mask */ + +#define DCB_DHCSR_S_RETIRE_ST_Pos 24U /*!< DCB DHCSR: Retire sticky status Position */ +#define DCB_DHCSR_S_RETIRE_ST_Msk (0x1UL << DCB_DHCSR_S_RETIRE_ST_Pos) /*!< DCB DHCSR: Retire sticky status Mask */ + +#define DCB_DHCSR_S_FPD_Pos 23U /*!< DCB DHCSR: Floating-point registers Debuggable Position */ +#define DCB_DHCSR_S_FPD_Msk (0x1UL << DCB_DHCSR_S_FPD_Pos) /*!< DCB DHCSR: Floating-point registers Debuggable Mask */ + +#define DCB_DHCSR_S_SUIDE_Pos 22U /*!< DCB DHCSR: Secure unprivileged halting debug enabled Position */ +#define DCB_DHCSR_S_SUIDE_Msk (0x1UL << DCB_DHCSR_S_SUIDE_Pos) /*!< DCB DHCSR: Secure unprivileged halting debug enabled Mask */ + +#define DCB_DHCSR_S_NSUIDE_Pos 21U /*!< DCB DHCSR: Non-secure unprivileged halting debug enabled Position */ +#define DCB_DHCSR_S_NSUIDE_Msk (0x1UL << DCB_DHCSR_S_NSUIDE_Pos) /*!< DCB DHCSR: Non-secure unprivileged halting debug enabled Mask */ + +#define DCB_DHCSR_S_SDE_Pos 20U /*!< DCB DHCSR: Secure debug enabled Position */ +#define DCB_DHCSR_S_SDE_Msk (0x1UL << DCB_DHCSR_S_SDE_Pos) /*!< DCB DHCSR: Secure debug enabled Mask */ + +#define DCB_DHCSR_S_LOCKUP_Pos 19U /*!< DCB DHCSR: Lockup status Position */ +#define DCB_DHCSR_S_LOCKUP_Msk (0x1UL << DCB_DHCSR_S_LOCKUP_Pos) /*!< DCB DHCSR: Lockup status Mask */ + +#define DCB_DHCSR_S_SLEEP_Pos 18U /*!< DCB DHCSR: Sleeping status Position */ +#define DCB_DHCSR_S_SLEEP_Msk (0x1UL << DCB_DHCSR_S_SLEEP_Pos) /*!< DCB DHCSR: Sleeping status Mask */ + +#define DCB_DHCSR_S_HALT_Pos 17U /*!< DCB DHCSR: Halted status Position */ +#define DCB_DHCSR_S_HALT_Msk (0x1UL << DCB_DHCSR_S_HALT_Pos) /*!< DCB DHCSR: Halted status Mask */ + +#define DCB_DHCSR_S_REGRDY_Pos 16U /*!< DCB DHCSR: Register ready status Position */ +#define DCB_DHCSR_S_REGRDY_Msk (0x1UL << DCB_DHCSR_S_REGRDY_Pos) /*!< DCB DHCSR: Register ready status Mask */ + +#define DCB_DHCSR_C_PMOV_Pos 6U /*!< DCB DHCSR: Halt on PMU overflow control Position */ +#define DCB_DHCSR_C_PMOV_Msk (0x1UL << DCB_DHCSR_C_PMOV_Pos) /*!< DCB DHCSR: Halt on PMU overflow control Mask */ + +#define DCB_DHCSR_C_SNAPSTALL_Pos 5U /*!< DCB DHCSR: Snap stall control Position */ +#define DCB_DHCSR_C_SNAPSTALL_Msk (0x1UL << DCB_DHCSR_C_SNAPSTALL_Pos) /*!< DCB DHCSR: Snap stall control Mask */ + +#define DCB_DHCSR_C_MASKINTS_Pos 3U /*!< DCB DHCSR: Mask interrupts control Position */ +#define DCB_DHCSR_C_MASKINTS_Msk (0x1UL << DCB_DHCSR_C_MASKINTS_Pos) /*!< DCB DHCSR: Mask interrupts control Mask */ + +#define DCB_DHCSR_C_STEP_Pos 2U /*!< DCB DHCSR: Step control Position */ +#define DCB_DHCSR_C_STEP_Msk (0x1UL << DCB_DHCSR_C_STEP_Pos) /*!< DCB DHCSR: Step control Mask */ + +#define DCB_DHCSR_C_HALT_Pos 1U /*!< DCB DHCSR: Halt control Position */ +#define DCB_DHCSR_C_HALT_Msk (0x1UL << DCB_DHCSR_C_HALT_Pos) /*!< DCB DHCSR: Halt control Mask */ + +#define DCB_DHCSR_C_DEBUGEN_Pos 0U /*!< DCB DHCSR: Debug enable control Position */ +#define DCB_DHCSR_C_DEBUGEN_Msk (0x1UL /*<< DCB_DHCSR_C_DEBUGEN_Pos*/) /*!< DCB DHCSR: Debug enable control Mask */ + +/* DCRSR, Debug Core Register Select Register Definitions */ +#define DCB_DCRSR_REGWnR_Pos 16U /*!< DCB DCRSR: Register write/not-read Position */ +#define DCB_DCRSR_REGWnR_Msk (0x1UL << DCB_DCRSR_REGWnR_Pos) /*!< DCB DCRSR: Register write/not-read Mask */ + +#define DCB_DCRSR_REGSEL_Pos 0U /*!< DCB DCRSR: Register selector Position */ +#define DCB_DCRSR_REGSEL_Msk (0x7FUL /*<< DCB_DCRSR_REGSEL_Pos*/) /*!< DCB DCRSR: Register selector Mask */ + +/* DCRDR, Debug Core Register Data Register Definitions */ +#define DCB_DCRDR_DBGTMP_Pos 0U /*!< DCB DCRDR: Data temporary buffer Position */ +#define DCB_DCRDR_DBGTMP_Msk (0xFFFFFFFFUL /*<< DCB_DCRDR_DBGTMP_Pos*/) /*!< DCB DCRDR: Data temporary buffer Mask */ + +/* DEMCR, Debug Exception and Monitor Control Register Definitions */ +#define DCB_DEMCR_TRCENA_Pos 24U /*!< DCB DEMCR: Trace enable Position */ +#define DCB_DEMCR_TRCENA_Msk (0x1UL << DCB_DEMCR_TRCENA_Pos) /*!< DCB DEMCR: Trace enable Mask */ + +#define DCB_DEMCR_MONPRKEY_Pos 23U /*!< DCB DEMCR: Monitor pend req key Position */ +#define DCB_DEMCR_MONPRKEY_Msk (0x1UL << DCB_DEMCR_MONPRKEY_Pos) /*!< DCB DEMCR: Monitor pend req key Mask */ + +#define DCB_DEMCR_UMON_EN_Pos 21U /*!< DCB DEMCR: Unprivileged monitor enable Position */ +#define DCB_DEMCR_UMON_EN_Msk (0x1UL << DCB_DEMCR_UMON_EN_Pos) /*!< DCB DEMCR: Unprivileged monitor enable Mask */ + +#define DCB_DEMCR_SDME_Pos 20U /*!< DCB DEMCR: Secure DebugMonitor enable Position */ +#define DCB_DEMCR_SDME_Msk (0x1UL << DCB_DEMCR_SDME_Pos) /*!< DCB DEMCR: Secure DebugMonitor enable Mask */ + +#define DCB_DEMCR_MON_REQ_Pos 19U /*!< DCB DEMCR: Monitor request Position */ +#define DCB_DEMCR_MON_REQ_Msk (0x1UL << DCB_DEMCR_MON_REQ_Pos) /*!< DCB DEMCR: Monitor request Mask */ + +#define DCB_DEMCR_MON_STEP_Pos 18U /*!< DCB DEMCR: Monitor step Position */ +#define DCB_DEMCR_MON_STEP_Msk (0x1UL << DCB_DEMCR_MON_STEP_Pos) /*!< DCB DEMCR: Monitor step Mask */ + +#define DCB_DEMCR_MON_PEND_Pos 17U /*!< DCB DEMCR: Monitor pend Position */ +#define DCB_DEMCR_MON_PEND_Msk (0x1UL << DCB_DEMCR_MON_PEND_Pos) /*!< DCB DEMCR: Monitor pend Mask */ + +#define DCB_DEMCR_MON_EN_Pos 16U /*!< DCB DEMCR: Monitor enable Position */ +#define DCB_DEMCR_MON_EN_Msk (0x1UL << DCB_DEMCR_MON_EN_Pos) /*!< DCB DEMCR: Monitor enable Mask */ + +#define DCB_DEMCR_VC_SFERR_Pos 11U /*!< DCB DEMCR: Vector Catch SecureFault Position */ +#define DCB_DEMCR_VC_SFERR_Msk (0x1UL << DCB_DEMCR_VC_SFERR_Pos) /*!< DCB DEMCR: Vector Catch SecureFault Mask */ + +#define DCB_DEMCR_VC_HARDERR_Pos 10U /*!< DCB DEMCR: Vector Catch HardFault errors Position */ +#define DCB_DEMCR_VC_HARDERR_Msk (0x1UL << DCB_DEMCR_VC_HARDERR_Pos) /*!< DCB DEMCR: Vector Catch HardFault errors Mask */ + +#define DCB_DEMCR_VC_INTERR_Pos 9U /*!< DCB DEMCR: Vector Catch interrupt errors Position */ +#define DCB_DEMCR_VC_INTERR_Msk (0x1UL << DCB_DEMCR_VC_INTERR_Pos) /*!< DCB DEMCR: Vector Catch interrupt errors Mask */ + +#define DCB_DEMCR_VC_BUSERR_Pos 8U /*!< DCB DEMCR: Vector Catch BusFault errors Position */ +#define DCB_DEMCR_VC_BUSERR_Msk (0x1UL << DCB_DEMCR_VC_BUSERR_Pos) /*!< DCB DEMCR: Vector Catch BusFault errors Mask */ + +#define DCB_DEMCR_VC_STATERR_Pos 7U /*!< DCB DEMCR: Vector Catch state errors Position */ +#define DCB_DEMCR_VC_STATERR_Msk (0x1UL << DCB_DEMCR_VC_STATERR_Pos) /*!< DCB DEMCR: Vector Catch state errors Mask */ + +#define DCB_DEMCR_VC_CHKERR_Pos 6U /*!< DCB DEMCR: Vector Catch check errors Position */ +#define DCB_DEMCR_VC_CHKERR_Msk (0x1UL << DCB_DEMCR_VC_CHKERR_Pos) /*!< DCB DEMCR: Vector Catch check errors Mask */ + +#define DCB_DEMCR_VC_NOCPERR_Pos 5U /*!< DCB DEMCR: Vector Catch NOCP errors Position */ +#define DCB_DEMCR_VC_NOCPERR_Msk (0x1UL << DCB_DEMCR_VC_NOCPERR_Pos) /*!< DCB DEMCR: Vector Catch NOCP errors Mask */ + +#define DCB_DEMCR_VC_MMERR_Pos 4U /*!< DCB DEMCR: Vector Catch MemManage errors Position */ +#define DCB_DEMCR_VC_MMERR_Msk (0x1UL << DCB_DEMCR_VC_MMERR_Pos) /*!< DCB DEMCR: Vector Catch MemManage errors Mask */ + +#define DCB_DEMCR_VC_CORERESET_Pos 0U /*!< DCB DEMCR: Vector Catch Core reset Position */ +#define DCB_DEMCR_VC_CORERESET_Msk (0x1UL /*<< DCB_DEMCR_VC_CORERESET_Pos*/) /*!< DCB DEMCR: Vector Catch Core reset Mask */ + +/* DSCEMCR, Debug Set Clear Exception and Monitor Control Register Definitions */ +#define DCB_DSCEMCR_CLR_MON_REQ_Pos 19U /*!< DCB DSCEMCR: Clear monitor request Position */ +#define DCB_DSCEMCR_CLR_MON_REQ_Msk (0x1UL << DCB_DSCEMCR_CLR_MON_REQ_Pos) /*!< DCB DSCEMCR: Clear monitor request Mask */ + +#define DCB_DSCEMCR_CLR_MON_PEND_Pos 17U /*!< DCB DSCEMCR: Clear monitor pend Position */ +#define DCB_DSCEMCR_CLR_MON_PEND_Msk (0x1UL << DCB_DSCEMCR_CLR_MON_PEND_Pos) /*!< DCB DSCEMCR: Clear monitor pend Mask */ + +#define DCB_DSCEMCR_SET_MON_REQ_Pos 3U /*!< DCB DSCEMCR: Set monitor request Position */ +#define DCB_DSCEMCR_SET_MON_REQ_Msk (0x1UL << DCB_DSCEMCR_SET_MON_REQ_Pos) /*!< DCB DSCEMCR: Set monitor request Mask */ + +#define DCB_DSCEMCR_SET_MON_PEND_Pos 1U /*!< DCB DSCEMCR: Set monitor pend Position */ +#define DCB_DSCEMCR_SET_MON_PEND_Msk (0x1UL << DCB_DSCEMCR_SET_MON_PEND_Pos) /*!< DCB DSCEMCR: Set monitor pend Mask */ + +/* DAUTHCTRL, Debug Authentication Control Register Definitions */ +#define DCB_DAUTHCTRL_UIDEN_Pos 10U /*!< DCB DAUTHCTRL: Unprivileged Invasive Debug Enable Position */ +#define DCB_DAUTHCTRL_UIDEN_Msk (0x1UL << DCB_DAUTHCTRL_UIDEN_Pos) /*!< DCB DAUTHCTRL: Unprivileged Invasive Debug Enable Mask */ + +#define DCB_DAUTHCTRL_UIDAPEN_Pos 9U /*!< DCB DAUTHCTRL: Unprivileged Invasive DAP Access Enable Position */ +#define DCB_DAUTHCTRL_UIDAPEN_Msk (0x1UL << DCB_DAUTHCTRL_UIDAPEN_Pos) /*!< DCB DAUTHCTRL: Unprivileged Invasive DAP Access Enable Mask */ + +#define DCB_DAUTHCTRL_FSDMA_Pos 8U /*!< DCB DAUTHCTRL: Force Secure DebugMonitor Allowed Position */ +#define DCB_DAUTHCTRL_FSDMA_Msk (0x1UL << DCB_DAUTHCTRL_FSDMA_Pos) /*!< DCB DAUTHCTRL: Force Secure DebugMonitor Allowed Mask */ + +#define DCB_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPNIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPNIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPNIDENSEL_Msk (0x1UL << DCB_DAUTHCTRL_SPNIDENSEL_Pos) /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Mask */ + +#define DCB_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< DCB DAUTHCTRL: Secure invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPIDENSEL_Msk (0x1UL /*<< DCB_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< DCB DAUTHCTRL: Secure invasive debug enable select Mask */ + +/* DSCSR, Debug Security Control and Status Register Definitions */ +#define DCB_DSCSR_CDSKEY_Pos 17U /*!< DCB DSCSR: CDS write-enable key Position */ +#define DCB_DSCSR_CDSKEY_Msk (0x1UL << DCB_DSCSR_CDSKEY_Pos) /*!< DCB DSCSR: CDS write-enable key Mask */ + +#define DCB_DSCSR_CDS_Pos 16U /*!< DCB DSCSR: Current domain Secure Position */ +#define DCB_DSCSR_CDS_Msk (0x1UL << DCB_DSCSR_CDS_Pos) /*!< DCB DSCSR: Current domain Secure Mask */ + +#define DCB_DSCSR_SBRSEL_Pos 1U /*!< DCB DSCSR: Secure banked register select Position */ +#define DCB_DSCSR_SBRSEL_Msk (0x1UL << DCB_DSCSR_SBRSEL_Pos) /*!< DCB DSCSR: Secure banked register select Mask */ + +#define DCB_DSCSR_SBRSELEN_Pos 0U /*!< DCB DSCSR: Secure banked register select enable Position */ +#define DCB_DSCSR_SBRSELEN_Msk (0x1UL /*<< DCB_DSCSR_SBRSELEN_Pos*/) /*!< DCB DSCSR: Secure banked register select enable Mask */ + +/*@} end of group CMSIS_DCB */ + + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DIB Debug Identification Block + \brief Type definitions for the Debug Identification Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Identification Block Registers (DIB). + */ +typedef struct +{ + __OM uint32_t DLAR; /*!< Offset: 0x000 ( /W) SCS Software Lock Access Register */ + __IM uint32_t DLSR; /*!< Offset: 0x004 (R/ ) SCS Software Lock Status Register */ + __IM uint32_t DAUTHSTATUS; /*!< Offset: 0x008 (R/ ) Debug Authentication Status Register */ + __IM uint32_t DDEVARCH; /*!< Offset: 0x00C (R/ ) SCS Device Architecture Register */ + __IM uint32_t DDEVTYPE; /*!< Offset: 0x010 (R/ ) SCS Device Type Register */ +} DIB_Type; + +/* DLAR, SCS Software Lock Access Register Definitions */ +#define DIB_DLAR_KEY_Pos 0U /*!< DIB DLAR: KEY Position */ +#define DIB_DLAR_KEY_Msk (0xFFFFFFFFUL /*<< DIB_DLAR_KEY_Pos */) /*!< DIB DLAR: KEY Mask */ + +/* DLSR, SCS Software Lock Status Register Definitions */ +#define DIB_DLSR_nTT_Pos 2U /*!< DIB DLSR: Not thirty-two bit Position */ +#define DIB_DLSR_nTT_Msk (0x1UL << DIB_DLSR_nTT_Pos ) /*!< DIB DLSR: Not thirty-two bit Mask */ + +#define DIB_DLSR_SLK_Pos 1U /*!< DIB DLSR: Software Lock status Position */ +#define DIB_DLSR_SLK_Msk (0x1UL << DIB_DLSR_SLK_Pos ) /*!< DIB DLSR: Software Lock status Mask */ + +#define DIB_DLSR_SLI_Pos 0U /*!< DIB DLSR: Software Lock implemented Position */ +#define DIB_DLSR_SLI_Msk (0x1UL /*<< DIB_DLSR_SLI_Pos*/) /*!< DIB DLSR: Software Lock implemented Mask */ + +/* DAUTHSTATUS, Debug Authentication Status Register Definitions */ +#define DIB_DAUTHSTATUS_SUNID_Pos 22U /*!< DIB DAUTHSTATUS: Secure Unprivileged Non-invasive Debug Allowed Position */ +#define DIB_DAUTHSTATUS_SUNID_Msk (0x3UL << DIB_DAUTHSTATUS_SUNID_Pos ) /*!< DIB DAUTHSTATUS: Secure Unprivileged Non-invasive Debug Allowed Mask */ + +#define DIB_DAUTHSTATUS_SUID_Pos 20U /*!< DIB DAUTHSTATUS: Secure Unprivileged Invasive Debug Allowed Position */ +#define DIB_DAUTHSTATUS_SUID_Msk (0x3UL << DIB_DAUTHSTATUS_SUID_Pos ) /*!< DIB DAUTHSTATUS: Secure Unprivileged Invasive Debug Allowed Mask */ + +#define DIB_DAUTHSTATUS_NSUNID_Pos 18U /*!< DIB DAUTHSTATUS: Non-secure Unprivileged Non-invasive Debug Allo Position */ +#define DIB_DAUTHSTATUS_NSUNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSUNID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Unprivileged Non-invasive Debug Allo Mask */ + +#define DIB_DAUTHSTATUS_NSUID_Pos 16U /*!< DIB DAUTHSTATUS: Non-secure Unprivileged Invasive Debug Allowed Position */ +#define DIB_DAUTHSTATUS_NSUID_Msk (0x3UL << DIB_DAUTHSTATUS_NSUID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Unprivileged Invasive Debug Allowed Mask */ + +#define DIB_DAUTHSTATUS_SNID_Pos 6U /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_SNID_Msk (0x3UL << DIB_DAUTHSTATUS_SNID_Pos ) /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_SID_Pos 4U /*!< DIB DAUTHSTATUS: Secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_SID_Msk (0x3UL << DIB_DAUTHSTATUS_SID_Pos ) /*!< DIB DAUTHSTATUS: Secure Invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSNID_Pos 2U /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSNID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSID_Pos 0U /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSID_Msk (0x3UL /*<< DIB_DAUTHSTATUS_NSID_Pos*/) /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Mask */ + +/* DDEVARCH, SCS Device Architecture Register Definitions */ +#define DIB_DDEVARCH_ARCHITECT_Pos 21U /*!< DIB DDEVARCH: Architect Position */ +#define DIB_DDEVARCH_ARCHITECT_Msk (0x7FFUL << DIB_DDEVARCH_ARCHITECT_Pos ) /*!< DIB DDEVARCH: Architect Mask */ + +#define DIB_DDEVARCH_PRESENT_Pos 20U /*!< DIB DDEVARCH: DEVARCH Present Position */ +#define DIB_DDEVARCH_PRESENT_Msk (0x1FUL << DIB_DDEVARCH_PRESENT_Pos ) /*!< DIB DDEVARCH: DEVARCH Present Mask */ + +#define DIB_DDEVARCH_REVISION_Pos 16U /*!< DIB DDEVARCH: Revision Position */ +#define DIB_DDEVARCH_REVISION_Msk (0xFUL << DIB_DDEVARCH_REVISION_Pos ) /*!< DIB DDEVARCH: Revision Mask */ + +#define DIB_DDEVARCH_ARCHVER_Pos 12U /*!< DIB DDEVARCH: Architecture Version Position */ +#define DIB_DDEVARCH_ARCHVER_Msk (0xFUL << DIB_DDEVARCH_ARCHVER_Pos ) /*!< DIB DDEVARCH: Architecture Version Mask */ + +#define DIB_DDEVARCH_ARCHPART_Pos 0U /*!< DIB DDEVARCH: Architecture Part Position */ +#define DIB_DDEVARCH_ARCHPART_Msk (0xFFFUL /*<< DIB_DDEVARCH_ARCHPART_Pos*/) /*!< DIB DDEVARCH: Architecture Part Mask */ + +/* DDEVTYPE, SCS Device Type Register Definitions */ +#define DIB_DDEVTYPE_SUB_Pos 4U /*!< DIB DDEVTYPE: Sub-type Position */ +#define DIB_DDEVTYPE_SUB_Msk (0xFUL << DIB_DDEVTYPE_SUB_Pos ) /*!< DIB DDEVTYPE: Sub-type Mask */ + +#define DIB_DDEVTYPE_MAJOR_Pos 0U /*!< DIB DDEVTYPE: Major type Position */ +#define DIB_DDEVTYPE_MAJOR_Msk (0xFUL /*<< DIB_DDEVTYPE_MAJOR_Pos*/) /*!< DIB DDEVTYPE: Major type Mask */ + + +/*@} end of group CMSIS_DIB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ + #define CoreDebug_BASE (0xE000EDF0UL) /*!< \deprecated Core Debug Base Address */ + #define DCB_BASE (0xE000EDF0UL) /*!< DCB Base Address */ + #define DIB_BASE (0xE000EFB0UL) /*!< DIB Base Address */ + #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ + #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ + #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ + #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ + #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ + #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ + #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< \deprecated Core Debug configuration struct */ + #define DCB ((DCB_Type *) DCB_BASE ) /*!< DCB configuration struct */ + #define DIB ((DIB_Type *) DIB_BASE ) /*!< DIB configuration struct */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ + #endif + + #if defined (__PMU_PRESENT) && (__PMU_PRESENT == 1U) + #define PMU_BASE (0xE0003000UL) /*!< PMU Base Address */ + #define PMU ((PMU_Type *) PMU_BASE ) /*!< PMU configuration struct */ + #endif + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ + #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ + #endif + + #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ + #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ + #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< \deprecated Core Debug Base Address (non-secure address space) */ + #define DCB_BASE_NS (0xE002EDF0UL) /*!< DCB Base Address (non-secure address space) */ + #define DIB_BASE_NS (0xE002EFB0UL) /*!< DIB Base Address (non-secure address space) */ + #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ + #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ + #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + + #define SCnSCB_NS ((SCnSCB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */ + #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ + #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ + #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ + #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< \deprecated Core Debug configuration struct (non-secure address space) */ + #define DCB_NS ((DCB_Type *) DCB_BASE_NS ) /*!< DCB configuration struct (non-secure address space) */ + #define DIB_NS ((DIB_Type *) DIB_BASE_NS ) /*!< DIB configuration struct (non-secure address space) */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ + #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ + #endif + + #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */ + #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */ + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_register_aliases Backwards Compatibility Aliases + \brief Register alias definitions for backwards compatibility. + @{ + */ +#define ID_ADR (ID_AFR) /*!< SCB Auxiliary Feature Register */ +/*@} */ + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* Special LR values for Secure/Non-Secure call handling and exception handling */ + +/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ +#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ + +/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ +#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ +#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ +#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ +#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ +#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ +#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */ +#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ + +/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ +#else +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ +#endif + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + __DSB(); +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Priority Grouping (non-secure) + \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB_NS->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB_NS->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping (non-secure) + \details Reads the priority grouping field from the non-secure NVIC when in secure state. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void) +{ + return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv8.h" + +#endif + +/* ########################## PMU functions and events #################################### */ + +#if defined (__PMU_PRESENT) && (__PMU_PRESENT == 1U) + +#include "pmu_armv8.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = FPU->MVFR0; + if ((mvfr0 & (FPU_MVFR0_FPSP_Msk | FPU_MVFR0_FPDP_Msk)) == 0x220U) + { + return 2U; /* Double + Single precision FPU */ + } + else if ((mvfr0 & (FPU_MVFR0_FPSP_Msk | FPU_MVFR0_FPDP_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + +/* ########################## MVE functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_MveFunctions MVE Functions + \brief Function that provides MVE type. + @{ + */ + +/** + \brief get MVE type + \details returns the MVE type + \returns + - \b 0: No Vector Extension (MVE) + - \b 1: Integer Vector Extension (MVE-I) + - \b 2: Floating-point Vector Extension (MVE-F) + */ +__STATIC_INLINE uint32_t SCB_GetMVEType(void) +{ + const uint32_t mvfr1 = FPU->MVFR1; + if ((mvfr1 & FPU_MVFR1_MVE_Msk) == (0x2U << FPU_MVFR1_MVE_Pos)) + { + return 2U; + } + else if ((mvfr1 & FPU_MVFR1_MVE_Msk) == (0x1U << FPU_MVFR1_MVE_Pos)) + { + return 1U; + } + else + { + return 0U; + } +} + + +/*@} end of CMSIS_Core_MveFunctions */ + + +/* ########################## Cache functions #################################### */ + +#if ((defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)) || \ + (defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U))) +#include "cachel1_armv7.h" +#endif + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + + +/* ################################## Debug Control function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DCBFunctions Debug Control Functions + \brief Functions that access the Debug Control Block. + @{ + */ + + +/** + \brief Set Debug Authentication Control Register + \details writes to Debug Authentication Control register. + \param [in] value value to be writen. + */ +__STATIC_INLINE void DCB_SetAuthCtrl(uint32_t value) +{ + __DSB(); + __ISB(); + DCB->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register + \details Reads Debug Authentication Control register. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t DCB_GetAuthCtrl(void) +{ + return (DCB->DAUTHCTRL); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Debug Authentication Control Register (non-secure) + \details writes to non-secure Debug Authentication Control register when in secure state. + \param [in] value value to be writen + */ +__STATIC_INLINE void TZ_DCB_SetAuthCtrl_NS(uint32_t value) +{ + __DSB(); + __ISB(); + DCB_NS->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register (non-secure) + \details Reads non-secure Debug Authentication Control register when in secure state. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t TZ_DCB_GetAuthCtrl_NS(void) +{ + return (DCB_NS->DAUTHCTRL); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## Debug Identification function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DIBFunctions Debug Identification Functions + \brief Functions that access the Debug Identification Block. + @{ + */ + + +/** + \brief Get Debug Authentication Status Register + \details Reads Debug Authentication Status register. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t DIB_GetAuthStatus(void) +{ + return (DIB->DAUTHSTATUS); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Debug Authentication Status Register (non-secure) + \details Reads non-secure Debug Authentication Status register when in secure state. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t TZ_DIB_GetAuthStatus_NS(void) +{ + return (DIB_NS->DAUTHSTATUS); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_ARMV81MML_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/CMSIS/Core/Include/core_armv8mbl.h b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/CMSIS/Core/Include/core_armv8mbl.h new file mode 100644 index 0000000000..e9c9b5bf59 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/CMSIS/Core/Include/core_armv8mbl.h @@ -0,0 +1,2222 @@ +/**************************************************************************//** + * @file core_armv8mbl.h + * @brief CMSIS Armv8-M Baseline Core Peripheral Access Layer Header File + * @version V5.1.0 + * @date 27. March 2020 + ******************************************************************************/ +/* + * Copyright (c) 2009-2020 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#elif defined ( __GNUC__ ) + #pragma GCC diagnostic ignored "-Wpedantic" /* disable pedantic warning due to unnamed structs/unions */ +#endif + +#ifndef __CORE_ARMV8MBL_H_GENERIC +#define __CORE_ARMV8MBL_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_ARMv8MBL + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS definitions */ +#define __ARMv8MBL_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __ARMv8MBL_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __ARMv8MBL_CMSIS_VERSION ((__ARMv8MBL_CMSIS_VERSION_MAIN << 16U) | \ + __ARMv8MBL_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (2U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_ARMV8MBL_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_ARMV8MBL_H_DEPENDANT +#define __CORE_ARMV8MBL_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __ARMv8MBL_REV + #define __ARMv8MBL_REV 0x0000U + #warning "__ARMv8MBL_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 0U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif + + #ifndef __ETM_PRESENT + #define __ETM_PRESENT 0U + #warning "__ETM_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MTB_PRESENT + #define __MTB_PRESENT 0U + #warning "__MTB_PRESENT not defined in device header file; using default!" + #endif + +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group ARMv8MBL */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core SAU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint32_t IPR[124U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ +#else + uint32_t RESERVED0; +#endif + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IOM uint32_t SHPR[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ +#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#endif + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + uint32_t RESERVED0[6U]; + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED14[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED15[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED16[1U]; + __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ + uint32_t RESERVED17[1U]; + __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ + uint32_t RESERVED18[1U]; + __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ + uint32_t RESERVED19[1U]; + __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ + uint32_t RESERVED20[1U]; + __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ + uint32_t RESERVED21[1U]; + __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ + uint32_t RESERVED22[1U]; + __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ + uint32_t RESERVED23[1U]; + __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ + uint32_t RESERVED24[1U]; + __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ + uint32_t RESERVED25[1U]; + __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ + uint32_t RESERVED26[1U]; + __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ + uint32_t RESERVED27[1U]; + __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ + uint32_t RESERVED28[1U]; + __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ + uint32_t RESERVED29[1U]; + __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ + uint32_t RESERVED30[1U]; + __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ + uint32_t RESERVED31[1U]; + __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x3UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Sizes Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Sizes Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ + uint32_t RESERVED3[809U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) Software Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) Software Lock Status Register */ + uint32_t RESERVED4[4U]; + __IM uint32_t TYPE; /*!< Offset: 0xFC8 (R/ ) Device Identifier Register */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Register */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_SWOSCALER_Pos 0U /*!< TPI ACPR: SWOSCALER Position */ +#define TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/) /*!< TPI ACPR: SWOSCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ +#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI Periodic Synchronization Control Register Definitions */ +#define TPI_PSCR_PSCount_Pos 0U /*!< TPI PSCR: PSCount Position */ +#define TPI_PSCR_PSCount_Msk (0x1FUL /*<< TPI_PSCR_PSCount_Pos*/) /*!< TPI PSCR: TPSCount Mask */ + +/* TPI Software Lock Status Register Definitions */ +#define TPI_LSR_nTT_Pos 1U /*!< TPI LSR: Not thirty-two bit. Position */ +#define TPI_LSR_nTT_Msk (0x1UL << TPI_LSR_nTT_Pos) /*!< TPI LSR: Not thirty-two bit. Mask */ + +#define TPI_LSR_SLK_Pos 1U /*!< TPI LSR: Software Lock status Position */ +#define TPI_LSR_SLK_Msk (0x1UL << TPI_LSR_SLK_Pos) /*!< TPI LSR: Software Lock status Mask */ + +#define TPI_LSR_SLI_Pos 0U /*!< TPI LSR: Software Lock implemented Position */ +#define TPI_LSR_SLI_Msk (0x1UL /*<< TPI_LSR_SLI_Pos*/) /*!< TPI LSR: Software Lock implemented Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFO depth Position */ +#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFO depth Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + uint32_t RESERVED0[7U]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 1U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ +#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/* MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: EN Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: EN Mask */ + +/* MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/* MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#endif +} SAU_Type; + +/* SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/* SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/* SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/* SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/* SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/* CoreDebug is deprecated. replaced by DCB (Debug Control Block) */ +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief \deprecated Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED0[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< \deprecated CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< \deprecated CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Position */ +#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< \deprecated CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< \deprecated CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< \deprecated CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< \deprecated CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< \deprecated CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< \deprecated CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< \deprecated CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< \deprecated CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< \deprecated CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< \deprecated CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< \deprecated CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< \deprecated CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_DWTENA_Pos 24U /*!< \deprecated CoreDebug DEMCR: DWTENA Position */ +#define CoreDebug_DEMCR_DWTENA_Msk (1UL << CoreDebug_DEMCR_DWTENA_Pos) /*!< \deprecated CoreDebug DEMCR: DWTENA Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Mask */ + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Position */ +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Mask */ + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Mask */ + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos 16U /*!< \deprecated CoreDebug DSCSR: CDS Position */ +#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< \deprecated CoreDebug DSCSR: CDS Mask */ + +#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< \deprecated CoreDebug DSCSR: SBRSEL Position */ +#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< \deprecated CoreDebug DSCSR: SBRSEL Mask */ + +#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< \deprecated CoreDebug DSCSR: SBRSELEN Position */ +#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< \deprecated CoreDebug DSCSR: SBRSELEN Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DCB Debug Control Block + \brief Type definitions for the Debug Control Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Control Block Registers (DCB). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED0[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} DCB_Type; + +/* DHCSR, Debug Halting Control and Status Register Definitions */ +#define DCB_DHCSR_DBGKEY_Pos 16U /*!< DCB DHCSR: Debug key Position */ +#define DCB_DHCSR_DBGKEY_Msk (0xFFFFUL << DCB_DHCSR_DBGKEY_Pos) /*!< DCB DHCSR: Debug key Mask */ + +#define DCB_DHCSR_S_RESTART_ST_Pos 26U /*!< DCB DHCSR: Restart sticky status Position */ +#define DCB_DHCSR_S_RESTART_ST_Msk (0x1UL << DCB_DHCSR_S_RESTART_ST_Pos) /*!< DCB DHCSR: Restart sticky status Mask */ + +#define DCB_DHCSR_S_RESET_ST_Pos 25U /*!< DCB DHCSR: Reset sticky status Position */ +#define DCB_DHCSR_S_RESET_ST_Msk (0x1UL << DCB_DHCSR_S_RESET_ST_Pos) /*!< DCB DHCSR: Reset sticky status Mask */ + +#define DCB_DHCSR_S_RETIRE_ST_Pos 24U /*!< DCB DHCSR: Retire sticky status Position */ +#define DCB_DHCSR_S_RETIRE_ST_Msk (0x1UL << DCB_DHCSR_S_RETIRE_ST_Pos) /*!< DCB DHCSR: Retire sticky status Mask */ + +#define DCB_DHCSR_S_SDE_Pos 20U /*!< DCB DHCSR: Secure debug enabled Position */ +#define DCB_DHCSR_S_SDE_Msk (0x1UL << DCB_DHCSR_S_SDE_Pos) /*!< DCB DHCSR: Secure debug enabled Mask */ + +#define DCB_DHCSR_S_LOCKUP_Pos 19U /*!< DCB DHCSR: Lockup status Position */ +#define DCB_DHCSR_S_LOCKUP_Msk (0x1UL << DCB_DHCSR_S_LOCKUP_Pos) /*!< DCB DHCSR: Lockup status Mask */ + +#define DCB_DHCSR_S_SLEEP_Pos 18U /*!< DCB DHCSR: Sleeping status Position */ +#define DCB_DHCSR_S_SLEEP_Msk (0x1UL << DCB_DHCSR_S_SLEEP_Pos) /*!< DCB DHCSR: Sleeping status Mask */ + +#define DCB_DHCSR_S_HALT_Pos 17U /*!< DCB DHCSR: Halted status Position */ +#define DCB_DHCSR_S_HALT_Msk (0x1UL << DCB_DHCSR_S_HALT_Pos) /*!< DCB DHCSR: Halted status Mask */ + +#define DCB_DHCSR_S_REGRDY_Pos 16U /*!< DCB DHCSR: Register ready status Position */ +#define DCB_DHCSR_S_REGRDY_Msk (0x1UL << DCB_DHCSR_S_REGRDY_Pos) /*!< DCB DHCSR: Register ready status Mask */ + +#define DCB_DHCSR_C_MASKINTS_Pos 3U /*!< DCB DHCSR: Mask interrupts control Position */ +#define DCB_DHCSR_C_MASKINTS_Msk (0x1UL << DCB_DHCSR_C_MASKINTS_Pos) /*!< DCB DHCSR: Mask interrupts control Mask */ + +#define DCB_DHCSR_C_STEP_Pos 2U /*!< DCB DHCSR: Step control Position */ +#define DCB_DHCSR_C_STEP_Msk (0x1UL << DCB_DHCSR_C_STEP_Pos) /*!< DCB DHCSR: Step control Mask */ + +#define DCB_DHCSR_C_HALT_Pos 1U /*!< DCB DHCSR: Halt control Position */ +#define DCB_DHCSR_C_HALT_Msk (0x1UL << DCB_DHCSR_C_HALT_Pos) /*!< DCB DHCSR: Halt control Mask */ + +#define DCB_DHCSR_C_DEBUGEN_Pos 0U /*!< DCB DHCSR: Debug enable control Position */ +#define DCB_DHCSR_C_DEBUGEN_Msk (0x1UL /*<< DCB_DHCSR_C_DEBUGEN_Pos*/) /*!< DCB DHCSR: Debug enable control Mask */ + +/* DCRSR, Debug Core Register Select Register Definitions */ +#define DCB_DCRSR_REGWnR_Pos 16U /*!< DCB DCRSR: Register write/not-read Position */ +#define DCB_DCRSR_REGWnR_Msk (0x1UL << DCB_DCRSR_REGWnR_Pos) /*!< DCB DCRSR: Register write/not-read Mask */ + +#define DCB_DCRSR_REGSEL_Pos 0U /*!< DCB DCRSR: Register selector Position */ +#define DCB_DCRSR_REGSEL_Msk (0x7FUL /*<< DCB_DCRSR_REGSEL_Pos*/) /*!< DCB DCRSR: Register selector Mask */ + +/* DCRDR, Debug Core Register Data Register Definitions */ +#define DCB_DCRDR_DBGTMP_Pos 0U /*!< DCB DCRDR: Data temporary buffer Position */ +#define DCB_DCRDR_DBGTMP_Msk (0xFFFFFFFFUL /*<< DCB_DCRDR_DBGTMP_Pos*/) /*!< DCB DCRDR: Data temporary buffer Mask */ + +/* DEMCR, Debug Exception and Monitor Control Register Definitions */ +#define DCB_DEMCR_TRCENA_Pos 24U /*!< DCB DEMCR: Trace enable Position */ +#define DCB_DEMCR_TRCENA_Msk (0x1UL << DCB_DEMCR_TRCENA_Pos) /*!< DCB DEMCR: Trace enable Mask */ + +#define DCB_DEMCR_VC_HARDERR_Pos 10U /*!< DCB DEMCR: Vector Catch HardFault errors Position */ +#define DCB_DEMCR_VC_HARDERR_Msk (0x1UL << DCB_DEMCR_VC_HARDERR_Pos) /*!< DCB DEMCR: Vector Catch HardFault errors Mask */ + +#define DCB_DEMCR_VC_CORERESET_Pos 0U /*!< DCB DEMCR: Vector Catch Core reset Position */ +#define DCB_DEMCR_VC_CORERESET_Msk (0x1UL /*<< DCB_DEMCR_VC_CORERESET_Pos*/) /*!< DCB DEMCR: Vector Catch Core reset Mask */ + +/* DAUTHCTRL, Debug Authentication Control Register Definitions */ +#define DCB_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPNIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPNIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPNIDENSEL_Msk (0x1UL << DCB_DAUTHCTRL_SPNIDENSEL_Pos) /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Mask */ + +#define DCB_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< DCB DAUTHCTRL: Secure invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPIDENSEL_Msk (0x1UL /*<< DCB_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< DCB DAUTHCTRL: Secure invasive debug enable select Mask */ + +/* DSCSR, Debug Security Control and Status Register Definitions */ +#define DCB_DSCSR_CDSKEY_Pos 17U /*!< DCB DSCSR: CDS write-enable key Position */ +#define DCB_DSCSR_CDSKEY_Msk (0x1UL << DCB_DSCSR_CDSKEY_Pos) /*!< DCB DSCSR: CDS write-enable key Mask */ + +#define DCB_DSCSR_CDS_Pos 16U /*!< DCB DSCSR: Current domain Secure Position */ +#define DCB_DSCSR_CDS_Msk (0x1UL << DCB_DSCSR_CDS_Pos) /*!< DCB DSCSR: Current domain Secure Mask */ + +#define DCB_DSCSR_SBRSEL_Pos 1U /*!< DCB DSCSR: Secure banked register select Position */ +#define DCB_DSCSR_SBRSEL_Msk (0x1UL << DCB_DSCSR_SBRSEL_Pos) /*!< DCB DSCSR: Secure banked register select Mask */ + +#define DCB_DSCSR_SBRSELEN_Pos 0U /*!< DCB DSCSR: Secure banked register select enable Position */ +#define DCB_DSCSR_SBRSELEN_Msk (0x1UL /*<< DCB_DSCSR_SBRSELEN_Pos*/) /*!< DCB DSCSR: Secure banked register select enable Mask */ + +/*@} end of group CMSIS_DCB */ + + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DIB Debug Identification Block + \brief Type definitions for the Debug Identification Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Identification Block Registers (DIB). + */ +typedef struct +{ + __OM uint32_t DLAR; /*!< Offset: 0x000 ( /W) SCS Software Lock Access Register */ + __IM uint32_t DLSR; /*!< Offset: 0x004 (R/ ) SCS Software Lock Status Register */ + __IM uint32_t DAUTHSTATUS; /*!< Offset: 0x008 (R/ ) Debug Authentication Status Register */ + __IM uint32_t DDEVARCH; /*!< Offset: 0x00C (R/ ) SCS Device Architecture Register */ + __IM uint32_t DDEVTYPE; /*!< Offset: 0x010 (R/ ) SCS Device Type Register */ +} DIB_Type; + +/* DLAR, SCS Software Lock Access Register Definitions */ +#define DIB_DLAR_KEY_Pos 0U /*!< DIB DLAR: KEY Position */ +#define DIB_DLAR_KEY_Msk (0xFFFFFFFFUL /*<< DIB_DLAR_KEY_Pos */) /*!< DIB DLAR: KEY Mask */ + +/* DLSR, SCS Software Lock Status Register Definitions */ +#define DIB_DLSR_nTT_Pos 2U /*!< DIB DLSR: Not thirty-two bit Position */ +#define DIB_DLSR_nTT_Msk (0x1UL << DIB_DLSR_nTT_Pos ) /*!< DIB DLSR: Not thirty-two bit Mask */ + +#define DIB_DLSR_SLK_Pos 1U /*!< DIB DLSR: Software Lock status Position */ +#define DIB_DLSR_SLK_Msk (0x1UL << DIB_DLSR_SLK_Pos ) /*!< DIB DLSR: Software Lock status Mask */ + +#define DIB_DLSR_SLI_Pos 0U /*!< DIB DLSR: Software Lock implemented Position */ +#define DIB_DLSR_SLI_Msk (0x1UL /*<< DIB_DLSR_SLI_Pos*/) /*!< DIB DLSR: Software Lock implemented Mask */ + +/* DAUTHSTATUS, Debug Authentication Status Register Definitions */ +#define DIB_DAUTHSTATUS_SNID_Pos 6U /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_SNID_Msk (0x3UL << DIB_DAUTHSTATUS_SNID_Pos ) /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_SID_Pos 4U /*!< DIB DAUTHSTATUS: Secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_SID_Msk (0x3UL << DIB_DAUTHSTATUS_SID_Pos ) /*!< DIB DAUTHSTATUS: Secure Invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSNID_Pos 2U /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSNID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSID_Pos 0U /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSID_Msk (0x3UL /*<< DIB_DAUTHSTATUS_NSID_Pos*/) /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Mask */ + +/* DDEVARCH, SCS Device Architecture Register Definitions */ +#define DIB_DDEVARCH_ARCHITECT_Pos 21U /*!< DIB DDEVARCH: Architect Position */ +#define DIB_DDEVARCH_ARCHITECT_Msk (0x7FFUL << DIB_DDEVARCH_ARCHITECT_Pos ) /*!< DIB DDEVARCH: Architect Mask */ + +#define DIB_DDEVARCH_PRESENT_Pos 20U /*!< DIB DDEVARCH: DEVARCH Present Position */ +#define DIB_DDEVARCH_PRESENT_Msk (0x1FUL << DIB_DDEVARCH_PRESENT_Pos ) /*!< DIB DDEVARCH: DEVARCH Present Mask */ + +#define DIB_DDEVARCH_REVISION_Pos 16U /*!< DIB DDEVARCH: Revision Position */ +#define DIB_DDEVARCH_REVISION_Msk (0xFUL << DIB_DDEVARCH_REVISION_Pos ) /*!< DIB DDEVARCH: Revision Mask */ + +#define DIB_DDEVARCH_ARCHVER_Pos 12U /*!< DIB DDEVARCH: Architecture Version Position */ +#define DIB_DDEVARCH_ARCHVER_Msk (0xFUL << DIB_DDEVARCH_ARCHVER_Pos ) /*!< DIB DDEVARCH: Architecture Version Mask */ + +#define DIB_DDEVARCH_ARCHPART_Pos 0U /*!< DIB DDEVARCH: Architecture Part Position */ +#define DIB_DDEVARCH_ARCHPART_Msk (0xFFFUL /*<< DIB_DDEVARCH_ARCHPART_Pos*/) /*!< DIB DDEVARCH: Architecture Part Mask */ + +/* DDEVTYPE, SCS Device Type Register Definitions */ +#define DIB_DDEVTYPE_SUB_Pos 4U /*!< DIB DDEVTYPE: Sub-type Position */ +#define DIB_DDEVTYPE_SUB_Msk (0xFUL << DIB_DDEVTYPE_SUB_Pos ) /*!< DIB DDEVTYPE: Sub-type Mask */ + +#define DIB_DDEVTYPE_MAJOR_Pos 0U /*!< DIB DDEVTYPE: Major type Position */ +#define DIB_DDEVTYPE_MAJOR_Msk (0xFUL /*<< DIB_DDEVTYPE_MAJOR_Pos*/) /*!< DIB DDEVTYPE: Major type Mask */ + + +/*@} end of group CMSIS_DIB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ + #define CoreDebug_BASE (0xE000EDF0UL) /*!< \deprecated Core Debug Base Address */ + #define DCB_BASE (0xE000EDF0UL) /*!< DCB Base Address */ + #define DIB_BASE (0xE000EFB0UL) /*!< DIB Base Address */ + #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + + #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ + #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ + #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ + #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ + #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< \deprecated Core Debug configuration struct */ + #define DCB ((DCB_Type *) DCB_BASE ) /*!< DCB configuration struct */ + #define DIB ((DIB_Type *) DIB_BASE ) /*!< DIB configuration struct */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ + #endif + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ + #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ + #endif + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ + #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< \deprecated Core Debug Base Address (non-secure address space) */ + #define DCB_BASE_NS (0xE002EDF0UL) /*!< DCB Base Address (non-secure address space) */ + #define DIB_BASE_NS (0xE002EFB0UL) /*!< DIB Base Address (non-secure address space) */ + #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ + #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ + #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + + #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ + #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ + #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ + #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< \deprecated Core Debug configuration struct (non-secure address space) */ + #define DCB_NS ((DCB_Type *) DCB_BASE_NS ) /*!< DCB configuration struct (non-secure address space) */ + #define DIB_NS ((DIB_Type *) DIB_BASE_NS ) /*!< DIB configuration struct (non-secure address space) */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ + #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ + #endif + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* Special LR values for Secure/Non-Secure call handling and exception handling */ + +/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ +#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ + +/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ +#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ +#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ +#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ +#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ +#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ +#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */ +#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ + +/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ +#else +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ +#endif + + +/* Interrupt Priorities are WORD accessible only under Armv6-M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + +#define __NVIC_SetPriorityGrouping(X) (void)(X) +#define __NVIC_GetPriorityGrouping() (0U) + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + If VTOR is not present address 0 must be mapped to SRAM. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t *vectors = (uint32_t *)SCB->VTOR; +#else + uint32_t *vectors = (uint32_t *)0x0U; +#endif + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + __DSB(); +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t *vectors = (uint32_t *)SCB->VTOR; +#else + uint32_t *vectors = (uint32_t *)0x0U; +#endif + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC_NS->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB_NS->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB_NS->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB_NS->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv8.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + + +/* ################################## Debug Control function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DCBFunctions Debug Control Functions + \brief Functions that access the Debug Control Block. + @{ + */ + + +/** + \brief Set Debug Authentication Control Register + \details writes to Debug Authentication Control register. + \param [in] value value to be writen. + */ +__STATIC_INLINE void DCB_SetAuthCtrl(uint32_t value) +{ + __DSB(); + __ISB(); + DCB->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register + \details Reads Debug Authentication Control register. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t DCB_GetAuthCtrl(void) +{ + return (DCB->DAUTHCTRL); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Debug Authentication Control Register (non-secure) + \details writes to non-secure Debug Authentication Control register when in secure state. + \param [in] value value to be writen + */ +__STATIC_INLINE void TZ_DCB_SetAuthCtrl_NS(uint32_t value) +{ + __DSB(); + __ISB(); + DCB_NS->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register (non-secure) + \details Reads non-secure Debug Authentication Control register when in secure state. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t TZ_DCB_GetAuthCtrl_NS(void) +{ + return (DCB_NS->DAUTHCTRL); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## Debug Identification function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DIBFunctions Debug Identification Functions + \brief Functions that access the Debug Identification Block. + @{ + */ + + +/** + \brief Get Debug Authentication Status Register + \details Reads Debug Authentication Status register. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t DIB_GetAuthStatus(void) +{ + return (DIB->DAUTHSTATUS); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Debug Authentication Status Register (non-secure) + \details Reads non-secure Debug Authentication Status register when in secure state. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t TZ_DIB_GetAuthStatus_NS(void) +{ + return (DIB_NS->DAUTHSTATUS); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_ARMV8MBL_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/CMSIS/Core/Include/core_armv8mml.h b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/CMSIS/Core/Include/core_armv8mml.h new file mode 100644 index 0000000000..c119fbf242 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/CMSIS/Core/Include/core_armv8mml.h @@ -0,0 +1,3209 @@ +/**************************************************************************//** + * @file core_armv8mml.h + * @brief CMSIS Armv8-M Mainline Core Peripheral Access Layer Header File + * @version V5.2.3 + * @date 13. October 2021 + ******************************************************************************/ +/* + * Copyright (c) 2009-2021 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#elif defined ( __GNUC__ ) + #pragma GCC diagnostic ignored "-Wpedantic" /* disable pedantic warning due to unnamed structs/unions */ +#endif + +#ifndef __CORE_ARMV8MML_H_GENERIC +#define __CORE_ARMV8MML_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_ARMv8MML + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS Armv8MML definitions */ +#define __ARMv8MML_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __ARMv8MML_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __ARMv8MML_CMSIS_VERSION ((__ARMv8MML_CMSIS_VERSION_MAIN << 16U) | \ + __ARMv8MML_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (80U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_ARMV8MML_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_ARMV8MML_H_DEPENDANT +#define __CORE_ARMV8MML_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __ARMv8MML_REV + #define __ARMv8MML_REV 0x0000U + #warning "__ARMv8MML_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DSP_PRESENT + #define __DSP_PRESENT 0U + #warning "__DSP_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 1U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group ARMv8MML */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core SAU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ +#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */ + uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */ + uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */ +#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */ + +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED6[580U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ + __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ + __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ + __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */ + uint32_t RESERVED7[21U]; + __IOM uint32_t SFSR; /*!< Offset: 0x0E4 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x0E8 (R/W) Secure Fault Address Register */ + uint32_t RESERVED3[69U]; + __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ + uint32_t RESERVED4[15U]; + __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ + uint32_t RESERVED5[1U]; + __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ + uint32_t RESERVED6[1U]; + __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ + __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ + __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ + __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ + __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ + __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ + __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ + __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ + __OM uint32_t BPIALL; /*!< Offset: 0x278 ( /W) Branch Predictor Invalidate All */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ +#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */ +#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */ +#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */ + +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */ +#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_CFSR_MEMFAULTSR_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */ +#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/* SCB Non-Secure Access Control Register Definitions */ +#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */ +#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */ + +#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */ +#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */ + +#define SCB_NSACR_CPn_Pos 0U /*!< SCB NSACR: CPn Position */ +#define SCB_NSACR_CPn_Msk (1UL /*<< SCB_NSACR_CPn_Pos*/) /*!< SCB NSACR: CPn Mask */ + +/* SCB Cache Level ID Register Definitions */ +#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ +#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ + +#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ +#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ + +/* SCB Cache Type Register Definitions */ +#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ +#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ + +#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ +#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ + +#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ +#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ + +#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ +#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ + +#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ +#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ + +/* SCB Cache Size ID Register Definitions */ +#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ +#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ + +#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ +#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ + +#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ +#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ + +#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ +#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ + +#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ +#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ + +#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ +#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ + +#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ +#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ + +/* SCB Cache Size Selection Register Definitions */ +#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ +#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ + +#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ +#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ + +/* SCB Software Triggered Interrupt Register Definitions */ +#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ +#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ + +/* SCB D-Cache Invalidate by Set-way Register Definitions */ +#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ +#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ + +#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ +#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ + +/* SCB D-Cache Clean by Set-way Register Definitions */ +#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ +#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ + +#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ +#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ + +/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ +#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ +#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ + +#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ +#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ + __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */ + uint32_t RESERVED6[4U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Stimulus Port Register Definitions */ +#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */ +#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */ + +#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */ +#define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */ + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */ +#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */ + +#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */ +#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED14[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED15[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED16[1U]; + __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ + uint32_t RESERVED17[1U]; + __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ + uint32_t RESERVED18[1U]; + __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ + uint32_t RESERVED19[1U]; + __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ + uint32_t RESERVED20[1U]; + __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ + uint32_t RESERVED21[1U]; + __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ + uint32_t RESERVED22[1U]; + __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ + uint32_t RESERVED23[1U]; + __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ + uint32_t RESERVED24[1U]; + __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ + uint32_t RESERVED25[1U]; + __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ + uint32_t RESERVED26[1U]; + __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ + uint32_t RESERVED27[1U]; + __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ + uint32_t RESERVED28[1U]; + __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ + uint32_t RESERVED29[1U]; + __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ + uint32_t RESERVED30[1U]; + __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ + uint32_t RESERVED31[1U]; + __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ + uint32_t RESERVED32[934U]; + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ + uint32_t RESERVED33[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */ +#define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Sizes Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Sizes Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ + uint32_t RESERVED3[809U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) Software Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) Software Lock Status Register */ + uint32_t RESERVED4[4U]; + __IM uint32_t TYPE; /*!< Offset: 0xFC8 (R/ ) Device Identifier Register */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Register */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_SWOSCALER_Pos 0U /*!< TPI ACPR: SWOSCALER Position */ +#define TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/) /*!< TPI ACPR: SWOSCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ +#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI Periodic Synchronization Control Register Definitions */ +#define TPI_PSCR_PSCount_Pos 0U /*!< TPI PSCR: PSCount Position */ +#define TPI_PSCR_PSCount_Msk (0x1FUL /*<< TPI_PSCR_PSCount_Pos*/) /*!< TPI PSCR: TPSCount Mask */ + +/* TPI Software Lock Status Register Definitions */ +#define TPI_LSR_nTT_Pos 1U /*!< TPI LSR: Not thirty-two bit. Position */ +#define TPI_LSR_nTT_Msk (0x1UL << TPI_LSR_nTT_Pos) /*!< TPI LSR: Not thirty-two bit. Mask */ + +#define TPI_LSR_SLK_Pos 1U /*!< TPI LSR: Software Lock status Position */ +#define TPI_LSR_SLK_Msk (0x1UL << TPI_LSR_SLK_Pos) /*!< TPI LSR: Software Lock status Mask */ + +#define TPI_LSR_SLI_Pos 0U /*!< TPI LSR: Software Lock implemented Position */ +#define TPI_LSR_SLI_Msk (0x1UL /*<< TPI_LSR_SLI_Pos*/) /*!< TPI LSR: Software Lock implemented Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFO depth Position */ +#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFO depth Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */ + __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */ + __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */ + __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */ + uint32_t RESERVED0[1]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ +#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/* MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */ + +/* MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/* MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#else + uint32_t RESERVED0[3]; +#endif + __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */ +} SAU_Type; + +/* SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/* SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/* SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/* SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/* SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/* Secure Fault Status Register Definitions */ +#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */ +#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */ + +#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */ +#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */ + +#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */ +#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */ + +#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */ +#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */ + +#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */ +#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */ + +#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */ +#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */ + +#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */ +#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */ + +#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */ +#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and VFP Feature Register 2 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */ +#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */ + +#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */ +#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */ + +#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */ +#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */ + +#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */ +#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */ + +#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */ +#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */ + +#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */ +#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */ +#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */ +#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and VFP Feature Register 0 Definitions */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and VFP Feature Register 1 Definitions */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/* Media and VFP Feature Register 2 Definitions */ +#define FPU_MVFR2_FPMisc_Pos 4U /*!< MVFR2: FPMisc bits Position */ +#define FPU_MVFR2_FPMisc_Msk (0xFUL << FPU_MVFR2_FPMisc_Pos) /*!< MVFR2: FPMisc bits Mask */ + +/*@} end of group CMSIS_FPU */ + +/* CoreDebug is deprecated. replaced by DCB (Debug Control Block) */ +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief \deprecated Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED0[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< \deprecated CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< \deprecated CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Position */ +#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< \deprecated CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< \deprecated CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< \deprecated CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< \deprecated CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< \deprecated CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< \deprecated CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< \deprecated CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< \deprecated CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< \deprecated CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< \deprecated CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< \deprecated CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< \deprecated CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< \deprecated CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< \deprecated CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< \deprecated CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< \deprecated CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< \deprecated CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< \deprecated CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< \deprecated CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< \deprecated CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< \deprecated CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< \deprecated CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< \deprecated CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< \deprecated CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< \deprecated CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< \deprecated CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< \deprecated CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< \deprecated CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< \deprecated CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< \deprecated CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Mask */ + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Position */ +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Mask */ + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Mask */ + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos 16U /*!< \deprecated CoreDebug DSCSR: CDS Position */ +#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< \deprecated CoreDebug DSCSR: CDS Mask */ + +#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< \deprecated CoreDebug DSCSR: SBRSEL Position */ +#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< \deprecated CoreDebug DSCSR: SBRSEL Mask */ + +#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< \deprecated CoreDebug DSCSR: SBRSELEN Position */ +#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< \deprecated CoreDebug DSCSR: SBRSELEN Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DCB Debug Control Block + \brief Type definitions for the Debug Control Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Control Block Registers (DCB). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED0[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} DCB_Type; + +/* DHCSR, Debug Halting Control and Status Register Definitions */ +#define DCB_DHCSR_DBGKEY_Pos 16U /*!< DCB DHCSR: Debug key Position */ +#define DCB_DHCSR_DBGKEY_Msk (0xFFFFUL << DCB_DHCSR_DBGKEY_Pos) /*!< DCB DHCSR: Debug key Mask */ + +#define DCB_DHCSR_S_RESTART_ST_Pos 26U /*!< DCB DHCSR: Restart sticky status Position */ +#define DCB_DHCSR_S_RESTART_ST_Msk (0x1UL << DCB_DHCSR_S_RESTART_ST_Pos) /*!< DCB DHCSR: Restart sticky status Mask */ + +#define DCB_DHCSR_S_RESET_ST_Pos 25U /*!< DCB DHCSR: Reset sticky status Position */ +#define DCB_DHCSR_S_RESET_ST_Msk (0x1UL << DCB_DHCSR_S_RESET_ST_Pos) /*!< DCB DHCSR: Reset sticky status Mask */ + +#define DCB_DHCSR_S_RETIRE_ST_Pos 24U /*!< DCB DHCSR: Retire sticky status Position */ +#define DCB_DHCSR_S_RETIRE_ST_Msk (0x1UL << DCB_DHCSR_S_RETIRE_ST_Pos) /*!< DCB DHCSR: Retire sticky status Mask */ + +#define DCB_DHCSR_S_SDE_Pos 20U /*!< DCB DHCSR: Secure debug enabled Position */ +#define DCB_DHCSR_S_SDE_Msk (0x1UL << DCB_DHCSR_S_SDE_Pos) /*!< DCB DHCSR: Secure debug enabled Mask */ + +#define DCB_DHCSR_S_LOCKUP_Pos 19U /*!< DCB DHCSR: Lockup status Position */ +#define DCB_DHCSR_S_LOCKUP_Msk (0x1UL << DCB_DHCSR_S_LOCKUP_Pos) /*!< DCB DHCSR: Lockup status Mask */ + +#define DCB_DHCSR_S_SLEEP_Pos 18U /*!< DCB DHCSR: Sleeping status Position */ +#define DCB_DHCSR_S_SLEEP_Msk (0x1UL << DCB_DHCSR_S_SLEEP_Pos) /*!< DCB DHCSR: Sleeping status Mask */ + +#define DCB_DHCSR_S_HALT_Pos 17U /*!< DCB DHCSR: Halted status Position */ +#define DCB_DHCSR_S_HALT_Msk (0x1UL << DCB_DHCSR_S_HALT_Pos) /*!< DCB DHCSR: Halted status Mask */ + +#define DCB_DHCSR_S_REGRDY_Pos 16U /*!< DCB DHCSR: Register ready status Position */ +#define DCB_DHCSR_S_REGRDY_Msk (0x1UL << DCB_DHCSR_S_REGRDY_Pos) /*!< DCB DHCSR: Register ready status Mask */ + +#define DCB_DHCSR_C_SNAPSTALL_Pos 5U /*!< DCB DHCSR: Snap stall control Position */ +#define DCB_DHCSR_C_SNAPSTALL_Msk (0x1UL << DCB_DHCSR_C_SNAPSTALL_Pos) /*!< DCB DHCSR: Snap stall control Mask */ + +#define DCB_DHCSR_C_MASKINTS_Pos 3U /*!< DCB DHCSR: Mask interrupts control Position */ +#define DCB_DHCSR_C_MASKINTS_Msk (0x1UL << DCB_DHCSR_C_MASKINTS_Pos) /*!< DCB DHCSR: Mask interrupts control Mask */ + +#define DCB_DHCSR_C_STEP_Pos 2U /*!< DCB DHCSR: Step control Position */ +#define DCB_DHCSR_C_STEP_Msk (0x1UL << DCB_DHCSR_C_STEP_Pos) /*!< DCB DHCSR: Step control Mask */ + +#define DCB_DHCSR_C_HALT_Pos 1U /*!< DCB DHCSR: Halt control Position */ +#define DCB_DHCSR_C_HALT_Msk (0x1UL << DCB_DHCSR_C_HALT_Pos) /*!< DCB DHCSR: Halt control Mask */ + +#define DCB_DHCSR_C_DEBUGEN_Pos 0U /*!< DCB DHCSR: Debug enable control Position */ +#define DCB_DHCSR_C_DEBUGEN_Msk (0x1UL /*<< DCB_DHCSR_C_DEBUGEN_Pos*/) /*!< DCB DHCSR: Debug enable control Mask */ + +/* DCRSR, Debug Core Register Select Register Definitions */ +#define DCB_DCRSR_REGWnR_Pos 16U /*!< DCB DCRSR: Register write/not-read Position */ +#define DCB_DCRSR_REGWnR_Msk (0x1UL << DCB_DCRSR_REGWnR_Pos) /*!< DCB DCRSR: Register write/not-read Mask */ + +#define DCB_DCRSR_REGSEL_Pos 0U /*!< DCB DCRSR: Register selector Position */ +#define DCB_DCRSR_REGSEL_Msk (0x7FUL /*<< DCB_DCRSR_REGSEL_Pos*/) /*!< DCB DCRSR: Register selector Mask */ + +/* DCRDR, Debug Core Register Data Register Definitions */ +#define DCB_DCRDR_DBGTMP_Pos 0U /*!< DCB DCRDR: Data temporary buffer Position */ +#define DCB_DCRDR_DBGTMP_Msk (0xFFFFFFFFUL /*<< DCB_DCRDR_DBGTMP_Pos*/) /*!< DCB DCRDR: Data temporary buffer Mask */ + +/* DEMCR, Debug Exception and Monitor Control Register Definitions */ +#define DCB_DEMCR_TRCENA_Pos 24U /*!< DCB DEMCR: Trace enable Position */ +#define DCB_DEMCR_TRCENA_Msk (0x1UL << DCB_DEMCR_TRCENA_Pos) /*!< DCB DEMCR: Trace enable Mask */ + +#define DCB_DEMCR_MONPRKEY_Pos 23U /*!< DCB DEMCR: Monitor pend req key Position */ +#define DCB_DEMCR_MONPRKEY_Msk (0x1UL << DCB_DEMCR_MONPRKEY_Pos) /*!< DCB DEMCR: Monitor pend req key Mask */ + +#define DCB_DEMCR_UMON_EN_Pos 21U /*!< DCB DEMCR: Unprivileged monitor enable Position */ +#define DCB_DEMCR_UMON_EN_Msk (0x1UL << DCB_DEMCR_UMON_EN_Pos) /*!< DCB DEMCR: Unprivileged monitor enable Mask */ + +#define DCB_DEMCR_SDME_Pos 20U /*!< DCB DEMCR: Secure DebugMonitor enable Position */ +#define DCB_DEMCR_SDME_Msk (0x1UL << DCB_DEMCR_SDME_Pos) /*!< DCB DEMCR: Secure DebugMonitor enable Mask */ + +#define DCB_DEMCR_MON_REQ_Pos 19U /*!< DCB DEMCR: Monitor request Position */ +#define DCB_DEMCR_MON_REQ_Msk (0x1UL << DCB_DEMCR_MON_REQ_Pos) /*!< DCB DEMCR: Monitor request Mask */ + +#define DCB_DEMCR_MON_STEP_Pos 18U /*!< DCB DEMCR: Monitor step Position */ +#define DCB_DEMCR_MON_STEP_Msk (0x1UL << DCB_DEMCR_MON_STEP_Pos) /*!< DCB DEMCR: Monitor step Mask */ + +#define DCB_DEMCR_MON_PEND_Pos 17U /*!< DCB DEMCR: Monitor pend Position */ +#define DCB_DEMCR_MON_PEND_Msk (0x1UL << DCB_DEMCR_MON_PEND_Pos) /*!< DCB DEMCR: Monitor pend Mask */ + +#define DCB_DEMCR_MON_EN_Pos 16U /*!< DCB DEMCR: Monitor enable Position */ +#define DCB_DEMCR_MON_EN_Msk (0x1UL << DCB_DEMCR_MON_EN_Pos) /*!< DCB DEMCR: Monitor enable Mask */ + +#define DCB_DEMCR_VC_SFERR_Pos 11U /*!< DCB DEMCR: Vector Catch SecureFault Position */ +#define DCB_DEMCR_VC_SFERR_Msk (0x1UL << DCB_DEMCR_VC_SFERR_Pos) /*!< DCB DEMCR: Vector Catch SecureFault Mask */ + +#define DCB_DEMCR_VC_HARDERR_Pos 10U /*!< DCB DEMCR: Vector Catch HardFault errors Position */ +#define DCB_DEMCR_VC_HARDERR_Msk (0x1UL << DCB_DEMCR_VC_HARDERR_Pos) /*!< DCB DEMCR: Vector Catch HardFault errors Mask */ + +#define DCB_DEMCR_VC_INTERR_Pos 9U /*!< DCB DEMCR: Vector Catch interrupt errors Position */ +#define DCB_DEMCR_VC_INTERR_Msk (0x1UL << DCB_DEMCR_VC_INTERR_Pos) /*!< DCB DEMCR: Vector Catch interrupt errors Mask */ + +#define DCB_DEMCR_VC_BUSERR_Pos 8U /*!< DCB DEMCR: Vector Catch BusFault errors Position */ +#define DCB_DEMCR_VC_BUSERR_Msk (0x1UL << DCB_DEMCR_VC_BUSERR_Pos) /*!< DCB DEMCR: Vector Catch BusFault errors Mask */ + +#define DCB_DEMCR_VC_STATERR_Pos 7U /*!< DCB DEMCR: Vector Catch state errors Position */ +#define DCB_DEMCR_VC_STATERR_Msk (0x1UL << DCB_DEMCR_VC_STATERR_Pos) /*!< DCB DEMCR: Vector Catch state errors Mask */ + +#define DCB_DEMCR_VC_CHKERR_Pos 6U /*!< DCB DEMCR: Vector Catch check errors Position */ +#define DCB_DEMCR_VC_CHKERR_Msk (0x1UL << DCB_DEMCR_VC_CHKERR_Pos) /*!< DCB DEMCR: Vector Catch check errors Mask */ + +#define DCB_DEMCR_VC_NOCPERR_Pos 5U /*!< DCB DEMCR: Vector Catch NOCP errors Position */ +#define DCB_DEMCR_VC_NOCPERR_Msk (0x1UL << DCB_DEMCR_VC_NOCPERR_Pos) /*!< DCB DEMCR: Vector Catch NOCP errors Mask */ + +#define DCB_DEMCR_VC_MMERR_Pos 4U /*!< DCB DEMCR: Vector Catch MemManage errors Position */ +#define DCB_DEMCR_VC_MMERR_Msk (0x1UL << DCB_DEMCR_VC_MMERR_Pos) /*!< DCB DEMCR: Vector Catch MemManage errors Mask */ + +#define DCB_DEMCR_VC_CORERESET_Pos 0U /*!< DCB DEMCR: Vector Catch Core reset Position */ +#define DCB_DEMCR_VC_CORERESET_Msk (0x1UL /*<< DCB_DEMCR_VC_CORERESET_Pos*/) /*!< DCB DEMCR: Vector Catch Core reset Mask */ + +/* DAUTHCTRL, Debug Authentication Control Register Definitions */ +#define DCB_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPNIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPNIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPNIDENSEL_Msk (0x1UL << DCB_DAUTHCTRL_SPNIDENSEL_Pos) /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Mask */ + +#define DCB_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< DCB DAUTHCTRL: Secure invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPIDENSEL_Msk (0x1UL /*<< DCB_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< DCB DAUTHCTRL: Secure invasive debug enable select Mask */ + +/* DSCSR, Debug Security Control and Status Register Definitions */ +#define DCB_DSCSR_CDSKEY_Pos 17U /*!< DCB DSCSR: CDS write-enable key Position */ +#define DCB_DSCSR_CDSKEY_Msk (0x1UL << DCB_DSCSR_CDSKEY_Pos) /*!< DCB DSCSR: CDS write-enable key Mask */ + +#define DCB_DSCSR_CDS_Pos 16U /*!< DCB DSCSR: Current domain Secure Position */ +#define DCB_DSCSR_CDS_Msk (0x1UL << DCB_DSCSR_CDS_Pos) /*!< DCB DSCSR: Current domain Secure Mask */ + +#define DCB_DSCSR_SBRSEL_Pos 1U /*!< DCB DSCSR: Secure banked register select Position */ +#define DCB_DSCSR_SBRSEL_Msk (0x1UL << DCB_DSCSR_SBRSEL_Pos) /*!< DCB DSCSR: Secure banked register select Mask */ + +#define DCB_DSCSR_SBRSELEN_Pos 0U /*!< DCB DSCSR: Secure banked register select enable Position */ +#define DCB_DSCSR_SBRSELEN_Msk (0x1UL /*<< DCB_DSCSR_SBRSELEN_Pos*/) /*!< DCB DSCSR: Secure banked register select enable Mask */ + +/*@} end of group CMSIS_DCB */ + + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DIB Debug Identification Block + \brief Type definitions for the Debug Identification Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Identification Block Registers (DIB). + */ +typedef struct +{ + __OM uint32_t DLAR; /*!< Offset: 0x000 ( /W) SCS Software Lock Access Register */ + __IM uint32_t DLSR; /*!< Offset: 0x004 (R/ ) SCS Software Lock Status Register */ + __IM uint32_t DAUTHSTATUS; /*!< Offset: 0x008 (R/ ) Debug Authentication Status Register */ + __IM uint32_t DDEVARCH; /*!< Offset: 0x00C (R/ ) SCS Device Architecture Register */ + __IM uint32_t DDEVTYPE; /*!< Offset: 0x010 (R/ ) SCS Device Type Register */ +} DIB_Type; + +/* DLAR, SCS Software Lock Access Register Definitions */ +#define DIB_DLAR_KEY_Pos 0U /*!< DIB DLAR: KEY Position */ +#define DIB_DLAR_KEY_Msk (0xFFFFFFFFUL /*<< DIB_DLAR_KEY_Pos */) /*!< DIB DLAR: KEY Mask */ + +/* DLSR, SCS Software Lock Status Register Definitions */ +#define DIB_DLSR_nTT_Pos 2U /*!< DIB DLSR: Not thirty-two bit Position */ +#define DIB_DLSR_nTT_Msk (0x1UL << DIB_DLSR_nTT_Pos ) /*!< DIB DLSR: Not thirty-two bit Mask */ + +#define DIB_DLSR_SLK_Pos 1U /*!< DIB DLSR: Software Lock status Position */ +#define DIB_DLSR_SLK_Msk (0x1UL << DIB_DLSR_SLK_Pos ) /*!< DIB DLSR: Software Lock status Mask */ + +#define DIB_DLSR_SLI_Pos 0U /*!< DIB DLSR: Software Lock implemented Position */ +#define DIB_DLSR_SLI_Msk (0x1UL /*<< DIB_DLSR_SLI_Pos*/) /*!< DIB DLSR: Software Lock implemented Mask */ + +/* DAUTHSTATUS, Debug Authentication Status Register Definitions */ +#define DIB_DAUTHSTATUS_SNID_Pos 6U /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_SNID_Msk (0x3UL << DIB_DAUTHSTATUS_SNID_Pos ) /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_SID_Pos 4U /*!< DIB DAUTHSTATUS: Secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_SID_Msk (0x3UL << DIB_DAUTHSTATUS_SID_Pos ) /*!< DIB DAUTHSTATUS: Secure Invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSNID_Pos 2U /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSNID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSID_Pos 0U /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSID_Msk (0x3UL /*<< DIB_DAUTHSTATUS_NSID_Pos*/) /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Mask */ + +/* DDEVARCH, SCS Device Architecture Register Definitions */ +#define DIB_DDEVARCH_ARCHITECT_Pos 21U /*!< DIB DDEVARCH: Architect Position */ +#define DIB_DDEVARCH_ARCHITECT_Msk (0x7FFUL << DIB_DDEVARCH_ARCHITECT_Pos ) /*!< DIB DDEVARCH: Architect Mask */ + +#define DIB_DDEVARCH_PRESENT_Pos 20U /*!< DIB DDEVARCH: DEVARCH Present Position */ +#define DIB_DDEVARCH_PRESENT_Msk (0x1FUL << DIB_DDEVARCH_PRESENT_Pos ) /*!< DIB DDEVARCH: DEVARCH Present Mask */ + +#define DIB_DDEVARCH_REVISION_Pos 16U /*!< DIB DDEVARCH: Revision Position */ +#define DIB_DDEVARCH_REVISION_Msk (0xFUL << DIB_DDEVARCH_REVISION_Pos ) /*!< DIB DDEVARCH: Revision Mask */ + +#define DIB_DDEVARCH_ARCHVER_Pos 12U /*!< DIB DDEVARCH: Architecture Version Position */ +#define DIB_DDEVARCH_ARCHVER_Msk (0xFUL << DIB_DDEVARCH_ARCHVER_Pos ) /*!< DIB DDEVARCH: Architecture Version Mask */ + +#define DIB_DDEVARCH_ARCHPART_Pos 0U /*!< DIB DDEVARCH: Architecture Part Position */ +#define DIB_DDEVARCH_ARCHPART_Msk (0xFFFUL /*<< DIB_DDEVARCH_ARCHPART_Pos*/) /*!< DIB DDEVARCH: Architecture Part Mask */ + +/* DDEVTYPE, SCS Device Type Register Definitions */ +#define DIB_DDEVTYPE_SUB_Pos 4U /*!< DIB DDEVTYPE: Sub-type Position */ +#define DIB_DDEVTYPE_SUB_Msk (0xFUL << DIB_DDEVTYPE_SUB_Pos ) /*!< DIB DDEVTYPE: Sub-type Mask */ + +#define DIB_DDEVTYPE_MAJOR_Pos 0U /*!< DIB DDEVTYPE: Major type Position */ +#define DIB_DDEVTYPE_MAJOR_Msk (0xFUL /*<< DIB_DDEVTYPE_MAJOR_Pos*/) /*!< DIB DDEVTYPE: Major type Mask */ + + +/*@} end of group CMSIS_DIB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ + #define CoreDebug_BASE (0xE000EDF0UL) /*!< \deprecated Core Debug Base Address */ + #define DCB_BASE (0xE000EDF0UL) /*!< DCB Base Address */ + #define DIB_BASE (0xE000EFB0UL) /*!< DIB Base Address */ + #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ + #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ + #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ + #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ + #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ + #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ + #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< \deprecated Core Debug configuration struct */ + #define DCB ((DCB_Type *) DCB_BASE ) /*!< DCB configuration struct */ + #define DIB ((DIB_Type *) DIB_BASE ) /*!< DIB configuration struct */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ + #endif + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ + #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ + #endif + + #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ + #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ + #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< \deprecated Core Debug Base Address (non-secure address space) */ + #define DCB_BASE_NS (0xE002EDF0UL) /*!< DCB Base Address (non-secure address space) */ + #define DIB_BASE_NS (0xE002EFB0UL) /*!< DIB Base Address (non-secure address space) */ + #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ + #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ + #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + + #define SCnSCB_NS ((SCnSCB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */ + #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ + #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ + #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ + #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< \deprecated Core Debug configuration struct (non-secure address space) */ + #define DCB_NS ((DCB_Type *) DCB_BASE_NS ) /*!< DCB configuration struct (non-secure address space) */ + #define DIB_NS ((DIB_Type *) DIB_BASE_NS ) /*!< DIB configuration struct (non-secure address space) */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ + #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ + #endif + + #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */ + #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */ + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_register_aliases Backwards Compatibility Aliases + \brief Register alias definitions for backwards compatibility. + @{ + */ +#define ID_ADR (ID_AFR) /*!< SCB Auxiliary Feature Register */ +/*@} */ + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* Special LR values for Secure/Non-Secure call handling and exception handling */ + +/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ +#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ + +/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ +#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ +#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ +#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ +#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ +#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ +#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */ +#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ + +/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ +#else +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ +#endif + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + __DSB(); +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Priority Grouping (non-secure) + \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB_NS->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB_NS->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping (non-secure) + \details Reads the priority grouping field from the non-secure NVIC when in secure state. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void) +{ + return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv8.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = FPU->MVFR0; + if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U) + { + return 2U; /* Double + Single precision FPU */ + } + else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + +/* ########################## Cache functions #################################### */ + +#if ((defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)) || \ + (defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U))) +#include "cachel1_armv7.h" +#endif + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + + +/* ################################## Debug Control function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DCBFunctions Debug Control Functions + \brief Functions that access the Debug Control Block. + @{ + */ + + +/** + \brief Set Debug Authentication Control Register + \details writes to Debug Authentication Control register. + \param [in] value value to be writen. + */ +__STATIC_INLINE void DCB_SetAuthCtrl(uint32_t value) +{ + __DSB(); + __ISB(); + DCB->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register + \details Reads Debug Authentication Control register. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t DCB_GetAuthCtrl(void) +{ + return (DCB->DAUTHCTRL); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Debug Authentication Control Register (non-secure) + \details writes to non-secure Debug Authentication Control register when in secure state. + \param [in] value value to be writen + */ +__STATIC_INLINE void TZ_DCB_SetAuthCtrl_NS(uint32_t value) +{ + __DSB(); + __ISB(); + DCB_NS->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register (non-secure) + \details Reads non-secure Debug Authentication Control register when in secure state. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t TZ_DCB_GetAuthCtrl_NS(void) +{ + return (DCB_NS->DAUTHCTRL); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## Debug Identification function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DIBFunctions Debug Identification Functions + \brief Functions that access the Debug Identification Block. + @{ + */ + + +/** + \brief Get Debug Authentication Status Register + \details Reads Debug Authentication Status register. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t DIB_GetAuthStatus(void) +{ + return (DIB->DAUTHSTATUS); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Debug Authentication Status Register (non-secure) + \details Reads non-secure Debug Authentication Status register when in secure state. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t TZ_DIB_GetAuthStatus_NS(void) +{ + return (DIB_NS->DAUTHSTATUS); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_ARMV8MML_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/CMSIS/Core/Include/core_cm0.h b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/CMSIS/Core/Include/core_cm0.h new file mode 100644 index 0000000000..0a0ba223e1 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/CMSIS/Core/Include/core_cm0.h @@ -0,0 +1,952 @@ +/**************************************************************************//** + * @file core_cm0.h + * @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File + * @version V5.0.8 + * @date 21. August 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM0_H_GENERIC +#define __CORE_CM0_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M0 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM0 definitions */ +#define __CM0_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM0_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16U) | \ + __CM0_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (0U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM0_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM0_H_DEPENDANT +#define __CORE_CM0_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM0_REV + #define __CM0_REV 0x0000U + #warning "__CM0_REV not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M0 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t _reserved0:1; /*!< bit: 0 Reserved */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[31U]; + __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RESERVED1[31U]; + __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[31U]; + __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[31U]; + uint32_t RESERVED4[64U]; + __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + uint32_t RESERVED0; + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. + Therefore they are not covered by the Cortex-M0 header file. + @{ + */ +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ +/*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M0 */ + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ + + +/* Interrupt Priorities are WORD accessible only under Armv6-M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + +#define __NVIC_SetPriorityGrouping(X) (void)(X) +#define __NVIC_GetPriorityGrouping() (0U) + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + Address 0 must be mapped to SRAM. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)(NVIC_USER_IRQ_OFFSET << 2); /* point to 1st user interrupt */ + *(vectors + (int32_t)IRQn) = vector; /* use pointer arithmetic to access vector */ + /* ARM Application Note 321 states that the M0 does not require the architectural barrier */ +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)(NVIC_USER_IRQ_OFFSET << 2); /* point to 1st user interrupt */ + return *(vectors + (int32_t)IRQn); /* use pointer arithmetic to access vector */ +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM0_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/CMSIS/Core/Include/core_cm0plus.h b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/CMSIS/Core/Include/core_cm0plus.h new file mode 100644 index 0000000000..879a384124 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/CMSIS/Core/Include/core_cm0plus.h @@ -0,0 +1,1087 @@ +/**************************************************************************//** + * @file core_cm0plus.h + * @brief CMSIS Cortex-M0+ Core Peripheral Access Layer Header File + * @version V5.0.9 + * @date 21. August 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM0PLUS_H_GENERIC +#define __CORE_CM0PLUS_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex-M0+ + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM0+ definitions */ +#define __CM0PLUS_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM0PLUS_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM0PLUS_CMSIS_VERSION ((__CM0PLUS_CMSIS_VERSION_MAIN << 16U) | \ + __CM0PLUS_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (0U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM0PLUS_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM0PLUS_H_DEPENDANT +#define __CORE_CM0PLUS_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM0PLUS_REV + #define __CM0PLUS_REV 0x0000U + #warning "__CM0PLUS_REV not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 0U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex-M0+ */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core MPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[31U]; + __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RESERVED1[31U]; + __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[31U]; + __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[31U]; + uint32_t RESERVED4[64U]; + __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ +#else + uint32_t RESERVED0; +#endif + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) +/* SCB Interrupt Control State Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 8U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#endif + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ +} MPU_Type; + +#define MPU_TYPE_RALIASES 1U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 8U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. + Therefore they are not covered by the Cortex-M0+ header file. + @{ + */ +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ +/*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M0+ */ + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ + + +/* Interrupt Priorities are WORD accessible only under Armv6-M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + +#define __NVIC_SetPriorityGrouping(X) (void)(X) +#define __NVIC_GetPriorityGrouping() (0U) + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + If VTOR is not present address 0 must be mapped to SRAM. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; +#else + uint32_t *vectors = (uint32_t *)(NVIC_USER_IRQ_OFFSET << 2); /* point to 1st user interrupt */ + *(vectors + (int32_t)IRQn) = vector; /* use pointer arithmetic to access vector */ +#endif + /* ARM Application Note 321 states that the M0+ does not require the architectural barrier */ +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +#else + uint32_t *vectors = (uint32_t *)(NVIC_USER_IRQ_OFFSET << 2); /* point to 1st user interrupt */ + return *(vectors + (int32_t)IRQn); /* use pointer arithmetic to access vector */ +#endif +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv7.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM0PLUS_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/CMSIS/Core/Include/core_cm1.h b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/CMSIS/Core/Include/core_cm1.h new file mode 100644 index 0000000000..83b8fc6a0d --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/CMSIS/Core/Include/core_cm1.h @@ -0,0 +1,979 @@ +/**************************************************************************//** + * @file core_cm1.h + * @brief CMSIS Cortex-M1 Core Peripheral Access Layer Header File + * @version V1.0.1 + * @date 12. November 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM1_H_GENERIC +#define __CORE_CM1_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M1 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM1 definitions */ +#define __CM1_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM1_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM1_CMSIS_VERSION ((__CM1_CMSIS_VERSION_MAIN << 16U) | \ + __CM1_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (1U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM1_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM1_H_DEPENDANT +#define __CORE_CM1_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM1_REV + #define __CM1_REV 0x0100U + #warning "__CM1_REV not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M1 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t _reserved0:1; /*!< bit: 0 Reserved */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[31U]; + __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[31U]; + __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[31U]; + __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[31U]; + uint32_t RESERVED4[64U]; + __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + uint32_t RESERVED0; + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_ITCMUAEN_Pos 4U /*!< ACTLR: Instruction TCM Upper Alias Enable Position */ +#define SCnSCB_ACTLR_ITCMUAEN_Msk (1UL << SCnSCB_ACTLR_ITCMUAEN_Pos) /*!< ACTLR: Instruction TCM Upper Alias Enable Mask */ + +#define SCnSCB_ACTLR_ITCMLAEN_Pos 3U /*!< ACTLR: Instruction TCM Lower Alias Enable Position */ +#define SCnSCB_ACTLR_ITCMLAEN_Msk (1UL << SCnSCB_ACTLR_ITCMLAEN_Pos) /*!< ACTLR: Instruction TCM Lower Alias Enable Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Cortex-M1 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. + Therefore they are not covered by the Cortex-M1 header file. + @{ + */ +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ +/*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M1 */ + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ + + +/* Interrupt Priorities are WORD accessible only under Armv6-M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + +#define __NVIC_SetPriorityGrouping(X) (void)(X) +#define __NVIC_GetPriorityGrouping() (0U) + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + Address 0 must be mapped to SRAM. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)0x0U; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + /* ARM Application Note 321 states that the M1 does not require the architectural barrier */ +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)0x0U; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM1_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/CMSIS/Core/Include/core_cm23.h b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/CMSIS/Core/Include/core_cm23.h new file mode 100644 index 0000000000..f2cf49fb16 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/CMSIS/Core/Include/core_cm23.h @@ -0,0 +1,2297 @@ +/**************************************************************************//** + * @file core_cm23.h + * @brief CMSIS Cortex-M23 Core Peripheral Access Layer Header File + * @version V5.1.0 + * @date 11. February 2020 + ******************************************************************************/ +/* + * Copyright (c) 2009-2020 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#elif defined ( __GNUC__ ) + #pragma GCC diagnostic ignored "-Wpedantic" /* disable pedantic warning due to unnamed structs/unions */ +#endif + +#ifndef __CORE_CM23_H_GENERIC +#define __CORE_CM23_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M23 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS definitions */ +#define __CM23_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM23_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM23_CMSIS_VERSION ((__CM23_CMSIS_VERSION_MAIN << 16U) | \ + __CM23_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (23U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM23_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM23_H_DEPENDANT +#define __CORE_CM23_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM23_REV + #define __CM23_REV 0x0000U + #warning "__CM23_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 0U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif + + #ifndef __ETM_PRESENT + #define __ETM_PRESENT 0U + #warning "__ETM_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MTB_PRESENT + #define __MTB_PRESENT 0U + #warning "__MTB_PRESENT not defined in device header file; using default!" + #endif + +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M23 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core SAU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint32_t IPR[124U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ +#else + uint32_t RESERVED0; +#endif + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IOM uint32_t SHPR[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ +#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#endif + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + uint32_t RESERVED0[6U]; + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED14[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED15[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED16[1U]; + __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ + uint32_t RESERVED17[1U]; + __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ + uint32_t RESERVED18[1U]; + __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ + uint32_t RESERVED19[1U]; + __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ + uint32_t RESERVED20[1U]; + __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ + uint32_t RESERVED21[1U]; + __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ + uint32_t RESERVED22[1U]; + __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ + uint32_t RESERVED23[1U]; + __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ + uint32_t RESERVED24[1U]; + __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ + uint32_t RESERVED25[1U]; + __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ + uint32_t RESERVED26[1U]; + __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ + uint32_t RESERVED27[1U]; + __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ + uint32_t RESERVED28[1U]; + __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ + uint32_t RESERVED29[1U]; + __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ + uint32_t RESERVED30[1U]; + __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ + uint32_t RESERVED31[1U]; + __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x3UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t ITFTTD0; /*!< Offset: 0xEEC (R/ ) Integration Test FIFO Test Data 0 Register */ + __IOM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/W) Integration Test ATB Control Register 2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) Integration Test ATB Control Register 0 */ + __IM uint32_t ITFTTD1; /*!< Offset: 0xEFC (R/ ) Integration Test FIFO Test Data 1 Register */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) Device Configuration Register */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Identifier Register */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ +#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration Test FIFO Test Data 0 Register Definitions */ +#define TPI_ITFTTD0_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD0: ATB Interface 2 ATVALIDPosition */ +#define TPI_ITFTTD0_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 2 ATVALID Mask */ + +#define TPI_ITFTTD0_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD0: ATB Interface 2 byte count Position */ +#define TPI_ITFTTD0_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 2 byte count Mask */ + +#define TPI_ITFTTD0_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Position */ +#define TPI_ITFTTD0_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Mask */ + +#define TPI_ITFTTD0_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD0: ATB Interface 1 byte count Position */ +#define TPI_ITFTTD0_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 1 byte countt Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data2_Pos 16U /*!< TPI ITFTTD0: ATB Interface 1 data2 Position */ +#define TPI_ITFTTD0_ATB_IF1_data2_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data2 Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data1_Pos 8U /*!< TPI ITFTTD0: ATB Interface 1 data1 Position */ +#define TPI_ITFTTD0_ATB_IF1_data1_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data1 Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data0_Pos 0U /*!< TPI ITFTTD0: ATB Interface 1 data0 Position */ +#define TPI_ITFTTD0_ATB_IF1_data0_Msk (0xFFUL /*<< TPI_ITFTTD0_ATB_IF1_data0_Pos*/) /*!< TPI ITFTTD0: ATB Interface 1 data0 Mask */ + +/* TPI Integration Test ATB Control Register 2 Register Definitions */ +#define TPI_ITATBCTR2_AFVALID2S_Pos 1U /*!< TPI ITATBCTR2: AFVALID2S Position */ +#define TPI_ITATBCTR2_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID2S_Pos) /*!< TPI ITATBCTR2: AFVALID2SS Mask */ + +#define TPI_ITATBCTR2_AFVALID1S_Pos 1U /*!< TPI ITATBCTR2: AFVALID1S Position */ +#define TPI_ITATBCTR2_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID1S_Pos) /*!< TPI ITATBCTR2: AFVALID1SS Mask */ + +#define TPI_ITATBCTR2_ATREADY2S_Pos 0U /*!< TPI ITATBCTR2: ATREADY2S Position */ +#define TPI_ITATBCTR2_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2S_Pos*/) /*!< TPI ITATBCTR2: ATREADY2S Mask */ + +#define TPI_ITATBCTR2_ATREADY1S_Pos 0U /*!< TPI ITATBCTR2: ATREADY1S Position */ +#define TPI_ITATBCTR2_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1S_Pos*/) /*!< TPI ITATBCTR2: ATREADY1S Mask */ + +/* TPI Integration Test FIFO Test Data 1 Register Definitions */ +#define TPI_ITFTTD1_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Position */ +#define TPI_ITFTTD1_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Mask */ + +#define TPI_ITFTTD1_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD1: ATB Interface 2 byte count Position */ +#define TPI_ITFTTD1_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 2 byte count Mask */ + +#define TPI_ITFTTD1_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Position */ +#define TPI_ITFTTD1_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Mask */ + +#define TPI_ITFTTD1_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD1: ATB Interface 1 byte count Position */ +#define TPI_ITFTTD1_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 1 byte countt Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data2_Pos 16U /*!< TPI ITFTTD1: ATB Interface 2 data2 Position */ +#define TPI_ITFTTD1_ATB_IF2_data2_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data2 Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data1_Pos 8U /*!< TPI ITFTTD1: ATB Interface 2 data1 Position */ +#define TPI_ITFTTD1_ATB_IF2_data1_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data1 Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data0_Pos 0U /*!< TPI ITFTTD1: ATB Interface 2 data0 Position */ +#define TPI_ITFTTD1_ATB_IF2_data0_Msk (0xFFUL /*<< TPI_ITFTTD1_ATB_IF2_data0_Pos*/) /*!< TPI ITFTTD1: ATB Interface 2 data0 Mask */ + +/* TPI Integration Test ATB Control Register 0 Definitions */ +#define TPI_ITATBCTR0_AFVALID2S_Pos 1U /*!< TPI ITATBCTR0: AFVALID2S Position */ +#define TPI_ITATBCTR0_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID2S_Pos) /*!< TPI ITATBCTR0: AFVALID2SS Mask */ + +#define TPI_ITATBCTR0_AFVALID1S_Pos 1U /*!< TPI ITATBCTR0: AFVALID1S Position */ +#define TPI_ITATBCTR0_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID1S_Pos) /*!< TPI ITATBCTR0: AFVALID1SS Mask */ + +#define TPI_ITATBCTR0_ATREADY2S_Pos 0U /*!< TPI ITATBCTR0: ATREADY2S Position */ +#define TPI_ITATBCTR0_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2S_Pos*/) /*!< TPI ITATBCTR0: ATREADY2S Mask */ + +#define TPI_ITATBCTR0_ATREADY1S_Pos 0U /*!< TPI ITATBCTR0: ATREADY1S Position */ +#define TPI_ITATBCTR0_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1S_Pos*/) /*!< TPI ITATBCTR0: ATREADY1S Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFOSZ Position */ +#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFOSZ Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x3FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + uint32_t RESERVED0[7U]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 1U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ +#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/* MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: EN Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: EN Mask */ + +/* MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/* MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#endif +} SAU_Type; + +/* SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/* SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/* SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/* SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/* SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/* CoreDebug is deprecated. replaced by DCB (Debug Control Block) */ +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief \deprecated Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED0[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< \deprecated CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< \deprecated CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Position */ +#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< \deprecated CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< \deprecated CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< \deprecated CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< \deprecated CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< \deprecated CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< \deprecated CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< \deprecated CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< \deprecated CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< \deprecated CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< \deprecated CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< \deprecated CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< \deprecated CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register */ +#define CoreDebug_DEMCR_DWTENA_Pos 24U /*!< \deprecated CoreDebug DEMCR: DWTENA Position */ +#define CoreDebug_DEMCR_DWTENA_Msk (1UL << CoreDebug_DEMCR_DWTENA_Pos) /*!< \deprecated CoreDebug DEMCR: DWTENA Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Mask */ + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Position */ +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Mask */ + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Mask */ + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos 16U /*!< \deprecated CoreDebug DSCSR: CDS Position */ +#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< \deprecated CoreDebug DSCSR: CDS Mask */ + +#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< \deprecated CoreDebug DSCSR: SBRSEL Position */ +#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< \deprecated CoreDebug DSCSR: SBRSEL Mask */ + +#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< \deprecated CoreDebug DSCSR: SBRSELEN Position */ +#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< \deprecated CoreDebug DSCSR: SBRSELEN Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DCB Debug Control Block + \brief Type definitions for the Debug Control Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Control Block Registers (DCB). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED0[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} DCB_Type; + +/* DHCSR, Debug Halting Control and Status Register Definitions */ +#define DCB_DHCSR_DBGKEY_Pos 16U /*!< DCB DHCSR: Debug key Position */ +#define DCB_DHCSR_DBGKEY_Msk (0xFFFFUL << DCB_DHCSR_DBGKEY_Pos) /*!< DCB DHCSR: Debug key Mask */ + +#define DCB_DHCSR_S_RESTART_ST_Pos 26U /*!< DCB DHCSR: Restart sticky status Position */ +#define DCB_DHCSR_S_RESTART_ST_Msk (0x1UL << DCB_DHCSR_S_RESTART_ST_Pos) /*!< DCB DHCSR: Restart sticky status Mask */ + +#define DCB_DHCSR_S_RESET_ST_Pos 25U /*!< DCB DHCSR: Reset sticky status Position */ +#define DCB_DHCSR_S_RESET_ST_Msk (0x1UL << DCB_DHCSR_S_RESET_ST_Pos) /*!< DCB DHCSR: Reset sticky status Mask */ + +#define DCB_DHCSR_S_RETIRE_ST_Pos 24U /*!< DCB DHCSR: Retire sticky status Position */ +#define DCB_DHCSR_S_RETIRE_ST_Msk (0x1UL << DCB_DHCSR_S_RETIRE_ST_Pos) /*!< DCB DHCSR: Retire sticky status Mask */ + +#define DCB_DHCSR_S_SDE_Pos 20U /*!< DCB DHCSR: Secure debug enabled Position */ +#define DCB_DHCSR_S_SDE_Msk (0x1UL << DCB_DHCSR_S_SDE_Pos) /*!< DCB DHCSR: Secure debug enabled Mask */ + +#define DCB_DHCSR_S_LOCKUP_Pos 19U /*!< DCB DHCSR: Lockup status Position */ +#define DCB_DHCSR_S_LOCKUP_Msk (0x1UL << DCB_DHCSR_S_LOCKUP_Pos) /*!< DCB DHCSR: Lockup status Mask */ + +#define DCB_DHCSR_S_SLEEP_Pos 18U /*!< DCB DHCSR: Sleeping status Position */ +#define DCB_DHCSR_S_SLEEP_Msk (0x1UL << DCB_DHCSR_S_SLEEP_Pos) /*!< DCB DHCSR: Sleeping status Mask */ + +#define DCB_DHCSR_S_HALT_Pos 17U /*!< DCB DHCSR: Halted status Position */ +#define DCB_DHCSR_S_HALT_Msk (0x1UL << DCB_DHCSR_S_HALT_Pos) /*!< DCB DHCSR: Halted status Mask */ + +#define DCB_DHCSR_S_REGRDY_Pos 16U /*!< DCB DHCSR: Register ready status Position */ +#define DCB_DHCSR_S_REGRDY_Msk (0x1UL << DCB_DHCSR_S_REGRDY_Pos) /*!< DCB DHCSR: Register ready status Mask */ + +#define DCB_DHCSR_C_MASKINTS_Pos 3U /*!< DCB DHCSR: Mask interrupts control Position */ +#define DCB_DHCSR_C_MASKINTS_Msk (0x1UL << DCB_DHCSR_C_MASKINTS_Pos) /*!< DCB DHCSR: Mask interrupts control Mask */ + +#define DCB_DHCSR_C_STEP_Pos 2U /*!< DCB DHCSR: Step control Position */ +#define DCB_DHCSR_C_STEP_Msk (0x1UL << DCB_DHCSR_C_STEP_Pos) /*!< DCB DHCSR: Step control Mask */ + +#define DCB_DHCSR_C_HALT_Pos 1U /*!< DCB DHCSR: Halt control Position */ +#define DCB_DHCSR_C_HALT_Msk (0x1UL << DCB_DHCSR_C_HALT_Pos) /*!< DCB DHCSR: Halt control Mask */ + +#define DCB_DHCSR_C_DEBUGEN_Pos 0U /*!< DCB DHCSR: Debug enable control Position */ +#define DCB_DHCSR_C_DEBUGEN_Msk (0x1UL /*<< DCB_DHCSR_C_DEBUGEN_Pos*/) /*!< DCB DHCSR: Debug enable control Mask */ + +/* DCRSR, Debug Core Register Select Register Definitions */ +#define DCB_DCRSR_REGWnR_Pos 16U /*!< DCB DCRSR: Register write/not-read Position */ +#define DCB_DCRSR_REGWnR_Msk (0x1UL << DCB_DCRSR_REGWnR_Pos) /*!< DCB DCRSR: Register write/not-read Mask */ + +#define DCB_DCRSR_REGSEL_Pos 0U /*!< DCB DCRSR: Register selector Position */ +#define DCB_DCRSR_REGSEL_Msk (0x7FUL /*<< DCB_DCRSR_REGSEL_Pos*/) /*!< DCB DCRSR: Register selector Mask */ + +/* DCRDR, Debug Core Register Data Register Definitions */ +#define DCB_DCRDR_DBGTMP_Pos 0U /*!< DCB DCRDR: Data temporary buffer Position */ +#define DCB_DCRDR_DBGTMP_Msk (0xFFFFFFFFUL /*<< DCB_DCRDR_DBGTMP_Pos*/) /*!< DCB DCRDR: Data temporary buffer Mask */ + +/* DEMCR, Debug Exception and Monitor Control Register Definitions */ +#define DCB_DEMCR_TRCENA_Pos 24U /*!< DCB DEMCR: Trace enable Position */ +#define DCB_DEMCR_TRCENA_Msk (0x1UL << DCB_DEMCR_TRCENA_Pos) /*!< DCB DEMCR: Trace enable Mask */ + +#define DCB_DEMCR_VC_HARDERR_Pos 10U /*!< DCB DEMCR: Vector Catch HardFault errors Position */ +#define DCB_DEMCR_VC_HARDERR_Msk (0x1UL << DCB_DEMCR_VC_HARDERR_Pos) /*!< DCB DEMCR: Vector Catch HardFault errors Mask */ + +#define DCB_DEMCR_VC_CORERESET_Pos 0U /*!< DCB DEMCR: Vector Catch Core reset Position */ +#define DCB_DEMCR_VC_CORERESET_Msk (0x1UL /*<< DCB_DEMCR_VC_CORERESET_Pos*/) /*!< DCB DEMCR: Vector Catch Core reset Mask */ + +/* DAUTHCTRL, Debug Authentication Control Register Definitions */ +#define DCB_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPNIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPNIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPNIDENSEL_Msk (0x1UL << DCB_DAUTHCTRL_SPNIDENSEL_Pos) /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Mask */ + +#define DCB_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< DCB DAUTHCTRL: Secure invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPIDENSEL_Msk (0x1UL /*<< DCB_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< DCB DAUTHCTRL: Secure invasive debug enable select Mask */ + +/* DSCSR, Debug Security Control and Status Register Definitions */ +#define DCB_DSCSR_CDSKEY_Pos 17U /*!< DCB DSCSR: CDS write-enable key Position */ +#define DCB_DSCSR_CDSKEY_Msk (0x1UL << DCB_DSCSR_CDSKEY_Pos) /*!< DCB DSCSR: CDS write-enable key Mask */ + +#define DCB_DSCSR_CDS_Pos 16U /*!< DCB DSCSR: Current domain Secure Position */ +#define DCB_DSCSR_CDS_Msk (0x1UL << DCB_DSCSR_CDS_Pos) /*!< DCB DSCSR: Current domain Secure Mask */ + +#define DCB_DSCSR_SBRSEL_Pos 1U /*!< DCB DSCSR: Secure banked register select Position */ +#define DCB_DSCSR_SBRSEL_Msk (0x1UL << DCB_DSCSR_SBRSEL_Pos) /*!< DCB DSCSR: Secure banked register select Mask */ + +#define DCB_DSCSR_SBRSELEN_Pos 0U /*!< DCB DSCSR: Secure banked register select enable Position */ +#define DCB_DSCSR_SBRSELEN_Msk (0x1UL /*<< DCB_DSCSR_SBRSELEN_Pos*/) /*!< DCB DSCSR: Secure banked register select enable Mask */ + +/*@} end of group CMSIS_DCB */ + + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DIB Debug Identification Block + \brief Type definitions for the Debug Identification Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Identification Block Registers (DIB). + */ +typedef struct +{ + __OM uint32_t DLAR; /*!< Offset: 0x000 ( /W) SCS Software Lock Access Register */ + __IM uint32_t DLSR; /*!< Offset: 0x004 (R/ ) SCS Software Lock Status Register */ + __IM uint32_t DAUTHSTATUS; /*!< Offset: 0x008 (R/ ) Debug Authentication Status Register */ + __IM uint32_t DDEVARCH; /*!< Offset: 0x00C (R/ ) SCS Device Architecture Register */ + __IM uint32_t DDEVTYPE; /*!< Offset: 0x010 (R/ ) SCS Device Type Register */ +} DIB_Type; + +/* DLAR, SCS Software Lock Access Register Definitions */ +#define DIB_DLAR_KEY_Pos 0U /*!< DIB DLAR: KEY Position */ +#define DIB_DLAR_KEY_Msk (0xFFFFFFFFUL /*<< DIB_DLAR_KEY_Pos */) /*!< DIB DLAR: KEY Mask */ + +/* DLSR, SCS Software Lock Status Register Definitions */ +#define DIB_DLSR_nTT_Pos 2U /*!< DIB DLSR: Not thirty-two bit Position */ +#define DIB_DLSR_nTT_Msk (0x1UL << DIB_DLSR_nTT_Pos ) /*!< DIB DLSR: Not thirty-two bit Mask */ + +#define DIB_DLSR_SLK_Pos 1U /*!< DIB DLSR: Software Lock status Position */ +#define DIB_DLSR_SLK_Msk (0x1UL << DIB_DLSR_SLK_Pos ) /*!< DIB DLSR: Software Lock status Mask */ + +#define DIB_DLSR_SLI_Pos 0U /*!< DIB DLSR: Software Lock implemented Position */ +#define DIB_DLSR_SLI_Msk (0x1UL /*<< DIB_DLSR_SLI_Pos*/) /*!< DIB DLSR: Software Lock implemented Mask */ + +/* DAUTHSTATUS, Debug Authentication Status Register Definitions */ +#define DIB_DAUTHSTATUS_SNID_Pos 6U /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_SNID_Msk (0x3UL << DIB_DAUTHSTATUS_SNID_Pos ) /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_SID_Pos 4U /*!< DIB DAUTHSTATUS: Secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_SID_Msk (0x3UL << DIB_DAUTHSTATUS_SID_Pos ) /*!< DIB DAUTHSTATUS: Secure Invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSNID_Pos 2U /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSNID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSID_Pos 0U /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSID_Msk (0x3UL /*<< DIB_DAUTHSTATUS_NSID_Pos*/) /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Mask */ + +/* DDEVARCH, SCS Device Architecture Register Definitions */ +#define DIB_DDEVARCH_ARCHITECT_Pos 21U /*!< DIB DDEVARCH: Architect Position */ +#define DIB_DDEVARCH_ARCHITECT_Msk (0x7FFUL << DIB_DDEVARCH_ARCHITECT_Pos ) /*!< DIB DDEVARCH: Architect Mask */ + +#define DIB_DDEVARCH_PRESENT_Pos 20U /*!< DIB DDEVARCH: DEVARCH Present Position */ +#define DIB_DDEVARCH_PRESENT_Msk (0x1FUL << DIB_DDEVARCH_PRESENT_Pos ) /*!< DIB DDEVARCH: DEVARCH Present Mask */ + +#define DIB_DDEVARCH_REVISION_Pos 16U /*!< DIB DDEVARCH: Revision Position */ +#define DIB_DDEVARCH_REVISION_Msk (0xFUL << DIB_DDEVARCH_REVISION_Pos ) /*!< DIB DDEVARCH: Revision Mask */ + +#define DIB_DDEVARCH_ARCHVER_Pos 12U /*!< DIB DDEVARCH: Architecture Version Position */ +#define DIB_DDEVARCH_ARCHVER_Msk (0xFUL << DIB_DDEVARCH_ARCHVER_Pos ) /*!< DIB DDEVARCH: Architecture Version Mask */ + +#define DIB_DDEVARCH_ARCHPART_Pos 0U /*!< DIB DDEVARCH: Architecture Part Position */ +#define DIB_DDEVARCH_ARCHPART_Msk (0xFFFUL /*<< DIB_DDEVARCH_ARCHPART_Pos*/) /*!< DIB DDEVARCH: Architecture Part Mask */ + +/* DDEVTYPE, SCS Device Type Register Definitions */ +#define DIB_DDEVTYPE_SUB_Pos 4U /*!< DIB DDEVTYPE: Sub-type Position */ +#define DIB_DDEVTYPE_SUB_Msk (0xFUL << DIB_DDEVTYPE_SUB_Pos ) /*!< DIB DDEVTYPE: Sub-type Mask */ + +#define DIB_DDEVTYPE_MAJOR_Pos 0U /*!< DIB DDEVTYPE: Major type Position */ +#define DIB_DDEVTYPE_MAJOR_Msk (0xFUL /*<< DIB_DDEVTYPE_MAJOR_Pos*/) /*!< DIB DDEVTYPE: Major type Mask */ + + +/*@} end of group CMSIS_DIB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ + #define CoreDebug_BASE (0xE000EDF0UL) /*!< \deprecated Core Debug Base Address */ + #define DCB_BASE (0xE000EDF0UL) /*!< DCB Base Address */ + #define DIB_BASE (0xE000EFB0UL) /*!< DIB Base Address */ + #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + + #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ + #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ + #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ + #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ + #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< \deprecated Core Debug configuration struct */ + #define DCB ((DCB_Type *) DCB_BASE ) /*!< DCB configuration struct */ + #define DIB ((DIB_Type *) DIB_BASE ) /*!< DIB configuration struct */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ + #endif + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ + #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ + #endif + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ + #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< \deprecated Core Debug Base Address (non-secure address space) */ + #define DCB_BASE_NS (0xE002EDF0UL) /*!< DCB Base Address (non-secure address space) */ + #define DIB_BASE_NS (0xE002EFB0UL) /*!< DIB Base Address (non-secure address space) */ + #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ + #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ + #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + + #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ + #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ + #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ + #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< \deprecated Core Debug configuration struct (non-secure address space) */ + #define DCB_NS ((DCB_Type *) DCB_BASE_NS ) /*!< DCB configuration struct (non-secure address space) */ + #define DIB_NS ((DIB_Type *) DIB_BASE_NS ) /*!< DIB configuration struct (non-secure address space) */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ + #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ + #endif + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else +/*#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping not available for Cortex-M23 */ +/*#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping not available for Cortex-M23 */ + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* Special LR values for Secure/Non-Secure call handling and exception handling */ + +/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ +#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ + +/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ +#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ +#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ +#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ +#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ +#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ +#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */ +#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ + +/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ +#else +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ +#endif + + +/* Interrupt Priorities are WORD accessible only under Armv6-M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + +#define __NVIC_SetPriorityGrouping(X) (void)(X) +#define __NVIC_GetPriorityGrouping() (0U) + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + If VTOR is not present address 0 must be mapped to SRAM. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t *vectors = (uint32_t *)SCB->VTOR; +#else + uint32_t *vectors = (uint32_t *)0x0U; +#endif + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + __DSB(); +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t *vectors = (uint32_t *)SCB->VTOR; +#else + uint32_t *vectors = (uint32_t *)0x0U; +#endif + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC_NS->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB_NS->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB_NS->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB_NS->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv8.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + + +/* ################################## Debug Control function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DCBFunctions Debug Control Functions + \brief Functions that access the Debug Control Block. + @{ + */ + + +/** + \brief Set Debug Authentication Control Register + \details writes to Debug Authentication Control register. + \param [in] value value to be writen. + */ +__STATIC_INLINE void DCB_SetAuthCtrl(uint32_t value) +{ + __DSB(); + __ISB(); + DCB->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register + \details Reads Debug Authentication Control register. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t DCB_GetAuthCtrl(void) +{ + return (DCB->DAUTHCTRL); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Debug Authentication Control Register (non-secure) + \details writes to non-secure Debug Authentication Control register when in secure state. + \param [in] value value to be writen + */ +__STATIC_INLINE void TZ_DCB_SetAuthCtrl_NS(uint32_t value) +{ + __DSB(); + __ISB(); + DCB_NS->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register (non-secure) + \details Reads non-secure Debug Authentication Control register when in secure state. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t TZ_DCB_GetAuthCtrl_NS(void) +{ + return (DCB_NS->DAUTHCTRL); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## Debug Identification function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DIBFunctions Debug Identification Functions + \brief Functions that access the Debug Identification Block. + @{ + */ + + +/** + \brief Get Debug Authentication Status Register + \details Reads Debug Authentication Status register. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t DIB_GetAuthStatus(void) +{ + return (DIB->DAUTHSTATUS); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Debug Authentication Status Register (non-secure) + \details Reads non-secure Debug Authentication Status register when in secure state. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t TZ_DIB_GetAuthStatus_NS(void) +{ + return (DIB_NS->DAUTHSTATUS); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM23_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/CMSIS/Core/Include/core_cm3.h b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/CMSIS/Core/Include/core_cm3.h new file mode 100644 index 0000000000..74fb87e5c5 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/CMSIS/Core/Include/core_cm3.h @@ -0,0 +1,1943 @@ +/**************************************************************************//** + * @file core_cm3.h + * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File + * @version V5.1.2 + * @date 04. June 2021 + ******************************************************************************/ +/* + * Copyright (c) 2009-2021 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM3_H_GENERIC +#define __CORE_CM3_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M3 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM3 definitions */ +#define __CM3_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM3_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16U) | \ + __CM3_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (3U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM3_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM3_H_DEPENDANT +#define __CORE_CM3_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM3_REV + #define __CM3_REV 0x0200U + #warning "__CM3_REV not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 1U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M3 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:1; /*!< bit: 9 Reserved */ + uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */ + uint32_t _reserved1:8; /*!< bit: 16..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit */ + uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */ +#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */ +#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24U]; + __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RESERVED1[24U]; + __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24U]; + __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24U]; + __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56U]; + __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[5U]; + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#if defined (__CM3_REV) && (__CM3_REV < 0x0201U) /* core r2p1 */ +#define SCB_VTOR_TBLBASE_Pos 29U /*!< SCB VTOR: TBLBASE Position */ +#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */ + +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#else +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#endif + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_CFSR_MEMFAULTSR_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ +#if defined (__CM3_REV) && (__CM3_REV >= 0x200U) + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +#else + uint32_t RESERVED1[1U]; +#endif +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/* Auxiliary Control Register Definitions */ +#if defined (__CM3_REV) && (__CM3_REV >= 0x200U) +#define SCnSCB_ACTLR_DISOOFP_Pos 9U /*!< ACTLR: DISOOFP Position */ +#define SCnSCB_ACTLR_DISOOFP_Msk (1UL << SCnSCB_ACTLR_DISOOFP_Pos) /*!< ACTLR: DISOOFP Mask */ + +#define SCnSCB_ACTLR_DISFPCA_Pos 8U /*!< ACTLR: DISFPCA Position */ +#define SCnSCB_ACTLR_DISFPCA_Msk (1UL << SCnSCB_ACTLR_DISFPCA_Pos) /*!< ACTLR: DISFPCA Mask */ + +#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ +#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR: DISDEFWBUF Position */ +#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ + +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ +#endif + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x1UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x1UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY2_Pos 0U /*!< TPI ITATBCTR2: ATREADY2 Position */ +#define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/) /*!< TPI ITATBCTR2: ATREADY2 Mask */ + +#define TPI_ITATBCTR2_ATREADY1_Pos 0U /*!< TPI ITATBCTR2: ATREADY1 Position */ +#define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/) /*!< TPI ITATBCTR2: ATREADY1 Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x1UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x1UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY2_Pos 0U /*!< TPI ITATBCTR0: ATREADY2 Position */ +#define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/) /*!< TPI ITATBCTR0: ATREADY2 Mask */ + +#define TPI_ITATBCTR0_ATREADY1_Pos 0U /*!< TPI ITATBCTR0: ATREADY1 Position */ +#define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/) /*!< TPI ITATBCTR0: ATREADY1 Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + /* ARM Application Note 321 states that the M3 does not require the architectural barrier */ +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv7.h" + +#endif + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM3_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/CMSIS/Core/Include/core_cm33.h b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/CMSIS/Core/Include/core_cm33.h new file mode 100644 index 0000000000..18a2e6fb03 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/CMSIS/Core/Include/core_cm33.h @@ -0,0 +1,3277 @@ +/**************************************************************************//** + * @file core_cm33.h + * @brief CMSIS Cortex-M33 Core Peripheral Access Layer Header File + * @version V5.2.3 + * @date 13. October 2021 + ******************************************************************************/ +/* + * Copyright (c) 2009-2021 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#elif defined ( __GNUC__ ) + #pragma GCC diagnostic ignored "-Wpedantic" /* disable pedantic warning due to unnamed structs/unions */ +#endif + +#ifndef __CORE_CM33_H_GENERIC +#define __CORE_CM33_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M33 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM33 definitions */ +#define __CM33_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM33_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM33_CMSIS_VERSION ((__CM33_CMSIS_VERSION_MAIN << 16U) | \ + __CM33_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (33U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined (__TARGET_FPU_VFP) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined (__ARM_FP) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined (__ARMVFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined (__TI_VFP_SUPPORT__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined (__FPU_VFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM33_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM33_H_DEPENDANT +#define __CORE_CM33_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM33_REV + #define __CM33_REV 0x0000U + #warning "__CM33_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DSP_PRESENT + #define __DSP_PRESENT 0U + #warning "__DSP_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 1U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M33 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core SAU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ +#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */ + uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */ + uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */ +#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */ + +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED6[580U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ + __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ + __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ + __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */ + uint32_t RESERVED7[21U]; + __IOM uint32_t SFSR; /*!< Offset: 0x0E4 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x0E8 (R/W) Secure Fault Address Register */ + uint32_t RESERVED3[69U]; + __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ + uint32_t RESERVED4[15U]; + __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ + uint32_t RESERVED5[1U]; + __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ + uint32_t RESERVED6[1U]; + __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ + __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ + __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ + __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ + __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ + __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ + __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ + __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ + __OM uint32_t BPIALL; /*!< Offset: 0x278 ( /W) Branch Predictor Invalidate All */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ +#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */ +#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */ +#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */ + +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */ +#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_CFSR_MEMFAULTSR_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */ +#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/* SCB Non-Secure Access Control Register Definitions */ +#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */ +#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */ + +#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */ +#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */ + +#define SCB_NSACR_CPn_Pos 0U /*!< SCB NSACR: CPn Position */ +#define SCB_NSACR_CPn_Msk (1UL /*<< SCB_NSACR_CPn_Pos*/) /*!< SCB NSACR: CPn Mask */ + +/* SCB Cache Level ID Register Definitions */ +#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ +#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ + +#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ +#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ + +/* SCB Cache Type Register Definitions */ +#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ +#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ + +#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ +#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ + +#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ +#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ + +#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ +#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ + +#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ +#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ + +/* SCB Cache Size ID Register Definitions */ +#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ +#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ + +#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ +#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ + +#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ +#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ + +#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ +#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ + +#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ +#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ + +#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ +#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ + +#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ +#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ + +/* SCB Cache Size Selection Register Definitions */ +#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ +#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ + +#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ +#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ + +/* SCB Software Triggered Interrupt Register Definitions */ +#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ +#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ + +/* SCB D-Cache Invalidate by Set-way Register Definitions */ +#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ +#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ + +#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ +#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ + +/* SCB D-Cache Clean by Set-way Register Definitions */ +#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ +#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ + +#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ +#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ + +/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ +#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ +#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ + +#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ +#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ + __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */ + uint32_t RESERVED6[4U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Stimulus Port Register Definitions */ +#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */ +#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */ + +#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */ +#define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */ + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */ +#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */ + +#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */ +#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED14[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED15[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED16[1U]; + __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ + uint32_t RESERVED17[1U]; + __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ + uint32_t RESERVED18[1U]; + __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ + uint32_t RESERVED19[1U]; + __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ + uint32_t RESERVED20[1U]; + __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ + uint32_t RESERVED21[1U]; + __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ + uint32_t RESERVED22[1U]; + __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ + uint32_t RESERVED23[1U]; + __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ + uint32_t RESERVED24[1U]; + __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ + uint32_t RESERVED25[1U]; + __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ + uint32_t RESERVED26[1U]; + __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ + uint32_t RESERVED27[1U]; + __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ + uint32_t RESERVED28[1U]; + __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ + uint32_t RESERVED29[1U]; + __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ + uint32_t RESERVED30[1U]; + __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ + uint32_t RESERVED31[1U]; + __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ + uint32_t RESERVED32[934U]; + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ + uint32_t RESERVED33[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */ +#define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t ITFTTD0; /*!< Offset: 0xEEC (R/ ) Integration Test FIFO Test Data 0 Register */ + __IOM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/W) Integration Test ATB Control Register 2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) Integration Test ATB Control Register 0 */ + __IM uint32_t ITFTTD1; /*!< Offset: 0xEFC (R/ ) Integration Test FIFO Test Data 1 Register */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) Device Configuration Register */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Identifier Register */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ +#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration Test FIFO Test Data 0 Register Definitions */ +#define TPI_ITFTTD0_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD0: ATB Interface 2 ATVALIDPosition */ +#define TPI_ITFTTD0_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 2 ATVALID Mask */ + +#define TPI_ITFTTD0_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD0: ATB Interface 2 byte count Position */ +#define TPI_ITFTTD0_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 2 byte count Mask */ + +#define TPI_ITFTTD0_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Position */ +#define TPI_ITFTTD0_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Mask */ + +#define TPI_ITFTTD0_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD0: ATB Interface 1 byte count Position */ +#define TPI_ITFTTD0_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 1 byte countt Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data2_Pos 16U /*!< TPI ITFTTD0: ATB Interface 1 data2 Position */ +#define TPI_ITFTTD0_ATB_IF1_data2_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data2 Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data1_Pos 8U /*!< TPI ITFTTD0: ATB Interface 1 data1 Position */ +#define TPI_ITFTTD0_ATB_IF1_data1_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data1 Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data0_Pos 0U /*!< TPI ITFTTD0: ATB Interface 1 data0 Position */ +#define TPI_ITFTTD0_ATB_IF1_data0_Msk (0xFFUL /*<< TPI_ITFTTD0_ATB_IF1_data0_Pos*/) /*!< TPI ITFTTD0: ATB Interface 1 data0 Mask */ + +/* TPI Integration Test ATB Control Register 2 Register Definitions */ +#define TPI_ITATBCTR2_AFVALID2S_Pos 1U /*!< TPI ITATBCTR2: AFVALID2S Position */ +#define TPI_ITATBCTR2_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID2S_Pos) /*!< TPI ITATBCTR2: AFVALID2SS Mask */ + +#define TPI_ITATBCTR2_AFVALID1S_Pos 1U /*!< TPI ITATBCTR2: AFVALID1S Position */ +#define TPI_ITATBCTR2_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID1S_Pos) /*!< TPI ITATBCTR2: AFVALID1SS Mask */ + +#define TPI_ITATBCTR2_ATREADY2S_Pos 0U /*!< TPI ITATBCTR2: ATREADY2S Position */ +#define TPI_ITATBCTR2_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2S_Pos*/) /*!< TPI ITATBCTR2: ATREADY2S Mask */ + +#define TPI_ITATBCTR2_ATREADY1S_Pos 0U /*!< TPI ITATBCTR2: ATREADY1S Position */ +#define TPI_ITATBCTR2_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1S_Pos*/) /*!< TPI ITATBCTR2: ATREADY1S Mask */ + +/* TPI Integration Test FIFO Test Data 1 Register Definitions */ +#define TPI_ITFTTD1_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Position */ +#define TPI_ITFTTD1_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Mask */ + +#define TPI_ITFTTD1_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD1: ATB Interface 2 byte count Position */ +#define TPI_ITFTTD1_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 2 byte count Mask */ + +#define TPI_ITFTTD1_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Position */ +#define TPI_ITFTTD1_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Mask */ + +#define TPI_ITFTTD1_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD1: ATB Interface 1 byte count Position */ +#define TPI_ITFTTD1_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 1 byte countt Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data2_Pos 16U /*!< TPI ITFTTD1: ATB Interface 2 data2 Position */ +#define TPI_ITFTTD1_ATB_IF2_data2_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data2 Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data1_Pos 8U /*!< TPI ITFTTD1: ATB Interface 2 data1 Position */ +#define TPI_ITFTTD1_ATB_IF2_data1_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data1 Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data0_Pos 0U /*!< TPI ITFTTD1: ATB Interface 2 data0 Position */ +#define TPI_ITFTTD1_ATB_IF2_data0_Msk (0xFFUL /*<< TPI_ITFTTD1_ATB_IF2_data0_Pos*/) /*!< TPI ITFTTD1: ATB Interface 2 data0 Mask */ + +/* TPI Integration Test ATB Control Register 0 Definitions */ +#define TPI_ITATBCTR0_AFVALID2S_Pos 1U /*!< TPI ITATBCTR0: AFVALID2S Position */ +#define TPI_ITATBCTR0_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID2S_Pos) /*!< TPI ITATBCTR0: AFVALID2SS Mask */ + +#define TPI_ITATBCTR0_AFVALID1S_Pos 1U /*!< TPI ITATBCTR0: AFVALID1S Position */ +#define TPI_ITATBCTR0_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID1S_Pos) /*!< TPI ITATBCTR0: AFVALID1SS Mask */ + +#define TPI_ITATBCTR0_ATREADY2S_Pos 0U /*!< TPI ITATBCTR0: ATREADY2S Position */ +#define TPI_ITATBCTR0_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2S_Pos*/) /*!< TPI ITATBCTR0: ATREADY2S Mask */ + +#define TPI_ITATBCTR0_ATREADY1S_Pos 0U /*!< TPI ITATBCTR0: ATREADY1S Position */ +#define TPI_ITATBCTR0_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1S_Pos*/) /*!< TPI ITATBCTR0: ATREADY1S Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFOSZ Position */ +#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFOSZ Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x3FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */ + __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */ + __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */ + __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */ + uint32_t RESERVED0[1]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ +#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/* MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */ + +/* MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/* MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#else + uint32_t RESERVED0[3]; +#endif + __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */ +} SAU_Type; + +/* SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/* SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/* SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/* SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/* SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/* Secure Fault Status Register Definitions */ +#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */ +#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */ + +#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */ +#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */ + +#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */ +#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */ + +#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */ +#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */ + +#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */ +#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */ + +#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */ +#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */ + +#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */ +#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */ + +#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */ +#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and VFP Feature Register 2 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */ +#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */ + +#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */ +#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */ + +#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */ +#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */ + +#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */ +#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */ + +#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */ +#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */ + +#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */ +#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */ +#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */ +#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and VFP Feature Register 0 Definitions */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and VFP Feature Register 1 Definitions */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/* Media and VFP Feature Register 2 Definitions */ +#define FPU_MVFR2_FPMisc_Pos 4U /*!< MVFR2: FPMisc bits Position */ +#define FPU_MVFR2_FPMisc_Msk (0xFUL << FPU_MVFR2_FPMisc_Pos) /*!< MVFR2: FPMisc bits Mask */ + +/*@} end of group CMSIS_FPU */ + +/* CoreDebug is deprecated. replaced by DCB (Debug Control Block) */ +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief \deprecated Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED0[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< \deprecated CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< \deprecated CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Position */ +#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< \deprecated CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< \deprecated CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< \deprecated CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< \deprecated CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< \deprecated CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< \deprecated CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< \deprecated CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< \deprecated CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< \deprecated CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< \deprecated CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< \deprecated CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< \deprecated CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< \deprecated CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< \deprecated CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< \deprecated CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< \deprecated CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< \deprecated CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< \deprecated CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< \deprecated CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< \deprecated CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< \deprecated CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< \deprecated CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< \deprecated CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< \deprecated CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< \deprecated CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< \deprecated CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< \deprecated CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< \deprecated CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< \deprecated CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< \deprecated CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Mask */ + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Position */ +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Mask */ + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Mask */ + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos 16U /*!< \deprecated CoreDebug DSCSR: CDS Position */ +#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< \deprecated CoreDebug DSCSR: CDS Mask */ + +#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< \deprecated CoreDebug DSCSR: SBRSEL Position */ +#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< \deprecated CoreDebug DSCSR: SBRSEL Mask */ + +#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< \deprecated CoreDebug DSCSR: SBRSELEN Position */ +#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< \deprecated CoreDebug DSCSR: SBRSELEN Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DCB Debug Control Block + \brief Type definitions for the Debug Control Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Control Block Registers (DCB). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED0[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} DCB_Type; + +/* DHCSR, Debug Halting Control and Status Register Definitions */ +#define DCB_DHCSR_DBGKEY_Pos 16U /*!< DCB DHCSR: Debug key Position */ +#define DCB_DHCSR_DBGKEY_Msk (0xFFFFUL << DCB_DHCSR_DBGKEY_Pos) /*!< DCB DHCSR: Debug key Mask */ + +#define DCB_DHCSR_S_RESTART_ST_Pos 26U /*!< DCB DHCSR: Restart sticky status Position */ +#define DCB_DHCSR_S_RESTART_ST_Msk (0x1UL << DCB_DHCSR_S_RESTART_ST_Pos) /*!< DCB DHCSR: Restart sticky status Mask */ + +#define DCB_DHCSR_S_RESET_ST_Pos 25U /*!< DCB DHCSR: Reset sticky status Position */ +#define DCB_DHCSR_S_RESET_ST_Msk (0x1UL << DCB_DHCSR_S_RESET_ST_Pos) /*!< DCB DHCSR: Reset sticky status Mask */ + +#define DCB_DHCSR_S_RETIRE_ST_Pos 24U /*!< DCB DHCSR: Retire sticky status Position */ +#define DCB_DHCSR_S_RETIRE_ST_Msk (0x1UL << DCB_DHCSR_S_RETIRE_ST_Pos) /*!< DCB DHCSR: Retire sticky status Mask */ + +#define DCB_DHCSR_S_SDE_Pos 20U /*!< DCB DHCSR: Secure debug enabled Position */ +#define DCB_DHCSR_S_SDE_Msk (0x1UL << DCB_DHCSR_S_SDE_Pos) /*!< DCB DHCSR: Secure debug enabled Mask */ + +#define DCB_DHCSR_S_LOCKUP_Pos 19U /*!< DCB DHCSR: Lockup status Position */ +#define DCB_DHCSR_S_LOCKUP_Msk (0x1UL << DCB_DHCSR_S_LOCKUP_Pos) /*!< DCB DHCSR: Lockup status Mask */ + +#define DCB_DHCSR_S_SLEEP_Pos 18U /*!< DCB DHCSR: Sleeping status Position */ +#define DCB_DHCSR_S_SLEEP_Msk (0x1UL << DCB_DHCSR_S_SLEEP_Pos) /*!< DCB DHCSR: Sleeping status Mask */ + +#define DCB_DHCSR_S_HALT_Pos 17U /*!< DCB DHCSR: Halted status Position */ +#define DCB_DHCSR_S_HALT_Msk (0x1UL << DCB_DHCSR_S_HALT_Pos) /*!< DCB DHCSR: Halted status Mask */ + +#define DCB_DHCSR_S_REGRDY_Pos 16U /*!< DCB DHCSR: Register ready status Position */ +#define DCB_DHCSR_S_REGRDY_Msk (0x1UL << DCB_DHCSR_S_REGRDY_Pos) /*!< DCB DHCSR: Register ready status Mask */ + +#define DCB_DHCSR_C_SNAPSTALL_Pos 5U /*!< DCB DHCSR: Snap stall control Position */ +#define DCB_DHCSR_C_SNAPSTALL_Msk (0x1UL << DCB_DHCSR_C_SNAPSTALL_Pos) /*!< DCB DHCSR: Snap stall control Mask */ + +#define DCB_DHCSR_C_MASKINTS_Pos 3U /*!< DCB DHCSR: Mask interrupts control Position */ +#define DCB_DHCSR_C_MASKINTS_Msk (0x1UL << DCB_DHCSR_C_MASKINTS_Pos) /*!< DCB DHCSR: Mask interrupts control Mask */ + +#define DCB_DHCSR_C_STEP_Pos 2U /*!< DCB DHCSR: Step control Position */ +#define DCB_DHCSR_C_STEP_Msk (0x1UL << DCB_DHCSR_C_STEP_Pos) /*!< DCB DHCSR: Step control Mask */ + +#define DCB_DHCSR_C_HALT_Pos 1U /*!< DCB DHCSR: Halt control Position */ +#define DCB_DHCSR_C_HALT_Msk (0x1UL << DCB_DHCSR_C_HALT_Pos) /*!< DCB DHCSR: Halt control Mask */ + +#define DCB_DHCSR_C_DEBUGEN_Pos 0U /*!< DCB DHCSR: Debug enable control Position */ +#define DCB_DHCSR_C_DEBUGEN_Msk (0x1UL /*<< DCB_DHCSR_C_DEBUGEN_Pos*/) /*!< DCB DHCSR: Debug enable control Mask */ + +/* DCRSR, Debug Core Register Select Register Definitions */ +#define DCB_DCRSR_REGWnR_Pos 16U /*!< DCB DCRSR: Register write/not-read Position */ +#define DCB_DCRSR_REGWnR_Msk (0x1UL << DCB_DCRSR_REGWnR_Pos) /*!< DCB DCRSR: Register write/not-read Mask */ + +#define DCB_DCRSR_REGSEL_Pos 0U /*!< DCB DCRSR: Register selector Position */ +#define DCB_DCRSR_REGSEL_Msk (0x7FUL /*<< DCB_DCRSR_REGSEL_Pos*/) /*!< DCB DCRSR: Register selector Mask */ + +/* DCRDR, Debug Core Register Data Register Definitions */ +#define DCB_DCRDR_DBGTMP_Pos 0U /*!< DCB DCRDR: Data temporary buffer Position */ +#define DCB_DCRDR_DBGTMP_Msk (0xFFFFFFFFUL /*<< DCB_DCRDR_DBGTMP_Pos*/) /*!< DCB DCRDR: Data temporary buffer Mask */ + +/* DEMCR, Debug Exception and Monitor Control Register Definitions */ +#define DCB_DEMCR_TRCENA_Pos 24U /*!< DCB DEMCR: Trace enable Position */ +#define DCB_DEMCR_TRCENA_Msk (0x1UL << DCB_DEMCR_TRCENA_Pos) /*!< DCB DEMCR: Trace enable Mask */ + +#define DCB_DEMCR_MONPRKEY_Pos 23U /*!< DCB DEMCR: Monitor pend req key Position */ +#define DCB_DEMCR_MONPRKEY_Msk (0x1UL << DCB_DEMCR_MONPRKEY_Pos) /*!< DCB DEMCR: Monitor pend req key Mask */ + +#define DCB_DEMCR_UMON_EN_Pos 21U /*!< DCB DEMCR: Unprivileged monitor enable Position */ +#define DCB_DEMCR_UMON_EN_Msk (0x1UL << DCB_DEMCR_UMON_EN_Pos) /*!< DCB DEMCR: Unprivileged monitor enable Mask */ + +#define DCB_DEMCR_SDME_Pos 20U /*!< DCB DEMCR: Secure DebugMonitor enable Position */ +#define DCB_DEMCR_SDME_Msk (0x1UL << DCB_DEMCR_SDME_Pos) /*!< DCB DEMCR: Secure DebugMonitor enable Mask */ + +#define DCB_DEMCR_MON_REQ_Pos 19U /*!< DCB DEMCR: Monitor request Position */ +#define DCB_DEMCR_MON_REQ_Msk (0x1UL << DCB_DEMCR_MON_REQ_Pos) /*!< DCB DEMCR: Monitor request Mask */ + +#define DCB_DEMCR_MON_STEP_Pos 18U /*!< DCB DEMCR: Monitor step Position */ +#define DCB_DEMCR_MON_STEP_Msk (0x1UL << DCB_DEMCR_MON_STEP_Pos) /*!< DCB DEMCR: Monitor step Mask */ + +#define DCB_DEMCR_MON_PEND_Pos 17U /*!< DCB DEMCR: Monitor pend Position */ +#define DCB_DEMCR_MON_PEND_Msk (0x1UL << DCB_DEMCR_MON_PEND_Pos) /*!< DCB DEMCR: Monitor pend Mask */ + +#define DCB_DEMCR_MON_EN_Pos 16U /*!< DCB DEMCR: Monitor enable Position */ +#define DCB_DEMCR_MON_EN_Msk (0x1UL << DCB_DEMCR_MON_EN_Pos) /*!< DCB DEMCR: Monitor enable Mask */ + +#define DCB_DEMCR_VC_SFERR_Pos 11U /*!< DCB DEMCR: Vector Catch SecureFault Position */ +#define DCB_DEMCR_VC_SFERR_Msk (0x1UL << DCB_DEMCR_VC_SFERR_Pos) /*!< DCB DEMCR: Vector Catch SecureFault Mask */ + +#define DCB_DEMCR_VC_HARDERR_Pos 10U /*!< DCB DEMCR: Vector Catch HardFault errors Position */ +#define DCB_DEMCR_VC_HARDERR_Msk (0x1UL << DCB_DEMCR_VC_HARDERR_Pos) /*!< DCB DEMCR: Vector Catch HardFault errors Mask */ + +#define DCB_DEMCR_VC_INTERR_Pos 9U /*!< DCB DEMCR: Vector Catch interrupt errors Position */ +#define DCB_DEMCR_VC_INTERR_Msk (0x1UL << DCB_DEMCR_VC_INTERR_Pos) /*!< DCB DEMCR: Vector Catch interrupt errors Mask */ + +#define DCB_DEMCR_VC_BUSERR_Pos 8U /*!< DCB DEMCR: Vector Catch BusFault errors Position */ +#define DCB_DEMCR_VC_BUSERR_Msk (0x1UL << DCB_DEMCR_VC_BUSERR_Pos) /*!< DCB DEMCR: Vector Catch BusFault errors Mask */ + +#define DCB_DEMCR_VC_STATERR_Pos 7U /*!< DCB DEMCR: Vector Catch state errors Position */ +#define DCB_DEMCR_VC_STATERR_Msk (0x1UL << DCB_DEMCR_VC_STATERR_Pos) /*!< DCB DEMCR: Vector Catch state errors Mask */ + +#define DCB_DEMCR_VC_CHKERR_Pos 6U /*!< DCB DEMCR: Vector Catch check errors Position */ +#define DCB_DEMCR_VC_CHKERR_Msk (0x1UL << DCB_DEMCR_VC_CHKERR_Pos) /*!< DCB DEMCR: Vector Catch check errors Mask */ + +#define DCB_DEMCR_VC_NOCPERR_Pos 5U /*!< DCB DEMCR: Vector Catch NOCP errors Position */ +#define DCB_DEMCR_VC_NOCPERR_Msk (0x1UL << DCB_DEMCR_VC_NOCPERR_Pos) /*!< DCB DEMCR: Vector Catch NOCP errors Mask */ + +#define DCB_DEMCR_VC_MMERR_Pos 4U /*!< DCB DEMCR: Vector Catch MemManage errors Position */ +#define DCB_DEMCR_VC_MMERR_Msk (0x1UL << DCB_DEMCR_VC_MMERR_Pos) /*!< DCB DEMCR: Vector Catch MemManage errors Mask */ + +#define DCB_DEMCR_VC_CORERESET_Pos 0U /*!< DCB DEMCR: Vector Catch Core reset Position */ +#define DCB_DEMCR_VC_CORERESET_Msk (0x1UL /*<< DCB_DEMCR_VC_CORERESET_Pos*/) /*!< DCB DEMCR: Vector Catch Core reset Mask */ + +/* DAUTHCTRL, Debug Authentication Control Register Definitions */ +#define DCB_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPNIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPNIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPNIDENSEL_Msk (0x1UL << DCB_DAUTHCTRL_SPNIDENSEL_Pos) /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Mask */ + +#define DCB_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< DCB DAUTHCTRL: Secure invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPIDENSEL_Msk (0x1UL /*<< DCB_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< DCB DAUTHCTRL: Secure invasive debug enable select Mask */ + +/* DSCSR, Debug Security Control and Status Register Definitions */ +#define DCB_DSCSR_CDSKEY_Pos 17U /*!< DCB DSCSR: CDS write-enable key Position */ +#define DCB_DSCSR_CDSKEY_Msk (0x1UL << DCB_DSCSR_CDSKEY_Pos) /*!< DCB DSCSR: CDS write-enable key Mask */ + +#define DCB_DSCSR_CDS_Pos 16U /*!< DCB DSCSR: Current domain Secure Position */ +#define DCB_DSCSR_CDS_Msk (0x1UL << DCB_DSCSR_CDS_Pos) /*!< DCB DSCSR: Current domain Secure Mask */ + +#define DCB_DSCSR_SBRSEL_Pos 1U /*!< DCB DSCSR: Secure banked register select Position */ +#define DCB_DSCSR_SBRSEL_Msk (0x1UL << DCB_DSCSR_SBRSEL_Pos) /*!< DCB DSCSR: Secure banked register select Mask */ + +#define DCB_DSCSR_SBRSELEN_Pos 0U /*!< DCB DSCSR: Secure banked register select enable Position */ +#define DCB_DSCSR_SBRSELEN_Msk (0x1UL /*<< DCB_DSCSR_SBRSELEN_Pos*/) /*!< DCB DSCSR: Secure banked register select enable Mask */ + +/*@} end of group CMSIS_DCB */ + + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DIB Debug Identification Block + \brief Type definitions for the Debug Identification Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Identification Block Registers (DIB). + */ +typedef struct +{ + __OM uint32_t DLAR; /*!< Offset: 0x000 ( /W) SCS Software Lock Access Register */ + __IM uint32_t DLSR; /*!< Offset: 0x004 (R/ ) SCS Software Lock Status Register */ + __IM uint32_t DAUTHSTATUS; /*!< Offset: 0x008 (R/ ) Debug Authentication Status Register */ + __IM uint32_t DDEVARCH; /*!< Offset: 0x00C (R/ ) SCS Device Architecture Register */ + __IM uint32_t DDEVTYPE; /*!< Offset: 0x010 (R/ ) SCS Device Type Register */ +} DIB_Type; + +/* DLAR, SCS Software Lock Access Register Definitions */ +#define DIB_DLAR_KEY_Pos 0U /*!< DIB DLAR: KEY Position */ +#define DIB_DLAR_KEY_Msk (0xFFFFFFFFUL /*<< DIB_DLAR_KEY_Pos */) /*!< DIB DLAR: KEY Mask */ + +/* DLSR, SCS Software Lock Status Register Definitions */ +#define DIB_DLSR_nTT_Pos 2U /*!< DIB DLSR: Not thirty-two bit Position */ +#define DIB_DLSR_nTT_Msk (0x1UL << DIB_DLSR_nTT_Pos ) /*!< DIB DLSR: Not thirty-two bit Mask */ + +#define DIB_DLSR_SLK_Pos 1U /*!< DIB DLSR: Software Lock status Position */ +#define DIB_DLSR_SLK_Msk (0x1UL << DIB_DLSR_SLK_Pos ) /*!< DIB DLSR: Software Lock status Mask */ + +#define DIB_DLSR_SLI_Pos 0U /*!< DIB DLSR: Software Lock implemented Position */ +#define DIB_DLSR_SLI_Msk (0x1UL /*<< DIB_DLSR_SLI_Pos*/) /*!< DIB DLSR: Software Lock implemented Mask */ + +/* DAUTHSTATUS, Debug Authentication Status Register Definitions */ +#define DIB_DAUTHSTATUS_SNID_Pos 6U /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_SNID_Msk (0x3UL << DIB_DAUTHSTATUS_SNID_Pos ) /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_SID_Pos 4U /*!< DIB DAUTHSTATUS: Secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_SID_Msk (0x3UL << DIB_DAUTHSTATUS_SID_Pos ) /*!< DIB DAUTHSTATUS: Secure Invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSNID_Pos 2U /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSNID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSID_Pos 0U /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSID_Msk (0x3UL /*<< DIB_DAUTHSTATUS_NSID_Pos*/) /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Mask */ + +/* DDEVARCH, SCS Device Architecture Register Definitions */ +#define DIB_DDEVARCH_ARCHITECT_Pos 21U /*!< DIB DDEVARCH: Architect Position */ +#define DIB_DDEVARCH_ARCHITECT_Msk (0x7FFUL << DIB_DDEVARCH_ARCHITECT_Pos ) /*!< DIB DDEVARCH: Architect Mask */ + +#define DIB_DDEVARCH_PRESENT_Pos 20U /*!< DIB DDEVARCH: DEVARCH Present Position */ +#define DIB_DDEVARCH_PRESENT_Msk (0x1FUL << DIB_DDEVARCH_PRESENT_Pos ) /*!< DIB DDEVARCH: DEVARCH Present Mask */ + +#define DIB_DDEVARCH_REVISION_Pos 16U /*!< DIB DDEVARCH: Revision Position */ +#define DIB_DDEVARCH_REVISION_Msk (0xFUL << DIB_DDEVARCH_REVISION_Pos ) /*!< DIB DDEVARCH: Revision Mask */ + +#define DIB_DDEVARCH_ARCHVER_Pos 12U /*!< DIB DDEVARCH: Architecture Version Position */ +#define DIB_DDEVARCH_ARCHVER_Msk (0xFUL << DIB_DDEVARCH_ARCHVER_Pos ) /*!< DIB DDEVARCH: Architecture Version Mask */ + +#define DIB_DDEVARCH_ARCHPART_Pos 0U /*!< DIB DDEVARCH: Architecture Part Position */ +#define DIB_DDEVARCH_ARCHPART_Msk (0xFFFUL /*<< DIB_DDEVARCH_ARCHPART_Pos*/) /*!< DIB DDEVARCH: Architecture Part Mask */ + +/* DDEVTYPE, SCS Device Type Register Definitions */ +#define DIB_DDEVTYPE_SUB_Pos 4U /*!< DIB DDEVTYPE: Sub-type Position */ +#define DIB_DDEVTYPE_SUB_Msk (0xFUL << DIB_DDEVTYPE_SUB_Pos ) /*!< DIB DDEVTYPE: Sub-type Mask */ + +#define DIB_DDEVTYPE_MAJOR_Pos 0U /*!< DIB DDEVTYPE: Major type Position */ +#define DIB_DDEVTYPE_MAJOR_Msk (0xFUL /*<< DIB_DDEVTYPE_MAJOR_Pos*/) /*!< DIB DDEVTYPE: Major type Mask */ + + +/*@} end of group CMSIS_DIB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ + #define CoreDebug_BASE (0xE000EDF0UL) /*!< \deprecated Core Debug Base Address */ + #define DCB_BASE (0xE000EDF0UL) /*!< DCB Base Address */ + #define DIB_BASE (0xE000EFB0UL) /*!< DIB Base Address */ + #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ + #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ + #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ + #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ + #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ + #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ + #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< \deprecated Core Debug configuration struct */ + #define DCB ((DCB_Type *) DCB_BASE ) /*!< DCB configuration struct */ + #define DIB ((DIB_Type *) DIB_BASE ) /*!< DIB configuration struct */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ + #endif + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ + #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ + #endif + + #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ + #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ + #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< \deprecated Core Debug Base Address (non-secure address space) */ + #define DCB_BASE_NS (0xE002EDF0UL) /*!< DCB Base Address (non-secure address space) */ + #define DIB_BASE_NS (0xE002EFB0UL) /*!< DIB Base Address (non-secure address space) */ + #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ + #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ + #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + + #define SCnSCB_NS ((SCnSCB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */ + #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ + #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ + #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ + #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< \deprecated Core Debug configuration struct (non-secure address space) */ + #define DCB_NS ((DCB_Type *) DCB_BASE_NS ) /*!< DCB configuration struct (non-secure address space) */ + #define DIB_NS ((DIB_Type *) DIB_BASE_NS ) /*!< DIB configuration struct (non-secure address space) */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ + #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ + #endif + + #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */ + #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */ + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_register_aliases Backwards Compatibility Aliases + \brief Register alias definitions for backwards compatibility. + @{ + */ +#define ID_ADR (ID_AFR) /*!< SCB Auxiliary Feature Register */ +/*@} */ + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* Special LR values for Secure/Non-Secure call handling and exception handling */ + +/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ +#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ + +/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ +#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ +#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ +#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ +#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ +#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ +#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */ +#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ + +/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ +#else +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ +#endif + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + __DSB(); +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Priority Grouping (non-secure) + \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB_NS->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB_NS->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping (non-secure) + \details Reads the priority grouping field from the non-secure NVIC when in secure state. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void) +{ + return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv8.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = FPU->MVFR0; + if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U) + { + return 2U; /* Double + Single precision FPU */ + } + else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + + +/* ################################## Debug Control function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DCBFunctions Debug Control Functions + \brief Functions that access the Debug Control Block. + @{ + */ + + +/** + \brief Set Debug Authentication Control Register + \details writes to Debug Authentication Control register. + \param [in] value value to be writen. + */ +__STATIC_INLINE void DCB_SetAuthCtrl(uint32_t value) +{ + __DSB(); + __ISB(); + DCB->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register + \details Reads Debug Authentication Control register. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t DCB_GetAuthCtrl(void) +{ + return (DCB->DAUTHCTRL); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Debug Authentication Control Register (non-secure) + \details writes to non-secure Debug Authentication Control register when in secure state. + \param [in] value value to be writen + */ +__STATIC_INLINE void TZ_DCB_SetAuthCtrl_NS(uint32_t value) +{ + __DSB(); + __ISB(); + DCB_NS->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register (non-secure) + \details Reads non-secure Debug Authentication Control register when in secure state. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t TZ_DCB_GetAuthCtrl_NS(void) +{ + return (DCB_NS->DAUTHCTRL); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## Debug Identification function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DIBFunctions Debug Identification Functions + \brief Functions that access the Debug Identification Block. + @{ + */ + + +/** + \brief Get Debug Authentication Status Register + \details Reads Debug Authentication Status register. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t DIB_GetAuthStatus(void) +{ + return (DIB->DAUTHSTATUS); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Debug Authentication Status Register (non-secure) + \details Reads non-secure Debug Authentication Status register when in secure state. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t TZ_DIB_GetAuthStatus_NS(void) +{ + return (DIB_NS->DAUTHSTATUS); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM33_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/CMSIS/Core/Include/core_cm35p.h b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/CMSIS/Core/Include/core_cm35p.h new file mode 100644 index 0000000000..3843d9542c --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/CMSIS/Core/Include/core_cm35p.h @@ -0,0 +1,3277 @@ +/**************************************************************************//** + * @file core_cm35p.h + * @brief CMSIS Cortex-M35P Core Peripheral Access Layer Header File + * @version V1.1.3 + * @date 13. October 2021 + ******************************************************************************/ +/* + * Copyright (c) 2018-2021 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#elif defined ( __GNUC__ ) + #pragma GCC diagnostic ignored "-Wpedantic" /* disable pedantic warning due to unnamed structs/unions */ +#endif + +#ifndef __CORE_CM35P_H_GENERIC +#define __CORE_CM35P_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M35P + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM35P definitions */ +#define __CM35P_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM35P_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM35P_CMSIS_VERSION ((__CM35P_CMSIS_VERSION_MAIN << 16U) | \ + __CM35P_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (35U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined (__TARGET_FPU_VFP) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined (__ARM_FP) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined (__ARMVFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined (__TI_VFP_SUPPORT__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined (__FPU_VFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM35P_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM35P_H_DEPENDANT +#define __CORE_CM35P_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM35P_REV + #define __CM35P_REV 0x0000U + #warning "__CM35P_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DSP_PRESENT + #define __DSP_PRESENT 0U + #warning "__DSP_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 1U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M35P */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core SAU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ +#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */ + uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */ + uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */ +#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */ + +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED6[580U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ + __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ + __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ + __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */ + uint32_t RESERVED7[21U]; + __IOM uint32_t SFSR; /*!< Offset: 0x0E4 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x0E8 (R/W) Secure Fault Address Register */ + uint32_t RESERVED3[69U]; + __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ + uint32_t RESERVED4[15U]; + __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ + uint32_t RESERVED5[1U]; + __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ + uint32_t RESERVED6[1U]; + __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ + __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ + __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ + __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ + __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ + __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ + __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ + __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ + __OM uint32_t BPIALL; /*!< Offset: 0x278 ( /W) Branch Predictor Invalidate All */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ +#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */ +#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */ +#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */ + +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */ +#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_CFSR_MEMFAULTSR_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */ +#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/* SCB Non-Secure Access Control Register Definitions */ +#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */ +#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */ + +#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */ +#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */ + +#define SCB_NSACR_CPn_Pos 0U /*!< SCB NSACR: CPn Position */ +#define SCB_NSACR_CPn_Msk (1UL /*<< SCB_NSACR_CPn_Pos*/) /*!< SCB NSACR: CPn Mask */ + +/* SCB Cache Level ID Register Definitions */ +#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ +#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ + +#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ +#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ + +/* SCB Cache Type Register Definitions */ +#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ +#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ + +#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ +#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ + +#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ +#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ + +#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ +#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ + +#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ +#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ + +/* SCB Cache Size ID Register Definitions */ +#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ +#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ + +#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ +#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ + +#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ +#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ + +#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ +#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ + +#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ +#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ + +#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ +#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ + +#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ +#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ + +/* SCB Cache Size Selection Register Definitions */ +#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ +#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ + +#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ +#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ + +/* SCB Software Triggered Interrupt Register Definitions */ +#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ +#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ + +/* SCB D-Cache Invalidate by Set-way Register Definitions */ +#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ +#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ + +#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ +#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ + +/* SCB D-Cache Clean by Set-way Register Definitions */ +#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ +#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ + +#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ +#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ + +/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ +#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ +#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ + +#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ +#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ + __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */ + uint32_t RESERVED6[4U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Stimulus Port Register Definitions */ +#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */ +#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */ + +#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */ +#define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */ + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */ +#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */ + +#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */ +#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED14[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED15[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED16[1U]; + __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ + uint32_t RESERVED17[1U]; + __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ + uint32_t RESERVED18[1U]; + __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ + uint32_t RESERVED19[1U]; + __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ + uint32_t RESERVED20[1U]; + __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ + uint32_t RESERVED21[1U]; + __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ + uint32_t RESERVED22[1U]; + __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ + uint32_t RESERVED23[1U]; + __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ + uint32_t RESERVED24[1U]; + __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ + uint32_t RESERVED25[1U]; + __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ + uint32_t RESERVED26[1U]; + __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ + uint32_t RESERVED27[1U]; + __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ + uint32_t RESERVED28[1U]; + __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ + uint32_t RESERVED29[1U]; + __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ + uint32_t RESERVED30[1U]; + __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ + uint32_t RESERVED31[1U]; + __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ + uint32_t RESERVED32[934U]; + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ + uint32_t RESERVED33[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */ +#define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t ITFTTD0; /*!< Offset: 0xEEC (R/ ) Integration Test FIFO Test Data 0 Register */ + __IOM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/W) Integration Test ATB Control Register 2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) Integration Test ATB Control Register 0 */ + __IM uint32_t ITFTTD1; /*!< Offset: 0xEFC (R/ ) Integration Test FIFO Test Data 1 Register */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) Device Configuration Register */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Identifier Register */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ +#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration Test FIFO Test Data 0 Register Definitions */ +#define TPI_ITFTTD0_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD0: ATB Interface 2 ATVALIDPosition */ +#define TPI_ITFTTD0_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 2 ATVALID Mask */ + +#define TPI_ITFTTD0_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD0: ATB Interface 2 byte count Position */ +#define TPI_ITFTTD0_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 2 byte count Mask */ + +#define TPI_ITFTTD0_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Position */ +#define TPI_ITFTTD0_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Mask */ + +#define TPI_ITFTTD0_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD0: ATB Interface 1 byte count Position */ +#define TPI_ITFTTD0_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 1 byte countt Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data2_Pos 16U /*!< TPI ITFTTD0: ATB Interface 1 data2 Position */ +#define TPI_ITFTTD0_ATB_IF1_data2_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data2 Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data1_Pos 8U /*!< TPI ITFTTD0: ATB Interface 1 data1 Position */ +#define TPI_ITFTTD0_ATB_IF1_data1_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data1 Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data0_Pos 0U /*!< TPI ITFTTD0: ATB Interface 1 data0 Position */ +#define TPI_ITFTTD0_ATB_IF1_data0_Msk (0xFFUL /*<< TPI_ITFTTD0_ATB_IF1_data0_Pos*/) /*!< TPI ITFTTD0: ATB Interface 1 data0 Mask */ + +/* TPI Integration Test ATB Control Register 2 Register Definitions */ +#define TPI_ITATBCTR2_AFVALID2S_Pos 1U /*!< TPI ITATBCTR2: AFVALID2S Position */ +#define TPI_ITATBCTR2_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID2S_Pos) /*!< TPI ITATBCTR2: AFVALID2SS Mask */ + +#define TPI_ITATBCTR2_AFVALID1S_Pos 1U /*!< TPI ITATBCTR2: AFVALID1S Position */ +#define TPI_ITATBCTR2_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID1S_Pos) /*!< TPI ITATBCTR2: AFVALID1SS Mask */ + +#define TPI_ITATBCTR2_ATREADY2S_Pos 0U /*!< TPI ITATBCTR2: ATREADY2S Position */ +#define TPI_ITATBCTR2_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2S_Pos*/) /*!< TPI ITATBCTR2: ATREADY2S Mask */ + +#define TPI_ITATBCTR2_ATREADY1S_Pos 0U /*!< TPI ITATBCTR2: ATREADY1S Position */ +#define TPI_ITATBCTR2_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1S_Pos*/) /*!< TPI ITATBCTR2: ATREADY1S Mask */ + +/* TPI Integration Test FIFO Test Data 1 Register Definitions */ +#define TPI_ITFTTD1_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Position */ +#define TPI_ITFTTD1_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Mask */ + +#define TPI_ITFTTD1_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD1: ATB Interface 2 byte count Position */ +#define TPI_ITFTTD1_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 2 byte count Mask */ + +#define TPI_ITFTTD1_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Position */ +#define TPI_ITFTTD1_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Mask */ + +#define TPI_ITFTTD1_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD1: ATB Interface 1 byte count Position */ +#define TPI_ITFTTD1_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 1 byte countt Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data2_Pos 16U /*!< TPI ITFTTD1: ATB Interface 2 data2 Position */ +#define TPI_ITFTTD1_ATB_IF2_data2_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data2 Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data1_Pos 8U /*!< TPI ITFTTD1: ATB Interface 2 data1 Position */ +#define TPI_ITFTTD1_ATB_IF2_data1_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data1 Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data0_Pos 0U /*!< TPI ITFTTD1: ATB Interface 2 data0 Position */ +#define TPI_ITFTTD1_ATB_IF2_data0_Msk (0xFFUL /*<< TPI_ITFTTD1_ATB_IF2_data0_Pos*/) /*!< TPI ITFTTD1: ATB Interface 2 data0 Mask */ + +/* TPI Integration Test ATB Control Register 0 Definitions */ +#define TPI_ITATBCTR0_AFVALID2S_Pos 1U /*!< TPI ITATBCTR0: AFVALID2S Position */ +#define TPI_ITATBCTR0_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID2S_Pos) /*!< TPI ITATBCTR0: AFVALID2SS Mask */ + +#define TPI_ITATBCTR0_AFVALID1S_Pos 1U /*!< TPI ITATBCTR0: AFVALID1S Position */ +#define TPI_ITATBCTR0_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID1S_Pos) /*!< TPI ITATBCTR0: AFVALID1SS Mask */ + +#define TPI_ITATBCTR0_ATREADY2S_Pos 0U /*!< TPI ITATBCTR0: ATREADY2S Position */ +#define TPI_ITATBCTR0_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2S_Pos*/) /*!< TPI ITATBCTR0: ATREADY2S Mask */ + +#define TPI_ITATBCTR0_ATREADY1S_Pos 0U /*!< TPI ITATBCTR0: ATREADY1S Position */ +#define TPI_ITATBCTR0_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1S_Pos*/) /*!< TPI ITATBCTR0: ATREADY1S Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFOSZ Position */ +#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFOSZ Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x3FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */ + __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */ + __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */ + __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */ + uint32_t RESERVED0[1]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ +#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/* MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */ + +/* MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/* MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#else + uint32_t RESERVED0[3]; +#endif + __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */ +} SAU_Type; + +/* SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/* SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/* SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/* SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/* SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/* Secure Fault Status Register Definitions */ +#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */ +#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */ + +#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */ +#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */ + +#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */ +#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */ + +#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */ +#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */ + +#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */ +#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */ + +#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */ +#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */ + +#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */ +#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */ + +#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */ +#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and VFP Feature Register 2 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */ +#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */ + +#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */ +#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */ + +#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */ +#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */ + +#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */ +#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */ + +#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */ +#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */ + +#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */ +#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */ +#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */ +#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and VFP Feature Register 0 Definitions */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and VFP Feature Register 1 Definitions */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/* Media and VFP Feature Register 2 Definitions */ +#define FPU_MVFR2_FPMisc_Pos 4U /*!< MVFR2: FPMisc bits Position */ +#define FPU_MVFR2_FPMisc_Msk (0xFUL << FPU_MVFR2_FPMisc_Pos) /*!< MVFR2: FPMisc bits Mask */ + +/*@} end of group CMSIS_FPU */ + +/* CoreDebug is deprecated. replaced by DCB (Debug Control Block) */ +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief \deprecated Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED0[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< \deprecated CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< \deprecated CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Position */ +#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< \deprecated CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< \deprecated CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< \deprecated CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< \deprecated CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< \deprecated CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< \deprecated CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< \deprecated CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< \deprecated CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< \deprecated CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< \deprecated CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< \deprecated CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< \deprecated CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< \deprecated CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< \deprecated CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< \deprecated CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< \deprecated CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< \deprecated CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< \deprecated CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< \deprecated CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< \deprecated CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< \deprecated CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< \deprecated CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< \deprecated CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< \deprecated CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< \deprecated CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< \deprecated CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< \deprecated CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< \deprecated CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< \deprecated CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< \deprecated CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Mask */ + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Position */ +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Mask */ + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Mask */ + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos 16U /*!< \deprecated CoreDebug DSCSR: CDS Position */ +#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< \deprecated CoreDebug DSCSR: CDS Mask */ + +#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< \deprecated CoreDebug DSCSR: SBRSEL Position */ +#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< \deprecated CoreDebug DSCSR: SBRSEL Mask */ + +#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< \deprecated CoreDebug DSCSR: SBRSELEN Position */ +#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< \deprecated CoreDebug DSCSR: SBRSELEN Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DCB Debug Control Block + \brief Type definitions for the Debug Control Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Control Block Registers (DCB). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED0[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} DCB_Type; + +/* DHCSR, Debug Halting Control and Status Register Definitions */ +#define DCB_DHCSR_DBGKEY_Pos 16U /*!< DCB DHCSR: Debug key Position */ +#define DCB_DHCSR_DBGKEY_Msk (0xFFFFUL << DCB_DHCSR_DBGKEY_Pos) /*!< DCB DHCSR: Debug key Mask */ + +#define DCB_DHCSR_S_RESTART_ST_Pos 26U /*!< DCB DHCSR: Restart sticky status Position */ +#define DCB_DHCSR_S_RESTART_ST_Msk (0x1UL << DCB_DHCSR_S_RESTART_ST_Pos) /*!< DCB DHCSR: Restart sticky status Mask */ + +#define DCB_DHCSR_S_RESET_ST_Pos 25U /*!< DCB DHCSR: Reset sticky status Position */ +#define DCB_DHCSR_S_RESET_ST_Msk (0x1UL << DCB_DHCSR_S_RESET_ST_Pos) /*!< DCB DHCSR: Reset sticky status Mask */ + +#define DCB_DHCSR_S_RETIRE_ST_Pos 24U /*!< DCB DHCSR: Retire sticky status Position */ +#define DCB_DHCSR_S_RETIRE_ST_Msk (0x1UL << DCB_DHCSR_S_RETIRE_ST_Pos) /*!< DCB DHCSR: Retire sticky status Mask */ + +#define DCB_DHCSR_S_SDE_Pos 20U /*!< DCB DHCSR: Secure debug enabled Position */ +#define DCB_DHCSR_S_SDE_Msk (0x1UL << DCB_DHCSR_S_SDE_Pos) /*!< DCB DHCSR: Secure debug enabled Mask */ + +#define DCB_DHCSR_S_LOCKUP_Pos 19U /*!< DCB DHCSR: Lockup status Position */ +#define DCB_DHCSR_S_LOCKUP_Msk (0x1UL << DCB_DHCSR_S_LOCKUP_Pos) /*!< DCB DHCSR: Lockup status Mask */ + +#define DCB_DHCSR_S_SLEEP_Pos 18U /*!< DCB DHCSR: Sleeping status Position */ +#define DCB_DHCSR_S_SLEEP_Msk (0x1UL << DCB_DHCSR_S_SLEEP_Pos) /*!< DCB DHCSR: Sleeping status Mask */ + +#define DCB_DHCSR_S_HALT_Pos 17U /*!< DCB DHCSR: Halted status Position */ +#define DCB_DHCSR_S_HALT_Msk (0x1UL << DCB_DHCSR_S_HALT_Pos) /*!< DCB DHCSR: Halted status Mask */ + +#define DCB_DHCSR_S_REGRDY_Pos 16U /*!< DCB DHCSR: Register ready status Position */ +#define DCB_DHCSR_S_REGRDY_Msk (0x1UL << DCB_DHCSR_S_REGRDY_Pos) /*!< DCB DHCSR: Register ready status Mask */ + +#define DCB_DHCSR_C_SNAPSTALL_Pos 5U /*!< DCB DHCSR: Snap stall control Position */ +#define DCB_DHCSR_C_SNAPSTALL_Msk (0x1UL << DCB_DHCSR_C_SNAPSTALL_Pos) /*!< DCB DHCSR: Snap stall control Mask */ + +#define DCB_DHCSR_C_MASKINTS_Pos 3U /*!< DCB DHCSR: Mask interrupts control Position */ +#define DCB_DHCSR_C_MASKINTS_Msk (0x1UL << DCB_DHCSR_C_MASKINTS_Pos) /*!< DCB DHCSR: Mask interrupts control Mask */ + +#define DCB_DHCSR_C_STEP_Pos 2U /*!< DCB DHCSR: Step control Position */ +#define DCB_DHCSR_C_STEP_Msk (0x1UL << DCB_DHCSR_C_STEP_Pos) /*!< DCB DHCSR: Step control Mask */ + +#define DCB_DHCSR_C_HALT_Pos 1U /*!< DCB DHCSR: Halt control Position */ +#define DCB_DHCSR_C_HALT_Msk (0x1UL << DCB_DHCSR_C_HALT_Pos) /*!< DCB DHCSR: Halt control Mask */ + +#define DCB_DHCSR_C_DEBUGEN_Pos 0U /*!< DCB DHCSR: Debug enable control Position */ +#define DCB_DHCSR_C_DEBUGEN_Msk (0x1UL /*<< DCB_DHCSR_C_DEBUGEN_Pos*/) /*!< DCB DHCSR: Debug enable control Mask */ + +/* DCRSR, Debug Core Register Select Register Definitions */ +#define DCB_DCRSR_REGWnR_Pos 16U /*!< DCB DCRSR: Register write/not-read Position */ +#define DCB_DCRSR_REGWnR_Msk (0x1UL << DCB_DCRSR_REGWnR_Pos) /*!< DCB DCRSR: Register write/not-read Mask */ + +#define DCB_DCRSR_REGSEL_Pos 0U /*!< DCB DCRSR: Register selector Position */ +#define DCB_DCRSR_REGSEL_Msk (0x7FUL /*<< DCB_DCRSR_REGSEL_Pos*/) /*!< DCB DCRSR: Register selector Mask */ + +/* DCRDR, Debug Core Register Data Register Definitions */ +#define DCB_DCRDR_DBGTMP_Pos 0U /*!< DCB DCRDR: Data temporary buffer Position */ +#define DCB_DCRDR_DBGTMP_Msk (0xFFFFFFFFUL /*<< DCB_DCRDR_DBGTMP_Pos*/) /*!< DCB DCRDR: Data temporary buffer Mask */ + +/* DEMCR, Debug Exception and Monitor Control Register Definitions */ +#define DCB_DEMCR_TRCENA_Pos 24U /*!< DCB DEMCR: Trace enable Position */ +#define DCB_DEMCR_TRCENA_Msk (0x1UL << DCB_DEMCR_TRCENA_Pos) /*!< DCB DEMCR: Trace enable Mask */ + +#define DCB_DEMCR_MONPRKEY_Pos 23U /*!< DCB DEMCR: Monitor pend req key Position */ +#define DCB_DEMCR_MONPRKEY_Msk (0x1UL << DCB_DEMCR_MONPRKEY_Pos) /*!< DCB DEMCR: Monitor pend req key Mask */ + +#define DCB_DEMCR_UMON_EN_Pos 21U /*!< DCB DEMCR: Unprivileged monitor enable Position */ +#define DCB_DEMCR_UMON_EN_Msk (0x1UL << DCB_DEMCR_UMON_EN_Pos) /*!< DCB DEMCR: Unprivileged monitor enable Mask */ + +#define DCB_DEMCR_SDME_Pos 20U /*!< DCB DEMCR: Secure DebugMonitor enable Position */ +#define DCB_DEMCR_SDME_Msk (0x1UL << DCB_DEMCR_SDME_Pos) /*!< DCB DEMCR: Secure DebugMonitor enable Mask */ + +#define DCB_DEMCR_MON_REQ_Pos 19U /*!< DCB DEMCR: Monitor request Position */ +#define DCB_DEMCR_MON_REQ_Msk (0x1UL << DCB_DEMCR_MON_REQ_Pos) /*!< DCB DEMCR: Monitor request Mask */ + +#define DCB_DEMCR_MON_STEP_Pos 18U /*!< DCB DEMCR: Monitor step Position */ +#define DCB_DEMCR_MON_STEP_Msk (0x1UL << DCB_DEMCR_MON_STEP_Pos) /*!< DCB DEMCR: Monitor step Mask */ + +#define DCB_DEMCR_MON_PEND_Pos 17U /*!< DCB DEMCR: Monitor pend Position */ +#define DCB_DEMCR_MON_PEND_Msk (0x1UL << DCB_DEMCR_MON_PEND_Pos) /*!< DCB DEMCR: Monitor pend Mask */ + +#define DCB_DEMCR_MON_EN_Pos 16U /*!< DCB DEMCR: Monitor enable Position */ +#define DCB_DEMCR_MON_EN_Msk (0x1UL << DCB_DEMCR_MON_EN_Pos) /*!< DCB DEMCR: Monitor enable Mask */ + +#define DCB_DEMCR_VC_SFERR_Pos 11U /*!< DCB DEMCR: Vector Catch SecureFault Position */ +#define DCB_DEMCR_VC_SFERR_Msk (0x1UL << DCB_DEMCR_VC_SFERR_Pos) /*!< DCB DEMCR: Vector Catch SecureFault Mask */ + +#define DCB_DEMCR_VC_HARDERR_Pos 10U /*!< DCB DEMCR: Vector Catch HardFault errors Position */ +#define DCB_DEMCR_VC_HARDERR_Msk (0x1UL << DCB_DEMCR_VC_HARDERR_Pos) /*!< DCB DEMCR: Vector Catch HardFault errors Mask */ + +#define DCB_DEMCR_VC_INTERR_Pos 9U /*!< DCB DEMCR: Vector Catch interrupt errors Position */ +#define DCB_DEMCR_VC_INTERR_Msk (0x1UL << DCB_DEMCR_VC_INTERR_Pos) /*!< DCB DEMCR: Vector Catch interrupt errors Mask */ + +#define DCB_DEMCR_VC_BUSERR_Pos 8U /*!< DCB DEMCR: Vector Catch BusFault errors Position */ +#define DCB_DEMCR_VC_BUSERR_Msk (0x1UL << DCB_DEMCR_VC_BUSERR_Pos) /*!< DCB DEMCR: Vector Catch BusFault errors Mask */ + +#define DCB_DEMCR_VC_STATERR_Pos 7U /*!< DCB DEMCR: Vector Catch state errors Position */ +#define DCB_DEMCR_VC_STATERR_Msk (0x1UL << DCB_DEMCR_VC_STATERR_Pos) /*!< DCB DEMCR: Vector Catch state errors Mask */ + +#define DCB_DEMCR_VC_CHKERR_Pos 6U /*!< DCB DEMCR: Vector Catch check errors Position */ +#define DCB_DEMCR_VC_CHKERR_Msk (0x1UL << DCB_DEMCR_VC_CHKERR_Pos) /*!< DCB DEMCR: Vector Catch check errors Mask */ + +#define DCB_DEMCR_VC_NOCPERR_Pos 5U /*!< DCB DEMCR: Vector Catch NOCP errors Position */ +#define DCB_DEMCR_VC_NOCPERR_Msk (0x1UL << DCB_DEMCR_VC_NOCPERR_Pos) /*!< DCB DEMCR: Vector Catch NOCP errors Mask */ + +#define DCB_DEMCR_VC_MMERR_Pos 4U /*!< DCB DEMCR: Vector Catch MemManage errors Position */ +#define DCB_DEMCR_VC_MMERR_Msk (0x1UL << DCB_DEMCR_VC_MMERR_Pos) /*!< DCB DEMCR: Vector Catch MemManage errors Mask */ + +#define DCB_DEMCR_VC_CORERESET_Pos 0U /*!< DCB DEMCR: Vector Catch Core reset Position */ +#define DCB_DEMCR_VC_CORERESET_Msk (0x1UL /*<< DCB_DEMCR_VC_CORERESET_Pos*/) /*!< DCB DEMCR: Vector Catch Core reset Mask */ + +/* DAUTHCTRL, Debug Authentication Control Register Definitions */ +#define DCB_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPNIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPNIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPNIDENSEL_Msk (0x1UL << DCB_DAUTHCTRL_SPNIDENSEL_Pos) /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Mask */ + +#define DCB_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< DCB DAUTHCTRL: Secure invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPIDENSEL_Msk (0x1UL /*<< DCB_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< DCB DAUTHCTRL: Secure invasive debug enable select Mask */ + +/* DSCSR, Debug Security Control and Status Register Definitions */ +#define DCB_DSCSR_CDSKEY_Pos 17U /*!< DCB DSCSR: CDS write-enable key Position */ +#define DCB_DSCSR_CDSKEY_Msk (0x1UL << DCB_DSCSR_CDSKEY_Pos) /*!< DCB DSCSR: CDS write-enable key Mask */ + +#define DCB_DSCSR_CDS_Pos 16U /*!< DCB DSCSR: Current domain Secure Position */ +#define DCB_DSCSR_CDS_Msk (0x1UL << DCB_DSCSR_CDS_Pos) /*!< DCB DSCSR: Current domain Secure Mask */ + +#define DCB_DSCSR_SBRSEL_Pos 1U /*!< DCB DSCSR: Secure banked register select Position */ +#define DCB_DSCSR_SBRSEL_Msk (0x1UL << DCB_DSCSR_SBRSEL_Pos) /*!< DCB DSCSR: Secure banked register select Mask */ + +#define DCB_DSCSR_SBRSELEN_Pos 0U /*!< DCB DSCSR: Secure banked register select enable Position */ +#define DCB_DSCSR_SBRSELEN_Msk (0x1UL /*<< DCB_DSCSR_SBRSELEN_Pos*/) /*!< DCB DSCSR: Secure banked register select enable Mask */ + +/*@} end of group CMSIS_DCB */ + + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DIB Debug Identification Block + \brief Type definitions for the Debug Identification Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Identification Block Registers (DIB). + */ +typedef struct +{ + __OM uint32_t DLAR; /*!< Offset: 0x000 ( /W) SCS Software Lock Access Register */ + __IM uint32_t DLSR; /*!< Offset: 0x004 (R/ ) SCS Software Lock Status Register */ + __IM uint32_t DAUTHSTATUS; /*!< Offset: 0x008 (R/ ) Debug Authentication Status Register */ + __IM uint32_t DDEVARCH; /*!< Offset: 0x00C (R/ ) SCS Device Architecture Register */ + __IM uint32_t DDEVTYPE; /*!< Offset: 0x010 (R/ ) SCS Device Type Register */ +} DIB_Type; + +/* DLAR, SCS Software Lock Access Register Definitions */ +#define DIB_DLAR_KEY_Pos 0U /*!< DIB DLAR: KEY Position */ +#define DIB_DLAR_KEY_Msk (0xFFFFFFFFUL /*<< DIB_DLAR_KEY_Pos */) /*!< DIB DLAR: KEY Mask */ + +/* DLSR, SCS Software Lock Status Register Definitions */ +#define DIB_DLSR_nTT_Pos 2U /*!< DIB DLSR: Not thirty-two bit Position */ +#define DIB_DLSR_nTT_Msk (0x1UL << DIB_DLSR_nTT_Pos ) /*!< DIB DLSR: Not thirty-two bit Mask */ + +#define DIB_DLSR_SLK_Pos 1U /*!< DIB DLSR: Software Lock status Position */ +#define DIB_DLSR_SLK_Msk (0x1UL << DIB_DLSR_SLK_Pos ) /*!< DIB DLSR: Software Lock status Mask */ + +#define DIB_DLSR_SLI_Pos 0U /*!< DIB DLSR: Software Lock implemented Position */ +#define DIB_DLSR_SLI_Msk (0x1UL /*<< DIB_DLSR_SLI_Pos*/) /*!< DIB DLSR: Software Lock implemented Mask */ + +/* DAUTHSTATUS, Debug Authentication Status Register Definitions */ +#define DIB_DAUTHSTATUS_SNID_Pos 6U /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_SNID_Msk (0x3UL << DIB_DAUTHSTATUS_SNID_Pos ) /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_SID_Pos 4U /*!< DIB DAUTHSTATUS: Secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_SID_Msk (0x3UL << DIB_DAUTHSTATUS_SID_Pos ) /*!< DIB DAUTHSTATUS: Secure Invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSNID_Pos 2U /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSNID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSID_Pos 0U /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSID_Msk (0x3UL /*<< DIB_DAUTHSTATUS_NSID_Pos*/) /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Mask */ + +/* DDEVARCH, SCS Device Architecture Register Definitions */ +#define DIB_DDEVARCH_ARCHITECT_Pos 21U /*!< DIB DDEVARCH: Architect Position */ +#define DIB_DDEVARCH_ARCHITECT_Msk (0x7FFUL << DIB_DDEVARCH_ARCHITECT_Pos ) /*!< DIB DDEVARCH: Architect Mask */ + +#define DIB_DDEVARCH_PRESENT_Pos 20U /*!< DIB DDEVARCH: DEVARCH Present Position */ +#define DIB_DDEVARCH_PRESENT_Msk (0x1FUL << DIB_DDEVARCH_PRESENT_Pos ) /*!< DIB DDEVARCH: DEVARCH Present Mask */ + +#define DIB_DDEVARCH_REVISION_Pos 16U /*!< DIB DDEVARCH: Revision Position */ +#define DIB_DDEVARCH_REVISION_Msk (0xFUL << DIB_DDEVARCH_REVISION_Pos ) /*!< DIB DDEVARCH: Revision Mask */ + +#define DIB_DDEVARCH_ARCHVER_Pos 12U /*!< DIB DDEVARCH: Architecture Version Position */ +#define DIB_DDEVARCH_ARCHVER_Msk (0xFUL << DIB_DDEVARCH_ARCHVER_Pos ) /*!< DIB DDEVARCH: Architecture Version Mask */ + +#define DIB_DDEVARCH_ARCHPART_Pos 0U /*!< DIB DDEVARCH: Architecture Part Position */ +#define DIB_DDEVARCH_ARCHPART_Msk (0xFFFUL /*<< DIB_DDEVARCH_ARCHPART_Pos*/) /*!< DIB DDEVARCH: Architecture Part Mask */ + +/* DDEVTYPE, SCS Device Type Register Definitions */ +#define DIB_DDEVTYPE_SUB_Pos 4U /*!< DIB DDEVTYPE: Sub-type Position */ +#define DIB_DDEVTYPE_SUB_Msk (0xFUL << DIB_DDEVTYPE_SUB_Pos ) /*!< DIB DDEVTYPE: Sub-type Mask */ + +#define DIB_DDEVTYPE_MAJOR_Pos 0U /*!< DIB DDEVTYPE: Major type Position */ +#define DIB_DDEVTYPE_MAJOR_Msk (0xFUL /*<< DIB_DDEVTYPE_MAJOR_Pos*/) /*!< DIB DDEVTYPE: Major type Mask */ + + +/*@} end of group CMSIS_DIB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ + #define CoreDebug_BASE (0xE000EDF0UL) /*!< \deprecated Core Debug Base Address */ + #define DCB_BASE (0xE000EDF0UL) /*!< DCB Base Address */ + #define DIB_BASE (0xE000EFB0UL) /*!< DIB Base Address */ + #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ + #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ + #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ + #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ + #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ + #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ + #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< \deprecated Core Debug configuration struct */ + #define DCB ((DCB_Type *) DCB_BASE ) /*!< DCB configuration struct */ + #define DIB ((DIB_Type *) DIB_BASE ) /*!< DIB configuration struct */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ + #endif + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ + #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ + #endif + + #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ + #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ + #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< \deprecated Core Debug Base Address (non-secure address space) */ + #define DCB_BASE_NS (0xE002EDF0UL) /*!< DCB Base Address (non-secure address space) */ + #define DIB_BASE_NS (0xE002EFB0UL) /*!< DIB Base Address (non-secure address space) */ + #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ + #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ + #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + + #define SCnSCB_NS ((SCnSCB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */ + #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ + #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ + #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ + #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< \deprecated Core Debug configuration struct (non-secure address space) */ + #define DCB_NS ((DCB_Type *) DCB_BASE_NS ) /*!< DCB configuration struct (non-secure address space) */ + #define DIB_NS ((DIB_Type *) DIB_BASE_NS ) /*!< DIB configuration struct (non-secure address space) */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ + #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ + #endif + + #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */ + #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */ + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_register_aliases Backwards Compatibility Aliases + \brief Register alias definitions for backwards compatibility. + @{ + */ +#define ID_ADR (ID_AFR) /*!< SCB Auxiliary Feature Register */ +/*@} */ + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* Special LR values for Secure/Non-Secure call handling and exception handling */ + +/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ +#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ + +/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ +#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ +#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ +#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ +#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ +#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ +#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */ +#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ + +/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ +#else +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ +#endif + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + __DSB(); +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Priority Grouping (non-secure) + \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB_NS->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB_NS->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping (non-secure) + \details Reads the priority grouping field from the non-secure NVIC when in secure state. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void) +{ + return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv8.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = FPU->MVFR0; + if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U) + { + return 2U; /* Double + Single precision FPU */ + } + else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + + +/* ################################## Debug Control function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DCBFunctions Debug Control Functions + \brief Functions that access the Debug Control Block. + @{ + */ + + +/** + \brief Set Debug Authentication Control Register + \details writes to Debug Authentication Control register. + \param [in] value value to be writen. + */ +__STATIC_INLINE void DCB_SetAuthCtrl(uint32_t value) +{ + __DSB(); + __ISB(); + DCB->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register + \details Reads Debug Authentication Control register. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t DCB_GetAuthCtrl(void) +{ + return (DCB->DAUTHCTRL); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Debug Authentication Control Register (non-secure) + \details writes to non-secure Debug Authentication Control register when in secure state. + \param [in] value value to be writen + */ +__STATIC_INLINE void TZ_DCB_SetAuthCtrl_NS(uint32_t value) +{ + __DSB(); + __ISB(); + DCB_NS->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register (non-secure) + \details Reads non-secure Debug Authentication Control register when in secure state. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t TZ_DCB_GetAuthCtrl_NS(void) +{ + return (DCB_NS->DAUTHCTRL); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## Debug Identification function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DIBFunctions Debug Identification Functions + \brief Functions that access the Debug Identification Block. + @{ + */ + + +/** + \brief Get Debug Authentication Status Register + \details Reads Debug Authentication Status register. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t DIB_GetAuthStatus(void) +{ + return (DIB->DAUTHSTATUS); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Debug Authentication Status Register (non-secure) + \details Reads non-secure Debug Authentication Status register when in secure state. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t TZ_DIB_GetAuthStatus_NS(void) +{ + return (DIB_NS->DAUTHSTATUS); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM35P_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/CMSIS/Core/Include/core_cm4.h b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/CMSIS/Core/Include/core_cm4.h new file mode 100644 index 0000000000..e21cd14925 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/CMSIS/Core/Include/core_cm4.h @@ -0,0 +1,2129 @@ +/**************************************************************************//** + * @file core_cm4.h + * @brief CMSIS Cortex-M4 Core Peripheral Access Layer Header File + * @version V5.1.2 + * @date 04. June 2021 + ******************************************************************************/ +/* + * Copyright (c) 2009-2020 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM4_H_GENERIC +#define __CORE_CM4_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M4 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM4 definitions */ +#define __CM4_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM4_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM4_CMSIS_VERSION ((__CM4_CMSIS_VERSION_MAIN << 16U) | \ + __CM4_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (4U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM4_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM4_H_DEPENDANT +#define __CORE_CM4_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM4_REV + #define __CM4_REV 0x0000U + #warning "__CM4_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 1U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M4 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:1; /*!< bit: 9 Reserved */ + uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit */ + uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */ +#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */ +#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ + uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24U]; + __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RESERVED1[24U]; + __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24U]; + __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24U]; + __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56U]; + __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[5U]; + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_CFSR_MEMFAULTSR_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_DISOOFP_Pos 9U /*!< ACTLR: DISOOFP Position */ +#define SCnSCB_ACTLR_DISOOFP_Msk (1UL << SCnSCB_ACTLR_DISOOFP_Pos) /*!< ACTLR: DISOOFP Mask */ + +#define SCnSCB_ACTLR_DISFPCA_Pos 8U /*!< ACTLR: DISFPCA Position */ +#define SCnSCB_ACTLR_DISFPCA_Msk (1UL << SCnSCB_ACTLR_DISFPCA_Pos) /*!< ACTLR: DISFPCA Mask */ + +#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ +#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR: DISDEFWBUF Position */ +#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ + +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x1UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x1UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY2_Pos 0U /*!< TPI ITATBCTR2: ATREADY2 Position */ +#define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/) /*!< TPI ITATBCTR2: ATREADY2 Mask */ + +#define TPI_ITATBCTR2_ATREADY1_Pos 0U /*!< TPI ITATBCTR2: ATREADY1 Position */ +#define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/) /*!< TPI ITATBCTR2: ATREADY1 Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x1UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x1UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY2_Pos 0U /*!< TPI ITATBCTR0: ATREADY2 Position */ +#define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/) /*!< TPI ITATBCTR0: ATREADY2 Mask */ + +#define TPI_ITATBCTR0_ATREADY1_Pos 0U /*!< TPI ITATBCTR0: ATREADY1 Position */ +#define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/) /*!< TPI ITATBCTR0: ATREADY1 Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif /* defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and FP Feature Register 2 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and FP Feature Register 0 Definitions */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and FP Feature Register 1 Definitions */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/* Media and FP Feature Register 2 Definitions */ + +#define FPU_MVFR2_VFP_Misc_Pos 4U /*!< MVFR2: VFP Misc bits Position */ +#define FPU_MVFR2_VFP_Misc_Msk (0xFUL << FPU_MVFR2_VFP_Misc_Pos) /*!< MVFR2: VFP Misc bits Mask */ + +/*@} end of group CMSIS_FPU */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +#define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ +#define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ +#define EXC_RETURN_HANDLER_FPU (0xFFFFFFE1UL) /* return to Handler mode, uses MSP after return, restore floating-point state */ +#define EXC_RETURN_THREAD_MSP_FPU (0xFFFFFFE9UL) /* return to Thread mode, uses MSP after return, restore floating-point state */ +#define EXC_RETURN_THREAD_PSP_FPU (0xFFFFFFEDUL) /* return to Thread mode, uses PSP after return, restore floating-point state */ + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + /* ARM Application Note 321 states that the M4 does not require the architectural barrier */ +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv7.h" + +#endif + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = FPU->MVFR0; + if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM4_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/CMSIS/Core/Include/core_cm55.h b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/CMSIS/Core/Include/core_cm55.h new file mode 100644 index 0000000000..faa30ce36a --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/CMSIS/Core/Include/core_cm55.h @@ -0,0 +1,4817 @@ +/**************************************************************************//** + * @file core_cm55.h + * @brief CMSIS Cortex-M55 Core Peripheral Access Layer Header File + * @version V1.2.4 + * @date 21. April 2022 + ******************************************************************************/ +/* + * Copyright (c) 2018-2022 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#elif defined ( __GNUC__ ) + #pragma GCC diagnostic ignored "-Wpedantic" /* disable pedantic warning due to unnamed structs/unions */ +#endif + +#ifndef __CORE_CM55_H_GENERIC +#define __CORE_CM55_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M55 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM55 definitions */ +#define __CM55_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM55_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM55_CMSIS_VERSION ((__CM55_CMSIS_VERSION_MAIN << 16U) | \ + __CM55_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (55U) /*!< Cortex-M Core */ + +#if defined ( __CC_ARM ) + #error Legacy Arm Compiler does not support Armv8.1-M target architecture. +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM55_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM55_H_DEPENDANT +#define __CORE_CM55_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM55_REV + #define __CM55_REV 0x0000U + #warning "__CM55_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #if __FPU_PRESENT != 0U + #ifndef __FPU_DP + #define __FPU_DP 0U + #warning "__FPU_DP not defined in device header file; using default!" + #endif + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __ICACHE_PRESENT + #define __ICACHE_PRESENT 0U + #warning "__ICACHE_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DCACHE_PRESENT + #define __DCACHE_PRESENT 0U + #warning "__DCACHE_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 1U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __PMU_PRESENT + #define __PMU_PRESENT 0U + #warning "__PMU_PRESENT not defined in device header file; using default!" + #endif + + #if __PMU_PRESENT != 0U + #ifndef __PMU_NUM_EVENTCNT + #define __PMU_NUM_EVENTCNT 8U + #warning "__PMU_NUM_EVENTCNT not defined in device header file; using default!" + #elif (__PMU_NUM_EVENTCNT > 8 || __PMU_NUM_EVENTCNT < 2) + #error "__PMU_NUM_EVENTCNT is out of range in device header file!" */ + #endif + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DSP_PRESENT + #define __DSP_PRESENT 0U + #warning "__DSP_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M55 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core EWIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core PMU Register + - Core MPU Register + - Core SAU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ +#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */ + uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */ + uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */ +#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */ + +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED6[580U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ + __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ + __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ + __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */ + uint32_t RESERVED7[21U]; + __IOM uint32_t SFSR; /*!< Offset: 0x0E4 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x0E8 (R/W) Secure Fault Address Register */ + uint32_t RESERVED3[69U]; + __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ + __IOM uint32_t RFSR; /*!< Offset: 0x204 (R/W) RAS Fault Status Register */ + uint32_t RESERVED4[14U]; + __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ + uint32_t RESERVED5[1U]; + __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ + uint32_t RESERVED6[1U]; + __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ + __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ + __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ + __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ + __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ + __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ + __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ + __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ + __OM uint32_t BPIALL; /*!< Offset: 0x278 ( /W) Branch Predictor Invalidate All */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ +#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_IESB_Pos 5U /*!< SCB AIRCR: Implicit ESB Enable Position */ +#define SCB_AIRCR_IESB_Msk (1UL << SCB_AIRCR_IESB_Pos) /*!< SCB AIRCR: Implicit ESB Enable Mask */ + +#define SCB_AIRCR_DIT_Pos 4U /*!< SCB AIRCR: Data Independent Timing Position */ +#define SCB_AIRCR_DIT_Msk (1UL << SCB_AIRCR_DIT_Pos) /*!< SCB AIRCR: Data Independent Timing Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_TRD_Pos 20U /*!< SCB CCR: TRD Position */ +#define SCB_CCR_TRD_Msk (1UL << SCB_CCR_TRD_Pos) /*!< SCB CCR: TRD Mask */ + +#define SCB_CCR_LOB_Pos 19U /*!< SCB CCR: LOB Position */ +#define SCB_CCR_LOB_Msk (1UL << SCB_CCR_LOB_Pos) /*!< SCB CCR: LOB Mask */ + +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */ +#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */ +#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */ + +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */ +#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_CFSR_MEMFAULTSR_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */ +#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_PMU_Pos 5U /*!< SCB DFSR: PMU Position */ +#define SCB_DFSR_PMU_Msk (1UL << SCB_DFSR_PMU_Pos) /*!< SCB DFSR: PMU Mask */ + +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/* SCB Non-Secure Access Control Register Definitions */ +#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */ +#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */ + +#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */ +#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */ + +#define SCB_NSACR_CP7_Pos 7U /*!< SCB NSACR: CP7 Position */ +#define SCB_NSACR_CP7_Msk (1UL << SCB_NSACR_CP7_Pos) /*!< SCB NSACR: CP7 Mask */ + +#define SCB_NSACR_CP6_Pos 6U /*!< SCB NSACR: CP6 Position */ +#define SCB_NSACR_CP6_Msk (1UL << SCB_NSACR_CP6_Pos) /*!< SCB NSACR: CP6 Mask */ + +#define SCB_NSACR_CP5_Pos 5U /*!< SCB NSACR: CP5 Position */ +#define SCB_NSACR_CP5_Msk (1UL << SCB_NSACR_CP5_Pos) /*!< SCB NSACR: CP5 Mask */ + +#define SCB_NSACR_CP4_Pos 4U /*!< SCB NSACR: CP4 Position */ +#define SCB_NSACR_CP4_Msk (1UL << SCB_NSACR_CP4_Pos) /*!< SCB NSACR: CP4 Mask */ + +#define SCB_NSACR_CP3_Pos 3U /*!< SCB NSACR: CP3 Position */ +#define SCB_NSACR_CP3_Msk (1UL << SCB_NSACR_CP3_Pos) /*!< SCB NSACR: CP3 Mask */ + +#define SCB_NSACR_CP2_Pos 2U /*!< SCB NSACR: CP2 Position */ +#define SCB_NSACR_CP2_Msk (1UL << SCB_NSACR_CP2_Pos) /*!< SCB NSACR: CP2 Mask */ + +#define SCB_NSACR_CP1_Pos 1U /*!< SCB NSACR: CP1 Position */ +#define SCB_NSACR_CP1_Msk (1UL << SCB_NSACR_CP1_Pos) /*!< SCB NSACR: CP1 Mask */ + +#define SCB_NSACR_CP0_Pos 0U /*!< SCB NSACR: CP0 Position */ +#define SCB_NSACR_CP0_Msk (1UL /*<< SCB_NSACR_CP0_Pos*/) /*!< SCB NSACR: CP0 Mask */ + +/* SCB Debug Feature Register 0 Definitions */ +#define SCB_ID_DFR_UDE_Pos 28U /*!< SCB ID_DFR: UDE Position */ +#define SCB_ID_DFR_UDE_Msk (0xFUL << SCB_ID_DFR_UDE_Pos) /*!< SCB ID_DFR: UDE Mask */ + +#define SCB_ID_DFR_MProfDbg_Pos 20U /*!< SCB ID_DFR: MProfDbg Position */ +#define SCB_ID_DFR_MProfDbg_Msk (0xFUL << SCB_ID_DFR_MProfDbg_Pos) /*!< SCB ID_DFR: MProfDbg Mask */ + +/* SCB Cache Level ID Register Definitions */ +#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ +#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ + +#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ +#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ + +/* SCB Cache Type Register Definitions */ +#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ +#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ + +#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ +#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ + +#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ +#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ + +#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ +#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ + +#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ +#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ + +/* SCB Cache Size ID Register Definitions */ +#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ +#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ + +#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ +#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ + +#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ +#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ + +#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ +#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ + +#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ +#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ + +#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ +#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ + +#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ +#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ + +/* SCB Cache Size Selection Register Definitions */ +#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ +#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ + +#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ +#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ + +/* SCB Software Triggered Interrupt Register Definitions */ +#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ +#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ + +/* SCB RAS Fault Status Register Definitions */ +#define SCB_RFSR_V_Pos 31U /*!< SCB RFSR: V Position */ +#define SCB_RFSR_V_Msk (1UL << SCB_RFSR_V_Pos) /*!< SCB RFSR: V Mask */ + +#define SCB_RFSR_IS_Pos 16U /*!< SCB RFSR: IS Position */ +#define SCB_RFSR_IS_Msk (0x7FFFUL << SCB_RFSR_IS_Pos) /*!< SCB RFSR: IS Mask */ + +#define SCB_RFSR_UET_Pos 0U /*!< SCB RFSR: UET Position */ +#define SCB_RFSR_UET_Msk (3UL /*<< SCB_RFSR_UET_Pos*/) /*!< SCB RFSR: UET Mask */ + +/* SCB D-Cache Invalidate by Set-way Register Definitions */ +#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ +#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ + +#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ +#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ + +/* SCB D-Cache Clean by Set-way Register Definitions */ +#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ +#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ + +#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ +#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ + +/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ +#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ +#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ + +#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ +#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ICB Implementation Control Block register (ICB) + \brief Type definitions for the Implementation Control Block Register + @{ + */ + +/** + \brief Structure type to access the Implementation Control Block (ICB). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ + __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */ +} ICB_Type; + +/* Auxiliary Control Register Definitions */ +#define ICB_ACTLR_DISCRITAXIRUW_Pos 27U /*!< ACTLR: DISCRITAXIRUW Position */ +#define ICB_ACTLR_DISCRITAXIRUW_Msk (1UL << ICB_ACTLR_DISCRITAXIRUW_Pos) /*!< ACTLR: DISCRITAXIRUW Mask */ + +#define ICB_ACTLR_DISDI_Pos 16U /*!< ACTLR: DISDI Position */ +#define ICB_ACTLR_DISDI_Msk (3UL << ICB_ACTLR_DISDI_Pos) /*!< ACTLR: DISDI Mask */ + +#define ICB_ACTLR_DISCRITAXIRUR_Pos 15U /*!< ACTLR: DISCRITAXIRUR Position */ +#define ICB_ACTLR_DISCRITAXIRUR_Msk (1UL << ICB_ACTLR_DISCRITAXIRUR_Pos) /*!< ACTLR: DISCRITAXIRUR Mask */ + +#define ICB_ACTLR_EVENTBUSEN_Pos 14U /*!< ACTLR: EVENTBUSEN Position */ +#define ICB_ACTLR_EVENTBUSEN_Msk (1UL << ICB_ACTLR_EVENTBUSEN_Pos) /*!< ACTLR: EVENTBUSEN Mask */ + +#define ICB_ACTLR_EVENTBUSEN_S_Pos 13U /*!< ACTLR: EVENTBUSEN_S Position */ +#define ICB_ACTLR_EVENTBUSEN_S_Msk (1UL << ICB_ACTLR_EVENTBUSEN_S_Pos) /*!< ACTLR: EVENTBUSEN_S Mask */ + +#define ICB_ACTLR_DISITMATBFLUSH_Pos 12U /*!< ACTLR: DISITMATBFLUSH Position */ +#define ICB_ACTLR_DISITMATBFLUSH_Msk (1UL << ICB_ACTLR_DISITMATBFLUSH_Pos) /*!< ACTLR: DISITMATBFLUSH Mask */ + +#define ICB_ACTLR_DISNWAMODE_Pos 11U /*!< ACTLR: DISNWAMODE Position */ +#define ICB_ACTLR_DISNWAMODE_Msk (1UL << ICB_ACTLR_DISNWAMODE_Pos) /*!< ACTLR: DISNWAMODE Mask */ + +#define ICB_ACTLR_FPEXCODIS_Pos 10U /*!< ACTLR: FPEXCODIS Position */ +#define ICB_ACTLR_FPEXCODIS_Msk (1UL << ICB_ACTLR_FPEXCODIS_Pos) /*!< ACTLR: FPEXCODIS Mask */ + +#define ICB_ACTLR_DISOLAP_Pos 7U /*!< ACTLR: DISOLAP Position */ +#define ICB_ACTLR_DISOLAP_Msk (1UL << ICB_ACTLR_DISOLAP_Pos) /*!< ACTLR: DISOLAP Mask */ + +#define ICB_ACTLR_DISOLAPS_Pos 6U /*!< ACTLR: DISOLAPS Position */ +#define ICB_ACTLR_DISOLAPS_Msk (1UL << ICB_ACTLR_DISOLAPS_Pos) /*!< ACTLR: DISOLAPS Mask */ + +#define ICB_ACTLR_DISLOBR_Pos 5U /*!< ACTLR: DISLOBR Position */ +#define ICB_ACTLR_DISLOBR_Msk (1UL << ICB_ACTLR_DISLOBR_Pos) /*!< ACTLR: DISLOBR Mask */ + +#define ICB_ACTLR_DISLO_Pos 4U /*!< ACTLR: DISLO Position */ +#define ICB_ACTLR_DISLO_Msk (1UL << ICB_ACTLR_DISLO_Pos) /*!< ACTLR: DISLO Mask */ + +#define ICB_ACTLR_DISLOLEP_Pos 3U /*!< ACTLR: DISLOLEP Position */ +#define ICB_ACTLR_DISLOLEP_Msk (1UL << ICB_ACTLR_DISLOLEP_Pos) /*!< ACTLR: DISLOLEP Mask */ + +#define ICB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ +#define ICB_ACTLR_DISFOLD_Msk (1UL << ICB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +/* Interrupt Controller Type Register Definitions */ +#define ICB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define ICB_ICTR_INTLINESNUM_Msk (0xFUL /*<< ICB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_ICB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */ + uint32_t RESERVED6[3U]; + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) ITM Device Type Register */ + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Stimulus Port Register Definitions */ +#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */ +#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */ + +#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */ +#define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */ + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */ +#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */ + +#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */ +#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED14[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED15[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED16[1U]; + __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ + uint32_t RESERVED17[1U]; + __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ + uint32_t RESERVED18[1U]; + __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ + uint32_t RESERVED19[1U]; + __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ + uint32_t RESERVED20[1U]; + __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ + uint32_t RESERVED21[1U]; + __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ + uint32_t RESERVED22[1U]; + __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ + uint32_t RESERVED23[1U]; + __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ + uint32_t RESERVED24[1U]; + __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ + uint32_t RESERVED25[1U]; + __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ + uint32_t RESERVED26[1U]; + __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ + uint32_t RESERVED27[1U]; + __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ + uint32_t RESERVED28[1U]; + __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ + uint32_t RESERVED29[1U]; + __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ + uint32_t RESERVED30[1U]; + __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ + uint32_t RESERVED31[1U]; + __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ + uint32_t RESERVED32[934U]; + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ + uint32_t RESERVED33[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */ +#define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup MemSysCtl_Type Memory System Control Registers (IMPLEMENTATION DEFINED) + \brief Type definitions for the Memory System Control Registers (MEMSYSCTL) + @{ + */ + +/** + \brief Structure type to access the Memory System Control Registers (MEMSYSCTL). + */ +typedef struct +{ + __IOM uint32_t MSCR; /*!< Offset: 0x000 (R/W) Memory System Control Register */ + __IOM uint32_t PFCR; /*!< Offset: 0x004 (R/W) Prefetcher Control Register */ + uint32_t RESERVED1[2U]; + __IOM uint32_t ITCMCR; /*!< Offset: 0x010 (R/W) ITCM Control Register */ + __IOM uint32_t DTCMCR; /*!< Offset: 0x014 (R/W) DTCM Control Register */ + __IOM uint32_t PAHBCR; /*!< Offset: 0x018 (R/W) P-AHB Control Register */ + uint32_t RESERVED2[313U]; + __IOM uint32_t ITGU_CTRL; /*!< Offset: 0x500 (R/W) ITGU Control Register */ + __IOM uint32_t ITGU_CFG; /*!< Offset: 0x504 (R/W) ITGU Configuration Register */ + uint32_t RESERVED3[2U]; + __IOM uint32_t ITGU_LUT[16U]; /*!< Offset: 0x510 (R/W) ITGU Look Up Table Register */ + uint32_t RESERVED4[44U]; + __IOM uint32_t DTGU_CTRL; /*!< Offset: 0x600 (R/W) DTGU Control Registers */ + __IOM uint32_t DTGU_CFG; /*!< Offset: 0x604 (R/W) DTGU Configuration Register */ + uint32_t RESERVED5[2U]; + __IOM uint32_t DTGU_LUT[16U]; /*!< Offset: 0x610 (R/W) DTGU Look Up Table Register */ +} MemSysCtl_Type; + +/* MEMSYSCTL Memory System Control Register (MSCR) Register Definitions */ +#define MEMSYSCTL_MSCR_CPWRDN_Pos 17U /*!< MEMSYSCTL MSCR: CPWRDN Position */ +#define MEMSYSCTL_MSCR_CPWRDN_Msk (0x1UL << MEMSYSCTL_MSCR_CPWRDN_Pos) /*!< MEMSYSCTL MSCR: CPWRDN Mask */ + +#define MEMSYSCTL_MSCR_DCCLEAN_Pos 16U /*!< MEMSYSCTL MSCR: DCCLEAN Position */ +#define MEMSYSCTL_MSCR_DCCLEAN_Msk (0x1UL << MEMSYSCTL_MSCR_DCCLEAN_Pos) /*!< MEMSYSCTL MSCR: DCCLEAN Mask */ + +#define MEMSYSCTL_MSCR_ICACTIVE_Pos 13U /*!< MEMSYSCTL MSCR: ICACTIVE Position */ +#define MEMSYSCTL_MSCR_ICACTIVE_Msk (0x1UL << MEMSYSCTL_MSCR_ICACTIVE_Pos) /*!< MEMSYSCTL MSCR: ICACTIVE Mask */ + +#define MEMSYSCTL_MSCR_DCACTIVE_Pos 12U /*!< MEMSYSCTL MSCR: DCACTIVE Position */ +#define MEMSYSCTL_MSCR_DCACTIVE_Msk (0x1UL << MEMSYSCTL_MSCR_DCACTIVE_Pos) /*!< MEMSYSCTL MSCR: DCACTIVE Mask */ + +#define MEMSYSCTL_MSCR_TECCCHKDIS_Pos 4U /*!< MEMSYSCTL MSCR: TECCCHKDIS Position */ +#define MEMSYSCTL_MSCR_TECCCHKDIS_Msk (0x1UL << MEMSYSCTL_MSCR_TECCCHKDIS_Pos) /*!< MEMSYSCTL MSCR: TECCCHKDIS Mask */ + +#define MEMSYSCTL_MSCR_EVECCFAULT_Pos 3U /*!< MEMSYSCTL MSCR: EVECCFAULT Position */ +#define MEMSYSCTL_MSCR_EVECCFAULT_Msk (0x1UL << MEMSYSCTL_MSCR_EVECCFAULT_Pos) /*!< MEMSYSCTL MSCR: EVECCFAULT Mask */ + +#define MEMSYSCTL_MSCR_FORCEWT_Pos 2U /*!< MEMSYSCTL MSCR: FORCEWT Position */ +#define MEMSYSCTL_MSCR_FORCEWT_Msk (0x1UL << MEMSYSCTL_MSCR_FORCEWT_Pos) /*!< MEMSYSCTL MSCR: FORCEWT Mask */ + +#define MEMSYSCTL_MSCR_ECCEN_Pos 1U /*!< MEMSYSCTL MSCR: ECCEN Position */ +#define MEMSYSCTL_MSCR_ECCEN_Msk (0x1UL << MEMSYSCTL_MSCR_ECCEN_Pos) /*!< MEMSYSCTL MSCR: ECCEN Mask */ + +/* MEMSYSCTL Prefetcher Control Register (PFCR) Register Definitions */ +#define MEMSYSCTL_PFCR_MAX_OS_Pos 7U /*!< MEMSYSCTL PFCR: MAX_OS Position */ +#define MEMSYSCTL_PFCR_MAX_OS_Msk (0x7UL << MEMSYSCTL_PFCR_MAX_OS_Pos) /*!< MEMSYSCTL PFCR: MAX_OS Mask */ + +#define MEMSYSCTL_PFCR_MAX_LA_Pos 4U /*!< MEMSYSCTL PFCR: MAX_LA Position */ +#define MEMSYSCTL_PFCR_MAX_LA_Msk (0x7UL << MEMSYSCTL_PFCR_MAX_LA_Pos) /*!< MEMSYSCTL PFCR: MAX_LA Mask */ + +#define MEMSYSCTL_PFCR_MIN_LA_Pos 1U /*!< MEMSYSCTL PFCR: MIN_LA Position */ +#define MEMSYSCTL_PFCR_MIN_LA_Msk (0x7UL << MEMSYSCTL_PFCR_MIN_LA_Pos) /*!< MEMSYSCTL PFCR: MIN_LA Mask */ + +#define MEMSYSCTL_PFCR_ENABLE_Pos 0U /*!< MEMSYSCTL PFCR: ENABLE Position */ +#define MEMSYSCTL_PFCR_ENABLE_Msk (0x1UL /*<< MEMSYSCTL_PFCR_ENABLE_Pos*/) /*!< MEMSYSCTL PFCR: ENABLE Mask */ + +/* MEMSYSCTL ITCM Control Register (ITCMCR) Register Definitions */ +#define MEMSYSCTL_ITCMCR_SZ_Pos 3U /*!< MEMSYSCTL ITCMCR: SZ Position */ +#define MEMSYSCTL_ITCMCR_SZ_Msk (0xFUL << MEMSYSCTL_ITCMCR_SZ_Pos) /*!< MEMSYSCTL ITCMCR: SZ Mask */ + +#define MEMSYSCTL_ITCMCR_EN_Pos 0U /*!< MEMSYSCTL ITCMCR: EN Position */ +#define MEMSYSCTL_ITCMCR_EN_Msk (0x1UL /*<< MEMSYSCTL_ITCMCR_EN_Pos*/) /*!< MEMSYSCTL ITCMCR: EN Mask */ + +/* MEMSYSCTL DTCM Control Register (DTCMCR) Register Definitions */ +#define MEMSYSCTL_DTCMCR_SZ_Pos 3U /*!< MEMSYSCTL DTCMCR: SZ Position */ +#define MEMSYSCTL_DTCMCR_SZ_Msk (0xFUL << MEMSYSCTL_DTCMCR_SZ_Pos) /*!< MEMSYSCTL DTCMCR: SZ Mask */ + +#define MEMSYSCTL_DTCMCR_EN_Pos 0U /*!< MEMSYSCTL DTCMCR: EN Position */ +#define MEMSYSCTL_DTCMCR_EN_Msk (0x1UL /*<< MEMSYSCTL_DTCMCR_EN_Pos*/) /*!< MEMSYSCTL DTCMCR: EN Mask */ + +/* MEMSYSCTL P-AHB Control Register (PAHBCR) Register Definitions */ +#define MEMSYSCTL_PAHBCR_SZ_Pos 1U /*!< MEMSYSCTL PAHBCR: SZ Position */ +#define MEMSYSCTL_PAHBCR_SZ_Msk (0x7UL << MEMSYSCTL_PAHBCR_SZ_Pos) /*!< MEMSYSCTL PAHBCR: SZ Mask */ + +#define MEMSYSCTL_PAHBCR_EN_Pos 0U /*!< MEMSYSCTL PAHBCR: EN Position */ +#define MEMSYSCTL_PAHBCR_EN_Msk (0x1UL /*<< MEMSYSCTL_PAHBCR_EN_Pos*/) /*!< MEMSYSCTL PAHBCR: EN Mask */ + +/* MEMSYSCTL ITGU Control Register (ITGU_CTRL) Register Definitions */ +#define MEMSYSCTL_ITGU_CTRL_DEREN_Pos 1U /*!< MEMSYSCTL ITGU_CTRL: DEREN Position */ +#define MEMSYSCTL_ITGU_CTRL_DEREN_Msk (0x1UL << MEMSYSCTL_ITGU_CTRL_DEREN_Pos) /*!< MEMSYSCTL ITGU_CTRL: DEREN Mask */ + +#define MEMSYSCTL_ITGU_CTRL_DBFEN_Pos 0U /*!< MEMSYSCTL ITGU_CTRL: DBFEN Position */ +#define MEMSYSCTL_ITGU_CTRL_DBFEN_Msk (0x1UL /*<< MEMSYSCTL_ITGU_CTRL_DBFEN_Pos*/) /*!< MEMSYSCTL ITGU_CTRL: DBFEN Mask */ + +/* MEMSYSCTL ITGU Configuration Register (ITGU_CFG) Register Definitions */ +#define MEMSYSCTL_ITGU_CFG_PRESENT_Pos 31U /*!< MEMSYSCTL ITGU_CFG: PRESENT Position */ +#define MEMSYSCTL_ITGU_CFG_PRESENT_Msk (0x1UL << MEMSYSCTL_ITGU_CFG_PRESENT_Pos) /*!< MEMSYSCTL ITGU_CFG: PRESENT Mask */ + +#define MEMSYSCTL_ITGU_CFG_NUMBLKS_Pos 8U /*!< MEMSYSCTL ITGU_CFG: NUMBLKS Position */ +#define MEMSYSCTL_ITGU_CFG_NUMBLKS_Msk (0xFUL << MEMSYSCTL_ITGU_CFG_NUMBLKS_Pos) /*!< MEMSYSCTL ITGU_CFG: NUMBLKS Mask */ + +#define MEMSYSCTL_ITGU_CFG_BLKSZ_Pos 0U /*!< MEMSYSCTL ITGU_CFG: BLKSZ Position */ +#define MEMSYSCTL_ITGU_CFG_BLKSZ_Msk (0xFUL /*<< MEMSYSCTL_ITGU_CFG_BLKSZ_Pos*/) /*!< MEMSYSCTL ITGU_CFG: BLKSZ Mask */ + +/* MEMSYSCTL DTGU Control Registers (DTGU_CTRL) Register Definitions */ +#define MEMSYSCTL_DTGU_CTRL_DEREN_Pos 1U /*!< MEMSYSCTL DTGU_CTRL: DEREN Position */ +#define MEMSYSCTL_DTGU_CTRL_DEREN_Msk (0x1UL << MEMSYSCTL_DTGU_CTRL_DEREN_Pos) /*!< MEMSYSCTL DTGU_CTRL: DEREN Mask */ + +#define MEMSYSCTL_DTGU_CTRL_DBFEN_Pos 0U /*!< MEMSYSCTL DTGU_CTRL: DBFEN Position */ +#define MEMSYSCTL_DTGU_CTRL_DBFEN_Msk (0x1UL /*<< MEMSYSCTL_DTGU_CTRL_DBFEN_Pos*/) /*!< MEMSYSCTL DTGU_CTRL: DBFEN Mask */ + +/* MEMSYSCTL DTGU Configuration Register (DTGU_CFG) Register Definitions */ +#define MEMSYSCTL_DTGU_CFG_PRESENT_Pos 31U /*!< MEMSYSCTL DTGU_CFG: PRESENT Position */ +#define MEMSYSCTL_DTGU_CFG_PRESENT_Msk (0x1UL << MEMSYSCTL_DTGU_CFG_PRESENT_Pos) /*!< MEMSYSCTL DTGU_CFG: PRESENT Mask */ + +#define MEMSYSCTL_DTGU_CFG_NUMBLKS_Pos 8U /*!< MEMSYSCTL DTGU_CFG: NUMBLKS Position */ +#define MEMSYSCTL_DTGU_CFG_NUMBLKS_Msk (0xFUL << MEMSYSCTL_DTGU_CFG_NUMBLKS_Pos) /*!< MEMSYSCTL DTGU_CFG: NUMBLKS Mask */ + +#define MEMSYSCTL_DTGU_CFG_BLKSZ_Pos 0U /*!< MEMSYSCTL DTGU_CFG: BLKSZ Position */ +#define MEMSYSCTL_DTGU_CFG_BLKSZ_Msk (0xFUL /*<< MEMSYSCTL_DTGU_CFG_BLKSZ_Pos*/) /*!< MEMSYSCTL DTGU_CFG: BLKSZ Mask */ + + +/*@}*/ /* end of group MemSysCtl_Type */ + + +/** + \ingroup CMSIS_core_register + \defgroup PwrModCtl_Type Power Mode Control Registers + \brief Type definitions for the Power Mode Control Registers (PWRMODCTL) + @{ + */ + +/** + \brief Structure type to access the Power Mode Control Registers (PWRMODCTL). + */ +typedef struct +{ + __IOM uint32_t CPDLPSTATE; /*!< Offset: 0x000 (R/W) Core Power Domain Low Power State Register */ + __IOM uint32_t DPDLPSTATE; /*!< Offset: 0x004 (R/W) Debug Power Domain Low Power State Register */ +} PwrModCtl_Type; + +/* PWRMODCTL Core Power Domain Low Power State (CPDLPSTATE) Register Definitions */ +#define PWRMODCTL_CPDLPSTATE_RLPSTATE_Pos 8U /*!< PWRMODCTL CPDLPSTATE: RLPSTATE Position */ +#define PWRMODCTL_CPDLPSTATE_RLPSTATE_Msk (0x3UL << PWRMODCTL_CPDLPSTATE_RLPSTATE_Pos) /*!< PWRMODCTL CPDLPSTATE: RLPSTATE Mask */ + +#define PWRMODCTL_CPDLPSTATE_ELPSTATE_Pos 4U /*!< PWRMODCTL CPDLPSTATE: ELPSTATE Position */ +#define PWRMODCTL_CPDLPSTATE_ELPSTATE_Msk (0x3UL << PWRMODCTL_CPDLPSTATE_ELPSTATE_Pos) /*!< PWRMODCTL CPDLPSTATE: ELPSTATE Mask */ + +#define PWRMODCTL_CPDLPSTATE_CLPSTATE_Pos 0U /*!< PWRMODCTL CPDLPSTATE: CLPSTATE Position */ +#define PWRMODCTL_CPDLPSTATE_CLPSTATE_Msk (0x3UL /*<< PWRMODCTL_CPDLPSTATE_CLPSTATE_Pos*/) /*!< PWRMODCTL CPDLPSTATE: CLPSTATE Mask */ + +/* PWRMODCTL Debug Power Domain Low Power State (DPDLPSTATE) Register Definitions */ +#define PWRMODCTL_DPDLPSTATE_DLPSTATE_Pos 0U /*!< PWRMODCTL DPDLPSTATE: DLPSTATE Position */ +#define PWRMODCTL_DPDLPSTATE_DLPSTATE_Msk (0x3UL /*<< PWRMODCTL_DPDLPSTATE_DLPSTATE_Pos*/) /*!< PWRMODCTL DPDLPSTATE: DLPSTATE Mask */ + +/*@}*/ /* end of group PwrModCtl_Type */ + + +/** + \ingroup CMSIS_core_register + \defgroup EWIC_Type External Wakeup Interrupt Controller Registers + \brief Type definitions for the External Wakeup Interrupt Controller Registers (EWIC) + @{ + */ + +/** + \brief Structure type to access the External Wakeup Interrupt Controller Registers (EWIC). + */ +typedef struct +{ + __OM uint32_t EVENTSPR; /*!< Offset: 0x000 ( /W) Event Set Pending Register */ + uint32_t RESERVED0[31U]; + __IM uint32_t EVENTMASKA; /*!< Offset: 0x080 (R/W) Event Mask A Register */ + __IM uint32_t EVENTMASK[15]; /*!< Offset: 0x084 (R/W) Event Mask Register */ +} EWIC_Type; + +/* EWIC External Wakeup Interrupt Controller (EVENTSPR) Register Definitions */ +#define EWIC_EVENTSPR_EDBGREQ_Pos 2U /*!< EWIC EVENTSPR: EDBGREQ Position */ +#define EWIC_EVENTSPR_EDBGREQ_Msk (0x1UL << EWIC_EVENTSPR_EDBGREQ_Pos) /*!< EWIC EVENTSPR: EDBGREQ Mask */ + +#define EWIC_EVENTSPR_NMI_Pos 1U /*!< EWIC EVENTSPR: NMI Position */ +#define EWIC_EVENTSPR_NMI_Msk (0x1UL << EWIC_EVENTSPR_NMI_Pos) /*!< EWIC EVENTSPR: NMI Mask */ + +#define EWIC_EVENTSPR_EVENT_Pos 0U /*!< EWIC EVENTSPR: EVENT Position */ +#define EWIC_EVENTSPR_EVENT_Msk (0x1UL /*<< EWIC_EVENTSPR_EVENT_Pos*/) /*!< EWIC EVENTSPR: EVENT Mask */ + +/* EWIC External Wakeup Interrupt Controller (EVENTMASKA) Register Definitions */ +#define EWIC_EVENTMASKA_EDBGREQ_Pos 2U /*!< EWIC EVENTMASKA: EDBGREQ Position */ +#define EWIC_EVENTMASKA_EDBGREQ_Msk (0x1UL << EWIC_EVENTMASKA_EDBGREQ_Pos) /*!< EWIC EVENTMASKA: EDBGREQ Mask */ + +#define EWIC_EVENTMASKA_NMI_Pos 1U /*!< EWIC EVENTMASKA: NMI Position */ +#define EWIC_EVENTMASKA_NMI_Msk (0x1UL << EWIC_EVENTMASKA_NMI_Pos) /*!< EWIC EVENTMASKA: NMI Mask */ + +#define EWIC_EVENTMASKA_EVENT_Pos 0U /*!< EWIC EVENTMASKA: EVENT Position */ +#define EWIC_EVENTMASKA_EVENT_Msk (0x1UL /*<< EWIC_EVENTMASKA_EVENT_Pos*/) /*!< EWIC EVENTMASKA: EVENT Mask */ + +/* EWIC External Wakeup Interrupt Controller (EVENTMASK) Register Definitions */ +#define EWIC_EVENTMASK_IRQ_Pos 0U /*!< EWIC EVENTMASKA: IRQ Position */ +#define EWIC_EVENTMASK_IRQ_Msk (0xFFFFFFFFUL /*<< EWIC_EVENTMASKA_IRQ_Pos*/) /*!< EWIC EVENTMASKA: IRQ Mask */ + +/*@}*/ /* end of group EWIC_Type */ + + +/** + \ingroup CMSIS_core_register + \defgroup ErrBnk_Type Error Banking Registers (IMPLEMENTATION DEFINED) + \brief Type definitions for the Error Banking Registers (ERRBNK) + @{ + */ + +/** + \brief Structure type to access the Error Banking Registers (ERRBNK). + */ +typedef struct +{ + __IOM uint32_t IEBR0; /*!< Offset: 0x000 (R/W) Instruction Cache Error Bank Register 0 */ + __IOM uint32_t IEBR1; /*!< Offset: 0x004 (R/W) Instruction Cache Error Bank Register 1 */ + uint32_t RESERVED0[2U]; + __IOM uint32_t DEBR0; /*!< Offset: 0x010 (R/W) Data Cache Error Bank Register 0 */ + __IOM uint32_t DEBR1; /*!< Offset: 0x014 (R/W) Data Cache Error Bank Register 1 */ + uint32_t RESERVED1[2U]; + __IOM uint32_t TEBR0; /*!< Offset: 0x020 (R/W) TCM Error Bank Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t TEBR1; /*!< Offset: 0x028 (R/W) TCM Error Bank Register 1 */ +} ErrBnk_Type; + +/* ERRBNK Instruction Cache Error Bank Register 0 (IEBR0) Register Definitions */ +#define ERRBNK_IEBR0_SWDEF_Pos 30U /*!< ERRBNK IEBR0: SWDEF Position */ +#define ERRBNK_IEBR0_SWDEF_Msk (0x3UL << ERRBNK_IEBR0_SWDEF_Pos) /*!< ERRBNK IEBR0: SWDEF Mask */ + +#define ERRBNK_IEBR0_BANK_Pos 16U /*!< ERRBNK IEBR0: BANK Position */ +#define ERRBNK_IEBR0_BANK_Msk (0x1UL << ERRBNK_IEBR0_BANK_Pos) /*!< ERRBNK IEBR0: BANK Mask */ + +#define ERRBNK_IEBR0_LOCATION_Pos 2U /*!< ERRBNK IEBR0: LOCATION Position */ +#define ERRBNK_IEBR0_LOCATION_Msk (0x3FFFUL << ERRBNK_IEBR0_LOCATION_Pos) /*!< ERRBNK IEBR0: LOCATION Mask */ + +#define ERRBNK_IEBR0_LOCKED_Pos 1U /*!< ERRBNK IEBR0: LOCKED Position */ +#define ERRBNK_IEBR0_LOCKED_Msk (0x1UL << ERRBNK_IEBR0_LOCKED_Pos) /*!< ERRBNK IEBR0: LOCKED Mask */ + +#define ERRBNK_IEBR0_VALID_Pos 0U /*!< ERRBNK IEBR0: VALID Position */ +#define ERRBNK_IEBR0_VALID_Msk (0x1UL << /*ERRBNK_IEBR0_VALID_Pos*/) /*!< ERRBNK IEBR0: VALID Mask */ + +/* ERRBNK Instruction Cache Error Bank Register 1 (IEBR1) Register Definitions */ +#define ERRBNK_IEBR1_SWDEF_Pos 30U /*!< ERRBNK IEBR1: SWDEF Position */ +#define ERRBNK_IEBR1_SWDEF_Msk (0x3UL << ERRBNK_IEBR1_SWDEF_Pos) /*!< ERRBNK IEBR1: SWDEF Mask */ + +#define ERRBNK_IEBR1_BANK_Pos 16U /*!< ERRBNK IEBR1: BANK Position */ +#define ERRBNK_IEBR1_BANK_Msk (0x1UL << ERRBNK_IEBR1_BANK_Pos) /*!< ERRBNK IEBR1: BANK Mask */ + +#define ERRBNK_IEBR1_LOCATION_Pos 2U /*!< ERRBNK IEBR1: LOCATION Position */ +#define ERRBNK_IEBR1_LOCATION_Msk (0x3FFFUL << ERRBNK_IEBR1_LOCATION_Pos) /*!< ERRBNK IEBR1: LOCATION Mask */ + +#define ERRBNK_IEBR1_LOCKED_Pos 1U /*!< ERRBNK IEBR1: LOCKED Position */ +#define ERRBNK_IEBR1_LOCKED_Msk (0x1UL << ERRBNK_IEBR1_LOCKED_Pos) /*!< ERRBNK IEBR1: LOCKED Mask */ + +#define ERRBNK_IEBR1_VALID_Pos 0U /*!< ERRBNK IEBR1: VALID Position */ +#define ERRBNK_IEBR1_VALID_Msk (0x1UL << /*ERRBNK_IEBR1_VALID_Pos*/) /*!< ERRBNK IEBR1: VALID Mask */ + +/* ERRBNK Data Cache Error Bank Register 0 (DEBR0) Register Definitions */ +#define ERRBNK_DEBR0_SWDEF_Pos 30U /*!< ERRBNK DEBR0: SWDEF Position */ +#define ERRBNK_DEBR0_SWDEF_Msk (0x3UL << ERRBNK_DEBR0_SWDEF_Pos) /*!< ERRBNK DEBR0: SWDEF Mask */ + +#define ERRBNK_DEBR0_TYPE_Pos 17U /*!< ERRBNK DEBR0: TYPE Position */ +#define ERRBNK_DEBR0_TYPE_Msk (0x1UL << ERRBNK_DEBR0_TYPE_Pos) /*!< ERRBNK DEBR0: TYPE Mask */ + +#define ERRBNK_DEBR0_BANK_Pos 16U /*!< ERRBNK DEBR0: BANK Position */ +#define ERRBNK_DEBR0_BANK_Msk (0x1UL << ERRBNK_DEBR0_BANK_Pos) /*!< ERRBNK DEBR0: BANK Mask */ + +#define ERRBNK_DEBR0_LOCATION_Pos 2U /*!< ERRBNK DEBR0: LOCATION Position */ +#define ERRBNK_DEBR0_LOCATION_Msk (0x3FFFUL << ERRBNK_DEBR0_LOCATION_Pos) /*!< ERRBNK DEBR0: LOCATION Mask */ + +#define ERRBNK_DEBR0_LOCKED_Pos 1U /*!< ERRBNK DEBR0: LOCKED Position */ +#define ERRBNK_DEBR0_LOCKED_Msk (0x1UL << ERRBNK_DEBR0_LOCKED_Pos) /*!< ERRBNK DEBR0: LOCKED Mask */ + +#define ERRBNK_DEBR0_VALID_Pos 0U /*!< ERRBNK DEBR0: VALID Position */ +#define ERRBNK_DEBR0_VALID_Msk (0x1UL << /*ERRBNK_DEBR0_VALID_Pos*/) /*!< ERRBNK DEBR0: VALID Mask */ + +/* ERRBNK Data Cache Error Bank Register 1 (DEBR1) Register Definitions */ +#define ERRBNK_DEBR1_SWDEF_Pos 30U /*!< ERRBNK DEBR1: SWDEF Position */ +#define ERRBNK_DEBR1_SWDEF_Msk (0x3UL << ERRBNK_DEBR1_SWDEF_Pos) /*!< ERRBNK DEBR1: SWDEF Mask */ + +#define ERRBNK_DEBR1_TYPE_Pos 17U /*!< ERRBNK DEBR1: TYPE Position */ +#define ERRBNK_DEBR1_TYPE_Msk (0x1UL << ERRBNK_DEBR1_TYPE_Pos) /*!< ERRBNK DEBR1: TYPE Mask */ + +#define ERRBNK_DEBR1_BANK_Pos 16U /*!< ERRBNK DEBR1: BANK Position */ +#define ERRBNK_DEBR1_BANK_Msk (0x1UL << ERRBNK_DEBR1_BANK_Pos) /*!< ERRBNK DEBR1: BANK Mask */ + +#define ERRBNK_DEBR1_LOCATION_Pos 2U /*!< ERRBNK DEBR1: LOCATION Position */ +#define ERRBNK_DEBR1_LOCATION_Msk (0x3FFFUL << ERRBNK_DEBR1_LOCATION_Pos) /*!< ERRBNK DEBR1: LOCATION Mask */ + +#define ERRBNK_DEBR1_LOCKED_Pos 1U /*!< ERRBNK DEBR1: LOCKED Position */ +#define ERRBNK_DEBR1_LOCKED_Msk (0x1UL << ERRBNK_DEBR1_LOCKED_Pos) /*!< ERRBNK DEBR1: LOCKED Mask */ + +#define ERRBNK_DEBR1_VALID_Pos 0U /*!< ERRBNK DEBR1: VALID Position */ +#define ERRBNK_DEBR1_VALID_Msk (0x1UL << /*ERRBNK_DEBR1_VALID_Pos*/) /*!< ERRBNK DEBR1: VALID Mask */ + +/* ERRBNK TCM Error Bank Register 0 (TEBR0) Register Definitions */ +#define ERRBNK_TEBR0_SWDEF_Pos 30U /*!< ERRBNK TEBR0: SWDEF Position */ +#define ERRBNK_TEBR0_SWDEF_Msk (0x3UL << ERRBNK_TEBR0_SWDEF_Pos) /*!< ERRBNK TEBR0: SWDEF Mask */ + +#define ERRBNK_TEBR0_POISON_Pos 28U /*!< ERRBNK TEBR0: POISON Position */ +#define ERRBNK_TEBR0_POISON_Msk (0x1UL << ERRBNK_TEBR0_POISON_Pos) /*!< ERRBNK TEBR0: POISON Mask */ + +#define ERRBNK_TEBR0_TYPE_Pos 27U /*!< ERRBNK TEBR0: TYPE Position */ +#define ERRBNK_TEBR0_TYPE_Msk (0x1UL << ERRBNK_TEBR0_TYPE_Pos) /*!< ERRBNK TEBR0: TYPE Mask */ + +#define ERRBNK_TEBR0_BANK_Pos 24U /*!< ERRBNK TEBR0: BANK Position */ +#define ERRBNK_TEBR0_BANK_Msk (0x3UL << ERRBNK_TEBR0_BANK_Pos) /*!< ERRBNK TEBR0: BANK Mask */ + +#define ERRBNK_TEBR0_LOCATION_Pos 2U /*!< ERRBNK TEBR0: LOCATION Position */ +#define ERRBNK_TEBR0_LOCATION_Msk (0x3FFFFFUL << ERRBNK_TEBR0_LOCATION_Pos) /*!< ERRBNK TEBR0: LOCATION Mask */ + +#define ERRBNK_TEBR0_LOCKED_Pos 1U /*!< ERRBNK TEBR0: LOCKED Position */ +#define ERRBNK_TEBR0_LOCKED_Msk (0x1UL << ERRBNK_TEBR0_LOCKED_Pos) /*!< ERRBNK TEBR0: LOCKED Mask */ + +#define ERRBNK_TEBR0_VALID_Pos 0U /*!< ERRBNK TEBR0: VALID Position */ +#define ERRBNK_TEBR0_VALID_Msk (0x1UL << /*ERRBNK_TEBR0_VALID_Pos*/) /*!< ERRBNK TEBR0: VALID Mask */ + +/* ERRBNK TCM Error Bank Register 1 (TEBR1) Register Definitions */ +#define ERRBNK_TEBR1_SWDEF_Pos 30U /*!< ERRBNK TEBR1: SWDEF Position */ +#define ERRBNK_TEBR1_SWDEF_Msk (0x3UL << ERRBNK_TEBR1_SWDEF_Pos) /*!< ERRBNK TEBR1: SWDEF Mask */ + +#define ERRBNK_TEBR1_POISON_Pos 28U /*!< ERRBNK TEBR1: POISON Position */ +#define ERRBNK_TEBR1_POISON_Msk (0x1UL << ERRBNK_TEBR1_POISON_Pos) /*!< ERRBNK TEBR1: POISON Mask */ + +#define ERRBNK_TEBR1_TYPE_Pos 27U /*!< ERRBNK TEBR1: TYPE Position */ +#define ERRBNK_TEBR1_TYPE_Msk (0x1UL << ERRBNK_TEBR1_TYPE_Pos) /*!< ERRBNK TEBR1: TYPE Mask */ + +#define ERRBNK_TEBR1_BANK_Pos 24U /*!< ERRBNK TEBR1: BANK Position */ +#define ERRBNK_TEBR1_BANK_Msk (0x3UL << ERRBNK_TEBR1_BANK_Pos) /*!< ERRBNK TEBR1: BANK Mask */ + +#define ERRBNK_TEBR1_LOCATION_Pos 2U /*!< ERRBNK TEBR1: LOCATION Position */ +#define ERRBNK_TEBR1_LOCATION_Msk (0x3FFFFFUL << ERRBNK_TEBR1_LOCATION_Pos) /*!< ERRBNK TEBR1: LOCATION Mask */ + +#define ERRBNK_TEBR1_LOCKED_Pos 1U /*!< ERRBNK TEBR1: LOCKED Position */ +#define ERRBNK_TEBR1_LOCKED_Msk (0x1UL << ERRBNK_TEBR1_LOCKED_Pos) /*!< ERRBNK TEBR1: LOCKED Mask */ + +#define ERRBNK_TEBR1_VALID_Pos 0U /*!< ERRBNK TEBR1: VALID Position */ +#define ERRBNK_TEBR1_VALID_Msk (0x1UL << /*ERRBNK_TEBR1_VALID_Pos*/) /*!< ERRBNK TEBR1: VALID Mask */ + +/*@}*/ /* end of group ErrBnk_Type */ + + +/** + \ingroup CMSIS_core_register + \defgroup PrcCfgInf_Type Processor Configuration Information Registers (IMPLEMENTATION DEFINED) + \brief Type definitions for the Processor Configuration Information Registerss (PRCCFGINF) + @{ + */ + +/** + \brief Structure type to access the Processor Configuration Information Registerss (PRCCFGINF). + */ +typedef struct +{ + __OM uint32_t CFGINFOSEL; /*!< Offset: 0x000 ( /W) Processor Configuration Information Selection Register */ + __IM uint32_t CFGINFORD; /*!< Offset: 0x004 (R/ ) Processor Configuration Information Read Data Register */ +} PrcCfgInf_Type; + +/* PRCCFGINF Processor Configuration Information Selection Register (CFGINFOSEL) Definitions */ + +/* PRCCFGINF Processor Configuration Information Read Data Register (CFGINFORD) Definitions */ + +/*@}*/ /* end of group PrcCfgInf_Type */ + + +/** + \ingroup CMSIS_core_register + \defgroup STL_Type Software Test Library Observation Registers + \brief Type definitions for the Software Test Library Observation Registerss (STL) + @{ + */ + +/** + \brief Structure type to access the Software Test Library Observation Registerss (STL). + */ +typedef struct +{ + __IM uint32_t STLNVICPENDOR; /*!< Offset: 0x000 (R/ ) NVIC Pending Priority Tree Register */ + __IM uint32_t STLNVICACTVOR; /*!< Offset: 0x004 (R/ ) NVIC Active Priority Tree Register */ + uint32_t RESERVED0[2U]; + __OM uint32_t STLIDMPUSR; /*!< Offset: 0x010 ( /W) MPU Sanple Register */ + __IM uint32_t STLIMPUOR; /*!< Offset: 0x014 (R/ ) MPU Region Hit Register */ + __IM uint32_t STLD0MPUOR; /*!< Offset: 0x018 (R/ ) MPU Memory Attributes Register 0 */ + __IM uint32_t STLD1MPUOR; /*!< Offset: 0x01C (R/ ) MPU Memory Attributes Register 1 */ + +} STL_Type; + +/* STL Software Test Library Observation Register (STLNVICPENDOR) Definitions */ +#define STL_STLNVICPENDOR_VALID_Pos 18U /*!< STL STLNVICPENDOR: VALID Position */ +#define STL_STLNVICPENDOR_VALID_Msk (0x1UL << STL_STLNVICPENDOR_VALID_Pos) /*!< STL STLNVICPENDOR: VALID Mask */ + +#define STL_STLNVICPENDOR_TARGET_Pos 17U /*!< STL STLNVICPENDOR: TARGET Position */ +#define STL_STLNVICPENDOR_TARGET_Msk (0x1UL << STL_STLNVICPENDOR_TARGET_Pos) /*!< STL STLNVICPENDOR: TARGET Mask */ + +#define STL_STLNVICPENDOR_PRIORITY_Pos 9U /*!< STL STLNVICPENDOR: PRIORITY Position */ +#define STL_STLNVICPENDOR_PRIORITY_Msk (0xFFUL << STL_STLNVICPENDOR_PRIORITY_Pos) /*!< STL STLNVICPENDOR: PRIORITY Mask */ + +#define STL_STLNVICPENDOR_INTNUM_Pos 0U /*!< STL STLNVICPENDOR: INTNUM Position */ +#define STL_STLNVICPENDOR_INTNUM_Msk (0x1FFUL /*<< STL_STLNVICPENDOR_INTNUM_Pos*/) /*!< STL STLNVICPENDOR: INTNUM Mask */ + +/* STL Software Test Library Observation Register (STLNVICACTVOR) Definitions */ +#define STL_STLNVICACTVOR_VALID_Pos 18U /*!< STL STLNVICACTVOR: VALID Position */ +#define STL_STLNVICACTVOR_VALID_Msk (0x1UL << STL_STLNVICACTVOR_VALID_Pos) /*!< STL STLNVICACTVOR: VALID Mask */ + +#define STL_STLNVICACTVOR_TARGET_Pos 17U /*!< STL STLNVICACTVOR: TARGET Position */ +#define STL_STLNVICACTVOR_TARGET_Msk (0x1UL << STL_STLNVICACTVOR_TARGET_Pos) /*!< STL STLNVICACTVOR: TARGET Mask */ + +#define STL_STLNVICACTVOR_PRIORITY_Pos 9U /*!< STL STLNVICACTVOR: PRIORITY Position */ +#define STL_STLNVICACTVOR_PRIORITY_Msk (0xFFUL << STL_STLNVICACTVOR_PRIORITY_Pos) /*!< STL STLNVICACTVOR: PRIORITY Mask */ + +#define STL_STLNVICACTVOR_INTNUM_Pos 0U /*!< STL STLNVICACTVOR: INTNUM Position */ +#define STL_STLNVICACTVOR_INTNUM_Msk (0x1FFUL /*<< STL_STLNVICACTVOR_INTNUM_Pos*/) /*!< STL STLNVICACTVOR: INTNUM Mask */ + +/* STL Software Test Library Observation Register (STLIDMPUSR) Definitions */ +#define STL_STLIDMPUSR_ADDR_Pos 5U /*!< STL STLIDMPUSR: ADDR Position */ +#define STL_STLIDMPUSR_ADDR_Msk (0x7FFFFFFUL << STL_STLIDMPUSR_ADDR_Pos) /*!< STL STLIDMPUSR: ADDR Mask */ + +#define STL_STLIDMPUSR_INSTR_Pos 2U /*!< STL STLIDMPUSR: INSTR Position */ +#define STL_STLIDMPUSR_INSTR_Msk (0x1UL << STL_STLIDMPUSR_INSTR_Pos) /*!< STL STLIDMPUSR: INSTR Mask */ + +#define STL_STLIDMPUSR_DATA_Pos 1U /*!< STL STLIDMPUSR: DATA Position */ +#define STL_STLIDMPUSR_DATA_Msk (0x1UL << STL_STLIDMPUSR_DATA_Pos) /*!< STL STLIDMPUSR: DATA Mask */ + +/* STL Software Test Library Observation Register (STLIMPUOR) Definitions */ +#define STL_STLIMPUOR_HITREGION_Pos 9U /*!< STL STLIMPUOR: HITREGION Position */ +#define STL_STLIMPUOR_HITREGION_Msk (0xFFUL << STL_STLIMPUOR_HITREGION_Pos) /*!< STL STLIMPUOR: HITREGION Mask */ + +#define STL_STLIMPUOR_ATTR_Pos 0U /*!< STL STLIMPUOR: ATTR Position */ +#define STL_STLIMPUOR_ATTR_Msk (0x1FFUL /*<< STL_STLIMPUOR_ATTR_Pos*/) /*!< STL STLIMPUOR: ATTR Mask */ + +/* STL Software Test Library Observation Register (STLD0MPUOR) Definitions */ +#define STL_STLD0MPUOR_HITREGION_Pos 9U /*!< STL STLD0MPUOR: HITREGION Position */ +#define STL_STLD0MPUOR_HITREGION_Msk (0xFFUL << STL_STLD0MPUOR_HITREGION_Pos) /*!< STL STLD0MPUOR: HITREGION Mask */ + +#define STL_STLD0MPUOR_ATTR_Pos 0U /*!< STL STLD0MPUOR: ATTR Position */ +#define STL_STLD0MPUOR_ATTR_Msk (0x1FFUL /*<< STL_STLD0MPUOR_ATTR_Pos*/) /*!< STL STLD0MPUOR: ATTR Mask */ + +/* STL Software Test Library Observation Register (STLD1MPUOR) Definitions */ +#define STL_STLD1MPUOR_HITREGION_Pos 9U /*!< STL STLD1MPUOR: HITREGION Position */ +#define STL_STLD1MPUOR_HITREGION_Msk (0xFFUL << STL_STLD1MPUOR_HITREGION_Pos) /*!< STL STLD1MPUOR: HITREGION Mask */ + +#define STL_STLD1MPUOR_ATTR_Pos 0U /*!< STL STLD1MPUOR: ATTR Position */ +#define STL_STLD1MPUOR_ATTR_Msk (0x1FFUL /*<< STL_STLD1MPUOR_ATTR_Pos*/) /*!< STL STLD1MPUOR: ATTR Mask */ + +/*@}*/ /* end of group STL_Type */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Sizes Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Sizes Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ + uint32_t RESERVED3[809U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) Software Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) Software Lock Status Register */ + uint32_t RESERVED4[4U]; + __IM uint32_t TYPE; /*!< Offset: 0xFC8 (R/ ) Device Identifier Register */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Register */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_SWOSCALER_Pos 0U /*!< TPI ACPR: SWOSCALER Position */ +#define TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/) /*!< TPI ACPR: SWOSCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ +#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ + +#define TPI_FFCR_EnFmt_Pos 0U /*!< TPI FFCR: EnFmt Position */ +#define TPI_FFCR_EnFmt_Msk (0x3UL << /*TPI_FFCR_EnFmt_Pos*/) /*!< TPI FFCR: EnFmt Mask */ + +/* TPI Periodic Synchronization Control Register Definitions */ +#define TPI_PSCR_PSCount_Pos 0U /*!< TPI PSCR: PSCount Position */ +#define TPI_PSCR_PSCount_Msk (0x1FUL /*<< TPI_PSCR_PSCount_Pos*/) /*!< TPI PSCR: TPSCount Mask */ + +/* TPI Software Lock Status Register Definitions */ +#define TPI_LSR_nTT_Pos 1U /*!< TPI LSR: Not thirty-two bit. Position */ +#define TPI_LSR_nTT_Msk (0x1UL << TPI_LSR_nTT_Pos) /*!< TPI LSR: Not thirty-two bit. Mask */ + +#define TPI_LSR_SLK_Pos 1U /*!< TPI LSR: Software Lock status Position */ +#define TPI_LSR_SLK_Msk (0x1UL << TPI_LSR_SLK_Pos) /*!< TPI LSR: Software Lock status Mask */ + +#define TPI_LSR_SLI_Pos 0U /*!< TPI LSR: Software Lock implemented Position */ +#define TPI_LSR_SLI_Msk (0x1UL /*<< TPI_LSR_SLI_Pos*/) /*!< TPI LSR: Software Lock implemented Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFO depth Position */ +#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFO depth Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + +#if defined (__PMU_PRESENT) && (__PMU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_PMU Performance Monitoring Unit (PMU) + \brief Type definitions for the Performance Monitoring Unit (PMU) + @{ + */ + +/** + \brief Structure type to access the Performance Monitoring Unit (PMU). + */ +typedef struct +{ + __IOM uint32_t EVCNTR[__PMU_NUM_EVENTCNT]; /*!< Offset: 0x0 (R/W) PMU Event Counter Registers */ +#if __PMU_NUM_EVENTCNT<31 + uint32_t RESERVED0[31U-__PMU_NUM_EVENTCNT]; +#endif + __IOM uint32_t CCNTR; /*!< Offset: 0x7C (R/W) PMU Cycle Counter Register */ + uint32_t RESERVED1[224]; + __IOM uint32_t EVTYPER[__PMU_NUM_EVENTCNT]; /*!< Offset: 0x400 (R/W) PMU Event Type and Filter Registers */ +#if __PMU_NUM_EVENTCNT<31 + uint32_t RESERVED2[31U-__PMU_NUM_EVENTCNT]; +#endif + __IOM uint32_t CCFILTR; /*!< Offset: 0x47C (R/W) PMU Cycle Counter Filter Register */ + uint32_t RESERVED3[480]; + __IOM uint32_t CNTENSET; /*!< Offset: 0xC00 (R/W) PMU Count Enable Set Register */ + uint32_t RESERVED4[7]; + __IOM uint32_t CNTENCLR; /*!< Offset: 0xC20 (R/W) PMU Count Enable Clear Register */ + uint32_t RESERVED5[7]; + __IOM uint32_t INTENSET; /*!< Offset: 0xC40 (R/W) PMU Interrupt Enable Set Register */ + uint32_t RESERVED6[7]; + __IOM uint32_t INTENCLR; /*!< Offset: 0xC60 (R/W) PMU Interrupt Enable Clear Register */ + uint32_t RESERVED7[7]; + __IOM uint32_t OVSCLR; /*!< Offset: 0xC80 (R/W) PMU Overflow Flag Status Clear Register */ + uint32_t RESERVED8[7]; + __IOM uint32_t SWINC; /*!< Offset: 0xCA0 (R/W) PMU Software Increment Register */ + uint32_t RESERVED9[7]; + __IOM uint32_t OVSSET; /*!< Offset: 0xCC0 (R/W) PMU Overflow Flag Status Set Register */ + uint32_t RESERVED10[79]; + __IOM uint32_t TYPE; /*!< Offset: 0xE00 (R/W) PMU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0xE04 (R/W) PMU Control Register */ + uint32_t RESERVED11[108]; + __IOM uint32_t AUTHSTATUS; /*!< Offset: 0xFB8 (R/W) PMU Authentication Status Register */ + __IOM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/W) PMU Device Architecture Register */ + uint32_t RESERVED12[3]; + __IOM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/W) PMU Device Type Register */ + __IOM uint32_t PIDR4; /*!< Offset: 0xFD0 (R/W) PMU Peripheral Identification Register 4 */ + uint32_t RESERVED13[3]; + __IOM uint32_t PIDR0; /*!< Offset: 0xFE0 (R/W) PMU Peripheral Identification Register 0 */ + __IOM uint32_t PIDR1; /*!< Offset: 0xFE4 (R/W) PMU Peripheral Identification Register 1 */ + __IOM uint32_t PIDR2; /*!< Offset: 0xFE8 (R/W) PMU Peripheral Identification Register 2 */ + __IOM uint32_t PIDR3; /*!< Offset: 0xFEC (R/W) PMU Peripheral Identification Register 3 */ + __IOM uint32_t CIDR0; /*!< Offset: 0xFF0 (R/W) PMU Component Identification Register 0 */ + __IOM uint32_t CIDR1; /*!< Offset: 0xFF4 (R/W) PMU Component Identification Register 1 */ + __IOM uint32_t CIDR2; /*!< Offset: 0xFF8 (R/W) PMU Component Identification Register 2 */ + __IOM uint32_t CIDR3; /*!< Offset: 0xFFC (R/W) PMU Component Identification Register 3 */ +} PMU_Type; + +/** \brief PMU Event Counter Registers (0-30) Definitions */ + +#define PMU_EVCNTR_CNT_Pos 0U /*!< PMU EVCNTR: Counter Position */ +#define PMU_EVCNTR_CNT_Msk (0xFFFFUL /*<< PMU_EVCNTRx_CNT_Pos*/) /*!< PMU EVCNTR: Counter Mask */ + +/** \brief PMU Event Type and Filter Registers (0-30) Definitions */ + +#define PMU_EVTYPER_EVENTTOCNT_Pos 0U /*!< PMU EVTYPER: Event to Count Position */ +#define PMU_EVTYPER_EVENTTOCNT_Msk (0xFFFFUL /*<< EVTYPERx_EVENTTOCNT_Pos*/) /*!< PMU EVTYPER: Event to Count Mask */ + +/** \brief PMU Count Enable Set Register Definitions */ + +#define PMU_CNTENSET_CNT0_ENABLE_Pos 0U /*!< PMU CNTENSET: Event Counter 0 Enable Set Position */ +#define PMU_CNTENSET_CNT0_ENABLE_Msk (1UL /*<< PMU_CNTENSET_CNT0_ENABLE_Pos*/) /*!< PMU CNTENSET: Event Counter 0 Enable Set Mask */ + +#define PMU_CNTENSET_CNT1_ENABLE_Pos 1U /*!< PMU CNTENSET: Event Counter 1 Enable Set Position */ +#define PMU_CNTENSET_CNT1_ENABLE_Msk (1UL << PMU_CNTENSET_CNT1_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 1 Enable Set Mask */ + +#define PMU_CNTENSET_CNT2_ENABLE_Pos 2U /*!< PMU CNTENSET: Event Counter 2 Enable Set Position */ +#define PMU_CNTENSET_CNT2_ENABLE_Msk (1UL << PMU_CNTENSET_CNT2_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 2 Enable Set Mask */ + +#define PMU_CNTENSET_CNT3_ENABLE_Pos 3U /*!< PMU CNTENSET: Event Counter 3 Enable Set Position */ +#define PMU_CNTENSET_CNT3_ENABLE_Msk (1UL << PMU_CNTENSET_CNT3_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 3 Enable Set Mask */ + +#define PMU_CNTENSET_CNT4_ENABLE_Pos 4U /*!< PMU CNTENSET: Event Counter 4 Enable Set Position */ +#define PMU_CNTENSET_CNT4_ENABLE_Msk (1UL << PMU_CNTENSET_CNT4_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 4 Enable Set Mask */ + +#define PMU_CNTENSET_CNT5_ENABLE_Pos 5U /*!< PMU CNTENSET: Event Counter 5 Enable Set Position */ +#define PMU_CNTENSET_CNT5_ENABLE_Msk (1UL << PMU_CNTENSET_CNT5_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 5 Enable Set Mask */ + +#define PMU_CNTENSET_CNT6_ENABLE_Pos 6U /*!< PMU CNTENSET: Event Counter 6 Enable Set Position */ +#define PMU_CNTENSET_CNT6_ENABLE_Msk (1UL << PMU_CNTENSET_CNT6_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 6 Enable Set Mask */ + +#define PMU_CNTENSET_CNT7_ENABLE_Pos 7U /*!< PMU CNTENSET: Event Counter 7 Enable Set Position */ +#define PMU_CNTENSET_CNT7_ENABLE_Msk (1UL << PMU_CNTENSET_CNT7_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 7 Enable Set Mask */ + +#define PMU_CNTENSET_CNT8_ENABLE_Pos 8U /*!< PMU CNTENSET: Event Counter 8 Enable Set Position */ +#define PMU_CNTENSET_CNT8_ENABLE_Msk (1UL << PMU_CNTENSET_CNT8_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 8 Enable Set Mask */ + +#define PMU_CNTENSET_CNT9_ENABLE_Pos 9U /*!< PMU CNTENSET: Event Counter 9 Enable Set Position */ +#define PMU_CNTENSET_CNT9_ENABLE_Msk (1UL << PMU_CNTENSET_CNT9_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 9 Enable Set Mask */ + +#define PMU_CNTENSET_CNT10_ENABLE_Pos 10U /*!< PMU CNTENSET: Event Counter 10 Enable Set Position */ +#define PMU_CNTENSET_CNT10_ENABLE_Msk (1UL << PMU_CNTENSET_CNT10_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 10 Enable Set Mask */ + +#define PMU_CNTENSET_CNT11_ENABLE_Pos 11U /*!< PMU CNTENSET: Event Counter 11 Enable Set Position */ +#define PMU_CNTENSET_CNT11_ENABLE_Msk (1UL << PMU_CNTENSET_CNT11_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 11 Enable Set Mask */ + +#define PMU_CNTENSET_CNT12_ENABLE_Pos 12U /*!< PMU CNTENSET: Event Counter 12 Enable Set Position */ +#define PMU_CNTENSET_CNT12_ENABLE_Msk (1UL << PMU_CNTENSET_CNT12_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 12 Enable Set Mask */ + +#define PMU_CNTENSET_CNT13_ENABLE_Pos 13U /*!< PMU CNTENSET: Event Counter 13 Enable Set Position */ +#define PMU_CNTENSET_CNT13_ENABLE_Msk (1UL << PMU_CNTENSET_CNT13_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 13 Enable Set Mask */ + +#define PMU_CNTENSET_CNT14_ENABLE_Pos 14U /*!< PMU CNTENSET: Event Counter 14 Enable Set Position */ +#define PMU_CNTENSET_CNT14_ENABLE_Msk (1UL << PMU_CNTENSET_CNT14_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 14 Enable Set Mask */ + +#define PMU_CNTENSET_CNT15_ENABLE_Pos 15U /*!< PMU CNTENSET: Event Counter 15 Enable Set Position */ +#define PMU_CNTENSET_CNT15_ENABLE_Msk (1UL << PMU_CNTENSET_CNT15_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 15 Enable Set Mask */ + +#define PMU_CNTENSET_CNT16_ENABLE_Pos 16U /*!< PMU CNTENSET: Event Counter 16 Enable Set Position */ +#define PMU_CNTENSET_CNT16_ENABLE_Msk (1UL << PMU_CNTENSET_CNT16_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 16 Enable Set Mask */ + +#define PMU_CNTENSET_CNT17_ENABLE_Pos 17U /*!< PMU CNTENSET: Event Counter 17 Enable Set Position */ +#define PMU_CNTENSET_CNT17_ENABLE_Msk (1UL << PMU_CNTENSET_CNT17_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 17 Enable Set Mask */ + +#define PMU_CNTENSET_CNT18_ENABLE_Pos 18U /*!< PMU CNTENSET: Event Counter 18 Enable Set Position */ +#define PMU_CNTENSET_CNT18_ENABLE_Msk (1UL << PMU_CNTENSET_CNT18_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 18 Enable Set Mask */ + +#define PMU_CNTENSET_CNT19_ENABLE_Pos 19U /*!< PMU CNTENSET: Event Counter 19 Enable Set Position */ +#define PMU_CNTENSET_CNT19_ENABLE_Msk (1UL << PMU_CNTENSET_CNT19_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 19 Enable Set Mask */ + +#define PMU_CNTENSET_CNT20_ENABLE_Pos 20U /*!< PMU CNTENSET: Event Counter 20 Enable Set Position */ +#define PMU_CNTENSET_CNT20_ENABLE_Msk (1UL << PMU_CNTENSET_CNT20_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 20 Enable Set Mask */ + +#define PMU_CNTENSET_CNT21_ENABLE_Pos 21U /*!< PMU CNTENSET: Event Counter 21 Enable Set Position */ +#define PMU_CNTENSET_CNT21_ENABLE_Msk (1UL << PMU_CNTENSET_CNT21_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 21 Enable Set Mask */ + +#define PMU_CNTENSET_CNT22_ENABLE_Pos 22U /*!< PMU CNTENSET: Event Counter 22 Enable Set Position */ +#define PMU_CNTENSET_CNT22_ENABLE_Msk (1UL << PMU_CNTENSET_CNT22_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 22 Enable Set Mask */ + +#define PMU_CNTENSET_CNT23_ENABLE_Pos 23U /*!< PMU CNTENSET: Event Counter 23 Enable Set Position */ +#define PMU_CNTENSET_CNT23_ENABLE_Msk (1UL << PMU_CNTENSET_CNT23_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 23 Enable Set Mask */ + +#define PMU_CNTENSET_CNT24_ENABLE_Pos 24U /*!< PMU CNTENSET: Event Counter 24 Enable Set Position */ +#define PMU_CNTENSET_CNT24_ENABLE_Msk (1UL << PMU_CNTENSET_CNT24_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 24 Enable Set Mask */ + +#define PMU_CNTENSET_CNT25_ENABLE_Pos 25U /*!< PMU CNTENSET: Event Counter 25 Enable Set Position */ +#define PMU_CNTENSET_CNT25_ENABLE_Msk (1UL << PMU_CNTENSET_CNT25_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 25 Enable Set Mask */ + +#define PMU_CNTENSET_CNT26_ENABLE_Pos 26U /*!< PMU CNTENSET: Event Counter 26 Enable Set Position */ +#define PMU_CNTENSET_CNT26_ENABLE_Msk (1UL << PMU_CNTENSET_CNT26_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 26 Enable Set Mask */ + +#define PMU_CNTENSET_CNT27_ENABLE_Pos 27U /*!< PMU CNTENSET: Event Counter 27 Enable Set Position */ +#define PMU_CNTENSET_CNT27_ENABLE_Msk (1UL << PMU_CNTENSET_CNT27_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 27 Enable Set Mask */ + +#define PMU_CNTENSET_CNT28_ENABLE_Pos 28U /*!< PMU CNTENSET: Event Counter 28 Enable Set Position */ +#define PMU_CNTENSET_CNT28_ENABLE_Msk (1UL << PMU_CNTENSET_CNT28_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 28 Enable Set Mask */ + +#define PMU_CNTENSET_CNT29_ENABLE_Pos 29U /*!< PMU CNTENSET: Event Counter 29 Enable Set Position */ +#define PMU_CNTENSET_CNT29_ENABLE_Msk (1UL << PMU_CNTENSET_CNT29_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 29 Enable Set Mask */ + +#define PMU_CNTENSET_CNT30_ENABLE_Pos 30U /*!< PMU CNTENSET: Event Counter 30 Enable Set Position */ +#define PMU_CNTENSET_CNT30_ENABLE_Msk (1UL << PMU_CNTENSET_CNT30_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 30 Enable Set Mask */ + +#define PMU_CNTENSET_CCNTR_ENABLE_Pos 31U /*!< PMU CNTENSET: Cycle Counter Enable Set Position */ +#define PMU_CNTENSET_CCNTR_ENABLE_Msk (1UL << PMU_CNTENSET_CCNTR_ENABLE_Pos) /*!< PMU CNTENSET: Cycle Counter Enable Set Mask */ + +/** \brief PMU Count Enable Clear Register Definitions */ + +#define PMU_CNTENSET_CNT0_ENABLE_Pos 0U /*!< PMU CNTENCLR: Event Counter 0 Enable Clear Position */ +#define PMU_CNTENCLR_CNT0_ENABLE_Msk (1UL /*<< PMU_CNTENCLR_CNT0_ENABLE_Pos*/) /*!< PMU CNTENCLR: Event Counter 0 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT1_ENABLE_Pos 1U /*!< PMU CNTENCLR: Event Counter 1 Enable Clear Position */ +#define PMU_CNTENCLR_CNT1_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT1_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 1 Enable Clear */ + +#define PMU_CNTENCLR_CNT2_ENABLE_Pos 2U /*!< PMU CNTENCLR: Event Counter 2 Enable Clear Position */ +#define PMU_CNTENCLR_CNT2_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT2_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 2 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT3_ENABLE_Pos 3U /*!< PMU CNTENCLR: Event Counter 3 Enable Clear Position */ +#define PMU_CNTENCLR_CNT3_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT3_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 3 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT4_ENABLE_Pos 4U /*!< PMU CNTENCLR: Event Counter 4 Enable Clear Position */ +#define PMU_CNTENCLR_CNT4_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT4_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 4 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT5_ENABLE_Pos 5U /*!< PMU CNTENCLR: Event Counter 5 Enable Clear Position */ +#define PMU_CNTENCLR_CNT5_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT5_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 5 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT6_ENABLE_Pos 6U /*!< PMU CNTENCLR: Event Counter 6 Enable Clear Position */ +#define PMU_CNTENCLR_CNT6_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT6_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 6 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT7_ENABLE_Pos 7U /*!< PMU CNTENCLR: Event Counter 7 Enable Clear Position */ +#define PMU_CNTENCLR_CNT7_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT7_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 7 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT8_ENABLE_Pos 8U /*!< PMU CNTENCLR: Event Counter 8 Enable Clear Position */ +#define PMU_CNTENCLR_CNT8_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT8_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 8 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT9_ENABLE_Pos 9U /*!< PMU CNTENCLR: Event Counter 9 Enable Clear Position */ +#define PMU_CNTENCLR_CNT9_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT9_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 9 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT10_ENABLE_Pos 10U /*!< PMU CNTENCLR: Event Counter 10 Enable Clear Position */ +#define PMU_CNTENCLR_CNT10_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT10_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 10 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT11_ENABLE_Pos 11U /*!< PMU CNTENCLR: Event Counter 11 Enable Clear Position */ +#define PMU_CNTENCLR_CNT11_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT11_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 11 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT12_ENABLE_Pos 12U /*!< PMU CNTENCLR: Event Counter 12 Enable Clear Position */ +#define PMU_CNTENCLR_CNT12_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT12_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 12 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT13_ENABLE_Pos 13U /*!< PMU CNTENCLR: Event Counter 13 Enable Clear Position */ +#define PMU_CNTENCLR_CNT13_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT13_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 13 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT14_ENABLE_Pos 14U /*!< PMU CNTENCLR: Event Counter 14 Enable Clear Position */ +#define PMU_CNTENCLR_CNT14_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT14_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 14 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT15_ENABLE_Pos 15U /*!< PMU CNTENCLR: Event Counter 15 Enable Clear Position */ +#define PMU_CNTENCLR_CNT15_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT15_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 15 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT16_ENABLE_Pos 16U /*!< PMU CNTENCLR: Event Counter 16 Enable Clear Position */ +#define PMU_CNTENCLR_CNT16_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT16_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 16 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT17_ENABLE_Pos 17U /*!< PMU CNTENCLR: Event Counter 17 Enable Clear Position */ +#define PMU_CNTENCLR_CNT17_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT17_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 17 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT18_ENABLE_Pos 18U /*!< PMU CNTENCLR: Event Counter 18 Enable Clear Position */ +#define PMU_CNTENCLR_CNT18_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT18_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 18 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT19_ENABLE_Pos 19U /*!< PMU CNTENCLR: Event Counter 19 Enable Clear Position */ +#define PMU_CNTENCLR_CNT19_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT19_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 19 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT20_ENABLE_Pos 20U /*!< PMU CNTENCLR: Event Counter 20 Enable Clear Position */ +#define PMU_CNTENCLR_CNT20_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT20_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 20 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT21_ENABLE_Pos 21U /*!< PMU CNTENCLR: Event Counter 21 Enable Clear Position */ +#define PMU_CNTENCLR_CNT21_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT21_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 21 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT22_ENABLE_Pos 22U /*!< PMU CNTENCLR: Event Counter 22 Enable Clear Position */ +#define PMU_CNTENCLR_CNT22_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT22_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 22 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT23_ENABLE_Pos 23U /*!< PMU CNTENCLR: Event Counter 23 Enable Clear Position */ +#define PMU_CNTENCLR_CNT23_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT23_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 23 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT24_ENABLE_Pos 24U /*!< PMU CNTENCLR: Event Counter 24 Enable Clear Position */ +#define PMU_CNTENCLR_CNT24_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT24_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 24 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT25_ENABLE_Pos 25U /*!< PMU CNTENCLR: Event Counter 25 Enable Clear Position */ +#define PMU_CNTENCLR_CNT25_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT25_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 25 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT26_ENABLE_Pos 26U /*!< PMU CNTENCLR: Event Counter 26 Enable Clear Position */ +#define PMU_CNTENCLR_CNT26_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT26_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 26 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT27_ENABLE_Pos 27U /*!< PMU CNTENCLR: Event Counter 27 Enable Clear Position */ +#define PMU_CNTENCLR_CNT27_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT27_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 27 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT28_ENABLE_Pos 28U /*!< PMU CNTENCLR: Event Counter 28 Enable Clear Position */ +#define PMU_CNTENCLR_CNT28_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT28_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 28 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT29_ENABLE_Pos 29U /*!< PMU CNTENCLR: Event Counter 29 Enable Clear Position */ +#define PMU_CNTENCLR_CNT29_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT29_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 29 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT30_ENABLE_Pos 30U /*!< PMU CNTENCLR: Event Counter 30 Enable Clear Position */ +#define PMU_CNTENCLR_CNT30_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT30_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 30 Enable Clear Mask */ + +#define PMU_CNTENCLR_CCNTR_ENABLE_Pos 31U /*!< PMU CNTENCLR: Cycle Counter Enable Clear Position */ +#define PMU_CNTENCLR_CCNTR_ENABLE_Msk (1UL << PMU_CNTENCLR_CCNTR_ENABLE_Pos) /*!< PMU CNTENCLR: Cycle Counter Enable Clear Mask */ + +/** \brief PMU Interrupt Enable Set Register Definitions */ + +#define PMU_INTENSET_CNT0_ENABLE_Pos 0U /*!< PMU INTENSET: Event Counter 0 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT0_ENABLE_Msk (1UL /*<< PMU_INTENSET_CNT0_ENABLE_Pos*/) /*!< PMU INTENSET: Event Counter 0 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT1_ENABLE_Pos 1U /*!< PMU INTENSET: Event Counter 1 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT1_ENABLE_Msk (1UL << PMU_INTENSET_CNT1_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 1 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT2_ENABLE_Pos 2U /*!< PMU INTENSET: Event Counter 2 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT2_ENABLE_Msk (1UL << PMU_INTENSET_CNT2_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 2 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT3_ENABLE_Pos 3U /*!< PMU INTENSET: Event Counter 3 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT3_ENABLE_Msk (1UL << PMU_INTENSET_CNT3_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 3 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT4_ENABLE_Pos 4U /*!< PMU INTENSET: Event Counter 4 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT4_ENABLE_Msk (1UL << PMU_INTENSET_CNT4_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 4 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT5_ENABLE_Pos 5U /*!< PMU INTENSET: Event Counter 5 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT5_ENABLE_Msk (1UL << PMU_INTENSET_CNT5_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 5 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT6_ENABLE_Pos 6U /*!< PMU INTENSET: Event Counter 6 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT6_ENABLE_Msk (1UL << PMU_INTENSET_CNT6_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 6 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT7_ENABLE_Pos 7U /*!< PMU INTENSET: Event Counter 7 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT7_ENABLE_Msk (1UL << PMU_INTENSET_CNT7_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 7 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT8_ENABLE_Pos 8U /*!< PMU INTENSET: Event Counter 8 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT8_ENABLE_Msk (1UL << PMU_INTENSET_CNT8_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 8 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT9_ENABLE_Pos 9U /*!< PMU INTENSET: Event Counter 9 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT9_ENABLE_Msk (1UL << PMU_INTENSET_CNT9_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 9 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT10_ENABLE_Pos 10U /*!< PMU INTENSET: Event Counter 10 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT10_ENABLE_Msk (1UL << PMU_INTENSET_CNT10_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 10 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT11_ENABLE_Pos 11U /*!< PMU INTENSET: Event Counter 11 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT11_ENABLE_Msk (1UL << PMU_INTENSET_CNT11_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 11 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT12_ENABLE_Pos 12U /*!< PMU INTENSET: Event Counter 12 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT12_ENABLE_Msk (1UL << PMU_INTENSET_CNT12_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 12 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT13_ENABLE_Pos 13U /*!< PMU INTENSET: Event Counter 13 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT13_ENABLE_Msk (1UL << PMU_INTENSET_CNT13_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 13 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT14_ENABLE_Pos 14U /*!< PMU INTENSET: Event Counter 14 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT14_ENABLE_Msk (1UL << PMU_INTENSET_CNT14_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 14 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT15_ENABLE_Pos 15U /*!< PMU INTENSET: Event Counter 15 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT15_ENABLE_Msk (1UL << PMU_INTENSET_CNT15_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 15 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT16_ENABLE_Pos 16U /*!< PMU INTENSET: Event Counter 16 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT16_ENABLE_Msk (1UL << PMU_INTENSET_CNT16_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 16 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT17_ENABLE_Pos 17U /*!< PMU INTENSET: Event Counter 17 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT17_ENABLE_Msk (1UL << PMU_INTENSET_CNT17_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 17 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT18_ENABLE_Pos 18U /*!< PMU INTENSET: Event Counter 18 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT18_ENABLE_Msk (1UL << PMU_INTENSET_CNT18_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 18 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT19_ENABLE_Pos 19U /*!< PMU INTENSET: Event Counter 19 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT19_ENABLE_Msk (1UL << PMU_INTENSET_CNT19_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 19 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT20_ENABLE_Pos 20U /*!< PMU INTENSET: Event Counter 20 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT20_ENABLE_Msk (1UL << PMU_INTENSET_CNT20_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 20 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT21_ENABLE_Pos 21U /*!< PMU INTENSET: Event Counter 21 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT21_ENABLE_Msk (1UL << PMU_INTENSET_CNT21_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 21 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT22_ENABLE_Pos 22U /*!< PMU INTENSET: Event Counter 22 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT22_ENABLE_Msk (1UL << PMU_INTENSET_CNT22_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 22 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT23_ENABLE_Pos 23U /*!< PMU INTENSET: Event Counter 23 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT23_ENABLE_Msk (1UL << PMU_INTENSET_CNT23_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 23 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT24_ENABLE_Pos 24U /*!< PMU INTENSET: Event Counter 24 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT24_ENABLE_Msk (1UL << PMU_INTENSET_CNT24_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 24 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT25_ENABLE_Pos 25U /*!< PMU INTENSET: Event Counter 25 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT25_ENABLE_Msk (1UL << PMU_INTENSET_CNT25_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 25 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT26_ENABLE_Pos 26U /*!< PMU INTENSET: Event Counter 26 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT26_ENABLE_Msk (1UL << PMU_INTENSET_CNT26_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 26 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT27_ENABLE_Pos 27U /*!< PMU INTENSET: Event Counter 27 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT27_ENABLE_Msk (1UL << PMU_INTENSET_CNT27_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 27 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT28_ENABLE_Pos 28U /*!< PMU INTENSET: Event Counter 28 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT28_ENABLE_Msk (1UL << PMU_INTENSET_CNT28_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 28 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT29_ENABLE_Pos 29U /*!< PMU INTENSET: Event Counter 29 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT29_ENABLE_Msk (1UL << PMU_INTENSET_CNT29_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 29 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT30_ENABLE_Pos 30U /*!< PMU INTENSET: Event Counter 30 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT30_ENABLE_Msk (1UL << PMU_INTENSET_CNT30_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 30 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CYCCNT_ENABLE_Pos 31U /*!< PMU INTENSET: Cycle Counter Interrupt Enable Set Position */ +#define PMU_INTENSET_CCYCNT_ENABLE_Msk (1UL << PMU_INTENSET_CYCCNT_ENABLE_Pos) /*!< PMU INTENSET: Cycle Counter Interrupt Enable Set Mask */ + +/** \brief PMU Interrupt Enable Clear Register Definitions */ + +#define PMU_INTENSET_CNT0_ENABLE_Pos 0U /*!< PMU INTENCLR: Event Counter 0 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT0_ENABLE_Msk (1UL /*<< PMU_INTENCLR_CNT0_ENABLE_Pos*/) /*!< PMU INTENCLR: Event Counter 0 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT1_ENABLE_Pos 1U /*!< PMU INTENCLR: Event Counter 1 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT1_ENABLE_Msk (1UL << PMU_INTENCLR_CNT1_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 1 Interrupt Enable Clear */ + +#define PMU_INTENCLR_CNT2_ENABLE_Pos 2U /*!< PMU INTENCLR: Event Counter 2 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT2_ENABLE_Msk (1UL << PMU_INTENCLR_CNT2_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 2 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT3_ENABLE_Pos 3U /*!< PMU INTENCLR: Event Counter 3 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT3_ENABLE_Msk (1UL << PMU_INTENCLR_CNT3_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 3 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT4_ENABLE_Pos 4U /*!< PMU INTENCLR: Event Counter 4 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT4_ENABLE_Msk (1UL << PMU_INTENCLR_CNT4_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 4 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT5_ENABLE_Pos 5U /*!< PMU INTENCLR: Event Counter 5 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT5_ENABLE_Msk (1UL << PMU_INTENCLR_CNT5_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 5 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT6_ENABLE_Pos 6U /*!< PMU INTENCLR: Event Counter 6 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT6_ENABLE_Msk (1UL << PMU_INTENCLR_CNT6_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 6 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT7_ENABLE_Pos 7U /*!< PMU INTENCLR: Event Counter 7 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT7_ENABLE_Msk (1UL << PMU_INTENCLR_CNT7_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 7 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT8_ENABLE_Pos 8U /*!< PMU INTENCLR: Event Counter 8 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT8_ENABLE_Msk (1UL << PMU_INTENCLR_CNT8_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 8 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT9_ENABLE_Pos 9U /*!< PMU INTENCLR: Event Counter 9 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT9_ENABLE_Msk (1UL << PMU_INTENCLR_CNT9_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 9 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT10_ENABLE_Pos 10U /*!< PMU INTENCLR: Event Counter 10 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT10_ENABLE_Msk (1UL << PMU_INTENCLR_CNT10_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 10 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT11_ENABLE_Pos 11U /*!< PMU INTENCLR: Event Counter 11 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT11_ENABLE_Msk (1UL << PMU_INTENCLR_CNT11_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 11 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT12_ENABLE_Pos 12U /*!< PMU INTENCLR: Event Counter 12 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT12_ENABLE_Msk (1UL << PMU_INTENCLR_CNT12_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 12 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT13_ENABLE_Pos 13U /*!< PMU INTENCLR: Event Counter 13 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT13_ENABLE_Msk (1UL << PMU_INTENCLR_CNT13_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 13 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT14_ENABLE_Pos 14U /*!< PMU INTENCLR: Event Counter 14 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT14_ENABLE_Msk (1UL << PMU_INTENCLR_CNT14_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 14 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT15_ENABLE_Pos 15U /*!< PMU INTENCLR: Event Counter 15 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT15_ENABLE_Msk (1UL << PMU_INTENCLR_CNT15_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 15 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT16_ENABLE_Pos 16U /*!< PMU INTENCLR: Event Counter 16 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT16_ENABLE_Msk (1UL << PMU_INTENCLR_CNT16_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 16 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT17_ENABLE_Pos 17U /*!< PMU INTENCLR: Event Counter 17 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT17_ENABLE_Msk (1UL << PMU_INTENCLR_CNT17_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 17 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT18_ENABLE_Pos 18U /*!< PMU INTENCLR: Event Counter 18 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT18_ENABLE_Msk (1UL << PMU_INTENCLR_CNT18_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 18 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT19_ENABLE_Pos 19U /*!< PMU INTENCLR: Event Counter 19 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT19_ENABLE_Msk (1UL << PMU_INTENCLR_CNT19_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 19 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT20_ENABLE_Pos 20U /*!< PMU INTENCLR: Event Counter 20 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT20_ENABLE_Msk (1UL << PMU_INTENCLR_CNT20_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 20 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT21_ENABLE_Pos 21U /*!< PMU INTENCLR: Event Counter 21 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT21_ENABLE_Msk (1UL << PMU_INTENCLR_CNT21_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 21 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT22_ENABLE_Pos 22U /*!< PMU INTENCLR: Event Counter 22 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT22_ENABLE_Msk (1UL << PMU_INTENCLR_CNT22_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 22 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT23_ENABLE_Pos 23U /*!< PMU INTENCLR: Event Counter 23 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT23_ENABLE_Msk (1UL << PMU_INTENCLR_CNT23_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 23 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT24_ENABLE_Pos 24U /*!< PMU INTENCLR: Event Counter 24 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT24_ENABLE_Msk (1UL << PMU_INTENCLR_CNT24_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 24 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT25_ENABLE_Pos 25U /*!< PMU INTENCLR: Event Counter 25 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT25_ENABLE_Msk (1UL << PMU_INTENCLR_CNT25_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 25 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT26_ENABLE_Pos 26U /*!< PMU INTENCLR: Event Counter 26 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT26_ENABLE_Msk (1UL << PMU_INTENCLR_CNT26_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 26 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT27_ENABLE_Pos 27U /*!< PMU INTENCLR: Event Counter 27 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT27_ENABLE_Msk (1UL << PMU_INTENCLR_CNT27_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 27 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT28_ENABLE_Pos 28U /*!< PMU INTENCLR: Event Counter 28 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT28_ENABLE_Msk (1UL << PMU_INTENCLR_CNT28_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 28 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT29_ENABLE_Pos 29U /*!< PMU INTENCLR: Event Counter 29 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT29_ENABLE_Msk (1UL << PMU_INTENCLR_CNT29_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 29 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT30_ENABLE_Pos 30U /*!< PMU INTENCLR: Event Counter 30 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT30_ENABLE_Msk (1UL << PMU_INTENCLR_CNT30_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 30 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CYCCNT_ENABLE_Pos 31U /*!< PMU INTENCLR: Cycle Counter Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CYCCNT_ENABLE_Msk (1UL << PMU_INTENCLR_CYCCNT_ENABLE_Pos) /*!< PMU INTENCLR: Cycle Counter Interrupt Enable Clear Mask */ + +/** \brief PMU Overflow Flag Status Set Register Definitions */ + +#define PMU_OVSSET_CNT0_STATUS_Pos 0U /*!< PMU OVSSET: Event Counter 0 Overflow Set Position */ +#define PMU_OVSSET_CNT0_STATUS_Msk (1UL /*<< PMU_OVSSET_CNT0_STATUS_Pos*/) /*!< PMU OVSSET: Event Counter 0 Overflow Set Mask */ + +#define PMU_OVSSET_CNT1_STATUS_Pos 1U /*!< PMU OVSSET: Event Counter 1 Overflow Set Position */ +#define PMU_OVSSET_CNT1_STATUS_Msk (1UL << PMU_OVSSET_CNT1_STATUS_Pos) /*!< PMU OVSSET: Event Counter 1 Overflow Set Mask */ + +#define PMU_OVSSET_CNT2_STATUS_Pos 2U /*!< PMU OVSSET: Event Counter 2 Overflow Set Position */ +#define PMU_OVSSET_CNT2_STATUS_Msk (1UL << PMU_OVSSET_CNT2_STATUS_Pos) /*!< PMU OVSSET: Event Counter 2 Overflow Set Mask */ + +#define PMU_OVSSET_CNT3_STATUS_Pos 3U /*!< PMU OVSSET: Event Counter 3 Overflow Set Position */ +#define PMU_OVSSET_CNT3_STATUS_Msk (1UL << PMU_OVSSET_CNT3_STATUS_Pos) /*!< PMU OVSSET: Event Counter 3 Overflow Set Mask */ + +#define PMU_OVSSET_CNT4_STATUS_Pos 4U /*!< PMU OVSSET: Event Counter 4 Overflow Set Position */ +#define PMU_OVSSET_CNT4_STATUS_Msk (1UL << PMU_OVSSET_CNT4_STATUS_Pos) /*!< PMU OVSSET: Event Counter 4 Overflow Set Mask */ + +#define PMU_OVSSET_CNT5_STATUS_Pos 5U /*!< PMU OVSSET: Event Counter 5 Overflow Set Position */ +#define PMU_OVSSET_CNT5_STATUS_Msk (1UL << PMU_OVSSET_CNT5_STATUS_Pos) /*!< PMU OVSSET: Event Counter 5 Overflow Set Mask */ + +#define PMU_OVSSET_CNT6_STATUS_Pos 6U /*!< PMU OVSSET: Event Counter 6 Overflow Set Position */ +#define PMU_OVSSET_CNT6_STATUS_Msk (1UL << PMU_OVSSET_CNT6_STATUS_Pos) /*!< PMU OVSSET: Event Counter 6 Overflow Set Mask */ + +#define PMU_OVSSET_CNT7_STATUS_Pos 7U /*!< PMU OVSSET: Event Counter 7 Overflow Set Position */ +#define PMU_OVSSET_CNT7_STATUS_Msk (1UL << PMU_OVSSET_CNT7_STATUS_Pos) /*!< PMU OVSSET: Event Counter 7 Overflow Set Mask */ + +#define PMU_OVSSET_CNT8_STATUS_Pos 8U /*!< PMU OVSSET: Event Counter 8 Overflow Set Position */ +#define PMU_OVSSET_CNT8_STATUS_Msk (1UL << PMU_OVSSET_CNT8_STATUS_Pos) /*!< PMU OVSSET: Event Counter 8 Overflow Set Mask */ + +#define PMU_OVSSET_CNT9_STATUS_Pos 9U /*!< PMU OVSSET: Event Counter 9 Overflow Set Position */ +#define PMU_OVSSET_CNT9_STATUS_Msk (1UL << PMU_OVSSET_CNT9_STATUS_Pos) /*!< PMU OVSSET: Event Counter 9 Overflow Set Mask */ + +#define PMU_OVSSET_CNT10_STATUS_Pos 10U /*!< PMU OVSSET: Event Counter 10 Overflow Set Position */ +#define PMU_OVSSET_CNT10_STATUS_Msk (1UL << PMU_OVSSET_CNT10_STATUS_Pos) /*!< PMU OVSSET: Event Counter 10 Overflow Set Mask */ + +#define PMU_OVSSET_CNT11_STATUS_Pos 11U /*!< PMU OVSSET: Event Counter 11 Overflow Set Position */ +#define PMU_OVSSET_CNT11_STATUS_Msk (1UL << PMU_OVSSET_CNT11_STATUS_Pos) /*!< PMU OVSSET: Event Counter 11 Overflow Set Mask */ + +#define PMU_OVSSET_CNT12_STATUS_Pos 12U /*!< PMU OVSSET: Event Counter 12 Overflow Set Position */ +#define PMU_OVSSET_CNT12_STATUS_Msk (1UL << PMU_OVSSET_CNT12_STATUS_Pos) /*!< PMU OVSSET: Event Counter 12 Overflow Set Mask */ + +#define PMU_OVSSET_CNT13_STATUS_Pos 13U /*!< PMU OVSSET: Event Counter 13 Overflow Set Position */ +#define PMU_OVSSET_CNT13_STATUS_Msk (1UL << PMU_OVSSET_CNT13_STATUS_Pos) /*!< PMU OVSSET: Event Counter 13 Overflow Set Mask */ + +#define PMU_OVSSET_CNT14_STATUS_Pos 14U /*!< PMU OVSSET: Event Counter 14 Overflow Set Position */ +#define PMU_OVSSET_CNT14_STATUS_Msk (1UL << PMU_OVSSET_CNT14_STATUS_Pos) /*!< PMU OVSSET: Event Counter 14 Overflow Set Mask */ + +#define PMU_OVSSET_CNT15_STATUS_Pos 15U /*!< PMU OVSSET: Event Counter 15 Overflow Set Position */ +#define PMU_OVSSET_CNT15_STATUS_Msk (1UL << PMU_OVSSET_CNT15_STATUS_Pos) /*!< PMU OVSSET: Event Counter 15 Overflow Set Mask */ + +#define PMU_OVSSET_CNT16_STATUS_Pos 16U /*!< PMU OVSSET: Event Counter 16 Overflow Set Position */ +#define PMU_OVSSET_CNT16_STATUS_Msk (1UL << PMU_OVSSET_CNT16_STATUS_Pos) /*!< PMU OVSSET: Event Counter 16 Overflow Set Mask */ + +#define PMU_OVSSET_CNT17_STATUS_Pos 17U /*!< PMU OVSSET: Event Counter 17 Overflow Set Position */ +#define PMU_OVSSET_CNT17_STATUS_Msk (1UL << PMU_OVSSET_CNT17_STATUS_Pos) /*!< PMU OVSSET: Event Counter 17 Overflow Set Mask */ + +#define PMU_OVSSET_CNT18_STATUS_Pos 18U /*!< PMU OVSSET: Event Counter 18 Overflow Set Position */ +#define PMU_OVSSET_CNT18_STATUS_Msk (1UL << PMU_OVSSET_CNT18_STATUS_Pos) /*!< PMU OVSSET: Event Counter 18 Overflow Set Mask */ + +#define PMU_OVSSET_CNT19_STATUS_Pos 19U /*!< PMU OVSSET: Event Counter 19 Overflow Set Position */ +#define PMU_OVSSET_CNT19_STATUS_Msk (1UL << PMU_OVSSET_CNT19_STATUS_Pos) /*!< PMU OVSSET: Event Counter 19 Overflow Set Mask */ + +#define PMU_OVSSET_CNT20_STATUS_Pos 20U /*!< PMU OVSSET: Event Counter 20 Overflow Set Position */ +#define PMU_OVSSET_CNT20_STATUS_Msk (1UL << PMU_OVSSET_CNT20_STATUS_Pos) /*!< PMU OVSSET: Event Counter 20 Overflow Set Mask */ + +#define PMU_OVSSET_CNT21_STATUS_Pos 21U /*!< PMU OVSSET: Event Counter 21 Overflow Set Position */ +#define PMU_OVSSET_CNT21_STATUS_Msk (1UL << PMU_OVSSET_CNT21_STATUS_Pos) /*!< PMU OVSSET: Event Counter 21 Overflow Set Mask */ + +#define PMU_OVSSET_CNT22_STATUS_Pos 22U /*!< PMU OVSSET: Event Counter 22 Overflow Set Position */ +#define PMU_OVSSET_CNT22_STATUS_Msk (1UL << PMU_OVSSET_CNT22_STATUS_Pos) /*!< PMU OVSSET: Event Counter 22 Overflow Set Mask */ + +#define PMU_OVSSET_CNT23_STATUS_Pos 23U /*!< PMU OVSSET: Event Counter 23 Overflow Set Position */ +#define PMU_OVSSET_CNT23_STATUS_Msk (1UL << PMU_OVSSET_CNT23_STATUS_Pos) /*!< PMU OVSSET: Event Counter 23 Overflow Set Mask */ + +#define PMU_OVSSET_CNT24_STATUS_Pos 24U /*!< PMU OVSSET: Event Counter 24 Overflow Set Position */ +#define PMU_OVSSET_CNT24_STATUS_Msk (1UL << PMU_OVSSET_CNT24_STATUS_Pos) /*!< PMU OVSSET: Event Counter 24 Overflow Set Mask */ + +#define PMU_OVSSET_CNT25_STATUS_Pos 25U /*!< PMU OVSSET: Event Counter 25 Overflow Set Position */ +#define PMU_OVSSET_CNT25_STATUS_Msk (1UL << PMU_OVSSET_CNT25_STATUS_Pos) /*!< PMU OVSSET: Event Counter 25 Overflow Set Mask */ + +#define PMU_OVSSET_CNT26_STATUS_Pos 26U /*!< PMU OVSSET: Event Counter 26 Overflow Set Position */ +#define PMU_OVSSET_CNT26_STATUS_Msk (1UL << PMU_OVSSET_CNT26_STATUS_Pos) /*!< PMU OVSSET: Event Counter 26 Overflow Set Mask */ + +#define PMU_OVSSET_CNT27_STATUS_Pos 27U /*!< PMU OVSSET: Event Counter 27 Overflow Set Position */ +#define PMU_OVSSET_CNT27_STATUS_Msk (1UL << PMU_OVSSET_CNT27_STATUS_Pos) /*!< PMU OVSSET: Event Counter 27 Overflow Set Mask */ + +#define PMU_OVSSET_CNT28_STATUS_Pos 28U /*!< PMU OVSSET: Event Counter 28 Overflow Set Position */ +#define PMU_OVSSET_CNT28_STATUS_Msk (1UL << PMU_OVSSET_CNT28_STATUS_Pos) /*!< PMU OVSSET: Event Counter 28 Overflow Set Mask */ + +#define PMU_OVSSET_CNT29_STATUS_Pos 29U /*!< PMU OVSSET: Event Counter 29 Overflow Set Position */ +#define PMU_OVSSET_CNT29_STATUS_Msk (1UL << PMU_OVSSET_CNT29_STATUS_Pos) /*!< PMU OVSSET: Event Counter 29 Overflow Set Mask */ + +#define PMU_OVSSET_CNT30_STATUS_Pos 30U /*!< PMU OVSSET: Event Counter 30 Overflow Set Position */ +#define PMU_OVSSET_CNT30_STATUS_Msk (1UL << PMU_OVSSET_CNT30_STATUS_Pos) /*!< PMU OVSSET: Event Counter 30 Overflow Set Mask */ + +#define PMU_OVSSET_CYCCNT_STATUS_Pos 31U /*!< PMU OVSSET: Cycle Counter Overflow Set Position */ +#define PMU_OVSSET_CYCCNT_STATUS_Msk (1UL << PMU_OVSSET_CYCCNT_STATUS_Pos) /*!< PMU OVSSET: Cycle Counter Overflow Set Mask */ + +/** \brief PMU Overflow Flag Status Clear Register Definitions */ + +#define PMU_OVSCLR_CNT0_STATUS_Pos 0U /*!< PMU OVSCLR: Event Counter 0 Overflow Clear Position */ +#define PMU_OVSCLR_CNT0_STATUS_Msk (1UL /*<< PMU_OVSCLR_CNT0_STATUS_Pos*/) /*!< PMU OVSCLR: Event Counter 0 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT1_STATUS_Pos 1U /*!< PMU OVSCLR: Event Counter 1 Overflow Clear Position */ +#define PMU_OVSCLR_CNT1_STATUS_Msk (1UL << PMU_OVSCLR_CNT1_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 1 Overflow Clear */ + +#define PMU_OVSCLR_CNT2_STATUS_Pos 2U /*!< PMU OVSCLR: Event Counter 2 Overflow Clear Position */ +#define PMU_OVSCLR_CNT2_STATUS_Msk (1UL << PMU_OVSCLR_CNT2_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 2 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT3_STATUS_Pos 3U /*!< PMU OVSCLR: Event Counter 3 Overflow Clear Position */ +#define PMU_OVSCLR_CNT3_STATUS_Msk (1UL << PMU_OVSCLR_CNT3_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 3 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT4_STATUS_Pos 4U /*!< PMU OVSCLR: Event Counter 4 Overflow Clear Position */ +#define PMU_OVSCLR_CNT4_STATUS_Msk (1UL << PMU_OVSCLR_CNT4_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 4 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT5_STATUS_Pos 5U /*!< PMU OVSCLR: Event Counter 5 Overflow Clear Position */ +#define PMU_OVSCLR_CNT5_STATUS_Msk (1UL << PMU_OVSCLR_CNT5_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 5 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT6_STATUS_Pos 6U /*!< PMU OVSCLR: Event Counter 6 Overflow Clear Position */ +#define PMU_OVSCLR_CNT6_STATUS_Msk (1UL << PMU_OVSCLR_CNT6_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 6 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT7_STATUS_Pos 7U /*!< PMU OVSCLR: Event Counter 7 Overflow Clear Position */ +#define PMU_OVSCLR_CNT7_STATUS_Msk (1UL << PMU_OVSCLR_CNT7_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 7 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT8_STATUS_Pos 8U /*!< PMU OVSCLR: Event Counter 8 Overflow Clear Position */ +#define PMU_OVSCLR_CNT8_STATUS_Msk (1UL << PMU_OVSCLR_CNT8_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 8 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT9_STATUS_Pos 9U /*!< PMU OVSCLR: Event Counter 9 Overflow Clear Position */ +#define PMU_OVSCLR_CNT9_STATUS_Msk (1UL << PMU_OVSCLR_CNT9_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 9 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT10_STATUS_Pos 10U /*!< PMU OVSCLR: Event Counter 10 Overflow Clear Position */ +#define PMU_OVSCLR_CNT10_STATUS_Msk (1UL << PMU_OVSCLR_CNT10_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 10 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT11_STATUS_Pos 11U /*!< PMU OVSCLR: Event Counter 11 Overflow Clear Position */ +#define PMU_OVSCLR_CNT11_STATUS_Msk (1UL << PMU_OVSCLR_CNT11_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 11 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT12_STATUS_Pos 12U /*!< PMU OVSCLR: Event Counter 12 Overflow Clear Position */ +#define PMU_OVSCLR_CNT12_STATUS_Msk (1UL << PMU_OVSCLR_CNT12_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 12 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT13_STATUS_Pos 13U /*!< PMU OVSCLR: Event Counter 13 Overflow Clear Position */ +#define PMU_OVSCLR_CNT13_STATUS_Msk (1UL << PMU_OVSCLR_CNT13_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 13 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT14_STATUS_Pos 14U /*!< PMU OVSCLR: Event Counter 14 Overflow Clear Position */ +#define PMU_OVSCLR_CNT14_STATUS_Msk (1UL << PMU_OVSCLR_CNT14_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 14 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT15_STATUS_Pos 15U /*!< PMU OVSCLR: Event Counter 15 Overflow Clear Position */ +#define PMU_OVSCLR_CNT15_STATUS_Msk (1UL << PMU_OVSCLR_CNT15_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 15 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT16_STATUS_Pos 16U /*!< PMU OVSCLR: Event Counter 16 Overflow Clear Position */ +#define PMU_OVSCLR_CNT16_STATUS_Msk (1UL << PMU_OVSCLR_CNT16_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 16 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT17_STATUS_Pos 17U /*!< PMU OVSCLR: Event Counter 17 Overflow Clear Position */ +#define PMU_OVSCLR_CNT17_STATUS_Msk (1UL << PMU_OVSCLR_CNT17_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 17 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT18_STATUS_Pos 18U /*!< PMU OVSCLR: Event Counter 18 Overflow Clear Position */ +#define PMU_OVSCLR_CNT18_STATUS_Msk (1UL << PMU_OVSCLR_CNT18_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 18 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT19_STATUS_Pos 19U /*!< PMU OVSCLR: Event Counter 19 Overflow Clear Position */ +#define PMU_OVSCLR_CNT19_STATUS_Msk (1UL << PMU_OVSCLR_CNT19_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 19 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT20_STATUS_Pos 20U /*!< PMU OVSCLR: Event Counter 20 Overflow Clear Position */ +#define PMU_OVSCLR_CNT20_STATUS_Msk (1UL << PMU_OVSCLR_CNT20_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 20 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT21_STATUS_Pos 21U /*!< PMU OVSCLR: Event Counter 21 Overflow Clear Position */ +#define PMU_OVSCLR_CNT21_STATUS_Msk (1UL << PMU_OVSCLR_CNT21_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 21 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT22_STATUS_Pos 22U /*!< PMU OVSCLR: Event Counter 22 Overflow Clear Position */ +#define PMU_OVSCLR_CNT22_STATUS_Msk (1UL << PMU_OVSCLR_CNT22_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 22 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT23_STATUS_Pos 23U /*!< PMU OVSCLR: Event Counter 23 Overflow Clear Position */ +#define PMU_OVSCLR_CNT23_STATUS_Msk (1UL << PMU_OVSCLR_CNT23_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 23 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT24_STATUS_Pos 24U /*!< PMU OVSCLR: Event Counter 24 Overflow Clear Position */ +#define PMU_OVSCLR_CNT24_STATUS_Msk (1UL << PMU_OVSCLR_CNT24_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 24 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT25_STATUS_Pos 25U /*!< PMU OVSCLR: Event Counter 25 Overflow Clear Position */ +#define PMU_OVSCLR_CNT25_STATUS_Msk (1UL << PMU_OVSCLR_CNT25_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 25 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT26_STATUS_Pos 26U /*!< PMU OVSCLR: Event Counter 26 Overflow Clear Position */ +#define PMU_OVSCLR_CNT26_STATUS_Msk (1UL << PMU_OVSCLR_CNT26_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 26 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT27_STATUS_Pos 27U /*!< PMU OVSCLR: Event Counter 27 Overflow Clear Position */ +#define PMU_OVSCLR_CNT27_STATUS_Msk (1UL << PMU_OVSCLR_CNT27_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 27 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT28_STATUS_Pos 28U /*!< PMU OVSCLR: Event Counter 28 Overflow Clear Position */ +#define PMU_OVSCLR_CNT28_STATUS_Msk (1UL << PMU_OVSCLR_CNT28_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 28 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT29_STATUS_Pos 29U /*!< PMU OVSCLR: Event Counter 29 Overflow Clear Position */ +#define PMU_OVSCLR_CNT29_STATUS_Msk (1UL << PMU_OVSCLR_CNT29_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 29 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT30_STATUS_Pos 30U /*!< PMU OVSCLR: Event Counter 30 Overflow Clear Position */ +#define PMU_OVSCLR_CNT30_STATUS_Msk (1UL << PMU_OVSCLR_CNT30_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 30 Overflow Clear Mask */ + +#define PMU_OVSCLR_CYCCNT_STATUS_Pos 31U /*!< PMU OVSCLR: Cycle Counter Overflow Clear Position */ +#define PMU_OVSCLR_CYCCNT_STATUS_Msk (1UL << PMU_OVSCLR_CYCCNT_STATUS_Pos) /*!< PMU OVSCLR: Cycle Counter Overflow Clear Mask */ + +/** \brief PMU Software Increment Counter */ + +#define PMU_SWINC_CNT0_Pos 0U /*!< PMU SWINC: Event Counter 0 Software Increment Position */ +#define PMU_SWINC_CNT0_Msk (1UL /*<< PMU_SWINC_CNT0_Pos */) /*!< PMU SWINC: Event Counter 0 Software Increment Mask */ + +#define PMU_SWINC_CNT1_Pos 1U /*!< PMU SWINC: Event Counter 1 Software Increment Position */ +#define PMU_SWINC_CNT1_Msk (1UL << PMU_SWINC_CNT1_Pos) /*!< PMU SWINC: Event Counter 1 Software Increment Mask */ + +#define PMU_SWINC_CNT2_Pos 2U /*!< PMU SWINC: Event Counter 2 Software Increment Position */ +#define PMU_SWINC_CNT2_Msk (1UL << PMU_SWINC_CNT2_Pos) /*!< PMU SWINC: Event Counter 2 Software Increment Mask */ + +#define PMU_SWINC_CNT3_Pos 3U /*!< PMU SWINC: Event Counter 3 Software Increment Position */ +#define PMU_SWINC_CNT3_Msk (1UL << PMU_SWINC_CNT3_Pos) /*!< PMU SWINC: Event Counter 3 Software Increment Mask */ + +#define PMU_SWINC_CNT4_Pos 4U /*!< PMU SWINC: Event Counter 4 Software Increment Position */ +#define PMU_SWINC_CNT4_Msk (1UL << PMU_SWINC_CNT4_Pos) /*!< PMU SWINC: Event Counter 4 Software Increment Mask */ + +#define PMU_SWINC_CNT5_Pos 5U /*!< PMU SWINC: Event Counter 5 Software Increment Position */ +#define PMU_SWINC_CNT5_Msk (1UL << PMU_SWINC_CNT5_Pos) /*!< PMU SWINC: Event Counter 5 Software Increment Mask */ + +#define PMU_SWINC_CNT6_Pos 6U /*!< PMU SWINC: Event Counter 6 Software Increment Position */ +#define PMU_SWINC_CNT6_Msk (1UL << PMU_SWINC_CNT6_Pos) /*!< PMU SWINC: Event Counter 6 Software Increment Mask */ + +#define PMU_SWINC_CNT7_Pos 7U /*!< PMU SWINC: Event Counter 7 Software Increment Position */ +#define PMU_SWINC_CNT7_Msk (1UL << PMU_SWINC_CNT7_Pos) /*!< PMU SWINC: Event Counter 7 Software Increment Mask */ + +#define PMU_SWINC_CNT8_Pos 8U /*!< PMU SWINC: Event Counter 8 Software Increment Position */ +#define PMU_SWINC_CNT8_Msk (1UL << PMU_SWINC_CNT8_Pos) /*!< PMU SWINC: Event Counter 8 Software Increment Mask */ + +#define PMU_SWINC_CNT9_Pos 9U /*!< PMU SWINC: Event Counter 9 Software Increment Position */ +#define PMU_SWINC_CNT9_Msk (1UL << PMU_SWINC_CNT9_Pos) /*!< PMU SWINC: Event Counter 9 Software Increment Mask */ + +#define PMU_SWINC_CNT10_Pos 10U /*!< PMU SWINC: Event Counter 10 Software Increment Position */ +#define PMU_SWINC_CNT10_Msk (1UL << PMU_SWINC_CNT10_Pos) /*!< PMU SWINC: Event Counter 10 Software Increment Mask */ + +#define PMU_SWINC_CNT11_Pos 11U /*!< PMU SWINC: Event Counter 11 Software Increment Position */ +#define PMU_SWINC_CNT11_Msk (1UL << PMU_SWINC_CNT11_Pos) /*!< PMU SWINC: Event Counter 11 Software Increment Mask */ + +#define PMU_SWINC_CNT12_Pos 12U /*!< PMU SWINC: Event Counter 12 Software Increment Position */ +#define PMU_SWINC_CNT12_Msk (1UL << PMU_SWINC_CNT12_Pos) /*!< PMU SWINC: Event Counter 12 Software Increment Mask */ + +#define PMU_SWINC_CNT13_Pos 13U /*!< PMU SWINC: Event Counter 13 Software Increment Position */ +#define PMU_SWINC_CNT13_Msk (1UL << PMU_SWINC_CNT13_Pos) /*!< PMU SWINC: Event Counter 13 Software Increment Mask */ + +#define PMU_SWINC_CNT14_Pos 14U /*!< PMU SWINC: Event Counter 14 Software Increment Position */ +#define PMU_SWINC_CNT14_Msk (1UL << PMU_SWINC_CNT14_Pos) /*!< PMU SWINC: Event Counter 14 Software Increment Mask */ + +#define PMU_SWINC_CNT15_Pos 15U /*!< PMU SWINC: Event Counter 15 Software Increment Position */ +#define PMU_SWINC_CNT15_Msk (1UL << PMU_SWINC_CNT15_Pos) /*!< PMU SWINC: Event Counter 15 Software Increment Mask */ + +#define PMU_SWINC_CNT16_Pos 16U /*!< PMU SWINC: Event Counter 16 Software Increment Position */ +#define PMU_SWINC_CNT16_Msk (1UL << PMU_SWINC_CNT16_Pos) /*!< PMU SWINC: Event Counter 16 Software Increment Mask */ + +#define PMU_SWINC_CNT17_Pos 17U /*!< PMU SWINC: Event Counter 17 Software Increment Position */ +#define PMU_SWINC_CNT17_Msk (1UL << PMU_SWINC_CNT17_Pos) /*!< PMU SWINC: Event Counter 17 Software Increment Mask */ + +#define PMU_SWINC_CNT18_Pos 18U /*!< PMU SWINC: Event Counter 18 Software Increment Position */ +#define PMU_SWINC_CNT18_Msk (1UL << PMU_SWINC_CNT18_Pos) /*!< PMU SWINC: Event Counter 18 Software Increment Mask */ + +#define PMU_SWINC_CNT19_Pos 19U /*!< PMU SWINC: Event Counter 19 Software Increment Position */ +#define PMU_SWINC_CNT19_Msk (1UL << PMU_SWINC_CNT19_Pos) /*!< PMU SWINC: Event Counter 19 Software Increment Mask */ + +#define PMU_SWINC_CNT20_Pos 20U /*!< PMU SWINC: Event Counter 20 Software Increment Position */ +#define PMU_SWINC_CNT20_Msk (1UL << PMU_SWINC_CNT20_Pos) /*!< PMU SWINC: Event Counter 20 Software Increment Mask */ + +#define PMU_SWINC_CNT21_Pos 21U /*!< PMU SWINC: Event Counter 21 Software Increment Position */ +#define PMU_SWINC_CNT21_Msk (1UL << PMU_SWINC_CNT21_Pos) /*!< PMU SWINC: Event Counter 21 Software Increment Mask */ + +#define PMU_SWINC_CNT22_Pos 22U /*!< PMU SWINC: Event Counter 22 Software Increment Position */ +#define PMU_SWINC_CNT22_Msk (1UL << PMU_SWINC_CNT22_Pos) /*!< PMU SWINC: Event Counter 22 Software Increment Mask */ + +#define PMU_SWINC_CNT23_Pos 23U /*!< PMU SWINC: Event Counter 23 Software Increment Position */ +#define PMU_SWINC_CNT23_Msk (1UL << PMU_SWINC_CNT23_Pos) /*!< PMU SWINC: Event Counter 23 Software Increment Mask */ + +#define PMU_SWINC_CNT24_Pos 24U /*!< PMU SWINC: Event Counter 24 Software Increment Position */ +#define PMU_SWINC_CNT24_Msk (1UL << PMU_SWINC_CNT24_Pos) /*!< PMU SWINC: Event Counter 24 Software Increment Mask */ + +#define PMU_SWINC_CNT25_Pos 25U /*!< PMU SWINC: Event Counter 25 Software Increment Position */ +#define PMU_SWINC_CNT25_Msk (1UL << PMU_SWINC_CNT25_Pos) /*!< PMU SWINC: Event Counter 25 Software Increment Mask */ + +#define PMU_SWINC_CNT26_Pos 26U /*!< PMU SWINC: Event Counter 26 Software Increment Position */ +#define PMU_SWINC_CNT26_Msk (1UL << PMU_SWINC_CNT26_Pos) /*!< PMU SWINC: Event Counter 26 Software Increment Mask */ + +#define PMU_SWINC_CNT27_Pos 27U /*!< PMU SWINC: Event Counter 27 Software Increment Position */ +#define PMU_SWINC_CNT27_Msk (1UL << PMU_SWINC_CNT27_Pos) /*!< PMU SWINC: Event Counter 27 Software Increment Mask */ + +#define PMU_SWINC_CNT28_Pos 28U /*!< PMU SWINC: Event Counter 28 Software Increment Position */ +#define PMU_SWINC_CNT28_Msk (1UL << PMU_SWINC_CNT28_Pos) /*!< PMU SWINC: Event Counter 28 Software Increment Mask */ + +#define PMU_SWINC_CNT29_Pos 29U /*!< PMU SWINC: Event Counter 29 Software Increment Position */ +#define PMU_SWINC_CNT29_Msk (1UL << PMU_SWINC_CNT29_Pos) /*!< PMU SWINC: Event Counter 29 Software Increment Mask */ + +#define PMU_SWINC_CNT30_Pos 30U /*!< PMU SWINC: Event Counter 30 Software Increment Position */ +#define PMU_SWINC_CNT30_Msk (1UL << PMU_SWINC_CNT30_Pos) /*!< PMU SWINC: Event Counter 30 Software Increment Mask */ + +/** \brief PMU Control Register Definitions */ + +#define PMU_CTRL_ENABLE_Pos 0U /*!< PMU CTRL: ENABLE Position */ +#define PMU_CTRL_ENABLE_Msk (1UL /*<< PMU_CTRL_ENABLE_Pos*/) /*!< PMU CTRL: ENABLE Mask */ + +#define PMU_CTRL_EVENTCNT_RESET_Pos 1U /*!< PMU CTRL: Event Counter Reset Position */ +#define PMU_CTRL_EVENTCNT_RESET_Msk (1UL << PMU_CTRL_EVENTCNT_RESET_Pos) /*!< PMU CTRL: Event Counter Reset Mask */ + +#define PMU_CTRL_CYCCNT_RESET_Pos 2U /*!< PMU CTRL: Cycle Counter Reset Position */ +#define PMU_CTRL_CYCCNT_RESET_Msk (1UL << PMU_CTRL_CYCCNT_RESET_Pos) /*!< PMU CTRL: Cycle Counter Reset Mask */ + +#define PMU_CTRL_CYCCNT_DISABLE_Pos 5U /*!< PMU CTRL: Disable Cycle Counter Position */ +#define PMU_CTRL_CYCCNT_DISABLE_Msk (1UL << PMU_CTRL_CYCCNT_DISABLE_Pos) /*!< PMU CTRL: Disable Cycle Counter Mask */ + +#define PMU_CTRL_FRZ_ON_OV_Pos 9U /*!< PMU CTRL: Freeze-on-overflow Position */ +#define PMU_CTRL_FRZ_ON_OV_Msk (1UL << PMU_CTRL_FRZ_ON_OVERFLOW_Pos) /*!< PMU CTRL: Freeze-on-overflow Mask */ + +#define PMU_CTRL_TRACE_ON_OV_Pos 11U /*!< PMU CTRL: Trace-on-overflow Position */ +#define PMU_CTRL_TRACE_ON_OV_Msk (1UL << PMU_CTRL_TRACE_ON_OVERFLOW_Pos) /*!< PMU CTRL: Trace-on-overflow Mask */ + +/** \brief PMU Type Register Definitions */ + +#define PMU_TYPE_NUM_CNTS_Pos 0U /*!< PMU TYPE: Number of Counters Position */ +#define PMU_TYPE_NUM_CNTS_Msk (0xFFUL /*<< PMU_TYPE_NUM_CNTS_Pos*/) /*!< PMU TYPE: Number of Counters Mask */ + +#define PMU_TYPE_SIZE_CNTS_Pos 8U /*!< PMU TYPE: Size of Counters Position */ +#define PMU_TYPE_SIZE_CNTS_Msk (0x3FUL << PMU_TYPE_SIZE_CNTS_Pos) /*!< PMU TYPE: Size of Counters Mask */ + +#define PMU_TYPE_CYCCNT_PRESENT_Pos 14U /*!< PMU TYPE: Cycle Counter Present Position */ +#define PMU_TYPE_CYCCNT_PRESENT_Msk (1UL << PMU_TYPE_CYCCNT_PRESENT_Pos) /*!< PMU TYPE: Cycle Counter Present Mask */ + +#define PMU_TYPE_FRZ_OV_SUPPORT_Pos 21U /*!< PMU TYPE: Freeze-on-overflow Support Position */ +#define PMU_TYPE_FRZ_OV_SUPPORT_Msk (1UL << PMU_TYPE_FRZ_OV_SUPPORT_Pos) /*!< PMU TYPE: Freeze-on-overflow Support Mask */ + +#define PMU_TYPE_TRACE_ON_OV_SUPPORT_Pos 23U /*!< PMU TYPE: Trace-on-overflow Support Position */ +#define PMU_TYPE_TRACE_ON_OV_SUPPORT_Msk (1UL << PMU_TYPE_FRZ_OV_SUPPORT_Pos) /*!< PMU TYPE: Trace-on-overflow Support Mask */ + +/** \brief PMU Authentication Status Register Definitions */ + +#define PMU_AUTHSTATUS_NSID_Pos 0U /*!< PMU AUTHSTATUS: Non-secure Invasive Debug Position */ +#define PMU_AUTHSTATUS_NSID_Msk (0x3UL /*<< PMU_AUTHSTATUS_NSID_Pos*/) /*!< PMU AUTHSTATUS: Non-secure Invasive Debug Mask */ + +#define PMU_AUTHSTATUS_NSNID_Pos 2U /*!< PMU AUTHSTATUS: Non-secure Non-invasive Debug Position */ +#define PMU_AUTHSTATUS_NSNID_Msk (0x3UL << PMU_AUTHSTATUS_NSNID_Pos) /*!< PMU AUTHSTATUS: Non-secure Non-invasive Debug Mask */ + +#define PMU_AUTHSTATUS_SID_Pos 4U /*!< PMU AUTHSTATUS: Secure Invasive Debug Position */ +#define PMU_AUTHSTATUS_SID_Msk (0x3UL << PMU_AUTHSTATUS_SID_Pos) /*!< PMU AUTHSTATUS: Secure Invasive Debug Mask */ + +#define PMU_AUTHSTATUS_SNID_Pos 6U /*!< PMU AUTHSTATUS: Secure Non-invasive Debug Position */ +#define PMU_AUTHSTATUS_SNID_Msk (0x3UL << PMU_AUTHSTATUS_SNID_Pos) /*!< PMU AUTHSTATUS: Secure Non-invasive Debug Mask */ + +#define PMU_AUTHSTATUS_NSUID_Pos 16U /*!< PMU AUTHSTATUS: Non-secure Unprivileged Invasive Debug Position */ +#define PMU_AUTHSTATUS_NSUID_Msk (0x3UL << PMU_AUTHSTATUS_NSUID_Pos) /*!< PMU AUTHSTATUS: Non-secure Unprivileged Invasive Debug Mask */ + +#define PMU_AUTHSTATUS_NSUNID_Pos 18U /*!< PMU AUTHSTATUS: Non-secure Unprivileged Non-invasive Debug Position */ +#define PMU_AUTHSTATUS_NSUNID_Msk (0x3UL << PMU_AUTHSTATUS_NSUNID_Pos) /*!< PMU AUTHSTATUS: Non-secure Unprivileged Non-invasive Debug Mask */ + +#define PMU_AUTHSTATUS_SUID_Pos 20U /*!< PMU AUTHSTATUS: Secure Unprivileged Invasive Debug Position */ +#define PMU_AUTHSTATUS_SUID_Msk (0x3UL << PMU_AUTHSTATUS_SUID_Pos) /*!< PMU AUTHSTATUS: Secure Unprivileged Invasive Debug Mask */ + +#define PMU_AUTHSTATUS_SUNID_Pos 22U /*!< PMU AUTHSTATUS: Secure Unprivileged Non-invasive Debug Position */ +#define PMU_AUTHSTATUS_SUNID_Msk (0x3UL << PMU_AUTHSTATUS_SUNID_Pos) /*!< PMU AUTHSTATUS: Secure Unprivileged Non-invasive Debug Mask */ + + +/*@} end of group CMSIS_PMU */ +#endif + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */ + __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */ + __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */ + __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */ + uint32_t RESERVED0[1]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ +#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/* MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_PXN_Pos 4U /*!< MPU RLAR: PXN Position */ +#define MPU_RLAR_PXN_Msk (1UL << MPU_RLAR_PXN_Pos) /*!< MPU RLAR: PXN Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */ + +/* MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/* MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#else + uint32_t RESERVED0[3]; +#endif + __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */ +} SAU_Type; + +/* SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/* SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/* SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/* SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/* SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/* Secure Fault Status Register Definitions */ +#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */ +#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */ + +#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */ +#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */ + +#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */ +#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */ + +#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */ +#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */ + +#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */ +#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */ + +#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */ +#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */ + +#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */ +#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */ + +#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */ +#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and VFP Feature Register 2 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */ +#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */ + +#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */ +#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */ + +#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */ +#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */ + +#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */ +#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */ + +#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */ +#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */ + +#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */ +#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */ +#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */ +#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +#define FPU_FPDSCR_FZ16_Pos 19U /*!< FPDSCR: FZ16 bit Position */ +#define FPU_FPDSCR_FZ16_Msk (1UL << FPU_FPDSCR_FZ16_Pos) /*!< FPDSCR: FZ16 bit Mask */ + +#define FPU_FPDSCR_LTPSIZE_Pos 16U /*!< FPDSCR: LTPSIZE bit Position */ +#define FPU_FPDSCR_LTPSIZE_Msk (7UL << FPU_FPDSCR_LTPSIZE_Pos) /*!< FPDSCR: LTPSIZE bit Mask */ + +/* Media and VFP Feature Register 0 Definitions */ +#define FPU_MVFR0_FPRound_Pos 28U /*!< MVFR0: FPRound bits Position */ +#define FPU_MVFR0_FPRound_Msk (0xFUL << FPU_MVFR0_FPRound_Pos) /*!< MVFR0: FPRound bits Mask */ + +#define FPU_MVFR0_FPSqrt_Pos 20U /*!< MVFR0: FPSqrt bits Position */ +#define FPU_MVFR0_FPSqrt_Msk (0xFUL << FPU_MVFR0_FPSqrt_Pos) /*!< MVFR0: FPSqrt bits Mask */ + +#define FPU_MVFR0_FPDivide_Pos 16U /*!< MVFR0: FPDivide bits Position */ +#define FPU_MVFR0_FPDivide_Msk (0xFUL << FPU_MVFR0_FPDivide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FPDP_Pos 8U /*!< MVFR0: FPDP bits Position */ +#define FPU_MVFR0_FPDP_Msk (0xFUL << FPU_MVFR0_FPDP_Pos) /*!< MVFR0: FPDP bits Mask */ + +#define FPU_MVFR0_FPSP_Pos 4U /*!< MVFR0: FPSP bits Position */ +#define FPU_MVFR0_FPSP_Msk (0xFUL << FPU_MVFR0_FPSP_Pos) /*!< MVFR0: FPSP bits Mask */ + +#define FPU_MVFR0_SIMDReg_Pos 0U /*!< MVFR0: SIMDReg bits Position */ +#define FPU_MVFR0_SIMDReg_Msk (0xFUL /*<< FPU_MVFR0_SIMDReg_Pos*/) /*!< MVFR0: SIMDReg bits Mask */ + +/* Media and VFP Feature Register 1 Definitions */ +#define FPU_MVFR1_FMAC_Pos 28U /*!< MVFR1: FMAC bits Position */ +#define FPU_MVFR1_FMAC_Msk (0xFUL << FPU_MVFR1_FMAC_Pos) /*!< MVFR1: FMAC bits Mask */ + +#define FPU_MVFR1_FPHP_Pos 24U /*!< MVFR1: FPHP bits Position */ +#define FPU_MVFR1_FPHP_Msk (0xFUL << FPU_MVFR1_FPHP_Pos) /*!< MVFR1: FPHP bits Mask */ + +#define FPU_MVFR1_FP16_Pos 20U /*!< MVFR1: FP16 bits Position */ +#define FPU_MVFR1_FP16_Msk (0xFUL << FPU_MVFR1_FP16_Pos) /*!< MVFR1: FP16 bits Mask */ + +#define FPU_MVFR1_MVE_Pos 8U /*!< MVFR1: MVE bits Position */ +#define FPU_MVFR1_MVE_Msk (0xFUL << FPU_MVFR1_MVE_Pos) /*!< MVFR1: MVE bits Mask */ + +#define FPU_MVFR1_FPDNaN_Pos 4U /*!< MVFR1: FPDNaN bits Position */ +#define FPU_MVFR1_FPDNaN_Msk (0xFUL << FPU_MVFR1_FPDNaN_Pos) /*!< MVFR1: FPDNaN bits Mask */ + +#define FPU_MVFR1_FPFtZ_Pos 0U /*!< MVFR1: FPFtZ bits Position */ +#define FPU_MVFR1_FPFtZ_Msk (0xFUL /*<< FPU_MVFR1_FPFtZ_Pos*/) /*!< MVFR1: FPFtZ bits Mask */ + +/* Media and VFP Feature Register 2 Definitions */ +#define FPU_MVFR2_FPMisc_Pos 4U /*!< MVFR2: FPMisc bits Position */ +#define FPU_MVFR2_FPMisc_Msk (0xFUL << FPU_MVFR2_FPMisc_Pos) /*!< MVFR2: FPMisc bits Mask */ + +/*@} end of group CMSIS_FPU */ + +/* CoreDebug is deprecated. replaced by DCB (Debug Control Block) */ +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief \deprecated Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + __OM uint32_t DSCEMCR; /*!< Offset: 0x010 ( /W) Debug Set Clear Exception and Monitor Control Register */ + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< \deprecated CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< \deprecated CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Position */ +#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_FPD_Pos 23U /*!< \deprecated CoreDebug DHCSR: S_FPD Position */ +#define CoreDebug_DHCSR_S_FPD_Msk (1UL << CoreDebug_DHCSR_S_FPD_Pos) /*!< \deprecated CoreDebug DHCSR: S_FPD Mask */ + +#define CoreDebug_DHCSR_S_SUIDE_Pos 22U /*!< \deprecated CoreDebug DHCSR: S_SUIDE Position */ +#define CoreDebug_DHCSR_S_SUIDE_Msk (1UL << CoreDebug_DHCSR_S_SUIDE_Pos) /*!< \deprecated CoreDebug DHCSR: S_SUIDE Mask */ + +#define CoreDebug_DHCSR_S_NSUIDE_Pos 21U /*!< \deprecated CoreDebug DHCSR: S_NSUIDE Position */ +#define CoreDebug_DHCSR_S_NSUIDE_Msk (1UL << CoreDebug_DHCSR_S_NSUIDE_Pos) /*!< \deprecated CoreDebug DHCSR: S_NSUIDE Mask */ + +#define CoreDebug_DHCSR_S_SDE_Pos 20U /*!< \deprecated CoreDebug DHCSR: S_SDE Position */ +#define CoreDebug_DHCSR_S_SDE_Msk (1UL << CoreDebug_DHCSR_S_SDE_Pos) /*!< \deprecated CoreDebug DHCSR: S_SDE Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< \deprecated CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< \deprecated CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< \deprecated CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< \deprecated CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< \deprecated CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_PMOV_Pos 6U /*!< \deprecated CoreDebug DHCSR: C_PMOV Position */ +#define CoreDebug_DHCSR_C_PMOV_Msk (1UL << CoreDebug_DHCSR_C_PMOV_Pos) /*!< \deprecated CoreDebug DHCSR: C_PMOV Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< \deprecated CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< \deprecated CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< \deprecated CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< \deprecated CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< \deprecated CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< \deprecated CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< \deprecated CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< \deprecated CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< \deprecated CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< \deprecated CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< \deprecated CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< \deprecated CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< \deprecated CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< \deprecated CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< \deprecated CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< \deprecated CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< \deprecated CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< \deprecated CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< \deprecated CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< \deprecated CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< \deprecated CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< \deprecated CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< \deprecated CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< \deprecated CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< \deprecated CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Mask */ + +/* Debug Set Clear Exception and Monitor Control Register Definitions */ +#define CoreDebug_DSCEMCR_CLR_MON_REQ_Pos 19U /*!< \deprecated CoreDebug DSCEMCR: CLR_MON_REQ, Position */ +#define CoreDebug_DSCEMCR_CLR_MON_REQ_Msk (1UL << CoreDebug_DSCEMCR_CLR_MON_REQ_Pos) /*!< \deprecated CoreDebug DSCEMCR: CLR_MON_REQ, Mask */ + +#define CoreDebug_DSCEMCR_CLR_MON_PEND_Pos 17U /*!< \deprecated CoreDebug DSCEMCR: CLR_MON_PEND, Position */ +#define CoreDebug_DSCEMCR_CLR_MON_PEND_Msk (1UL << CoreDebug_DSCEMCR_CLR_MON_PEND_Pos) /*!< \deprecated CoreDebug DSCEMCR: CLR_MON_PEND, Mask */ + +#define CoreDebug_DSCEMCR_SET_MON_REQ_Pos 3U /*!< \deprecated CoreDebug DSCEMCR: SET_MON_REQ, Position */ +#define CoreDebug_DSCEMCR_SET_MON_REQ_Msk (1UL << CoreDebug_DSCEMCR_SET_MON_REQ_Pos) /*!< \deprecated CoreDebug DSCEMCR: SET_MON_REQ, Mask */ + +#define CoreDebug_DSCEMCR_SET_MON_PEND_Pos 1U /*!< \deprecated CoreDebug DSCEMCR: SET_MON_PEND, Position */ +#define CoreDebug_DSCEMCR_SET_MON_PEND_Msk (1UL << CoreDebug_DSCEMCR_SET_MON_PEND_Pos) /*!< \deprecated CoreDebug DSCEMCR: SET_MON_PEND, Mask */ + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_UIDEN_Pos 10U /*!< \deprecated CoreDebug DAUTHCTRL: UIDEN, Position */ +#define CoreDebug_DAUTHCTRL_UIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_UIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: UIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_UIDAPEN_Pos 9U /*!< \deprecated CoreDebug DAUTHCTRL: UIDAPEN, Position */ +#define CoreDebug_DAUTHCTRL_UIDAPEN_Msk (1UL << CoreDebug_DAUTHCTRL_UIDAPEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: UIDAPEN, Mask */ + +#define CoreDebug_DAUTHCTRL_FSDMA_Pos 8U /*!< \deprecated CoreDebug DAUTHCTRL: FSDMA, Position */ +#define CoreDebug_DAUTHCTRL_FSDMA_Msk (1UL << CoreDebug_DAUTHCTRL_FSDMA_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: FSDMA, Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Position */ +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Mask */ + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Mask */ + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos 16U /*!< \deprecated CoreDebug DSCSR: CDS Position */ +#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< \deprecated CoreDebug DSCSR: CDS Mask */ + +#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< \deprecated CoreDebug DSCSR: SBRSEL Position */ +#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< \deprecated CoreDebug DSCSR: SBRSEL Mask */ + +#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< \deprecated CoreDebug DSCSR: SBRSELEN Position */ +#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< \deprecated CoreDebug DSCSR: SBRSELEN Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DCB Debug Control Block + \brief Type definitions for the Debug Control Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Control Block Registers (DCB). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + __OM uint32_t DSCEMCR; /*!< Offset: 0x010 ( /W) Debug Set Clear Exception and Monitor Control Register */ + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} DCB_Type; + +/* DHCSR, Debug Halting Control and Status Register Definitions */ +#define DCB_DHCSR_DBGKEY_Pos 16U /*!< DCB DHCSR: Debug key Position */ +#define DCB_DHCSR_DBGKEY_Msk (0xFFFFUL << DCB_DHCSR_DBGKEY_Pos) /*!< DCB DHCSR: Debug key Mask */ + +#define DCB_DHCSR_S_RESTART_ST_Pos 26U /*!< DCB DHCSR: Restart sticky status Position */ +#define DCB_DHCSR_S_RESTART_ST_Msk (0x1UL << DCB_DHCSR_S_RESTART_ST_Pos) /*!< DCB DHCSR: Restart sticky status Mask */ + +#define DCB_DHCSR_S_RESET_ST_Pos 25U /*!< DCB DHCSR: Reset sticky status Position */ +#define DCB_DHCSR_S_RESET_ST_Msk (0x1UL << DCB_DHCSR_S_RESET_ST_Pos) /*!< DCB DHCSR: Reset sticky status Mask */ + +#define DCB_DHCSR_S_RETIRE_ST_Pos 24U /*!< DCB DHCSR: Retire sticky status Position */ +#define DCB_DHCSR_S_RETIRE_ST_Msk (0x1UL << DCB_DHCSR_S_RETIRE_ST_Pos) /*!< DCB DHCSR: Retire sticky status Mask */ + +#define DCB_DHCSR_S_FPD_Pos 23U /*!< DCB DHCSR: Floating-point registers Debuggable Position */ +#define DCB_DHCSR_S_FPD_Msk (0x1UL << DCB_DHCSR_S_FPD_Pos) /*!< DCB DHCSR: Floating-point registers Debuggable Mask */ + +#define DCB_DHCSR_S_SUIDE_Pos 22U /*!< DCB DHCSR: Secure unprivileged halting debug enabled Position */ +#define DCB_DHCSR_S_SUIDE_Msk (0x1UL << DCB_DHCSR_S_SUIDE_Pos) /*!< DCB DHCSR: Secure unprivileged halting debug enabled Mask */ + +#define DCB_DHCSR_S_NSUIDE_Pos 21U /*!< DCB DHCSR: Non-secure unprivileged halting debug enabled Position */ +#define DCB_DHCSR_S_NSUIDE_Msk (0x1UL << DCB_DHCSR_S_NSUIDE_Pos) /*!< DCB DHCSR: Non-secure unprivileged halting debug enabled Mask */ + +#define DCB_DHCSR_S_SDE_Pos 20U /*!< DCB DHCSR: Secure debug enabled Position */ +#define DCB_DHCSR_S_SDE_Msk (0x1UL << DCB_DHCSR_S_SDE_Pos) /*!< DCB DHCSR: Secure debug enabled Mask */ + +#define DCB_DHCSR_S_LOCKUP_Pos 19U /*!< DCB DHCSR: Lockup status Position */ +#define DCB_DHCSR_S_LOCKUP_Msk (0x1UL << DCB_DHCSR_S_LOCKUP_Pos) /*!< DCB DHCSR: Lockup status Mask */ + +#define DCB_DHCSR_S_SLEEP_Pos 18U /*!< DCB DHCSR: Sleeping status Position */ +#define DCB_DHCSR_S_SLEEP_Msk (0x1UL << DCB_DHCSR_S_SLEEP_Pos) /*!< DCB DHCSR: Sleeping status Mask */ + +#define DCB_DHCSR_S_HALT_Pos 17U /*!< DCB DHCSR: Halted status Position */ +#define DCB_DHCSR_S_HALT_Msk (0x1UL << DCB_DHCSR_S_HALT_Pos) /*!< DCB DHCSR: Halted status Mask */ + +#define DCB_DHCSR_S_REGRDY_Pos 16U /*!< DCB DHCSR: Register ready status Position */ +#define DCB_DHCSR_S_REGRDY_Msk (0x1UL << DCB_DHCSR_S_REGRDY_Pos) /*!< DCB DHCSR: Register ready status Mask */ + +#define DCB_DHCSR_C_PMOV_Pos 6U /*!< DCB DHCSR: Halt on PMU overflow control Position */ +#define DCB_DHCSR_C_PMOV_Msk (0x1UL << DCB_DHCSR_C_PMOV_Pos) /*!< DCB DHCSR: Halt on PMU overflow control Mask */ + +#define DCB_DHCSR_C_SNAPSTALL_Pos 5U /*!< DCB DHCSR: Snap stall control Position */ +#define DCB_DHCSR_C_SNAPSTALL_Msk (0x1UL << DCB_DHCSR_C_SNAPSTALL_Pos) /*!< DCB DHCSR: Snap stall control Mask */ + +#define DCB_DHCSR_C_MASKINTS_Pos 3U /*!< DCB DHCSR: Mask interrupts control Position */ +#define DCB_DHCSR_C_MASKINTS_Msk (0x1UL << DCB_DHCSR_C_MASKINTS_Pos) /*!< DCB DHCSR: Mask interrupts control Mask */ + +#define DCB_DHCSR_C_STEP_Pos 2U /*!< DCB DHCSR: Step control Position */ +#define DCB_DHCSR_C_STEP_Msk (0x1UL << DCB_DHCSR_C_STEP_Pos) /*!< DCB DHCSR: Step control Mask */ + +#define DCB_DHCSR_C_HALT_Pos 1U /*!< DCB DHCSR: Halt control Position */ +#define DCB_DHCSR_C_HALT_Msk (0x1UL << DCB_DHCSR_C_HALT_Pos) /*!< DCB DHCSR: Halt control Mask */ + +#define DCB_DHCSR_C_DEBUGEN_Pos 0U /*!< DCB DHCSR: Debug enable control Position */ +#define DCB_DHCSR_C_DEBUGEN_Msk (0x1UL /*<< DCB_DHCSR_C_DEBUGEN_Pos*/) /*!< DCB DHCSR: Debug enable control Mask */ + +/* DCRSR, Debug Core Register Select Register Definitions */ +#define DCB_DCRSR_REGWnR_Pos 16U /*!< DCB DCRSR: Register write/not-read Position */ +#define DCB_DCRSR_REGWnR_Msk (0x1UL << DCB_DCRSR_REGWnR_Pos) /*!< DCB DCRSR: Register write/not-read Mask */ + +#define DCB_DCRSR_REGSEL_Pos 0U /*!< DCB DCRSR: Register selector Position */ +#define DCB_DCRSR_REGSEL_Msk (0x7FUL /*<< DCB_DCRSR_REGSEL_Pos*/) /*!< DCB DCRSR: Register selector Mask */ + +/* DCRDR, Debug Core Register Data Register Definitions */ +#define DCB_DCRDR_DBGTMP_Pos 0U /*!< DCB DCRDR: Data temporary buffer Position */ +#define DCB_DCRDR_DBGTMP_Msk (0xFFFFFFFFUL /*<< DCB_DCRDR_DBGTMP_Pos*/) /*!< DCB DCRDR: Data temporary buffer Mask */ + +/* DEMCR, Debug Exception and Monitor Control Register Definitions */ +#define DCB_DEMCR_TRCENA_Pos 24U /*!< DCB DEMCR: Trace enable Position */ +#define DCB_DEMCR_TRCENA_Msk (0x1UL << DCB_DEMCR_TRCENA_Pos) /*!< DCB DEMCR: Trace enable Mask */ + +#define DCB_DEMCR_MONPRKEY_Pos 23U /*!< DCB DEMCR: Monitor pend req key Position */ +#define DCB_DEMCR_MONPRKEY_Msk (0x1UL << DCB_DEMCR_MONPRKEY_Pos) /*!< DCB DEMCR: Monitor pend req key Mask */ + +#define DCB_DEMCR_UMON_EN_Pos 21U /*!< DCB DEMCR: Unprivileged monitor enable Position */ +#define DCB_DEMCR_UMON_EN_Msk (0x1UL << DCB_DEMCR_UMON_EN_Pos) /*!< DCB DEMCR: Unprivileged monitor enable Mask */ + +#define DCB_DEMCR_SDME_Pos 20U /*!< DCB DEMCR: Secure DebugMonitor enable Position */ +#define DCB_DEMCR_SDME_Msk (0x1UL << DCB_DEMCR_SDME_Pos) /*!< DCB DEMCR: Secure DebugMonitor enable Mask */ + +#define DCB_DEMCR_MON_REQ_Pos 19U /*!< DCB DEMCR: Monitor request Position */ +#define DCB_DEMCR_MON_REQ_Msk (0x1UL << DCB_DEMCR_MON_REQ_Pos) /*!< DCB DEMCR: Monitor request Mask */ + +#define DCB_DEMCR_MON_STEP_Pos 18U /*!< DCB DEMCR: Monitor step Position */ +#define DCB_DEMCR_MON_STEP_Msk (0x1UL << DCB_DEMCR_MON_STEP_Pos) /*!< DCB DEMCR: Monitor step Mask */ + +#define DCB_DEMCR_MON_PEND_Pos 17U /*!< DCB DEMCR: Monitor pend Position */ +#define DCB_DEMCR_MON_PEND_Msk (0x1UL << DCB_DEMCR_MON_PEND_Pos) /*!< DCB DEMCR: Monitor pend Mask */ + +#define DCB_DEMCR_MON_EN_Pos 16U /*!< DCB DEMCR: Monitor enable Position */ +#define DCB_DEMCR_MON_EN_Msk (0x1UL << DCB_DEMCR_MON_EN_Pos) /*!< DCB DEMCR: Monitor enable Mask */ + +#define DCB_DEMCR_VC_SFERR_Pos 11U /*!< DCB DEMCR: Vector Catch SecureFault Position */ +#define DCB_DEMCR_VC_SFERR_Msk (0x1UL << DCB_DEMCR_VC_SFERR_Pos) /*!< DCB DEMCR: Vector Catch SecureFault Mask */ + +#define DCB_DEMCR_VC_HARDERR_Pos 10U /*!< DCB DEMCR: Vector Catch HardFault errors Position */ +#define DCB_DEMCR_VC_HARDERR_Msk (0x1UL << DCB_DEMCR_VC_HARDERR_Pos) /*!< DCB DEMCR: Vector Catch HardFault errors Mask */ + +#define DCB_DEMCR_VC_INTERR_Pos 9U /*!< DCB DEMCR: Vector Catch interrupt errors Position */ +#define DCB_DEMCR_VC_INTERR_Msk (0x1UL << DCB_DEMCR_VC_INTERR_Pos) /*!< DCB DEMCR: Vector Catch interrupt errors Mask */ + +#define DCB_DEMCR_VC_BUSERR_Pos 8U /*!< DCB DEMCR: Vector Catch BusFault errors Position */ +#define DCB_DEMCR_VC_BUSERR_Msk (0x1UL << DCB_DEMCR_VC_BUSERR_Pos) /*!< DCB DEMCR: Vector Catch BusFault errors Mask */ + +#define DCB_DEMCR_VC_STATERR_Pos 7U /*!< DCB DEMCR: Vector Catch state errors Position */ +#define DCB_DEMCR_VC_STATERR_Msk (0x1UL << DCB_DEMCR_VC_STATERR_Pos) /*!< DCB DEMCR: Vector Catch state errors Mask */ + +#define DCB_DEMCR_VC_CHKERR_Pos 6U /*!< DCB DEMCR: Vector Catch check errors Position */ +#define DCB_DEMCR_VC_CHKERR_Msk (0x1UL << DCB_DEMCR_VC_CHKERR_Pos) /*!< DCB DEMCR: Vector Catch check errors Mask */ + +#define DCB_DEMCR_VC_NOCPERR_Pos 5U /*!< DCB DEMCR: Vector Catch NOCP errors Position */ +#define DCB_DEMCR_VC_NOCPERR_Msk (0x1UL << DCB_DEMCR_VC_NOCPERR_Pos) /*!< DCB DEMCR: Vector Catch NOCP errors Mask */ + +#define DCB_DEMCR_VC_MMERR_Pos 4U /*!< DCB DEMCR: Vector Catch MemManage errors Position */ +#define DCB_DEMCR_VC_MMERR_Msk (0x1UL << DCB_DEMCR_VC_MMERR_Pos) /*!< DCB DEMCR: Vector Catch MemManage errors Mask */ + +#define DCB_DEMCR_VC_CORERESET_Pos 0U /*!< DCB DEMCR: Vector Catch Core reset Position */ +#define DCB_DEMCR_VC_CORERESET_Msk (0x1UL /*<< DCB_DEMCR_VC_CORERESET_Pos*/) /*!< DCB DEMCR: Vector Catch Core reset Mask */ + +/* DSCEMCR, Debug Set Clear Exception and Monitor Control Register Definitions */ +#define DCB_DSCEMCR_CLR_MON_REQ_Pos 19U /*!< DCB DSCEMCR: Clear monitor request Position */ +#define DCB_DSCEMCR_CLR_MON_REQ_Msk (0x1UL << DCB_DSCEMCR_CLR_MON_REQ_Pos) /*!< DCB DSCEMCR: Clear monitor request Mask */ + +#define DCB_DSCEMCR_CLR_MON_PEND_Pos 17U /*!< DCB DSCEMCR: Clear monitor pend Position */ +#define DCB_DSCEMCR_CLR_MON_PEND_Msk (0x1UL << DCB_DSCEMCR_CLR_MON_PEND_Pos) /*!< DCB DSCEMCR: Clear monitor pend Mask */ + +#define DCB_DSCEMCR_SET_MON_REQ_Pos 3U /*!< DCB DSCEMCR: Set monitor request Position */ +#define DCB_DSCEMCR_SET_MON_REQ_Msk (0x1UL << DCB_DSCEMCR_SET_MON_REQ_Pos) /*!< DCB DSCEMCR: Set monitor request Mask */ + +#define DCB_DSCEMCR_SET_MON_PEND_Pos 1U /*!< DCB DSCEMCR: Set monitor pend Position */ +#define DCB_DSCEMCR_SET_MON_PEND_Msk (0x1UL << DCB_DSCEMCR_SET_MON_PEND_Pos) /*!< DCB DSCEMCR: Set monitor pend Mask */ + +/* DAUTHCTRL, Debug Authentication Control Register Definitions */ +#define DCB_DAUTHCTRL_UIDEN_Pos 10U /*!< DCB DAUTHCTRL: Unprivileged Invasive Debug Enable Position */ +#define DCB_DAUTHCTRL_UIDEN_Msk (0x1UL << DCB_DAUTHCTRL_UIDEN_Pos) /*!< DCB DAUTHCTRL: Unprivileged Invasive Debug Enable Mask */ + +#define DCB_DAUTHCTRL_UIDAPEN_Pos 9U /*!< DCB DAUTHCTRL: Unprivileged Invasive DAP Access Enable Position */ +#define DCB_DAUTHCTRL_UIDAPEN_Msk (0x1UL << DCB_DAUTHCTRL_UIDAPEN_Pos) /*!< DCB DAUTHCTRL: Unprivileged Invasive DAP Access Enable Mask */ + +#define DCB_DAUTHCTRL_FSDMA_Pos 8U /*!< DCB DAUTHCTRL: Force Secure DebugMonitor Allowed Position */ +#define DCB_DAUTHCTRL_FSDMA_Msk (0x1UL << DCB_DAUTHCTRL_FSDMA_Pos) /*!< DCB DAUTHCTRL: Force Secure DebugMonitor Allowed Mask */ + +#define DCB_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPNIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPNIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPNIDENSEL_Msk (0x1UL << DCB_DAUTHCTRL_SPNIDENSEL_Pos) /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Mask */ + +#define DCB_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< DCB DAUTHCTRL: Secure invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPIDENSEL_Msk (0x1UL /*<< DCB_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< DCB DAUTHCTRL: Secure invasive debug enable select Mask */ + +/* DSCSR, Debug Security Control and Status Register Definitions */ +#define DCB_DSCSR_CDSKEY_Pos 17U /*!< DCB DSCSR: CDS write-enable key Position */ +#define DCB_DSCSR_CDSKEY_Msk (0x1UL << DCB_DSCSR_CDSKEY_Pos) /*!< DCB DSCSR: CDS write-enable key Mask */ + +#define DCB_DSCSR_CDS_Pos 16U /*!< DCB DSCSR: Current domain Secure Position */ +#define DCB_DSCSR_CDS_Msk (0x1UL << DCB_DSCSR_CDS_Pos) /*!< DCB DSCSR: Current domain Secure Mask */ + +#define DCB_DSCSR_SBRSEL_Pos 1U /*!< DCB DSCSR: Secure banked register select Position */ +#define DCB_DSCSR_SBRSEL_Msk (0x1UL << DCB_DSCSR_SBRSEL_Pos) /*!< DCB DSCSR: Secure banked register select Mask */ + +#define DCB_DSCSR_SBRSELEN_Pos 0U /*!< DCB DSCSR: Secure banked register select enable Position */ +#define DCB_DSCSR_SBRSELEN_Msk (0x1UL /*<< DCB_DSCSR_SBRSELEN_Pos*/) /*!< DCB DSCSR: Secure banked register select enable Mask */ + +/*@} end of group CMSIS_DCB */ + + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DIB Debug Identification Block + \brief Type definitions for the Debug Identification Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Identification Block Registers (DIB). + */ +typedef struct +{ + __OM uint32_t DLAR; /*!< Offset: 0x000 ( /W) SCS Software Lock Access Register */ + __IM uint32_t DLSR; /*!< Offset: 0x004 (R/ ) SCS Software Lock Status Register */ + __IM uint32_t DAUTHSTATUS; /*!< Offset: 0x008 (R/ ) Debug Authentication Status Register */ + __IM uint32_t DDEVARCH; /*!< Offset: 0x00C (R/ ) SCS Device Architecture Register */ + __IM uint32_t DDEVTYPE; /*!< Offset: 0x010 (R/ ) SCS Device Type Register */ +} DIB_Type; + +/* DLAR, SCS Software Lock Access Register Definitions */ +#define DIB_DLAR_KEY_Pos 0U /*!< DIB DLAR: KEY Position */ +#define DIB_DLAR_KEY_Msk (0xFFFFFFFFUL /*<< DIB_DLAR_KEY_Pos */) /*!< DIB DLAR: KEY Mask */ + +/* DLSR, SCS Software Lock Status Register Definitions */ +#define DIB_DLSR_nTT_Pos 2U /*!< DIB DLSR: Not thirty-two bit Position */ +#define DIB_DLSR_nTT_Msk (0x1UL << DIB_DLSR_nTT_Pos ) /*!< DIB DLSR: Not thirty-two bit Mask */ + +#define DIB_DLSR_SLK_Pos 1U /*!< DIB DLSR: Software Lock status Position */ +#define DIB_DLSR_SLK_Msk (0x1UL << DIB_DLSR_SLK_Pos ) /*!< DIB DLSR: Software Lock status Mask */ + +#define DIB_DLSR_SLI_Pos 0U /*!< DIB DLSR: Software Lock implemented Position */ +#define DIB_DLSR_SLI_Msk (0x1UL /*<< DIB_DLSR_SLI_Pos*/) /*!< DIB DLSR: Software Lock implemented Mask */ + +/* DAUTHSTATUS, Debug Authentication Status Register Definitions */ +#define DIB_DAUTHSTATUS_SUNID_Pos 22U /*!< DIB DAUTHSTATUS: Secure Unprivileged Non-invasive Debug Allowed Position */ +#define DIB_DAUTHSTATUS_SUNID_Msk (0x3UL << DIB_DAUTHSTATUS_SUNID_Pos ) /*!< DIB DAUTHSTATUS: Secure Unprivileged Non-invasive Debug Allowed Mask */ + +#define DIB_DAUTHSTATUS_SUID_Pos 20U /*!< DIB DAUTHSTATUS: Secure Unprivileged Invasive Debug Allowed Position */ +#define DIB_DAUTHSTATUS_SUID_Msk (0x3UL << DIB_DAUTHSTATUS_SUID_Pos ) /*!< DIB DAUTHSTATUS: Secure Unprivileged Invasive Debug Allowed Mask */ + +#define DIB_DAUTHSTATUS_NSUNID_Pos 18U /*!< DIB DAUTHSTATUS: Non-secure Unprivileged Non-invasive Debug Allo Position */ +#define DIB_DAUTHSTATUS_NSUNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSUNID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Unprivileged Non-invasive Debug Allo Mask */ + +#define DIB_DAUTHSTATUS_NSUID_Pos 16U /*!< DIB DAUTHSTATUS: Non-secure Unprivileged Invasive Debug Allowed Position */ +#define DIB_DAUTHSTATUS_NSUID_Msk (0x3UL << DIB_DAUTHSTATUS_NSUID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Unprivileged Invasive Debug Allowed Mask */ + +#define DIB_DAUTHSTATUS_SNID_Pos 6U /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_SNID_Msk (0x3UL << DIB_DAUTHSTATUS_SNID_Pos ) /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_SID_Pos 4U /*!< DIB DAUTHSTATUS: Secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_SID_Msk (0x3UL << DIB_DAUTHSTATUS_SID_Pos ) /*!< DIB DAUTHSTATUS: Secure Invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSNID_Pos 2U /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSNID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSID_Pos 0U /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSID_Msk (0x3UL /*<< DIB_DAUTHSTATUS_NSID_Pos*/) /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Mask */ + +/* DDEVARCH, SCS Device Architecture Register Definitions */ +#define DIB_DDEVARCH_ARCHITECT_Pos 21U /*!< DIB DDEVARCH: Architect Position */ +#define DIB_DDEVARCH_ARCHITECT_Msk (0x7FFUL << DIB_DDEVARCH_ARCHITECT_Pos ) /*!< DIB DDEVARCH: Architect Mask */ + +#define DIB_DDEVARCH_PRESENT_Pos 20U /*!< DIB DDEVARCH: DEVARCH Present Position */ +#define DIB_DDEVARCH_PRESENT_Msk (0x1FUL << DIB_DDEVARCH_PRESENT_Pos ) /*!< DIB DDEVARCH: DEVARCH Present Mask */ + +#define DIB_DDEVARCH_REVISION_Pos 16U /*!< DIB DDEVARCH: Revision Position */ +#define DIB_DDEVARCH_REVISION_Msk (0xFUL << DIB_DDEVARCH_REVISION_Pos ) /*!< DIB DDEVARCH: Revision Mask */ + +#define DIB_DDEVARCH_ARCHVER_Pos 12U /*!< DIB DDEVARCH: Architecture Version Position */ +#define DIB_DDEVARCH_ARCHVER_Msk (0xFUL << DIB_DDEVARCH_ARCHVER_Pos ) /*!< DIB DDEVARCH: Architecture Version Mask */ + +#define DIB_DDEVARCH_ARCHPART_Pos 0U /*!< DIB DDEVARCH: Architecture Part Position */ +#define DIB_DDEVARCH_ARCHPART_Msk (0xFFFUL /*<< DIB_DDEVARCH_ARCHPART_Pos*/) /*!< DIB DDEVARCH: Architecture Part Mask */ + +/* DDEVTYPE, SCS Device Type Register Definitions */ +#define DIB_DDEVTYPE_SUB_Pos 4U /*!< DIB DDEVTYPE: Sub-type Position */ +#define DIB_DDEVTYPE_SUB_Msk (0xFUL << DIB_DDEVTYPE_SUB_Pos ) /*!< DIB DDEVTYPE: Sub-type Mask */ + +#define DIB_DDEVTYPE_MAJOR_Pos 0U /*!< DIB DDEVTYPE: Major type Position */ +#define DIB_DDEVTYPE_MAJOR_Msk (0xFUL /*<< DIB_DDEVTYPE_MAJOR_Pos*/) /*!< DIB DDEVTYPE: Major type Mask */ + + +/*@} end of group CMSIS_DIB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define MEMSYSCTL_BASE (0xE001E000UL) /*!< Memory System Control Base Address */ + #define ERRBNK_BASE (0xE001E100UL) /*!< Error Banking Base Address */ + #define PWRMODCTL_BASE (0xE001E300UL) /*!< Power Mode Control Base Address */ + #define EWIC_BASE (0xE001E400UL) /*!< External Wakeup Interrupt Controller Base Address */ + #define PRCCFGINF_BASE (0xE001E700UL) /*!< Processor Configuration Information Base Address */ + #define STL_BASE (0xE001E800UL) /*!< Software Test Library Base Address */ + #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ + #define CoreDebug_BASE (0xE000EDF0UL) /*!< \deprecated Core Debug Base Address */ + #define DCB_BASE (0xE000EDF0UL) /*!< DCB Base Address */ + #define DIB_BASE (0xE000EFB0UL) /*!< DIB Base Address */ + #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + #define ICB ((ICB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ + #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ + #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ + #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ + #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ + #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ + #define MEMSYSCTL ((MemSysCtl_Type *) MEMSYSCTL_BASE ) /*!< Memory System Control configuration struct */ + #define ERRBNK ((ErrBnk_Type *) ERRBNK_BASE ) /*!< Error Banking configuration struct */ + #define PWRMODCTL ((PwrModCtl_Type *) PWRMODCTL_BASE ) /*!< Power Mode Control configuration struct */ + #define EWIC ((EWIC_Type *) EWIC_BASE ) /*!< EWIC configuration struct */ + #define PRCCFGINF ((PrcCfgInf_Type *) PRCCFGINF_BASE ) /*!< Processor Configuration Information configuration struct */ + #define STL ((STL_Type *) STL_BASE ) /*!< Software Test Library configuration struct */ + #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< \deprecated Core Debug configuration struct */ + #define DCB ((DCB_Type *) DCB_BASE ) /*!< DCB configuration struct */ + #define DIB ((DIB_Type *) DIB_BASE ) /*!< DIB configuration struct */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ + #endif + + #if defined (__PMU_PRESENT) && (__PMU_PRESENT == 1U) + #define PMU_BASE (0xE0003000UL) /*!< PMU Base Address */ + #define PMU ((PMU_Type *) PMU_BASE ) /*!< PMU configuration struct */ + #endif + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ + #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ + #endif + + #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ + #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ + #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< \deprecated Core Debug Base Address (non-secure address space) */ + #define DCB_BASE_NS (0xE002EDF0UL) /*!< DCB Base Address (non-secure address space) */ + #define DIB_BASE_NS (0xE002EFB0UL) /*!< DIB Base Address (non-secure address space) */ + #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ + #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ + #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + + #define ICB_NS ((ICB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */ + #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ + #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ + #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ + #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< \deprecated Core Debug configuration struct (non-secure address space) */ + #define DCB_NS ((DCB_Type *) DCB_BASE_NS ) /*!< DCB configuration struct (non-secure address space) */ + #define DIB_NS ((DIB_Type *) DIB_BASE_NS ) /*!< DIB configuration struct (non-secure address space) */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ + #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ + #endif + + #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */ + #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */ + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_register_aliases Backwards Compatibility Aliases + \brief Register alias definitions for backwards compatibility. + @{ + */ +#define ID_ADR (ID_AFR) /*!< SCB Auxiliary Feature Register */ + +/* 'SCnSCB' is deprecated and replaced by 'ICB' */ +typedef ICB_Type SCnSCB_Type; + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_DISCRITAXIRUW_Pos (ICB_ACTLR_DISCRITAXIRUW_Pos) +#define SCnSCB_ACTLR_DISCRITAXIRUW_Msk (ICB_ACTLR_DISCRITAXIRUW_Msk) + +#define SCnSCB_ACTLR_DISDI_Pos (ICB_ACTLR_DISDI_Pos) +#define SCnSCB_ACTLR_DISDI_Msk (ICB_ACTLR_DISDI_Msk) + +#define SCnSCB_ACTLR_DISCRITAXIRUR_Pos (ICB_ACTLR_DISCRITAXIRUR_Pos) +#define SCnSCB_ACTLR_DISCRITAXIRUR_Msk (ICB_ACTLR_DISCRITAXIRUR_Msk) + +#define SCnSCB_ACTLR_EVENTBUSEN_Pos (ICB_ACTLR_EVENTBUSEN_Pos) +#define SCnSCB_ACTLR_EVENTBUSEN_Msk (ICB_ACTLR_EVENTBUSEN_Msk) + +#define SCnSCB_ACTLR_EVENTBUSEN_S_Pos (ICB_ACTLR_EVENTBUSEN_S_Pos) +#define SCnSCB_ACTLR_EVENTBUSEN_S_Msk (ICB_ACTLR_EVENTBUSEN_S_Msk) + +#define SCnSCB_ACTLR_DISITMATBFLUSH_Pos (ICB_ACTLR_DISITMATBFLUSH_Pos) +#define SCnSCB_ACTLR_DISITMATBFLUSH_Msk (ICB_ACTLR_DISITMATBFLUSH_Msk) + +#define SCnSCB_ACTLR_DISNWAMODE_Pos (ICB_ACTLR_DISNWAMODE_Pos) +#define SCnSCB_ACTLR_DISNWAMODE_Msk (ICB_ACTLR_DISNWAMODE_Msk) + +#define SCnSCB_ACTLR_FPEXCODIS_Pos (ICB_ACTLR_FPEXCODIS_Pos) +#define SCnSCB_ACTLR_FPEXCODIS_Msk (ICB_ACTLR_FPEXCODIS_Msk) + +#define SCnSCB_ACTLR_DISOLAP_Pos (ICB_ACTLR_DISOLAP_Pos) +#define SCnSCB_ACTLR_DISOLAP_Msk (ICB_ACTLR_DISOLAP_Msk) + +#define SCnSCB_ACTLR_DISOLAPS_Pos (ICB_ACTLR_DISOLAPS_Pos) +#define SCnSCB_ACTLR_DISOLAPS_Msk (ICB_ACTLR_DISOLAPS_Msk) + +#define SCnSCB_ACTLR_DISLOBR_Pos (ICB_ACTLR_DISLOBR_Pos) +#define SCnSCB_ACTLR_DISLOBR_Msk (ICB_ACTLR_DISLOBR_Msk) + +#define SCnSCB_ACTLR_DISLO_Pos (ICB_ACTLR_DISLO_Pos) +#define SCnSCB_ACTLR_DISLO_Msk (ICB_ACTLR_DISLO_Msk) + +#define SCnSCB_ACTLR_DISLOLEP_Pos (ICB_ACTLR_DISLOLEP_Pos) +#define SCnSCB_ACTLR_DISLOLEP_Msk (ICB_ACTLR_DISLOLEP_Msk) + +#define SCnSCB_ACTLR_DISFOLD_Pos (ICB_ACTLR_DISFOLD_Pos) +#define SCnSCB_ACTLR_DISFOLD_Msk (ICB_ACTLR_DISFOLD_Msk) + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos (ICB_ICTR_INTLINESNUM_Pos) +#define SCnSCB_ICTR_INTLINESNUM_Msk (ICB_ICTR_INTLINESNUM_Msk) + +#define SCnSCB (ICB) +#define SCnSCB_NS (ICB_NS) + +/*@} */ + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* Special LR values for Secure/Non-Secure call handling and exception handling */ + +/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ +#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ + +/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ +#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ +#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ +#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ +#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ +#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ +#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */ +#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ + +/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ +#else +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ +#endif + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + __DSB(); +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Priority Grouping (non-secure) + \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB_NS->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB_NS->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping (non-secure) + \details Reads the priority grouping field from the non-secure NVIC when in secure state. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void) +{ + return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv8.h" + +#endif + +/* ########################## PMU functions and events #################################### */ + +#if defined (__PMU_PRESENT) && (__PMU_PRESENT == 1U) + +#include "pmu_armv8.h" + +/** + \brief Cortex-M55 PMU events + \note Architectural PMU events can be found in pmu_armv8.h +*/ + +#define ARMCM55_PMU_ECC_ERR 0xC000 /*!< Any ECC error */ +#define ARMCM55_PMU_ECC_ERR_FATAL 0xC001 /*!< Any fatal ECC error */ +#define ARMCM55_PMU_ECC_ERR_DCACHE 0xC010 /*!< Any ECC error in the data cache */ +#define ARMCM55_PMU_ECC_ERR_ICACHE 0xC011 /*!< Any ECC error in the instruction cache */ +#define ARMCM55_PMU_ECC_ERR_FATAL_DCACHE 0xC012 /*!< Any fatal ECC error in the data cache */ +#define ARMCM55_PMU_ECC_ERR_FATAL_ICACHE 0xC013 /*!< Any fatal ECC error in the instruction cache*/ +#define ARMCM55_PMU_ECC_ERR_DTCM 0xC020 /*!< Any ECC error in the DTCM */ +#define ARMCM55_PMU_ECC_ERR_ITCM 0xC021 /*!< Any ECC error in the ITCM */ +#define ARMCM55_PMU_ECC_ERR_FATAL_DTCM 0xC022 /*!< Any fatal ECC error in the DTCM */ +#define ARMCM55_PMU_ECC_ERR_FATAL_ITCM 0xC023 /*!< Any fatal ECC error in the ITCM */ +#define ARMCM55_PMU_PF_LINEFILL 0xC100 /*!< A prefetcher starts a line-fill */ +#define ARMCM55_PMU_PF_CANCEL 0xC101 /*!< A prefetcher stops prefetching */ +#define ARMCM55_PMU_PF_DROP_LINEFILL 0xC102 /*!< A linefill triggered by a prefetcher has been dropped because of lack of buffering */ +#define ARMCM55_PMU_NWAMODE_ENTER 0xC200 /*!< No write-allocate mode entry */ +#define ARMCM55_PMU_NWAMODE 0xC201 /*!< Write-allocate store is not allocated into the data cache due to no-write-allocate mode */ +#define ARMCM55_PMU_SAHB_ACCESS 0xC300 /*!< Read or write access on the S-AHB interface to the TCM */ +#define ARMCM55_PMU_PAHB_ACCESS 0xC301 /*!< Read or write access to the P-AHB write interface */ +#define ARMCM55_PMU_AXI_WRITE_ACCESS 0xC302 /*!< Any beat access to M-AXI write interface */ +#define ARMCM55_PMU_AXI_READ_ACCESS 0xC303 /*!< Any beat access to M-AXI read interface */ +#define ARMCM55_PMU_DOSTIMEOUT_DOUBLE 0xC400 /*!< Denial of Service timeout has fired twice and caused buffers to drain to allow forward progress */ +#define ARMCM55_PMU_DOSTIMEOUT_TRIPLE 0xC401 /*!< Denial of Service timeout has fired three times and blocked the LSU to force forward progress */ + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = FPU->MVFR0; + if ((mvfr0 & (FPU_MVFR0_FPSP_Msk | FPU_MVFR0_FPDP_Msk)) == 0x220U) + { + return 2U; /* Double + Single precision FPU */ + } + else if ((mvfr0 & (FPU_MVFR0_FPSP_Msk | FPU_MVFR0_FPDP_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + +/* ########################## MVE functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_MveFunctions MVE Functions + \brief Function that provides MVE type. + @{ + */ + +/** + \brief get MVE type + \details returns the MVE type + \returns + - \b 0: No Vector Extension (MVE) + - \b 1: Integer Vector Extension (MVE-I) + - \b 2: Floating-point Vector Extension (MVE-F) + */ +__STATIC_INLINE uint32_t SCB_GetMVEType(void) +{ + const uint32_t mvfr1 = FPU->MVFR1; + if ((mvfr1 & FPU_MVFR1_MVE_Msk) == (0x2U << FPU_MVFR1_MVE_Pos)) + { + return 2U; + } + else if ((mvfr1 & FPU_MVFR1_MVE_Msk) == (0x1U << FPU_MVFR1_MVE_Pos)) + { + return 1U; + } + else + { + return 0U; + } +} + + +/*@} end of CMSIS_Core_MveFunctions */ + + +/* ########################## Cache functions #################################### */ + +#if ((defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)) || \ + (defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U))) +#include "cachel1_armv7.h" +#endif + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + + +/* ################################## Debug Control function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DCBFunctions Debug Control Functions + \brief Functions that access the Debug Control Block. + @{ + */ + + +/** + \brief Set Debug Authentication Control Register + \details writes to Debug Authentication Control register. + \param [in] value value to be writen. + */ +__STATIC_INLINE void DCB_SetAuthCtrl(uint32_t value) +{ + __DSB(); + __ISB(); + DCB->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register + \details Reads Debug Authentication Control register. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t DCB_GetAuthCtrl(void) +{ + return (DCB->DAUTHCTRL); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Debug Authentication Control Register (non-secure) + \details writes to non-secure Debug Authentication Control register when in secure state. + \param [in] value value to be writen + */ +__STATIC_INLINE void TZ_DCB_SetAuthCtrl_NS(uint32_t value) +{ + __DSB(); + __ISB(); + DCB_NS->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register (non-secure) + \details Reads non-secure Debug Authentication Control register when in secure state. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t TZ_DCB_GetAuthCtrl_NS(void) +{ + return (DCB_NS->DAUTHCTRL); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## Debug Identification function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DIBFunctions Debug Identification Functions + \brief Functions that access the Debug Identification Block. + @{ + */ + + +/** + \brief Get Debug Authentication Status Register + \details Reads Debug Authentication Status register. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t DIB_GetAuthStatus(void) +{ + return (DIB->DAUTHSTATUS); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Debug Authentication Status Register (non-secure) + \details Reads non-secure Debug Authentication Status register when in secure state. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t TZ_DIB_GetAuthStatus_NS(void) +{ + return (DIB_NS->DAUTHSTATUS); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM55_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/CMSIS/Core/Include/core_cm7.h b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/CMSIS/Core/Include/core_cm7.h new file mode 100644 index 0000000000..010506e9fa --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/CMSIS/Core/Include/core_cm7.h @@ -0,0 +1,2366 @@ +/**************************************************************************//** + * @file core_cm7.h + * @brief CMSIS Cortex-M7 Core Peripheral Access Layer Header File + * @version V5.1.6 + * @date 04. June 2021 + ******************************************************************************/ +/* + * Copyright (c) 2009-2021 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM7_H_GENERIC +#define __CORE_CM7_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M7 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM7 definitions */ +#define __CM7_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM7_CMSIS_VERSION_SUB ( __CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM7_CMSIS_VERSION ((__CM7_CMSIS_VERSION_MAIN << 16U) | \ + __CM7_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (7U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM7_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM7_H_DEPENDANT +#define __CORE_CM7_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM7_REV + #define __CM7_REV 0x0000U + #warning "__CM7_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __ICACHE_PRESENT + #define __ICACHE_PRESENT 0U + #warning "__ICACHE_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DCACHE_PRESENT + #define __DCACHE_PRESENT 0U + #warning "__DCACHE_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DTCM_PRESENT + #define __DTCM_PRESENT 0U + #warning "__DTCM_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 1U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M7 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:1; /*!< bit: 9 Reserved */ + uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit */ + uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */ +#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */ +#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ + uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24U]; + __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RESERVED1[24U]; + __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24U]; + __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24U]; + __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56U]; + __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t ID_MFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ID_ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[1U]; + __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ + __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ + __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ + __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + uint32_t RESERVED3[93U]; + __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ + uint32_t RESERVED4[15U]; + __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ + uint32_t RESERVED5[1U]; + __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ + uint32_t RESERVED6[1U]; + __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ + __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ + __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ + __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ + __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ + __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ + __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ + __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ + __OM uint32_t BPIALL; /*!< Offset: 0x278 ( /W) Branch Predictor Invalidate All */ + uint32_t RESERVED7[5U]; + __IOM uint32_t ITCMCR; /*!< Offset: 0x290 (R/W) Instruction Tightly-Coupled Memory Control Register */ + __IOM uint32_t DTCMCR; /*!< Offset: 0x294 (R/W) Data Tightly-Coupled Memory Control Registers */ + __IOM uint32_t AHBPCR; /*!< Offset: 0x298 (R/W) AHBP Control Register */ + __IOM uint32_t CACR; /*!< Offset: 0x29C (R/W) L1 Cache Control Register */ + __IOM uint32_t AHBSCR; /*!< Offset: 0x2A0 (R/W) AHB Slave Control Register */ + uint32_t RESERVED8[1U]; + __IOM uint32_t ABFSR; /*!< Offset: 0x2A8 (R/W) Auxiliary Bus Fault Status Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: Branch prediction enable bit Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: Branch prediction enable bit Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: Instruction cache enable bit Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: Instruction cache enable bit Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: Cache enable bit Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: Cache enable bit Mask */ + +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_CFSR_MEMFAULTSR_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/* SCB Cache Level ID Register Definitions */ +#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ +#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ + +#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ +#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ + +/* SCB Cache Type Register Definitions */ +#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ +#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ + +#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ +#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ + +#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ +#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ + +#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ +#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ + +#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ +#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ + +/* SCB Cache Size ID Register Definitions */ +#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ +#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ + +#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ +#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ + +#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ +#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ + +#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ +#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ + +#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ +#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ + +#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ +#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ + +#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ +#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ + +/* SCB Cache Size Selection Register Definitions */ +#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ +#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ + +#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ +#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ + +/* SCB Software Triggered Interrupt Register Definitions */ +#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ +#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ + +/* SCB D-Cache Invalidate by Set-way Register Definitions */ +#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ +#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ + +#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ +#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ + +/* SCB D-Cache Clean by Set-way Register Definitions */ +#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ +#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ + +#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ +#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ + +/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ +#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ +#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ + +#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ +#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ + +/* Instruction Tightly-Coupled Memory Control Register Definitions */ +#define SCB_ITCMCR_SZ_Pos 3U /*!< SCB ITCMCR: SZ Position */ +#define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) /*!< SCB ITCMCR: SZ Mask */ + +#define SCB_ITCMCR_RETEN_Pos 2U /*!< SCB ITCMCR: RETEN Position */ +#define SCB_ITCMCR_RETEN_Msk (1UL << SCB_ITCMCR_RETEN_Pos) /*!< SCB ITCMCR: RETEN Mask */ + +#define SCB_ITCMCR_RMW_Pos 1U /*!< SCB ITCMCR: RMW Position */ +#define SCB_ITCMCR_RMW_Msk (1UL << SCB_ITCMCR_RMW_Pos) /*!< SCB ITCMCR: RMW Mask */ + +#define SCB_ITCMCR_EN_Pos 0U /*!< SCB ITCMCR: EN Position */ +#define SCB_ITCMCR_EN_Msk (1UL /*<< SCB_ITCMCR_EN_Pos*/) /*!< SCB ITCMCR: EN Mask */ + +/* Data Tightly-Coupled Memory Control Register Definitions */ +#define SCB_DTCMCR_SZ_Pos 3U /*!< SCB DTCMCR: SZ Position */ +#define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) /*!< SCB DTCMCR: SZ Mask */ + +#define SCB_DTCMCR_RETEN_Pos 2U /*!< SCB DTCMCR: RETEN Position */ +#define SCB_DTCMCR_RETEN_Msk (1UL << SCB_DTCMCR_RETEN_Pos) /*!< SCB DTCMCR: RETEN Mask */ + +#define SCB_DTCMCR_RMW_Pos 1U /*!< SCB DTCMCR: RMW Position */ +#define SCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos) /*!< SCB DTCMCR: RMW Mask */ + +#define SCB_DTCMCR_EN_Pos 0U /*!< SCB DTCMCR: EN Position */ +#define SCB_DTCMCR_EN_Msk (1UL /*<< SCB_DTCMCR_EN_Pos*/) /*!< SCB DTCMCR: EN Mask */ + +/* AHBP Control Register Definitions */ +#define SCB_AHBPCR_SZ_Pos 1U /*!< SCB AHBPCR: SZ Position */ +#define SCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos) /*!< SCB AHBPCR: SZ Mask */ + +#define SCB_AHBPCR_EN_Pos 0U /*!< SCB AHBPCR: EN Position */ +#define SCB_AHBPCR_EN_Msk (1UL /*<< SCB_AHBPCR_EN_Pos*/) /*!< SCB AHBPCR: EN Mask */ + +/* L1 Cache Control Register Definitions */ +#define SCB_CACR_FORCEWT_Pos 2U /*!< SCB CACR: FORCEWT Position */ +#define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: FORCEWT Mask */ + +#define SCB_CACR_ECCEN_Pos 1U /*!< \deprecated SCB CACR: ECCEN Position */ +#define SCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos) /*!< \deprecated SCB CACR: ECCEN Mask */ + +#define SCB_CACR_ECCDIS_Pos 1U /*!< SCB CACR: ECCDIS Position */ +#define SCB_CACR_ECCDIS_Msk (1UL << SCB_CACR_ECCDIS_Pos) /*!< SCB CACR: ECCDIS Mask */ + +#define SCB_CACR_SIWT_Pos 0U /*!< SCB CACR: SIWT Position */ +#define SCB_CACR_SIWT_Msk (1UL /*<< SCB_CACR_SIWT_Pos*/) /*!< SCB CACR: SIWT Mask */ + +/* AHBS Control Register Definitions */ +#define SCB_AHBSCR_INITCOUNT_Pos 11U /*!< SCB AHBSCR: INITCOUNT Position */ +#define SCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBSCR_INITCOUNT_Pos) /*!< SCB AHBSCR: INITCOUNT Mask */ + +#define SCB_AHBSCR_TPRI_Pos 2U /*!< SCB AHBSCR: TPRI Position */ +#define SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBSCR_TPRI_Pos) /*!< SCB AHBSCR: TPRI Mask */ + +#define SCB_AHBSCR_CTL_Pos 0U /*!< SCB AHBSCR: CTL Position*/ +#define SCB_AHBSCR_CTL_Msk (3UL /*<< SCB_AHBSCR_CTL_Pos*/) /*!< SCB AHBSCR: CTL Mask */ + +/* Auxiliary Bus Fault Status Register Definitions */ +#define SCB_ABFSR_AXIMTYPE_Pos 8U /*!< SCB ABFSR: AXIMTYPE Position*/ +#define SCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos) /*!< SCB ABFSR: AXIMTYPE Mask */ + +#define SCB_ABFSR_EPPB_Pos 4U /*!< SCB ABFSR: EPPB Position*/ +#define SCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos) /*!< SCB ABFSR: EPPB Mask */ + +#define SCB_ABFSR_AXIM_Pos 3U /*!< SCB ABFSR: AXIM Position*/ +#define SCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos) /*!< SCB ABFSR: AXIM Mask */ + +#define SCB_ABFSR_AHBP_Pos 2U /*!< SCB ABFSR: AHBP Position*/ +#define SCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos) /*!< SCB ABFSR: AHBP Mask */ + +#define SCB_ABFSR_DTCM_Pos 1U /*!< SCB ABFSR: DTCM Position*/ +#define SCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos) /*!< SCB ABFSR: DTCM Mask */ + +#define SCB_ABFSR_ITCM_Pos 0U /*!< SCB ABFSR: ITCM Position*/ +#define SCB_ABFSR_ITCM_Msk (1UL /*<< SCB_ABFSR_ITCM_Pos*/) /*!< SCB ABFSR: ITCM Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_DISDYNADD_Pos 26U /*!< ACTLR: DISDYNADD Position */ +#define SCnSCB_ACTLR_DISDYNADD_Msk (1UL << SCnSCB_ACTLR_DISDYNADD_Pos) /*!< ACTLR: DISDYNADD Mask */ + +#define SCnSCB_ACTLR_DISISSCH1_Pos 21U /*!< ACTLR: DISISSCH1 Position */ +#define SCnSCB_ACTLR_DISISSCH1_Msk (0x1FUL << SCnSCB_ACTLR_DISISSCH1_Pos) /*!< ACTLR: DISISSCH1 Mask */ + +#define SCnSCB_ACTLR_DISDI_Pos 16U /*!< ACTLR: DISDI Position */ +#define SCnSCB_ACTLR_DISDI_Msk (0x1FUL << SCnSCB_ACTLR_DISDI_Pos) /*!< ACTLR: DISDI Mask */ + +#define SCnSCB_ACTLR_DISCRITAXIRUR_Pos 15U /*!< ACTLR: DISCRITAXIRUR Position */ +#define SCnSCB_ACTLR_DISCRITAXIRUR_Msk (1UL << SCnSCB_ACTLR_DISCRITAXIRUR_Pos) /*!< ACTLR: DISCRITAXIRUR Mask */ + +#define SCnSCB_ACTLR_DISBTACALLOC_Pos 14U /*!< ACTLR: DISBTACALLOC Position */ +#define SCnSCB_ACTLR_DISBTACALLOC_Msk (1UL << SCnSCB_ACTLR_DISBTACALLOC_Pos) /*!< ACTLR: DISBTACALLOC Mask */ + +#define SCnSCB_ACTLR_DISBTACREAD_Pos 13U /*!< ACTLR: DISBTACREAD Position */ +#define SCnSCB_ACTLR_DISBTACREAD_Msk (1UL << SCnSCB_ACTLR_DISBTACREAD_Pos) /*!< ACTLR: DISBTACREAD Mask */ + +#define SCnSCB_ACTLR_DISITMATBFLUSH_Pos 12U /*!< ACTLR: DISITMATBFLUSH Position */ +#define SCnSCB_ACTLR_DISITMATBFLUSH_Msk (1UL << SCnSCB_ACTLR_DISITMATBFLUSH_Pos) /*!< ACTLR: DISITMATBFLUSH Mask */ + +#define SCnSCB_ACTLR_DISRAMODE_Pos 11U /*!< ACTLR: DISRAMODE Position */ +#define SCnSCB_ACTLR_DISRAMODE_Msk (1UL << SCnSCB_ACTLR_DISRAMODE_Pos) /*!< ACTLR: DISRAMODE Mask */ + +#define SCnSCB_ACTLR_FPEXCODIS_Pos 10U /*!< ACTLR: FPEXCODIS Position */ +#define SCnSCB_ACTLR_FPEXCODIS_Msk (1UL << SCnSCB_ACTLR_FPEXCODIS_Pos) /*!< ACTLR: FPEXCODIS Mask */ + +#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ +#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED3[981U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( W) Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x1UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x1UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY2_Pos 0U /*!< TPI ITATBCTR2: ATREADY2 Position */ +#define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/) /*!< TPI ITATBCTR2: ATREADY2 Mask */ + +#define TPI_ITATBCTR2_ATREADY1_Pos 0U /*!< TPI ITATBCTR2: ATREADY1 Position */ +#define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/) /*!< TPI ITATBCTR2: ATREADY1 Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x1UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x1UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY2_Pos 0U /*!< TPI ITATBCTR0: ATREADY2 Position */ +#define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/) /*!< TPI ITATBCTR0: ATREADY2 Mask */ + +#define TPI_ITATBCTR0_ATREADY1_Pos 0U /*!< TPI ITATBCTR0: ATREADY1 Position */ +#define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/) /*!< TPI ITATBCTR0: ATREADY1 Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif /* defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and FP Feature Register 2 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and FP Feature Register 0 Definitions */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and FP Feature Register 1 Definitions */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/* Media and FP Feature Register 2 Definitions */ + +#define FPU_MVFR2_VFP_Misc_Pos 4U /*!< MVFR2: VFP Misc bits Position */ +#define FPU_MVFR2_VFP_Misc_Msk (0xFUL << FPU_MVFR2_VFP_Misc_Pos) /*!< MVFR2: VFP Misc bits Mask */ + +/*@} end of group CMSIS_FPU */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +#define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ +#define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ +#define EXC_RETURN_HANDLER_FPU (0xFFFFFFE1UL) /* return to Handler mode, uses MSP after return, restore floating-point state */ +#define EXC_RETURN_THREAD_MSP_FPU (0xFFFFFFE9UL) /* return to Thread mode, uses MSP after return, restore floating-point state */ +#define EXC_RETURN_THREAD_PSP_FPU (0xFFFFFFEDUL) /* return to Thread mode, uses PSP after return, restore floating-point state */ + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + __DSB(); +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv7.h" + +#endif + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = SCB->MVFR0; + if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U) + { + return 2U; /* Double + Single precision FPU */ + } + else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + +/*@} end of CMSIS_Core_FpuFunctions */ + + +/* ########################## Cache functions #################################### */ + +#if ((defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)) || \ + (defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U))) +#include "cachel1_armv7.h" +#endif + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM7_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/CMSIS/Core/Include/core_cm85.h b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/CMSIS/Core/Include/core_cm85.h new file mode 100644 index 0000000000..6046311189 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/CMSIS/Core/Include/core_cm85.h @@ -0,0 +1,4672 @@ +/**************************************************************************//** + * @file core_cm85.h + * @brief CMSIS Cortex-M85 Core Peripheral Access Layer Header File + * @version V1.0.4 + * @date 21. April 2022 + ******************************************************************************/ +/* + * Copyright (c) 2022 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#elif defined ( __GNUC__ ) + #pragma GCC diagnostic ignored "-Wpedantic" /* disable pedantic warning due to unnamed structs/unions */ +#endif + +#ifndef __CORE_CM85_H_GENERIC +#define __CORE_CM85_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M85 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM85 definitions */ + +#define __CORTEX_M (85U) /*!< Cortex-M Core */ + +#if defined ( __CC_ARM ) + #error Legacy Arm Compiler does not support Armv8.1-M target architecture. +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM85_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM85_H_DEPENDANT +#define __CORE_CM85_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM85_REV + #define __CM85_REV 0x0001U + #warning "__CM85_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #if __FPU_PRESENT != 0U + #ifndef __FPU_DP + #define __FPU_DP 0U + #warning "__FPU_DP not defined in device header file; using default!" + #endif + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __ICACHE_PRESENT + #define __ICACHE_PRESENT 0U + #warning "__ICACHE_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DCACHE_PRESENT + #define __DCACHE_PRESENT 0U + #warning "__DCACHE_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 1U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __PMU_PRESENT + #define __PMU_PRESENT 0U + #warning "__PMU_PRESENT not defined in device header file; using default!" + #endif + + #if __PMU_PRESENT != 0U + #ifndef __PMU_NUM_EVENTCNT + #define __PMU_NUM_EVENTCNT 8U + #warning "__PMU_NUM_EVENTCNT not defined in device header file; using default!" + #elif (__PMU_NUM_EVENTCNT > 8 || __PMU_NUM_EVENTCNT < 2) + #error "__PMU_NUM_EVENTCNT is out of range in device header file!" */ + #endif + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DSP_PRESENT + #define __DSP_PRESENT 0U + #warning "__DSP_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M85 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core EWIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core PMU Register + - Core MPU Register + - Core SAU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:1; /*!< bit: 20 Reserved */ + uint32_t B:1; /*!< bit: 21 BTI active (read 0) */ + uint32_t _reserved2:2; /*!< bit: 22..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ +#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_B_Pos 21U /*!< xPSR: B Position */ +#define xPSR_B_Msk (1UL << xPSR_B_Pos) /*!< xPSR: B Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */ + uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */ + uint32_t BTI_EN:1; /*!< bit: 4 Privileged branch target identification enable */ + uint32_t UBTI_EN:1; /*!< bit: 5 Unprivileged branch target identification enable */ + uint32_t PAC_EN:1; /*!< bit: 6 Privileged pointer authentication enable */ + uint32_t UPAC_EN:1; /*!< bit: 7 Unprivileged pointer authentication enable */ + uint32_t _reserved1:24; /*!< bit: 8..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_UPAC_EN_Pos 7U /*!< CONTROL: UPAC_EN Position */ +#define CONTROL_UPAC_EN_Msk (1UL << CONTROL_UPAC_EN_Pos) /*!< CONTROL: UPAC_EN Mask */ + +#define CONTROL_PAC_EN_Pos 6U /*!< CONTROL: PAC_EN Position */ +#define CONTROL_PAC_EN_Msk (1UL << CONTROL_PAC_EN_Pos) /*!< CONTROL: PAC_EN Mask */ + +#define CONTROL_UBTI_EN_Pos 5U /*!< CONTROL: UBTI_EN Position */ +#define CONTROL_UBTI_EN_Msk (1UL << CONTROL_UBTI_EN_Pos) /*!< CONTROL: UBTI_EN Mask */ + +#define CONTROL_BTI_EN_Pos 4U /*!< CONTROL: BTI_EN Position */ +#define CONTROL_BTI_EN_Msk (1UL << CONTROL_BTI_EN_Pos) /*!< CONTROL: BTI_EN Mask */ + +#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */ +#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */ + +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED6[580U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ + __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ + __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ + __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */ + uint32_t RESERVED7[21U]; + __IOM uint32_t SFSR; /*!< Offset: 0x0E4 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x0E8 (R/W) Secure Fault Address Register */ + uint32_t RESERVED3[69U]; + __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ + __IOM uint32_t RFSR; /*!< Offset: 0x204 (R/W) RAS Fault Status Register */ + uint32_t RESERVED4[14U]; + __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ + uint32_t RESERVED5[1U]; + __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ + uint32_t RESERVED6[1U]; + __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ + __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ + __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ + __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ + __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ + __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ + __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ + __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ + __OM uint32_t BPIALL; /*!< Offset: 0x278 ( /W) Branch Predictor Invalidate All */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ +#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_IESB_Pos 5U /*!< SCB AIRCR: Implicit ESB Enable Position */ +#define SCB_AIRCR_IESB_Msk (1UL << SCB_AIRCR_IESB_Pos) /*!< SCB AIRCR: Implicit ESB Enable Mask */ + +#define SCB_AIRCR_DIT_Pos 4U /*!< SCB AIRCR: Data Independent Timing Position */ +#define SCB_AIRCR_DIT_Msk (1UL << SCB_AIRCR_DIT_Pos) /*!< SCB AIRCR: Data Independent Timing Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_TRD_Pos 20U /*!< SCB CCR: TRD Position */ +#define SCB_CCR_TRD_Msk (1UL << SCB_CCR_TRD_Pos) /*!< SCB CCR: TRD Mask */ + +#define SCB_CCR_LOB_Pos 19U /*!< SCB CCR: LOB Position */ +#define SCB_CCR_LOB_Msk (1UL << SCB_CCR_LOB_Pos) /*!< SCB CCR: LOB Mask */ + +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */ +#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */ +#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */ + +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */ +#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_CFSR_MEMFAULTSR_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */ +#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_PMU_Pos 5U /*!< SCB DFSR: PMU Position */ +#define SCB_DFSR_PMU_Msk (1UL << SCB_DFSR_PMU_Pos) /*!< SCB DFSR: PMU Mask */ + +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/* SCB Non-Secure Access Control Register Definitions */ +#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */ +#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */ + +#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */ +#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */ + +#define SCB_NSACR_CP7_Pos 7U /*!< SCB NSACR: CP7 Position */ +#define SCB_NSACR_CP7_Msk (1UL << SCB_NSACR_CP7_Pos) /*!< SCB NSACR: CP7 Mask */ + +#define SCB_NSACR_CP6_Pos 6U /*!< SCB NSACR: CP6 Position */ +#define SCB_NSACR_CP6_Msk (1UL << SCB_NSACR_CP6_Pos) /*!< SCB NSACR: CP6 Mask */ + +#define SCB_NSACR_CP5_Pos 5U /*!< SCB NSACR: CP5 Position */ +#define SCB_NSACR_CP5_Msk (1UL << SCB_NSACR_CP5_Pos) /*!< SCB NSACR: CP5 Mask */ + +#define SCB_NSACR_CP4_Pos 4U /*!< SCB NSACR: CP4 Position */ +#define SCB_NSACR_CP4_Msk (1UL << SCB_NSACR_CP4_Pos) /*!< SCB NSACR: CP4 Mask */ + +#define SCB_NSACR_CP3_Pos 3U /*!< SCB NSACR: CP3 Position */ +#define SCB_NSACR_CP3_Msk (1UL << SCB_NSACR_CP3_Pos) /*!< SCB NSACR: CP3 Mask */ + +#define SCB_NSACR_CP2_Pos 2U /*!< SCB NSACR: CP2 Position */ +#define SCB_NSACR_CP2_Msk (1UL << SCB_NSACR_CP2_Pos) /*!< SCB NSACR: CP2 Mask */ + +#define SCB_NSACR_CP1_Pos 1U /*!< SCB NSACR: CP1 Position */ +#define SCB_NSACR_CP1_Msk (1UL << SCB_NSACR_CP1_Pos) /*!< SCB NSACR: CP1 Mask */ + +#define SCB_NSACR_CP0_Pos 0U /*!< SCB NSACR: CP0 Position */ +#define SCB_NSACR_CP0_Msk (1UL /*<< SCB_NSACR_CP0_Pos*/) /*!< SCB NSACR: CP0 Mask */ + +/* SCB Debug Feature Register 0 Definitions */ +#define SCB_ID_DFR_UDE_Pos 28U /*!< SCB ID_DFR: UDE Position */ +#define SCB_ID_DFR_UDE_Msk (0xFUL << SCB_ID_DFR_UDE_Pos) /*!< SCB ID_DFR: UDE Mask */ + +#define SCB_ID_DFR_MProfDbg_Pos 20U /*!< SCB ID_DFR: MProfDbg Position */ +#define SCB_ID_DFR_MProfDbg_Msk (0xFUL << SCB_ID_DFR_MProfDbg_Pos) /*!< SCB ID_DFR: MProfDbg Mask */ + +/* SCB Cache Level ID Register Definitions */ +#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ +#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ + +#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ +#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ + +/* SCB Cache Type Register Definitions */ +#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ +#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ + +#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ +#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ + +#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ +#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ + +#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ +#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ + +#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ +#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ + +/* SCB Cache Size ID Register Definitions */ +#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ +#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ + +#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ +#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ + +#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ +#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ + +#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ +#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ + +#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ +#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ + +#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ +#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ + +#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ +#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ + +/* SCB Cache Size Selection Register Definitions */ +#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ +#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ + +#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ +#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ + +/* SCB Software Triggered Interrupt Register Definitions */ +#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ +#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ + +/* SCB RAS Fault Status Register Definitions */ +#define SCB_RFSR_V_Pos 31U /*!< SCB RFSR: V Position */ +#define SCB_RFSR_V_Msk (1UL << SCB_RFSR_V_Pos) /*!< SCB RFSR: V Mask */ + +#define SCB_RFSR_IS_Pos 16U /*!< SCB RFSR: IS Position */ +#define SCB_RFSR_IS_Msk (0x7FFFUL << SCB_RFSR_IS_Pos) /*!< SCB RFSR: IS Mask */ + +#define SCB_RFSR_UET_Pos 0U /*!< SCB RFSR: UET Position */ +#define SCB_RFSR_UET_Msk (3UL /*<< SCB_RFSR_UET_Pos*/) /*!< SCB RFSR: UET Mask */ + +/* SCB D-Cache Invalidate by Set-way Register Definitions */ +#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ +#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ + +#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ +#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ + +/* SCB D-Cache Clean by Set-way Register Definitions */ +#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ +#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ + +#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ +#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ + +/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ +#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ +#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ + +#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ +#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ICB Implementation Control Block register (ICB) + \brief Type definitions for the Implementation Control Block Register + @{ + */ + +/** + \brief Structure type to access the Implementation Control Block (ICB). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ + __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */ +} ICB_Type; + +/* Auxiliary Control Register Definitions */ +#define ICB_ACTLR_DISCRITAXIRUW_Pos 27U /*!< ACTLR: DISCRITAXIRUW Position */ +#define ICB_ACTLR_DISCRITAXIRUW_Msk (1UL << ICB_ACTLR_DISCRITAXIRUW_Pos) /*!< ACTLR: DISCRITAXIRUW Mask */ + +#define ICB_ACTLR_DISCRITAXIRUR_Pos 15U /*!< ACTLR: DISCRITAXIRUR Position */ +#define ICB_ACTLR_DISCRITAXIRUR_Msk (1UL << ICB_ACTLR_DISCRITAXIRUR_Pos) /*!< ACTLR: DISCRITAXIRUR Mask */ + +#define ICB_ACTLR_EVENTBUSEN_Pos 14U /*!< ACTLR: EVENTBUSEN Position */ +#define ICB_ACTLR_EVENTBUSEN_Msk (1UL << ICB_ACTLR_EVENTBUSEN_Pos) /*!< ACTLR: EVENTBUSEN Mask */ + +#define ICB_ACTLR_EVENTBUSEN_S_Pos 13U /*!< ACTLR: EVENTBUSEN_S Position */ +#define ICB_ACTLR_EVENTBUSEN_S_Msk (1UL << ICB_ACTLR_EVENTBUSEN_S_Pos) /*!< ACTLR: EVENTBUSEN_S Mask */ + +#define ICB_ACTLR_DISITMATBFLUSH_Pos 12U /*!< ACTLR: DISITMATBFLUSH Position */ +#define ICB_ACTLR_DISITMATBFLUSH_Msk (1UL << ICB_ACTLR_DISITMATBFLUSH_Pos) /*!< ACTLR: DISITMATBFLUSH Mask */ + +#define ICB_ACTLR_DISNWAMODE_Pos 11U /*!< ACTLR: DISNWAMODE Position */ +#define ICB_ACTLR_DISNWAMODE_Msk (1UL << ICB_ACTLR_DISNWAMODE_Pos) /*!< ACTLR: DISNWAMODE Mask */ + +#define ICB_ACTLR_FPEXCODIS_Pos 10U /*!< ACTLR: FPEXCODIS Position */ +#define ICB_ACTLR_FPEXCODIS_Msk (1UL << ICB_ACTLR_FPEXCODIS_Pos) /*!< ACTLR: FPEXCODIS Mask */ + +/* Interrupt Controller Type Register Definitions */ +#define ICB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define ICB_ICTR_INTLINESNUM_Msk (0xFUL /*<< ICB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_ICB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */ + uint32_t RESERVED6[3U]; + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) ITM Device Type Register */ + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Stimulus Port Register Definitions */ +#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */ +#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */ + +#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */ +#define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */ + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */ +#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */ + +#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */ +#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED14[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED15[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED16[1U]; + __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ + uint32_t RESERVED17[1U]; + __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ + uint32_t RESERVED18[1U]; + __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ + uint32_t RESERVED19[1U]; + __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ + uint32_t RESERVED20[1U]; + __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ + uint32_t RESERVED21[1U]; + __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ + uint32_t RESERVED22[1U]; + __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ + uint32_t RESERVED23[1U]; + __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ + uint32_t RESERVED24[1U]; + __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ + uint32_t RESERVED25[1U]; + __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ + uint32_t RESERVED26[1U]; + __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ + uint32_t RESERVED27[1U]; + __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ + uint32_t RESERVED28[1U]; + __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ + uint32_t RESERVED29[1U]; + __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ + uint32_t RESERVED30[1U]; + __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ + uint32_t RESERVED31[1U]; + __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ + uint32_t RESERVED32[934U]; + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ + uint32_t RESERVED33[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */ +#define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup MemSysCtl_Type Memory System Control Registers (IMPLEMENTATION DEFINED) + \brief Type definitions for the Memory System Control Registers (MEMSYSCTL) + @{ + */ + +/** + \brief Structure type to access the Memory System Control Registers (MEMSYSCTL). + */ +typedef struct +{ + __IOM uint32_t MSCR; /*!< Offset: 0x000 (R/W) Memory System Control Register */ + __IOM uint32_t PFCR; /*!< Offset: 0x004 (R/W) Prefetcher Control Register */ + uint32_t RESERVED1[2U]; + __IOM uint32_t ITCMCR; /*!< Offset: 0x010 (R/W) ITCM Control Register */ + __IOM uint32_t DTCMCR; /*!< Offset: 0x014 (R/W) DTCM Control Register */ + __IOM uint32_t PAHBCR; /*!< Offset: 0x018 (R/W) P-AHB Control Register */ + uint32_t RESERVED2[313U]; + __IOM uint32_t ITGU_CTRL; /*!< Offset: 0x500 (R/W) ITGU Control Register */ + __IOM uint32_t ITGU_CFG; /*!< Offset: 0x504 (R/W) ITGU Configuration Register */ + uint32_t RESERVED3[2U]; + __IOM uint32_t ITGU_LUT[16U]; /*!< Offset: 0x510 (R/W) ITGU Look Up Table Register */ + uint32_t RESERVED4[44U]; + __IOM uint32_t DTGU_CTRL; /*!< Offset: 0x600 (R/W) DTGU Control Registers */ + __IOM uint32_t DTGU_CFG; /*!< Offset: 0x604 (R/W) DTGU Configuration Register */ + uint32_t RESERVED5[2U]; + __IOM uint32_t DTGU_LUT[16U]; /*!< Offset: 0x610 (R/W) DTGU Look Up Table Register */ +} MemSysCtl_Type; + +/* MEMSYSCTL Memory System Control Register (MSCR) Register Definitions */ +#define MEMSYSCTL_MSCR_CPWRDN_Pos 17U /*!< MEMSYSCTL MSCR: CPWRDN Position */ +#define MEMSYSCTL_MSCR_CPWRDN_Msk (0x1UL << MEMSYSCTL_MSCR_CPWRDN_Pos) /*!< MEMSYSCTL MSCR: CPWRDN Mask */ + +#define MEMSYSCTL_MSCR_DCCLEAN_Pos 16U /*!< MEMSYSCTL MSCR: DCCLEAN Position */ +#define MEMSYSCTL_MSCR_DCCLEAN_Msk (0x1UL << MEMSYSCTL_MSCR_DCCLEAN_Pos) /*!< MEMSYSCTL MSCR: DCCLEAN Mask */ + +#define MEMSYSCTL_MSCR_ICACTIVE_Pos 13U /*!< MEMSYSCTL MSCR: ICACTIVE Position */ +#define MEMSYSCTL_MSCR_ICACTIVE_Msk (0x1UL << MEMSYSCTL_MSCR_ICACTIVE_Pos) /*!< MEMSYSCTL MSCR: ICACTIVE Mask */ + +#define MEMSYSCTL_MSCR_DCACTIVE_Pos 12U /*!< MEMSYSCTL MSCR: DCACTIVE Position */ +#define MEMSYSCTL_MSCR_DCACTIVE_Msk (0x1UL << MEMSYSCTL_MSCR_DCACTIVE_Pos) /*!< MEMSYSCTL MSCR: DCACTIVE Mask */ + +#define MEMSYSCTL_MSCR_EVECCFAULT_Pos 3U /*!< MEMSYSCTL MSCR: EVECCFAULT Position */ +#define MEMSYSCTL_MSCR_EVECCFAULT_Msk (0x1UL << MEMSYSCTL_MSCR_EVECCFAULT_Pos) /*!< MEMSYSCTL MSCR: EVECCFAULT Mask */ + +#define MEMSYSCTL_MSCR_FORCEWT_Pos 2U /*!< MEMSYSCTL MSCR: FORCEWT Position */ +#define MEMSYSCTL_MSCR_FORCEWT_Msk (0x1UL << MEMSYSCTL_MSCR_FORCEWT_Pos) /*!< MEMSYSCTL MSCR: FORCEWT Mask */ + +#define MEMSYSCTL_MSCR_ECCEN_Pos 1U /*!< MEMSYSCTL MSCR: ECCEN Position */ +#define MEMSYSCTL_MSCR_ECCEN_Msk (0x1UL << MEMSYSCTL_MSCR_ECCEN_Pos) /*!< MEMSYSCTL MSCR: ECCEN Mask */ + +/* MEMSYSCTL Prefetcher Control Register (PFCR) Register Definitions */ +#define MEMSYSCTL_PFCR_DIS_NLP_Pos 7U /*!< MEMSYSCTL PFCR: DIS_NLP Position */ +#define MEMSYSCTL_PFCR_DIS_NLP_Msk (0x1UL << MEMSYSCTL_PFCR_DIS_NLP_Pos) /*!< MEMSYSCTL PFCR: DIS_NLP Mask */ + +#define MEMSYSCTL_PFCR_ENABLE_Pos 0U /*!< MEMSYSCTL PFCR: ENABLE Position */ +#define MEMSYSCTL_PFCR_ENABLE_Msk (0x1UL /*<< MEMSYSCTL_PFCR_ENABLE_Pos*/) /*!< MEMSYSCTL PFCR: ENABLE Mask */ + +/* MEMSYSCTL ITCM Control Register (ITCMCR) Register Definitions */ +#define MEMSYSCTL_ITCMCR_SZ_Pos 3U /*!< MEMSYSCTL ITCMCR: SZ Position */ +#define MEMSYSCTL_ITCMCR_SZ_Msk (0xFUL << MEMSYSCTL_ITCMCR_SZ_Pos) /*!< MEMSYSCTL ITCMCR: SZ Mask */ + +#define MEMSYSCTL_ITCMCR_EN_Pos 0U /*!< MEMSYSCTL ITCMCR: EN Position */ +#define MEMSYSCTL_ITCMCR_EN_Msk (0x1UL /*<< MEMSYSCTL_ITCMCR_EN_Pos*/) /*!< MEMSYSCTL ITCMCR: EN Mask */ + +/* MEMSYSCTL DTCM Control Register (DTCMCR) Register Definitions */ +#define MEMSYSCTL_DTCMCR_SZ_Pos 3U /*!< MEMSYSCTL DTCMCR: SZ Position */ +#define MEMSYSCTL_DTCMCR_SZ_Msk (0xFUL << MEMSYSCTL_DTCMCR_SZ_Pos) /*!< MEMSYSCTL DTCMCR: SZ Mask */ + +#define MEMSYSCTL_DTCMCR_EN_Pos 0U /*!< MEMSYSCTL DTCMCR: EN Position */ +#define MEMSYSCTL_DTCMCR_EN_Msk (0x1UL /*<< MEMSYSCTL_DTCMCR_EN_Pos*/) /*!< MEMSYSCTL DTCMCR: EN Mask */ + +/* MEMSYSCTL P-AHB Control Register (PAHBCR) Register Definitions */ +#define MEMSYSCTL_PAHBCR_SZ_Pos 1U /*!< MEMSYSCTL PAHBCR: SZ Position */ +#define MEMSYSCTL_PAHBCR_SZ_Msk (0x7UL << MEMSYSCTL_PAHBCR_SZ_Pos) /*!< MEMSYSCTL PAHBCR: SZ Mask */ + +#define MEMSYSCTL_PAHBCR_EN_Pos 0U /*!< MEMSYSCTL PAHBCR: EN Position */ +#define MEMSYSCTL_PAHBCR_EN_Msk (0x1UL /*<< MEMSYSCTL_PAHBCR_EN_Pos*/) /*!< MEMSYSCTL PAHBCR: EN Mask */ + +/* MEMSYSCTL ITGU Control Register (ITGU_CTRL) Register Definitions */ +#define MEMSYSCTL_ITGU_CTRL_DEREN_Pos 1U /*!< MEMSYSCTL ITGU_CTRL: DEREN Position */ +#define MEMSYSCTL_ITGU_CTRL_DEREN_Msk (0x1UL << MEMSYSCTL_ITGU_CTRL_DEREN_Pos) /*!< MEMSYSCTL ITGU_CTRL: DEREN Mask */ + +#define MEMSYSCTL_ITGU_CTRL_DBFEN_Pos 0U /*!< MEMSYSCTL ITGU_CTRL: DBFEN Position */ +#define MEMSYSCTL_ITGU_CTRL_DBFEN_Msk (0x1UL /*<< MEMSYSCTL_ITGU_CTRL_DBFEN_Pos*/) /*!< MEMSYSCTL ITGU_CTRL: DBFEN Mask */ + +/* MEMSYSCTL ITGU Configuration Register (ITGU_CFG) Register Definitions */ +#define MEMSYSCTL_ITGU_CFG_PRESENT_Pos 31U /*!< MEMSYSCTL ITGU_CFG: PRESENT Position */ +#define MEMSYSCTL_ITGU_CFG_PRESENT_Msk (0x1UL << MEMSYSCTL_ITGU_CFG_PRESENT_Pos) /*!< MEMSYSCTL ITGU_CFG: PRESENT Mask */ + +#define MEMSYSCTL_ITGU_CFG_NUMBLKS_Pos 8U /*!< MEMSYSCTL ITGU_CFG: NUMBLKS Position */ +#define MEMSYSCTL_ITGU_CFG_NUMBLKS_Msk (0xFUL << MEMSYSCTL_ITGU_CFG_NUMBLKS_Pos) /*!< MEMSYSCTL ITGU_CFG: NUMBLKS Mask */ + +#define MEMSYSCTL_ITGU_CFG_BLKSZ_Pos 0U /*!< MEMSYSCTL ITGU_CFG: BLKSZ Position */ +#define MEMSYSCTL_ITGU_CFG_BLKSZ_Msk (0xFUL /*<< MEMSYSCTL_ITGU_CFG_BLKSZ_Pos*/) /*!< MEMSYSCTL ITGU_CFG: BLKSZ Mask */ + +/* MEMSYSCTL DTGU Control Registers (DTGU_CTRL) Register Definitions */ +#define MEMSYSCTL_DTGU_CTRL_DEREN_Pos 1U /*!< MEMSYSCTL DTGU_CTRL: DEREN Position */ +#define MEMSYSCTL_DTGU_CTRL_DEREN_Msk (0x1UL << MEMSYSCTL_DTGU_CTRL_DEREN_Pos) /*!< MEMSYSCTL DTGU_CTRL: DEREN Mask */ + +#define MEMSYSCTL_DTGU_CTRL_DBFEN_Pos 0U /*!< MEMSYSCTL DTGU_CTRL: DBFEN Position */ +#define MEMSYSCTL_DTGU_CTRL_DBFEN_Msk (0x1UL /*<< MEMSYSCTL_DTGU_CTRL_DBFEN_Pos*/) /*!< MEMSYSCTL DTGU_CTRL: DBFEN Mask */ + +/* MEMSYSCTL DTGU Configuration Register (DTGU_CFG) Register Definitions */ +#define MEMSYSCTL_DTGU_CFG_PRESENT_Pos 31U /*!< MEMSYSCTL DTGU_CFG: PRESENT Position */ +#define MEMSYSCTL_DTGU_CFG_PRESENT_Msk (0x1UL << MEMSYSCTL_DTGU_CFG_PRESENT_Pos) /*!< MEMSYSCTL DTGU_CFG: PRESENT Mask */ + +#define MEMSYSCTL_DTGU_CFG_NUMBLKS_Pos 8U /*!< MEMSYSCTL DTGU_CFG: NUMBLKS Position */ +#define MEMSYSCTL_DTGU_CFG_NUMBLKS_Msk (0xFUL << MEMSYSCTL_DTGU_CFG_NUMBLKS_Pos) /*!< MEMSYSCTL DTGU_CFG: NUMBLKS Mask */ + +#define MEMSYSCTL_DTGU_CFG_BLKSZ_Pos 0U /*!< MEMSYSCTL DTGU_CFG: BLKSZ Position */ +#define MEMSYSCTL_DTGU_CFG_BLKSZ_Msk (0xFUL /*<< MEMSYSCTL_DTGU_CFG_BLKSZ_Pos*/) /*!< MEMSYSCTL DTGU_CFG: BLKSZ Mask */ + + +/*@}*/ /* end of group MemSysCtl_Type */ + + +/** + \ingroup CMSIS_core_register + \defgroup PwrModCtl_Type Power Mode Control Registers + \brief Type definitions for the Power Mode Control Registers (PWRMODCTL) + @{ + */ + +/** + \brief Structure type to access the Power Mode Control Registers (PWRMODCTL). + */ +typedef struct +{ + __IOM uint32_t CPDLPSTATE; /*!< Offset: 0x000 (R/W) Core Power Domain Low Power State Register */ + __IOM uint32_t DPDLPSTATE; /*!< Offset: 0x004 (R/W) Debug Power Domain Low Power State Register */ +} PwrModCtl_Type; + +/* PWRMODCTL Core Power Domain Low Power State (CPDLPSTATE) Register Definitions */ +#define PWRMODCTL_CPDLPSTATE_RLPSTATE_Pos 8U /*!< PWRMODCTL CPDLPSTATE: RLPSTATE Position */ +#define PWRMODCTL_CPDLPSTATE_RLPSTATE_Msk (0x3UL << PWRMODCTL_CPDLPSTATE_RLPSTATE_Pos) /*!< PWRMODCTL CPDLPSTATE: RLPSTATE Mask */ + +#define PWRMODCTL_CPDLPSTATE_ELPSTATE_Pos 4U /*!< PWRMODCTL CPDLPSTATE: ELPSTATE Position */ +#define PWRMODCTL_CPDLPSTATE_ELPSTATE_Msk (0x3UL << PWRMODCTL_CPDLPSTATE_ELPSTATE_Pos) /*!< PWRMODCTL CPDLPSTATE: ELPSTATE Mask */ + +#define PWRMODCTL_CPDLPSTATE_CLPSTATE_Pos 0U /*!< PWRMODCTL CPDLPSTATE: CLPSTATE Position */ +#define PWRMODCTL_CPDLPSTATE_CLPSTATE_Msk (0x3UL /*<< PWRMODCTL_CPDLPSTATE_CLPSTATE_Pos*/) /*!< PWRMODCTL CPDLPSTATE: CLPSTATE Mask */ + +/* PWRMODCTL Debug Power Domain Low Power State (DPDLPSTATE) Register Definitions */ +#define PWRMODCTL_DPDLPSTATE_DLPSTATE_Pos 0U /*!< PWRMODCTL DPDLPSTATE: DLPSTATE Position */ +#define PWRMODCTL_DPDLPSTATE_DLPSTATE_Msk (0x3UL /*<< PWRMODCTL_DPDLPSTATE_DLPSTATE_Pos*/) /*!< PWRMODCTL DPDLPSTATE: DLPSTATE Mask */ + +/*@}*/ /* end of group PwrModCtl_Type */ + + +/** + \ingroup CMSIS_core_register + \defgroup EWIC_Type External Wakeup Interrupt Controller Registers + \brief Type definitions for the External Wakeup Interrupt Controller Registers (EWIC) + @{ + */ + +/** + \brief Structure type to access the External Wakeup Interrupt Controller Registers (EWIC). + */ +typedef struct +{ + __OM uint32_t EVENTSPR; /*!< Offset: 0x000 ( /W) Event Set Pending Register */ + uint32_t RESERVED0[31U]; + __IM uint32_t EVENTMASKA; /*!< Offset: 0x080 (R/W) Event Mask A Register */ + __IM uint32_t EVENTMASK[15]; /*!< Offset: 0x084 (R/W) Event Mask Register */ +} EWIC_Type; + +/* EWIC External Wakeup Interrupt Controller (EVENTSPR) Register Definitions */ +#define EWIC_EVENTSPR_EDBGREQ_Pos 2U /*!< EWIC EVENTSPR: EDBGREQ Position */ +#define EWIC_EVENTSPR_EDBGREQ_Msk (0x1UL << EWIC_EVENTSPR_EDBGREQ_Pos) /*!< EWIC EVENTSPR: EDBGREQ Mask */ + +#define EWIC_EVENTSPR_NMI_Pos 1U /*!< EWIC EVENTSPR: NMI Position */ +#define EWIC_EVENTSPR_NMI_Msk (0x1UL << EWIC_EVENTSPR_NMI_Pos) /*!< EWIC EVENTSPR: NMI Mask */ + +#define EWIC_EVENTSPR_EVENT_Pos 0U /*!< EWIC EVENTSPR: EVENT Position */ +#define EWIC_EVENTSPR_EVENT_Msk (0x1UL /*<< EWIC_EVENTSPR_EVENT_Pos*/) /*!< EWIC EVENTSPR: EVENT Mask */ + +/* EWIC External Wakeup Interrupt Controller (EVENTMASKA) Register Definitions */ +#define EWIC_EVENTMASKA_EDBGREQ_Pos 2U /*!< EWIC EVENTMASKA: EDBGREQ Position */ +#define EWIC_EVENTMASKA_EDBGREQ_Msk (0x1UL << EWIC_EVENTMASKA_EDBGREQ_Pos) /*!< EWIC EVENTMASKA: EDBGREQ Mask */ + +#define EWIC_EVENTMASKA_NMI_Pos 1U /*!< EWIC EVENTMASKA: NMI Position */ +#define EWIC_EVENTMASKA_NMI_Msk (0x1UL << EWIC_EVENTMASKA_NMI_Pos) /*!< EWIC EVENTMASKA: NMI Mask */ + +#define EWIC_EVENTMASKA_EVENT_Pos 0U /*!< EWIC EVENTMASKA: EVENT Position */ +#define EWIC_EVENTMASKA_EVENT_Msk (0x1UL /*<< EWIC_EVENTMASKA_EVENT_Pos*/) /*!< EWIC EVENTMASKA: EVENT Mask */ + +/* EWIC External Wakeup Interrupt Controller (EVENTMASK) Register Definitions */ +#define EWIC_EVENTMASK_IRQ_Pos 0U /*!< EWIC EVENTMASKA: IRQ Position */ +#define EWIC_EVENTMASK_IRQ_Msk (0xFFFFFFFFUL /*<< EWIC_EVENTMASKA_IRQ_Pos*/) /*!< EWIC EVENTMASKA: IRQ Mask */ + +/*@}*/ /* end of group EWIC_Type */ + + +/** + \ingroup CMSIS_core_register + \defgroup ErrBnk_Type Error Banking Registers (IMPLEMENTATION DEFINED) + \brief Type definitions for the Error Banking Registers (ERRBNK) + @{ + */ + +/** + \brief Structure type to access the Error Banking Registers (ERRBNK). + */ +typedef struct +{ + __IOM uint32_t IEBR0; /*!< Offset: 0x000 (R/W) Instruction Cache Error Bank Register 0 */ + __IOM uint32_t IEBR1; /*!< Offset: 0x004 (R/W) Instruction Cache Error Bank Register 1 */ + uint32_t RESERVED0[2U]; + __IOM uint32_t DEBR0; /*!< Offset: 0x010 (R/W) Data Cache Error Bank Register 0 */ + __IOM uint32_t DEBR1; /*!< Offset: 0x014 (R/W) Data Cache Error Bank Register 1 */ + uint32_t RESERVED1[2U]; + __IOM uint32_t TEBR0; /*!< Offset: 0x020 (R/W) TCM Error Bank Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t TEBR1; /*!< Offset: 0x028 (R/W) TCM Error Bank Register 1 */ +} ErrBnk_Type; + +/* ERRBNK Instruction Cache Error Bank Register 0 (IEBR0) Register Definitions */ +#define ERRBNK_IEBR0_SWDEF_Pos 30U /*!< ERRBNK IEBR0: SWDEF Position */ +#define ERRBNK_IEBR0_SWDEF_Msk (0x3UL << ERRBNK_IEBR0_SWDEF_Pos) /*!< ERRBNK IEBR0: SWDEF Mask */ + +#define ERRBNK_IEBR0_BANK_Pos 16U /*!< ERRBNK IEBR0: BANK Position */ +#define ERRBNK_IEBR0_BANK_Msk (0x1UL << ERRBNK_IEBR0_BANK_Pos) /*!< ERRBNK IEBR0: BANK Mask */ + +#define ERRBNK_IEBR0_LOCATION_Pos 2U /*!< ERRBNK IEBR0: LOCATION Position */ +#define ERRBNK_IEBR0_LOCATION_Msk (0x3FFFUL << ERRBNK_IEBR0_LOCATION_Pos) /*!< ERRBNK IEBR0: LOCATION Mask */ + +#define ERRBNK_IEBR0_LOCKED_Pos 1U /*!< ERRBNK IEBR0: LOCKED Position */ +#define ERRBNK_IEBR0_LOCKED_Msk (0x1UL << ERRBNK_IEBR0_LOCKED_Pos) /*!< ERRBNK IEBR0: LOCKED Mask */ + +#define ERRBNK_IEBR0_VALID_Pos 0U /*!< ERRBNK IEBR0: VALID Position */ +#define ERRBNK_IEBR0_VALID_Msk (0x1UL << /*ERRBNK_IEBR0_VALID_Pos*/) /*!< ERRBNK IEBR0: VALID Mask */ + +/* ERRBNK Instruction Cache Error Bank Register 1 (IEBR1) Register Definitions */ +#define ERRBNK_IEBR1_SWDEF_Pos 30U /*!< ERRBNK IEBR1: SWDEF Position */ +#define ERRBNK_IEBR1_SWDEF_Msk (0x3UL << ERRBNK_IEBR1_SWDEF_Pos) /*!< ERRBNK IEBR1: SWDEF Mask */ + +#define ERRBNK_IEBR1_BANK_Pos 16U /*!< ERRBNK IEBR1: BANK Position */ +#define ERRBNK_IEBR1_BANK_Msk (0x1UL << ERRBNK_IEBR1_BANK_Pos) /*!< ERRBNK IEBR1: BANK Mask */ + +#define ERRBNK_IEBR1_LOCATION_Pos 2U /*!< ERRBNK IEBR1: LOCATION Position */ +#define ERRBNK_IEBR1_LOCATION_Msk (0x3FFFUL << ERRBNK_IEBR1_LOCATION_Pos) /*!< ERRBNK IEBR1: LOCATION Mask */ + +#define ERRBNK_IEBR1_LOCKED_Pos 1U /*!< ERRBNK IEBR1: LOCKED Position */ +#define ERRBNK_IEBR1_LOCKED_Msk (0x1UL << ERRBNK_IEBR1_LOCKED_Pos) /*!< ERRBNK IEBR1: LOCKED Mask */ + +#define ERRBNK_IEBR1_VALID_Pos 0U /*!< ERRBNK IEBR1: VALID Position */ +#define ERRBNK_IEBR1_VALID_Msk (0x1UL << /*ERRBNK_IEBR1_VALID_Pos*/) /*!< ERRBNK IEBR1: VALID Mask */ + +/* ERRBNK Data Cache Error Bank Register 0 (DEBR0) Register Definitions */ +#define ERRBNK_DEBR0_SWDEF_Pos 30U /*!< ERRBNK DEBR0: SWDEF Position */ +#define ERRBNK_DEBR0_SWDEF_Msk (0x3UL << ERRBNK_DEBR0_SWDEF_Pos) /*!< ERRBNK DEBR0: SWDEF Mask */ + +#define ERRBNK_DEBR0_TYPE_Pos 17U /*!< ERRBNK DEBR0: TYPE Position */ +#define ERRBNK_DEBR0_TYPE_Msk (0x1UL << ERRBNK_DEBR0_TYPE_Pos) /*!< ERRBNK DEBR0: TYPE Mask */ + +#define ERRBNK_DEBR0_BANK_Pos 16U /*!< ERRBNK DEBR0: BANK Position */ +#define ERRBNK_DEBR0_BANK_Msk (0x1UL << ERRBNK_DEBR0_BANK_Pos) /*!< ERRBNK DEBR0: BANK Mask */ + +#define ERRBNK_DEBR0_LOCATION_Pos 2U /*!< ERRBNK DEBR0: LOCATION Position */ +#define ERRBNK_DEBR0_LOCATION_Msk (0x3FFFUL << ERRBNK_DEBR0_LOCATION_Pos) /*!< ERRBNK DEBR0: LOCATION Mask */ + +#define ERRBNK_DEBR0_LOCKED_Pos 1U /*!< ERRBNK DEBR0: LOCKED Position */ +#define ERRBNK_DEBR0_LOCKED_Msk (0x1UL << ERRBNK_DEBR0_LOCKED_Pos) /*!< ERRBNK DEBR0: LOCKED Mask */ + +#define ERRBNK_DEBR0_VALID_Pos 0U /*!< ERRBNK DEBR0: VALID Position */ +#define ERRBNK_DEBR0_VALID_Msk (0x1UL << /*ERRBNK_DEBR0_VALID_Pos*/) /*!< ERRBNK DEBR0: VALID Mask */ + +/* ERRBNK Data Cache Error Bank Register 1 (DEBR1) Register Definitions */ +#define ERRBNK_DEBR1_SWDEF_Pos 30U /*!< ERRBNK DEBR1: SWDEF Position */ +#define ERRBNK_DEBR1_SWDEF_Msk (0x3UL << ERRBNK_DEBR1_SWDEF_Pos) /*!< ERRBNK DEBR1: SWDEF Mask */ + +#define ERRBNK_DEBR1_TYPE_Pos 17U /*!< ERRBNK DEBR1: TYPE Position */ +#define ERRBNK_DEBR1_TYPE_Msk (0x1UL << ERRBNK_DEBR1_TYPE_Pos) /*!< ERRBNK DEBR1: TYPE Mask */ + +#define ERRBNK_DEBR1_BANK_Pos 16U /*!< ERRBNK DEBR1: BANK Position */ +#define ERRBNK_DEBR1_BANK_Msk (0x1UL << ERRBNK_DEBR1_BANK_Pos) /*!< ERRBNK DEBR1: BANK Mask */ + +#define ERRBNK_DEBR1_LOCATION_Pos 2U /*!< ERRBNK DEBR1: LOCATION Position */ +#define ERRBNK_DEBR1_LOCATION_Msk (0x3FFFUL << ERRBNK_DEBR1_LOCATION_Pos) /*!< ERRBNK DEBR1: LOCATION Mask */ + +#define ERRBNK_DEBR1_LOCKED_Pos 1U /*!< ERRBNK DEBR1: LOCKED Position */ +#define ERRBNK_DEBR1_LOCKED_Msk (0x1UL << ERRBNK_DEBR1_LOCKED_Pos) /*!< ERRBNK DEBR1: LOCKED Mask */ + +#define ERRBNK_DEBR1_VALID_Pos 0U /*!< ERRBNK DEBR1: VALID Position */ +#define ERRBNK_DEBR1_VALID_Msk (0x1UL << /*ERRBNK_DEBR1_VALID_Pos*/) /*!< ERRBNK DEBR1: VALID Mask */ + +/* ERRBNK TCM Error Bank Register 0 (TEBR0) Register Definitions */ +#define ERRBNK_TEBR0_SWDEF_Pos 30U /*!< ERRBNK TEBR0: SWDEF Position */ +#define ERRBNK_TEBR0_SWDEF_Msk (0x3UL << ERRBNK_TEBR0_SWDEF_Pos) /*!< ERRBNK TEBR0: SWDEF Mask */ + +#define ERRBNK_TEBR0_POISON_Pos 28U /*!< ERRBNK TEBR0: POISON Position */ +#define ERRBNK_TEBR0_POISON_Msk (0x1UL << ERRBNK_TEBR0_POISON_Pos) /*!< ERRBNK TEBR0: POISON Mask */ + +#define ERRBNK_TEBR0_TYPE_Pos 27U /*!< ERRBNK TEBR0: TYPE Position */ +#define ERRBNK_TEBR0_TYPE_Msk (0x1UL << ERRBNK_TEBR0_TYPE_Pos) /*!< ERRBNK TEBR0: TYPE Mask */ + +#define ERRBNK_TEBR0_BANK_Pos 24U /*!< ERRBNK TEBR0: BANK Position */ +#define ERRBNK_TEBR0_BANK_Msk (0x3UL << ERRBNK_TEBR0_BANK_Pos) /*!< ERRBNK TEBR0: BANK Mask */ + +#define ERRBNK_TEBR0_LOCATION_Pos 2U /*!< ERRBNK TEBR0: LOCATION Position */ +#define ERRBNK_TEBR0_LOCATION_Msk (0x3FFFFFUL << ERRBNK_TEBR0_LOCATION_Pos) /*!< ERRBNK TEBR0: LOCATION Mask */ + +#define ERRBNK_TEBR0_LOCKED_Pos 1U /*!< ERRBNK TEBR0: LOCKED Position */ +#define ERRBNK_TEBR0_LOCKED_Msk (0x1UL << ERRBNK_TEBR0_LOCKED_Pos) /*!< ERRBNK TEBR0: LOCKED Mask */ + +#define ERRBNK_TEBR0_VALID_Pos 0U /*!< ERRBNK TEBR0: VALID Position */ +#define ERRBNK_TEBR0_VALID_Msk (0x1UL << /*ERRBNK_TEBR0_VALID_Pos*/) /*!< ERRBNK TEBR0: VALID Mask */ + +/* ERRBNK TCM Error Bank Register 1 (TEBR1) Register Definitions */ +#define ERRBNK_TEBR1_SWDEF_Pos 30U /*!< ERRBNK TEBR1: SWDEF Position */ +#define ERRBNK_TEBR1_SWDEF_Msk (0x3UL << ERRBNK_TEBR1_SWDEF_Pos) /*!< ERRBNK TEBR1: SWDEF Mask */ + +#define ERRBNK_TEBR1_POISON_Pos 28U /*!< ERRBNK TEBR1: POISON Position */ +#define ERRBNK_TEBR1_POISON_Msk (0x1UL << ERRBNK_TEBR1_POISON_Pos) /*!< ERRBNK TEBR1: POISON Mask */ + +#define ERRBNK_TEBR1_TYPE_Pos 27U /*!< ERRBNK TEBR1: TYPE Position */ +#define ERRBNK_TEBR1_TYPE_Msk (0x1UL << ERRBNK_TEBR1_TYPE_Pos) /*!< ERRBNK TEBR1: TYPE Mask */ + +#define ERRBNK_TEBR1_BANK_Pos 24U /*!< ERRBNK TEBR1: BANK Position */ +#define ERRBNK_TEBR1_BANK_Msk (0x3UL << ERRBNK_TEBR1_BANK_Pos) /*!< ERRBNK TEBR1: BANK Mask */ + +#define ERRBNK_TEBR1_LOCATION_Pos 2U /*!< ERRBNK TEBR1: LOCATION Position */ +#define ERRBNK_TEBR1_LOCATION_Msk (0x3FFFFFUL << ERRBNK_TEBR1_LOCATION_Pos) /*!< ERRBNK TEBR1: LOCATION Mask */ + +#define ERRBNK_TEBR1_LOCKED_Pos 1U /*!< ERRBNK TEBR1: LOCKED Position */ +#define ERRBNK_TEBR1_LOCKED_Msk (0x1UL << ERRBNK_TEBR1_LOCKED_Pos) /*!< ERRBNK TEBR1: LOCKED Mask */ + +#define ERRBNK_TEBR1_VALID_Pos 0U /*!< ERRBNK TEBR1: VALID Position */ +#define ERRBNK_TEBR1_VALID_Msk (0x1UL << /*ERRBNK_TEBR1_VALID_Pos*/) /*!< ERRBNK TEBR1: VALID Mask */ + +/*@}*/ /* end of group ErrBnk_Type */ + + +/** + \ingroup CMSIS_core_register + \defgroup PrcCfgInf_Type Processor Configuration Information Registers (IMPLEMENTATION DEFINED) + \brief Type definitions for the Processor Configuration Information Registerss (PRCCFGINF) + @{ + */ + +/** + \brief Structure type to access the Processor Configuration Information Registerss (PRCCFGINF). + */ +typedef struct +{ + __OM uint32_t CFGINFOSEL; /*!< Offset: 0x000 ( /W) Processor Configuration Information Selection Register */ + __IM uint32_t CFGINFORD; /*!< Offset: 0x004 (R/ ) Processor Configuration Information Read Data Register */ +} PrcCfgInf_Type; + +/* PRCCFGINF Processor Configuration Information Selection Register (CFGINFOSEL) Definitions */ + +/* PRCCFGINF Processor Configuration Information Read Data Register (CFGINFORD) Definitions */ + +/*@}*/ /* end of group PrcCfgInf_Type */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Sizes Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Sizes Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ + uint32_t RESERVED3[809U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) Software Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) Software Lock Status Register */ + uint32_t RESERVED4[4U]; + __IM uint32_t TYPE; /*!< Offset: 0xFC8 (R/ ) Device Identifier Register */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Register */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_SWOSCALER_Pos 0U /*!< TPI ACPR: SWOSCALER Position */ +#define TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/) /*!< TPI ACPR: SWOSCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ +#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ + +#define TPI_FFCR_EnFmt_Pos 0U /*!< TPI FFCR: EnFmt Position */ +#define TPI_FFCR_EnFmt_Msk (0x3UL << /*TPI_FFCR_EnFmt_Pos*/) /*!< TPI FFCR: EnFmt Mask */ + +/* TPI Periodic Synchronization Control Register Definitions */ +#define TPI_PSCR_PSCount_Pos 0U /*!< TPI PSCR: PSCount Position */ +#define TPI_PSCR_PSCount_Msk (0x1FUL /*<< TPI_PSCR_PSCount_Pos*/) /*!< TPI PSCR: TPSCount Mask */ + +/* TPI Software Lock Status Register Definitions */ +#define TPI_LSR_nTT_Pos 1U /*!< TPI LSR: Not thirty-two bit. Position */ +#define TPI_LSR_nTT_Msk (0x1UL << TPI_LSR_nTT_Pos) /*!< TPI LSR: Not thirty-two bit. Mask */ + +#define TPI_LSR_SLK_Pos 1U /*!< TPI LSR: Software Lock status Position */ +#define TPI_LSR_SLK_Msk (0x1UL << TPI_LSR_SLK_Pos) /*!< TPI LSR: Software Lock status Mask */ + +#define TPI_LSR_SLI_Pos 0U /*!< TPI LSR: Software Lock implemented Position */ +#define TPI_LSR_SLI_Msk (0x1UL /*<< TPI_LSR_SLI_Pos*/) /*!< TPI LSR: Software Lock implemented Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFO depth Position */ +#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFO depth Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + +#if defined (__PMU_PRESENT) && (__PMU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_PMU Performance Monitoring Unit (PMU) + \brief Type definitions for the Performance Monitoring Unit (PMU) + @{ + */ + +/** + \brief Structure type to access the Performance Monitoring Unit (PMU). + */ +typedef struct +{ + __IOM uint32_t EVCNTR[__PMU_NUM_EVENTCNT]; /*!< Offset: 0x0 (R/W) PMU Event Counter Registers */ +#if __PMU_NUM_EVENTCNT<31 + uint32_t RESERVED0[31U-__PMU_NUM_EVENTCNT]; +#endif + __IOM uint32_t CCNTR; /*!< Offset: 0x7C (R/W) PMU Cycle Counter Register */ + uint32_t RESERVED1[224]; + __IOM uint32_t EVTYPER[__PMU_NUM_EVENTCNT]; /*!< Offset: 0x400 (R/W) PMU Event Type and Filter Registers */ +#if __PMU_NUM_EVENTCNT<31 + uint32_t RESERVED2[31U-__PMU_NUM_EVENTCNT]; +#endif + __IOM uint32_t CCFILTR; /*!< Offset: 0x47C (R/W) PMU Cycle Counter Filter Register */ + uint32_t RESERVED3[480]; + __IOM uint32_t CNTENSET; /*!< Offset: 0xC00 (R/W) PMU Count Enable Set Register */ + uint32_t RESERVED4[7]; + __IOM uint32_t CNTENCLR; /*!< Offset: 0xC20 (R/W) PMU Count Enable Clear Register */ + uint32_t RESERVED5[7]; + __IOM uint32_t INTENSET; /*!< Offset: 0xC40 (R/W) PMU Interrupt Enable Set Register */ + uint32_t RESERVED6[7]; + __IOM uint32_t INTENCLR; /*!< Offset: 0xC60 (R/W) PMU Interrupt Enable Clear Register */ + uint32_t RESERVED7[7]; + __IOM uint32_t OVSCLR; /*!< Offset: 0xC80 (R/W) PMU Overflow Flag Status Clear Register */ + uint32_t RESERVED8[7]; + __IOM uint32_t SWINC; /*!< Offset: 0xCA0 (R/W) PMU Software Increment Register */ + uint32_t RESERVED9[7]; + __IOM uint32_t OVSSET; /*!< Offset: 0xCC0 (R/W) PMU Overflow Flag Status Set Register */ + uint32_t RESERVED10[79]; + __IOM uint32_t TYPE; /*!< Offset: 0xE00 (R/W) PMU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0xE04 (R/W) PMU Control Register */ + uint32_t RESERVED11[108]; + __IOM uint32_t AUTHSTATUS; /*!< Offset: 0xFB8 (R/W) PMU Authentication Status Register */ + __IOM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/W) PMU Device Architecture Register */ + uint32_t RESERVED12[3]; + __IOM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/W) PMU Device Type Register */ + __IOM uint32_t PIDR4; /*!< Offset: 0xFD0 (R/W) PMU Peripheral Identification Register 4 */ + uint32_t RESERVED13[3]; + __IOM uint32_t PIDR0; /*!< Offset: 0xFE0 (R/W) PMU Peripheral Identification Register 0 */ + __IOM uint32_t PIDR1; /*!< Offset: 0xFE4 (R/W) PMU Peripheral Identification Register 1 */ + __IOM uint32_t PIDR2; /*!< Offset: 0xFE8 (R/W) PMU Peripheral Identification Register 2 */ + __IOM uint32_t PIDR3; /*!< Offset: 0xFEC (R/W) PMU Peripheral Identification Register 3 */ + __IOM uint32_t CIDR0; /*!< Offset: 0xFF0 (R/W) PMU Component Identification Register 0 */ + __IOM uint32_t CIDR1; /*!< Offset: 0xFF4 (R/W) PMU Component Identification Register 1 */ + __IOM uint32_t CIDR2; /*!< Offset: 0xFF8 (R/W) PMU Component Identification Register 2 */ + __IOM uint32_t CIDR3; /*!< Offset: 0xFFC (R/W) PMU Component Identification Register 3 */ +} PMU_Type; + +/** \brief PMU Event Counter Registers (0-30) Definitions */ + +#define PMU_EVCNTR_CNT_Pos 0U /*!< PMU EVCNTR: Counter Position */ +#define PMU_EVCNTR_CNT_Msk (0xFFFFUL /*<< PMU_EVCNTRx_CNT_Pos*/) /*!< PMU EVCNTR: Counter Mask */ + +/** \brief PMU Event Type and Filter Registers (0-30) Definitions */ + +#define PMU_EVTYPER_EVENTTOCNT_Pos 0U /*!< PMU EVTYPER: Event to Count Position */ +#define PMU_EVTYPER_EVENTTOCNT_Msk (0xFFFFUL /*<< EVTYPERx_EVENTTOCNT_Pos*/) /*!< PMU EVTYPER: Event to Count Mask */ + +/** \brief PMU Count Enable Set Register Definitions */ + +#define PMU_CNTENSET_CNT0_ENABLE_Pos 0U /*!< PMU CNTENSET: Event Counter 0 Enable Set Position */ +#define PMU_CNTENSET_CNT0_ENABLE_Msk (1UL /*<< PMU_CNTENSET_CNT0_ENABLE_Pos*/) /*!< PMU CNTENSET: Event Counter 0 Enable Set Mask */ + +#define PMU_CNTENSET_CNT1_ENABLE_Pos 1U /*!< PMU CNTENSET: Event Counter 1 Enable Set Position */ +#define PMU_CNTENSET_CNT1_ENABLE_Msk (1UL << PMU_CNTENSET_CNT1_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 1 Enable Set Mask */ + +#define PMU_CNTENSET_CNT2_ENABLE_Pos 2U /*!< PMU CNTENSET: Event Counter 2 Enable Set Position */ +#define PMU_CNTENSET_CNT2_ENABLE_Msk (1UL << PMU_CNTENSET_CNT2_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 2 Enable Set Mask */ + +#define PMU_CNTENSET_CNT3_ENABLE_Pos 3U /*!< PMU CNTENSET: Event Counter 3 Enable Set Position */ +#define PMU_CNTENSET_CNT3_ENABLE_Msk (1UL << PMU_CNTENSET_CNT3_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 3 Enable Set Mask */ + +#define PMU_CNTENSET_CNT4_ENABLE_Pos 4U /*!< PMU CNTENSET: Event Counter 4 Enable Set Position */ +#define PMU_CNTENSET_CNT4_ENABLE_Msk (1UL << PMU_CNTENSET_CNT4_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 4 Enable Set Mask */ + +#define PMU_CNTENSET_CNT5_ENABLE_Pos 5U /*!< PMU CNTENSET: Event Counter 5 Enable Set Position */ +#define PMU_CNTENSET_CNT5_ENABLE_Msk (1UL << PMU_CNTENSET_CNT5_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 5 Enable Set Mask */ + +#define PMU_CNTENSET_CNT6_ENABLE_Pos 6U /*!< PMU CNTENSET: Event Counter 6 Enable Set Position */ +#define PMU_CNTENSET_CNT6_ENABLE_Msk (1UL << PMU_CNTENSET_CNT6_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 6 Enable Set Mask */ + +#define PMU_CNTENSET_CNT7_ENABLE_Pos 7U /*!< PMU CNTENSET: Event Counter 7 Enable Set Position */ +#define PMU_CNTENSET_CNT7_ENABLE_Msk (1UL << PMU_CNTENSET_CNT7_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 7 Enable Set Mask */ + +#define PMU_CNTENSET_CNT8_ENABLE_Pos 8U /*!< PMU CNTENSET: Event Counter 8 Enable Set Position */ +#define PMU_CNTENSET_CNT8_ENABLE_Msk (1UL << PMU_CNTENSET_CNT8_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 8 Enable Set Mask */ + +#define PMU_CNTENSET_CNT9_ENABLE_Pos 9U /*!< PMU CNTENSET: Event Counter 9 Enable Set Position */ +#define PMU_CNTENSET_CNT9_ENABLE_Msk (1UL << PMU_CNTENSET_CNT9_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 9 Enable Set Mask */ + +#define PMU_CNTENSET_CNT10_ENABLE_Pos 10U /*!< PMU CNTENSET: Event Counter 10 Enable Set Position */ +#define PMU_CNTENSET_CNT10_ENABLE_Msk (1UL << PMU_CNTENSET_CNT10_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 10 Enable Set Mask */ + +#define PMU_CNTENSET_CNT11_ENABLE_Pos 11U /*!< PMU CNTENSET: Event Counter 11 Enable Set Position */ +#define PMU_CNTENSET_CNT11_ENABLE_Msk (1UL << PMU_CNTENSET_CNT11_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 11 Enable Set Mask */ + +#define PMU_CNTENSET_CNT12_ENABLE_Pos 12U /*!< PMU CNTENSET: Event Counter 12 Enable Set Position */ +#define PMU_CNTENSET_CNT12_ENABLE_Msk (1UL << PMU_CNTENSET_CNT12_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 12 Enable Set Mask */ + +#define PMU_CNTENSET_CNT13_ENABLE_Pos 13U /*!< PMU CNTENSET: Event Counter 13 Enable Set Position */ +#define PMU_CNTENSET_CNT13_ENABLE_Msk (1UL << PMU_CNTENSET_CNT13_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 13 Enable Set Mask */ + +#define PMU_CNTENSET_CNT14_ENABLE_Pos 14U /*!< PMU CNTENSET: Event Counter 14 Enable Set Position */ +#define PMU_CNTENSET_CNT14_ENABLE_Msk (1UL << PMU_CNTENSET_CNT14_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 14 Enable Set Mask */ + +#define PMU_CNTENSET_CNT15_ENABLE_Pos 15U /*!< PMU CNTENSET: Event Counter 15 Enable Set Position */ +#define PMU_CNTENSET_CNT15_ENABLE_Msk (1UL << PMU_CNTENSET_CNT15_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 15 Enable Set Mask */ + +#define PMU_CNTENSET_CNT16_ENABLE_Pos 16U /*!< PMU CNTENSET: Event Counter 16 Enable Set Position */ +#define PMU_CNTENSET_CNT16_ENABLE_Msk (1UL << PMU_CNTENSET_CNT16_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 16 Enable Set Mask */ + +#define PMU_CNTENSET_CNT17_ENABLE_Pos 17U /*!< PMU CNTENSET: Event Counter 17 Enable Set Position */ +#define PMU_CNTENSET_CNT17_ENABLE_Msk (1UL << PMU_CNTENSET_CNT17_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 17 Enable Set Mask */ + +#define PMU_CNTENSET_CNT18_ENABLE_Pos 18U /*!< PMU CNTENSET: Event Counter 18 Enable Set Position */ +#define PMU_CNTENSET_CNT18_ENABLE_Msk (1UL << PMU_CNTENSET_CNT18_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 18 Enable Set Mask */ + +#define PMU_CNTENSET_CNT19_ENABLE_Pos 19U /*!< PMU CNTENSET: Event Counter 19 Enable Set Position */ +#define PMU_CNTENSET_CNT19_ENABLE_Msk (1UL << PMU_CNTENSET_CNT19_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 19 Enable Set Mask */ + +#define PMU_CNTENSET_CNT20_ENABLE_Pos 20U /*!< PMU CNTENSET: Event Counter 20 Enable Set Position */ +#define PMU_CNTENSET_CNT20_ENABLE_Msk (1UL << PMU_CNTENSET_CNT20_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 20 Enable Set Mask */ + +#define PMU_CNTENSET_CNT21_ENABLE_Pos 21U /*!< PMU CNTENSET: Event Counter 21 Enable Set Position */ +#define PMU_CNTENSET_CNT21_ENABLE_Msk (1UL << PMU_CNTENSET_CNT21_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 21 Enable Set Mask */ + +#define PMU_CNTENSET_CNT22_ENABLE_Pos 22U /*!< PMU CNTENSET: Event Counter 22 Enable Set Position */ +#define PMU_CNTENSET_CNT22_ENABLE_Msk (1UL << PMU_CNTENSET_CNT22_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 22 Enable Set Mask */ + +#define PMU_CNTENSET_CNT23_ENABLE_Pos 23U /*!< PMU CNTENSET: Event Counter 23 Enable Set Position */ +#define PMU_CNTENSET_CNT23_ENABLE_Msk (1UL << PMU_CNTENSET_CNT23_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 23 Enable Set Mask */ + +#define PMU_CNTENSET_CNT24_ENABLE_Pos 24U /*!< PMU CNTENSET: Event Counter 24 Enable Set Position */ +#define PMU_CNTENSET_CNT24_ENABLE_Msk (1UL << PMU_CNTENSET_CNT24_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 24 Enable Set Mask */ + +#define PMU_CNTENSET_CNT25_ENABLE_Pos 25U /*!< PMU CNTENSET: Event Counter 25 Enable Set Position */ +#define PMU_CNTENSET_CNT25_ENABLE_Msk (1UL << PMU_CNTENSET_CNT25_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 25 Enable Set Mask */ + +#define PMU_CNTENSET_CNT26_ENABLE_Pos 26U /*!< PMU CNTENSET: Event Counter 26 Enable Set Position */ +#define PMU_CNTENSET_CNT26_ENABLE_Msk (1UL << PMU_CNTENSET_CNT26_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 26 Enable Set Mask */ + +#define PMU_CNTENSET_CNT27_ENABLE_Pos 27U /*!< PMU CNTENSET: Event Counter 27 Enable Set Position */ +#define PMU_CNTENSET_CNT27_ENABLE_Msk (1UL << PMU_CNTENSET_CNT27_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 27 Enable Set Mask */ + +#define PMU_CNTENSET_CNT28_ENABLE_Pos 28U /*!< PMU CNTENSET: Event Counter 28 Enable Set Position */ +#define PMU_CNTENSET_CNT28_ENABLE_Msk (1UL << PMU_CNTENSET_CNT28_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 28 Enable Set Mask */ + +#define PMU_CNTENSET_CNT29_ENABLE_Pos 29U /*!< PMU CNTENSET: Event Counter 29 Enable Set Position */ +#define PMU_CNTENSET_CNT29_ENABLE_Msk (1UL << PMU_CNTENSET_CNT29_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 29 Enable Set Mask */ + +#define PMU_CNTENSET_CNT30_ENABLE_Pos 30U /*!< PMU CNTENSET: Event Counter 30 Enable Set Position */ +#define PMU_CNTENSET_CNT30_ENABLE_Msk (1UL << PMU_CNTENSET_CNT30_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 30 Enable Set Mask */ + +#define PMU_CNTENSET_CCNTR_ENABLE_Pos 31U /*!< PMU CNTENSET: Cycle Counter Enable Set Position */ +#define PMU_CNTENSET_CCNTR_ENABLE_Msk (1UL << PMU_CNTENSET_CCNTR_ENABLE_Pos) /*!< PMU CNTENSET: Cycle Counter Enable Set Mask */ + +/** \brief PMU Count Enable Clear Register Definitions */ + +#define PMU_CNTENSET_CNT0_ENABLE_Pos 0U /*!< PMU CNTENCLR: Event Counter 0 Enable Clear Position */ +#define PMU_CNTENCLR_CNT0_ENABLE_Msk (1UL /*<< PMU_CNTENCLR_CNT0_ENABLE_Pos*/) /*!< PMU CNTENCLR: Event Counter 0 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT1_ENABLE_Pos 1U /*!< PMU CNTENCLR: Event Counter 1 Enable Clear Position */ +#define PMU_CNTENCLR_CNT1_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT1_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 1 Enable Clear */ + +#define PMU_CNTENCLR_CNT2_ENABLE_Pos 2U /*!< PMU CNTENCLR: Event Counter 2 Enable Clear Position */ +#define PMU_CNTENCLR_CNT2_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT2_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 2 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT3_ENABLE_Pos 3U /*!< PMU CNTENCLR: Event Counter 3 Enable Clear Position */ +#define PMU_CNTENCLR_CNT3_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT3_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 3 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT4_ENABLE_Pos 4U /*!< PMU CNTENCLR: Event Counter 4 Enable Clear Position */ +#define PMU_CNTENCLR_CNT4_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT4_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 4 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT5_ENABLE_Pos 5U /*!< PMU CNTENCLR: Event Counter 5 Enable Clear Position */ +#define PMU_CNTENCLR_CNT5_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT5_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 5 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT6_ENABLE_Pos 6U /*!< PMU CNTENCLR: Event Counter 6 Enable Clear Position */ +#define PMU_CNTENCLR_CNT6_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT6_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 6 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT7_ENABLE_Pos 7U /*!< PMU CNTENCLR: Event Counter 7 Enable Clear Position */ +#define PMU_CNTENCLR_CNT7_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT7_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 7 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT8_ENABLE_Pos 8U /*!< PMU CNTENCLR: Event Counter 8 Enable Clear Position */ +#define PMU_CNTENCLR_CNT8_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT8_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 8 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT9_ENABLE_Pos 9U /*!< PMU CNTENCLR: Event Counter 9 Enable Clear Position */ +#define PMU_CNTENCLR_CNT9_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT9_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 9 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT10_ENABLE_Pos 10U /*!< PMU CNTENCLR: Event Counter 10 Enable Clear Position */ +#define PMU_CNTENCLR_CNT10_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT10_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 10 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT11_ENABLE_Pos 11U /*!< PMU CNTENCLR: Event Counter 11 Enable Clear Position */ +#define PMU_CNTENCLR_CNT11_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT11_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 11 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT12_ENABLE_Pos 12U /*!< PMU CNTENCLR: Event Counter 12 Enable Clear Position */ +#define PMU_CNTENCLR_CNT12_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT12_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 12 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT13_ENABLE_Pos 13U /*!< PMU CNTENCLR: Event Counter 13 Enable Clear Position */ +#define PMU_CNTENCLR_CNT13_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT13_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 13 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT14_ENABLE_Pos 14U /*!< PMU CNTENCLR: Event Counter 14 Enable Clear Position */ +#define PMU_CNTENCLR_CNT14_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT14_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 14 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT15_ENABLE_Pos 15U /*!< PMU CNTENCLR: Event Counter 15 Enable Clear Position */ +#define PMU_CNTENCLR_CNT15_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT15_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 15 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT16_ENABLE_Pos 16U /*!< PMU CNTENCLR: Event Counter 16 Enable Clear Position */ +#define PMU_CNTENCLR_CNT16_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT16_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 16 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT17_ENABLE_Pos 17U /*!< PMU CNTENCLR: Event Counter 17 Enable Clear Position */ +#define PMU_CNTENCLR_CNT17_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT17_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 17 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT18_ENABLE_Pos 18U /*!< PMU CNTENCLR: Event Counter 18 Enable Clear Position */ +#define PMU_CNTENCLR_CNT18_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT18_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 18 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT19_ENABLE_Pos 19U /*!< PMU CNTENCLR: Event Counter 19 Enable Clear Position */ +#define PMU_CNTENCLR_CNT19_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT19_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 19 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT20_ENABLE_Pos 20U /*!< PMU CNTENCLR: Event Counter 20 Enable Clear Position */ +#define PMU_CNTENCLR_CNT20_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT20_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 20 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT21_ENABLE_Pos 21U /*!< PMU CNTENCLR: Event Counter 21 Enable Clear Position */ +#define PMU_CNTENCLR_CNT21_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT21_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 21 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT22_ENABLE_Pos 22U /*!< PMU CNTENCLR: Event Counter 22 Enable Clear Position */ +#define PMU_CNTENCLR_CNT22_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT22_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 22 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT23_ENABLE_Pos 23U /*!< PMU CNTENCLR: Event Counter 23 Enable Clear Position */ +#define PMU_CNTENCLR_CNT23_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT23_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 23 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT24_ENABLE_Pos 24U /*!< PMU CNTENCLR: Event Counter 24 Enable Clear Position */ +#define PMU_CNTENCLR_CNT24_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT24_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 24 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT25_ENABLE_Pos 25U /*!< PMU CNTENCLR: Event Counter 25 Enable Clear Position */ +#define PMU_CNTENCLR_CNT25_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT25_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 25 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT26_ENABLE_Pos 26U /*!< PMU CNTENCLR: Event Counter 26 Enable Clear Position */ +#define PMU_CNTENCLR_CNT26_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT26_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 26 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT27_ENABLE_Pos 27U /*!< PMU CNTENCLR: Event Counter 27 Enable Clear Position */ +#define PMU_CNTENCLR_CNT27_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT27_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 27 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT28_ENABLE_Pos 28U /*!< PMU CNTENCLR: Event Counter 28 Enable Clear Position */ +#define PMU_CNTENCLR_CNT28_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT28_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 28 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT29_ENABLE_Pos 29U /*!< PMU CNTENCLR: Event Counter 29 Enable Clear Position */ +#define PMU_CNTENCLR_CNT29_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT29_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 29 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT30_ENABLE_Pos 30U /*!< PMU CNTENCLR: Event Counter 30 Enable Clear Position */ +#define PMU_CNTENCLR_CNT30_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT30_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 30 Enable Clear Mask */ + +#define PMU_CNTENCLR_CCNTR_ENABLE_Pos 31U /*!< PMU CNTENCLR: Cycle Counter Enable Clear Position */ +#define PMU_CNTENCLR_CCNTR_ENABLE_Msk (1UL << PMU_CNTENCLR_CCNTR_ENABLE_Pos) /*!< PMU CNTENCLR: Cycle Counter Enable Clear Mask */ + +/** \brief PMU Interrupt Enable Set Register Definitions */ + +#define PMU_INTENSET_CNT0_ENABLE_Pos 0U /*!< PMU INTENSET: Event Counter 0 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT0_ENABLE_Msk (1UL /*<< PMU_INTENSET_CNT0_ENABLE_Pos*/) /*!< PMU INTENSET: Event Counter 0 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT1_ENABLE_Pos 1U /*!< PMU INTENSET: Event Counter 1 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT1_ENABLE_Msk (1UL << PMU_INTENSET_CNT1_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 1 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT2_ENABLE_Pos 2U /*!< PMU INTENSET: Event Counter 2 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT2_ENABLE_Msk (1UL << PMU_INTENSET_CNT2_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 2 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT3_ENABLE_Pos 3U /*!< PMU INTENSET: Event Counter 3 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT3_ENABLE_Msk (1UL << PMU_INTENSET_CNT3_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 3 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT4_ENABLE_Pos 4U /*!< PMU INTENSET: Event Counter 4 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT4_ENABLE_Msk (1UL << PMU_INTENSET_CNT4_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 4 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT5_ENABLE_Pos 5U /*!< PMU INTENSET: Event Counter 5 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT5_ENABLE_Msk (1UL << PMU_INTENSET_CNT5_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 5 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT6_ENABLE_Pos 6U /*!< PMU INTENSET: Event Counter 6 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT6_ENABLE_Msk (1UL << PMU_INTENSET_CNT6_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 6 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT7_ENABLE_Pos 7U /*!< PMU INTENSET: Event Counter 7 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT7_ENABLE_Msk (1UL << PMU_INTENSET_CNT7_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 7 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT8_ENABLE_Pos 8U /*!< PMU INTENSET: Event Counter 8 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT8_ENABLE_Msk (1UL << PMU_INTENSET_CNT8_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 8 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT9_ENABLE_Pos 9U /*!< PMU INTENSET: Event Counter 9 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT9_ENABLE_Msk (1UL << PMU_INTENSET_CNT9_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 9 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT10_ENABLE_Pos 10U /*!< PMU INTENSET: Event Counter 10 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT10_ENABLE_Msk (1UL << PMU_INTENSET_CNT10_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 10 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT11_ENABLE_Pos 11U /*!< PMU INTENSET: Event Counter 11 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT11_ENABLE_Msk (1UL << PMU_INTENSET_CNT11_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 11 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT12_ENABLE_Pos 12U /*!< PMU INTENSET: Event Counter 12 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT12_ENABLE_Msk (1UL << PMU_INTENSET_CNT12_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 12 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT13_ENABLE_Pos 13U /*!< PMU INTENSET: Event Counter 13 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT13_ENABLE_Msk (1UL << PMU_INTENSET_CNT13_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 13 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT14_ENABLE_Pos 14U /*!< PMU INTENSET: Event Counter 14 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT14_ENABLE_Msk (1UL << PMU_INTENSET_CNT14_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 14 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT15_ENABLE_Pos 15U /*!< PMU INTENSET: Event Counter 15 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT15_ENABLE_Msk (1UL << PMU_INTENSET_CNT15_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 15 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT16_ENABLE_Pos 16U /*!< PMU INTENSET: Event Counter 16 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT16_ENABLE_Msk (1UL << PMU_INTENSET_CNT16_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 16 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT17_ENABLE_Pos 17U /*!< PMU INTENSET: Event Counter 17 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT17_ENABLE_Msk (1UL << PMU_INTENSET_CNT17_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 17 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT18_ENABLE_Pos 18U /*!< PMU INTENSET: Event Counter 18 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT18_ENABLE_Msk (1UL << PMU_INTENSET_CNT18_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 18 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT19_ENABLE_Pos 19U /*!< PMU INTENSET: Event Counter 19 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT19_ENABLE_Msk (1UL << PMU_INTENSET_CNT19_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 19 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT20_ENABLE_Pos 20U /*!< PMU INTENSET: Event Counter 20 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT20_ENABLE_Msk (1UL << PMU_INTENSET_CNT20_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 20 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT21_ENABLE_Pos 21U /*!< PMU INTENSET: Event Counter 21 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT21_ENABLE_Msk (1UL << PMU_INTENSET_CNT21_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 21 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT22_ENABLE_Pos 22U /*!< PMU INTENSET: Event Counter 22 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT22_ENABLE_Msk (1UL << PMU_INTENSET_CNT22_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 22 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT23_ENABLE_Pos 23U /*!< PMU INTENSET: Event Counter 23 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT23_ENABLE_Msk (1UL << PMU_INTENSET_CNT23_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 23 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT24_ENABLE_Pos 24U /*!< PMU INTENSET: Event Counter 24 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT24_ENABLE_Msk (1UL << PMU_INTENSET_CNT24_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 24 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT25_ENABLE_Pos 25U /*!< PMU INTENSET: Event Counter 25 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT25_ENABLE_Msk (1UL << PMU_INTENSET_CNT25_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 25 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT26_ENABLE_Pos 26U /*!< PMU INTENSET: Event Counter 26 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT26_ENABLE_Msk (1UL << PMU_INTENSET_CNT26_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 26 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT27_ENABLE_Pos 27U /*!< PMU INTENSET: Event Counter 27 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT27_ENABLE_Msk (1UL << PMU_INTENSET_CNT27_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 27 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT28_ENABLE_Pos 28U /*!< PMU INTENSET: Event Counter 28 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT28_ENABLE_Msk (1UL << PMU_INTENSET_CNT28_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 28 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT29_ENABLE_Pos 29U /*!< PMU INTENSET: Event Counter 29 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT29_ENABLE_Msk (1UL << PMU_INTENSET_CNT29_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 29 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT30_ENABLE_Pos 30U /*!< PMU INTENSET: Event Counter 30 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT30_ENABLE_Msk (1UL << PMU_INTENSET_CNT30_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 30 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CYCCNT_ENABLE_Pos 31U /*!< PMU INTENSET: Cycle Counter Interrupt Enable Set Position */ +#define PMU_INTENSET_CCYCNT_ENABLE_Msk (1UL << PMU_INTENSET_CYCCNT_ENABLE_Pos) /*!< PMU INTENSET: Cycle Counter Interrupt Enable Set Mask */ + +/** \brief PMU Interrupt Enable Clear Register Definitions */ + +#define PMU_INTENSET_CNT0_ENABLE_Pos 0U /*!< PMU INTENCLR: Event Counter 0 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT0_ENABLE_Msk (1UL /*<< PMU_INTENCLR_CNT0_ENABLE_Pos*/) /*!< PMU INTENCLR: Event Counter 0 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT1_ENABLE_Pos 1U /*!< PMU INTENCLR: Event Counter 1 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT1_ENABLE_Msk (1UL << PMU_INTENCLR_CNT1_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 1 Interrupt Enable Clear */ + +#define PMU_INTENCLR_CNT2_ENABLE_Pos 2U /*!< PMU INTENCLR: Event Counter 2 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT2_ENABLE_Msk (1UL << PMU_INTENCLR_CNT2_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 2 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT3_ENABLE_Pos 3U /*!< PMU INTENCLR: Event Counter 3 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT3_ENABLE_Msk (1UL << PMU_INTENCLR_CNT3_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 3 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT4_ENABLE_Pos 4U /*!< PMU INTENCLR: Event Counter 4 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT4_ENABLE_Msk (1UL << PMU_INTENCLR_CNT4_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 4 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT5_ENABLE_Pos 5U /*!< PMU INTENCLR: Event Counter 5 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT5_ENABLE_Msk (1UL << PMU_INTENCLR_CNT5_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 5 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT6_ENABLE_Pos 6U /*!< PMU INTENCLR: Event Counter 6 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT6_ENABLE_Msk (1UL << PMU_INTENCLR_CNT6_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 6 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT7_ENABLE_Pos 7U /*!< PMU INTENCLR: Event Counter 7 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT7_ENABLE_Msk (1UL << PMU_INTENCLR_CNT7_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 7 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT8_ENABLE_Pos 8U /*!< PMU INTENCLR: Event Counter 8 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT8_ENABLE_Msk (1UL << PMU_INTENCLR_CNT8_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 8 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT9_ENABLE_Pos 9U /*!< PMU INTENCLR: Event Counter 9 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT9_ENABLE_Msk (1UL << PMU_INTENCLR_CNT9_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 9 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT10_ENABLE_Pos 10U /*!< PMU INTENCLR: Event Counter 10 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT10_ENABLE_Msk (1UL << PMU_INTENCLR_CNT10_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 10 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT11_ENABLE_Pos 11U /*!< PMU INTENCLR: Event Counter 11 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT11_ENABLE_Msk (1UL << PMU_INTENCLR_CNT11_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 11 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT12_ENABLE_Pos 12U /*!< PMU INTENCLR: Event Counter 12 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT12_ENABLE_Msk (1UL << PMU_INTENCLR_CNT12_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 12 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT13_ENABLE_Pos 13U /*!< PMU INTENCLR: Event Counter 13 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT13_ENABLE_Msk (1UL << PMU_INTENCLR_CNT13_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 13 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT14_ENABLE_Pos 14U /*!< PMU INTENCLR: Event Counter 14 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT14_ENABLE_Msk (1UL << PMU_INTENCLR_CNT14_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 14 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT15_ENABLE_Pos 15U /*!< PMU INTENCLR: Event Counter 15 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT15_ENABLE_Msk (1UL << PMU_INTENCLR_CNT15_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 15 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT16_ENABLE_Pos 16U /*!< PMU INTENCLR: Event Counter 16 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT16_ENABLE_Msk (1UL << PMU_INTENCLR_CNT16_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 16 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT17_ENABLE_Pos 17U /*!< PMU INTENCLR: Event Counter 17 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT17_ENABLE_Msk (1UL << PMU_INTENCLR_CNT17_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 17 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT18_ENABLE_Pos 18U /*!< PMU INTENCLR: Event Counter 18 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT18_ENABLE_Msk (1UL << PMU_INTENCLR_CNT18_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 18 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT19_ENABLE_Pos 19U /*!< PMU INTENCLR: Event Counter 19 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT19_ENABLE_Msk (1UL << PMU_INTENCLR_CNT19_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 19 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT20_ENABLE_Pos 20U /*!< PMU INTENCLR: Event Counter 20 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT20_ENABLE_Msk (1UL << PMU_INTENCLR_CNT20_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 20 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT21_ENABLE_Pos 21U /*!< PMU INTENCLR: Event Counter 21 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT21_ENABLE_Msk (1UL << PMU_INTENCLR_CNT21_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 21 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT22_ENABLE_Pos 22U /*!< PMU INTENCLR: Event Counter 22 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT22_ENABLE_Msk (1UL << PMU_INTENCLR_CNT22_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 22 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT23_ENABLE_Pos 23U /*!< PMU INTENCLR: Event Counter 23 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT23_ENABLE_Msk (1UL << PMU_INTENCLR_CNT23_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 23 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT24_ENABLE_Pos 24U /*!< PMU INTENCLR: Event Counter 24 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT24_ENABLE_Msk (1UL << PMU_INTENCLR_CNT24_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 24 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT25_ENABLE_Pos 25U /*!< PMU INTENCLR: Event Counter 25 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT25_ENABLE_Msk (1UL << PMU_INTENCLR_CNT25_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 25 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT26_ENABLE_Pos 26U /*!< PMU INTENCLR: Event Counter 26 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT26_ENABLE_Msk (1UL << PMU_INTENCLR_CNT26_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 26 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT27_ENABLE_Pos 27U /*!< PMU INTENCLR: Event Counter 27 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT27_ENABLE_Msk (1UL << PMU_INTENCLR_CNT27_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 27 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT28_ENABLE_Pos 28U /*!< PMU INTENCLR: Event Counter 28 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT28_ENABLE_Msk (1UL << PMU_INTENCLR_CNT28_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 28 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT29_ENABLE_Pos 29U /*!< PMU INTENCLR: Event Counter 29 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT29_ENABLE_Msk (1UL << PMU_INTENCLR_CNT29_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 29 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT30_ENABLE_Pos 30U /*!< PMU INTENCLR: Event Counter 30 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT30_ENABLE_Msk (1UL << PMU_INTENCLR_CNT30_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 30 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CYCCNT_ENABLE_Pos 31U /*!< PMU INTENCLR: Cycle Counter Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CYCCNT_ENABLE_Msk (1UL << PMU_INTENCLR_CYCCNT_ENABLE_Pos) /*!< PMU INTENCLR: Cycle Counter Interrupt Enable Clear Mask */ + +/** \brief PMU Overflow Flag Status Set Register Definitions */ + +#define PMU_OVSSET_CNT0_STATUS_Pos 0U /*!< PMU OVSSET: Event Counter 0 Overflow Set Position */ +#define PMU_OVSSET_CNT0_STATUS_Msk (1UL /*<< PMU_OVSSET_CNT0_STATUS_Pos*/) /*!< PMU OVSSET: Event Counter 0 Overflow Set Mask */ + +#define PMU_OVSSET_CNT1_STATUS_Pos 1U /*!< PMU OVSSET: Event Counter 1 Overflow Set Position */ +#define PMU_OVSSET_CNT1_STATUS_Msk (1UL << PMU_OVSSET_CNT1_STATUS_Pos) /*!< PMU OVSSET: Event Counter 1 Overflow Set Mask */ + +#define PMU_OVSSET_CNT2_STATUS_Pos 2U /*!< PMU OVSSET: Event Counter 2 Overflow Set Position */ +#define PMU_OVSSET_CNT2_STATUS_Msk (1UL << PMU_OVSSET_CNT2_STATUS_Pos) /*!< PMU OVSSET: Event Counter 2 Overflow Set Mask */ + +#define PMU_OVSSET_CNT3_STATUS_Pos 3U /*!< PMU OVSSET: Event Counter 3 Overflow Set Position */ +#define PMU_OVSSET_CNT3_STATUS_Msk (1UL << PMU_OVSSET_CNT3_STATUS_Pos) /*!< PMU OVSSET: Event Counter 3 Overflow Set Mask */ + +#define PMU_OVSSET_CNT4_STATUS_Pos 4U /*!< PMU OVSSET: Event Counter 4 Overflow Set Position */ +#define PMU_OVSSET_CNT4_STATUS_Msk (1UL << PMU_OVSSET_CNT4_STATUS_Pos) /*!< PMU OVSSET: Event Counter 4 Overflow Set Mask */ + +#define PMU_OVSSET_CNT5_STATUS_Pos 5U /*!< PMU OVSSET: Event Counter 5 Overflow Set Position */ +#define PMU_OVSSET_CNT5_STATUS_Msk (1UL << PMU_OVSSET_CNT5_STATUS_Pos) /*!< PMU OVSSET: Event Counter 5 Overflow Set Mask */ + +#define PMU_OVSSET_CNT6_STATUS_Pos 6U /*!< PMU OVSSET: Event Counter 6 Overflow Set Position */ +#define PMU_OVSSET_CNT6_STATUS_Msk (1UL << PMU_OVSSET_CNT6_STATUS_Pos) /*!< PMU OVSSET: Event Counter 6 Overflow Set Mask */ + +#define PMU_OVSSET_CNT7_STATUS_Pos 7U /*!< PMU OVSSET: Event Counter 7 Overflow Set Position */ +#define PMU_OVSSET_CNT7_STATUS_Msk (1UL << PMU_OVSSET_CNT7_STATUS_Pos) /*!< PMU OVSSET: Event Counter 7 Overflow Set Mask */ + +#define PMU_OVSSET_CNT8_STATUS_Pos 8U /*!< PMU OVSSET: Event Counter 8 Overflow Set Position */ +#define PMU_OVSSET_CNT8_STATUS_Msk (1UL << PMU_OVSSET_CNT8_STATUS_Pos) /*!< PMU OVSSET: Event Counter 8 Overflow Set Mask */ + +#define PMU_OVSSET_CNT9_STATUS_Pos 9U /*!< PMU OVSSET: Event Counter 9 Overflow Set Position */ +#define PMU_OVSSET_CNT9_STATUS_Msk (1UL << PMU_OVSSET_CNT9_STATUS_Pos) /*!< PMU OVSSET: Event Counter 9 Overflow Set Mask */ + +#define PMU_OVSSET_CNT10_STATUS_Pos 10U /*!< PMU OVSSET: Event Counter 10 Overflow Set Position */ +#define PMU_OVSSET_CNT10_STATUS_Msk (1UL << PMU_OVSSET_CNT10_STATUS_Pos) /*!< PMU OVSSET: Event Counter 10 Overflow Set Mask */ + +#define PMU_OVSSET_CNT11_STATUS_Pos 11U /*!< PMU OVSSET: Event Counter 11 Overflow Set Position */ +#define PMU_OVSSET_CNT11_STATUS_Msk (1UL << PMU_OVSSET_CNT11_STATUS_Pos) /*!< PMU OVSSET: Event Counter 11 Overflow Set Mask */ + +#define PMU_OVSSET_CNT12_STATUS_Pos 12U /*!< PMU OVSSET: Event Counter 12 Overflow Set Position */ +#define PMU_OVSSET_CNT12_STATUS_Msk (1UL << PMU_OVSSET_CNT12_STATUS_Pos) /*!< PMU OVSSET: Event Counter 12 Overflow Set Mask */ + +#define PMU_OVSSET_CNT13_STATUS_Pos 13U /*!< PMU OVSSET: Event Counter 13 Overflow Set Position */ +#define PMU_OVSSET_CNT13_STATUS_Msk (1UL << PMU_OVSSET_CNT13_STATUS_Pos) /*!< PMU OVSSET: Event Counter 13 Overflow Set Mask */ + +#define PMU_OVSSET_CNT14_STATUS_Pos 14U /*!< PMU OVSSET: Event Counter 14 Overflow Set Position */ +#define PMU_OVSSET_CNT14_STATUS_Msk (1UL << PMU_OVSSET_CNT14_STATUS_Pos) /*!< PMU OVSSET: Event Counter 14 Overflow Set Mask */ + +#define PMU_OVSSET_CNT15_STATUS_Pos 15U /*!< PMU OVSSET: Event Counter 15 Overflow Set Position */ +#define PMU_OVSSET_CNT15_STATUS_Msk (1UL << PMU_OVSSET_CNT15_STATUS_Pos) /*!< PMU OVSSET: Event Counter 15 Overflow Set Mask */ + +#define PMU_OVSSET_CNT16_STATUS_Pos 16U /*!< PMU OVSSET: Event Counter 16 Overflow Set Position */ +#define PMU_OVSSET_CNT16_STATUS_Msk (1UL << PMU_OVSSET_CNT16_STATUS_Pos) /*!< PMU OVSSET: Event Counter 16 Overflow Set Mask */ + +#define PMU_OVSSET_CNT17_STATUS_Pos 17U /*!< PMU OVSSET: Event Counter 17 Overflow Set Position */ +#define PMU_OVSSET_CNT17_STATUS_Msk (1UL << PMU_OVSSET_CNT17_STATUS_Pos) /*!< PMU OVSSET: Event Counter 17 Overflow Set Mask */ + +#define PMU_OVSSET_CNT18_STATUS_Pos 18U /*!< PMU OVSSET: Event Counter 18 Overflow Set Position */ +#define PMU_OVSSET_CNT18_STATUS_Msk (1UL << PMU_OVSSET_CNT18_STATUS_Pos) /*!< PMU OVSSET: Event Counter 18 Overflow Set Mask */ + +#define PMU_OVSSET_CNT19_STATUS_Pos 19U /*!< PMU OVSSET: Event Counter 19 Overflow Set Position */ +#define PMU_OVSSET_CNT19_STATUS_Msk (1UL << PMU_OVSSET_CNT19_STATUS_Pos) /*!< PMU OVSSET: Event Counter 19 Overflow Set Mask */ + +#define PMU_OVSSET_CNT20_STATUS_Pos 20U /*!< PMU OVSSET: Event Counter 20 Overflow Set Position */ +#define PMU_OVSSET_CNT20_STATUS_Msk (1UL << PMU_OVSSET_CNT20_STATUS_Pos) /*!< PMU OVSSET: Event Counter 20 Overflow Set Mask */ + +#define PMU_OVSSET_CNT21_STATUS_Pos 21U /*!< PMU OVSSET: Event Counter 21 Overflow Set Position */ +#define PMU_OVSSET_CNT21_STATUS_Msk (1UL << PMU_OVSSET_CNT21_STATUS_Pos) /*!< PMU OVSSET: Event Counter 21 Overflow Set Mask */ + +#define PMU_OVSSET_CNT22_STATUS_Pos 22U /*!< PMU OVSSET: Event Counter 22 Overflow Set Position */ +#define PMU_OVSSET_CNT22_STATUS_Msk (1UL << PMU_OVSSET_CNT22_STATUS_Pos) /*!< PMU OVSSET: Event Counter 22 Overflow Set Mask */ + +#define PMU_OVSSET_CNT23_STATUS_Pos 23U /*!< PMU OVSSET: Event Counter 23 Overflow Set Position */ +#define PMU_OVSSET_CNT23_STATUS_Msk (1UL << PMU_OVSSET_CNT23_STATUS_Pos) /*!< PMU OVSSET: Event Counter 23 Overflow Set Mask */ + +#define PMU_OVSSET_CNT24_STATUS_Pos 24U /*!< PMU OVSSET: Event Counter 24 Overflow Set Position */ +#define PMU_OVSSET_CNT24_STATUS_Msk (1UL << PMU_OVSSET_CNT24_STATUS_Pos) /*!< PMU OVSSET: Event Counter 24 Overflow Set Mask */ + +#define PMU_OVSSET_CNT25_STATUS_Pos 25U /*!< PMU OVSSET: Event Counter 25 Overflow Set Position */ +#define PMU_OVSSET_CNT25_STATUS_Msk (1UL << PMU_OVSSET_CNT25_STATUS_Pos) /*!< PMU OVSSET: Event Counter 25 Overflow Set Mask */ + +#define PMU_OVSSET_CNT26_STATUS_Pos 26U /*!< PMU OVSSET: Event Counter 26 Overflow Set Position */ +#define PMU_OVSSET_CNT26_STATUS_Msk (1UL << PMU_OVSSET_CNT26_STATUS_Pos) /*!< PMU OVSSET: Event Counter 26 Overflow Set Mask */ + +#define PMU_OVSSET_CNT27_STATUS_Pos 27U /*!< PMU OVSSET: Event Counter 27 Overflow Set Position */ +#define PMU_OVSSET_CNT27_STATUS_Msk (1UL << PMU_OVSSET_CNT27_STATUS_Pos) /*!< PMU OVSSET: Event Counter 27 Overflow Set Mask */ + +#define PMU_OVSSET_CNT28_STATUS_Pos 28U /*!< PMU OVSSET: Event Counter 28 Overflow Set Position */ +#define PMU_OVSSET_CNT28_STATUS_Msk (1UL << PMU_OVSSET_CNT28_STATUS_Pos) /*!< PMU OVSSET: Event Counter 28 Overflow Set Mask */ + +#define PMU_OVSSET_CNT29_STATUS_Pos 29U /*!< PMU OVSSET: Event Counter 29 Overflow Set Position */ +#define PMU_OVSSET_CNT29_STATUS_Msk (1UL << PMU_OVSSET_CNT29_STATUS_Pos) /*!< PMU OVSSET: Event Counter 29 Overflow Set Mask */ + +#define PMU_OVSSET_CNT30_STATUS_Pos 30U /*!< PMU OVSSET: Event Counter 30 Overflow Set Position */ +#define PMU_OVSSET_CNT30_STATUS_Msk (1UL << PMU_OVSSET_CNT30_STATUS_Pos) /*!< PMU OVSSET: Event Counter 30 Overflow Set Mask */ + +#define PMU_OVSSET_CYCCNT_STATUS_Pos 31U /*!< PMU OVSSET: Cycle Counter Overflow Set Position */ +#define PMU_OVSSET_CYCCNT_STATUS_Msk (1UL << PMU_OVSSET_CYCCNT_STATUS_Pos) /*!< PMU OVSSET: Cycle Counter Overflow Set Mask */ + +/** \brief PMU Overflow Flag Status Clear Register Definitions */ + +#define PMU_OVSCLR_CNT0_STATUS_Pos 0U /*!< PMU OVSCLR: Event Counter 0 Overflow Clear Position */ +#define PMU_OVSCLR_CNT0_STATUS_Msk (1UL /*<< PMU_OVSCLR_CNT0_STATUS_Pos*/) /*!< PMU OVSCLR: Event Counter 0 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT1_STATUS_Pos 1U /*!< PMU OVSCLR: Event Counter 1 Overflow Clear Position */ +#define PMU_OVSCLR_CNT1_STATUS_Msk (1UL << PMU_OVSCLR_CNT1_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 1 Overflow Clear */ + +#define PMU_OVSCLR_CNT2_STATUS_Pos 2U /*!< PMU OVSCLR: Event Counter 2 Overflow Clear Position */ +#define PMU_OVSCLR_CNT2_STATUS_Msk (1UL << PMU_OVSCLR_CNT2_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 2 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT3_STATUS_Pos 3U /*!< PMU OVSCLR: Event Counter 3 Overflow Clear Position */ +#define PMU_OVSCLR_CNT3_STATUS_Msk (1UL << PMU_OVSCLR_CNT3_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 3 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT4_STATUS_Pos 4U /*!< PMU OVSCLR: Event Counter 4 Overflow Clear Position */ +#define PMU_OVSCLR_CNT4_STATUS_Msk (1UL << PMU_OVSCLR_CNT4_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 4 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT5_STATUS_Pos 5U /*!< PMU OVSCLR: Event Counter 5 Overflow Clear Position */ +#define PMU_OVSCLR_CNT5_STATUS_Msk (1UL << PMU_OVSCLR_CNT5_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 5 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT6_STATUS_Pos 6U /*!< PMU OVSCLR: Event Counter 6 Overflow Clear Position */ +#define PMU_OVSCLR_CNT6_STATUS_Msk (1UL << PMU_OVSCLR_CNT6_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 6 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT7_STATUS_Pos 7U /*!< PMU OVSCLR: Event Counter 7 Overflow Clear Position */ +#define PMU_OVSCLR_CNT7_STATUS_Msk (1UL << PMU_OVSCLR_CNT7_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 7 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT8_STATUS_Pos 8U /*!< PMU OVSCLR: Event Counter 8 Overflow Clear Position */ +#define PMU_OVSCLR_CNT8_STATUS_Msk (1UL << PMU_OVSCLR_CNT8_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 8 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT9_STATUS_Pos 9U /*!< PMU OVSCLR: Event Counter 9 Overflow Clear Position */ +#define PMU_OVSCLR_CNT9_STATUS_Msk (1UL << PMU_OVSCLR_CNT9_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 9 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT10_STATUS_Pos 10U /*!< PMU OVSCLR: Event Counter 10 Overflow Clear Position */ +#define PMU_OVSCLR_CNT10_STATUS_Msk (1UL << PMU_OVSCLR_CNT10_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 10 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT11_STATUS_Pos 11U /*!< PMU OVSCLR: Event Counter 11 Overflow Clear Position */ +#define PMU_OVSCLR_CNT11_STATUS_Msk (1UL << PMU_OVSCLR_CNT11_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 11 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT12_STATUS_Pos 12U /*!< PMU OVSCLR: Event Counter 12 Overflow Clear Position */ +#define PMU_OVSCLR_CNT12_STATUS_Msk (1UL << PMU_OVSCLR_CNT12_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 12 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT13_STATUS_Pos 13U /*!< PMU OVSCLR: Event Counter 13 Overflow Clear Position */ +#define PMU_OVSCLR_CNT13_STATUS_Msk (1UL << PMU_OVSCLR_CNT13_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 13 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT14_STATUS_Pos 14U /*!< PMU OVSCLR: Event Counter 14 Overflow Clear Position */ +#define PMU_OVSCLR_CNT14_STATUS_Msk (1UL << PMU_OVSCLR_CNT14_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 14 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT15_STATUS_Pos 15U /*!< PMU OVSCLR: Event Counter 15 Overflow Clear Position */ +#define PMU_OVSCLR_CNT15_STATUS_Msk (1UL << PMU_OVSCLR_CNT15_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 15 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT16_STATUS_Pos 16U /*!< PMU OVSCLR: Event Counter 16 Overflow Clear Position */ +#define PMU_OVSCLR_CNT16_STATUS_Msk (1UL << PMU_OVSCLR_CNT16_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 16 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT17_STATUS_Pos 17U /*!< PMU OVSCLR: Event Counter 17 Overflow Clear Position */ +#define PMU_OVSCLR_CNT17_STATUS_Msk (1UL << PMU_OVSCLR_CNT17_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 17 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT18_STATUS_Pos 18U /*!< PMU OVSCLR: Event Counter 18 Overflow Clear Position */ +#define PMU_OVSCLR_CNT18_STATUS_Msk (1UL << PMU_OVSCLR_CNT18_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 18 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT19_STATUS_Pos 19U /*!< PMU OVSCLR: Event Counter 19 Overflow Clear Position */ +#define PMU_OVSCLR_CNT19_STATUS_Msk (1UL << PMU_OVSCLR_CNT19_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 19 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT20_STATUS_Pos 20U /*!< PMU OVSCLR: Event Counter 20 Overflow Clear Position */ +#define PMU_OVSCLR_CNT20_STATUS_Msk (1UL << PMU_OVSCLR_CNT20_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 20 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT21_STATUS_Pos 21U /*!< PMU OVSCLR: Event Counter 21 Overflow Clear Position */ +#define PMU_OVSCLR_CNT21_STATUS_Msk (1UL << PMU_OVSCLR_CNT21_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 21 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT22_STATUS_Pos 22U /*!< PMU OVSCLR: Event Counter 22 Overflow Clear Position */ +#define PMU_OVSCLR_CNT22_STATUS_Msk (1UL << PMU_OVSCLR_CNT22_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 22 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT23_STATUS_Pos 23U /*!< PMU OVSCLR: Event Counter 23 Overflow Clear Position */ +#define PMU_OVSCLR_CNT23_STATUS_Msk (1UL << PMU_OVSCLR_CNT23_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 23 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT24_STATUS_Pos 24U /*!< PMU OVSCLR: Event Counter 24 Overflow Clear Position */ +#define PMU_OVSCLR_CNT24_STATUS_Msk (1UL << PMU_OVSCLR_CNT24_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 24 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT25_STATUS_Pos 25U /*!< PMU OVSCLR: Event Counter 25 Overflow Clear Position */ +#define PMU_OVSCLR_CNT25_STATUS_Msk (1UL << PMU_OVSCLR_CNT25_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 25 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT26_STATUS_Pos 26U /*!< PMU OVSCLR: Event Counter 26 Overflow Clear Position */ +#define PMU_OVSCLR_CNT26_STATUS_Msk (1UL << PMU_OVSCLR_CNT26_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 26 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT27_STATUS_Pos 27U /*!< PMU OVSCLR: Event Counter 27 Overflow Clear Position */ +#define PMU_OVSCLR_CNT27_STATUS_Msk (1UL << PMU_OVSCLR_CNT27_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 27 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT28_STATUS_Pos 28U /*!< PMU OVSCLR: Event Counter 28 Overflow Clear Position */ +#define PMU_OVSCLR_CNT28_STATUS_Msk (1UL << PMU_OVSCLR_CNT28_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 28 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT29_STATUS_Pos 29U /*!< PMU OVSCLR: Event Counter 29 Overflow Clear Position */ +#define PMU_OVSCLR_CNT29_STATUS_Msk (1UL << PMU_OVSCLR_CNT29_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 29 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT30_STATUS_Pos 30U /*!< PMU OVSCLR: Event Counter 30 Overflow Clear Position */ +#define PMU_OVSCLR_CNT30_STATUS_Msk (1UL << PMU_OVSCLR_CNT30_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 30 Overflow Clear Mask */ + +#define PMU_OVSCLR_CYCCNT_STATUS_Pos 31U /*!< PMU OVSCLR: Cycle Counter Overflow Clear Position */ +#define PMU_OVSCLR_CYCCNT_STATUS_Msk (1UL << PMU_OVSCLR_CYCCNT_STATUS_Pos) /*!< PMU OVSCLR: Cycle Counter Overflow Clear Mask */ + +/** \brief PMU Software Increment Counter */ + +#define PMU_SWINC_CNT0_Pos 0U /*!< PMU SWINC: Event Counter 0 Software Increment Position */ +#define PMU_SWINC_CNT0_Msk (1UL /*<< PMU_SWINC_CNT0_Pos */) /*!< PMU SWINC: Event Counter 0 Software Increment Mask */ + +#define PMU_SWINC_CNT1_Pos 1U /*!< PMU SWINC: Event Counter 1 Software Increment Position */ +#define PMU_SWINC_CNT1_Msk (1UL << PMU_SWINC_CNT1_Pos) /*!< PMU SWINC: Event Counter 1 Software Increment Mask */ + +#define PMU_SWINC_CNT2_Pos 2U /*!< PMU SWINC: Event Counter 2 Software Increment Position */ +#define PMU_SWINC_CNT2_Msk (1UL << PMU_SWINC_CNT2_Pos) /*!< PMU SWINC: Event Counter 2 Software Increment Mask */ + +#define PMU_SWINC_CNT3_Pos 3U /*!< PMU SWINC: Event Counter 3 Software Increment Position */ +#define PMU_SWINC_CNT3_Msk (1UL << PMU_SWINC_CNT3_Pos) /*!< PMU SWINC: Event Counter 3 Software Increment Mask */ + +#define PMU_SWINC_CNT4_Pos 4U /*!< PMU SWINC: Event Counter 4 Software Increment Position */ +#define PMU_SWINC_CNT4_Msk (1UL << PMU_SWINC_CNT4_Pos) /*!< PMU SWINC: Event Counter 4 Software Increment Mask */ + +#define PMU_SWINC_CNT5_Pos 5U /*!< PMU SWINC: Event Counter 5 Software Increment Position */ +#define PMU_SWINC_CNT5_Msk (1UL << PMU_SWINC_CNT5_Pos) /*!< PMU SWINC: Event Counter 5 Software Increment Mask */ + +#define PMU_SWINC_CNT6_Pos 6U /*!< PMU SWINC: Event Counter 6 Software Increment Position */ +#define PMU_SWINC_CNT6_Msk (1UL << PMU_SWINC_CNT6_Pos) /*!< PMU SWINC: Event Counter 6 Software Increment Mask */ + +#define PMU_SWINC_CNT7_Pos 7U /*!< PMU SWINC: Event Counter 7 Software Increment Position */ +#define PMU_SWINC_CNT7_Msk (1UL << PMU_SWINC_CNT7_Pos) /*!< PMU SWINC: Event Counter 7 Software Increment Mask */ + +#define PMU_SWINC_CNT8_Pos 8U /*!< PMU SWINC: Event Counter 8 Software Increment Position */ +#define PMU_SWINC_CNT8_Msk (1UL << PMU_SWINC_CNT8_Pos) /*!< PMU SWINC: Event Counter 8 Software Increment Mask */ + +#define PMU_SWINC_CNT9_Pos 9U /*!< PMU SWINC: Event Counter 9 Software Increment Position */ +#define PMU_SWINC_CNT9_Msk (1UL << PMU_SWINC_CNT9_Pos) /*!< PMU SWINC: Event Counter 9 Software Increment Mask */ + +#define PMU_SWINC_CNT10_Pos 10U /*!< PMU SWINC: Event Counter 10 Software Increment Position */ +#define PMU_SWINC_CNT10_Msk (1UL << PMU_SWINC_CNT10_Pos) /*!< PMU SWINC: Event Counter 10 Software Increment Mask */ + +#define PMU_SWINC_CNT11_Pos 11U /*!< PMU SWINC: Event Counter 11 Software Increment Position */ +#define PMU_SWINC_CNT11_Msk (1UL << PMU_SWINC_CNT11_Pos) /*!< PMU SWINC: Event Counter 11 Software Increment Mask */ + +#define PMU_SWINC_CNT12_Pos 12U /*!< PMU SWINC: Event Counter 12 Software Increment Position */ +#define PMU_SWINC_CNT12_Msk (1UL << PMU_SWINC_CNT12_Pos) /*!< PMU SWINC: Event Counter 12 Software Increment Mask */ + +#define PMU_SWINC_CNT13_Pos 13U /*!< PMU SWINC: Event Counter 13 Software Increment Position */ +#define PMU_SWINC_CNT13_Msk (1UL << PMU_SWINC_CNT13_Pos) /*!< PMU SWINC: Event Counter 13 Software Increment Mask */ + +#define PMU_SWINC_CNT14_Pos 14U /*!< PMU SWINC: Event Counter 14 Software Increment Position */ +#define PMU_SWINC_CNT14_Msk (1UL << PMU_SWINC_CNT14_Pos) /*!< PMU SWINC: Event Counter 14 Software Increment Mask */ + +#define PMU_SWINC_CNT15_Pos 15U /*!< PMU SWINC: Event Counter 15 Software Increment Position */ +#define PMU_SWINC_CNT15_Msk (1UL << PMU_SWINC_CNT15_Pos) /*!< PMU SWINC: Event Counter 15 Software Increment Mask */ + +#define PMU_SWINC_CNT16_Pos 16U /*!< PMU SWINC: Event Counter 16 Software Increment Position */ +#define PMU_SWINC_CNT16_Msk (1UL << PMU_SWINC_CNT16_Pos) /*!< PMU SWINC: Event Counter 16 Software Increment Mask */ + +#define PMU_SWINC_CNT17_Pos 17U /*!< PMU SWINC: Event Counter 17 Software Increment Position */ +#define PMU_SWINC_CNT17_Msk (1UL << PMU_SWINC_CNT17_Pos) /*!< PMU SWINC: Event Counter 17 Software Increment Mask */ + +#define PMU_SWINC_CNT18_Pos 18U /*!< PMU SWINC: Event Counter 18 Software Increment Position */ +#define PMU_SWINC_CNT18_Msk (1UL << PMU_SWINC_CNT18_Pos) /*!< PMU SWINC: Event Counter 18 Software Increment Mask */ + +#define PMU_SWINC_CNT19_Pos 19U /*!< PMU SWINC: Event Counter 19 Software Increment Position */ +#define PMU_SWINC_CNT19_Msk (1UL << PMU_SWINC_CNT19_Pos) /*!< PMU SWINC: Event Counter 19 Software Increment Mask */ + +#define PMU_SWINC_CNT20_Pos 20U /*!< PMU SWINC: Event Counter 20 Software Increment Position */ +#define PMU_SWINC_CNT20_Msk (1UL << PMU_SWINC_CNT20_Pos) /*!< PMU SWINC: Event Counter 20 Software Increment Mask */ + +#define PMU_SWINC_CNT21_Pos 21U /*!< PMU SWINC: Event Counter 21 Software Increment Position */ +#define PMU_SWINC_CNT21_Msk (1UL << PMU_SWINC_CNT21_Pos) /*!< PMU SWINC: Event Counter 21 Software Increment Mask */ + +#define PMU_SWINC_CNT22_Pos 22U /*!< PMU SWINC: Event Counter 22 Software Increment Position */ +#define PMU_SWINC_CNT22_Msk (1UL << PMU_SWINC_CNT22_Pos) /*!< PMU SWINC: Event Counter 22 Software Increment Mask */ + +#define PMU_SWINC_CNT23_Pos 23U /*!< PMU SWINC: Event Counter 23 Software Increment Position */ +#define PMU_SWINC_CNT23_Msk (1UL << PMU_SWINC_CNT23_Pos) /*!< PMU SWINC: Event Counter 23 Software Increment Mask */ + +#define PMU_SWINC_CNT24_Pos 24U /*!< PMU SWINC: Event Counter 24 Software Increment Position */ +#define PMU_SWINC_CNT24_Msk (1UL << PMU_SWINC_CNT24_Pos) /*!< PMU SWINC: Event Counter 24 Software Increment Mask */ + +#define PMU_SWINC_CNT25_Pos 25U /*!< PMU SWINC: Event Counter 25 Software Increment Position */ +#define PMU_SWINC_CNT25_Msk (1UL << PMU_SWINC_CNT25_Pos) /*!< PMU SWINC: Event Counter 25 Software Increment Mask */ + +#define PMU_SWINC_CNT26_Pos 26U /*!< PMU SWINC: Event Counter 26 Software Increment Position */ +#define PMU_SWINC_CNT26_Msk (1UL << PMU_SWINC_CNT26_Pos) /*!< PMU SWINC: Event Counter 26 Software Increment Mask */ + +#define PMU_SWINC_CNT27_Pos 27U /*!< PMU SWINC: Event Counter 27 Software Increment Position */ +#define PMU_SWINC_CNT27_Msk (1UL << PMU_SWINC_CNT27_Pos) /*!< PMU SWINC: Event Counter 27 Software Increment Mask */ + +#define PMU_SWINC_CNT28_Pos 28U /*!< PMU SWINC: Event Counter 28 Software Increment Position */ +#define PMU_SWINC_CNT28_Msk (1UL << PMU_SWINC_CNT28_Pos) /*!< PMU SWINC: Event Counter 28 Software Increment Mask */ + +#define PMU_SWINC_CNT29_Pos 29U /*!< PMU SWINC: Event Counter 29 Software Increment Position */ +#define PMU_SWINC_CNT29_Msk (1UL << PMU_SWINC_CNT29_Pos) /*!< PMU SWINC: Event Counter 29 Software Increment Mask */ + +#define PMU_SWINC_CNT30_Pos 30U /*!< PMU SWINC: Event Counter 30 Software Increment Position */ +#define PMU_SWINC_CNT30_Msk (1UL << PMU_SWINC_CNT30_Pos) /*!< PMU SWINC: Event Counter 30 Software Increment Mask */ + +/** \brief PMU Control Register Definitions */ + +#define PMU_CTRL_ENABLE_Pos 0U /*!< PMU CTRL: ENABLE Position */ +#define PMU_CTRL_ENABLE_Msk (1UL /*<< PMU_CTRL_ENABLE_Pos*/) /*!< PMU CTRL: ENABLE Mask */ + +#define PMU_CTRL_EVENTCNT_RESET_Pos 1U /*!< PMU CTRL: Event Counter Reset Position */ +#define PMU_CTRL_EVENTCNT_RESET_Msk (1UL << PMU_CTRL_EVENTCNT_RESET_Pos) /*!< PMU CTRL: Event Counter Reset Mask */ + +#define PMU_CTRL_CYCCNT_RESET_Pos 2U /*!< PMU CTRL: Cycle Counter Reset Position */ +#define PMU_CTRL_CYCCNT_RESET_Msk (1UL << PMU_CTRL_CYCCNT_RESET_Pos) /*!< PMU CTRL: Cycle Counter Reset Mask */ + +#define PMU_CTRL_CYCCNT_DISABLE_Pos 5U /*!< PMU CTRL: Disable Cycle Counter Position */ +#define PMU_CTRL_CYCCNT_DISABLE_Msk (1UL << PMU_CTRL_CYCCNT_DISABLE_Pos) /*!< PMU CTRL: Disable Cycle Counter Mask */ + +#define PMU_CTRL_FRZ_ON_OV_Pos 9U /*!< PMU CTRL: Freeze-on-overflow Position */ +#define PMU_CTRL_FRZ_ON_OV_Msk (1UL << PMU_CTRL_FRZ_ON_OVERFLOW_Pos) /*!< PMU CTRL: Freeze-on-overflow Mask */ + +#define PMU_CTRL_TRACE_ON_OV_Pos 11U /*!< PMU CTRL: Trace-on-overflow Position */ +#define PMU_CTRL_TRACE_ON_OV_Msk (1UL << PMU_CTRL_TRACE_ON_OVERFLOW_Pos) /*!< PMU CTRL: Trace-on-overflow Mask */ + +/** \brief PMU Type Register Definitions */ + +#define PMU_TYPE_NUM_CNTS_Pos 0U /*!< PMU TYPE: Number of Counters Position */ +#define PMU_TYPE_NUM_CNTS_Msk (0xFFUL /*<< PMU_TYPE_NUM_CNTS_Pos*/) /*!< PMU TYPE: Number of Counters Mask */ + +#define PMU_TYPE_SIZE_CNTS_Pos 8U /*!< PMU TYPE: Size of Counters Position */ +#define PMU_TYPE_SIZE_CNTS_Msk (0x3FUL << PMU_TYPE_SIZE_CNTS_Pos) /*!< PMU TYPE: Size of Counters Mask */ + +#define PMU_TYPE_CYCCNT_PRESENT_Pos 14U /*!< PMU TYPE: Cycle Counter Present Position */ +#define PMU_TYPE_CYCCNT_PRESENT_Msk (1UL << PMU_TYPE_CYCCNT_PRESENT_Pos) /*!< PMU TYPE: Cycle Counter Present Mask */ + +#define PMU_TYPE_FRZ_OV_SUPPORT_Pos 21U /*!< PMU TYPE: Freeze-on-overflow Support Position */ +#define PMU_TYPE_FRZ_OV_SUPPORT_Msk (1UL << PMU_TYPE_FRZ_OV_SUPPORT_Pos) /*!< PMU TYPE: Freeze-on-overflow Support Mask */ + +#define PMU_TYPE_TRACE_ON_OV_SUPPORT_Pos 23U /*!< PMU TYPE: Trace-on-overflow Support Position */ +#define PMU_TYPE_TRACE_ON_OV_SUPPORT_Msk (1UL << PMU_TYPE_FRZ_OV_SUPPORT_Pos) /*!< PMU TYPE: Trace-on-overflow Support Mask */ + +/** \brief PMU Authentication Status Register Definitions */ + +#define PMU_AUTHSTATUS_NSID_Pos 0U /*!< PMU AUTHSTATUS: Non-secure Invasive Debug Position */ +#define PMU_AUTHSTATUS_NSID_Msk (0x3UL /*<< PMU_AUTHSTATUS_NSID_Pos*/) /*!< PMU AUTHSTATUS: Non-secure Invasive Debug Mask */ + +#define PMU_AUTHSTATUS_NSNID_Pos 2U /*!< PMU AUTHSTATUS: Non-secure Non-invasive Debug Position */ +#define PMU_AUTHSTATUS_NSNID_Msk (0x3UL << PMU_AUTHSTATUS_NSNID_Pos) /*!< PMU AUTHSTATUS: Non-secure Non-invasive Debug Mask */ + +#define PMU_AUTHSTATUS_SID_Pos 4U /*!< PMU AUTHSTATUS: Secure Invasive Debug Position */ +#define PMU_AUTHSTATUS_SID_Msk (0x3UL << PMU_AUTHSTATUS_SID_Pos) /*!< PMU AUTHSTATUS: Secure Invasive Debug Mask */ + +#define PMU_AUTHSTATUS_SNID_Pos 6U /*!< PMU AUTHSTATUS: Secure Non-invasive Debug Position */ +#define PMU_AUTHSTATUS_SNID_Msk (0x3UL << PMU_AUTHSTATUS_SNID_Pos) /*!< PMU AUTHSTATUS: Secure Non-invasive Debug Mask */ + +#define PMU_AUTHSTATUS_NSUID_Pos 16U /*!< PMU AUTHSTATUS: Non-secure Unprivileged Invasive Debug Position */ +#define PMU_AUTHSTATUS_NSUID_Msk (0x3UL << PMU_AUTHSTATUS_NSUID_Pos) /*!< PMU AUTHSTATUS: Non-secure Unprivileged Invasive Debug Mask */ + +#define PMU_AUTHSTATUS_NSUNID_Pos 18U /*!< PMU AUTHSTATUS: Non-secure Unprivileged Non-invasive Debug Position */ +#define PMU_AUTHSTATUS_NSUNID_Msk (0x3UL << PMU_AUTHSTATUS_NSUNID_Pos) /*!< PMU AUTHSTATUS: Non-secure Unprivileged Non-invasive Debug Mask */ + +#define PMU_AUTHSTATUS_SUID_Pos 20U /*!< PMU AUTHSTATUS: Secure Unprivileged Invasive Debug Position */ +#define PMU_AUTHSTATUS_SUID_Msk (0x3UL << PMU_AUTHSTATUS_SUID_Pos) /*!< PMU AUTHSTATUS: Secure Unprivileged Invasive Debug Mask */ + +#define PMU_AUTHSTATUS_SUNID_Pos 22U /*!< PMU AUTHSTATUS: Secure Unprivileged Non-invasive Debug Position */ +#define PMU_AUTHSTATUS_SUNID_Msk (0x3UL << PMU_AUTHSTATUS_SUNID_Pos) /*!< PMU AUTHSTATUS: Secure Unprivileged Non-invasive Debug Mask */ + + +/*@} end of group CMSIS_PMU */ +#endif + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */ + __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */ + __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */ + __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */ + uint32_t RESERVED0[1]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ +#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/* MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_PXN_Pos 4U /*!< MPU RLAR: PXN Position */ +#define MPU_RLAR_PXN_Msk (1UL << MPU_RLAR_PXN_Pos) /*!< MPU RLAR: PXN Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */ + +/* MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/* MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#else + uint32_t RESERVED0[3]; +#endif + __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */ +} SAU_Type; + +/* SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/* SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/* SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/* SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/* SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/* Secure Fault Status Register Definitions */ +#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */ +#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */ + +#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */ +#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */ + +#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */ +#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */ + +#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */ +#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */ + +#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */ +#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */ + +#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */ +#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */ + +#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */ +#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */ + +#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */ +#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and VFP Feature Register 2 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */ +#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */ + +#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */ +#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */ + +#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */ +#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */ + +#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */ +#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */ + +#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */ +#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */ + +#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */ +#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */ +#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */ +#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +#define FPU_FPDSCR_FZ16_Pos 19U /*!< FPDSCR: FZ16 bit Position */ +#define FPU_FPDSCR_FZ16_Msk (1UL << FPU_FPDSCR_FZ16_Pos) /*!< FPDSCR: FZ16 bit Mask */ + +#define FPU_FPDSCR_LTPSIZE_Pos 16U /*!< FPDSCR: LTPSIZE bit Position */ +#define FPU_FPDSCR_LTPSIZE_Msk (7UL << FPU_FPDSCR_LTPSIZE_Pos) /*!< FPDSCR: LTPSIZE bit Mask */ + +/* Media and VFP Feature Register 0 Definitions */ +#define FPU_MVFR0_FPRound_Pos 28U /*!< MVFR0: FPRound bits Position */ +#define FPU_MVFR0_FPRound_Msk (0xFUL << FPU_MVFR0_FPRound_Pos) /*!< MVFR0: FPRound bits Mask */ + +#define FPU_MVFR0_FPSqrt_Pos 20U /*!< MVFR0: FPSqrt bits Position */ +#define FPU_MVFR0_FPSqrt_Msk (0xFUL << FPU_MVFR0_FPSqrt_Pos) /*!< MVFR0: FPSqrt bits Mask */ + +#define FPU_MVFR0_FPDivide_Pos 16U /*!< MVFR0: FPDivide bits Position */ +#define FPU_MVFR0_FPDivide_Msk (0xFUL << FPU_MVFR0_FPDivide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FPDP_Pos 8U /*!< MVFR0: FPDP bits Position */ +#define FPU_MVFR0_FPDP_Msk (0xFUL << FPU_MVFR0_FPDP_Pos) /*!< MVFR0: FPDP bits Mask */ + +#define FPU_MVFR0_FPSP_Pos 4U /*!< MVFR0: FPSP bits Position */ +#define FPU_MVFR0_FPSP_Msk (0xFUL << FPU_MVFR0_FPSP_Pos) /*!< MVFR0: FPSP bits Mask */ + +#define FPU_MVFR0_SIMDReg_Pos 0U /*!< MVFR0: SIMDReg bits Position */ +#define FPU_MVFR0_SIMDReg_Msk (0xFUL /*<< FPU_MVFR0_SIMDReg_Pos*/) /*!< MVFR0: SIMDReg bits Mask */ + +/* Media and VFP Feature Register 1 Definitions */ +#define FPU_MVFR1_FMAC_Pos 28U /*!< MVFR1: FMAC bits Position */ +#define FPU_MVFR1_FMAC_Msk (0xFUL << FPU_MVFR1_FMAC_Pos) /*!< MVFR1: FMAC bits Mask */ + +#define FPU_MVFR1_FPHP_Pos 24U /*!< MVFR1: FPHP bits Position */ +#define FPU_MVFR1_FPHP_Msk (0xFUL << FPU_MVFR1_FPHP_Pos) /*!< MVFR1: FPHP bits Mask */ + +#define FPU_MVFR1_FP16_Pos 20U /*!< MVFR1: FP16 bits Position */ +#define FPU_MVFR1_FP16_Msk (0xFUL << FPU_MVFR1_FP16_Pos) /*!< MVFR1: FP16 bits Mask */ + +#define FPU_MVFR1_MVE_Pos 8U /*!< MVFR1: MVE bits Position */ +#define FPU_MVFR1_MVE_Msk (0xFUL << FPU_MVFR1_MVE_Pos) /*!< MVFR1: MVE bits Mask */ + +#define FPU_MVFR1_FPDNaN_Pos 4U /*!< MVFR1: FPDNaN bits Position */ +#define FPU_MVFR1_FPDNaN_Msk (0xFUL << FPU_MVFR1_FPDNaN_Pos) /*!< MVFR1: FPDNaN bits Mask */ + +#define FPU_MVFR1_FPFtZ_Pos 0U /*!< MVFR1: FPFtZ bits Position */ +#define FPU_MVFR1_FPFtZ_Msk (0xFUL /*<< FPU_MVFR1_FPFtZ_Pos*/) /*!< MVFR1: FPFtZ bits Mask */ + +/* Media and VFP Feature Register 2 Definitions */ +#define FPU_MVFR2_FPMisc_Pos 4U /*!< MVFR2: FPMisc bits Position */ +#define FPU_MVFR2_FPMisc_Msk (0xFUL << FPU_MVFR2_FPMisc_Pos) /*!< MVFR2: FPMisc bits Mask */ + +/*@} end of group CMSIS_FPU */ + +/* CoreDebug is deprecated. replaced by DCB (Debug Control Block) */ +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief \deprecated Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + __OM uint32_t DSCEMCR; /*!< Offset: 0x010 ( /W) Debug Set Clear Exception and Monitor Control Register */ + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< \deprecated CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< \deprecated CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Position */ +#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_FPD_Pos 23U /*!< \deprecated CoreDebug DHCSR: S_FPD Position */ +#define CoreDebug_DHCSR_S_FPD_Msk (1UL << CoreDebug_DHCSR_S_FPD_Pos) /*!< \deprecated CoreDebug DHCSR: S_FPD Mask */ + +#define CoreDebug_DHCSR_S_SUIDE_Pos 22U /*!< \deprecated CoreDebug DHCSR: S_SUIDE Position */ +#define CoreDebug_DHCSR_S_SUIDE_Msk (1UL << CoreDebug_DHCSR_S_SUIDE_Pos) /*!< \deprecated CoreDebug DHCSR: S_SUIDE Mask */ + +#define CoreDebug_DHCSR_S_NSUIDE_Pos 21U /*!< \deprecated CoreDebug DHCSR: S_NSUIDE Position */ +#define CoreDebug_DHCSR_S_NSUIDE_Msk (1UL << CoreDebug_DHCSR_S_NSUIDE_Pos) /*!< \deprecated CoreDebug DHCSR: S_NSUIDE Mask */ + +#define CoreDebug_DHCSR_S_SDE_Pos 20U /*!< \deprecated CoreDebug DHCSR: S_SDE Position */ +#define CoreDebug_DHCSR_S_SDE_Msk (1UL << CoreDebug_DHCSR_S_SDE_Pos) /*!< \deprecated CoreDebug DHCSR: S_SDE Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< \deprecated CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< \deprecated CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< \deprecated CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< \deprecated CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< \deprecated CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_PMOV_Pos 6U /*!< \deprecated CoreDebug DHCSR: C_PMOV Position */ +#define CoreDebug_DHCSR_C_PMOV_Msk (1UL << CoreDebug_DHCSR_C_PMOV_Pos) /*!< \deprecated CoreDebug DHCSR: C_PMOV Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< \deprecated CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< \deprecated CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< \deprecated CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< \deprecated CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< \deprecated CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< \deprecated CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< \deprecated CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< \deprecated CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< \deprecated CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< \deprecated CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< \deprecated CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< \deprecated CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< \deprecated CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< \deprecated CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< \deprecated CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< \deprecated CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< \deprecated CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< \deprecated CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< \deprecated CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< \deprecated CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< \deprecated CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< \deprecated CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< \deprecated CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< \deprecated CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< \deprecated CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Mask */ + +/* Debug Set Clear Exception and Monitor Control Register Definitions */ +#define CoreDebug_DSCEMCR_CLR_MON_REQ_Pos 19U /*!< \deprecated CoreDebug DSCEMCR: CLR_MON_REQ, Position */ +#define CoreDebug_DSCEMCR_CLR_MON_REQ_Msk (1UL << CoreDebug_DSCEMCR_CLR_MON_REQ_Pos) /*!< \deprecated CoreDebug DSCEMCR: CLR_MON_REQ, Mask */ + +#define CoreDebug_DSCEMCR_CLR_MON_PEND_Pos 17U /*!< \deprecated CoreDebug DSCEMCR: CLR_MON_PEND, Position */ +#define CoreDebug_DSCEMCR_CLR_MON_PEND_Msk (1UL << CoreDebug_DSCEMCR_CLR_MON_PEND_Pos) /*!< \deprecated CoreDebug DSCEMCR: CLR_MON_PEND, Mask */ + +#define CoreDebug_DSCEMCR_SET_MON_REQ_Pos 3U /*!< \deprecated CoreDebug DSCEMCR: SET_MON_REQ, Position */ +#define CoreDebug_DSCEMCR_SET_MON_REQ_Msk (1UL << CoreDebug_DSCEMCR_SET_MON_REQ_Pos) /*!< \deprecated CoreDebug DSCEMCR: SET_MON_REQ, Mask */ + +#define CoreDebug_DSCEMCR_SET_MON_PEND_Pos 1U /*!< \deprecated CoreDebug DSCEMCR: SET_MON_PEND, Position */ +#define CoreDebug_DSCEMCR_SET_MON_PEND_Msk (1UL << CoreDebug_DSCEMCR_SET_MON_PEND_Pos) /*!< \deprecated CoreDebug DSCEMCR: SET_MON_PEND, Mask */ + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_UIDEN_Pos 10U /*!< \deprecated CoreDebug DAUTHCTRL: UIDEN, Position */ +#define CoreDebug_DAUTHCTRL_UIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_UIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: UIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_UIDAPEN_Pos 9U /*!< \deprecated CoreDebug DAUTHCTRL: UIDAPEN, Position */ +#define CoreDebug_DAUTHCTRL_UIDAPEN_Msk (1UL << CoreDebug_DAUTHCTRL_UIDAPEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: UIDAPEN, Mask */ + +#define CoreDebug_DAUTHCTRL_FSDMA_Pos 8U /*!< \deprecated CoreDebug DAUTHCTRL: FSDMA, Position */ +#define CoreDebug_DAUTHCTRL_FSDMA_Msk (1UL << CoreDebug_DAUTHCTRL_FSDMA_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: FSDMA, Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Position */ +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Mask */ + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Mask */ + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos 16U /*!< \deprecated CoreDebug DSCSR: CDS Position */ +#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< \deprecated CoreDebug DSCSR: CDS Mask */ + +#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< \deprecated CoreDebug DSCSR: SBRSEL Position */ +#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< \deprecated CoreDebug DSCSR: SBRSEL Mask */ + +#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< \deprecated CoreDebug DSCSR: SBRSELEN Position */ +#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< \deprecated CoreDebug DSCSR: SBRSELEN Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DCB Debug Control Block + \brief Type definitions for the Debug Control Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Control Block Registers (DCB). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + __OM uint32_t DSCEMCR; /*!< Offset: 0x010 ( /W) Debug Set Clear Exception and Monitor Control Register */ + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} DCB_Type; + +/* DHCSR, Debug Halting Control and Status Register Definitions */ +#define DCB_DHCSR_DBGKEY_Pos 16U /*!< DCB DHCSR: Debug key Position */ +#define DCB_DHCSR_DBGKEY_Msk (0xFFFFUL << DCB_DHCSR_DBGKEY_Pos) /*!< DCB DHCSR: Debug key Mask */ + +#define DCB_DHCSR_S_RESTART_ST_Pos 26U /*!< DCB DHCSR: Restart sticky status Position */ +#define DCB_DHCSR_S_RESTART_ST_Msk (0x1UL << DCB_DHCSR_S_RESTART_ST_Pos) /*!< DCB DHCSR: Restart sticky status Mask */ + +#define DCB_DHCSR_S_RESET_ST_Pos 25U /*!< DCB DHCSR: Reset sticky status Position */ +#define DCB_DHCSR_S_RESET_ST_Msk (0x1UL << DCB_DHCSR_S_RESET_ST_Pos) /*!< DCB DHCSR: Reset sticky status Mask */ + +#define DCB_DHCSR_S_RETIRE_ST_Pos 24U /*!< DCB DHCSR: Retire sticky status Position */ +#define DCB_DHCSR_S_RETIRE_ST_Msk (0x1UL << DCB_DHCSR_S_RETIRE_ST_Pos) /*!< DCB DHCSR: Retire sticky status Mask */ + +#define DCB_DHCSR_S_FPD_Pos 23U /*!< DCB DHCSR: Floating-point registers Debuggable Position */ +#define DCB_DHCSR_S_FPD_Msk (0x1UL << DCB_DHCSR_S_FPD_Pos) /*!< DCB DHCSR: Floating-point registers Debuggable Mask */ + +#define DCB_DHCSR_S_SUIDE_Pos 22U /*!< DCB DHCSR: Secure unprivileged halting debug enabled Position */ +#define DCB_DHCSR_S_SUIDE_Msk (0x1UL << DCB_DHCSR_S_SUIDE_Pos) /*!< DCB DHCSR: Secure unprivileged halting debug enabled Mask */ + +#define DCB_DHCSR_S_NSUIDE_Pos 21U /*!< DCB DHCSR: Non-secure unprivileged halting debug enabled Position */ +#define DCB_DHCSR_S_NSUIDE_Msk (0x1UL << DCB_DHCSR_S_NSUIDE_Pos) /*!< DCB DHCSR: Non-secure unprivileged halting debug enabled Mask */ + +#define DCB_DHCSR_S_SDE_Pos 20U /*!< DCB DHCSR: Secure debug enabled Position */ +#define DCB_DHCSR_S_SDE_Msk (0x1UL << DCB_DHCSR_S_SDE_Pos) /*!< DCB DHCSR: Secure debug enabled Mask */ + +#define DCB_DHCSR_S_LOCKUP_Pos 19U /*!< DCB DHCSR: Lockup status Position */ +#define DCB_DHCSR_S_LOCKUP_Msk (0x1UL << DCB_DHCSR_S_LOCKUP_Pos) /*!< DCB DHCSR: Lockup status Mask */ + +#define DCB_DHCSR_S_SLEEP_Pos 18U /*!< DCB DHCSR: Sleeping status Position */ +#define DCB_DHCSR_S_SLEEP_Msk (0x1UL << DCB_DHCSR_S_SLEEP_Pos) /*!< DCB DHCSR: Sleeping status Mask */ + +#define DCB_DHCSR_S_HALT_Pos 17U /*!< DCB DHCSR: Halted status Position */ +#define DCB_DHCSR_S_HALT_Msk (0x1UL << DCB_DHCSR_S_HALT_Pos) /*!< DCB DHCSR: Halted status Mask */ + +#define DCB_DHCSR_S_REGRDY_Pos 16U /*!< DCB DHCSR: Register ready status Position */ +#define DCB_DHCSR_S_REGRDY_Msk (0x1UL << DCB_DHCSR_S_REGRDY_Pos) /*!< DCB DHCSR: Register ready status Mask */ + +#define DCB_DHCSR_C_PMOV_Pos 6U /*!< DCB DHCSR: Halt on PMU overflow control Position */ +#define DCB_DHCSR_C_PMOV_Msk (0x1UL << DCB_DHCSR_C_PMOV_Pos) /*!< DCB DHCSR: Halt on PMU overflow control Mask */ + +#define DCB_DHCSR_C_SNAPSTALL_Pos 5U /*!< DCB DHCSR: Snap stall control Position */ +#define DCB_DHCSR_C_SNAPSTALL_Msk (0x1UL << DCB_DHCSR_C_SNAPSTALL_Pos) /*!< DCB DHCSR: Snap stall control Mask */ + +#define DCB_DHCSR_C_MASKINTS_Pos 3U /*!< DCB DHCSR: Mask interrupts control Position */ +#define DCB_DHCSR_C_MASKINTS_Msk (0x1UL << DCB_DHCSR_C_MASKINTS_Pos) /*!< DCB DHCSR: Mask interrupts control Mask */ + +#define DCB_DHCSR_C_STEP_Pos 2U /*!< DCB DHCSR: Step control Position */ +#define DCB_DHCSR_C_STEP_Msk (0x1UL << DCB_DHCSR_C_STEP_Pos) /*!< DCB DHCSR: Step control Mask */ + +#define DCB_DHCSR_C_HALT_Pos 1U /*!< DCB DHCSR: Halt control Position */ +#define DCB_DHCSR_C_HALT_Msk (0x1UL << DCB_DHCSR_C_HALT_Pos) /*!< DCB DHCSR: Halt control Mask */ + +#define DCB_DHCSR_C_DEBUGEN_Pos 0U /*!< DCB DHCSR: Debug enable control Position */ +#define DCB_DHCSR_C_DEBUGEN_Msk (0x1UL /*<< DCB_DHCSR_C_DEBUGEN_Pos*/) /*!< DCB DHCSR: Debug enable control Mask */ + +/* DCRSR, Debug Core Register Select Register Definitions */ +#define DCB_DCRSR_REGWnR_Pos 16U /*!< DCB DCRSR: Register write/not-read Position */ +#define DCB_DCRSR_REGWnR_Msk (0x1UL << DCB_DCRSR_REGWnR_Pos) /*!< DCB DCRSR: Register write/not-read Mask */ + +#define DCB_DCRSR_REGSEL_Pos 0U /*!< DCB DCRSR: Register selector Position */ +#define DCB_DCRSR_REGSEL_Msk (0x7FUL /*<< DCB_DCRSR_REGSEL_Pos*/) /*!< DCB DCRSR: Register selector Mask */ + +/* DCRDR, Debug Core Register Data Register Definitions */ +#define DCB_DCRDR_DBGTMP_Pos 0U /*!< DCB DCRDR: Data temporary buffer Position */ +#define DCB_DCRDR_DBGTMP_Msk (0xFFFFFFFFUL /*<< DCB_DCRDR_DBGTMP_Pos*/) /*!< DCB DCRDR: Data temporary buffer Mask */ + +/* DEMCR, Debug Exception and Monitor Control Register Definitions */ +#define DCB_DEMCR_TRCENA_Pos 24U /*!< DCB DEMCR: Trace enable Position */ +#define DCB_DEMCR_TRCENA_Msk (0x1UL << DCB_DEMCR_TRCENA_Pos) /*!< DCB DEMCR: Trace enable Mask */ + +#define DCB_DEMCR_MONPRKEY_Pos 23U /*!< DCB DEMCR: Monitor pend req key Position */ +#define DCB_DEMCR_MONPRKEY_Msk (0x1UL << DCB_DEMCR_MONPRKEY_Pos) /*!< DCB DEMCR: Monitor pend req key Mask */ + +#define DCB_DEMCR_UMON_EN_Pos 21U /*!< DCB DEMCR: Unprivileged monitor enable Position */ +#define DCB_DEMCR_UMON_EN_Msk (0x1UL << DCB_DEMCR_UMON_EN_Pos) /*!< DCB DEMCR: Unprivileged monitor enable Mask */ + +#define DCB_DEMCR_SDME_Pos 20U /*!< DCB DEMCR: Secure DebugMonitor enable Position */ +#define DCB_DEMCR_SDME_Msk (0x1UL << DCB_DEMCR_SDME_Pos) /*!< DCB DEMCR: Secure DebugMonitor enable Mask */ + +#define DCB_DEMCR_MON_REQ_Pos 19U /*!< DCB DEMCR: Monitor request Position */ +#define DCB_DEMCR_MON_REQ_Msk (0x1UL << DCB_DEMCR_MON_REQ_Pos) /*!< DCB DEMCR: Monitor request Mask */ + +#define DCB_DEMCR_MON_STEP_Pos 18U /*!< DCB DEMCR: Monitor step Position */ +#define DCB_DEMCR_MON_STEP_Msk (0x1UL << DCB_DEMCR_MON_STEP_Pos) /*!< DCB DEMCR: Monitor step Mask */ + +#define DCB_DEMCR_MON_PEND_Pos 17U /*!< DCB DEMCR: Monitor pend Position */ +#define DCB_DEMCR_MON_PEND_Msk (0x1UL << DCB_DEMCR_MON_PEND_Pos) /*!< DCB DEMCR: Monitor pend Mask */ + +#define DCB_DEMCR_MON_EN_Pos 16U /*!< DCB DEMCR: Monitor enable Position */ +#define DCB_DEMCR_MON_EN_Msk (0x1UL << DCB_DEMCR_MON_EN_Pos) /*!< DCB DEMCR: Monitor enable Mask */ + +#define DCB_DEMCR_VC_SFERR_Pos 11U /*!< DCB DEMCR: Vector Catch SecureFault Position */ +#define DCB_DEMCR_VC_SFERR_Msk (0x1UL << DCB_DEMCR_VC_SFERR_Pos) /*!< DCB DEMCR: Vector Catch SecureFault Mask */ + +#define DCB_DEMCR_VC_HARDERR_Pos 10U /*!< DCB DEMCR: Vector Catch HardFault errors Position */ +#define DCB_DEMCR_VC_HARDERR_Msk (0x1UL << DCB_DEMCR_VC_HARDERR_Pos) /*!< DCB DEMCR: Vector Catch HardFault errors Mask */ + +#define DCB_DEMCR_VC_INTERR_Pos 9U /*!< DCB DEMCR: Vector Catch interrupt errors Position */ +#define DCB_DEMCR_VC_INTERR_Msk (0x1UL << DCB_DEMCR_VC_INTERR_Pos) /*!< DCB DEMCR: Vector Catch interrupt errors Mask */ + +#define DCB_DEMCR_VC_BUSERR_Pos 8U /*!< DCB DEMCR: Vector Catch BusFault errors Position */ +#define DCB_DEMCR_VC_BUSERR_Msk (0x1UL << DCB_DEMCR_VC_BUSERR_Pos) /*!< DCB DEMCR: Vector Catch BusFault errors Mask */ + +#define DCB_DEMCR_VC_STATERR_Pos 7U /*!< DCB DEMCR: Vector Catch state errors Position */ +#define DCB_DEMCR_VC_STATERR_Msk (0x1UL << DCB_DEMCR_VC_STATERR_Pos) /*!< DCB DEMCR: Vector Catch state errors Mask */ + +#define DCB_DEMCR_VC_CHKERR_Pos 6U /*!< DCB DEMCR: Vector Catch check errors Position */ +#define DCB_DEMCR_VC_CHKERR_Msk (0x1UL << DCB_DEMCR_VC_CHKERR_Pos) /*!< DCB DEMCR: Vector Catch check errors Mask */ + +#define DCB_DEMCR_VC_NOCPERR_Pos 5U /*!< DCB DEMCR: Vector Catch NOCP errors Position */ +#define DCB_DEMCR_VC_NOCPERR_Msk (0x1UL << DCB_DEMCR_VC_NOCPERR_Pos) /*!< DCB DEMCR: Vector Catch NOCP errors Mask */ + +#define DCB_DEMCR_VC_MMERR_Pos 4U /*!< DCB DEMCR: Vector Catch MemManage errors Position */ +#define DCB_DEMCR_VC_MMERR_Msk (0x1UL << DCB_DEMCR_VC_MMERR_Pos) /*!< DCB DEMCR: Vector Catch MemManage errors Mask */ + +#define DCB_DEMCR_VC_CORERESET_Pos 0U /*!< DCB DEMCR: Vector Catch Core reset Position */ +#define DCB_DEMCR_VC_CORERESET_Msk (0x1UL /*<< DCB_DEMCR_VC_CORERESET_Pos*/) /*!< DCB DEMCR: Vector Catch Core reset Mask */ + +/* DSCEMCR, Debug Set Clear Exception and Monitor Control Register Definitions */ +#define DCB_DSCEMCR_CLR_MON_REQ_Pos 19U /*!< DCB DSCEMCR: Clear monitor request Position */ +#define DCB_DSCEMCR_CLR_MON_REQ_Msk (0x1UL << DCB_DSCEMCR_CLR_MON_REQ_Pos) /*!< DCB DSCEMCR: Clear monitor request Mask */ + +#define DCB_DSCEMCR_CLR_MON_PEND_Pos 17U /*!< DCB DSCEMCR: Clear monitor pend Position */ +#define DCB_DSCEMCR_CLR_MON_PEND_Msk (0x1UL << DCB_DSCEMCR_CLR_MON_PEND_Pos) /*!< DCB DSCEMCR: Clear monitor pend Mask */ + +#define DCB_DSCEMCR_SET_MON_REQ_Pos 3U /*!< DCB DSCEMCR: Set monitor request Position */ +#define DCB_DSCEMCR_SET_MON_REQ_Msk (0x1UL << DCB_DSCEMCR_SET_MON_REQ_Pos) /*!< DCB DSCEMCR: Set monitor request Mask */ + +#define DCB_DSCEMCR_SET_MON_PEND_Pos 1U /*!< DCB DSCEMCR: Set monitor pend Position */ +#define DCB_DSCEMCR_SET_MON_PEND_Msk (0x1UL << DCB_DSCEMCR_SET_MON_PEND_Pos) /*!< DCB DSCEMCR: Set monitor pend Mask */ + +/* DAUTHCTRL, Debug Authentication Control Register Definitions */ +#define DCB_DAUTHCTRL_UIDEN_Pos 10U /*!< DCB DAUTHCTRL: Unprivileged Invasive Debug Enable Position */ +#define DCB_DAUTHCTRL_UIDEN_Msk (0x1UL << DCB_DAUTHCTRL_UIDEN_Pos) /*!< DCB DAUTHCTRL: Unprivileged Invasive Debug Enable Mask */ + +#define DCB_DAUTHCTRL_UIDAPEN_Pos 9U /*!< DCB DAUTHCTRL: Unprivileged Invasive DAP Access Enable Position */ +#define DCB_DAUTHCTRL_UIDAPEN_Msk (0x1UL << DCB_DAUTHCTRL_UIDAPEN_Pos) /*!< DCB DAUTHCTRL: Unprivileged Invasive DAP Access Enable Mask */ + +#define DCB_DAUTHCTRL_FSDMA_Pos 8U /*!< DCB DAUTHCTRL: Force Secure DebugMonitor Allowed Position */ +#define DCB_DAUTHCTRL_FSDMA_Msk (0x1UL << DCB_DAUTHCTRL_FSDMA_Pos) /*!< DCB DAUTHCTRL: Force Secure DebugMonitor Allowed Mask */ + +#define DCB_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPNIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPNIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPNIDENSEL_Msk (0x1UL << DCB_DAUTHCTRL_SPNIDENSEL_Pos) /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Mask */ + +#define DCB_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< DCB DAUTHCTRL: Secure invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPIDENSEL_Msk (0x1UL /*<< DCB_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< DCB DAUTHCTRL: Secure invasive debug enable select Mask */ + +/* DSCSR, Debug Security Control and Status Register Definitions */ +#define DCB_DSCSR_CDSKEY_Pos 17U /*!< DCB DSCSR: CDS write-enable key Position */ +#define DCB_DSCSR_CDSKEY_Msk (0x1UL << DCB_DSCSR_CDSKEY_Pos) /*!< DCB DSCSR: CDS write-enable key Mask */ + +#define DCB_DSCSR_CDS_Pos 16U /*!< DCB DSCSR: Current domain Secure Position */ +#define DCB_DSCSR_CDS_Msk (0x1UL << DCB_DSCSR_CDS_Pos) /*!< DCB DSCSR: Current domain Secure Mask */ + +#define DCB_DSCSR_SBRSEL_Pos 1U /*!< DCB DSCSR: Secure banked register select Position */ +#define DCB_DSCSR_SBRSEL_Msk (0x1UL << DCB_DSCSR_SBRSEL_Pos) /*!< DCB DSCSR: Secure banked register select Mask */ + +#define DCB_DSCSR_SBRSELEN_Pos 0U /*!< DCB DSCSR: Secure banked register select enable Position */ +#define DCB_DSCSR_SBRSELEN_Msk (0x1UL /*<< DCB_DSCSR_SBRSELEN_Pos*/) /*!< DCB DSCSR: Secure banked register select enable Mask */ + +/*@} end of group CMSIS_DCB */ + + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DIB Debug Identification Block + \brief Type definitions for the Debug Identification Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Identification Block Registers (DIB). + */ +typedef struct +{ + __OM uint32_t DLAR; /*!< Offset: 0x000 ( /W) SCS Software Lock Access Register */ + __IM uint32_t DLSR; /*!< Offset: 0x004 (R/ ) SCS Software Lock Status Register */ + __IM uint32_t DAUTHSTATUS; /*!< Offset: 0x008 (R/ ) Debug Authentication Status Register */ + __IM uint32_t DDEVARCH; /*!< Offset: 0x00C (R/ ) SCS Device Architecture Register */ + __IM uint32_t DDEVTYPE; /*!< Offset: 0x010 (R/ ) SCS Device Type Register */ +} DIB_Type; + +/* DLAR, SCS Software Lock Access Register Definitions */ +#define DIB_DLAR_KEY_Pos 0U /*!< DIB DLAR: KEY Position */ +#define DIB_DLAR_KEY_Msk (0xFFFFFFFFUL /*<< DIB_DLAR_KEY_Pos */) /*!< DIB DLAR: KEY Mask */ + +/* DLSR, SCS Software Lock Status Register Definitions */ +#define DIB_DLSR_nTT_Pos 2U /*!< DIB DLSR: Not thirty-two bit Position */ +#define DIB_DLSR_nTT_Msk (0x1UL << DIB_DLSR_nTT_Pos ) /*!< DIB DLSR: Not thirty-two bit Mask */ + +#define DIB_DLSR_SLK_Pos 1U /*!< DIB DLSR: Software Lock status Position */ +#define DIB_DLSR_SLK_Msk (0x1UL << DIB_DLSR_SLK_Pos ) /*!< DIB DLSR: Software Lock status Mask */ + +#define DIB_DLSR_SLI_Pos 0U /*!< DIB DLSR: Software Lock implemented Position */ +#define DIB_DLSR_SLI_Msk (0x1UL /*<< DIB_DLSR_SLI_Pos*/) /*!< DIB DLSR: Software Lock implemented Mask */ + +/* DAUTHSTATUS, Debug Authentication Status Register Definitions */ +#define DIB_DAUTHSTATUS_SUNID_Pos 22U /*!< DIB DAUTHSTATUS: Secure Unprivileged Non-invasive Debug Allowed Position */ +#define DIB_DAUTHSTATUS_SUNID_Msk (0x3UL << DIB_DAUTHSTATUS_SUNID_Pos ) /*!< DIB DAUTHSTATUS: Secure Unprivileged Non-invasive Debug Allowed Mask */ + +#define DIB_DAUTHSTATUS_SUID_Pos 20U /*!< DIB DAUTHSTATUS: Secure Unprivileged Invasive Debug Allowed Position */ +#define DIB_DAUTHSTATUS_SUID_Msk (0x3UL << DIB_DAUTHSTATUS_SUID_Pos ) /*!< DIB DAUTHSTATUS: Secure Unprivileged Invasive Debug Allowed Mask */ + +#define DIB_DAUTHSTATUS_NSUNID_Pos 18U /*!< DIB DAUTHSTATUS: Non-secure Unprivileged Non-invasive Debug Allo Position */ +#define DIB_DAUTHSTATUS_NSUNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSUNID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Unprivileged Non-invasive Debug Allo Mask */ + +#define DIB_DAUTHSTATUS_NSUID_Pos 16U /*!< DIB DAUTHSTATUS: Non-secure Unprivileged Invasive Debug Allowed Position */ +#define DIB_DAUTHSTATUS_NSUID_Msk (0x3UL << DIB_DAUTHSTATUS_NSUID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Unprivileged Invasive Debug Allowed Mask */ + +#define DIB_DAUTHSTATUS_SNID_Pos 6U /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_SNID_Msk (0x3UL << DIB_DAUTHSTATUS_SNID_Pos ) /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_SID_Pos 4U /*!< DIB DAUTHSTATUS: Secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_SID_Msk (0x3UL << DIB_DAUTHSTATUS_SID_Pos ) /*!< DIB DAUTHSTATUS: Secure Invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSNID_Pos 2U /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSNID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSID_Pos 0U /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSID_Msk (0x3UL /*<< DIB_DAUTHSTATUS_NSID_Pos*/) /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Mask */ + +/* DDEVARCH, SCS Device Architecture Register Definitions */ +#define DIB_DDEVARCH_ARCHITECT_Pos 21U /*!< DIB DDEVARCH: Architect Position */ +#define DIB_DDEVARCH_ARCHITECT_Msk (0x7FFUL << DIB_DDEVARCH_ARCHITECT_Pos ) /*!< DIB DDEVARCH: Architect Mask */ + +#define DIB_DDEVARCH_PRESENT_Pos 20U /*!< DIB DDEVARCH: DEVARCH Present Position */ +#define DIB_DDEVARCH_PRESENT_Msk (0x1FUL << DIB_DDEVARCH_PRESENT_Pos ) /*!< DIB DDEVARCH: DEVARCH Present Mask */ + +#define DIB_DDEVARCH_REVISION_Pos 16U /*!< DIB DDEVARCH: Revision Position */ +#define DIB_DDEVARCH_REVISION_Msk (0xFUL << DIB_DDEVARCH_REVISION_Pos ) /*!< DIB DDEVARCH: Revision Mask */ + +#define DIB_DDEVARCH_ARCHVER_Pos 12U /*!< DIB DDEVARCH: Architecture Version Position */ +#define DIB_DDEVARCH_ARCHVER_Msk (0xFUL << DIB_DDEVARCH_ARCHVER_Pos ) /*!< DIB DDEVARCH: Architecture Version Mask */ + +#define DIB_DDEVARCH_ARCHPART_Pos 0U /*!< DIB DDEVARCH: Architecture Part Position */ +#define DIB_DDEVARCH_ARCHPART_Msk (0xFFFUL /*<< DIB_DDEVARCH_ARCHPART_Pos*/) /*!< DIB DDEVARCH: Architecture Part Mask */ + +/* DDEVTYPE, SCS Device Type Register Definitions */ +#define DIB_DDEVTYPE_SUB_Pos 4U /*!< DIB DDEVTYPE: Sub-type Position */ +#define DIB_DDEVTYPE_SUB_Msk (0xFUL << DIB_DDEVTYPE_SUB_Pos ) /*!< DIB DDEVTYPE: Sub-type Mask */ + +#define DIB_DDEVTYPE_MAJOR_Pos 0U /*!< DIB DDEVTYPE: Major type Position */ +#define DIB_DDEVTYPE_MAJOR_Msk (0xFUL /*<< DIB_DDEVTYPE_MAJOR_Pos*/) /*!< DIB DDEVTYPE: Major type Mask */ + + +/*@} end of group CMSIS_DIB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define MEMSYSCTL_BASE (0xE001E000UL) /*!< Memory System Control Base Address */ + #define ERRBNK_BASE (0xE001E100UL) /*!< Error Banking Base Address */ + #define PWRMODCTL_BASE (0xE001E300UL) /*!< Power Mode Control Base Address */ + #define EWIC_BASE (0xE001E400UL) /*!< External Wakeup Interrupt Controller Base Address */ + #define PRCCFGINF_BASE (0xE001E700UL) /*!< Processor Configuration Information Base Address */ + #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ + #define CoreDebug_BASE (0xE000EDF0UL) /*!< \deprecated Core Debug Base Address */ + #define DCB_BASE (0xE000EDF0UL) /*!< DCB Base Address */ + #define DIB_BASE (0xE000EFB0UL) /*!< DIB Base Address */ + #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + #define ICB ((ICB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ + #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ + #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ + #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ + #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ + #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ + #define MEMSYSCTL ((MemSysCtl_Type *) MEMSYSCTL_BASE ) /*!< Memory System Control configuration struct */ + #define ERRBNK ((ErrBnk_Type *) ERRBNK_BASE ) /*!< Error Banking configuration struct */ + #define PWRMODCTL ((PwrModCtl_Type *) PWRMODCTL_BASE ) /*!< Power Mode Control configuration struct */ + #define EWIC ((EWIC_Type *) EWIC_BASE ) /*!< EWIC configuration struct */ + #define PRCCFGINF ((PrcCfgInf_Type *) PRCCFGINF_BASE ) /*!< Processor Configuration Information configuration struct */ + #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< \deprecated Core Debug configuration struct */ + #define DCB ((DCB_Type *) DCB_BASE ) /*!< DCB configuration struct */ + #define DIB ((DIB_Type *) DIB_BASE ) /*!< DIB configuration struct */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ + #endif + + #if defined (__PMU_PRESENT) && (__PMU_PRESENT == 1U) + #define PMU_BASE (0xE0003000UL) /*!< PMU Base Address */ + #define PMU ((PMU_Type *) PMU_BASE ) /*!< PMU configuration struct */ + #endif + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ + #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ + #endif + + #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ + #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ + #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< \deprecated Core Debug Base Address (non-secure address space) */ + #define DCB_BASE_NS (0xE002EDF0UL) /*!< DCB Base Address (non-secure address space) */ + #define DIB_BASE_NS (0xE002EFB0UL) /*!< DIB Base Address (non-secure address space) */ + #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ + #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ + #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + + #define ICB_NS ((ICB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */ + #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ + #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ + #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ + #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< \deprecated Core Debug configuration struct (non-secure address space) */ + #define DCB_NS ((DCB_Type *) DCB_BASE_NS ) /*!< DCB configuration struct (non-secure address space) */ + #define DIB_NS ((DIB_Type *) DIB_BASE_NS ) /*!< DIB configuration struct (non-secure address space) */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ + #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ + #endif + + #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */ + #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */ + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_register_aliases Backwards Compatibility Aliases + \brief Register alias definitions for backwards compatibility. + @{ + */ + +/*@} */ + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* Special LR values for Secure/Non-Secure call handling and exception handling */ + +/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ +#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ + +/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ +#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ +#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ +#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ +#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ +#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ +#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */ +#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ + +/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ +#else +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ +#endif + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + __DSB(); +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Priority Grouping (non-secure) + \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB_NS->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB_NS->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping (non-secure) + \details Reads the priority grouping field from the non-secure NVIC when in secure state. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void) +{ + return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv8.h" + +#endif + +/* ########################## PMU functions and events #################################### */ + +#if defined (__PMU_PRESENT) && (__PMU_PRESENT == 1U) + +#include "pmu_armv8.h" + +/** + \brief Cortex-M85 PMU events + \note Architectural PMU events can be found in pmu_armv8.h +*/ + +#define ARMCM85_PMU_ECC_ERR 0xC000 /*!< One or more Error Correcting Code (ECC) errors detected */ +#define ARMCM85_PMU_ECC_ERR_MBIT 0xC001 /*!< One or more multi-bit ECC errors detected */ +#define ARMCM85_PMU_ECC_ERR_DCACHE 0xC010 /*!< One or more ECC errors in the data cache */ +#define ARMCM85_PMU_ECC_ERR_ICACHE 0xC011 /*!< One or more ECC errors in the instruction cache */ +#define ARMCM85_PMU_ECC_ERR_MBIT_DCACHE 0xC012 /*!< One or more multi-bit ECC errors in the data cache */ +#define ARMCM85_PMU_ECC_ERR_MBIT_ICACHE 0xC013 /*!< One or more multi-bit ECC errors in the instruction cache */ +#define ARMCM85_PMU_ECC_ERR_DTCM 0xC020 /*!< One or more ECC errors in the Data Tightly Coupled Memory (DTCM) */ +#define ARMCM85_PMU_ECC_ERR_ITCM 0xC021 /*!< One or more ECC errors in the Instruction Tightly Coupled Memory (ITCM) */ +#define ARMCM85_PMU_ECC_ERR_MBIT_DTCM 0xC022 /*!< One or more multi-bit ECC errors in the DTCM */ +#define ARMCM85_PMU_ECC_ERR_MBIT_ITCM 0xC023 /*!< One or more multi-bit ECC errors in the ITCM */ +#define ARMCM85_PMU_PF_LINEFILL 0xC100 /*!< The prefetcher starts a line-fill */ +#define ARMCM85_PMU_PF_CANCEL 0xC101 /*!< The prefetcher stops prefetching */ +#define ARMCM85_PMU_PF_DROP_LINEFILL 0xC102 /*!< A linefill triggered by a prefetcher has been dropped because of lack of buffering */ +#define ARMCM85_PMU_NWAMODE_ENTER 0xC200 /*!< No write-allocate mode entry */ +#define ARMCM85_PMU_NWAMODE 0xC201 /*!< Write-allocate store is not allocated into the data cache due to no-write-allocate mode */ +#define ARMCM85_PMU_SAHB_ACCESS 0xC300 /*!< Read or write access on the S-AHB interface to the TCM */ +#define ARMCM85_PMU_PAHB_ACCESS 0xC301 /*!< Read or write access on the P-AHB write interface */ +#define ARMCM85_PMU_AXI_WRITE_ACCESS 0xC302 /*!< Any beat access to M-AXI write interface */ +#define ARMCM85_PMU_AXI_READ_ACCESS 0xC303 /*!< Any beat access to M-AXI read interface */ +#define ARMCM85_PMU_DOSTIMEOUT_DOUBLE 0xC400 /*!< Denial of Service timeout has fired twice and caused buffers to drain to allow forward progress */ +#define ARMCM85_PMU_DOSTIMEOUT_TRIPLE 0xC401 /*!< Denial of Service timeout has fired three times and blocked the LSU to force forward progress */ + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = FPU->MVFR0; + if ((mvfr0 & (FPU_MVFR0_FPSP_Msk | FPU_MVFR0_FPDP_Msk)) == 0x220U) + { + return 2U; /* Double + Single precision FPU */ + } + else if ((mvfr0 & (FPU_MVFR0_FPSP_Msk | FPU_MVFR0_FPDP_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + +/* ########################## MVE functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_MveFunctions MVE Functions + \brief Function that provides MVE type. + @{ + */ + +/** + \brief get MVE type + \details returns the MVE type + \returns + - \b 0: No Vector Extension (MVE) + - \b 1: Integer Vector Extension (MVE-I) + - \b 2: Floating-point Vector Extension (MVE-F) + */ +__STATIC_INLINE uint32_t SCB_GetMVEType(void) +{ + const uint32_t mvfr1 = FPU->MVFR1; + if ((mvfr1 & FPU_MVFR1_MVE_Msk) == (0x2U << FPU_MVFR1_MVE_Pos)) + { + return 2U; + } + else if ((mvfr1 & FPU_MVFR1_MVE_Msk) == (0x1U << FPU_MVFR1_MVE_Pos)) + { + return 1U; + } + else + { + return 0U; + } +} + + +/*@} end of CMSIS_Core_MveFunctions */ + + +/* ########################## Cache functions #################################### */ + +#if ((defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)) || \ + (defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U))) +#include "cachel1_armv7.h" +#endif + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + +/* ################### PAC Key functions ########################### */ + +#if (defined (__ARM_FEATURE_PAUTH) && (__ARM_FEATURE_PAUTH == 1)) +#include "pac_armv81.h" +#endif + + +/* ################################## Debug Control function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DCBFunctions Debug Control Functions + \brief Functions that access the Debug Control Block. + @{ + */ + + +/** + \brief Set Debug Authentication Control Register + \details writes to Debug Authentication Control register. + \param [in] value value to be writen. + */ +__STATIC_INLINE void DCB_SetAuthCtrl(uint32_t value) +{ + __DSB(); + __ISB(); + DCB->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register + \details Reads Debug Authentication Control register. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t DCB_GetAuthCtrl(void) +{ + return (DCB->DAUTHCTRL); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Debug Authentication Control Register (non-secure) + \details writes to non-secure Debug Authentication Control register when in secure state. + \param [in] value value to be writen + */ +__STATIC_INLINE void TZ_DCB_SetAuthCtrl_NS(uint32_t value) +{ + __DSB(); + __ISB(); + DCB_NS->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register (non-secure) + \details Reads non-secure Debug Authentication Control register when in secure state. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t TZ_DCB_GetAuthCtrl_NS(void) +{ + return (DCB_NS->DAUTHCTRL); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## Debug Identification function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DIBFunctions Debug Identification Functions + \brief Functions that access the Debug Identification Block. + @{ + */ + + +/** + \brief Get Debug Authentication Status Register + \details Reads Debug Authentication Status register. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t DIB_GetAuthStatus(void) +{ + return (DIB->DAUTHSTATUS); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Debug Authentication Status Register (non-secure) + \details Reads non-secure Debug Authentication Status register when in secure state. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t TZ_DIB_GetAuthStatus_NS(void) +{ + return (DIB_NS->DAUTHSTATUS); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM85_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/CMSIS/Core/Include/core_sc000.h b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/CMSIS/Core/Include/core_sc000.h new file mode 100644 index 0000000000..e252068ce6 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/CMSIS/Core/Include/core_sc000.h @@ -0,0 +1,1030 @@ +/**************************************************************************//** + * @file core_sc000.h + * @brief CMSIS SC000 Core Peripheral Access Layer Header File + * @version V5.0.7 + * @date 27. March 2020 + ******************************************************************************/ +/* + * Copyright (c) 2009-2020 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_SC000_H_GENERIC +#define __CORE_SC000_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup SC000 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS SC000 definitions */ +#define __SC000_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __SC000_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __SC000_CMSIS_VERSION ((__SC000_CMSIS_VERSION_MAIN << 16U) | \ + __SC000_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_SC (000U) /*!< Cortex secure core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_SC000_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_SC000_H_DEPENDANT +#define __CORE_SC000_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __SC000_REV + #define __SC000_REV 0x0000U + #warning "__SC000_REV not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 0U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group SC000 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core MPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t _reserved0:1; /*!< bit: 0 Reserved */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[31U]; + __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[31U]; + __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[31U]; + __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[31U]; + uint32_t RESERVED4[64U]; + __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED0[1U]; + __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + uint32_t RESERVED1[154U]; + __IOM uint32_t SFCR; /*!< Offset: 0x290 (R/W) Security Features Control Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ +} MPU_Type; + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 8U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief SC000 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. + Therefore they are not covered by the SC000 header file. + @{ + */ +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else +/*#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping not available for SC000 */ +/*#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping not available for SC000 */ + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ +/*#define NVIC_GetActive __NVIC_GetActive not available for SC000 */ + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ + + +/* Interrupt Priorities are WORD accessible only under Armv6-M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + /* ARM Application Note 321 states that the M0 and M0+ do not require the architectural barrier - assume SC000 is the same */ +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_SC000_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/CMSIS/Core/Include/core_sc300.h b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/CMSIS/Core/Include/core_sc300.h new file mode 100644 index 0000000000..d66621031e --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/CMSIS/Core/Include/core_sc300.h @@ -0,0 +1,1917 @@ +/**************************************************************************//** + * @file core_sc300.h + * @brief CMSIS SC300 Core Peripheral Access Layer Header File + * @version V5.0.10 + * @date 04. June 2021 + ******************************************************************************/ +/* + * Copyright (c) 2009-2021 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_SC300_H_GENERIC +#define __CORE_SC300_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup SC3000 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS SC300 definitions */ +#define __SC300_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __SC300_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __SC300_CMSIS_VERSION ((__SC300_CMSIS_VERSION_MAIN << 16U) | \ + __SC300_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_SC (300U) /*!< Cortex secure core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_SC300_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_SC300_H_DEPENDANT +#define __CORE_SC300_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __SC300_REV + #define __SC300_REV 0x0000U + #warning "__SC300_REV not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 1U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group SC300 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:1; /*!< bit: 9 Reserved */ + uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */ + uint32_t _reserved1:8; /*!< bit: 16..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit */ + uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */ +#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */ +#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24U]; + __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RESERVED1[24U]; + __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24U]; + __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24U]; + __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56U]; + __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[5U]; + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + uint32_t RESERVED1[129U]; + __IOM uint32_t SFCR; /*!< Offset: 0x290 (R/W) Security Features Control Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLBASE_Pos 29U /*!< SCB VTOR: TBLBASE Position */ +#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */ + +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_CFSR_MEMFAULTSR_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ +#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR: DISDEFWBUF Position */ +#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ + +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x1UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x1UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY2_Pos 0U /*!< TPI ITATBCTR2: ATREADY2 Position */ +#define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/) /*!< TPI ITATBCTR2: ATREADY2 Mask */ + +#define TPI_ITATBCTR2_ATREADY1_Pos 0U /*!< TPI ITATBCTR2: ATREADY1 Position */ +#define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/) /*!< TPI ITATBCTR2: ATREADY1 Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x1UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x1UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY2_Pos 0U /*!< TPI ITATBCTR0: ATREADY2 Position */ +#define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/) /*!< TPI ITATBCTR0: ATREADY2 Mask */ + +#define TPI_ITATBCTR0_ATREADY1_Pos 0U /*!< TPI ITATBCTR0: ATREADY1 Position */ +#define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/) /*!< TPI ITATBCTR0: ATREADY1 Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + /* ARM Application Note 321 states that the M3 does not require the architectural barrier */ +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_SC300_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/CMSIS/Core/Include/core_starmc1.h b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/CMSIS/Core/Include/core_starmc1.h new file mode 100644 index 0000000000..ebc0f77eb7 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/CMSIS/Core/Include/core_starmc1.h @@ -0,0 +1,3592 @@ +/**************************************************************************//** + * @file core_starmc1.h + * @brief CMSIS ArmChina STAR-MC1 Core Peripheral Access Layer Header File + * @version V1.0.2 + * @date 07. April 2022 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. + * Copyright (c) 2018-2022 Arm China. + * All rights reserved. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#elif defined ( __GNUC__ ) + #pragma GCC diagnostic ignored "-Wpedantic" /* disable pedantic warning due to unnamed structs/unions */ +#endif + +#ifndef __CORE_STAR_H_GENERIC +#define __CORE_STAR_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup STAR-MC1 + @{ + */ + +#include "cmsis_version.h" + +/* Macro Define for STAR-MC1 */ +#define __STAR_MC (1U) /*!< STAR-MC Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined (__TARGET_FPU_VFP) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined (__ARM_FP) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined (__ARMVFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined (__TI_VFP_SUPPORT__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined (__FPU_VFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_STAR_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_STAR_H_DEPENDANT +#define __CORE_STAR_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __STAR_REV + #define __STAR_REV 0x0000U + #warning "__STAR_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DSP_PRESENT + #define __DSP_PRESENT 0U + #warning "__DSP_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __ICACHE_PRESENT + #define __ICACHE_PRESENT 0U + #warning "__ICACHE_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DCACHE_PRESENT + #define __DCACHE_PRESENT 0U + #warning "__DCACHE_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DTCM_PRESENT + #define __DTCM_PRESENT 0U + #warning "__DTCM_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group STAR-MC1 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core SAU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for STAR-MC1 processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ +#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */ + uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */ + uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */ +#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */ + +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED6[580U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ID_ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[1U]; + __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ + __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ + __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ + __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */ + uint32_t RESERVED_ADD1[21U]; + __IOM uint32_t SFSR; /*!< Offset: 0x0E4 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x0E8 (R/W) Secure Fault Address Register */ + uint32_t RESERVED3[69U]; + __OM uint32_t STIR; /*!< Offset: F00-D00=0x200 ( /W) Software Triggered Interrupt Register */ + uint32_t RESERVED4[15U]; + __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ + uint32_t RESERVED5[1U]; + __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ + uint32_t RESERVED6[1U]; + __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ + __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ + __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ + __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ + __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ + __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ + __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ + __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ +} SCB_Type; + +typedef struct +{ + __IOM uint32_t CACR; /*!< Offset: 0x0 (R/W) L1 Cache Control Register */ + __IOM uint32_t ITCMCR; /*!< Offset: 0x10 (R/W) Instruction Tightly-Coupled Memory Control Register */ + __IOM uint32_t DTCMCR; /*!< Offset: 0x14 (R/W) Data Tightly-Coupled Memory Control Registers */ +}EMSS_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ +#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */ +#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */ +#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */ + +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */ +#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_CFSR_MEMFAULTSR_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */ +#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/* SCB Non-Secure Access Control Register Definitions */ +#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */ +#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */ + +#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */ +#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */ + +#define SCB_NSACR_CPn_Pos 0U /*!< SCB NSACR: CPn Position */ +#define SCB_NSACR_CPn_Msk (1UL /*<< SCB_NSACR_CPn_Pos*/) /*!< SCB NSACR: CPn Mask */ + +/* SCB Cache Level ID Register Definitions */ +#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ +#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ + +#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ +#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ + +#define SCB_CLIDR_IC_Pos 0U /*!< SCB CLIDR: IC Position */ +#define SCB_CLIDR_IC_Msk (1UL << SCB_CLIDR_IC_Pos) /*!< SCB CLIDR: IC Mask */ + +#define SCB_CLIDR_DC_Pos 1U /*!< SCB CLIDR: DC Position */ +#define SCB_CLIDR_DC_Msk (1UL << SCB_CLIDR_DC_Pos) /*!< SCB CLIDR: DC Mask */ + + + +/* SCB Cache Type Register Definitions */ +#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ +#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ + +#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ +#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ + +#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ +#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ + +#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ +#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ + +#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ +#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ + +/* SCB Cache Size ID Register Definitions */ +#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ +#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ + +#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ +#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ + +#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ +#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ + +#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ +#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ + +#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ +#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ + +#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ +#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ + +#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ +#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ + +/* SCB Cache Size Selection Register Definitions */ +#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ +#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ + +#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ +#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ + +/* SCB Software Triggered Interrupt Register Definitions */ +#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ +#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ + +/* SCB D-Cache line Invalidate by Set-way Register Definitions */ +#define SCB_DCISW_LEVEL_Pos 1U /*!< SCB DCISW: Level Position */ +#define SCB_DCISW_LEVEL_Msk (7UL << SCB_DCISW_LEVEL_Pos) /*!< SCB DCISW: Level Mask */ + +#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ +#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ + +#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ +#define SCB_DCISW_SET_Msk (0xFFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ + +/* SCB D-Cache Clean line by Set-way Register Definitions */ +#define SCB_DCCSW_LEVEL_Pos 1U /*!< SCB DCCSW: Level Position */ +#define SCB_DCCSW_LEVEL_Msk (7UL << SCB_DCCSW_LEVEL_Pos) /*!< SCB DCCSW: Level Mask */ + +#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ +#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ + +#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ +#define SCB_DCCSW_SET_Msk (0xFFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ + +/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ +#define SCB_DCCISW_LEVEL_Pos 1U /*!< SCB DCCISW: Level Position */ +#define SCB_DCCISW_LEVEL_Msk (7UL << SCB_DCCISW_LEVEL_Pos) /*!< SCB DCCISW: Level Mask */ + +#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ +#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ + +#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ +#define SCB_DCCISW_SET_Msk (0xFFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ + +/* ArmChina: Implementation Defined */ +/* Instruction Tightly-Coupled Memory Control Register Definitions */ +#define SCB_ITCMCR_SZ_Pos 3U /*!< SCB ITCMCR: SZ Position */ +#define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) /*!< SCB ITCMCR: SZ Mask */ + +#define SCB_ITCMCR_EN_Pos 0U /*!< SCB ITCMCR: EN Position */ +#define SCB_ITCMCR_EN_Msk (1UL /*<< SCB_ITCMCR_EN_Pos*/) /*!< SCB ITCMCR: EN Mask */ + +/* Data Tightly-Coupled Memory Control Register Definitions */ +#define SCB_DTCMCR_SZ_Pos 3U /*!< SCB DTCMCR: SZ Position */ +#define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) /*!< SCB DTCMCR: SZ Mask */ + +#define SCB_DTCMCR_EN_Pos 0U /*!< SCB DTCMCR: EN Position */ +#define SCB_DTCMCR_EN_Msk (1UL /*<< SCB_DTCMCR_EN_Pos*/) /*!< SCB DTCMCR: EN Mask */ + +/* L1 Cache Control Register Definitions */ +#define SCB_CACR_DCCLEAN_Pos 16U /*!< SCB CACR: DCCLEAN Position */ +#define SCB_CACR_DCCLEAN_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: DCCLEAN Mask */ + +#define SCB_CACR_ICACTIVE_Pos 13U /*!< SCB CACR: ICACTIVE Position */ +#define SCB_CACR_ICACTIVE_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: ICACTIVE Mask */ + +#define SCB_CACR_DCACTIVE_Pos 12U /*!< SCB CACR: DCACTIVE Position */ +#define SCB_CACR_DCACTIVE_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: DCACTIVE Mask */ + +#define SCB_CACR_FORCEWT_Pos 2U /*!< SCB CACR: FORCEWT Position */ +#define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: FORCEWT Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ + __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */ + uint32_t RESERVED6[4U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Stimulus Port Register Definitions */ +#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */ +#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */ + +#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */ +#define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */ + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */ +#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */ + +#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */ +#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED14[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED15[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED16[1U]; + __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ + uint32_t RESERVED17[1U]; + __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ + uint32_t RESERVED18[1U]; + __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ + uint32_t RESERVED19[1U]; + __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ + uint32_t RESERVED20[1U]; + __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ + uint32_t RESERVED21[1U]; + __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ + uint32_t RESERVED22[1U]; + __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ + uint32_t RESERVED23[1U]; + __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ + uint32_t RESERVED24[1U]; + __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ + uint32_t RESERVED25[1U]; + __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ + uint32_t RESERVED26[1U]; + __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ + uint32_t RESERVED27[1U]; + __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ + uint32_t RESERVED28[1U]; + __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ + uint32_t RESERVED29[1U]; + __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ + uint32_t RESERVED30[1U]; + __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ + uint32_t RESERVED31[1U]; + __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ + uint32_t RESERVED32[934U]; + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ + uint32_t RESERVED33[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */ +#define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t ITFTTD0; /*!< Offset: 0xEEC (R/ ) Integration Test FIFO Test Data 0 Register */ + __IOM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/W) Integration Test ATB Control Register 2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) Integration Test ATB Control Register 0 */ + __IM uint32_t ITFTTD1; /*!< Offset: 0xEFC (R/ ) Integration Test FIFO Test Data 1 Register */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) Device Configuration Register */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Identifier Register */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ +#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration Test FIFO Test Data 0 Register Definitions */ +#define TPI_ITFTTD0_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD0: ATB Interface 2 ATVALIDPosition */ +#define TPI_ITFTTD0_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 2 ATVALID Mask */ + +#define TPI_ITFTTD0_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD0: ATB Interface 2 byte count Position */ +#define TPI_ITFTTD0_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 2 byte count Mask */ + +#define TPI_ITFTTD0_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Position */ +#define TPI_ITFTTD0_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Mask */ + +#define TPI_ITFTTD0_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD0: ATB Interface 1 byte count Position */ +#define TPI_ITFTTD0_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 1 byte countt Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data2_Pos 16U /*!< TPI ITFTTD0: ATB Interface 1 data2 Position */ +#define TPI_ITFTTD0_ATB_IF1_data2_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data2 Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data1_Pos 8U /*!< TPI ITFTTD0: ATB Interface 1 data1 Position */ +#define TPI_ITFTTD0_ATB_IF1_data1_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data1 Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data0_Pos 0U /*!< TPI ITFTTD0: ATB Interface 1 data0 Position */ +#define TPI_ITFTTD0_ATB_IF1_data0_Msk (0xFFUL /*<< TPI_ITFTTD0_ATB_IF1_data0_Pos*/) /*!< TPI ITFTTD0: ATB Interface 1 data0 Mask */ + +/* TPI Integration Test ATB Control Register 2 Register Definitions */ +#define TPI_ITATBCTR2_AFVALID2S_Pos 1U /*!< TPI ITATBCTR2: AFVALID2S Position */ +#define TPI_ITATBCTR2_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID2S_Pos) /*!< TPI ITATBCTR2: AFVALID2SS Mask */ + +#define TPI_ITATBCTR2_AFVALID1S_Pos 1U /*!< TPI ITATBCTR2: AFVALID1S Position */ +#define TPI_ITATBCTR2_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID1S_Pos) /*!< TPI ITATBCTR2: AFVALID1SS Mask */ + +#define TPI_ITATBCTR2_ATREADY2S_Pos 0U /*!< TPI ITATBCTR2: ATREADY2S Position */ +#define TPI_ITATBCTR2_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2S_Pos*/) /*!< TPI ITATBCTR2: ATREADY2S Mask */ + +#define TPI_ITATBCTR2_ATREADY1S_Pos 0U /*!< TPI ITATBCTR2: ATREADY1S Position */ +#define TPI_ITATBCTR2_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1S_Pos*/) /*!< TPI ITATBCTR2: ATREADY1S Mask */ + +/* TPI Integration Test FIFO Test Data 1 Register Definitions */ +#define TPI_ITFTTD1_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Position */ +#define TPI_ITFTTD1_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Mask */ + +#define TPI_ITFTTD1_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD1: ATB Interface 2 byte count Position */ +#define TPI_ITFTTD1_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 2 byte count Mask */ + +#define TPI_ITFTTD1_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Position */ +#define TPI_ITFTTD1_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Mask */ + +#define TPI_ITFTTD1_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD1: ATB Interface 1 byte count Position */ +#define TPI_ITFTTD1_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 1 byte countt Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data2_Pos 16U /*!< TPI ITFTTD1: ATB Interface 2 data2 Position */ +#define TPI_ITFTTD1_ATB_IF2_data2_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data2 Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data1_Pos 8U /*!< TPI ITFTTD1: ATB Interface 2 data1 Position */ +#define TPI_ITFTTD1_ATB_IF2_data1_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data1 Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data0_Pos 0U /*!< TPI ITFTTD1: ATB Interface 2 data0 Position */ +#define TPI_ITFTTD1_ATB_IF2_data0_Msk (0xFFUL /*<< TPI_ITFTTD1_ATB_IF2_data0_Pos*/) /*!< TPI ITFTTD1: ATB Interface 2 data0 Mask */ + +/* TPI Integration Test ATB Control Register 0 Definitions */ +#define TPI_ITATBCTR0_AFVALID2S_Pos 1U /*!< TPI ITATBCTR0: AFVALID2S Position */ +#define TPI_ITATBCTR0_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID2S_Pos) /*!< TPI ITATBCTR0: AFVALID2SS Mask */ + +#define TPI_ITATBCTR0_AFVALID1S_Pos 1U /*!< TPI ITATBCTR0: AFVALID1S Position */ +#define TPI_ITATBCTR0_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID1S_Pos) /*!< TPI ITATBCTR0: AFVALID1SS Mask */ + +#define TPI_ITATBCTR0_ATREADY2S_Pos 0U /*!< TPI ITATBCTR0: ATREADY2S Position */ +#define TPI_ITATBCTR0_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2S_Pos*/) /*!< TPI ITATBCTR0: ATREADY2S Mask */ + +#define TPI_ITATBCTR0_ATREADY1S_Pos 0U /*!< TPI ITATBCTR0: ATREADY1S Position */ +#define TPI_ITATBCTR0_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1S_Pos*/) /*!< TPI ITATBCTR0: ATREADY1S Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFOSZ Position */ +#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFOSZ Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x3FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */ + __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */ + __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */ + __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */ + uint32_t RESERVED0[1]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ +#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/* MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */ + +/* MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/* MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#else + uint32_t RESERVED0[3]; +#endif + __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */ +} SAU_Type; + +/* SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/* SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/* SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/* SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/* SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/* Secure Fault Status Register Definitions */ +#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */ +#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */ + +#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */ +#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */ + +#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */ +#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */ + +#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */ +#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */ + +#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */ +#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */ + +#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */ +#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */ + +#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */ +#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */ + +#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */ +#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and VFP Feature Register 2 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */ +#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */ + +#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */ +#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */ + +#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */ +#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */ + +#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */ +#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */ + +#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */ +#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */ + +#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */ +#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */ +#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */ +#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and VFP Feature Register 0 Definitions */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and VFP Feature Register 1 Definitions */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/* Media and VFP Feature Register 2 Definitions */ +#define FPU_MVFR2_FPMisc_Pos 4U /*!< MVFR2: FPMisc bits Position */ +#define FPU_MVFR2_FPMisc_Msk (0xFUL << FPU_MVFR2_FPMisc_Pos) /*!< MVFR2: FPMisc bits Mask */ + +/*@} end of group CMSIS_FPU */ + + + + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DCB Debug Control Block + \brief Type definitions for the Debug Control Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Control Block Registers (DCB). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED0[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} DCB_Type; + +/* DHCSR, Debug Halting Control and Status Register Definitions */ +#define DCB_DHCSR_DBGKEY_Pos 16U /*!< DCB DHCSR: Debug key Position */ +#define DCB_DHCSR_DBGKEY_Msk (0xFFFFUL << DCB_DHCSR_DBGKEY_Pos) /*!< DCB DHCSR: Debug key Mask */ + +#define DCB_DHCSR_S_RESTART_ST_Pos 26U /*!< DCB DHCSR: Restart sticky status Position */ +#define DCB_DHCSR_S_RESTART_ST_Msk (0x1UL << DCB_DHCSR_S_RESTART_ST_Pos) /*!< DCB DHCSR: Restart sticky status Mask */ + +#define DCB_DHCSR_S_RESET_ST_Pos 25U /*!< DCB DHCSR: Reset sticky status Position */ +#define DCB_DHCSR_S_RESET_ST_Msk (0x1UL << DCB_DHCSR_S_RESET_ST_Pos) /*!< DCB DHCSR: Reset sticky status Mask */ + +#define DCB_DHCSR_S_RETIRE_ST_Pos 24U /*!< DCB DHCSR: Retire sticky status Position */ +#define DCB_DHCSR_S_RETIRE_ST_Msk (0x1UL << DCB_DHCSR_S_RETIRE_ST_Pos) /*!< DCB DHCSR: Retire sticky status Mask */ + +#define DCB_DHCSR_S_SDE_Pos 20U /*!< DCB DHCSR: Secure debug enabled Position */ +#define DCB_DHCSR_S_SDE_Msk (0x1UL << DCB_DHCSR_S_SDE_Pos) /*!< DCB DHCSR: Secure debug enabled Mask */ + +#define DCB_DHCSR_S_LOCKUP_Pos 19U /*!< DCB DHCSR: Lockup status Position */ +#define DCB_DHCSR_S_LOCKUP_Msk (0x1UL << DCB_DHCSR_S_LOCKUP_Pos) /*!< DCB DHCSR: Lockup status Mask */ + +#define DCB_DHCSR_S_SLEEP_Pos 18U /*!< DCB DHCSR: Sleeping status Position */ +#define DCB_DHCSR_S_SLEEP_Msk (0x1UL << DCB_DHCSR_S_SLEEP_Pos) /*!< DCB DHCSR: Sleeping status Mask */ + +#define DCB_DHCSR_S_HALT_Pos 17U /*!< DCB DHCSR: Halted status Position */ +#define DCB_DHCSR_S_HALT_Msk (0x1UL << DCB_DHCSR_S_HALT_Pos) /*!< DCB DHCSR: Halted status Mask */ + +#define DCB_DHCSR_S_REGRDY_Pos 16U /*!< DCB DHCSR: Register ready status Position */ +#define DCB_DHCSR_S_REGRDY_Msk (0x1UL << DCB_DHCSR_S_REGRDY_Pos) /*!< DCB DHCSR: Register ready status Mask */ + +#define DCB_DHCSR_C_SNAPSTALL_Pos 5U /*!< DCB DHCSR: Snap stall control Position */ +#define DCB_DHCSR_C_SNAPSTALL_Msk (0x1UL << DCB_DHCSR_C_SNAPSTALL_Pos) /*!< DCB DHCSR: Snap stall control Mask */ + +#define DCB_DHCSR_C_MASKINTS_Pos 3U /*!< DCB DHCSR: Mask interrupts control Position */ +#define DCB_DHCSR_C_MASKINTS_Msk (0x1UL << DCB_DHCSR_C_MASKINTS_Pos) /*!< DCB DHCSR: Mask interrupts control Mask */ + +#define DCB_DHCSR_C_STEP_Pos 2U /*!< DCB DHCSR: Step control Position */ +#define DCB_DHCSR_C_STEP_Msk (0x1UL << DCB_DHCSR_C_STEP_Pos) /*!< DCB DHCSR: Step control Mask */ + +#define DCB_DHCSR_C_HALT_Pos 1U /*!< DCB DHCSR: Halt control Position */ +#define DCB_DHCSR_C_HALT_Msk (0x1UL << DCB_DHCSR_C_HALT_Pos) /*!< DCB DHCSR: Halt control Mask */ + +#define DCB_DHCSR_C_DEBUGEN_Pos 0U /*!< DCB DHCSR: Debug enable control Position */ +#define DCB_DHCSR_C_DEBUGEN_Msk (0x1UL /*<< DCB_DHCSR_C_DEBUGEN_Pos*/) /*!< DCB DHCSR: Debug enable control Mask */ + +/* DCRSR, Debug Core Register Select Register Definitions */ +#define DCB_DCRSR_REGWnR_Pos 16U /*!< DCB DCRSR: Register write/not-read Position */ +#define DCB_DCRSR_REGWnR_Msk (0x1UL << DCB_DCRSR_REGWnR_Pos) /*!< DCB DCRSR: Register write/not-read Mask */ + +#define DCB_DCRSR_REGSEL_Pos 0U /*!< DCB DCRSR: Register selector Position */ +#define DCB_DCRSR_REGSEL_Msk (0x7FUL /*<< DCB_DCRSR_REGSEL_Pos*/) /*!< DCB DCRSR: Register selector Mask */ + +/* DCRDR, Debug Core Register Data Register Definitions */ +#define DCB_DCRDR_DBGTMP_Pos 0U /*!< DCB DCRDR: Data temporary buffer Position */ +#define DCB_DCRDR_DBGTMP_Msk (0xFFFFFFFFUL /*<< DCB_DCRDR_DBGTMP_Pos*/) /*!< DCB DCRDR: Data temporary buffer Mask */ + +/* DEMCR, Debug Exception and Monitor Control Register Definitions */ +#define DCB_DEMCR_TRCENA_Pos 24U /*!< DCB DEMCR: Trace enable Position */ +#define DCB_DEMCR_TRCENA_Msk (0x1UL << DCB_DEMCR_TRCENA_Pos) /*!< DCB DEMCR: Trace enable Mask */ + +#define DCB_DEMCR_MONPRKEY_Pos 23U /*!< DCB DEMCR: Monitor pend req key Position */ +#define DCB_DEMCR_MONPRKEY_Msk (0x1UL << DCB_DEMCR_MONPRKEY_Pos) /*!< DCB DEMCR: Monitor pend req key Mask */ + +#define DCB_DEMCR_UMON_EN_Pos 21U /*!< DCB DEMCR: Unprivileged monitor enable Position */ +#define DCB_DEMCR_UMON_EN_Msk (0x1UL << DCB_DEMCR_UMON_EN_Pos) /*!< DCB DEMCR: Unprivileged monitor enable Mask */ + +#define DCB_DEMCR_SDME_Pos 20U /*!< DCB DEMCR: Secure DebugMonitor enable Position */ +#define DCB_DEMCR_SDME_Msk (0x1UL << DCB_DEMCR_SDME_Pos) /*!< DCB DEMCR: Secure DebugMonitor enable Mask */ + +#define DCB_DEMCR_MON_REQ_Pos 19U /*!< DCB DEMCR: Monitor request Position */ +#define DCB_DEMCR_MON_REQ_Msk (0x1UL << DCB_DEMCR_MON_REQ_Pos) /*!< DCB DEMCR: Monitor request Mask */ + +#define DCB_DEMCR_MON_STEP_Pos 18U /*!< DCB DEMCR: Monitor step Position */ +#define DCB_DEMCR_MON_STEP_Msk (0x1UL << DCB_DEMCR_MON_STEP_Pos) /*!< DCB DEMCR: Monitor step Mask */ + +#define DCB_DEMCR_MON_PEND_Pos 17U /*!< DCB DEMCR: Monitor pend Position */ +#define DCB_DEMCR_MON_PEND_Msk (0x1UL << DCB_DEMCR_MON_PEND_Pos) /*!< DCB DEMCR: Monitor pend Mask */ + +#define DCB_DEMCR_MON_EN_Pos 16U /*!< DCB DEMCR: Monitor enable Position */ +#define DCB_DEMCR_MON_EN_Msk (0x1UL << DCB_DEMCR_MON_EN_Pos) /*!< DCB DEMCR: Monitor enable Mask */ + +#define DCB_DEMCR_VC_SFERR_Pos 11U /*!< DCB DEMCR: Vector Catch SecureFault Position */ +#define DCB_DEMCR_VC_SFERR_Msk (0x1UL << DCB_DEMCR_VC_SFERR_Pos) /*!< DCB DEMCR: Vector Catch SecureFault Mask */ + +#define DCB_DEMCR_VC_HARDERR_Pos 10U /*!< DCB DEMCR: Vector Catch HardFault errors Position */ +#define DCB_DEMCR_VC_HARDERR_Msk (0x1UL << DCB_DEMCR_VC_HARDERR_Pos) /*!< DCB DEMCR: Vector Catch HardFault errors Mask */ + +#define DCB_DEMCR_VC_INTERR_Pos 9U /*!< DCB DEMCR: Vector Catch interrupt errors Position */ +#define DCB_DEMCR_VC_INTERR_Msk (0x1UL << DCB_DEMCR_VC_INTERR_Pos) /*!< DCB DEMCR: Vector Catch interrupt errors Mask */ + +#define DCB_DEMCR_VC_BUSERR_Pos 8U /*!< DCB DEMCR: Vector Catch BusFault errors Position */ +#define DCB_DEMCR_VC_BUSERR_Msk (0x1UL << DCB_DEMCR_VC_BUSERR_Pos) /*!< DCB DEMCR: Vector Catch BusFault errors Mask */ + +#define DCB_DEMCR_VC_STATERR_Pos 7U /*!< DCB DEMCR: Vector Catch state errors Position */ +#define DCB_DEMCR_VC_STATERR_Msk (0x1UL << DCB_DEMCR_VC_STATERR_Pos) /*!< DCB DEMCR: Vector Catch state errors Mask */ + +#define DCB_DEMCR_VC_CHKERR_Pos 6U /*!< DCB DEMCR: Vector Catch check errors Position */ +#define DCB_DEMCR_VC_CHKERR_Msk (0x1UL << DCB_DEMCR_VC_CHKERR_Pos) /*!< DCB DEMCR: Vector Catch check errors Mask */ + +#define DCB_DEMCR_VC_NOCPERR_Pos 5U /*!< DCB DEMCR: Vector Catch NOCP errors Position */ +#define DCB_DEMCR_VC_NOCPERR_Msk (0x1UL << DCB_DEMCR_VC_NOCPERR_Pos) /*!< DCB DEMCR: Vector Catch NOCP errors Mask */ + +#define DCB_DEMCR_VC_MMERR_Pos 4U /*!< DCB DEMCR: Vector Catch MemManage errors Position */ +#define DCB_DEMCR_VC_MMERR_Msk (0x1UL << DCB_DEMCR_VC_MMERR_Pos) /*!< DCB DEMCR: Vector Catch MemManage errors Mask */ + +#define DCB_DEMCR_VC_CORERESET_Pos 0U /*!< DCB DEMCR: Vector Catch Core reset Position */ +#define DCB_DEMCR_VC_CORERESET_Msk (0x1UL /*<< DCB_DEMCR_VC_CORERESET_Pos*/) /*!< DCB DEMCR: Vector Catch Core reset Mask */ + +/* DAUTHCTRL, Debug Authentication Control Register Definitions */ +#define DCB_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPNIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPNIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPNIDENSEL_Msk (0x1UL << DCB_DAUTHCTRL_SPNIDENSEL_Pos) /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Mask */ + +#define DCB_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< DCB DAUTHCTRL: Secure invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPIDENSEL_Msk (0x1UL /*<< DCB_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< DCB DAUTHCTRL: Secure invasive debug enable select Mask */ + +/* DSCSR, Debug Security Control and Status Register Definitions */ +#define DCB_DSCSR_CDSKEY_Pos 17U /*!< DCB DSCSR: CDS write-enable key Position */ +#define DCB_DSCSR_CDSKEY_Msk (0x1UL << DCB_DSCSR_CDSKEY_Pos) /*!< DCB DSCSR: CDS write-enable key Mask */ + +#define DCB_DSCSR_CDS_Pos 16U /*!< DCB DSCSR: Current domain Secure Position */ +#define DCB_DSCSR_CDS_Msk (0x1UL << DCB_DSCSR_CDS_Pos) /*!< DCB DSCSR: Current domain Secure Mask */ + +#define DCB_DSCSR_SBRSEL_Pos 1U /*!< DCB DSCSR: Secure banked register select Position */ +#define DCB_DSCSR_SBRSEL_Msk (0x1UL << DCB_DSCSR_SBRSEL_Pos) /*!< DCB DSCSR: Secure banked register select Mask */ + +#define DCB_DSCSR_SBRSELEN_Pos 0U /*!< DCB DSCSR: Secure banked register select enable Position */ +#define DCB_DSCSR_SBRSELEN_Msk (0x1UL /*<< DCB_DSCSR_SBRSELEN_Pos*/) /*!< DCB DSCSR: Secure banked register select enable Mask */ + +/*@} end of group CMSIS_DCB */ + + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DIB Debug Identification Block + \brief Type definitions for the Debug Identification Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Identification Block Registers (DIB). + */ +typedef struct +{ + __OM uint32_t DLAR; /*!< Offset: 0x000 ( /W) SCS Software Lock Access Register */ + __IM uint32_t DLSR; /*!< Offset: 0x004 (R/ ) SCS Software Lock Status Register */ + __IM uint32_t DAUTHSTATUS; /*!< Offset: 0x008 (R/ ) Debug Authentication Status Register */ + __IM uint32_t DDEVARCH; /*!< Offset: 0x00C (R/ ) SCS Device Architecture Register */ + __IM uint32_t DDEVTYPE; /*!< Offset: 0x010 (R/ ) SCS Device Type Register */ +} DIB_Type; + +/* DLAR, SCS Software Lock Access Register Definitions */ +#define DIB_DLAR_KEY_Pos 0U /*!< DIB DLAR: KEY Position */ +#define DIB_DLAR_KEY_Msk (0xFFFFFFFFUL /*<< DIB_DLAR_KEY_Pos */) /*!< DIB DLAR: KEY Mask */ + +/* DLSR, SCS Software Lock Status Register Definitions */ +#define DIB_DLSR_nTT_Pos 2U /*!< DIB DLSR: Not thirty-two bit Position */ +#define DIB_DLSR_nTT_Msk (0x1UL << DIB_DLSR_nTT_Pos ) /*!< DIB DLSR: Not thirty-two bit Mask */ + +#define DIB_DLSR_SLK_Pos 1U /*!< DIB DLSR: Software Lock status Position */ +#define DIB_DLSR_SLK_Msk (0x1UL << DIB_DLSR_SLK_Pos ) /*!< DIB DLSR: Software Lock status Mask */ + +#define DIB_DLSR_SLI_Pos 0U /*!< DIB DLSR: Software Lock implemented Position */ +#define DIB_DLSR_SLI_Msk (0x1UL /*<< DIB_DLSR_SLI_Pos*/) /*!< DIB DLSR: Software Lock implemented Mask */ + +/* DAUTHSTATUS, Debug Authentication Status Register Definitions */ +#define DIB_DAUTHSTATUS_SNID_Pos 6U /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_SNID_Msk (0x3UL << DIB_DAUTHSTATUS_SNID_Pos ) /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_SID_Pos 4U /*!< DIB DAUTHSTATUS: Secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_SID_Msk (0x3UL << DIB_DAUTHSTATUS_SID_Pos ) /*!< DIB DAUTHSTATUS: Secure Invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSNID_Pos 2U /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSNID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSID_Pos 0U /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSID_Msk (0x3UL /*<< DIB_DAUTHSTATUS_NSID_Pos*/) /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Mask */ + +/* DDEVARCH, SCS Device Architecture Register Definitions */ +#define DIB_DDEVARCH_ARCHITECT_Pos 21U /*!< DIB DDEVARCH: Architect Position */ +#define DIB_DDEVARCH_ARCHITECT_Msk (0x7FFUL << DIB_DDEVARCH_ARCHITECT_Pos ) /*!< DIB DDEVARCH: Architect Mask */ + +#define DIB_DDEVARCH_PRESENT_Pos 20U /*!< DIB DDEVARCH: DEVARCH Present Position */ +#define DIB_DDEVARCH_PRESENT_Msk (0x1FUL << DIB_DDEVARCH_PRESENT_Pos ) /*!< DIB DDEVARCH: DEVARCH Present Mask */ + +#define DIB_DDEVARCH_REVISION_Pos 16U /*!< DIB DDEVARCH: Revision Position */ +#define DIB_DDEVARCH_REVISION_Msk (0xFUL << DIB_DDEVARCH_REVISION_Pos ) /*!< DIB DDEVARCH: Revision Mask */ + +#define DIB_DDEVARCH_ARCHVER_Pos 12U /*!< DIB DDEVARCH: Architecture Version Position */ +#define DIB_DDEVARCH_ARCHVER_Msk (0xFUL << DIB_DDEVARCH_ARCHVER_Pos ) /*!< DIB DDEVARCH: Architecture Version Mask */ + +#define DIB_DDEVARCH_ARCHPART_Pos 0U /*!< DIB DDEVARCH: Architecture Part Position */ +#define DIB_DDEVARCH_ARCHPART_Msk (0xFFFUL /*<< DIB_DDEVARCH_ARCHPART_Pos*/) /*!< DIB DDEVARCH: Architecture Part Mask */ + +/* DDEVTYPE, SCS Device Type Register Definitions */ +#define DIB_DDEVTYPE_SUB_Pos 4U /*!< DIB DDEVTYPE: Sub-type Position */ +#define DIB_DDEVTYPE_SUB_Msk (0xFUL << DIB_DDEVTYPE_SUB_Pos ) /*!< DIB DDEVTYPE: Sub-type Mask */ + +#define DIB_DDEVTYPE_MAJOR_Pos 0U /*!< DIB DDEVTYPE: Major type Position */ +#define DIB_DDEVTYPE_MAJOR_Msk (0xFUL /*<< DIB_DDEVTYPE_MAJOR_Pos*/) /*!< DIB DDEVTYPE: Major type Mask */ + + +/*@} end of group CMSIS_DIB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ + #define DCB_BASE (0xE000EDF0UL) /*!< DCB Base Address */ + #define DIB_BASE (0xE000EFB0UL) /*!< DIB Base Address */ + #define EMSS_BASE (0xE001E000UL) /*!AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + __DSB(); +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses including + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/** + \brief Software Reset + \details Initiates a system reset request to reset the CPU. + */ +__NO_RETURN __STATIC_INLINE void __SW_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses including + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_BFHFNMINS_Msk) | /* Keep BFHFNMINS unchanged. Use this Reset function in case your case need to keep it */ + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | /* Keep priority group unchanged */ + SCB_AIRCR_SYSRESETREQ_Msk ); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Priority Grouping (non-secure) + \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB_NS->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB_NS->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping (non-secure) + \details Reads the priority grouping field from the non-secure NVIC when in secure state. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void) +{ + return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv8.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = FPU->MVFR0; + if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U) + { + return 2U; /* Double + Single precision FPU */ + } + else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + +/* ################################## Debug Control function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DCBFunctions Debug Control Functions + \brief Functions that access the Debug Control Block. + @{ + */ + + +/** + \brief Set Debug Authentication Control Register + \details writes to Debug Authentication Control register. + \param [in] value value to be writen. + */ +__STATIC_INLINE void DCB_SetAuthCtrl(uint32_t value) +{ + __DSB(); + __ISB(); + DCB->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register + \details Reads Debug Authentication Control register. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t DCB_GetAuthCtrl(void) +{ + return (DCB->DAUTHCTRL); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Debug Authentication Control Register (non-secure) + \details writes to non-secure Debug Authentication Control register when in secure state. + \param [in] value value to be writen + */ +__STATIC_INLINE void TZ_DCB_SetAuthCtrl_NS(uint32_t value) +{ + __DSB(); + __ISB(); + DCB_NS->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register (non-secure) + \details Reads non-secure Debug Authentication Control register when in secure state. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t TZ_DCB_GetAuthCtrl_NS(void) +{ + return (DCB_NS->DAUTHCTRL); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## Debug Identification function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DIBFunctions Debug Identification Functions + \brief Functions that access the Debug Identification Block. + @{ + */ + + +/** + \brief Get Debug Authentication Status Register + \details Reads Debug Authentication Status register. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t DIB_GetAuthStatus(void) +{ + return (DIB->DAUTHSTATUS); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Debug Authentication Status Register (non-secure) + \details Reads non-secure Debug Authentication Status register when in secure state. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t TZ_DIB_GetAuthStatus_NS(void) +{ + return (DIB_NS->DAUTHSTATUS); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + +#if ((defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)) || \ + (defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U))) + +/* ########################## Cache functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_CacheFunctions Cache Functions + \brief Functions that configure Instruction and Data cache. + @{ + */ + +/* Cache Size ID Register Macros */ +#define CCSIDR_WAYS(x) (((x) & SCB_CCSIDR_ASSOCIATIVITY_Msk) >> SCB_CCSIDR_ASSOCIATIVITY_Pos) +#define CCSIDR_SETS(x) (((x) & SCB_CCSIDR_NUMSETS_Msk ) >> SCB_CCSIDR_NUMSETS_Pos ) + +#define __SCB_DCACHE_LINE_SIZE 32U /*!< STAR-MC1 cache line size is fixed to 32 bytes (8 words). See also register SCB_CCSIDR */ +#define __SCB_ICACHE_LINE_SIZE 32U /*!< STAR-MC1 cache line size is fixed to 32 bytes (8 words). See also register SCB_CCSIDR */ + +/** + \brief Enable I-Cache + \details Turns on I-Cache + */ +__STATIC_FORCEINLINE void SCB_EnableICache (void) +{ + #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) + if (SCB->CCR & SCB_CCR_IC_Msk) return; /* return if ICache is already enabled */ + + __DSB(); + __ISB(); + SCB->ICIALLU = 0UL; /* invalidate I-Cache */ + __DSB(); + __ISB(); + SCB->CCR |= (uint32_t)SCB_CCR_IC_Msk; /* enable I-Cache */ + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Disable I-Cache + \details Turns off I-Cache + */ +__STATIC_FORCEINLINE void SCB_DisableICache (void) +{ + #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) + __DSB(); + __ISB(); + SCB->CCR &= ~(uint32_t)SCB_CCR_IC_Msk; /* disable I-Cache */ + SCB->ICIALLU = 0UL; /* invalidate I-Cache */ + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Invalidate I-Cache + \details Invalidates I-Cache + */ +__STATIC_FORCEINLINE void SCB_InvalidateICache (void) +{ + #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) + __DSB(); + __ISB(); + SCB->ICIALLU = 0UL; + __DSB(); + __ISB(); + #endif +} + + +/** + \brief I-Cache Invalidate by address + \details Invalidates I-Cache for the given address. + I-Cache is invalidated starting from a 32 byte aligned address in 32 byte granularity. + I-Cache memory blocks which are part of given address + given size are invalidated. + \param[in] addr address + \param[in] isize size of memory block (in number of bytes) +*/ +__STATIC_FORCEINLINE void SCB_InvalidateICache_by_Addr (void *addr, int32_t isize) +{ + #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) + if ( isize > 0 ) { + int32_t op_size = isize + (((uint32_t)addr) & (__SCB_ICACHE_LINE_SIZE - 1U)); + uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_ICACHE_LINE_SIZE - 1U) */; + + __DSB(); + + do { + SCB->ICIMVAU = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */ + op_addr += __SCB_ICACHE_LINE_SIZE; + op_size -= __SCB_ICACHE_LINE_SIZE; + } while ( op_size > 0 ); + + __DSB(); + __ISB(); + } + #endif +} + + +/** + \brief Enable D-Cache + \details Turns on D-Cache + */ +__STATIC_FORCEINLINE void SCB_EnableDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + if (SCB->CCR & SCB_CCR_DC_Msk) return; /* return if DCache is already enabled */ + + SCB->CSSELR = 0U; /* select Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) | + ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + __DSB(); + + SCB->CCR |= (uint32_t)SCB_CCR_DC_Msk; /* enable D-Cache */ + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Disable D-Cache + \details Turns off D-Cache + */ +__STATIC_FORCEINLINE void SCB_DisableDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /* select Level 1 data cache */ + __DSB(); + + SCB->CCR &= ~(uint32_t)SCB_CCR_DC_Msk; /* disable D-Cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* clean & invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) | + ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Invalidate D-Cache + \details Invalidates D-Cache + */ +__STATIC_FORCEINLINE void SCB_InvalidateDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /* select Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) | + ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Clean D-Cache + \details Cleans D-Cache + */ +__STATIC_FORCEINLINE void SCB_CleanDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /* select Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* clean D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCCSW = (((sets << SCB_DCCSW_SET_Pos) & SCB_DCCSW_SET_Msk) | + ((ways << SCB_DCCSW_WAY_Pos) & SCB_DCCSW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Clean & Invalidate D-Cache + \details Cleans and Invalidates D-Cache + */ +__STATIC_FORCEINLINE void SCB_CleanInvalidateDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /* select Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* clean & invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) | + ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief D-Cache Invalidate by address + \details Invalidates D-Cache for the given address. + D-Cache is invalidated starting from a 32 byte aligned address in 32 byte granularity. + D-Cache memory blocks which are part of given address + given size are invalidated. + \param[in] addr address + \param[in] dsize size of memory block (in number of bytes) +*/ +__STATIC_FORCEINLINE void SCB_InvalidateDCache_by_Addr (void *addr, int32_t dsize) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + if ( dsize > 0 ) { + int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U)); + uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */; + + __DSB(); + + do { + SCB->DCIMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */ + op_addr += __SCB_DCACHE_LINE_SIZE; + op_size -= __SCB_DCACHE_LINE_SIZE; + } while ( op_size > 0 ); + + __DSB(); + __ISB(); + } + #endif +} + + +/** + \brief D-Cache Clean by address + \details Cleans D-Cache for the given address + D-Cache is cleaned starting from a 32 byte aligned address in 32 byte granularity. + D-Cache memory blocks which are part of given address + given size are cleaned. + \param[in] addr address + \param[in] dsize size of memory block (in number of bytes) +*/ +__STATIC_FORCEINLINE void SCB_CleanDCache_by_Addr (uint32_t *addr, int32_t dsize) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + if ( dsize > 0 ) { + int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U)); + uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */; + + __DSB(); + + do { + SCB->DCCMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */ + op_addr += __SCB_DCACHE_LINE_SIZE; + op_size -= __SCB_DCACHE_LINE_SIZE; + } while ( op_size > 0 ); + + __DSB(); + __ISB(); + } + #endif +} + + +/** + \brief D-Cache Clean and Invalidate by address + \details Cleans and invalidates D_Cache for the given address + D-Cache is cleaned and invalidated starting from a 32 byte aligned address in 32 byte granularity. + D-Cache memory blocks which are part of given address + given size are cleaned and invalidated. + \param[in] addr address (aligned to 32-byte boundary) + \param[in] dsize size of memory block (in number of bytes) +*/ +__STATIC_FORCEINLINE void SCB_CleanInvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + if ( dsize > 0 ) { + int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U)); + uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */; + + __DSB(); + + do { + SCB->DCCIMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */ + op_addr += __SCB_DCACHE_LINE_SIZE; + op_size -= __SCB_DCACHE_LINE_SIZE; + } while ( op_size > 0 ); + + __DSB(); + __ISB(); + } + #endif +} + +/*@} end of CMSIS_Core_CacheFunctions */ +#endif + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_STAR_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/CMSIS/Core/Include/mpu_armv7.h b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/CMSIS/Core/Include/mpu_armv7.h new file mode 100644 index 0000000000..9909f83990 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/CMSIS/Core/Include/mpu_armv7.h @@ -0,0 +1,275 @@ +/****************************************************************************** + * @file mpu_armv7.h + * @brief CMSIS MPU API for Armv7-M MPU + * @version V5.1.2 + * @date 25. May 2020 + ******************************************************************************/ +/* + * Copyright (c) 2017-2020 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef ARM_MPU_ARMV7_H +#define ARM_MPU_ARMV7_H + +#define ARM_MPU_REGION_SIZE_32B ((uint8_t)0x04U) ///!< MPU Region Size 32 Bytes +#define ARM_MPU_REGION_SIZE_64B ((uint8_t)0x05U) ///!< MPU Region Size 64 Bytes +#define ARM_MPU_REGION_SIZE_128B ((uint8_t)0x06U) ///!< MPU Region Size 128 Bytes +#define ARM_MPU_REGION_SIZE_256B ((uint8_t)0x07U) ///!< MPU Region Size 256 Bytes +#define ARM_MPU_REGION_SIZE_512B ((uint8_t)0x08U) ///!< MPU Region Size 512 Bytes +#define ARM_MPU_REGION_SIZE_1KB ((uint8_t)0x09U) ///!< MPU Region Size 1 KByte +#define ARM_MPU_REGION_SIZE_2KB ((uint8_t)0x0AU) ///!< MPU Region Size 2 KBytes +#define ARM_MPU_REGION_SIZE_4KB ((uint8_t)0x0BU) ///!< MPU Region Size 4 KBytes +#define ARM_MPU_REGION_SIZE_8KB ((uint8_t)0x0CU) ///!< MPU Region Size 8 KBytes +#define ARM_MPU_REGION_SIZE_16KB ((uint8_t)0x0DU) ///!< MPU Region Size 16 KBytes +#define ARM_MPU_REGION_SIZE_32KB ((uint8_t)0x0EU) ///!< MPU Region Size 32 KBytes +#define ARM_MPU_REGION_SIZE_64KB ((uint8_t)0x0FU) ///!< MPU Region Size 64 KBytes +#define ARM_MPU_REGION_SIZE_128KB ((uint8_t)0x10U) ///!< MPU Region Size 128 KBytes +#define ARM_MPU_REGION_SIZE_256KB ((uint8_t)0x11U) ///!< MPU Region Size 256 KBytes +#define ARM_MPU_REGION_SIZE_512KB ((uint8_t)0x12U) ///!< MPU Region Size 512 KBytes +#define ARM_MPU_REGION_SIZE_1MB ((uint8_t)0x13U) ///!< MPU Region Size 1 MByte +#define ARM_MPU_REGION_SIZE_2MB ((uint8_t)0x14U) ///!< MPU Region Size 2 MBytes +#define ARM_MPU_REGION_SIZE_4MB ((uint8_t)0x15U) ///!< MPU Region Size 4 MBytes +#define ARM_MPU_REGION_SIZE_8MB ((uint8_t)0x16U) ///!< MPU Region Size 8 MBytes +#define ARM_MPU_REGION_SIZE_16MB ((uint8_t)0x17U) ///!< MPU Region Size 16 MBytes +#define ARM_MPU_REGION_SIZE_32MB ((uint8_t)0x18U) ///!< MPU Region Size 32 MBytes +#define ARM_MPU_REGION_SIZE_64MB ((uint8_t)0x19U) ///!< MPU Region Size 64 MBytes +#define ARM_MPU_REGION_SIZE_128MB ((uint8_t)0x1AU) ///!< MPU Region Size 128 MBytes +#define ARM_MPU_REGION_SIZE_256MB ((uint8_t)0x1BU) ///!< MPU Region Size 256 MBytes +#define ARM_MPU_REGION_SIZE_512MB ((uint8_t)0x1CU) ///!< MPU Region Size 512 MBytes +#define ARM_MPU_REGION_SIZE_1GB ((uint8_t)0x1DU) ///!< MPU Region Size 1 GByte +#define ARM_MPU_REGION_SIZE_2GB ((uint8_t)0x1EU) ///!< MPU Region Size 2 GBytes +#define ARM_MPU_REGION_SIZE_4GB ((uint8_t)0x1FU) ///!< MPU Region Size 4 GBytes + +#define ARM_MPU_AP_NONE 0U ///!< MPU Access Permission no access +#define ARM_MPU_AP_PRIV 1U ///!< MPU Access Permission privileged access only +#define ARM_MPU_AP_URO 2U ///!< MPU Access Permission unprivileged access read-only +#define ARM_MPU_AP_FULL 3U ///!< MPU Access Permission full access +#define ARM_MPU_AP_PRO 5U ///!< MPU Access Permission privileged access read-only +#define ARM_MPU_AP_RO 6U ///!< MPU Access Permission read-only access + +/** MPU Region Base Address Register Value +* +* \param Region The region to be configured, number 0 to 15. +* \param BaseAddress The base address for the region. +*/ +#define ARM_MPU_RBAR(Region, BaseAddress) \ + (((BaseAddress) & MPU_RBAR_ADDR_Msk) | \ + ((Region) & MPU_RBAR_REGION_Msk) | \ + (MPU_RBAR_VALID_Msk)) + +/** +* MPU Memory Access Attributes +* +* \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral. +* \param IsShareable Region is shareable between multiple bus masters. +* \param IsCacheable Region is cacheable, i.e. its value may be kept in cache. +* \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy. +*/ +#define ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable) \ + ((((TypeExtField) << MPU_RASR_TEX_Pos) & MPU_RASR_TEX_Msk) | \ + (((IsShareable) << MPU_RASR_S_Pos) & MPU_RASR_S_Msk) | \ + (((IsCacheable) << MPU_RASR_C_Pos) & MPU_RASR_C_Msk) | \ + (((IsBufferable) << MPU_RASR_B_Pos) & MPU_RASR_B_Msk)) + +/** +* MPU Region Attribute and Size Register Value +* +* \param DisableExec Instruction access disable bit, 1= disable instruction fetches. +* \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode. +* \param AccessAttributes Memory access attribution, see \ref ARM_MPU_ACCESS_. +* \param SubRegionDisable Sub-region disable field. +* \param Size Region size of the region to be configured, for example 4K, 8K. +*/ +#define ARM_MPU_RASR_EX(DisableExec, AccessPermission, AccessAttributes, SubRegionDisable, Size) \ + ((((DisableExec) << MPU_RASR_XN_Pos) & MPU_RASR_XN_Msk) | \ + (((AccessPermission) << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk) | \ + (((AccessAttributes) & (MPU_RASR_TEX_Msk | MPU_RASR_S_Msk | MPU_RASR_C_Msk | MPU_RASR_B_Msk))) | \ + (((SubRegionDisable) << MPU_RASR_SRD_Pos) & MPU_RASR_SRD_Msk) | \ + (((Size) << MPU_RASR_SIZE_Pos) & MPU_RASR_SIZE_Msk) | \ + (((MPU_RASR_ENABLE_Msk)))) + +/** +* MPU Region Attribute and Size Register Value +* +* \param DisableExec Instruction access disable bit, 1= disable instruction fetches. +* \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode. +* \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral. +* \param IsShareable Region is shareable between multiple bus masters. +* \param IsCacheable Region is cacheable, i.e. its value may be kept in cache. +* \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy. +* \param SubRegionDisable Sub-region disable field. +* \param Size Region size of the region to be configured, for example 4K, 8K. +*/ +#define ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable, SubRegionDisable, Size) \ + ARM_MPU_RASR_EX(DisableExec, AccessPermission, ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable), SubRegionDisable, Size) + +/** +* MPU Memory Access Attribute for strongly ordered memory. +* - TEX: 000b +* - Shareable +* - Non-cacheable +* - Non-bufferable +*/ +#define ARM_MPU_ACCESS_ORDERED ARM_MPU_ACCESS_(0U, 1U, 0U, 0U) + +/** +* MPU Memory Access Attribute for device memory. +* - TEX: 000b (if shareable) or 010b (if non-shareable) +* - Shareable or non-shareable +* - Non-cacheable +* - Bufferable (if shareable) or non-bufferable (if non-shareable) +* +* \param IsShareable Configures the device memory as shareable or non-shareable. +*/ +#define ARM_MPU_ACCESS_DEVICE(IsShareable) ((IsShareable) ? ARM_MPU_ACCESS_(0U, 1U, 0U, 1U) : ARM_MPU_ACCESS_(2U, 0U, 0U, 0U)) + +/** +* MPU Memory Access Attribute for normal memory. +* - TEX: 1BBb (reflecting outer cacheability rules) +* - Shareable or non-shareable +* - Cacheable or non-cacheable (reflecting inner cacheability rules) +* - Bufferable or non-bufferable (reflecting inner cacheability rules) +* +* \param OuterCp Configures the outer cache policy. +* \param InnerCp Configures the inner cache policy. +* \param IsShareable Configures the memory as shareable or non-shareable. +*/ +#define ARM_MPU_ACCESS_NORMAL(OuterCp, InnerCp, IsShareable) ARM_MPU_ACCESS_((4U | (OuterCp)), IsShareable, ((InnerCp) >> 1U), ((InnerCp) & 1U)) + +/** +* MPU Memory Access Attribute non-cacheable policy. +*/ +#define ARM_MPU_CACHEP_NOCACHE 0U + +/** +* MPU Memory Access Attribute write-back, write and read allocate policy. +*/ +#define ARM_MPU_CACHEP_WB_WRA 1U + +/** +* MPU Memory Access Attribute write-through, no write allocate policy. +*/ +#define ARM_MPU_CACHEP_WT_NWA 2U + +/** +* MPU Memory Access Attribute write-back, no write allocate policy. +*/ +#define ARM_MPU_CACHEP_WB_NWA 3U + + +/** +* Struct for a single MPU Region +*/ +typedef struct { + uint32_t RBAR; //!< The region base address register value (RBAR) + uint32_t RASR; //!< The region attribute and size register value (RASR) \ref MPU_RASR +} ARM_MPU_Region_t; + +/** Enable the MPU. +* \param MPU_Control Default access permissions for unconfigured regions. +*/ +__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control) +{ + __DMB(); + MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; +#endif + __DSB(); + __ISB(); +} + +/** Disable the MPU. +*/ +__STATIC_INLINE void ARM_MPU_Disable(void) +{ + __DMB(); +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; +#endif + MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk; + __DSB(); + __ISB(); +} + +/** Clear and disable the given MPU region. +* \param rnr Region number to be cleared. +*/ +__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr) +{ + MPU->RNR = rnr; + MPU->RASR = 0U; +} + +/** Configure an MPU region. +* \param rbar Value for RBAR register. +* \param rasr Value for RASR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rbar, uint32_t rasr) +{ + MPU->RBAR = rbar; + MPU->RASR = rasr; +} + +/** Configure the given MPU region. +* \param rnr Region number to be configured. +* \param rbar Value for RBAR register. +* \param rasr Value for RASR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegionEx(uint32_t rnr, uint32_t rbar, uint32_t rasr) +{ + MPU->RNR = rnr; + MPU->RBAR = rbar; + MPU->RASR = rasr; +} + +/** Memcpy with strictly ordered memory access, e.g. used by code in ARM_MPU_Load(). +* \param dst Destination data is copied to. +* \param src Source data is copied from. +* \param len Amount of data words to be copied. +*/ +__STATIC_INLINE void ARM_MPU_OrderedMemcpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len) +{ + uint32_t i; + for (i = 0U; i < len; ++i) + { + dst[i] = src[i]; + } +} + +/** Load the given number of MPU regions from a table. +* \param table Pointer to the MPU configuration table. +* \param cnt Amount of regions to be configured. +*/ +__STATIC_INLINE void ARM_MPU_Load(ARM_MPU_Region_t const* table, uint32_t cnt) +{ + const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U; + while (cnt > MPU_TYPE_RALIASES) { + ARM_MPU_OrderedMemcpy(&(MPU->RBAR), &(table->RBAR), MPU_TYPE_RALIASES*rowWordSize); + table += MPU_TYPE_RALIASES; + cnt -= MPU_TYPE_RALIASES; + } + ARM_MPU_OrderedMemcpy(&(MPU->RBAR), &(table->RBAR), cnt*rowWordSize); +} + +#endif diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/CMSIS/Core/Include/mpu_armv8.h b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/CMSIS/Core/Include/mpu_armv8.h new file mode 100644 index 0000000000..19855b9667 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/CMSIS/Core/Include/mpu_armv8.h @@ -0,0 +1,352 @@ +/****************************************************************************** + * @file mpu_armv8.h + * @brief CMSIS MPU API for Armv8-M and Armv8.1-M MPU + * @version V5.1.3 + * @date 03. February 2021 + ******************************************************************************/ +/* + * Copyright (c) 2017-2021 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef ARM_MPU_ARMV8_H +#define ARM_MPU_ARMV8_H + +/** \brief Attribute for device memory (outer only) */ +#define ARM_MPU_ATTR_DEVICE ( 0U ) + +/** \brief Attribute for non-cacheable, normal memory */ +#define ARM_MPU_ATTR_NON_CACHEABLE ( 4U ) + +/** \brief Attribute for normal memory (outer and inner) +* \param NT Non-Transient: Set to 1 for non-transient data. +* \param WB Write-Back: Set to 1 to use write-back update policy. +* \param RA Read Allocation: Set to 1 to use cache allocation on read miss. +* \param WA Write Allocation: Set to 1 to use cache allocation on write miss. +*/ +#define ARM_MPU_ATTR_MEMORY_(NT, WB, RA, WA) \ + ((((NT) & 1U) << 3U) | (((WB) & 1U) << 2U) | (((RA) & 1U) << 1U) | ((WA) & 1U)) + +/** \brief Device memory type non Gathering, non Re-ordering, non Early Write Acknowledgement */ +#define ARM_MPU_ATTR_DEVICE_nGnRnE (0U) + +/** \brief Device memory type non Gathering, non Re-ordering, Early Write Acknowledgement */ +#define ARM_MPU_ATTR_DEVICE_nGnRE (1U) + +/** \brief Device memory type non Gathering, Re-ordering, Early Write Acknowledgement */ +#define ARM_MPU_ATTR_DEVICE_nGRE (2U) + +/** \brief Device memory type Gathering, Re-ordering, Early Write Acknowledgement */ +#define ARM_MPU_ATTR_DEVICE_GRE (3U) + +/** \brief Memory Attribute +* \param O Outer memory attributes +* \param I O == ARM_MPU_ATTR_DEVICE: Device memory attributes, else: Inner memory attributes +*/ +#define ARM_MPU_ATTR(O, I) ((((O) & 0xFU) << 4U) | ((((O) & 0xFU) != 0U) ? ((I) & 0xFU) : (((I) & 0x3U) << 2U))) + +/** \brief Normal memory non-shareable */ +#define ARM_MPU_SH_NON (0U) + +/** \brief Normal memory outer shareable */ +#define ARM_MPU_SH_OUTER (2U) + +/** \brief Normal memory inner shareable */ +#define ARM_MPU_SH_INNER (3U) + +/** \brief Memory access permissions +* \param RO Read-Only: Set to 1 for read-only memory. +* \param NP Non-Privileged: Set to 1 for non-privileged memory. +*/ +#define ARM_MPU_AP_(RO, NP) ((((RO) & 1U) << 1U) | ((NP) & 1U)) + +/** \brief Region Base Address Register value +* \param BASE The base address bits [31:5] of a memory region. The value is zero extended. Effective address gets 32 byte aligned. +* \param SH Defines the Shareability domain for this memory region. +* \param RO Read-Only: Set to 1 for a read-only memory region. +* \param NP Non-Privileged: Set to 1 for a non-privileged memory region. +* \oaram XN eXecute Never: Set to 1 for a non-executable memory region. +*/ +#define ARM_MPU_RBAR(BASE, SH, RO, NP, XN) \ + (((BASE) & MPU_RBAR_BASE_Msk) | \ + (((SH) << MPU_RBAR_SH_Pos) & MPU_RBAR_SH_Msk) | \ + ((ARM_MPU_AP_(RO, NP) << MPU_RBAR_AP_Pos) & MPU_RBAR_AP_Msk) | \ + (((XN) << MPU_RBAR_XN_Pos) & MPU_RBAR_XN_Msk)) + +/** \brief Region Limit Address Register value +* \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended. +* \param IDX The attribute index to be associated with this memory region. +*/ +#define ARM_MPU_RLAR(LIMIT, IDX) \ + (((LIMIT) & MPU_RLAR_LIMIT_Msk) | \ + (((IDX) << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \ + (MPU_RLAR_EN_Msk)) + +#if defined(MPU_RLAR_PXN_Pos) + +/** \brief Region Limit Address Register with PXN value +* \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended. +* \param PXN Privileged execute never. Defines whether code can be executed from this privileged region. +* \param IDX The attribute index to be associated with this memory region. +*/ +#define ARM_MPU_RLAR_PXN(LIMIT, PXN, IDX) \ + (((LIMIT) & MPU_RLAR_LIMIT_Msk) | \ + (((PXN) << MPU_RLAR_PXN_Pos) & MPU_RLAR_PXN_Msk) | \ + (((IDX) << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \ + (MPU_RLAR_EN_Msk)) + +#endif + +/** +* Struct for a single MPU Region +*/ +typedef struct { + uint32_t RBAR; /*!< Region Base Address Register value */ + uint32_t RLAR; /*!< Region Limit Address Register value */ +} ARM_MPU_Region_t; + +/** Enable the MPU. +* \param MPU_Control Default access permissions for unconfigured regions. +*/ +__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control) +{ + __DMB(); + MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; +#endif + __DSB(); + __ISB(); +} + +/** Disable the MPU. +*/ +__STATIC_INLINE void ARM_MPU_Disable(void) +{ + __DMB(); +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; +#endif + MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk; + __DSB(); + __ISB(); +} + +#ifdef MPU_NS +/** Enable the Non-secure MPU. +* \param MPU_Control Default access permissions for unconfigured regions. +*/ +__STATIC_INLINE void ARM_MPU_Enable_NS(uint32_t MPU_Control) +{ + __DMB(); + MPU_NS->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB_NS->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; +#endif + __DSB(); + __ISB(); +} + +/** Disable the Non-secure MPU. +*/ +__STATIC_INLINE void ARM_MPU_Disable_NS(void) +{ + __DMB(); +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB_NS->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; +#endif + MPU_NS->CTRL &= ~MPU_CTRL_ENABLE_Msk; + __DSB(); + __ISB(); +} +#endif + +/** Set the memory attribute encoding to the given MPU. +* \param mpu Pointer to the MPU to be configured. +* \param idx The attribute index to be set [0-7] +* \param attr The attribute value to be set. +*/ +__STATIC_INLINE void ARM_MPU_SetMemAttrEx(MPU_Type* mpu, uint8_t idx, uint8_t attr) +{ + const uint8_t reg = idx / 4U; + const uint32_t pos = ((idx % 4U) * 8U); + const uint32_t mask = 0xFFU << pos; + + if (reg >= (sizeof(mpu->MAIR) / sizeof(mpu->MAIR[0]))) { + return; // invalid index + } + + mpu->MAIR[reg] = ((mpu->MAIR[reg] & ~mask) | ((attr << pos) & mask)); +} + +/** Set the memory attribute encoding. +* \param idx The attribute index to be set [0-7] +* \param attr The attribute value to be set. +*/ +__STATIC_INLINE void ARM_MPU_SetMemAttr(uint8_t idx, uint8_t attr) +{ + ARM_MPU_SetMemAttrEx(MPU, idx, attr); +} + +#ifdef MPU_NS +/** Set the memory attribute encoding to the Non-secure MPU. +* \param idx The attribute index to be set [0-7] +* \param attr The attribute value to be set. +*/ +__STATIC_INLINE void ARM_MPU_SetMemAttr_NS(uint8_t idx, uint8_t attr) +{ + ARM_MPU_SetMemAttrEx(MPU_NS, idx, attr); +} +#endif + +/** Clear and disable the given MPU region of the given MPU. +* \param mpu Pointer to MPU to be used. +* \param rnr Region number to be cleared. +*/ +__STATIC_INLINE void ARM_MPU_ClrRegionEx(MPU_Type* mpu, uint32_t rnr) +{ + mpu->RNR = rnr; + mpu->RLAR = 0U; +} + +/** Clear and disable the given MPU region. +* \param rnr Region number to be cleared. +*/ +__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr) +{ + ARM_MPU_ClrRegionEx(MPU, rnr); +} + +#ifdef MPU_NS +/** Clear and disable the given Non-secure MPU region. +* \param rnr Region number to be cleared. +*/ +__STATIC_INLINE void ARM_MPU_ClrRegion_NS(uint32_t rnr) +{ + ARM_MPU_ClrRegionEx(MPU_NS, rnr); +} +#endif + +/** Configure the given MPU region of the given MPU. +* \param mpu Pointer to MPU to be used. +* \param rnr Region number to be configured. +* \param rbar Value for RBAR register. +* \param rlar Value for RLAR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegionEx(MPU_Type* mpu, uint32_t rnr, uint32_t rbar, uint32_t rlar) +{ + mpu->RNR = rnr; + mpu->RBAR = rbar; + mpu->RLAR = rlar; +} + +/** Configure the given MPU region. +* \param rnr Region number to be configured. +* \param rbar Value for RBAR register. +* \param rlar Value for RLAR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rnr, uint32_t rbar, uint32_t rlar) +{ + ARM_MPU_SetRegionEx(MPU, rnr, rbar, rlar); +} + +#ifdef MPU_NS +/** Configure the given Non-secure MPU region. +* \param rnr Region number to be configured. +* \param rbar Value for RBAR register. +* \param rlar Value for RLAR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegion_NS(uint32_t rnr, uint32_t rbar, uint32_t rlar) +{ + ARM_MPU_SetRegionEx(MPU_NS, rnr, rbar, rlar); +} +#endif + +/** Memcpy with strictly ordered memory access, e.g. used by code in ARM_MPU_LoadEx() +* \param dst Destination data is copied to. +* \param src Source data is copied from. +* \param len Amount of data words to be copied. +*/ +__STATIC_INLINE void ARM_MPU_OrderedMemcpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len) +{ + uint32_t i; + for (i = 0U; i < len; ++i) + { + dst[i] = src[i]; + } +} + +/** Load the given number of MPU regions from a table to the given MPU. +* \param mpu Pointer to the MPU registers to be used. +* \param rnr First region number to be configured. +* \param table Pointer to the MPU configuration table. +* \param cnt Amount of regions to be configured. +*/ +__STATIC_INLINE void ARM_MPU_LoadEx(MPU_Type* mpu, uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) +{ + const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U; + if (cnt == 1U) { + mpu->RNR = rnr; + ARM_MPU_OrderedMemcpy(&(mpu->RBAR), &(table->RBAR), rowWordSize); + } else { + uint32_t rnrBase = rnr & ~(MPU_TYPE_RALIASES-1U); + uint32_t rnrOffset = rnr % MPU_TYPE_RALIASES; + + mpu->RNR = rnrBase; + while ((rnrOffset + cnt) > MPU_TYPE_RALIASES) { + uint32_t c = MPU_TYPE_RALIASES - rnrOffset; + ARM_MPU_OrderedMemcpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), c*rowWordSize); + table += c; + cnt -= c; + rnrOffset = 0U; + rnrBase += MPU_TYPE_RALIASES; + mpu->RNR = rnrBase; + } + + ARM_MPU_OrderedMemcpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), cnt*rowWordSize); + } +} + +/** Load the given number of MPU regions from a table. +* \param rnr First region number to be configured. +* \param table Pointer to the MPU configuration table. +* \param cnt Amount of regions to be configured. +*/ +__STATIC_INLINE void ARM_MPU_Load(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) +{ + ARM_MPU_LoadEx(MPU, rnr, table, cnt); +} + +#ifdef MPU_NS +/** Load the given number of MPU regions from a table to the Non-secure MPU. +* \param rnr First region number to be configured. +* \param table Pointer to the MPU configuration table. +* \param cnt Amount of regions to be configured. +*/ +__STATIC_INLINE void ARM_MPU_Load_NS(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) +{ + ARM_MPU_LoadEx(MPU_NS, rnr, table, cnt); +} +#endif + +#endif + diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/CMSIS/Core/Include/pac_armv81.h b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/CMSIS/Core/Include/pac_armv81.h new file mode 100644 index 0000000000..854b60a204 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/CMSIS/Core/Include/pac_armv81.h @@ -0,0 +1,206 @@ +/****************************************************************************** + * @file pac_armv81.h + * @brief CMSIS PAC key functions for Armv8.1-M PAC extension + * @version V1.0.0 + * @date 23. March 2022 + ******************************************************************************/ +/* + * Copyright (c) 2022 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef PAC_ARMV81_H +#define PAC_ARMV81_H + + +/* ################### PAC Key functions ########################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_PacKeyFunctions PAC Key functions + \brief Functions that access the PAC keys. + @{ + */ + +#if (defined (__ARM_FEATURE_PAUTH) && (__ARM_FEATURE_PAUTH == 1)) + +/** + \brief read the PAC key used for privileged mode + \details Reads the PAC key stored in the PAC_KEY_P registers. + \param [out] pPacKey 128bit PAC key + */ +__STATIC_FORCEINLINE void __get_PAC_KEY_P (uint32_t* pPacKey) { + __ASM volatile ( + "mrs r1, pac_key_p_0\n" + "str r1,[%0,#0]\n" + "mrs r1, pac_key_p_1\n" + "str r1,[%0,#4]\n" + "mrs r1, pac_key_p_2\n" + "str r1,[%0,#8]\n" + "mrs r1, pac_key_p_3\n" + "str r1,[%0,#12]\n" + : : "r" (pPacKey) : "memory", "r1" + ); +} + +/** + \brief write the PAC key used for privileged mode + \details writes the given PAC key to the PAC_KEY_P registers. + \param [in] pPacKey 128bit PAC key + */ +__STATIC_FORCEINLINE void __set_PAC_KEY_P (uint32_t* pPacKey) { + __ASM volatile ( + "ldr r1,[%0,#0]\n" + "msr pac_key_p_0, r1\n" + "ldr r1,[%0,#4]\n" + "msr pac_key_p_1, r1\n" + "ldr r1,[%0,#8]\n" + "msr pac_key_p_2, r1\n" + "ldr r1,[%0,#12]\n" + "msr pac_key_p_3, r1\n" + : : "r" (pPacKey) : "memory", "r1" + ); +} + +/** + \brief read the PAC key used for unprivileged mode + \details Reads the PAC key stored in the PAC_KEY_U registers. + \param [out] pPacKey 128bit PAC key + */ +__STATIC_FORCEINLINE void __get_PAC_KEY_U (uint32_t* pPacKey) { + __ASM volatile ( + "mrs r1, pac_key_u_0\n" + "str r1,[%0,#0]\n" + "mrs r1, pac_key_u_1\n" + "str r1,[%0,#4]\n" + "mrs r1, pac_key_u_2\n" + "str r1,[%0,#8]\n" + "mrs r1, pac_key_u_3\n" + "str r1,[%0,#12]\n" + : : "r" (pPacKey) : "memory", "r1" + ); +} + +/** + \brief write the PAC key used for unprivileged mode + \details writes the given PAC key to the PAC_KEY_U registers. + \param [in] pPacKey 128bit PAC key + */ +__STATIC_FORCEINLINE void __set_PAC_KEY_U (uint32_t* pPacKey) { + __ASM volatile ( + "ldr r1,[%0,#0]\n" + "msr pac_key_u_0, r1\n" + "ldr r1,[%0,#4]\n" + "msr pac_key_u_1, r1\n" + "ldr r1,[%0,#8]\n" + "msr pac_key_u_2, r1\n" + "ldr r1,[%0,#12]\n" + "msr pac_key_u_3, r1\n" + : : "r" (pPacKey) : "memory", "r1" + ); +} + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + +/** + \brief read the PAC key used for privileged mode (non-secure) + \details Reads the PAC key stored in the non-secure PAC_KEY_P registers when in secure mode. + \param [out] pPacKey 128bit PAC key + */ +__STATIC_FORCEINLINE void __TZ_get_PAC_KEY_P_NS (uint32_t* pPacKey) { + __ASM volatile ( + "mrs r1, pac_key_p_0_ns\n" + "str r1,[%0,#0]\n" + "mrs r1, pac_key_p_1_ns\n" + "str r1,[%0,#4]\n" + "mrs r1, pac_key_p_2_ns\n" + "str r1,[%0,#8]\n" + "mrs r1, pac_key_p_3_ns\n" + "str r1,[%0,#12]\n" + : : "r" (pPacKey) : "memory", "r1" + ); +} + +/** + \brief write the PAC key used for privileged mode (non-secure) + \details writes the given PAC key to the non-secure PAC_KEY_P registers when in secure mode. + \param [in] pPacKey 128bit PAC key + */ +__STATIC_FORCEINLINE void __TZ_set_PAC_KEY_P_NS (uint32_t* pPacKey) { + __ASM volatile ( + "ldr r1,[%0,#0]\n" + "msr pac_key_p_0_ns, r1\n" + "ldr r1,[%0,#4]\n" + "msr pac_key_p_1_ns, r1\n" + "ldr r1,[%0,#8]\n" + "msr pac_key_p_2_ns, r1\n" + "ldr r1,[%0,#12]\n" + "msr pac_key_p_3_ns, r1\n" + : : "r" (pPacKey) : "memory", "r1" + ); +} + +/** + \brief read the PAC key used for unprivileged mode (non-secure) + \details Reads the PAC key stored in the non-secure PAC_KEY_U registers when in secure mode. + \param [out] pPacKey 128bit PAC key + */ +__STATIC_FORCEINLINE void __TZ_get_PAC_KEY_U_NS (uint32_t* pPacKey) { + __ASM volatile ( + "mrs r1, pac_key_u_0_ns\n" + "str r1,[%0,#0]\n" + "mrs r1, pac_key_u_1_ns\n" + "str r1,[%0,#4]\n" + "mrs r1, pac_key_u_2_ns\n" + "str r1,[%0,#8]\n" + "mrs r1, pac_key_u_3_ns\n" + "str r1,[%0,#12]\n" + : : "r" (pPacKey) : "memory", "r1" + ); +} + +/** + \brief write the PAC key used for unprivileged mode (non-secure) + \details writes the given PAC key to the non-secure PAC_KEY_U registers when in secure mode. + \param [in] pPacKey 128bit PAC key + */ +__STATIC_FORCEINLINE void __TZ_set_PAC_KEY_U_NS (uint32_t* pPacKey) { + __ASM volatile ( + "ldr r1,[%0,#0]\n" + "msr pac_key_u_0_ns, r1\n" + "ldr r1,[%0,#4]\n" + "msr pac_key_u_1_ns, r1\n" + "ldr r1,[%0,#8]\n" + "msr pac_key_u_2_ns, r1\n" + "ldr r1,[%0,#12]\n" + "msr pac_key_u_3_ns, r1\n" + : : "r" (pPacKey) : "memory", "r1" + ); +} + +#endif /* (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) */ + +#endif /* (defined (__ARM_FEATURE_PAUTH) && (__ARM_FEATURE_PAUTH == 1)) */ + +/*@} end of CMSIS_Core_PacKeyFunctions */ + + +#endif /* PAC_ARMV81_H */ diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/CMSIS/Core/Include/pmu_armv8.h b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/CMSIS/Core/Include/pmu_armv8.h new file mode 100644 index 0000000000..aa53bb47c1 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/CMSIS/Core/Include/pmu_armv8.h @@ -0,0 +1,337 @@ +/****************************************************************************** + * @file pmu_armv8.h + * @brief CMSIS PMU API for Armv8.1-M PMU + * @version V1.0.1 + * @date 15. April 2020 + ******************************************************************************/ +/* + * Copyright (c) 2020 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef ARM_PMU_ARMV8_H +#define ARM_PMU_ARMV8_H + +/** + * \brief PMU Events + * \note See the Armv8.1-M Architecture Reference Manual for full details on these PMU events. + * */ + +#define ARM_PMU_SW_INCR 0x0000 /*!< Software update to the PMU_SWINC register, architecturally executed and condition code check pass */ +#define ARM_PMU_L1I_CACHE_REFILL 0x0001 /*!< L1 I-Cache refill */ +#define ARM_PMU_L1D_CACHE_REFILL 0x0003 /*!< L1 D-Cache refill */ +#define ARM_PMU_L1D_CACHE 0x0004 /*!< L1 D-Cache access */ +#define ARM_PMU_LD_RETIRED 0x0006 /*!< Memory-reading instruction architecturally executed and condition code check pass */ +#define ARM_PMU_ST_RETIRED 0x0007 /*!< Memory-writing instruction architecturally executed and condition code check pass */ +#define ARM_PMU_INST_RETIRED 0x0008 /*!< Instruction architecturally executed */ +#define ARM_PMU_EXC_TAKEN 0x0009 /*!< Exception entry */ +#define ARM_PMU_EXC_RETURN 0x000A /*!< Exception return instruction architecturally executed and the condition code check pass */ +#define ARM_PMU_PC_WRITE_RETIRED 0x000C /*!< Software change to the Program Counter (PC). Instruction is architecturally executed and condition code check pass */ +#define ARM_PMU_BR_IMMED_RETIRED 0x000D /*!< Immediate branch architecturally executed */ +#define ARM_PMU_BR_RETURN_RETIRED 0x000E /*!< Function return instruction architecturally executed and the condition code check pass */ +#define ARM_PMU_UNALIGNED_LDST_RETIRED 0x000F /*!< Unaligned memory memory-reading or memory-writing instruction architecturally executed and condition code check pass */ +#define ARM_PMU_BR_MIS_PRED 0x0010 /*!< Mispredicted or not predicted branch speculatively executed */ +#define ARM_PMU_CPU_CYCLES 0x0011 /*!< Cycle */ +#define ARM_PMU_BR_PRED 0x0012 /*!< Predictable branch speculatively executed */ +#define ARM_PMU_MEM_ACCESS 0x0013 /*!< Data memory access */ +#define ARM_PMU_L1I_CACHE 0x0014 /*!< Level 1 instruction cache access */ +#define ARM_PMU_L1D_CACHE_WB 0x0015 /*!< Level 1 data cache write-back */ +#define ARM_PMU_L2D_CACHE 0x0016 /*!< Level 2 data cache access */ +#define ARM_PMU_L2D_CACHE_REFILL 0x0017 /*!< Level 2 data cache refill */ +#define ARM_PMU_L2D_CACHE_WB 0x0018 /*!< Level 2 data cache write-back */ +#define ARM_PMU_BUS_ACCESS 0x0019 /*!< Bus access */ +#define ARM_PMU_MEMORY_ERROR 0x001A /*!< Local memory error */ +#define ARM_PMU_INST_SPEC 0x001B /*!< Instruction speculatively executed */ +#define ARM_PMU_BUS_CYCLES 0x001D /*!< Bus cycles */ +#define ARM_PMU_CHAIN 0x001E /*!< For an odd numbered counter, increment when an overflow occurs on the preceding even-numbered counter on the same PE */ +#define ARM_PMU_L1D_CACHE_ALLOCATE 0x001F /*!< Level 1 data cache allocation without refill */ +#define ARM_PMU_L2D_CACHE_ALLOCATE 0x0020 /*!< Level 2 data cache allocation without refill */ +#define ARM_PMU_BR_RETIRED 0x0021 /*!< Branch instruction architecturally executed */ +#define ARM_PMU_BR_MIS_PRED_RETIRED 0x0022 /*!< Mispredicted branch instruction architecturally executed */ +#define ARM_PMU_STALL_FRONTEND 0x0023 /*!< No operation issued because of the frontend */ +#define ARM_PMU_STALL_BACKEND 0x0024 /*!< No operation issued because of the backend */ +#define ARM_PMU_L2I_CACHE 0x0027 /*!< Level 2 instruction cache access */ +#define ARM_PMU_L2I_CACHE_REFILL 0x0028 /*!< Level 2 instruction cache refill */ +#define ARM_PMU_L3D_CACHE_ALLOCATE 0x0029 /*!< Level 3 data cache allocation without refill */ +#define ARM_PMU_L3D_CACHE_REFILL 0x002A /*!< Level 3 data cache refill */ +#define ARM_PMU_L3D_CACHE 0x002B /*!< Level 3 data cache access */ +#define ARM_PMU_L3D_CACHE_WB 0x002C /*!< Level 3 data cache write-back */ +#define ARM_PMU_LL_CACHE_RD 0x0036 /*!< Last level data cache read */ +#define ARM_PMU_LL_CACHE_MISS_RD 0x0037 /*!< Last level data cache read miss */ +#define ARM_PMU_L1D_CACHE_MISS_RD 0x0039 /*!< Level 1 data cache read miss */ +#define ARM_PMU_OP_COMPLETE 0x003A /*!< Operation retired */ +#define ARM_PMU_OP_SPEC 0x003B /*!< Operation speculatively executed */ +#define ARM_PMU_STALL 0x003C /*!< Stall cycle for instruction or operation not sent for execution */ +#define ARM_PMU_STALL_OP_BACKEND 0x003D /*!< Stall cycle for instruction or operation not sent for execution due to pipeline backend */ +#define ARM_PMU_STALL_OP_FRONTEND 0x003E /*!< Stall cycle for instruction or operation not sent for execution due to pipeline frontend */ +#define ARM_PMU_STALL_OP 0x003F /*!< Instruction or operation slots not occupied each cycle */ +#define ARM_PMU_L1D_CACHE_RD 0x0040 /*!< Level 1 data cache read */ +#define ARM_PMU_LE_RETIRED 0x0100 /*!< Loop end instruction executed */ +#define ARM_PMU_LE_SPEC 0x0101 /*!< Loop end instruction speculatively executed */ +#define ARM_PMU_BF_RETIRED 0x0104 /*!< Branch future instruction architecturally executed and condition code check pass */ +#define ARM_PMU_BF_SPEC 0x0105 /*!< Branch future instruction speculatively executed and condition code check pass */ +#define ARM_PMU_LE_CANCEL 0x0108 /*!< Loop end instruction not taken */ +#define ARM_PMU_BF_CANCEL 0x0109 /*!< Branch future instruction not taken */ +#define ARM_PMU_SE_CALL_S 0x0114 /*!< Call to secure function, resulting in Security state change */ +#define ARM_PMU_SE_CALL_NS 0x0115 /*!< Call to non-secure function, resulting in Security state change */ +#define ARM_PMU_DWT_CMPMATCH0 0x0118 /*!< DWT comparator 0 match */ +#define ARM_PMU_DWT_CMPMATCH1 0x0119 /*!< DWT comparator 1 match */ +#define ARM_PMU_DWT_CMPMATCH2 0x011A /*!< DWT comparator 2 match */ +#define ARM_PMU_DWT_CMPMATCH3 0x011B /*!< DWT comparator 3 match */ +#define ARM_PMU_MVE_INST_RETIRED 0x0200 /*!< MVE instruction architecturally executed */ +#define ARM_PMU_MVE_INST_SPEC 0x0201 /*!< MVE instruction speculatively executed */ +#define ARM_PMU_MVE_FP_RETIRED 0x0204 /*!< MVE floating-point instruction architecturally executed */ +#define ARM_PMU_MVE_FP_SPEC 0x0205 /*!< MVE floating-point instruction speculatively executed */ +#define ARM_PMU_MVE_FP_HP_RETIRED 0x0208 /*!< MVE half-precision floating-point instruction architecturally executed */ +#define ARM_PMU_MVE_FP_HP_SPEC 0x0209 /*!< MVE half-precision floating-point instruction speculatively executed */ +#define ARM_PMU_MVE_FP_SP_RETIRED 0x020C /*!< MVE single-precision floating-point instruction architecturally executed */ +#define ARM_PMU_MVE_FP_SP_SPEC 0x020D /*!< MVE single-precision floating-point instruction speculatively executed */ +#define ARM_PMU_MVE_FP_MAC_RETIRED 0x0214 /*!< MVE floating-point multiply or multiply-accumulate instruction architecturally executed */ +#define ARM_PMU_MVE_FP_MAC_SPEC 0x0215 /*!< MVE floating-point multiply or multiply-accumulate instruction speculatively executed */ +#define ARM_PMU_MVE_INT_RETIRED 0x0224 /*!< MVE integer instruction architecturally executed */ +#define ARM_PMU_MVE_INT_SPEC 0x0225 /*!< MVE integer instruction speculatively executed */ +#define ARM_PMU_MVE_INT_MAC_RETIRED 0x0228 /*!< MVE multiply or multiply-accumulate instruction architecturally executed */ +#define ARM_PMU_MVE_INT_MAC_SPEC 0x0229 /*!< MVE multiply or multiply-accumulate instruction speculatively executed */ +#define ARM_PMU_MVE_LDST_RETIRED 0x0238 /*!< MVE load or store instruction architecturally executed */ +#define ARM_PMU_MVE_LDST_SPEC 0x0239 /*!< MVE load or store instruction speculatively executed */ +#define ARM_PMU_MVE_LD_RETIRED 0x023C /*!< MVE load instruction architecturally executed */ +#define ARM_PMU_MVE_LD_SPEC 0x023D /*!< MVE load instruction speculatively executed */ +#define ARM_PMU_MVE_ST_RETIRED 0x0240 /*!< MVE store instruction architecturally executed */ +#define ARM_PMU_MVE_ST_SPEC 0x0241 /*!< MVE store instruction speculatively executed */ +#define ARM_PMU_MVE_LDST_CONTIG_RETIRED 0x0244 /*!< MVE contiguous load or store instruction architecturally executed */ +#define ARM_PMU_MVE_LDST_CONTIG_SPEC 0x0245 /*!< MVE contiguous load or store instruction speculatively executed */ +#define ARM_PMU_MVE_LD_CONTIG_RETIRED 0x0248 /*!< MVE contiguous load instruction architecturally executed */ +#define ARM_PMU_MVE_LD_CONTIG_SPEC 0x0249 /*!< MVE contiguous load instruction speculatively executed */ +#define ARM_PMU_MVE_ST_CONTIG_RETIRED 0x024C /*!< MVE contiguous store instruction architecturally executed */ +#define ARM_PMU_MVE_ST_CONTIG_SPEC 0x024D /*!< MVE contiguous store instruction speculatively executed */ +#define ARM_PMU_MVE_LDST_NONCONTIG_RETIRED 0x0250 /*!< MVE non-contiguous load or store instruction architecturally executed */ +#define ARM_PMU_MVE_LDST_NONCONTIG_SPEC 0x0251 /*!< MVE non-contiguous load or store instruction speculatively executed */ +#define ARM_PMU_MVE_LD_NONCONTIG_RETIRED 0x0254 /*!< MVE non-contiguous load instruction architecturally executed */ +#define ARM_PMU_MVE_LD_NONCONTIG_SPEC 0x0255 /*!< MVE non-contiguous load instruction speculatively executed */ +#define ARM_PMU_MVE_ST_NONCONTIG_RETIRED 0x0258 /*!< MVE non-contiguous store instruction architecturally executed */ +#define ARM_PMU_MVE_ST_NONCONTIG_SPEC 0x0259 /*!< MVE non-contiguous store instruction speculatively executed */ +#define ARM_PMU_MVE_LDST_MULTI_RETIRED 0x025C /*!< MVE memory instruction targeting multiple registers architecturally executed */ +#define ARM_PMU_MVE_LDST_MULTI_SPEC 0x025D /*!< MVE memory instruction targeting multiple registers speculatively executed */ +#define ARM_PMU_MVE_LD_MULTI_RETIRED 0x0260 /*!< MVE memory load instruction targeting multiple registers architecturally executed */ +#define ARM_PMU_MVE_LD_MULTI_SPEC 0x0261 /*!< MVE memory load instruction targeting multiple registers speculatively executed */ +#define ARM_PMU_MVE_ST_MULTI_RETIRED 0x0261 /*!< MVE memory store instruction targeting multiple registers architecturally executed */ +#define ARM_PMU_MVE_ST_MULTI_SPEC 0x0265 /*!< MVE memory store instruction targeting multiple registers speculatively executed */ +#define ARM_PMU_MVE_LDST_UNALIGNED_RETIRED 0x028C /*!< MVE unaligned memory load or store instruction architecturally executed */ +#define ARM_PMU_MVE_LDST_UNALIGNED_SPEC 0x028D /*!< MVE unaligned memory load or store instruction speculatively executed */ +#define ARM_PMU_MVE_LD_UNALIGNED_RETIRED 0x0290 /*!< MVE unaligned load instruction architecturally executed */ +#define ARM_PMU_MVE_LD_UNALIGNED_SPEC 0x0291 /*!< MVE unaligned load instruction speculatively executed */ +#define ARM_PMU_MVE_ST_UNALIGNED_RETIRED 0x0294 /*!< MVE unaligned store instruction architecturally executed */ +#define ARM_PMU_MVE_ST_UNALIGNED_SPEC 0x0295 /*!< MVE unaligned store instruction speculatively executed */ +#define ARM_PMU_MVE_LDST_UNALIGNED_NONCONTIG_RETIRED 0x0298 /*!< MVE unaligned noncontiguous load or store instruction architecturally executed */ +#define ARM_PMU_MVE_LDST_UNALIGNED_NONCONTIG_SPEC 0x0299 /*!< MVE unaligned noncontiguous load or store instruction speculatively executed */ +#define ARM_PMU_MVE_VREDUCE_RETIRED 0x02A0 /*!< MVE vector reduction instruction architecturally executed */ +#define ARM_PMU_MVE_VREDUCE_SPEC 0x02A1 /*!< MVE vector reduction instruction speculatively executed */ +#define ARM_PMU_MVE_VREDUCE_FP_RETIRED 0x02A4 /*!< MVE floating-point vector reduction instruction architecturally executed */ +#define ARM_PMU_MVE_VREDUCE_FP_SPEC 0x02A5 /*!< MVE floating-point vector reduction instruction speculatively executed */ +#define ARM_PMU_MVE_VREDUCE_INT_RETIRED 0x02A8 /*!< MVE integer vector reduction instruction architecturally executed */ +#define ARM_PMU_MVE_VREDUCE_INT_SPEC 0x02A9 /*!< MVE integer vector reduction instruction speculatively executed */ +#define ARM_PMU_MVE_PRED 0x02B8 /*!< Cycles where one or more predicated beats architecturally executed */ +#define ARM_PMU_MVE_STALL 0x02CC /*!< Stall cycles caused by an MVE instruction */ +#define ARM_PMU_MVE_STALL_RESOURCE 0x02CD /*!< Stall cycles caused by an MVE instruction because of resource conflicts */ +#define ARM_PMU_MVE_STALL_RESOURCE_MEM 0x02CE /*!< Stall cycles caused by an MVE instruction because of memory resource conflicts */ +#define ARM_PMU_MVE_STALL_RESOURCE_FP 0x02CF /*!< Stall cycles caused by an MVE instruction because of floating-point resource conflicts */ +#define ARM_PMU_MVE_STALL_RESOURCE_INT 0x02D0 /*!< Stall cycles caused by an MVE instruction because of integer resource conflicts */ +#define ARM_PMU_MVE_STALL_BREAK 0x02D3 /*!< Stall cycles caused by an MVE chain break */ +#define ARM_PMU_MVE_STALL_DEPENDENCY 0x02D4 /*!< Stall cycles caused by MVE register dependency */ +#define ARM_PMU_ITCM_ACCESS 0x4007 /*!< Instruction TCM access */ +#define ARM_PMU_DTCM_ACCESS 0x4008 /*!< Data TCM access */ +#define ARM_PMU_TRCEXTOUT0 0x4010 /*!< ETM external output 0 */ +#define ARM_PMU_TRCEXTOUT1 0x4011 /*!< ETM external output 1 */ +#define ARM_PMU_TRCEXTOUT2 0x4012 /*!< ETM external output 2 */ +#define ARM_PMU_TRCEXTOUT3 0x4013 /*!< ETM external output 3 */ +#define ARM_PMU_CTI_TRIGOUT4 0x4018 /*!< Cross-trigger Interface output trigger 4 */ +#define ARM_PMU_CTI_TRIGOUT5 0x4019 /*!< Cross-trigger Interface output trigger 5 */ +#define ARM_PMU_CTI_TRIGOUT6 0x401A /*!< Cross-trigger Interface output trigger 6 */ +#define ARM_PMU_CTI_TRIGOUT7 0x401B /*!< Cross-trigger Interface output trigger 7 */ + +/** \brief PMU Functions */ + +__STATIC_INLINE void ARM_PMU_Enable(void); +__STATIC_INLINE void ARM_PMU_Disable(void); + +__STATIC_INLINE void ARM_PMU_Set_EVTYPER(uint32_t num, uint32_t type); + +__STATIC_INLINE void ARM_PMU_CYCCNT_Reset(void); +__STATIC_INLINE void ARM_PMU_EVCNTR_ALL_Reset(void); + +__STATIC_INLINE void ARM_PMU_CNTR_Enable(uint32_t mask); +__STATIC_INLINE void ARM_PMU_CNTR_Disable(uint32_t mask); + +__STATIC_INLINE uint32_t ARM_PMU_Get_CCNTR(void); +__STATIC_INLINE uint32_t ARM_PMU_Get_EVCNTR(uint32_t num); + +__STATIC_INLINE uint32_t ARM_PMU_Get_CNTR_OVS(void); +__STATIC_INLINE void ARM_PMU_Set_CNTR_OVS(uint32_t mask); + +__STATIC_INLINE void ARM_PMU_Set_CNTR_IRQ_Enable(uint32_t mask); +__STATIC_INLINE void ARM_PMU_Set_CNTR_IRQ_Disable(uint32_t mask); + +__STATIC_INLINE void ARM_PMU_CNTR_Increment(uint32_t mask); + +/** + \brief Enable the PMU +*/ +__STATIC_INLINE void ARM_PMU_Enable(void) +{ + PMU->CTRL |= PMU_CTRL_ENABLE_Msk; +} + +/** + \brief Disable the PMU +*/ +__STATIC_INLINE void ARM_PMU_Disable(void) +{ + PMU->CTRL &= ~PMU_CTRL_ENABLE_Msk; +} + +/** + \brief Set event to count for PMU eventer counter + \param [in] num Event counter (0-30) to configure + \param [in] type Event to count +*/ +__STATIC_INLINE void ARM_PMU_Set_EVTYPER(uint32_t num, uint32_t type) +{ + PMU->EVTYPER[num] = type; +} + +/** + \brief Reset cycle counter +*/ +__STATIC_INLINE void ARM_PMU_CYCCNT_Reset(void) +{ + PMU->CTRL |= PMU_CTRL_CYCCNT_RESET_Msk; +} + +/** + \brief Reset all event counters +*/ +__STATIC_INLINE void ARM_PMU_EVCNTR_ALL_Reset(void) +{ + PMU->CTRL |= PMU_CTRL_EVENTCNT_RESET_Msk; +} + +/** + \brief Enable counters + \param [in] mask Counters to enable + \note Enables one or more of the following: + - event counters (0-30) + - cycle counter +*/ +__STATIC_INLINE void ARM_PMU_CNTR_Enable(uint32_t mask) +{ + PMU->CNTENSET = mask; +} + +/** + \brief Disable counters + \param [in] mask Counters to enable + \note Disables one or more of the following: + - event counters (0-30) + - cycle counter +*/ +__STATIC_INLINE void ARM_PMU_CNTR_Disable(uint32_t mask) +{ + PMU->CNTENCLR = mask; +} + +/** + \brief Read cycle counter + \return Cycle count +*/ +__STATIC_INLINE uint32_t ARM_PMU_Get_CCNTR(void) +{ + return PMU->CCNTR; +} + +/** + \brief Read event counter + \param [in] num Event counter (0-30) to read + \return Event count +*/ +__STATIC_INLINE uint32_t ARM_PMU_Get_EVCNTR(uint32_t num) +{ + return PMU_EVCNTR_CNT_Msk & PMU->EVCNTR[num]; +} + +/** + \brief Read counter overflow status + \return Counter overflow status bits for the following: + - event counters (0-30) + - cycle counter +*/ +__STATIC_INLINE uint32_t ARM_PMU_Get_CNTR_OVS(void) +{ + return PMU->OVSSET; +} + +/** + \brief Clear counter overflow status + \param [in] mask Counter overflow status bits to clear + \note Clears overflow status bits for one or more of the following: + - event counters (0-30) + - cycle counter +*/ +__STATIC_INLINE void ARM_PMU_Set_CNTR_OVS(uint32_t mask) +{ + PMU->OVSCLR = mask; +} + +/** + \brief Enable counter overflow interrupt request + \param [in] mask Counter overflow interrupt request bits to set + \note Sets overflow interrupt request bits for one or more of the following: + - event counters (0-30) + - cycle counter +*/ +__STATIC_INLINE void ARM_PMU_Set_CNTR_IRQ_Enable(uint32_t mask) +{ + PMU->INTENSET = mask; +} + +/** + \brief Disable counter overflow interrupt request + \param [in] mask Counter overflow interrupt request bits to clear + \note Clears overflow interrupt request bits for one or more of the following: + - event counters (0-30) + - cycle counter +*/ +__STATIC_INLINE void ARM_PMU_Set_CNTR_IRQ_Disable(uint32_t mask) +{ + PMU->INTENCLR = mask; +} + +/** + \brief Software increment event counter + \param [in] mask Counters to increment + \note Software increment bits for one or more event counters (0-30) +*/ +__STATIC_INLINE void ARM_PMU_CNTR_Increment(uint32_t mask) +{ + PMU->SWINC = mask; +} + +#endif diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/CMSIS/Core/Include/tz_context.h b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/CMSIS/Core/Include/tz_context.h new file mode 100644 index 0000000000..facc2c9a47 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/CMSIS/Core/Include/tz_context.h @@ -0,0 +1,70 @@ +/****************************************************************************** + * @file tz_context.h + * @brief Context Management for Armv8-M TrustZone + * @version V1.0.1 + * @date 10. January 2018 + ******************************************************************************/ +/* + * Copyright (c) 2017-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef TZ_CONTEXT_H +#define TZ_CONTEXT_H + +#include + +#ifndef TZ_MODULEID_T +#define TZ_MODULEID_T +/// \details Data type that identifies secure software modules called by a process. +typedef uint32_t TZ_ModuleId_t; +#endif + +/// \details TZ Memory ID identifies an allocated memory slot. +typedef uint32_t TZ_MemoryId_t; + +/// Initialize secure context memory system +/// \return execution status (1: success, 0: error) +uint32_t TZ_InitContextSystem_S (void); + +/// Allocate context memory for calling secure software modules in TrustZone +/// \param[in] module identifies software modules called from non-secure mode +/// \return value != 0 id TrustZone memory slot identifier +/// \return value 0 no memory available or internal error +TZ_MemoryId_t TZ_AllocModuleContext_S (TZ_ModuleId_t module); + +/// Free context memory that was previously allocated with \ref TZ_AllocModuleContext_S +/// \param[in] id TrustZone memory slot identifier +/// \return execution status (1: success, 0: error) +uint32_t TZ_FreeModuleContext_S (TZ_MemoryId_t id); + +/// Load secure context (called on RTOS thread context switch) +/// \param[in] id TrustZone memory slot identifier +/// \return execution status (1: success, 0: error) +uint32_t TZ_LoadContext_S (TZ_MemoryId_t id); + +/// Store secure context (called on RTOS thread context switch) +/// \param[in] id TrustZone memory slot identifier +/// \return execution status (1: success, 0: error) +uint32_t TZ_StoreContext_S (TZ_MemoryId_t id); + +#endif // TZ_CONTEXT_H diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/CMSIS/Core/Template/ARMv8-M/main_s.c b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/CMSIS/Core/Template/ARMv8-M/main_s.c new file mode 100644 index 0000000000..0e56b7cb94 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/CMSIS/Core/Template/ARMv8-M/main_s.c @@ -0,0 +1,58 @@ +/****************************************************************************** + * @file main_s.c + * @brief Code template for secure main function + * @version V1.1.1 + * @date 10. January 2018 + ******************************************************************************/ +/* + * Copyright (c) 2013-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* Use CMSE intrinsics */ +#include + +#include "RTE_Components.h" +#include CMSIS_device_header + +/* TZ_START_NS: Start address of non-secure application */ +#ifndef TZ_START_NS +#define TZ_START_NS (0x200000U) +#endif + +/* typedef for non-secure callback functions */ +typedef void (*funcptr_void) (void) __attribute__((cmse_nonsecure_call)); + +/* Secure main() */ +int main(void) { + funcptr_void NonSecure_ResetHandler; + + /* Add user setup code for secure part here*/ + + /* Set non-secure main stack (MSP_NS) */ + __TZ_set_MSP_NS(*((uint32_t *)(TZ_START_NS))); + + /* Get non-secure reset handler */ + NonSecure_ResetHandler = (funcptr_void)(*((uint32_t *)((TZ_START_NS) + 4U))); + + /* Start non-secure state software application */ + NonSecure_ResetHandler(); + + /* Non-secure software does not return, this code is not executed */ + while (1) { + __NOP(); + } +} diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/CMSIS/Core/Template/ARMv8-M/tz_context.c b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/CMSIS/Core/Template/ARMv8-M/tz_context.c new file mode 100644 index 0000000000..e2e82942f8 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/CMSIS/Core/Template/ARMv8-M/tz_context.c @@ -0,0 +1,200 @@ +/****************************************************************************** + * @file tz_context.c + * @brief Context Management for Armv8-M TrustZone - Sample implementation + * @version V1.1.1 + * @date 10. January 2018 + ******************************************************************************/ +/* + * Copyright (c) 2016-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "RTE_Components.h" +#include CMSIS_device_header +#include "tz_context.h" + +/// Number of process slots (threads may call secure library code) +#ifndef TZ_PROCESS_STACK_SLOTS +#define TZ_PROCESS_STACK_SLOTS 8U +#endif + +/// Stack size of the secure library code +#ifndef TZ_PROCESS_STACK_SIZE +#define TZ_PROCESS_STACK_SIZE 256U +#endif + +typedef struct { + uint32_t sp_top; // stack space top + uint32_t sp_limit; // stack space limit + uint32_t sp; // current stack pointer +} stack_info_t; + +static stack_info_t ProcessStackInfo [TZ_PROCESS_STACK_SLOTS]; +static uint64_t ProcessStackMemory[TZ_PROCESS_STACK_SLOTS][TZ_PROCESS_STACK_SIZE/8U]; +static uint32_t ProcessStackFreeSlot = 0xFFFFFFFFU; + + +/// Initialize secure context memory system +/// \return execution status (1: success, 0: error) +__attribute__((cmse_nonsecure_entry)) +uint32_t TZ_InitContextSystem_S (void) { + uint32_t n; + + if (__get_IPSR() == 0U) { + return 0U; // Thread Mode + } + + for (n = 0U; n < TZ_PROCESS_STACK_SLOTS; n++) { + ProcessStackInfo[n].sp = 0U; + ProcessStackInfo[n].sp_limit = (uint32_t)&ProcessStackMemory[n]; + ProcessStackInfo[n].sp_top = (uint32_t)&ProcessStackMemory[n] + TZ_PROCESS_STACK_SIZE; + *((uint32_t *)ProcessStackMemory[n]) = n + 1U; + } + *((uint32_t *)ProcessStackMemory[--n]) = 0xFFFFFFFFU; + + ProcessStackFreeSlot = 0U; + + // Default process stack pointer and stack limit + __set_PSPLIM((uint32_t)ProcessStackMemory); + __set_PSP ((uint32_t)ProcessStackMemory); + + // Privileged Thread Mode using PSP + __set_CONTROL(0x02U); + + return 1U; // Success +} + + +/// Allocate context memory for calling secure software modules in TrustZone +/// \param[in] module identifies software modules called from non-secure mode +/// \return value != 0 id TrustZone memory slot identifier +/// \return value 0 no memory available or internal error +__attribute__((cmse_nonsecure_entry)) +TZ_MemoryId_t TZ_AllocModuleContext_S (TZ_ModuleId_t module) { + uint32_t slot; + + (void)module; // Ignore (fixed Stack size) + + if (__get_IPSR() == 0U) { + return 0U; // Thread Mode + } + + if (ProcessStackFreeSlot == 0xFFFFFFFFU) { + return 0U; // No slot available + } + + slot = ProcessStackFreeSlot; + ProcessStackFreeSlot = *((uint32_t *)ProcessStackMemory[slot]); + + ProcessStackInfo[slot].sp = ProcessStackInfo[slot].sp_top; + + return (slot + 1U); +} + + +/// Free context memory that was previously allocated with \ref TZ_AllocModuleContext_S +/// \param[in] id TrustZone memory slot identifier +/// \return execution status (1: success, 0: error) +__attribute__((cmse_nonsecure_entry)) +uint32_t TZ_FreeModuleContext_S (TZ_MemoryId_t id) { + uint32_t slot; + + if (__get_IPSR() == 0U) { + return 0U; // Thread Mode + } + + if ((id == 0U) || (id > TZ_PROCESS_STACK_SLOTS)) { + return 0U; // Invalid ID + } + + slot = id - 1U; + + if (ProcessStackInfo[slot].sp == 0U) { + return 0U; // Inactive slot + } + ProcessStackInfo[slot].sp = 0U; + + *((uint32_t *)ProcessStackMemory[slot]) = ProcessStackFreeSlot; + ProcessStackFreeSlot = slot; + + return 1U; // Success +} + + +/// Load secure context (called on RTOS thread context switch) +/// \param[in] id TrustZone memory slot identifier +/// \return execution status (1: success, 0: error) +__attribute__((cmse_nonsecure_entry)) +uint32_t TZ_LoadContext_S (TZ_MemoryId_t id) { + uint32_t slot; + + if ((__get_IPSR() == 0U) || ((__get_CONTROL() & 2U) == 0U)) { + return 0U; // Thread Mode or using Main Stack for threads + } + + if ((id == 0U) || (id > TZ_PROCESS_STACK_SLOTS)) { + return 0U; // Invalid ID + } + + slot = id - 1U; + + if (ProcessStackInfo[slot].sp == 0U) { + return 0U; // Inactive slot + } + + // Setup process stack pointer and stack limit + __set_PSPLIM(ProcessStackInfo[slot].sp_limit); + __set_PSP (ProcessStackInfo[slot].sp); + + return 1U; // Success +} + + +/// Store secure context (called on RTOS thread context switch) +/// \param[in] id TrustZone memory slot identifier +/// \return execution status (1: success, 0: error) +__attribute__((cmse_nonsecure_entry)) +uint32_t TZ_StoreContext_S (TZ_MemoryId_t id) { + uint32_t slot; + uint32_t sp; + + if ((__get_IPSR() == 0U) || ((__get_CONTROL() & 2U) == 0U)) { + return 0U; // Thread Mode or using Main Stack for threads + } + + if ((id == 0U) || (id > TZ_PROCESS_STACK_SLOTS)) { + return 0U; // Invalid ID + } + + slot = id - 1U; + + if (ProcessStackInfo[slot].sp == 0U) { + return 0U; // Inactive slot + } + + sp = __get_PSP(); + if ((sp < ProcessStackInfo[slot].sp_limit) || + (sp > ProcessStackInfo[slot].sp_top)) { + return 0U; // SP out of range + } + ProcessStackInfo[slot].sp = sp; + + // Default process stack pointer and stack limit + __set_PSPLIM((uint32_t)ProcessStackMemory); + __set_PSP ((uint32_t)ProcessStackMemory); + + return 1U; // Success +} diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/CMSIS/Include/cmsis_armcc.h b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/CMSIS/Include/cmsis_armcc.h new file mode 100644 index 0000000000..a955d47139 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/CMSIS/Include/cmsis_armcc.h @@ -0,0 +1,888 @@ +/**************************************************************************//** + * @file cmsis_armcc.h + * @brief CMSIS compiler ARMCC (Arm Compiler 5) header file + * @version V5.3.2 + * @date 27. May 2021 + ******************************************************************************/ +/* + * Copyright (c) 2009-2021 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_ARMCC_H +#define __CMSIS_ARMCC_H + + +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 400677) + #error "Please use Arm Compiler Toolchain V4.0.677 or later!" +#endif + +/* CMSIS compiler control architecture macros */ +#if ((defined (__TARGET_ARCH_6_M ) && (__TARGET_ARCH_6_M == 1)) || \ + (defined (__TARGET_ARCH_6S_M ) && (__TARGET_ARCH_6S_M == 1)) ) + #define __ARM_ARCH_6M__ 1 +#endif + +#if (defined (__TARGET_ARCH_7_M ) && (__TARGET_ARCH_7_M == 1)) + #define __ARM_ARCH_7M__ 1 +#endif + +#if (defined (__TARGET_ARCH_7E_M) && (__TARGET_ARCH_7E_M == 1)) + #define __ARM_ARCH_7EM__ 1 +#endif + + /* __ARM_ARCH_8M_BASE__ not applicable */ + /* __ARM_ARCH_8M_MAIN__ not applicable */ + /* __ARM_ARCH_8_1M_MAIN__ not applicable */ + +/* CMSIS compiler control DSP macros */ +#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + #define __ARM_FEATURE_DSP 1 +#endif + +/* CMSIS compiler specific defines */ +#ifndef __ASM + #define __ASM __asm +#endif +#ifndef __INLINE + #define __INLINE __inline +#endif +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static __inline +#endif +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE static __forceinline +#endif +#ifndef __NO_RETURN + #define __NO_RETURN __declspec(noreturn) +#endif +#ifndef __USED + #define __USED __attribute__((used)) +#endif +#ifndef __WEAK + #define __WEAK __attribute__((weak)) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed)) +#endif +#ifndef __PACKED_STRUCT + #define __PACKED_STRUCT __packed struct +#endif +#ifndef __PACKED_UNION + #define __PACKED_UNION __packed union +#endif +#ifndef __UNALIGNED_UINT32 /* deprecated */ + #define __UNALIGNED_UINT32(x) (*((__packed uint32_t *)(x))) +#endif +#ifndef __UNALIGNED_UINT16_WRITE + #define __UNALIGNED_UINT16_WRITE(addr, val) ((*((__packed uint16_t *)(addr))) = (val)) +#endif +#ifndef __UNALIGNED_UINT16_READ + #define __UNALIGNED_UINT16_READ(addr) (*((const __packed uint16_t *)(addr))) +#endif +#ifndef __UNALIGNED_UINT32_WRITE + #define __UNALIGNED_UINT32_WRITE(addr, val) ((*((__packed uint32_t *)(addr))) = (val)) +#endif +#ifndef __UNALIGNED_UINT32_READ + #define __UNALIGNED_UINT32_READ(addr) (*((const __packed uint32_t *)(addr))) +#endif +#ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __RESTRICT + #define __RESTRICT __restrict +#endif +#ifndef __COMPILER_BARRIER + #define __COMPILER_BARRIER() __memory_changed() +#endif + +/* ######################### Startup and Lowlevel Init ######################## */ + +#ifndef __PROGRAM_START +#define __PROGRAM_START __main +#endif + +#ifndef __INITIAL_SP +#define __INITIAL_SP Image$$ARM_LIB_STACK$$ZI$$Limit +#endif + +#ifndef __STACK_LIMIT +#define __STACK_LIMIT Image$$ARM_LIB_STACK$$ZI$$Base +#endif + +#ifndef __VECTOR_TABLE +#define __VECTOR_TABLE __Vectors +#endif + +#ifndef __VECTOR_TABLE_ATTRIBUTE +#define __VECTOR_TABLE_ATTRIBUTE __attribute__((used, section("RESET"))) +#endif + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP __nop + + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +#define __WFI __wfi + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE __wfe + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV __sev + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +#define __ISB() __isb(0xF) + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +#define __DSB() __dsb(0xF) + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +#define __DMB() __dmb(0xF) + + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV __rev + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. + \param [in] value Value to reverse + \return Reversed value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value) +{ + rev16 r0, r0 + bx lr +} +#endif + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. + \param [in] value Value to reverse + \return Reversed value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int16_t __REVSH(int16_t value) +{ + revsh r0, r0 + bx lr +} +#endif + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +#define __ROR __ror + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __breakpoint(value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + #define __RBIT __rbit +#else +__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value) +{ + uint32_t result; + uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */ + + result = value; /* r will be reversed bits of v; first get LSB of v */ + for (value >>= 1U; value != 0U; value >>= 1U) + { + result <<= 1U; + result |= value & 1U; + s--; + } + result <<= s; /* shift when v's highest bits are zero */ + return result; +} +#endif + + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +#define __CLZ __clz + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr)) +#else + #define __LDREXB(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint8_t ) __ldrex(ptr)) _Pragma("pop") +#endif + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __LDREXH(ptr) ((uint16_t) __ldrex(ptr)) +#else + #define __LDREXH(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint16_t) __ldrex(ptr)) _Pragma("pop") +#endif + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr)) +#else + #define __LDREXW(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex(ptr)) _Pragma("pop") +#endif + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __STREXB(value, ptr) __strex(value, ptr) +#else + #define __STREXB(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") +#endif + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __STREXH(value, ptr) __strex(value, ptr) +#else + #define __STREXH(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") +#endif + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __STREXW(value, ptr) __strex(value, ptr) +#else + #define __STREXW(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") +#endif + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +#define __CLREX __clrex + + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT __ssat + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT __usat + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value) +{ + rrx r0, r0 + bx lr +} +#endif + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDRBT(ptr) ((uint8_t ) __ldrt(ptr)) + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDRHT(ptr) ((uint16_t) __ldrt(ptr)) + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDRT(ptr) ((uint32_t ) __ldrt(ptr)) + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +#define __STRBT(value, ptr) __strt(value, ptr) + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +#define __STRHT(value, ptr) __strt(value, ptr) + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +#define __STRT(value, ptr) __strt(value, ptr) + +#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +__attribute__((always_inline)) __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat) +{ + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; +} + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat) +{ + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing special-purpose register PRIMASK. + Can only be executed in Privileged modes. + */ +/* intrinsic void __enable_irq(); */ + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting special-purpose register PRIMASK. + Can only be executed in Privileged modes. + */ +/* intrinsic void __disable_irq(); */ + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__STATIC_INLINE uint32_t __get_CONTROL(void) +{ + register uint32_t __regControl __ASM("control"); + return(__regControl); +} + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__STATIC_INLINE void __set_CONTROL(uint32_t control) +{ + register uint32_t __regControl __ASM("control"); + __regControl = control; + __ISB(); +} + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__STATIC_INLINE uint32_t __get_IPSR(void) +{ + register uint32_t __regIPSR __ASM("ipsr"); + return(__regIPSR); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__STATIC_INLINE uint32_t __get_APSR(void) +{ + register uint32_t __regAPSR __ASM("apsr"); + return(__regAPSR); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__STATIC_INLINE uint32_t __get_xPSR(void) +{ + register uint32_t __regXPSR __ASM("xpsr"); + return(__regXPSR); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__STATIC_INLINE uint32_t __get_PSP(void) +{ + register uint32_t __regProcessStackPointer __ASM("psp"); + return(__regProcessStackPointer); +} + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) +{ + register uint32_t __regProcessStackPointer __ASM("psp"); + __regProcessStackPointer = topOfProcStack; +} + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__STATIC_INLINE uint32_t __get_MSP(void) +{ + register uint32_t __regMainStackPointer __ASM("msp"); + return(__regMainStackPointer); +} + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) +{ + register uint32_t __regMainStackPointer __ASM("msp"); + __regMainStackPointer = topOfMainStack; +} + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__STATIC_INLINE uint32_t __get_PRIMASK(void) +{ + register uint32_t __regPriMask __ASM("primask"); + return(__regPriMask); +} + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__STATIC_INLINE void __set_PRIMASK(uint32_t priMask) +{ + register uint32_t __regPriMask __ASM("primask"); + __regPriMask = (priMask); +} + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing special-purpose register FAULTMASK. + Can only be executed in Privileged modes. + */ +#define __enable_fault_irq __enable_fiq + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting special-purpose register FAULTMASK. + Can only be executed in Privileged modes. + */ +#define __disable_fault_irq __disable_fiq + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__STATIC_INLINE uint32_t __get_BASEPRI(void) +{ + register uint32_t __regBasePri __ASM("basepri"); + return(__regBasePri); +} + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__STATIC_INLINE void __set_BASEPRI(uint32_t basePri) +{ + register uint32_t __regBasePri __ASM("basepri"); + __regBasePri = (basePri & 0xFFU); +} + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + register uint32_t __regBasePriMax __ASM("basepri_max"); + __regBasePriMax = (basePri & 0xFFU); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__STATIC_INLINE uint32_t __get_FAULTMASK(void) +{ + register uint32_t __regFaultMask __ASM("faultmask"); + return(__regFaultMask); +} + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) +{ + register uint32_t __regFaultMask __ASM("faultmask"); + __regFaultMask = (faultMask & (uint32_t)1U); +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ + + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +__STATIC_INLINE uint32_t __get_FPSCR(void) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) + register uint32_t __regfpscr __ASM("fpscr"); + return(__regfpscr); +#else + return(0U); +#endif +} + + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +__STATIC_INLINE void __set_FPSCR(uint32_t fpscr) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) + register uint32_t __regfpscr __ASM("fpscr"); + __regfpscr = (fpscr); +#else + (void)fpscr; +#endif +} + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + +#define __SADD8 __sadd8 +#define __QADD8 __qadd8 +#define __SHADD8 __shadd8 +#define __UADD8 __uadd8 +#define __UQADD8 __uqadd8 +#define __UHADD8 __uhadd8 +#define __SSUB8 __ssub8 +#define __QSUB8 __qsub8 +#define __SHSUB8 __shsub8 +#define __USUB8 __usub8 +#define __UQSUB8 __uqsub8 +#define __UHSUB8 __uhsub8 +#define __SADD16 __sadd16 +#define __QADD16 __qadd16 +#define __SHADD16 __shadd16 +#define __UADD16 __uadd16 +#define __UQADD16 __uqadd16 +#define __UHADD16 __uhadd16 +#define __SSUB16 __ssub16 +#define __QSUB16 __qsub16 +#define __SHSUB16 __shsub16 +#define __USUB16 __usub16 +#define __UQSUB16 __uqsub16 +#define __UHSUB16 __uhsub16 +#define __SASX __sasx +#define __QASX __qasx +#define __SHASX __shasx +#define __UASX __uasx +#define __UQASX __uqasx +#define __UHASX __uhasx +#define __SSAX __ssax +#define __QSAX __qsax +#define __SHSAX __shsax +#define __USAX __usax +#define __UQSAX __uqsax +#define __UHSAX __uhsax +#define __USAD8 __usad8 +#define __USADA8 __usada8 +#define __SSAT16 __ssat16 +#define __USAT16 __usat16 +#define __UXTB16 __uxtb16 +#define __UXTAB16 __uxtab16 +#define __SXTB16 __sxtb16 +#define __SXTAB16 __sxtab16 +#define __SMUAD __smuad +#define __SMUADX __smuadx +#define __SMLAD __smlad +#define __SMLADX __smladx +#define __SMLALD __smlald +#define __SMLALDX __smlaldx +#define __SMUSD __smusd +#define __SMUSDX __smusdx +#define __SMLSD __smlsd +#define __SMLSDX __smlsdx +#define __SMLSLD __smlsld +#define __SMLSLDX __smlsldx +#define __SEL __sel +#define __QADD __qadd +#define __QSUB __qsub + +#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ + ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) + +#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ + ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) + +#define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \ + ((int64_t)(ARG3) << 32U) ) >> 32U)) + +#define __SXTB16_RORn(ARG1, ARG2) __SXTB16(__ROR(ARG1, ARG2)) + +#define __SXTAB16_RORn(ARG1, ARG2, ARG3) __SXTAB16(ARG1, __ROR(ARG2, ARG3)) + +#endif /* ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#endif /* __CMSIS_ARMCC_H */ diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/CMSIS/Include/cmsis_armclang.h b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/CMSIS/Include/cmsis_armclang.h new file mode 100644 index 0000000000..6911417747 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/CMSIS/Include/cmsis_armclang.h @@ -0,0 +1,1503 @@ +/**************************************************************************//** + * @file cmsis_armclang.h + * @brief CMSIS compiler armclang (Arm Compiler 6) header file + * @version V5.4.3 + * @date 27. May 2021 + ******************************************************************************/ +/* + * Copyright (c) 2009-2021 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/*lint -esym(9058, IRQn)*/ /* disable MISRA 2012 Rule 2.4 for IRQn */ + +#ifndef __CMSIS_ARMCLANG_H +#define __CMSIS_ARMCLANG_H + +#pragma clang system_header /* treat file as system include file */ + +/* CMSIS compiler specific defines */ +#ifndef __ASM + #define __ASM __asm +#endif +#ifndef __INLINE + #define __INLINE __inline +#endif +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static __inline +#endif +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __attribute__((always_inline)) static __inline +#endif +#ifndef __NO_RETURN + #define __NO_RETURN __attribute__((__noreturn__)) +#endif +#ifndef __USED + #define __USED __attribute__((used)) +#endif +#ifndef __WEAK + #define __WEAK __attribute__((weak)) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_UNION + #define __PACKED_UNION union __attribute__((packed, aligned(1))) +#endif +#ifndef __UNALIGNED_UINT32 /* deprecated */ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32 */ + struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) +#endif +#ifndef __UNALIGNED_UINT16_WRITE + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT16_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_WRITE */ + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT16_READ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT16_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_READ */ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) +#endif +#ifndef __UNALIGNED_UINT32_WRITE + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_WRITE */ + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT32_READ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_READ */ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) +#endif +#ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __RESTRICT + #define __RESTRICT __restrict +#endif +#ifndef __COMPILER_BARRIER + #define __COMPILER_BARRIER() __ASM volatile("":::"memory") +#endif + +/* ######################### Startup and Lowlevel Init ######################## */ + +#ifndef __PROGRAM_START +#define __PROGRAM_START __main +#endif + +#ifndef __INITIAL_SP +#define __INITIAL_SP Image$$ARM_LIB_STACK$$ZI$$Limit +#endif + +#ifndef __STACK_LIMIT +#define __STACK_LIMIT Image$$ARM_LIB_STACK$$ZI$$Base +#endif + +#ifndef __VECTOR_TABLE +#define __VECTOR_TABLE __Vectors +#endif + +#ifndef __VECTOR_TABLE_ATTRIBUTE +#define __VECTOR_TABLE_ATTRIBUTE __attribute__((used, section("RESET"))) +#endif + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +#ifndef __STACK_SEAL +#define __STACK_SEAL Image$$STACKSEAL$$ZI$$Base +#endif + +#ifndef __TZ_STACK_SEAL_SIZE +#define __TZ_STACK_SEAL_SIZE 8U +#endif + +#ifndef __TZ_STACK_SEAL_VALUE +#define __TZ_STACK_SEAL_VALUE 0xFEF5EDA5FEF5EDA5ULL +#endif + + +__STATIC_FORCEINLINE void __TZ_set_STACKSEAL_S (uint32_t* stackTop) { + *((uint64_t *)stackTop) = __TZ_STACK_SEAL_VALUE; +} +#endif + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/* Define macros for porting to both thumb1 and thumb2. + * For thumb1, use low register (r0-r7), specified by constraint "l" + * Otherwise, use general registers, specified by constraint "r" */ +#if defined (__thumb__) && !defined (__thumb2__) +#define __CMSIS_GCC_OUT_REG(r) "=l" (r) +#define __CMSIS_GCC_RW_REG(r) "+l" (r) +#define __CMSIS_GCC_USE_REG(r) "l" (r) +#else +#define __CMSIS_GCC_OUT_REG(r) "=r" (r) +#define __CMSIS_GCC_RW_REG(r) "+r" (r) +#define __CMSIS_GCC_USE_REG(r) "r" (r) +#endif + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP __builtin_arm_nop + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +#define __WFI __builtin_arm_wfi + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE __builtin_arm_wfe + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV __builtin_arm_sev + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +#define __ISB() __builtin_arm_isb(0xF) + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +#define __DSB() __builtin_arm_dsb(0xF) + + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +#define __DMB() __builtin_arm_dmb(0xF) + + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV(value) __builtin_bswap32(value) + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV16(value) __ROR(__REV(value), 16) + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REVSH(value) (int16_t)__builtin_bswap16(value) + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) +{ + op2 %= 32U; + if (op2 == 0U) + { + return op1; + } + return (op1 >> op2) | (op1 << (32U - op2)); +} + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __ASM volatile ("bkpt "#value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +#define __RBIT __builtin_arm_rbit + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +__STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value) +{ + /* Even though __builtin_clz produces a CLZ instruction on ARM, formally + __builtin_clz(0) is undefined behaviour, so handle this case specially. + This guarantees ARM-compatible results if happening to compile on a non-ARM + target, and ensures the compiler doesn't decide to activate any + optimisations using the logic "value was passed to __builtin_clz, so it + is non-zero". + ARM Compiler 6.10 and possibly earlier will optimise this test away, leaving a + single CLZ instruction. + */ + if (value == 0U) + { + return 32U; + } + return __builtin_clz(value); +} + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) + +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDREXB (uint8_t)__builtin_arm_ldrex + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDREXH (uint16_t)__builtin_arm_ldrex + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDREXW (uint32_t)__builtin_arm_ldrex + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXB (uint32_t)__builtin_arm_strex + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXH (uint32_t)__builtin_arm_strex + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXW (uint32_t)__builtin_arm_strex + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +#define __CLREX __builtin_arm_clrex + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT __builtin_arm_ssat + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT __builtin_arm_usat + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) ); +} + +#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) */ + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat) +{ + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; +} + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat) +{ + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) + +/** + \brief Load-Acquire (8 bit) + \details Executes a LDAB instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return ((uint8_t) result); +} + + +/** + \brief Load-Acquire (16 bit) + \details Executes a LDAH instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return ((uint16_t) result); +} + + +/** + \brief Load-Acquire (32 bit) + \details Executes a LDA instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return(result); +} + + +/** + \brief Store-Release (8 bit) + \details Executes a STLB instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Store-Release (16 bit) + \details Executes a STLH instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Store-Release (32 bit) + \details Executes a STL instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Load-Acquire Exclusive (8 bit) + \details Executes a LDAB exclusive instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDAEXB (uint8_t)__builtin_arm_ldaex + + +/** + \brief Load-Acquire Exclusive (16 bit) + \details Executes a LDAH exclusive instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDAEXH (uint16_t)__builtin_arm_ldaex + + +/** + \brief Load-Acquire Exclusive (32 bit) + \details Executes a LDA exclusive instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDAEX (uint32_t)__builtin_arm_ldaex + + +/** + \brief Store-Release Exclusive (8 bit) + \details Executes a STLB exclusive instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEXB (uint32_t)__builtin_arm_stlex + + +/** + \brief Store-Release Exclusive (16 bit) + \details Executes a STLH exclusive instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEXH (uint32_t)__builtin_arm_stlex + + +/** + \brief Store-Release Exclusive (32 bit) + \details Executes a STL exclusive instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEX (uint32_t)__builtin_arm_stlex + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing special-purpose register PRIMASK. + Can only be executed in Privileged modes. + */ +#ifndef __ARM_COMPAT_H +__STATIC_FORCEINLINE void __enable_irq(void) +{ + __ASM volatile ("cpsie i" : : : "memory"); +} +#endif + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting special-purpose register PRIMASK. + Can only be executed in Privileged modes. + */ +#ifndef __ARM_COMPAT_H +__STATIC_FORCEINLINE void __disable_irq(void) +{ + __ASM volatile ("cpsid i" : : : "memory"); +} +#endif + + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CONTROL(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Control Register (non-secure) + \details Returns the content of the non-secure Control Register when in secure mode. + \return non-secure Control Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) +{ + __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); + __ISB(); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Control Register (non-secure) + \details Writes the given value to the non-secure Control Register when in secure state. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) +{ + __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); + __ISB(); +} +#endif + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_IPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_APSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_xPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer (non-secure) + \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state. + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state. + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); +} +#endif + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer (non-secure) + \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state. + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); +} +#endif + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Stack Pointer (non-secure) + \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state. + \return SP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, sp_ns" : "=r" (result) ); + return(result); +} + + +/** + \brief Set Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state. + \param [in] topOfStack Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack) +{ + __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : ); +} +#endif + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Priority Mask (non-secure) + \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Priority Mask (non-secure) + \details Assigns the given value to the non-secure Priority Mask Register when in secure state. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) +{ + __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); +} +#endif + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing special-purpose register FAULTMASK. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __enable_fault_irq(void) +{ + __ASM volatile ("cpsie f" : : : "memory"); +} + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting special-purpose register FAULTMASK. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __disable_fault_irq(void) +{ + __ASM volatile ("cpsid f" : : : "memory"); +} + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Base Priority (non-secure) + \details Returns the current value of the non-secure Base Priority register when in secure state. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri) +{ + __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Base Priority (non-secure) + \details Assigns the given value to the non-secure Base Priority register when in secure state. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); +} +#endif + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Fault Mask (non-secure) + \details Returns the current value of the non-secure Fault Mask register when in secure state. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Fault Mask (non-secure) + \details Assigns the given value to the non-secure Fault Mask register when in secure state. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); +} +#endif + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) + +/** + \brief Get Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void) +{ +#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim" : "=r" (result) ); + return result; +#endif +} + +#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) +{ +#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) ) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) +{ +#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) +{ +#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) ) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); +#endif +} +#endif + + +/** + \brief Get Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void) +{ +#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim" : "=r" (result) ); + return result; +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state. + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void) +{ +#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) ) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). + \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) +{ +#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state. + \param [in] MainStackPtrLimit Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) +{ +#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) ) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); +#endif +} +#endif + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) */ + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#define __get_FPSCR (uint32_t)__builtin_arm_get_fpscr +#else +#define __get_FPSCR() ((uint32_t)0U) +#endif + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#define __set_FPSCR __builtin_arm_set_fpscr +#else +#define __set_FPSCR(x) ((void)(x)) +#endif + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) + +#define __SADD8 __builtin_arm_sadd8 +#define __QADD8 __builtin_arm_qadd8 +#define __SHADD8 __builtin_arm_shadd8 +#define __UADD8 __builtin_arm_uadd8 +#define __UQADD8 __builtin_arm_uqadd8 +#define __UHADD8 __builtin_arm_uhadd8 +#define __SSUB8 __builtin_arm_ssub8 +#define __QSUB8 __builtin_arm_qsub8 +#define __SHSUB8 __builtin_arm_shsub8 +#define __USUB8 __builtin_arm_usub8 +#define __UQSUB8 __builtin_arm_uqsub8 +#define __UHSUB8 __builtin_arm_uhsub8 +#define __SADD16 __builtin_arm_sadd16 +#define __QADD16 __builtin_arm_qadd16 +#define __SHADD16 __builtin_arm_shadd16 +#define __UADD16 __builtin_arm_uadd16 +#define __UQADD16 __builtin_arm_uqadd16 +#define __UHADD16 __builtin_arm_uhadd16 +#define __SSUB16 __builtin_arm_ssub16 +#define __QSUB16 __builtin_arm_qsub16 +#define __SHSUB16 __builtin_arm_shsub16 +#define __USUB16 __builtin_arm_usub16 +#define __UQSUB16 __builtin_arm_uqsub16 +#define __UHSUB16 __builtin_arm_uhsub16 +#define __SASX __builtin_arm_sasx +#define __QASX __builtin_arm_qasx +#define __SHASX __builtin_arm_shasx +#define __UASX __builtin_arm_uasx +#define __UQASX __builtin_arm_uqasx +#define __UHASX __builtin_arm_uhasx +#define __SSAX __builtin_arm_ssax +#define __QSAX __builtin_arm_qsax +#define __SHSAX __builtin_arm_shsax +#define __USAX __builtin_arm_usax +#define __UQSAX __builtin_arm_uqsax +#define __UHSAX __builtin_arm_uhsax +#define __USAD8 __builtin_arm_usad8 +#define __USADA8 __builtin_arm_usada8 +#define __SSAT16 __builtin_arm_ssat16 +#define __USAT16 __builtin_arm_usat16 +#define __UXTB16 __builtin_arm_uxtb16 +#define __UXTAB16 __builtin_arm_uxtab16 +#define __SXTB16 __builtin_arm_sxtb16 +#define __SXTAB16 __builtin_arm_sxtab16 +#define __SMUAD __builtin_arm_smuad +#define __SMUADX __builtin_arm_smuadx +#define __SMLAD __builtin_arm_smlad +#define __SMLADX __builtin_arm_smladx +#define __SMLALD __builtin_arm_smlald +#define __SMLALDX __builtin_arm_smlaldx +#define __SMUSD __builtin_arm_smusd +#define __SMUSDX __builtin_arm_smusdx +#define __SMLSD __builtin_arm_smlsd +#define __SMLSDX __builtin_arm_smlsdx +#define __SMLSLD __builtin_arm_smlsld +#define __SMLSLDX __builtin_arm_smlsldx +#define __SEL __builtin_arm_sel +#define __QADD __builtin_arm_qadd +#define __QSUB __builtin_arm_qsub + +#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ + ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) + +#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ + ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) + +#define __SXTB16_RORn(ARG1, ARG2) __SXTB16(__ROR(ARG1, ARG2)) + +#define __SXTAB16_RORn(ARG1, ARG2, ARG3) __SXTAB16(ARG1, __ROR(ARG2, ARG3)) + +__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) +{ + int32_t result; + + __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#endif /* (__ARM_FEATURE_DSP == 1) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#endif /* __CMSIS_ARMCLANG_H */ diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/CMSIS/Include/cmsis_armclang_ltm.h b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/CMSIS/Include/cmsis_armclang_ltm.h new file mode 100644 index 0000000000..1e255d5907 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/CMSIS/Include/cmsis_armclang_ltm.h @@ -0,0 +1,1928 @@ +/**************************************************************************//** + * @file cmsis_armclang_ltm.h + * @brief CMSIS compiler armclang (Arm Compiler 6) header file + * @version V1.5.3 + * @date 27. May 2021 + ******************************************************************************/ +/* + * Copyright (c) 2018-2021 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/*lint -esym(9058, IRQn)*/ /* disable MISRA 2012 Rule 2.4 for IRQn */ + +#ifndef __CMSIS_ARMCLANG_H +#define __CMSIS_ARMCLANG_H + +#pragma clang system_header /* treat file as system include file */ + +/* CMSIS compiler specific defines */ +#ifndef __ASM + #define __ASM __asm +#endif +#ifndef __INLINE + #define __INLINE __inline +#endif +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static __inline +#endif +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __attribute__((always_inline)) static __inline +#endif +#ifndef __NO_RETURN + #define __NO_RETURN __attribute__((__noreturn__)) +#endif +#ifndef __USED + #define __USED __attribute__((used)) +#endif +#ifndef __WEAK + #define __WEAK __attribute__((weak)) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_UNION + #define __PACKED_UNION union __attribute__((packed, aligned(1))) +#endif +#ifndef __UNALIGNED_UINT32 /* deprecated */ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32 */ + struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) +#endif +#ifndef __UNALIGNED_UINT16_WRITE + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT16_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_WRITE */ + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT16_READ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT16_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_READ */ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) +#endif +#ifndef __UNALIGNED_UINT32_WRITE + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_WRITE */ + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT32_READ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_READ */ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) +#endif +#ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __RESTRICT + #define __RESTRICT __restrict +#endif +#ifndef __COMPILER_BARRIER + #define __COMPILER_BARRIER() __ASM volatile("":::"memory") +#endif + +/* ######################### Startup and Lowlevel Init ######################## */ + +#ifndef __PROGRAM_START +#define __PROGRAM_START __main +#endif + +#ifndef __INITIAL_SP +#define __INITIAL_SP Image$$ARM_LIB_STACK$$ZI$$Limit +#endif + +#ifndef __STACK_LIMIT +#define __STACK_LIMIT Image$$ARM_LIB_STACK$$ZI$$Base +#endif + +#ifndef __VECTOR_TABLE +#define __VECTOR_TABLE __Vectors +#endif + +#ifndef __VECTOR_TABLE_ATTRIBUTE +#define __VECTOR_TABLE_ATTRIBUTE __attribute__((used, section("RESET"))) +#endif + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +#ifndef __STACK_SEAL +#define __STACK_SEAL Image$$STACKSEAL$$ZI$$Base +#endif + +#ifndef __TZ_STACK_SEAL_SIZE +#define __TZ_STACK_SEAL_SIZE 8U +#endif + +#ifndef __TZ_STACK_SEAL_VALUE +#define __TZ_STACK_SEAL_VALUE 0xFEF5EDA5FEF5EDA5ULL +#endif + + +__STATIC_FORCEINLINE void __TZ_set_STACKSEAL_S (uint32_t* stackTop) { + *((uint64_t *)stackTop) = __TZ_STACK_SEAL_VALUE; +} +#endif + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/* Define macros for porting to both thumb1 and thumb2. + * For thumb1, use low register (r0-r7), specified by constraint "l" + * Otherwise, use general registers, specified by constraint "r" */ +#if defined (__thumb__) && !defined (__thumb2__) +#define __CMSIS_GCC_OUT_REG(r) "=l" (r) +#define __CMSIS_GCC_USE_REG(r) "l" (r) +#else +#define __CMSIS_GCC_OUT_REG(r) "=r" (r) +#define __CMSIS_GCC_USE_REG(r) "r" (r) +#endif + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP __builtin_arm_nop + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +#define __WFI __builtin_arm_wfi + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE __builtin_arm_wfe + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV __builtin_arm_sev + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +#define __ISB() __builtin_arm_isb(0xF) + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +#define __DSB() __builtin_arm_dsb(0xF) + + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +#define __DMB() __builtin_arm_dmb(0xF) + + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV(value) __builtin_bswap32(value) + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV16(value) __ROR(__REV(value), 16) + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REVSH(value) (int16_t)__builtin_bswap16(value) + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) +{ + op2 %= 32U; + if (op2 == 0U) + { + return op1; + } + return (op1 >> op2) | (op1 << (32U - op2)); +} + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __ASM volatile ("bkpt "#value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +#define __RBIT __builtin_arm_rbit + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +__STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value) +{ + /* Even though __builtin_clz produces a CLZ instruction on ARM, formally + __builtin_clz(0) is undefined behaviour, so handle this case specially. + This guarantees ARM-compatible results if happening to compile on a non-ARM + target, and ensures the compiler doesn't decide to activate any + optimisations using the logic "value was passed to __builtin_clz, so it + is non-zero". + ARM Compiler 6.10 and possibly earlier will optimise this test away, leaving a + single CLZ instruction. + */ + if (value == 0U) + { + return 32U; + } + return __builtin_clz(value); +} + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDREXB (uint8_t)__builtin_arm_ldrex + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDREXH (uint16_t)__builtin_arm_ldrex + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDREXW (uint32_t)__builtin_arm_ldrex + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXB (uint32_t)__builtin_arm_strex + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXH (uint32_t)__builtin_arm_strex + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXW (uint32_t)__builtin_arm_strex + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +#define __CLREX __builtin_arm_clrex + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT __builtin_arm_ssat + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT __builtin_arm_usat + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) ); +} + +#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat) +{ + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; +} + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat) +{ + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief Load-Acquire (8 bit) + \details Executes a LDAB instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return ((uint8_t) result); +} + + +/** + \brief Load-Acquire (16 bit) + \details Executes a LDAH instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return ((uint16_t) result); +} + + +/** + \brief Load-Acquire (32 bit) + \details Executes a LDA instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return(result); +} + + +/** + \brief Store-Release (8 bit) + \details Executes a STLB instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Store-Release (16 bit) + \details Executes a STLH instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Store-Release (32 bit) + \details Executes a STL instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Load-Acquire Exclusive (8 bit) + \details Executes a LDAB exclusive instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDAEXB (uint8_t)__builtin_arm_ldaex + + +/** + \brief Load-Acquire Exclusive (16 bit) + \details Executes a LDAH exclusive instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDAEXH (uint16_t)__builtin_arm_ldaex + + +/** + \brief Load-Acquire Exclusive (32 bit) + \details Executes a LDA exclusive instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDAEX (uint32_t)__builtin_arm_ldaex + + +/** + \brief Store-Release Exclusive (8 bit) + \details Executes a STLB exclusive instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEXB (uint32_t)__builtin_arm_stlex + + +/** + \brief Store-Release Exclusive (16 bit) + \details Executes a STLH exclusive instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEXH (uint32_t)__builtin_arm_stlex + + +/** + \brief Store-Release Exclusive (32 bit) + \details Executes a STL exclusive instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEX (uint32_t)__builtin_arm_stlex + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing special-purpose register PRIMASK. + Can only be executed in Privileged modes. + */ +#ifndef __ARM_COMPAT_H +__STATIC_FORCEINLINE void __enable_irq(void) +{ + __ASM volatile ("cpsie i" : : : "memory"); +} +#endif + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting special-purpose register PRIMASK. + Can only be executed in Privileged modes. + */ +#ifndef __ARM_COMPAT_H +__STATIC_FORCEINLINE void __disable_irq(void) +{ + __ASM volatile ("cpsid i" : : : "memory"); +} +#endif + + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CONTROL(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Control Register (non-secure) + \details Returns the content of the non-secure Control Register when in secure mode. + \return non-secure Control Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) +{ + __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); + __ISB(); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Control Register (non-secure) + \details Writes the given value to the non-secure Control Register when in secure state. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) +{ + __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); + __ISB(); +} +#endif + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_IPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_APSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_xPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer (non-secure) + \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state. + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state. + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); +} +#endif + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer (non-secure) + \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state. + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); +} +#endif + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Stack Pointer (non-secure) + \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state. + \return SP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, sp_ns" : "=r" (result) ); + return(result); +} + + +/** + \brief Set Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state. + \param [in] topOfStack Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack) +{ + __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : ); +} +#endif + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Priority Mask (non-secure) + \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Priority Mask (non-secure) + \details Assigns the given value to the non-secure Priority Mask Register when in secure state. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) +{ + __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); +} +#endif + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing special-purpose register FAULTMASK. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __enable_fault_irq(void) +{ + __ASM volatile ("cpsie f" : : : "memory"); +} + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting special-purpose register FAULTMASK. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __disable_fault_irq(void) +{ + __ASM volatile ("cpsid f" : : : "memory"); +} + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Base Priority (non-secure) + \details Returns the current value of the non-secure Base Priority register when in secure state. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri) +{ + __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Base Priority (non-secure) + \details Assigns the given value to the non-secure Base Priority register when in secure state. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); +} +#endif + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Fault Mask (non-secure) + \details Returns the current value of the non-secure Fault Mask register when in secure state. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Fault Mask (non-secure) + \details Assigns the given value to the non-secure Fault Mask register when in secure state. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); +} +#endif + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + +/** + \brief Get Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim" : "=r" (result) ); + return result; +#endif +} + +#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); +#endif +} +#endif + + +/** + \brief Get Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim" : "=r" (result) ); + return result; +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state. + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). + \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state. + \param [in] MainStackPtrLimit Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); +#endif +} +#endif + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#define __get_FPSCR (uint32_t)__builtin_arm_get_fpscr +#else +#define __get_FPSCR() ((uint32_t)0U) +#endif + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#define __set_FPSCR __builtin_arm_set_fpscr +#else +#define __set_FPSCR(x) ((void)(x)) +#endif + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) + +__STATIC_FORCEINLINE uint32_t __SADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__STATIC_FORCEINLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__STATIC_FORCEINLINE uint32_t __SADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USAD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#define __SSAT16(ARG1,ARG2) \ +({ \ + int32_t __RES, __ARG1 = (ARG1); \ + __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +#define __USAT16(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +__STATIC_FORCEINLINE uint32_t __UXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint32_t __SEL (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE int32_t __QADD( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE int32_t __QSUB( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ + ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) + +#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ + ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) + +#define __SXTB16_RORn(ARG1, ARG2) __SXTB16(__ROR(ARG1, ARG2)) + +#define __SXTAB16_RORn(ARG1, ARG2, ARG3) __SXTAB16(ARG1, __ROR(ARG2, ARG3)) + +__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) +{ + int32_t result; + + __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#endif /* (__ARM_FEATURE_DSP == 1) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#endif /* __CMSIS_ARMCLANG_H */ diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/CMSIS/Include/cmsis_compiler.h b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/CMSIS/Include/cmsis_compiler.h new file mode 100644 index 0000000000..adbf296f15 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/CMSIS/Include/cmsis_compiler.h @@ -0,0 +1,283 @@ +/**************************************************************************//** + * @file cmsis_compiler.h + * @brief CMSIS compiler generic header file + * @version V5.1.0 + * @date 09. October 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_COMPILER_H +#define __CMSIS_COMPILER_H + +#include + +/* + * Arm Compiler 4/5 + */ +#if defined ( __CC_ARM ) + #include "cmsis_armcc.h" + + +/* + * Arm Compiler 6.6 LTM (armclang) + */ +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) && (__ARMCC_VERSION < 6100100) + #include "cmsis_armclang_ltm.h" + + /* + * Arm Compiler above 6.10.1 (armclang) + */ +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6100100) + #include "cmsis_armclang.h" + + +/* + * GNU Compiler + */ +#elif defined ( __GNUC__ ) + #include "cmsis_gcc.h" + + +/* + * IAR Compiler + */ +#elif defined ( __ICCARM__ ) + #include + + +/* + * TI Arm Compiler + */ +#elif defined ( __TI_ARM__ ) + #include + + #ifndef __ASM + #define __ASM __asm + #endif + #ifndef __INLINE + #define __INLINE inline + #endif + #ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline + #endif + #ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __STATIC_INLINE + #endif + #ifndef __NO_RETURN + #define __NO_RETURN __attribute__((noreturn)) + #endif + #ifndef __USED + #define __USED __attribute__((used)) + #endif + #ifndef __WEAK + #define __WEAK __attribute__((weak)) + #endif + #ifndef __PACKED + #define __PACKED __attribute__((packed)) + #endif + #ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed)) + #endif + #ifndef __PACKED_UNION + #define __PACKED_UNION union __attribute__((packed)) + #endif + #ifndef __UNALIGNED_UINT32 /* deprecated */ + struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + #endif + #ifndef __UNALIGNED_UINT16_WRITE + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void*)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT16_READ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) + #endif + #ifndef __UNALIGNED_UINT32_WRITE + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT32_READ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) + #endif + #ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) + #endif + #ifndef __RESTRICT + #define __RESTRICT __restrict + #endif + #ifndef __COMPILER_BARRIER + #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored. + #define __COMPILER_BARRIER() (void)0 + #endif + + +/* + * TASKING Compiler + */ +#elif defined ( __TASKING__ ) + /* + * The CMSIS functions have been implemented as intrinsics in the compiler. + * Please use "carm -?i" to get an up to date list of all intrinsics, + * Including the CMSIS ones. + */ + + #ifndef __ASM + #define __ASM __asm + #endif + #ifndef __INLINE + #define __INLINE inline + #endif + #ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline + #endif + #ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __STATIC_INLINE + #endif + #ifndef __NO_RETURN + #define __NO_RETURN __attribute__((noreturn)) + #endif + #ifndef __USED + #define __USED __attribute__((used)) + #endif + #ifndef __WEAK + #define __WEAK __attribute__((weak)) + #endif + #ifndef __PACKED + #define __PACKED __packed__ + #endif + #ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __packed__ + #endif + #ifndef __PACKED_UNION + #define __PACKED_UNION union __packed__ + #endif + #ifndef __UNALIGNED_UINT32 /* deprecated */ + struct __packed__ T_UINT32 { uint32_t v; }; + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + #endif + #ifndef __UNALIGNED_UINT16_WRITE + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT16_READ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) + #endif + #ifndef __UNALIGNED_UINT32_WRITE + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT32_READ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) + #endif + #ifndef __ALIGNED + #define __ALIGNED(x) __align(x) + #endif + #ifndef __RESTRICT + #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. + #define __RESTRICT + #endif + #ifndef __COMPILER_BARRIER + #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored. + #define __COMPILER_BARRIER() (void)0 + #endif + + +/* + * COSMIC Compiler + */ +#elif defined ( __CSMC__ ) + #include + + #ifndef __ASM + #define __ASM _asm + #endif + #ifndef __INLINE + #define __INLINE inline + #endif + #ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline + #endif + #ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __STATIC_INLINE + #endif + #ifndef __NO_RETURN + // NO RETURN is automatically detected hence no warning here + #define __NO_RETURN + #endif + #ifndef __USED + #warning No compiler specific solution for __USED. __USED is ignored. + #define __USED + #endif + #ifndef __WEAK + #define __WEAK __weak + #endif + #ifndef __PACKED + #define __PACKED @packed + #endif + #ifndef __PACKED_STRUCT + #define __PACKED_STRUCT @packed struct + #endif + #ifndef __PACKED_UNION + #define __PACKED_UNION @packed union + #endif + #ifndef __UNALIGNED_UINT32 /* deprecated */ + @packed struct T_UINT32 { uint32_t v; }; + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + #endif + #ifndef __UNALIGNED_UINT16_WRITE + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT16_READ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) + #endif + #ifndef __UNALIGNED_UINT32_WRITE + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT32_READ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) + #endif + #ifndef __ALIGNED + #warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored. + #define __ALIGNED(x) + #endif + #ifndef __RESTRICT + #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. + #define __RESTRICT + #endif + #ifndef __COMPILER_BARRIER + #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored. + #define __COMPILER_BARRIER() (void)0 + #endif + + +#else + #error Unknown compiler. +#endif + + +#endif /* __CMSIS_COMPILER_H */ + diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/CMSIS/Include/cmsis_gcc.h b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/CMSIS/Include/cmsis_gcc.h new file mode 100644 index 0000000000..67bda4ef3c --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/CMSIS/Include/cmsis_gcc.h @@ -0,0 +1,2211 @@ +/**************************************************************************//** + * @file cmsis_gcc.h + * @brief CMSIS compiler GCC header file + * @version V5.4.1 + * @date 27. May 2021 + ******************************************************************************/ +/* + * Copyright (c) 2009-2021 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_GCC_H +#define __CMSIS_GCC_H + +/* ignore some GCC warnings */ +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wsign-conversion" +#pragma GCC diagnostic ignored "-Wconversion" +#pragma GCC diagnostic ignored "-Wunused-parameter" + +/* Fallback for __has_builtin */ +#ifndef __has_builtin + #define __has_builtin(x) (0) +#endif + +/* CMSIS compiler specific defines */ +#ifndef __ASM + #define __ASM __asm +#endif +#ifndef __INLINE + #define __INLINE inline +#endif +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline +#endif +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __attribute__((always_inline)) static inline +#endif +#ifndef __NO_RETURN + #define __NO_RETURN __attribute__((__noreturn__)) +#endif +#ifndef __USED + #define __USED __attribute__((used)) +#endif +#ifndef __WEAK + #define __WEAK __attribute__((weak)) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_UNION + #define __PACKED_UNION union __attribute__((packed, aligned(1))) +#endif +#ifndef __UNALIGNED_UINT32 /* deprecated */ + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) +#endif +#ifndef __UNALIGNED_UINT16_WRITE + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT16_READ + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) +#endif +#ifndef __UNALIGNED_UINT32_WRITE + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT32_READ + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) +#endif +#ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __RESTRICT + #define __RESTRICT __restrict +#endif +#ifndef __COMPILER_BARRIER + #define __COMPILER_BARRIER() __ASM volatile("":::"memory") +#endif + +/* ######################### Startup and Lowlevel Init ######################## */ + +#ifndef __PROGRAM_START + +/** + \brief Initializes data and bss sections + \details This default implementations initialized all data and additional bss + sections relying on .copy.table and .zero.table specified properly + in the used linker script. + + */ +__STATIC_FORCEINLINE __NO_RETURN void __cmsis_start(void) +{ + extern void _start(void) __NO_RETURN; + + typedef struct { + uint32_t const* src; + uint32_t* dest; + uint32_t wlen; + } __copy_table_t; + + typedef struct { + uint32_t* dest; + uint32_t wlen; + } __zero_table_t; + + extern const __copy_table_t __copy_table_start__; + extern const __copy_table_t __copy_table_end__; + extern const __zero_table_t __zero_table_start__; + extern const __zero_table_t __zero_table_end__; + + for (__copy_table_t const* pTable = &__copy_table_start__; pTable < &__copy_table_end__; ++pTable) { + for(uint32_t i=0u; iwlen; ++i) { + pTable->dest[i] = pTable->src[i]; + } + } + + for (__zero_table_t const* pTable = &__zero_table_start__; pTable < &__zero_table_end__; ++pTable) { + for(uint32_t i=0u; iwlen; ++i) { + pTable->dest[i] = 0u; + } + } + + _start(); +} + +#define __PROGRAM_START __cmsis_start +#endif + +#ifndef __INITIAL_SP +#define __INITIAL_SP __StackTop +#endif + +#ifndef __STACK_LIMIT +#define __STACK_LIMIT __StackLimit +#endif + +#ifndef __VECTOR_TABLE +#define __VECTOR_TABLE __Vectors +#endif + +#ifndef __VECTOR_TABLE_ATTRIBUTE +#define __VECTOR_TABLE_ATTRIBUTE __attribute__((used, section(".vectors"))) +#endif + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +#ifndef __STACK_SEAL +#define __STACK_SEAL __StackSeal +#endif + +#ifndef __TZ_STACK_SEAL_SIZE +#define __TZ_STACK_SEAL_SIZE 8U +#endif + +#ifndef __TZ_STACK_SEAL_VALUE +#define __TZ_STACK_SEAL_VALUE 0xFEF5EDA5FEF5EDA5ULL +#endif + + +__STATIC_FORCEINLINE void __TZ_set_STACKSEAL_S (uint32_t* stackTop) { + *((uint64_t *)stackTop) = __TZ_STACK_SEAL_VALUE; +} +#endif + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/* Define macros for porting to both thumb1 and thumb2. + * For thumb1, use low register (r0-r7), specified by constraint "l" + * Otherwise, use general registers, specified by constraint "r" */ +#if defined (__thumb__) && !defined (__thumb2__) +#define __CMSIS_GCC_OUT_REG(r) "=l" (r) +#define __CMSIS_GCC_RW_REG(r) "+l" (r) +#define __CMSIS_GCC_USE_REG(r) "l" (r) +#else +#define __CMSIS_GCC_OUT_REG(r) "=r" (r) +#define __CMSIS_GCC_RW_REG(r) "+r" (r) +#define __CMSIS_GCC_USE_REG(r) "r" (r) +#endif + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP() __ASM volatile ("nop") + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +#define __WFI() __ASM volatile ("wfi":::"memory") + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE() __ASM volatile ("wfe":::"memory") + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV() __ASM volatile ("sev") + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +__STATIC_FORCEINLINE void __ISB(void) +{ + __ASM volatile ("isb 0xF":::"memory"); +} + + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +__STATIC_FORCEINLINE void __DSB(void) +{ + __ASM volatile ("dsb 0xF":::"memory"); +} + + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +__STATIC_FORCEINLINE void __DMB(void) +{ + __ASM volatile ("dmb 0xF":::"memory"); +} + + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE uint32_t __REV(uint32_t value) +{ +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5) + return __builtin_bswap32(value); +#else + uint32_t result; + + __ASM ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return result; +#endif +} + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE uint32_t __REV16(uint32_t value) +{ + uint32_t result; + + __ASM ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return result; +} + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE int16_t __REVSH(int16_t value) +{ +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + return (int16_t)__builtin_bswap16(value); +#else + int16_t result; + + __ASM ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return result; +#endif +} + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) +{ + op2 %= 32U; + if (op2 == 0U) + { + return op1; + } + return (op1 >> op2) | (op1 << (32U - op2)); +} + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __ASM volatile ("bkpt "#value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE uint32_t __RBIT(uint32_t value) +{ + uint32_t result; + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) + __ASM ("rbit %0, %1" : "=r" (result) : "r" (value) ); +#else + uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */ + + result = value; /* r will be reversed bits of v; first get LSB of v */ + for (value >>= 1U; value != 0U; value >>= 1U) + { + result <<= 1U; + result |= value & 1U; + s--; + } + result <<= s; /* shift when v's highest bits are zero */ +#endif + return result; +} + + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +__STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value) +{ + /* Even though __builtin_clz produces a CLZ instruction on ARM, formally + __builtin_clz(0) is undefined behaviour, so handle this case specially. + This guarantees ARM-compatible results if happening to compile on a non-ARM + target, and ensures the compiler doesn't decide to activate any + optimisations using the logic "value was passed to __builtin_clz, so it + is non-zero". + ARM GCC 7.3 and possibly earlier will optimise this test away, leaving a + single CLZ instruction. + */ + if (value == 0U) + { + return 32U; + } + return __builtin_clz(value); +} + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDREXB(volatile uint8_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDREXH(volatile uint16_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDREXW(volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); + return(result); +} + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr) +{ + uint32_t result; + + __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr) +{ + uint32_t result; + + __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); + return(result); +} + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +__STATIC_FORCEINLINE void __CLREX(void) +{ + __ASM volatile ("clrex" ::: "memory"); +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] ARG1 Value to be saturated + \param [in] ARG2 Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT(ARG1, ARG2) \ +__extension__ \ +({ \ + int32_t __RES, __ARG1 = (ARG1); \ + __ASM volatile ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) : "cc" ); \ + __RES; \ + }) + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] ARG1 Value to be saturated + \param [in] ARG2 Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT(ARG1, ARG2) \ +__extension__ \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM volatile ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) : "cc" ); \ + __RES; \ + }) + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" ); +#endif + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" ); +#endif + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) ); +} + +#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat) +{ + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; +} + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat) +{ + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief Load-Acquire (8 bit) + \details Executes a LDAB instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return ((uint8_t) result); +} + + +/** + \brief Load-Acquire (16 bit) + \details Executes a LDAH instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return ((uint16_t) result); +} + + +/** + \brief Load-Acquire (32 bit) + \details Executes a LDA instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return(result); +} + + +/** + \brief Store-Release (8 bit) + \details Executes a STLB instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Store-Release (16 bit) + \details Executes a STLH instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Store-Release (32 bit) + \details Executes a STL instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Load-Acquire Exclusive (8 bit) + \details Executes a LDAB exclusive instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDAEXB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldaexb %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return ((uint8_t) result); +} + + +/** + \brief Load-Acquire Exclusive (16 bit) + \details Executes a LDAH exclusive instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDAEXH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldaexh %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return ((uint16_t) result); +} + + +/** + \brief Load-Acquire Exclusive (32 bit) + \details Executes a LDA exclusive instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDAEX(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldaex %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return(result); +} + + +/** + \brief Store-Release Exclusive (8 bit) + \details Executes a STLB exclusive instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("stlexb %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); + return(result); +} + + +/** + \brief Store-Release Exclusive (16 bit) + \details Executes a STLH exclusive instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("stlexh %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); + return(result); +} + + +/** + \brief Store-Release Exclusive (32 bit) + \details Executes a STL exclusive instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("stlex %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); + return(result); +} + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing special-purpose register PRIMASK. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __enable_irq(void) +{ + __ASM volatile ("cpsie i" : : : "memory"); +} + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting special-purpose register PRIMASK. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __disable_irq(void) +{ + __ASM volatile ("cpsid i" : : : "memory"); +} + + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CONTROL(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Control Register (non-secure) + \details Returns the content of the non-secure Control Register when in secure mode. + \return non-secure Control Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) +{ + __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); + __ISB(); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Control Register (non-secure) + \details Writes the given value to the non-secure Control Register when in secure state. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) +{ + __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); + __ISB(); +} +#endif + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_IPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_APSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_xPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer (non-secure) + \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state. + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state. + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); +} +#endif + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer (non-secure) + \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state. + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); +} +#endif + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Stack Pointer (non-secure) + \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state. + \return SP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, sp_ns" : "=r" (result) ); + return(result); +} + + +/** + \brief Set Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state. + \param [in] topOfStack Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack) +{ + __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : ); +} +#endif + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Priority Mask (non-secure) + \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Priority Mask (non-secure) + \details Assigns the given value to the non-secure Priority Mask Register when in secure state. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) +{ + __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); +} +#endif + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing special-purpose register FAULTMASK. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __enable_fault_irq(void) +{ + __ASM volatile ("cpsie f" : : : "memory"); +} + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting special-purpose register FAULTMASK. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __disable_fault_irq(void) +{ + __ASM volatile ("cpsid f" : : : "memory"); +} + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Base Priority (non-secure) + \details Returns the current value of the non-secure Base Priority register when in secure state. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri) +{ + __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Base Priority (non-secure) + \details Assigns the given value to the non-secure Base Priority register when in secure state. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); +} +#endif + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Fault Mask (non-secure) + \details Returns the current value of the non-secure Fault Mask register when in secure state. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Fault Mask (non-secure) + \details Assigns the given value to the non-secure Fault Mask register when in secure state. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); +} +#endif + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + +/** + \brief Get Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim" : "=r" (result) ); + return result; +#endif +} + +#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); +#endif +} +#endif + + +/** + \brief Get Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim" : "=r" (result) ); + return result; +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state. + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). + \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state. + \param [in] MainStackPtrLimit Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); +#endif +} +#endif + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +__STATIC_FORCEINLINE uint32_t __get_FPSCR(void) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#if __has_builtin(__builtin_arm_get_fpscr) +// Re-enable using built-in when GCC has been fixed +// || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2) + /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */ + return __builtin_arm_get_fpscr(); +#else + uint32_t result; + + __ASM volatile ("VMRS %0, fpscr" : "=r" (result) ); + return(result); +#endif +#else + return(0U); +#endif +} + + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +__STATIC_FORCEINLINE void __set_FPSCR(uint32_t fpscr) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#if __has_builtin(__builtin_arm_set_fpscr) +// Re-enable using built-in when GCC has been fixed +// || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2) + /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */ + __builtin_arm_set_fpscr(fpscr); +#else + __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc", "memory"); +#endif +#else + (void)fpscr; +#endif +} + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) + +__STATIC_FORCEINLINE uint32_t __SADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__STATIC_FORCEINLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__STATIC_FORCEINLINE uint32_t __SADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USAD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#define __SSAT16(ARG1, ARG2) \ +__extension__ \ +({ \ + int32_t __RES, __ARG1 = (ARG1); \ + __ASM volatile ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) : "cc" ); \ + __RES; \ + }) + +#define __USAT16(ARG1, ARG2) \ +__extension__ \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM volatile ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) : "cc" ); \ + __RES; \ + }) + +__STATIC_FORCEINLINE uint32_t __UXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM ("uxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM ("sxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTB16_RORn(uint32_t op1, uint32_t rotate) +{ + uint32_t result; + if (__builtin_constant_p(rotate) && ((rotate == 8U) || (rotate == 16U) || (rotate == 24U))) { + __ASM volatile ("sxtb16 %0, %1, ROR %2" : "=r" (result) : "r" (op1), "i" (rotate) ); + } else { + result = __SXTB16(__ROR(op1, rotate)) ; + } + return result; +} + +__STATIC_FORCEINLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTAB16_RORn(uint32_t op1, uint32_t op2, uint32_t rotate) +{ + uint32_t result; + if (__builtin_constant_p(rotate) && ((rotate == 8U) || (rotate == 16U) || (rotate == 24U))) { + __ASM volatile ("sxtab16 %0, %1, %2, ROR %3" : "=r" (result) : "r" (op1) , "r" (op2) , "i" (rotate)); + } else { + result = __SXTAB16(op1, __ROR(op2, rotate)); + } + return result; +} + + +__STATIC_FORCEINLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint32_t __SEL (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE int32_t __QADD( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE int32_t __QSUB( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +#define __PKHBT(ARG1,ARG2,ARG3) \ +__extension__ \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) + +#define __PKHTB(ARG1,ARG2,ARG3) \ +__extension__ \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + if (ARG3 == 0) \ + __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \ + else \ + __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) + + +__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) +{ + int32_t result; + + __ASM ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#endif /* (__ARM_FEATURE_DSP == 1) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#pragma GCC diagnostic pop + +#endif /* __CMSIS_GCC_H */ diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/CMSIS/Include/cmsis_iccarm.h b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/CMSIS/Include/cmsis_iccarm.h new file mode 100644 index 0000000000..65b824b009 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/CMSIS/Include/cmsis_iccarm.h @@ -0,0 +1,1002 @@ +/**************************************************************************//** + * @file cmsis_iccarm.h + * @brief CMSIS compiler ICCARM (IAR Compiler for Arm) header file + * @version V5.3.0 + * @date 14. April 2021 + ******************************************************************************/ + +//------------------------------------------------------------------------------ +// +// Copyright (c) 2017-2021 IAR Systems +// Copyright (c) 2017-2021 Arm Limited. All rights reserved. +// +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License") +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +//------------------------------------------------------------------------------ + + +#ifndef __CMSIS_ICCARM_H__ +#define __CMSIS_ICCARM_H__ + +#ifndef __ICCARM__ + #error This file should only be compiled by ICCARM +#endif + +#pragma system_include + +#define __IAR_FT _Pragma("inline=forced") __intrinsic + +#if (__VER__ >= 8000000) + #define __ICCARM_V8 1 +#else + #define __ICCARM_V8 0 +#endif + +#ifndef __ALIGNED + #if __ICCARM_V8 + #define __ALIGNED(x) __attribute__((aligned(x))) + #elif (__VER__ >= 7080000) + /* Needs IAR language extensions */ + #define __ALIGNED(x) __attribute__((aligned(x))) + #else + #warning No compiler specific solution for __ALIGNED.__ALIGNED is ignored. + #define __ALIGNED(x) + #endif +#endif + + +/* Define compiler macros for CPU architecture, used in CMSIS 5. + */ +#if __ARM_ARCH_6M__ || __ARM_ARCH_7M__ || __ARM_ARCH_7EM__ || __ARM_ARCH_8M_BASE__ || __ARM_ARCH_8M_MAIN__ +/* Macros already defined */ +#else + #if defined(__ARM8M_MAINLINE__) || defined(__ARM8EM_MAINLINE__) + #define __ARM_ARCH_8M_MAIN__ 1 + #elif defined(__ARM8M_BASELINE__) + #define __ARM_ARCH_8M_BASE__ 1 + #elif defined(__ARM_ARCH_PROFILE) && __ARM_ARCH_PROFILE == 'M' + #if __ARM_ARCH == 6 + #define __ARM_ARCH_6M__ 1 + #elif __ARM_ARCH == 7 + #if __ARM_FEATURE_DSP + #define __ARM_ARCH_7EM__ 1 + #else + #define __ARM_ARCH_7M__ 1 + #endif + #endif /* __ARM_ARCH */ + #endif /* __ARM_ARCH_PROFILE == 'M' */ +#endif + +/* Alternativ core deduction for older ICCARM's */ +#if !defined(__ARM_ARCH_6M__) && !defined(__ARM_ARCH_7M__) && !defined(__ARM_ARCH_7EM__) && \ + !defined(__ARM_ARCH_8M_BASE__) && !defined(__ARM_ARCH_8M_MAIN__) + #if defined(__ARM6M__) && (__CORE__ == __ARM6M__) + #define __ARM_ARCH_6M__ 1 + #elif defined(__ARM7M__) && (__CORE__ == __ARM7M__) + #define __ARM_ARCH_7M__ 1 + #elif defined(__ARM7EM__) && (__CORE__ == __ARM7EM__) + #define __ARM_ARCH_7EM__ 1 + #elif defined(__ARM8M_BASELINE__) && (__CORE == __ARM8M_BASELINE__) + #define __ARM_ARCH_8M_BASE__ 1 + #elif defined(__ARM8M_MAINLINE__) && (__CORE == __ARM8M_MAINLINE__) + #define __ARM_ARCH_8M_MAIN__ 1 + #elif defined(__ARM8EM_MAINLINE__) && (__CORE == __ARM8EM_MAINLINE__) + #define __ARM_ARCH_8M_MAIN__ 1 + #else + #error "Unknown target." + #endif +#endif + + + +#if defined(__ARM_ARCH_6M__) && __ARM_ARCH_6M__==1 + #define __IAR_M0_FAMILY 1 +#elif defined(__ARM_ARCH_8M_BASE__) && __ARM_ARCH_8M_BASE__==1 + #define __IAR_M0_FAMILY 1 +#else + #define __IAR_M0_FAMILY 0 +#endif + + +#ifndef __ASM + #define __ASM __asm +#endif + +#ifndef __COMPILER_BARRIER + #define __COMPILER_BARRIER() __ASM volatile("":::"memory") +#endif + +#ifndef __INLINE + #define __INLINE inline +#endif + +#ifndef __NO_RETURN + #if __ICCARM_V8 + #define __NO_RETURN __attribute__((__noreturn__)) + #else + #define __NO_RETURN _Pragma("object_attribute=__noreturn") + #endif +#endif + +#ifndef __PACKED + #if __ICCARM_V8 + #define __PACKED __attribute__((packed, aligned(1))) + #else + /* Needs IAR language extensions */ + #define __PACKED __packed + #endif +#endif + +#ifndef __PACKED_STRUCT + #if __ICCARM_V8 + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) + #else + /* Needs IAR language extensions */ + #define __PACKED_STRUCT __packed struct + #endif +#endif + +#ifndef __PACKED_UNION + #if __ICCARM_V8 + #define __PACKED_UNION union __attribute__((packed, aligned(1))) + #else + /* Needs IAR language extensions */ + #define __PACKED_UNION __packed union + #endif +#endif + +#ifndef __RESTRICT + #if __ICCARM_V8 + #define __RESTRICT __restrict + #else + /* Needs IAR language extensions */ + #define __RESTRICT restrict + #endif +#endif + +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline +#endif + +#ifndef __FORCEINLINE + #define __FORCEINLINE _Pragma("inline=forced") +#endif + +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __FORCEINLINE __STATIC_INLINE +#endif + +#ifndef __UNALIGNED_UINT16_READ +#pragma language=save +#pragma language=extended +__IAR_FT uint16_t __iar_uint16_read(void const *ptr) +{ + return *(__packed uint16_t*)(ptr); +} +#pragma language=restore +#define __UNALIGNED_UINT16_READ(PTR) __iar_uint16_read(PTR) +#endif + + +#ifndef __UNALIGNED_UINT16_WRITE +#pragma language=save +#pragma language=extended +__IAR_FT void __iar_uint16_write(void const *ptr, uint16_t val) +{ + *(__packed uint16_t*)(ptr) = val;; +} +#pragma language=restore +#define __UNALIGNED_UINT16_WRITE(PTR,VAL) __iar_uint16_write(PTR,VAL) +#endif + +#ifndef __UNALIGNED_UINT32_READ +#pragma language=save +#pragma language=extended +__IAR_FT uint32_t __iar_uint32_read(void const *ptr) +{ + return *(__packed uint32_t*)(ptr); +} +#pragma language=restore +#define __UNALIGNED_UINT32_READ(PTR) __iar_uint32_read(PTR) +#endif + +#ifndef __UNALIGNED_UINT32_WRITE +#pragma language=save +#pragma language=extended +__IAR_FT void __iar_uint32_write(void const *ptr, uint32_t val) +{ + *(__packed uint32_t*)(ptr) = val;; +} +#pragma language=restore +#define __UNALIGNED_UINT32_WRITE(PTR,VAL) __iar_uint32_write(PTR,VAL) +#endif + +#ifndef __UNALIGNED_UINT32 /* deprecated */ +#pragma language=save +#pragma language=extended +__packed struct __iar_u32 { uint32_t v; }; +#pragma language=restore +#define __UNALIGNED_UINT32(PTR) (((struct __iar_u32 *)(PTR))->v) +#endif + +#ifndef __USED + #if __ICCARM_V8 + #define __USED __attribute__((used)) + #else + #define __USED _Pragma("__root") + #endif +#endif + +#undef __WEAK /* undo the definition from DLib_Defaults.h */ +#ifndef __WEAK + #if __ICCARM_V8 + #define __WEAK __attribute__((weak)) + #else + #define __WEAK _Pragma("__weak") + #endif +#endif + +#ifndef __PROGRAM_START +#define __PROGRAM_START __iar_program_start +#endif + +#ifndef __INITIAL_SP +#define __INITIAL_SP CSTACK$$Limit +#endif + +#ifndef __STACK_LIMIT +#define __STACK_LIMIT CSTACK$$Base +#endif + +#ifndef __VECTOR_TABLE +#define __VECTOR_TABLE __vector_table +#endif + +#ifndef __VECTOR_TABLE_ATTRIBUTE +#define __VECTOR_TABLE_ATTRIBUTE @".intvec" +#endif + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +#ifndef __STACK_SEAL +#define __STACK_SEAL STACKSEAL$$Base +#endif + +#ifndef __TZ_STACK_SEAL_SIZE +#define __TZ_STACK_SEAL_SIZE 8U +#endif + +#ifndef __TZ_STACK_SEAL_VALUE +#define __TZ_STACK_SEAL_VALUE 0xFEF5EDA5FEF5EDA5ULL +#endif + +__STATIC_FORCEINLINE void __TZ_set_STACKSEAL_S (uint32_t* stackTop) { + *((uint64_t *)stackTop) = __TZ_STACK_SEAL_VALUE; +} +#endif + +#ifndef __ICCARM_INTRINSICS_VERSION__ + #define __ICCARM_INTRINSICS_VERSION__ 0 +#endif + +#if __ICCARM_INTRINSICS_VERSION__ == 2 + + #if defined(__CLZ) + #undef __CLZ + #endif + #if defined(__REVSH) + #undef __REVSH + #endif + #if defined(__RBIT) + #undef __RBIT + #endif + #if defined(__SSAT) + #undef __SSAT + #endif + #if defined(__USAT) + #undef __USAT + #endif + + #include "iccarm_builtin.h" + + #define __disable_fault_irq __iar_builtin_disable_fiq + #define __disable_irq __iar_builtin_disable_interrupt + #define __enable_fault_irq __iar_builtin_enable_fiq + #define __enable_irq __iar_builtin_enable_interrupt + #define __arm_rsr __iar_builtin_rsr + #define __arm_wsr __iar_builtin_wsr + + + #define __get_APSR() (__arm_rsr("APSR")) + #define __get_BASEPRI() (__arm_rsr("BASEPRI")) + #define __get_CONTROL() (__arm_rsr("CONTROL")) + #define __get_FAULTMASK() (__arm_rsr("FAULTMASK")) + + #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) + #define __get_FPSCR() (__arm_rsr("FPSCR")) + #define __set_FPSCR(VALUE) (__arm_wsr("FPSCR", (VALUE))) + #else + #define __get_FPSCR() ( 0 ) + #define __set_FPSCR(VALUE) ((void)VALUE) + #endif + + #define __get_IPSR() (__arm_rsr("IPSR")) + #define __get_MSP() (__arm_rsr("MSP")) + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + #define __get_MSPLIM() (0U) + #else + #define __get_MSPLIM() (__arm_rsr("MSPLIM")) + #endif + #define __get_PRIMASK() (__arm_rsr("PRIMASK")) + #define __get_PSP() (__arm_rsr("PSP")) + + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + #define __get_PSPLIM() (0U) + #else + #define __get_PSPLIM() (__arm_rsr("PSPLIM")) + #endif + + #define __get_xPSR() (__arm_rsr("xPSR")) + + #define __set_BASEPRI(VALUE) (__arm_wsr("BASEPRI", (VALUE))) + #define __set_BASEPRI_MAX(VALUE) (__arm_wsr("BASEPRI_MAX", (VALUE))) + +__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) +{ + __arm_wsr("CONTROL", control); + __iar_builtin_ISB(); +} + + #define __set_FAULTMASK(VALUE) (__arm_wsr("FAULTMASK", (VALUE))) + #define __set_MSP(VALUE) (__arm_wsr("MSP", (VALUE))) + + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + #define __set_MSPLIM(VALUE) ((void)(VALUE)) + #else + #define __set_MSPLIM(VALUE) (__arm_wsr("MSPLIM", (VALUE))) + #endif + #define __set_PRIMASK(VALUE) (__arm_wsr("PRIMASK", (VALUE))) + #define __set_PSP(VALUE) (__arm_wsr("PSP", (VALUE))) + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + #define __set_PSPLIM(VALUE) ((void)(VALUE)) + #else + #define __set_PSPLIM(VALUE) (__arm_wsr("PSPLIM", (VALUE))) + #endif + + #define __TZ_get_CONTROL_NS() (__arm_rsr("CONTROL_NS")) + +__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) +{ + __arm_wsr("CONTROL_NS", control); + __iar_builtin_ISB(); +} + + #define __TZ_get_PSP_NS() (__arm_rsr("PSP_NS")) + #define __TZ_set_PSP_NS(VALUE) (__arm_wsr("PSP_NS", (VALUE))) + #define __TZ_get_MSP_NS() (__arm_rsr("MSP_NS")) + #define __TZ_set_MSP_NS(VALUE) (__arm_wsr("MSP_NS", (VALUE))) + #define __TZ_get_SP_NS() (__arm_rsr("SP_NS")) + #define __TZ_set_SP_NS(VALUE) (__arm_wsr("SP_NS", (VALUE))) + #define __TZ_get_PRIMASK_NS() (__arm_rsr("PRIMASK_NS")) + #define __TZ_set_PRIMASK_NS(VALUE) (__arm_wsr("PRIMASK_NS", (VALUE))) + #define __TZ_get_BASEPRI_NS() (__arm_rsr("BASEPRI_NS")) + #define __TZ_set_BASEPRI_NS(VALUE) (__arm_wsr("BASEPRI_NS", (VALUE))) + #define __TZ_get_FAULTMASK_NS() (__arm_rsr("FAULTMASK_NS")) + #define __TZ_set_FAULTMASK_NS(VALUE)(__arm_wsr("FAULTMASK_NS", (VALUE))) + + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + #define __TZ_get_PSPLIM_NS() (0U) + #define __TZ_set_PSPLIM_NS(VALUE) ((void)(VALUE)) + #else + #define __TZ_get_PSPLIM_NS() (__arm_rsr("PSPLIM_NS")) + #define __TZ_set_PSPLIM_NS(VALUE) (__arm_wsr("PSPLIM_NS", (VALUE))) + #endif + + #define __TZ_get_MSPLIM_NS() (__arm_rsr("MSPLIM_NS")) + #define __TZ_set_MSPLIM_NS(VALUE) (__arm_wsr("MSPLIM_NS", (VALUE))) + + #define __NOP __iar_builtin_no_operation + + #define __CLZ __iar_builtin_CLZ + #define __CLREX __iar_builtin_CLREX + + #define __DMB __iar_builtin_DMB + #define __DSB __iar_builtin_DSB + #define __ISB __iar_builtin_ISB + + #define __LDREXB __iar_builtin_LDREXB + #define __LDREXH __iar_builtin_LDREXH + #define __LDREXW __iar_builtin_LDREX + + #define __RBIT __iar_builtin_RBIT + #define __REV __iar_builtin_REV + #define __REV16 __iar_builtin_REV16 + + __IAR_FT int16_t __REVSH(int16_t val) + { + return (int16_t) __iar_builtin_REVSH(val); + } + + #define __ROR __iar_builtin_ROR + #define __RRX __iar_builtin_RRX + + #define __SEV __iar_builtin_SEV + + #if !__IAR_M0_FAMILY + #define __SSAT __iar_builtin_SSAT + #endif + + #define __STREXB __iar_builtin_STREXB + #define __STREXH __iar_builtin_STREXH + #define __STREXW __iar_builtin_STREX + + #if !__IAR_M0_FAMILY + #define __USAT __iar_builtin_USAT + #endif + + #define __WFE __iar_builtin_WFE + #define __WFI __iar_builtin_WFI + + #if __ARM_MEDIA__ + #define __SADD8 __iar_builtin_SADD8 + #define __QADD8 __iar_builtin_QADD8 + #define __SHADD8 __iar_builtin_SHADD8 + #define __UADD8 __iar_builtin_UADD8 + #define __UQADD8 __iar_builtin_UQADD8 + #define __UHADD8 __iar_builtin_UHADD8 + #define __SSUB8 __iar_builtin_SSUB8 + #define __QSUB8 __iar_builtin_QSUB8 + #define __SHSUB8 __iar_builtin_SHSUB8 + #define __USUB8 __iar_builtin_USUB8 + #define __UQSUB8 __iar_builtin_UQSUB8 + #define __UHSUB8 __iar_builtin_UHSUB8 + #define __SADD16 __iar_builtin_SADD16 + #define __QADD16 __iar_builtin_QADD16 + #define __SHADD16 __iar_builtin_SHADD16 + #define __UADD16 __iar_builtin_UADD16 + #define __UQADD16 __iar_builtin_UQADD16 + #define __UHADD16 __iar_builtin_UHADD16 + #define __SSUB16 __iar_builtin_SSUB16 + #define __QSUB16 __iar_builtin_QSUB16 + #define __SHSUB16 __iar_builtin_SHSUB16 + #define __USUB16 __iar_builtin_USUB16 + #define __UQSUB16 __iar_builtin_UQSUB16 + #define __UHSUB16 __iar_builtin_UHSUB16 + #define __SASX __iar_builtin_SASX + #define __QASX __iar_builtin_QASX + #define __SHASX __iar_builtin_SHASX + #define __UASX __iar_builtin_UASX + #define __UQASX __iar_builtin_UQASX + #define __UHASX __iar_builtin_UHASX + #define __SSAX __iar_builtin_SSAX + #define __QSAX __iar_builtin_QSAX + #define __SHSAX __iar_builtin_SHSAX + #define __USAX __iar_builtin_USAX + #define __UQSAX __iar_builtin_UQSAX + #define __UHSAX __iar_builtin_UHSAX + #define __USAD8 __iar_builtin_USAD8 + #define __USADA8 __iar_builtin_USADA8 + #define __SSAT16 __iar_builtin_SSAT16 + #define __USAT16 __iar_builtin_USAT16 + #define __UXTB16 __iar_builtin_UXTB16 + #define __UXTAB16 __iar_builtin_UXTAB16 + #define __SXTB16 __iar_builtin_SXTB16 + #define __SXTAB16 __iar_builtin_SXTAB16 + #define __SMUAD __iar_builtin_SMUAD + #define __SMUADX __iar_builtin_SMUADX + #define __SMMLA __iar_builtin_SMMLA + #define __SMLAD __iar_builtin_SMLAD + #define __SMLADX __iar_builtin_SMLADX + #define __SMLALD __iar_builtin_SMLALD + #define __SMLALDX __iar_builtin_SMLALDX + #define __SMUSD __iar_builtin_SMUSD + #define __SMUSDX __iar_builtin_SMUSDX + #define __SMLSD __iar_builtin_SMLSD + #define __SMLSDX __iar_builtin_SMLSDX + #define __SMLSLD __iar_builtin_SMLSLD + #define __SMLSLDX __iar_builtin_SMLSLDX + #define __SEL __iar_builtin_SEL + #define __QADD __iar_builtin_QADD + #define __QSUB __iar_builtin_QSUB + #define __PKHBT __iar_builtin_PKHBT + #define __PKHTB __iar_builtin_PKHTB + #endif + +#else /* __ICCARM_INTRINSICS_VERSION__ == 2 */ + + #if __IAR_M0_FAMILY + /* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */ + #define __CLZ __cmsis_iar_clz_not_active + #define __SSAT __cmsis_iar_ssat_not_active + #define __USAT __cmsis_iar_usat_not_active + #define __RBIT __cmsis_iar_rbit_not_active + #define __get_APSR __cmsis_iar_get_APSR_not_active + #endif + + + #if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) )) + #define __get_FPSCR __cmsis_iar_get_FPSR_not_active + #define __set_FPSCR __cmsis_iar_set_FPSR_not_active + #endif + + #ifdef __INTRINSICS_INCLUDED + #error intrinsics.h is already included previously! + #endif + + #include + + #if __IAR_M0_FAMILY + /* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */ + #undef __CLZ + #undef __SSAT + #undef __USAT + #undef __RBIT + #undef __get_APSR + + __STATIC_INLINE uint8_t __CLZ(uint32_t data) + { + if (data == 0U) { return 32U; } + + uint32_t count = 0U; + uint32_t mask = 0x80000000U; + + while ((data & mask) == 0U) + { + count += 1U; + mask = mask >> 1U; + } + return count; + } + + __STATIC_INLINE uint32_t __RBIT(uint32_t v) + { + uint8_t sc = 31U; + uint32_t r = v; + for (v >>= 1U; v; v >>= 1U) + { + r <<= 1U; + r |= v & 1U; + sc--; + } + return (r << sc); + } + + __STATIC_INLINE uint32_t __get_APSR(void) + { + uint32_t res; + __asm("MRS %0,APSR" : "=r" (res)); + return res; + } + + #endif + + #if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) )) + #undef __get_FPSCR + #undef __set_FPSCR + #define __get_FPSCR() (0) + #define __set_FPSCR(VALUE) ((void)VALUE) + #endif + + #pragma diag_suppress=Pe940 + #pragma diag_suppress=Pe177 + + #define __enable_irq __enable_interrupt + #define __disable_irq __disable_interrupt + #define __NOP __no_operation + + #define __get_xPSR __get_PSR + + #if (!defined(__ARM_ARCH_6M__) || __ARM_ARCH_6M__==0) + + __IAR_FT uint32_t __LDREXW(uint32_t volatile *ptr) + { + return __LDREX((unsigned long *)ptr); + } + + __IAR_FT uint32_t __STREXW(uint32_t value, uint32_t volatile *ptr) + { + return __STREX(value, (unsigned long *)ptr); + } + #endif + + + /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */ + #if (__CORTEX_M >= 0x03) + + __IAR_FT uint32_t __RRX(uint32_t value) + { + uint32_t result; + __ASM volatile("RRX %0, %1" : "=r"(result) : "r" (value)); + return(result); + } + + __IAR_FT void __set_BASEPRI_MAX(uint32_t value) + { + __asm volatile("MSR BASEPRI_MAX,%0"::"r" (value)); + } + + + #define __enable_fault_irq __enable_fiq + #define __disable_fault_irq __disable_fiq + + + #endif /* (__CORTEX_M >= 0x03) */ + + __IAR_FT uint32_t __ROR(uint32_t op1, uint32_t op2) + { + return (op1 >> op2) | (op1 << ((sizeof(op1)*8)-op2)); + } + + #if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + + __IAR_FT uint32_t __get_MSPLIM(void) + { + uint32_t res; + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + res = 0U; + #else + __asm volatile("MRS %0,MSPLIM" : "=r" (res)); + #endif + return res; + } + + __IAR_FT void __set_MSPLIM(uint32_t value) + { + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)value; + #else + __asm volatile("MSR MSPLIM,%0" :: "r" (value)); + #endif + } + + __IAR_FT uint32_t __get_PSPLIM(void) + { + uint32_t res; + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + res = 0U; + #else + __asm volatile("MRS %0,PSPLIM" : "=r" (res)); + #endif + return res; + } + + __IAR_FT void __set_PSPLIM(uint32_t value) + { + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)value; + #else + __asm volatile("MSR PSPLIM,%0" :: "r" (value)); + #endif + } + + __IAR_FT uint32_t __TZ_get_CONTROL_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,CONTROL_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_CONTROL_NS(uint32_t value) + { + __asm volatile("MSR CONTROL_NS,%0" :: "r" (value)); + __iar_builtin_ISB(); + } + + __IAR_FT uint32_t __TZ_get_PSP_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,PSP_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_PSP_NS(uint32_t value) + { + __asm volatile("MSR PSP_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_MSP_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,MSP_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_MSP_NS(uint32_t value) + { + __asm volatile("MSR MSP_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_SP_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,SP_NS" : "=r" (res)); + return res; + } + __IAR_FT void __TZ_set_SP_NS(uint32_t value) + { + __asm volatile("MSR SP_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_PRIMASK_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,PRIMASK_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_PRIMASK_NS(uint32_t value) + { + __asm volatile("MSR PRIMASK_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_BASEPRI_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,BASEPRI_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_BASEPRI_NS(uint32_t value) + { + __asm volatile("MSR BASEPRI_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_FAULTMASK_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,FAULTMASK_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_FAULTMASK_NS(uint32_t value) + { + __asm volatile("MSR FAULTMASK_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_PSPLIM_NS(void) + { + uint32_t res; + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + res = 0U; + #else + __asm volatile("MRS %0,PSPLIM_NS" : "=r" (res)); + #endif + return res; + } + + __IAR_FT void __TZ_set_PSPLIM_NS(uint32_t value) + { + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)value; + #else + __asm volatile("MSR PSPLIM_NS,%0" :: "r" (value)); + #endif + } + + __IAR_FT uint32_t __TZ_get_MSPLIM_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,MSPLIM_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_MSPLIM_NS(uint32_t value) + { + __asm volatile("MSR MSPLIM_NS,%0" :: "r" (value)); + } + + #endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */ + +#endif /* __ICCARM_INTRINSICS_VERSION__ == 2 */ + +#define __BKPT(value) __asm volatile ("BKPT %0" : : "i"(value)) + +#if __IAR_M0_FAMILY + __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat) + { + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; + } + + __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat) + { + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; + } +#endif + +#if (__CORTEX_M >= 0x03) /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */ + + __IAR_FT uint8_t __LDRBT(volatile uint8_t *addr) + { + uint32_t res; + __ASM volatile ("LDRBT %0, [%1]" : "=r" (res) : "r" (addr) : "memory"); + return ((uint8_t)res); + } + + __IAR_FT uint16_t __LDRHT(volatile uint16_t *addr) + { + uint32_t res; + __ASM volatile ("LDRHT %0, [%1]" : "=r" (res) : "r" (addr) : "memory"); + return ((uint16_t)res); + } + + __IAR_FT uint32_t __LDRT(volatile uint32_t *addr) + { + uint32_t res; + __ASM volatile ("LDRT %0, [%1]" : "=r" (res) : "r" (addr) : "memory"); + return res; + } + + __IAR_FT void __STRBT(uint8_t value, volatile uint8_t *addr) + { + __ASM volatile ("STRBT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory"); + } + + __IAR_FT void __STRHT(uint16_t value, volatile uint16_t *addr) + { + __ASM volatile ("STRHT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory"); + } + + __IAR_FT void __STRT(uint32_t value, volatile uint32_t *addr) + { + __ASM volatile ("STRT %1, [%0]" : : "r" (addr), "r" (value) : "memory"); + } + +#endif /* (__CORTEX_M >= 0x03) */ + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + + + __IAR_FT uint8_t __LDAB(volatile uint8_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return ((uint8_t)res); + } + + __IAR_FT uint16_t __LDAH(volatile uint16_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return ((uint16_t)res); + } + + __IAR_FT uint32_t __LDA(volatile uint32_t *ptr) + { + uint32_t res; + __ASM volatile ("LDA %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return res; + } + + __IAR_FT void __STLB(uint8_t value, volatile uint8_t *ptr) + { + __ASM volatile ("STLB %1, [%0]" :: "r" (ptr), "r" (value) : "memory"); + } + + __IAR_FT void __STLH(uint16_t value, volatile uint16_t *ptr) + { + __ASM volatile ("STLH %1, [%0]" :: "r" (ptr), "r" (value) : "memory"); + } + + __IAR_FT void __STL(uint32_t value, volatile uint32_t *ptr) + { + __ASM volatile ("STL %1, [%0]" :: "r" (ptr), "r" (value) : "memory"); + } + + __IAR_FT uint8_t __LDAEXB(volatile uint8_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAEXB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return ((uint8_t)res); + } + + __IAR_FT uint16_t __LDAEXH(volatile uint16_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAEXH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return ((uint16_t)res); + } + + __IAR_FT uint32_t __LDAEX(volatile uint32_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAEX %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return res; + } + + __IAR_FT uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr) + { + uint32_t res; + __ASM volatile ("STLEXB %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory"); + return res; + } + + __IAR_FT uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr) + { + uint32_t res; + __ASM volatile ("STLEXH %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory"); + return res; + } + + __IAR_FT uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr) + { + uint32_t res; + __ASM volatile ("STLEX %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory"); + return res; + } + +#endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */ + +#undef __IAR_FT +#undef __IAR_M0_FAMILY +#undef __ICCARM_V8 + +#pragma diag_default=Pe940 +#pragma diag_default=Pe177 + +#define __SXTB16_RORn(ARG1, ARG2) __SXTB16(__ROR(ARG1, ARG2)) + +#define __SXTAB16_RORn(ARG1, ARG2, ARG3) __SXTAB16(ARG1, __ROR(ARG2, ARG3)) + +#endif /* __CMSIS_ICCARM_H__ */ diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/CMSIS/Include/cmsis_version.h b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/CMSIS/Include/cmsis_version.h new file mode 100644 index 0000000000..8b4765f186 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/CMSIS/Include/cmsis_version.h @@ -0,0 +1,39 @@ +/**************************************************************************//** + * @file cmsis_version.h + * @brief CMSIS Core(M) Version definitions + * @version V5.0.5 + * @date 02. February 2022 + ******************************************************************************/ +/* + * Copyright (c) 2009-2022 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CMSIS_VERSION_H +#define __CMSIS_VERSION_H + +/* CMSIS Version definitions */ +#define __CM_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS Core(M) main version */ +#define __CM_CMSIS_VERSION_SUB ( 6U) /*!< [15:0] CMSIS Core(M) sub version */ +#define __CM_CMSIS_VERSION ((__CM_CMSIS_VERSION_MAIN << 16U) | \ + __CM_CMSIS_VERSION_SUB ) /*!< CMSIS Core(M) version number */ +#endif diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/CMSIS/Include/core_cm0plus.h b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/CMSIS/Include/core_cm0plus.h new file mode 100644 index 0000000000..879a384124 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/CMSIS/Include/core_cm0plus.h @@ -0,0 +1,1087 @@ +/**************************************************************************//** + * @file core_cm0plus.h + * @brief CMSIS Cortex-M0+ Core Peripheral Access Layer Header File + * @version V5.0.9 + * @date 21. August 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM0PLUS_H_GENERIC +#define __CORE_CM0PLUS_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex-M0+ + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM0+ definitions */ +#define __CM0PLUS_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM0PLUS_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM0PLUS_CMSIS_VERSION ((__CM0PLUS_CMSIS_VERSION_MAIN << 16U) | \ + __CM0PLUS_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (0U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM0PLUS_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM0PLUS_H_DEPENDANT +#define __CORE_CM0PLUS_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM0PLUS_REV + #define __CM0PLUS_REV 0x0000U + #warning "__CM0PLUS_REV not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 0U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex-M0+ */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core MPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[31U]; + __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RESERVED1[31U]; + __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[31U]; + __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[31U]; + uint32_t RESERVED4[64U]; + __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ +#else + uint32_t RESERVED0; +#endif + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) +/* SCB Interrupt Control State Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 8U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#endif + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ +} MPU_Type; + +#define MPU_TYPE_RALIASES 1U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 8U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. + Therefore they are not covered by the Cortex-M0+ header file. + @{ + */ +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ +/*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M0+ */ + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ + + +/* Interrupt Priorities are WORD accessible only under Armv6-M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + +#define __NVIC_SetPriorityGrouping(X) (void)(X) +#define __NVIC_GetPriorityGrouping() (0U) + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + If VTOR is not present address 0 must be mapped to SRAM. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; +#else + uint32_t *vectors = (uint32_t *)(NVIC_USER_IRQ_OFFSET << 2); /* point to 1st user interrupt */ + *(vectors + (int32_t)IRQn) = vector; /* use pointer arithmetic to access vector */ +#endif + /* ARM Application Note 321 states that the M0+ does not require the architectural barrier */ +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +#else + uint32_t *vectors = (uint32_t *)(NVIC_USER_IRQ_OFFSET << 2); /* point to 1st user interrupt */ + return *(vectors + (int32_t)IRQn); /* use pointer arithmetic to access vector */ +#endif +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv7.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM0PLUS_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/CMSIS/Include/core_cm3.h b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/CMSIS/Include/core_cm3.h new file mode 100644 index 0000000000..74fb87e5c5 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/CMSIS/Include/core_cm3.h @@ -0,0 +1,1943 @@ +/**************************************************************************//** + * @file core_cm3.h + * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File + * @version V5.1.2 + * @date 04. June 2021 + ******************************************************************************/ +/* + * Copyright (c) 2009-2021 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM3_H_GENERIC +#define __CORE_CM3_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M3 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM3 definitions */ +#define __CM3_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM3_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16U) | \ + __CM3_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (3U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM3_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM3_H_DEPENDANT +#define __CORE_CM3_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM3_REV + #define __CM3_REV 0x0200U + #warning "__CM3_REV not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 1U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M3 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:1; /*!< bit: 9 Reserved */ + uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */ + uint32_t _reserved1:8; /*!< bit: 16..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit */ + uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */ +#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */ +#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24U]; + __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RESERVED1[24U]; + __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24U]; + __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24U]; + __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56U]; + __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[5U]; + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#if defined (__CM3_REV) && (__CM3_REV < 0x0201U) /* core r2p1 */ +#define SCB_VTOR_TBLBASE_Pos 29U /*!< SCB VTOR: TBLBASE Position */ +#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */ + +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#else +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#endif + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_CFSR_MEMFAULTSR_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ +#if defined (__CM3_REV) && (__CM3_REV >= 0x200U) + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +#else + uint32_t RESERVED1[1U]; +#endif +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/* Auxiliary Control Register Definitions */ +#if defined (__CM3_REV) && (__CM3_REV >= 0x200U) +#define SCnSCB_ACTLR_DISOOFP_Pos 9U /*!< ACTLR: DISOOFP Position */ +#define SCnSCB_ACTLR_DISOOFP_Msk (1UL << SCnSCB_ACTLR_DISOOFP_Pos) /*!< ACTLR: DISOOFP Mask */ + +#define SCnSCB_ACTLR_DISFPCA_Pos 8U /*!< ACTLR: DISFPCA Position */ +#define SCnSCB_ACTLR_DISFPCA_Msk (1UL << SCnSCB_ACTLR_DISFPCA_Pos) /*!< ACTLR: DISFPCA Mask */ + +#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ +#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR: DISDEFWBUF Position */ +#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ + +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ +#endif + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x1UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x1UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY2_Pos 0U /*!< TPI ITATBCTR2: ATREADY2 Position */ +#define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/) /*!< TPI ITATBCTR2: ATREADY2 Mask */ + +#define TPI_ITATBCTR2_ATREADY1_Pos 0U /*!< TPI ITATBCTR2: ATREADY1 Position */ +#define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/) /*!< TPI ITATBCTR2: ATREADY1 Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x1UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x1UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY2_Pos 0U /*!< TPI ITATBCTR0: ATREADY2 Position */ +#define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/) /*!< TPI ITATBCTR0: ATREADY2 Mask */ + +#define TPI_ITATBCTR0_ATREADY1_Pos 0U /*!< TPI ITATBCTR0: ATREADY1 Position */ +#define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/) /*!< TPI ITATBCTR0: ATREADY1 Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + /* ARM Application Note 321 states that the M3 does not require the architectural barrier */ +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv7.h" + +#endif + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM3_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/CMSIS/Include/mpu_armv7.h b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/CMSIS/Include/mpu_armv7.h new file mode 100644 index 0000000000..9909f83990 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/CMSIS/Include/mpu_armv7.h @@ -0,0 +1,275 @@ +/****************************************************************************** + * @file mpu_armv7.h + * @brief CMSIS MPU API for Armv7-M MPU + * @version V5.1.2 + * @date 25. May 2020 + ******************************************************************************/ +/* + * Copyright (c) 2017-2020 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef ARM_MPU_ARMV7_H +#define ARM_MPU_ARMV7_H + +#define ARM_MPU_REGION_SIZE_32B ((uint8_t)0x04U) ///!< MPU Region Size 32 Bytes +#define ARM_MPU_REGION_SIZE_64B ((uint8_t)0x05U) ///!< MPU Region Size 64 Bytes +#define ARM_MPU_REGION_SIZE_128B ((uint8_t)0x06U) ///!< MPU Region Size 128 Bytes +#define ARM_MPU_REGION_SIZE_256B ((uint8_t)0x07U) ///!< MPU Region Size 256 Bytes +#define ARM_MPU_REGION_SIZE_512B ((uint8_t)0x08U) ///!< MPU Region Size 512 Bytes +#define ARM_MPU_REGION_SIZE_1KB ((uint8_t)0x09U) ///!< MPU Region Size 1 KByte +#define ARM_MPU_REGION_SIZE_2KB ((uint8_t)0x0AU) ///!< MPU Region Size 2 KBytes +#define ARM_MPU_REGION_SIZE_4KB ((uint8_t)0x0BU) ///!< MPU Region Size 4 KBytes +#define ARM_MPU_REGION_SIZE_8KB ((uint8_t)0x0CU) ///!< MPU Region Size 8 KBytes +#define ARM_MPU_REGION_SIZE_16KB ((uint8_t)0x0DU) ///!< MPU Region Size 16 KBytes +#define ARM_MPU_REGION_SIZE_32KB ((uint8_t)0x0EU) ///!< MPU Region Size 32 KBytes +#define ARM_MPU_REGION_SIZE_64KB ((uint8_t)0x0FU) ///!< MPU Region Size 64 KBytes +#define ARM_MPU_REGION_SIZE_128KB ((uint8_t)0x10U) ///!< MPU Region Size 128 KBytes +#define ARM_MPU_REGION_SIZE_256KB ((uint8_t)0x11U) ///!< MPU Region Size 256 KBytes +#define ARM_MPU_REGION_SIZE_512KB ((uint8_t)0x12U) ///!< MPU Region Size 512 KBytes +#define ARM_MPU_REGION_SIZE_1MB ((uint8_t)0x13U) ///!< MPU Region Size 1 MByte +#define ARM_MPU_REGION_SIZE_2MB ((uint8_t)0x14U) ///!< MPU Region Size 2 MBytes +#define ARM_MPU_REGION_SIZE_4MB ((uint8_t)0x15U) ///!< MPU Region Size 4 MBytes +#define ARM_MPU_REGION_SIZE_8MB ((uint8_t)0x16U) ///!< MPU Region Size 8 MBytes +#define ARM_MPU_REGION_SIZE_16MB ((uint8_t)0x17U) ///!< MPU Region Size 16 MBytes +#define ARM_MPU_REGION_SIZE_32MB ((uint8_t)0x18U) ///!< MPU Region Size 32 MBytes +#define ARM_MPU_REGION_SIZE_64MB ((uint8_t)0x19U) ///!< MPU Region Size 64 MBytes +#define ARM_MPU_REGION_SIZE_128MB ((uint8_t)0x1AU) ///!< MPU Region Size 128 MBytes +#define ARM_MPU_REGION_SIZE_256MB ((uint8_t)0x1BU) ///!< MPU Region Size 256 MBytes +#define ARM_MPU_REGION_SIZE_512MB ((uint8_t)0x1CU) ///!< MPU Region Size 512 MBytes +#define ARM_MPU_REGION_SIZE_1GB ((uint8_t)0x1DU) ///!< MPU Region Size 1 GByte +#define ARM_MPU_REGION_SIZE_2GB ((uint8_t)0x1EU) ///!< MPU Region Size 2 GBytes +#define ARM_MPU_REGION_SIZE_4GB ((uint8_t)0x1FU) ///!< MPU Region Size 4 GBytes + +#define ARM_MPU_AP_NONE 0U ///!< MPU Access Permission no access +#define ARM_MPU_AP_PRIV 1U ///!< MPU Access Permission privileged access only +#define ARM_MPU_AP_URO 2U ///!< MPU Access Permission unprivileged access read-only +#define ARM_MPU_AP_FULL 3U ///!< MPU Access Permission full access +#define ARM_MPU_AP_PRO 5U ///!< MPU Access Permission privileged access read-only +#define ARM_MPU_AP_RO 6U ///!< MPU Access Permission read-only access + +/** MPU Region Base Address Register Value +* +* \param Region The region to be configured, number 0 to 15. +* \param BaseAddress The base address for the region. +*/ +#define ARM_MPU_RBAR(Region, BaseAddress) \ + (((BaseAddress) & MPU_RBAR_ADDR_Msk) | \ + ((Region) & MPU_RBAR_REGION_Msk) | \ + (MPU_RBAR_VALID_Msk)) + +/** +* MPU Memory Access Attributes +* +* \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral. +* \param IsShareable Region is shareable between multiple bus masters. +* \param IsCacheable Region is cacheable, i.e. its value may be kept in cache. +* \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy. +*/ +#define ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable) \ + ((((TypeExtField) << MPU_RASR_TEX_Pos) & MPU_RASR_TEX_Msk) | \ + (((IsShareable) << MPU_RASR_S_Pos) & MPU_RASR_S_Msk) | \ + (((IsCacheable) << MPU_RASR_C_Pos) & MPU_RASR_C_Msk) | \ + (((IsBufferable) << MPU_RASR_B_Pos) & MPU_RASR_B_Msk)) + +/** +* MPU Region Attribute and Size Register Value +* +* \param DisableExec Instruction access disable bit, 1= disable instruction fetches. +* \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode. +* \param AccessAttributes Memory access attribution, see \ref ARM_MPU_ACCESS_. +* \param SubRegionDisable Sub-region disable field. +* \param Size Region size of the region to be configured, for example 4K, 8K. +*/ +#define ARM_MPU_RASR_EX(DisableExec, AccessPermission, AccessAttributes, SubRegionDisable, Size) \ + ((((DisableExec) << MPU_RASR_XN_Pos) & MPU_RASR_XN_Msk) | \ + (((AccessPermission) << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk) | \ + (((AccessAttributes) & (MPU_RASR_TEX_Msk | MPU_RASR_S_Msk | MPU_RASR_C_Msk | MPU_RASR_B_Msk))) | \ + (((SubRegionDisable) << MPU_RASR_SRD_Pos) & MPU_RASR_SRD_Msk) | \ + (((Size) << MPU_RASR_SIZE_Pos) & MPU_RASR_SIZE_Msk) | \ + (((MPU_RASR_ENABLE_Msk)))) + +/** +* MPU Region Attribute and Size Register Value +* +* \param DisableExec Instruction access disable bit, 1= disable instruction fetches. +* \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode. +* \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral. +* \param IsShareable Region is shareable between multiple bus masters. +* \param IsCacheable Region is cacheable, i.e. its value may be kept in cache. +* \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy. +* \param SubRegionDisable Sub-region disable field. +* \param Size Region size of the region to be configured, for example 4K, 8K. +*/ +#define ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable, SubRegionDisable, Size) \ + ARM_MPU_RASR_EX(DisableExec, AccessPermission, ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable), SubRegionDisable, Size) + +/** +* MPU Memory Access Attribute for strongly ordered memory. +* - TEX: 000b +* - Shareable +* - Non-cacheable +* - Non-bufferable +*/ +#define ARM_MPU_ACCESS_ORDERED ARM_MPU_ACCESS_(0U, 1U, 0U, 0U) + +/** +* MPU Memory Access Attribute for device memory. +* - TEX: 000b (if shareable) or 010b (if non-shareable) +* - Shareable or non-shareable +* - Non-cacheable +* - Bufferable (if shareable) or non-bufferable (if non-shareable) +* +* \param IsShareable Configures the device memory as shareable or non-shareable. +*/ +#define ARM_MPU_ACCESS_DEVICE(IsShareable) ((IsShareable) ? ARM_MPU_ACCESS_(0U, 1U, 0U, 1U) : ARM_MPU_ACCESS_(2U, 0U, 0U, 0U)) + +/** +* MPU Memory Access Attribute for normal memory. +* - TEX: 1BBb (reflecting outer cacheability rules) +* - Shareable or non-shareable +* - Cacheable or non-cacheable (reflecting inner cacheability rules) +* - Bufferable or non-bufferable (reflecting inner cacheability rules) +* +* \param OuterCp Configures the outer cache policy. +* \param InnerCp Configures the inner cache policy. +* \param IsShareable Configures the memory as shareable or non-shareable. +*/ +#define ARM_MPU_ACCESS_NORMAL(OuterCp, InnerCp, IsShareable) ARM_MPU_ACCESS_((4U | (OuterCp)), IsShareable, ((InnerCp) >> 1U), ((InnerCp) & 1U)) + +/** +* MPU Memory Access Attribute non-cacheable policy. +*/ +#define ARM_MPU_CACHEP_NOCACHE 0U + +/** +* MPU Memory Access Attribute write-back, write and read allocate policy. +*/ +#define ARM_MPU_CACHEP_WB_WRA 1U + +/** +* MPU Memory Access Attribute write-through, no write allocate policy. +*/ +#define ARM_MPU_CACHEP_WT_NWA 2U + +/** +* MPU Memory Access Attribute write-back, no write allocate policy. +*/ +#define ARM_MPU_CACHEP_WB_NWA 3U + + +/** +* Struct for a single MPU Region +*/ +typedef struct { + uint32_t RBAR; //!< The region base address register value (RBAR) + uint32_t RASR; //!< The region attribute and size register value (RASR) \ref MPU_RASR +} ARM_MPU_Region_t; + +/** Enable the MPU. +* \param MPU_Control Default access permissions for unconfigured regions. +*/ +__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control) +{ + __DMB(); + MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; +#endif + __DSB(); + __ISB(); +} + +/** Disable the MPU. +*/ +__STATIC_INLINE void ARM_MPU_Disable(void) +{ + __DMB(); +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; +#endif + MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk; + __DSB(); + __ISB(); +} + +/** Clear and disable the given MPU region. +* \param rnr Region number to be cleared. +*/ +__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr) +{ + MPU->RNR = rnr; + MPU->RASR = 0U; +} + +/** Configure an MPU region. +* \param rbar Value for RBAR register. +* \param rasr Value for RASR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rbar, uint32_t rasr) +{ + MPU->RBAR = rbar; + MPU->RASR = rasr; +} + +/** Configure the given MPU region. +* \param rnr Region number to be configured. +* \param rbar Value for RBAR register. +* \param rasr Value for RASR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegionEx(uint32_t rnr, uint32_t rbar, uint32_t rasr) +{ + MPU->RNR = rnr; + MPU->RBAR = rbar; + MPU->RASR = rasr; +} + +/** Memcpy with strictly ordered memory access, e.g. used by code in ARM_MPU_Load(). +* \param dst Destination data is copied to. +* \param src Source data is copied from. +* \param len Amount of data words to be copied. +*/ +__STATIC_INLINE void ARM_MPU_OrderedMemcpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len) +{ + uint32_t i; + for (i = 0U; i < len; ++i) + { + dst[i] = src[i]; + } +} + +/** Load the given number of MPU regions from a table. +* \param table Pointer to the MPU configuration table. +* \param cnt Amount of regions to be configured. +*/ +__STATIC_INLINE void ARM_MPU_Load(ARM_MPU_Region_t const* table, uint32_t cnt) +{ + const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U; + while (cnt > MPU_TYPE_RALIASES) { + ARM_MPU_OrderedMemcpy(&(MPU->RBAR), &(table->RBAR), MPU_TYPE_RALIASES*rowWordSize); + table += MPU_TYPE_RALIASES; + cnt -= MPU_TYPE_RALIASES; + } + ARM_MPU_OrderedMemcpy(&(MPU->RBAR), &(table->RBAR), cnt*rowWordSize); +} + +#endif diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/CMSIS/LICENSE.txt b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/CMSIS/LICENSE.txt new file mode 100644 index 0000000000..8dada3edaf --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/CMSIS/LICENSE.txt @@ -0,0 +1,201 @@ + Apache License + Version 2.0, January 2004 + http://www.apache.org/licenses/ + + TERMS AND CONDITIONS FOR USE, REPRODUCTION, AND DISTRIBUTION + + 1. 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We also recommend that a + file or class name and description of purpose be included on the + same "printed page" as the copyright notice for easier + identification within third-party archives. + + Copyright {yyyy} {name of copyright owner} + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/CMSIS/README.md b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/CMSIS/README.md new file mode 100644 index 0000000000..0630bf8cd4 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/CMSIS/README.md @@ -0,0 +1,141 @@ +# CMSIS Version 5 + +[![Version](https://img.shields.io/github/v/release/arm-software/CMSIS_5)](https://github.com/ARM-software/CMSIS_5/releases/latest) [![License](https://img.shields.io/github/license/arm-software/CMSIS_5)](https://arm-software.github.io/CMSIS_5/General/html/LICENSE.txt) + +The branch *master* of this GitHub repository contains ![Version](https://img.shields.io/github/v/release/arm-software/CMSIS_5?display_name=release&label=%20&sort=semver). +The [documentation](http://arm-software.github.io/CMSIS_5/General/html/index.html) is available under http://arm-software.github.io/CMSIS_5/General/html/index.html + +Use [Issues](https://github.com/ARM-software/CMSIS_5#issues-and-labels) to provide feedback and report problems for CMSIS Version 5. + +**Note:** The branch *develop* of this GitHub repository reflects our current state of development and is constantly updated. It gives our users and partners contiguous access to the CMSIS development. It allows you to review the work and provide feedback or create pull requests for contributions. + +A [pre-built documentation](https://arm-software.github.io/CMSIS_5/develop/General/html/index.html) is updated from time to time, but may be also generated using the instructions under [Generate CMSIS Pack for Release](https://github.com/ARM-software/CMSIS_5#generate-cmsis-pack-for-release). + +## Overview of CMSIS Components + +The following is an list of all CMSIS components that are available. + +| CMSIS-... | Target Processors | Description | +|:----------|:--------------------|:-------------| +|[Core(M)](http://arm-software.github.io/CMSIS_5/Core/html/index.html) | All Cortex-M, SecurCore | Standardized API for the Cortex-M processor core and peripherals. Includes intrinsic functions for Cortex-M4/M7/M33/M35P SIMD instructions.| +|[Core(A)](http://arm-software.github.io/CMSIS_5/Core_A/html/index.html)| Cortex-A5/A7/A9 | API and basic run-time system for the Cortex-A5/A7/A9 processor core and peripherals.| +|[Driver](http://arm-software.github.io/CMSIS_5/Driver/html/index.html) | All Cortex-M, SecurCore | Generic peripheral driver interfaces for middleware. Connects microcontroller peripherals with middleware that implements for example communication stacks, file systems, or graphic user interfaces.| +|[DSP](http://arm-software.github.io/CMSIS_5/DSP/html/index.html) | All Cortex-M | DSP library collection with over 60 Functions for various data types: fixed-point (fractional q7, q15, q31) and single precision floating-point (32-bit). Implementations optimized for the SIMD instruction set are available for Cortex-M4/M7/M33/M35P.| +|[NN](http://arm-software.github.io/CMSIS_5/NN/html/index.html) | All Cortex-M | Collection of efficient neural network kernels developed to maximize the performance and minimize the memory footprint on Cortex-M processor cores.| +|[RTOS v1](http://arm-software.github.io/CMSIS_5/RTOS/html/index.html) | Cortex-M0/M0+/M3/M4/M7 | Common API for real-time operating systems along with a reference implementation based on RTX. It enables software components that can work across multiple RTOS systems.| +|[RTOS v2](http://arm-software.github.io/CMSIS_5/RTOS2/html/index.html)| All Cortex-M, Cortex-A5/A7/A9 | Extends CMSIS-RTOS v1 with Armv8-M support, dynamic object creation, provisions for multi-core systems, binary compatible interface. | +|[Pack](http://arm-software.github.io/CMSIS_5/Pack/html/index.html) | All Cortex-M, SecurCore, Cortex-A5/A7/A9 | Describes a delivery mechanism for software components, device parameters, and evaluation board support. It simplifies software re-use and product life-cycle management (PLM).
Is part of the [Open CMSIS Pack project](https://www.open-cmsis-pack.org). | +|[Build](http://arm-software.github.io/CMSIS_5/Build/html/index.html) | All Cortex-M, SecurCore, Cortex-A5/A7/A9 | A set of tools, software frameworks, and work flows that improve productivity, for example with Continuous Integration (CI) support.
Is replaced with the [CMSIS-Toolbox](https://github.com/Open-CMSIS-Pack/devtools/tree/main/tools). | +|[SVD](http://arm-software.github.io/CMSIS_5/SVD/html/index.html) | All Cortex-M, SecurCore | Peripheral description of a device that can be used to create peripheral awareness in debuggers or CMSIS-Core header files.| +|[DAP](http://arm-software.github.io/CMSIS_5/DAP/html/index.html) | All Cortex | Firmware for a debug unit that interfaces to the CoreSight Debug Access Port. | +|[Zone](http://arm-software.github.io/CMSIS_5/Zone/html/index.html) | All Cortex-M | Defines methods to describe system resources and to partition these resources into multiple projects and execution areas. | + +## Implemented Enhancements + - CMSIS-Pack generation with [shell script template](https://arm-software.github.io/CMSIS_5/Pack/html/bash_script.html) for Windows and Linux + - CMSIS-Pack: [Git workflow](https://arm-software.github.io/CMSIS_5/Pack/html/element_repository.html) via Eclipse menu *Window - Preferences - CMSIS Packs - Manage Local Repositories* and [MDK](http://www.keil.com/support/man/docs/uv4/uv4_ca_packinst_repo.htm) + - [CMSIS-Zone release 1.0](https://arm-software.github.io/CMSIS_5/Zone/html/index.html) with support for multi-processor, TrustZone, and MPU configuration + - Support for Armv8.1M Architecture and Cortex-M55 (release in March 2020) + - CMSIS-DSP is fully ported to SIMD for Cortex-M family (Armv8.1-M) and Cortex-A & Cortex-R with NEON, using the same APIs. + +## Further Planned Enhancements + - CMSIS-Pack: + - System Description SDF Format: describe more complex debug topologies than with a Debug Description in a tool agnostic way + - CPDSC project file format: allows project templates that are agnostic of an IDE + - Minimize need for IDE specific settings: CMSIS-Pack supports IDE specific parameters. Analyze and minimize + - CMSIS-Build: command-line driven make system for CMSIS-Pack based projects (to support CI tests) + +For further details see also the [Slides of the Embedded World CMSIS Partner Meeting](https://github.com/ARM-software/CMSIS_5/blob/develop/CMSIS_Review_Meeting_2020.pdf). + +## Other related GitHub repositories + +| Repository | Description | +|:--------------------------- |:--------------------------------------------------------- | +| [cmsis-pack-eclipse](https://github.com/ARM-software/cmsis-pack-eclipse) | CMSIS-Pack Management for Eclipse reference implementation Pack support | +| [CMSIS-FreeRTOS](https://github.com/arm-software/CMSIS-FreeRTOS) | CMSIS-RTOS adoption of FreeRTOS | +| [CMSIS-Driver](https://github.com/arm-software/CMSIS-Driver) | Generic MCU driver implementations and templates for Ethernet MAC/PHY and Flash. | +| [CMSIS-Driver_Validation](https://github.com/ARM-software/CMSIS-Driver_Validation) | CMSIS-Driver Validation can be used to verify CMSIS-Driver in a user system | +| [CMSIS-Zone](https://github.com/ARM-software/CMSIS-Zone) | CMSIS-Zone Utility along with example projects and FreeMarker templates | +| [NXP_LPC](https://github.com/ARM-software/NXP_LPC) | CMSIS Driver Implementations for the NXP LPC Microcontroller Series | +| [mdk-packs](https://github.com/mdk-packs) | IoT cloud connectors as trail implementations for MDK (help us to make it generic)| +| [trustedfirmware.org](https://www.trustedfirmware.org/) | Arm Trusted Firmware provides a reference implementation of secure world software for Armv8-A and Armv8-M.| + + +## Directory Structure + +| Directory | Content | +|:-------------------- |:--------------------------------------------------------- | +| CMSIS/Core | CMSIS-Core(M) related files (for release) | +| CMSIS/Core_A | CMSIS-Core(A) related files (for release) | +| CMSIS/CoreValidation | Validation for Core(M) and Core(A) (NOT part of release) | +| CMSIS/DAP | CMSIS-DAP related files and examples | +| CMSIS/Driver | CMSIS-Driver API headers and template files | +| CMSIS/DSP | CMSIS-DSP related files | +| CMSIS/NN | CMSIS-NN related files | +| CMSIS/RTOS | RTOS v1 related files (for Cortex-M) | +| CMSIS/RTOS2 | RTOS v2 related files (for Cortex-M & Armv8-M) | +| CMSIS/Pack | CMSIS-Pack examples and tutorials | +| CMSIS/DoxyGen | Source of the documentation | +| CMSIS/Utilities | Utility programs | + +## Generate CMSIS Pack for Release + +This GitHub development repository lacks pre-built libraries of various software components (RTOS, RTOS2). +In order to generate a full pack one needs to have the build environment available to build these libraries. +This causes some sort of inconvenience. Hence the pre-built libraries may be moved out into separate pack(s) +in the future. + +To build a complete CMSIS pack for installation the following additional tools are required: + - **doxygen.exe** Version: 1.8.6 (Documentation Generator) + - **mscgen.exe** Version: 0.20 (Message Sequence Chart Converter) + - **7z.exe (7-Zip)** Version: 16.02 (File Archiver) + +Using these tools, you can generate on a Windows PC: + - **CMSIS Documentation** using the batch file **gen_doc.sh** (located in ./CMSIS/Doxygen). + - **CMSIS Software Pack** using the batch file **gen_pack.sh** (located in ./CMSIS/Utilities). + The bash script does not generate the documentation. The pre-built libraries for RTX4 and RTX5 + are not included within this repository. + +The file ./CMSIS/DoxyGen/How2Doc.txt describes the rules for creating API documentation. + +## License + +Arm CMSIS is licensed under Apache 2.0. + +## Contributions and Pull Requests + +Contributions are accepted under Apache 2.0. Only submit contributions where you have authored all of the code. + +### Issues and Labels + +Please feel free to raise an [issue on GitHub](https://github.com/ARM-software/CMSIS_5/issues) +to report misbehavior (i.e. bugs) or start discussions about enhancements. This +is your best way to interact directly with the maintenance team and the community. +We encourage you to append implementation suggestions as this helps to decrease the +workload of the very limited maintenance team. + +We will be monitoring and responding to issues as best we can. +Please attempt to avoid filing duplicates of open or closed items when possible. +In the spirit of openness we will be tagging issues with the following: + +- **bug** – We consider this issue to be a bug that will be investigated. + +- **wontfix** - We appreciate this issue but decided not to change the current behavior. + +- **enhancement** – Denotes something that will be implemented soon. + +- **future** - Denotes something not yet schedule for implementation. + +- **out-of-scope** - We consider this issue loosely related to CMSIS. It might by implemented outside of CMSIS. Let us know about your work. + +- **question** – We have further questions to this issue. Please review and provide feedback. + +- **documentation** - This issue is a documentation flaw that will be improved in future. + +- **review** - This issue is under review. Please be patient. + +- **DONE** - We consider this issue as resolved - please review and close it. In case of no further activity this issues will be closed after a week. + +- **duplicate** - This issue is already addressed elsewhere, see comment with provided references. + +- **Important Information** - We provide essential information regarding planned or resolved major enhancements. + diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Include/ht32f5xxxx_01.h b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Include/ht32f5xxxx_01.h new file mode 100644 index 0000000000..f72fd72a6f --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Include/ht32f5xxxx_01.h @@ -0,0 +1,2749 @@ +/***************************************************************************//** + * @file ht32f5xxxx_01.h + * @brief CMSIS Cortex-M0+ Device Peripheral Access Layer Header File + * @version $Rev:: 7319 $ + * @date $Date:: 2023-10-28 #$ + * + * @note + * Copyright (C) Holtek Semiconductor Inc. All rights reserved. + * + * @par + * Holtek supplies this software for Cortex-M processor-based + * microcontrollers. This file can be freely distributed within + * development tools that are supporting such ARM-based processors. + * + * @par + * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR + * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + ******************************************************************************/ + +// Supported Device +// ======================================== +// HT32F50020, HT32F50030 +// HT32F50220, HT32F50230 +// HT32F50231, HT32F50241 +// HT32F50343 +// HT32F50431, HT32F50441 +// HT32F50442, HT32F50452 +// HT32F52220, HT32F52230 +// HT32F52231, HT32F52241 +// HT32F52243, HT32F52253 +// HT32F52331, HT32F52341 +// HT32F52342, HT32F52352 +// HT32F52344, HT32F52354 +// HT32F52357, HT32F52367 +// HT32F53231, HT32F53241 +// HT32F53242, HT32F53252 +// HT32F54231, HT32F54241 +// HT32F54243, HT32F54253 +// HT32F57331, HT32F57341 +// HT32F57342, HT32F57352 +// HT32F5826, HT32F5828 +// HT32F0006 +// HT32F0008 +// HT32F61141 +// HT32F61244, HT32F61245 +// HT32F65230, HT32F65240 +// HT32F65232 +// HT32F66242, HT32F66246 +// HT32F67041, HT32F67051 +// HT32F52234, HT32F52244 + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup HT32F5xxxx HT32F5xxxx + * @{ + */ + + +#ifndef __HT32F5XXXX_01_H__ +#define __HT32F5XXXX_01_H__ + +#include "ht32_config.h" + +#ifdef __cplusplus + extern "C" { +#endif + +#if !defined(USE_HT32F52220_30) && \ + !defined(USE_HT32F52231_41) && \ + !defined(USE_HT32F52331_41) && \ + !defined(USE_HT32F52342_52) && \ + !defined(USE_HT32F52243_53) && \ + !defined(USE_HT32F5826) && \ + !defined(USE_HT32F0008) && \ + !defined(USE_HT32F50220_30) && \ + !defined(USE_HT32F50231_41) && \ + !defined(USE_HT32F52344_54) && \ + !defined(USE_HT32F0006) && \ + !defined(USE_HT32F52357_67) && \ + !defined(USE_HT32F65230_40) && \ + !defined(USE_HT32F54231_41) && \ + !defined(USE_HT32F54243_53) && \ + !defined(USE_HT32F57331_41) && \ + !defined(USE_HT32F57342_52) && \ + !defined(USE_HT32F50343) && \ + !defined(USE_HT32F65232) && \ + !defined(USE_HT32F61141) && \ + !defined(USE_HT32F61244_45) && \ + !defined(USE_HT32F50020_30) && \ + !defined(USE_HT32F67041_51) && \ + !defined(USE_HT32F50431_41) && \ + !defined(USE_HT32F50442_52) && \ + !defined(USE_HT32F53231_41) && \ + !defined(USE_HT32F53242_52) && \ + !defined(USE_HT32F66242) && \ + !defined(USE_HT32F66246) && \ + !defined(USE_HT32F52234_44) + + //#define USE_HT32F52220_30 + //#define USE_HT32F52231_41 + //#define USE_HT32F52331_41 + //#define USE_HT32F52342_52 + //#define USE_HT32F52243_53 + //#define USE_HT32F5826 + //#define USE_HT32F0008 + //#define USE_HT32F50220_30 + //#define USE_HT32F50231_41 + //#define USE_HT32F52344_54 + //#define USE_HT32F0006 + //#define USE_HT32F52357_67 + //#define USE_HT32F65230_40 + //#define USE_HT32F54231_41 + //#define USE_HT32F54243_53 + //#define USE_HT32F57331_41 + //#define USE_HT32F57342_52 + //#define USE_HT32F50343 + //#define USE_HT32F65232 + //#define USE_HT32F61141 + //#define USE_HT32F61244_45 + //#define USE_HT32F50020_30 + //#define USE_HT32F67041_51 + //#define USE_HT32F50431_41 + //#define USE_HT32F50442_52 + //#define USE_HT32F53231_41 + //#define USE_HT32F53242_52 + //#define USE_HT32F66242 + //#define USE_HT32F66246 + //#define USE_HT32F52234_44 + +#endif + +#if !defined(USE_NOCHIP) && \ + !defined(USE_HT32F52220_30) && \ + !defined(USE_HT32F52231_41) && \ + !defined(USE_HT32F52331_41) && \ + !defined(USE_HT32F52342_52) && \ + !defined(USE_HT32F52243_53) && \ + !defined(USE_HT32F5826) && \ + !defined(USE_HT32F0008) && \ + !defined(USE_HT32F50220_30) && \ + !defined(USE_HT32F50231_41) && \ + !defined(USE_HT32F52344_54) && \ + !defined(USE_HT32F0006) && \ + !defined(USE_HT32F52357_67) && \ + !defined(USE_HT32F65230_40) && \ + !defined(USE_HT32F54231_41) && \ + !defined(USE_HT32F54243_53) && \ + !defined(USE_HT32F57331_41) && \ + !defined(USE_HT32F57342_52) && \ + !defined(USE_HT32F50343) && \ + !defined(USE_HT32F65232) && \ + !defined(USE_HT32F61141) && \ + !defined(USE_HT32F61244_45) && \ + !defined(USE_HT32F50020_30) && \ + !defined(USE_HT32F67041_51) && \ + !defined(USE_HT32F50431_41) && \ + !defined(USE_HT32F50442_52) && \ + !defined(USE_HT32F53231_41) && \ + !defined(USE_HT32F53242_52) && \ + !defined(USE_HT32F66242) && \ + !defined(USE_HT32F66246) && \ + !defined(USE_HT32F52234_44) + + #error Please add "USE_HT32Fxxxxx_xx" define into C Preprocessor Symbols of the Project configuration. + +#endif + +/** @addtogroup Library_configuration_section + * @{ + */ +/** + * @brief Value of the High Speed Internal oscillator in Hz + */ +#if defined(USE_HT32F50220_30) || defined(USE_HT32F50231_41) + #define HSI_VALUE 20000000UL /*!< Value of the Internal High Speed oscillator in Hz */ +#elif defined(USE_HT32F50020_30) + #define HSI_VALUE 16000000UL /*!< Value of the Internal High Speed oscillator in Hz */ +#else + #define HSI_VALUE 8000000UL /*!< Value of the High Speed Internal oscillator in Hz */ +#endif + +/** + * @brief Value of the Low Speed Internal oscillator in Hz + */ +#define LSI_VALUE 32000UL /*!< Value of the Low Speed Internal oscillator in Hz */ + +#if !defined(USE_HT32F52220_30) && !defined(USE_HT32F66242) && !defined(USE_HT32F66246) +/** + * @brief Value of the Low Speed External oscillator in Hz + */ +#define LSE_VALUE 32768UL /*!< Value of the Low Speed External oscillator in Hz */ +#endif + +/** + * @brief Adjust the High Speed External oscillator (HSE) Startup Timeout value + */ +#define HSE_READY_TIME ((uint16_t)0xFFFF) /*!< Time out for HSE start up */ +/** + * @} + */ + +/** @addtogroup Configuration_section_for_CMSIS + * @{ + */ +#define __MPU_PRESENT 0 /*!< MPU present or not */ +#define __VTOR_PRESENT 1 /*!< VTOR present or not */ +#define __NVIC_PRIO_BITS 2 /*!< Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ + +/** + * @} + */ + + +/** @addtogroup Configuration_for_Interrupt_Number + * @{ + */ +typedef enum IRQn +{ +/****** Cortex-M0+ Processor Exceptions Numbers ******************************** */ + NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13, /*!< 3 Cortex-M0+ Hard Fault Interrupt */ + SVCall_IRQn = -5, /*!< 11 Cortex-M0+ SV Call Interrupt */ + PendSV_IRQn = -2, /*!< 14 Cortex-M0+ Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< 15 Cortex-M0+ System Tick Interrupt */ + +/****** HT32 Specific Interrupt Numbers *************************************** */ + LVD_BOD_IRQn = 0, /*!< Low voltage & Brown-out detection interrupt */ + #if !defined(USE_HT32F52220_30) + RTC_IRQn = 1, /*!< RTC Wake-up Interrupt */ + #endif + FLASH_IRQn = 2, /*!< FLASH global Interrupt */ + EVWUP_IRQn = 3, /*!< EXTI Event Wake-up & WAKEUP pin Interrupt */ + EXTI0_1_IRQn = 4, /*!< EXTI0-1 Line detection Interrupt */ + EXTI2_3_IRQn = 5, /*!< EXTI2-3 Line detection Interrupt */ + #if defined(USE_HT32F65230_40) || defined(USE_HT32F65232) + EXTI4_9_IRQn = 6, /*!< EXTI4-9 Line detection Interrupt */ + #elif defined(USE_HT32F50020_30) + EXTI4_7_IRQn = 6, /*!< EXTI4-7 Line detection Interrupt */ + #else + EXTI4_15_IRQn = 6, /*!< EXTI4-15 Line detection Interrupt */ + #endif + #if defined(USE_HT32F65230_40) || defined(USE_HT32F65232) || defined(USE_HT32F66242) || defined(USE_HT32F66246) + #if defined(USE_HT32F65230_40) || defined(USE_HT32F65232) + EXTI10_15_IRQn = 7, /*!< EXTI10-15 Line detection Interrupt */ + #elif defined(USE_HT32F66246) + CAN0_IRQn = 7, /*!< CAN0 global Interrupt */ + #endif + ADC0_IRQn = 8, /*!< ADC0 Interrupt */ + #if defined(USE_HT32F65230_40) + ADC1_IRQn = 9, /*!< ADC1 Interrupt */ + #elif defined(USE_HT32F66242) + CORDIC_IRQn = 9, /*!< CORDIC global Interrupt */ + #elif defined(USE_HT32F66246) + CORDIC_IRQn = 9, /*!< CORDIC global Interrupt */ + #endif + MCTM0_BRK_IRQn = 10, /*!< MCTM BRK Interrupt */ + MCTM0_UP_IRQn = 11, /*!< MCTM UP Interrupt */ + MCTM0_TR_UP2_IRQn = 12, /*!< MCTM TR & UP2 Interrupt */ + MCTM0_CC_IRQn = 13, /*!< MCTM CC Interrupt */ + GPTM0_G_IRQn = 14, /*!< GPTM G Interrupt */ + GPTM0_VCLK_IRQn = 15, /*!< GPTM VCLK Interrupt */ + BFTM0_IRQn = 16, /*!< Basic Function Timer0 Interrupt */ + BFTM1_IRQn = 17, /*!< Basic Function Timer1 Interrupt */ + CMP0_IRQn = 18, /*!< Comparator0 Interrupt */ + CMP1_IRQn = 19, /*!< Comparator1 Interrupt */ + #if defined(USE_HT32F65230_40) + CMP2_IRQn = 20, /*!< Comparator2 Interrupt */ + #elif defined(USE_HT32F66242) + PID_IRQn = 20, /*!< PID global Interrupt */ + #elif defined(USE_HT32F66246) + PID_IRQn = 20, /*!< PID global Interrupt */ + #endif + I2C0_IRQn = 21, /*!< I2C global Interrupt */ + SPI0_IRQn = 22, /*!< SPI global Interrupt */ + USART0_IRQn = 23, /*!< USART global Interrupt */ + UART0_IRQn = 24, /*!< UART global Interrupt */ + PDMACH0_1_IRQn = 25, /*!< PDMA channel 0-1 Interrupt */ + PDMACH2_3_IRQn = 26, /*!< PDMA channel 2-3 Interrupt */ + PDMACH4_5_IRQn = 27, /*!< PDMA channel 4-5 Interrupt */ + SCTM0_IRQn = 28, /*!< Single Channel Timer0 Interrupt */ + SCTM1_IRQn = 29, /*!< Single Channel Timer1 Interrupt */ + SCTM2_IRQn = 30, /*!< Single Channel Timer2 Interrupt */ + SCTM3_IRQn = 31, /*!< Single Channel Timer3 Interrupt */ + #else + #if defined(USE_HT32F52342_52) || defined(USE_HT32F5826) || defined(USE_HT32F52344_54) || defined(USE_HT32F54243_53) || defined(USE_HT32F53242_52) || defined(USE_HT32F50442_52) + COMP_IRQn = 7, /*!< Comparator global Interrupt */ + #endif + #if defined(USE_HT32F52357_67) || defined(USE_HT32F57342_52) + COMP_DAC_IRQn = 7, /*!< Comparator & DAC global Interrupt */ + #endif + #if defined(USE_HT32F52234_44) + DAC0_1_IRQn = 7, /*!< DAC0 & DAC1 global Interrupt */ + #endif + #if !defined(USE_HT32F0008) + ADC0_IRQn = 8, /*!< ADC Interrupt */ + #endif + #if defined(USE_HT32F52243_53) || defined(USE_HT32F54243_53) || defined(USE_HT32F52234_44) + I2C2_IRQn = 9, /*!< I2C2 global Interrupt */ + #endif + #if defined(USE_HT32F52357_67) || defined(USE_HT32F57342_52) || defined(USE_HT32F67041_51) + AES_IRQn = 9, /*!< AES global Interrupt */ + #endif + #if !defined(USE_HT32F52220_30) && !defined(USE_HT32F0008) && !defined(USE_HT32F50220_30) && !defined(USE_HT32F0006) && !defined(USE_HT32F57342_52) && !defined(USE_HT32F57331_41) && !defined(USE_HT32F50343) && !defined(USE_HT32F61244_45) && !defined(USE_HT32F50020_30) && !defined(USE_HT32F67041_51) && !defined(USE_HT32F52234_44) + MCTM0_IRQn = 10, /*!< Motor Control Timer0 interrupt */ + #endif + #if defined(USE_HT32F50343) + PWM2_IRQn = 10, /*!< PWM Timer2 interrupt */ + #endif + #if defined(USE_HT32F52342_52) || defined(USE_HT32F5826) + GPTM1_IRQn = 11, /*!< General-Purpose Timer1 Interrupt */ + #endif + #if defined(USE_HT32F52357_67) + QSPI_IRQn = 11, /*!< QSPI global Interrupt */ + #endif + #if defined(USE_HT32F57342_52) || defined(USE_HT32F57331_41) + LCD_IRQn = 11, /*!< LCD global Interrupt */ + #endif + #if defined(USE_HT32F54231_41) || defined(USE_HT32F54243_53) + TKEY_IRQn = 11, /*!< Touch-Key global Interrupt */ + #endif + #if defined(USE_HT32F67041_51) + RF_IRQn = 11, /*!< 2.4G RF global Interrupt */ + #endif + #if !defined(USE_HT32F50020_30) && !defined(USE_HT32F52234_44) + GPTM0_IRQn = 12, /*!< General-Purpose Timer0 Interrupt */ + #endif + #if !defined(USE_HT32F0008) && !defined(USE_HT32F50220_30) && !defined(USE_HT32F50231_41) && !defined(USE_HT32F57331_41) && !defined(USE_HT32F53231_41) && !defined(USE_HT32F53242_52) && !defined(USE_HT32F50431_41) && !defined(USE_HT32F50442_52) + SCTM0_IRQn = 13, /*!< Single Channel Timer0 Interrupt */ + SCTM1_IRQn = 14, /*!< Single Channel Timer1 Interrupt */ + #endif + #if defined(USE_HT32F52231_41) || defined(USE_HT32F52331_41) || defined(USE_HT32F52243_53) || defined(USE_HT32F0006) || defined(USE_HT32F54243_53) || defined(USE_HT32F50020_30) || defined(USE_HT32F67041_51) + SCTM2_IRQn = 15, /*!< Single Channel Timer2 Interrupt */ + #endif + #if defined(USE_HT32F52231_41) || defined(USE_HT32F52331_41) || defined(USE_HT32F52243_53) || defined(USE_HT32F0006) || defined(USE_HT32F54243_53) || defined(USE_HT32F67041_51) + SCTM3_IRQn = 16, /*!< Single Channel Timer3 Interrupt */ + #endif + #if defined(USE_HT32F0008) || defined(USE_HT32F50220_30) || defined(USE_HT32F50231_41) || defined(USE_HT32F52357_67) || defined(USE_HT32F57342_52) || defined(USE_HT32F57331_41) || defined(USE_HT32F50343) || defined(USE_HT32F53231_41) || defined(USE_HT32F53242_52) || defined(USE_HT32F50431_41) || defined(USE_HT32F50442_52) || defined(USE_HT32F52234_44) + PWM0_IRQn = 15, /*!< PWM Timer0 Interrupt */ + #endif + #if defined(USE_HT32F0008) || defined(USE_HT32F50220_30) || defined(USE_HT32F50231_41) || defined(USE_HT32F52357_67) || defined(USE_HT32F57342_52) || defined(USE_HT32F57331_41) || defined(USE_HT32F50343) || defined(USE_HT32F53242_52) || defined(USE_HT32F50442_52) + PWM1_IRQn = 16, /*!< PWM Timer1 Interrupt */ + #endif + BFTM0_IRQn = 17, /*!< Basic Function Timer0 Interrupt */ + #if !defined(USE_HT32F52220_30) && !defined(USE_HT32F50220_30) && !defined(USE_HT32F50020_30) + BFTM1_IRQn = 18, /*!< Basic Function Timer1 Interrupt */ + #endif + I2C0_IRQn = 19, /*!< I2C0 global Interrupt */ + #if !defined(USE_HT32F52220_30) && !defined(USE_HT32F0008) && !defined(USE_HT32F50220_30) && !defined(USE_HT32F52344_54) && !defined(USE_HT32F0006) && !defined(USE_HT32F61244_45) && !defined(USE_HT32F50020_30) + I2C1_IRQn = 20, /*!< I2C1 global Interrupt */ + #endif + SPI0_IRQn = 21, /*!< SPI0 global Interrupt */ + #if !defined(USE_HT32F52220_30) && !defined(USE_HT32F0008) && !defined(USE_HT32F0006) && !defined(USE_HT32F50020_30) && !defined(USE_HT32F61244_45) && !defined(USE_HT32F52234_44) + SPI1_IRQn = 22, /*!< SPI1 global Interrupt */ + #endif + #if defined(USE_HT32F0006) || defined(USE_HT32F61244_45) + QSPI_IRQn = 22, /*!< QSPI global Interrupt */ + #endif + #if !defined(USE_HT32F50220_30) && !defined(USE_HT32F52344_54) && !defined(USE_HT32F50343) && !defined(USE_HT32F61244_45) && !defined(USE_HT32F50020_30) && !defined(USE_HT32F67041_51) + USART0_IRQn = 23, /*!< USART0 global Interrupt */ + #endif + #if defined(USE_HT32F52342_52) || defined(USE_HT32F52243_53) || defined(USE_HT32F5826) || defined(USE_HT32F52357_67) || defined(USE_HT32F54243_53) || defined(USE_HT32F53242_52) || defined(USE_HT32F50442_52) + USART1_IRQn = 24, /*!< USART1 global Interrupt */ + #endif + UART0_IRQn = 25, /*!< UART0 global Interrupt */ + #if !defined(USE_HT32F52220_30) && !defined(USE_HT32F0008) && !defined(USE_HT32F0006) && !defined(USE_HT32F61244_45) && !defined(USE_HT32F52234_44) + UART1_IRQn = 26, /*!< UART1 global Interrupt */ + #endif + #if defined(USE_HT32F52357_67) + UART0_UART2_IRQn = 25, /*!< UART0 & UART2 global Interrupt */ + UART1_UART3_IRQn = 26, /*!< UART1 & UART3 global Interrupt */ + #endif + #if defined(USE_HT32F52331_41) || defined(USE_HT32F52342_52) || defined(USE_HT32F5826) || defined(USE_HT32F52357_67) || defined(USE_HT32F57342_52) || defined(USE_HT32F57331_41) || defined(USE_HT32F61141) + SCI_IRQn = 27, /*!< Smart Card Interface Interrupt */ + #endif + #if defined(USE_HT32F53231_41) || defined(USE_HT32F53242_52) + CAN0_IRQn = 27, /*!< CAN0 global Interrupt */ + #endif + #if defined(USE_HT32F0006) || defined(USE_HT32F61244_45) + MIDI_IRQn = 27, /*!< MIDI global Interrupt */ + #endif + #if defined(USE_HT32F52342_52) || defined(USE_HT32F5826) || defined(USE_HT32F0006) || defined(USE_HT32F52357_67) || defined(USE_HT32F57342_52) + I2S_IRQn = 28, /*!< I2S global Interrupt */ + #endif + #if defined(USE_HT32F52243_53) || defined(USE_HT32F54243_53) + UART2_IRQn = 27, /*!< UART2 global Interrupt */ + UART3_IRQn = 28, /*!< UART3 global Interrupt */ + #endif + #if defined(USE_HT32F0008) + AES_IRQn = 28, /*!< AES global Interrupt */ + #endif + #if defined(USE_HT32F50343) + SLED0_IRQn = 27, /*!< SLED0 global Interrupt */ + SLED1_IRQn = 28, /*!< SLED1 global Interrupt */ + #endif + #if defined(USE_HT32F52331_41) || defined(USE_HT32F52342_52) || defined(USE_HT32F5826) || defined(USE_HT32F0008) || defined(USE_HT32F52344_54) || defined(USE_HT32F0006) || defined(USE_HT32F52357_67) || defined(USE_HT32F57342_52) || defined(USE_HT32F57331_41) || defined(USE_HT32F50343) || defined(USE_HT32F61141) + USB_IRQn = 29, /*!< USB interrupt */ + #endif + #if defined(USE_HT32F54231_41) || defined(USE_HT32F54243_53) || defined(USE_HT32F50020_30) || defined(USE_HT32F53231_41) || defined(USE_HT32F53242_52) || defined(USE_HT32F50431_41) || defined(USE_HT32F50442_52) + LEDC_IRQn = 29, /*!< LEDC global Interrupt */ + #endif + #if defined(USE_HT32F52342_52) || defined(USE_HT32F52243_53) || defined(USE_HT32F5826) || defined(USE_HT32F0008) || defined(USE_HT32F52344_54) || defined(USE_HT32F0006) || defined(USE_HT32F52357_67) || defined(USE_HT32F57342_52) || defined(USE_HT32F50343) || defined(USE_HT32F54243_53) || defined(USE_HT32F61244_45) || defined(USE_HT32F67041_51) || defined(USE_HT32F53231_41) || defined(USE_HT32F53242_52) || defined(USE_HT32F50431_41) || defined(USE_HT32F50442_52) || defined(USE_HT32F52234_44) + PDMACH0_1_IRQn = 30, /*!< PDMA channel 0-1 interrupt */ + PDMACH2_5_IRQn = 31, /*!< PDMA channel 2-5 interrupt */ + #endif + #endif +} IRQn_Type; + +#define EXTI0_IRQn EXTI0_1_IRQn +#define EXTI1_IRQn EXTI0_1_IRQn +#define EXTI2_IRQn EXTI2_3_IRQn +#define EXTI3_IRQn EXTI2_3_IRQn +#if defined(USE_HT32F65230_40) || defined(USE_HT32F65232) +#define EXTI4_IRQn EXTI4_9_IRQn +#define EXTI5_IRQn EXTI4_9_IRQn +#define EXTI6_IRQn EXTI4_9_IRQn +#define EXTI7_IRQn EXTI4_9_IRQn +#define EXTI8_IRQn EXTI4_9_IRQn +#define EXTI9_IRQn EXTI4_9_IRQn +#define EXTI10_IRQn EXTI10_15_IRQn +#define EXTI11_IRQn EXTI10_15_IRQn +#define EXTI12_IRQn EXTI10_15_IRQn +#define EXTI13_IRQn EXTI10_15_IRQn +#define EXTI14_IRQn EXTI10_15_IRQn +#define EXTI15_IRQn EXTI10_15_IRQn +#elif defined(USE_HT32F50020_30) +#define EXTI4_IRQn EXTI4_7_IRQn +#define EXTI5_IRQn EXTI4_7_IRQn +#define EXTI6_IRQn EXTI4_7_IRQn +#define EXTI7_IRQn EXTI4_7_IRQn +#else +#define EXTI4_IRQn EXTI4_15_IRQn +#define EXTI5_IRQn EXTI4_15_IRQn +#define EXTI6_IRQn EXTI4_15_IRQn +#define EXTI7_IRQn EXTI4_15_IRQn +#define EXTI8_IRQn EXTI4_15_IRQn +#define EXTI9_IRQn EXTI4_15_IRQn +#define EXTI10_IRQn EXTI4_15_IRQn +#define EXTI11_IRQn EXTI4_15_IRQn +#define EXTI12_IRQn EXTI4_15_IRQn +#define EXTI13_IRQn EXTI4_15_IRQn +#define EXTI14_IRQn EXTI4_15_IRQn +#define EXTI15_IRQn EXTI4_15_IRQn +#endif + +#define PDMACH0_IRQn PDMACH0_1_IRQn +#define PDMACH1_IRQn PDMACH0_1_IRQn +#if defined(USE_HT32F65230_40) || defined(USE_HT32F65232) || defined(USE_HT32F66242) || defined(USE_HT32F66246) +#define PDMACH2_IRQn PDMACH2_3_IRQn +#define PDMACH3_IRQn PDMACH2_3_IRQn +#define PDMACH4_IRQn PDMACH4_5_IRQn +#define PDMACH5_IRQn PDMACH4_5_IRQn +#else +#define PDMACH2_IRQn PDMACH2_5_IRQn +#define PDMACH3_IRQn PDMACH2_5_IRQn +#define PDMACH4_IRQn PDMACH2_5_IRQn +#define PDMACH5_IRQn PDMACH2_5_IRQn +#endif + + +/** + * @} + */ + +#include "core_cm0plus.h" /* Cortex-M0+ processor and core peripherals */ +#include "system_ht32f5xxxx_01.h" /* HT32 system */ + + +/** @addtogroup Exported_Types + * @{ + */ + +typedef signed long long s64; +typedef signed int s32; +typedef signed short s16; +typedef signed char s8; + +typedef const s64 sc64; /*!< Read Only */ +typedef const s32 sc32; /*!< Read Only */ +typedef const s16 sc16; /*!< Read Only */ +typedef const s8 sc8; /*!< Read Only */ + +typedef __IO s64 vs64; +typedef __IO s32 vs32; +typedef __IO s16 vs16; +typedef __IO s8 vs8; + +typedef __I s64 vsc64; /*!< Read Only */ +typedef __I s32 vsc32; /*!< Read Only */ +typedef __I s16 vsc16; /*!< Read Only */ +typedef __I s8 vsc8; /*!< Read Only */ + +typedef unsigned long long u64; +typedef unsigned int u32; +typedef unsigned short u16; +typedef unsigned char u8; + +typedef const u64 uc64; /*!< Read Only */ +typedef const u32 uc32; /*!< Read Only */ +typedef const u16 uc16; /*!< Read Only */ +typedef const u8 uc8; /*!< Read Only */ + +typedef __IO u64 vu64; +typedef __IO u32 vu32; +typedef __IO u16 vu16; +typedef __IO u8 vu8; + +typedef __I u64 vuc64; /*!< Read Only */ +typedef __I u32 vuc32; /*!< Read Only */ +typedef __I u16 vuc16; /*!< Read Only */ +typedef __I u8 vuc8; /*!< Read Only */ + + +typedef enum {DISABLE = 0, ENABLE = !DISABLE} EventStatus, ControlStatus; + +#if !defined(bool) && !defined(__cplusplus) // user may already included or CPP +typedef enum {FALSE = 0, TRUE = !FALSE} bool; +#define false FALSE +#define true TRUE +#else +#define FALSE 0 +#define TRUE 1 +#endif + +typedef enum {RESET = 0, SET = !RESET} FlagStatus; + +typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrStatus; + +/** + * @} + */ + +#if defined (__CC_ARM) + #define __ALIGN4 __align(4) +#elif defined (__ICCARM__) + #define __ALIGN4 _Pragma("data_alignment = 4") +#elif defined (__GNUC__) + #define __ALIGN4 __attribute__((aligned(4))) +#endif + +#if defined (__GNUC__) + #define __PACKED_H + #define __PACKED_F __attribute__ ((packed)) +#elif defined (__ICCARM__) || (__CC_ARM) + #define __PACKED_H __packed + #define __PACKED_F +#endif + +#if defined (__CC_ARM) +#pragma anon_unions +#endif + + +#define U8_MAX ((u8)255) +#define S8_MAX ((s8)127) +#define S8_MIN ((s8)-128) +#define U16_MAX ((u16)65535u) +#define S16_MAX ((s16)32767) +#define S16_MIN ((s16)-32768) +#define U32_MAX ((u32)4294967295uL) +#define S32_MAX ((s32)2147483647) +#define S32_MIN ((s32)-2147483648) + + +/** + * @brief Exported constants and macro + */ +#define IS_CONTROL_STATUS(STATUS) ((STATUS == DISABLE) || (STATUS == ENABLE)) + +#define wb(addr, value) (*((u8 volatile *) (addr)) = value) +#define rb(addr) (*((u8 volatile *) (addr))) +#define whw(addr, value) (*((u16 volatile *) (addr)) = value) +#define rhw(addr) (*((u16 volatile *) (addr))) +#define ww(addr, value) (*((u32 volatile *) (addr)) = value) +#define rw(addr) (*((u32 volatile *) (addr))) + + +#define ResetBit_BB(Addr, BitNumber) (rw(Addr) &= ~(1UL << BitNumber)) +#define SetBit_BB(Addr, BitNumber) (rw(Addr) |= (1UL << BitNumber)) +#define GetBit_BB(Addr, BitNumber) ((rw(Addr) >> BitNumber) & 1UL) +#define WriteBit_BB(Addr, BitNumber, Value) (Addr = ((Addr & ~((u32)1 << BitNumber)) | ((u32)Value << BitNumber))) + +#define STRCAT2_(a, b) a##b +#define STRCAT2(a, b) STRCAT2_(a, b) +#define STRCAT3_(a, b, c) a##b##c +#define STRCAT3(a, b, c) STRCAT3_(a, b, c) + +#define IPN_NULL (0) +#define IPN_MCTM0 (0x4002C000) +#define IPN_MCTM1 (0x4002D000) +#define IPN_GPTM0 (0x4006E000) +#define IPN_GPTM1 (0x4006F000) +#define IPN_SCTM0 (0x40034000) +#define IPN_SCTM1 (0x40074000) +#define IPN_SCTM2 (0x40035000) +#define IPN_SCTM3 (0x40075000) +#define IPN_PWM0 (0x40031000) +#define IPN_PWM1 (0x40071000) +#define IPN_PWM2 (0x40031000) +#define IPN_BFTM0 (0x40076000) +#define IPN_BFTM1 (0x40077000) +#define IPN_CHECK(IP) STRCAT2(IPN_, IP) +#define IS_IPN_BFTM(IP) (IPN_CHECK(IP) == IPN_BFTM0) || (IPN_CHECK(IP) == IPN_BFTM1) +#define IS_IPN_MCTM(IP) (IPN_CHECK(IP) == IPN_MCTM0) || (IPN_CHECK(IP) == IPN_MCTM1) +#define IS_IPN_GPTM(IP) (IPN_CHECK(IP) == IPN_GPTM0) || (IPN_CHECK(IP) == IPN_GPTM1) +#define IS_IPN_SCTM(IP) (IPN_CHECK(IP) == IPN_SCTM0) || (IPN_CHECK(IP) == IPN_SCTM1) || (IPN_CHECK(IP) == IPN_SCTM2) || (IPN_CHECK(IP) == IPN_SCTM3) +#define IS_IPN_PWM(IP) (IPN_CHECK(IP) == IPN_PWM0) || (IPN_CHECK(IP) == IPN_PWM1) || (IPN_CHECK(IP) == IPN_PWM2) +#define IS_IPN_TM(IP) (IS_IPN_MCTM(IP) || IS_IPN_GPTM(IP) || IS_IPN_SCTM(IP) || IS_IPN_PWM(IP)) + + +/** @addtogroup Peripheral_Registers_Structures + * @{ + */ + + +/** + * @brief Universal Synchronous Asynchronous Receiver Transmitter + */ +typedef struct +{ + /* USART0: 0x40000000 */ + /* USART1: 0x40040000 */ + /* UART0: 0x40001000 */ + /* UART2: 0x40002000 */ + /* UART1: 0x40041000 */ + /* UART3: 0x40042000 */ + __IO uint32_t DR; /*!< 0x000 Data Register */ + __IO uint32_t CR; /*!< 0x004 Control Register */ + __IO uint32_t FCR; /*!< 0x008 FIFO Control Register */ + __IO uint32_t IER; /*!< 0x00C Interrupt Enable Register */ + __IO uint32_t SR; /*!< 0x010 Status Register */ + __IO uint32_t TPR; /*!< 0x014 Timing Parameter Register */ + __IO uint32_t ICR; /*!< 0x018 IrDA COntrol Register */ + __IO uint32_t RCR; /*!< 0x01C RS485 Control Register */ + __IO uint32_t SCR; /*!< 0x020 Synchronous Control Register */ + __IO uint32_t DLR; /*!< 0x024 Divisor Latch Register */ + __IO uint32_t DTR; /*!< 0x028 Debug/Test Register */ +} HT_USART_TypeDef; + + +/** + * @brief SPI + */ +typedef struct +{ + /* SPI0: 0x40004000 */ + /* SPI1: 0x40044000 */ + __IO uint32_t CR0; /*!< 0x000 Control Register 0 */ + __IO uint32_t CR1; /*!< 0x004 Control Register 1 */ + __IO uint32_t IER; /*!< 0x008 Interrupt Enable Register */ + __IO uint32_t CPR; /*!< 0x00C Clock Prescaler Register */ + __IO uint32_t DR; /*!< 0x010 Data Register */ + __IO uint32_t SR; /*!< 0x014 Status Register */ + __IO uint32_t FCR; /*!< 0x018 FIFO Control Register */ + __IO uint32_t FSR; /*!< 0x01C FIFO Status Register */ + __IO uint32_t FTOCR; /*!< 0x020 FIFO Time Out Counter Register */ +#if defined(USE_HT32F0006) || defined(USE_HT32F61244_45) + __IO uint32_t MIDICR0; /*!< 0x040 MIDI Control Register 0 */ + __IO uint32_t MIDICR1; /*!< 0x044 MIDI Control Register 1 */ +#endif +} HT_SPI_TypeDef; + + +#if defined(USE_HT32F65230_40) || defined(USE_HT32F65232) || defined(USE_HT32F66242) || defined(USE_HT32F66246) +/** + * @brief Analog to Digital Converter + */ +typedef struct +{ + /* ADC0: 0x40010000 */ + /* ADC1: 0x40050000 */ + __IO uint32_t CFGR; /*!< 0x000 ADC Configuration Register (ADC1 only) */ + __IO uint32_t RST; /*!< 0x004 ADC Reset Register */ + __IO uint32_t CONV; /*!< 0x008 ADC Regular Conversion Mode Register */ + __IO uint32_t HCONV; /*!< 0x00C ADC High-priority Conversion Mode Register */ + __IO uint32_t LST[2]; /*!< 0x010 - 0x014 ADC Conversion List Register */ + uint32_t RESERVE0[2]; /*!< 0x018 - 0x01C Reserved */ + __IO uint32_t HLST; /*!< 0x020 ADC High-priority Conversion List Register */ + uint32_t RESERVE1[3]; /*!< 0x024 - 0x02C Reserved */ + #if defined(USE_HT32F65230_40) + __IO uint32_t OFR[12]; /*!< 0x030 - 0x05C ADC Input Offset Register 0-11 */ + uint32_t RESERVE2[4]; /*!< 0x060 - 0x06C Reserved */ + __IO uint32_t STR[12]; /*!< 0x070 - 0x08C ADC Input Sampling Time Register 0-11 */ + uint32_t RESERVE3[4]; /*!< 0x090 - 0x0AC Reserved */ + #endif + #if defined(USE_HT32F65232) + __IO uint32_t OFR[15]; /*!< 0x030 - 0x068 ADC Input Offset Register 0-14 */ + uint32_t RESERVE2[1]; /*!< 0x06C Reserved */ + __IO uint32_t STR[15]; /*!< 0x070 - 0x0A8 ADC Input Sampling Time Register 0-14 */ + uint32_t RESERVE3[1]; /*!< 0x0AC Reserved */ + #endif + #if defined(USE_HT32F66242) + uint32_t RESERVE2[16]; /*!< 0x030 - 0x06C Reserved */ + __IO uint32_t STR[16]; /*!< 0x070 - 0x0AC ADC Input Sampling Time Register 0-15 */ + #endif + #if defined(USE_HT32F66246) + uint32_t RESERVE2[16]; /*!< 0x030 - 0x06C Reserved */ + __IO uint32_t STR[16]; /*!< 0x070 - 0x0AC ADC Input Sampling Time Register 0-15 */ + #endif + __IO uint32_t DR[8]; /*!< 0x0B0 - 0x0CC ADC Regular Conversion Data Register 0-7 */ + uint32_t RESERVE4[8]; /*!< 0x0D0 - 0x0EC Reserved */ + __IO uint32_t HDR[4]; /*!< 0x0F0 - 0x0FC ADC High-priority Conversion Data Register 0-3 */ + __IO uint32_t TCR; /*!< 0x100 ADC Trigger Control Register */ + __IO uint32_t TSR; /*!< 0x104 ADC Trigger Source Register */ + uint32_t RESERVE5[2]; /*!< 0x108 - 0x10C Reserved */ + __IO uint32_t HTCR; /*!< 0x110 ADC High-priority Trigger Control Register */ + __IO uint32_t HTSR; /*!< 0x114 ADC High-priority Trigger Source Register */ + uint32_t RESERVE6[2]; /*!< 0x118 - 0x11C Reserved */ + __IO uint32_t WCR; /*!< 0x120 ADC Watchdog Control Register */ + __IO uint32_t LTR; /*!< 0x124 ADC Watchdog Threshold Register */ + __IO uint32_t UTR; /*!< 0x128 ADC Watchdog Threshold Register */ + uint32_t RESERVE7[1]; /*!< 0x12C Reserved */ + __IO uint32_t IER; /*!< 0x130 ADC Interrupt Enable Register */ + __IO uint32_t IRAW; /*!< 0x134 ADC Interrupt Raw Status Register */ + __IO uint32_t ISR; /*!< 0x138 ADC Interrupt Status Register */ + __IO uint32_t ICLR; /*!< 0x13C ADC Interrupt Clear Register */ + __IO uint32_t PDMAR; /*!< 0x140 ADC PDMA Request Register */ + #if defined(USE_HT32F65230_40) + uint32_t RESERVE8[3]; /*!< 0x144 - 0x14C Reserved */ + __IO uint32_t DIESR; /*!< 0x150 Dual ADC Interrupt Enable/Status Register (ADC1 only) */ + __IO uint32_t DPDMAR; /*!< 0x154 Dual ADC PDMA Request Register (ADC1 only) */ + #endif + #if defined(USE_HT32F66242) + uint32_t RESERVE8[3]; /*!< 0x144 - 0x14C Reserved */ + __IO uint32_t VREFCR; /*!< 0x150 ADC Reference Voltage Control Register */ + uint32_t RESERVE9[3]; /*!< 0x154 - 0x15C Reserved */ + __IO uint32_t HDR4[8]; /*!< 0x160 - 0x17C ADC High-priority Conversion Data Register 4-11 */ + uint32_t RESERVE10[4]; /*!< 0x180 - 0x18C Reserved */ + __IO uint32_t STR16[2]; /*!< 0x190 - 0x194 ADC Input Sampling Time Register 16-17 */ + #endif + #if defined(USE_HT32F66246) + uint32_t RESERVE8[3]; /*!< 0x144 - 0x14C Reserved */ + __IO uint32_t VREFCR; /*!< 0x150 ADC Reference Voltage Control Register */ + uint32_t RESERVE9[3]; /*!< 0x154 - 0x15C Reserved */ + __IO uint32_t HDR4[8]; /*!< 0x160 - 0x17C ADC High-priority Conversion Data Register 4-11 */ + uint32_t RESERVE10[4]; /*!< 0x180 - 0x18C Reserved */ + __IO uint32_t STR16[2]; /*!< 0x190 - 0x194 ADC Input Sampling Time Register 16-17 */ + #endif +} HT_ADC_TypeDef; +#else +/** + * @brief Analog to Digital Converter + */ +typedef struct +{ + /* ADC: 0x40010000 */ + __IO uint32_t CR; /*!< 0x000 ADC Conversion Control Register */ + #if defined(USE_HT32F50020_30) + __IO uint32_t LST[1]; /*!< 0x004 ADC Conversion List Register 0 */ + uint32_t RESERVE0[6]; /*!< 0x008 - 0x01C Reserved */ + #else + __IO uint32_t LST[2]; /*!< 0x004 - 0x008 ADC Conversion List Register 0-1 */ + uint32_t RESERVE0[5]; /*!< 0x00C - 0x01C Reserved */ + #endif + __IO uint32_t STR; /*!< 0x020 ADC Input Sampling Time Register */ + uint32_t RESERVE1[3]; /*!< 0x024 - 0x02C Reserved */ + #if defined(USE_HT32F50020_30) + __IO uint32_t DR[4]; /*!< 0x030 - 0x03C ADC Conversion Data Register 0-3 */ + uint32_t RESERVE2[13]; /*!< 0x040 - 0x070 Reserved */ + #else + __IO uint32_t DR[8]; /*!< 0x030 - 0x04C ADC Conversion Data Register 0-7 */ + uint32_t RESERVE2[8]; /*!< 0x050 - 0x06C Reserved */ + __IO uint32_t TCR; /*!< 0x070 ADC Trigger Control Register */ + #endif + __IO uint32_t TSR; /*!< 0x074 ADC Trigger Source Register */ + #if defined(USE_HT32F50020_30) + __IO uint32_t RESERVE3[2]; /*!< 0x078 - 0x07C Reserved */ + #else + __IO uint32_t WCR; /*!< 0x078 ADC Watchdog Control Register */ + __IO uint32_t WTR; /*!< 0x07C ADC Watchdog Threshold Register */ + #endif + __IO uint32_t IER; /*!< 0x080 ADC Interrupt Enable Register */ + __IO uint32_t IRAW; /*!< 0x084 ADC Interrupt Raw Status Register */ + __IO uint32_t ISR; /*!< 0x088 ADC Interrupt Status Register */ + __IO uint32_t ICLR; /*!< 0x08C ADC Interrupt Clear Register */ + #if defined(USE_HT32F52342_52) || defined(USE_HT32F52243_53) || defined(USE_HT32F5826) || defined(USE_HT32F52344_54) || defined(USE_HT32F0006) || defined(USE_HT32F52357_67) || defined(USE_HT32F57342_52) || defined(USE_HT32F50343) || defined(USE_HT32F54243_53) || defined(USE_HT32F61244_45) || defined(USE_HT32F67041_51) || defined(USE_HT32F53231_41) || defined(USE_HT32F53242_52) || defined(USE_HT32F50431_41) || defined(USE_HT32F50442_52) || defined(USE_HT32F52234_44) + __IO uint32_t PDMAR; /*!< 0x090 ADC PDMA Request Register */ + #else + uint32_t RESERVE4; /*!< 0x090 Reserved */ + #endif + #if defined(USE_HT32F52344_54) || defined(USE_HT32F52357_67) || defined(USE_HT32F57342_52) || defined(USE_HT32F57331_41) || defined(USE_HT32F50343) || defined(USE_HT32F54231_41) || defined(USE_HT32F54243_53) || defined(USE_HT32F67041_51) || defined(USE_HT32F50020_30) || defined(USE_HT32F53231_41) || defined(USE_HT32F53242_52) || defined(USE_HT32F50431_41) || defined(USE_HT32F50442_52) || defined(USE_HT32F52234_44) + uint32_t RESERVE5[3]; /*!< 0x094 - 0x09C Reserved */ + __IO uint32_t VREFCR; /*!< 0x0A0 ADC Reference Voltage Control Register */ + __IO uint32_t VREFVALR; /*!< 0x0A4 ADC Reference Voltage Value Register */ + #endif +} HT_ADC_TypeDef; +#endif + + +/** + * @brief Digital to Analog Converter + */ +typedef struct +{ + /* DACDUAL16: 0x40054000 */ + __IO uint32_t CR; /*!< 0x000 D/A Converter Control Register */ + __IO uint32_t RH; /*!< 0x004 D/A R-channel data register */ + __IO uint32_t LH; /*!< 0x008 D/A L-channel data register */ + __IO uint32_t TG; /*!< 0x00c D/A data trigger Register */ +} HT_DAC_DUAL16_TypeDef; + +/** + * @brief Digital to Analog Converter Channel + */ +typedef struct +{ + __IO uint32_t CR; /*!< 0x000 DAC Channel Control Register */ + uint32_t RESERVE0[2]; /*!< 0x004 - 0x008 Reserved */ + __IO uint32_t DHR; /*!< 0x00C DAC Channel Data Holding Register */ + __IO uint32_t DOR; /*!< 0x010 DAC Channel Data Output Register */ + uint32_t RESERVE1[3]; /*!< 0x014 - 0x01C Reserved */ +} HT_DACCH_TypeDef; + +/** + * @brief Digital to Analog Converter + */ +typedef struct +{ + /* DAC1: 0x40014000 */ + /* DAC0: 0x40054000 */ + __IO uint32_t CFGR; /*!< 0x000 DAC Configuration Register */ + uint32_t RESERVE0[3]; /*!< 0x004 - 0x00C Reserved */ + HT_DACCH_TypeDef DACCH0; /*!< 0x010 DAC channel 0 registers */ + HT_DACCH_TypeDef DACCH1; /*!< 0x030 DAC channel 1 registers */ +} HT_DAC_TypeDef; + +/** + * @brief Comparator + */ +typedef struct +{ + /* CMP0: 0x40058000 */ + /* CMP1: 0x40058100 */ + /* CMP2: 0x40058200 */ + __IO uint32_t CR; /*!< 0x000 Comparator Control Register */ + __IO uint32_t VALR; /*!< 0x004 Comparator Voltage Reference Value Register */ + __IO uint32_t IER; /*!< 0x008 Comparator Interrupt Enable Register */ + __IO uint32_t TFR; /*!< 0x00C Comparator Transition Flag Register */ + #if defined(USE_HT32F65230_40) || defined(USE_HT32F65232) || defined(USE_HT32F66242) || defined(USE_HT32F66246) + __IO uint32_t CI; /*!< 0x010 Comparator Input Control Register */ + #endif + #if defined(USE_HT32F65232) || defined(USE_HT32F66242) || defined(USE_HT32F66246) + __IO uint32_t CO; /*!< 0x014 Comparator Output Control Register */ + #endif +} HT_CMP_TypeDef; + + +/** + * @brief Operational Amplifier + */ +typedef struct +{ + /* OPA0: 0x40018000 */ + /* OPA1: 0x40018100 */ + __IO uint32_t CR; /*!< 0x000 Operational Amplifier Control Register */ + #if defined(USE_HT32F65232) + __IO uint32_t VOS; /*!< 0x004 Operational Amplifier Input Offset Register */ + __IO uint32_t DAC; /*!< 0x008 Operational Amplifier Voltage Reference Value Register */ + #endif +} HT_OPA_TypeDef; + +/** + * @brief Programmable Gain Amplifier 0~X + */ +typedef struct +{ + /* PGA0: 0x40018000 */ + /* PGA1: 0x40018008 */ + /* PGA2: 0x40018010 */ + /* PGA3: 0x40018018 */ + __IO uint32_t CR; /*!< 0x000 Programmable Gain Amplifier Control Register */ + __IO uint32_t VOS; /*!< 0x004 Programmable Gain Amplifier Offset Control Register */ +} HT_PGA0_X_TypeDef; + +/** + * @brief Programmable Gain Amplifier + */ +typedef struct +{ + /* PGA: 0x40018000 */ + __IO uint32_t VR; /*!< 0x020 PGA Voltage Follower Control Register */ +} HT_PGA_TypeDef; + +/** + * @brief General Purpose I/O + */ +typedef struct +{ + /* GPIOA: 0x400B0000 */ + /* GPIOB: 0x400B2000 */ + /* GPIOC: 0x400B4000 */ + /* GPIOD: 0x400B6000 */ + /* GPIOE: 0x400B8000 */ + /* GPIOF: 0x400BA000 */ + __IO uint32_t DIRCR; /*!< 0x000 Data Direction Control Register */ + __IO uint32_t INER; /*!< 0x004 Input function enable register */ + __IO uint32_t PUR; /*!< 0x008 Pull-Up Selection Register */ + __IO uint32_t PDR; /*!< 0x00C Pull-Down Selection Register */ + __IO uint32_t ODR; /*!< 0x010 Open Drain Selection Register */ + __IO uint32_t DRVR; /*!< 0x014 Drive Current Selection Register */ + __IO uint32_t LOCKR; /*!< 0x018 Lock Register */ + __IO uint32_t DINR; /*!< 0x01c Data Input Register */ + __IO uint32_t DOUTR; /*!< 0x020 Data Output Register */ + __IO uint32_t SRR; /*!< 0x024 Output Set and Reset Control Register */ + __IO uint32_t RR; /*!< 0x028 Output Reset Control Register */ + #if defined(USE_HT32F50220_30) || defined(USE_HT32F50231_41) || defined(USE_HT32F54231_41) || defined(USE_HT32F54243_53) || defined(USE_HT32F53231_41) || defined(USE_HT32F53242_52) || defined(USE_HT32F50431_41) || defined(USE_HT32F50442_52) + __IO uint32_t SCER; /*!< 0x02C Sink Current Enhanced Selection Register */ + #endif +} HT_GPIO_TypeDef; + + +/** + * @brief AFIO + */ +typedef struct +{ + /* AFIO: 0x40022000 */ + #if defined(USE_HT32F50020_30) + __IO uint32_t ESSR[1]; /*!< 0x000 EXTI Source Selection Register 0 */ + uint32_t RESERVE0[7]; /*!< 0x004 - 0x01C Reserved */ + #else + __IO uint32_t ESSR[2]; /*!< 0x000 EXTI Source Selection Register 0 ~ 1 */ + uint32_t RESERVE0[6]; /*!< 0x008 - 0x01C Reserved */ + #endif + __IO uint32_t GPACFGR[2]; /*!< 0x020 GPIO Port A Configuration Register 0 ~ 1 */ + __IO uint32_t GPBCFGR[2]; /*!< 0x028 GPIO Port B Configuration Register 0 ~ 1 */ + #if !defined(USE_HT32F52220_30) + __IO uint32_t GPCCFGR[2]; /*!< 0x030 GPIO Port C Configuration Register 0 ~ 1 */ + #endif + #if defined(USE_HT32F52342_52) || defined(USE_HT32F52243_53) || defined(USE_HT32F5826) || defined(USE_HT32F52344_54) || defined(USE_HT32F0006) || defined(USE_HT32F52357_67) || defined(USE_HT32F57342_52) || defined(USE_HT32F57331_41) || defined(USE_HT32F54243_53) || defined(USE_HT32F61244_45) || defined(USE_HT32F53231_41) || defined(USE_HT32F53242_52) || defined(USE_HT32F50431_41) || defined(USE_HT32F50442_52) + __IO uint32_t GPDCFGR[2]; /*!< 0x038 GPIO Port D Configuration Register 0 ~ 1 */ + #endif + #if defined(USE_HT32F52357_67) || defined(USE_HT32F57342_52) || defined(USE_HT32F57331_41) + __IO uint32_t GPECFGR[2]; /*!< 0x040 GPIO Port E Configuration Register 0 ~ 1 */ + #endif + #if defined(USE_HT32F0008) || defined(USE_HT32F50020_30) + uint32_t RESERVE1[4]; /*!< 0x038 - 0x044 Reserved */ + __IO uint32_t GPFCFGR[2]; /*!< 0x048 GPIO Port F Configuration Register 0 ~ 1 */ + #endif +} HT_AFIO_TypeDef; + + +/** + * @brief External Interrupt/Event Controller + */ +typedef struct +{ + /* EXTI: 0x40024000 */ + __IO uint32_t CFGR0; /*!< 0x000 EXTI Interrupt 0 Configuration Register */ + __IO uint32_t CFGR1; /*!< 0x004 EXTI Interrupt 1 Configuration Register */ + __IO uint32_t CFGR2; /*!< 0x008 EXTI Interrupt 2 Configuration Register */ + __IO uint32_t CFGR3; /*!< 0x00C EXTI Interrupt 3 Configuration Register */ + __IO uint32_t CFGR4; /*!< 0x010 EXTI Interrupt 4 Configuration Register */ + __IO uint32_t CFGR5; /*!< 0x014 EXTI Interrupt 5 Configuration Register */ + __IO uint32_t CFGR6; /*!< 0x018 EXTI Interrupt 6 Configuration Register */ + __IO uint32_t CFGR7; /*!< 0x01C EXTI Interrupt 7 Configuration Register */ + #if defined(USE_HT32F50020_30) + __IO uint32_t RESERVE0[8]; /*!< 0x020 - 0x3C Reserved */ + #else + __IO uint32_t CFGR8; /*!< 0x020 EXTI Interrupt 8 Configuration Register */ + __IO uint32_t CFGR9; /*!< 0x024 EXTI Interrupt 9 Configuration Register */ + __IO uint32_t CFGR10; /*!< 0x028 EXTI Interrupt 10 Configuration Register */ + __IO uint32_t CFGR11; /*!< 0x02C EXTI Interrupt 11 Configuration Register */ + __IO uint32_t CFGR12; /*!< 0x030 EXTI Interrupt 12 Configuration Register */ + __IO uint32_t CFGR13; /*!< 0x034 EXTI Interrupt 13 Configuration Register */ + __IO uint32_t CFGR14; /*!< 0x038 EXTI Interrupt 14 Configuration Register */ + __IO uint32_t CFGR15; /*!< 0x03C EXTI Interrupt 15 Configuration Register */ + #endif + __IO uint32_t CR; /*!< 0x040 EXTI Interrupt Control Register */ + __IO uint32_t EDGEFLGR; /*!< 0x044 EXTI Interrupt Edge Flag Register */ + __IO uint32_t EDGESR; /*!< 0x048 EXTI Interrupt Edge Status Register */ + __IO uint32_t SSCR; /*!< 0x04C EXTI Interrupt Software Set Command Register */ + __IO uint32_t WAKUPCR; /*!< 0x050 EXTI Interrupt Wakeup Control Register */ + __IO uint32_t WAKUPPOLR; /*!< 0x054 EXTI Interrupt Wakeup Polarity Register */ + __IO uint32_t WAKUPFLG; /*!< 0x058 EXTI Interrupt Wakeup Flag Register */ +} HT_EXTI_TypeDef; + + +/** + * @brief Inter-integrated Circuit Interface + */ +typedef struct +{ + /* I2C2: 0x40008000 */ + /* I2C0: 0x40048000 */ + /* I2C1: 0x40049000 */ + __IO uint32_t CR; /*!< 0x000 Control Register */ + __IO uint32_t IER; /*!< 0x004 Interrupt Enable Register */ + __IO uint32_t ADDR; /*!< 0x008 Address Register */ + __IO uint32_t SR; /*!< 0x00C Status Register */ + __IO uint32_t SHPGR; /*!< 0x010 SCL High Period Generation Register */ + __IO uint32_t SLPGR; /*!< 0x014 SCL Low Period Generation Register */ + __IO uint32_t DR; /*!< 0x018 Data Register */ + __IO uint32_t TAR; /*!< 0x01C Target Register */ + __IO uint32_t ADDMR; /*!< 0x020 Address Mask Register */ + __IO uint32_t ADDSR; /*!< 0x024 Address Snoop Register */ + __IO uint32_t TOUT; /*!< 0x028 Timeout Register */ +} HT_I2C_TypeDef; + + +/** + * @brief WATCHDOG + */ +typedef struct +{ + /* WDT: 0x40068000 */ + __IO uint32_t CR; /*!< 0x000 Control Register */ + __IO uint32_t MR0; /*!< 0x004 Mode 0 Register */ + __IO uint32_t MR1; /*!< 0x008 Mode 1 Register */ + __IO uint32_t SR; /*!< 0x00C Status Register */ + __IO uint32_t PR; /*!< 0x010 Write Protect Register */ + uint32_t RESERVED0[1]; /*!< 0x014 Reserved */ + __IO uint32_t CSR; /*!< 0x018 Clock Selection Register */ +} HT_WDT_TypeDef; + + +/** + * @brief Real-Time Clock + */ +typedef struct +{ + /* RTC: 0x4006A000 */ + __IO uint32_t CNT; /*!< 0x000 RTC Counter Register */ + __IO uint32_t CMP; /*!< 0x004 RTC Compare Register */ + __IO uint32_t CR; /*!< 0x008 RTC Control Register */ + __IO uint32_t SR; /*!< 0x00C RTC Status Register */ + __IO uint32_t IWEN; /*!< 0x010 RTC Interrupt/Wake-up Enable Register */ +} HT_RTC_TypeDef; + + +/** + * @brief Power Control Unit + */ +typedef struct +{ + /* PWRCU: 0x4006A100 */ + __IO uint32_t SR; /*!< 0x000 Status Register */ + __IO uint32_t CR; /*!< 0x004 Control Register */ + #if !defined(USE_HT32F50220_30) && !defined(USE_HT32F50231_41) && !defined(USE_HT32F65230_40) && !defined(USE_HT32F50343) && !defined(USE_HT32F54231_41) && !defined(USE_HT32F54243_53) && !defined(USE_HT32F50020_30) && !defined(USE_HT32F53231_41) && !defined(USE_HT32F53242_52) && !defined(USE_HT32F50431_41) && !defined(USE_HT32F50442_52) && !defined(USE_HT32F66242) && !defined(USE_HT32F66246) + __IO uint32_t TEST; /*!< 0x008 Test Register */ + #else + uint32_t RESERVE0[1]; /*!< 0x008 Reserved */ + #endif + #if defined(USE_HT32F52342_52) || defined(USE_HT32F5826) || defined(USE_HT32F52357_67) + __IO uint32_t HSIRCR; /*!< 0x00C HSI Ready Counter Control Register */ + #else + uint32_t RESERVE1[1]; /*!< 0x00C Reserved */ + #endif + __IO uint32_t LVDCSR; /*!< 0x010 Low Voltage/Brown Out Detect Control and Status Register*/ + #if defined(USE_HT32F57342_52) + uint32_t RESERVE2[2]; /*!< 0x014 ~ 0x18 Reserved */ + __IO uint32_t LDOSR ; /*!< 0x01C Power Control LDO Status Register */ + #endif + #if defined(USE_HT32F52342_52) || defined(USE_HT32F5826) || defined(USE_HT32F52357_67) + uint32_t RESERVE3[59]; /*!< 0x014 ~ 0x0FC Reserved */ + __IO uint32_t BAKREG[10]; /*!< 0x100 ~ 0x124 Backup Register 0 ~ 9 */ + #endif +} HT_PWRCU_TypeDef; + + +/** + * @brief General-Purpose Timer + */ +typedef struct +{ + /* GPTM0: 0x4006E000 */ + /* GPTM1: 0x4006F000 */ + __IO uint32_t CNTCFR; /*!< 0x000 Counter Configuration Register */ + __IO uint32_t MDCFR; /*!< 0x004 Mode Configuration Register */ + __IO uint32_t TRCFR; /*!< 0x008 Trigger Configuration Register */ + uint32_t RESERVED0[1]; /*!< 0x00C Reserved */ + __IO uint32_t CTR; /*!< 0x010 Control Register */ + uint32_t RESERVED1[3]; /*!< 0x014 - 0x01C Reserved */ + __IO uint32_t CH0ICFR; /*!< 0x020 Channel-0 Input Configuration Register */ + __IO uint32_t CH1ICFR; /*!< 0x024 Channel-1 Input Configuration Register */ + __IO uint32_t CH2ICFR; /*!< 0x028 Channel-2 Input Configuration Register */ + __IO uint32_t CH3ICFR; /*!< 0x02C Channel-3 Input Configuration Register */ + uint32_t RESERVED2[4]; /*!< 0x030 - 0x03C Reserved */ + __IO uint32_t CH0OCFR; /*!< 0x040 Channel-0 Output Configuration Register */ + __IO uint32_t CH1OCFR; /*!< 0x044 Channel-1 Output Configuration Register */ + __IO uint32_t CH2OCFR; /*!< 0x048 Channel-2 Output Configuration Register */ + __IO uint32_t CH3OCFR; /*!< 0x04C Channel-3 Output Configuration Register */ + __IO uint32_t CHCTR; /*!< 0x050 Channel Control Register */ + __IO uint32_t CHPOLR; /*!< 0x054 Channel Polarity Configuration Register */ + uint32_t RESERVED3[7]; /*!< 0x058 - 0x070 Reserved */ + __IO uint32_t DICTR; /*!< 0x074 DMA / Interrupt Control Register */ + __IO uint32_t EVGR; /*!< 0x078 Event Generator Register */ + __IO uint32_t INTSR; /*!< 0x07C Interrupt Status Register */ + __IO uint32_t CNTR; /*!< 0x080 Counter Register */ + __IO uint32_t PSCR; /*!< 0x084 Prescaler Register */ + __IO uint32_t CRR; /*!< 0x088 Counter Reload Register */ + uint32_t RESERVED4[1]; /*!< 0x08C Reserved */ + __IO uint32_t CH0CCR; /*!< 0x090 Channel 0 Capture/Compare Register */ + __IO uint32_t CH1CCR; /*!< 0x094 Channel 1 Capture/Compare Register */ + __IO uint32_t CH2CCR; /*!< 0x098 Channel 2 Capture/Compare Register */ + __IO uint32_t CH3CCR; /*!< 0x09C Channel 3 Capture/Compare Register */ + __IO uint32_t CH0ACR; /*!< 0x0A0 Channel 0 Asymmetric Compare Register */ + __IO uint32_t CH1ACR; /*!< 0x0A4 Channel 1 Asymmetric Compare Register */ + __IO uint32_t CH2ACR; /*!< 0x0A8 Channel 2 Asymmetric Compare Register */ + __IO uint32_t CH3ACR; /*!< 0x0AC Channel 3 Asymmetric Compare Register */ +} HT_GPTM_TypeDef; + + +/** + * @brief Flash Memory Controller + */ +typedef struct +{ + /* FLASH: 0x40080000 */ + __IO uint32_t TADR; /*!< 0x000 Flash Target Address Register */ + __IO uint32_t WRDR; /*!< 0x004 Flash Write Data Register */ + uint32_t RESERVED0[1]; /*!< 0x008 Reserved */ + __IO uint32_t OCMR; /*!< 0x00C Flash Operation Command Register */ + __IO uint32_t OPCR; /*!< 0x010 Flash Operation Control Register */ + __IO uint32_t OIER; /*!< 0x014 Flash Operation Interrupt Enable Register */ + __IO uint32_t OISR; /*!< 0x018 Flash Operation Interrupt and Status Register */ + uint32_t RESERVED1[1]; /*!< 0x01C Reserved */ + __IO uint32_t PPSR[4]; /*!< 0x020 ~ 0x02C Flash Page Erase/Program Protection Status Register */ + __IO uint32_t CPSR; /*!< 0x030 Flash Security Protection Status Register */ + uint32_t RESERVED2[51]; /*!< 0x034 ~ 0x0FC Reserved */ + __IO uint32_t VMCR; /*!< 0x100 Flash Vector Mapping Control Register */ + uint32_t RESERVED3[31]; /*!< 0x104 ~ 0x17C Reserved */ + __IO uint32_t MDID; /*!< 0x180 Manufacturer and Device ID Register */ + __IO uint32_t PNSR; /*!< 0x184 Flash Page Number Status Register */ + __IO uint32_t PSSR; /*!< 0x188 Flash Page Size Status Register */ + __IO uint32_t DID; /*!< 0x18C Device ID Register */ + uint32_t RESERVED4[28]; /*!< 0x190 ~ 0x1FC Reserved */ + #if defined(USE_HT32F50220_30) || defined(USE_HT32F50231_41) + uint32_t RESERVED5[1]; /*!< 0x200 Reserved */ + #else + __IO uint32_t CFCR; /*!< 0x200 Flash Cache and Pre-fetch Control Register */ + #endif + uint32_t RESERVED6[67]; /*!< 0x204 ~ 0x30C Reserved */ + __IO uint32_t CID[4]; /*!< 0x310 ~ 0x31C Custom ID Register */ +} HT_FLASH_TypeDef; + + +/** + * @brief Clock Control Unit + */ +typedef struct +{ + /* CKCU: 0x40088000 */ + __IO uint32_t GCFGR; /*!< 0x000 Global Clock Configuration Register */ + __IO uint32_t GCCR; /*!< 0x004 Global Clock Control Register */ + __IO uint32_t GCSR; /*!< 0x008 Global Clock Status Register */ + __IO uint32_t GCIR; /*!< 0x00C Global Clock Interrupt Register */ + uint32_t RESERVED0[2]; /*!< 0x010 ~ 0x14 Reserved */ + #if !defined(USE_HT32F50220_30) && !defined(USE_HT32F50231_41) + __IO uint32_t PLLCFGR; /*!< 0x018 PLL Configuration Register */ + __IO uint32_t PLLCR; /*!< 0x01C PLL Control Register */ + #else + uint32_t RESERVED1[2]; /*!< 0x018 ~ 0x1C Reserved */ + #endif + __IO uint32_t AHBCFGR; /*!< 0x020 AHB Configuration Register */ + __IO uint32_t AHBCCR; /*!< 0x024 AHB Clock Control Register */ + #if defined(USE_HT32F0008) + uint32_t RESERVED1[1]; /*!< 0x028 Reserved */ + #else + __IO uint32_t APBCFGR; /*!< 0x028 APB Configuration Register */ + #endif + __IO uint32_t APBCCR0; /*!< 0x02C APB Clock Control Register 0 */ + __IO uint32_t APBCCR1; /*!< 0x030 APB Clock Control Register 1 */ + __IO uint32_t CKST; /*!< 0x034 Clock source status Register */ + #if !defined(USE_HT32F50020_30) + __IO uint32_t APBPCSR0; /*!< 0x038 APB Peripheral Clock Selection Register 0 */ + __IO uint32_t APBPCSR1; /*!< 0x03C APB Peripheral Clock Selection Register 1 */ + #else + uint32_t RESERVED2[2]; /*!< 0x038 ~ 0x3C Reserved */ + #endif + #if !defined(USE_HT32F50020_30) + __IO uint32_t HSICR; /*!< 0x040 HSI Control Register */ + __IO uint32_t HSIATCR; /*!< 0x044 HSI Auto Trimming Counter Register */ + #else + uint32_t RESERVED3[2]; /*!< 0x040 ~ 0x44 Reserved */ + #endif + #if defined(USE_HT32F0008) || defined(USE_HT32F50220_30) || defined(USE_HT32F50231_41) || defined(USE_HT32F0006) || defined(USE_HT32F52357_67) || defined(USE_HT32F57342_52) || defined(USE_HT32F57331_41) || defined(USE_HT32F50343) || defined(USE_HT32F54231_41) || defined(USE_HT32F54243_53) || defined(USE_HT32F61244_45) || defined(USE_HT32F53231_41) || defined(USE_HT32F53242_52) || defined(USE_HT32F50431_41) || defined(USE_HT32F50442_52) + __IO uint32_t APBPCSR2; /*!< 0x048 APB Peripheral Clock Selection Register 2 */ + uint32_t RESERVED4[173]; /*!< 0x04C ~ 0x2FC Reserved */ + #elif defined(USE_HT32F52234_44) + __IO uint32_t APBPCSR2; /*!< 0x048 APB Peripheral Clock Selection Register 2 */ + __IO uint32_t HSIRDYCR; /*!< 0x04C HSI Ready Counter Register */ + uint32_t RESERVED4[172]; /*!< 0x050 ~ 0x2FC Reserved */ + #else + uint32_t RESERVED4[174]; /*!< 0x048 ~ 0x2FC Reserved */ + #endif + #if !defined(USE_HT32F50020_30) + __IO uint32_t LPCR; /*!< 0x300 Low Power Control Register */ + #else + uint32_t RESERVED5; /*!< 0x300 Reserved */ + #endif + __IO uint32_t MCUDBGCR; /*!< 0x304 MCU Debug Control Register */ +} HT_CKCU_TypeDef; + + +/** + * @brief Reset Control Unit + */ +typedef struct +{ + /* RSTCU: 0x40088100 */ + __IO uint32_t GRSR; /*!< 0x000 Global Reset Status Register */ + __IO uint32_t AHBPRST; /*!< 0x004 AHB Peripheral Reset Register */ + __IO uint32_t APBPRST0; /*!< 0x008 APB Peripheral Reset Register 0 */ + __IO uint32_t APBPRST1; /*!< 0x00C APB Peripheral Reset Register 1 */ +} HT_RSTCU_TypeDef; + + +/** + * @brief Smart Card Interface + */ +typedef struct +{ + /* SCI0: 0x40043000 */ + /* SCI1: 0x4003A000 */ + __IO uint32_t CR; /*!< 0x000 Control Register */ + __IO uint32_t SR; /*!< 0x004 Status Register */ + __IO uint32_t CCR; /*!< 0x008 Contact Control Register */ + __IO uint32_t ETU; /*!< 0x00C Elementary Time Unit Register */ + __IO uint32_t GT; /*!< 0x010 Guardtime Register */ + __IO uint32_t WT; /*!< 0x014 Waiting Time Register */ + __IO uint32_t IER; /*!< 0x018 Interrupt Enable Register */ + __IO uint32_t IPR; /*!< 0x01C Interrupt Pending Register */ + __IO uint32_t TXB; /*!< 0x020 Transmit Buffer Register */ + __IO uint32_t RXB; /*!< 0x024 Receive Buffer Register */ + __IO uint32_t PSC; /*!< 0x028 Prescaler Register */ +} HT_SCI_TypeDef; + + +/** + * @brief Basic Function Timer + */ +typedef struct +{ + /* BFTM0: 0x40076000 */ + /* BFTM1: 0x40077000 */ + __IO uint32_t CR; /*!< 0x000 Control Register */ + __IO uint32_t SR; /*!< 0x004 Status Register */ + __IO uint32_t CNTR; /*!< 0x008 Counter Value Register */ + __IO uint32_t CMP; /*!< 0x00C Compare Value Register */ +} HT_BFTM_TypeDef; + + +#if 0 +/** + * @brief Motor Control Timer + */ +typedef struct +{ + /* MCTM0: 0x4002C000 */ + __IO uint32_t CNTCFR; /*!< 0x000 Counter Configuration Register */ + __IO uint32_t MDCFR; /*!< 0x004 Mode Configuration Register */ + __IO uint32_t TRCFR; /*!< 0x008 Trigger Configuration Register */ + uint32_t RESERVED0[1]; /*!< 0x00C Reserved */ + __IO uint32_t CTR; /*!< 0x010 Control Register */ + uint32_t RESERVED1[3]; /*!< 0x014 - 0x01C Reserved */ + __IO uint32_t CH0ICFR; /*!< 0x020 Channel-0 Input Configuration Register */ + __IO uint32_t CH1ICFR; /*!< 0x024 Channel-1 Input Configuration Register */ + __IO uint32_t CH2ICFR; /*!< 0x028 Channel-2 Input Configuration Register */ + __IO uint32_t CH3ICFR; /*!< 0x02C Channel-3 Input Configuration Register */ + uint32_t RESERVED2[4]; /*!< 0x030 - 0x03C Reserved */ + __IO uint32_t CH0OCFR; /*!< 0x040 Channel-0 Output Configuration Register */ + __IO uint32_t CH1OCFR; /*!< 0x044 Channel-1 Output Configuration Register */ + __IO uint32_t CH2OCFR; /*!< 0x048 Channel-2 Output Configuration Register */ + __IO uint32_t CH3OCFR; /*!< 0x04C Channel-3 Output Configuration Register */ + __IO uint32_t CHCTR; /*!< 0x050 Channel Control Register */ + __IO uint32_t CHPOLR; /*!< 0x054 Channel Polarity Configuration Register */ + uint32_t RESERVED3[5]; /*!< 0x058 - 0x068 Reserved */ + __IO uint32_t CHBRKCFR; /*!< 0x06C Channel Break Configuration Register */ + __IO uint32_t CHBRKCTR; /*!< 0x070 Channel Break Control Register */ + __IO uint32_t DICTR; /*!< 0x074 DMA / Interrupt Control Register */ + __IO uint32_t EVGR; /*!< 0x078 Event Generator Register */ + __IO uint32_t INTSR; /*!< 0x07C Interrupt Status Register */ + __IO uint32_t CNTR; /*!< 0x080 Counter Register */ + __IO uint32_t PSCR; /*!< 0x084 Prescaler Register */ + __IO uint32_t CRR; /*!< 0x088 Counter Reload Register */ + __IO uint32_t REPR; /*!< 0x08C Repetition Register */ + __IO uint32_t CH0CCR; /*!< 0x090 Channel 0 Capture/Compare Register */ + __IO uint32_t CH1CCR; /*!< 0x094 Channel 1 Capture/Compare Register */ + __IO uint32_t CH2CCR; /*!< 0x098 Channel 2 Capture/Compare Register */ + __IO uint32_t CH3CCR; /*!< 0x09C Channel 3 Capture/Compare Register */ + __IO uint32_t CH0ACR; /*!< 0x0A0 Channel 0 Asymmetric Compare Register */ + __IO uint32_t CH1ACR; /*!< 0x0A4 Channel 1 Asymmetric Compare Register */ + __IO uint32_t CH2ACR; /*!< 0x0A8 Channel 2 Asymmetric Compare Register */ + __IO uint32_t CH3ACR; /*!< 0x0AC Channel 3 Asymmetric Compare Register */ +} HT_MCTM_TypeDef; +#endif + + +/** + * @brief Timer + */ +typedef struct +{ + __IO uint32_t CNTCFR; /*!< 0x000 Counter Configuration Register */ + __IO uint32_t MDCFR; /*!< 0x004 Mode Configuration Register */ + __IO uint32_t TRCFR; /*!< 0x008 Trigger Configuration Register */ + uint32_t RESERVED0[1]; /*!< 0x00C Reserved */ + __IO uint32_t CTR; /*!< 0x010 Control Register */ + uint32_t RESERVED1[3]; /*!< 0x014 - 0x01C Reserved */ + __IO uint32_t CH0ICFR; /*!< 0x020 Channel-0 Input Configuration Register */ + __IO uint32_t CH1ICFR; /*!< 0x024 Channel-1 Input Configuration Register */ + __IO uint32_t CH2ICFR; /*!< 0x028 Channel-2 Input Configuration Register */ + __IO uint32_t CH3ICFR; /*!< 0x02C Channel-3 Input Configuration Register */ + uint32_t RESERVED2[4]; /*!< 0x030 - 0x03C Reserved */ + __IO uint32_t CH0OCFR; /*!< 0x040 Channel-0 Output Configuration Register */ + __IO uint32_t CH1OCFR; /*!< 0x044 Channel-1 Output Configuration Register */ + __IO uint32_t CH2OCFR; /*!< 0x048 Channel-2 Output Configuration Register */ + __IO uint32_t CH3OCFR; /*!< 0x04C Channel-3 Output Configuration Register */ + __IO uint32_t CHCTR; /*!< 0x050 Channel Control Register */ + __IO uint32_t CHPOLR; /*!< 0x054 Channel Polarity Configuration Register */ + uint32_t RESERVED3[5]; /*!< 0x058 - 0x068 Reserved */ + __IO uint32_t CHBRKCFR; /*!< 0x06C Channel Break Configuration Register */ + __IO uint32_t CHBRKCTR; /*!< 0x070 Channel Break Control Register */ + __IO uint32_t DICTR; /*!< 0x074 DMA / Interrupt Control Register */ + __IO uint32_t EVGR; /*!< 0x078 Event Generator Register */ + __IO uint32_t INTSR; /*!< 0x07C Interrupt Status Register */ + __IO uint32_t CNTR; /*!< 0x080 Counter Register */ + __IO uint32_t PSCR; /*!< 0x084 Prescaler Register */ + __IO uint32_t CRR; /*!< 0x088 Counter Reload Register */ + __IO uint32_t REPR; /*!< 0x08C Repetition Register */ + __IO uint32_t CH0CCR; /*!< 0x090 Channel 0 Capture/Compare Register */ + __IO uint32_t CH1CCR; /*!< 0x094 Channel 1 Capture/Compare Register */ + __IO uint32_t CH2CCR; /*!< 0x098 Channel 2 Capture/Compare Register */ + __IO uint32_t CH3CCR; /*!< 0x09C Channel 3 Capture/Compare Register */ + __IO uint32_t CH0ACR; /*!< 0x0A0 Channel 0 Asymmetric Compare Register */ + __IO uint32_t CH1ACR; /*!< 0x0A4 Channel 1 Asymmetric Compare Register */ + __IO uint32_t CH2ACR; /*!< 0x0A8 Channel 2 Asymmetric Compare Register */ + __IO uint32_t CH3ACR; /*!< 0x0AC Channel 3 Asymmetric Compare Register */ + #if defined(USE_HT32F50343) + uint32_t RESERVED4[20]; /*!< 0x0B0 - 0x0FC Reserved */ + __IO uint32_t CH4OCFR; /*!< 0x100 Channel-4 Output Configuration Register */ + __IO uint32_t CH5OCFR; /*!< 0x104 Channel-5 Output Configuration Register */ + __IO uint32_t CH6OCFR; /*!< 0x108 Channel-6 Output Configuration Register */ + __IO uint32_t CH7OCFR; /*!< 0x10C Channel-7 Output Configuration Register */ + __IO uint32_t CH4CR; /*!< 0x110 Channel 4 Compare Register */ + __IO uint32_t CH5CR; /*!< 0x114 Channel 5 Compare Register */ + __IO uint32_t CH6CR; /*!< 0x118 Channel 6 Compare Register */ + __IO uint32_t CH7CR; /*!< 0x11C Channel 7 Compare Register */ + #endif +} HT_TM_TypeDef; + + +/** + * @brief Peripheral Direct Memory Access Channel + */ +typedef struct +{ + __IO uint32_t CR; /*!< 0x000 PDMA Channel Control Register */ + __IO uint32_t SADR; /*!< 0x004 PDMA Channel Source Address Register */ + __IO uint32_t DADR; /*!< 0x008 PDMA Channel Destination Address Register */ + uint32_t RESERVED0[1]; /*!< 0x00C Reserved */ + __IO uint32_t TSR; /*!< 0x010 PDMA Channel Transfer Size Register */ + __IO uint32_t CTSR; /*!< 0x014 PDMA Channel Current Transfer Size Register */ +} HT_PDMACH_TypeDef; + + +/** + * @brief Peripheral Direct Memory Access Global + */ +typedef struct +{ + /* PDMA: 0x40090000 */ + HT_PDMACH_TypeDef PDMACH0; /*!< 0x000 PDMA channel 0 registers */ + HT_PDMACH_TypeDef PDMACH1; /*!< 0x018 PDMA channel 1 registers */ + HT_PDMACH_TypeDef PDMACH2; /*!< 0x030 PDMA channel 2 registers */ + HT_PDMACH_TypeDef PDMACH3; /*!< 0x048 PDMA channel 3 registers */ + HT_PDMACH_TypeDef PDMACH4; /*!< 0x060 PDMA channel 4 registers */ + HT_PDMACH_TypeDef PDMACH5; /*!< 0x078 PDMA channel 5 registers */ + uint32_t RESERVED0[36];/*!< 0x090 - 0x11C Reserved */ + __IO uint32_t ISR; /*!< 0x120 PDMA Interrupt Status Register */ + uint32_t RESERVED1[1]; /*!< 0x124 Reserved */ + __IO uint32_t ISCR; /*!< 0x128 PDMA Interrupt Status Clear Register */ + uint32_t RESERVED2[1]; /*!< 0x12C Reserved */ + __IO uint32_t IER; /*!< 0x130 PDMA Interrupt Enable Register */ +} HT_PDMA_TypeDef; + + +/** + * @brief Universal Serial Bus Global + */ +typedef struct +{ + /* USB: 0x400A8000 */ + __IO uint32_t CSR; /*!< 0x000 USB Control and Status Register */ + __IO uint32_t IER; /*!< 0x004 USB Interrupt Enable Register */ + __IO uint32_t ISR; /*!< 0x008 USB Interrupt Status Register */ + __IO uint32_t FCR; /*!< 0x00C USB Frame Count Register */ + __IO uint32_t DEVAR; /*!< 0x010 USB Device Address Register */ + __IO uint32_t EP0CSR; /*!< 0x014 USB Endpoint 0 Control and Status Register */ + __IO uint32_t EP0IER; /*!< 0x018 USB Endpoint 0 Interrupt Enable Register */ + __IO uint32_t EP0ISR; /*!< 0x01C USB Endpoint 0 Interrupt Status Register */ + __IO uint32_t EP0TCR; /*!< 0x020 USB Endpoint 0 Transfer Count Register */ + __IO uint32_t EP0CFGR; /*!< 0x024 USB Endpoint 0 Configuration Register */ + __IO uint32_t EP1CSR; /*!< 0x028 USB Endpoint 1 Control and Status Register */ + __IO uint32_t EP1IER; /*!< 0x02C USB Endpoint 1 Interrupt Enable Register */ + __IO uint32_t EP1ISR; /*!< 0x030 USB Endpoint 1 Interrupt Status Register */ + __IO uint32_t EP1TCR; /*!< 0x034 USB Endpoint 1 Transfer Count Register */ + __IO uint32_t EP1CFGR; /*!< 0x038 USB Endpoint 1 Configuration Register */ + __IO uint32_t EP2CSR; /*!< 0x03C USB Endpoint 2 Control and Status Register */ + __IO uint32_t EP2IER; /*!< 0x040 USB Endpoint 2 Interrupt Enable Register */ + __IO uint32_t EP2ISR; /*!< 0x044 USB Endpoint 2 Interrupt Status Register */ + __IO uint32_t EP2TCR; /*!< 0x048 USB Endpoint 2 Transfer Count Register */ + __IO uint32_t EP2CFGR; /*!< 0x04C USB Endpoint 2 Configuration Register */ + __IO uint32_t EP3CSR; /*!< 0x050 USB Endpoint 3 Control and Status Register */ + __IO uint32_t EP3IER; /*!< 0x054 USB Endpoint 3 Interrupt Enable Register */ + __IO uint32_t EP3ISR; /*!< 0x058 USB Endpoint 3 Interrupt Status Register */ + __IO uint32_t EP3TCR; /*!< 0x05C USB Endpoint 3 Transfer Count Register */ + __IO uint32_t EP3CFGR; /*!< 0x060 USB Endpoint 3 Configuration Register */ + __IO uint32_t EP4CSR; /*!< 0x064 USB Endpoint 4 Control and Status Register */ + __IO uint32_t EP4IER; /*!< 0x068 USB Endpoint 4 Interrupt Enable Register */ + __IO uint32_t EP4ISR; /*!< 0x06C USB Endpoint 4 Interrupt Status Register */ + __IO uint32_t EP4TCR; /*!< 0x070 USB Endpoint 4 Transfer Count Register */ + __IO uint32_t EP4CFGR; /*!< 0x074 USB Endpoint 4 Configuration Register */ + __IO uint32_t EP5CSR; /*!< 0x078 USB Endpoint 5 Control and Status Register */ + __IO uint32_t EP5IER; /*!< 0x07C USB Endpoint 5 Interrupt Enable Register */ + __IO uint32_t EP5ISR; /*!< 0x080 USB Endpoint 5 Interrupt Status Register */ + __IO uint32_t EP5TCR; /*!< 0x084 USB Endpoint 5 Transfer Count Register */ + __IO uint32_t EP5CFGR; /*!< 0x088 USB Endpoint 5 Configuration Register */ + __IO uint32_t EP6CSR; /*!< 0x08C USB Endpoint 6 Control and Status Register */ + __IO uint32_t EP6IER; /*!< 0x090 USB Endpoint 6 Interrupt Enable Register */ + __IO uint32_t EP6ISR; /*!< 0x094 USB Endpoint 6 Interrupt Status Register */ + __IO uint32_t EP6TCR; /*!< 0x098 USB Endpoint 6 Transfer Count Register */ + __IO uint32_t EP6CFGR; /*!< 0x09C USB Endpoint 6 Configuration Register */ + __IO uint32_t EP7CSR; /*!< 0x0A0 USB Endpoint 7 Control and Status Register */ + __IO uint32_t EP7IER; /*!< 0x0A4 USB Endpoint 7 Interrupt Enable Register */ + __IO uint32_t EP7ISR; /*!< 0x0A8 USB Endpoint 7 Interrupt Status Register */ + __IO uint32_t EP7TCR; /*!< 0x0AC USB Endpoint 7 Transfer Count Register */ + __IO uint32_t EP7CFGR; /*!< 0x0B0 USB Endpoint 7 Configuration Register */ + #if defined(USE_HT32F61141) + __IO uint32_t EP8CSR; /*!< 0x0B4 USB Endpoint 8 Control and Status Register */ + __IO uint32_t EP8IER; /*!< 0x0B8 USB Endpoint 8 Interrupt Enable Register */ + __IO uint32_t EP8ISR; /*!< 0x0BC USB Endpoint 8 Interrupt Status Register */ + __IO uint32_t EP8TCR; /*!< 0x0C0 USB Endpoint 8 Transfer Count Register */ + __IO uint32_t EP8CFGR; /*!< 0x0C4 USB Endpoint 8 Configuration Register */ + __IO uint32_t EP9CSR; /*!< 0x0C8 USB Endpoint 9 Control and Status Register */ + __IO uint32_t EP9IER; /*!< 0x0CC USB Endpoint 9 Interrupt Enable Register */ + __IO uint32_t EP9ISR; /*!< 0x0D0 USB Endpoint 9 Interrupt Status Register */ + __IO uint32_t EP9TCR; /*!< 0x0D4 USB Endpoint 9 Transfer Count Register */ + __IO uint32_t EP9CFGR; /*!< 0x0D8 USB Endpoint 9 Configuration Register */ + #endif +} HT_USB_TypeDef; + + +/** + * @brief Universal Serial Bus Endpoint + */ +typedef struct +{ + /* USB Endpoint0: 0x400A8014 */ + /* USB Endpoint1: 0x400A8028 */ + /* USB Endpoint2: 0x400A803C */ + /* USB Endpoint3: 0x400A8050 */ + /* USB Endpoint4: 0x400A8064 */ + /* USB Endpoint5: 0x400A8078 */ + /* USB Endpoint6: 0x400A808C */ + /* USB Endpoint7: 0x400A80A0 */ + /* USB Endpoint8: 0x400A80B4 */ + /* USB Endpoint9: 0x400A80C8 */ + __IO uint32_t CSR; /*!< 0x000 USB Endpoint n Control and Status Register */ + __IO uint32_t IER; /*!< 0x004 USB Endpoint n Interrupt Enable Register */ + __IO uint32_t ISR; /*!< 0x008 USB Endpoint n Interrupt Status Register */ + __IO uint32_t TCR; /*!< 0x00C USB Endpoint n Transfer Count Register */ + __IO uint32_t CFGR; /*!< 0x010 USB Endpoint n Configuration Register */ +} HT_USBEP_TypeDef; + + +/** + * @brief External Bus Interface + */ +typedef struct +{ + /* EBI: 0x40098000 */ + __IO uint32_t CR; /*!< 0x000 EBI Control Register */ + uint32_t RESERVED0[1]; /*!< 0x004 Reserved */ + __IO uint32_t SR; /*!< 0x008 EBI Status Register */ + uint32_t RESERVED1[1]; /*!< 0x00C Reserved */ + __IO uint32_t ATR; /*!< 0x010 EBI Address Timing Register */ + __IO uint32_t RTR; /*!< 0x014 EBI Read Timing Register */ + __IO uint32_t WTR; /*!< 0x018 EBI Write Timing Register */ + __IO uint32_t PR; /*!< 0x01C EBI Parity Register */ +} HT_EBI_TypeDef; + + +/** + * @brief Cyclic Redundancy Check + */ +typedef struct +{ + /* CRC: 0x4008A000 */ + __IO uint32_t CR; /*!< 0x000 CRC Control Register */ + __IO uint32_t SDR; /*!< 0x004 CRC Seed Register */ + __IO uint32_t CSR; /*!< 0x008 CRC Checksum Register */ + __IO uint32_t DR; /*!< 0x00C CRC Data Register */ +} HT_CRC_TypeDef; + + +/** + * @brief Integrated Interchip Sound + */ +typedef struct +{ + /* I2S: 0x40026000 */ + __IO uint32_t CR; /*!< 0x000 I2S Control Register */ + __IO uint32_t IER; /*!< 0x004 I2S Interrupt Enable Register */ + __IO uint32_t CDR; /*!< 0x008 I2S Clock Divider Register */ + __IO uint32_t TXDR; /*!< 0x00C I2S TX Data Register */ + __IO uint32_t RXDR; /*!< 0x010 I2S RX Data Register */ + __IO uint32_t FCR; /*!< 0x014 I2S FIFO Control Register */ + __IO uint32_t SR; /*!< 0x018 I2S Status Register */ + __IO uint32_t RCNTR; /*!< 0x01C I2S Rate Counter Register */ +} HT_I2S_TypeDef; + + +/** + * @brief PWM Timer + */ +typedef struct +{ + /* PWM0: 0x40031000 */ + /* PWM2: 0x40032000 */ + /* PWM1: 0x40071000 */ + __IO uint32_t CNTCFR; /*!< 0x000 Counter Configuration Register */ + __IO uint32_t MDCFR; /*!< 0x004 Mode Configuration Register */ + __IO uint32_t TRCFR; /*!< 0x008 Trigger Configuration Register */ + uint32_t RESERVED0[1]; /*!< 0x00C Reserved */ + __IO uint32_t CTR; /*!< 0x010 Control Register */ + uint32_t RESERVED1[11]; /*!< 0x014 - 0x03C Reserved */ + __IO uint32_t CH0OCFR; /*!< 0x040 Channel-0 Output Configuration Register */ + __IO uint32_t CH1OCFR; /*!< 0x044 Channel-1 Output Configuration Register */ + __IO uint32_t CH2OCFR; /*!< 0x048 Channel-2 Output Configuration Register */ + __IO uint32_t CH3OCFR; /*!< 0x04C Channel-3 Output Configuration Register */ + __IO uint32_t CHCTR; /*!< 0x050 Channel Control Register */ + __IO uint32_t CHPOLR; /*!< 0x054 Channel Polarity Configuration Register */ + uint32_t RESERVED2[7]; /*!< 0x058 - 0x070 Reserved */ + __IO uint32_t DICTR; /*!< 0x074 DMA / Interrupt Control Register */ + __IO uint32_t EVGR; /*!< 0x078 Event Generator Register */ + __IO uint32_t INTSR; /*!< 0x07C Interrupt Status Register */ + __IO uint32_t CNTR; /*!< 0x080 Counter Register */ + __IO uint32_t PSCR; /*!< 0x084 Prescaler Register */ + __IO uint32_t CRR; /*!< 0x088 Counter Reload Register */ + uint32_t RESERVED3[1]; /*!< 0x08C Reserved */ + __IO uint32_t CH0CR; /*!< 0x090 Channel 0 Compare Register */ + __IO uint32_t CH1CR; /*!< 0x094 Channel 1 Compare Register */ + __IO uint32_t CH2CR; /*!< 0x098 Channel 2 Compare Register */ + __IO uint32_t CH3CR; /*!< 0x09C Channel 3 Compare Register */ + __IO uint32_t CH0ACR; /*!< 0x0A0 Channel 0 Asymmetric Compare Register */ + __IO uint32_t CH1ACR; /*!< 0x0A4 Channel 1 Asymmetric Compare Register */ + __IO uint32_t CH2ACR; /*!< 0x0A8 Channel 2 Asymmetric Compare Register */ + __IO uint32_t CH3ACR; /*!< 0x0AC Channel 3 Asymmetric Compare Register */ + #if defined(USE_HT32F50343) + uint32_t RESERVED4[20]; /*!< 0x0B0 - 0x0FC Reserved */ + __IO uint32_t CH4OCFR; /*!< 0x100 Channel-4 Output Configuration Register */ + __IO uint32_t CH5OCFR; /*!< 0x104 Channel-5 Output Configuration Register */ + __IO uint32_t CH6OCFR; /*!< 0x108 Channel-6 Output Configuration Register */ + __IO uint32_t CH7OCFR; /*!< 0x10C Channel-7 Output Configuration Register */ + __IO uint32_t CH4CR; /*!< 0x110 Channel 4 Compare Register */ + __IO uint32_t CH5CR; /*!< 0x114 Channel 5 Compare Register */ + __IO uint32_t CH6CR; /*!< 0x118 Channel 6 Compare Register */ + __IO uint32_t CH7CR; /*!< 0x11C Channel 7 Compare Register */ + #endif +} HT_PWM_TypeDef; + + +/** + * @brief Single Channel Timer + */ +typedef struct +{ + /* SCTM0: 0x40034000 */ + /* SCTM1: 0x40074000 */ + /* SCTM2: 0x40035000 */ + /* SCTM3: 0x40075000 */ + __IO uint32_t CNTCFR; /*!< 0x000 Counter Configuration Register */ + __IO uint32_t MDCFR; /*!< 0x004 Mode Configuration Register */ + __IO uint32_t TRCFR; /*!< 0x008 Trigger Configuration Register */ + uint32_t RESERVED0[1]; /*!< 0x00C Reserved */ + __IO uint32_t CTR; /*!< 0x010 Control Register */ + uint32_t RESERVED1[3]; /*!< 0x014 - 0x01C Reserved */ + __IO uint32_t CH0ICFR; /*!< 0x020 Channel 0 Input Configuration Register */ + #if defined(USE_HT32F65230_40) || defined(USE_HT32F65232) || defined(USE_HT32F66242) || defined(USE_HT32F66246) + __IO uint32_t CH1ICFR; /*!< 0x024 Channel 1 Input Configuration Register */ + uint32_t RESERVED2[6]; /*!< 0x028 - 0x03C Reserved */ + #else + uint32_t RESERVED2[7]; /*!< 0x024 - 0x03C Reserved */ + #endif + __IO uint32_t CHOCFR; /*!< 0x040 Channel Output Configuration Register */ + #if defined(USE_HT32F50020_30) + __IO uint32_t CH1OCFR; /*!< 0x044 Channel 1 Output Configuration Register */ + uint32_t RESERVED3[2]; /*!< 0x048 - 0x04C Reserved */ + #else + uint32_t RESERVED3[3]; /*!< 0x044 - 0x04C Reserved */ + #endif + __IO uint32_t CHCTR; /*!< 0x050 Channel Control Register */ + __IO uint32_t CHPOLR; /*!< 0x054 Channel Polarity Configuration Register */ + uint32_t RESERVED4[7]; /*!< 0x058 - 0x070 Reserved */ + __IO uint32_t DICTR; /*!< 0x074 Interrupt Control Register */ + __IO uint32_t EVGR; /*!< 0x078 Event Generator Register */ + __IO uint32_t INTSR; /*!< 0x07C Interrupt Status Register */ + __IO uint32_t CNTR; /*!< 0x080 Counter Register */ + __IO uint32_t PSCR; /*!< 0x084 Prescaler Register */ + __IO uint32_t CRR; /*!< 0x088 Counter Reload Register */ + uint32_t RESERVED5[1]; /*!< 0x08C Reserved */ + __IO uint32_t CH0CCR; /*!< 0x090 Channel 0 Capture/Compare Register */ + #if defined(USE_HT32F65230_40) || defined(USE_HT32F65232) || defined(USE_HT32F50020_30) || defined(USE_HT32F66242) || defined(USE_HT32F66246) + __IO uint32_t CH1CCR; /*!< 0x094 Channel 1 Capture Register */ + #endif +} HT_SCTM_TypeDef; + + +/** + * @brief Divider + */ +typedef struct +{ + /* DIV: 0x400CA000 */ + __IO uint32_t CR; /*!< 0x000 Control Register */ + __IO uint32_t DDR; /*!< 0x004 Dividend register */ + __IO uint32_t DSR; /*!< 0x008 Divisor Register */ + __IO uint32_t QTR; /*!< 0x00C Quotient Register */ + __IO uint32_t RMR; /*!< 0x010 Remainder Register */ +} HT_DIV_TypeDef; + + +/** + * @brief Advanced Encryption Standard + */ +typedef struct +{ + /* AES: 0x400C8000 */ + __IO uint32_t CR; /*!< 0x000 Control Register */ + __IO uint32_t SR; /*!< 0x004 Status Register */ + __IO uint32_t PDMAR; /*!< 0x008 PDMA Register */ + __IO uint32_t ISR; /*!< 0x00C Interrupt Status Register */ + __IO uint32_t IER; /*!< 0x010 Interrupt Enable Register */ + __IO uint32_t DINR; /*!< 0x014 Data Input Register */ + __IO uint32_t DOUTR; /*!< 0x018 Data Output Register */ + #if defined(USE_HT32F52357_67) + __IO uint32_t KEYR[8]; /*!< 0x01C - 0x038 Key Register 0~7 */ + #else + __IO uint32_t KEYR[4]; /*!< 0x01C - 0x028 Key Register 0~3 */ + uint32_t RESERVED0[4]; /*!< 0x02C - 0x038 Reserved */ + #endif + __IO uint32_t IVR[4]; /*!< 0x03C - 0x048 Initial Vector Register 0~3 */ +} HT_AES_TypeDef; + + +/** + * @brief MIDI + */ +typedef struct +{ + /* MIDI: 0x40060000 */ + __IO uint32_t CHAN; /*!< 0x000 MIDI Channel Number Select */ + __IO uint32_t FREQ; /*!< 0x004 MIDI Frequency Number */ + __IO uint32_t VOL; /*!< 0x008 MIDI Volume Control */ + __IO uint32_t ST_ADDR; /*!< 0x00C MIDI Start Address */ + __IO uint32_t RE_NUM; /*!< 0x010 MIDI Repeat Number */ + __IO uint32_t END_ADDR; /*!< 0x014 MIDI End Address */ + __IO uint32_t IER; /*!< 0x018 MIDI Interrupt/DMA Enable Register */ + __IO uint32_t SR; /*!< 0x01C MIDI Status Register */ + __IO uint32_t MCU_CH0; /*!< 0x020 MIDI MCU Channel 0 data */ + __IO uint32_t MCU_CH1; /*!< 0x024 MIDI MCU Channel 1 data */ + __IO uint32_t MCU_CH2; /*!< 0x028 MIDI MCU Channel 2 data */ + __IO uint32_t MCU_CH3; /*!< 0x02C MIDI MCU Channel 3 data */ + __IO uint32_t MIDIL; /*!< 0x030 MIDI Engine Waveform of Left Channel */ + __IO uint32_t MIDIR; /*!< 0x034 MIDI Engine Waveform of Right Channel */ + __IO uint32_t SPI_DATA; /*!< 0x038 MIDI SPI Flash data read */ + __IO uint32_t SPI_ADDR; /*!< 0x03C MIDI SPI Flash address read */ + __IO uint32_t CTRL; /*!< 0x040 MIDI Control Register */ +} HT_MIDI_TypeDef; + + +/** + * @brief LCD + */ +typedef struct +{ + /* LCD: 0x4001A000 */ + __IO uint32_t CR; /*!< 0x000 Control Register */ + __IO uint32_t FCR; /*!< 0x004 Frame Control Register */ + __IO uint32_t IER; /*!< 0x008 Interrupt Enable Register */ + __IO uint32_t SR; /*!< 0x00C Status Register */ + __IO uint32_t CLR; /*!< 0x010 Clear Register */ + uint32_t RESERVED[3]; /*!< 0x014 - 0x020 Reserved */ + __IO uint32_t RAM[16]; /*!< 0x020 - 0x05C Display Memory */ +} HT_LCD_TypeDef; + + +/** + * @brief Serial SLED Interface + */ +typedef struct +{ + /* SLED0: 0x4000E000 */ + /* SLED1: 0x4004E000 */ + __IO uint32_t CR; /*!< 0x000 Control Register */ + __IO uint32_t SR; /*!< 0x004 Status Register */ + __IO uint32_t CDR; /*!< 0x008 Clock Divider Register */ + __IO uint32_t TCR; /*!< 0x00C Timne Code Register */ + union { + __IO uint8_t DR_8BIT; /*!< 0x010 Data Register, 8-bit access, duplicate 4 times into 32-bit */ + __IO uint16_t DR_16BIT; /*!< 0x010 Data Register, 16-bit access, duplicate 2 times into 32-bit */ + __IO uint32_t DR_32BIT; /*!< 0x010 Data Register */ + }; + __IO uint32_t FCR; /*!< 0x014 FIFO Control Register */ +} HT_SLED_TypeDef; + + +/** + * @brief Touch Key Module + */ +typedef struct +{ + __IO uint32_t CR; /*!< 0x000 Touch Key Module Control Register */ + __IO uint32_t KCFGR; /*!< 0x004 Touch Key Module Key Configuration Register */ + __IO uint32_t SR; /*!< 0x008 Touch Key Module Status Register */ + __IO uint32_t ROCPR; /*!< 0x00C Touch Key Module Reference OSC Capacitor Register */ + __IO uint32_t K3CPR; /*!< 0x010 Touch Key Module Key 3 Capacitor Register */ + __IO uint32_t K2CPR; /*!< 0x014 Touch Key Module Key 2 Capacitor Register */ + __IO uint32_t K1CPR; /*!< 0x018 Touch Key Module Key 1 Capacitor Register */ + __IO uint32_t K0CPR; /*!< 0x01C Touch Key Module Key 0 Capacitor Register */ + __IO uint32_t CFCNTR; /*!< 0x020 Touch Key Module C/F Counter Register */ + __IO uint32_t K3CNTR; /*!< 0x024 Touch Key Module Key 3 Counter Register */ + __IO uint32_t K2CNTR; /*!< 0x028 Touch Key Module Key 2 Counter Register */ + __IO uint32_t K1CNTR; /*!< 0x02C Touch Key Module Key 1 Counter Register */ + __IO uint32_t K0CNTR; /*!< 0x030 Touch Key Module Key 0 Counter Register */ + __IO uint32_t K3THR; /*!< 0x034 Touch Key Module Key 3 Threshold Register */ + __IO uint32_t K2THR; /*!< 0x038 Touch Key Module Key 2 Threshold Register */ + __IO uint32_t K1THR; /*!< 0x03C Touch Key Module Key 1 Threshold Register */ + __IO uint32_t K0THR; /*!< 0x040 Touch Key Module Key 0 Threshold Register */ + uint32_t RESERVED0[47]; /*!< 0x044 - 0x0FC Reserved */ +} HT_TKM_TypeDef; + + +/** + * @brief Touch Key + */ +typedef struct +{ + /* TKEY: 0x4001A000 */ + __IO uint32_t TKCR; /*!< 0x000 Touch Key Control Register */ + __IO uint32_t TKCNTR; /*!< 0x004 Touch Key Counter Register */ + __IO uint32_t TKTSCRR; /*!< 0x008 Touch Key Time Slot Counter Reload Register */ + __IO uint32_t TKIER; /*!< 0x00C Touch Key Interrupt Enable Register */ + __IO uint32_t TKSR; /*!< 0x010 Touch Key Status Register */ + uint32_t RESERVED0[59]; /*!< 0x014 - 0x0FC Reserved */ + HT_TKM_TypeDef TKM0; /*!< 0x100 Touch Key Module 0 registers */ + HT_TKM_TypeDef TKM1; /*!< 0x200 Touch Key Module 1 registers */ + HT_TKM_TypeDef TKM2; /*!< 0x300 Touch Key Module 2 registers */ + HT_TKM_TypeDef TKM3; /*!< 0x400 Touch Key Module 3 registers */ + HT_TKM_TypeDef TKM4; /*!< 0x500 Touch Key Module 4 registers */ + HT_TKM_TypeDef TKM5; /*!< 0x600 Touch Key Module 5 registers */ +} HT_TKEY_TypeDef; + + +/** + * @brief LED Controller + */ +typedef struct +{ + /* LEDC: 0x4005A000 */ + __IO uint32_t CR; /*!< 0x000 LED Control Register */ + __IO uint32_t CER; /*!< 0x004 LED COM Enable Register */ + __IO uint32_t PCR; /*!< 0x008 LED Polarity Control Register */ + __IO uint32_t IER; /*!< 0x00C LED Interrupt Enable Register */ + __IO uint32_t SR; /*!< 0x010 LED Status Register */ + __IO uint32_t DTCR; /*!< 0x014 LED Dead Time Control Register */ + #if defined(USE_HT32F54231_41) || defined(USE_HT32F50020_30) || defined(USE_HT32F53231_41) || defined(USE_HT32F53242_52) || defined(USE_HT32F50431_41) || defined(USE_HT32F50442_52) + __IO uint32_t DR[8]; /*!< 0x018 - 0x034 LED Data Register */ + #endif + #if defined(USE_HT32F54243_53) + __IO uint32_t DR[12]; /*!< 0x018 - 0x044 LED Data Register */ + #endif +} HT_LEDC_TypeDef; + + +/** + * @brief Controller Area Network Interface + */ +typedef struct +{ + __IO uint32_t CREQ; /*!< 0x000 CAN Interface Command Request Register */ + __IO uint32_t CMASK; /*!< 0x004 CAN Interface Command Mask Register */ + __IO uint32_t MASK0; /*!< 0x008 CAN Interface Mask Register 0 */ + __IO uint32_t MASK1; /*!< 0x00C CAN Interface Mask Register 1 */ + __IO uint32_t ARB0; /*!< 0x010 CAN Interface Arbitration Register 0 */ + __IO uint32_t ARB1; /*!< 0x014 CAN Interface Arbitration Register 1 */ + __IO uint32_t MCR; /*!< 0x018 CAN Interface Message Control Register */ + __IO uint32_t DA0R; /*!< 0x01C CAN Interface Data A 0 Register */ + __IO uint32_t DA1R; /*!< 0x020 CAN Interface Data A 1 Register */ + __IO uint32_t DB0R; /*!< 0x024 CAN Interface Data B 0 Register */ + __IO uint32_t DB1R; /*!< 0x028 CAN Interface Data B 1 Register */ +} HT_CANIF_TypeDef; + +/** + * @brief Controller Area Network Global + */ +typedef struct +{ + /* CAN: 0x4000C000 */ + __IO uint32_t CR; /*!< 0x000 Control Register */ + __IO uint32_t SR; /*!< 0x004 Status Register */ + __IO uint32_t ECR; /*!< 0x008 Error Counter Register */ + __IO uint32_t BTR; /*!< 0x00C Bit Timing Register */ + __IO uint32_t IR; /*!< 0x010 Interrupt Register */ + __IO uint32_t TR; /*!< 0x014 Test Register */ + __IO uint32_t BRPER; /*!< 0x018 BRP Extension Register */ + uint32_t RESERVED0[1]; /*!< 0x01C Reserved */ + HT_CANIF_TypeDef IF0; /*!< 0x020 - 0x048 CAN Interface 0 registers */ + uint32_t RESERVED1[13];/*!< 0x04C - 0x07C Reserved */ + HT_CANIF_TypeDef IF1; /*!< 0x080 - 0x0A8 CAN Interface 1 registers */ + uint32_t RESERVED2[21];/*!< 0x0AC - 0x0FC Reserved */ + __IO uint32_t TRR0; /*!< 0x100 Transmission Request Register 0 */ + __IO uint32_t TRR1; /*!< 0x104 Transmission Request Register 1 */ + uint32_t RESERVED3[6]; /*!< 0x108 - 0x11C Reserved */ + __IO uint32_t NDR0; /*!< 0x120 New Data Register 0 */ + __IO uint32_t NDR1; /*!< 0x124 New Data Register 1 */ + uint32_t RESERVED4[6]; /*!< 0x128 - 0x13C Reserved */ + __IO uint32_t IPR0; /*!< 0x140 Interrupt Pending Register 0 */ + __IO uint32_t IPR1; /*!< 0x144 Interrupt Pending Register 1 */ + uint32_t RESERVED5[6]; /*!< 0x148 - 0x15C Reserved */ + __IO uint32_t MVR0; /*!< 0x160 Message Valid Register 0 */ + __IO uint32_t MVR1; /*!< 0x164 Message Valid Register 1 */ +} HT_CAN_TypeDef; + +/** + * @brief Coordinate Rotation Digital Computer + */ +typedef struct +{ + /* CORDIC: 0x400DC000 */ + __IO uint32_t CSR; /*!< 0x000 Control/Satus Register */ + __IO uint32_t WDATA; /*!< 0x004 Argument Register */ + __IO uint32_t RDATA; /*!< 0x008 Result Register */ +} HT_CORDIC_TypeDef; + +/** + * @brief Proportional Integral Derivative controller + */ +typedef struct +{ + /* PID: 0x400EC000 */ + __IO uint32_t CR0; /*!< 0x000 Control Register 0 */ + __IO uint32_t UI_INPUT; /*!< 0x004 */ + __IO uint32_t ERR_n; /*!< 0x008 */ + __IO uint32_t PID_OUT; /*!< 0x00C */ + __IO uint32_t SPD1ERR1; /*!< 0x010 */ + __IO uint32_t SPD1KP; /*!< 0x014 */ + __IO uint32_t SPD1KI; /*!< 0x018 */ + __IO uint32_t SPD1KD; /*!< 0x01C */ + __IO uint32_t SPD1UI1; /*!< 0x020 */ + __IO uint32_t SPD1UI_MAX; /*!< 0x024 */ + __IO uint32_t SPD1UI_MIN; /*!< 0x028 */ + __IO uint32_t SPD1_PIDOUT_LIM; /*!< 0x02C */ + __IO uint32_t IQ1ERR1; /*!< 0x030 */ + __IO uint32_t IQ1KP; /*!< 0x034 */ + __IO uint32_t IQ1KI; /*!< 0x038 */ + __IO uint32_t IQ1KD; /*!< 0x03C */ + __IO uint32_t IQ1UI1; /*!< 0x040 */ + __IO uint32_t IQ1UI_MAX; /*!< 0x044 */ + __IO uint32_t IQ1UI_MIN; /*!< 0x048 */ + __IO uint32_t IQ1_PIDOUT_LIM; /*!< 0x04C */ + __IO uint32_t ID1ERR1; /*!< 0x050 */ + __IO uint32_t ID1KP; /*!< 0x054 */ + __IO uint32_t ID1KI; /*!< 0x058 */ + __IO uint32_t ID1KD; /*!< 0x05C */ + __IO uint32_t ID1UI1; /*!< 0x060 */ + __IO uint32_t ID1UI_MAX; /*!< 0x064 */ + __IO uint32_t ID1UI_MIN; /*!< 0x068 */ + __IO uint32_t ID1_PIDOUT_LIM; /*!< 0x06C */ + __IO uint32_t FWNK1ERR1; /*!< 0x070 */ + __IO uint32_t FWNK1KP; /*!< 0x074 */ + __IO uint32_t FWNK1KI; /*!< 0x078 */ + __IO uint32_t FWNK1KD; /*!< 0x07C */ + __IO uint32_t FWNK1UI1; /*!< 0x080 */ + __IO uint32_t FWNK1UI_MAX; /*!< 0x084 */ + __IO uint32_t FWNK1UI_MIN; /*!< 0x088 */ + __IO uint32_t FWNK1_PIDOUT_LIM;/*!< 0x08C */ + __IO uint32_t PLL1ERR1; /*!< 0x090 */ + __IO uint32_t PLL1KP; /*!< 0x094 */ + __IO uint32_t PLL1KI; /*!< 0x098 */ + __IO uint32_t PLL1KD; /*!< 0x09C */ + __IO uint32_t PLL1UI1; /*!< 0x0A0 */ + __IO uint32_t PLL1UI_MAX; /*!< 0x0A4 */ + __IO uint32_t PLL1UI_MIN; /*!< 0x0A8 */ + __IO uint32_t PLL1_PIDOUT_LIM; /*!< 0x0AC */ + __IO uint32_t USR1ERR1; /*!< 0x0B0 */ + __IO uint32_t USR1KP; /*!< 0x0B4 */ + __IO uint32_t USR1KI; /*!< 0x0B8 */ + __IO uint32_t USR1KD; /*!< 0x0BC */ + __IO uint32_t USR1UI1; /*!< 0x0C0 */ + __IO uint32_t USR1UI_MAX; /*!< 0x0C4 */ + __IO uint32_t USR1UI_MIN; /*!< 0x0C8 */ + __IO uint32_t USR1_PIDOUT_LIM; /*!< 0x0CC */ +} HT_PID_TypeDef; +/** + * @} + */ + +/** + * @brief RF + */ +typedef struct +{ + /* RF: 0x400D0000 */ + __IO uint8_t TRXADR0; /*!< 0x000 TX/RX ADDRESS 5BYTES(LSB) */ + __IO uint8_t TRXADR1; /*!< 0x001 TX/RX ADDRESS 5BYTES */ + __IO uint8_t TRXADR2; /*!< 0x002 TX/RX ADDRESS 5BYTES */ + __IO uint8_t TRXADR3; /*!< 0x003 TX/RX ADDRESS 5BYTES */ + __IO uint8_t TRXADR4; /*!< 0x004 TX/RX ADDRESS 5BYTES(MSB) */ + __IO uint8_t RXP1ADR0; /*!< 0x005 RX PIPE1 ADDRESS 5BYTES(LSB) */ + __IO uint8_t RXP1ADR1; /*!< 0x006 RX PIPE1 ADDRESS 5BYTES */ + __IO uint8_t RXP1ADR2; /*!< 0x007 RX PIPE1 ADDRESS 5BYTES */ + __IO uint8_t RXP1ADR3; /*!< 0x008 RX PIPE1 ADDRESS 5BYTES */ + __IO uint8_t RXP1ADR4; /*!< 0x009 RX PIPE1 ADDRESS 5BYTES(MSB) */ + __IO uint8_t RXP2ADR0; /*!< 0x00A RX PIPE2 ADDRESS 5BYTES(LSB) */ + __IO uint8_t RXP3ADR0; /*!< 0x00B RX PIPE3 ADDRESS 5BYTES(LSB) */ + __IO uint8_t RXP4ADR0; /*!< 0x00C RX PIPE4 ADDRESS 5BYTES(LSB) */ + __IO uint8_t RXP5ADR0; /*!< 0x00D RX PIPE5 ADDRESS 5BYTES(LSB) */ + uint8_t RESERVED0[2]; /*!< 0x00E - 0x00F Reserved */ + __IO uint8_t TXFIFO; /*!< 0x010 TX FIFO WRITE ONLY */ + uint8_t RESERVED1[3]; /*!< 0x011 - 0x013 Reserved */ + __IO uint8_t RXFIFO; /*!< 0x014 RX FIFO READ ONLY */ + uint8_t RESERVED2[3]; /*!< 0x015 - 0x017 Reserved */ + __IO uint8_t FWREND; /*!< 0x018 FIFO Read/Write End */ + __IO uint8_t FLUSHFF; /*!< 0x019 FLUSH TX/RX FIFO */ + __IO uint8_t TXFFSEL; /*!< 0x01A Write TX FIFO Select ACK Payload or NACK Payload */ + __IO uint8_t PIPESEL; /*!< 0x01B Write TX FIFO for PIPE ACK Payload */ + __IO uint8_t RFC1; /*!< 0x01C RF Control Register 1 */ + __IO uint8_t RFC2; /*!< 0x01D RF Control Register 2 */ + __IO uint8_t RFC3; /*!< 0x01E RF Control Register 3 */ + uint8_t RESERVED3[1]; /*!< 0x01F Reserved */ + __IO uint8_t CFG1; /*!< 0x020 Configuration Control Register 1 */ + __IO uint8_t RC1; /*!< 0x021 Reset/Clock Control Register 1 */ + __IO uint8_t RC2; /*!< 0x022 Reset/Clock Control Register 2 */ + __IO uint8_t MASK; /*!< 0x023 Mask Control Register */ + __IO uint8_t IRQ1; /*!< 0x024 Interrupt Control Register 1 */ + __IO uint8_t STATUS; /*!< 0x025 FIFO Status Control Register */ + __IO uint8_t IO1; /*!< 0x026 IO Control Register 1 */ + __IO uint8_t IO2; /*!< 0x027 IO Control Register 2 */ + __IO uint8_t IO3; /*!< 0x028 IO Control Register 3 */ + __IO uint8_t PKT1; /*!< 0x029 Packet Control Register 1 */ + __IO uint8_t PKT2; /*!< 0x02A Packet Control Register 2 */ + __IO uint8_t PKT3; /*!< 0x02B Packet Control Register 3 */ + __IO uint8_t PKT4; /*!< 0x02C Packet Control Register 4 */ + __IO uint8_t PKT5; /*!< 0x02D Packet Control Register 5 */ + __IO uint8_t MOD1; /*!< 0x02E Modulator Control Register 1 */ + __IO uint8_t MOD2; /*!< 0x02F Modulator Control Register 2 */ + __IO uint8_t DM1; /*!< 0x030 De-modulator Control Register 1 */ + __IO uint8_t DM2; /*!< 0x031 De-modulator Control Register 2 */ + __IO uint8_t RT1; /*!< 0x032 PTX Retransmission Control Register 1 */ + __IO uint8_t RT2; /*!< 0x033 PTX Retransmission Control Register 2 */ + __IO uint8_t CE; /*!< 0x034 Chip Enable Control Register */ + __IO uint8_t CP21; /*!< 0x035 CP Control Register 21 */ + __IO uint8_t CP22; /*!< 0x036 CP Control Register 22 */ + __IO uint8_t CP31; /*!< 0x037 CP Control Register 31 */ + __IO uint8_t CP2R; /*!< 0x038 CP Control Register 2 for Read */ + __IO uint8_t CP3R; /*!< 0x039 CP Control Register 3 for Read */ + __IO uint8_t CP2RX; /*!< 0x03A CP Control Register 2 for RX */ + __IO uint8_t CP3RX; /*!< 0x03B CP Control Register 3 for RX */ + __IO uint8_t PDB; /*!< 0x03C RF Power Down Bar Enable Control Register */ + __IO uint8_t RF1; /*!< 0x03D RF RX control Register 1 */ + uint8_t RESERVED4[2]; /*!< 0x03E - 0x03F Reserved */ + __IO uint8_t OM; /*!< 0x040 Operation Mode Control Register */ + __IO uint8_t CFO1; /*!< 0x041 Carrier Frequency Offset Control Register 1 */ + __IO uint8_t SX1; /*!< 0x042 Fractional-N Synthesizer Control Register 1 */ + __IO uint8_t SX2; /*!< 0x043 Fractional-N Synthesizer Control Register 2 */ + __IO uint8_t SX3; /*!< 0x044 Fractional-N Synthesizer Control Register 3 */ + __IO uint8_t SX4; /*!< 0x045 Fractional-N Synthesizer Control Register 4 */ + __IO uint8_t STA1; /*!< 0x046 Status Control Register 1 */ + __IO uint8_t RSSI1; /*!< 0x047 RSSI Control Register 1 */ + __IO uint8_t RSSI2; /*!< 0x048 RSSI Control Register 2 */ + __IO uint8_t RSSI3; /*!< 0x049 RSSI Control Register 3 */ + __IO uint8_t DPL1; /*!< 0x04A Dynamic Payload Length Control Register 1 */ + __IO uint8_t DPL2; /*!< 0x04B Dynamic Payload Length Control Register 2 */ + __IO uint8_t RXPW0; /*!< 0x04C RX Payload Length Control Register 0 */ + __IO uint8_t RXPW1; /*!< 0x04D RX Payload Length Control Register 1 */ + __IO uint8_t RXPW2; /*!< 0x04E RX Payload Length Control Register 2 */ + __IO uint8_t RXPW3; /*!< 0x04F RX Payload Length Control Register 3 */ + __IO uint8_t RXPW4; /*!< 0x050 RX Payload Length Control Register 4 */ + __IO uint8_t RXPW5; /*!< 0x051 RX Payload Length Control Register 5 */ + __IO uint8_t ENAA; /*!< 0x052 Enable Auto-ACK Control Register */ + __IO uint8_t PEN; /*!< 0x053 Pipe Enable Control Register */ + __IO uint8_t XO1; /*!< 0x054 XO Control Register 1 */ + __IO uint8_t XO2; /*!< 0x055 XO Control Register 2 */ + __IO uint8_t TXP1; /*!< 0x056 TX Power Control Register 1 */ + __IO uint8_t DM3; /*!< 0x057 De-modulator Control Register 3 */ + __IO uint8_t AGC1; /*!< 0x058 AGC Control Register 1 */ + __IO uint8_t AGC2; /*!< 0x059 AGC Control Register 2 */ + __IO uint8_t AGC3; /*!< 0x05A AGC Control Register 3 */ + __IO uint8_t AGC4; /*!< 0x05B AGC Control Register 4 */ + __IO uint8_t FCF1; /*!< 0x05C Filter Coefficient Control Register 1 */ + __IO uint8_t FCF2; /*!< 0x05D Filter Coefficient Control Register 2 */ + __IO uint8_t FCF3; /*!< 0x05E Filter Coefficient Control Register 3 */ + __IO uint8_t FCF4; /*!< 0x05F Filter Coefficient Control Register 4 */ + __IO uint8_t RXG; /*!< 0x060 RX Gain Control Register */ + __IO uint8_t CP1; /*!< 0x061 CP Control Register 1 */ + __IO uint8_t CP2; /*!< 0x062 CP Control Register 2 */ + __IO uint8_t CP3; /*!< 0x063 CP Control Register 3 */ + __IO uint8_t OD1; /*!< 0x064 MMD and OD Control Register 1 */ + __IO uint8_t OD2; /*!< 0x065 MMD and OD Control Register 2 */ + __IO uint8_t VC1; /*!< 0x066 VCO Control Register 1 */ + __IO uint8_t VC2; /*!< 0x067 VCO Control Register 2 */ + __IO uint8_t VC3; /*!< 0x068 VCO Control Register 3 */ + __IO uint8_t RX1; /*!< 0x069 RX Control Register 1 */ + __IO uint8_t RX2; /*!< 0x06A RX Control Register 2 */ + __IO uint8_t RX3; /*!< 0x06B RX Control Register 3 */ + __IO uint8_t RX4; /*!< 0x06C RX Control Register 4 */ + __IO uint8_t RX5; /*!< 0x06D RX Control Register 5 */ + __IO uint8_t TX1; /*!< 0x06E TX Control Register 1 */ + __IO uint8_t TX2; /*!< 0x06F TX Control Register 2 */ + __IO uint8_t TX3; /*!< 0x070 TX Control Register 3 */ + __IO uint8_t CA1; /*!< 0x071 VCO DFC Calibration Control Register 1 */ + __IO uint8_t CA2; /*!< 0x072 VCO DFC Calibration Control Register 2 */ + __IO uint8_t CA3; /*!< 0x073 VCO DFC Calibration Control Register 3 */ + __IO uint8_t LD1; /*!< 0x074 LDO Control Register 1 */ + __IO uint8_t LD2; /*!< 0x075 LDO Control Register 2 */ + __IO uint8_t LD3; /*!< 0x076 LDO Control Register 3 */ + __IO uint8_t RTM1; /*!< 0x077 RF Test Mode Control Register 1 */ + uint8_t RESERVED5[8]; /*!< 0x078 - 0x07F Reserved */ + __IO uint8_t TEST1; /*!< 0x080 Test Control Register 1 */ + __IO uint8_t TEST2; /*!< 0x081 Test Control Register 2 */ + __IO uint8_t TEST3; /*!< 0x082 Test Control Register 3 */ + __IO uint8_t TEST4; /*!< 0x083 Test Control Register 4 */ + __IO uint8_t TEST5; /*!< 0x084 Test Control Register 5 */ + __IO uint8_t TEST6; /*!< 0x085 Test Control Register 6 */ + __IO uint8_t TEST7; /*!< 0x086 Test Control Register 7 */ +} HT_RF_TypeDef; +/** + * @} + */ + +/** @addtogroup Peripheral_Memory_Map + * @{ + */ + +#define HT_SRAM_BASE (0x20000000UL) + +#define HT_PERIPH_BASE (0x40000000UL) + +#define HT_APBPERIPH_BASE (HT_PERIPH_BASE) /* 0x40000000 */ +#define HT_AHBPERIPH_BASE (HT_PERIPH_BASE + 0x80000) /* 0x40080000 */ + +/* APB */ +#define HT_USART0_BASE (HT_APBPERIPH_BASE + 0x0000) /* 0x40000000 */ +#define HT_UART0_BASE (HT_APBPERIPH_BASE + 0x1000) /* 0x40001000 */ +#define HT_UART2_BASE (HT_APBPERIPH_BASE + 0x2000) /* 0x40002000 */ +#define HT_SPI0_BASE (HT_APBPERIPH_BASE + 0x4000) /* 0x40004000 */ +#define HT_I2C2_BASE (HT_APBPERIPH_BASE + 0x8000) /* 0x40008000 */ +#define HT_CAN0_BASE (HT_APBPERIPH_BASE + 0xC000) /* 0x4000C000 */ +#define HT_SLED0_BASE (HT_APBPERIPH_BASE + 0xE000) /* 0x4000E000 */ +#define HT_ADC0_BASE (HT_APBPERIPH_BASE + 0x10000) /* 0x40010000 */ +#define HT_DAC1_BASE (HT_APBPERIPH_BASE + 0x14000) /* 0x40014000 */ +#define HT_OPA0_BASE (HT_APBPERIPH_BASE + 0x18000) /* 0x40018000 */ +#define HT_PGA0_BASE (HT_APBPERIPH_BASE + 0x18000) /* 0x40018000 */ +#define HT_PGA1_BASE (HT_APBPERIPH_BASE + 0x18008) /* 0x40018008 */ +#define HT_PGA2_BASE (HT_APBPERIPH_BASE + 0x18010) /* 0x40018010 */ +#define HT_PGA3_BASE (HT_APBPERIPH_BASE + 0x18018) /* 0x40018018 */ +#define HT_PGA_BASE (HT_APBPERIPH_BASE + 0x18020) /* 0x40018020 */ +#define HT_OPA1_BASE (HT_APBPERIPH_BASE + 0x18100) /* 0x40018100 */ +#define HT_LCD_BASE (HT_APBPERIPH_BASE + 0x1A000) /* 0x4001A000 */ +#define HT_TKEY_BASE (HT_APBPERIPH_BASE + 0x1A000) /* 0x4001A000 */ +#define HT_AFIO_BASE (HT_APBPERIPH_BASE + 0x22000) /* 0x40022000 */ +#define HT_EXTI_BASE (HT_APBPERIPH_BASE + 0x24000) /* 0x40024000 */ +#define HT_I2S_BASE (HT_APBPERIPH_BASE + 0x26000) /* 0x40026000 */ +#define HT_MCTM0_BASE (HT_APBPERIPH_BASE + 0x2C000) /* 0x4002C000 */ +#define HT_PWM0_BASE (HT_APBPERIPH_BASE + 0x31000) /* 0x40031000 */ +#define HT_SCTM0_BASE (HT_APBPERIPH_BASE + 0x34000) /* 0x40034000 */ +#define HT_PWM2_BASE (HT_APBPERIPH_BASE + 0x32000) /* 0x40031000 */ +#define HT_SCTM2_BASE (HT_APBPERIPH_BASE + 0x35000) /* 0x40035000 */ +#define HT_SCI1_BASE (HT_APBPERIPH_BASE + 0x3A000) /* 0x4003A000 */ +#define HT_USART1_BASE (HT_APBPERIPH_BASE + 0x40000) /* 0x40040000 */ +#define HT_UART1_BASE (HT_APBPERIPH_BASE + 0x41000) /* 0x40041000 */ +#define HT_UART3_BASE (HT_APBPERIPH_BASE + 0x42000) /* 0x40042000 */ +#define HT_SCI0_BASE (HT_APBPERIPH_BASE + 0x43000) /* 0x40043000 */ +#define HT_SPI1_BASE (HT_APBPERIPH_BASE + 0x44000) /* 0x40044000 */ +#define HT_I2C0_BASE (HT_APBPERIPH_BASE + 0x48000) /* 0x40048000 */ +#define HT_I2C1_BASE (HT_APBPERIPH_BASE + 0x49000) /* 0x40049000 */ +#define HT_SLED1_BASE (HT_APBPERIPH_BASE + 0x4E000) /* 0x4004E000 */ +#define HT_ADC1_BASE (HT_APBPERIPH_BASE + 0x50000) /* 0x40050000 */ +#define HT_DACDUAL16_BASE (HT_APBPERIPH_BASE + 0x54000) /* 0x40054000 */ +#define HT_DAC0_BASE (HT_APBPERIPH_BASE + 0x54000) /* 0x40054000 */ +#define HT_CMP0_BASE (HT_APBPERIPH_BASE + 0x58000) /* 0x40058000 */ +#define HT_CMP1_BASE (HT_APBPERIPH_BASE + 0x58100) /* 0x40058100 */ +#define HT_CMP2_BASE (HT_APBPERIPH_BASE + 0x58200) /* 0x40058200 */ +#define HT_LEDC_BASE (HT_APBPERIPH_BASE + 0x5A000) /* 0x4005A000 */ +#define HT_MIDI_BASE (HT_APBPERIPH_BASE + 0x60000) /* 0x40060000 */ +#define HT_WDT_BASE (HT_APBPERIPH_BASE + 0x68000) /* 0x40068000 */ +#define HT_RTC_BASE (HT_APBPERIPH_BASE + 0x6A000) /* 0x4006A000 */ +#define HT_PWRCU_BASE (HT_APBPERIPH_BASE + 0x6A100) /* 0x4006A100 */ +#define HT_GPTM0_BASE (HT_APBPERIPH_BASE + 0x6E000) /* 0x4006E000 */ +#define HT_GPTM1_BASE (HT_APBPERIPH_BASE + 0x6F000) /* 0x4006F000 */ +#define HT_PWM1_BASE (HT_APBPERIPH_BASE + 0x71000) /* 0x40071000 */ +#define HT_SCTM1_BASE (HT_APBPERIPH_BASE + 0x74000) /* 0x40074000 */ +#define HT_SCTM3_BASE (HT_APBPERIPH_BASE + 0x75000) /* 0x40075000 */ +#define HT_BFTM0_BASE (HT_APBPERIPH_BASE + 0x76000) /* 0x40076000 */ +#define HT_BFTM1_BASE (HT_APBPERIPH_BASE + 0x77000) /* 0x40077000 */ + +/* AHB */ +#define HT_FLASH_BASE (HT_AHBPERIPH_BASE + 0x0000) /* 0x40080000 */ +#define HT_CKCU_BASE (HT_AHBPERIPH_BASE + 0x8000) /* 0x40088000 */ +#define HT_RSTCU_BASE (HT_AHBPERIPH_BASE + 0x8100) /* 0x40088100 */ +#define HT_CRC_BASE (HT_AHBPERIPH_BASE + 0xA000) /* 0x4008A000 */ +#define HT_PDMA_BASE (HT_AHBPERIPH_BASE + 0x10000) /* 0x40090000 */ +#define HT_EBI_BASE (HT_AHBPERIPH_BASE + 0x18000) /* 0x40098000 */ +#define HT_USB_BASE (HT_AHBPERIPH_BASE + 0x28000) /* 0x400A8000 */ +#define HT_USB_EP0_BASE (HT_USB_BASE + 0x0014) /* 0x400A8014 */ +#define HT_USB_EP1_BASE (HT_USB_BASE + 0x0028) /* 0x400A8028 */ +#define HT_USB_EP2_BASE (HT_USB_BASE + 0x003C) /* 0x400A803C */ +#define HT_USB_EP3_BASE (HT_USB_BASE + 0x0050) /* 0x400A8050 */ +#define HT_USB_EP4_BASE (HT_USB_BASE + 0x0064) /* 0x400A8064 */ +#define HT_USB_EP5_BASE (HT_USB_BASE + 0x0078) /* 0x400A8078 */ +#define HT_USB_EP6_BASE (HT_USB_BASE + 0x008C) /* 0x400A808C */ +#define HT_USB_EP7_BASE (HT_USB_BASE + 0x00A0) /* 0x400A80A0 */ +#define HT_USB_EP8_BASE (HT_USB_BASE + 0x00B4) /* 0x400A80B4 */ +#define HT_USB_EP9_BASE (HT_USB_BASE + 0x00C8) /* 0x400A80C8 */ +#define HT_USB_SRAM_BASE (HT_AHBPERIPH_BASE + 0x2A000) /* 0x400AA000 */ +#define HT_GPIOA_BASE (HT_AHBPERIPH_BASE + 0x30000) /* 0x400B0000 */ +#define HT_GPIOB_BASE (HT_AHBPERIPH_BASE + 0x32000) /* 0x400B2000 */ +#define HT_GPIOC_BASE (HT_AHBPERIPH_BASE + 0x34000) /* 0x400B4000 */ +#define HT_GPIOD_BASE (HT_AHBPERIPH_BASE + 0x36000) /* 0x400B6000 */ +#define HT_GPIOE_BASE (HT_AHBPERIPH_BASE + 0x38000) /* 0x400B8000 */ +#define HT_GPIOF_BASE (HT_AHBPERIPH_BASE + 0x3A000) /* 0x400BA000 */ +#define HT_AES_BASE (HT_AHBPERIPH_BASE + 0x48000) /* 0x400C8000 */ +#define HT_DIV_BASE (HT_AHBPERIPH_BASE + 0x4A000) /* 0x400CA000 */ +#define HT_RF_BASE (HT_AHBPERIPH_BASE + 0x50000) /* 0x400D0000 */ +#define HT_CORDIC_BASE (HT_AHBPERIPH_BASE + 0x5C000) /* 0x400DC000 */ +#define HT_PID_BASE (HT_AHBPERIPH_BASE + 0x5E000) /* 0x400DE000 */ +#define HT_QSPI_BASE (HT_AHBPERIPH_BASE + 0x60000) /* 0x400E0000 */ + +/** + * @} + */ + +/* Peripheral declaration */ +#define HT_FLASH ((HT_FLASH_TypeDef *) HT_FLASH_BASE) +#define HT_CKCU ((HT_CKCU_TypeDef *) HT_CKCU_BASE) +#define HT_PWRCU ((HT_PWRCU_TypeDef *) HT_PWRCU_BASE) +#define HT_RSTCU ((HT_RSTCU_TypeDef *) HT_RSTCU_BASE) +#define HT_AFIO ((HT_AFIO_TypeDef *) HT_AFIO_BASE) +#define HT_EXTI ((HT_EXTI_TypeDef *) HT_EXTI_BASE) +#define HT_GPIOA ((HT_GPIO_TypeDef *) HT_GPIOA_BASE) +#define HT_GPIOB ((HT_GPIO_TypeDef *) HT_GPIOB_BASE) +#define HT_BFTM0 ((HT_BFTM_TypeDef *) HT_BFTM0_BASE) +#define HT_WDT ((HT_WDT_TypeDef *) HT_WDT_BASE) +#define HT_UART0 ((HT_USART_TypeDef *) HT_UART0_BASE) +#define HT_SPI0 ((HT_SPI_TypeDef *) HT_SPI0_BASE) +#define HT_I2C0 ((HT_I2C_TypeDef *) HT_I2C0_BASE) + +#if !defined(USE_HT32F50020_30) && !defined(USE_HT32F52234_44) +#define HT_GPTM0 ((HT_TM_TypeDef *) HT_GPTM0_BASE) +#endif + +#if !defined(USE_HT32F0008) && !defined(USE_HT32F61141) +#define HT_ADC0 ((HT_ADC_TypeDef *) HT_ADC0_BASE) +#endif + +#if !defined(USE_HT32F0008) && !defined(USE_HT32F50220_30) && !defined(USE_HT32F50231_41) && !defined(USE_HT32F57331_41) && !defined(USE_HT32F53231_41) && !defined(USE_HT32F53242_52) && !defined(USE_HT32F50431_41) && !defined(USE_HT32F50442_52) +#define HT_SCTM0 ((HT_TM_TypeDef *) HT_SCTM0_BASE) +#define HT_SCTM1 ((HT_TM_TypeDef *) HT_SCTM1_BASE) +#endif + +#if defined(USE_HT32F52231_41) || defined(USE_HT32F52331_41) || defined(USE_HT32F52243_53) || defined(USE_HT32F0006) || defined(USE_HT32F65230_40) || defined(USE_HT32F65232) || defined(USE_HT32F54243_53) || defined(USE_HT32F50020_30) || defined(USE_HT32F67041_51) || defined(USE_HT32F66242) || defined(USE_HT32F66246) +#define HT_SCTM2 ((HT_TM_TypeDef *) HT_SCTM2_BASE) +#endif + +#if defined(USE_HT32F52231_41) || defined(USE_HT32F52331_41) || defined(USE_HT32F52243_53) || defined(USE_HT32F0006) || defined(USE_HT32F65230_40) || defined(USE_HT32F65232) || defined(USE_HT32F54243_53) || defined(USE_HT32F67041_51) || defined(USE_HT32F66242) || defined(USE_HT32F66246) +#define HT_SCTM3 ((HT_TM_TypeDef *) HT_SCTM3_BASE) +#endif + +#if !defined(USE_HT32F50220_30) && !defined(USE_HT32F52344_54) && !defined(USE_HT32F50343) && !defined(USE_HT32F61141) && !defined(USE_HT32F61244_45) && !defined(USE_HT32F50020_30) && !defined(USE_HT32F67041_51) +#define HT_USART0 ((HT_USART_TypeDef *) HT_USART0_BASE) +#endif + +#if defined(USE_HT32F52331_41) || defined(USE_HT32F52342_52) || defined(USE_HT32F5826) || defined(USE_HT32F52357_67) || defined(USE_HT32F57342_52) || defined(USE_HT32F57331_41) || defined(USE_HT32F61141) +#define HT_SCI0 ((HT_SCI_TypeDef *) HT_SCI0_BASE) +#endif + +#if defined(USE_HT32F52331_41) || defined(USE_HT32F52342_52) || defined(USE_HT32F5826) || defined(USE_HT32F0008) || defined(USE_HT32F52344_54) || defined(USE_HT32F0006) || defined(USE_HT32F52357_67) || defined(USE_HT32F57342_52) || defined(USE_HT32F57331_41) || defined(USE_HT32F50343) || defined(USE_HT32F61141) +#define HT_USB ((HT_USB_TypeDef *) HT_USB_BASE) +#define HT_USBEP0 ((HT_USBEP_TypeDef *) HT_USB_EP0_BASE) +#define HT_USBEP1 ((HT_USBEP_TypeDef *) HT_USB_EP1_BASE) +#define HT_USBEP2 ((HT_USBEP_TypeDef *) HT_USB_EP2_BASE) +#define HT_USBEP3 ((HT_USBEP_TypeDef *) HT_USB_EP3_BASE) +#define HT_USBEP4 ((HT_USBEP_TypeDef *) HT_USB_EP4_BASE) +#define HT_USBEP5 ((HT_USBEP_TypeDef *) HT_USB_EP5_BASE) +#define HT_USBEP6 ((HT_USBEP_TypeDef *) HT_USB_EP6_BASE) +#define HT_USBEP7 ((HT_USBEP_TypeDef *) HT_USB_EP7_BASE) +#endif + +#if defined(USE_HT32F52231_41) || defined(USE_HT32F52331_41) +#define HT_BFTM1 ((HT_BFTM_TypeDef *) HT_BFTM1_BASE) +#define HT_MCTM0 ((HT_TM_TypeDef *) HT_MCTM0_BASE) +#define HT_RTC ((HT_RTC_TypeDef *) HT_RTC_BASE) +#define HT_UART1 ((HT_USART_TypeDef *) HT_UART1_BASE) +#define HT_SPI1 ((HT_SPI_TypeDef *) HT_SPI1_BASE) +#define HT_I2C1 ((HT_I2C_TypeDef *) HT_I2C1_BASE) +#define HT_CRC ((HT_CRC_TypeDef *) HT_CRC_BASE) +#define HT_GPIOC ((HT_GPIO_TypeDef *) HT_GPIOC_BASE) +#endif + +#if defined(USE_HT32F52342_52) || defined(USE_HT32F5826) +#define HT_PDMA ((HT_PDMA_TypeDef *) HT_PDMA_BASE) +#define HT_CMP0 ((HT_CMP_TypeDef *) HT_CMP0_BASE) +#define HT_CMP1 ((HT_CMP_TypeDef *) HT_CMP1_BASE) +#define HT_BFTM1 ((HT_BFTM_TypeDef *) HT_BFTM1_BASE) +#define HT_GPTM1 ((HT_TM_TypeDef *) HT_GPTM1_BASE) +#define HT_MCTM0 ((HT_TM_TypeDef *) HT_MCTM0_BASE) +#define HT_RTC ((HT_RTC_TypeDef *) HT_RTC_BASE) +#define HT_SCI1 ((HT_SCI_TypeDef *) HT_SCI1_BASE) +#define HT_EBI ((HT_EBI_TypeDef *) HT_EBI_BASE) +#define HT_I2S ((HT_I2S_TypeDef *) HT_I2S_BASE) +#define HT_USART1 ((HT_USART_TypeDef *) HT_USART1_BASE) +#define HT_UART1 ((HT_USART_TypeDef *) HT_UART1_BASE) +#define HT_SPI1 ((HT_SPI_TypeDef *) HT_SPI1_BASE) +#define HT_I2C1 ((HT_I2C_TypeDef *) HT_I2C1_BASE) +#define HT_CRC ((HT_CRC_TypeDef *) HT_CRC_BASE) +#define HT_GPIOC ((HT_GPIO_TypeDef *) HT_GPIOC_BASE) +#define HT_GPIOD ((HT_GPIO_TypeDef *) HT_GPIOD_BASE) +#endif + +#if defined(USE_HT32F52243_53) +#define HT_PDMA ((HT_PDMA_TypeDef *) HT_PDMA_BASE) +#define HT_BFTM1 ((HT_BFTM_TypeDef *) HT_BFTM1_BASE) +#define HT_MCTM0 ((HT_TM_TypeDef *) HT_MCTM0_BASE) +#define HT_RTC ((HT_RTC_TypeDef *) HT_RTC_BASE) +#define HT_USART1 ((HT_USART_TypeDef *) HT_USART1_BASE) +#define HT_UART1 ((HT_USART_TypeDef *) HT_UART1_BASE) +#define HT_UART2 ((HT_USART_TypeDef *) HT_UART2_BASE) +#define HT_UART3 ((HT_USART_TypeDef *) HT_UART3_BASE) +#define HT_SPI1 ((HT_SPI_TypeDef *) HT_SPI1_BASE) +#define HT_I2C1 ((HT_I2C_TypeDef *) HT_I2C1_BASE) +#define HT_I2C2 ((HT_I2C_TypeDef *) HT_I2C2_BASE) +#define HT_CRC ((HT_CRC_TypeDef *) HT_CRC_BASE) +#define HT_DIV ((HT_DIV_TypeDef *) HT_DIV_BASE) +#define HT_GPIOC ((HT_GPIO_TypeDef *) HT_GPIOC_BASE) +#define HT_GPIOD ((HT_GPIO_TypeDef *) HT_GPIOD_BASE) +#endif + +#if defined(USE_HT32F0008) +#define HT_PDMA ((HT_PDMA_TypeDef *) HT_PDMA_BASE) +#define HT_BFTM1 ((HT_BFTM_TypeDef *) HT_BFTM1_BASE) +#define HT_PWM0 ((HT_TM_TypeDef *) HT_PWM0_BASE) +#define HT_PWM1 ((HT_TM_TypeDef *) HT_PWM1_BASE) +#define HT_RTC ((HT_RTC_TypeDef *) HT_RTC_BASE) +#define HT_AES ((HT_AES_TypeDef *) HT_AES_BASE) +#define HT_CRC ((HT_CRC_TypeDef *) HT_CRC_BASE) +#define HT_DIV ((HT_DIV_TypeDef *) HT_DIV_BASE) +#define HT_GPIOC ((HT_GPIO_TypeDef *) HT_GPIOC_BASE) +#define HT_GPIOF ((HT_GPIO_TypeDef *) HT_GPIOF_BASE) +#endif + +#if defined(USE_HT32F50220_30) +#define HT_PWM0 ((HT_TM_TypeDef *) HT_PWM0_BASE) +#define HT_PWM1 ((HT_TM_TypeDef *) HT_PWM1_BASE) +#define HT_RTC ((HT_RTC_TypeDef *) HT_RTC_BASE) +#define HT_DIV ((HT_DIV_TypeDef *) HT_DIV_BASE) +#define HT_UART1 ((HT_USART_TypeDef *) HT_UART1_BASE) +#define HT_SPI1 ((HT_SPI_TypeDef *) HT_SPI1_BASE) +#define HT_GPIOC ((HT_GPIO_TypeDef *) HT_GPIOC_BASE) +#endif + +#if defined(USE_HT32F50231_41) +#define HT_BFTM1 ((HT_BFTM_TypeDef *) HT_BFTM1_BASE) +#define HT_PWM0 ((HT_TM_TypeDef *) HT_PWM0_BASE) +#define HT_PWM1 ((HT_TM_TypeDef *) HT_PWM1_BASE) +#define HT_MCTM0 ((HT_TM_TypeDef *) HT_MCTM0_BASE) +#define HT_RTC ((HT_RTC_TypeDef *) HT_RTC_BASE) +#define HT_UART1 ((HT_USART_TypeDef *) HT_UART1_BASE) +#define HT_SPI1 ((HT_SPI_TypeDef *) HT_SPI1_BASE) +#define HT_I2C1 ((HT_I2C_TypeDef *) HT_I2C1_BASE) +#define HT_CRC ((HT_CRC_TypeDef *) HT_CRC_BASE) +#define HT_DIV ((HT_DIV_TypeDef *) HT_DIV_BASE) +#define HT_GPIOC ((HT_GPIO_TypeDef *) HT_GPIOC_BASE) +#endif + +#if defined(USE_HT32F52344_54) +#define HT_PDMA ((HT_PDMA_TypeDef *) HT_PDMA_BASE) +#define HT_CMP0 ((HT_CMP_TypeDef *) HT_CMP0_BASE) +#define HT_CMP1 ((HT_CMP_TypeDef *) HT_CMP1_BASE) +#define HT_BFTM1 ((HT_BFTM_TypeDef *) HT_BFTM1_BASE) +#define HT_MCTM0 ((HT_TM_TypeDef *) HT_MCTM0_BASE) +#define HT_RTC ((HT_RTC_TypeDef *) HT_RTC_BASE) +#define HT_EBI ((HT_EBI_TypeDef *) HT_EBI_BASE) +#define HT_SPI1 ((HT_SPI_TypeDef *) HT_SPI1_BASE) +#define HT_UART1 ((HT_USART_TypeDef *) HT_UART1_BASE) +#define HT_CRC ((HT_CRC_TypeDef *) HT_CRC_BASE) +#define HT_DIV ((HT_DIV_TypeDef *) HT_DIV_BASE) +#define HT_GPIOC ((HT_GPIO_TypeDef *) HT_GPIOC_BASE) +#define HT_GPIOD ((HT_GPIO_TypeDef *) HT_GPIOD_BASE) +#endif + +#if defined(USE_HT32F0006) +#define HT_PDMA ((HT_PDMA_TypeDef *) HT_PDMA_BASE) +#define HT_BFTM1 ((HT_BFTM_TypeDef *) HT_BFTM1_BASE) +#define HT_RTC ((HT_RTC_TypeDef *) HT_RTC_BASE) +#define HT_CRC ((HT_CRC_TypeDef *) HT_CRC_BASE) +#define HT_DIV ((HT_DIV_TypeDef *) HT_DIV_BASE) +#define HT_GPIOC ((HT_GPIO_TypeDef *) HT_GPIOC_BASE) +#define HT_GPIOD ((HT_GPIO_TypeDef *) HT_GPIOD_BASE) +#define HT_QSPI ((HT_SPI_TypeDef *) HT_QSPI_BASE) +#define HT_I2S ((HT_I2S_TypeDef *) HT_I2S_BASE) +#define HT_DACDUAL16 ((HT_DAC_DUAL16_TypeDef *) HT_DACDUAL16_BASE) +#define HT_MIDI ((HT_MIDI_TypeDef *) HT_MIDI_BASE) +#endif + +#if defined(USE_HT32F52357_67) +#define HT_PDMA ((HT_PDMA_TypeDef *) HT_PDMA_BASE) +#define HT_DAC0 ((HT_DAC_TypeDef *) HT_DAC0_BASE) +#define HT_CMP0 ((HT_CMP_TypeDef *) HT_CMP0_BASE) +#define HT_CMP1 ((HT_CMP_TypeDef *) HT_CMP1_BASE) +#define HT_BFTM1 ((HT_BFTM_TypeDef *) HT_BFTM1_BASE) +#define HT_PWM0 ((HT_TM_TypeDef *) HT_PWM0_BASE) +#define HT_PWM1 ((HT_TM_TypeDef *) HT_PWM1_BASE) +#define HT_MCTM0 ((HT_TM_TypeDef *) HT_MCTM0_BASE) +#define HT_RTC ((HT_RTC_TypeDef *) HT_RTC_BASE) +#define HT_SCI1 ((HT_SCI_TypeDef *) HT_SCI1_BASE) +#define HT_EBI ((HT_EBI_TypeDef *) HT_EBI_BASE) +#define HT_I2S ((HT_I2S_TypeDef *) HT_I2S_BASE) +#define HT_USART1 ((HT_USART_TypeDef *) HT_USART1_BASE) +#define HT_UART1 ((HT_USART_TypeDef *) HT_UART1_BASE) +#define HT_UART2 ((HT_USART_TypeDef *) HT_UART2_BASE) +#define HT_UART3 ((HT_USART_TypeDef *) HT_UART3_BASE) +#define HT_SPI1 ((HT_SPI_TypeDef *) HT_SPI1_BASE) +#define HT_QSPI ((HT_SPI_TypeDef *) HT_QSPI_BASE) +#define HT_I2C1 ((HT_I2C_TypeDef *) HT_I2C1_BASE) +#define HT_CRC ((HT_CRC_TypeDef *) HT_CRC_BASE) +#define HT_DIV ((HT_DIV_TypeDef *) HT_DIV_BASE) +#define HT_AES ((HT_AES_TypeDef *) HT_AES_BASE) +#define HT_GPIOC ((HT_GPIO_TypeDef *) HT_GPIOC_BASE) +#define HT_GPIOD ((HT_GPIO_TypeDef *) HT_GPIOD_BASE) +#define HT_GPIOE ((HT_GPIO_TypeDef *) HT_GPIOE_BASE) +#endif + +#if defined(USE_HT32F57342_52) +#define HT_PDMA ((HT_PDMA_TypeDef *) HT_PDMA_BASE) +#define HT_DAC0 ((HT_DAC_TypeDef *) HT_DAC0_BASE) +#define HT_CMP0 ((HT_CMP_TypeDef *) HT_CMP0_BASE) +#define HT_CMP1 ((HT_CMP_TypeDef *) HT_CMP1_BASE) +#define HT_BFTM1 ((HT_BFTM_TypeDef *) HT_BFTM1_BASE) +#define HT_PWM0 ((HT_TM_TypeDef *) HT_PWM0_BASE) +#define HT_PWM1 ((HT_TM_TypeDef *) HT_PWM1_BASE) +#define HT_RTC ((HT_RTC_TypeDef *) HT_RTC_BASE) +#define HT_SCI1 ((HT_SCI_TypeDef *) HT_SCI1_BASE) +#define HT_I2S ((HT_I2S_TypeDef *) HT_I2S_BASE) +#define HT_UART1 ((HT_USART_TypeDef *) HT_UART1_BASE) +#define HT_SPI1 ((HT_SPI_TypeDef *) HT_SPI1_BASE) +#define HT_I2C1 ((HT_I2C_TypeDef *) HT_I2C1_BASE) +#define HT_CRC ((HT_CRC_TypeDef *) HT_CRC_BASE) +#define HT_DIV ((HT_DIV_TypeDef *) HT_DIV_BASE) +#define HT_AES ((HT_AES_TypeDef *) HT_AES_BASE) +#define HT_GPIOC ((HT_GPIO_TypeDef *) HT_GPIOC_BASE) +#define HT_GPIOD ((HT_GPIO_TypeDef *) HT_GPIOD_BASE) +#define HT_GPIOE ((HT_GPIO_TypeDef *) HT_GPIOE_BASE) +#define HT_LCD ((HT_LCD_TypeDef *) HT_LCD_BASE) +#endif + +#if defined(USE_HT32F57331_41) +#define HT_BFTM1 ((HT_BFTM_TypeDef *) HT_BFTM1_BASE) +#define HT_PWM0 ((HT_TM_TypeDef *) HT_PWM0_BASE) +#define HT_PWM1 ((HT_TM_TypeDef *) HT_PWM1_BASE) +#define HT_RTC ((HT_RTC_TypeDef *) HT_RTC_BASE) +#define HT_UART1 ((HT_USART_TypeDef *) HT_UART1_BASE) +#define HT_SPI1 ((HT_SPI_TypeDef *) HT_SPI1_BASE) +#define HT_I2C1 ((HT_I2C_TypeDef *) HT_I2C1_BASE) +#define HT_CRC ((HT_CRC_TypeDef *) HT_CRC_BASE) +#define HT_DIV ((HT_DIV_TypeDef *) HT_DIV_BASE) +#define HT_GPIOC ((HT_GPIO_TypeDef *) HT_GPIOC_BASE) +#define HT_GPIOD ((HT_GPIO_TypeDef *) HT_GPIOD_BASE) +#define HT_LCD ((HT_LCD_TypeDef *) HT_LCD_BASE) +#endif + +#if defined(USE_HT32F65230_40) +#define HT_PDMA ((HT_PDMA_TypeDef *) HT_PDMA_BASE) +#define HT_ADC1 ((HT_ADC_TypeDef *) HT_ADC1_BASE) +#define HT_CMP0 ((HT_CMP_TypeDef *) HT_CMP0_BASE) +#define HT_CMP1 ((HT_CMP_TypeDef *) HT_CMP1_BASE) +#define HT_CMP2 ((HT_CMP_TypeDef *) HT_CMP2_BASE) +#define HT_OPA0 ((HT_OPA_TypeDef *) HT_OPA0_BASE) +#define HT_OPA1 ((HT_OPA_TypeDef *) HT_OPA1_BASE) +#define HT_BFTM1 ((HT_BFTM_TypeDef *) HT_BFTM1_BASE) +#define HT_MCTM0 ((HT_TM_TypeDef *) HT_MCTM0_BASE) +#define HT_RTC ((HT_RTC_TypeDef *) HT_RTC_BASE) +#define HT_CRC ((HT_CRC_TypeDef *) HT_CRC_BASE) +#define HT_DIV ((HT_DIV_TypeDef *) HT_DIV_BASE) +#define HT_GPIOC ((HT_GPIO_TypeDef *) HT_GPIOC_BASE) +#endif + +#if defined(USE_HT32F65232) +#define HT_PDMA ((HT_PDMA_TypeDef *) HT_PDMA_BASE) +#define HT_CMP0 ((HT_CMP_TypeDef *) HT_CMP0_BASE) +#define HT_CMP1 ((HT_CMP_TypeDef *) HT_CMP1_BASE) +#define HT_OPA0 ((HT_OPA_TypeDef *) HT_OPA0_BASE) +#define HT_BFTM1 ((HT_BFTM_TypeDef *) HT_BFTM1_BASE) +#define HT_MCTM0 ((HT_TM_TypeDef *) HT_MCTM0_BASE) +#define HT_RTC ((HT_RTC_TypeDef *) HT_RTC_BASE) +#define HT_CRC ((HT_CRC_TypeDef *) HT_CRC_BASE) +#define HT_DIV ((HT_DIV_TypeDef *) HT_DIV_BASE) +#define HT_GPIOC ((HT_GPIO_TypeDef *) HT_GPIOC_BASE) +#endif + +#if defined(USE_HT32F50343) +#define HT_UART1 ((HT_USART_TypeDef *) HT_UART1_BASE) +#define HT_SPI1 ((HT_SPI_TypeDef *) HT_SPI1_BASE) +#define HT_I2C1 ((HT_I2C_TypeDef *) HT_I2C1_BASE) +#define HT_RTC ((HT_RTC_TypeDef *) HT_RTC_BASE) +#define HT_PWM0 ((HT_TM_TypeDef *) HT_PWM0_BASE) +#define HT_PWM1 ((HT_TM_TypeDef *) HT_PWM1_BASE) +#define HT_PWM2 ((HT_TM_TypeDef *) HT_PWM2_BASE) +#define HT_BFTM1 ((HT_BFTM_TypeDef *) HT_BFTM1_BASE) +#define HT_SLED0 ((HT_SLED_TypeDef *) HT_SLED0_BASE) +#define HT_SLED1 ((HT_SLED_TypeDef *) HT_SLED1_BASE) +#define HT_GPIOC ((HT_GPIO_TypeDef *) HT_GPIOC_BASE) +#define HT_GPIOD ((HT_GPIO_TypeDef *) HT_GPIOD_BASE) +#define HT_CRC ((HT_CRC_TypeDef *) HT_CRC_BASE) +#define HT_DIV ((HT_DIV_TypeDef *) HT_DIV_BASE) +#define HT_PDMA ((HT_PDMA_TypeDef *) HT_PDMA_BASE) +#endif + +#if defined(USE_HT32F54231_41) +#define HT_BFTM1 ((HT_BFTM_TypeDef *) HT_BFTM1_BASE) +#define HT_MCTM0 ((HT_TM_TypeDef *) HT_MCTM0_BASE) +#define HT_RTC ((HT_RTC_TypeDef *) HT_RTC_BASE) +#define HT_UART1 ((HT_USART_TypeDef *) HT_UART1_BASE) +#define HT_SPI1 ((HT_SPI_TypeDef *) HT_SPI1_BASE) +#define HT_I2C1 ((HT_I2C_TypeDef *) HT_I2C1_BASE) +#define HT_CRC ((HT_CRC_TypeDef *) HT_CRC_BASE) +#define HT_DIV ((HT_DIV_TypeDef *) HT_DIV_BASE) +#define HT_GPIOC ((HT_GPIO_TypeDef *) HT_GPIOC_BASE) +#define HT_TKEY ((HT_TKEY_TypeDef *) HT_TKEY_BASE) +#define HT_LEDC ((HT_LEDC_TypeDef *) HT_LEDC_BASE) +#endif + +#if defined(USE_HT32F54243_53) +#define HT_PDMA ((HT_PDMA_TypeDef *) HT_PDMA_BASE) +#define HT_CMP0 ((HT_CMP_TypeDef *) HT_CMP0_BASE) +#define HT_CMP1 ((HT_CMP_TypeDef *) HT_CMP1_BASE) +#define HT_BFTM1 ((HT_BFTM_TypeDef *) HT_BFTM1_BASE) +#define HT_MCTM0 ((HT_TM_TypeDef *) HT_MCTM0_BASE) +#define HT_RTC ((HT_RTC_TypeDef *) HT_RTC_BASE) +#define HT_USART1 ((HT_USART_TypeDef *) HT_USART1_BASE) +#define HT_UART1 ((HT_USART_TypeDef *) HT_UART1_BASE) +#define HT_UART2 ((HT_USART_TypeDef *) HT_UART2_BASE) +#define HT_UART3 ((HT_USART_TypeDef *) HT_UART3_BASE) +#define HT_SPI1 ((HT_SPI_TypeDef *) HT_SPI1_BASE) +#define HT_I2C1 ((HT_I2C_TypeDef *) HT_I2C1_BASE) +#define HT_I2C2 ((HT_I2C_TypeDef *) HT_I2C2_BASE) +#define HT_CRC ((HT_CRC_TypeDef *) HT_CRC_BASE) +#define HT_DIV ((HT_DIV_TypeDef *) HT_DIV_BASE) +#define HT_GPIOC ((HT_GPIO_TypeDef *) HT_GPIOC_BASE) +#define HT_GPIOD ((HT_GPIO_TypeDef *) HT_GPIOD_BASE) +#define HT_TKEY ((HT_TKEY_TypeDef *) HT_TKEY_BASE) +#define HT_LEDC ((HT_LEDC_TypeDef *) HT_LEDC_BASE) +#endif + +#if defined(USE_HT32F61141) +#define HT_BFTM1 ((HT_BFTM_TypeDef *) HT_BFTM1_BASE) +#define HT_RTC ((HT_RTC_TypeDef *) HT_RTC_BASE) +#define HT_UART1 ((HT_USART_TypeDef *) HT_UART1_BASE) +#define HT_SCI1 ((HT_SCI_TypeDef *) HT_SCI1_BASE) +#define HT_USBEP8 ((HT_USBEP_TypeDef *) HT_USB_EP8_BASE) +#define HT_USBEP9 ((HT_USBEP_TypeDef *) HT_USB_EP9_BASE) +#define HT_CRC ((HT_CRC_TypeDef *) HT_CRC_BASE) +#define HT_GPIOC ((HT_GPIO_TypeDef *) HT_GPIOC_BASE) +#endif + +#if defined(USE_HT32F61244_45) +#define HT_PDMA ((HT_PDMA_TypeDef *) HT_PDMA_BASE) +#define HT_BFTM1 ((HT_BFTM_TypeDef *) HT_BFTM1_BASE) +#define HT_LSTM0 ((HT_RTC_TypeDef *) HT_RTC_BASE) +#define HT_CRC ((HT_CRC_TypeDef *) HT_CRC_BASE) +#define HT_GPIOC ((HT_GPIO_TypeDef *) HT_GPIOC_BASE) +#define HT_GPIOD ((HT_GPIO_TypeDef *) HT_GPIOD_BASE) +#define HT_QSPI ((HT_SPI_TypeDef *) HT_QSPI_BASE) +#define HT_DACDUAL16 ((HT_DAC_DUAL16_TypeDef *) HT_DACDUAL16_BASE) +#define HT_MIDI ((HT_MIDI_TypeDef *) HT_MIDI_BASE) + +#define HT_RTC HT_LSTM0 +#endif + +#if defined(USE_HT32F50020_30) +#define HT_RTC ((HT_RTC_TypeDef *) HT_RTC_BASE) +#define HT_UART1 ((HT_USART_TypeDef *) HT_UART1_BASE) +#define HT_GPIOC ((HT_GPIO_TypeDef *) HT_GPIOC_BASE) +#define HT_GPIOF ((HT_GPIO_TypeDef *) HT_GPIOF_BASE) +#define HT_LEDC ((HT_LEDC_TypeDef *) HT_LEDC_BASE) +#endif + +#if defined(USE_HT32F67041_51) +#define HT_AES ((HT_AES_TypeDef *) HT_AES_BASE) +#define HT_BFTM1 ((HT_BFTM_TypeDef *) HT_BFTM1_BASE) +#define HT_CRC ((HT_CRC_TypeDef *) HT_CRC_BASE) +#define HT_DIV ((HT_DIV_TypeDef *) HT_DIV_BASE) +#define HT_I2C1 ((HT_I2C_TypeDef *) HT_I2C1_BASE) +#define HT_PDMA ((HT_PDMA_TypeDef *) HT_PDMA_BASE) +#define HT_RTC ((HT_RTC_TypeDef *) HT_RTC_BASE) +#define HT_SPI1 ((HT_SPI_TypeDef *) HT_SPI1_BASE) +#define HT_UART1 ((HT_USART_TypeDef *) HT_UART1_BASE) +#define HT_RF ((HT_RF_TypeDef *) HT_RF_BASE) +#endif + +#if defined(USE_HT32F50442_52) +#define HT_PDMA ((HT_PDMA_TypeDef *) HT_PDMA_BASE) +#define HT_CMP0 ((HT_CMP_TypeDef *) HT_CMP0_BASE) +#define HT_CMP1 ((HT_CMP_TypeDef *) HT_CMP1_BASE) +#define HT_BFTM1 ((HT_BFTM_TypeDef *) HT_BFTM1_BASE) +#define HT_MCTM0 ((HT_TM_TypeDef *) HT_MCTM0_BASE) +#define HT_PWM0 ((HT_TM_TypeDef *) HT_PWM0_BASE) +#define HT_PWM1 ((HT_TM_TypeDef *) HT_PWM1_BASE) +#define HT_RTC ((HT_RTC_TypeDef *) HT_RTC_BASE) +#define HT_EBI ((HT_EBI_TypeDef *) HT_EBI_BASE) +#define HT_USART1 ((HT_USART_TypeDef *) HT_USART1_BASE) +#define HT_UART1 ((HT_USART_TypeDef *) HT_UART1_BASE) +#define HT_SPI1 ((HT_SPI_TypeDef *) HT_SPI1_BASE) +#define HT_I2C1 ((HT_I2C_TypeDef *) HT_I2C1_BASE) +#define HT_CRC ((HT_CRC_TypeDef *) HT_CRC_BASE) +#define HT_LEDC ((HT_LEDC_TypeDef *) HT_LEDC_BASE) +#define HT_DIV ((HT_DIV_TypeDef *) HT_DIV_BASE) +#define HT_GPIOC ((HT_GPIO_TypeDef *) HT_GPIOC_BASE) +#define HT_GPIOD ((HT_GPIO_TypeDef *) HT_GPIOD_BASE) +#endif + +#if defined(USE_HT32F50431_41) +#define HT_PDMA ((HT_PDMA_TypeDef *) HT_PDMA_BASE) +#define HT_BFTM1 ((HT_BFTM_TypeDef *) HT_BFTM1_BASE) +#define HT_PWM0 ((HT_TM_TypeDef *) HT_PWM0_BASE) +#define HT_MCTM0 ((HT_TM_TypeDef *) HT_MCTM0_BASE) +#define HT_RTC ((HT_RTC_TypeDef *) HT_RTC_BASE) +#define HT_UART1 ((HT_USART_TypeDef *) HT_UART1_BASE) +#define HT_SPI1 ((HT_SPI_TypeDef *) HT_SPI1_BASE) +#define HT_I2C1 ((HT_I2C_TypeDef *) HT_I2C1_BASE) +#define HT_CRC ((HT_CRC_TypeDef *) HT_CRC_BASE) +#define HT_DIV ((HT_DIV_TypeDef *) HT_DIV_BASE) +#define HT_LEDC ((HT_LEDC_TypeDef *) HT_LEDC_BASE) +#define HT_GPIOC ((HT_GPIO_TypeDef *) HT_GPIOC_BASE) +#define HT_GPIOD ((HT_GPIO_TypeDef *) HT_GPIOD_BASE) +#endif + +#if defined(USE_HT32F53242_52) +#define HT_PDMA ((HT_PDMA_TypeDef *) HT_PDMA_BASE) +#define HT_CMP0 ((HT_CMP_TypeDef *) HT_CMP0_BASE) +#define HT_CMP1 ((HT_CMP_TypeDef *) HT_CMP1_BASE) +#define HT_BFTM1 ((HT_BFTM_TypeDef *) HT_BFTM1_BASE) +#define HT_MCTM0 ((HT_TM_TypeDef *) HT_MCTM0_BASE) +#define HT_PWM0 ((HT_TM_TypeDef *) HT_PWM0_BASE) +#define HT_PWM1 ((HT_TM_TypeDef *) HT_PWM1_BASE) +#define HT_RTC ((HT_RTC_TypeDef *) HT_RTC_BASE) +#define HT_EBI ((HT_EBI_TypeDef *) HT_EBI_BASE) +#define HT_USART1 ((HT_USART_TypeDef *) HT_USART1_BASE) +#define HT_UART1 ((HT_USART_TypeDef *) HT_UART1_BASE) +#define HT_SPI1 ((HT_SPI_TypeDef *) HT_SPI1_BASE) +#define HT_I2C1 ((HT_I2C_TypeDef *) HT_I2C1_BASE) +#define HT_CRC ((HT_CRC_TypeDef *) HT_CRC_BASE) +#define HT_LEDC ((HT_LEDC_TypeDef *) HT_LEDC_BASE) +#define HT_DIV ((HT_DIV_TypeDef *) HT_DIV_BASE) +#define HT_CAN0 ((HT_CAN_TypeDef *) HT_CAN0_BASE) +#define HT_GPIOC ((HT_GPIO_TypeDef *) HT_GPIOC_BASE) +#define HT_GPIOD ((HT_GPIO_TypeDef *) HT_GPIOD_BASE) +#endif + +#if defined(USE_HT32F53231_41) +#define HT_PDMA ((HT_PDMA_TypeDef *) HT_PDMA_BASE) +#define HT_BFTM1 ((HT_BFTM_TypeDef *) HT_BFTM1_BASE) +#define HT_PWM0 ((HT_TM_TypeDef *) HT_PWM0_BASE) +#define HT_MCTM0 ((HT_TM_TypeDef *) HT_MCTM0_BASE) +#define HT_RTC ((HT_RTC_TypeDef *) HT_RTC_BASE) +#define HT_UART1 ((HT_USART_TypeDef *) HT_UART1_BASE) +#define HT_SPI1 ((HT_SPI_TypeDef *) HT_SPI1_BASE) +#define HT_I2C1 ((HT_I2C_TypeDef *) HT_I2C1_BASE) +#define HT_CRC ((HT_CRC_TypeDef *) HT_CRC_BASE) +#define HT_DIV ((HT_DIV_TypeDef *) HT_DIV_BASE) +#define HT_LEDC ((HT_LEDC_TypeDef *) HT_LEDC_BASE) +#define HT_CAN0 ((HT_CAN_TypeDef *) HT_CAN0_BASE) +#define HT_GPIOC ((HT_GPIO_TypeDef *) HT_GPIOC_BASE) +#define HT_GPIOD ((HT_GPIO_TypeDef *) HT_GPIOD_BASE) +#endif + +#if defined(USE_HT32F66242) +#define HT_PDMA ((HT_PDMA_TypeDef *) HT_PDMA_BASE) +#define HT_CMP0 ((HT_CMP_TypeDef *) HT_CMP0_BASE) +#define HT_CMP1 ((HT_CMP_TypeDef *) HT_CMP1_BASE) +#define HT_BFTM1 ((HT_BFTM_TypeDef *) HT_BFTM1_BASE) +#define HT_MCTM0 ((HT_TM_TypeDef *) HT_MCTM0_BASE) +#define HT_CRC ((HT_CRC_TypeDef *) HT_CRC_BASE) +#define HT_DIV ((HT_DIV_TypeDef *) HT_DIV_BASE) +#define HT_GPIOC ((HT_GPIO_TypeDef *) HT_GPIOC_BASE) +#define HT_PGA0 ((HT_PGA0_X_TypeDef *) HT_PGA0_BASE) +#define HT_PGA1 ((HT_PGA0_X_TypeDef *) HT_PGA1_BASE) +#define HT_PGA2 ((HT_PGA0_X_TypeDef *) HT_PGA2_BASE) +#define HT_PGA3 ((HT_PGA0_X_TypeDef *) HT_PGA3_BASE) +#define HT_PGA ((HT_PGA_TypeDef *) HT_PGA_BASE) +#define HT_PID ((HT_LCD_TypeDef *) HT_LCD_BASE) +#define HT_CORDIC ((HT_CORDIC_TypeDef *) HT_CORDIC_BASE) +#define HT_LSTM0 ((HT_RTC_TypeDef *) HT_RTC_BASE) + +#define HT_RTC HT_LSTM0 +#endif + +#if defined(USE_HT32F66246) +#define HT_PDMA ((HT_PDMA_TypeDef *) HT_PDMA_BASE) +#define HT_CMP0 ((HT_CMP_TypeDef *) HT_CMP0_BASE) +#define HT_CMP1 ((HT_CMP_TypeDef *) HT_CMP1_BASE) +#define HT_BFTM1 ((HT_BFTM_TypeDef *) HT_BFTM1_BASE) +#define HT_MCTM0 ((HT_TM_TypeDef *) HT_MCTM0_BASE) +#define HT_CRC ((HT_CRC_TypeDef *) HT_CRC_BASE) +#define HT_DIV ((HT_DIV_TypeDef *) HT_DIV_BASE) +#define HT_GPIOC ((HT_GPIO_TypeDef *) HT_GPIOC_BASE) +#define HT_CAN0 ((HT_CAN_TypeDef *) HT_CAN0_BASE) +#define HT_PGA0 ((HT_PGA0_X_TypeDef *) HT_PGA0_BASE) +#define HT_PGA1 ((HT_PGA0_X_TypeDef *) HT_PGA1_BASE) +#define HT_PGA2 ((HT_PGA0_X_TypeDef *) HT_PGA2_BASE) +#define HT_PGA3 ((HT_PGA0_X_TypeDef *) HT_PGA3_BASE) +#define HT_PGA ((HT_PGA_TypeDef *) HT_PGA_BASE) +#define HT_PID ((HT_LCD_TypeDef *) HT_LCD_BASE) +#define HT_CORDIC ((HT_CORDIC_TypeDef *) HT_CORDIC_BASE) +#define HT_LSTM0 ((HT_RTC_TypeDef *) HT_RTC_BASE) + +#define HT_RTC HT_LSTM0 +#endif + +#if defined(USE_HT32F52234_44) +#define HT_PDMA ((HT_PDMA_TypeDef *) HT_PDMA_BASE) +#define HT_BFTM1 ((HT_BFTM_TypeDef *) HT_BFTM1_BASE) +#define HT_PWM0 ((HT_TM_TypeDef *) HT_PWM0_BASE) +#define HT_DAC0 ((HT_DAC_TypeDef *) HT_DAC0_BASE) +#define HT_DAC1 ((HT_DAC_TypeDef *) HT_DAC1_BASE) +#define HT_I2C1 ((HT_I2C_TypeDef *) HT_I2C1_BASE) +#define HT_I2C2 ((HT_I2C_TypeDef *) HT_I2C2_BASE) +#define HT_RTC ((HT_RTC_TypeDef *) HT_RTC_BASE) +#define HT_CRC ((HT_CRC_TypeDef *) HT_CRC_BASE) +#define HT_DIV ((HT_DIV_TypeDef *) HT_DIV_BASE) +#define HT_GPIOC ((HT_GPIO_TypeDef *) HT_GPIOC_BASE) +#endif + +#if defined USE_HT32_DRIVER + #include "ht32f5xxxx_lib.h" +#endif + +/** + * @brief Adjust the value of High Speed External oscillator (HSE) + Tip: To avoid from modifying every time for different HSE, please define + the "HSE_VALUE=n000000" ("n" represents n MHz) in your own toolchain compiler preprocessor, + or edit the "HSE_VALUE" in the "ht32f5xxxx_conf.h" file. + */ +#if !defined HSE_VALUE + #if defined(USE_HT32F50220_30) || defined(USE_HT32F50231_41) + /* Available HSE_VALUE: 4 MHz ~ 20 MHz */ + #define HSE_VALUE 20000000UL /*!< Value of the External oscillator in Hz */ + #elif defined(USE_HT32F50020_30) + /* Available HSE_VALUE: 4 MHz ~ 16 MHz */ + #define HSE_VALUE 16000000UL /*!< Value of the External oscillator in Hz */ + #elif defined(USE_HT32F0006) + /* Available HSE_VALUE: 4 MHz ~ 16 MHz */ + #define HSE_VALUE 12000000UL /*!< Value of the External oscillator in Hz */ + #elif defined(USE_HT32F61244_45) + /* Available HSE_VALUE: 4 MHz ~ 16 MHz */ + #define HSE_VALUE 12000000UL /*!< Value of the External oscillator in Hz */ + #elif defined(USE_HT32F67041_51) + /* Available HSE_VALUE: 16 MHz */ + #define HSE_VALUE 16000000UL /*!< Value of the External oscillator in Hz */ + #else + /* Available HSE_VALUE: 4 MHz ~ 16 MHz */ + #define HSE_VALUE 8000000UL /*!< Value of the External oscillator in Hz */ + #endif +#endif + +/** + * @brief Define for backward compatibility + */ +#define HT_ADC HT_ADC0 +#define ADC ADC0 +#define ADC_IRQn ADC0_IRQn + +#define HT_DAC HT_DAC0 +#define AFIO_FUN_DAC AFIO_FUN_DAC0 +#define CKCU_PCLK_DAC CKCU_PCLK_DAC0 + +#if defined(USE_HT32F52357_67) + #define UART0_IRQn UART0_UART2_IRQn + #define UART2_IRQn UART0_UART2_IRQn + #define UART1_IRQn UART1_UART3_IRQn + #define UART3_IRQn UART1_UART3_IRQn +#endif + +#if defined(USE_HT32F65230_40) || defined(USE_HT32F65232) + // Alias + #define GPTM0_IRQn GPTM0_G_IRQn + #define GPTM0_IRQHandler GPTM0_G_IRQHandler + #define MCTM0_IRQn MCTM0_UP_IRQn + #define MCTM0_IRQHandler MCTM0_G_IRQHandler + #define MCTM1_IRQn MCTM1_UP_IRQn + #define MCTM1_IRQHandler MCTM1_G_IRQHandler +#endif + +#define AFIO_ESS_Enum u32 + +#if 0 // Set as 1 for backward compatibility +#if defined(USE_HT32F50020_30) +#define EXTI8_IRQn EXTI0_1_IRQn +#define EXTI9_IRQn EXTI0_1_IRQn +#define EXTI10_IRQn EXTI2_3_IRQn +#define EXTI11_IRQn EXTI2_3_IRQn +#define EXTI12_IRQn EXTI4_7_IRQn +#define EXTI13_IRQn EXTI4_7_IRQn +#define EXTI14_IRQn EXTI4_7_IRQn +#define EXTI15_IRQn EXTI4_7_IRQn + +#define EXTI_CHANNEL_8 EXTI_CHANNEL_0 +#define EXTI_CHANNEL_9 EXTI_CHANNEL_1 +#define EXTI_CHANNEL_10 EXTI_CHANNEL_2 +#define EXTI_CHANNEL_11 EXTI_CHANNEL_3 +#define EXTI_CHANNEL_12 EXTI_CHANNEL_4 +#define EXTI_CHANNEL_13 EXTI_CHANNEL_5 +#define EXTI_CHANNEL_14 EXTI_CHANNEL_6 +#define EXTI_CHANNEL_15 EXTI_CHANNEL_7 +#endif +#endif + +#if (LIBCFG_SPI_NO_MULTI_MASTER) +#define SPI_SELOutputCmd(...) +#endif + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif + + +/** + * @} + */ + +/** + * @} + */ + +/******************* (C) COPYRIGHT Holtek Semiconductor Inc. *****END OF FILE*** */ diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Include/system_ht32f0006.h b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Include/system_ht32f0006.h new file mode 100644 index 0000000000..388963ffe1 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Include/system_ht32f0006.h @@ -0,0 +1,74 @@ +/**************************************************************************//** + * @file system_ht32f0006.h + * @brief CMSIS Cortex-M0+ Device Peripheral Access Layer System Header File + * for the Holtek HT32F0006 Device + * @version $Rev:: 1725 $ + * @date $Date:: 2017-08-24 #$ + * + * @note + * Copyright (C) Holtek Semiconductor Inc. All rights reserved. + * + * @par + * ARM Limited (ARM) supplies this software for use with Cortex-M processor-based + * microcontrollers. This file can be freely distributed within development + * tools that are supporting such ARM based processors. + * + * @par + * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR + * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + ******************************************************************************/ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup HT32F5xxxx_system + * @{ + */ + + +#ifndef __SYSTEM_HT32F0006_H +#define __SYSTEM_HT32F0006_H + +#ifdef __cplusplus + extern "C" { +#endif + +/** @addtogroup HT32F0006_System_Exported_types + * @{ + */ +extern __IO uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ +/** + * @} + */ + + +/** @addtogroup HT32F0006_System_Exported_Functions + * @{ + */ +extern void SystemInit(void); +extern void SystemCoreClockUpdate(void); +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif + + +/** + * @} + */ + +/** + * @} + */ + +/******************* (C) COPYRIGHT Holtek Semiconductor Inc. *****END OF FILE*** */ diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Include/system_ht32f5826.h b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Include/system_ht32f5826.h new file mode 100644 index 0000000000..a1f54a57ca --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Include/system_ht32f5826.h @@ -0,0 +1,74 @@ +/**************************************************************************//** + * @file system_ht32f5826.h + * @brief CMSIS Cortex-M0+ Device Peripheral Access Layer System Header File + * for the Holtek HT32F5xxxx Device Series + * @version $Rev:: 1725 $ + * @date $Date:: 2017-08-24 #$ + * + * @note + * Copyright (C) Holtek Semiconductor Inc. All rights reserved. + * + * @par + * ARM Limited (ARM) supplies this software for use with Cortex-M processor-based + * microcontrollers. This file can be freely distributed within development + * tools that are supporting such ARM based processors. + * + * @par + * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR + * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + ******************************************************************************/ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup HT32F5xxxx_system + * @{ + */ + + +#ifndef __SYSTEM_HT32F5826_H +#define __SYSTEM_HT32F5826_H + +#ifdef __cplusplus + extern "C" { +#endif + +/** @addtogroup HT32F5xxxx_System_Exported_types + * @{ + */ +extern __IO uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ +/** + * @} + */ + + +/** @addtogroup HT32F5xxxx_System_Exported_Functions + * @{ + */ +extern void SystemInit(void); +extern void SystemCoreClockUpdate(void); +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif + + +/** + * @} + */ + +/** + * @} + */ + +/******************* (C) COPYRIGHT Holtek Semiconductor Inc. *****END OF FILE*** */ diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Include/system_ht32f5xxxx_01.h b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Include/system_ht32f5xxxx_01.h new file mode 100644 index 0000000000..bf83db5162 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Include/system_ht32f5xxxx_01.h @@ -0,0 +1,74 @@ +/**************************************************************************//** + * @file system_ht32f5xxxx_01.h + * @brief CMSIS Cortex-M0+ Device Peripheral Access Layer System Header File + * for the Holtek HT32F5xxxx Device Series + * @version $Rev:: 1725 $ + * @date $Date:: 2017-08-24 #$ + * + * @note + * Copyright (C) Holtek Semiconductor Inc. All rights reserved. + * + * @par + * ARM Limited (ARM) supplies this software for use with Cortex-M processor-based + * microcontrollers. This file can be freely distributed within development + * tools that are supporting such ARM based processors. + * + * @par + * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR + * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + ******************************************************************************/ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup HT32F5xxxx_system + * @{ + */ + + +#ifndef __SYSTEM_HT32F5XXXX_01_H +#define __SYSTEM_HT32F5XXXX_01_H + +#ifdef __cplusplus + extern "C" { +#endif + +/** @addtogroup HT32F5xxxx_System_Exported_types + * @{ + */ +extern __IO uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ +/** + * @} + */ + + +/** @addtogroup HT32F5xxxx_System_Exported_Functions + * @{ + */ +extern void SystemInit(void); +extern void SystemCoreClockUpdate(void); +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif + + +/** + * @} + */ + +/** + * @} + */ + +/******************* (C) COPYRIGHT Holtek Semiconductor Inc. *****END OF FILE*** */ diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Include/system_ht32f5xxxx_02.h b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Include/system_ht32f5xxxx_02.h new file mode 100644 index 0000000000..cffecbeac6 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Include/system_ht32f5xxxx_02.h @@ -0,0 +1,74 @@ +/**************************************************************************//** + * @file system_ht32f5xxxx_02.h + * @brief CMSIS Cortex-M0+ Device Peripheral Access Layer System Header File + * for the Holtek HT32F5xxxx Device Series + * @version $Rev:: 1725 $ + * @date $Date:: 2017-08-24 #$ + * + * @note + * Copyright (C) Holtek Semiconductor Inc. All rights reserved. + * + * @par + * ARM Limited (ARM) supplies this software for use with Cortex-M processor-based + * microcontrollers. This file can be freely distributed within development + * tools that are supporting such ARM based processors. + * + * @par + * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR + * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + ******************************************************************************/ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup HT32F5xxxx_system + * @{ + */ + + +#ifndef __SYSTEM_HT32F5XXXX_02_H +#define __SYSTEM_HT32F5XXXX_02_H + +#ifdef __cplusplus + extern "C" { +#endif + +/** @addtogroup HT32F5xxxx_System_Exported_types + * @{ + */ +extern __IO uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ +/** + * @} + */ + + +/** @addtogroup HT32F5xxxx_System_Exported_Functions + * @{ + */ +extern void SystemInit(void); +extern void SystemCoreClockUpdate(void); +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif + + +/** + * @} + */ + +/** + * @} + */ + +/******************* (C) COPYRIGHT Holtek Semiconductor Inc. *****END OF FILE*** */ diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Include/system_ht32f5xxxx_03.h b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Include/system_ht32f5xxxx_03.h new file mode 100644 index 0000000000..35c215726d --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Include/system_ht32f5xxxx_03.h @@ -0,0 +1,74 @@ +/**************************************************************************//** + * @file system_ht32f5xxxx_03.h + * @brief CMSIS Cortex-M0+ Device Peripheral Access Layer System Header File + * for the Holtek HT32F5xxxx Device Series + * @version $Rev:: 1725 $ + * @date $Date:: 2017-08-24 #$ + * + * @note + * Copyright (C) Holtek Semiconductor Inc. All rights reserved. + * + * @par + * ARM Limited (ARM) supplies this software for use with Cortex-M processor-based + * microcontrollers. This file can be freely distributed within development + * tools that are supporting such ARM based processors. + * + * @par + * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR + * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + ******************************************************************************/ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup HT32F5xxxx_system + * @{ + */ + + +#ifndef __SYSTEM_HT32F5XXXX_03_H +#define __SYSTEM_HT32F5XXXX_03_H + +#ifdef __cplusplus + extern "C" { +#endif + +/** @addtogroup HT32F5xxxx_System_Exported_types + * @{ + */ +extern __IO uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ +/** + * @} + */ + + +/** @addtogroup HT32F5xxxx_System_Exported_Functions + * @{ + */ +extern void SystemInit(void); +extern void SystemCoreClockUpdate(void); +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif + + +/** + * @} + */ + +/** + * @} + */ + +/******************* (C) COPYRIGHT Holtek Semiconductor Inc. *****END OF FILE*** */ diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Include/system_ht32f5xxxx_04.h b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Include/system_ht32f5xxxx_04.h new file mode 100644 index 0000000000..7ddd2dc9d9 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Include/system_ht32f5xxxx_04.h @@ -0,0 +1,74 @@ +/**************************************************************************//** + * @file system_ht32f5xxxx_04.h + * @brief CMSIS Cortex-M0+ Device Peripheral Access Layer System Header File + * for the Holtek HT32F5xxxx Device Series + * @version $Rev:: 1725 $ + * @date $Date:: 2017-08-24 #$ + * + * @note + * Copyright (C) Holtek Semiconductor Inc. All rights reserved. + * + * @par + * ARM Limited (ARM) supplies this software for use with Cortex-M processor-based + * microcontrollers. This file can be freely distributed within development + * tools that are supporting such ARM based processors. + * + * @par + * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR + * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + ******************************************************************************/ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup HT32F5xxxx_system + * @{ + */ + + +#ifndef __SYSTEM_HT32F5XXXX_04_H +#define __SYSTEM_HT32F5XXXX_04_H + +#ifdef __cplusplus + extern "C" { +#endif + +/** @addtogroup HT32F5xxxx_System_Exported_types + * @{ + */ +extern __IO uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ +/** + * @} + */ + + +/** @addtogroup HT32F5xxxx_System_Exported_Functions + * @{ + */ +extern void SystemInit(void); +extern void SystemCoreClockUpdate(void); +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif + + +/** + * @} + */ + +/** + * @} + */ + +/******************* (C) COPYRIGHT Holtek Semiconductor Inc. *****END OF FILE*** */ diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Include/system_ht32f5xxxx_05.h b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Include/system_ht32f5xxxx_05.h new file mode 100644 index 0000000000..c0ead9e7d5 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Include/system_ht32f5xxxx_05.h @@ -0,0 +1,74 @@ +/**************************************************************************//** + * @file system_ht32f5xxxx_05.h + * @brief CMSIS Cortex-M0+ Device Peripheral Access Layer System Header File + * for the Holtek HT32F5xxxx Device Series + * @version $Rev:: 1725 $ + * @date $Date:: 2017-08-24 #$ + * + * @note + * Copyright (C) Holtek Semiconductor Inc. All rights reserved. + * + * @par + * ARM Limited (ARM) supplies this software for use with Cortex-M processor-based + * microcontrollers. This file can be freely distributed within development + * tools that are supporting such ARM based processors. + * + * @par + * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR + * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + ******************************************************************************/ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup HT32F5xxxx_system + * @{ + */ + + +#ifndef __SYSTEM_HT32F5XXXX_05_H +#define __SYSTEM_HT32F5XXXX_05_H + +#ifdef __cplusplus + extern "C" { +#endif + +/** @addtogroup HT32F5xxxx_System_Exported_types + * @{ + */ +extern __IO uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ +/** + * @} + */ + + +/** @addtogroup HT32F5xxxx_System_Exported_Functions + * @{ + */ +extern void SystemInit(void); +extern void SystemCoreClockUpdate(void); +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif + + +/** + * @} + */ + +/** + * @} + */ + +/******************* (C) COPYRIGHT Holtek Semiconductor Inc. *****END OF FILE*** */ diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Include/system_ht32f5xxxx_06.h b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Include/system_ht32f5xxxx_06.h new file mode 100644 index 0000000000..e8600c85bb --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Include/system_ht32f5xxxx_06.h @@ -0,0 +1,74 @@ +/**************************************************************************//** + * @file system_ht32f5xxxx_06.h + * @brief CMSIS Cortex-M0+ Device Peripheral Access Layer System Header File + * for the Holtek HT32F5xxxx Device Series + * @version $Rev:: 1725 $ + * @date $Date:: 2017-08-24 #$ + * + * @note + * Copyright (C) Holtek Semiconductor Inc. All rights reserved. + * + * @par + * ARM Limited (ARM) supplies this software for use with Cortex-M processor-based + * microcontrollers. This file can be freely distributed within development + * tools that are supporting such ARM based processors. + * + * @par + * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR + * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + ******************************************************************************/ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup HT32F5xxxx_system + * @{ + */ + + +#ifndef __SYSTEM_HT32F5XXXX_06_H +#define __SYSTEM_HT32F5XXXX_06_H + +#ifdef __cplusplus + extern "C" { +#endif + +/** @addtogroup HT32F5xxxx_System_Exported_types + * @{ + */ +extern __IO uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ +/** + * @} + */ + + +/** @addtogroup HT32F5xxxx_System_Exported_Functions + * @{ + */ +extern void SystemInit(void); +extern void SystemCoreClockUpdate(void); +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif + + +/** + * @} + */ + +/** + * @} + */ + +/******************* (C) COPYRIGHT Holtek Semiconductor Inc. *****END OF FILE*** */ diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Include/system_ht32f5xxxx_07.h b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Include/system_ht32f5xxxx_07.h new file mode 100644 index 0000000000..30a451c6c1 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Include/system_ht32f5xxxx_07.h @@ -0,0 +1,74 @@ +/**************************************************************************//** + * @file system_ht32f5xxxx_07.h + * @brief CMSIS Cortex-M0+ Device Peripheral Access Layer System Header File + * for the Holtek HT32F5xxxx Device Series + * @version $Rev:: 1725 $ + * @date $Date:: 2017-08-24 #$ + * + * @note + * Copyright (C) Holtek Semiconductor Inc. All rights reserved. + * + * @par + * ARM Limited (ARM) supplies this software for use with Cortex-M processor-based + * microcontrollers. This file can be freely distributed within development + * tools that are supporting such ARM based processors. + * + * @par + * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR + * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + ******************************************************************************/ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup HT32F5xxxx_system + * @{ + */ + + +#ifndef __SYSTEM_HT32F5XXXX_07_H +#define __SYSTEM_HT32F5XXXX_07_H + +#ifdef __cplusplus + extern "C" { +#endif + +/** @addtogroup HT32F5xxxx_System_Exported_types + * @{ + */ +extern __IO uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ +/** + * @} + */ + + +/** @addtogroup HT32F5xxxx_System_Exported_Functions + * @{ + */ +extern void SystemInit(void); +extern void SystemCoreClockUpdate(void); +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif + + +/** + * @} + */ + +/** + * @} + */ + +/******************* (C) COPYRIGHT Holtek Semiconductor Inc. *****END OF FILE*** */ diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Include/system_ht32f5xxxx_08.h b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Include/system_ht32f5xxxx_08.h new file mode 100644 index 0000000000..5f982d45b9 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Include/system_ht32f5xxxx_08.h @@ -0,0 +1,74 @@ +/**************************************************************************//** + * @file system_ht32f5xxxx_08.h + * @brief CMSIS Cortex-M0+ Device Peripheral Access Layer System Header File + * for the Holtek HT32F5xxxx Device Series + * @version $Rev:: 1725 $ + * @date $Date:: 2017-08-24 #$ + * + * @note + * Copyright (C) Holtek Semiconductor Inc. All rights reserved. + * + * @par + * ARM Limited (ARM) supplies this software for use with Cortex-M processor-based + * microcontrollers. This file can be freely distributed within development + * tools that are supporting such ARM based processors. + * + * @par + * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR + * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + ******************************************************************************/ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup HT32F5xxxx_system + * @{ + */ + + +#ifndef __SYSTEM_HT32F5XXXX_08_H +#define __SYSTEM_HT32F5XXXX_08_H + +#ifdef __cplusplus + extern "C" { +#endif + +/** @addtogroup HT32F5xxxx_System_Exported_types + * @{ + */ +extern __IO uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ +/** + * @} + */ + + +/** @addtogroup HT32F5xxxx_System_Exported_Functions + * @{ + */ +extern void SystemInit(void); +extern void SystemCoreClockUpdate(void); +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif + + +/** + * @} + */ + +/** + * @} + */ + +/******************* (C) COPYRIGHT Holtek Semiconductor Inc. *****END OF FILE*** */ diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Include/system_ht32f5xxxx_09.h b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Include/system_ht32f5xxxx_09.h new file mode 100644 index 0000000000..85528c095c --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Include/system_ht32f5xxxx_09.h @@ -0,0 +1,74 @@ +/**************************************************************************//** + * @file system_ht32f5xxxx_09.h + * @brief CMSIS Cortex-M0+ Device Peripheral Access Layer System Header File + * for the Holtek HT32F5xxxx Device Series + * @version $Rev:: 1725 $ + * @date $Date:: 2017-08-24 #$ + * + * @note + * Copyright (C) Holtek Semiconductor Inc. All rights reserved. + * + * @par + * ARM Limited (ARM) supplies this software for use with Cortex-M processor-based + * microcontrollers. This file can be freely distributed within development + * tools that are supporting such ARM based processors. + * + * @par + * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR + * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + ******************************************************************************/ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup HT32F5xxxx_system + * @{ + */ + + +#ifndef __SYSTEM_HT32F5XXXX_09_H +#define __SYSTEM_HT32F5XXXX_09_H + +#ifdef __cplusplus + extern "C" { +#endif + +/** @addtogroup HT32F5xxxx_System_Exported_types + * @{ + */ +extern __IO uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ +/** + * @} + */ + + +/** @addtogroup HT32F5xxxx_System_Exported_Functions + * @{ + */ +extern void SystemInit(void); +extern void SystemCoreClockUpdate(void); +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif + + +/** + * @} + */ + +/** + * @} + */ + +/******************* (C) COPYRIGHT Holtek Semiconductor Inc. *****END OF FILE*** */ diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Include/system_ht32f5xxxx_10.h b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Include/system_ht32f5xxxx_10.h new file mode 100644 index 0000000000..8ae7e67c9e --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Include/system_ht32f5xxxx_10.h @@ -0,0 +1,74 @@ +/**************************************************************************//** + * @file system_ht32f5xxxx_10.h + * @brief CMSIS Cortex-M0+ Device Peripheral Access Layer System Header File + * for the Holtek HT32F5xxxx Device Series + * @version $Rev:: 1725 $ + * @date $Date:: 2017-08-24 #$ + * + * @note + * Copyright (C) Holtek Semiconductor Inc. All rights reserved. + * + * @par + * ARM Limited (ARM) supplies this software for use with Cortex-M processor-based + * microcontrollers. This file can be freely distributed within development + * tools that are supporting such ARM based processors. + * + * @par + * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR + * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + ******************************************************************************/ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup HT32F5xxxx_system + * @{ + */ + + +#ifndef __SYSTEM_HT32F5XXXX_10_H +#define __SYSTEM_HT32F5XXXX_10_H + +#ifdef __cplusplus + extern "C" { +#endif + +/** @addtogroup HT32F5xxxx_System_Exported_types + * @{ + */ +extern __IO uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ +/** + * @} + */ + + +/** @addtogroup HT32F5xxxx_System_Exported_Functions + * @{ + */ +extern void SystemInit(void); +extern void SystemCoreClockUpdate(void); +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif + + +/** + * @} + */ + +/** + * @} + */ + +/******************* (C) COPYRIGHT Holtek Semiconductor Inc. *****END OF FILE*** */ diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Include/system_ht32f5xxxx_11.h b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Include/system_ht32f5xxxx_11.h new file mode 100644 index 0000000000..c9a7e04c33 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Include/system_ht32f5xxxx_11.h @@ -0,0 +1,74 @@ +/**************************************************************************//** + * @file system_ht32f5xxxx_11.h + * @brief CMSIS Cortex-M0+ Device Peripheral Access Layer System Header File + * for the Holtek HT32F5xxxx Device Series + * @version $Rev:: 1725 $ + * @date $Date:: 2017-08-24 #$ + * + * @note + * Copyright (C) Holtek Semiconductor Inc. All rights reserved. + * + * @par + * ARM Limited (ARM) supplies this software for use with Cortex-M processor-based + * microcontrollers. This file can be freely distributed within development + * tools that are supporting such ARM based processors. + * + * @par + * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR + * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + ******************************************************************************/ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup HT32F5xxxx_system + * @{ + */ + + +#ifndef __SYSTEM_HT32F5XXXX_11_H +#define __SYSTEM_HT32F5XXXX_11_H + +#ifdef __cplusplus + extern "C" { +#endif + +/** @addtogroup HT32F5xxxx_System_Exported_types + * @{ + */ +extern __IO uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ +/** + * @} + */ + + +/** @addtogroup HT32F5xxxx_System_Exported_Functions + * @{ + */ +extern void SystemInit(void); +extern void SystemCoreClockUpdate(void); +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif + + +/** + * @} + */ + +/** + * @} + */ + +/******************* (C) COPYRIGHT Holtek Semiconductor Inc. *****END OF FILE*** */ diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Include/system_ht32f5xxxx_12.h b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Include/system_ht32f5xxxx_12.h new file mode 100644 index 0000000000..0f4983569e --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Include/system_ht32f5xxxx_12.h @@ -0,0 +1,74 @@ +/**************************************************************************//** + * @file system_ht32f5xxxx_12.h + * @brief CMSIS Cortex-M0+ Device Peripheral Access Layer System Header File + * for the Holtek HT32F5xxxx Device Series + * @version $Rev:: 1725 $ + * @date $Date:: 2017-08-24 #$ + * + * @note + * Copyright (C) Holtek Semiconductor Inc. All rights reserved. + * + * @par + * ARM Limited (ARM) supplies this software for use with Cortex-M processor-based + * microcontrollers. This file can be freely distributed within development + * tools that are supporting such ARM based processors. + * + * @par + * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR + * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + ******************************************************************************/ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup HT32F5xxxx_system + * @{ + */ + + +#ifndef __SYSTEM_HT32F5XXXX_12_H +#define __SYSTEM_HT32F5XXXX_12_H + +#ifdef __cplusplus + extern "C" { +#endif + +/** @addtogroup HT32F5xxxx_System_Exported_types + * @{ + */ +extern __IO uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ +/** + * @} + */ + + +/** @addtogroup HT32F5xxxx_System_Exported_Functions + * @{ + */ +extern void SystemInit(void); +extern void SystemCoreClockUpdate(void); +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif + + +/** + * @} + */ + +/** + * @} + */ + +/******************* (C) COPYRIGHT Holtek Semiconductor Inc. *****END OF FILE*** */ diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Include/system_ht32f5xxxx_13.h b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Include/system_ht32f5xxxx_13.h new file mode 100644 index 0000000000..8176285eea --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Include/system_ht32f5xxxx_13.h @@ -0,0 +1,74 @@ +/**************************************************************************//** + * @file system_ht32f5xxxx_13.h + * @brief CMSIS Cortex-M0+ Device Peripheral Access Layer System Header File + * for the Holtek HT32F5xxxx Device Series + * @version $Rev:: 1725 $ + * @date $Date:: 2017-08-24 #$ + * + * @note + * Copyright (C) Holtek Semiconductor Inc. All rights reserved. + * + * @par + * ARM Limited (ARM) supplies this software for use with Cortex-M processor-based + * microcontrollers. This file can be freely distributed within development + * tools that are supporting such ARM based processors. + * + * @par + * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR + * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + ******************************************************************************/ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup HT32F5xxxx_system + * @{ + */ + + +#ifndef __SYSTEM_HT32F5XXXX_13_H +#define __SYSTEM_HT32F5XXXX_13_H + +#ifdef __cplusplus + extern "C" { +#endif + +/** @addtogroup HT32F5xxxx_System_Exported_types + * @{ + */ +extern __IO uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ +/** + * @} + */ + + +/** @addtogroup HT32F5xxxx_System_Exported_Functions + * @{ + */ +extern void SystemInit(void); +extern void SystemCoreClockUpdate(void); +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif + + +/** + * @} + */ + +/** + * @} + */ + +/******************* (C) COPYRIGHT Holtek Semiconductor Inc. *****END OF FILE*** */ diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Include/system_ht32f5xxxx_14.h b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Include/system_ht32f5xxxx_14.h new file mode 100644 index 0000000000..042adba38d --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Include/system_ht32f5xxxx_14.h @@ -0,0 +1,74 @@ +/**************************************************************************//** + * @file system_ht32f5xxxx_14.h + * @brief CMSIS Cortex-M0+ Device Peripheral Access Layer System Header File + * for the Holtek HT32F5xxxx Device Series + * @version $Rev:: 1725 $ + * @date $Date:: 2017-08-24 #$ + * + * @note + * Copyright (C) Holtek Semiconductor Inc. All rights reserved. + * + * @par + * ARM Limited (ARM) supplies this software for use with Cortex-M processor-based + * microcontrollers. This file can be freely distributed within development + * tools that are supporting such ARM based processors. + * + * @par + * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR + * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + ******************************************************************************/ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup HT32F5xxxx_system + * @{ + */ + + +#ifndef __SYSTEM_HT32F5XXXX_14_H +#define __SYSTEM_HT32F5XXXX_14_H + +#ifdef __cplusplus + extern "C" { +#endif + +/** @addtogroup HT32F5xxxx_System_Exported_types + * @{ + */ +extern __IO uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ +/** + * @} + */ + + +/** @addtogroup HT32F5xxxx_System_Exported_Functions + * @{ + */ +extern void SystemInit(void); +extern void SystemCoreClockUpdate(void); +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif + + +/** + * @} + */ + +/** + * @} + */ + +/******************* (C) COPYRIGHT Holtek Semiconductor Inc. *****END OF FILE*** */ diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Include/system_ht32f5xxxx_15.h b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Include/system_ht32f5xxxx_15.h new file mode 100644 index 0000000000..f6d6fc1787 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Include/system_ht32f5xxxx_15.h @@ -0,0 +1,74 @@ +/**************************************************************************//** + * @file system_ht32f5xxxx_15.h + * @brief CMSIS Cortex-M0+ Device Peripheral Access Layer System Header File + * for the Holtek HT32F5xxxx Device Series + * @version $Rev:: 1725 $ + * @date $Date:: 2017-08-24 #$ + * + * @note + * Copyright (C) Holtek Semiconductor Inc. All rights reserved. + * + * @par + * ARM Limited (ARM) supplies this software for use with Cortex-M processor-based + * microcontrollers. This file can be freely distributed within development + * tools that are supporting such ARM based processors. + * + * @par + * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR + * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + ******************************************************************************/ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup HT32F5xxxx_system + * @{ + */ + + +#ifndef __SYSTEM_HT32F5XXXX_15_H +#define __SYSTEM_HT32F5XXXX_15_H + +#ifdef __cplusplus + extern "C" { +#endif + +/** @addtogroup HT32F5xxxx_System_Exported_types + * @{ + */ +extern __IO uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ +/** + * @} + */ + + +/** @addtogroup HT32F5xxxx_System_Exported_Functions + * @{ + */ +extern void SystemInit(void); +extern void SystemCoreClockUpdate(void); +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif + + +/** + * @} + */ + +/** + * @} + */ + +/******************* (C) COPYRIGHT Holtek Semiconductor Inc. *****END OF FILE*** */ diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Include/system_ht32f5xxxx_16.h b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Include/system_ht32f5xxxx_16.h new file mode 100644 index 0000000000..ca845b0ea3 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Include/system_ht32f5xxxx_16.h @@ -0,0 +1,74 @@ +/**************************************************************************//** + * @file system_ht32f5xxxx_16.h + * @brief CMSIS Cortex-M0+ Device Peripheral Access Layer System Header File + * for the Holtek HT32F5xxxx Device Series + * @version $Rev:: 1725 $ + * @date $Date:: 2017-08-24 #$ + * + * @note + * Copyright (C) Holtek Semiconductor Inc. All rights reserved. + * + * @par + * ARM Limited (ARM) supplies this software for use with Cortex-M processor-based + * microcontrollers. This file can be freely distributed within development + * tools that are supporting such ARM based processors. + * + * @par + * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR + * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + ******************************************************************************/ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup HT32F5xxxx_system + * @{ + */ + + +#ifndef __SYSTEM_HT32F5XXXX_16_H +#define __SYSTEM_HT32F5XXXX_16_H + +#ifdef __cplusplus + extern "C" { +#endif + +/** @addtogroup HT32F5xxxx_System_Exported_types + * @{ + */ +extern __IO uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ +/** + * @} + */ + + +/** @addtogroup HT32F5xxxx_System_Exported_Functions + * @{ + */ +extern void SystemInit(void); +extern void SystemCoreClockUpdate(void); +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif + + +/** + * @} + */ + +/** + * @} + */ + +/******************* (C) COPYRIGHT Holtek Semiconductor Inc. *****END OF FILE*** */ diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Include/system_ht32f5xxxx_17.h b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Include/system_ht32f5xxxx_17.h new file mode 100644 index 0000000000..ecf72bd705 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Include/system_ht32f5xxxx_17.h @@ -0,0 +1,74 @@ +/**************************************************************************//** + * @file system_ht32f5xxxx_17.h + * @brief CMSIS Cortex-M0+ Device Peripheral Access Layer System Header File + * for the Holtek HT32F5xxxx Device Series + * @version $Rev:: 1725 $ + * @date $Date:: 2017-08-24 #$ + * + * @note + * Copyright (C) Holtek Semiconductor Inc. All rights reserved. + * + * @par + * ARM Limited (ARM) supplies this software for use with Cortex-M processor-based + * microcontrollers. This file can be freely distributed within development + * tools that are supporting such ARM based processors. + * + * @par + * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR + * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + ******************************************************************************/ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup HT32F5xxxx_system + * @{ + */ + + +#ifndef __SYSTEM_HT32F5XXXX_17_H +#define __SYSTEM_HT32F5XXXX_17_H + +#ifdef __cplusplus + extern "C" { +#endif + +/** @addtogroup HT32F5xxxx_System_Exported_types + * @{ + */ +extern __IO uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ +/** + * @} + */ + + +/** @addtogroup HT32F5xxxx_System_Exported_Functions + * @{ + */ +extern void SystemInit(void); +extern void SystemCoreClockUpdate(void); +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif + + +/** + * @} + */ + +/** + * @} + */ + +/******************* (C) COPYRIGHT Holtek Semiconductor Inc. *****END OF FILE*** */ diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Include/system_ht32f5xxxx_18.h b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Include/system_ht32f5xxxx_18.h new file mode 100644 index 0000000000..73ba94f18a --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Include/system_ht32f5xxxx_18.h @@ -0,0 +1,74 @@ +/**************************************************************************//** + * @file system_ht32f5xxxx_18.h + * @brief CMSIS Cortex-M0+ Device Peripheral Access Layer System Header File + * for the Holtek HT32F5xxxx Device Series + * @version $Rev:: 7408 $ + * @date $Date:: 2023-12-14 #$ + * + * @note + * Copyright (C) Holtek Semiconductor Inc. All rights reserved. + * + * @par + * ARM Limited (ARM) supplies this software for use with Cortex-M processor-based + * microcontrollers. This file can be freely distributed within development + * tools that are supporting such ARM based processors. + * + * @par + * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR + * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + ******************************************************************************/ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup HT32F5xxxx_system + * @{ + */ + + +#ifndef __SYSTEM_HT32F5XXXX_18_H +#define __SYSTEM_HT32F5XXXX_18_H + +#ifdef __cplusplus + extern "C" { +#endif + +/** @addtogroup HT32F5xxxx_System_Exported_types + * @{ + */ +extern __IO uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ +/** + * @} + */ + + +/** @addtogroup HT32F5xxxx_System_Exported_Functions + * @{ + */ +extern void SystemInit(void); +extern void SystemCoreClockUpdate(void); +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif + + +/** + * @} + */ + +/** + * @} + */ + +/******************* (C) COPYRIGHT Holtek Semiconductor Inc. *****END OF FILE*** */ diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_hf5032.s b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_hf5032.s new file mode 100644 index 0000000000..a86606d966 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_hf5032.s @@ -0,0 +1,327 @@ +;/*---------------------------------------------------------------------------------------------------------*/ +;/* Holtek Semiconductor Inc. */ +;/* */ +;/* Copyright (C) Holtek Semiconductor Inc. */ +;/* All rights reserved. */ +;/* */ +;/*----------------------------------------------------------------------------------------------------------- +; File Name : startup_ht32f5xxxx_02.s +; Version : $Rev:: 7119 $ +; Date : $Date:: 2023-08-15 #$ +; Description : Startup code. +;-----------------------------------------------------------------------------------------------------------*/ + +; Supported Device +; ======================================== +; HT32F50220, HT32F50230 +; HT32F50231, HT32F50241 +; HT50F32002 +; HT32F59041 +; HF5032 +; HT32F61641 +; HT32F59046 +; HT32F61041 + +;/* <<< Use Configuration Wizard in Context Menu >>> */ + +;// HT32 Device +;// Select HT32 Device for the assembly setting. +;// Notice that the project's Asm Define has the higher priority. +;// <0=> By Project Asm Define +;// <7=> HT32F50220/30 +;// <8=> HT32F50231/41 +;// <7=> HT50F32002 +;// <8=> HT32F59041 +;// <7=> HF5032 +;// <8=> HT32F61641 +;// <8=> HT32F59046 +;// <8=> HT32F61041 +USE_HT32_CHIP_SET EQU 7 ; Notice that the project's Asm Define has the higher priority. + +_HT32FWID EQU 0xFFFFFFFF +;_HT32FWID EQU 0x00050220 +;_HT32FWID EQU 0x00050230 +;_HT32FWID EQU 0x00050231 +;_HT32FWID EQU 0x00050241 +;_HT32FWID EQU 0x00032002 +;_HT32FWID EQU 0x00059041 +;_HT32FWID EQU 0x000F5032 +;_HT32FWID EQU 0x00061641 +;_HT32FWID EQU 0x00059046 +;_HT32FWID EQU 0x00061041 + +HT32F50220_30 EQU 7 +HT32F50231_41 EQU 8 +HT50F32002 EQU 7 +HT32F59041 EQU 8 +HF5032 EQU 7 +HT32F61641 EQU 8 +HT32F59046 EQU 8 +HT32F61041 EQU 8 + + IF USE_HT32_CHIP_SET=0 + ; Use project's Asm Define setting (default) + ELSE + IF :DEF:USE_HT32_CHIP + ; Use project's Asm Define setting (higher priority than the "USE_HT32_CHIP_SET") + ELSE + ; Use "USE_HT32_CHIP_SET" in the "startup_ht32xxxxx_xx.s" file +USE_HT32_CHIP EQU USE_HT32_CHIP_SET + ENDIF + ENDIF + +; Amount of memory (in bytes) allocated for Stack and Heap +; Tailor those values to your application needs +;// Stack Size (in Bytes, must 8 byte aligned) <0-4096:8> +Stack_Size EQU 512 + + AREA STACK, NOINIT, READWRITE, ALIGN = 3 +__HT_check_sp +Stack_Mem SPACE Stack_Size +__initial_sp + +;// Heap Size (in Bytes) <0-4096:8> +Heap_Size EQU 0 + + AREA HEAP, NOINIT, READWRITE, ALIGN = 3 +__HT_check_heap +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + PRESERVE8 + THUMB + +;******************************************************************************* +; Fill-up the Vector Table entries with the exceptions ISR address +;******************************************************************************* + AREA RESET, CODE, READONLY + EXPORT __Vectors +_RESERVED EQU 0xFFFFFFFF +__Vectors + DCD __initial_sp ; ---, 00, 0x000, Top address of Stack + DCD Reset_Handler ; ---, 01, 0x004, Reset Handler + DCD NMI_Handler ; -14, 02, 0x008, NMI Handler + DCD HardFault_Handler ; -13, 03, 0x00C, Hard Fault Handler + DCD _RESERVED ; ---, 04, 0x010, Reserved + DCD _RESERVED ; ---, 05, 0x014, Reserved + DCD _RESERVED ; ---, 06, 0x018, Reserved + DCD _RESERVED ; ---, 07, 0x01C, Reserved + DCD _HT32FWID ; ---, 08, 0x020, Reserved + DCD _RESERVED ; ---, 09, 0x024, Reserved + DCD _RESERVED ; ---, 10, 0x028, Reserved + DCD SVC_Handler ; -05, 11, 0x02C, SVC Handler + DCD _RESERVED ; ---, 12, 0x030, Reserved + DCD _RESERVED ; ---, 13, 0x034, Reserved + DCD PendSV_Handler ; -02, 14, 0x038, PendSV Handler + DCD SysTick_Handler ; -01, 15, 0x03C, SysTick Handler + + ; External Interrupt Handler + DCD LVD_BOD_IRQHandler ; 00, 16, 0x040, + DCD RTC_IRQHandler ; 01, 17, 0x044, + DCD FLASH_IRQHandler ; 02, 18, 0x048, + DCD EVWUP_IRQHandler ; 03, 19, 0x04C, + DCD EXTI0_1_IRQHandler ; 04, 20, 0x050, + DCD EXTI2_3_IRQHandler ; 05, 21, 0x054, + DCD EXTI4_15_IRQHandler ; 06, 22, 0x058, + DCD _RESERVED ; 07, 23, 0x05C, + DCD ADC_IRQHandler ; 08, 24, 0x060, + DCD _RESERVED ; 09, 25, 0x064, + IF (USE_HT32_CHIP=HT32F50220_30) + DCD _RESERVED ; 10, 26, 0x068, + ELSE + DCD MCTM0_IRQHandler ; 10, 26, 0x068, + ENDIF + DCD _RESERVED ; 11, 27, 0x06C, + DCD GPTM0_IRQHandler ; 12, 28, 0x070, + DCD _RESERVED ; 13, 29, 0x074, + DCD _RESERVED ; 14, 30, 0x078, + DCD PWM0_IRQHandler ; 15, 31, 0x07C, + DCD PWM1_IRQHandler ; 16, 32, 0x080, + DCD BFTM0_IRQHandler ; 17, 33, 0x084, + IF (USE_HT32_CHIP=HT32F50220_30) + DCD _RESERVED ; 18, 34, 0x088, + ELSE + DCD BFTM1_IRQHandler ; 18, 34, 0x088, + ENDIF + DCD I2C0_IRQHandler ; 19, 35, 0x08C, + IF (USE_HT32_CHIP=HT32F50220_30) + DCD _RESERVED ; 20, 36, 0x090, + ELSE + DCD I2C1_IRQHandler ; 20, 36, 0x090, + ENDIF + DCD SPI0_IRQHandler ; 21, 37, 0x094, + DCD SPI1_IRQHandler ; 22, 38, 0x098, + IF (USE_HT32_CHIP=HT32F50220_30) + DCD _RESERVED ; 23, 39, 0x09C, + ELSE + DCD USART0_IRQHandler ; 23, 39, 0x09C, + ENDIF + DCD _RESERVED ; 24, 40, 0x0A0, + DCD UART0_IRQHandler ; 25, 41, 0x0A4, + DCD UART1_IRQHandler ; 26, 42, 0x0A8, + +; Reset handler routine +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + LDR R0, =BootProcess + BLX R0 + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +BootProcess PROC + LDR R0, =0x40080300 + LDR R1,[R0, #0x10] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x14] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x18] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x1C] + CMP R1, #0 + BEQ BP2 +BP1 LDR R0, =0x40080180 + LDR R1,[R0, #0xC] + LSLS R1, R1, #4 + LSRS R1, R1, #20 + CMP R1, #0 + BEQ BP3 + CMP R1, #5 + BEQ BP3 + CMP R1, #6 + BEQ BP3 +BP2 DSB + LDR R0, =0x20000000 + LDR R1, =0x05fa0004 + STR R1, [R0] + LDR R1, =0xe000ed00 + LDR R0, =0x05fa0004 + STR R0, [R1, #0xC] + DSB + B . +BP3 LDR R0, =0x20000000 + LDR R1, [R0] + LDR R0, =0x05fa0004 + CMP R0, R1 + BEQ BP4 + BX LR +BP4 LDR R0, =0x40088100 + LDR R1, =0x00000001 + STR R1, [R0] + LDR R0, =0x20000000 + LDR R1, =0x0 + STR R1, [R0] + BX LR + ENDP + +; Dummy Exception Handlers +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP + +HardFault_Handler PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP + +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP + +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP + +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + EXPORT LVD_BOD_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT EVWUP_IRQHandler [WEAK] + EXPORT EXTI0_1_IRQHandler [WEAK] + EXPORT EXTI2_3_IRQHandler [WEAK] + EXPORT EXTI4_15_IRQHandler [WEAK] + EXPORT ADC_IRQHandler [WEAK] + EXPORT MCTM0_IRQHandler [WEAK] + EXPORT GPTM0_IRQHandler [WEAK] + EXPORT PWM0_IRQHandler [WEAK] + EXPORT PWM1_IRQHandler [WEAK] + EXPORT BFTM0_IRQHandler [WEAK] + EXPORT BFTM1_IRQHandler [WEAK] + EXPORT I2C0_IRQHandler [WEAK] + EXPORT I2C1_IRQHandler [WEAK] + EXPORT SPI0_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT USART0_IRQHandler [WEAK] + EXPORT UART0_IRQHandler [WEAK] + EXPORT UART1_IRQHandler [WEAK] + +LVD_BOD_IRQHandler +RTC_IRQHandler +FLASH_IRQHandler +EVWUP_IRQHandler +EXTI0_1_IRQHandler +EXTI2_3_IRQHandler +EXTI4_15_IRQHandler +ADC_IRQHandler +MCTM0_IRQHandler +GPTM0_IRQHandler +PWM0_IRQHandler +PWM1_IRQHandler +BFTM0_IRQHandler +BFTM1_IRQHandler +I2C0_IRQHandler +I2C1_IRQHandler +SPI0_IRQHandler +SPI1_IRQHandler +USART0_IRQHandler +UART0_IRQHandler +UART1_IRQHandler + B . + ENDP + + ALIGN + +;******************************************************************************* +; User Stack and Heap initialization +;******************************************************************************* + IF :DEF:__MICROLIB + + EXPORT __HT_check_heap + EXPORT __HT_check_sp + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, = (Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + + ENDIF + + END diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f0006.s b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f0006.s new file mode 100644 index 0000000000..e0b5ba76e2 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f0006.s @@ -0,0 +1,304 @@ +;/*---------------------------------------------------------------------------------------------------------*/ +;/* Holtek Semiconductor Inc. */ +;/* */ +;/* Copyright (C) Holtek Semiconductor Inc. */ +;/* All rights reserved. */ +;/* */ +;/*----------------------------------------------------------------------------------------------------------- +; File Name : startup_ht32f5xxxx_07.s +; Version : $Rev:: 5740 $ +; Date : $Date:: 2022-02-17 #$ +; Description : Startup code. +;-----------------------------------------------------------------------------------------------------------*/ + +; Supported Device +; ======================================== +; HT32F0006 +; HT32F61352 +; HT32F61355, HT32F61356, HT32F61357 + +;/* <<< Use Configuration Wizard in Context Menu >>> */ + +;// HT32 Device +;// Select HT32 Device for the assembly setting. +;// Notice that the project's Asm Define has the higher priority. +;// <0=> By Project Asm Define +;// <10=> HT32F0006 +;// <10=> HT32F61352 +;// <17=> HT32F61355/56/57 +USE_HT32_CHIP_SET EQU 10 ; Notice that the project's Asm Define has the higher priority. + +_HT32FWID EQU 0xFFFFFFFF +;_HT32FWID EQU 0x00000006 +;_HT32FWID EQU 0x00061352 +;_HT32FWID EQU 0x00061355 +;_HT32FWID EQU 0x00061356 +;_HT32FWID EQU 0x00061357 + +HT32F0006 EQU 10 +HT32F61352 EQU 10 +HT32F61355_56_57 EQU 17 + + IF USE_HT32_CHIP_SET=0 + ; Use project's Asm Define setting (default) + ELSE + IF :DEF:USE_HT32_CHIP + ; Use project's Asm Define setting (higher priority than the "USE_HT32_CHIP_SET") + ELSE + ; Use "USE_HT32_CHIP_SET" in the "startup_ht32xxxxx_xx.s" file +USE_HT32_CHIP EQU USE_HT32_CHIP_SET + ENDIF + ENDIF + +; Amount of memory (in bytes) allocated for Stack and Heap +; Tailor those values to your application needs +;// Stack Size (in Bytes, must 8 byte aligned) <0-16384:8> +Stack_Size EQU 512 + + AREA STACK, NOINIT, READWRITE, ALIGN = 3 +__HT_check_sp +Stack_Mem SPACE Stack_Size +__initial_sp + +;// Heap Size (in Bytes) <0-16384:8> +Heap_Size EQU 0 + + AREA HEAP, NOINIT, READWRITE, ALIGN = 3 +__HT_check_heap +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + PRESERVE8 + THUMB + +;******************************************************************************* +; Fill-up the Vector Table entries with the exceptions ISR address +;******************************************************************************* + AREA RESET, CODE, READONLY + EXPORT __Vectors +_RESERVED EQU 0xFFFFFFFF +__Vectors + DCD __initial_sp ; ---, 00, 0x000, Top address of Stack + DCD Reset_Handler ; ---, 01, 0x004, Reset Handler + DCD NMI_Handler ; -14, 02, 0x008, NMI Handler + DCD HardFault_Handler ; -13, 03, 0x00C, Hard Fault Handler + DCD _RESERVED ; ---, 04, 0x010, Reserved + DCD _RESERVED ; ---, 05, 0x014, Reserved + DCD _RESERVED ; ---, 06, 0x018, Reserved + DCD _RESERVED ; ---, 07, 0x01C, Reserved + DCD _HT32FWID ; ---, 08, 0x020, Reserved + DCD _RESERVED ; ---, 09, 0x024, Reserved + DCD _RESERVED ; ---, 10, 0x028, Reserved + DCD SVC_Handler ; -05, 11, 0x02C, SVC Handler + DCD _RESERVED ; ---, 12, 0x030, Reserved + DCD _RESERVED ; ---, 13, 0x034, Reserved + DCD PendSV_Handler ; -02, 14, 0x038, PendSV Handler + DCD SysTick_Handler ; -01, 15, 0x03C, SysTick Handler + + ; External Interrupt Handler + DCD LVD_BOD_IRQHandler ; 00, 16, 0x040, + DCD RTC_IRQHandler ; 01, 17, 0x044, + DCD FLASH_IRQHandler ; 02, 18, 0x048, + DCD EVWUP_IRQHandler ; 03, 19, 0x04C, + DCD EXTI0_1_IRQHandler ; 04, 20, 0x050, + DCD EXTI2_3_IRQHandler ; 05, 21, 0x054, + DCD EXTI4_15_IRQHandler ; 06, 22, 0x058, + DCD _RESERVED ; 07, 23, 0x05C, + DCD ADC_IRQHandler ; 08, 24, 0x060, + DCD _RESERVED ; 09, 25, 0x064, + DCD _RESERVED ; 10, 26, 0x068, + DCD _RESERVED ; 11, 27, 0x06C, + DCD GPTM0_IRQHandler ; 12, 28, 0x070, + DCD SCTM0_IRQHandler ; 13, 29, 0x074, + DCD SCTM1_IRQHandler ; 14, 30, 0x078, + DCD SCTM2_IRQHandler ; 15, 31, 0x07C, + DCD SCTM3_IRQHandler ; 16, 32, 0x080, + DCD BFTM0_IRQHandler ; 17, 33, 0x084, + DCD BFTM1_IRQHandler ; 18, 34, 0x088, + DCD I2C0_IRQHandler ; 19, 35, 0x08C, + DCD _RESERVED ; 20, 36, 0x090, + DCD SPI0_IRQHandler ; 21, 37, 0x094, + DCD QSPI_IRQHandler ; 22, 38, 0x098, + DCD USART0_IRQHandler ; 23, 39, 0x09C, + DCD _RESERVED ; 24, 40, 0x0A0, + DCD UART0_IRQHandler ; 25, 41, 0x0A4, + DCD _RESERVED ; 26, 42, 0x0A8, + DCD MIDI_IRQHandler ; 27, 43, 0x0AC, + DCD I2S_IRQHandler ; 28, 44, 0x0B0, + DCD USB_IRQHandler ; 29, 45, 0x0B4, + DCD PDMA_CH0_1_IRQHandler ; 30, 46, 0x0B8, + DCD PDMA_CH2_5_IRQHandler ; 31, 47, 0x0BC, + +; Reset handler routine +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + LDR R0, =BootProcess + BLX R0 + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +BootProcess PROC + LDR R0, =0x40080300 + LDR R1,[R0, #0x10] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x14] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x18] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x1C] + CMP R1, #0 + BEQ BP2 +BP1 LDR R0, =0x40080180 + LDR R1,[R0, #0xC] + LSLS R1, R1, #4 + LSRS R1, R1, #20 + CMP R1, #0 + BEQ BP3 + CMP R1, #5 + BEQ BP3 + CMP R1, #6 + BEQ BP3 +BP2 DSB + LDR R0, =0x20000000 + LDR R1, =0x05fa0004 + STR R1, [R0] + LDR R1, =0xe000ed00 + LDR R0, =0x05fa0004 + STR R0, [R1, #0xC] + DSB + B . +BP3 LDR R0, =0x20000000 + LDR R1, [R0] + LDR R0, =0x05fa0004 + CMP R0, R1 + BEQ BP4 + BX LR +BP4 LDR R0, =0x40088100 + LDR R1, =0x00000001 + STR R1, [R0] + LDR R0, =0x20000000 + LDR R1, =0x0 + STR R1, [R0] + BX LR + ENDP + +; Dummy Exception Handlers +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP + +HardFault_Handler PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP + +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP + +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP + +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + EXPORT LVD_BOD_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT EVWUP_IRQHandler [WEAK] + EXPORT EXTI0_1_IRQHandler [WEAK] + EXPORT EXTI2_3_IRQHandler [WEAK] + EXPORT EXTI4_15_IRQHandler [WEAK] + EXPORT ADC_IRQHandler [WEAK] + EXPORT GPTM0_IRQHandler [WEAK] + EXPORT SCTM0_IRQHandler [WEAK] + EXPORT SCTM1_IRQHandler [WEAK] + EXPORT SCTM2_IRQHandler [WEAK] + EXPORT SCTM3_IRQHandler [WEAK] + EXPORT BFTM0_IRQHandler [WEAK] + EXPORT BFTM1_IRQHandler [WEAK] + EXPORT I2C0_IRQHandler [WEAK] + EXPORT SPI0_IRQHandler [WEAK] + EXPORT QSPI_IRQHandler [WEAK] + EXPORT USART0_IRQHandler [WEAK] + EXPORT UART0_IRQHandler [WEAK] + EXPORT MIDI_IRQHandler [WEAK] + EXPORT I2S_IRQHandler [WEAK] + EXPORT USB_IRQHandler [WEAK] + EXPORT PDMA_CH0_1_IRQHandler [WEAK] + EXPORT PDMA_CH2_5_IRQHandler [WEAK] + +LVD_BOD_IRQHandler +RTC_IRQHandler +FLASH_IRQHandler +EVWUP_IRQHandler +EXTI0_1_IRQHandler +EXTI2_3_IRQHandler +EXTI4_15_IRQHandler +ADC_IRQHandler +GPTM0_IRQHandler +SCTM0_IRQHandler +SCTM1_IRQHandler +SCTM2_IRQHandler +SCTM3_IRQHandler +BFTM0_IRQHandler +BFTM1_IRQHandler +I2C0_IRQHandler +SPI0_IRQHandler +QSPI_IRQHandler +USART0_IRQHandler +UART0_IRQHandler +MIDI_IRQHandler +I2S_IRQHandler +USB_IRQHandler +PDMA_CH0_1_IRQHandler +PDMA_CH2_5_IRQHandler + B . + ENDP + + ALIGN + +;******************************************************************************* +; User Stack and Heap initialization +;******************************************************************************* + IF :DEF:__MICROLIB + + EXPORT __HT_check_heap + EXPORT __HT_check_sp + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, = (Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + + ENDIF + + END diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f0008.s b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f0008.s new file mode 100644 index 0000000000..db72cb363f --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f0008.s @@ -0,0 +1,403 @@ +;/*---------------------------------------------------------------------------------------------------------*/ +;/* Holtek Semiconductor Inc. */ +;/* */ +;/* Copyright (C) Holtek Semiconductor Inc. */ +;/* All rights reserved. */ +;/* */ +;/*----------------------------------------------------------------------------------------------------------- +; File Name : startup_ht32f5xxxx_03.s +; Version : $Rev:: 6877 $ +; Date : $Date:: 2023-05-04 #$ +; Description : Startup code. +;-----------------------------------------------------------------------------------------------------------*/ + +; Supported Device +; ======================================== +; HT32F0008 +; HT32F52142 +; HT32F52344, HT32F52354 +; HT32F52357, HT32F52367 +; HT50F3200T + +;/* <<< Use Configuration Wizard in Context Menu >>> */ + +;// HT32 Device +;// Select HT32 Device for the assembly setting. +;// Notice that the project's Asm Define has the higher priority. +;// <0=> By Project Asm Define +;// <6=> HT32F0008 +;// <6=> HT32F52142 +;// <9=> HT32F52344/54 +;// <11=> HT32F52357/67 +;// <11=> HT50F3200T +USE_HT32_CHIP_SET EQU 6 ; Notice that the project's Asm Define has the higher priority. + +_HT32FWID EQU 0xFFFFFFFF +;_HT32FWID EQU 0x00000008 +;_HT32FWID EQU 0x00052142 +;_HT32FWID EQU 0x00052344 +;_HT32FWID EQU 0x00052354 +;_HT32FWID EQU 0x00052357 +;_HT32FWID EQU 0x00052367 +;_HT32FWID EQU 0x0003200F + +HT32F0008 EQU 6 +HT32F52142 EQU 6 +HT32F52344_54 EQU 9 +HT32F52357_67 EQU 11 +HT50F3200T EQU 11 + + IF USE_HT32_CHIP_SET=0 + ; Use project's Asm Define setting (default) + ELSE + IF :DEF:USE_HT32_CHIP + ; Use project's Asm Define setting (higher priority than the "USE_HT32_CHIP_SET") + ELSE + ; Use "USE_HT32_CHIP_SET" in the "startup_ht32xxxxx_xx.s" file +USE_HT32_CHIP EQU USE_HT32_CHIP_SET + ENDIF + ENDIF + +; Amount of memory (in bytes) allocated for Stack and Heap +; Tailor those values to your application needs +;// Stack Size (in Bytes, must 8 byte aligned) <0-16384:8> +Stack_Size EQU 512 + + AREA STACK, NOINIT, READWRITE, ALIGN = 3 +__HT_check_sp +Stack_Mem SPACE Stack_Size +__initial_sp + +;// Heap Size (in Bytes) <0-16384:8> +Heap_Size EQU 0 + + AREA HEAP, NOINIT, READWRITE, ALIGN = 3 +__HT_check_heap +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + PRESERVE8 + THUMB + +;******************************************************************************* +; Fill-up the Vector Table entries with the exceptions ISR address +;******************************************************************************* + AREA RESET, CODE, READONLY + EXPORT __Vectors +_RESERVED EQU 0xFFFFFFFF +__Vectors + DCD __initial_sp ; ---, 00, 0x000, Top address of Stack + DCD Reset_Handler ; ---, 01, 0x004, Reset Handler + DCD NMI_Handler ; -14, 02, 0x008, NMI Handler + DCD HardFault_Handler ; -13, 03, 0x00C, Hard Fault Handler + DCD _RESERVED ; ---, 04, 0x010, Reserved + DCD _RESERVED ; ---, 05, 0x014, Reserved + DCD _RESERVED ; ---, 06, 0x018, Reserved + DCD _RESERVED ; ---, 07, 0x01C, Reserved + DCD _HT32FWID ; ---, 08, 0x020, Reserved + DCD _RESERVED ; ---, 09, 0x024, Reserved + DCD _RESERVED ; ---, 10, 0x028, Reserved + DCD SVC_Handler ; -05, 11, 0x02C, SVC Handler + DCD _RESERVED ; ---, 12, 0x030, Reserved + DCD _RESERVED ; ---, 13, 0x034, Reserved + DCD PendSV_Handler ; -02, 14, 0x038, PendSV Handler + DCD SysTick_Handler ; -01, 15, 0x03C, SysTick Handler + + ; External Interrupt Handler + DCD LVD_BOD_IRQHandler ; 00, 16, 0x040, + DCD RTC_IRQHandler ; 01, 17, 0x044, + DCD FLASH_IRQHandler ; 02, 18, 0x048, + DCD EVWUP_IRQHandler ; 03, 19, 0x04C, + DCD EXTI0_1_IRQHandler ; 04, 20, 0x050, + DCD EXTI2_3_IRQHandler ; 05, 21, 0x054, + DCD EXTI4_15_IRQHandler ; 06, 22, 0x058, + IF (USE_HT32_CHIP=HT32F0008) + DCD _RESERVED ; 07, 23, 0x05C, + ENDIF + IF (USE_HT32_CHIP=HT32F52344_54) + DCD COMP_IRQHandler ; 07, 23, 0x05C, + ENDIF + IF (USE_HT32_CHIP=HT32F52357_67) + DCD COMP_DAC_IRQHandler ; 07, 23, 0x05C, + ENDIF + IF (USE_HT32_CHIP=HT32F0008) + DCD _RESERVED ; 08, 24, 0x060, + ELSE + DCD ADC_IRQHandler ; 08, 24, 0x060, + ENDIF + IF (USE_HT32_CHIP=HT32F52357_67) + DCD AES_IRQHandler ; 09, 25, 0x064, + ELSE + DCD _RESERVED ; 09, 25, 0x064, + ENDIF + IF (USE_HT32_CHIP=HT32F0008) + DCD _RESERVED ; 10, 26, 0x068, + ELSE + DCD MCTM0_IRQHandler ; 10, 26, 0x068, + ENDIF + IF (USE_HT32_CHIP=HT32F52357_67) + DCD QSPI_IRQHandler ; 11, 27, 0x06C, + ELSE + DCD _RESERVED ; 11, 27, 0x06C, + ENDIF + DCD GPTM0_IRQHandler ; 12, 28, 0x070, + IF (USE_HT32_CHIP=HT32F0008) + DCD _RESERVED ; 13, 29, 0x074, + DCD _RESERVED ; 14, 30, 0x078, + ELSE + DCD SCTM0_IRQHandler ; 13, 29, 0x074, + DCD SCTM1_IRQHandler ; 14, 30, 0x078, + ENDIF + IF (USE_HT32_CHIP=HT32F0008) || (USE_HT32_CHIP=HT32F52357_67) + DCD PWM0_IRQHandler ; 15, 31, 0x07C, + DCD PWM1_IRQHandler ; 16, 32, 0x080, + ENDIF + IF (USE_HT32_CHIP=HT32F52344_54) + DCD _RESERVED ; 15, 31, 0x07C, + DCD _RESERVED ; 16, 32, 0x080, + ENDIF + DCD BFTM0_IRQHandler ; 17, 33, 0x084, + DCD BFTM1_IRQHandler ; 18, 34, 0x088, + DCD I2C0_IRQHandler ; 19, 35, 0x08C, + IF (USE_HT32_CHIP=HT32F0008) || (USE_HT32_CHIP=HT32F52344_54) + DCD _RESERVED ; 20, 36, 0x090, + ELSE + DCD I2C1_IRQHandler ; 20, 36, 0x090, + ENDIF + DCD SPI0_IRQHandler ; 21, 37, 0x094, + IF (USE_HT32_CHIP=HT32F0008) + DCD _RESERVED ; 22, 38, 0x098, + ELSE + DCD SPI1_IRQHandler ; 22, 38, 0x098, + ENDIF + IF (USE_HT32_CHIP=HT32F52344_54) + DCD _RESERVED ; 23, 39, 0x09C, + ELSE + DCD USART0_IRQHandler ; 23, 39, 0x09C, + ENDIF + IF (USE_HT32_CHIP=HT32F0008) + DCD _RESERVED ; 24, 40, 0x0A0, + DCD UART0_IRQHandler ; 25, 41, 0x0A4, + DCD _RESERVED ; 26, 42, 0x0A8, + ENDIF + IF (USE_HT32_CHIP=HT32F52344_54) + DCD _RESERVED ; 24, 40, 0x0A0, + DCD UART0_IRQHandler ; 25, 41, 0x0A4, + DCD UART1_IRQHandler ; 26, 42, 0x0A8, + ENDIF + IF (USE_HT32_CHIP=HT32F52357_67) + DCD USART1_IRQHandler ; 24, 40, 0x0A0, + DCD UART0_UART2_IRQHandler ; 25, 41, 0x0A4, + DCD UART1_UART3_IRQHandler ; 26, 42, 0x0A8, + ENDIF + IF (USE_HT32_CHIP=HT32F52357_67) + DCD SCI_IRQHandler ; 27, 43, 0xAC, + ELSE + DCD _RESERVED ; 27, 43, 0xAC, + ENDIF + IF (USE_HT32_CHIP=HT32F0008) + DCD AES_IRQHandler ; 28, 44, 0x0B0, + ENDIF + IF (USE_HT32_CHIP=HT32F52344_54) + DCD _RESERVED ; 28, 44, 0x0B0, + ENDIF + IF (USE_HT32_CHIP=HT32F52357_67) + DCD I2S_IRQHandler ; 28, 44, 0x0B0, + ENDIF + DCD USB_IRQHandler ; 29, 45, 0x0B4, + DCD PDMA_CH0_1_IRQHandler ; 30, 46, 0x0B8, + DCD PDMA_CH2_5_IRQHandler ; 31, 47, 0x0BC, + +; Reset handler routine +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + LDR R0, =BootProcess + BLX R0 + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +BootProcess PROC + LDR R0, =0x40080300 + LDR R1,[R0, #0x10] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x14] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x18] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x1C] + CMP R1, #0 + BEQ BP2 +BP1 LDR R0, =0x40080180 + LDR R1,[R0, #0xC] + LSLS R1, R1, #4 + LSRS R1, R1, #20 + CMP R1, #0 + BEQ BP3 + CMP R1, #5 + BEQ BP3 + CMP R1, #6 + BEQ BP3 +BP2 DSB + LDR R0, =0x20000000 + LDR R1, =0x05fa0004 + STR R1, [R0] + LDR R1, =0xe000ed00 + LDR R0, =0x05fa0004 + STR R0, [R1, #0xC] + DSB + B . +BP3 LDR R0, =0x20000000 + LDR R1, [R0] + LDR R0, =0x05fa0004 + CMP R0, R1 + BEQ BP4 + BX LR +BP4 LDR R0, =0x40088100 + LDR R1, =0x00000001 + STR R1, [R0] + LDR R0, =0x20000000 + LDR R1, =0x0 + STR R1, [R0] + BX LR + ENDP + +; Dummy Exception Handlers +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP + +HardFault_Handler PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP + +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP + +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP + +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + EXPORT LVD_BOD_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT EVWUP_IRQHandler [WEAK] + EXPORT EXTI0_1_IRQHandler [WEAK] + EXPORT EXTI2_3_IRQHandler [WEAK] + EXPORT EXTI4_15_IRQHandler [WEAK] + EXPORT COMP_IRQHandler [WEAK] + EXPORT COMP_DAC_IRQHandler [WEAK] + EXPORT ADC_IRQHandler [WEAK] + EXPORT MCTM0_IRQHandler [WEAK] + EXPORT GPTM0_IRQHandler [WEAK] + EXPORT SCTM0_IRQHandler [WEAK] + EXPORT SCTM1_IRQHandler [WEAK] + EXPORT PWM0_IRQHandler [WEAK] + EXPORT PWM1_IRQHandler [WEAK] + EXPORT BFTM0_IRQHandler [WEAK] + EXPORT BFTM1_IRQHandler [WEAK] + EXPORT I2C0_IRQHandler [WEAK] + EXPORT I2C1_IRQHandler [WEAK] + EXPORT SPI0_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT QSPI_IRQHandler [WEAK] + EXPORT USART0_IRQHandler [WEAK] + EXPORT USART1_IRQHandler [WEAK] + EXPORT UART0_IRQHandler [WEAK] + EXPORT UART1_IRQHandler [WEAK] + EXPORT UART0_UART2_IRQHandler [WEAK] + EXPORT UART1_UART3_IRQHandler [WEAK] + EXPORT SCI_IRQHandler [WEAK] + EXPORT I2S_IRQHandler [WEAK] + EXPORT AES_IRQHandler [WEAK] + EXPORT USB_IRQHandler [WEAK] + EXPORT PDMA_CH0_1_IRQHandler [WEAK] + EXPORT PDMA_CH2_5_IRQHandler [WEAK] + +LVD_BOD_IRQHandler +RTC_IRQHandler +FLASH_IRQHandler +EVWUP_IRQHandler +EXTI0_1_IRQHandler +EXTI2_3_IRQHandler +EXTI4_15_IRQHandler +COMP_IRQHandler +COMP_DAC_IRQHandler +ADC_IRQHandler +MCTM0_IRQHandler +GPTM0_IRQHandler +SCTM0_IRQHandler +SCTM1_IRQHandler +PWM0_IRQHandler +PWM1_IRQHandler +BFTM0_IRQHandler +BFTM1_IRQHandler +I2C0_IRQHandler +I2C1_IRQHandler +SPI0_IRQHandler +SPI1_IRQHandler +QSPI_IRQHandler +USART0_IRQHandler +USART1_IRQHandler +UART0_IRQHandler +UART1_IRQHandler +UART0_UART2_IRQHandler +UART1_UART3_IRQHandler +SCI_IRQHandler +I2S_IRQHandler +AES_IRQHandler +USB_IRQHandler +PDMA_CH0_1_IRQHandler +PDMA_CH2_5_IRQHandler + B . + ENDP + + ALIGN + +;******************************************************************************* +; User Stack and Heap initialization +;******************************************************************************* + IF :DEF:__MICROLIB + + EXPORT __HT_check_heap + EXPORT __HT_check_sp + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, = (Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + + ENDIF + + END diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f50020_30.s b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f50020_30.s new file mode 100644 index 0000000000..45853e20f1 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f50020_30.s @@ -0,0 +1,235 @@ +;/*---------------------------------------------------------------------------------------------------------*/ +;/* Holtek Semiconductor Inc. */ +;/* */ +;/* Copyright (C) Holtek Semiconductor Inc. */ +;/* All rights reserved. */ +;/* */ +;/*----------------------------------------------------------------------------------------------------------- +; File Name : startup_ht32f5xxxx_13.s +; Version : $Rev:: 7119 $ +; Date : $Date:: 2023-08-15 #$ +; Description : Startup code. +;-----------------------------------------------------------------------------------------------------------*/ + +; Supported Device +; ======================================== +; HT32F50020, HT32F50030 +; HT32F61630 +; HT32F61030 + +;/* <<< Use Configuration Wizard in Context Menu >>> */ + +;// HT32 Device +;// Select HT32 Device for the assembly setting. +;// Notice that the project's Asm Define has the higher priority. +;// <0=> By Project Asm Define +;// <25=> HT32F50020/30 +;// <25=> HT32F61630 +;// <25=> HT32F61030 +USE_HT32_CHIP_SET EQU 25 ; Notice that the project's Asm Define has the higher priority. + +_HT32FWID EQU 0xFFFFFFFF +;_HT32FWID EQU 0x00050020 +;_HT32FWID EQU 0x00050030 +;_HT32FWID EQU 0x00061630 +;_HT32FWID EQU 0x00061030 + +HT32F50020_30 EQU 25 +HT32F61630 EQU 25 +HT32F61030 EQU 25 + + IF USE_HT32_CHIP_SET=0 + ; Use project's Asm Define setting (default) + ELSE + IF :DEF:USE_HT32_CHIP + ; Use project's Asm Define setting (higher priority than the "USE_HT32_CHIP_SET") + ELSE + ; Use "USE_HT32_CHIP_SET" in the "startup_ht32xxxxx_xx.s" file +USE_HT32_CHIP EQU USE_HT32_CHIP_SET + ENDIF + ENDIF + +; Amount of memory (in bytes) allocated for Stack and Heap +; Tailor those values to your application needs +;// Stack Size (in Bytes, must 8 byte aligned) <0-2048:8> +Stack_Size EQU 512 + + AREA STACK, NOINIT, READWRITE, ALIGN = 3 +__HT_check_sp +Stack_Mem SPACE Stack_Size +__initial_sp + +;// Heap Size (in Bytes) <0-2048:8> +Heap_Size EQU 0 + + AREA HEAP, NOINIT, READWRITE, ALIGN = 3 +__HT_check_heap +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + PRESERVE8 + THUMB + +;******************************************************************************* +; Fill-up the Vector Table entries with the exceptions ISR address +;******************************************************************************* + AREA RESET, CODE, READONLY + EXPORT __Vectors +_RESERVED EQU 0xFFFFFFFF +__Vectors + DCD __initial_sp ; ---, 00, 0x000, Top address of Stack + DCD Reset_Handler ; ---, 01, 0x004, Reset Handler + DCD NMI_Handler ; -14, 02, 0x008, NMI Handler + DCD HardFault_Handler ; -13, 03, 0x00C, Hard Fault Handler + DCD _RESERVED ; ---, 04, 0x010, Reserved + DCD _RESERVED ; ---, 05, 0x014, Reserved + DCD _RESERVED ; ---, 06, 0x018, Reserved + DCD _RESERVED ; ---, 07, 0x01C, Reserved + DCD _HT32FWID ; ---, 08, 0x020, Reserved + DCD _RESERVED ; ---, 09, 0x024, Reserved + DCD _RESERVED ; ---, 10, 0x028, Reserved + DCD SVC_Handler ; -05, 11, 0x02C, SVC Handler + DCD _RESERVED ; ---, 12, 0x030, Reserved + DCD _RESERVED ; ---, 13, 0x034, Reserved + DCD PendSV_Handler ; -02, 14, 0x038, PendSV Handler + DCD SysTick_Handler ; -01, 15, 0x03C, SysTick Handler + + ; External Interrupt Handler + DCD LVD_BOD_IRQHandler ; 00, 16, 0x040, + DCD RTC_IRQHandler ; 01, 17, 0x044, + DCD FLASH_IRQHandler ; 02, 18, 0x048, + DCD EVWUP_IRQHandler ; 03, 19, 0x04C, + DCD EXTI0_1_IRQHandler ; 04, 20, 0x050, + DCD EXTI2_3_IRQHandler ; 05, 21, 0x054, + DCD EXTI4_7_IRQHandler ; 06, 22, 0x058, + DCD _RESERVED ; 07, 23, 0x05C, + DCD ADC_IRQHandler ; 08, 24, 0x060, + DCD _RESERVED ; 09, 25, 0x064, + DCD _RESERVED ; 10, 26, 0x068, + DCD _RESERVED ; 11, 27, 0x06C, + DCD _RESERVED ; 12, 28, 0x070, + DCD SCTM0_IRQHandler ; 13, 29, 0x074, + DCD SCTM1_IRQHandler ; 14, 30, 0x078, + DCD SCTM2_IRQHandler ; 15, 31, 0x07C, + DCD _RESERVED ; 16, 32, 0x080, + DCD BFTM0_IRQHandler ; 17, 33, 0x084, + DCD _RESERVED ; 18, 34, 0x088, + DCD I2C0_IRQHandler ; 19, 35, 0x08C, + DCD _RESERVED ; 20, 36, 0x090, + DCD SPI0_IRQHandler ; 21, 37, 0x094, + DCD _RESERVED ; 22, 38, 0x098, + DCD _RESERVED ; 23, 39, 0x09C, + DCD _RESERVED ; 24, 40, 0x0A0, + DCD UART0_IRQHandler ; 25, 41, 0x0A4, + DCD UART1_IRQHandler ; 26, 42, 0x0A8, + DCD _RESERVED ; 27, 43, 0x0AC, + DCD _RESERVED ; 28, 44, 0x0B0, + DCD LEDC_IRQHandler ; 29, 45, 0x0B4, + +; Reset handler routine +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception Handlers +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP + +HardFault_Handler PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP + +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP + +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP + +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + EXPORT LVD_BOD_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT EVWUP_IRQHandler [WEAK] + EXPORT EXTI0_1_IRQHandler [WEAK] + EXPORT EXTI2_3_IRQHandler [WEAK] + EXPORT EXTI4_7_IRQHandler [WEAK] + EXPORT ADC_IRQHandler [WEAK] + EXPORT SCTM0_IRQHandler [WEAK] + EXPORT SCTM1_IRQHandler [WEAK] + EXPORT SCTM2_IRQHandler [WEAK] + EXPORT BFTM0_IRQHandler [WEAK] + EXPORT I2C0_IRQHandler [WEAK] + EXPORT SPI0_IRQHandler [WEAK] + EXPORT UART0_IRQHandler [WEAK] + EXPORT UART1_IRQHandler [WEAK] + EXPORT LEDC_IRQHandler [WEAK] + +LVD_BOD_IRQHandler +RTC_IRQHandler +FLASH_IRQHandler +EVWUP_IRQHandler +EXTI0_1_IRQHandler +EXTI2_3_IRQHandler +EXTI4_7_IRQHandler +ADC_IRQHandler +SCTM0_IRQHandler +SCTM1_IRQHandler +SCTM2_IRQHandler +BFTM0_IRQHandler +I2C0_IRQHandler +SPI0_IRQHandler +UART0_IRQHandler +UART1_IRQHandler +LEDC_IRQHandler + B . + ENDP + + ALIGN + +;******************************************************************************* +; User Stack and Heap initialization +;******************************************************************************* + IF :DEF:__MICROLIB + + EXPORT __HT_check_heap + EXPORT __HT_check_sp + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, = (Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + + ENDIF + + END diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f50220_30.s b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f50220_30.s new file mode 100644 index 0000000000..a86606d966 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f50220_30.s @@ -0,0 +1,327 @@ +;/*---------------------------------------------------------------------------------------------------------*/ +;/* Holtek Semiconductor Inc. */ +;/* */ +;/* Copyright (C) Holtek Semiconductor Inc. */ +;/* All rights reserved. */ +;/* */ +;/*----------------------------------------------------------------------------------------------------------- +; File Name : startup_ht32f5xxxx_02.s +; Version : $Rev:: 7119 $ +; Date : $Date:: 2023-08-15 #$ +; Description : Startup code. +;-----------------------------------------------------------------------------------------------------------*/ + +; Supported Device +; ======================================== +; HT32F50220, HT32F50230 +; HT32F50231, HT32F50241 +; HT50F32002 +; HT32F59041 +; HF5032 +; HT32F61641 +; HT32F59046 +; HT32F61041 + +;/* <<< Use Configuration Wizard in Context Menu >>> */ + +;// HT32 Device +;// Select HT32 Device for the assembly setting. +;// Notice that the project's Asm Define has the higher priority. +;// <0=> By Project Asm Define +;// <7=> HT32F50220/30 +;// <8=> HT32F50231/41 +;// <7=> HT50F32002 +;// <8=> HT32F59041 +;// <7=> HF5032 +;// <8=> HT32F61641 +;// <8=> HT32F59046 +;// <8=> HT32F61041 +USE_HT32_CHIP_SET EQU 7 ; Notice that the project's Asm Define has the higher priority. + +_HT32FWID EQU 0xFFFFFFFF +;_HT32FWID EQU 0x00050220 +;_HT32FWID EQU 0x00050230 +;_HT32FWID EQU 0x00050231 +;_HT32FWID EQU 0x00050241 +;_HT32FWID EQU 0x00032002 +;_HT32FWID EQU 0x00059041 +;_HT32FWID EQU 0x000F5032 +;_HT32FWID EQU 0x00061641 +;_HT32FWID EQU 0x00059046 +;_HT32FWID EQU 0x00061041 + +HT32F50220_30 EQU 7 +HT32F50231_41 EQU 8 +HT50F32002 EQU 7 +HT32F59041 EQU 8 +HF5032 EQU 7 +HT32F61641 EQU 8 +HT32F59046 EQU 8 +HT32F61041 EQU 8 + + IF USE_HT32_CHIP_SET=0 + ; Use project's Asm Define setting (default) + ELSE + IF :DEF:USE_HT32_CHIP + ; Use project's Asm Define setting (higher priority than the "USE_HT32_CHIP_SET") + ELSE + ; Use "USE_HT32_CHIP_SET" in the "startup_ht32xxxxx_xx.s" file +USE_HT32_CHIP EQU USE_HT32_CHIP_SET + ENDIF + ENDIF + +; Amount of memory (in bytes) allocated for Stack and Heap +; Tailor those values to your application needs +;// Stack Size (in Bytes, must 8 byte aligned) <0-4096:8> +Stack_Size EQU 512 + + AREA STACK, NOINIT, READWRITE, ALIGN = 3 +__HT_check_sp +Stack_Mem SPACE Stack_Size +__initial_sp + +;// Heap Size (in Bytes) <0-4096:8> +Heap_Size EQU 0 + + AREA HEAP, NOINIT, READWRITE, ALIGN = 3 +__HT_check_heap +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + PRESERVE8 + THUMB + +;******************************************************************************* +; Fill-up the Vector Table entries with the exceptions ISR address +;******************************************************************************* + AREA RESET, CODE, READONLY + EXPORT __Vectors +_RESERVED EQU 0xFFFFFFFF +__Vectors + DCD __initial_sp ; ---, 00, 0x000, Top address of Stack + DCD Reset_Handler ; ---, 01, 0x004, Reset Handler + DCD NMI_Handler ; -14, 02, 0x008, NMI Handler + DCD HardFault_Handler ; -13, 03, 0x00C, Hard Fault Handler + DCD _RESERVED ; ---, 04, 0x010, Reserved + DCD _RESERVED ; ---, 05, 0x014, Reserved + DCD _RESERVED ; ---, 06, 0x018, Reserved + DCD _RESERVED ; ---, 07, 0x01C, Reserved + DCD _HT32FWID ; ---, 08, 0x020, Reserved + DCD _RESERVED ; ---, 09, 0x024, Reserved + DCD _RESERVED ; ---, 10, 0x028, Reserved + DCD SVC_Handler ; -05, 11, 0x02C, SVC Handler + DCD _RESERVED ; ---, 12, 0x030, Reserved + DCD _RESERVED ; ---, 13, 0x034, Reserved + DCD PendSV_Handler ; -02, 14, 0x038, PendSV Handler + DCD SysTick_Handler ; -01, 15, 0x03C, SysTick Handler + + ; External Interrupt Handler + DCD LVD_BOD_IRQHandler ; 00, 16, 0x040, + DCD RTC_IRQHandler ; 01, 17, 0x044, + DCD FLASH_IRQHandler ; 02, 18, 0x048, + DCD EVWUP_IRQHandler ; 03, 19, 0x04C, + DCD EXTI0_1_IRQHandler ; 04, 20, 0x050, + DCD EXTI2_3_IRQHandler ; 05, 21, 0x054, + DCD EXTI4_15_IRQHandler ; 06, 22, 0x058, + DCD _RESERVED ; 07, 23, 0x05C, + DCD ADC_IRQHandler ; 08, 24, 0x060, + DCD _RESERVED ; 09, 25, 0x064, + IF (USE_HT32_CHIP=HT32F50220_30) + DCD _RESERVED ; 10, 26, 0x068, + ELSE + DCD MCTM0_IRQHandler ; 10, 26, 0x068, + ENDIF + DCD _RESERVED ; 11, 27, 0x06C, + DCD GPTM0_IRQHandler ; 12, 28, 0x070, + DCD _RESERVED ; 13, 29, 0x074, + DCD _RESERVED ; 14, 30, 0x078, + DCD PWM0_IRQHandler ; 15, 31, 0x07C, + DCD PWM1_IRQHandler ; 16, 32, 0x080, + DCD BFTM0_IRQHandler ; 17, 33, 0x084, + IF (USE_HT32_CHIP=HT32F50220_30) + DCD _RESERVED ; 18, 34, 0x088, + ELSE + DCD BFTM1_IRQHandler ; 18, 34, 0x088, + ENDIF + DCD I2C0_IRQHandler ; 19, 35, 0x08C, + IF (USE_HT32_CHIP=HT32F50220_30) + DCD _RESERVED ; 20, 36, 0x090, + ELSE + DCD I2C1_IRQHandler ; 20, 36, 0x090, + ENDIF + DCD SPI0_IRQHandler ; 21, 37, 0x094, + DCD SPI1_IRQHandler ; 22, 38, 0x098, + IF (USE_HT32_CHIP=HT32F50220_30) + DCD _RESERVED ; 23, 39, 0x09C, + ELSE + DCD USART0_IRQHandler ; 23, 39, 0x09C, + ENDIF + DCD _RESERVED ; 24, 40, 0x0A0, + DCD UART0_IRQHandler ; 25, 41, 0x0A4, + DCD UART1_IRQHandler ; 26, 42, 0x0A8, + +; Reset handler routine +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + LDR R0, =BootProcess + BLX R0 + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +BootProcess PROC + LDR R0, =0x40080300 + LDR R1,[R0, #0x10] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x14] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x18] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x1C] + CMP R1, #0 + BEQ BP2 +BP1 LDR R0, =0x40080180 + LDR R1,[R0, #0xC] + LSLS R1, R1, #4 + LSRS R1, R1, #20 + CMP R1, #0 + BEQ BP3 + CMP R1, #5 + BEQ BP3 + CMP R1, #6 + BEQ BP3 +BP2 DSB + LDR R0, =0x20000000 + LDR R1, =0x05fa0004 + STR R1, [R0] + LDR R1, =0xe000ed00 + LDR R0, =0x05fa0004 + STR R0, [R1, #0xC] + DSB + B . +BP3 LDR R0, =0x20000000 + LDR R1, [R0] + LDR R0, =0x05fa0004 + CMP R0, R1 + BEQ BP4 + BX LR +BP4 LDR R0, =0x40088100 + LDR R1, =0x00000001 + STR R1, [R0] + LDR R0, =0x20000000 + LDR R1, =0x0 + STR R1, [R0] + BX LR + ENDP + +; Dummy Exception Handlers +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP + +HardFault_Handler PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP + +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP + +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP + +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + EXPORT LVD_BOD_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT EVWUP_IRQHandler [WEAK] + EXPORT EXTI0_1_IRQHandler [WEAK] + EXPORT EXTI2_3_IRQHandler [WEAK] + EXPORT EXTI4_15_IRQHandler [WEAK] + EXPORT ADC_IRQHandler [WEAK] + EXPORT MCTM0_IRQHandler [WEAK] + EXPORT GPTM0_IRQHandler [WEAK] + EXPORT PWM0_IRQHandler [WEAK] + EXPORT PWM1_IRQHandler [WEAK] + EXPORT BFTM0_IRQHandler [WEAK] + EXPORT BFTM1_IRQHandler [WEAK] + EXPORT I2C0_IRQHandler [WEAK] + EXPORT I2C1_IRQHandler [WEAK] + EXPORT SPI0_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT USART0_IRQHandler [WEAK] + EXPORT UART0_IRQHandler [WEAK] + EXPORT UART1_IRQHandler [WEAK] + +LVD_BOD_IRQHandler +RTC_IRQHandler +FLASH_IRQHandler +EVWUP_IRQHandler +EXTI0_1_IRQHandler +EXTI2_3_IRQHandler +EXTI4_15_IRQHandler +ADC_IRQHandler +MCTM0_IRQHandler +GPTM0_IRQHandler +PWM0_IRQHandler +PWM1_IRQHandler +BFTM0_IRQHandler +BFTM1_IRQHandler +I2C0_IRQHandler +I2C1_IRQHandler +SPI0_IRQHandler +SPI1_IRQHandler +USART0_IRQHandler +UART0_IRQHandler +UART1_IRQHandler + B . + ENDP + + ALIGN + +;******************************************************************************* +; User Stack and Heap initialization +;******************************************************************************* + IF :DEF:__MICROLIB + + EXPORT __HT_check_heap + EXPORT __HT_check_sp + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, = (Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + + ENDIF + + END diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f50231_41.s b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f50231_41.s new file mode 100644 index 0000000000..8e68952909 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f50231_41.s @@ -0,0 +1,327 @@ +;/*---------------------------------------------------------------------------------------------------------*/ +;/* Holtek Semiconductor Inc. */ +;/* */ +;/* Copyright (C) Holtek Semiconductor Inc. */ +;/* All rights reserved. */ +;/* */ +;/*----------------------------------------------------------------------------------------------------------- +; File Name : startup_ht32f5xxxx_02.s +; Version : $Rev:: 7119 $ +; Date : $Date:: 2023-08-15 #$ +; Description : Startup code. +;-----------------------------------------------------------------------------------------------------------*/ + +; Supported Device +; ======================================== +; HT32F50220, HT32F50230 +; HT32F50231, HT32F50241 +; HT50F32002 +; HT32F59041 +; HF5032 +; HT32F61641 +; HT32F59046 +; HT32F61041 + +;/* <<< Use Configuration Wizard in Context Menu >>> */ + +;// HT32 Device +;// Select HT32 Device for the assembly setting. +;// Notice that the project's Asm Define has the higher priority. +;// <0=> By Project Asm Define +;// <7=> HT32F50220/30 +;// <8=> HT32F50231/41 +;// <7=> HT50F32002 +;// <8=> HT32F59041 +;// <7=> HF5032 +;// <8=> HT32F61641 +;// <8=> HT32F59046 +;// <8=> HT32F61041 +USE_HT32_CHIP_SET EQU 8 ; Notice that the project's Asm Define has the higher priority. + +_HT32FWID EQU 0xFFFFFFFF +;_HT32FWID EQU 0x00050220 +;_HT32FWID EQU 0x00050230 +;_HT32FWID EQU 0x00050231 +;_HT32FWID EQU 0x00050241 +;_HT32FWID EQU 0x00032002 +;_HT32FWID EQU 0x00059041 +;_HT32FWID EQU 0x000F5032 +;_HT32FWID EQU 0x00061641 +;_HT32FWID EQU 0x00059046 +;_HT32FWID EQU 0x00061041 + +HT32F50220_30 EQU 7 +HT32F50231_41 EQU 8 +HT50F32002 EQU 7 +HT32F59041 EQU 8 +HF5032 EQU 7 +HT32F61641 EQU 8 +HT32F59046 EQU 8 +HT32F61041 EQU 8 + + IF USE_HT32_CHIP_SET=0 + ; Use project's Asm Define setting (default) + ELSE + IF :DEF:USE_HT32_CHIP + ; Use project's Asm Define setting (higher priority than the "USE_HT32_CHIP_SET") + ELSE + ; Use "USE_HT32_CHIP_SET" in the "startup_ht32xxxxx_xx.s" file +USE_HT32_CHIP EQU USE_HT32_CHIP_SET + ENDIF + ENDIF + +; Amount of memory (in bytes) allocated for Stack and Heap +; Tailor those values to your application needs +;// Stack Size (in Bytes, must 8 byte aligned) <0-4096:8> +Stack_Size EQU 512 + + AREA STACK, NOINIT, READWRITE, ALIGN = 3 +__HT_check_sp +Stack_Mem SPACE Stack_Size +__initial_sp + +;// Heap Size (in Bytes) <0-4096:8> +Heap_Size EQU 0 + + AREA HEAP, NOINIT, READWRITE, ALIGN = 3 +__HT_check_heap +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + PRESERVE8 + THUMB + +;******************************************************************************* +; Fill-up the Vector Table entries with the exceptions ISR address +;******************************************************************************* + AREA RESET, CODE, READONLY + EXPORT __Vectors +_RESERVED EQU 0xFFFFFFFF +__Vectors + DCD __initial_sp ; ---, 00, 0x000, Top address of Stack + DCD Reset_Handler ; ---, 01, 0x004, Reset Handler + DCD NMI_Handler ; -14, 02, 0x008, NMI Handler + DCD HardFault_Handler ; -13, 03, 0x00C, Hard Fault Handler + DCD _RESERVED ; ---, 04, 0x010, Reserved + DCD _RESERVED ; ---, 05, 0x014, Reserved + DCD _RESERVED ; ---, 06, 0x018, Reserved + DCD _RESERVED ; ---, 07, 0x01C, Reserved + DCD _HT32FWID ; ---, 08, 0x020, Reserved + DCD _RESERVED ; ---, 09, 0x024, Reserved + DCD _RESERVED ; ---, 10, 0x028, Reserved + DCD SVC_Handler ; -05, 11, 0x02C, SVC Handler + DCD _RESERVED ; ---, 12, 0x030, Reserved + DCD _RESERVED ; ---, 13, 0x034, Reserved + DCD PendSV_Handler ; -02, 14, 0x038, PendSV Handler + DCD SysTick_Handler ; -01, 15, 0x03C, SysTick Handler + + ; External Interrupt Handler + DCD LVD_BOD_IRQHandler ; 00, 16, 0x040, + DCD RTC_IRQHandler ; 01, 17, 0x044, + DCD FLASH_IRQHandler ; 02, 18, 0x048, + DCD EVWUP_IRQHandler ; 03, 19, 0x04C, + DCD EXTI0_1_IRQHandler ; 04, 20, 0x050, + DCD EXTI2_3_IRQHandler ; 05, 21, 0x054, + DCD EXTI4_15_IRQHandler ; 06, 22, 0x058, + DCD _RESERVED ; 07, 23, 0x05C, + DCD ADC_IRQHandler ; 08, 24, 0x060, + DCD _RESERVED ; 09, 25, 0x064, + IF (USE_HT32_CHIP=HT32F50220_30) + DCD _RESERVED ; 10, 26, 0x068, + ELSE + DCD MCTM0_IRQHandler ; 10, 26, 0x068, + ENDIF + DCD _RESERVED ; 11, 27, 0x06C, + DCD GPTM0_IRQHandler ; 12, 28, 0x070, + DCD _RESERVED ; 13, 29, 0x074, + DCD _RESERVED ; 14, 30, 0x078, + DCD PWM0_IRQHandler ; 15, 31, 0x07C, + DCD PWM1_IRQHandler ; 16, 32, 0x080, + DCD BFTM0_IRQHandler ; 17, 33, 0x084, + IF (USE_HT32_CHIP=HT32F50220_30) + DCD _RESERVED ; 18, 34, 0x088, + ELSE + DCD BFTM1_IRQHandler ; 18, 34, 0x088, + ENDIF + DCD I2C0_IRQHandler ; 19, 35, 0x08C, + IF (USE_HT32_CHIP=HT32F50220_30) + DCD _RESERVED ; 20, 36, 0x090, + ELSE + DCD I2C1_IRQHandler ; 20, 36, 0x090, + ENDIF + DCD SPI0_IRQHandler ; 21, 37, 0x094, + DCD SPI1_IRQHandler ; 22, 38, 0x098, + IF (USE_HT32_CHIP=HT32F50220_30) + DCD _RESERVED ; 23, 39, 0x09C, + ELSE + DCD USART0_IRQHandler ; 23, 39, 0x09C, + ENDIF + DCD _RESERVED ; 24, 40, 0x0A0, + DCD UART0_IRQHandler ; 25, 41, 0x0A4, + DCD UART1_IRQHandler ; 26, 42, 0x0A8, + +; Reset handler routine +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + LDR R0, =BootProcess + BLX R0 + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +BootProcess PROC + LDR R0, =0x40080300 + LDR R1,[R0, #0x10] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x14] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x18] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x1C] + CMP R1, #0 + BEQ BP2 +BP1 LDR R0, =0x40080180 + LDR R1,[R0, #0xC] + LSLS R1, R1, #4 + LSRS R1, R1, #20 + CMP R1, #0 + BEQ BP3 + CMP R1, #5 + BEQ BP3 + CMP R1, #6 + BEQ BP3 +BP2 DSB + LDR R0, =0x20000000 + LDR R1, =0x05fa0004 + STR R1, [R0] + LDR R1, =0xe000ed00 + LDR R0, =0x05fa0004 + STR R0, [R1, #0xC] + DSB + B . +BP3 LDR R0, =0x20000000 + LDR R1, [R0] + LDR R0, =0x05fa0004 + CMP R0, R1 + BEQ BP4 + BX LR +BP4 LDR R0, =0x40088100 + LDR R1, =0x00000001 + STR R1, [R0] + LDR R0, =0x20000000 + LDR R1, =0x0 + STR R1, [R0] + BX LR + ENDP + +; Dummy Exception Handlers +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP + +HardFault_Handler PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP + +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP + +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP + +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + EXPORT LVD_BOD_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT EVWUP_IRQHandler [WEAK] + EXPORT EXTI0_1_IRQHandler [WEAK] + EXPORT EXTI2_3_IRQHandler [WEAK] + EXPORT EXTI4_15_IRQHandler [WEAK] + EXPORT ADC_IRQHandler [WEAK] + EXPORT MCTM0_IRQHandler [WEAK] + EXPORT GPTM0_IRQHandler [WEAK] + EXPORT PWM0_IRQHandler [WEAK] + EXPORT PWM1_IRQHandler [WEAK] + EXPORT BFTM0_IRQHandler [WEAK] + EXPORT BFTM1_IRQHandler [WEAK] + EXPORT I2C0_IRQHandler [WEAK] + EXPORT I2C1_IRQHandler [WEAK] + EXPORT SPI0_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT USART0_IRQHandler [WEAK] + EXPORT UART0_IRQHandler [WEAK] + EXPORT UART1_IRQHandler [WEAK] + +LVD_BOD_IRQHandler +RTC_IRQHandler +FLASH_IRQHandler +EVWUP_IRQHandler +EXTI0_1_IRQHandler +EXTI2_3_IRQHandler +EXTI4_15_IRQHandler +ADC_IRQHandler +MCTM0_IRQHandler +GPTM0_IRQHandler +PWM0_IRQHandler +PWM1_IRQHandler +BFTM0_IRQHandler +BFTM1_IRQHandler +I2C0_IRQHandler +I2C1_IRQHandler +SPI0_IRQHandler +SPI1_IRQHandler +USART0_IRQHandler +UART0_IRQHandler +UART1_IRQHandler + B . + ENDP + + ALIGN + +;******************************************************************************* +; User Stack and Heap initialization +;******************************************************************************* + IF :DEF:__MICROLIB + + EXPORT __HT_check_heap + EXPORT __HT_check_sp + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, = (Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + + ENDIF + + END diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f50343.s b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f50343.s new file mode 100644 index 0000000000..1a58d66e73 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f50343.s @@ -0,0 +1,298 @@ +;/*---------------------------------------------------------------------------------------------------------*/ +;/* Holtek Semiconductor Inc. */ +;/* */ +;/* Copyright (C) Holtek Semiconductor Inc. */ +;/* All rights reserved. */ +;/* */ +;/*----------------------------------------------------------------------------------------------------------- +; File Name : startup_ht32f5xxxx_06.s +; Version : $Rev:: 5740 $ +; Date : $Date:: 2022-02-17 #$ +; Description : Startup code. +;-----------------------------------------------------------------------------------------------------------*/ + +; Supported Device +; ======================================== +; HT32F50343 + +;/* <<< Use Configuration Wizard in Context Menu >>> */ + +;// HT32 Device +;// Select HT32 Device for the assembly setting. +;// Notice that the project's Asm Define has the higher priority. +;// <0=> By Project Asm Define +;// <15=> HT32F50343 +USE_HT32_CHIP_SET EQU 15 ; Notice that the project's Asm Define has the higher priority. + +_HT32FWID EQU 0xFFFFFFFF +;_HT32FWID EQU 0x00050343 + +HT32F50343 EQU 15 + + IF USE_HT32_CHIP_SET=0 + ; Use project's Asm Define setting (default) + ELSE + IF :DEF:USE_HT32_CHIP + ; Use project's Asm Define setting (higher priority than the "USE_HT32_CHIP_SET") + ELSE + ; Use "USE_HT32_CHIP_SET" in the "startup_ht32xxxxx_xx.s" file +USE_HT32_CHIP EQU USE_HT32_CHIP_SET + ENDIF + ENDIF + +; Amount of memory (in bytes) allocated for Stack and Heap +; Tailor those values to your application needs +;// Stack Size (in Bytes, must 8 byte aligned) <0-12288:8> +Stack_Size EQU 512 + + AREA STACK, NOINIT, READWRITE, ALIGN = 3 +__HT_check_sp +Stack_Mem SPACE Stack_Size +__initial_sp + +;// Heap Size (in Bytes) <0-12288:8> +Heap_Size EQU 0 + + AREA HEAP, NOINIT, READWRITE, ALIGN = 3 +__HT_check_heap +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + PRESERVE8 + THUMB + +;******************************************************************************* +; Fill-up the Vector Table entries with the exceptions ISR address +;******************************************************************************* + AREA RESET, CODE, READONLY + EXPORT __Vectors +_RESERVED EQU 0xFFFFFFFF +__Vectors + DCD __initial_sp ; ---, 00, 0x000, Top address of Stack + DCD Reset_Handler ; ---, 01, 0x004, Reset Handler + DCD NMI_Handler ; -14, 02, 0x008, NMI Handler + DCD HardFault_Handler ; -13, 03, 0x00C, Hard Fault Handler + DCD _RESERVED ; ---, 04, 0x010, Reserved + DCD _RESERVED ; ---, 05, 0x014, Reserved + DCD _RESERVED ; ---, 06, 0x018, Reserved + DCD _RESERVED ; ---, 07, 0x01C, Reserved + DCD _HT32FWID ; ---, 08, 0x020, Reserved + DCD _RESERVED ; ---, 09, 0x024, Reserved + DCD _RESERVED ; ---, 10, 0x028, Reserved + DCD SVC_Handler ; -05, 11, 0x02C, SVC Handler + DCD _RESERVED ; ---, 12, 0x030, Reserved + DCD _RESERVED ; ---, 13, 0x034, Reserved + DCD PendSV_Handler ; -02, 14, 0x038, PendSV Handler + DCD SysTick_Handler ; -01, 15, 0x03C, SysTick Handler + + ; External Interrupt Handler + DCD LVD_BOD_IRQHandler ; 00, 16, 0x040, + DCD RTC_IRQHandler ; 01, 17, 0x044, + DCD FLASH_IRQHandler ; 02, 18, 0x048, + DCD EVWUP_IRQHandler ; 03, 19, 0x04C, + DCD EXTI0_1_IRQHandler ; 04, 20, 0x050, + DCD EXTI2_3_IRQHandler ; 05, 21, 0x054, + DCD EXTI4_15_IRQHandler ; 06, 22, 0x058, + DCD _RESERVED ; 07, 23, 0x05C, + DCD ADC_IRQHandler ; 08, 24, 0x060, + DCD _RESERVED ; 09, 25, 0x064, + DCD PWM2_IRQHandler ; 10, 26, 0x068, + DCD _RESERVED ; 11, 27, 0x06C, + DCD GPTM0_IRQHandler ; 12, 28, 0x070, + DCD SCTM0_IRQHandler ; 13, 29, 0x074, + DCD SCTM1_IRQHandler ; 14, 30, 0x078, + DCD PWM0_IRQHandler ; 15, 31, 0x07C, + DCD PWM1_IRQHandler ; 16, 32, 0x080, + DCD BFTM0_IRQHandler ; 17, 33, 0x084, + DCD BFTM1_IRQHandler ; 18, 34, 0x088, + DCD I2C0_IRQHandler ; 19, 35, 0x08C, + DCD I2C1_IRQHandler ; 20, 36, 0x090, + DCD SPI0_IRQHandler ; 21, 37, 0x094, + DCD SPI1_IRQHandler ; 22, 38, 0x098, + DCD _RESERVED ; 23, 39, 0x09C, + DCD _RESERVED ; 24, 40, 0x0A0, + DCD UART0_IRQHandler ; 25, 41, 0x0A4, + DCD UART1_IRQHandler ; 26, 42, 0x0A8, + DCD SLED0_IRQHandler ; 27, 43, 0x0AC, + DCD SLED1_IRQHandler ; 28, 44, 0x0B0, + DCD USB_IRQHandler ; 29, 45, 0x0B4, + DCD PDMA_CH0_1_IRQHandler ; 30, 46, 0x0B8, + DCD PDMA_CH2_5_IRQHandler ; 31, 47, 0x0BC, + +; Reset handler routine +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + LDR R0, =BootProcess + BLX R0 + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +BootProcess PROC + LDR R0, =0x40080300 + LDR R1,[R0, #0x10] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x14] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x18] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x1C] + CMP R1, #0 + BEQ BP2 +BP1 LDR R0, =0x40080180 + LDR R1,[R0, #0xC] + LSLS R1, R1, #4 + LSRS R1, R1, #20 + CMP R1, #0 + BEQ BP3 + CMP R1, #5 + BEQ BP3 + CMP R1, #6 + BEQ BP3 +BP2 DSB + LDR R0, =0x20000000 + LDR R1, =0x05fa0004 + STR R1, [R0] + LDR R1, =0xe000ed00 + LDR R0, =0x05fa0004 + STR R0, [R1, #0xC] + DSB + B . +BP3 LDR R0, =0x20000000 + LDR R1, [R0] + LDR R0, =0x05fa0004 + CMP R0, R1 + BEQ BP4 + BX LR +BP4 LDR R0, =0x40088100 + LDR R1, =0x00000001 + STR R1, [R0] + LDR R0, =0x20000000 + LDR R1, =0x0 + STR R1, [R0] + BX LR + ENDP + +; Dummy Exception Handlers +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP + +HardFault_Handler PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP + +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP + +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP + +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + EXPORT LVD_BOD_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT EVWUP_IRQHandler [WEAK] + EXPORT EXTI0_1_IRQHandler [WEAK] + EXPORT EXTI2_3_IRQHandler [WEAK] + EXPORT EXTI4_15_IRQHandler [WEAK] + EXPORT ADC_IRQHandler [WEAK] + EXPORT PWM2_IRQHandler [WEAK] + EXPORT GPTM0_IRQHandler [WEAK] + EXPORT SCTM0_IRQHandler [WEAK] + EXPORT SCTM1_IRQHandler [WEAK] + EXPORT PWM0_IRQHandler [WEAK] + EXPORT PWM1_IRQHandler [WEAK] + EXPORT BFTM0_IRQHandler [WEAK] + EXPORT BFTM1_IRQHandler [WEAK] + EXPORT I2C0_IRQHandler [WEAK] + EXPORT I2C1_IRQHandler [WEAK] + EXPORT SPI0_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT UART0_IRQHandler [WEAK] + EXPORT UART1_IRQHandler [WEAK] + EXPORT SLED0_IRQHandler [WEAK] + EXPORT SLED1_IRQHandler [WEAK] + EXPORT USB_IRQHandler [WEAK] + EXPORT PDMA_CH0_1_IRQHandler [WEAK] + EXPORT PDMA_CH2_5_IRQHandler [WEAK] + +LVD_BOD_IRQHandler +RTC_IRQHandler +FLASH_IRQHandler +EVWUP_IRQHandler +EXTI0_1_IRQHandler +EXTI2_3_IRQHandler +EXTI4_15_IRQHandler +ADC_IRQHandler +PWM2_IRQHandler +GPTM0_IRQHandler +SCTM0_IRQHandler +SCTM1_IRQHandler +PWM0_IRQHandler +PWM1_IRQHandler +BFTM0_IRQHandler +BFTM1_IRQHandler +I2C0_IRQHandler +I2C1_IRQHandler +SPI0_IRQHandler +SPI1_IRQHandler +UART0_IRQHandler +UART1_IRQHandler +SLED0_IRQHandler +SLED1_IRQHandler +USB_IRQHandler +PDMA_CH0_1_IRQHandler +PDMA_CH2_5_IRQHandler + B . + ENDP + + ALIGN + +;******************************************************************************* +; User Stack and Heap initialization +;******************************************************************************* + IF :DEF:__MICROLIB + + EXPORT __HT_check_heap + EXPORT __HT_check_sp + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, = (Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + + ENDIF + + END diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f50431_41.s b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f50431_41.s new file mode 100644 index 0000000000..be3f3ca0f7 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f50431_41.s @@ -0,0 +1,264 @@ +;/*---------------------------------------------------------------------------------------------------------*/ +;/* Holtek Semiconductor Inc. */ +;/* */ +;/* Copyright (C) Holtek Semiconductor Inc. */ +;/* All rights reserved. */ +;/* */ +;/*----------------------------------------------------------------------------------------------------------- +; File Name : startup_ht32f5xxxx_14.s +; Version : $Rev:: 6793 $ +; Date : $Date:: 2023-03-14 #$ +; Description : Startup code. +;-----------------------------------------------------------------------------------------------------------*/ + +; Supported Device +; ======================================== +; HT32F50442, HT32F50452 +; HT32F50431, HT32F50441 + +;/* <<< Use Configuration Wizard in Context Menu >>> */ + +;// HT32 Device +;// Select HT32 Device for the assembly setting. +;// Notice that the project's Asm Define has the higher priority. +;// <0=> By Project Asm Define +;// <26=> HT32F50442/52 +;// <30=> HT32F50431/41 +USE_HT32_CHIP_SET EQU 30 ; Notice that the project's Asm Define has the higher priority. + +_HT32FWID EQU 0xFFFFFFFF +;_HT32FWID EQU 0x00050442 +;_HT32FWID EQU 0x00050452 +;_HT32FWID EQU 0x00050431 +;_HT32FWID EQU 0x00050441 + +HT32F50442_52 EQU 26 +HT32F50431_41 EQU 30 + + IF USE_HT32_CHIP_SET=0 + ; Use project's Asm Define setting (default) + ELSE + IF :DEF:USE_HT32_CHIP + ; Use project's Asm Define setting (higher priority than the "USE_HT32_CHIP_SET") + ELSE + ; Use "USE_HT32_CHIP_SET" in the "startup_ht32xxxxx_xx.s" file +USE_HT32_CHIP EQU USE_HT32_CHIP_SET + ENDIF + ENDIF + +; Amount of memory (in bytes) allocated for Stack and Heap +; Tailor those values to your application needs +;// Stack Size (in Bytes, must 8 byte aligned) <0-16384:8> +Stack_Size EQU 512 + + AREA STACK, NOINIT, READWRITE, ALIGN = 3 +__HT_check_sp +Stack_Mem SPACE Stack_Size +__initial_sp + +;// Heap Size (in Bytes) <0-16384:8> +Heap_Size EQU 0 + + AREA HEAP, NOINIT, READWRITE, ALIGN = 3 +__HT_check_heap +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + PRESERVE8 + THUMB + +;******************************************************************************* +; Fill-up the Vector Table entries with the exceptions ISR address +;******************************************************************************* + AREA RESET, CODE, READONLY + EXPORT __Vectors +_RESERVED EQU 0xFFFFFFFF +__Vectors + DCD __initial_sp ; ---, 00, 0x000, Top address of Stack + DCD Reset_Handler ; ---, 01, 0x004, Reset Handler + DCD NMI_Handler ; -14, 02, 0x008, NMI Handler + DCD HardFault_Handler ; -13, 03, 0x00C, Hard Fault Handler + DCD _RESERVED ; ---, 04, 0x010, Reserved + DCD _RESERVED ; ---, 05, 0x014, Reserved + DCD _RESERVED ; ---, 06, 0x018, Reserved + DCD _RESERVED ; ---, 07, 0x01C, Reserved + DCD _HT32FWID ; ---, 08, 0x020, Reserved + DCD _RESERVED ; ---, 09, 0x024, Reserved + DCD _RESERVED ; ---, 10, 0x028, Reserved + DCD SVC_Handler ; -05, 11, 0x02C, SVC Handler + DCD _RESERVED ; ---, 12, 0x030, Reserved + DCD _RESERVED ; ---, 13, 0x034, Reserved + DCD PendSV_Handler ; -02, 14, 0x038, PendSV Handler + DCD SysTick_Handler ; -01, 15, 0x03C, SysTick Handler + + ; External Interrupt Handler + DCD LVD_BOD_IRQHandler ; 00, 16, 0x040, + DCD RTC_IRQHandler ; 01, 17, 0x044, + DCD FLASH_IRQHandler ; 02, 18, 0x048, + DCD EVWUP_IRQHandler ; 03, 19, 0x04C, + DCD EXTI0_1_IRQHandler ; 04, 20, 0x050, + DCD EXTI2_3_IRQHandler ; 05, 21, 0x054, + DCD EXTI4_15_IRQHandler ; 06, 22, 0x058, + IF (USE_HT32_CHIP=HT32F50442_52) + DCD COMP_IRQHandler ; 07, 23, 0x05C, + ELSE + DCD _RESERVED ; 07, 23, 0x05C, + ENDIF + DCD ADC_IRQHandler ; 08, 24, 0x060, + DCD _RESERVED ; 09, 25, 0x064, + DCD MCTM0_IRQHandler ; 10, 26, 0x068, + DCD _RESERVED ; 11, 27, 0x06C, + DCD GPTM0_IRQHandler ; 12, 28, 0x070, + DCD _RESERVED ; 13, 29, 0x074, + DCD _RESERVED ; 14, 30, 0x078, + DCD PWM0_IRQHandler ; 15, 31, 0x07C, + IF (USE_HT32_CHIP=HT32F50442_52) + DCD PWM1_IRQHandler ; 16, 32, 0x080, + ELSE + DCD _RESERVED ; 16, 32, 0x080, + ENDIF + DCD BFTM0_IRQHandler ; 17, 33, 0x084, + DCD BFTM1_IRQHandler ; 18, 34, 0x088, + DCD I2C0_IRQHandler ; 19, 35, 0x08C, + DCD I2C1_IRQHandler ; 20, 36, 0x090, + DCD SPI0_IRQHandler ; 21, 37, 0x094, + DCD SPI1_IRQHandler ; 22, 38, 0x098, + DCD USART0_IRQHandler ; 23, 39, 0x09C, + IF (USE_HT32_CHIP=HT32F50442_52) + DCD USART1_IRQHandler ; 24, 40, 0x0A0, + ELSE + DCD _RESERVED ; 24, 40, 0x0A0, + ENDIF + DCD UART0_IRQHandler ; 25, 41, 0x0A4, + DCD UART1_IRQHandler ; 26, 42, 0x0A8, + DCD _RESERVED ; 27, 43, 0x0AC, + DCD _RESERVED ; 28, 44, 0x0B0, + DCD LEDC_IRQHandler ; 29, 45, 0x0B4, + DCD PDMA_CH0_1_IRQHandler ; 30, 46, 0x0B8, + DCD PDMA_CH2_5_IRQHandler ; 31, 47, 0x0BC, + +; Reset handler routine +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception Handlers +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP + +HardFault_Handler PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP + +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP + +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP + +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + EXPORT LVD_BOD_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT EVWUP_IRQHandler [WEAK] + EXPORT EXTI0_1_IRQHandler [WEAK] + EXPORT EXTI2_3_IRQHandler [WEAK] + EXPORT EXTI4_15_IRQHandler [WEAK] + EXPORT COMP_IRQHandler [WEAK] + EXPORT ADC_IRQHandler [WEAK] + EXPORT MCTM0_IRQHandler [WEAK] + EXPORT GPTM0_IRQHandler [WEAK] + EXPORT PWM0_IRQHandler [WEAK] + EXPORT PWM1_IRQHandler [WEAK] + EXPORT BFTM0_IRQHandler [WEAK] + EXPORT BFTM1_IRQHandler [WEAK] + EXPORT I2C0_IRQHandler [WEAK] + EXPORT I2C1_IRQHandler [WEAK] + EXPORT SPI0_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT USART0_IRQHandler [WEAK] + EXPORT USART1_IRQHandler [WEAK] + EXPORT UART0_IRQHandler [WEAK] + EXPORT UART1_IRQHandler [WEAK] + EXPORT LEDC_IRQHandler [WEAK] + EXPORT PDMA_CH0_1_IRQHandler [WEAK] + EXPORT PDMA_CH2_5_IRQHandler [WEAK] + +LVD_BOD_IRQHandler +RTC_IRQHandler +FLASH_IRQHandler +EVWUP_IRQHandler +EXTI0_1_IRQHandler +EXTI2_3_IRQHandler +EXTI4_15_IRQHandler +COMP_IRQHandler +ADC_IRQHandler +MCTM0_IRQHandler +GPTM0_IRQHandler +PWM0_IRQHandler +PWM1_IRQHandler +BFTM0_IRQHandler +BFTM1_IRQHandler +I2C0_IRQHandler +I2C1_IRQHandler +SPI0_IRQHandler +SPI1_IRQHandler +USART0_IRQHandler +USART1_IRQHandler +UART0_IRQHandler +UART1_IRQHandler +LEDC_IRQHandler +PDMA_CH0_1_IRQHandler +PDMA_CH2_5_IRQHandler + B . + ENDP + + ALIGN + +;******************************************************************************* +; User Stack and Heap initialization +;******************************************************************************* + IF :DEF:__MICROLIB + + EXPORT __HT_check_heap + EXPORT __HT_check_sp + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, = (Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + + ENDIF + + END diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f50442_52.s b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f50442_52.s new file mode 100644 index 0000000000..214cdf9e32 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f50442_52.s @@ -0,0 +1,264 @@ +;/*---------------------------------------------------------------------------------------------------------*/ +;/* Holtek Semiconductor Inc. */ +;/* */ +;/* Copyright (C) Holtek Semiconductor Inc. */ +;/* All rights reserved. */ +;/* */ +;/*----------------------------------------------------------------------------------------------------------- +; File Name : startup_ht32f5xxxx_14.s +; Version : $Rev:: 6793 $ +; Date : $Date:: 2023-03-14 #$ +; Description : Startup code. +;-----------------------------------------------------------------------------------------------------------*/ + +; Supported Device +; ======================================== +; HT32F50442, HT32F50452 +; HT32F50431, HT32F50441 + +;/* <<< Use Configuration Wizard in Context Menu >>> */ + +;// HT32 Device +;// Select HT32 Device for the assembly setting. +;// Notice that the project's Asm Define has the higher priority. +;// <0=> By Project Asm Define +;// <26=> HT32F50442/52 +;// <30=> HT32F50431/41 +USE_HT32_CHIP_SET EQU 26 ; Notice that the project's Asm Define has the higher priority. + +_HT32FWID EQU 0xFFFFFFFF +;_HT32FWID EQU 0x00050442 +;_HT32FWID EQU 0x00050452 +;_HT32FWID EQU 0x00050431 +;_HT32FWID EQU 0x00050441 + +HT32F50442_52 EQU 26 +HT32F50431_41 EQU 30 + + IF USE_HT32_CHIP_SET=0 + ; Use project's Asm Define setting (default) + ELSE + IF :DEF:USE_HT32_CHIP + ; Use project's Asm Define setting (higher priority than the "USE_HT32_CHIP_SET") + ELSE + ; Use "USE_HT32_CHIP_SET" in the "startup_ht32xxxxx_xx.s" file +USE_HT32_CHIP EQU USE_HT32_CHIP_SET + ENDIF + ENDIF + +; Amount of memory (in bytes) allocated for Stack and Heap +; Tailor those values to your application needs +;// Stack Size (in Bytes, must 8 byte aligned) <0-16384:8> +Stack_Size EQU 512 + + AREA STACK, NOINIT, READWRITE, ALIGN = 3 +__HT_check_sp +Stack_Mem SPACE Stack_Size +__initial_sp + +;// Heap Size (in Bytes) <0-16384:8> +Heap_Size EQU 0 + + AREA HEAP, NOINIT, READWRITE, ALIGN = 3 +__HT_check_heap +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + PRESERVE8 + THUMB + +;******************************************************************************* +; Fill-up the Vector Table entries with the exceptions ISR address +;******************************************************************************* + AREA RESET, CODE, READONLY + EXPORT __Vectors +_RESERVED EQU 0xFFFFFFFF +__Vectors + DCD __initial_sp ; ---, 00, 0x000, Top address of Stack + DCD Reset_Handler ; ---, 01, 0x004, Reset Handler + DCD NMI_Handler ; -14, 02, 0x008, NMI Handler + DCD HardFault_Handler ; -13, 03, 0x00C, Hard Fault Handler + DCD _RESERVED ; ---, 04, 0x010, Reserved + DCD _RESERVED ; ---, 05, 0x014, Reserved + DCD _RESERVED ; ---, 06, 0x018, Reserved + DCD _RESERVED ; ---, 07, 0x01C, Reserved + DCD _HT32FWID ; ---, 08, 0x020, Reserved + DCD _RESERVED ; ---, 09, 0x024, Reserved + DCD _RESERVED ; ---, 10, 0x028, Reserved + DCD SVC_Handler ; -05, 11, 0x02C, SVC Handler + DCD _RESERVED ; ---, 12, 0x030, Reserved + DCD _RESERVED ; ---, 13, 0x034, Reserved + DCD PendSV_Handler ; -02, 14, 0x038, PendSV Handler + DCD SysTick_Handler ; -01, 15, 0x03C, SysTick Handler + + ; External Interrupt Handler + DCD LVD_BOD_IRQHandler ; 00, 16, 0x040, + DCD RTC_IRQHandler ; 01, 17, 0x044, + DCD FLASH_IRQHandler ; 02, 18, 0x048, + DCD EVWUP_IRQHandler ; 03, 19, 0x04C, + DCD EXTI0_1_IRQHandler ; 04, 20, 0x050, + DCD EXTI2_3_IRQHandler ; 05, 21, 0x054, + DCD EXTI4_15_IRQHandler ; 06, 22, 0x058, + IF (USE_HT32_CHIP=HT32F50442_52) + DCD COMP_IRQHandler ; 07, 23, 0x05C, + ELSE + DCD _RESERVED ; 07, 23, 0x05C, + ENDIF + DCD ADC_IRQHandler ; 08, 24, 0x060, + DCD _RESERVED ; 09, 25, 0x064, + DCD MCTM0_IRQHandler ; 10, 26, 0x068, + DCD _RESERVED ; 11, 27, 0x06C, + DCD GPTM0_IRQHandler ; 12, 28, 0x070, + DCD _RESERVED ; 13, 29, 0x074, + DCD _RESERVED ; 14, 30, 0x078, + DCD PWM0_IRQHandler ; 15, 31, 0x07C, + IF (USE_HT32_CHIP=HT32F50442_52) + DCD PWM1_IRQHandler ; 16, 32, 0x080, + ELSE + DCD _RESERVED ; 16, 32, 0x080, + ENDIF + DCD BFTM0_IRQHandler ; 17, 33, 0x084, + DCD BFTM1_IRQHandler ; 18, 34, 0x088, + DCD I2C0_IRQHandler ; 19, 35, 0x08C, + DCD I2C1_IRQHandler ; 20, 36, 0x090, + DCD SPI0_IRQHandler ; 21, 37, 0x094, + DCD SPI1_IRQHandler ; 22, 38, 0x098, + DCD USART0_IRQHandler ; 23, 39, 0x09C, + IF (USE_HT32_CHIP=HT32F50442_52) + DCD USART1_IRQHandler ; 24, 40, 0x0A0, + ELSE + DCD _RESERVED ; 24, 40, 0x0A0, + ENDIF + DCD UART0_IRQHandler ; 25, 41, 0x0A4, + DCD UART1_IRQHandler ; 26, 42, 0x0A8, + DCD _RESERVED ; 27, 43, 0x0AC, + DCD _RESERVED ; 28, 44, 0x0B0, + DCD LEDC_IRQHandler ; 29, 45, 0x0B4, + DCD PDMA_CH0_1_IRQHandler ; 30, 46, 0x0B8, + DCD PDMA_CH2_5_IRQHandler ; 31, 47, 0x0BC, + +; Reset handler routine +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception Handlers +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP + +HardFault_Handler PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP + +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP + +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP + +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + EXPORT LVD_BOD_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT EVWUP_IRQHandler [WEAK] + EXPORT EXTI0_1_IRQHandler [WEAK] + EXPORT EXTI2_3_IRQHandler [WEAK] + EXPORT EXTI4_15_IRQHandler [WEAK] + EXPORT COMP_IRQHandler [WEAK] + EXPORT ADC_IRQHandler [WEAK] + EXPORT MCTM0_IRQHandler [WEAK] + EXPORT GPTM0_IRQHandler [WEAK] + EXPORT PWM0_IRQHandler [WEAK] + EXPORT PWM1_IRQHandler [WEAK] + EXPORT BFTM0_IRQHandler [WEAK] + EXPORT BFTM1_IRQHandler [WEAK] + EXPORT I2C0_IRQHandler [WEAK] + EXPORT I2C1_IRQHandler [WEAK] + EXPORT SPI0_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT USART0_IRQHandler [WEAK] + EXPORT USART1_IRQHandler [WEAK] + EXPORT UART0_IRQHandler [WEAK] + EXPORT UART1_IRQHandler [WEAK] + EXPORT LEDC_IRQHandler [WEAK] + EXPORT PDMA_CH0_1_IRQHandler [WEAK] + EXPORT PDMA_CH2_5_IRQHandler [WEAK] + +LVD_BOD_IRQHandler +RTC_IRQHandler +FLASH_IRQHandler +EVWUP_IRQHandler +EXTI0_1_IRQHandler +EXTI2_3_IRQHandler +EXTI4_15_IRQHandler +COMP_IRQHandler +ADC_IRQHandler +MCTM0_IRQHandler +GPTM0_IRQHandler +PWM0_IRQHandler +PWM1_IRQHandler +BFTM0_IRQHandler +BFTM1_IRQHandler +I2C0_IRQHandler +I2C1_IRQHandler +SPI0_IRQHandler +SPI1_IRQHandler +USART0_IRQHandler +USART1_IRQHandler +UART0_IRQHandler +UART1_IRQHandler +LEDC_IRQHandler +PDMA_CH0_1_IRQHandler +PDMA_CH2_5_IRQHandler + B . + ENDP + + ALIGN + +;******************************************************************************* +; User Stack and Heap initialization +;******************************************************************************* + IF :DEF:__MICROLIB + + EXPORT __HT_check_heap + EXPORT __HT_check_sp + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, = (Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + + ENDIF + + END diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f52142.s b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f52142.s new file mode 100644 index 0000000000..db72cb363f --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f52142.s @@ -0,0 +1,403 @@ +;/*---------------------------------------------------------------------------------------------------------*/ +;/* Holtek Semiconductor Inc. */ +;/* */ +;/* Copyright (C) Holtek Semiconductor Inc. */ +;/* All rights reserved. */ +;/* */ +;/*----------------------------------------------------------------------------------------------------------- +; File Name : startup_ht32f5xxxx_03.s +; Version : $Rev:: 6877 $ +; Date : $Date:: 2023-05-04 #$ +; Description : Startup code. +;-----------------------------------------------------------------------------------------------------------*/ + +; Supported Device +; ======================================== +; HT32F0008 +; HT32F52142 +; HT32F52344, HT32F52354 +; HT32F52357, HT32F52367 +; HT50F3200T + +;/* <<< Use Configuration Wizard in Context Menu >>> */ + +;// HT32 Device +;// Select HT32 Device for the assembly setting. +;// Notice that the project's Asm Define has the higher priority. +;// <0=> By Project Asm Define +;// <6=> HT32F0008 +;// <6=> HT32F52142 +;// <9=> HT32F52344/54 +;// <11=> HT32F52357/67 +;// <11=> HT50F3200T +USE_HT32_CHIP_SET EQU 6 ; Notice that the project's Asm Define has the higher priority. + +_HT32FWID EQU 0xFFFFFFFF +;_HT32FWID EQU 0x00000008 +;_HT32FWID EQU 0x00052142 +;_HT32FWID EQU 0x00052344 +;_HT32FWID EQU 0x00052354 +;_HT32FWID EQU 0x00052357 +;_HT32FWID EQU 0x00052367 +;_HT32FWID EQU 0x0003200F + +HT32F0008 EQU 6 +HT32F52142 EQU 6 +HT32F52344_54 EQU 9 +HT32F52357_67 EQU 11 +HT50F3200T EQU 11 + + IF USE_HT32_CHIP_SET=0 + ; Use project's Asm Define setting (default) + ELSE + IF :DEF:USE_HT32_CHIP + ; Use project's Asm Define setting (higher priority than the "USE_HT32_CHIP_SET") + ELSE + ; Use "USE_HT32_CHIP_SET" in the "startup_ht32xxxxx_xx.s" file +USE_HT32_CHIP EQU USE_HT32_CHIP_SET + ENDIF + ENDIF + +; Amount of memory (in bytes) allocated for Stack and Heap +; Tailor those values to your application needs +;// Stack Size (in Bytes, must 8 byte aligned) <0-16384:8> +Stack_Size EQU 512 + + AREA STACK, NOINIT, READWRITE, ALIGN = 3 +__HT_check_sp +Stack_Mem SPACE Stack_Size +__initial_sp + +;// Heap Size (in Bytes) <0-16384:8> +Heap_Size EQU 0 + + AREA HEAP, NOINIT, READWRITE, ALIGN = 3 +__HT_check_heap +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + PRESERVE8 + THUMB + +;******************************************************************************* +; Fill-up the Vector Table entries with the exceptions ISR address +;******************************************************************************* + AREA RESET, CODE, READONLY + EXPORT __Vectors +_RESERVED EQU 0xFFFFFFFF +__Vectors + DCD __initial_sp ; ---, 00, 0x000, Top address of Stack + DCD Reset_Handler ; ---, 01, 0x004, Reset Handler + DCD NMI_Handler ; -14, 02, 0x008, NMI Handler + DCD HardFault_Handler ; -13, 03, 0x00C, Hard Fault Handler + DCD _RESERVED ; ---, 04, 0x010, Reserved + DCD _RESERVED ; ---, 05, 0x014, Reserved + DCD _RESERVED ; ---, 06, 0x018, Reserved + DCD _RESERVED ; ---, 07, 0x01C, Reserved + DCD _HT32FWID ; ---, 08, 0x020, Reserved + DCD _RESERVED ; ---, 09, 0x024, Reserved + DCD _RESERVED ; ---, 10, 0x028, Reserved + DCD SVC_Handler ; -05, 11, 0x02C, SVC Handler + DCD _RESERVED ; ---, 12, 0x030, Reserved + DCD _RESERVED ; ---, 13, 0x034, Reserved + DCD PendSV_Handler ; -02, 14, 0x038, PendSV Handler + DCD SysTick_Handler ; -01, 15, 0x03C, SysTick Handler + + ; External Interrupt Handler + DCD LVD_BOD_IRQHandler ; 00, 16, 0x040, + DCD RTC_IRQHandler ; 01, 17, 0x044, + DCD FLASH_IRQHandler ; 02, 18, 0x048, + DCD EVWUP_IRQHandler ; 03, 19, 0x04C, + DCD EXTI0_1_IRQHandler ; 04, 20, 0x050, + DCD EXTI2_3_IRQHandler ; 05, 21, 0x054, + DCD EXTI4_15_IRQHandler ; 06, 22, 0x058, + IF (USE_HT32_CHIP=HT32F0008) + DCD _RESERVED ; 07, 23, 0x05C, + ENDIF + IF (USE_HT32_CHIP=HT32F52344_54) + DCD COMP_IRQHandler ; 07, 23, 0x05C, + ENDIF + IF (USE_HT32_CHIP=HT32F52357_67) + DCD COMP_DAC_IRQHandler ; 07, 23, 0x05C, + ENDIF + IF (USE_HT32_CHIP=HT32F0008) + DCD _RESERVED ; 08, 24, 0x060, + ELSE + DCD ADC_IRQHandler ; 08, 24, 0x060, + ENDIF + IF (USE_HT32_CHIP=HT32F52357_67) + DCD AES_IRQHandler ; 09, 25, 0x064, + ELSE + DCD _RESERVED ; 09, 25, 0x064, + ENDIF + IF (USE_HT32_CHIP=HT32F0008) + DCD _RESERVED ; 10, 26, 0x068, + ELSE + DCD MCTM0_IRQHandler ; 10, 26, 0x068, + ENDIF + IF (USE_HT32_CHIP=HT32F52357_67) + DCD QSPI_IRQHandler ; 11, 27, 0x06C, + ELSE + DCD _RESERVED ; 11, 27, 0x06C, + ENDIF + DCD GPTM0_IRQHandler ; 12, 28, 0x070, + IF (USE_HT32_CHIP=HT32F0008) + DCD _RESERVED ; 13, 29, 0x074, + DCD _RESERVED ; 14, 30, 0x078, + ELSE + DCD SCTM0_IRQHandler ; 13, 29, 0x074, + DCD SCTM1_IRQHandler ; 14, 30, 0x078, + ENDIF + IF (USE_HT32_CHIP=HT32F0008) || (USE_HT32_CHIP=HT32F52357_67) + DCD PWM0_IRQHandler ; 15, 31, 0x07C, + DCD PWM1_IRQHandler ; 16, 32, 0x080, + ENDIF + IF (USE_HT32_CHIP=HT32F52344_54) + DCD _RESERVED ; 15, 31, 0x07C, + DCD _RESERVED ; 16, 32, 0x080, + ENDIF + DCD BFTM0_IRQHandler ; 17, 33, 0x084, + DCD BFTM1_IRQHandler ; 18, 34, 0x088, + DCD I2C0_IRQHandler ; 19, 35, 0x08C, + IF (USE_HT32_CHIP=HT32F0008) || (USE_HT32_CHIP=HT32F52344_54) + DCD _RESERVED ; 20, 36, 0x090, + ELSE + DCD I2C1_IRQHandler ; 20, 36, 0x090, + ENDIF + DCD SPI0_IRQHandler ; 21, 37, 0x094, + IF (USE_HT32_CHIP=HT32F0008) + DCD _RESERVED ; 22, 38, 0x098, + ELSE + DCD SPI1_IRQHandler ; 22, 38, 0x098, + ENDIF + IF (USE_HT32_CHIP=HT32F52344_54) + DCD _RESERVED ; 23, 39, 0x09C, + ELSE + DCD USART0_IRQHandler ; 23, 39, 0x09C, + ENDIF + IF (USE_HT32_CHIP=HT32F0008) + DCD _RESERVED ; 24, 40, 0x0A0, + DCD UART0_IRQHandler ; 25, 41, 0x0A4, + DCD _RESERVED ; 26, 42, 0x0A8, + ENDIF + IF (USE_HT32_CHIP=HT32F52344_54) + DCD _RESERVED ; 24, 40, 0x0A0, + DCD UART0_IRQHandler ; 25, 41, 0x0A4, + DCD UART1_IRQHandler ; 26, 42, 0x0A8, + ENDIF + IF (USE_HT32_CHIP=HT32F52357_67) + DCD USART1_IRQHandler ; 24, 40, 0x0A0, + DCD UART0_UART2_IRQHandler ; 25, 41, 0x0A4, + DCD UART1_UART3_IRQHandler ; 26, 42, 0x0A8, + ENDIF + IF (USE_HT32_CHIP=HT32F52357_67) + DCD SCI_IRQHandler ; 27, 43, 0xAC, + ELSE + DCD _RESERVED ; 27, 43, 0xAC, + ENDIF + IF (USE_HT32_CHIP=HT32F0008) + DCD AES_IRQHandler ; 28, 44, 0x0B0, + ENDIF + IF (USE_HT32_CHIP=HT32F52344_54) + DCD _RESERVED ; 28, 44, 0x0B0, + ENDIF + IF (USE_HT32_CHIP=HT32F52357_67) + DCD I2S_IRQHandler ; 28, 44, 0x0B0, + ENDIF + DCD USB_IRQHandler ; 29, 45, 0x0B4, + DCD PDMA_CH0_1_IRQHandler ; 30, 46, 0x0B8, + DCD PDMA_CH2_5_IRQHandler ; 31, 47, 0x0BC, + +; Reset handler routine +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + LDR R0, =BootProcess + BLX R0 + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +BootProcess PROC + LDR R0, =0x40080300 + LDR R1,[R0, #0x10] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x14] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x18] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x1C] + CMP R1, #0 + BEQ BP2 +BP1 LDR R0, =0x40080180 + LDR R1,[R0, #0xC] + LSLS R1, R1, #4 + LSRS R1, R1, #20 + CMP R1, #0 + BEQ BP3 + CMP R1, #5 + BEQ BP3 + CMP R1, #6 + BEQ BP3 +BP2 DSB + LDR R0, =0x20000000 + LDR R1, =0x05fa0004 + STR R1, [R0] + LDR R1, =0xe000ed00 + LDR R0, =0x05fa0004 + STR R0, [R1, #0xC] + DSB + B . +BP3 LDR R0, =0x20000000 + LDR R1, [R0] + LDR R0, =0x05fa0004 + CMP R0, R1 + BEQ BP4 + BX LR +BP4 LDR R0, =0x40088100 + LDR R1, =0x00000001 + STR R1, [R0] + LDR R0, =0x20000000 + LDR R1, =0x0 + STR R1, [R0] + BX LR + ENDP + +; Dummy Exception Handlers +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP + +HardFault_Handler PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP + +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP + +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP + +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + EXPORT LVD_BOD_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT EVWUP_IRQHandler [WEAK] + EXPORT EXTI0_1_IRQHandler [WEAK] + EXPORT EXTI2_3_IRQHandler [WEAK] + EXPORT EXTI4_15_IRQHandler [WEAK] + EXPORT COMP_IRQHandler [WEAK] + EXPORT COMP_DAC_IRQHandler [WEAK] + EXPORT ADC_IRQHandler [WEAK] + EXPORT MCTM0_IRQHandler [WEAK] + EXPORT GPTM0_IRQHandler [WEAK] + EXPORT SCTM0_IRQHandler [WEAK] + EXPORT SCTM1_IRQHandler [WEAK] + EXPORT PWM0_IRQHandler [WEAK] + EXPORT PWM1_IRQHandler [WEAK] + EXPORT BFTM0_IRQHandler [WEAK] + EXPORT BFTM1_IRQHandler [WEAK] + EXPORT I2C0_IRQHandler [WEAK] + EXPORT I2C1_IRQHandler [WEAK] + EXPORT SPI0_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT QSPI_IRQHandler [WEAK] + EXPORT USART0_IRQHandler [WEAK] + EXPORT USART1_IRQHandler [WEAK] + EXPORT UART0_IRQHandler [WEAK] + EXPORT UART1_IRQHandler [WEAK] + EXPORT UART0_UART2_IRQHandler [WEAK] + EXPORT UART1_UART3_IRQHandler [WEAK] + EXPORT SCI_IRQHandler [WEAK] + EXPORT I2S_IRQHandler [WEAK] + EXPORT AES_IRQHandler [WEAK] + EXPORT USB_IRQHandler [WEAK] + EXPORT PDMA_CH0_1_IRQHandler [WEAK] + EXPORT PDMA_CH2_5_IRQHandler [WEAK] + +LVD_BOD_IRQHandler +RTC_IRQHandler +FLASH_IRQHandler +EVWUP_IRQHandler +EXTI0_1_IRQHandler +EXTI2_3_IRQHandler +EXTI4_15_IRQHandler +COMP_IRQHandler +COMP_DAC_IRQHandler +ADC_IRQHandler +MCTM0_IRQHandler +GPTM0_IRQHandler +SCTM0_IRQHandler +SCTM1_IRQHandler +PWM0_IRQHandler +PWM1_IRQHandler +BFTM0_IRQHandler +BFTM1_IRQHandler +I2C0_IRQHandler +I2C1_IRQHandler +SPI0_IRQHandler +SPI1_IRQHandler +QSPI_IRQHandler +USART0_IRQHandler +USART1_IRQHandler +UART0_IRQHandler +UART1_IRQHandler +UART0_UART2_IRQHandler +UART1_UART3_IRQHandler +SCI_IRQHandler +I2S_IRQHandler +AES_IRQHandler +USB_IRQHandler +PDMA_CH0_1_IRQHandler +PDMA_CH2_5_IRQHandler + B . + ENDP + + ALIGN + +;******************************************************************************* +; User Stack and Heap initialization +;******************************************************************************* + IF :DEF:__MICROLIB + + EXPORT __HT_check_heap + EXPORT __HT_check_sp + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, = (Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + + ENDIF + + END diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f52220_30.s b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f52220_30.s new file mode 100644 index 0000000000..ae562b2a89 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f52220_30.s @@ -0,0 +1,482 @@ +;/*---------------------------------------------------------------------------------------------------------*/ +;/* Holtek Semiconductor Inc. */ +;/* */ +;/* Copyright (C) Holtek Semiconductor Inc. */ +;/* All rights reserved. */ +;/* */ +;/*----------------------------------------------------------------------------------------------------------- +; File Name : startup_ht32f5xxxx_01.s +; Version : $Rev:: 6953 $ +; Date : $Date:: 2023-05-30 #$ +; Description : Startup code. +;-----------------------------------------------------------------------------------------------------------*/ + +; Supported Device +; ======================================== +; HT32F52220, HT32F52230 +; HT32F52231, HT32F52241 +; HT32F52331, HT32F52341 +; HT32F52342, HT32F52352 +; HT32F52243, HT32F52253 +; HT32F0008 +; HT32F52344, HT32F52354 +; HT32F0006 +; HT32F61352 +; HT50F32003 +; HT32F62030, HT32F62040, HT32F62050 +; HT32F67741 +; HT32F67232 +; HT32F67233 + +;/* <<< Use Configuration Wizard in Context Menu >>> */ + +;// HT32 Device +;// Select HT32 Device for the assembly setting. +;// Notice that the project's Asm Define has the higher priority. +;// <0=> By Project Asm Define +;// <1=> HT32F52220/30 +;// <2=> HT32F52231/41 +;// <3=> HT32F52331/41 +;// <4=> HT32F52342/52 +;// <5=> HT32F52243/53 +;// <6=> HT32F0008 +;// <9=> HT32F52344/54 +;// <10=> HT32F0006 +;// <10=> HT32F61352 +;// <4=> HT50F32003 +;// <2=> HT32F67741 +;// <1=> HT32F67232 +;// <1=> HT32F67233 +;// <1=> HT32F62030 +;// <2=> HT32F62040 +;// <5=> HT32F62050 +USE_HT32_CHIP_SET EQU 1 ; Notice that the project's Asm Define has the higher priority. + +_HT32FWID EQU 0xFFFFFFFF +;_HT32FWID EQU 0x00052220 +;_HT32FWID EQU 0x00052230 +;_HT32FWID EQU 0x00052231 +;_HT32FWID EQU 0x00052241 +;_HT32FWID EQU 0x00052331 +;_HT32FWID EQU 0x00052341 +;_HT32FWID EQU 0x00052342 +;_HT32FWID EQU 0x00052352 +;_HT32FWID EQU 0x00052243 +;_HT32FWID EQU 0x00052253 +;_HT32FWID EQU 0x00000008 +;_HT32FWID EQU 0x00052344 +;_HT32FWID EQU 0x00052354 +;_HT32FWID EQU 0x00000006 +;_HT32FWID EQU 0x00061352 +;_HT32FWID EQU 0x00032003 +;_HT32FWID EQU 0x00062030 +;_HT32FWID EQU 0x00062040 +;_HT32FWID EQU 0x00062050 +;_HT32FWID EQU 0x00067741 +;_HT32FWID EQU 0x00067232 +;_HT32FWID EQU 0x00067233 + +HT32F52220_30 EQU 1 +HT32F52231_41 EQU 2 +HT32F52331_41 EQU 3 +HT32F52342_52 EQU 4 +HT32F52243_53 EQU 5 +HT32F0008 EQU 6 +HT32F52344_54 EQU 9 +HT32F0006 EQU 10 +HT32F61352 EQU 10 +HT50F32003 EQU 4 +HT32F62030 EQU 1 +HT32F62040 EQU 2 +HT32F62050 EQU 5 +HT32F67741 EQU 2 +HT32F67232 EQU 1 +HT32F67233 EQU 1 + + IF USE_HT32_CHIP_SET=0 + ; Use project's Asm Define setting (default) + ELSE + IF :DEF:USE_HT32_CHIP + ; Use project's Asm Define setting (higher priority than the "USE_HT32_CHIP_SET") + ELSE + ; Use "USE_HT32_CHIP_SET" in the "startup_ht32xxxxx_xx.s" file +USE_HT32_CHIP EQU USE_HT32_CHIP_SET + ENDIF + ENDIF + +; Amount of memory (in bytes) allocated for Stack and Heap +; Tailor those values to your application needs +;// Stack Size (in Bytes, must 8 byte aligned) <0-16384:8> +Stack_Size EQU 512 + + AREA STACK, NOINIT, READWRITE, ALIGN = 3 +__HT_check_sp +Stack_Mem SPACE Stack_Size +__initial_sp + +;// Heap Size (in Bytes) <0-16384:8> +Heap_Size EQU 0 + + AREA HEAP, NOINIT, READWRITE, ALIGN = 3 +__HT_check_heap +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + PRESERVE8 + THUMB + +;******************************************************************************* +; Fill-up the Vector Table entries with the exceptions ISR address +;******************************************************************************* + AREA RESET, CODE, READONLY + EXPORT __Vectors +_RESERVED EQU 0xFFFFFFFF +__Vectors + DCD __initial_sp ; ---, 00, 0x000, Top address of Stack + DCD Reset_Handler ; ---, 01, 0x004, Reset Handler + DCD NMI_Handler ; -14, 02, 0x008, NMI Handler + DCD HardFault_Handler ; -13, 03, 0x00C, Hard Fault Handler + DCD _RESERVED ; ---, 04, 0x010, Reserved + DCD _RESERVED ; ---, 05, 0x014, Reserved + DCD _RESERVED ; ---, 06, 0x018, Reserved + DCD _RESERVED ; ---, 07, 0x01C, Reserved + DCD _HT32FWID ; ---, 08, 0x020, Reserved + DCD _RESERVED ; ---, 09, 0x024, Reserved + DCD _RESERVED ; ---, 10, 0x028, Reserved + DCD SVC_Handler ; -05, 11, 0x02C, SVC Handler + DCD _RESERVED ; ---, 12, 0x030, Reserved + DCD _RESERVED ; ---, 13, 0x034, Reserved + DCD PendSV_Handler ; -02, 14, 0x038, PendSV Handler + DCD SysTick_Handler ; -01, 15, 0x03C, SysTick Handler + + ; External Interrupt Handler + DCD LVD_BOD_IRQHandler ; 00, 16, 0x040, + IF (USE_HT32_CHIP=HT32F52220_30) + DCD _RESERVED ; 01, 17, 0x044, + ELSE + DCD RTC_IRQHandler ; 01, 17, 0x044, + ENDIF + DCD FLASH_IRQHandler ; 02, 18, 0x048, + DCD EVWUP_IRQHandler ; 03, 19, 0x04C, + DCD EXTI0_1_IRQHandler ; 04, 20, 0x050, + DCD EXTI2_3_IRQHandler ; 05, 21, 0x054, + DCD EXTI4_15_IRQHandler ; 06, 22, 0x058, + IF (USE_HT32_CHIP=HT32F52342_52) || (USE_HT32_CHIP=HT32F52344_54) + DCD COMP_IRQHandler ; 07, 23, 0x05C, + ELSE + DCD _RESERVED ; 07, 23, 0x05C, + ENDIF + IF (USE_HT32_CHIP=HT32F0008) + DCD _RESERVED ; 08, 24, 0x060, + ELSE + DCD ADC_IRQHandler ; 08, 24, 0x060, + ENDIF + IF (USE_HT32_CHIP=HT32F52243_53) + DCD I2C2_IRQHandler ; 09, 25, 0x064, + ELSE + DCD _RESERVED ; 09, 25, 0x064, + ENDIF + IF (USE_HT32_CHIP=HT32F52220_30) || (USE_HT32_CHIP=HT32F0008) || (USE_HT32_CHIP=HT32F0006) + DCD _RESERVED ; 10, 26, 0x068, + ELSE + DCD MCTM0_IRQHandler ; 10, 26, 0x068, + ENDIF + IF (USE_HT32_CHIP=HT32F52342_52) + DCD GPTM1_IRQHandler ; 11, 27, 0x06C, + ELSE + DCD _RESERVED ; 11, 27, 0x06C, + ENDIF + DCD GPTM0_IRQHandler ; 12, 28, 0x070, + IF (USE_HT32_CHIP=HT32F0008) + DCD _RESERVED ; 13, 29, 0x074, + DCD _RESERVED ; 14, 30, 0x078, + ELSE + DCD SCTM0_IRQHandler ; 13, 29, 0x074, + DCD SCTM1_IRQHandler ; 14, 30, 0x078, + ENDIF + IF (USE_HT32_CHIP=HT32F52231_41) || (USE_HT32_CHIP=HT32F52331_41) || (USE_HT32_CHIP=HT32F52243_53) || (USE_HT32_CHIP=HT32F0006) + DCD SCTM2_IRQHandler ; 15, 31, 0x07C, + DCD SCTM3_IRQHandler ; 16, 32, 0x080, + ENDIF + IF (USE_HT32_CHIP=HT32F0008) + DCD PWM0_IRQHandler ; 15, 31, 0x07C, + DCD PWM1_IRQHandler ; 16, 32, 0x080, + ENDIF + IF (USE_HT32_CHIP=HT32F52220_30) || (USE_HT32_CHIP=HT32F52342_52) || (USE_HT32_CHIP=HT32F52344_54) + DCD _RESERVED ; 15, 31, 0x07C, + DCD _RESERVED ; 16, 32, 0x080, + ENDIF + DCD BFTM0_IRQHandler ; 17, 33, 0x084, + IF (USE_HT32_CHIP=HT32F52220_30) + DCD _RESERVED ; 18, 34, 0x088, + ELSE + DCD BFTM1_IRQHandler ; 18, 34, 0x088, + ENDIF + DCD I2C0_IRQHandler ; 19, 35, 0x08C, + IF (USE_HT32_CHIP=HT32F52220_30) || (USE_HT32_CHIP=HT32F0008) || (USE_HT32_CHIP=HT32F52344_54) || (USE_HT32_CHIP=HT32F0006) + DCD _RESERVED ; 20, 36, 0x090, + ELSE + DCD I2C1_IRQHandler ; 20, 36, 0x090, + ENDIF + DCD SPI0_IRQHandler ; 21, 37, 0x094, + IF (USE_HT32_CHIP=HT32F52220_30) || (USE_HT32_CHIP=HT32F0008) + DCD _RESERVED ; 22, 38, 0x098, + ELSE + IF (USE_HT32_CHIP=HT32F0006) + DCD QSPI_IRQHandler ; 22, 38, 0x098, + ELSE + DCD SPI1_IRQHandler ; 22, 38, 0x098, + ENDIF + ENDIF + IF (USE_HT32_CHIP=HT32F52344_54) + DCD _RESERVED ; 23, 39, 0x09C, + ELSE + DCD USART0_IRQHandler ; 23, 39, 0x09C, + ENDIF + IF (USE_HT32_CHIP=HT32F52342_52) || (USE_HT32_CHIP=HT32F52243_53) + DCD USART1_IRQHandler ; 24, 40, 0x0A0, + ELSE + DCD _RESERVED ; 24, 40, 0x0A0, + ENDIF + DCD UART0_IRQHandler ; 25, 41, 0x0A4, + IF (USE_HT32_CHIP=HT32F52220_30) || (USE_HT32_CHIP=HT32F0008) || (USE_HT32_CHIP=HT32F0006) + DCD _RESERVED ; 26, 42, 0x0A8, + ELSE + DCD UART1_IRQHandler ; 26, 42, 0x0A8, + ENDIF + IF (USE_HT32_CHIP=HT32F52331_41) || (USE_HT32_CHIP=HT32F52342_52) + DCD SCI_IRQHandler ; 27, 43, 0x0AC, + ENDIF + IF (USE_HT32_CHIP=HT32F52243_53) + DCD UART2_IRQHandler ; 27, 43, 0x0AC, + ENDIF + IF (USE_HT32_CHIP=HT32F0006) + DCD MIDI_IRQHandler ; 27, 43, 0x0AC, + ENDIF + IF (USE_HT32_CHIP=HT32F0008) || (USE_HT32_CHIP=HT32F52344_54) + DCD _RESERVED ; 27, 43, 0xAC, + ENDIF + IF (USE_HT32_CHIP=HT32F52342_52) || (USE_HT32_CHIP=HT32F0006) + DCD I2S_IRQHandler ; 28, 44, 0x0B0, + ENDIF + IF (USE_HT32_CHIP=HT32F52331_41) || (USE_HT32_CHIP=HT32F52344_54) + DCD _RESERVED ; 28, 44, 0x0B0, + ENDIF + IF (USE_HT32_CHIP=HT32F52243_53) + DCD UART3_IRQHandler ; 28, 44, 0x0B0, + ENDIF + IF (USE_HT32_CHIP=HT32F0008) + DCD AES_IRQHandler ; 28, 44, 0x0B0, + ENDIF + IF (USE_HT32_CHIP=HT32F52331_41) || (USE_HT32_CHIP=HT32F52342_52) || (USE_HT32_CHIP=HT32F0008) || (USE_HT32_CHIP=HT32F52344_54) || (USE_HT32_CHIP=HT32F0006) + DCD USB_IRQHandler ; 29, 45, 0x0B4, + ENDIF + IF (USE_HT32_CHIP=HT32F52243_53) + DCD _RESERVED ; 29, 45, 0x0B4, + ENDIF + IF (USE_HT32_CHIP=HT32F52342_52) || (USE_HT32_CHIP=HT32F52243_53) || (USE_HT32_CHIP=HT32F0008) || (USE_HT32_CHIP=HT32F52344_54) || (USE_HT32_CHIP=HT32F0006) + DCD PDMA_CH0_1_IRQHandler ; 30, 46, 0x0B8, + DCD PDMA_CH2_5_IRQHandler ; 31, 47, 0x0BC, + ENDIF + +; Reset handler routine +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + LDR R0, =BootProcess + BLX R0 + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +BootProcess PROC + LDR R0, =0x40080300 + LDR R1,[R0, #0x10] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x14] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x18] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x1C] + CMP R1, #0 + BEQ BP2 +BP1 LDR R0, =0x40080180 + LDR R1,[R0, #0xC] + LSLS R1, R1, #4 + LSRS R1, R1, #20 + CMP R1, #0 + BEQ BP3 + CMP R1, #5 + BEQ BP3 + CMP R1, #6 + BEQ BP3 +BP2 DSB + LDR R0, =0x20000000 + LDR R1, =0x05fa0004 + STR R1, [R0] + LDR R1, =0xe000ed00 + LDR R0, =0x05fa0004 + STR R0, [R1, #0xC] + DSB + B . +BP3 LDR R0, =0x20000000 + LDR R1, [R0] + LDR R0, =0x05fa0004 + CMP R0, R1 + BEQ BP4 + BX LR +BP4 LDR R0, =0x40088100 + LDR R1, =0x00000001 + STR R1, [R0] + LDR R0, =0x20000000 + LDR R1, =0x0 + STR R1, [R0] + BX LR + ENDP + +; Dummy Exception Handlers +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP + +HardFault_Handler PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP + +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP + +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP + +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + EXPORT LVD_BOD_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT EVWUP_IRQHandler [WEAK] + EXPORT EXTI0_1_IRQHandler [WEAK] + EXPORT EXTI2_3_IRQHandler [WEAK] + EXPORT EXTI4_15_IRQHandler [WEAK] + EXPORT COMP_IRQHandler [WEAK] + EXPORT ADC_IRQHandler [WEAK] + EXPORT MCTM0_IRQHandler [WEAK] + EXPORT GPTM1_IRQHandler [WEAK] + EXPORT GPTM0_IRQHandler [WEAK] + EXPORT SCTM0_IRQHandler [WEAK] + EXPORT SCTM1_IRQHandler [WEAK] + EXPORT SCTM2_IRQHandler [WEAK] + EXPORT SCTM3_IRQHandler [WEAK] + EXPORT PWM0_IRQHandler [WEAK] + EXPORT PWM1_IRQHandler [WEAK] + EXPORT BFTM0_IRQHandler [WEAK] + EXPORT BFTM1_IRQHandler [WEAK] + EXPORT I2C0_IRQHandler [WEAK] + EXPORT I2C1_IRQHandler [WEAK] + EXPORT I2C2_IRQHandler [WEAK] + EXPORT SPI0_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT QSPI_IRQHandler [WEAK] + EXPORT USART0_IRQHandler [WEAK] + EXPORT USART1_IRQHandler [WEAK] + EXPORT UART0_IRQHandler [WEAK] + EXPORT UART1_IRQHandler [WEAK] + EXPORT UART2_IRQHandler [WEAK] + EXPORT UART3_IRQHandler [WEAK] + EXPORT SCI_IRQHandler [WEAK] + EXPORT MIDI_IRQHandler [WEAK] + EXPORT I2S_IRQHandler [WEAK] + EXPORT AES_IRQHandler [WEAK] + EXPORT USB_IRQHandler [WEAK] + EXPORT PDMA_CH0_1_IRQHandler [WEAK] + EXPORT PDMA_CH2_5_IRQHandler [WEAK] + +LVD_BOD_IRQHandler +RTC_IRQHandler +FLASH_IRQHandler +EVWUP_IRQHandler +EXTI0_1_IRQHandler +EXTI2_3_IRQHandler +EXTI4_15_IRQHandler +COMP_IRQHandler +ADC_IRQHandler +MCTM0_IRQHandler +GPTM1_IRQHandler +GPTM0_IRQHandler +SCTM0_IRQHandler +SCTM1_IRQHandler +SCTM2_IRQHandler +SCTM3_IRQHandler +PWM0_IRQHandler +PWM1_IRQHandler +BFTM0_IRQHandler +BFTM1_IRQHandler +I2C0_IRQHandler +I2C1_IRQHandler +I2C2_IRQHandler +SPI0_IRQHandler +SPI1_IRQHandler +QSPI_IRQHandler +USART0_IRQHandler +USART1_IRQHandler +UART0_IRQHandler +UART1_IRQHandler +UART2_IRQHandler +UART3_IRQHandler +SCI_IRQHandler +MIDI_IRQHandler +I2S_IRQHandler +AES_IRQHandler +USB_IRQHandler +PDMA_CH0_1_IRQHandler +PDMA_CH2_5_IRQHandler + B . + ENDP + + ALIGN + +;******************************************************************************* +; User Stack and Heap initialization +;******************************************************************************* + IF :DEF:__MICROLIB + + EXPORT __HT_check_heap + EXPORT __HT_check_sp + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, = (Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + + ENDIF + + END diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f52231_41.s b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f52231_41.s new file mode 100644 index 0000000000..c653285b1f --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f52231_41.s @@ -0,0 +1,482 @@ +;/*---------------------------------------------------------------------------------------------------------*/ +;/* Holtek Semiconductor Inc. */ +;/* */ +;/* Copyright (C) Holtek Semiconductor Inc. */ +;/* All rights reserved. */ +;/* */ +;/*----------------------------------------------------------------------------------------------------------- +; File Name : startup_ht32f5xxxx_01.s +; Version : $Rev:: 6953 $ +; Date : $Date:: 2023-05-30 #$ +; Description : Startup code. +;-----------------------------------------------------------------------------------------------------------*/ + +; Supported Device +; ======================================== +; HT32F52220, HT32F52230 +; HT32F52231, HT32F52241 +; HT32F52331, HT32F52341 +; HT32F52342, HT32F52352 +; HT32F52243, HT32F52253 +; HT32F0008 +; HT32F52344, HT32F52354 +; HT32F0006 +; HT32F61352 +; HT50F32003 +; HT32F62030, HT32F62040, HT32F62050 +; HT32F67741 +; HT32F67232 +; HT32F67233 + +;/* <<< Use Configuration Wizard in Context Menu >>> */ + +;// HT32 Device +;// Select HT32 Device for the assembly setting. +;// Notice that the project's Asm Define has the higher priority. +;// <0=> By Project Asm Define +;// <1=> HT32F52220/30 +;// <2=> HT32F52231/41 +;// <3=> HT32F52331/41 +;// <4=> HT32F52342/52 +;// <5=> HT32F52243/53 +;// <6=> HT32F0008 +;// <9=> HT32F52344/54 +;// <10=> HT32F0006 +;// <10=> HT32F61352 +;// <4=> HT50F32003 +;// <2=> HT32F67741 +;// <1=> HT32F67232 +;// <1=> HT32F67233 +;// <1=> HT32F62030 +;// <2=> HT32F62040 +;// <5=> HT32F62050 +USE_HT32_CHIP_SET EQU 2 ; Notice that the project's Asm Define has the higher priority. + +_HT32FWID EQU 0xFFFFFFFF +;_HT32FWID EQU 0x00052220 +;_HT32FWID EQU 0x00052230 +;_HT32FWID EQU 0x00052231 +;_HT32FWID EQU 0x00052241 +;_HT32FWID EQU 0x00052331 +;_HT32FWID EQU 0x00052341 +;_HT32FWID EQU 0x00052342 +;_HT32FWID EQU 0x00052352 +;_HT32FWID EQU 0x00052243 +;_HT32FWID EQU 0x00052253 +;_HT32FWID EQU 0x00000008 +;_HT32FWID EQU 0x00052344 +;_HT32FWID EQU 0x00052354 +;_HT32FWID EQU 0x00000006 +;_HT32FWID EQU 0x00061352 +;_HT32FWID EQU 0x00032003 +;_HT32FWID EQU 0x00062030 +;_HT32FWID EQU 0x00062040 +;_HT32FWID EQU 0x00062050 +;_HT32FWID EQU 0x00067741 +;_HT32FWID EQU 0x00067232 +;_HT32FWID EQU 0x00067233 + +HT32F52220_30 EQU 1 +HT32F52231_41 EQU 2 +HT32F52331_41 EQU 3 +HT32F52342_52 EQU 4 +HT32F52243_53 EQU 5 +HT32F0008 EQU 6 +HT32F52344_54 EQU 9 +HT32F0006 EQU 10 +HT32F61352 EQU 10 +HT50F32003 EQU 4 +HT32F62030 EQU 1 +HT32F62040 EQU 2 +HT32F62050 EQU 5 +HT32F67741 EQU 2 +HT32F67232 EQU 1 +HT32F67233 EQU 1 + + IF USE_HT32_CHIP_SET=0 + ; Use project's Asm Define setting (default) + ELSE + IF :DEF:USE_HT32_CHIP + ; Use project's Asm Define setting (higher priority than the "USE_HT32_CHIP_SET") + ELSE + ; Use "USE_HT32_CHIP_SET" in the "startup_ht32xxxxx_xx.s" file +USE_HT32_CHIP EQU USE_HT32_CHIP_SET + ENDIF + ENDIF + +; Amount of memory (in bytes) allocated for Stack and Heap +; Tailor those values to your application needs +;// Stack Size (in Bytes, must 8 byte aligned) <0-16384:8> +Stack_Size EQU 512 + + AREA STACK, NOINIT, READWRITE, ALIGN = 3 +__HT_check_sp +Stack_Mem SPACE Stack_Size +__initial_sp + +;// Heap Size (in Bytes) <0-16384:8> +Heap_Size EQU 0 + + AREA HEAP, NOINIT, READWRITE, ALIGN = 3 +__HT_check_heap +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + PRESERVE8 + THUMB + +;******************************************************************************* +; Fill-up the Vector Table entries with the exceptions ISR address +;******************************************************************************* + AREA RESET, CODE, READONLY + EXPORT __Vectors +_RESERVED EQU 0xFFFFFFFF +__Vectors + DCD __initial_sp ; ---, 00, 0x000, Top address of Stack + DCD Reset_Handler ; ---, 01, 0x004, Reset Handler + DCD NMI_Handler ; -14, 02, 0x008, NMI Handler + DCD HardFault_Handler ; -13, 03, 0x00C, Hard Fault Handler + DCD _RESERVED ; ---, 04, 0x010, Reserved + DCD _RESERVED ; ---, 05, 0x014, Reserved + DCD _RESERVED ; ---, 06, 0x018, Reserved + DCD _RESERVED ; ---, 07, 0x01C, Reserved + DCD _HT32FWID ; ---, 08, 0x020, Reserved + DCD _RESERVED ; ---, 09, 0x024, Reserved + DCD _RESERVED ; ---, 10, 0x028, Reserved + DCD SVC_Handler ; -05, 11, 0x02C, SVC Handler + DCD _RESERVED ; ---, 12, 0x030, Reserved + DCD _RESERVED ; ---, 13, 0x034, Reserved + DCD PendSV_Handler ; -02, 14, 0x038, PendSV Handler + DCD SysTick_Handler ; -01, 15, 0x03C, SysTick Handler + + ; External Interrupt Handler + DCD LVD_BOD_IRQHandler ; 00, 16, 0x040, + IF (USE_HT32_CHIP=HT32F52220_30) + DCD _RESERVED ; 01, 17, 0x044, + ELSE + DCD RTC_IRQHandler ; 01, 17, 0x044, + ENDIF + DCD FLASH_IRQHandler ; 02, 18, 0x048, + DCD EVWUP_IRQHandler ; 03, 19, 0x04C, + DCD EXTI0_1_IRQHandler ; 04, 20, 0x050, + DCD EXTI2_3_IRQHandler ; 05, 21, 0x054, + DCD EXTI4_15_IRQHandler ; 06, 22, 0x058, + IF (USE_HT32_CHIP=HT32F52342_52) || (USE_HT32_CHIP=HT32F52344_54) + DCD COMP_IRQHandler ; 07, 23, 0x05C, + ELSE + DCD _RESERVED ; 07, 23, 0x05C, + ENDIF + IF (USE_HT32_CHIP=HT32F0008) + DCD _RESERVED ; 08, 24, 0x060, + ELSE + DCD ADC_IRQHandler ; 08, 24, 0x060, + ENDIF + IF (USE_HT32_CHIP=HT32F52243_53) + DCD I2C2_IRQHandler ; 09, 25, 0x064, + ELSE + DCD _RESERVED ; 09, 25, 0x064, + ENDIF + IF (USE_HT32_CHIP=HT32F52220_30) || (USE_HT32_CHIP=HT32F0008) || (USE_HT32_CHIP=HT32F0006) + DCD _RESERVED ; 10, 26, 0x068, + ELSE + DCD MCTM0_IRQHandler ; 10, 26, 0x068, + ENDIF + IF (USE_HT32_CHIP=HT32F52342_52) + DCD GPTM1_IRQHandler ; 11, 27, 0x06C, + ELSE + DCD _RESERVED ; 11, 27, 0x06C, + ENDIF + DCD GPTM0_IRQHandler ; 12, 28, 0x070, + IF (USE_HT32_CHIP=HT32F0008) + DCD _RESERVED ; 13, 29, 0x074, + DCD _RESERVED ; 14, 30, 0x078, + ELSE + DCD SCTM0_IRQHandler ; 13, 29, 0x074, + DCD SCTM1_IRQHandler ; 14, 30, 0x078, + ENDIF + IF (USE_HT32_CHIP=HT32F52231_41) || (USE_HT32_CHIP=HT32F52331_41) || (USE_HT32_CHIP=HT32F52243_53) || (USE_HT32_CHIP=HT32F0006) + DCD SCTM2_IRQHandler ; 15, 31, 0x07C, + DCD SCTM3_IRQHandler ; 16, 32, 0x080, + ENDIF + IF (USE_HT32_CHIP=HT32F0008) + DCD PWM0_IRQHandler ; 15, 31, 0x07C, + DCD PWM1_IRQHandler ; 16, 32, 0x080, + ENDIF + IF (USE_HT32_CHIP=HT32F52220_30) || (USE_HT32_CHIP=HT32F52342_52) || (USE_HT32_CHIP=HT32F52344_54) + DCD _RESERVED ; 15, 31, 0x07C, + DCD _RESERVED ; 16, 32, 0x080, + ENDIF + DCD BFTM0_IRQHandler ; 17, 33, 0x084, + IF (USE_HT32_CHIP=HT32F52220_30) + DCD _RESERVED ; 18, 34, 0x088, + ELSE + DCD BFTM1_IRQHandler ; 18, 34, 0x088, + ENDIF + DCD I2C0_IRQHandler ; 19, 35, 0x08C, + IF (USE_HT32_CHIP=HT32F52220_30) || (USE_HT32_CHIP=HT32F0008) || (USE_HT32_CHIP=HT32F52344_54) || (USE_HT32_CHIP=HT32F0006) + DCD _RESERVED ; 20, 36, 0x090, + ELSE + DCD I2C1_IRQHandler ; 20, 36, 0x090, + ENDIF + DCD SPI0_IRQHandler ; 21, 37, 0x094, + IF (USE_HT32_CHIP=HT32F52220_30) || (USE_HT32_CHIP=HT32F0008) + DCD _RESERVED ; 22, 38, 0x098, + ELSE + IF (USE_HT32_CHIP=HT32F0006) + DCD QSPI_IRQHandler ; 22, 38, 0x098, + ELSE + DCD SPI1_IRQHandler ; 22, 38, 0x098, + ENDIF + ENDIF + IF (USE_HT32_CHIP=HT32F52344_54) + DCD _RESERVED ; 23, 39, 0x09C, + ELSE + DCD USART0_IRQHandler ; 23, 39, 0x09C, + ENDIF + IF (USE_HT32_CHIP=HT32F52342_52) || (USE_HT32_CHIP=HT32F52243_53) + DCD USART1_IRQHandler ; 24, 40, 0x0A0, + ELSE + DCD _RESERVED ; 24, 40, 0x0A0, + ENDIF + DCD UART0_IRQHandler ; 25, 41, 0x0A4, + IF (USE_HT32_CHIP=HT32F52220_30) || (USE_HT32_CHIP=HT32F0008) || (USE_HT32_CHIP=HT32F0006) + DCD _RESERVED ; 26, 42, 0x0A8, + ELSE + DCD UART1_IRQHandler ; 26, 42, 0x0A8, + ENDIF + IF (USE_HT32_CHIP=HT32F52331_41) || (USE_HT32_CHIP=HT32F52342_52) + DCD SCI_IRQHandler ; 27, 43, 0x0AC, + ENDIF + IF (USE_HT32_CHIP=HT32F52243_53) + DCD UART2_IRQHandler ; 27, 43, 0x0AC, + ENDIF + IF (USE_HT32_CHIP=HT32F0006) + DCD MIDI_IRQHandler ; 27, 43, 0x0AC, + ENDIF + IF (USE_HT32_CHIP=HT32F0008) || (USE_HT32_CHIP=HT32F52344_54) + DCD _RESERVED ; 27, 43, 0xAC, + ENDIF + IF (USE_HT32_CHIP=HT32F52342_52) || (USE_HT32_CHIP=HT32F0006) + DCD I2S_IRQHandler ; 28, 44, 0x0B0, + ENDIF + IF (USE_HT32_CHIP=HT32F52331_41) || (USE_HT32_CHIP=HT32F52344_54) + DCD _RESERVED ; 28, 44, 0x0B0, + ENDIF + IF (USE_HT32_CHIP=HT32F52243_53) + DCD UART3_IRQHandler ; 28, 44, 0x0B0, + ENDIF + IF (USE_HT32_CHIP=HT32F0008) + DCD AES_IRQHandler ; 28, 44, 0x0B0, + ENDIF + IF (USE_HT32_CHIP=HT32F52331_41) || (USE_HT32_CHIP=HT32F52342_52) || (USE_HT32_CHIP=HT32F0008) || (USE_HT32_CHIP=HT32F52344_54) || (USE_HT32_CHIP=HT32F0006) + DCD USB_IRQHandler ; 29, 45, 0x0B4, + ENDIF + IF (USE_HT32_CHIP=HT32F52243_53) + DCD _RESERVED ; 29, 45, 0x0B4, + ENDIF + IF (USE_HT32_CHIP=HT32F52342_52) || (USE_HT32_CHIP=HT32F52243_53) || (USE_HT32_CHIP=HT32F0008) || (USE_HT32_CHIP=HT32F52344_54) || (USE_HT32_CHIP=HT32F0006) + DCD PDMA_CH0_1_IRQHandler ; 30, 46, 0x0B8, + DCD PDMA_CH2_5_IRQHandler ; 31, 47, 0x0BC, + ENDIF + +; Reset handler routine +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + LDR R0, =BootProcess + BLX R0 + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +BootProcess PROC + LDR R0, =0x40080300 + LDR R1,[R0, #0x10] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x14] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x18] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x1C] + CMP R1, #0 + BEQ BP2 +BP1 LDR R0, =0x40080180 + LDR R1,[R0, #0xC] + LSLS R1, R1, #4 + LSRS R1, R1, #20 + CMP R1, #0 + BEQ BP3 + CMP R1, #5 + BEQ BP3 + CMP R1, #6 + BEQ BP3 +BP2 DSB + LDR R0, =0x20000000 + LDR R1, =0x05fa0004 + STR R1, [R0] + LDR R1, =0xe000ed00 + LDR R0, =0x05fa0004 + STR R0, [R1, #0xC] + DSB + B . +BP3 LDR R0, =0x20000000 + LDR R1, [R0] + LDR R0, =0x05fa0004 + CMP R0, R1 + BEQ BP4 + BX LR +BP4 LDR R0, =0x40088100 + LDR R1, =0x00000001 + STR R1, [R0] + LDR R0, =0x20000000 + LDR R1, =0x0 + STR R1, [R0] + BX LR + ENDP + +; Dummy Exception Handlers +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP + +HardFault_Handler PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP + +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP + +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP + +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + EXPORT LVD_BOD_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT EVWUP_IRQHandler [WEAK] + EXPORT EXTI0_1_IRQHandler [WEAK] + EXPORT EXTI2_3_IRQHandler [WEAK] + EXPORT EXTI4_15_IRQHandler [WEAK] + EXPORT COMP_IRQHandler [WEAK] + EXPORT ADC_IRQHandler [WEAK] + EXPORT MCTM0_IRQHandler [WEAK] + EXPORT GPTM1_IRQHandler [WEAK] + EXPORT GPTM0_IRQHandler [WEAK] + EXPORT SCTM0_IRQHandler [WEAK] + EXPORT SCTM1_IRQHandler [WEAK] + EXPORT SCTM2_IRQHandler [WEAK] + EXPORT SCTM3_IRQHandler [WEAK] + EXPORT PWM0_IRQHandler [WEAK] + EXPORT PWM1_IRQHandler [WEAK] + EXPORT BFTM0_IRQHandler [WEAK] + EXPORT BFTM1_IRQHandler [WEAK] + EXPORT I2C0_IRQHandler [WEAK] + EXPORT I2C1_IRQHandler [WEAK] + EXPORT I2C2_IRQHandler [WEAK] + EXPORT SPI0_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT QSPI_IRQHandler [WEAK] + EXPORT USART0_IRQHandler [WEAK] + EXPORT USART1_IRQHandler [WEAK] + EXPORT UART0_IRQHandler [WEAK] + EXPORT UART1_IRQHandler [WEAK] + EXPORT UART2_IRQHandler [WEAK] + EXPORT UART3_IRQHandler [WEAK] + EXPORT SCI_IRQHandler [WEAK] + EXPORT MIDI_IRQHandler [WEAK] + EXPORT I2S_IRQHandler [WEAK] + EXPORT AES_IRQHandler [WEAK] + EXPORT USB_IRQHandler [WEAK] + EXPORT PDMA_CH0_1_IRQHandler [WEAK] + EXPORT PDMA_CH2_5_IRQHandler [WEAK] + +LVD_BOD_IRQHandler +RTC_IRQHandler +FLASH_IRQHandler +EVWUP_IRQHandler +EXTI0_1_IRQHandler +EXTI2_3_IRQHandler +EXTI4_15_IRQHandler +COMP_IRQHandler +ADC_IRQHandler +MCTM0_IRQHandler +GPTM1_IRQHandler +GPTM0_IRQHandler +SCTM0_IRQHandler +SCTM1_IRQHandler +SCTM2_IRQHandler +SCTM3_IRQHandler +PWM0_IRQHandler +PWM1_IRQHandler +BFTM0_IRQHandler +BFTM1_IRQHandler +I2C0_IRQHandler +I2C1_IRQHandler +I2C2_IRQHandler +SPI0_IRQHandler +SPI1_IRQHandler +QSPI_IRQHandler +USART0_IRQHandler +USART1_IRQHandler +UART0_IRQHandler +UART1_IRQHandler +UART2_IRQHandler +UART3_IRQHandler +SCI_IRQHandler +MIDI_IRQHandler +I2S_IRQHandler +AES_IRQHandler +USB_IRQHandler +PDMA_CH0_1_IRQHandler +PDMA_CH2_5_IRQHandler + B . + ENDP + + ALIGN + +;******************************************************************************* +; User Stack and Heap initialization +;******************************************************************************* + IF :DEF:__MICROLIB + + EXPORT __HT_check_heap + EXPORT __HT_check_sp + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, = (Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + + ENDIF + + END diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f52234_44.s b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f52234_44.s new file mode 100644 index 0000000000..9f80e3bd0e --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f52234_44.s @@ -0,0 +1,239 @@ +;/*---------------------------------------------------------------------------------------------------------*/ +;/* Holtek Semiconductor Inc. */ +;/* */ +;/* Copyright (C) Holtek Semiconductor Inc. */ +;/* All rights reserved. */ +;/* */ +;/*----------------------------------------------------------------------------------------------------------- +; File Name : startup_ht32f5xxxx_17.s +; Version : $Rev:: 7027 $ +; Date : $Date:: 2023-07-18 #$ +; Description : Startup code. +;-----------------------------------------------------------------------------------------------------------*/ + +; Supported Device +; ======================================== +; HT32F52234, HT32F52244 + +;/* <<< Use Configuration Wizard in Context Menu >>> */ + +;// HT32 Device +;// Select HT32 Device for the assembly setting. +;// Notice that the project's Asm Define has the higher priority. +;// <0=> By Project Asm Define +;// <33=> HT32F52234/44 +USE_HT32_CHIP_SET EQU 33 ; Notice that the project's Asm Define has the higher priority. + +_HT32FWID EQU 0xFFFFFFFF +;_HT32FWID EQU 0x00052234 +;_HT32FWID EQU 0x00052244 + +HT32F52234_44 EQU 33 + + IF USE_HT32_CHIP_SET=0 + ; Use project's Asm Define setting (default) + ELSE + IF :DEF:USE_HT32_CHIP + ; Use project's Asm Define setting (higher priority than the "USE_HT32_CHIP_SET") + ELSE + ; Use "USE_HT32_CHIP_SET" in the "startup_ht32xxxxx_xx.s" file +USE_HT32_CHIP EQU USE_HT32_CHIP_SET + ENDIF + ENDIF + +; Amount of memory (in bytes) allocated for Stack and Heap +; Tailor those values to your application needs +;// Stack Size (in Bytes, must 8 byte aligned) <0-8192:8> +Stack_Size EQU 512 + + AREA STACK, NOINIT, READWRITE, ALIGN = 3 +__HT_check_sp +Stack_Mem SPACE Stack_Size +__initial_sp + +;// Heap Size (in Bytes) <0-8192:8> +Heap_Size EQU 0 + + AREA HEAP, NOINIT, READWRITE, ALIGN = 3 +__HT_check_heap +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + PRESERVE8 + THUMB + +;******************************************************************************* +; Fill-up the Vector Table entries with the exceptions ISR address +;******************************************************************************* + AREA RESET, CODE, READONLY + EXPORT __Vectors +_RESERVED EQU 0xFFFFFFFF +__Vectors + DCD __initial_sp ; ---, 00, 0x000, Top address of Stack + DCD Reset_Handler ; ---, 01, 0x004, Reset Handler + DCD NMI_Handler ; -14, 02, 0x008, NMI Handler + DCD HardFault_Handler ; -13, 03, 0x00C, Hard Fault Handler + DCD _RESERVED ; ---, 04, 0x010, Reserved + DCD _RESERVED ; ---, 05, 0x014, Reserved + DCD _RESERVED ; ---, 06, 0x018, Reserved + DCD _RESERVED ; ---, 07, 0x01C, Reserved + DCD _HT32FWID ; ---, 08, 0x020, Reserved + DCD _RESERVED ; ---, 09, 0x024, Reserved + DCD _RESERVED ; ---, 10, 0x028, Reserved + DCD SVC_Handler ; -05, 11, 0x02C, SVC Handler + DCD _RESERVED ; ---, 12, 0x030, Reserved + DCD _RESERVED ; ---, 13, 0x034, Reserved + DCD PendSV_Handler ; -02, 14, 0x038, PendSV Handler + DCD SysTick_Handler ; -01, 15, 0x03C, SysTick Handler + + ; External Interrupt Handler + DCD LVD_BOD_IRQHandler ; 00, 16, 0x040, + DCD RTC_IRQHandler ; 01, 17, 0x044, + DCD FLASH_IRQHandler ; 02, 18, 0x048, + DCD EVWUP_IRQHandler ; 03, 19, 0x04C, + DCD EXTI0_1_IRQHandler ; 04, 20, 0x050, + DCD EXTI2_3_IRQHandler ; 05, 21, 0x054, + DCD EXTI4_15_IRQHandler ; 06, 22, 0x058, + DCD DAC0_1_IRQHandler ; 07, 23, 0x05C, + DCD ADC_IRQHandler ; 08, 24, 0x060, + DCD I2C2_IRQHandler ; 09, 25, 0x064, + DCD _RESERVED ; 10, 26, 0x068, + DCD _RESERVED ; 11, 27, 0x06C, + DCD _RESERVED ; 12, 28, 0x070, + DCD SCTM0_IRQHandler ; 13, 29, 0x074, + DCD SCTM1_IRQHandler ; 14, 30, 0x078, + DCD PWM0_IRQHandler ; 15, 31, 0x07C, + DCD _RESERVED ; 16, 32, 0x080, + DCD BFTM0_IRQHandler ; 17, 33, 0x084, + DCD BFTM1_IRQHandler ; 18, 34, 0x088, + DCD I2C0_IRQHandler ; 19, 35, 0x08C, + DCD I2C1_IRQHandler ; 20, 36, 0x090, + DCD SPI0_IRQHandler ; 21, 37, 0x094, + DCD _RESERVED ; 22, 38, 0x098, + DCD USART0_IRQHandler ; 23, 39, 0x09C, + DCD _RESERVED ; 24, 40, 0x0A0, + DCD UART0_IRQHandler ; 25, 41, 0x0A4, + DCD _RESERVED ; 26, 42, 0x0A8, + DCD _RESERVED ; 27, 43, 0x0AC, + DCD _RESERVED ; 28, 44, 0x0B0, + DCD _RESERVED ; 29, 45, 0x0B4, + DCD PDMA_CH0_1_IRQHandler ; 30, 46, 0x0B8, + DCD PDMA_CH2_5_IRQHandler ; 31, 47, 0x0BC, + +; Reset handler routine +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception Handlers +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP + +HardFault_Handler PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP + +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP + +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP + +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + EXPORT LVD_BOD_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT EVWUP_IRQHandler [WEAK] + EXPORT EXTI0_1_IRQHandler [WEAK] + EXPORT EXTI2_3_IRQHandler [WEAK] + EXPORT EXTI4_15_IRQHandler [WEAK] + EXPORT DAC0_1_IRQHandler [WEAK] + EXPORT ADC_IRQHandler [WEAK] + EXPORT I2C2_IRQHandler [WEAK] + EXPORT SCTM0_IRQHandler [WEAK] + EXPORT SCTM1_IRQHandler [WEAK] + EXPORT PWM0_IRQHandler [WEAK] + EXPORT BFTM0_IRQHandler [WEAK] + EXPORT BFTM1_IRQHandler [WEAK] + EXPORT I2C0_IRQHandler [WEAK] + EXPORT I2C1_IRQHandler [WEAK] + EXPORT SPI0_IRQHandler [WEAK] + EXPORT USART0_IRQHandler [WEAK] + EXPORT UART0_IRQHandler [WEAK] + EXPORT PDMA_CH0_1_IRQHandler [WEAK] + EXPORT PDMA_CH2_5_IRQHandler [WEAK] + +LVD_BOD_IRQHandler +RTC_IRQHandler +FLASH_IRQHandler +EVWUP_IRQHandler +EXTI0_1_IRQHandler +EXTI2_3_IRQHandler +EXTI4_15_IRQHandler +DAC0_1_IRQHandler +ADC_IRQHandler +I2C2_IRQHandler +SCTM0_IRQHandler +SCTM1_IRQHandler +PWM0_IRQHandler +BFTM0_IRQHandler +BFTM1_IRQHandler +I2C0_IRQHandler +I2C1_IRQHandler +SPI0_IRQHandler +USART0_IRQHandler +UART0_IRQHandler +PDMA_CH0_1_IRQHandler +PDMA_CH2_5_IRQHandler + B . + ENDP + + ALIGN + +;******************************************************************************* +; User Stack and Heap initialization +;******************************************************************************* + IF :DEF:__MICROLIB + + EXPORT __HT_check_heap + EXPORT __HT_check_sp + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, = (Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + + ENDIF + + END diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f52243_53.s b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f52243_53.s new file mode 100644 index 0000000000..e9b3a2c194 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f52243_53.s @@ -0,0 +1,482 @@ +;/*---------------------------------------------------------------------------------------------------------*/ +;/* Holtek Semiconductor Inc. */ +;/* */ +;/* Copyright (C) Holtek Semiconductor Inc. */ +;/* All rights reserved. */ +;/* */ +;/*----------------------------------------------------------------------------------------------------------- +; File Name : startup_ht32f5xxxx_01.s +; Version : $Rev:: 6953 $ +; Date : $Date:: 2023-05-30 #$ +; Description : Startup code. +;-----------------------------------------------------------------------------------------------------------*/ + +; Supported Device +; ======================================== +; HT32F52220, HT32F52230 +; HT32F52231, HT32F52241 +; HT32F52331, HT32F52341 +; HT32F52342, HT32F52352 +; HT32F52243, HT32F52253 +; HT32F0008 +; HT32F52344, HT32F52354 +; HT32F0006 +; HT32F61352 +; HT50F32003 +; HT32F62030, HT32F62040, HT32F62050 +; HT32F67741 +; HT32F67232 +; HT32F67233 + +;/* <<< Use Configuration Wizard in Context Menu >>> */ + +;// HT32 Device +;// Select HT32 Device for the assembly setting. +;// Notice that the project's Asm Define has the higher priority. +;// <0=> By Project Asm Define +;// <1=> HT32F52220/30 +;// <2=> HT32F52231/41 +;// <3=> HT32F52331/41 +;// <4=> HT32F52342/52 +;// <5=> HT32F52243/53 +;// <6=> HT32F0008 +;// <9=> HT32F52344/54 +;// <10=> HT32F0006 +;// <10=> HT32F61352 +;// <4=> HT50F32003 +;// <2=> HT32F67741 +;// <1=> HT32F67232 +;// <1=> HT32F67233 +;// <1=> HT32F62030 +;// <2=> HT32F62040 +;// <5=> HT32F62050 +USE_HT32_CHIP_SET EQU 5 ; Notice that the project's Asm Define has the higher priority. + +_HT32FWID EQU 0xFFFFFFFF +;_HT32FWID EQU 0x00052220 +;_HT32FWID EQU 0x00052230 +;_HT32FWID EQU 0x00052231 +;_HT32FWID EQU 0x00052241 +;_HT32FWID EQU 0x00052331 +;_HT32FWID EQU 0x00052341 +;_HT32FWID EQU 0x00052342 +;_HT32FWID EQU 0x00052352 +;_HT32FWID EQU 0x00052243 +;_HT32FWID EQU 0x00052253 +;_HT32FWID EQU 0x00000008 +;_HT32FWID EQU 0x00052344 +;_HT32FWID EQU 0x00052354 +;_HT32FWID EQU 0x00000006 +;_HT32FWID EQU 0x00061352 +;_HT32FWID EQU 0x00032003 +;_HT32FWID EQU 0x00062030 +;_HT32FWID EQU 0x00062040 +;_HT32FWID EQU 0x00062050 +;_HT32FWID EQU 0x00067741 +;_HT32FWID EQU 0x00067232 +;_HT32FWID EQU 0x00067233 + +HT32F52220_30 EQU 1 +HT32F52231_41 EQU 2 +HT32F52331_41 EQU 3 +HT32F52342_52 EQU 4 +HT32F52243_53 EQU 5 +HT32F0008 EQU 6 +HT32F52344_54 EQU 9 +HT32F0006 EQU 10 +HT32F61352 EQU 10 +HT50F32003 EQU 4 +HT32F62030 EQU 1 +HT32F62040 EQU 2 +HT32F62050 EQU 5 +HT32F67741 EQU 2 +HT32F67232 EQU 1 +HT32F67233 EQU 1 + + IF USE_HT32_CHIP_SET=0 + ; Use project's Asm Define setting (default) + ELSE + IF :DEF:USE_HT32_CHIP + ; Use project's Asm Define setting (higher priority than the "USE_HT32_CHIP_SET") + ELSE + ; Use "USE_HT32_CHIP_SET" in the "startup_ht32xxxxx_xx.s" file +USE_HT32_CHIP EQU USE_HT32_CHIP_SET + ENDIF + ENDIF + +; Amount of memory (in bytes) allocated for Stack and Heap +; Tailor those values to your application needs +;// Stack Size (in Bytes, must 8 byte aligned) <0-16384:8> +Stack_Size EQU 512 + + AREA STACK, NOINIT, READWRITE, ALIGN = 3 +__HT_check_sp +Stack_Mem SPACE Stack_Size +__initial_sp + +;// Heap Size (in Bytes) <0-16384:8> +Heap_Size EQU 0 + + AREA HEAP, NOINIT, READWRITE, ALIGN = 3 +__HT_check_heap +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + PRESERVE8 + THUMB + +;******************************************************************************* +; Fill-up the Vector Table entries with the exceptions ISR address +;******************************************************************************* + AREA RESET, CODE, READONLY + EXPORT __Vectors +_RESERVED EQU 0xFFFFFFFF +__Vectors + DCD __initial_sp ; ---, 00, 0x000, Top address of Stack + DCD Reset_Handler ; ---, 01, 0x004, Reset Handler + DCD NMI_Handler ; -14, 02, 0x008, NMI Handler + DCD HardFault_Handler ; -13, 03, 0x00C, Hard Fault Handler + DCD _RESERVED ; ---, 04, 0x010, Reserved + DCD _RESERVED ; ---, 05, 0x014, Reserved + DCD _RESERVED ; ---, 06, 0x018, Reserved + DCD _RESERVED ; ---, 07, 0x01C, Reserved + DCD _HT32FWID ; ---, 08, 0x020, Reserved + DCD _RESERVED ; ---, 09, 0x024, Reserved + DCD _RESERVED ; ---, 10, 0x028, Reserved + DCD SVC_Handler ; -05, 11, 0x02C, SVC Handler + DCD _RESERVED ; ---, 12, 0x030, Reserved + DCD _RESERVED ; ---, 13, 0x034, Reserved + DCD PendSV_Handler ; -02, 14, 0x038, PendSV Handler + DCD SysTick_Handler ; -01, 15, 0x03C, SysTick Handler + + ; External Interrupt Handler + DCD LVD_BOD_IRQHandler ; 00, 16, 0x040, + IF (USE_HT32_CHIP=HT32F52220_30) + DCD _RESERVED ; 01, 17, 0x044, + ELSE + DCD RTC_IRQHandler ; 01, 17, 0x044, + ENDIF + DCD FLASH_IRQHandler ; 02, 18, 0x048, + DCD EVWUP_IRQHandler ; 03, 19, 0x04C, + DCD EXTI0_1_IRQHandler ; 04, 20, 0x050, + DCD EXTI2_3_IRQHandler ; 05, 21, 0x054, + DCD EXTI4_15_IRQHandler ; 06, 22, 0x058, + IF (USE_HT32_CHIP=HT32F52342_52) || (USE_HT32_CHIP=HT32F52344_54) + DCD COMP_IRQHandler ; 07, 23, 0x05C, + ELSE + DCD _RESERVED ; 07, 23, 0x05C, + ENDIF + IF (USE_HT32_CHIP=HT32F0008) + DCD _RESERVED ; 08, 24, 0x060, + ELSE + DCD ADC_IRQHandler ; 08, 24, 0x060, + ENDIF + IF (USE_HT32_CHIP=HT32F52243_53) + DCD I2C2_IRQHandler ; 09, 25, 0x064, + ELSE + DCD _RESERVED ; 09, 25, 0x064, + ENDIF + IF (USE_HT32_CHIP=HT32F52220_30) || (USE_HT32_CHIP=HT32F0008) || (USE_HT32_CHIP=HT32F0006) + DCD _RESERVED ; 10, 26, 0x068, + ELSE + DCD MCTM0_IRQHandler ; 10, 26, 0x068, + ENDIF + IF (USE_HT32_CHIP=HT32F52342_52) + DCD GPTM1_IRQHandler ; 11, 27, 0x06C, + ELSE + DCD _RESERVED ; 11, 27, 0x06C, + ENDIF + DCD GPTM0_IRQHandler ; 12, 28, 0x070, + IF (USE_HT32_CHIP=HT32F0008) + DCD _RESERVED ; 13, 29, 0x074, + DCD _RESERVED ; 14, 30, 0x078, + ELSE + DCD SCTM0_IRQHandler ; 13, 29, 0x074, + DCD SCTM1_IRQHandler ; 14, 30, 0x078, + ENDIF + IF (USE_HT32_CHIP=HT32F52231_41) || (USE_HT32_CHIP=HT32F52331_41) || (USE_HT32_CHIP=HT32F52243_53) || (USE_HT32_CHIP=HT32F0006) + DCD SCTM2_IRQHandler ; 15, 31, 0x07C, + DCD SCTM3_IRQHandler ; 16, 32, 0x080, + ENDIF + IF (USE_HT32_CHIP=HT32F0008) + DCD PWM0_IRQHandler ; 15, 31, 0x07C, + DCD PWM1_IRQHandler ; 16, 32, 0x080, + ENDIF + IF (USE_HT32_CHIP=HT32F52220_30) || (USE_HT32_CHIP=HT32F52342_52) || (USE_HT32_CHIP=HT32F52344_54) + DCD _RESERVED ; 15, 31, 0x07C, + DCD _RESERVED ; 16, 32, 0x080, + ENDIF + DCD BFTM0_IRQHandler ; 17, 33, 0x084, + IF (USE_HT32_CHIP=HT32F52220_30) + DCD _RESERVED ; 18, 34, 0x088, + ELSE + DCD BFTM1_IRQHandler ; 18, 34, 0x088, + ENDIF + DCD I2C0_IRQHandler ; 19, 35, 0x08C, + IF (USE_HT32_CHIP=HT32F52220_30) || (USE_HT32_CHIP=HT32F0008) || (USE_HT32_CHIP=HT32F52344_54) || (USE_HT32_CHIP=HT32F0006) + DCD _RESERVED ; 20, 36, 0x090, + ELSE + DCD I2C1_IRQHandler ; 20, 36, 0x090, + ENDIF + DCD SPI0_IRQHandler ; 21, 37, 0x094, + IF (USE_HT32_CHIP=HT32F52220_30) || (USE_HT32_CHIP=HT32F0008) + DCD _RESERVED ; 22, 38, 0x098, + ELSE + IF (USE_HT32_CHIP=HT32F0006) + DCD QSPI_IRQHandler ; 22, 38, 0x098, + ELSE + DCD SPI1_IRQHandler ; 22, 38, 0x098, + ENDIF + ENDIF + IF (USE_HT32_CHIP=HT32F52344_54) + DCD _RESERVED ; 23, 39, 0x09C, + ELSE + DCD USART0_IRQHandler ; 23, 39, 0x09C, + ENDIF + IF (USE_HT32_CHIP=HT32F52342_52) || (USE_HT32_CHIP=HT32F52243_53) + DCD USART1_IRQHandler ; 24, 40, 0x0A0, + ELSE + DCD _RESERVED ; 24, 40, 0x0A0, + ENDIF + DCD UART0_IRQHandler ; 25, 41, 0x0A4, + IF (USE_HT32_CHIP=HT32F52220_30) || (USE_HT32_CHIP=HT32F0008) || (USE_HT32_CHIP=HT32F0006) + DCD _RESERVED ; 26, 42, 0x0A8, + ELSE + DCD UART1_IRQHandler ; 26, 42, 0x0A8, + ENDIF + IF (USE_HT32_CHIP=HT32F52331_41) || (USE_HT32_CHIP=HT32F52342_52) + DCD SCI_IRQHandler ; 27, 43, 0x0AC, + ENDIF + IF (USE_HT32_CHIP=HT32F52243_53) + DCD UART2_IRQHandler ; 27, 43, 0x0AC, + ENDIF + IF (USE_HT32_CHIP=HT32F0006) + DCD MIDI_IRQHandler ; 27, 43, 0x0AC, + ENDIF + IF (USE_HT32_CHIP=HT32F0008) || (USE_HT32_CHIP=HT32F52344_54) + DCD _RESERVED ; 27, 43, 0xAC, + ENDIF + IF (USE_HT32_CHIP=HT32F52342_52) || (USE_HT32_CHIP=HT32F0006) + DCD I2S_IRQHandler ; 28, 44, 0x0B0, + ENDIF + IF (USE_HT32_CHIP=HT32F52331_41) || (USE_HT32_CHIP=HT32F52344_54) + DCD _RESERVED ; 28, 44, 0x0B0, + ENDIF + IF (USE_HT32_CHIP=HT32F52243_53) + DCD UART3_IRQHandler ; 28, 44, 0x0B0, + ENDIF + IF (USE_HT32_CHIP=HT32F0008) + DCD AES_IRQHandler ; 28, 44, 0x0B0, + ENDIF + IF (USE_HT32_CHIP=HT32F52331_41) || (USE_HT32_CHIP=HT32F52342_52) || (USE_HT32_CHIP=HT32F0008) || (USE_HT32_CHIP=HT32F52344_54) || (USE_HT32_CHIP=HT32F0006) + DCD USB_IRQHandler ; 29, 45, 0x0B4, + ENDIF + IF (USE_HT32_CHIP=HT32F52243_53) + DCD _RESERVED ; 29, 45, 0x0B4, + ENDIF + IF (USE_HT32_CHIP=HT32F52342_52) || (USE_HT32_CHIP=HT32F52243_53) || (USE_HT32_CHIP=HT32F0008) || (USE_HT32_CHIP=HT32F52344_54) || (USE_HT32_CHIP=HT32F0006) + DCD PDMA_CH0_1_IRQHandler ; 30, 46, 0x0B8, + DCD PDMA_CH2_5_IRQHandler ; 31, 47, 0x0BC, + ENDIF + +; Reset handler routine +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + LDR R0, =BootProcess + BLX R0 + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +BootProcess PROC + LDR R0, =0x40080300 + LDR R1,[R0, #0x10] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x14] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x18] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x1C] + CMP R1, #0 + BEQ BP2 +BP1 LDR R0, =0x40080180 + LDR R1,[R0, #0xC] + LSLS R1, R1, #4 + LSRS R1, R1, #20 + CMP R1, #0 + BEQ BP3 + CMP R1, #5 + BEQ BP3 + CMP R1, #6 + BEQ BP3 +BP2 DSB + LDR R0, =0x20000000 + LDR R1, =0x05fa0004 + STR R1, [R0] + LDR R1, =0xe000ed00 + LDR R0, =0x05fa0004 + STR R0, [R1, #0xC] + DSB + B . +BP3 LDR R0, =0x20000000 + LDR R1, [R0] + LDR R0, =0x05fa0004 + CMP R0, R1 + BEQ BP4 + BX LR +BP4 LDR R0, =0x40088100 + LDR R1, =0x00000001 + STR R1, [R0] + LDR R0, =0x20000000 + LDR R1, =0x0 + STR R1, [R0] + BX LR + ENDP + +; Dummy Exception Handlers +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP + +HardFault_Handler PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP + +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP + +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP + +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + EXPORT LVD_BOD_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT EVWUP_IRQHandler [WEAK] + EXPORT EXTI0_1_IRQHandler [WEAK] + EXPORT EXTI2_3_IRQHandler [WEAK] + EXPORT EXTI4_15_IRQHandler [WEAK] + EXPORT COMP_IRQHandler [WEAK] + EXPORT ADC_IRQHandler [WEAK] + EXPORT MCTM0_IRQHandler [WEAK] + EXPORT GPTM1_IRQHandler [WEAK] + EXPORT GPTM0_IRQHandler [WEAK] + EXPORT SCTM0_IRQHandler [WEAK] + EXPORT SCTM1_IRQHandler [WEAK] + EXPORT SCTM2_IRQHandler [WEAK] + EXPORT SCTM3_IRQHandler [WEAK] + EXPORT PWM0_IRQHandler [WEAK] + EXPORT PWM1_IRQHandler [WEAK] + EXPORT BFTM0_IRQHandler [WEAK] + EXPORT BFTM1_IRQHandler [WEAK] + EXPORT I2C0_IRQHandler [WEAK] + EXPORT I2C1_IRQHandler [WEAK] + EXPORT I2C2_IRQHandler [WEAK] + EXPORT SPI0_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT QSPI_IRQHandler [WEAK] + EXPORT USART0_IRQHandler [WEAK] + EXPORT USART1_IRQHandler [WEAK] + EXPORT UART0_IRQHandler [WEAK] + EXPORT UART1_IRQHandler [WEAK] + EXPORT UART2_IRQHandler [WEAK] + EXPORT UART3_IRQHandler [WEAK] + EXPORT SCI_IRQHandler [WEAK] + EXPORT MIDI_IRQHandler [WEAK] + EXPORT I2S_IRQHandler [WEAK] + EXPORT AES_IRQHandler [WEAK] + EXPORT USB_IRQHandler [WEAK] + EXPORT PDMA_CH0_1_IRQHandler [WEAK] + EXPORT PDMA_CH2_5_IRQHandler [WEAK] + +LVD_BOD_IRQHandler +RTC_IRQHandler +FLASH_IRQHandler +EVWUP_IRQHandler +EXTI0_1_IRQHandler +EXTI2_3_IRQHandler +EXTI4_15_IRQHandler +COMP_IRQHandler +ADC_IRQHandler +MCTM0_IRQHandler +GPTM1_IRQHandler +GPTM0_IRQHandler +SCTM0_IRQHandler +SCTM1_IRQHandler +SCTM2_IRQHandler +SCTM3_IRQHandler +PWM0_IRQHandler +PWM1_IRQHandler +BFTM0_IRQHandler +BFTM1_IRQHandler +I2C0_IRQHandler +I2C1_IRQHandler +I2C2_IRQHandler +SPI0_IRQHandler +SPI1_IRQHandler +QSPI_IRQHandler +USART0_IRQHandler +USART1_IRQHandler +UART0_IRQHandler +UART1_IRQHandler +UART2_IRQHandler +UART3_IRQHandler +SCI_IRQHandler +MIDI_IRQHandler +I2S_IRQHandler +AES_IRQHandler +USB_IRQHandler +PDMA_CH0_1_IRQHandler +PDMA_CH2_5_IRQHandler + B . + ENDP + + ALIGN + +;******************************************************************************* +; User Stack and Heap initialization +;******************************************************************************* + IF :DEF:__MICROLIB + + EXPORT __HT_check_heap + EXPORT __HT_check_sp + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, = (Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + + ENDIF + + END diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f52331_41.s b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f52331_41.s new file mode 100644 index 0000000000..8cd61fd13a --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f52331_41.s @@ -0,0 +1,482 @@ +;/*---------------------------------------------------------------------------------------------------------*/ +;/* Holtek Semiconductor Inc. */ +;/* */ +;/* Copyright (C) Holtek Semiconductor Inc. */ +;/* All rights reserved. */ +;/* */ +;/*----------------------------------------------------------------------------------------------------------- +; File Name : startup_ht32f5xxxx_01.s +; Version : $Rev:: 6953 $ +; Date : $Date:: 2023-05-30 #$ +; Description : Startup code. +;-----------------------------------------------------------------------------------------------------------*/ + +; Supported Device +; ======================================== +; HT32F52220, HT32F52230 +; HT32F52231, HT32F52241 +; HT32F52331, HT32F52341 +; HT32F52342, HT32F52352 +; HT32F52243, HT32F52253 +; HT32F0008 +; HT32F52344, HT32F52354 +; HT32F0006 +; HT32F61352 +; HT50F32003 +; HT32F62030, HT32F62040, HT32F62050 +; HT32F67741 +; HT32F67232 +; HT32F67233 + +;/* <<< Use Configuration Wizard in Context Menu >>> */ + +;// HT32 Device +;// Select HT32 Device for the assembly setting. +;// Notice that the project's Asm Define has the higher priority. +;// <0=> By Project Asm Define +;// <1=> HT32F52220/30 +;// <2=> HT32F52231/41 +;// <3=> HT32F52331/41 +;// <4=> HT32F52342/52 +;// <5=> HT32F52243/53 +;// <6=> HT32F0008 +;// <9=> HT32F52344/54 +;// <10=> HT32F0006 +;// <10=> HT32F61352 +;// <4=> HT50F32003 +;// <2=> HT32F67741 +;// <1=> HT32F67232 +;// <1=> HT32F67233 +;// <1=> HT32F62030 +;// <2=> HT32F62040 +;// <5=> HT32F62050 +USE_HT32_CHIP_SET EQU 3 ; Notice that the project's Asm Define has the higher priority. + +_HT32FWID EQU 0xFFFFFFFF +;_HT32FWID EQU 0x00052220 +;_HT32FWID EQU 0x00052230 +;_HT32FWID EQU 0x00052231 +;_HT32FWID EQU 0x00052241 +;_HT32FWID EQU 0x00052331 +;_HT32FWID EQU 0x00052341 +;_HT32FWID EQU 0x00052342 +;_HT32FWID EQU 0x00052352 +;_HT32FWID EQU 0x00052243 +;_HT32FWID EQU 0x00052253 +;_HT32FWID EQU 0x00000008 +;_HT32FWID EQU 0x00052344 +;_HT32FWID EQU 0x00052354 +;_HT32FWID EQU 0x00000006 +;_HT32FWID EQU 0x00061352 +;_HT32FWID EQU 0x00032003 +;_HT32FWID EQU 0x00062030 +;_HT32FWID EQU 0x00062040 +;_HT32FWID EQU 0x00062050 +;_HT32FWID EQU 0x00067741 +;_HT32FWID EQU 0x00067232 +;_HT32FWID EQU 0x00067233 + +HT32F52220_30 EQU 1 +HT32F52231_41 EQU 2 +HT32F52331_41 EQU 3 +HT32F52342_52 EQU 4 +HT32F52243_53 EQU 5 +HT32F0008 EQU 6 +HT32F52344_54 EQU 9 +HT32F0006 EQU 10 +HT32F61352 EQU 10 +HT50F32003 EQU 4 +HT32F62030 EQU 1 +HT32F62040 EQU 2 +HT32F62050 EQU 5 +HT32F67741 EQU 2 +HT32F67232 EQU 1 +HT32F67233 EQU 1 + + IF USE_HT32_CHIP_SET=0 + ; Use project's Asm Define setting (default) + ELSE + IF :DEF:USE_HT32_CHIP + ; Use project's Asm Define setting (higher priority than the "USE_HT32_CHIP_SET") + ELSE + ; Use "USE_HT32_CHIP_SET" in the "startup_ht32xxxxx_xx.s" file +USE_HT32_CHIP EQU USE_HT32_CHIP_SET + ENDIF + ENDIF + +; Amount of memory (in bytes) allocated for Stack and Heap +; Tailor those values to your application needs +;// Stack Size (in Bytes, must 8 byte aligned) <0-16384:8> +Stack_Size EQU 512 + + AREA STACK, NOINIT, READWRITE, ALIGN = 3 +__HT_check_sp +Stack_Mem SPACE Stack_Size +__initial_sp + +;// Heap Size (in Bytes) <0-16384:8> +Heap_Size EQU 0 + + AREA HEAP, NOINIT, READWRITE, ALIGN = 3 +__HT_check_heap +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + PRESERVE8 + THUMB + +;******************************************************************************* +; Fill-up the Vector Table entries with the exceptions ISR address +;******************************************************************************* + AREA RESET, CODE, READONLY + EXPORT __Vectors +_RESERVED EQU 0xFFFFFFFF +__Vectors + DCD __initial_sp ; ---, 00, 0x000, Top address of Stack + DCD Reset_Handler ; ---, 01, 0x004, Reset Handler + DCD NMI_Handler ; -14, 02, 0x008, NMI Handler + DCD HardFault_Handler ; -13, 03, 0x00C, Hard Fault Handler + DCD _RESERVED ; ---, 04, 0x010, Reserved + DCD _RESERVED ; ---, 05, 0x014, Reserved + DCD _RESERVED ; ---, 06, 0x018, Reserved + DCD _RESERVED ; ---, 07, 0x01C, Reserved + DCD _HT32FWID ; ---, 08, 0x020, Reserved + DCD _RESERVED ; ---, 09, 0x024, Reserved + DCD _RESERVED ; ---, 10, 0x028, Reserved + DCD SVC_Handler ; -05, 11, 0x02C, SVC Handler + DCD _RESERVED ; ---, 12, 0x030, Reserved + DCD _RESERVED ; ---, 13, 0x034, Reserved + DCD PendSV_Handler ; -02, 14, 0x038, PendSV Handler + DCD SysTick_Handler ; -01, 15, 0x03C, SysTick Handler + + ; External Interrupt Handler + DCD LVD_BOD_IRQHandler ; 00, 16, 0x040, + IF (USE_HT32_CHIP=HT32F52220_30) + DCD _RESERVED ; 01, 17, 0x044, + ELSE + DCD RTC_IRQHandler ; 01, 17, 0x044, + ENDIF + DCD FLASH_IRQHandler ; 02, 18, 0x048, + DCD EVWUP_IRQHandler ; 03, 19, 0x04C, + DCD EXTI0_1_IRQHandler ; 04, 20, 0x050, + DCD EXTI2_3_IRQHandler ; 05, 21, 0x054, + DCD EXTI4_15_IRQHandler ; 06, 22, 0x058, + IF (USE_HT32_CHIP=HT32F52342_52) || (USE_HT32_CHIP=HT32F52344_54) + DCD COMP_IRQHandler ; 07, 23, 0x05C, + ELSE + DCD _RESERVED ; 07, 23, 0x05C, + ENDIF + IF (USE_HT32_CHIP=HT32F0008) + DCD _RESERVED ; 08, 24, 0x060, + ELSE + DCD ADC_IRQHandler ; 08, 24, 0x060, + ENDIF + IF (USE_HT32_CHIP=HT32F52243_53) + DCD I2C2_IRQHandler ; 09, 25, 0x064, + ELSE + DCD _RESERVED ; 09, 25, 0x064, + ENDIF + IF (USE_HT32_CHIP=HT32F52220_30) || (USE_HT32_CHIP=HT32F0008) || (USE_HT32_CHIP=HT32F0006) + DCD _RESERVED ; 10, 26, 0x068, + ELSE + DCD MCTM0_IRQHandler ; 10, 26, 0x068, + ENDIF + IF (USE_HT32_CHIP=HT32F52342_52) + DCD GPTM1_IRQHandler ; 11, 27, 0x06C, + ELSE + DCD _RESERVED ; 11, 27, 0x06C, + ENDIF + DCD GPTM0_IRQHandler ; 12, 28, 0x070, + IF (USE_HT32_CHIP=HT32F0008) + DCD _RESERVED ; 13, 29, 0x074, + DCD _RESERVED ; 14, 30, 0x078, + ELSE + DCD SCTM0_IRQHandler ; 13, 29, 0x074, + DCD SCTM1_IRQHandler ; 14, 30, 0x078, + ENDIF + IF (USE_HT32_CHIP=HT32F52231_41) || (USE_HT32_CHIP=HT32F52331_41) || (USE_HT32_CHIP=HT32F52243_53) || (USE_HT32_CHIP=HT32F0006) + DCD SCTM2_IRQHandler ; 15, 31, 0x07C, + DCD SCTM3_IRQHandler ; 16, 32, 0x080, + ENDIF + IF (USE_HT32_CHIP=HT32F0008) + DCD PWM0_IRQHandler ; 15, 31, 0x07C, + DCD PWM1_IRQHandler ; 16, 32, 0x080, + ENDIF + IF (USE_HT32_CHIP=HT32F52220_30) || (USE_HT32_CHIP=HT32F52342_52) || (USE_HT32_CHIP=HT32F52344_54) + DCD _RESERVED ; 15, 31, 0x07C, + DCD _RESERVED ; 16, 32, 0x080, + ENDIF + DCD BFTM0_IRQHandler ; 17, 33, 0x084, + IF (USE_HT32_CHIP=HT32F52220_30) + DCD _RESERVED ; 18, 34, 0x088, + ELSE + DCD BFTM1_IRQHandler ; 18, 34, 0x088, + ENDIF + DCD I2C0_IRQHandler ; 19, 35, 0x08C, + IF (USE_HT32_CHIP=HT32F52220_30) || (USE_HT32_CHIP=HT32F0008) || (USE_HT32_CHIP=HT32F52344_54) || (USE_HT32_CHIP=HT32F0006) + DCD _RESERVED ; 20, 36, 0x090, + ELSE + DCD I2C1_IRQHandler ; 20, 36, 0x090, + ENDIF + DCD SPI0_IRQHandler ; 21, 37, 0x094, + IF (USE_HT32_CHIP=HT32F52220_30) || (USE_HT32_CHIP=HT32F0008) + DCD _RESERVED ; 22, 38, 0x098, + ELSE + IF (USE_HT32_CHIP=HT32F0006) + DCD QSPI_IRQHandler ; 22, 38, 0x098, + ELSE + DCD SPI1_IRQHandler ; 22, 38, 0x098, + ENDIF + ENDIF + IF (USE_HT32_CHIP=HT32F52344_54) + DCD _RESERVED ; 23, 39, 0x09C, + ELSE + DCD USART0_IRQHandler ; 23, 39, 0x09C, + ENDIF + IF (USE_HT32_CHIP=HT32F52342_52) || (USE_HT32_CHIP=HT32F52243_53) + DCD USART1_IRQHandler ; 24, 40, 0x0A0, + ELSE + DCD _RESERVED ; 24, 40, 0x0A0, + ENDIF + DCD UART0_IRQHandler ; 25, 41, 0x0A4, + IF (USE_HT32_CHIP=HT32F52220_30) || (USE_HT32_CHIP=HT32F0008) || (USE_HT32_CHIP=HT32F0006) + DCD _RESERVED ; 26, 42, 0x0A8, + ELSE + DCD UART1_IRQHandler ; 26, 42, 0x0A8, + ENDIF + IF (USE_HT32_CHIP=HT32F52331_41) || (USE_HT32_CHIP=HT32F52342_52) + DCD SCI_IRQHandler ; 27, 43, 0x0AC, + ENDIF + IF (USE_HT32_CHIP=HT32F52243_53) + DCD UART2_IRQHandler ; 27, 43, 0x0AC, + ENDIF + IF (USE_HT32_CHIP=HT32F0006) + DCD MIDI_IRQHandler ; 27, 43, 0x0AC, + ENDIF + IF (USE_HT32_CHIP=HT32F0008) || (USE_HT32_CHIP=HT32F52344_54) + DCD _RESERVED ; 27, 43, 0xAC, + ENDIF + IF (USE_HT32_CHIP=HT32F52342_52) || (USE_HT32_CHIP=HT32F0006) + DCD I2S_IRQHandler ; 28, 44, 0x0B0, + ENDIF + IF (USE_HT32_CHIP=HT32F52331_41) || (USE_HT32_CHIP=HT32F52344_54) + DCD _RESERVED ; 28, 44, 0x0B0, + ENDIF + IF (USE_HT32_CHIP=HT32F52243_53) + DCD UART3_IRQHandler ; 28, 44, 0x0B0, + ENDIF + IF (USE_HT32_CHIP=HT32F0008) + DCD AES_IRQHandler ; 28, 44, 0x0B0, + ENDIF + IF (USE_HT32_CHIP=HT32F52331_41) || (USE_HT32_CHIP=HT32F52342_52) || (USE_HT32_CHIP=HT32F0008) || (USE_HT32_CHIP=HT32F52344_54) || (USE_HT32_CHIP=HT32F0006) + DCD USB_IRQHandler ; 29, 45, 0x0B4, + ENDIF + IF (USE_HT32_CHIP=HT32F52243_53) + DCD _RESERVED ; 29, 45, 0x0B4, + ENDIF + IF (USE_HT32_CHIP=HT32F52342_52) || (USE_HT32_CHIP=HT32F52243_53) || (USE_HT32_CHIP=HT32F0008) || (USE_HT32_CHIP=HT32F52344_54) || (USE_HT32_CHIP=HT32F0006) + DCD PDMA_CH0_1_IRQHandler ; 30, 46, 0x0B8, + DCD PDMA_CH2_5_IRQHandler ; 31, 47, 0x0BC, + ENDIF + +; Reset handler routine +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + LDR R0, =BootProcess + BLX R0 + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +BootProcess PROC + LDR R0, =0x40080300 + LDR R1,[R0, #0x10] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x14] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x18] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x1C] + CMP R1, #0 + BEQ BP2 +BP1 LDR R0, =0x40080180 + LDR R1,[R0, #0xC] + LSLS R1, R1, #4 + LSRS R1, R1, #20 + CMP R1, #0 + BEQ BP3 + CMP R1, #5 + BEQ BP3 + CMP R1, #6 + BEQ BP3 +BP2 DSB + LDR R0, =0x20000000 + LDR R1, =0x05fa0004 + STR R1, [R0] + LDR R1, =0xe000ed00 + LDR R0, =0x05fa0004 + STR R0, [R1, #0xC] + DSB + B . +BP3 LDR R0, =0x20000000 + LDR R1, [R0] + LDR R0, =0x05fa0004 + CMP R0, R1 + BEQ BP4 + BX LR +BP4 LDR R0, =0x40088100 + LDR R1, =0x00000001 + STR R1, [R0] + LDR R0, =0x20000000 + LDR R1, =0x0 + STR R1, [R0] + BX LR + ENDP + +; Dummy Exception Handlers +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP + +HardFault_Handler PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP + +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP + +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP + +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + EXPORT LVD_BOD_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT EVWUP_IRQHandler [WEAK] + EXPORT EXTI0_1_IRQHandler [WEAK] + EXPORT EXTI2_3_IRQHandler [WEAK] + EXPORT EXTI4_15_IRQHandler [WEAK] + EXPORT COMP_IRQHandler [WEAK] + EXPORT ADC_IRQHandler [WEAK] + EXPORT MCTM0_IRQHandler [WEAK] + EXPORT GPTM1_IRQHandler [WEAK] + EXPORT GPTM0_IRQHandler [WEAK] + EXPORT SCTM0_IRQHandler [WEAK] + EXPORT SCTM1_IRQHandler [WEAK] + EXPORT SCTM2_IRQHandler [WEAK] + EXPORT SCTM3_IRQHandler [WEAK] + EXPORT PWM0_IRQHandler [WEAK] + EXPORT PWM1_IRQHandler [WEAK] + EXPORT BFTM0_IRQHandler [WEAK] + EXPORT BFTM1_IRQHandler [WEAK] + EXPORT I2C0_IRQHandler [WEAK] + EXPORT I2C1_IRQHandler [WEAK] + EXPORT I2C2_IRQHandler [WEAK] + EXPORT SPI0_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT QSPI_IRQHandler [WEAK] + EXPORT USART0_IRQHandler [WEAK] + EXPORT USART1_IRQHandler [WEAK] + EXPORT UART0_IRQHandler [WEAK] + EXPORT UART1_IRQHandler [WEAK] + EXPORT UART2_IRQHandler [WEAK] + EXPORT UART3_IRQHandler [WEAK] + EXPORT SCI_IRQHandler [WEAK] + EXPORT MIDI_IRQHandler [WEAK] + EXPORT I2S_IRQHandler [WEAK] + EXPORT AES_IRQHandler [WEAK] + EXPORT USB_IRQHandler [WEAK] + EXPORT PDMA_CH0_1_IRQHandler [WEAK] + EXPORT PDMA_CH2_5_IRQHandler [WEAK] + +LVD_BOD_IRQHandler +RTC_IRQHandler +FLASH_IRQHandler +EVWUP_IRQHandler +EXTI0_1_IRQHandler +EXTI2_3_IRQHandler +EXTI4_15_IRQHandler +COMP_IRQHandler +ADC_IRQHandler +MCTM0_IRQHandler +GPTM1_IRQHandler +GPTM0_IRQHandler +SCTM0_IRQHandler +SCTM1_IRQHandler +SCTM2_IRQHandler +SCTM3_IRQHandler +PWM0_IRQHandler +PWM1_IRQHandler +BFTM0_IRQHandler +BFTM1_IRQHandler +I2C0_IRQHandler +I2C1_IRQHandler +I2C2_IRQHandler +SPI0_IRQHandler +SPI1_IRQHandler +QSPI_IRQHandler +USART0_IRQHandler +USART1_IRQHandler +UART0_IRQHandler +UART1_IRQHandler +UART2_IRQHandler +UART3_IRQHandler +SCI_IRQHandler +MIDI_IRQHandler +I2S_IRQHandler +AES_IRQHandler +USB_IRQHandler +PDMA_CH0_1_IRQHandler +PDMA_CH2_5_IRQHandler + B . + ENDP + + ALIGN + +;******************************************************************************* +; User Stack and Heap initialization +;******************************************************************************* + IF :DEF:__MICROLIB + + EXPORT __HT_check_heap + EXPORT __HT_check_sp + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, = (Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + + ENDIF + + END diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f52342_52.s b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f52342_52.s new file mode 100644 index 0000000000..2285fed9c8 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f52342_52.s @@ -0,0 +1,482 @@ +;/*---------------------------------------------------------------------------------------------------------*/ +;/* Holtek Semiconductor Inc. */ +;/* */ +;/* Copyright (C) Holtek Semiconductor Inc. */ +;/* All rights reserved. */ +;/* */ +;/*----------------------------------------------------------------------------------------------------------- +; File Name : startup_ht32f5xxxx_01.s +; Version : $Rev:: 6953 $ +; Date : $Date:: 2023-05-30 #$ +; Description : Startup code. +;-----------------------------------------------------------------------------------------------------------*/ + +; Supported Device +; ======================================== +; HT32F52220, HT32F52230 +; HT32F52231, HT32F52241 +; HT32F52331, HT32F52341 +; HT32F52342, HT32F52352 +; HT32F52243, HT32F52253 +; HT32F0008 +; HT32F52344, HT32F52354 +; HT32F0006 +; HT32F61352 +; HT50F32003 +; HT32F62030, HT32F62040, HT32F62050 +; HT32F67741 +; HT32F67232 +; HT32F67233 + +;/* <<< Use Configuration Wizard in Context Menu >>> */ + +;// HT32 Device +;// Select HT32 Device for the assembly setting. +;// Notice that the project's Asm Define has the higher priority. +;// <0=> By Project Asm Define +;// <1=> HT32F52220/30 +;// <2=> HT32F52231/41 +;// <3=> HT32F52331/41 +;// <4=> HT32F52342/52 +;// <5=> HT32F52243/53 +;// <6=> HT32F0008 +;// <9=> HT32F52344/54 +;// <10=> HT32F0006 +;// <10=> HT32F61352 +;// <4=> HT50F32003 +;// <2=> HT32F67741 +;// <1=> HT32F67232 +;// <1=> HT32F67233 +;// <1=> HT32F62030 +;// <2=> HT32F62040 +;// <5=> HT32F62050 +USE_HT32_CHIP_SET EQU 4 ; Notice that the project's Asm Define has the higher priority. + +_HT32FWID EQU 0xFFFFFFFF +;_HT32FWID EQU 0x00052220 +;_HT32FWID EQU 0x00052230 +;_HT32FWID EQU 0x00052231 +;_HT32FWID EQU 0x00052241 +;_HT32FWID EQU 0x00052331 +;_HT32FWID EQU 0x00052341 +;_HT32FWID EQU 0x00052342 +;_HT32FWID EQU 0x00052352 +;_HT32FWID EQU 0x00052243 +;_HT32FWID EQU 0x00052253 +;_HT32FWID EQU 0x00000008 +;_HT32FWID EQU 0x00052344 +;_HT32FWID EQU 0x00052354 +;_HT32FWID EQU 0x00000006 +;_HT32FWID EQU 0x00061352 +;_HT32FWID EQU 0x00032003 +;_HT32FWID EQU 0x00062030 +;_HT32FWID EQU 0x00062040 +;_HT32FWID EQU 0x00062050 +;_HT32FWID EQU 0x00067741 +;_HT32FWID EQU 0x00067232 +;_HT32FWID EQU 0x00067233 + +HT32F52220_30 EQU 1 +HT32F52231_41 EQU 2 +HT32F52331_41 EQU 3 +HT32F52342_52 EQU 4 +HT32F52243_53 EQU 5 +HT32F0008 EQU 6 +HT32F52344_54 EQU 9 +HT32F0006 EQU 10 +HT32F61352 EQU 10 +HT50F32003 EQU 4 +HT32F62030 EQU 1 +HT32F62040 EQU 2 +HT32F62050 EQU 5 +HT32F67741 EQU 2 +HT32F67232 EQU 1 +HT32F67233 EQU 1 + + IF USE_HT32_CHIP_SET=0 + ; Use project's Asm Define setting (default) + ELSE + IF :DEF:USE_HT32_CHIP + ; Use project's Asm Define setting (higher priority than the "USE_HT32_CHIP_SET") + ELSE + ; Use "USE_HT32_CHIP_SET" in the "startup_ht32xxxxx_xx.s" file +USE_HT32_CHIP EQU USE_HT32_CHIP_SET + ENDIF + ENDIF + +; Amount of memory (in bytes) allocated for Stack and Heap +; Tailor those values to your application needs +;// Stack Size (in Bytes, must 8 byte aligned) <0-16384:8> +Stack_Size EQU 512 + + AREA STACK, NOINIT, READWRITE, ALIGN = 3 +__HT_check_sp +Stack_Mem SPACE Stack_Size +__initial_sp + +;// Heap Size (in Bytes) <0-16384:8> +Heap_Size EQU 0 + + AREA HEAP, NOINIT, READWRITE, ALIGN = 3 +__HT_check_heap +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + PRESERVE8 + THUMB + +;******************************************************************************* +; Fill-up the Vector Table entries with the exceptions ISR address +;******************************************************************************* + AREA RESET, CODE, READONLY + EXPORT __Vectors +_RESERVED EQU 0xFFFFFFFF +__Vectors + DCD __initial_sp ; ---, 00, 0x000, Top address of Stack + DCD Reset_Handler ; ---, 01, 0x004, Reset Handler + DCD NMI_Handler ; -14, 02, 0x008, NMI Handler + DCD HardFault_Handler ; -13, 03, 0x00C, Hard Fault Handler + DCD _RESERVED ; ---, 04, 0x010, Reserved + DCD _RESERVED ; ---, 05, 0x014, Reserved + DCD _RESERVED ; ---, 06, 0x018, Reserved + DCD _RESERVED ; ---, 07, 0x01C, Reserved + DCD _HT32FWID ; ---, 08, 0x020, Reserved + DCD _RESERVED ; ---, 09, 0x024, Reserved + DCD _RESERVED ; ---, 10, 0x028, Reserved + DCD SVC_Handler ; -05, 11, 0x02C, SVC Handler + DCD _RESERVED ; ---, 12, 0x030, Reserved + DCD _RESERVED ; ---, 13, 0x034, Reserved + DCD PendSV_Handler ; -02, 14, 0x038, PendSV Handler + DCD SysTick_Handler ; -01, 15, 0x03C, SysTick Handler + + ; External Interrupt Handler + DCD LVD_BOD_IRQHandler ; 00, 16, 0x040, + IF (USE_HT32_CHIP=HT32F52220_30) + DCD _RESERVED ; 01, 17, 0x044, + ELSE + DCD RTC_IRQHandler ; 01, 17, 0x044, + ENDIF + DCD FLASH_IRQHandler ; 02, 18, 0x048, + DCD EVWUP_IRQHandler ; 03, 19, 0x04C, + DCD EXTI0_1_IRQHandler ; 04, 20, 0x050, + DCD EXTI2_3_IRQHandler ; 05, 21, 0x054, + DCD EXTI4_15_IRQHandler ; 06, 22, 0x058, + IF (USE_HT32_CHIP=HT32F52342_52) || (USE_HT32_CHIP=HT32F52344_54) + DCD COMP_IRQHandler ; 07, 23, 0x05C, + ELSE + DCD _RESERVED ; 07, 23, 0x05C, + ENDIF + IF (USE_HT32_CHIP=HT32F0008) + DCD _RESERVED ; 08, 24, 0x060, + ELSE + DCD ADC_IRQHandler ; 08, 24, 0x060, + ENDIF + IF (USE_HT32_CHIP=HT32F52243_53) + DCD I2C2_IRQHandler ; 09, 25, 0x064, + ELSE + DCD _RESERVED ; 09, 25, 0x064, + ENDIF + IF (USE_HT32_CHIP=HT32F52220_30) || (USE_HT32_CHIP=HT32F0008) || (USE_HT32_CHIP=HT32F0006) + DCD _RESERVED ; 10, 26, 0x068, + ELSE + DCD MCTM0_IRQHandler ; 10, 26, 0x068, + ENDIF + IF (USE_HT32_CHIP=HT32F52342_52) + DCD GPTM1_IRQHandler ; 11, 27, 0x06C, + ELSE + DCD _RESERVED ; 11, 27, 0x06C, + ENDIF + DCD GPTM0_IRQHandler ; 12, 28, 0x070, + IF (USE_HT32_CHIP=HT32F0008) + DCD _RESERVED ; 13, 29, 0x074, + DCD _RESERVED ; 14, 30, 0x078, + ELSE + DCD SCTM0_IRQHandler ; 13, 29, 0x074, + DCD SCTM1_IRQHandler ; 14, 30, 0x078, + ENDIF + IF (USE_HT32_CHIP=HT32F52231_41) || (USE_HT32_CHIP=HT32F52331_41) || (USE_HT32_CHIP=HT32F52243_53) || (USE_HT32_CHIP=HT32F0006) + DCD SCTM2_IRQHandler ; 15, 31, 0x07C, + DCD SCTM3_IRQHandler ; 16, 32, 0x080, + ENDIF + IF (USE_HT32_CHIP=HT32F0008) + DCD PWM0_IRQHandler ; 15, 31, 0x07C, + DCD PWM1_IRQHandler ; 16, 32, 0x080, + ENDIF + IF (USE_HT32_CHIP=HT32F52220_30) || (USE_HT32_CHIP=HT32F52342_52) || (USE_HT32_CHIP=HT32F52344_54) + DCD _RESERVED ; 15, 31, 0x07C, + DCD _RESERVED ; 16, 32, 0x080, + ENDIF + DCD BFTM0_IRQHandler ; 17, 33, 0x084, + IF (USE_HT32_CHIP=HT32F52220_30) + DCD _RESERVED ; 18, 34, 0x088, + ELSE + DCD BFTM1_IRQHandler ; 18, 34, 0x088, + ENDIF + DCD I2C0_IRQHandler ; 19, 35, 0x08C, + IF (USE_HT32_CHIP=HT32F52220_30) || (USE_HT32_CHIP=HT32F0008) || (USE_HT32_CHIP=HT32F52344_54) || (USE_HT32_CHIP=HT32F0006) + DCD _RESERVED ; 20, 36, 0x090, + ELSE + DCD I2C1_IRQHandler ; 20, 36, 0x090, + ENDIF + DCD SPI0_IRQHandler ; 21, 37, 0x094, + IF (USE_HT32_CHIP=HT32F52220_30) || (USE_HT32_CHIP=HT32F0008) + DCD _RESERVED ; 22, 38, 0x098, + ELSE + IF (USE_HT32_CHIP=HT32F0006) + DCD QSPI_IRQHandler ; 22, 38, 0x098, + ELSE + DCD SPI1_IRQHandler ; 22, 38, 0x098, + ENDIF + ENDIF + IF (USE_HT32_CHIP=HT32F52344_54) + DCD _RESERVED ; 23, 39, 0x09C, + ELSE + DCD USART0_IRQHandler ; 23, 39, 0x09C, + ENDIF + IF (USE_HT32_CHIP=HT32F52342_52) || (USE_HT32_CHIP=HT32F52243_53) + DCD USART1_IRQHandler ; 24, 40, 0x0A0, + ELSE + DCD _RESERVED ; 24, 40, 0x0A0, + ENDIF + DCD UART0_IRQHandler ; 25, 41, 0x0A4, + IF (USE_HT32_CHIP=HT32F52220_30) || (USE_HT32_CHIP=HT32F0008) || (USE_HT32_CHIP=HT32F0006) + DCD _RESERVED ; 26, 42, 0x0A8, + ELSE + DCD UART1_IRQHandler ; 26, 42, 0x0A8, + ENDIF + IF (USE_HT32_CHIP=HT32F52331_41) || (USE_HT32_CHIP=HT32F52342_52) + DCD SCI_IRQHandler ; 27, 43, 0x0AC, + ENDIF + IF (USE_HT32_CHIP=HT32F52243_53) + DCD UART2_IRQHandler ; 27, 43, 0x0AC, + ENDIF + IF (USE_HT32_CHIP=HT32F0006) + DCD MIDI_IRQHandler ; 27, 43, 0x0AC, + ENDIF + IF (USE_HT32_CHIP=HT32F0008) || (USE_HT32_CHIP=HT32F52344_54) + DCD _RESERVED ; 27, 43, 0xAC, + ENDIF + IF (USE_HT32_CHIP=HT32F52342_52) || (USE_HT32_CHIP=HT32F0006) + DCD I2S_IRQHandler ; 28, 44, 0x0B0, + ENDIF + IF (USE_HT32_CHIP=HT32F52331_41) || (USE_HT32_CHIP=HT32F52344_54) + DCD _RESERVED ; 28, 44, 0x0B0, + ENDIF + IF (USE_HT32_CHIP=HT32F52243_53) + DCD UART3_IRQHandler ; 28, 44, 0x0B0, + ENDIF + IF (USE_HT32_CHIP=HT32F0008) + DCD AES_IRQHandler ; 28, 44, 0x0B0, + ENDIF + IF (USE_HT32_CHIP=HT32F52331_41) || (USE_HT32_CHIP=HT32F52342_52) || (USE_HT32_CHIP=HT32F0008) || (USE_HT32_CHIP=HT32F52344_54) || (USE_HT32_CHIP=HT32F0006) + DCD USB_IRQHandler ; 29, 45, 0x0B4, + ENDIF + IF (USE_HT32_CHIP=HT32F52243_53) + DCD _RESERVED ; 29, 45, 0x0B4, + ENDIF + IF (USE_HT32_CHIP=HT32F52342_52) || (USE_HT32_CHIP=HT32F52243_53) || (USE_HT32_CHIP=HT32F0008) || (USE_HT32_CHIP=HT32F52344_54) || (USE_HT32_CHIP=HT32F0006) + DCD PDMA_CH0_1_IRQHandler ; 30, 46, 0x0B8, + DCD PDMA_CH2_5_IRQHandler ; 31, 47, 0x0BC, + ENDIF + +; Reset handler routine +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + LDR R0, =BootProcess + BLX R0 + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +BootProcess PROC + LDR R0, =0x40080300 + LDR R1,[R0, #0x10] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x14] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x18] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x1C] + CMP R1, #0 + BEQ BP2 +BP1 LDR R0, =0x40080180 + LDR R1,[R0, #0xC] + LSLS R1, R1, #4 + LSRS R1, R1, #20 + CMP R1, #0 + BEQ BP3 + CMP R1, #5 + BEQ BP3 + CMP R1, #6 + BEQ BP3 +BP2 DSB + LDR R0, =0x20000000 + LDR R1, =0x05fa0004 + STR R1, [R0] + LDR R1, =0xe000ed00 + LDR R0, =0x05fa0004 + STR R0, [R1, #0xC] + DSB + B . +BP3 LDR R0, =0x20000000 + LDR R1, [R0] + LDR R0, =0x05fa0004 + CMP R0, R1 + BEQ BP4 + BX LR +BP4 LDR R0, =0x40088100 + LDR R1, =0x00000001 + STR R1, [R0] + LDR R0, =0x20000000 + LDR R1, =0x0 + STR R1, [R0] + BX LR + ENDP + +; Dummy Exception Handlers +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP + +HardFault_Handler PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP + +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP + +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP + +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + EXPORT LVD_BOD_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT EVWUP_IRQHandler [WEAK] + EXPORT EXTI0_1_IRQHandler [WEAK] + EXPORT EXTI2_3_IRQHandler [WEAK] + EXPORT EXTI4_15_IRQHandler [WEAK] + EXPORT COMP_IRQHandler [WEAK] + EXPORT ADC_IRQHandler [WEAK] + EXPORT MCTM0_IRQHandler [WEAK] + EXPORT GPTM1_IRQHandler [WEAK] + EXPORT GPTM0_IRQHandler [WEAK] + EXPORT SCTM0_IRQHandler [WEAK] + EXPORT SCTM1_IRQHandler [WEAK] + EXPORT SCTM2_IRQHandler [WEAK] + EXPORT SCTM3_IRQHandler [WEAK] + EXPORT PWM0_IRQHandler [WEAK] + EXPORT PWM1_IRQHandler [WEAK] + EXPORT BFTM0_IRQHandler [WEAK] + EXPORT BFTM1_IRQHandler [WEAK] + EXPORT I2C0_IRQHandler [WEAK] + EXPORT I2C1_IRQHandler [WEAK] + EXPORT I2C2_IRQHandler [WEAK] + EXPORT SPI0_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT QSPI_IRQHandler [WEAK] + EXPORT USART0_IRQHandler [WEAK] + EXPORT USART1_IRQHandler [WEAK] + EXPORT UART0_IRQHandler [WEAK] + EXPORT UART1_IRQHandler [WEAK] + EXPORT UART2_IRQHandler [WEAK] + EXPORT UART3_IRQHandler [WEAK] + EXPORT SCI_IRQHandler [WEAK] + EXPORT MIDI_IRQHandler [WEAK] + EXPORT I2S_IRQHandler [WEAK] + EXPORT AES_IRQHandler [WEAK] + EXPORT USB_IRQHandler [WEAK] + EXPORT PDMA_CH0_1_IRQHandler [WEAK] + EXPORT PDMA_CH2_5_IRQHandler [WEAK] + +LVD_BOD_IRQHandler +RTC_IRQHandler +FLASH_IRQHandler +EVWUP_IRQHandler +EXTI0_1_IRQHandler +EXTI2_3_IRQHandler +EXTI4_15_IRQHandler +COMP_IRQHandler +ADC_IRQHandler +MCTM0_IRQHandler +GPTM1_IRQHandler +GPTM0_IRQHandler +SCTM0_IRQHandler +SCTM1_IRQHandler +SCTM2_IRQHandler +SCTM3_IRQHandler +PWM0_IRQHandler +PWM1_IRQHandler +BFTM0_IRQHandler +BFTM1_IRQHandler +I2C0_IRQHandler +I2C1_IRQHandler +I2C2_IRQHandler +SPI0_IRQHandler +SPI1_IRQHandler +QSPI_IRQHandler +USART0_IRQHandler +USART1_IRQHandler +UART0_IRQHandler +UART1_IRQHandler +UART2_IRQHandler +UART3_IRQHandler +SCI_IRQHandler +MIDI_IRQHandler +I2S_IRQHandler +AES_IRQHandler +USB_IRQHandler +PDMA_CH0_1_IRQHandler +PDMA_CH2_5_IRQHandler + B . + ENDP + + ALIGN + +;******************************************************************************* +; User Stack and Heap initialization +;******************************************************************************* + IF :DEF:__MICROLIB + + EXPORT __HT_check_heap + EXPORT __HT_check_sp + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, = (Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + + ENDIF + + END diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f52344_54.s b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f52344_54.s new file mode 100644 index 0000000000..e745eaa803 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f52344_54.s @@ -0,0 +1,403 @@ +;/*---------------------------------------------------------------------------------------------------------*/ +;/* Holtek Semiconductor Inc. */ +;/* */ +;/* Copyright (C) Holtek Semiconductor Inc. */ +;/* All rights reserved. */ +;/* */ +;/*----------------------------------------------------------------------------------------------------------- +; File Name : startup_ht32f5xxxx_03.s +; Version : $Rev:: 6877 $ +; Date : $Date:: 2023-05-04 #$ +; Description : Startup code. +;-----------------------------------------------------------------------------------------------------------*/ + +; Supported Device +; ======================================== +; HT32F0008 +; HT32F52142 +; HT32F52344, HT32F52354 +; HT32F52357, HT32F52367 +; HT50F3200T + +;/* <<< Use Configuration Wizard in Context Menu >>> */ + +;// HT32 Device +;// Select HT32 Device for the assembly setting. +;// Notice that the project's Asm Define has the higher priority. +;// <0=> By Project Asm Define +;// <6=> HT32F0008 +;// <6=> HT32F52142 +;// <9=> HT32F52344/54 +;// <11=> HT32F52357/67 +;// <11=> HT50F3200T +USE_HT32_CHIP_SET EQU 9 ; Notice that the project's Asm Define has the higher priority. + +_HT32FWID EQU 0xFFFFFFFF +;_HT32FWID EQU 0x00000008 +;_HT32FWID EQU 0x00052142 +;_HT32FWID EQU 0x00052344 +;_HT32FWID EQU 0x00052354 +;_HT32FWID EQU 0x00052357 +;_HT32FWID EQU 0x00052367 +;_HT32FWID EQU 0x0003200F + +HT32F0008 EQU 6 +HT32F52142 EQU 6 +HT32F52344_54 EQU 9 +HT32F52357_67 EQU 11 +HT50F3200T EQU 11 + + IF USE_HT32_CHIP_SET=0 + ; Use project's Asm Define setting (default) + ELSE + IF :DEF:USE_HT32_CHIP + ; Use project's Asm Define setting (higher priority than the "USE_HT32_CHIP_SET") + ELSE + ; Use "USE_HT32_CHIP_SET" in the "startup_ht32xxxxx_xx.s" file +USE_HT32_CHIP EQU USE_HT32_CHIP_SET + ENDIF + ENDIF + +; Amount of memory (in bytes) allocated for Stack and Heap +; Tailor those values to your application needs +;// Stack Size (in Bytes, must 8 byte aligned) <0-16384:8> +Stack_Size EQU 512 + + AREA STACK, NOINIT, READWRITE, ALIGN = 3 +__HT_check_sp +Stack_Mem SPACE Stack_Size +__initial_sp + +;// Heap Size (in Bytes) <0-16384:8> +Heap_Size EQU 0 + + AREA HEAP, NOINIT, READWRITE, ALIGN = 3 +__HT_check_heap +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + PRESERVE8 + THUMB + +;******************************************************************************* +; Fill-up the Vector Table entries with the exceptions ISR address +;******************************************************************************* + AREA RESET, CODE, READONLY + EXPORT __Vectors +_RESERVED EQU 0xFFFFFFFF +__Vectors + DCD __initial_sp ; ---, 00, 0x000, Top address of Stack + DCD Reset_Handler ; ---, 01, 0x004, Reset Handler + DCD NMI_Handler ; -14, 02, 0x008, NMI Handler + DCD HardFault_Handler ; -13, 03, 0x00C, Hard Fault Handler + DCD _RESERVED ; ---, 04, 0x010, Reserved + DCD _RESERVED ; ---, 05, 0x014, Reserved + DCD _RESERVED ; ---, 06, 0x018, Reserved + DCD _RESERVED ; ---, 07, 0x01C, Reserved + DCD _HT32FWID ; ---, 08, 0x020, Reserved + DCD _RESERVED ; ---, 09, 0x024, Reserved + DCD _RESERVED ; ---, 10, 0x028, Reserved + DCD SVC_Handler ; -05, 11, 0x02C, SVC Handler + DCD _RESERVED ; ---, 12, 0x030, Reserved + DCD _RESERVED ; ---, 13, 0x034, Reserved + DCD PendSV_Handler ; -02, 14, 0x038, PendSV Handler + DCD SysTick_Handler ; -01, 15, 0x03C, SysTick Handler + + ; External Interrupt Handler + DCD LVD_BOD_IRQHandler ; 00, 16, 0x040, + DCD RTC_IRQHandler ; 01, 17, 0x044, + DCD FLASH_IRQHandler ; 02, 18, 0x048, + DCD EVWUP_IRQHandler ; 03, 19, 0x04C, + DCD EXTI0_1_IRQHandler ; 04, 20, 0x050, + DCD EXTI2_3_IRQHandler ; 05, 21, 0x054, + DCD EXTI4_15_IRQHandler ; 06, 22, 0x058, + IF (USE_HT32_CHIP=HT32F0008) + DCD _RESERVED ; 07, 23, 0x05C, + ENDIF + IF (USE_HT32_CHIP=HT32F52344_54) + DCD COMP_IRQHandler ; 07, 23, 0x05C, + ENDIF + IF (USE_HT32_CHIP=HT32F52357_67) + DCD COMP_DAC_IRQHandler ; 07, 23, 0x05C, + ENDIF + IF (USE_HT32_CHIP=HT32F0008) + DCD _RESERVED ; 08, 24, 0x060, + ELSE + DCD ADC_IRQHandler ; 08, 24, 0x060, + ENDIF + IF (USE_HT32_CHIP=HT32F52357_67) + DCD AES_IRQHandler ; 09, 25, 0x064, + ELSE + DCD _RESERVED ; 09, 25, 0x064, + ENDIF + IF (USE_HT32_CHIP=HT32F0008) + DCD _RESERVED ; 10, 26, 0x068, + ELSE + DCD MCTM0_IRQHandler ; 10, 26, 0x068, + ENDIF + IF (USE_HT32_CHIP=HT32F52357_67) + DCD QSPI_IRQHandler ; 11, 27, 0x06C, + ELSE + DCD _RESERVED ; 11, 27, 0x06C, + ENDIF + DCD GPTM0_IRQHandler ; 12, 28, 0x070, + IF (USE_HT32_CHIP=HT32F0008) + DCD _RESERVED ; 13, 29, 0x074, + DCD _RESERVED ; 14, 30, 0x078, + ELSE + DCD SCTM0_IRQHandler ; 13, 29, 0x074, + DCD SCTM1_IRQHandler ; 14, 30, 0x078, + ENDIF + IF (USE_HT32_CHIP=HT32F0008) || (USE_HT32_CHIP=HT32F52357_67) + DCD PWM0_IRQHandler ; 15, 31, 0x07C, + DCD PWM1_IRQHandler ; 16, 32, 0x080, + ENDIF + IF (USE_HT32_CHIP=HT32F52344_54) + DCD _RESERVED ; 15, 31, 0x07C, + DCD _RESERVED ; 16, 32, 0x080, + ENDIF + DCD BFTM0_IRQHandler ; 17, 33, 0x084, + DCD BFTM1_IRQHandler ; 18, 34, 0x088, + DCD I2C0_IRQHandler ; 19, 35, 0x08C, + IF (USE_HT32_CHIP=HT32F0008) || (USE_HT32_CHIP=HT32F52344_54) + DCD _RESERVED ; 20, 36, 0x090, + ELSE + DCD I2C1_IRQHandler ; 20, 36, 0x090, + ENDIF + DCD SPI0_IRQHandler ; 21, 37, 0x094, + IF (USE_HT32_CHIP=HT32F0008) + DCD _RESERVED ; 22, 38, 0x098, + ELSE + DCD SPI1_IRQHandler ; 22, 38, 0x098, + ENDIF + IF (USE_HT32_CHIP=HT32F52344_54) + DCD _RESERVED ; 23, 39, 0x09C, + ELSE + DCD USART0_IRQHandler ; 23, 39, 0x09C, + ENDIF + IF (USE_HT32_CHIP=HT32F0008) + DCD _RESERVED ; 24, 40, 0x0A0, + DCD UART0_IRQHandler ; 25, 41, 0x0A4, + DCD _RESERVED ; 26, 42, 0x0A8, + ENDIF + IF (USE_HT32_CHIP=HT32F52344_54) + DCD _RESERVED ; 24, 40, 0x0A0, + DCD UART0_IRQHandler ; 25, 41, 0x0A4, + DCD UART1_IRQHandler ; 26, 42, 0x0A8, + ENDIF + IF (USE_HT32_CHIP=HT32F52357_67) + DCD USART1_IRQHandler ; 24, 40, 0x0A0, + DCD UART0_UART2_IRQHandler ; 25, 41, 0x0A4, + DCD UART1_UART3_IRQHandler ; 26, 42, 0x0A8, + ENDIF + IF (USE_HT32_CHIP=HT32F52357_67) + DCD SCI_IRQHandler ; 27, 43, 0xAC, + ELSE + DCD _RESERVED ; 27, 43, 0xAC, + ENDIF + IF (USE_HT32_CHIP=HT32F0008) + DCD AES_IRQHandler ; 28, 44, 0x0B0, + ENDIF + IF (USE_HT32_CHIP=HT32F52344_54) + DCD _RESERVED ; 28, 44, 0x0B0, + ENDIF + IF (USE_HT32_CHIP=HT32F52357_67) + DCD I2S_IRQHandler ; 28, 44, 0x0B0, + ENDIF + DCD USB_IRQHandler ; 29, 45, 0x0B4, + DCD PDMA_CH0_1_IRQHandler ; 30, 46, 0x0B8, + DCD PDMA_CH2_5_IRQHandler ; 31, 47, 0x0BC, + +; Reset handler routine +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + LDR R0, =BootProcess + BLX R0 + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +BootProcess PROC + LDR R0, =0x40080300 + LDR R1,[R0, #0x10] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x14] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x18] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x1C] + CMP R1, #0 + BEQ BP2 +BP1 LDR R0, =0x40080180 + LDR R1,[R0, #0xC] + LSLS R1, R1, #4 + LSRS R1, R1, #20 + CMP R1, #0 + BEQ BP3 + CMP R1, #5 + BEQ BP3 + CMP R1, #6 + BEQ BP3 +BP2 DSB + LDR R0, =0x20000000 + LDR R1, =0x05fa0004 + STR R1, [R0] + LDR R1, =0xe000ed00 + LDR R0, =0x05fa0004 + STR R0, [R1, #0xC] + DSB + B . +BP3 LDR R0, =0x20000000 + LDR R1, [R0] + LDR R0, =0x05fa0004 + CMP R0, R1 + BEQ BP4 + BX LR +BP4 LDR R0, =0x40088100 + LDR R1, =0x00000001 + STR R1, [R0] + LDR R0, =0x20000000 + LDR R1, =0x0 + STR R1, [R0] + BX LR + ENDP + +; Dummy Exception Handlers +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP + +HardFault_Handler PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP + +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP + +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP + +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + EXPORT LVD_BOD_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT EVWUP_IRQHandler [WEAK] + EXPORT EXTI0_1_IRQHandler [WEAK] + EXPORT EXTI2_3_IRQHandler [WEAK] + EXPORT EXTI4_15_IRQHandler [WEAK] + EXPORT COMP_IRQHandler [WEAK] + EXPORT COMP_DAC_IRQHandler [WEAK] + EXPORT ADC_IRQHandler [WEAK] + EXPORT MCTM0_IRQHandler [WEAK] + EXPORT GPTM0_IRQHandler [WEAK] + EXPORT SCTM0_IRQHandler [WEAK] + EXPORT SCTM1_IRQHandler [WEAK] + EXPORT PWM0_IRQHandler [WEAK] + EXPORT PWM1_IRQHandler [WEAK] + EXPORT BFTM0_IRQHandler [WEAK] + EXPORT BFTM1_IRQHandler [WEAK] + EXPORT I2C0_IRQHandler [WEAK] + EXPORT I2C1_IRQHandler [WEAK] + EXPORT SPI0_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT QSPI_IRQHandler [WEAK] + EXPORT USART0_IRQHandler [WEAK] + EXPORT USART1_IRQHandler [WEAK] + EXPORT UART0_IRQHandler [WEAK] + EXPORT UART1_IRQHandler [WEAK] + EXPORT UART0_UART2_IRQHandler [WEAK] + EXPORT UART1_UART3_IRQHandler [WEAK] + EXPORT SCI_IRQHandler [WEAK] + EXPORT I2S_IRQHandler [WEAK] + EXPORT AES_IRQHandler [WEAK] + EXPORT USB_IRQHandler [WEAK] + EXPORT PDMA_CH0_1_IRQHandler [WEAK] + EXPORT PDMA_CH2_5_IRQHandler [WEAK] + +LVD_BOD_IRQHandler +RTC_IRQHandler +FLASH_IRQHandler +EVWUP_IRQHandler +EXTI0_1_IRQHandler +EXTI2_3_IRQHandler +EXTI4_15_IRQHandler +COMP_IRQHandler +COMP_DAC_IRQHandler +ADC_IRQHandler +MCTM0_IRQHandler +GPTM0_IRQHandler +SCTM0_IRQHandler +SCTM1_IRQHandler +PWM0_IRQHandler +PWM1_IRQHandler +BFTM0_IRQHandler +BFTM1_IRQHandler +I2C0_IRQHandler +I2C1_IRQHandler +SPI0_IRQHandler +SPI1_IRQHandler +QSPI_IRQHandler +USART0_IRQHandler +USART1_IRQHandler +UART0_IRQHandler +UART1_IRQHandler +UART0_UART2_IRQHandler +UART1_UART3_IRQHandler +SCI_IRQHandler +I2S_IRQHandler +AES_IRQHandler +USB_IRQHandler +PDMA_CH0_1_IRQHandler +PDMA_CH2_5_IRQHandler + B . + ENDP + + ALIGN + +;******************************************************************************* +; User Stack and Heap initialization +;******************************************************************************* + IF :DEF:__MICROLIB + + EXPORT __HT_check_heap + EXPORT __HT_check_sp + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, = (Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + + ENDIF + + END diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f52357_67.s b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f52357_67.s new file mode 100644 index 0000000000..4533138d12 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f52357_67.s @@ -0,0 +1,403 @@ +;/*---------------------------------------------------------------------------------------------------------*/ +;/* Holtek Semiconductor Inc. */ +;/* */ +;/* Copyright (C) Holtek Semiconductor Inc. */ +;/* All rights reserved. */ +;/* */ +;/*----------------------------------------------------------------------------------------------------------- +; File Name : startup_ht32f5xxxx_03.s +; Version : $Rev:: 6877 $ +; Date : $Date:: 2023-05-04 #$ +; Description : Startup code. +;-----------------------------------------------------------------------------------------------------------*/ + +; Supported Device +; ======================================== +; HT32F0008 +; HT32F52142 +; HT32F52344, HT32F52354 +; HT32F52357, HT32F52367 +; HT50F3200T + +;/* <<< Use Configuration Wizard in Context Menu >>> */ + +;// HT32 Device +;// Select HT32 Device for the assembly setting. +;// Notice that the project's Asm Define has the higher priority. +;// <0=> By Project Asm Define +;// <6=> HT32F0008 +;// <6=> HT32F52142 +;// <9=> HT32F52344/54 +;// <11=> HT32F52357/67 +;// <11=> HT50F3200T +USE_HT32_CHIP_SET EQU 11 ; Notice that the project's Asm Define has the higher priority. + +_HT32FWID EQU 0xFFFFFFFF +;_HT32FWID EQU 0x00000008 +;_HT32FWID EQU 0x00052142 +;_HT32FWID EQU 0x00052344 +;_HT32FWID EQU 0x00052354 +;_HT32FWID EQU 0x00052357 +;_HT32FWID EQU 0x00052367 +;_HT32FWID EQU 0x0003200F + +HT32F0008 EQU 6 +HT32F52142 EQU 6 +HT32F52344_54 EQU 9 +HT32F52357_67 EQU 11 +HT50F3200T EQU 11 + + IF USE_HT32_CHIP_SET=0 + ; Use project's Asm Define setting (default) + ELSE + IF :DEF:USE_HT32_CHIP + ; Use project's Asm Define setting (higher priority than the "USE_HT32_CHIP_SET") + ELSE + ; Use "USE_HT32_CHIP_SET" in the "startup_ht32xxxxx_xx.s" file +USE_HT32_CHIP EQU USE_HT32_CHIP_SET + ENDIF + ENDIF + +; Amount of memory (in bytes) allocated for Stack and Heap +; Tailor those values to your application needs +;// Stack Size (in Bytes, must 8 byte aligned) <0-16384:8> +Stack_Size EQU 512 + + AREA STACK, NOINIT, READWRITE, ALIGN = 3 +__HT_check_sp +Stack_Mem SPACE Stack_Size +__initial_sp + +;// Heap Size (in Bytes) <0-16384:8> +Heap_Size EQU 0 + + AREA HEAP, NOINIT, READWRITE, ALIGN = 3 +__HT_check_heap +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + PRESERVE8 + THUMB + +;******************************************************************************* +; Fill-up the Vector Table entries with the exceptions ISR address +;******************************************************************************* + AREA RESET, CODE, READONLY + EXPORT __Vectors +_RESERVED EQU 0xFFFFFFFF +__Vectors + DCD __initial_sp ; ---, 00, 0x000, Top address of Stack + DCD Reset_Handler ; ---, 01, 0x004, Reset Handler + DCD NMI_Handler ; -14, 02, 0x008, NMI Handler + DCD HardFault_Handler ; -13, 03, 0x00C, Hard Fault Handler + DCD _RESERVED ; ---, 04, 0x010, Reserved + DCD _RESERVED ; ---, 05, 0x014, Reserved + DCD _RESERVED ; ---, 06, 0x018, Reserved + DCD _RESERVED ; ---, 07, 0x01C, Reserved + DCD _HT32FWID ; ---, 08, 0x020, Reserved + DCD _RESERVED ; ---, 09, 0x024, Reserved + DCD _RESERVED ; ---, 10, 0x028, Reserved + DCD SVC_Handler ; -05, 11, 0x02C, SVC Handler + DCD _RESERVED ; ---, 12, 0x030, Reserved + DCD _RESERVED ; ---, 13, 0x034, Reserved + DCD PendSV_Handler ; -02, 14, 0x038, PendSV Handler + DCD SysTick_Handler ; -01, 15, 0x03C, SysTick Handler + + ; External Interrupt Handler + DCD LVD_BOD_IRQHandler ; 00, 16, 0x040, + DCD RTC_IRQHandler ; 01, 17, 0x044, + DCD FLASH_IRQHandler ; 02, 18, 0x048, + DCD EVWUP_IRQHandler ; 03, 19, 0x04C, + DCD EXTI0_1_IRQHandler ; 04, 20, 0x050, + DCD EXTI2_3_IRQHandler ; 05, 21, 0x054, + DCD EXTI4_15_IRQHandler ; 06, 22, 0x058, + IF (USE_HT32_CHIP=HT32F0008) + DCD _RESERVED ; 07, 23, 0x05C, + ENDIF + IF (USE_HT32_CHIP=HT32F52344_54) + DCD COMP_IRQHandler ; 07, 23, 0x05C, + ENDIF + IF (USE_HT32_CHIP=HT32F52357_67) + DCD COMP_DAC_IRQHandler ; 07, 23, 0x05C, + ENDIF + IF (USE_HT32_CHIP=HT32F0008) + DCD _RESERVED ; 08, 24, 0x060, + ELSE + DCD ADC_IRQHandler ; 08, 24, 0x060, + ENDIF + IF (USE_HT32_CHIP=HT32F52357_67) + DCD AES_IRQHandler ; 09, 25, 0x064, + ELSE + DCD _RESERVED ; 09, 25, 0x064, + ENDIF + IF (USE_HT32_CHIP=HT32F0008) + DCD _RESERVED ; 10, 26, 0x068, + ELSE + DCD MCTM0_IRQHandler ; 10, 26, 0x068, + ENDIF + IF (USE_HT32_CHIP=HT32F52357_67) + DCD QSPI_IRQHandler ; 11, 27, 0x06C, + ELSE + DCD _RESERVED ; 11, 27, 0x06C, + ENDIF + DCD GPTM0_IRQHandler ; 12, 28, 0x070, + IF (USE_HT32_CHIP=HT32F0008) + DCD _RESERVED ; 13, 29, 0x074, + DCD _RESERVED ; 14, 30, 0x078, + ELSE + DCD SCTM0_IRQHandler ; 13, 29, 0x074, + DCD SCTM1_IRQHandler ; 14, 30, 0x078, + ENDIF + IF (USE_HT32_CHIP=HT32F0008) || (USE_HT32_CHIP=HT32F52357_67) + DCD PWM0_IRQHandler ; 15, 31, 0x07C, + DCD PWM1_IRQHandler ; 16, 32, 0x080, + ENDIF + IF (USE_HT32_CHIP=HT32F52344_54) + DCD _RESERVED ; 15, 31, 0x07C, + DCD _RESERVED ; 16, 32, 0x080, + ENDIF + DCD BFTM0_IRQHandler ; 17, 33, 0x084, + DCD BFTM1_IRQHandler ; 18, 34, 0x088, + DCD I2C0_IRQHandler ; 19, 35, 0x08C, + IF (USE_HT32_CHIP=HT32F0008) || (USE_HT32_CHIP=HT32F52344_54) + DCD _RESERVED ; 20, 36, 0x090, + ELSE + DCD I2C1_IRQHandler ; 20, 36, 0x090, + ENDIF + DCD SPI0_IRQHandler ; 21, 37, 0x094, + IF (USE_HT32_CHIP=HT32F0008) + DCD _RESERVED ; 22, 38, 0x098, + ELSE + DCD SPI1_IRQHandler ; 22, 38, 0x098, + ENDIF + IF (USE_HT32_CHIP=HT32F52344_54) + DCD _RESERVED ; 23, 39, 0x09C, + ELSE + DCD USART0_IRQHandler ; 23, 39, 0x09C, + ENDIF + IF (USE_HT32_CHIP=HT32F0008) + DCD _RESERVED ; 24, 40, 0x0A0, + DCD UART0_IRQHandler ; 25, 41, 0x0A4, + DCD _RESERVED ; 26, 42, 0x0A8, + ENDIF + IF (USE_HT32_CHIP=HT32F52344_54) + DCD _RESERVED ; 24, 40, 0x0A0, + DCD UART0_IRQHandler ; 25, 41, 0x0A4, + DCD UART1_IRQHandler ; 26, 42, 0x0A8, + ENDIF + IF (USE_HT32_CHIP=HT32F52357_67) + DCD USART1_IRQHandler ; 24, 40, 0x0A0, + DCD UART0_UART2_IRQHandler ; 25, 41, 0x0A4, + DCD UART1_UART3_IRQHandler ; 26, 42, 0x0A8, + ENDIF + IF (USE_HT32_CHIP=HT32F52357_67) + DCD SCI_IRQHandler ; 27, 43, 0xAC, + ELSE + DCD _RESERVED ; 27, 43, 0xAC, + ENDIF + IF (USE_HT32_CHIP=HT32F0008) + DCD AES_IRQHandler ; 28, 44, 0x0B0, + ENDIF + IF (USE_HT32_CHIP=HT32F52344_54) + DCD _RESERVED ; 28, 44, 0x0B0, + ENDIF + IF (USE_HT32_CHIP=HT32F52357_67) + DCD I2S_IRQHandler ; 28, 44, 0x0B0, + ENDIF + DCD USB_IRQHandler ; 29, 45, 0x0B4, + DCD PDMA_CH0_1_IRQHandler ; 30, 46, 0x0B8, + DCD PDMA_CH2_5_IRQHandler ; 31, 47, 0x0BC, + +; Reset handler routine +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + LDR R0, =BootProcess + BLX R0 + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +BootProcess PROC + LDR R0, =0x40080300 + LDR R1,[R0, #0x10] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x14] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x18] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x1C] + CMP R1, #0 + BEQ BP2 +BP1 LDR R0, =0x40080180 + LDR R1,[R0, #0xC] + LSLS R1, R1, #4 + LSRS R1, R1, #20 + CMP R1, #0 + BEQ BP3 + CMP R1, #5 + BEQ BP3 + CMP R1, #6 + BEQ BP3 +BP2 DSB + LDR R0, =0x20000000 + LDR R1, =0x05fa0004 + STR R1, [R0] + LDR R1, =0xe000ed00 + LDR R0, =0x05fa0004 + STR R0, [R1, #0xC] + DSB + B . +BP3 LDR R0, =0x20000000 + LDR R1, [R0] + LDR R0, =0x05fa0004 + CMP R0, R1 + BEQ BP4 + BX LR +BP4 LDR R0, =0x40088100 + LDR R1, =0x00000001 + STR R1, [R0] + LDR R0, =0x20000000 + LDR R1, =0x0 + STR R1, [R0] + BX LR + ENDP + +; Dummy Exception Handlers +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP + +HardFault_Handler PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP + +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP + +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP + +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + EXPORT LVD_BOD_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT EVWUP_IRQHandler [WEAK] + EXPORT EXTI0_1_IRQHandler [WEAK] + EXPORT EXTI2_3_IRQHandler [WEAK] + EXPORT EXTI4_15_IRQHandler [WEAK] + EXPORT COMP_IRQHandler [WEAK] + EXPORT COMP_DAC_IRQHandler [WEAK] + EXPORT ADC_IRQHandler [WEAK] + EXPORT MCTM0_IRQHandler [WEAK] + EXPORT GPTM0_IRQHandler [WEAK] + EXPORT SCTM0_IRQHandler [WEAK] + EXPORT SCTM1_IRQHandler [WEAK] + EXPORT PWM0_IRQHandler [WEAK] + EXPORT PWM1_IRQHandler [WEAK] + EXPORT BFTM0_IRQHandler [WEAK] + EXPORT BFTM1_IRQHandler [WEAK] + EXPORT I2C0_IRQHandler [WEAK] + EXPORT I2C1_IRQHandler [WEAK] + EXPORT SPI0_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT QSPI_IRQHandler [WEAK] + EXPORT USART0_IRQHandler [WEAK] + EXPORT USART1_IRQHandler [WEAK] + EXPORT UART0_IRQHandler [WEAK] + EXPORT UART1_IRQHandler [WEAK] + EXPORT UART0_UART2_IRQHandler [WEAK] + EXPORT UART1_UART3_IRQHandler [WEAK] + EXPORT SCI_IRQHandler [WEAK] + EXPORT I2S_IRQHandler [WEAK] + EXPORT AES_IRQHandler [WEAK] + EXPORT USB_IRQHandler [WEAK] + EXPORT PDMA_CH0_1_IRQHandler [WEAK] + EXPORT PDMA_CH2_5_IRQHandler [WEAK] + +LVD_BOD_IRQHandler +RTC_IRQHandler +FLASH_IRQHandler +EVWUP_IRQHandler +EXTI0_1_IRQHandler +EXTI2_3_IRQHandler +EXTI4_15_IRQHandler +COMP_IRQHandler +COMP_DAC_IRQHandler +ADC_IRQHandler +MCTM0_IRQHandler +GPTM0_IRQHandler +SCTM0_IRQHandler +SCTM1_IRQHandler +PWM0_IRQHandler +PWM1_IRQHandler +BFTM0_IRQHandler +BFTM1_IRQHandler +I2C0_IRQHandler +I2C1_IRQHandler +SPI0_IRQHandler +SPI1_IRQHandler +QSPI_IRQHandler +USART0_IRQHandler +USART1_IRQHandler +UART0_IRQHandler +UART1_IRQHandler +UART0_UART2_IRQHandler +UART1_UART3_IRQHandler +SCI_IRQHandler +I2S_IRQHandler +AES_IRQHandler +USB_IRQHandler +PDMA_CH0_1_IRQHandler +PDMA_CH2_5_IRQHandler + B . + ENDP + + ALIGN + +;******************************************************************************* +; User Stack and Heap initialization +;******************************************************************************* + IF :DEF:__MICROLIB + + EXPORT __HT_check_heap + EXPORT __HT_check_sp + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, = (Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + + ENDIF + + END diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f53231_41.s b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f53231_41.s new file mode 100644 index 0000000000..e1bc80febe --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f53231_41.s @@ -0,0 +1,266 @@ +;/*---------------------------------------------------------------------------------------------------------*/ +;/* Holtek Semiconductor Inc. */ +;/* */ +;/* Copyright (C) Holtek Semiconductor Inc. */ +;/* All rights reserved. */ +;/* */ +;/*----------------------------------------------------------------------------------------------------------- +; File Name : startup_ht32f5xxxx_15.s +; Version : $Rev:: 6874 $ +; Date : $Date:: 2023-05-03 #$ +; Description : Startup code. +;-----------------------------------------------------------------------------------------------------------*/ + +; Supported Device +; ======================================== +; HT32F53242, HT32F53252 +; HT32F53231, HT32F53241 + +;/* <<< Use Configuration Wizard in Context Menu >>> */ + +;// HT32 Device +;// Select HT32 Device for the assembly setting. +;// Notice that the project's Asm Define has the higher priority. +;// <0=> By Project Asm Define +;// <28=> HT32F53242/52 +;// <29=> HT32F53231/41 +USE_HT32_CHIP_SET EQU 29 ; Notice that the project's Asm Define has the higher priority. + +_HT32FWID EQU 0xFFFFFFFF +;_HT32FWID EQU 0x00053242 +;_HT32FWID EQU 0x00053252 +;_HT32FWID EQU 0x00053231 +;_HT32FWID EQU 0x00053241 + +HT32F53242_52 EQU 28 +HT32F53231_41 EQU 29 + + IF USE_HT32_CHIP_SET=0 + ; Use project's Asm Define setting (default) + ELSE + IF :DEF:USE_HT32_CHIP + ; Use project's Asm Define setting (higher priority than the "USE_HT32_CHIP_SET") + ELSE + ; Use "USE_HT32_CHIP_SET" in the "startup_ht32xxxxx_xx.s" file +USE_HT32_CHIP EQU USE_HT32_CHIP_SET + ENDIF + ENDIF + +; Amount of memory (in bytes) allocated for Stack and Heap +; Tailor those values to your application needs +;// Stack Size (in Bytes, must 8 byte aligned) <0-16384:8> +Stack_Size EQU 512 + + AREA STACK, NOINIT, READWRITE, ALIGN = 3 +__HT_check_sp +Stack_Mem SPACE Stack_Size +__initial_sp + +;// Heap Size (in Bytes) <0-16384:8> +Heap_Size EQU 0 + + AREA HEAP, NOINIT, READWRITE, ALIGN = 3 +__HT_check_heap +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + PRESERVE8 + THUMB + +;******************************************************************************* +; Fill-up the Vector Table entries with the exceptions ISR address +;******************************************************************************* + AREA RESET, CODE, READONLY + EXPORT __Vectors +_RESERVED EQU 0xFFFFFFFF +__Vectors + DCD __initial_sp ; ---, 00, 0x000, Top address of Stack + DCD Reset_Handler ; ---, 01, 0x004, Reset Handler + DCD NMI_Handler ; -14, 02, 0x008, NMI Handler + DCD HardFault_Handler ; -13, 03, 0x00C, Hard Fault Handler + DCD _RESERVED ; ---, 04, 0x010, Reserved + DCD _RESERVED ; ---, 05, 0x014, Reserved + DCD _RESERVED ; ---, 06, 0x018, Reserved + DCD _RESERVED ; ---, 07, 0x01C, Reserved + DCD _HT32FWID ; ---, 08, 0x020, Reserved + DCD _RESERVED ; ---, 09, 0x024, Reserved + DCD _RESERVED ; ---, 10, 0x028, Reserved + DCD SVC_Handler ; -05, 11, 0x02C, SVC Handler + DCD _RESERVED ; ---, 12, 0x030, Reserved + DCD _RESERVED ; ---, 13, 0x034, Reserved + DCD PendSV_Handler ; -02, 14, 0x038, PendSV Handler + DCD SysTick_Handler ; -01, 15, 0x03C, SysTick Handler + + ; External Interrupt Handler + DCD LVD_BOD_IRQHandler ; 00, 16, 0x040, + DCD RTC_IRQHandler ; 01, 17, 0x044, + DCD FLASH_IRQHandler ; 02, 18, 0x048, + DCD EVWUP_IRQHandler ; 03, 19, 0x04C, + DCD EXTI0_1_IRQHandler ; 04, 20, 0x050, + DCD EXTI2_3_IRQHandler ; 05, 21, 0x054, + DCD EXTI4_15_IRQHandler ; 06, 22, 0x058, + IF (USE_HT32_CHIP=HT32F53242_52) + DCD COMP_IRQHandler ; 07, 23, 0x05C, + ELSE + DCD _RESERVED ; 07, 23, 0x05C, + ENDIF + DCD ADC_IRQHandler ; 08, 24, 0x060, + DCD _RESERVED ; 09, 25, 0x064, + DCD MCTM0_IRQHandler ; 10, 26, 0x068, + DCD _RESERVED ; 11, 27, 0x06C, + DCD GPTM0_IRQHandler ; 12, 28, 0x070, + DCD _RESERVED ; 13, 29, 0x074, + DCD _RESERVED ; 14, 30, 0x078, + DCD PWM0_IRQHandler ; 15, 31, 0x07C, + IF (USE_HT32_CHIP=HT32F53242_52) + DCD PWM1_IRQHandler ; 16, 32, 0x080, + ELSE + DCD _RESERVED ; 16, 32, 0x080, + ENDIF + DCD BFTM0_IRQHandler ; 17, 33, 0x084, + DCD BFTM1_IRQHandler ; 18, 34, 0x088, + DCD I2C0_IRQHandler ; 19, 35, 0x08C, + DCD I2C1_IRQHandler ; 20, 36, 0x090, + DCD SPI0_IRQHandler ; 21, 37, 0x094, + DCD SPI1_IRQHandler ; 22, 38, 0x098, + DCD USART0_IRQHandler ; 23, 39, 0x09C, + IF (USE_HT32_CHIP=HT32F53242_52) + DCD USART1_IRQHandler ; 24, 40, 0x0A0, + ELSE + DCD _RESERVED ; 24, 40, 0x0A0, + ENDIF + DCD UART0_IRQHandler ; 25, 41, 0x0A4, + DCD UART1_IRQHandler ; 26, 42, 0x0A8, + DCD CAN0_IRQHandler ; 27, 43, 0x0AC, + DCD _RESERVED ; 28, 44, 0x0B0, + DCD LEDC_IRQHandler ; 29, 45, 0x0B4, + DCD PDMA_CH0_1_IRQHandler ; 30, 46, 0x0B8, + DCD PDMA_CH2_5_IRQHandler ; 31, 47, 0x0BC, + +; Reset handler routine +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception Handlers +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP + +HardFault_Handler PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP + +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP + +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP + +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + EXPORT LVD_BOD_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT EVWUP_IRQHandler [WEAK] + EXPORT EXTI0_1_IRQHandler [WEAK] + EXPORT EXTI2_3_IRQHandler [WEAK] + EXPORT EXTI4_15_IRQHandler [WEAK] + EXPORT COMP_IRQHandler [WEAK] + EXPORT ADC_IRQHandler [WEAK] + EXPORT MCTM0_IRQHandler [WEAK] + EXPORT GPTM0_IRQHandler [WEAK] + EXPORT PWM0_IRQHandler [WEAK] + EXPORT PWM1_IRQHandler [WEAK] + EXPORT BFTM0_IRQHandler [WEAK] + EXPORT BFTM1_IRQHandler [WEAK] + EXPORT I2C0_IRQHandler [WEAK] + EXPORT I2C1_IRQHandler [WEAK] + EXPORT SPI0_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT USART0_IRQHandler [WEAK] + EXPORT USART1_IRQHandler [WEAK] + EXPORT UART0_IRQHandler [WEAK] + EXPORT UART1_IRQHandler [WEAK] + EXPORT CAN0_IRQHandler [WEAK] + EXPORT LEDC_IRQHandler [WEAK] + EXPORT PDMA_CH0_1_IRQHandler [WEAK] + EXPORT PDMA_CH2_5_IRQHandler [WEAK] + +LVD_BOD_IRQHandler +RTC_IRQHandler +FLASH_IRQHandler +EVWUP_IRQHandler +EXTI0_1_IRQHandler +EXTI2_3_IRQHandler +EXTI4_15_IRQHandler +COMP_IRQHandler +ADC_IRQHandler +MCTM0_IRQHandler +GPTM0_IRQHandler +PWM0_IRQHandler +PWM1_IRQHandler +BFTM0_IRQHandler +BFTM1_IRQHandler +I2C0_IRQHandler +I2C1_IRQHandler +SPI0_IRQHandler +SPI1_IRQHandler +USART0_IRQHandler +USART1_IRQHandler +UART0_IRQHandler +UART1_IRQHandler +CAN0_IRQHandler +LEDC_IRQHandler +PDMA_CH0_1_IRQHandler +PDMA_CH2_5_IRQHandler + B . + ENDP + + ALIGN + +;******************************************************************************* +; User Stack and Heap initialization +;******************************************************************************* + IF :DEF:__MICROLIB + + EXPORT __HT_check_heap + EXPORT __HT_check_sp + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, = (Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + + ENDIF + + END diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f53242_52.s b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f53242_52.s new file mode 100644 index 0000000000..f4dbd9cf62 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f53242_52.s @@ -0,0 +1,266 @@ +;/*---------------------------------------------------------------------------------------------------------*/ +;/* Holtek Semiconductor Inc. */ +;/* */ +;/* Copyright (C) Holtek Semiconductor Inc. */ +;/* All rights reserved. */ +;/* */ +;/*----------------------------------------------------------------------------------------------------------- +; File Name : startup_ht32f5xxxx_15.s +; Version : $Rev:: 6874 $ +; Date : $Date:: 2023-05-03 #$ +; Description : Startup code. +;-----------------------------------------------------------------------------------------------------------*/ + +; Supported Device +; ======================================== +; HT32F53242, HT32F53252 +; HT32F53231, HT32F53241 + +;/* <<< Use Configuration Wizard in Context Menu >>> */ + +;// HT32 Device +;// Select HT32 Device for the assembly setting. +;// Notice that the project's Asm Define has the higher priority. +;// <0=> By Project Asm Define +;// <28=> HT32F53242/52 +;// <29=> HT32F53231/41 +USE_HT32_CHIP_SET EQU 28 ; Notice that the project's Asm Define has the higher priority. + +_HT32FWID EQU 0xFFFFFFFF +;_HT32FWID EQU 0x00053242 +;_HT32FWID EQU 0x00053252 +;_HT32FWID EQU 0x00053231 +;_HT32FWID EQU 0x00053241 + +HT32F53242_52 EQU 28 +HT32F53231_41 EQU 29 + + IF USE_HT32_CHIP_SET=0 + ; Use project's Asm Define setting (default) + ELSE + IF :DEF:USE_HT32_CHIP + ; Use project's Asm Define setting (higher priority than the "USE_HT32_CHIP_SET") + ELSE + ; Use "USE_HT32_CHIP_SET" in the "startup_ht32xxxxx_xx.s" file +USE_HT32_CHIP EQU USE_HT32_CHIP_SET + ENDIF + ENDIF + +; Amount of memory (in bytes) allocated for Stack and Heap +; Tailor those values to your application needs +;// Stack Size (in Bytes, must 8 byte aligned) <0-16384:8> +Stack_Size EQU 512 + + AREA STACK, NOINIT, READWRITE, ALIGN = 3 +__HT_check_sp +Stack_Mem SPACE Stack_Size +__initial_sp + +;// Heap Size (in Bytes) <0-16384:8> +Heap_Size EQU 0 + + AREA HEAP, NOINIT, READWRITE, ALIGN = 3 +__HT_check_heap +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + PRESERVE8 + THUMB + +;******************************************************************************* +; Fill-up the Vector Table entries with the exceptions ISR address +;******************************************************************************* + AREA RESET, CODE, READONLY + EXPORT __Vectors +_RESERVED EQU 0xFFFFFFFF +__Vectors + DCD __initial_sp ; ---, 00, 0x000, Top address of Stack + DCD Reset_Handler ; ---, 01, 0x004, Reset Handler + DCD NMI_Handler ; -14, 02, 0x008, NMI Handler + DCD HardFault_Handler ; -13, 03, 0x00C, Hard Fault Handler + DCD _RESERVED ; ---, 04, 0x010, Reserved + DCD _RESERVED ; ---, 05, 0x014, Reserved + DCD _RESERVED ; ---, 06, 0x018, Reserved + DCD _RESERVED ; ---, 07, 0x01C, Reserved + DCD _HT32FWID ; ---, 08, 0x020, Reserved + DCD _RESERVED ; ---, 09, 0x024, Reserved + DCD _RESERVED ; ---, 10, 0x028, Reserved + DCD SVC_Handler ; -05, 11, 0x02C, SVC Handler + DCD _RESERVED ; ---, 12, 0x030, Reserved + DCD _RESERVED ; ---, 13, 0x034, Reserved + DCD PendSV_Handler ; -02, 14, 0x038, PendSV Handler + DCD SysTick_Handler ; -01, 15, 0x03C, SysTick Handler + + ; External Interrupt Handler + DCD LVD_BOD_IRQHandler ; 00, 16, 0x040, + DCD RTC_IRQHandler ; 01, 17, 0x044, + DCD FLASH_IRQHandler ; 02, 18, 0x048, + DCD EVWUP_IRQHandler ; 03, 19, 0x04C, + DCD EXTI0_1_IRQHandler ; 04, 20, 0x050, + DCD EXTI2_3_IRQHandler ; 05, 21, 0x054, + DCD EXTI4_15_IRQHandler ; 06, 22, 0x058, + IF (USE_HT32_CHIP=HT32F53242_52) + DCD COMP_IRQHandler ; 07, 23, 0x05C, + ELSE + DCD _RESERVED ; 07, 23, 0x05C, + ENDIF + DCD ADC_IRQHandler ; 08, 24, 0x060, + DCD _RESERVED ; 09, 25, 0x064, + DCD MCTM0_IRQHandler ; 10, 26, 0x068, + DCD _RESERVED ; 11, 27, 0x06C, + DCD GPTM0_IRQHandler ; 12, 28, 0x070, + DCD _RESERVED ; 13, 29, 0x074, + DCD _RESERVED ; 14, 30, 0x078, + DCD PWM0_IRQHandler ; 15, 31, 0x07C, + IF (USE_HT32_CHIP=HT32F53242_52) + DCD PWM1_IRQHandler ; 16, 32, 0x080, + ELSE + DCD _RESERVED ; 16, 32, 0x080, + ENDIF + DCD BFTM0_IRQHandler ; 17, 33, 0x084, + DCD BFTM1_IRQHandler ; 18, 34, 0x088, + DCD I2C0_IRQHandler ; 19, 35, 0x08C, + DCD I2C1_IRQHandler ; 20, 36, 0x090, + DCD SPI0_IRQHandler ; 21, 37, 0x094, + DCD SPI1_IRQHandler ; 22, 38, 0x098, + DCD USART0_IRQHandler ; 23, 39, 0x09C, + IF (USE_HT32_CHIP=HT32F53242_52) + DCD USART1_IRQHandler ; 24, 40, 0x0A0, + ELSE + DCD _RESERVED ; 24, 40, 0x0A0, + ENDIF + DCD UART0_IRQHandler ; 25, 41, 0x0A4, + DCD UART1_IRQHandler ; 26, 42, 0x0A8, + DCD CAN0_IRQHandler ; 27, 43, 0x0AC, + DCD _RESERVED ; 28, 44, 0x0B0, + DCD LEDC_IRQHandler ; 29, 45, 0x0B4, + DCD PDMA_CH0_1_IRQHandler ; 30, 46, 0x0B8, + DCD PDMA_CH2_5_IRQHandler ; 31, 47, 0x0BC, + +; Reset handler routine +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception Handlers +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP + +HardFault_Handler PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP + +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP + +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP + +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + EXPORT LVD_BOD_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT EVWUP_IRQHandler [WEAK] + EXPORT EXTI0_1_IRQHandler [WEAK] + EXPORT EXTI2_3_IRQHandler [WEAK] + EXPORT EXTI4_15_IRQHandler [WEAK] + EXPORT COMP_IRQHandler [WEAK] + EXPORT ADC_IRQHandler [WEAK] + EXPORT MCTM0_IRQHandler [WEAK] + EXPORT GPTM0_IRQHandler [WEAK] + EXPORT PWM0_IRQHandler [WEAK] + EXPORT PWM1_IRQHandler [WEAK] + EXPORT BFTM0_IRQHandler [WEAK] + EXPORT BFTM1_IRQHandler [WEAK] + EXPORT I2C0_IRQHandler [WEAK] + EXPORT I2C1_IRQHandler [WEAK] + EXPORT SPI0_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT USART0_IRQHandler [WEAK] + EXPORT USART1_IRQHandler [WEAK] + EXPORT UART0_IRQHandler [WEAK] + EXPORT UART1_IRQHandler [WEAK] + EXPORT CAN0_IRQHandler [WEAK] + EXPORT LEDC_IRQHandler [WEAK] + EXPORT PDMA_CH0_1_IRQHandler [WEAK] + EXPORT PDMA_CH2_5_IRQHandler [WEAK] + +LVD_BOD_IRQHandler +RTC_IRQHandler +FLASH_IRQHandler +EVWUP_IRQHandler +EXTI0_1_IRQHandler +EXTI2_3_IRQHandler +EXTI4_15_IRQHandler +COMP_IRQHandler +ADC_IRQHandler +MCTM0_IRQHandler +GPTM0_IRQHandler +PWM0_IRQHandler +PWM1_IRQHandler +BFTM0_IRQHandler +BFTM1_IRQHandler +I2C0_IRQHandler +I2C1_IRQHandler +SPI0_IRQHandler +SPI1_IRQHandler +USART0_IRQHandler +USART1_IRQHandler +UART0_IRQHandler +UART1_IRQHandler +CAN0_IRQHandler +LEDC_IRQHandler +PDMA_CH0_1_IRQHandler +PDMA_CH2_5_IRQHandler + B . + ENDP + + ALIGN + +;******************************************************************************* +; User Stack and Heap initialization +;******************************************************************************* + IF :DEF:__MICROLIB + + EXPORT __HT_check_heap + EXPORT __HT_check_sp + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, = (Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + + ENDIF + + END diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f54231_41.s b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f54231_41.s new file mode 100644 index 0000000000..5db17956e7 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f54231_41.s @@ -0,0 +1,343 @@ +;/*---------------------------------------------------------------------------------------------------------*/ +;/* Holtek Semiconductor Inc. */ +;/* */ +;/* Copyright (C) Holtek Semiconductor Inc. */ +;/* All rights reserved. */ +;/* */ +;/*----------------------------------------------------------------------------------------------------------- +; File Name : startup_ht32f5xxxx_09.s +; Version : $Rev:: 5740 $ +; Date : $Date:: 2022-02-17 #$ +; Description : Startup code. +;-----------------------------------------------------------------------------------------------------------*/ + +; Supported Device +; ======================================== +; HT32F54231, HT32F54241 +; HT32F54243, HT32F54253 + +;/* <<< Use Configuration Wizard in Context Menu >>> */ + +;// HT32 Device +;// Select HT32 Device for the assembly setting. +;// Notice that the project's Asm Define has the higher priority. +;// <0=> By Project Asm Define +;// <19=> HT32F54231/41 +;// <20=> HT32F54243/53 +USE_HT32_CHIP_SET EQU 19 ; Notice that the project's Asm Define has the higher priority. + +_HT32FWID EQU 0xFFFFFFFF +;_HT32FWID EQU 0x00054231 +;_HT32FWID EQU 0x00054241 +;_HT32FWID EQU 0x00054243 +;_HT32FWID EQU 0x00054253 + +HT32F54231_41 EQU 19 +HT32F54243_53 EQU 20 + + IF USE_HT32_CHIP_SET=0 + ; Use project's Asm Define setting (default) + ELSE + IF :DEF:USE_HT32_CHIP + ; Use project's Asm Define setting (higher priority than the "USE_HT32_CHIP_SET") + ELSE + ; Use "USE_HT32_CHIP_SET" in the "startup_ht32xxxxx_xx.s" file +USE_HT32_CHIP EQU USE_HT32_CHIP_SET + ENDIF + ENDIF + +; Amount of memory (in bytes) allocated for Stack and Heap +; Tailor those values to your application needs +;// Stack Size (in Bytes, must 8 byte aligned) <0-16384:8> +Stack_Size EQU 512 + + AREA STACK, NOINIT, READWRITE, ALIGN = 3 +__HT_check_sp +Stack_Mem SPACE Stack_Size +__initial_sp + +;// Heap Size (in Bytes) <0-16384:8> +Heap_Size EQU 0 + + AREA HEAP, NOINIT, READWRITE, ALIGN = 3 +__HT_check_heap +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + PRESERVE8 + THUMB + +;******************************************************************************* +; Fill-up the Vector Table entries with the exceptions ISR address +;******************************************************************************* + AREA RESET, CODE, READONLY + EXPORT __Vectors +_RESERVED EQU 0xFFFFFFFF +__Vectors + DCD __initial_sp ; ---, 00, 0x000, Top address of Stack + DCD Reset_Handler ; ---, 01, 0x004, Reset Handler + DCD NMI_Handler ; -14, 02, 0x008, NMI Handler + DCD HardFault_Handler ; -13, 03, 0x00C, Hard Fault Handler + DCD _RESERVED ; ---, 04, 0x010, Reserved + DCD _RESERVED ; ---, 05, 0x014, Reserved + DCD _RESERVED ; ---, 06, 0x018, Reserved + DCD _RESERVED ; ---, 07, 0x01C, Reserved + DCD _HT32FWID ; ---, 08, 0x020, Reserved + DCD _RESERVED ; ---, 09, 0x024, Reserved + DCD _RESERVED ; ---, 10, 0x028, Reserved + DCD SVC_Handler ; -05, 11, 0x02C, SVC Handler + DCD _RESERVED ; ---, 12, 0x030, Reserved + DCD _RESERVED ; ---, 13, 0x034, Reserved + DCD PendSV_Handler ; -02, 14, 0x038, PendSV Handler + DCD SysTick_Handler ; -01, 15, 0x03C, SysTick Handler + + ; External Interrupt Handler + DCD LVD_BOD_IRQHandler ; 00, 16, 0x040, + DCD RTC_IRQHandler ; 01, 17, 0x044, + DCD FLASH_IRQHandler ; 02, 18, 0x048, + DCD EVWUP_IRQHandler ; 03, 19, 0x04C, + DCD EXTI0_1_IRQHandler ; 04, 20, 0x050, + DCD EXTI2_3_IRQHandler ; 05, 21, 0x054, + DCD EXTI4_15_IRQHandler ; 06, 22, 0x058, + IF (USE_HT32_CHIP=HT32F54231_41) + DCD _RESERVED ; 07, 23, 0x05C, + ENDIF + IF (USE_HT32_CHIP=HT32F54243_53) + DCD COMP_IRQHandler ; 07, 23, 0x05C, + ENDIF + DCD ADC_IRQHandler ; 08, 24, 0x060, + IF (USE_HT32_CHIP=HT32F54231_41) + DCD _RESERVED ; 09, 25, 0x064, + ENDIF + IF (USE_HT32_CHIP=HT32F54243_53) + DCD I2C2_IRQHandler ; 09, 25, 0x064, + ENDIF + DCD MCTM0_IRQHandler ; 10, 26, 0x068, + DCD TKEY_IRQHandler ; 11, 27, 0x06C, + DCD GPTM0_IRQHandler ; 12, 28, 0x070, + DCD SCTM0_IRQHandler ; 13, 29, 0x074, + DCD SCTM1_IRQHandler ; 14, 30, 0x078, + IF (USE_HT32_CHIP=HT32F54231_41) + DCD _RESERVED ; 15, 31, 0x07C, + DCD _RESERVED ; 16, 32, 0x080, + ENDIF + IF (USE_HT32_CHIP=HT32F54243_53) + DCD SCTM2_IRQHandler ; 15, 31, 0x07C, + DCD SCTM3_IRQHandler ; 16, 32, 0x080, + ENDIF + DCD BFTM0_IRQHandler ; 17, 33, 0x084, + DCD BFTM1_IRQHandler ; 18, 34, 0x088, + DCD I2C0_IRQHandler ; 19, 35, 0x08C, + DCD I2C1_IRQHandler ; 20, 36, 0x090, + DCD SPI0_IRQHandler ; 21, 37, 0x094, + DCD SPI1_IRQHandler ; 22, 38, 0x098, + DCD USART0_IRQHandler ; 23, 39, 0x09C, + IF (USE_HT32_CHIP=HT32F54231_41) + DCD _RESERVED ; 24, 40, 0x0A0, + ENDIF + IF (USE_HT32_CHIP=HT32F54243_53) + DCD USART1_IRQHandler ; 24, 40, 0x0A0, + ENDIF + DCD UART0_IRQHandler ; 25, 41, 0x0A4, + DCD UART1_IRQHandler ; 26, 42, 0x0A8, + IF (USE_HT32_CHIP=HT32F54231_41) + DCD _RESERVED ; 27, 43, 0x0AC, + DCD _RESERVED ; 28, 44, 0x0B0, + ENDIF + IF (USE_HT32_CHIP=HT32F54243_53) + DCD UART2_IRQHandler ; 27, 43, 0x0AC, + DCD UART3_IRQHandler ; 28, 44, 0x0B0, + ENDIF + DCD LEDC_IRQHandler ; 29, 45, 0x0B4, + IF (USE_HT32_CHIP=HT32F54243_53) + DCD PDMA_CH0_1_IRQHandler ; 30, 46, 0x0B8, + DCD PDMA_CH2_5_IRQHandler ; 31, 47, 0x0BC, + ENDIF + +; Reset handler routine +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + LDR R0, =BootProcess + BLX R0 + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +BootProcess PROC + LDR R0, =0x40080300 + LDR R1,[R0, #0x10] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x14] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x18] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x1C] + CMP R1, #0 + BEQ BP2 +BP1 LDR R0, =0x40080180 + LDR R1,[R0, #0xC] + LSLS R1, R1, #4 + LSRS R1, R1, #20 + CMP R1, #0 + BEQ BP3 + CMP R1, #5 + BEQ BP3 + CMP R1, #6 + BEQ BP3 +BP2 DSB + LDR R0, =0x20000000 + LDR R1, =0x05fa0004 + STR R1, [R0] + LDR R1, =0xe000ed00 + LDR R0, =0x05fa0004 + STR R0, [R1, #0xC] + DSB + B . +BP3 LDR R0, =0x20000000 + LDR R1, [R0] + LDR R0, =0x05fa0004 + CMP R0, R1 + BEQ BP4 + BX LR +BP4 LDR R0, =0x40088100 + LDR R1, =0x00000001 + STR R1, [R0] + LDR R0, =0x20000000 + LDR R1, =0x0 + STR R1, [R0] + BX LR + ENDP + +; Dummy Exception Handlers +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP + +HardFault_Handler PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP + +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP + +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP + +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + EXPORT LVD_BOD_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT EVWUP_IRQHandler [WEAK] + EXPORT EXTI0_1_IRQHandler [WEAK] + EXPORT EXTI2_3_IRQHandler [WEAK] + EXPORT EXTI4_15_IRQHandler [WEAK] + EXPORT COMP_IRQHandler [WEAK] + EXPORT ADC_IRQHandler [WEAK] + EXPORT I2C2_IRQHandler [WEAK] + EXPORT MCTM0_IRQHandler [WEAK] + EXPORT TKEY_IRQHandler [WEAK] + EXPORT GPTM0_IRQHandler [WEAK] + EXPORT SCTM0_IRQHandler [WEAK] + EXPORT SCTM1_IRQHandler [WEAK] + EXPORT SCTM2_IRQHandler [WEAK] + EXPORT SCTM3_IRQHandler [WEAK] + EXPORT BFTM0_IRQHandler [WEAK] + EXPORT BFTM1_IRQHandler [WEAK] + EXPORT I2C0_IRQHandler [WEAK] + EXPORT I2C1_IRQHandler [WEAK] + EXPORT SPI0_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT USART0_IRQHandler [WEAK] + EXPORT USART1_IRQHandler [WEAK] + EXPORT UART0_IRQHandler [WEAK] + EXPORT UART1_IRQHandler [WEAK] + EXPORT UART2_IRQHandler [WEAK] + EXPORT UART3_IRQHandler [WEAK] + EXPORT LEDC_IRQHandler [WEAK] + EXPORT PDMA_CH0_1_IRQHandler [WEAK] + EXPORT PDMA_CH2_5_IRQHandler [WEAK] + +LVD_BOD_IRQHandler +RTC_IRQHandler +FLASH_IRQHandler +EVWUP_IRQHandler +EXTI0_1_IRQHandler +EXTI2_3_IRQHandler +EXTI4_15_IRQHandler +COMP_IRQHandler +ADC_IRQHandler +I2C2_IRQHandler +MCTM0_IRQHandler +TKEY_IRQHandler +GPTM0_IRQHandler +SCTM0_IRQHandler +SCTM1_IRQHandler +SCTM2_IRQHandler +SCTM3_IRQHandler +BFTM0_IRQHandler +BFTM1_IRQHandler +I2C0_IRQHandler +I2C1_IRQHandler +SPI0_IRQHandler +SPI1_IRQHandler +USART0_IRQHandler +USART1_IRQHandler +UART0_IRQHandler +UART1_IRQHandler +UART2_IRQHandler +UART3_IRQHandler +LEDC_IRQHandler +PDMA_CH0_1_IRQHandler +PDMA_CH2_5_IRQHandler + B . + ENDP + + ALIGN + +;******************************************************************************* +; User Stack and Heap initialization +;******************************************************************************* + IF :DEF:__MICROLIB + + EXPORT __HT_check_heap + EXPORT __HT_check_sp + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, = (Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + + ENDIF + + END diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f54243_53.s b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f54243_53.s new file mode 100644 index 0000000000..657d0d6523 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f54243_53.s @@ -0,0 +1,343 @@ +;/*---------------------------------------------------------------------------------------------------------*/ +;/* Holtek Semiconductor Inc. */ +;/* */ +;/* Copyright (C) Holtek Semiconductor Inc. */ +;/* All rights reserved. */ +;/* */ +;/*----------------------------------------------------------------------------------------------------------- +; File Name : startup_ht32f5xxxx_09.s +; Version : $Rev:: 5740 $ +; Date : $Date:: 2022-02-17 #$ +; Description : Startup code. +;-----------------------------------------------------------------------------------------------------------*/ + +; Supported Device +; ======================================== +; HT32F54231, HT32F54241 +; HT32F54243, HT32F54253 + +;/* <<< Use Configuration Wizard in Context Menu >>> */ + +;// HT32 Device +;// Select HT32 Device for the assembly setting. +;// Notice that the project's Asm Define has the higher priority. +;// <0=> By Project Asm Define +;// <19=> HT32F54231/41 +;// <20=> HT32F54243/53 +USE_HT32_CHIP_SET EQU 20 ; Notice that the project's Asm Define has the higher priority. + +_HT32FWID EQU 0xFFFFFFFF +;_HT32FWID EQU 0x00054231 +;_HT32FWID EQU 0x00054241 +;_HT32FWID EQU 0x00054243 +;_HT32FWID EQU 0x00054253 + +HT32F54231_41 EQU 19 +HT32F54243_53 EQU 20 + + IF USE_HT32_CHIP_SET=0 + ; Use project's Asm Define setting (default) + ELSE + IF :DEF:USE_HT32_CHIP + ; Use project's Asm Define setting (higher priority than the "USE_HT32_CHIP_SET") + ELSE + ; Use "USE_HT32_CHIP_SET" in the "startup_ht32xxxxx_xx.s" file +USE_HT32_CHIP EQU USE_HT32_CHIP_SET + ENDIF + ENDIF + +; Amount of memory (in bytes) allocated for Stack and Heap +; Tailor those values to your application needs +;// Stack Size (in Bytes, must 8 byte aligned) <0-16384:8> +Stack_Size EQU 512 + + AREA STACK, NOINIT, READWRITE, ALIGN = 3 +__HT_check_sp +Stack_Mem SPACE Stack_Size +__initial_sp + +;// Heap Size (in Bytes) <0-16384:8> +Heap_Size EQU 0 + + AREA HEAP, NOINIT, READWRITE, ALIGN = 3 +__HT_check_heap +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + PRESERVE8 + THUMB + +;******************************************************************************* +; Fill-up the Vector Table entries with the exceptions ISR address +;******************************************************************************* + AREA RESET, CODE, READONLY + EXPORT __Vectors +_RESERVED EQU 0xFFFFFFFF +__Vectors + DCD __initial_sp ; ---, 00, 0x000, Top address of Stack + DCD Reset_Handler ; ---, 01, 0x004, Reset Handler + DCD NMI_Handler ; -14, 02, 0x008, NMI Handler + DCD HardFault_Handler ; -13, 03, 0x00C, Hard Fault Handler + DCD _RESERVED ; ---, 04, 0x010, Reserved + DCD _RESERVED ; ---, 05, 0x014, Reserved + DCD _RESERVED ; ---, 06, 0x018, Reserved + DCD _RESERVED ; ---, 07, 0x01C, Reserved + DCD _HT32FWID ; ---, 08, 0x020, Reserved + DCD _RESERVED ; ---, 09, 0x024, Reserved + DCD _RESERVED ; ---, 10, 0x028, Reserved + DCD SVC_Handler ; -05, 11, 0x02C, SVC Handler + DCD _RESERVED ; ---, 12, 0x030, Reserved + DCD _RESERVED ; ---, 13, 0x034, Reserved + DCD PendSV_Handler ; -02, 14, 0x038, PendSV Handler + DCD SysTick_Handler ; -01, 15, 0x03C, SysTick Handler + + ; External Interrupt Handler + DCD LVD_BOD_IRQHandler ; 00, 16, 0x040, + DCD RTC_IRQHandler ; 01, 17, 0x044, + DCD FLASH_IRQHandler ; 02, 18, 0x048, + DCD EVWUP_IRQHandler ; 03, 19, 0x04C, + DCD EXTI0_1_IRQHandler ; 04, 20, 0x050, + DCD EXTI2_3_IRQHandler ; 05, 21, 0x054, + DCD EXTI4_15_IRQHandler ; 06, 22, 0x058, + IF (USE_HT32_CHIP=HT32F54231_41) + DCD _RESERVED ; 07, 23, 0x05C, + ENDIF + IF (USE_HT32_CHIP=HT32F54243_53) + DCD COMP_IRQHandler ; 07, 23, 0x05C, + ENDIF + DCD ADC_IRQHandler ; 08, 24, 0x060, + IF (USE_HT32_CHIP=HT32F54231_41) + DCD _RESERVED ; 09, 25, 0x064, + ENDIF + IF (USE_HT32_CHIP=HT32F54243_53) + DCD I2C2_IRQHandler ; 09, 25, 0x064, + ENDIF + DCD MCTM0_IRQHandler ; 10, 26, 0x068, + DCD TKEY_IRQHandler ; 11, 27, 0x06C, + DCD GPTM0_IRQHandler ; 12, 28, 0x070, + DCD SCTM0_IRQHandler ; 13, 29, 0x074, + DCD SCTM1_IRQHandler ; 14, 30, 0x078, + IF (USE_HT32_CHIP=HT32F54231_41) + DCD _RESERVED ; 15, 31, 0x07C, + DCD _RESERVED ; 16, 32, 0x080, + ENDIF + IF (USE_HT32_CHIP=HT32F54243_53) + DCD SCTM2_IRQHandler ; 15, 31, 0x07C, + DCD SCTM3_IRQHandler ; 16, 32, 0x080, + ENDIF + DCD BFTM0_IRQHandler ; 17, 33, 0x084, + DCD BFTM1_IRQHandler ; 18, 34, 0x088, + DCD I2C0_IRQHandler ; 19, 35, 0x08C, + DCD I2C1_IRQHandler ; 20, 36, 0x090, + DCD SPI0_IRQHandler ; 21, 37, 0x094, + DCD SPI1_IRQHandler ; 22, 38, 0x098, + DCD USART0_IRQHandler ; 23, 39, 0x09C, + IF (USE_HT32_CHIP=HT32F54231_41) + DCD _RESERVED ; 24, 40, 0x0A0, + ENDIF + IF (USE_HT32_CHIP=HT32F54243_53) + DCD USART1_IRQHandler ; 24, 40, 0x0A0, + ENDIF + DCD UART0_IRQHandler ; 25, 41, 0x0A4, + DCD UART1_IRQHandler ; 26, 42, 0x0A8, + IF (USE_HT32_CHIP=HT32F54231_41) + DCD _RESERVED ; 27, 43, 0x0AC, + DCD _RESERVED ; 28, 44, 0x0B0, + ENDIF + IF (USE_HT32_CHIP=HT32F54243_53) + DCD UART2_IRQHandler ; 27, 43, 0x0AC, + DCD UART3_IRQHandler ; 28, 44, 0x0B0, + ENDIF + DCD LEDC_IRQHandler ; 29, 45, 0x0B4, + IF (USE_HT32_CHIP=HT32F54243_53) + DCD PDMA_CH0_1_IRQHandler ; 30, 46, 0x0B8, + DCD PDMA_CH2_5_IRQHandler ; 31, 47, 0x0BC, + ENDIF + +; Reset handler routine +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + LDR R0, =BootProcess + BLX R0 + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +BootProcess PROC + LDR R0, =0x40080300 + LDR R1,[R0, #0x10] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x14] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x18] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x1C] + CMP R1, #0 + BEQ BP2 +BP1 LDR R0, =0x40080180 + LDR R1,[R0, #0xC] + LSLS R1, R1, #4 + LSRS R1, R1, #20 + CMP R1, #0 + BEQ BP3 + CMP R1, #5 + BEQ BP3 + CMP R1, #6 + BEQ BP3 +BP2 DSB + LDR R0, =0x20000000 + LDR R1, =0x05fa0004 + STR R1, [R0] + LDR R1, =0xe000ed00 + LDR R0, =0x05fa0004 + STR R0, [R1, #0xC] + DSB + B . +BP3 LDR R0, =0x20000000 + LDR R1, [R0] + LDR R0, =0x05fa0004 + CMP R0, R1 + BEQ BP4 + BX LR +BP4 LDR R0, =0x40088100 + LDR R1, =0x00000001 + STR R1, [R0] + LDR R0, =0x20000000 + LDR R1, =0x0 + STR R1, [R0] + BX LR + ENDP + +; Dummy Exception Handlers +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP + +HardFault_Handler PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP + +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP + +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP + +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + EXPORT LVD_BOD_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT EVWUP_IRQHandler [WEAK] + EXPORT EXTI0_1_IRQHandler [WEAK] + EXPORT EXTI2_3_IRQHandler [WEAK] + EXPORT EXTI4_15_IRQHandler [WEAK] + EXPORT COMP_IRQHandler [WEAK] + EXPORT ADC_IRQHandler [WEAK] + EXPORT I2C2_IRQHandler [WEAK] + EXPORT MCTM0_IRQHandler [WEAK] + EXPORT TKEY_IRQHandler [WEAK] + EXPORT GPTM0_IRQHandler [WEAK] + EXPORT SCTM0_IRQHandler [WEAK] + EXPORT SCTM1_IRQHandler [WEAK] + EXPORT SCTM2_IRQHandler [WEAK] + EXPORT SCTM3_IRQHandler [WEAK] + EXPORT BFTM0_IRQHandler [WEAK] + EXPORT BFTM1_IRQHandler [WEAK] + EXPORT I2C0_IRQHandler [WEAK] + EXPORT I2C1_IRQHandler [WEAK] + EXPORT SPI0_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT USART0_IRQHandler [WEAK] + EXPORT USART1_IRQHandler [WEAK] + EXPORT UART0_IRQHandler [WEAK] + EXPORT UART1_IRQHandler [WEAK] + EXPORT UART2_IRQHandler [WEAK] + EXPORT UART3_IRQHandler [WEAK] + EXPORT LEDC_IRQHandler [WEAK] + EXPORT PDMA_CH0_1_IRQHandler [WEAK] + EXPORT PDMA_CH2_5_IRQHandler [WEAK] + +LVD_BOD_IRQHandler +RTC_IRQHandler +FLASH_IRQHandler +EVWUP_IRQHandler +EXTI0_1_IRQHandler +EXTI2_3_IRQHandler +EXTI4_15_IRQHandler +COMP_IRQHandler +ADC_IRQHandler +I2C2_IRQHandler +MCTM0_IRQHandler +TKEY_IRQHandler +GPTM0_IRQHandler +SCTM0_IRQHandler +SCTM1_IRQHandler +SCTM2_IRQHandler +SCTM3_IRQHandler +BFTM0_IRQHandler +BFTM1_IRQHandler +I2C0_IRQHandler +I2C1_IRQHandler +SPI0_IRQHandler +SPI1_IRQHandler +USART0_IRQHandler +USART1_IRQHandler +UART0_IRQHandler +UART1_IRQHandler +UART2_IRQHandler +UART3_IRQHandler +LEDC_IRQHandler +PDMA_CH0_1_IRQHandler +PDMA_CH2_5_IRQHandler + B . + ENDP + + ALIGN + +;******************************************************************************* +; User Stack and Heap initialization +;******************************************************************************* + IF :DEF:__MICROLIB + + EXPORT __HT_check_heap + EXPORT __HT_check_sp + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, = (Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + + ENDIF + + END diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f57331_41.s b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f57331_41.s new file mode 100644 index 0000000000..cbaf7f3ee1 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f57331_41.s @@ -0,0 +1,350 @@ +;/*---------------------------------------------------------------------------------------------------------*/ +;/* Holtek Semiconductor Inc. */ +;/* */ +;/* Copyright (C) Holtek Semiconductor Inc. */ +;/* All rights reserved. */ +;/* */ +;/*----------------------------------------------------------------------------------------------------------- +; File Name : startup_ht32f5xxxx_05.s +; Version : $Rev:: 6993 $ +; Date : $Date:: 2023-06-26 #$ +; Description : Startup code. +;-----------------------------------------------------------------------------------------------------------*/ + +; Supported Device +; ======================================== +; HT32F57331, HT32F57341 +; HT32F57342, HT32F57352 +; HT32F59741 +; HT32F5828 +; HT32F67742 +; HT32F59746 + +;/* <<< Use Configuration Wizard in Context Menu >>> */ + +;// HT32 Device +;// Select HT32 Device for the assembly setting. +;// Notice that the project's Asm Define has the higher priority. +;// <0=> By Project Asm Define +;// <13=> HT32F57331/41 +;// <14=> HT32F57342/52 +;// <13=> HT32F59741 +;// <14=> HT32F5828 +;// <13=> HT32F67742 +;// <13=> HT32F59746 +USE_HT32_CHIP_SET EQU 13 ; Notice that the project's Asm Define has the higher priority. + +_HT32FWID EQU 0xFFFFFFFF +;_HT32FWID EQU 0x00057331 +;_HT32FWID EQU 0x00057341 +;_HT32FWID EQU 0x00057342 +;_HT32FWID EQU 0x00057352 +;_HT32FWID EQU 0x00059741 +;_HT32FWID EQU 0x00005828 +;_HT32FWID EQU 0x00067742 +;_HT32FWID EQU 0x00059746 + +HT32F57331_41 EQU 13 +HT32F57342_52 EQU 14 +HT32F59741 EQU 13 +HT32F5828 EQU 14 +HT32F67742 EQU 13 +HT32F59746 EQU 13 + + IF USE_HT32_CHIP_SET=0 + ; Use project's Asm Define setting (default) + ELSE + IF :DEF:USE_HT32_CHIP + ; Use project's Asm Define setting (higher priority than the "USE_HT32_CHIP_SET") + ELSE + ; Use "USE_HT32_CHIP_SET" in the "startup_ht32xxxxx_xx.s" file +USE_HT32_CHIP EQU USE_HT32_CHIP_SET + ENDIF + ENDIF + +; Amount of memory (in bytes) allocated for Stack and Heap +; Tailor those values to your application needs +;// Stack Size (in Bytes, must 8 byte aligned) <0-16384:8> +Stack_Size EQU 512 + + AREA STACK, NOINIT, READWRITE, ALIGN = 3 +__HT_check_sp +Stack_Mem SPACE Stack_Size +__initial_sp + +;// Heap Size (in Bytes) <0-16384:8> +Heap_Size EQU 0 + + AREA HEAP, NOINIT, READWRITE, ALIGN = 3 +__HT_check_heap +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + PRESERVE8 + THUMB + +;******************************************************************************* +; Fill-up the Vector Table entries with the exceptions ISR address +;******************************************************************************* + AREA RESET, CODE, READONLY + EXPORT __Vectors +_RESERVED EQU 0xFFFFFFFF +__Vectors + DCD __initial_sp ; ---, 00, 0x000, Top address of Stack + DCD Reset_Handler ; ---, 01, 0x004, Reset Handler + DCD NMI_Handler ; -14, 02, 0x008, NMI Handler + DCD HardFault_Handler ; -13, 03, 0x00C, Hard Fault Handler + DCD _RESERVED ; ---, 04, 0x010, Reserved + DCD _RESERVED ; ---, 05, 0x014, Reserved + DCD _RESERVED ; ---, 06, 0x018, Reserved + DCD _RESERVED ; ---, 07, 0x01C, Reserved + DCD _HT32FWID ; ---, 08, 0x020, Reserved + DCD _RESERVED ; ---, 09, 0x024, Reserved + DCD _RESERVED ; ---, 10, 0x028, Reserved + DCD SVC_Handler ; -05, 11, 0x02C, SVC Handler + DCD _RESERVED ; ---, 12, 0x030, Reserved + DCD _RESERVED ; ---, 13, 0x034, Reserved + DCD PendSV_Handler ; -02, 14, 0x038, PendSV Handler + DCD SysTick_Handler ; -01, 15, 0x03C, SysTick Handler + + ; External Interrupt Handler + DCD LVD_BOD_IRQHandler ; 00, 16, 0x040, + DCD RTC_IRQHandler ; 01, 17, 0x044, + DCD FLASH_IRQHandler ; 02, 18, 0x048, + DCD EVWUP_IRQHandler ; 03, 19, 0x04C, + DCD EXTI0_1_IRQHandler ; 04, 20, 0x050, + DCD EXTI2_3_IRQHandler ; 05, 21, 0x054, + DCD EXTI4_15_IRQHandler ; 06, 22, 0x058, + IF (USE_HT32_CHIP=HT32F57331_41) + DCD _RESERVED ; 07, 23, 0x05C, + ENDIF + IF (USE_HT32_CHIP=HT32F57342_52) + DCD COMP_DAC_IRQHandler ; 07, 23, 0x05C, + ENDIF + DCD ADC_IRQHandler ; 08, 24, 0x060, + IF (USE_HT32_CHIP=HT32F57331_41) + DCD _RESERVED ; 09, 25, 0x064, + ENDIF + IF (USE_HT32_CHIP=HT32F57342_52) + DCD AES_IRQHandler ; 09, 25, 0x064, + ENDIF + DCD _RESERVED ; 10, 26, 0x068, + DCD LCD_IRQHandler ; 11, 27, 0x06C, + DCD GPTM0_IRQHandler ; 12, 28, 0x070, + IF (USE_HT32_CHIP=HT32F57331_41) + DCD _RESERVED ; 13, 29, 0x074, + DCD _RESERVED ; 14, 30, 0x078, + ENDIF + IF (USE_HT32_CHIP=HT32F57342_52) + DCD SCTM0_IRQHandler ; 13, 29, 0x074, + DCD SCTM1_IRQHandler ; 14, 30, 0x078, + ENDIF + DCD PWM0_IRQHandler ; 15, 31, 0x07C, + DCD PWM1_IRQHandler ; 16, 32, 0x080, + DCD BFTM0_IRQHandler ; 17, 33, 0x084, + DCD BFTM1_IRQHandler ; 18, 34, 0x088, + DCD I2C0_IRQHandler ; 19, 35, 0x08C, + DCD I2C1_IRQHandler ; 20, 36, 0x090, + DCD SPI0_IRQHandler ; 21, 37, 0x094, + DCD SPI1_IRQHandler ; 22, 38, 0x098, + DCD USART0_IRQHandler ; 23, 39, 0x09C, + DCD _RESERVED ; 24, 40, 0x0A0, + DCD UART0_IRQHandler ; 25, 41, 0x0A4, + DCD UART1_IRQHandler ; 26, 42, 0x0A8, + DCD SCI_IRQHandler ; 27, 43, 0x0AC, + DCD I2S_IRQHandler ; 28, 44, 0x0B0, + DCD USB_IRQHandler ; 29, 45, 0x0B4, + IF (USE_HT32_CHIP=HT32F57331_41) + DCD _RESERVED ; 30, 46, 0x0B8, + DCD _RESERVED ; 31, 47, 0x0BC, + ENDIF + IF (USE_HT32_CHIP=HT32F57342_52) + DCD PDMA_CH0_1_IRQHandler ; 30, 46, 0x0B8, + DCD PDMA_CH2_5_IRQHandler ; 31, 47, 0x0BC, + ENDIF + +; Reset handler routine +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + LDR R0, =BootProcess + BLX R0 + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +BootProcess PROC + LDR R0, =0x40080300 + LDR R1,[R0, #0x10] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x14] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x18] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x1C] + CMP R1, #0 + BEQ BP2 +BP1 LDR R0, =0x40080180 + LDR R1,[R0, #0xC] + LSLS R1, R1, #4 + LSRS R1, R1, #20 + CMP R1, #0 + BEQ BP3 + CMP R1, #5 + BEQ BP3 + CMP R1, #6 + BEQ BP3 +BP2 DSB + LDR R0, =0x20000000 + LDR R1, =0x05fa0004 + STR R1, [R0] + LDR R1, =0xe000ed00 + LDR R0, =0x05fa0004 + STR R0, [R1, #0xC] + DSB + B . +BP3 LDR R0, =0x20000000 + LDR R1, [R0] + LDR R0, =0x05fa0004 + CMP R0, R1 + BEQ BP4 + BX LR +BP4 LDR R0, =0x40088100 + LDR R1, =0x00000001 + STR R1, [R0] + LDR R0, =0x20000000 + LDR R1, =0x0 + STR R1, [R0] + BX LR + ENDP + +; Dummy Exception Handlers +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP + +HardFault_Handler PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP + +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP + +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP + +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + EXPORT LVD_BOD_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT EVWUP_IRQHandler [WEAK] + EXPORT EXTI0_1_IRQHandler [WEAK] + EXPORT EXTI2_3_IRQHandler [WEAK] + EXPORT EXTI4_15_IRQHandler [WEAK] + EXPORT COMP_DAC_IRQHandler [WEAK] + EXPORT ADC_IRQHandler [WEAK] + EXPORT AES_IRQHandler [WEAK] + EXPORT LCD_IRQHandler [WEAK] + EXPORT GPTM0_IRQHandler [WEAK] + EXPORT SCTM0_IRQHandler [WEAK] + EXPORT SCTM1_IRQHandler [WEAK] + EXPORT PWM0_IRQHandler [WEAK] + EXPORT PWM1_IRQHandler [WEAK] + EXPORT BFTM0_IRQHandler [WEAK] + EXPORT BFTM1_IRQHandler [WEAK] + EXPORT I2C0_IRQHandler [WEAK] + EXPORT I2C1_IRQHandler [WEAK] + EXPORT SPI0_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT USART0_IRQHandler [WEAK] + EXPORT USART1_IRQHandler [WEAK] + EXPORT UART0_IRQHandler [WEAK] + EXPORT UART1_IRQHandler [WEAK] + EXPORT SCI_IRQHandler [WEAK] + EXPORT I2S_IRQHandler [WEAK] + EXPORT USB_IRQHandler [WEAK] + EXPORT PDMA_CH0_1_IRQHandler [WEAK] + EXPORT PDMA_CH2_5_IRQHandler [WEAK] + +LVD_BOD_IRQHandler +RTC_IRQHandler +FLASH_IRQHandler +EVWUP_IRQHandler +EXTI0_1_IRQHandler +EXTI2_3_IRQHandler +EXTI4_15_IRQHandler +COMP_DAC_IRQHandler +ADC_IRQHandler +AES_IRQHandler +LCD_IRQHandler +GPTM0_IRQHandler +SCTM0_IRQHandler +SCTM1_IRQHandler +PWM0_IRQHandler +PWM1_IRQHandler +BFTM0_IRQHandler +BFTM1_IRQHandler +I2C0_IRQHandler +I2C1_IRQHandler +SPI0_IRQHandler +SPI1_IRQHandler +USART0_IRQHandler +USART1_IRQHandler +UART0_IRQHandler +UART1_IRQHandler +SCI_IRQHandler +I2S_IRQHandler +USB_IRQHandler +PDMA_CH0_1_IRQHandler +PDMA_CH2_5_IRQHandler + B . + ENDP + + ALIGN + +;******************************************************************************* +; User Stack and Heap initialization +;******************************************************************************* + IF :DEF:__MICROLIB + + EXPORT __HT_check_heap + EXPORT __HT_check_sp + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, = (Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + + ENDIF + + END diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f57342_52.s b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f57342_52.s new file mode 100644 index 0000000000..b1d916864c --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f57342_52.s @@ -0,0 +1,350 @@ +;/*---------------------------------------------------------------------------------------------------------*/ +;/* Holtek Semiconductor Inc. */ +;/* */ +;/* Copyright (C) Holtek Semiconductor Inc. */ +;/* All rights reserved. */ +;/* */ +;/*----------------------------------------------------------------------------------------------------------- +; File Name : startup_ht32f5xxxx_05.s +; Version : $Rev:: 6993 $ +; Date : $Date:: 2023-06-26 #$ +; Description : Startup code. +;-----------------------------------------------------------------------------------------------------------*/ + +; Supported Device +; ======================================== +; HT32F57331, HT32F57341 +; HT32F57342, HT32F57352 +; HT32F59741 +; HT32F5828 +; HT32F67742 +; HT32F59746 + +;/* <<< Use Configuration Wizard in Context Menu >>> */ + +;// HT32 Device +;// Select HT32 Device for the assembly setting. +;// Notice that the project's Asm Define has the higher priority. +;// <0=> By Project Asm Define +;// <13=> HT32F57331/41 +;// <14=> HT32F57342/52 +;// <13=> HT32F59741 +;// <14=> HT32F5828 +;// <13=> HT32F67742 +;// <13=> HT32F59746 +USE_HT32_CHIP_SET EQU 14 ; Notice that the project's Asm Define has the higher priority. + +_HT32FWID EQU 0xFFFFFFFF +;_HT32FWID EQU 0x00057331 +;_HT32FWID EQU 0x00057341 +;_HT32FWID EQU 0x00057342 +;_HT32FWID EQU 0x00057352 +;_HT32FWID EQU 0x00059741 +;_HT32FWID EQU 0x00005828 +;_HT32FWID EQU 0x00067742 +;_HT32FWID EQU 0x00059746 + +HT32F57331_41 EQU 13 +HT32F57342_52 EQU 14 +HT32F59741 EQU 13 +HT32F5828 EQU 14 +HT32F67742 EQU 13 +HT32F59746 EQU 13 + + IF USE_HT32_CHIP_SET=0 + ; Use project's Asm Define setting (default) + ELSE + IF :DEF:USE_HT32_CHIP + ; Use project's Asm Define setting (higher priority than the "USE_HT32_CHIP_SET") + ELSE + ; Use "USE_HT32_CHIP_SET" in the "startup_ht32xxxxx_xx.s" file +USE_HT32_CHIP EQU USE_HT32_CHIP_SET + ENDIF + ENDIF + +; Amount of memory (in bytes) allocated for Stack and Heap +; Tailor those values to your application needs +;// Stack Size (in Bytes, must 8 byte aligned) <0-16384:8> +Stack_Size EQU 512 + + AREA STACK, NOINIT, READWRITE, ALIGN = 3 +__HT_check_sp +Stack_Mem SPACE Stack_Size +__initial_sp + +;// Heap Size (in Bytes) <0-16384:8> +Heap_Size EQU 0 + + AREA HEAP, NOINIT, READWRITE, ALIGN = 3 +__HT_check_heap +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + PRESERVE8 + THUMB + +;******************************************************************************* +; Fill-up the Vector Table entries with the exceptions ISR address +;******************************************************************************* + AREA RESET, CODE, READONLY + EXPORT __Vectors +_RESERVED EQU 0xFFFFFFFF +__Vectors + DCD __initial_sp ; ---, 00, 0x000, Top address of Stack + DCD Reset_Handler ; ---, 01, 0x004, Reset Handler + DCD NMI_Handler ; -14, 02, 0x008, NMI Handler + DCD HardFault_Handler ; -13, 03, 0x00C, Hard Fault Handler + DCD _RESERVED ; ---, 04, 0x010, Reserved + DCD _RESERVED ; ---, 05, 0x014, Reserved + DCD _RESERVED ; ---, 06, 0x018, Reserved + DCD _RESERVED ; ---, 07, 0x01C, Reserved + DCD _HT32FWID ; ---, 08, 0x020, Reserved + DCD _RESERVED ; ---, 09, 0x024, Reserved + DCD _RESERVED ; ---, 10, 0x028, Reserved + DCD SVC_Handler ; -05, 11, 0x02C, SVC Handler + DCD _RESERVED ; ---, 12, 0x030, Reserved + DCD _RESERVED ; ---, 13, 0x034, Reserved + DCD PendSV_Handler ; -02, 14, 0x038, PendSV Handler + DCD SysTick_Handler ; -01, 15, 0x03C, SysTick Handler + + ; External Interrupt Handler + DCD LVD_BOD_IRQHandler ; 00, 16, 0x040, + DCD RTC_IRQHandler ; 01, 17, 0x044, + DCD FLASH_IRQHandler ; 02, 18, 0x048, + DCD EVWUP_IRQHandler ; 03, 19, 0x04C, + DCD EXTI0_1_IRQHandler ; 04, 20, 0x050, + DCD EXTI2_3_IRQHandler ; 05, 21, 0x054, + DCD EXTI4_15_IRQHandler ; 06, 22, 0x058, + IF (USE_HT32_CHIP=HT32F57331_41) + DCD _RESERVED ; 07, 23, 0x05C, + ENDIF + IF (USE_HT32_CHIP=HT32F57342_52) + DCD COMP_DAC_IRQHandler ; 07, 23, 0x05C, + ENDIF + DCD ADC_IRQHandler ; 08, 24, 0x060, + IF (USE_HT32_CHIP=HT32F57331_41) + DCD _RESERVED ; 09, 25, 0x064, + ENDIF + IF (USE_HT32_CHIP=HT32F57342_52) + DCD AES_IRQHandler ; 09, 25, 0x064, + ENDIF + DCD _RESERVED ; 10, 26, 0x068, + DCD LCD_IRQHandler ; 11, 27, 0x06C, + DCD GPTM0_IRQHandler ; 12, 28, 0x070, + IF (USE_HT32_CHIP=HT32F57331_41) + DCD _RESERVED ; 13, 29, 0x074, + DCD _RESERVED ; 14, 30, 0x078, + ENDIF + IF (USE_HT32_CHIP=HT32F57342_52) + DCD SCTM0_IRQHandler ; 13, 29, 0x074, + DCD SCTM1_IRQHandler ; 14, 30, 0x078, + ENDIF + DCD PWM0_IRQHandler ; 15, 31, 0x07C, + DCD PWM1_IRQHandler ; 16, 32, 0x080, + DCD BFTM0_IRQHandler ; 17, 33, 0x084, + DCD BFTM1_IRQHandler ; 18, 34, 0x088, + DCD I2C0_IRQHandler ; 19, 35, 0x08C, + DCD I2C1_IRQHandler ; 20, 36, 0x090, + DCD SPI0_IRQHandler ; 21, 37, 0x094, + DCD SPI1_IRQHandler ; 22, 38, 0x098, + DCD USART0_IRQHandler ; 23, 39, 0x09C, + DCD _RESERVED ; 24, 40, 0x0A0, + DCD UART0_IRQHandler ; 25, 41, 0x0A4, + DCD UART1_IRQHandler ; 26, 42, 0x0A8, + DCD SCI_IRQHandler ; 27, 43, 0x0AC, + DCD I2S_IRQHandler ; 28, 44, 0x0B0, + DCD USB_IRQHandler ; 29, 45, 0x0B4, + IF (USE_HT32_CHIP=HT32F57331_41) + DCD _RESERVED ; 30, 46, 0x0B8, + DCD _RESERVED ; 31, 47, 0x0BC, + ENDIF + IF (USE_HT32_CHIP=HT32F57342_52) + DCD PDMA_CH0_1_IRQHandler ; 30, 46, 0x0B8, + DCD PDMA_CH2_5_IRQHandler ; 31, 47, 0x0BC, + ENDIF + +; Reset handler routine +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + LDR R0, =BootProcess + BLX R0 + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +BootProcess PROC + LDR R0, =0x40080300 + LDR R1,[R0, #0x10] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x14] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x18] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x1C] + CMP R1, #0 + BEQ BP2 +BP1 LDR R0, =0x40080180 + LDR R1,[R0, #0xC] + LSLS R1, R1, #4 + LSRS R1, R1, #20 + CMP R1, #0 + BEQ BP3 + CMP R1, #5 + BEQ BP3 + CMP R1, #6 + BEQ BP3 +BP2 DSB + LDR R0, =0x20000000 + LDR R1, =0x05fa0004 + STR R1, [R0] + LDR R1, =0xe000ed00 + LDR R0, =0x05fa0004 + STR R0, [R1, #0xC] + DSB + B . +BP3 LDR R0, =0x20000000 + LDR R1, [R0] + LDR R0, =0x05fa0004 + CMP R0, R1 + BEQ BP4 + BX LR +BP4 LDR R0, =0x40088100 + LDR R1, =0x00000001 + STR R1, [R0] + LDR R0, =0x20000000 + LDR R1, =0x0 + STR R1, [R0] + BX LR + ENDP + +; Dummy Exception Handlers +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP + +HardFault_Handler PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP + +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP + +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP + +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + EXPORT LVD_BOD_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT EVWUP_IRQHandler [WEAK] + EXPORT EXTI0_1_IRQHandler [WEAK] + EXPORT EXTI2_3_IRQHandler [WEAK] + EXPORT EXTI4_15_IRQHandler [WEAK] + EXPORT COMP_DAC_IRQHandler [WEAK] + EXPORT ADC_IRQHandler [WEAK] + EXPORT AES_IRQHandler [WEAK] + EXPORT LCD_IRQHandler [WEAK] + EXPORT GPTM0_IRQHandler [WEAK] + EXPORT SCTM0_IRQHandler [WEAK] + EXPORT SCTM1_IRQHandler [WEAK] + EXPORT PWM0_IRQHandler [WEAK] + EXPORT PWM1_IRQHandler [WEAK] + EXPORT BFTM0_IRQHandler [WEAK] + EXPORT BFTM1_IRQHandler [WEAK] + EXPORT I2C0_IRQHandler [WEAK] + EXPORT I2C1_IRQHandler [WEAK] + EXPORT SPI0_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT USART0_IRQHandler [WEAK] + EXPORT USART1_IRQHandler [WEAK] + EXPORT UART0_IRQHandler [WEAK] + EXPORT UART1_IRQHandler [WEAK] + EXPORT SCI_IRQHandler [WEAK] + EXPORT I2S_IRQHandler [WEAK] + EXPORT USB_IRQHandler [WEAK] + EXPORT PDMA_CH0_1_IRQHandler [WEAK] + EXPORT PDMA_CH2_5_IRQHandler [WEAK] + +LVD_BOD_IRQHandler +RTC_IRQHandler +FLASH_IRQHandler +EVWUP_IRQHandler +EXTI0_1_IRQHandler +EXTI2_3_IRQHandler +EXTI4_15_IRQHandler +COMP_DAC_IRQHandler +ADC_IRQHandler +AES_IRQHandler +LCD_IRQHandler +GPTM0_IRQHandler +SCTM0_IRQHandler +SCTM1_IRQHandler +PWM0_IRQHandler +PWM1_IRQHandler +BFTM0_IRQHandler +BFTM1_IRQHandler +I2C0_IRQHandler +I2C1_IRQHandler +SPI0_IRQHandler +SPI1_IRQHandler +USART0_IRQHandler +USART1_IRQHandler +UART0_IRQHandler +UART1_IRQHandler +SCI_IRQHandler +I2S_IRQHandler +USB_IRQHandler +PDMA_CH0_1_IRQHandler +PDMA_CH2_5_IRQHandler + B . + ENDP + + ALIGN + +;******************************************************************************* +; User Stack and Heap initialization +;******************************************************************************* + IF :DEF:__MICROLIB + + EXPORT __HT_check_heap + EXPORT __HT_check_sp + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, = (Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + + ENDIF + + END diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f5826.s b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f5826.s new file mode 100644 index 0000000000..eba919c13e --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f5826.s @@ -0,0 +1,311 @@ +;/*---------------------------------------------------------------------------------------------------------*/ +;/* Holtek Semiconductor Inc. */ +;/* */ +;/* Copyright (C) Holtek Semiconductor Inc. */ +;/* All rights reserved. */ +;/* */ +;/*----------------------------------------------------------------------------------------------------------- +; File Name : startup_ht32f5826.s +; Version : $Rev:: 5740 $ +; Date : $Date:: 2022-02-17 #$ +; Description : Startup code. +;-----------------------------------------------------------------------------------------------------------*/ + +; Supported Device +; ======================================== +; HT32F5826 + +;/* <<< Use Configuration Wizard in Context Menu >>> */ + +;// HT32 Device +;// Select HT32 Device for the assembly setting. +;// Notice that the project's Asm Define has the higher priority. +;// <0=> By Project Asm Define +;// <1=> HT32F5826 +USE_HT32_CHIP_SET EQU 1 ; Notice that the project's Asm Define has the higher priority. + +_HT32FWID EQU 0xFFFFFFFF +;_HT32FWID EQU 0x00005826 + +HT32F5826 EQU 1 + + IF USE_HT32_CHIP_SET=0 + ; Use project's Asm Define setting (default) + ELSE + IF :DEF:USE_HT32_CHIP + ; Use project's Asm Define setting (higher priority than the "USE_HT32_CHIP_SET") + ELSE + ; Use "USE_HT32_CHIP_SET" in the "startup_ht32xxxxx_xx.s" file +USE_HT32_CHIP EQU USE_HT32_CHIP_SET + ENDIF + ENDIF + +; Amount of memory (in bytes) allocated for Stack and Heap +; Tailor those values to your application needs +;// Stack Size (in Bytes, must 8 byte aligned) <0-16384:8> +Stack_Size EQU 512 + + AREA STACK, NOINIT, READWRITE, ALIGN = 3 +__HT_check_sp +Stack_Mem SPACE Stack_Size +__initial_sp + +;// Heap Size (in Bytes) <0-16384:8> +Heap_Size EQU 0 + + AREA HEAP, NOINIT, READWRITE, ALIGN = 3 +__HT_check_heap +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + PRESERVE8 + THUMB + +;******************************************************************************* +; Fill-up the Vector Table entries with the exceptions ISR address +;******************************************************************************* + AREA RESET, CODE, READONLY + EXPORT __Vectors +_RESERVED EQU 0xFFFFFFFF +__Vectors + DCD __initial_sp ; ---, 00, 0x000, Top address of Stack + DCD Reset_Handler ; ---, 01, 0x004, Reset Handler + DCD NMI_Handler ; -14, 02, 0x008, NMI Handler + DCD HardFault_Handler ; -13, 03, 0x00C, Hard Fault Handler + DCD _RESERVED ; ---, 04, 0x010, Reserved + DCD _RESERVED ; ---, 05, 0x014, Reserved + DCD _RESERVED ; ---, 06, 0x018, Reserved + DCD _RESERVED ; ---, 07, 0x01C, Reserved + DCD _HT32FWID ; ---, 08, 0x020, Reserved + DCD _RESERVED ; ---, 09, 0x024, Reserved + DCD _RESERVED ; ---, 10, 0x028, Reserved + DCD SVC_Handler ; -05, 11, 0x02C, SVC Handler + DCD _RESERVED ; ---, 12, 0x030, Reserved + DCD _RESERVED ; ---, 13, 0x034, Reserved + DCD PendSV_Handler ; -02, 14, 0x038, PendSV Handler + DCD SysTick_Handler ; -01, 15, 0x03C, SysTick Handler + + ; External Interrupt Handler + DCD LVD_BOD_IRQHandler ; 00, 16, 0x040, + DCD RTC_IRQHandler ; 01, 17, 0x044, + DCD FLASH_IRQHandler ; 02, 18, 0x048, + DCD EVWUP_IRQHandler ; 03, 19, 0x04C, + DCD EXTI0_1_IRQHandler ; 04, 20, 0x050, + DCD EXTI2_3_IRQHandler ; 05, 21, 0x054, + DCD EXTI4_15_IRQHandler ; 06, 22, 0x058, + DCD COMP_IRQHandler ; 07, 23, 0x05C, + DCD ADC_IRQHandler ; 08, 24, 0x060, + DCD _RESERVED ; 09, 25, 0x064, + DCD MCTM0_IRQHandler ; 10, 26, 0x068, + DCD GPTM1_IRQHandler ; 11, 27, 0x06C, + DCD GPTM0_IRQHandler ; 12, 28, 0x070, + DCD SCTM0_IRQHandler ; 13, 29, 0x074, + DCD SCTM1_IRQHandler ; 14, 30, 0x078, + DCD _RESERVED ; 15, 31, 0x07C, + DCD _RESERVED ; 16, 32, 0x080, + DCD BFTM0_IRQHandler ; 17, 33, 0x084, + DCD BFTM1_IRQHandler ; 18, 34, 0x088, + DCD I2C0_IRQHandler ; 19, 35, 0x08C, + DCD I2C1_IRQHandler ; 20, 36, 0x090, + DCD SPI0_IRQHandler ; 21, 37, 0x094, + DCD SPI1_IRQHandler ; 22, 38, 0x098, + DCD USART0_IRQHandler ; 23, 39, 0x09C, + DCD USART1_IRQHandler ; 24, 40, 0x0A0, + DCD UART0_IRQHandler ; 25, 41, 0x0A4, + DCD UART1_IRQHandler ; 26, 42, 0x0A8, + DCD SCI_IRQHandler ; 27, 43, 0x0AC, + DCD I2S_IRQHandler ; 28, 44, 0x0B0, + DCD USB_IRQHandler ; 29, 45, 0x0B4, + DCD PDMA_CH0_1_IRQHandler ; 30, 46, 0x0B8, + DCD PDMA_CH2_5_IRQHandler ; 31, 47, 0x0BC, + +; Reset handler routine +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + LDR R0, =BootProcess + BLX R0 + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +BootProcess PROC + LDR R0, =0x40080300 + LDR R1,[R0, #0x10] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x14] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x18] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x1C] + CMP R1, #0 + BEQ BP2 +BP1 LDR R0, =0x40080180 + LDR R1,[R0, #0xC] + LSLS R1, R1, #4 + LSRS R1, R1, #20 + CMP R1, #0 + BEQ BP3 + CMP R1, #5 + BEQ BP3 + CMP R1, #6 + BEQ BP3 +BP2 DSB + LDR R0, =0x20000000 + LDR R1, =0x05fa0004 + STR R1, [R0] + LDR R1, =0xe000ed00 + LDR R0, =0x05fa0004 + STR R0, [R1, #0xC] + DSB + B . +BP3 LDR R0, =0x20000000 + LDR R1, [R0] + LDR R0, =0x05fa0004 + CMP R0, R1 + BEQ BP4 + BX LR +BP4 LDR R0, =0x40088100 + LDR R1, =0x00000001 + STR R1, [R0] + LDR R0, =0x20000000 + LDR R1, =0x0 + STR R1, [R0] + BX LR + ENDP + +; Dummy Exception Handlers +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP + +HardFault_Handler PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP + +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP + +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP + +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + EXPORT LVD_BOD_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT EVWUP_IRQHandler [WEAK] + EXPORT EXTI0_1_IRQHandler [WEAK] + EXPORT EXTI2_3_IRQHandler [WEAK] + EXPORT EXTI4_15_IRQHandler [WEAK] + EXPORT COMP_IRQHandler [WEAK] + EXPORT ADC_IRQHandler [WEAK] + EXPORT MCTM0_IRQHandler [WEAK] + EXPORT GPTM1_IRQHandler [WEAK] + EXPORT GPTM0_IRQHandler [WEAK] + EXPORT SCTM0_IRQHandler [WEAK] + EXPORT SCTM1_IRQHandler [WEAK] + EXPORT SCTM2_IRQHandler [WEAK] + EXPORT SCTM3_IRQHandler [WEAK] + EXPORT BFTM0_IRQHandler [WEAK] + EXPORT BFTM1_IRQHandler [WEAK] + EXPORT I2C0_IRQHandler [WEAK] + EXPORT I2C1_IRQHandler [WEAK] + EXPORT SPI0_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT USART0_IRQHandler [WEAK] + EXPORT USART1_IRQHandler [WEAK] + EXPORT UART0_IRQHandler [WEAK] + EXPORT UART1_IRQHandler [WEAK] + EXPORT UART2_IRQHandler [WEAK] + EXPORT UART3_IRQHandler [WEAK] + EXPORT SCI_IRQHandler [WEAK] + EXPORT I2S_IRQHandler [WEAK] + EXPORT USB_IRQHandler [WEAK] + EXPORT PDMA_CH0_1_IRQHandler [WEAK] + EXPORT PDMA_CH2_5_IRQHandler [WEAK] + +LVD_BOD_IRQHandler +RTC_IRQHandler +FLASH_IRQHandler +EVWUP_IRQHandler +EXTI0_1_IRQHandler +EXTI2_3_IRQHandler +EXTI4_15_IRQHandler +COMP_IRQHandler +ADC_IRQHandler +MCTM0_IRQHandler +GPTM1_IRQHandler +GPTM0_IRQHandler +SCTM0_IRQHandler +SCTM1_IRQHandler +SCTM2_IRQHandler +SCTM3_IRQHandler +BFTM0_IRQHandler +BFTM1_IRQHandler +I2C0_IRQHandler +I2C1_IRQHandler +I2C2_IRQHandler +SPI0_IRQHandler +SPI1_IRQHandler +USART0_IRQHandler +USART1_IRQHandler +UART0_IRQHandler +UART1_IRQHandler +UART2_IRQHandler +UART3_IRQHandler +SCI_IRQHandler +I2S_IRQHandler +USB_IRQHandler +PDMA_CH0_1_IRQHandler +PDMA_CH2_5_IRQHandler + B . + ENDP + + ALIGN + +;******************************************************************************* +; User Stack and Heap initialization +;******************************************************************************* + IF :DEF:__MICROLIB + + EXPORT __HT_check_heap + EXPORT __HT_check_sp + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, = (Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + + ENDIF + + END diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f5828.s b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f5828.s new file mode 100644 index 0000000000..b1d916864c --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f5828.s @@ -0,0 +1,350 @@ +;/*---------------------------------------------------------------------------------------------------------*/ +;/* Holtek Semiconductor Inc. */ +;/* */ +;/* Copyright (C) Holtek Semiconductor Inc. */ +;/* All rights reserved. */ +;/* */ +;/*----------------------------------------------------------------------------------------------------------- +; File Name : startup_ht32f5xxxx_05.s +; Version : $Rev:: 6993 $ +; Date : $Date:: 2023-06-26 #$ +; Description : Startup code. +;-----------------------------------------------------------------------------------------------------------*/ + +; Supported Device +; ======================================== +; HT32F57331, HT32F57341 +; HT32F57342, HT32F57352 +; HT32F59741 +; HT32F5828 +; HT32F67742 +; HT32F59746 + +;/* <<< Use Configuration Wizard in Context Menu >>> */ + +;// HT32 Device +;// Select HT32 Device for the assembly setting. +;// Notice that the project's Asm Define has the higher priority. +;// <0=> By Project Asm Define +;// <13=> HT32F57331/41 +;// <14=> HT32F57342/52 +;// <13=> HT32F59741 +;// <14=> HT32F5828 +;// <13=> HT32F67742 +;// <13=> HT32F59746 +USE_HT32_CHIP_SET EQU 14 ; Notice that the project's Asm Define has the higher priority. + +_HT32FWID EQU 0xFFFFFFFF +;_HT32FWID EQU 0x00057331 +;_HT32FWID EQU 0x00057341 +;_HT32FWID EQU 0x00057342 +;_HT32FWID EQU 0x00057352 +;_HT32FWID EQU 0x00059741 +;_HT32FWID EQU 0x00005828 +;_HT32FWID EQU 0x00067742 +;_HT32FWID EQU 0x00059746 + +HT32F57331_41 EQU 13 +HT32F57342_52 EQU 14 +HT32F59741 EQU 13 +HT32F5828 EQU 14 +HT32F67742 EQU 13 +HT32F59746 EQU 13 + + IF USE_HT32_CHIP_SET=0 + ; Use project's Asm Define setting (default) + ELSE + IF :DEF:USE_HT32_CHIP + ; Use project's Asm Define setting (higher priority than the "USE_HT32_CHIP_SET") + ELSE + ; Use "USE_HT32_CHIP_SET" in the "startup_ht32xxxxx_xx.s" file +USE_HT32_CHIP EQU USE_HT32_CHIP_SET + ENDIF + ENDIF + +; Amount of memory (in bytes) allocated for Stack and Heap +; Tailor those values to your application needs +;// Stack Size (in Bytes, must 8 byte aligned) <0-16384:8> +Stack_Size EQU 512 + + AREA STACK, NOINIT, READWRITE, ALIGN = 3 +__HT_check_sp +Stack_Mem SPACE Stack_Size +__initial_sp + +;// Heap Size (in Bytes) <0-16384:8> +Heap_Size EQU 0 + + AREA HEAP, NOINIT, READWRITE, ALIGN = 3 +__HT_check_heap +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + PRESERVE8 + THUMB + +;******************************************************************************* +; Fill-up the Vector Table entries with the exceptions ISR address +;******************************************************************************* + AREA RESET, CODE, READONLY + EXPORT __Vectors +_RESERVED EQU 0xFFFFFFFF +__Vectors + DCD __initial_sp ; ---, 00, 0x000, Top address of Stack + DCD Reset_Handler ; ---, 01, 0x004, Reset Handler + DCD NMI_Handler ; -14, 02, 0x008, NMI Handler + DCD HardFault_Handler ; -13, 03, 0x00C, Hard Fault Handler + DCD _RESERVED ; ---, 04, 0x010, Reserved + DCD _RESERVED ; ---, 05, 0x014, Reserved + DCD _RESERVED ; ---, 06, 0x018, Reserved + DCD _RESERVED ; ---, 07, 0x01C, Reserved + DCD _HT32FWID ; ---, 08, 0x020, Reserved + DCD _RESERVED ; ---, 09, 0x024, Reserved + DCD _RESERVED ; ---, 10, 0x028, Reserved + DCD SVC_Handler ; -05, 11, 0x02C, SVC Handler + DCD _RESERVED ; ---, 12, 0x030, Reserved + DCD _RESERVED ; ---, 13, 0x034, Reserved + DCD PendSV_Handler ; -02, 14, 0x038, PendSV Handler + DCD SysTick_Handler ; -01, 15, 0x03C, SysTick Handler + + ; External Interrupt Handler + DCD LVD_BOD_IRQHandler ; 00, 16, 0x040, + DCD RTC_IRQHandler ; 01, 17, 0x044, + DCD FLASH_IRQHandler ; 02, 18, 0x048, + DCD EVWUP_IRQHandler ; 03, 19, 0x04C, + DCD EXTI0_1_IRQHandler ; 04, 20, 0x050, + DCD EXTI2_3_IRQHandler ; 05, 21, 0x054, + DCD EXTI4_15_IRQHandler ; 06, 22, 0x058, + IF (USE_HT32_CHIP=HT32F57331_41) + DCD _RESERVED ; 07, 23, 0x05C, + ENDIF + IF (USE_HT32_CHIP=HT32F57342_52) + DCD COMP_DAC_IRQHandler ; 07, 23, 0x05C, + ENDIF + DCD ADC_IRQHandler ; 08, 24, 0x060, + IF (USE_HT32_CHIP=HT32F57331_41) + DCD _RESERVED ; 09, 25, 0x064, + ENDIF + IF (USE_HT32_CHIP=HT32F57342_52) + DCD AES_IRQHandler ; 09, 25, 0x064, + ENDIF + DCD _RESERVED ; 10, 26, 0x068, + DCD LCD_IRQHandler ; 11, 27, 0x06C, + DCD GPTM0_IRQHandler ; 12, 28, 0x070, + IF (USE_HT32_CHIP=HT32F57331_41) + DCD _RESERVED ; 13, 29, 0x074, + DCD _RESERVED ; 14, 30, 0x078, + ENDIF + IF (USE_HT32_CHIP=HT32F57342_52) + DCD SCTM0_IRQHandler ; 13, 29, 0x074, + DCD SCTM1_IRQHandler ; 14, 30, 0x078, + ENDIF + DCD PWM0_IRQHandler ; 15, 31, 0x07C, + DCD PWM1_IRQHandler ; 16, 32, 0x080, + DCD BFTM0_IRQHandler ; 17, 33, 0x084, + DCD BFTM1_IRQHandler ; 18, 34, 0x088, + DCD I2C0_IRQHandler ; 19, 35, 0x08C, + DCD I2C1_IRQHandler ; 20, 36, 0x090, + DCD SPI0_IRQHandler ; 21, 37, 0x094, + DCD SPI1_IRQHandler ; 22, 38, 0x098, + DCD USART0_IRQHandler ; 23, 39, 0x09C, + DCD _RESERVED ; 24, 40, 0x0A0, + DCD UART0_IRQHandler ; 25, 41, 0x0A4, + DCD UART1_IRQHandler ; 26, 42, 0x0A8, + DCD SCI_IRQHandler ; 27, 43, 0x0AC, + DCD I2S_IRQHandler ; 28, 44, 0x0B0, + DCD USB_IRQHandler ; 29, 45, 0x0B4, + IF (USE_HT32_CHIP=HT32F57331_41) + DCD _RESERVED ; 30, 46, 0x0B8, + DCD _RESERVED ; 31, 47, 0x0BC, + ENDIF + IF (USE_HT32_CHIP=HT32F57342_52) + DCD PDMA_CH0_1_IRQHandler ; 30, 46, 0x0B8, + DCD PDMA_CH2_5_IRQHandler ; 31, 47, 0x0BC, + ENDIF + +; Reset handler routine +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + LDR R0, =BootProcess + BLX R0 + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +BootProcess PROC + LDR R0, =0x40080300 + LDR R1,[R0, #0x10] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x14] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x18] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x1C] + CMP R1, #0 + BEQ BP2 +BP1 LDR R0, =0x40080180 + LDR R1,[R0, #0xC] + LSLS R1, R1, #4 + LSRS R1, R1, #20 + CMP R1, #0 + BEQ BP3 + CMP R1, #5 + BEQ BP3 + CMP R1, #6 + BEQ BP3 +BP2 DSB + LDR R0, =0x20000000 + LDR R1, =0x05fa0004 + STR R1, [R0] + LDR R1, =0xe000ed00 + LDR R0, =0x05fa0004 + STR R0, [R1, #0xC] + DSB + B . +BP3 LDR R0, =0x20000000 + LDR R1, [R0] + LDR R0, =0x05fa0004 + CMP R0, R1 + BEQ BP4 + BX LR +BP4 LDR R0, =0x40088100 + LDR R1, =0x00000001 + STR R1, [R0] + LDR R0, =0x20000000 + LDR R1, =0x0 + STR R1, [R0] + BX LR + ENDP + +; Dummy Exception Handlers +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP + +HardFault_Handler PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP + +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP + +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP + +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + EXPORT LVD_BOD_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT EVWUP_IRQHandler [WEAK] + EXPORT EXTI0_1_IRQHandler [WEAK] + EXPORT EXTI2_3_IRQHandler [WEAK] + EXPORT EXTI4_15_IRQHandler [WEAK] + EXPORT COMP_DAC_IRQHandler [WEAK] + EXPORT ADC_IRQHandler [WEAK] + EXPORT AES_IRQHandler [WEAK] + EXPORT LCD_IRQHandler [WEAK] + EXPORT GPTM0_IRQHandler [WEAK] + EXPORT SCTM0_IRQHandler [WEAK] + EXPORT SCTM1_IRQHandler [WEAK] + EXPORT PWM0_IRQHandler [WEAK] + EXPORT PWM1_IRQHandler [WEAK] + EXPORT BFTM0_IRQHandler [WEAK] + EXPORT BFTM1_IRQHandler [WEAK] + EXPORT I2C0_IRQHandler [WEAK] + EXPORT I2C1_IRQHandler [WEAK] + EXPORT SPI0_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT USART0_IRQHandler [WEAK] + EXPORT USART1_IRQHandler [WEAK] + EXPORT UART0_IRQHandler [WEAK] + EXPORT UART1_IRQHandler [WEAK] + EXPORT SCI_IRQHandler [WEAK] + EXPORT I2S_IRQHandler [WEAK] + EXPORT USB_IRQHandler [WEAK] + EXPORT PDMA_CH0_1_IRQHandler [WEAK] + EXPORT PDMA_CH2_5_IRQHandler [WEAK] + +LVD_BOD_IRQHandler +RTC_IRQHandler +FLASH_IRQHandler +EVWUP_IRQHandler +EXTI0_1_IRQHandler +EXTI2_3_IRQHandler +EXTI4_15_IRQHandler +COMP_DAC_IRQHandler +ADC_IRQHandler +AES_IRQHandler +LCD_IRQHandler +GPTM0_IRQHandler +SCTM0_IRQHandler +SCTM1_IRQHandler +PWM0_IRQHandler +PWM1_IRQHandler +BFTM0_IRQHandler +BFTM1_IRQHandler +I2C0_IRQHandler +I2C1_IRQHandler +SPI0_IRQHandler +SPI1_IRQHandler +USART0_IRQHandler +USART1_IRQHandler +UART0_IRQHandler +UART1_IRQHandler +SCI_IRQHandler +I2S_IRQHandler +USB_IRQHandler +PDMA_CH0_1_IRQHandler +PDMA_CH2_5_IRQHandler + B . + ENDP + + ALIGN + +;******************************************************************************* +; User Stack and Heap initialization +;******************************************************************************* + IF :DEF:__MICROLIB + + EXPORT __HT_check_heap + EXPORT __HT_check_sp + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, = (Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + + ENDIF + + END diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f59041.s b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f59041.s new file mode 100644 index 0000000000..8e68952909 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f59041.s @@ -0,0 +1,327 @@ +;/*---------------------------------------------------------------------------------------------------------*/ +;/* Holtek Semiconductor Inc. */ +;/* */ +;/* Copyright (C) Holtek Semiconductor Inc. */ +;/* All rights reserved. */ +;/* */ +;/*----------------------------------------------------------------------------------------------------------- +; File Name : startup_ht32f5xxxx_02.s +; Version : $Rev:: 7119 $ +; Date : $Date:: 2023-08-15 #$ +; Description : Startup code. +;-----------------------------------------------------------------------------------------------------------*/ + +; Supported Device +; ======================================== +; HT32F50220, HT32F50230 +; HT32F50231, HT32F50241 +; HT50F32002 +; HT32F59041 +; HF5032 +; HT32F61641 +; HT32F59046 +; HT32F61041 + +;/* <<< Use Configuration Wizard in Context Menu >>> */ + +;// HT32 Device +;// Select HT32 Device for the assembly setting. +;// Notice that the project's Asm Define has the higher priority. +;// <0=> By Project Asm Define +;// <7=> HT32F50220/30 +;// <8=> HT32F50231/41 +;// <7=> HT50F32002 +;// <8=> HT32F59041 +;// <7=> HF5032 +;// <8=> HT32F61641 +;// <8=> HT32F59046 +;// <8=> HT32F61041 +USE_HT32_CHIP_SET EQU 8 ; Notice that the project's Asm Define has the higher priority. + +_HT32FWID EQU 0xFFFFFFFF +;_HT32FWID EQU 0x00050220 +;_HT32FWID EQU 0x00050230 +;_HT32FWID EQU 0x00050231 +;_HT32FWID EQU 0x00050241 +;_HT32FWID EQU 0x00032002 +;_HT32FWID EQU 0x00059041 +;_HT32FWID EQU 0x000F5032 +;_HT32FWID EQU 0x00061641 +;_HT32FWID EQU 0x00059046 +;_HT32FWID EQU 0x00061041 + +HT32F50220_30 EQU 7 +HT32F50231_41 EQU 8 +HT50F32002 EQU 7 +HT32F59041 EQU 8 +HF5032 EQU 7 +HT32F61641 EQU 8 +HT32F59046 EQU 8 +HT32F61041 EQU 8 + + IF USE_HT32_CHIP_SET=0 + ; Use project's Asm Define setting (default) + ELSE + IF :DEF:USE_HT32_CHIP + ; Use project's Asm Define setting (higher priority than the "USE_HT32_CHIP_SET") + ELSE + ; Use "USE_HT32_CHIP_SET" in the "startup_ht32xxxxx_xx.s" file +USE_HT32_CHIP EQU USE_HT32_CHIP_SET + ENDIF + ENDIF + +; Amount of memory (in bytes) allocated for Stack and Heap +; Tailor those values to your application needs +;// Stack Size (in Bytes, must 8 byte aligned) <0-4096:8> +Stack_Size EQU 512 + + AREA STACK, NOINIT, READWRITE, ALIGN = 3 +__HT_check_sp +Stack_Mem SPACE Stack_Size +__initial_sp + +;// Heap Size (in Bytes) <0-4096:8> +Heap_Size EQU 0 + + AREA HEAP, NOINIT, READWRITE, ALIGN = 3 +__HT_check_heap +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + PRESERVE8 + THUMB + +;******************************************************************************* +; Fill-up the Vector Table entries with the exceptions ISR address +;******************************************************************************* + AREA RESET, CODE, READONLY + EXPORT __Vectors +_RESERVED EQU 0xFFFFFFFF +__Vectors + DCD __initial_sp ; ---, 00, 0x000, Top address of Stack + DCD Reset_Handler ; ---, 01, 0x004, Reset Handler + DCD NMI_Handler ; -14, 02, 0x008, NMI Handler + DCD HardFault_Handler ; -13, 03, 0x00C, Hard Fault Handler + DCD _RESERVED ; ---, 04, 0x010, Reserved + DCD _RESERVED ; ---, 05, 0x014, Reserved + DCD _RESERVED ; ---, 06, 0x018, Reserved + DCD _RESERVED ; ---, 07, 0x01C, Reserved + DCD _HT32FWID ; ---, 08, 0x020, Reserved + DCD _RESERVED ; ---, 09, 0x024, Reserved + DCD _RESERVED ; ---, 10, 0x028, Reserved + DCD SVC_Handler ; -05, 11, 0x02C, SVC Handler + DCD _RESERVED ; ---, 12, 0x030, Reserved + DCD _RESERVED ; ---, 13, 0x034, Reserved + DCD PendSV_Handler ; -02, 14, 0x038, PendSV Handler + DCD SysTick_Handler ; -01, 15, 0x03C, SysTick Handler + + ; External Interrupt Handler + DCD LVD_BOD_IRQHandler ; 00, 16, 0x040, + DCD RTC_IRQHandler ; 01, 17, 0x044, + DCD FLASH_IRQHandler ; 02, 18, 0x048, + DCD EVWUP_IRQHandler ; 03, 19, 0x04C, + DCD EXTI0_1_IRQHandler ; 04, 20, 0x050, + DCD EXTI2_3_IRQHandler ; 05, 21, 0x054, + DCD EXTI4_15_IRQHandler ; 06, 22, 0x058, + DCD _RESERVED ; 07, 23, 0x05C, + DCD ADC_IRQHandler ; 08, 24, 0x060, + DCD _RESERVED ; 09, 25, 0x064, + IF (USE_HT32_CHIP=HT32F50220_30) + DCD _RESERVED ; 10, 26, 0x068, + ELSE + DCD MCTM0_IRQHandler ; 10, 26, 0x068, + ENDIF + DCD _RESERVED ; 11, 27, 0x06C, + DCD GPTM0_IRQHandler ; 12, 28, 0x070, + DCD _RESERVED ; 13, 29, 0x074, + DCD _RESERVED ; 14, 30, 0x078, + DCD PWM0_IRQHandler ; 15, 31, 0x07C, + DCD PWM1_IRQHandler ; 16, 32, 0x080, + DCD BFTM0_IRQHandler ; 17, 33, 0x084, + IF (USE_HT32_CHIP=HT32F50220_30) + DCD _RESERVED ; 18, 34, 0x088, + ELSE + DCD BFTM1_IRQHandler ; 18, 34, 0x088, + ENDIF + DCD I2C0_IRQHandler ; 19, 35, 0x08C, + IF (USE_HT32_CHIP=HT32F50220_30) + DCD _RESERVED ; 20, 36, 0x090, + ELSE + DCD I2C1_IRQHandler ; 20, 36, 0x090, + ENDIF + DCD SPI0_IRQHandler ; 21, 37, 0x094, + DCD SPI1_IRQHandler ; 22, 38, 0x098, + IF (USE_HT32_CHIP=HT32F50220_30) + DCD _RESERVED ; 23, 39, 0x09C, + ELSE + DCD USART0_IRQHandler ; 23, 39, 0x09C, + ENDIF + DCD _RESERVED ; 24, 40, 0x0A0, + DCD UART0_IRQHandler ; 25, 41, 0x0A4, + DCD UART1_IRQHandler ; 26, 42, 0x0A8, + +; Reset handler routine +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + LDR R0, =BootProcess + BLX R0 + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +BootProcess PROC + LDR R0, =0x40080300 + LDR R1,[R0, #0x10] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x14] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x18] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x1C] + CMP R1, #0 + BEQ BP2 +BP1 LDR R0, =0x40080180 + LDR R1,[R0, #0xC] + LSLS R1, R1, #4 + LSRS R1, R1, #20 + CMP R1, #0 + BEQ BP3 + CMP R1, #5 + BEQ BP3 + CMP R1, #6 + BEQ BP3 +BP2 DSB + LDR R0, =0x20000000 + LDR R1, =0x05fa0004 + STR R1, [R0] + LDR R1, =0xe000ed00 + LDR R0, =0x05fa0004 + STR R0, [R1, #0xC] + DSB + B . +BP3 LDR R0, =0x20000000 + LDR R1, [R0] + LDR R0, =0x05fa0004 + CMP R0, R1 + BEQ BP4 + BX LR +BP4 LDR R0, =0x40088100 + LDR R1, =0x00000001 + STR R1, [R0] + LDR R0, =0x20000000 + LDR R1, =0x0 + STR R1, [R0] + BX LR + ENDP + +; Dummy Exception Handlers +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP + +HardFault_Handler PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP + +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP + +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP + +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + EXPORT LVD_BOD_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT EVWUP_IRQHandler [WEAK] + EXPORT EXTI0_1_IRQHandler [WEAK] + EXPORT EXTI2_3_IRQHandler [WEAK] + EXPORT EXTI4_15_IRQHandler [WEAK] + EXPORT ADC_IRQHandler [WEAK] + EXPORT MCTM0_IRQHandler [WEAK] + EXPORT GPTM0_IRQHandler [WEAK] + EXPORT PWM0_IRQHandler [WEAK] + EXPORT PWM1_IRQHandler [WEAK] + EXPORT BFTM0_IRQHandler [WEAK] + EXPORT BFTM1_IRQHandler [WEAK] + EXPORT I2C0_IRQHandler [WEAK] + EXPORT I2C1_IRQHandler [WEAK] + EXPORT SPI0_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT USART0_IRQHandler [WEAK] + EXPORT UART0_IRQHandler [WEAK] + EXPORT UART1_IRQHandler [WEAK] + +LVD_BOD_IRQHandler +RTC_IRQHandler +FLASH_IRQHandler +EVWUP_IRQHandler +EXTI0_1_IRQHandler +EXTI2_3_IRQHandler +EXTI4_15_IRQHandler +ADC_IRQHandler +MCTM0_IRQHandler +GPTM0_IRQHandler +PWM0_IRQHandler +PWM1_IRQHandler +BFTM0_IRQHandler +BFTM1_IRQHandler +I2C0_IRQHandler +I2C1_IRQHandler +SPI0_IRQHandler +SPI1_IRQHandler +USART0_IRQHandler +UART0_IRQHandler +UART1_IRQHandler + B . + ENDP + + ALIGN + +;******************************************************************************* +; User Stack and Heap initialization +;******************************************************************************* + IF :DEF:__MICROLIB + + EXPORT __HT_check_heap + EXPORT __HT_check_sp + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, = (Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + + ENDIF + + END diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f59046.s b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f59046.s new file mode 100644 index 0000000000..8e68952909 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f59046.s @@ -0,0 +1,327 @@ +;/*---------------------------------------------------------------------------------------------------------*/ +;/* Holtek Semiconductor Inc. */ +;/* */ +;/* Copyright (C) Holtek Semiconductor Inc. */ +;/* All rights reserved. */ +;/* */ +;/*----------------------------------------------------------------------------------------------------------- +; File Name : startup_ht32f5xxxx_02.s +; Version : $Rev:: 7119 $ +; Date : $Date:: 2023-08-15 #$ +; Description : Startup code. +;-----------------------------------------------------------------------------------------------------------*/ + +; Supported Device +; ======================================== +; HT32F50220, HT32F50230 +; HT32F50231, HT32F50241 +; HT50F32002 +; HT32F59041 +; HF5032 +; HT32F61641 +; HT32F59046 +; HT32F61041 + +;/* <<< Use Configuration Wizard in Context Menu >>> */ + +;// HT32 Device +;// Select HT32 Device for the assembly setting. +;// Notice that the project's Asm Define has the higher priority. +;// <0=> By Project Asm Define +;// <7=> HT32F50220/30 +;// <8=> HT32F50231/41 +;// <7=> HT50F32002 +;// <8=> HT32F59041 +;// <7=> HF5032 +;// <8=> HT32F61641 +;// <8=> HT32F59046 +;// <8=> HT32F61041 +USE_HT32_CHIP_SET EQU 8 ; Notice that the project's Asm Define has the higher priority. + +_HT32FWID EQU 0xFFFFFFFF +;_HT32FWID EQU 0x00050220 +;_HT32FWID EQU 0x00050230 +;_HT32FWID EQU 0x00050231 +;_HT32FWID EQU 0x00050241 +;_HT32FWID EQU 0x00032002 +;_HT32FWID EQU 0x00059041 +;_HT32FWID EQU 0x000F5032 +;_HT32FWID EQU 0x00061641 +;_HT32FWID EQU 0x00059046 +;_HT32FWID EQU 0x00061041 + +HT32F50220_30 EQU 7 +HT32F50231_41 EQU 8 +HT50F32002 EQU 7 +HT32F59041 EQU 8 +HF5032 EQU 7 +HT32F61641 EQU 8 +HT32F59046 EQU 8 +HT32F61041 EQU 8 + + IF USE_HT32_CHIP_SET=0 + ; Use project's Asm Define setting (default) + ELSE + IF :DEF:USE_HT32_CHIP + ; Use project's Asm Define setting (higher priority than the "USE_HT32_CHIP_SET") + ELSE + ; Use "USE_HT32_CHIP_SET" in the "startup_ht32xxxxx_xx.s" file +USE_HT32_CHIP EQU USE_HT32_CHIP_SET + ENDIF + ENDIF + +; Amount of memory (in bytes) allocated for Stack and Heap +; Tailor those values to your application needs +;// Stack Size (in Bytes, must 8 byte aligned) <0-4096:8> +Stack_Size EQU 512 + + AREA STACK, NOINIT, READWRITE, ALIGN = 3 +__HT_check_sp +Stack_Mem SPACE Stack_Size +__initial_sp + +;// Heap Size (in Bytes) <0-4096:8> +Heap_Size EQU 0 + + AREA HEAP, NOINIT, READWRITE, ALIGN = 3 +__HT_check_heap +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + PRESERVE8 + THUMB + +;******************************************************************************* +; Fill-up the Vector Table entries with the exceptions ISR address +;******************************************************************************* + AREA RESET, CODE, READONLY + EXPORT __Vectors +_RESERVED EQU 0xFFFFFFFF +__Vectors + DCD __initial_sp ; ---, 00, 0x000, Top address of Stack + DCD Reset_Handler ; ---, 01, 0x004, Reset Handler + DCD NMI_Handler ; -14, 02, 0x008, NMI Handler + DCD HardFault_Handler ; -13, 03, 0x00C, Hard Fault Handler + DCD _RESERVED ; ---, 04, 0x010, Reserved + DCD _RESERVED ; ---, 05, 0x014, Reserved + DCD _RESERVED ; ---, 06, 0x018, Reserved + DCD _RESERVED ; ---, 07, 0x01C, Reserved + DCD _HT32FWID ; ---, 08, 0x020, Reserved + DCD _RESERVED ; ---, 09, 0x024, Reserved + DCD _RESERVED ; ---, 10, 0x028, Reserved + DCD SVC_Handler ; -05, 11, 0x02C, SVC Handler + DCD _RESERVED ; ---, 12, 0x030, Reserved + DCD _RESERVED ; ---, 13, 0x034, Reserved + DCD PendSV_Handler ; -02, 14, 0x038, PendSV Handler + DCD SysTick_Handler ; -01, 15, 0x03C, SysTick Handler + + ; External Interrupt Handler + DCD LVD_BOD_IRQHandler ; 00, 16, 0x040, + DCD RTC_IRQHandler ; 01, 17, 0x044, + DCD FLASH_IRQHandler ; 02, 18, 0x048, + DCD EVWUP_IRQHandler ; 03, 19, 0x04C, + DCD EXTI0_1_IRQHandler ; 04, 20, 0x050, + DCD EXTI2_3_IRQHandler ; 05, 21, 0x054, + DCD EXTI4_15_IRQHandler ; 06, 22, 0x058, + DCD _RESERVED ; 07, 23, 0x05C, + DCD ADC_IRQHandler ; 08, 24, 0x060, + DCD _RESERVED ; 09, 25, 0x064, + IF (USE_HT32_CHIP=HT32F50220_30) + DCD _RESERVED ; 10, 26, 0x068, + ELSE + DCD MCTM0_IRQHandler ; 10, 26, 0x068, + ENDIF + DCD _RESERVED ; 11, 27, 0x06C, + DCD GPTM0_IRQHandler ; 12, 28, 0x070, + DCD _RESERVED ; 13, 29, 0x074, + DCD _RESERVED ; 14, 30, 0x078, + DCD PWM0_IRQHandler ; 15, 31, 0x07C, + DCD PWM1_IRQHandler ; 16, 32, 0x080, + DCD BFTM0_IRQHandler ; 17, 33, 0x084, + IF (USE_HT32_CHIP=HT32F50220_30) + DCD _RESERVED ; 18, 34, 0x088, + ELSE + DCD BFTM1_IRQHandler ; 18, 34, 0x088, + ENDIF + DCD I2C0_IRQHandler ; 19, 35, 0x08C, + IF (USE_HT32_CHIP=HT32F50220_30) + DCD _RESERVED ; 20, 36, 0x090, + ELSE + DCD I2C1_IRQHandler ; 20, 36, 0x090, + ENDIF + DCD SPI0_IRQHandler ; 21, 37, 0x094, + DCD SPI1_IRQHandler ; 22, 38, 0x098, + IF (USE_HT32_CHIP=HT32F50220_30) + DCD _RESERVED ; 23, 39, 0x09C, + ELSE + DCD USART0_IRQHandler ; 23, 39, 0x09C, + ENDIF + DCD _RESERVED ; 24, 40, 0x0A0, + DCD UART0_IRQHandler ; 25, 41, 0x0A4, + DCD UART1_IRQHandler ; 26, 42, 0x0A8, + +; Reset handler routine +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + LDR R0, =BootProcess + BLX R0 + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +BootProcess PROC + LDR R0, =0x40080300 + LDR R1,[R0, #0x10] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x14] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x18] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x1C] + CMP R1, #0 + BEQ BP2 +BP1 LDR R0, =0x40080180 + LDR R1,[R0, #0xC] + LSLS R1, R1, #4 + LSRS R1, R1, #20 + CMP R1, #0 + BEQ BP3 + CMP R1, #5 + BEQ BP3 + CMP R1, #6 + BEQ BP3 +BP2 DSB + LDR R0, =0x20000000 + LDR R1, =0x05fa0004 + STR R1, [R0] + LDR R1, =0xe000ed00 + LDR R0, =0x05fa0004 + STR R0, [R1, #0xC] + DSB + B . +BP3 LDR R0, =0x20000000 + LDR R1, [R0] + LDR R0, =0x05fa0004 + CMP R0, R1 + BEQ BP4 + BX LR +BP4 LDR R0, =0x40088100 + LDR R1, =0x00000001 + STR R1, [R0] + LDR R0, =0x20000000 + LDR R1, =0x0 + STR R1, [R0] + BX LR + ENDP + +; Dummy Exception Handlers +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP + +HardFault_Handler PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP + +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP + +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP + +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + EXPORT LVD_BOD_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT EVWUP_IRQHandler [WEAK] + EXPORT EXTI0_1_IRQHandler [WEAK] + EXPORT EXTI2_3_IRQHandler [WEAK] + EXPORT EXTI4_15_IRQHandler [WEAK] + EXPORT ADC_IRQHandler [WEAK] + EXPORT MCTM0_IRQHandler [WEAK] + EXPORT GPTM0_IRQHandler [WEAK] + EXPORT PWM0_IRQHandler [WEAK] + EXPORT PWM1_IRQHandler [WEAK] + EXPORT BFTM0_IRQHandler [WEAK] + EXPORT BFTM1_IRQHandler [WEAK] + EXPORT I2C0_IRQHandler [WEAK] + EXPORT I2C1_IRQHandler [WEAK] + EXPORT SPI0_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT USART0_IRQHandler [WEAK] + EXPORT UART0_IRQHandler [WEAK] + EXPORT UART1_IRQHandler [WEAK] + +LVD_BOD_IRQHandler +RTC_IRQHandler +FLASH_IRQHandler +EVWUP_IRQHandler +EXTI0_1_IRQHandler +EXTI2_3_IRQHandler +EXTI4_15_IRQHandler +ADC_IRQHandler +MCTM0_IRQHandler +GPTM0_IRQHandler +PWM0_IRQHandler +PWM1_IRQHandler +BFTM0_IRQHandler +BFTM1_IRQHandler +I2C0_IRQHandler +I2C1_IRQHandler +SPI0_IRQHandler +SPI1_IRQHandler +USART0_IRQHandler +UART0_IRQHandler +UART1_IRQHandler + B . + ENDP + + ALIGN + +;******************************************************************************* +; User Stack and Heap initialization +;******************************************************************************* + IF :DEF:__MICROLIB + + EXPORT __HT_check_heap + EXPORT __HT_check_sp + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, = (Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + + ENDIF + + END diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f59741.s b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f59741.s new file mode 100644 index 0000000000..cbaf7f3ee1 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f59741.s @@ -0,0 +1,350 @@ +;/*---------------------------------------------------------------------------------------------------------*/ +;/* Holtek Semiconductor Inc. */ +;/* */ +;/* Copyright (C) Holtek Semiconductor Inc. */ +;/* All rights reserved. */ +;/* */ +;/*----------------------------------------------------------------------------------------------------------- +; File Name : startup_ht32f5xxxx_05.s +; Version : $Rev:: 6993 $ +; Date : $Date:: 2023-06-26 #$ +; Description : Startup code. +;-----------------------------------------------------------------------------------------------------------*/ + +; Supported Device +; ======================================== +; HT32F57331, HT32F57341 +; HT32F57342, HT32F57352 +; HT32F59741 +; HT32F5828 +; HT32F67742 +; HT32F59746 + +;/* <<< Use Configuration Wizard in Context Menu >>> */ + +;// HT32 Device +;// Select HT32 Device for the assembly setting. +;// Notice that the project's Asm Define has the higher priority. +;// <0=> By Project Asm Define +;// <13=> HT32F57331/41 +;// <14=> HT32F57342/52 +;// <13=> HT32F59741 +;// <14=> HT32F5828 +;// <13=> HT32F67742 +;// <13=> HT32F59746 +USE_HT32_CHIP_SET EQU 13 ; Notice that the project's Asm Define has the higher priority. + +_HT32FWID EQU 0xFFFFFFFF +;_HT32FWID EQU 0x00057331 +;_HT32FWID EQU 0x00057341 +;_HT32FWID EQU 0x00057342 +;_HT32FWID EQU 0x00057352 +;_HT32FWID EQU 0x00059741 +;_HT32FWID EQU 0x00005828 +;_HT32FWID EQU 0x00067742 +;_HT32FWID EQU 0x00059746 + +HT32F57331_41 EQU 13 +HT32F57342_52 EQU 14 +HT32F59741 EQU 13 +HT32F5828 EQU 14 +HT32F67742 EQU 13 +HT32F59746 EQU 13 + + IF USE_HT32_CHIP_SET=0 + ; Use project's Asm Define setting (default) + ELSE + IF :DEF:USE_HT32_CHIP + ; Use project's Asm Define setting (higher priority than the "USE_HT32_CHIP_SET") + ELSE + ; Use "USE_HT32_CHIP_SET" in the "startup_ht32xxxxx_xx.s" file +USE_HT32_CHIP EQU USE_HT32_CHIP_SET + ENDIF + ENDIF + +; Amount of memory (in bytes) allocated for Stack and Heap +; Tailor those values to your application needs +;// Stack Size (in Bytes, must 8 byte aligned) <0-16384:8> +Stack_Size EQU 512 + + AREA STACK, NOINIT, READWRITE, ALIGN = 3 +__HT_check_sp +Stack_Mem SPACE Stack_Size +__initial_sp + +;// Heap Size (in Bytes) <0-16384:8> +Heap_Size EQU 0 + + AREA HEAP, NOINIT, READWRITE, ALIGN = 3 +__HT_check_heap +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + PRESERVE8 + THUMB + +;******************************************************************************* +; Fill-up the Vector Table entries with the exceptions ISR address +;******************************************************************************* + AREA RESET, CODE, READONLY + EXPORT __Vectors +_RESERVED EQU 0xFFFFFFFF +__Vectors + DCD __initial_sp ; ---, 00, 0x000, Top address of Stack + DCD Reset_Handler ; ---, 01, 0x004, Reset Handler + DCD NMI_Handler ; -14, 02, 0x008, NMI Handler + DCD HardFault_Handler ; -13, 03, 0x00C, Hard Fault Handler + DCD _RESERVED ; ---, 04, 0x010, Reserved + DCD _RESERVED ; ---, 05, 0x014, Reserved + DCD _RESERVED ; ---, 06, 0x018, Reserved + DCD _RESERVED ; ---, 07, 0x01C, Reserved + DCD _HT32FWID ; ---, 08, 0x020, Reserved + DCD _RESERVED ; ---, 09, 0x024, Reserved + DCD _RESERVED ; ---, 10, 0x028, Reserved + DCD SVC_Handler ; -05, 11, 0x02C, SVC Handler + DCD _RESERVED ; ---, 12, 0x030, Reserved + DCD _RESERVED ; ---, 13, 0x034, Reserved + DCD PendSV_Handler ; -02, 14, 0x038, PendSV Handler + DCD SysTick_Handler ; -01, 15, 0x03C, SysTick Handler + + ; External Interrupt Handler + DCD LVD_BOD_IRQHandler ; 00, 16, 0x040, + DCD RTC_IRQHandler ; 01, 17, 0x044, + DCD FLASH_IRQHandler ; 02, 18, 0x048, + DCD EVWUP_IRQHandler ; 03, 19, 0x04C, + DCD EXTI0_1_IRQHandler ; 04, 20, 0x050, + DCD EXTI2_3_IRQHandler ; 05, 21, 0x054, + DCD EXTI4_15_IRQHandler ; 06, 22, 0x058, + IF (USE_HT32_CHIP=HT32F57331_41) + DCD _RESERVED ; 07, 23, 0x05C, + ENDIF + IF (USE_HT32_CHIP=HT32F57342_52) + DCD COMP_DAC_IRQHandler ; 07, 23, 0x05C, + ENDIF + DCD ADC_IRQHandler ; 08, 24, 0x060, + IF (USE_HT32_CHIP=HT32F57331_41) + DCD _RESERVED ; 09, 25, 0x064, + ENDIF + IF (USE_HT32_CHIP=HT32F57342_52) + DCD AES_IRQHandler ; 09, 25, 0x064, + ENDIF + DCD _RESERVED ; 10, 26, 0x068, + DCD LCD_IRQHandler ; 11, 27, 0x06C, + DCD GPTM0_IRQHandler ; 12, 28, 0x070, + IF (USE_HT32_CHIP=HT32F57331_41) + DCD _RESERVED ; 13, 29, 0x074, + DCD _RESERVED ; 14, 30, 0x078, + ENDIF + IF (USE_HT32_CHIP=HT32F57342_52) + DCD SCTM0_IRQHandler ; 13, 29, 0x074, + DCD SCTM1_IRQHandler ; 14, 30, 0x078, + ENDIF + DCD PWM0_IRQHandler ; 15, 31, 0x07C, + DCD PWM1_IRQHandler ; 16, 32, 0x080, + DCD BFTM0_IRQHandler ; 17, 33, 0x084, + DCD BFTM1_IRQHandler ; 18, 34, 0x088, + DCD I2C0_IRQHandler ; 19, 35, 0x08C, + DCD I2C1_IRQHandler ; 20, 36, 0x090, + DCD SPI0_IRQHandler ; 21, 37, 0x094, + DCD SPI1_IRQHandler ; 22, 38, 0x098, + DCD USART0_IRQHandler ; 23, 39, 0x09C, + DCD _RESERVED ; 24, 40, 0x0A0, + DCD UART0_IRQHandler ; 25, 41, 0x0A4, + DCD UART1_IRQHandler ; 26, 42, 0x0A8, + DCD SCI_IRQHandler ; 27, 43, 0x0AC, + DCD I2S_IRQHandler ; 28, 44, 0x0B0, + DCD USB_IRQHandler ; 29, 45, 0x0B4, + IF (USE_HT32_CHIP=HT32F57331_41) + DCD _RESERVED ; 30, 46, 0x0B8, + DCD _RESERVED ; 31, 47, 0x0BC, + ENDIF + IF (USE_HT32_CHIP=HT32F57342_52) + DCD PDMA_CH0_1_IRQHandler ; 30, 46, 0x0B8, + DCD PDMA_CH2_5_IRQHandler ; 31, 47, 0x0BC, + ENDIF + +; Reset handler routine +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + LDR R0, =BootProcess + BLX R0 + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +BootProcess PROC + LDR R0, =0x40080300 + LDR R1,[R0, #0x10] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x14] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x18] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x1C] + CMP R1, #0 + BEQ BP2 +BP1 LDR R0, =0x40080180 + LDR R1,[R0, #0xC] + LSLS R1, R1, #4 + LSRS R1, R1, #20 + CMP R1, #0 + BEQ BP3 + CMP R1, #5 + BEQ BP3 + CMP R1, #6 + BEQ BP3 +BP2 DSB + LDR R0, =0x20000000 + LDR R1, =0x05fa0004 + STR R1, [R0] + LDR R1, =0xe000ed00 + LDR R0, =0x05fa0004 + STR R0, [R1, #0xC] + DSB + B . +BP3 LDR R0, =0x20000000 + LDR R1, [R0] + LDR R0, =0x05fa0004 + CMP R0, R1 + BEQ BP4 + BX LR +BP4 LDR R0, =0x40088100 + LDR R1, =0x00000001 + STR R1, [R0] + LDR R0, =0x20000000 + LDR R1, =0x0 + STR R1, [R0] + BX LR + ENDP + +; Dummy Exception Handlers +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP + +HardFault_Handler PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP + +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP + +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP + +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + EXPORT LVD_BOD_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT EVWUP_IRQHandler [WEAK] + EXPORT EXTI0_1_IRQHandler [WEAK] + EXPORT EXTI2_3_IRQHandler [WEAK] + EXPORT EXTI4_15_IRQHandler [WEAK] + EXPORT COMP_DAC_IRQHandler [WEAK] + EXPORT ADC_IRQHandler [WEAK] + EXPORT AES_IRQHandler [WEAK] + EXPORT LCD_IRQHandler [WEAK] + EXPORT GPTM0_IRQHandler [WEAK] + EXPORT SCTM0_IRQHandler [WEAK] + EXPORT SCTM1_IRQHandler [WEAK] + EXPORT PWM0_IRQHandler [WEAK] + EXPORT PWM1_IRQHandler [WEAK] + EXPORT BFTM0_IRQHandler [WEAK] + EXPORT BFTM1_IRQHandler [WEAK] + EXPORT I2C0_IRQHandler [WEAK] + EXPORT I2C1_IRQHandler [WEAK] + EXPORT SPI0_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT USART0_IRQHandler [WEAK] + EXPORT USART1_IRQHandler [WEAK] + EXPORT UART0_IRQHandler [WEAK] + EXPORT UART1_IRQHandler [WEAK] + EXPORT SCI_IRQHandler [WEAK] + EXPORT I2S_IRQHandler [WEAK] + EXPORT USB_IRQHandler [WEAK] + EXPORT PDMA_CH0_1_IRQHandler [WEAK] + EXPORT PDMA_CH2_5_IRQHandler [WEAK] + +LVD_BOD_IRQHandler +RTC_IRQHandler +FLASH_IRQHandler +EVWUP_IRQHandler +EXTI0_1_IRQHandler +EXTI2_3_IRQHandler +EXTI4_15_IRQHandler +COMP_DAC_IRQHandler +ADC_IRQHandler +AES_IRQHandler +LCD_IRQHandler +GPTM0_IRQHandler +SCTM0_IRQHandler +SCTM1_IRQHandler +PWM0_IRQHandler +PWM1_IRQHandler +BFTM0_IRQHandler +BFTM1_IRQHandler +I2C0_IRQHandler +I2C1_IRQHandler +SPI0_IRQHandler +SPI1_IRQHandler +USART0_IRQHandler +USART1_IRQHandler +UART0_IRQHandler +UART1_IRQHandler +SCI_IRQHandler +I2S_IRQHandler +USB_IRQHandler +PDMA_CH0_1_IRQHandler +PDMA_CH2_5_IRQHandler + B . + ENDP + + ALIGN + +;******************************************************************************* +; User Stack and Heap initialization +;******************************************************************************* + IF :DEF:__MICROLIB + + EXPORT __HT_check_heap + EXPORT __HT_check_sp + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, = (Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + + ENDIF + + END diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f59746.s b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f59746.s new file mode 100644 index 0000000000..cbaf7f3ee1 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f59746.s @@ -0,0 +1,350 @@ +;/*---------------------------------------------------------------------------------------------------------*/ +;/* Holtek Semiconductor Inc. */ +;/* */ +;/* Copyright (C) Holtek Semiconductor Inc. */ +;/* All rights reserved. */ +;/* */ +;/*----------------------------------------------------------------------------------------------------------- +; File Name : startup_ht32f5xxxx_05.s +; Version : $Rev:: 6993 $ +; Date : $Date:: 2023-06-26 #$ +; Description : Startup code. +;-----------------------------------------------------------------------------------------------------------*/ + +; Supported Device +; ======================================== +; HT32F57331, HT32F57341 +; HT32F57342, HT32F57352 +; HT32F59741 +; HT32F5828 +; HT32F67742 +; HT32F59746 + +;/* <<< Use Configuration Wizard in Context Menu >>> */ + +;// HT32 Device +;// Select HT32 Device for the assembly setting. +;// Notice that the project's Asm Define has the higher priority. +;// <0=> By Project Asm Define +;// <13=> HT32F57331/41 +;// <14=> HT32F57342/52 +;// <13=> HT32F59741 +;// <14=> HT32F5828 +;// <13=> HT32F67742 +;// <13=> HT32F59746 +USE_HT32_CHIP_SET EQU 13 ; Notice that the project's Asm Define has the higher priority. + +_HT32FWID EQU 0xFFFFFFFF +;_HT32FWID EQU 0x00057331 +;_HT32FWID EQU 0x00057341 +;_HT32FWID EQU 0x00057342 +;_HT32FWID EQU 0x00057352 +;_HT32FWID EQU 0x00059741 +;_HT32FWID EQU 0x00005828 +;_HT32FWID EQU 0x00067742 +;_HT32FWID EQU 0x00059746 + +HT32F57331_41 EQU 13 +HT32F57342_52 EQU 14 +HT32F59741 EQU 13 +HT32F5828 EQU 14 +HT32F67742 EQU 13 +HT32F59746 EQU 13 + + IF USE_HT32_CHIP_SET=0 + ; Use project's Asm Define setting (default) + ELSE + IF :DEF:USE_HT32_CHIP + ; Use project's Asm Define setting (higher priority than the "USE_HT32_CHIP_SET") + ELSE + ; Use "USE_HT32_CHIP_SET" in the "startup_ht32xxxxx_xx.s" file +USE_HT32_CHIP EQU USE_HT32_CHIP_SET + ENDIF + ENDIF + +; Amount of memory (in bytes) allocated for Stack and Heap +; Tailor those values to your application needs +;// Stack Size (in Bytes, must 8 byte aligned) <0-16384:8> +Stack_Size EQU 512 + + AREA STACK, NOINIT, READWRITE, ALIGN = 3 +__HT_check_sp +Stack_Mem SPACE Stack_Size +__initial_sp + +;// Heap Size (in Bytes) <0-16384:8> +Heap_Size EQU 0 + + AREA HEAP, NOINIT, READWRITE, ALIGN = 3 +__HT_check_heap +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + PRESERVE8 + THUMB + +;******************************************************************************* +; Fill-up the Vector Table entries with the exceptions ISR address +;******************************************************************************* + AREA RESET, CODE, READONLY + EXPORT __Vectors +_RESERVED EQU 0xFFFFFFFF +__Vectors + DCD __initial_sp ; ---, 00, 0x000, Top address of Stack + DCD Reset_Handler ; ---, 01, 0x004, Reset Handler + DCD NMI_Handler ; -14, 02, 0x008, NMI Handler + DCD HardFault_Handler ; -13, 03, 0x00C, Hard Fault Handler + DCD _RESERVED ; ---, 04, 0x010, Reserved + DCD _RESERVED ; ---, 05, 0x014, Reserved + DCD _RESERVED ; ---, 06, 0x018, Reserved + DCD _RESERVED ; ---, 07, 0x01C, Reserved + DCD _HT32FWID ; ---, 08, 0x020, Reserved + DCD _RESERVED ; ---, 09, 0x024, Reserved + DCD _RESERVED ; ---, 10, 0x028, Reserved + DCD SVC_Handler ; -05, 11, 0x02C, SVC Handler + DCD _RESERVED ; ---, 12, 0x030, Reserved + DCD _RESERVED ; ---, 13, 0x034, Reserved + DCD PendSV_Handler ; -02, 14, 0x038, PendSV Handler + DCD SysTick_Handler ; -01, 15, 0x03C, SysTick Handler + + ; External Interrupt Handler + DCD LVD_BOD_IRQHandler ; 00, 16, 0x040, + DCD RTC_IRQHandler ; 01, 17, 0x044, + DCD FLASH_IRQHandler ; 02, 18, 0x048, + DCD EVWUP_IRQHandler ; 03, 19, 0x04C, + DCD EXTI0_1_IRQHandler ; 04, 20, 0x050, + DCD EXTI2_3_IRQHandler ; 05, 21, 0x054, + DCD EXTI4_15_IRQHandler ; 06, 22, 0x058, + IF (USE_HT32_CHIP=HT32F57331_41) + DCD _RESERVED ; 07, 23, 0x05C, + ENDIF + IF (USE_HT32_CHIP=HT32F57342_52) + DCD COMP_DAC_IRQHandler ; 07, 23, 0x05C, + ENDIF + DCD ADC_IRQHandler ; 08, 24, 0x060, + IF (USE_HT32_CHIP=HT32F57331_41) + DCD _RESERVED ; 09, 25, 0x064, + ENDIF + IF (USE_HT32_CHIP=HT32F57342_52) + DCD AES_IRQHandler ; 09, 25, 0x064, + ENDIF + DCD _RESERVED ; 10, 26, 0x068, + DCD LCD_IRQHandler ; 11, 27, 0x06C, + DCD GPTM0_IRQHandler ; 12, 28, 0x070, + IF (USE_HT32_CHIP=HT32F57331_41) + DCD _RESERVED ; 13, 29, 0x074, + DCD _RESERVED ; 14, 30, 0x078, + ENDIF + IF (USE_HT32_CHIP=HT32F57342_52) + DCD SCTM0_IRQHandler ; 13, 29, 0x074, + DCD SCTM1_IRQHandler ; 14, 30, 0x078, + ENDIF + DCD PWM0_IRQHandler ; 15, 31, 0x07C, + DCD PWM1_IRQHandler ; 16, 32, 0x080, + DCD BFTM0_IRQHandler ; 17, 33, 0x084, + DCD BFTM1_IRQHandler ; 18, 34, 0x088, + DCD I2C0_IRQHandler ; 19, 35, 0x08C, + DCD I2C1_IRQHandler ; 20, 36, 0x090, + DCD SPI0_IRQHandler ; 21, 37, 0x094, + DCD SPI1_IRQHandler ; 22, 38, 0x098, + DCD USART0_IRQHandler ; 23, 39, 0x09C, + DCD _RESERVED ; 24, 40, 0x0A0, + DCD UART0_IRQHandler ; 25, 41, 0x0A4, + DCD UART1_IRQHandler ; 26, 42, 0x0A8, + DCD SCI_IRQHandler ; 27, 43, 0x0AC, + DCD I2S_IRQHandler ; 28, 44, 0x0B0, + DCD USB_IRQHandler ; 29, 45, 0x0B4, + IF (USE_HT32_CHIP=HT32F57331_41) + DCD _RESERVED ; 30, 46, 0x0B8, + DCD _RESERVED ; 31, 47, 0x0BC, + ENDIF + IF (USE_HT32_CHIP=HT32F57342_52) + DCD PDMA_CH0_1_IRQHandler ; 30, 46, 0x0B8, + DCD PDMA_CH2_5_IRQHandler ; 31, 47, 0x0BC, + ENDIF + +; Reset handler routine +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + LDR R0, =BootProcess + BLX R0 + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +BootProcess PROC + LDR R0, =0x40080300 + LDR R1,[R0, #0x10] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x14] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x18] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x1C] + CMP R1, #0 + BEQ BP2 +BP1 LDR R0, =0x40080180 + LDR R1,[R0, #0xC] + LSLS R1, R1, #4 + LSRS R1, R1, #20 + CMP R1, #0 + BEQ BP3 + CMP R1, #5 + BEQ BP3 + CMP R1, #6 + BEQ BP3 +BP2 DSB + LDR R0, =0x20000000 + LDR R1, =0x05fa0004 + STR R1, [R0] + LDR R1, =0xe000ed00 + LDR R0, =0x05fa0004 + STR R0, [R1, #0xC] + DSB + B . +BP3 LDR R0, =0x20000000 + LDR R1, [R0] + LDR R0, =0x05fa0004 + CMP R0, R1 + BEQ BP4 + BX LR +BP4 LDR R0, =0x40088100 + LDR R1, =0x00000001 + STR R1, [R0] + LDR R0, =0x20000000 + LDR R1, =0x0 + STR R1, [R0] + BX LR + ENDP + +; Dummy Exception Handlers +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP + +HardFault_Handler PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP + +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP + +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP + +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + EXPORT LVD_BOD_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT EVWUP_IRQHandler [WEAK] + EXPORT EXTI0_1_IRQHandler [WEAK] + EXPORT EXTI2_3_IRQHandler [WEAK] + EXPORT EXTI4_15_IRQHandler [WEAK] + EXPORT COMP_DAC_IRQHandler [WEAK] + EXPORT ADC_IRQHandler [WEAK] + EXPORT AES_IRQHandler [WEAK] + EXPORT LCD_IRQHandler [WEAK] + EXPORT GPTM0_IRQHandler [WEAK] + EXPORT SCTM0_IRQHandler [WEAK] + EXPORT SCTM1_IRQHandler [WEAK] + EXPORT PWM0_IRQHandler [WEAK] + EXPORT PWM1_IRQHandler [WEAK] + EXPORT BFTM0_IRQHandler [WEAK] + EXPORT BFTM1_IRQHandler [WEAK] + EXPORT I2C0_IRQHandler [WEAK] + EXPORT I2C1_IRQHandler [WEAK] + EXPORT SPI0_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT USART0_IRQHandler [WEAK] + EXPORT USART1_IRQHandler [WEAK] + EXPORT UART0_IRQHandler [WEAK] + EXPORT UART1_IRQHandler [WEAK] + EXPORT SCI_IRQHandler [WEAK] + EXPORT I2S_IRQHandler [WEAK] + EXPORT USB_IRQHandler [WEAK] + EXPORT PDMA_CH0_1_IRQHandler [WEAK] + EXPORT PDMA_CH2_5_IRQHandler [WEAK] + +LVD_BOD_IRQHandler +RTC_IRQHandler +FLASH_IRQHandler +EVWUP_IRQHandler +EXTI0_1_IRQHandler +EXTI2_3_IRQHandler +EXTI4_15_IRQHandler +COMP_DAC_IRQHandler +ADC_IRQHandler +AES_IRQHandler +LCD_IRQHandler +GPTM0_IRQHandler +SCTM0_IRQHandler +SCTM1_IRQHandler +PWM0_IRQHandler +PWM1_IRQHandler +BFTM0_IRQHandler +BFTM1_IRQHandler +I2C0_IRQHandler +I2C1_IRQHandler +SPI0_IRQHandler +SPI1_IRQHandler +USART0_IRQHandler +USART1_IRQHandler +UART0_IRQHandler +UART1_IRQHandler +SCI_IRQHandler +I2S_IRQHandler +USB_IRQHandler +PDMA_CH0_1_IRQHandler +PDMA_CH2_5_IRQHandler + B . + ENDP + + ALIGN + +;******************************************************************************* +; User Stack and Heap initialization +;******************************************************************************* + IF :DEF:__MICROLIB + + EXPORT __HT_check_heap + EXPORT __HT_check_sp + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, = (Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + + ENDIF + + END diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f5xxxx_01.s b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f5xxxx_01.s new file mode 100644 index 0000000000..b11048b5e0 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f5xxxx_01.s @@ -0,0 +1,482 @@ +;/*---------------------------------------------------------------------------------------------------------*/ +;/* Holtek Semiconductor Inc. */ +;/* */ +;/* Copyright (C) Holtek Semiconductor Inc. */ +;/* All rights reserved. */ +;/* */ +;/*----------------------------------------------------------------------------------------------------------- +; File Name : startup_ht32f5xxxx_01.s +; Version : $Rev:: 6953 $ +; Date : $Date:: 2023-05-30 #$ +; Description : Startup code. +;-----------------------------------------------------------------------------------------------------------*/ + +; Supported Device +; ======================================== +; HT32F52220, HT32F52230 +; HT32F52231, HT32F52241 +; HT32F52331, HT32F52341 +; HT32F52342, HT32F52352 +; HT32F52243, HT32F52253 +; HT32F0008 +; HT32F52344, HT32F52354 +; HT32F0006 +; HT32F61352 +; HT50F32003 +; HT32F62030, HT32F62040, HT32F62050 +; HT32F67741 +; HT32F67232 +; HT32F67233 + +;/* <<< Use Configuration Wizard in Context Menu >>> */ + +;// HT32 Device +;// Select HT32 Device for the assembly setting. +;// Notice that the project's Asm Define has the higher priority. +;// <0=> By Project Asm Define +;// <1=> HT32F52220/30 +;// <2=> HT32F52231/41 +;// <3=> HT32F52331/41 +;// <4=> HT32F52342/52 +;// <5=> HT32F52243/53 +;// <6=> HT32F0008 +;// <9=> HT32F52344/54 +;// <10=> HT32F0006 +;// <10=> HT32F61352 +;// <4=> HT50F32003 +;// <2=> HT32F67741 +;// <1=> HT32F67232 +;// <1=> HT32F67233 +;// <1=> HT32F62030 +;// <2=> HT32F62040 +;// <5=> HT32F62050 +USE_HT32_CHIP_SET EQU 0 ; Notice that the project's Asm Define has the higher priority. + +_HT32FWID EQU 0xFFFFFFFF +;_HT32FWID EQU 0x00052220 +;_HT32FWID EQU 0x00052230 +;_HT32FWID EQU 0x00052231 +;_HT32FWID EQU 0x00052241 +;_HT32FWID EQU 0x00052331 +;_HT32FWID EQU 0x00052341 +;_HT32FWID EQU 0x00052342 +;_HT32FWID EQU 0x00052352 +;_HT32FWID EQU 0x00052243 +;_HT32FWID EQU 0x00052253 +;_HT32FWID EQU 0x00000008 +;_HT32FWID EQU 0x00052344 +;_HT32FWID EQU 0x00052354 +;_HT32FWID EQU 0x00000006 +;_HT32FWID EQU 0x00061352 +;_HT32FWID EQU 0x00032003 +;_HT32FWID EQU 0x00062030 +;_HT32FWID EQU 0x00062040 +;_HT32FWID EQU 0x00062050 +;_HT32FWID EQU 0x00067741 +;_HT32FWID EQU 0x00067232 +;_HT32FWID EQU 0x00067233 + +HT32F52220_30 EQU 1 +HT32F52231_41 EQU 2 +HT32F52331_41 EQU 3 +HT32F52342_52 EQU 4 +HT32F52243_53 EQU 5 +HT32F0008 EQU 6 +HT32F52344_54 EQU 9 +HT32F0006 EQU 10 +HT32F61352 EQU 10 +HT50F32003 EQU 4 +HT32F62030 EQU 1 +HT32F62040 EQU 2 +HT32F62050 EQU 5 +HT32F67741 EQU 2 +HT32F67232 EQU 1 +HT32F67233 EQU 1 + + IF USE_HT32_CHIP_SET=0 + ; Use project's Asm Define setting (default) + ELSE + IF :DEF:USE_HT32_CHIP + ; Use project's Asm Define setting (higher priority than the "USE_HT32_CHIP_SET") + ELSE + ; Use "USE_HT32_CHIP_SET" in the "startup_ht32xxxxx_xx.s" file +USE_HT32_CHIP EQU USE_HT32_CHIP_SET + ENDIF + ENDIF + +; Amount of memory (in bytes) allocated for Stack and Heap +; Tailor those values to your application needs +;// Stack Size (in Bytes, must 8 byte aligned) <0-16384:8> +Stack_Size EQU 512 + + AREA STACK, NOINIT, READWRITE, ALIGN = 3 +__HT_check_sp +Stack_Mem SPACE Stack_Size +__initial_sp + +;// Heap Size (in Bytes) <0-16384:8> +Heap_Size EQU 0 + + AREA HEAP, NOINIT, READWRITE, ALIGN = 3 +__HT_check_heap +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + PRESERVE8 + THUMB + +;******************************************************************************* +; Fill-up the Vector Table entries with the exceptions ISR address +;******************************************************************************* + AREA RESET, CODE, READONLY + EXPORT __Vectors +_RESERVED EQU 0xFFFFFFFF +__Vectors + DCD __initial_sp ; ---, 00, 0x000, Top address of Stack + DCD Reset_Handler ; ---, 01, 0x004, Reset Handler + DCD NMI_Handler ; -14, 02, 0x008, NMI Handler + DCD HardFault_Handler ; -13, 03, 0x00C, Hard Fault Handler + DCD _RESERVED ; ---, 04, 0x010, Reserved + DCD _RESERVED ; ---, 05, 0x014, Reserved + DCD _RESERVED ; ---, 06, 0x018, Reserved + DCD _RESERVED ; ---, 07, 0x01C, Reserved + DCD _HT32FWID ; ---, 08, 0x020, Reserved + DCD _RESERVED ; ---, 09, 0x024, Reserved + DCD _RESERVED ; ---, 10, 0x028, Reserved + DCD SVC_Handler ; -05, 11, 0x02C, SVC Handler + DCD _RESERVED ; ---, 12, 0x030, Reserved + DCD _RESERVED ; ---, 13, 0x034, Reserved + DCD PendSV_Handler ; -02, 14, 0x038, PendSV Handler + DCD SysTick_Handler ; -01, 15, 0x03C, SysTick Handler + + ; External Interrupt Handler + DCD LVD_BOD_IRQHandler ; 00, 16, 0x040, + IF (USE_HT32_CHIP=HT32F52220_30) + DCD _RESERVED ; 01, 17, 0x044, + ELSE + DCD RTC_IRQHandler ; 01, 17, 0x044, + ENDIF + DCD FLASH_IRQHandler ; 02, 18, 0x048, + DCD EVWUP_IRQHandler ; 03, 19, 0x04C, + DCD EXTI0_1_IRQHandler ; 04, 20, 0x050, + DCD EXTI2_3_IRQHandler ; 05, 21, 0x054, + DCD EXTI4_15_IRQHandler ; 06, 22, 0x058, + IF (USE_HT32_CHIP=HT32F52342_52) || (USE_HT32_CHIP=HT32F52344_54) + DCD COMP_IRQHandler ; 07, 23, 0x05C, + ELSE + DCD _RESERVED ; 07, 23, 0x05C, + ENDIF + IF (USE_HT32_CHIP=HT32F0008) + DCD _RESERVED ; 08, 24, 0x060, + ELSE + DCD ADC_IRQHandler ; 08, 24, 0x060, + ENDIF + IF (USE_HT32_CHIP=HT32F52243_53) + DCD I2C2_IRQHandler ; 09, 25, 0x064, + ELSE + DCD _RESERVED ; 09, 25, 0x064, + ENDIF + IF (USE_HT32_CHIP=HT32F52220_30) || (USE_HT32_CHIP=HT32F0008) || (USE_HT32_CHIP=HT32F0006) + DCD _RESERVED ; 10, 26, 0x068, + ELSE + DCD MCTM0_IRQHandler ; 10, 26, 0x068, + ENDIF + IF (USE_HT32_CHIP=HT32F52342_52) + DCD GPTM1_IRQHandler ; 11, 27, 0x06C, + ELSE + DCD _RESERVED ; 11, 27, 0x06C, + ENDIF + DCD GPTM0_IRQHandler ; 12, 28, 0x070, + IF (USE_HT32_CHIP=HT32F0008) + DCD _RESERVED ; 13, 29, 0x074, + DCD _RESERVED ; 14, 30, 0x078, + ELSE + DCD SCTM0_IRQHandler ; 13, 29, 0x074, + DCD SCTM1_IRQHandler ; 14, 30, 0x078, + ENDIF + IF (USE_HT32_CHIP=HT32F52231_41) || (USE_HT32_CHIP=HT32F52331_41) || (USE_HT32_CHIP=HT32F52243_53) || (USE_HT32_CHIP=HT32F0006) + DCD SCTM2_IRQHandler ; 15, 31, 0x07C, + DCD SCTM3_IRQHandler ; 16, 32, 0x080, + ENDIF + IF (USE_HT32_CHIP=HT32F0008) + DCD PWM0_IRQHandler ; 15, 31, 0x07C, + DCD PWM1_IRQHandler ; 16, 32, 0x080, + ENDIF + IF (USE_HT32_CHIP=HT32F52220_30) || (USE_HT32_CHIP=HT32F52342_52) || (USE_HT32_CHIP=HT32F52344_54) + DCD _RESERVED ; 15, 31, 0x07C, + DCD _RESERVED ; 16, 32, 0x080, + ENDIF + DCD BFTM0_IRQHandler ; 17, 33, 0x084, + IF (USE_HT32_CHIP=HT32F52220_30) + DCD _RESERVED ; 18, 34, 0x088, + ELSE + DCD BFTM1_IRQHandler ; 18, 34, 0x088, + ENDIF + DCD I2C0_IRQHandler ; 19, 35, 0x08C, + IF (USE_HT32_CHIP=HT32F52220_30) || (USE_HT32_CHIP=HT32F0008) || (USE_HT32_CHIP=HT32F52344_54) || (USE_HT32_CHIP=HT32F0006) + DCD _RESERVED ; 20, 36, 0x090, + ELSE + DCD I2C1_IRQHandler ; 20, 36, 0x090, + ENDIF + DCD SPI0_IRQHandler ; 21, 37, 0x094, + IF (USE_HT32_CHIP=HT32F52220_30) || (USE_HT32_CHIP=HT32F0008) + DCD _RESERVED ; 22, 38, 0x098, + ELSE + IF (USE_HT32_CHIP=HT32F0006) + DCD QSPI_IRQHandler ; 22, 38, 0x098, + ELSE + DCD SPI1_IRQHandler ; 22, 38, 0x098, + ENDIF + ENDIF + IF (USE_HT32_CHIP=HT32F52344_54) + DCD _RESERVED ; 23, 39, 0x09C, + ELSE + DCD USART0_IRQHandler ; 23, 39, 0x09C, + ENDIF + IF (USE_HT32_CHIP=HT32F52342_52) || (USE_HT32_CHIP=HT32F52243_53) + DCD USART1_IRQHandler ; 24, 40, 0x0A0, + ELSE + DCD _RESERVED ; 24, 40, 0x0A0, + ENDIF + DCD UART0_IRQHandler ; 25, 41, 0x0A4, + IF (USE_HT32_CHIP=HT32F52220_30) || (USE_HT32_CHIP=HT32F0008) || (USE_HT32_CHIP=HT32F0006) + DCD _RESERVED ; 26, 42, 0x0A8, + ELSE + DCD UART1_IRQHandler ; 26, 42, 0x0A8, + ENDIF + IF (USE_HT32_CHIP=HT32F52331_41) || (USE_HT32_CHIP=HT32F52342_52) + DCD SCI_IRQHandler ; 27, 43, 0x0AC, + ENDIF + IF (USE_HT32_CHIP=HT32F52243_53) + DCD UART2_IRQHandler ; 27, 43, 0x0AC, + ENDIF + IF (USE_HT32_CHIP=HT32F0006) + DCD MIDI_IRQHandler ; 27, 43, 0x0AC, + ENDIF + IF (USE_HT32_CHIP=HT32F0008) || (USE_HT32_CHIP=HT32F52344_54) + DCD _RESERVED ; 27, 43, 0xAC, + ENDIF + IF (USE_HT32_CHIP=HT32F52342_52) || (USE_HT32_CHIP=HT32F0006) + DCD I2S_IRQHandler ; 28, 44, 0x0B0, + ENDIF + IF (USE_HT32_CHIP=HT32F52331_41) || (USE_HT32_CHIP=HT32F52344_54) + DCD _RESERVED ; 28, 44, 0x0B0, + ENDIF + IF (USE_HT32_CHIP=HT32F52243_53) + DCD UART3_IRQHandler ; 28, 44, 0x0B0, + ENDIF + IF (USE_HT32_CHIP=HT32F0008) + DCD AES_IRQHandler ; 28, 44, 0x0B0, + ENDIF + IF (USE_HT32_CHIP=HT32F52331_41) || (USE_HT32_CHIP=HT32F52342_52) || (USE_HT32_CHIP=HT32F0008) || (USE_HT32_CHIP=HT32F52344_54) || (USE_HT32_CHIP=HT32F0006) + DCD USB_IRQHandler ; 29, 45, 0x0B4, + ENDIF + IF (USE_HT32_CHIP=HT32F52243_53) + DCD _RESERVED ; 29, 45, 0x0B4, + ENDIF + IF (USE_HT32_CHIP=HT32F52342_52) || (USE_HT32_CHIP=HT32F52243_53) || (USE_HT32_CHIP=HT32F0008) || (USE_HT32_CHIP=HT32F52344_54) || (USE_HT32_CHIP=HT32F0006) + DCD PDMA_CH0_1_IRQHandler ; 30, 46, 0x0B8, + DCD PDMA_CH2_5_IRQHandler ; 31, 47, 0x0BC, + ENDIF + +; Reset handler routine +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + LDR R0, =BootProcess + BLX R0 + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +BootProcess PROC + LDR R0, =0x40080300 + LDR R1,[R0, #0x10] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x14] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x18] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x1C] + CMP R1, #0 + BEQ BP2 +BP1 LDR R0, =0x40080180 + LDR R1,[R0, #0xC] + LSLS R1, R1, #4 + LSRS R1, R1, #20 + CMP R1, #0 + BEQ BP3 + CMP R1, #5 + BEQ BP3 + CMP R1, #6 + BEQ BP3 +BP2 DSB + LDR R0, =0x20000000 + LDR R1, =0x05fa0004 + STR R1, [R0] + LDR R1, =0xe000ed00 + LDR R0, =0x05fa0004 + STR R0, [R1, #0xC] + DSB + B . +BP3 LDR R0, =0x20000000 + LDR R1, [R0] + LDR R0, =0x05fa0004 + CMP R0, R1 + BEQ BP4 + BX LR +BP4 LDR R0, =0x40088100 + LDR R1, =0x00000001 + STR R1, [R0] + LDR R0, =0x20000000 + LDR R1, =0x0 + STR R1, [R0] + BX LR + ENDP + +; Dummy Exception Handlers +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP + +HardFault_Handler PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP + +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP + +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP + +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + EXPORT LVD_BOD_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT EVWUP_IRQHandler [WEAK] + EXPORT EXTI0_1_IRQHandler [WEAK] + EXPORT EXTI2_3_IRQHandler [WEAK] + EXPORT EXTI4_15_IRQHandler [WEAK] + EXPORT COMP_IRQHandler [WEAK] + EXPORT ADC_IRQHandler [WEAK] + EXPORT MCTM0_IRQHandler [WEAK] + EXPORT GPTM1_IRQHandler [WEAK] + EXPORT GPTM0_IRQHandler [WEAK] + EXPORT SCTM0_IRQHandler [WEAK] + EXPORT SCTM1_IRQHandler [WEAK] + EXPORT SCTM2_IRQHandler [WEAK] + EXPORT SCTM3_IRQHandler [WEAK] + EXPORT PWM0_IRQHandler [WEAK] + EXPORT PWM1_IRQHandler [WEAK] + EXPORT BFTM0_IRQHandler [WEAK] + EXPORT BFTM1_IRQHandler [WEAK] + EXPORT I2C0_IRQHandler [WEAK] + EXPORT I2C1_IRQHandler [WEAK] + EXPORT I2C2_IRQHandler [WEAK] + EXPORT SPI0_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT QSPI_IRQHandler [WEAK] + EXPORT USART0_IRQHandler [WEAK] + EXPORT USART1_IRQHandler [WEAK] + EXPORT UART0_IRQHandler [WEAK] + EXPORT UART1_IRQHandler [WEAK] + EXPORT UART2_IRQHandler [WEAK] + EXPORT UART3_IRQHandler [WEAK] + EXPORT SCI_IRQHandler [WEAK] + EXPORT MIDI_IRQHandler [WEAK] + EXPORT I2S_IRQHandler [WEAK] + EXPORT AES_IRQHandler [WEAK] + EXPORT USB_IRQHandler [WEAK] + EXPORT PDMA_CH0_1_IRQHandler [WEAK] + EXPORT PDMA_CH2_5_IRQHandler [WEAK] + +LVD_BOD_IRQHandler +RTC_IRQHandler +FLASH_IRQHandler +EVWUP_IRQHandler +EXTI0_1_IRQHandler +EXTI2_3_IRQHandler +EXTI4_15_IRQHandler +COMP_IRQHandler +ADC_IRQHandler +MCTM0_IRQHandler +GPTM1_IRQHandler +GPTM0_IRQHandler +SCTM0_IRQHandler +SCTM1_IRQHandler +SCTM2_IRQHandler +SCTM3_IRQHandler +PWM0_IRQHandler +PWM1_IRQHandler +BFTM0_IRQHandler +BFTM1_IRQHandler +I2C0_IRQHandler +I2C1_IRQHandler +I2C2_IRQHandler +SPI0_IRQHandler +SPI1_IRQHandler +QSPI_IRQHandler +USART0_IRQHandler +USART1_IRQHandler +UART0_IRQHandler +UART1_IRQHandler +UART2_IRQHandler +UART3_IRQHandler +SCI_IRQHandler +MIDI_IRQHandler +I2S_IRQHandler +AES_IRQHandler +USB_IRQHandler +PDMA_CH0_1_IRQHandler +PDMA_CH2_5_IRQHandler + B . + ENDP + + ALIGN + +;******************************************************************************* +; User Stack and Heap initialization +;******************************************************************************* + IF :DEF:__MICROLIB + + EXPORT __HT_check_heap + EXPORT __HT_check_sp + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, = (Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + + ENDIF + + END diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f5xxxx_02.s b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f5xxxx_02.s new file mode 100644 index 0000000000..de2009c868 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f5xxxx_02.s @@ -0,0 +1,327 @@ +;/*---------------------------------------------------------------------------------------------------------*/ +;/* Holtek Semiconductor Inc. */ +;/* */ +;/* Copyright (C) Holtek Semiconductor Inc. */ +;/* All rights reserved. */ +;/* */ +;/*----------------------------------------------------------------------------------------------------------- +; File Name : startup_ht32f5xxxx_02.s +; Version : $Rev:: 7119 $ +; Date : $Date:: 2023-08-15 #$ +; Description : Startup code. +;-----------------------------------------------------------------------------------------------------------*/ + +; Supported Device +; ======================================== +; HT32F50220, HT32F50230 +; HT32F50231, HT32F50241 +; HT50F32002 +; HT32F59041 +; HF5032 +; HT32F61641 +; HT32F59046 +; HT32F61041 + +;/* <<< Use Configuration Wizard in Context Menu >>> */ + +;// HT32 Device +;// Select HT32 Device for the assembly setting. +;// Notice that the project's Asm Define has the higher priority. +;// <0=> By Project Asm Define +;// <7=> HT32F50220/30 +;// <8=> HT32F50231/41 +;// <7=> HT50F32002 +;// <8=> HT32F59041 +;// <7=> HF5032 +;// <8=> HT32F61641 +;// <8=> HT32F59046 +;// <8=> HT32F61041 +USE_HT32_CHIP_SET EQU 0 ; Notice that the project's Asm Define has the higher priority. + +_HT32FWID EQU 0xFFFFFFFF +;_HT32FWID EQU 0x00050220 +;_HT32FWID EQU 0x00050230 +;_HT32FWID EQU 0x00050231 +;_HT32FWID EQU 0x00050241 +;_HT32FWID EQU 0x00032002 +;_HT32FWID EQU 0x00059041 +;_HT32FWID EQU 0x000F5032 +;_HT32FWID EQU 0x00061641 +;_HT32FWID EQU 0x00059046 +;_HT32FWID EQU 0x00061041 + +HT32F50220_30 EQU 7 +HT32F50231_41 EQU 8 +HT50F32002 EQU 7 +HT32F59041 EQU 8 +HF5032 EQU 7 +HT32F61641 EQU 8 +HT32F59046 EQU 8 +HT32F61041 EQU 8 + + IF USE_HT32_CHIP_SET=0 + ; Use project's Asm Define setting (default) + ELSE + IF :DEF:USE_HT32_CHIP + ; Use project's Asm Define setting (higher priority than the "USE_HT32_CHIP_SET") + ELSE + ; Use "USE_HT32_CHIP_SET" in the "startup_ht32xxxxx_xx.s" file +USE_HT32_CHIP EQU USE_HT32_CHIP_SET + ENDIF + ENDIF + +; Amount of memory (in bytes) allocated for Stack and Heap +; Tailor those values to your application needs +;// Stack Size (in Bytes, must 8 byte aligned) <0-4096:8> +Stack_Size EQU 512 + + AREA STACK, NOINIT, READWRITE, ALIGN = 3 +__HT_check_sp +Stack_Mem SPACE Stack_Size +__initial_sp + +;// Heap Size (in Bytes) <0-4096:8> +Heap_Size EQU 0 + + AREA HEAP, NOINIT, READWRITE, ALIGN = 3 +__HT_check_heap +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + PRESERVE8 + THUMB + +;******************************************************************************* +; Fill-up the Vector Table entries with the exceptions ISR address +;******************************************************************************* + AREA RESET, CODE, READONLY + EXPORT __Vectors +_RESERVED EQU 0xFFFFFFFF +__Vectors + DCD __initial_sp ; ---, 00, 0x000, Top address of Stack + DCD Reset_Handler ; ---, 01, 0x004, Reset Handler + DCD NMI_Handler ; -14, 02, 0x008, NMI Handler + DCD HardFault_Handler ; -13, 03, 0x00C, Hard Fault Handler + DCD _RESERVED ; ---, 04, 0x010, Reserved + DCD _RESERVED ; ---, 05, 0x014, Reserved + DCD _RESERVED ; ---, 06, 0x018, Reserved + DCD _RESERVED ; ---, 07, 0x01C, Reserved + DCD _HT32FWID ; ---, 08, 0x020, Reserved + DCD _RESERVED ; ---, 09, 0x024, Reserved + DCD _RESERVED ; ---, 10, 0x028, Reserved + DCD SVC_Handler ; -05, 11, 0x02C, SVC Handler + DCD _RESERVED ; ---, 12, 0x030, Reserved + DCD _RESERVED ; ---, 13, 0x034, Reserved + DCD PendSV_Handler ; -02, 14, 0x038, PendSV Handler + DCD SysTick_Handler ; -01, 15, 0x03C, SysTick Handler + + ; External Interrupt Handler + DCD LVD_BOD_IRQHandler ; 00, 16, 0x040, + DCD RTC_IRQHandler ; 01, 17, 0x044, + DCD FLASH_IRQHandler ; 02, 18, 0x048, + DCD EVWUP_IRQHandler ; 03, 19, 0x04C, + DCD EXTI0_1_IRQHandler ; 04, 20, 0x050, + DCD EXTI2_3_IRQHandler ; 05, 21, 0x054, + DCD EXTI4_15_IRQHandler ; 06, 22, 0x058, + DCD _RESERVED ; 07, 23, 0x05C, + DCD ADC_IRQHandler ; 08, 24, 0x060, + DCD _RESERVED ; 09, 25, 0x064, + IF (USE_HT32_CHIP=HT32F50220_30) + DCD _RESERVED ; 10, 26, 0x068, + ELSE + DCD MCTM0_IRQHandler ; 10, 26, 0x068, + ENDIF + DCD _RESERVED ; 11, 27, 0x06C, + DCD GPTM0_IRQHandler ; 12, 28, 0x070, + DCD _RESERVED ; 13, 29, 0x074, + DCD _RESERVED ; 14, 30, 0x078, + DCD PWM0_IRQHandler ; 15, 31, 0x07C, + DCD PWM1_IRQHandler ; 16, 32, 0x080, + DCD BFTM0_IRQHandler ; 17, 33, 0x084, + IF (USE_HT32_CHIP=HT32F50220_30) + DCD _RESERVED ; 18, 34, 0x088, + ELSE + DCD BFTM1_IRQHandler ; 18, 34, 0x088, + ENDIF + DCD I2C0_IRQHandler ; 19, 35, 0x08C, + IF (USE_HT32_CHIP=HT32F50220_30) + DCD _RESERVED ; 20, 36, 0x090, + ELSE + DCD I2C1_IRQHandler ; 20, 36, 0x090, + ENDIF + DCD SPI0_IRQHandler ; 21, 37, 0x094, + DCD SPI1_IRQHandler ; 22, 38, 0x098, + IF (USE_HT32_CHIP=HT32F50220_30) + DCD _RESERVED ; 23, 39, 0x09C, + ELSE + DCD USART0_IRQHandler ; 23, 39, 0x09C, + ENDIF + DCD _RESERVED ; 24, 40, 0x0A0, + DCD UART0_IRQHandler ; 25, 41, 0x0A4, + DCD UART1_IRQHandler ; 26, 42, 0x0A8, + +; Reset handler routine +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + LDR R0, =BootProcess + BLX R0 + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +BootProcess PROC + LDR R0, =0x40080300 + LDR R1,[R0, #0x10] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x14] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x18] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x1C] + CMP R1, #0 + BEQ BP2 +BP1 LDR R0, =0x40080180 + LDR R1,[R0, #0xC] + LSLS R1, R1, #4 + LSRS R1, R1, #20 + CMP R1, #0 + BEQ BP3 + CMP R1, #5 + BEQ BP3 + CMP R1, #6 + BEQ BP3 +BP2 DSB + LDR R0, =0x20000000 + LDR R1, =0x05fa0004 + STR R1, [R0] + LDR R1, =0xe000ed00 + LDR R0, =0x05fa0004 + STR R0, [R1, #0xC] + DSB + B . +BP3 LDR R0, =0x20000000 + LDR R1, [R0] + LDR R0, =0x05fa0004 + CMP R0, R1 + BEQ BP4 + BX LR +BP4 LDR R0, =0x40088100 + LDR R1, =0x00000001 + STR R1, [R0] + LDR R0, =0x20000000 + LDR R1, =0x0 + STR R1, [R0] + BX LR + ENDP + +; Dummy Exception Handlers +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP + +HardFault_Handler PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP + +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP + +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP + +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + EXPORT LVD_BOD_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT EVWUP_IRQHandler [WEAK] + EXPORT EXTI0_1_IRQHandler [WEAK] + EXPORT EXTI2_3_IRQHandler [WEAK] + EXPORT EXTI4_15_IRQHandler [WEAK] + EXPORT ADC_IRQHandler [WEAK] + EXPORT MCTM0_IRQHandler [WEAK] + EXPORT GPTM0_IRQHandler [WEAK] + EXPORT PWM0_IRQHandler [WEAK] + EXPORT PWM1_IRQHandler [WEAK] + EXPORT BFTM0_IRQHandler [WEAK] + EXPORT BFTM1_IRQHandler [WEAK] + EXPORT I2C0_IRQHandler [WEAK] + EXPORT I2C1_IRQHandler [WEAK] + EXPORT SPI0_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT USART0_IRQHandler [WEAK] + EXPORT UART0_IRQHandler [WEAK] + EXPORT UART1_IRQHandler [WEAK] + +LVD_BOD_IRQHandler +RTC_IRQHandler +FLASH_IRQHandler +EVWUP_IRQHandler +EXTI0_1_IRQHandler +EXTI2_3_IRQHandler +EXTI4_15_IRQHandler +ADC_IRQHandler +MCTM0_IRQHandler +GPTM0_IRQHandler +PWM0_IRQHandler +PWM1_IRQHandler +BFTM0_IRQHandler +BFTM1_IRQHandler +I2C0_IRQHandler +I2C1_IRQHandler +SPI0_IRQHandler +SPI1_IRQHandler +USART0_IRQHandler +UART0_IRQHandler +UART1_IRQHandler + B . + ENDP + + ALIGN + +;******************************************************************************* +; User Stack and Heap initialization +;******************************************************************************* + IF :DEF:__MICROLIB + + EXPORT __HT_check_heap + EXPORT __HT_check_sp + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, = (Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + + ENDIF + + END diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f5xxxx_03.s b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f5xxxx_03.s new file mode 100644 index 0000000000..1ff2f77f4b --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f5xxxx_03.s @@ -0,0 +1,403 @@ +;/*---------------------------------------------------------------------------------------------------------*/ +;/* Holtek Semiconductor Inc. */ +;/* */ +;/* Copyright (C) Holtek Semiconductor Inc. */ +;/* All rights reserved. */ +;/* */ +;/*----------------------------------------------------------------------------------------------------------- +; File Name : startup_ht32f5xxxx_03.s +; Version : $Rev:: 6877 $ +; Date : $Date:: 2023-05-04 #$ +; Description : Startup code. +;-----------------------------------------------------------------------------------------------------------*/ + +; Supported Device +; ======================================== +; HT32F0008 +; HT32F52142 +; HT32F52344, HT32F52354 +; HT32F52357, HT32F52367 +; HT50F3200T + +;/* <<< Use Configuration Wizard in Context Menu >>> */ + +;// HT32 Device +;// Select HT32 Device for the assembly setting. +;// Notice that the project's Asm Define has the higher priority. +;// <0=> By Project Asm Define +;// <6=> HT32F0008 +;// <6=> HT32F52142 +;// <9=> HT32F52344/54 +;// <11=> HT32F52357/67 +;// <11=> HT50F3200T +USE_HT32_CHIP_SET EQU 0 ; Notice that the project's Asm Define has the higher priority. + +_HT32FWID EQU 0xFFFFFFFF +;_HT32FWID EQU 0x00000008 +;_HT32FWID EQU 0x00052142 +;_HT32FWID EQU 0x00052344 +;_HT32FWID EQU 0x00052354 +;_HT32FWID EQU 0x00052357 +;_HT32FWID EQU 0x00052367 +;_HT32FWID EQU 0x0003200F + +HT32F0008 EQU 6 +HT32F52142 EQU 6 +HT32F52344_54 EQU 9 +HT32F52357_67 EQU 11 +HT50F3200T EQU 11 + + IF USE_HT32_CHIP_SET=0 + ; Use project's Asm Define setting (default) + ELSE + IF :DEF:USE_HT32_CHIP + ; Use project's Asm Define setting (higher priority than the "USE_HT32_CHIP_SET") + ELSE + ; Use "USE_HT32_CHIP_SET" in the "startup_ht32xxxxx_xx.s" file +USE_HT32_CHIP EQU USE_HT32_CHIP_SET + ENDIF + ENDIF + +; Amount of memory (in bytes) allocated for Stack and Heap +; Tailor those values to your application needs +;// Stack Size (in Bytes, must 8 byte aligned) <0-16384:8> +Stack_Size EQU 512 + + AREA STACK, NOINIT, READWRITE, ALIGN = 3 +__HT_check_sp +Stack_Mem SPACE Stack_Size +__initial_sp + +;// Heap Size (in Bytes) <0-16384:8> +Heap_Size EQU 0 + + AREA HEAP, NOINIT, READWRITE, ALIGN = 3 +__HT_check_heap +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + PRESERVE8 + THUMB + +;******************************************************************************* +; Fill-up the Vector Table entries with the exceptions ISR address +;******************************************************************************* + AREA RESET, CODE, READONLY + EXPORT __Vectors +_RESERVED EQU 0xFFFFFFFF +__Vectors + DCD __initial_sp ; ---, 00, 0x000, Top address of Stack + DCD Reset_Handler ; ---, 01, 0x004, Reset Handler + DCD NMI_Handler ; -14, 02, 0x008, NMI Handler + DCD HardFault_Handler ; -13, 03, 0x00C, Hard Fault Handler + DCD _RESERVED ; ---, 04, 0x010, Reserved + DCD _RESERVED ; ---, 05, 0x014, Reserved + DCD _RESERVED ; ---, 06, 0x018, Reserved + DCD _RESERVED ; ---, 07, 0x01C, Reserved + DCD _HT32FWID ; ---, 08, 0x020, Reserved + DCD _RESERVED ; ---, 09, 0x024, Reserved + DCD _RESERVED ; ---, 10, 0x028, Reserved + DCD SVC_Handler ; -05, 11, 0x02C, SVC Handler + DCD _RESERVED ; ---, 12, 0x030, Reserved + DCD _RESERVED ; ---, 13, 0x034, Reserved + DCD PendSV_Handler ; -02, 14, 0x038, PendSV Handler + DCD SysTick_Handler ; -01, 15, 0x03C, SysTick Handler + + ; External Interrupt Handler + DCD LVD_BOD_IRQHandler ; 00, 16, 0x040, + DCD RTC_IRQHandler ; 01, 17, 0x044, + DCD FLASH_IRQHandler ; 02, 18, 0x048, + DCD EVWUP_IRQHandler ; 03, 19, 0x04C, + DCD EXTI0_1_IRQHandler ; 04, 20, 0x050, + DCD EXTI2_3_IRQHandler ; 05, 21, 0x054, + DCD EXTI4_15_IRQHandler ; 06, 22, 0x058, + IF (USE_HT32_CHIP=HT32F0008) + DCD _RESERVED ; 07, 23, 0x05C, + ENDIF + IF (USE_HT32_CHIP=HT32F52344_54) + DCD COMP_IRQHandler ; 07, 23, 0x05C, + ENDIF + IF (USE_HT32_CHIP=HT32F52357_67) + DCD COMP_DAC_IRQHandler ; 07, 23, 0x05C, + ENDIF + IF (USE_HT32_CHIP=HT32F0008) + DCD _RESERVED ; 08, 24, 0x060, + ELSE + DCD ADC_IRQHandler ; 08, 24, 0x060, + ENDIF + IF (USE_HT32_CHIP=HT32F52357_67) + DCD AES_IRQHandler ; 09, 25, 0x064, + ELSE + DCD _RESERVED ; 09, 25, 0x064, + ENDIF + IF (USE_HT32_CHIP=HT32F0008) + DCD _RESERVED ; 10, 26, 0x068, + ELSE + DCD MCTM0_IRQHandler ; 10, 26, 0x068, + ENDIF + IF (USE_HT32_CHIP=HT32F52357_67) + DCD QSPI_IRQHandler ; 11, 27, 0x06C, + ELSE + DCD _RESERVED ; 11, 27, 0x06C, + ENDIF + DCD GPTM0_IRQHandler ; 12, 28, 0x070, + IF (USE_HT32_CHIP=HT32F0008) + DCD _RESERVED ; 13, 29, 0x074, + DCD _RESERVED ; 14, 30, 0x078, + ELSE + DCD SCTM0_IRQHandler ; 13, 29, 0x074, + DCD SCTM1_IRQHandler ; 14, 30, 0x078, + ENDIF + IF (USE_HT32_CHIP=HT32F0008) || (USE_HT32_CHIP=HT32F52357_67) + DCD PWM0_IRQHandler ; 15, 31, 0x07C, + DCD PWM1_IRQHandler ; 16, 32, 0x080, + ENDIF + IF (USE_HT32_CHIP=HT32F52344_54) + DCD _RESERVED ; 15, 31, 0x07C, + DCD _RESERVED ; 16, 32, 0x080, + ENDIF + DCD BFTM0_IRQHandler ; 17, 33, 0x084, + DCD BFTM1_IRQHandler ; 18, 34, 0x088, + DCD I2C0_IRQHandler ; 19, 35, 0x08C, + IF (USE_HT32_CHIP=HT32F0008) || (USE_HT32_CHIP=HT32F52344_54) + DCD _RESERVED ; 20, 36, 0x090, + ELSE + DCD I2C1_IRQHandler ; 20, 36, 0x090, + ENDIF + DCD SPI0_IRQHandler ; 21, 37, 0x094, + IF (USE_HT32_CHIP=HT32F0008) + DCD _RESERVED ; 22, 38, 0x098, + ELSE + DCD SPI1_IRQHandler ; 22, 38, 0x098, + ENDIF + IF (USE_HT32_CHIP=HT32F52344_54) + DCD _RESERVED ; 23, 39, 0x09C, + ELSE + DCD USART0_IRQHandler ; 23, 39, 0x09C, + ENDIF + IF (USE_HT32_CHIP=HT32F0008) + DCD _RESERVED ; 24, 40, 0x0A0, + DCD UART0_IRQHandler ; 25, 41, 0x0A4, + DCD _RESERVED ; 26, 42, 0x0A8, + ENDIF + IF (USE_HT32_CHIP=HT32F52344_54) + DCD _RESERVED ; 24, 40, 0x0A0, + DCD UART0_IRQHandler ; 25, 41, 0x0A4, + DCD UART1_IRQHandler ; 26, 42, 0x0A8, + ENDIF + IF (USE_HT32_CHIP=HT32F52357_67) + DCD USART1_IRQHandler ; 24, 40, 0x0A0, + DCD UART0_UART2_IRQHandler ; 25, 41, 0x0A4, + DCD UART1_UART3_IRQHandler ; 26, 42, 0x0A8, + ENDIF + IF (USE_HT32_CHIP=HT32F52357_67) + DCD SCI_IRQHandler ; 27, 43, 0xAC, + ELSE + DCD _RESERVED ; 27, 43, 0xAC, + ENDIF + IF (USE_HT32_CHIP=HT32F0008) + DCD AES_IRQHandler ; 28, 44, 0x0B0, + ENDIF + IF (USE_HT32_CHIP=HT32F52344_54) + DCD _RESERVED ; 28, 44, 0x0B0, + ENDIF + IF (USE_HT32_CHIP=HT32F52357_67) + DCD I2S_IRQHandler ; 28, 44, 0x0B0, + ENDIF + DCD USB_IRQHandler ; 29, 45, 0x0B4, + DCD PDMA_CH0_1_IRQHandler ; 30, 46, 0x0B8, + DCD PDMA_CH2_5_IRQHandler ; 31, 47, 0x0BC, + +; Reset handler routine +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + LDR R0, =BootProcess + BLX R0 + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +BootProcess PROC + LDR R0, =0x40080300 + LDR R1,[R0, #0x10] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x14] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x18] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x1C] + CMP R1, #0 + BEQ BP2 +BP1 LDR R0, =0x40080180 + LDR R1,[R0, #0xC] + LSLS R1, R1, #4 + LSRS R1, R1, #20 + CMP R1, #0 + BEQ BP3 + CMP R1, #5 + BEQ BP3 + CMP R1, #6 + BEQ BP3 +BP2 DSB + LDR R0, =0x20000000 + LDR R1, =0x05fa0004 + STR R1, [R0] + LDR R1, =0xe000ed00 + LDR R0, =0x05fa0004 + STR R0, [R1, #0xC] + DSB + B . +BP3 LDR R0, =0x20000000 + LDR R1, [R0] + LDR R0, =0x05fa0004 + CMP R0, R1 + BEQ BP4 + BX LR +BP4 LDR R0, =0x40088100 + LDR R1, =0x00000001 + STR R1, [R0] + LDR R0, =0x20000000 + LDR R1, =0x0 + STR R1, [R0] + BX LR + ENDP + +; Dummy Exception Handlers +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP + +HardFault_Handler PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP + +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP + +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP + +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + EXPORT LVD_BOD_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT EVWUP_IRQHandler [WEAK] + EXPORT EXTI0_1_IRQHandler [WEAK] + EXPORT EXTI2_3_IRQHandler [WEAK] + EXPORT EXTI4_15_IRQHandler [WEAK] + EXPORT COMP_IRQHandler [WEAK] + EXPORT COMP_DAC_IRQHandler [WEAK] + EXPORT ADC_IRQHandler [WEAK] + EXPORT MCTM0_IRQHandler [WEAK] + EXPORT GPTM0_IRQHandler [WEAK] + EXPORT SCTM0_IRQHandler [WEAK] + EXPORT SCTM1_IRQHandler [WEAK] + EXPORT PWM0_IRQHandler [WEAK] + EXPORT PWM1_IRQHandler [WEAK] + EXPORT BFTM0_IRQHandler [WEAK] + EXPORT BFTM1_IRQHandler [WEAK] + EXPORT I2C0_IRQHandler [WEAK] + EXPORT I2C1_IRQHandler [WEAK] + EXPORT SPI0_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT QSPI_IRQHandler [WEAK] + EXPORT USART0_IRQHandler [WEAK] + EXPORT USART1_IRQHandler [WEAK] + EXPORT UART0_IRQHandler [WEAK] + EXPORT UART1_IRQHandler [WEAK] + EXPORT UART0_UART2_IRQHandler [WEAK] + EXPORT UART1_UART3_IRQHandler [WEAK] + EXPORT SCI_IRQHandler [WEAK] + EXPORT I2S_IRQHandler [WEAK] + EXPORT AES_IRQHandler [WEAK] + EXPORT USB_IRQHandler [WEAK] + EXPORT PDMA_CH0_1_IRQHandler [WEAK] + EXPORT PDMA_CH2_5_IRQHandler [WEAK] + +LVD_BOD_IRQHandler +RTC_IRQHandler +FLASH_IRQHandler +EVWUP_IRQHandler +EXTI0_1_IRQHandler +EXTI2_3_IRQHandler +EXTI4_15_IRQHandler +COMP_IRQHandler +COMP_DAC_IRQHandler +ADC_IRQHandler +MCTM0_IRQHandler +GPTM0_IRQHandler +SCTM0_IRQHandler +SCTM1_IRQHandler +PWM0_IRQHandler +PWM1_IRQHandler +BFTM0_IRQHandler +BFTM1_IRQHandler +I2C0_IRQHandler +I2C1_IRQHandler +SPI0_IRQHandler +SPI1_IRQHandler +QSPI_IRQHandler +USART0_IRQHandler +USART1_IRQHandler +UART0_IRQHandler +UART1_IRQHandler +UART0_UART2_IRQHandler +UART1_UART3_IRQHandler +SCI_IRQHandler +I2S_IRQHandler +AES_IRQHandler +USB_IRQHandler +PDMA_CH0_1_IRQHandler +PDMA_CH2_5_IRQHandler + B . + ENDP + + ALIGN + +;******************************************************************************* +; User Stack and Heap initialization +;******************************************************************************* + IF :DEF:__MICROLIB + + EXPORT __HT_check_heap + EXPORT __HT_check_sp + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, = (Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + + ENDIF + + END diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f5xxxx_05.s b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f5xxxx_05.s new file mode 100644 index 0000000000..842644ceee --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f5xxxx_05.s @@ -0,0 +1,350 @@ +;/*---------------------------------------------------------------------------------------------------------*/ +;/* Holtek Semiconductor Inc. */ +;/* */ +;/* Copyright (C) Holtek Semiconductor Inc. */ +;/* All rights reserved. */ +;/* */ +;/*----------------------------------------------------------------------------------------------------------- +; File Name : startup_ht32f5xxxx_05.s +; Version : $Rev:: 6993 $ +; Date : $Date:: 2023-06-26 #$ +; Description : Startup code. +;-----------------------------------------------------------------------------------------------------------*/ + +; Supported Device +; ======================================== +; HT32F57331, HT32F57341 +; HT32F57342, HT32F57352 +; HT32F59741 +; HT32F5828 +; HT32F67742 +; HT32F59746 + +;/* <<< Use Configuration Wizard in Context Menu >>> */ + +;// HT32 Device +;// Select HT32 Device for the assembly setting. +;// Notice that the project's Asm Define has the higher priority. +;// <0=> By Project Asm Define +;// <13=> HT32F57331/41 +;// <14=> HT32F57342/52 +;// <13=> HT32F59741 +;// <14=> HT32F5828 +;// <13=> HT32F67742 +;// <13=> HT32F59746 +USE_HT32_CHIP_SET EQU 0 ; Notice that the project's Asm Define has the higher priority. + +_HT32FWID EQU 0xFFFFFFFF +;_HT32FWID EQU 0x00057331 +;_HT32FWID EQU 0x00057341 +;_HT32FWID EQU 0x00057342 +;_HT32FWID EQU 0x00057352 +;_HT32FWID EQU 0x00059741 +;_HT32FWID EQU 0x00005828 +;_HT32FWID EQU 0x00067742 +;_HT32FWID EQU 0x00059746 + +HT32F57331_41 EQU 13 +HT32F57342_52 EQU 14 +HT32F59741 EQU 13 +HT32F5828 EQU 14 +HT32F67742 EQU 13 +HT32F59746 EQU 13 + + IF USE_HT32_CHIP_SET=0 + ; Use project's Asm Define setting (default) + ELSE + IF :DEF:USE_HT32_CHIP + ; Use project's Asm Define setting (higher priority than the "USE_HT32_CHIP_SET") + ELSE + ; Use "USE_HT32_CHIP_SET" in the "startup_ht32xxxxx_xx.s" file +USE_HT32_CHIP EQU USE_HT32_CHIP_SET + ENDIF + ENDIF + +; Amount of memory (in bytes) allocated for Stack and Heap +; Tailor those values to your application needs +;// Stack Size (in Bytes, must 8 byte aligned) <0-16384:8> +Stack_Size EQU 512 + + AREA STACK, NOINIT, READWRITE, ALIGN = 3 +__HT_check_sp +Stack_Mem SPACE Stack_Size +__initial_sp + +;// Heap Size (in Bytes) <0-16384:8> +Heap_Size EQU 0 + + AREA HEAP, NOINIT, READWRITE, ALIGN = 3 +__HT_check_heap +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + PRESERVE8 + THUMB + +;******************************************************************************* +; Fill-up the Vector Table entries with the exceptions ISR address +;******************************************************************************* + AREA RESET, CODE, READONLY + EXPORT __Vectors +_RESERVED EQU 0xFFFFFFFF +__Vectors + DCD __initial_sp ; ---, 00, 0x000, Top address of Stack + DCD Reset_Handler ; ---, 01, 0x004, Reset Handler + DCD NMI_Handler ; -14, 02, 0x008, NMI Handler + DCD HardFault_Handler ; -13, 03, 0x00C, Hard Fault Handler + DCD _RESERVED ; ---, 04, 0x010, Reserved + DCD _RESERVED ; ---, 05, 0x014, Reserved + DCD _RESERVED ; ---, 06, 0x018, Reserved + DCD _RESERVED ; ---, 07, 0x01C, Reserved + DCD _HT32FWID ; ---, 08, 0x020, Reserved + DCD _RESERVED ; ---, 09, 0x024, Reserved + DCD _RESERVED ; ---, 10, 0x028, Reserved + DCD SVC_Handler ; -05, 11, 0x02C, SVC Handler + DCD _RESERVED ; ---, 12, 0x030, Reserved + DCD _RESERVED ; ---, 13, 0x034, Reserved + DCD PendSV_Handler ; -02, 14, 0x038, PendSV Handler + DCD SysTick_Handler ; -01, 15, 0x03C, SysTick Handler + + ; External Interrupt Handler + DCD LVD_BOD_IRQHandler ; 00, 16, 0x040, + DCD RTC_IRQHandler ; 01, 17, 0x044, + DCD FLASH_IRQHandler ; 02, 18, 0x048, + DCD EVWUP_IRQHandler ; 03, 19, 0x04C, + DCD EXTI0_1_IRQHandler ; 04, 20, 0x050, + DCD EXTI2_3_IRQHandler ; 05, 21, 0x054, + DCD EXTI4_15_IRQHandler ; 06, 22, 0x058, + IF (USE_HT32_CHIP=HT32F57331_41) + DCD _RESERVED ; 07, 23, 0x05C, + ENDIF + IF (USE_HT32_CHIP=HT32F57342_52) + DCD COMP_DAC_IRQHandler ; 07, 23, 0x05C, + ENDIF + DCD ADC_IRQHandler ; 08, 24, 0x060, + IF (USE_HT32_CHIP=HT32F57331_41) + DCD _RESERVED ; 09, 25, 0x064, + ENDIF + IF (USE_HT32_CHIP=HT32F57342_52) + DCD AES_IRQHandler ; 09, 25, 0x064, + ENDIF + DCD _RESERVED ; 10, 26, 0x068, + DCD LCD_IRQHandler ; 11, 27, 0x06C, + DCD GPTM0_IRQHandler ; 12, 28, 0x070, + IF (USE_HT32_CHIP=HT32F57331_41) + DCD _RESERVED ; 13, 29, 0x074, + DCD _RESERVED ; 14, 30, 0x078, + ENDIF + IF (USE_HT32_CHIP=HT32F57342_52) + DCD SCTM0_IRQHandler ; 13, 29, 0x074, + DCD SCTM1_IRQHandler ; 14, 30, 0x078, + ENDIF + DCD PWM0_IRQHandler ; 15, 31, 0x07C, + DCD PWM1_IRQHandler ; 16, 32, 0x080, + DCD BFTM0_IRQHandler ; 17, 33, 0x084, + DCD BFTM1_IRQHandler ; 18, 34, 0x088, + DCD I2C0_IRQHandler ; 19, 35, 0x08C, + DCD I2C1_IRQHandler ; 20, 36, 0x090, + DCD SPI0_IRQHandler ; 21, 37, 0x094, + DCD SPI1_IRQHandler ; 22, 38, 0x098, + DCD USART0_IRQHandler ; 23, 39, 0x09C, + DCD _RESERVED ; 24, 40, 0x0A0, + DCD UART0_IRQHandler ; 25, 41, 0x0A4, + DCD UART1_IRQHandler ; 26, 42, 0x0A8, + DCD SCI_IRQHandler ; 27, 43, 0x0AC, + DCD I2S_IRQHandler ; 28, 44, 0x0B0, + DCD USB_IRQHandler ; 29, 45, 0x0B4, + IF (USE_HT32_CHIP=HT32F57331_41) + DCD _RESERVED ; 30, 46, 0x0B8, + DCD _RESERVED ; 31, 47, 0x0BC, + ENDIF + IF (USE_HT32_CHIP=HT32F57342_52) + DCD PDMA_CH0_1_IRQHandler ; 30, 46, 0x0B8, + DCD PDMA_CH2_5_IRQHandler ; 31, 47, 0x0BC, + ENDIF + +; Reset handler routine +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + LDR R0, =BootProcess + BLX R0 + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +BootProcess PROC + LDR R0, =0x40080300 + LDR R1,[R0, #0x10] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x14] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x18] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x1C] + CMP R1, #0 + BEQ BP2 +BP1 LDR R0, =0x40080180 + LDR R1,[R0, #0xC] + LSLS R1, R1, #4 + LSRS R1, R1, #20 + CMP R1, #0 + BEQ BP3 + CMP R1, #5 + BEQ BP3 + CMP R1, #6 + BEQ BP3 +BP2 DSB + LDR R0, =0x20000000 + LDR R1, =0x05fa0004 + STR R1, [R0] + LDR R1, =0xe000ed00 + LDR R0, =0x05fa0004 + STR R0, [R1, #0xC] + DSB + B . +BP3 LDR R0, =0x20000000 + LDR R1, [R0] + LDR R0, =0x05fa0004 + CMP R0, R1 + BEQ BP4 + BX LR +BP4 LDR R0, =0x40088100 + LDR R1, =0x00000001 + STR R1, [R0] + LDR R0, =0x20000000 + LDR R1, =0x0 + STR R1, [R0] + BX LR + ENDP + +; Dummy Exception Handlers +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP + +HardFault_Handler PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP + +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP + +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP + +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + EXPORT LVD_BOD_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT EVWUP_IRQHandler [WEAK] + EXPORT EXTI0_1_IRQHandler [WEAK] + EXPORT EXTI2_3_IRQHandler [WEAK] + EXPORT EXTI4_15_IRQHandler [WEAK] + EXPORT COMP_DAC_IRQHandler [WEAK] + EXPORT ADC_IRQHandler [WEAK] + EXPORT AES_IRQHandler [WEAK] + EXPORT LCD_IRQHandler [WEAK] + EXPORT GPTM0_IRQHandler [WEAK] + EXPORT SCTM0_IRQHandler [WEAK] + EXPORT SCTM1_IRQHandler [WEAK] + EXPORT PWM0_IRQHandler [WEAK] + EXPORT PWM1_IRQHandler [WEAK] + EXPORT BFTM0_IRQHandler [WEAK] + EXPORT BFTM1_IRQHandler [WEAK] + EXPORT I2C0_IRQHandler [WEAK] + EXPORT I2C1_IRQHandler [WEAK] + EXPORT SPI0_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT USART0_IRQHandler [WEAK] + EXPORT USART1_IRQHandler [WEAK] + EXPORT UART0_IRQHandler [WEAK] + EXPORT UART1_IRQHandler [WEAK] + EXPORT SCI_IRQHandler [WEAK] + EXPORT I2S_IRQHandler [WEAK] + EXPORT USB_IRQHandler [WEAK] + EXPORT PDMA_CH0_1_IRQHandler [WEAK] + EXPORT PDMA_CH2_5_IRQHandler [WEAK] + +LVD_BOD_IRQHandler +RTC_IRQHandler +FLASH_IRQHandler +EVWUP_IRQHandler +EXTI0_1_IRQHandler +EXTI2_3_IRQHandler +EXTI4_15_IRQHandler +COMP_DAC_IRQHandler +ADC_IRQHandler +AES_IRQHandler +LCD_IRQHandler +GPTM0_IRQHandler +SCTM0_IRQHandler +SCTM1_IRQHandler +PWM0_IRQHandler +PWM1_IRQHandler +BFTM0_IRQHandler +BFTM1_IRQHandler +I2C0_IRQHandler +I2C1_IRQHandler +SPI0_IRQHandler +SPI1_IRQHandler +USART0_IRQHandler +USART1_IRQHandler +UART0_IRQHandler +UART1_IRQHandler +SCI_IRQHandler +I2S_IRQHandler +USB_IRQHandler +PDMA_CH0_1_IRQHandler +PDMA_CH2_5_IRQHandler + B . + ENDP + + ALIGN + +;******************************************************************************* +; User Stack and Heap initialization +;******************************************************************************* + IF :DEF:__MICROLIB + + EXPORT __HT_check_heap + EXPORT __HT_check_sp + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, = (Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + + ENDIF + + END diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f5xxxx_06.s b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f5xxxx_06.s new file mode 100644 index 0000000000..bf17a58ce7 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f5xxxx_06.s @@ -0,0 +1,298 @@ +;/*---------------------------------------------------------------------------------------------------------*/ +;/* Holtek Semiconductor Inc. */ +;/* */ +;/* Copyright (C) Holtek Semiconductor Inc. */ +;/* All rights reserved. */ +;/* */ +;/*----------------------------------------------------------------------------------------------------------- +; File Name : startup_ht32f5xxxx_06.s +; Version : $Rev:: 5740 $ +; Date : $Date:: 2022-02-17 #$ +; Description : Startup code. +;-----------------------------------------------------------------------------------------------------------*/ + +; Supported Device +; ======================================== +; HT32F50343 + +;/* <<< Use Configuration Wizard in Context Menu >>> */ + +;// HT32 Device +;// Select HT32 Device for the assembly setting. +;// Notice that the project's Asm Define has the higher priority. +;// <0=> By Project Asm Define +;// <15=> HT32F50343 +USE_HT32_CHIP_SET EQU 0 ; Notice that the project's Asm Define has the higher priority. + +_HT32FWID EQU 0xFFFFFFFF +;_HT32FWID EQU 0x00050343 + +HT32F50343 EQU 15 + + IF USE_HT32_CHIP_SET=0 + ; Use project's Asm Define setting (default) + ELSE + IF :DEF:USE_HT32_CHIP + ; Use project's Asm Define setting (higher priority than the "USE_HT32_CHIP_SET") + ELSE + ; Use "USE_HT32_CHIP_SET" in the "startup_ht32xxxxx_xx.s" file +USE_HT32_CHIP EQU USE_HT32_CHIP_SET + ENDIF + ENDIF + +; Amount of memory (in bytes) allocated for Stack and Heap +; Tailor those values to your application needs +;// Stack Size (in Bytes, must 8 byte aligned) <0-12288:8> +Stack_Size EQU 512 + + AREA STACK, NOINIT, READWRITE, ALIGN = 3 +__HT_check_sp +Stack_Mem SPACE Stack_Size +__initial_sp + +;// Heap Size (in Bytes) <0-12288:8> +Heap_Size EQU 0 + + AREA HEAP, NOINIT, READWRITE, ALIGN = 3 +__HT_check_heap +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + PRESERVE8 + THUMB + +;******************************************************************************* +; Fill-up the Vector Table entries with the exceptions ISR address +;******************************************************************************* + AREA RESET, CODE, READONLY + EXPORT __Vectors +_RESERVED EQU 0xFFFFFFFF +__Vectors + DCD __initial_sp ; ---, 00, 0x000, Top address of Stack + DCD Reset_Handler ; ---, 01, 0x004, Reset Handler + DCD NMI_Handler ; -14, 02, 0x008, NMI Handler + DCD HardFault_Handler ; -13, 03, 0x00C, Hard Fault Handler + DCD _RESERVED ; ---, 04, 0x010, Reserved + DCD _RESERVED ; ---, 05, 0x014, Reserved + DCD _RESERVED ; ---, 06, 0x018, Reserved + DCD _RESERVED ; ---, 07, 0x01C, Reserved + DCD _HT32FWID ; ---, 08, 0x020, Reserved + DCD _RESERVED ; ---, 09, 0x024, Reserved + DCD _RESERVED ; ---, 10, 0x028, Reserved + DCD SVC_Handler ; -05, 11, 0x02C, SVC Handler + DCD _RESERVED ; ---, 12, 0x030, Reserved + DCD _RESERVED ; ---, 13, 0x034, Reserved + DCD PendSV_Handler ; -02, 14, 0x038, PendSV Handler + DCD SysTick_Handler ; -01, 15, 0x03C, SysTick Handler + + ; External Interrupt Handler + DCD LVD_BOD_IRQHandler ; 00, 16, 0x040, + DCD RTC_IRQHandler ; 01, 17, 0x044, + DCD FLASH_IRQHandler ; 02, 18, 0x048, + DCD EVWUP_IRQHandler ; 03, 19, 0x04C, + DCD EXTI0_1_IRQHandler ; 04, 20, 0x050, + DCD EXTI2_3_IRQHandler ; 05, 21, 0x054, + DCD EXTI4_15_IRQHandler ; 06, 22, 0x058, + DCD _RESERVED ; 07, 23, 0x05C, + DCD ADC_IRQHandler ; 08, 24, 0x060, + DCD _RESERVED ; 09, 25, 0x064, + DCD PWM2_IRQHandler ; 10, 26, 0x068, + DCD _RESERVED ; 11, 27, 0x06C, + DCD GPTM0_IRQHandler ; 12, 28, 0x070, + DCD SCTM0_IRQHandler ; 13, 29, 0x074, + DCD SCTM1_IRQHandler ; 14, 30, 0x078, + DCD PWM0_IRQHandler ; 15, 31, 0x07C, + DCD PWM1_IRQHandler ; 16, 32, 0x080, + DCD BFTM0_IRQHandler ; 17, 33, 0x084, + DCD BFTM1_IRQHandler ; 18, 34, 0x088, + DCD I2C0_IRQHandler ; 19, 35, 0x08C, + DCD I2C1_IRQHandler ; 20, 36, 0x090, + DCD SPI0_IRQHandler ; 21, 37, 0x094, + DCD SPI1_IRQHandler ; 22, 38, 0x098, + DCD _RESERVED ; 23, 39, 0x09C, + DCD _RESERVED ; 24, 40, 0x0A0, + DCD UART0_IRQHandler ; 25, 41, 0x0A4, + DCD UART1_IRQHandler ; 26, 42, 0x0A8, + DCD SLED0_IRQHandler ; 27, 43, 0x0AC, + DCD SLED1_IRQHandler ; 28, 44, 0x0B0, + DCD USB_IRQHandler ; 29, 45, 0x0B4, + DCD PDMA_CH0_1_IRQHandler ; 30, 46, 0x0B8, + DCD PDMA_CH2_5_IRQHandler ; 31, 47, 0x0BC, + +; Reset handler routine +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + LDR R0, =BootProcess + BLX R0 + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +BootProcess PROC + LDR R0, =0x40080300 + LDR R1,[R0, #0x10] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x14] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x18] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x1C] + CMP R1, #0 + BEQ BP2 +BP1 LDR R0, =0x40080180 + LDR R1,[R0, #0xC] + LSLS R1, R1, #4 + LSRS R1, R1, #20 + CMP R1, #0 + BEQ BP3 + CMP R1, #5 + BEQ BP3 + CMP R1, #6 + BEQ BP3 +BP2 DSB + LDR R0, =0x20000000 + LDR R1, =0x05fa0004 + STR R1, [R0] + LDR R1, =0xe000ed00 + LDR R0, =0x05fa0004 + STR R0, [R1, #0xC] + DSB + B . +BP3 LDR R0, =0x20000000 + LDR R1, [R0] + LDR R0, =0x05fa0004 + CMP R0, R1 + BEQ BP4 + BX LR +BP4 LDR R0, =0x40088100 + LDR R1, =0x00000001 + STR R1, [R0] + LDR R0, =0x20000000 + LDR R1, =0x0 + STR R1, [R0] + BX LR + ENDP + +; Dummy Exception Handlers +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP + +HardFault_Handler PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP + +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP + +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP + +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + EXPORT LVD_BOD_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT EVWUP_IRQHandler [WEAK] + EXPORT EXTI0_1_IRQHandler [WEAK] + EXPORT EXTI2_3_IRQHandler [WEAK] + EXPORT EXTI4_15_IRQHandler [WEAK] + EXPORT ADC_IRQHandler [WEAK] + EXPORT PWM2_IRQHandler [WEAK] + EXPORT GPTM0_IRQHandler [WEAK] + EXPORT SCTM0_IRQHandler [WEAK] + EXPORT SCTM1_IRQHandler [WEAK] + EXPORT PWM0_IRQHandler [WEAK] + EXPORT PWM1_IRQHandler [WEAK] + EXPORT BFTM0_IRQHandler [WEAK] + EXPORT BFTM1_IRQHandler [WEAK] + EXPORT I2C0_IRQHandler [WEAK] + EXPORT I2C1_IRQHandler [WEAK] + EXPORT SPI0_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT UART0_IRQHandler [WEAK] + EXPORT UART1_IRQHandler [WEAK] + EXPORT SLED0_IRQHandler [WEAK] + EXPORT SLED1_IRQHandler [WEAK] + EXPORT USB_IRQHandler [WEAK] + EXPORT PDMA_CH0_1_IRQHandler [WEAK] + EXPORT PDMA_CH2_5_IRQHandler [WEAK] + +LVD_BOD_IRQHandler +RTC_IRQHandler +FLASH_IRQHandler +EVWUP_IRQHandler +EXTI0_1_IRQHandler +EXTI2_3_IRQHandler +EXTI4_15_IRQHandler +ADC_IRQHandler +PWM2_IRQHandler +GPTM0_IRQHandler +SCTM0_IRQHandler +SCTM1_IRQHandler +PWM0_IRQHandler +PWM1_IRQHandler +BFTM0_IRQHandler +BFTM1_IRQHandler +I2C0_IRQHandler +I2C1_IRQHandler +SPI0_IRQHandler +SPI1_IRQHandler +UART0_IRQHandler +UART1_IRQHandler +SLED0_IRQHandler +SLED1_IRQHandler +USB_IRQHandler +PDMA_CH0_1_IRQHandler +PDMA_CH2_5_IRQHandler + B . + ENDP + + ALIGN + +;******************************************************************************* +; User Stack and Heap initialization +;******************************************************************************* + IF :DEF:__MICROLIB + + EXPORT __HT_check_heap + EXPORT __HT_check_sp + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, = (Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + + ENDIF + + END diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f5xxxx_07.s b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f5xxxx_07.s new file mode 100644 index 0000000000..10f210c5a2 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f5xxxx_07.s @@ -0,0 +1,304 @@ +;/*---------------------------------------------------------------------------------------------------------*/ +;/* Holtek Semiconductor Inc. */ +;/* */ +;/* Copyright (C) Holtek Semiconductor Inc. */ +;/* All rights reserved. */ +;/* */ +;/*----------------------------------------------------------------------------------------------------------- +; File Name : startup_ht32f5xxxx_07.s +; Version : $Rev:: 5740 $ +; Date : $Date:: 2022-02-17 #$ +; Description : Startup code. +;-----------------------------------------------------------------------------------------------------------*/ + +; Supported Device +; ======================================== +; HT32F0006 +; HT32F61352 +; HT32F61355, HT32F61356, HT32F61357 + +;/* <<< Use Configuration Wizard in Context Menu >>> */ + +;// HT32 Device +;// Select HT32 Device for the assembly setting. +;// Notice that the project's Asm Define has the higher priority. +;// <0=> By Project Asm Define +;// <10=> HT32F0006 +;// <10=> HT32F61352 +;// <17=> HT32F61355/56/57 +USE_HT32_CHIP_SET EQU 0 ; Notice that the project's Asm Define has the higher priority. + +_HT32FWID EQU 0xFFFFFFFF +;_HT32FWID EQU 0x00000006 +;_HT32FWID EQU 0x00061352 +;_HT32FWID EQU 0x00061355 +;_HT32FWID EQU 0x00061356 +;_HT32FWID EQU 0x00061357 + +HT32F0006 EQU 10 +HT32F61352 EQU 10 +HT32F61355_56_57 EQU 17 + + IF USE_HT32_CHIP_SET=0 + ; Use project's Asm Define setting (default) + ELSE + IF :DEF:USE_HT32_CHIP + ; Use project's Asm Define setting (higher priority than the "USE_HT32_CHIP_SET") + ELSE + ; Use "USE_HT32_CHIP_SET" in the "startup_ht32xxxxx_xx.s" file +USE_HT32_CHIP EQU USE_HT32_CHIP_SET + ENDIF + ENDIF + +; Amount of memory (in bytes) allocated for Stack and Heap +; Tailor those values to your application needs +;// Stack Size (in Bytes, must 8 byte aligned) <0-16384:8> +Stack_Size EQU 512 + + AREA STACK, NOINIT, READWRITE, ALIGN = 3 +__HT_check_sp +Stack_Mem SPACE Stack_Size +__initial_sp + +;// Heap Size (in Bytes) <0-16384:8> +Heap_Size EQU 0 + + AREA HEAP, NOINIT, READWRITE, ALIGN = 3 +__HT_check_heap +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + PRESERVE8 + THUMB + +;******************************************************************************* +; Fill-up the Vector Table entries with the exceptions ISR address +;******************************************************************************* + AREA RESET, CODE, READONLY + EXPORT __Vectors +_RESERVED EQU 0xFFFFFFFF +__Vectors + DCD __initial_sp ; ---, 00, 0x000, Top address of Stack + DCD Reset_Handler ; ---, 01, 0x004, Reset Handler + DCD NMI_Handler ; -14, 02, 0x008, NMI Handler + DCD HardFault_Handler ; -13, 03, 0x00C, Hard Fault Handler + DCD _RESERVED ; ---, 04, 0x010, Reserved + DCD _RESERVED ; ---, 05, 0x014, Reserved + DCD _RESERVED ; ---, 06, 0x018, Reserved + DCD _RESERVED ; ---, 07, 0x01C, Reserved + DCD _HT32FWID ; ---, 08, 0x020, Reserved + DCD _RESERVED ; ---, 09, 0x024, Reserved + DCD _RESERVED ; ---, 10, 0x028, Reserved + DCD SVC_Handler ; -05, 11, 0x02C, SVC Handler + DCD _RESERVED ; ---, 12, 0x030, Reserved + DCD _RESERVED ; ---, 13, 0x034, Reserved + DCD PendSV_Handler ; -02, 14, 0x038, PendSV Handler + DCD SysTick_Handler ; -01, 15, 0x03C, SysTick Handler + + ; External Interrupt Handler + DCD LVD_BOD_IRQHandler ; 00, 16, 0x040, + DCD RTC_IRQHandler ; 01, 17, 0x044, + DCD FLASH_IRQHandler ; 02, 18, 0x048, + DCD EVWUP_IRQHandler ; 03, 19, 0x04C, + DCD EXTI0_1_IRQHandler ; 04, 20, 0x050, + DCD EXTI2_3_IRQHandler ; 05, 21, 0x054, + DCD EXTI4_15_IRQHandler ; 06, 22, 0x058, + DCD _RESERVED ; 07, 23, 0x05C, + DCD ADC_IRQHandler ; 08, 24, 0x060, + DCD _RESERVED ; 09, 25, 0x064, + DCD _RESERVED ; 10, 26, 0x068, + DCD _RESERVED ; 11, 27, 0x06C, + DCD GPTM0_IRQHandler ; 12, 28, 0x070, + DCD SCTM0_IRQHandler ; 13, 29, 0x074, + DCD SCTM1_IRQHandler ; 14, 30, 0x078, + DCD SCTM2_IRQHandler ; 15, 31, 0x07C, + DCD SCTM3_IRQHandler ; 16, 32, 0x080, + DCD BFTM0_IRQHandler ; 17, 33, 0x084, + DCD BFTM1_IRQHandler ; 18, 34, 0x088, + DCD I2C0_IRQHandler ; 19, 35, 0x08C, + DCD _RESERVED ; 20, 36, 0x090, + DCD SPI0_IRQHandler ; 21, 37, 0x094, + DCD QSPI_IRQHandler ; 22, 38, 0x098, + DCD USART0_IRQHandler ; 23, 39, 0x09C, + DCD _RESERVED ; 24, 40, 0x0A0, + DCD UART0_IRQHandler ; 25, 41, 0x0A4, + DCD _RESERVED ; 26, 42, 0x0A8, + DCD MIDI_IRQHandler ; 27, 43, 0x0AC, + DCD I2S_IRQHandler ; 28, 44, 0x0B0, + DCD USB_IRQHandler ; 29, 45, 0x0B4, + DCD PDMA_CH0_1_IRQHandler ; 30, 46, 0x0B8, + DCD PDMA_CH2_5_IRQHandler ; 31, 47, 0x0BC, + +; Reset handler routine +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + LDR R0, =BootProcess + BLX R0 + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +BootProcess PROC + LDR R0, =0x40080300 + LDR R1,[R0, #0x10] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x14] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x18] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x1C] + CMP R1, #0 + BEQ BP2 +BP1 LDR R0, =0x40080180 + LDR R1,[R0, #0xC] + LSLS R1, R1, #4 + LSRS R1, R1, #20 + CMP R1, #0 + BEQ BP3 + CMP R1, #5 + BEQ BP3 + CMP R1, #6 + BEQ BP3 +BP2 DSB + LDR R0, =0x20000000 + LDR R1, =0x05fa0004 + STR R1, [R0] + LDR R1, =0xe000ed00 + LDR R0, =0x05fa0004 + STR R0, [R1, #0xC] + DSB + B . +BP3 LDR R0, =0x20000000 + LDR R1, [R0] + LDR R0, =0x05fa0004 + CMP R0, R1 + BEQ BP4 + BX LR +BP4 LDR R0, =0x40088100 + LDR R1, =0x00000001 + STR R1, [R0] + LDR R0, =0x20000000 + LDR R1, =0x0 + STR R1, [R0] + BX LR + ENDP + +; Dummy Exception Handlers +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP + +HardFault_Handler PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP + +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP + +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP + +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + EXPORT LVD_BOD_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT EVWUP_IRQHandler [WEAK] + EXPORT EXTI0_1_IRQHandler [WEAK] + EXPORT EXTI2_3_IRQHandler [WEAK] + EXPORT EXTI4_15_IRQHandler [WEAK] + EXPORT ADC_IRQHandler [WEAK] + EXPORT GPTM0_IRQHandler [WEAK] + EXPORT SCTM0_IRQHandler [WEAK] + EXPORT SCTM1_IRQHandler [WEAK] + EXPORT SCTM2_IRQHandler [WEAK] + EXPORT SCTM3_IRQHandler [WEAK] + EXPORT BFTM0_IRQHandler [WEAK] + EXPORT BFTM1_IRQHandler [WEAK] + EXPORT I2C0_IRQHandler [WEAK] + EXPORT SPI0_IRQHandler [WEAK] + EXPORT QSPI_IRQHandler [WEAK] + EXPORT USART0_IRQHandler [WEAK] + EXPORT UART0_IRQHandler [WEAK] + EXPORT MIDI_IRQHandler [WEAK] + EXPORT I2S_IRQHandler [WEAK] + EXPORT USB_IRQHandler [WEAK] + EXPORT PDMA_CH0_1_IRQHandler [WEAK] + EXPORT PDMA_CH2_5_IRQHandler [WEAK] + +LVD_BOD_IRQHandler +RTC_IRQHandler +FLASH_IRQHandler +EVWUP_IRQHandler +EXTI0_1_IRQHandler +EXTI2_3_IRQHandler +EXTI4_15_IRQHandler +ADC_IRQHandler +GPTM0_IRQHandler +SCTM0_IRQHandler +SCTM1_IRQHandler +SCTM2_IRQHandler +SCTM3_IRQHandler +BFTM0_IRQHandler +BFTM1_IRQHandler +I2C0_IRQHandler +SPI0_IRQHandler +QSPI_IRQHandler +USART0_IRQHandler +UART0_IRQHandler +MIDI_IRQHandler +I2S_IRQHandler +USB_IRQHandler +PDMA_CH0_1_IRQHandler +PDMA_CH2_5_IRQHandler + B . + ENDP + + ALIGN + +;******************************************************************************* +; User Stack and Heap initialization +;******************************************************************************* + IF :DEF:__MICROLIB + + EXPORT __HT_check_heap + EXPORT __HT_check_sp + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, = (Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + + ENDIF + + END diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f5xxxx_08.s b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f5xxxx_08.s new file mode 100644 index 0000000000..24cf68758d --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f5xxxx_08.s @@ -0,0 +1,278 @@ +;/*---------------------------------------------------------------------------------------------------------*/ +;/* Holtek Semiconductor Inc. */ +;/* */ +;/* Copyright (C) Holtek Semiconductor Inc. */ +;/* All rights reserved. */ +;/* */ +;/*----------------------------------------------------------------------------------------------------------- +; File Name : startup_ht32f5xxxx_08.s +; Version : $Rev:: 6877 $ +; Date : $Date:: 2023-05-04 #$ +; Description : Startup code. +;-----------------------------------------------------------------------------------------------------------*/ + +; Supported Device +; ======================================== +; HT32F65230, HT32F65240 +; HT32F65232 +; MXTX6306 +; HT50F3200S + +;/* <<< Use Configuration Wizard in Context Menu >>> */ + +;// HT32 Device +;// Select HT32 Device for the assembly setting. +;// Notice that the project's Asm Define has the higher priority. +;// <0=> By Project Asm Define +;// <12=> HT32F65230_40 +;// <18=> HT32F65232 +;// <12=> MXTX6306 +;// <12=> HT50F3200S +USE_HT32_CHIP_SET EQU 0 ; Notice that the project's Asm Define has the higher priority. + +_HT32FWID EQU 0xFFFFFFFF +;_HT32FWID EQU 0x00065230 +;_HT32FWID EQU 0x00065240 +;_HT32FWID EQU 0x00065232 +;_HT32FWID EQU 0x00006306 +;_HT32FWID EQU 0x0003200F + +HT32F65230_40 EQU 12 +HT32F65232 EQU 18 +MXTX6306 EQU 12 +HT50F3200S EQU 12 + + IF USE_HT32_CHIP_SET=0 + ; Use project's Asm Define setting (default) + ELSE + IF :DEF:USE_HT32_CHIP + ; Use project's Asm Define setting (higher priority than the "USE_HT32_CHIP_SET") + ELSE + ; Use "USE_HT32_CHIP_SET" in the "startup_ht32xxxxx_xx.s" file +USE_HT32_CHIP EQU USE_HT32_CHIP_SET + ENDIF + ENDIF + +; Amount of memory (in bytes) allocated for Stack and Heap +; Tailor those values to your application needs +;// Stack Size (in Bytes, must 8 byte aligned) <0-8192:8> +Stack_Size EQU 512 + + AREA STACK, NOINIT, READWRITE, ALIGN = 3 +__HT_check_sp +Stack_Mem SPACE Stack_Size +__initial_sp + +;// Heap Size (in Bytes) <0-8192:8> +Heap_Size EQU 0 + + AREA HEAP, NOINIT, READWRITE, ALIGN = 3 +__HT_check_heap +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + PRESERVE8 + THUMB + +;******************************************************************************* +; Fill-up the Vector Table entries with the exceptions ISR address +;******************************************************************************* + AREA RESET, CODE, READONLY + EXPORT __Vectors +_RESERVED EQU 0xFFFFFFFF +__Vectors + DCD __initial_sp ; ---, 00, 0x000, Top address of Stack + DCD Reset_Handler ; ---, 01, 0x004, Reset Handler + DCD NMI_Handler ; -14, 02, 0x008, NMI Handler + DCD HardFault_Handler ; -13, 03, 0x00C, Hard Fault Handler + DCD _RESERVED ; ---, 04, 0x010, Reserved + DCD _RESERVED ; ---, 05, 0x014, Reserved + DCD _RESERVED ; ---, 06, 0x018, Reserved + DCD _RESERVED ; ---, 07, 0x01C, Reserved + DCD _HT32FWID ; ---, 08, 0x020, Reserved + DCD _RESERVED ; ---, 09, 0x024, Reserved + DCD _RESERVED ; ---, 10, 0x028, Reserved + DCD SVC_Handler ; -05, 11, 0x02C, SVC Handler + DCD _RESERVED ; ---, 12, 0x030, Reserved + DCD _RESERVED ; ---, 13, 0x034, Reserved + DCD PendSV_Handler ; -02, 14, 0x038, PendSV Handler + DCD SysTick_Handler ; -01, 15, 0x03C, SysTick Handler + + ; External Interrupt Handler + DCD LVD_BOD_IRQHandler ; 00, 16, 0x040, + DCD RTC_IRQHandler ; 01, 17, 0x044, + DCD FLASH_IRQHandler ; 02, 18, 0x048, + DCD EVWUP_IRQHandler ; 03, 19, 0x04C, + DCD EXTI0_1_IRQHandler ; 04, 20, 0x050, + DCD EXTI2_3_IRQHandler ; 05, 21, 0x054, + DCD EXTI4_9_IRQHandler ; 06, 22, 0x058, + DCD EXTI10_15_IRQHandler ; 07, 23, 0x05C, + DCD ADC0_IRQHandler ; 08, 24, 0x060, + IF (USE_HT32_CHIP=HT32F65230_40) + DCD ADC1_IRQHandler ; 09, 25, 0x064, + ELSE + DCD _RESERVED ; 09, 25, 0x064, + ENDIF + DCD MCTM0_BRK_IRQHandler ; 10, 26, 0x068, + DCD MCTM0_UP_IRQHandler ; 11, 27, 0x06C, + DCD MCTM0_TR_UP2_IRQHandler ; 12, 28, 0x070, + DCD MCTM0_CC_IRQHandler ; 13, 29, 0x074, + DCD GPTM0_G_IRQHandler ; 14, 30, 0x078, + DCD GPTM0_VCLK_IRQHandler ; 15, 31, 0x07C, + DCD BFTM0_IRQHandler ; 16, 32, 0x080, + DCD BFTM1_IRQHandler ; 17, 33, 0x084, + DCD CMP0_IRQHandler ; 18, 34, 0x088, + DCD CMP1_IRQHandler ; 19, 35, 0x08C, + IF (USE_HT32_CHIP=HT32F65230_40) + DCD CMP2_IRQHandler ; 20, 36, 0x090, + ELSE + DCD _RESERVED ; 20, 36, 0x090, + ENDIF + DCD I2C0_IRQHandler ; 21, 37, 0x094, + DCD SPI0_IRQHandler ; 22, 38, 0x098, + DCD USART0_IRQHandler ; 23, 39, 0x09C, + DCD UART0_IRQHandler ; 24, 40, 0x0A0, + DCD PDMA_CH0_1_IRQHandler ; 25, 41, 0x0A4, + DCD PDMA_CH2_3_IRQHandler ; 26, 42, 0x0A8, + DCD PDMA_CH4_5_IRQHandler ; 27, 43, 0x0AC, + DCD SCTM0_IRQHandler ; 28, 44, 0x0B0, + DCD SCTM1_IRQHandler ; 29, 45, 0x0B4, + DCD SCTM2_IRQHandler ; 30, 46, 0x0B8, + DCD SCTM3_IRQHandler ; 31, 47, 0x0BC, + +; Reset handler routine +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception Handlers +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP + +HardFault_Handler PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP + +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP + +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP + +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + EXPORT LVD_BOD_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT EVWUP_IRQHandler [WEAK] + EXPORT EXTI0_1_IRQHandler [WEAK] + EXPORT EXTI2_3_IRQHandler [WEAK] + EXPORT EXTI4_9_IRQHandler [WEAK] + EXPORT EXTI10_15_IRQHandler [WEAK] + EXPORT ADC0_IRQHandler [WEAK] + EXPORT ADC1_IRQHandler [WEAK] + EXPORT MCTM0_BRK_IRQHandler [WEAK] + EXPORT MCTM0_UP_IRQHandler [WEAK] + EXPORT MCTM0_TR_UP2_IRQHandler [WEAK] + EXPORT MCTM0_CC_IRQHandler [WEAK] + EXPORT GPTM0_G_IRQHandler [WEAK] + EXPORT GPTM0_VCLK_IRQHandler [WEAK] + EXPORT BFTM0_IRQHandler [WEAK] + EXPORT BFTM1_IRQHandler [WEAK] + EXPORT CMP0_IRQHandler [WEAK] + EXPORT CMP1_IRQHandler [WEAK] + EXPORT CMP2_IRQHandler [WEAK] + EXPORT I2C0_IRQHandler [WEAK] + EXPORT SPI0_IRQHandler [WEAK] + EXPORT USART0_IRQHandler [WEAK] + EXPORT UART0_IRQHandler [WEAK] + EXPORT PDMA_CH0_1_IRQHandler [WEAK] + EXPORT PDMA_CH2_3_IRQHandler [WEAK] + EXPORT PDMA_CH4_5_IRQHandler [WEAK] + EXPORT SCTM0_IRQHandler [WEAK] + EXPORT SCTM1_IRQHandler [WEAK] + EXPORT SCTM2_IRQHandler [WEAK] + EXPORT SCTM3_IRQHandler [WEAK] +LVD_BOD_IRQHandler +RTC_IRQHandler +FLASH_IRQHandler +EVWUP_IRQHandler +EXTI0_1_IRQHandler +EXTI2_3_IRQHandler +EXTI4_9_IRQHandler +EXTI10_15_IRQHandler +ADC0_IRQHandler +ADC1_IRQHandler +MCTM0_BRK_IRQHandler +MCTM0_UP_IRQHandler +MCTM0_TR_UP2_IRQHandler +MCTM0_CC_IRQHandler +GPTM0_G_IRQHandler +GPTM0_VCLK_IRQHandler +BFTM0_IRQHandler +BFTM1_IRQHandler +CMP0_IRQHandler +CMP1_IRQHandler +CMP2_IRQHandler +I2C0_IRQHandler +SPI0_IRQHandler +USART0_IRQHandler +UART0_IRQHandler +PDMA_CH0_1_IRQHandler +PDMA_CH2_3_IRQHandler +PDMA_CH4_5_IRQHandler +SCTM0_IRQHandler +SCTM1_IRQHandler +SCTM2_IRQHandler +SCTM3_IRQHandler + B . + ENDP + + ALIGN + +;******************************************************************************* +; User Stack and Heap initialization +;******************************************************************************* + IF :DEF:__MICROLIB + + EXPORT __HT_check_heap + EXPORT __HT_check_sp + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, = (Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + + ENDIF + + END diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f5xxxx_09.s b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f5xxxx_09.s new file mode 100644 index 0000000000..089c851eb1 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f5xxxx_09.s @@ -0,0 +1,343 @@ +;/*---------------------------------------------------------------------------------------------------------*/ +;/* Holtek Semiconductor Inc. */ +;/* */ +;/* Copyright (C) Holtek Semiconductor Inc. */ +;/* All rights reserved. */ +;/* */ +;/*----------------------------------------------------------------------------------------------------------- +; File Name : startup_ht32f5xxxx_09.s +; Version : $Rev:: 5740 $ +; Date : $Date:: 2022-02-17 #$ +; Description : Startup code. +;-----------------------------------------------------------------------------------------------------------*/ + +; Supported Device +; ======================================== +; HT32F54231, HT32F54241 +; HT32F54243, HT32F54253 + +;/* <<< Use Configuration Wizard in Context Menu >>> */ + +;// HT32 Device +;// Select HT32 Device for the assembly setting. +;// Notice that the project's Asm Define has the higher priority. +;// <0=> By Project Asm Define +;// <19=> HT32F54231/41 +;// <20=> HT32F54243/53 +USE_HT32_CHIP_SET EQU 0 ; Notice that the project's Asm Define has the higher priority. + +_HT32FWID EQU 0xFFFFFFFF +;_HT32FWID EQU 0x00054231 +;_HT32FWID EQU 0x00054241 +;_HT32FWID EQU 0x00054243 +;_HT32FWID EQU 0x00054253 + +HT32F54231_41 EQU 19 +HT32F54243_53 EQU 20 + + IF USE_HT32_CHIP_SET=0 + ; Use project's Asm Define setting (default) + ELSE + IF :DEF:USE_HT32_CHIP + ; Use project's Asm Define setting (higher priority than the "USE_HT32_CHIP_SET") + ELSE + ; Use "USE_HT32_CHIP_SET" in the "startup_ht32xxxxx_xx.s" file +USE_HT32_CHIP EQU USE_HT32_CHIP_SET + ENDIF + ENDIF + +; Amount of memory (in bytes) allocated for Stack and Heap +; Tailor those values to your application needs +;// Stack Size (in Bytes, must 8 byte aligned) <0-16384:8> +Stack_Size EQU 512 + + AREA STACK, NOINIT, READWRITE, ALIGN = 3 +__HT_check_sp +Stack_Mem SPACE Stack_Size +__initial_sp + +;// Heap Size (in Bytes) <0-16384:8> +Heap_Size EQU 0 + + AREA HEAP, NOINIT, READWRITE, ALIGN = 3 +__HT_check_heap +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + PRESERVE8 + THUMB + +;******************************************************************************* +; Fill-up the Vector Table entries with the exceptions ISR address +;******************************************************************************* + AREA RESET, CODE, READONLY + EXPORT __Vectors +_RESERVED EQU 0xFFFFFFFF +__Vectors + DCD __initial_sp ; ---, 00, 0x000, Top address of Stack + DCD Reset_Handler ; ---, 01, 0x004, Reset Handler + DCD NMI_Handler ; -14, 02, 0x008, NMI Handler + DCD HardFault_Handler ; -13, 03, 0x00C, Hard Fault Handler + DCD _RESERVED ; ---, 04, 0x010, Reserved + DCD _RESERVED ; ---, 05, 0x014, Reserved + DCD _RESERVED ; ---, 06, 0x018, Reserved + DCD _RESERVED ; ---, 07, 0x01C, Reserved + DCD _HT32FWID ; ---, 08, 0x020, Reserved + DCD _RESERVED ; ---, 09, 0x024, Reserved + DCD _RESERVED ; ---, 10, 0x028, Reserved + DCD SVC_Handler ; -05, 11, 0x02C, SVC Handler + DCD _RESERVED ; ---, 12, 0x030, Reserved + DCD _RESERVED ; ---, 13, 0x034, Reserved + DCD PendSV_Handler ; -02, 14, 0x038, PendSV Handler + DCD SysTick_Handler ; -01, 15, 0x03C, SysTick Handler + + ; External Interrupt Handler + DCD LVD_BOD_IRQHandler ; 00, 16, 0x040, + DCD RTC_IRQHandler ; 01, 17, 0x044, + DCD FLASH_IRQHandler ; 02, 18, 0x048, + DCD EVWUP_IRQHandler ; 03, 19, 0x04C, + DCD EXTI0_1_IRQHandler ; 04, 20, 0x050, + DCD EXTI2_3_IRQHandler ; 05, 21, 0x054, + DCD EXTI4_15_IRQHandler ; 06, 22, 0x058, + IF (USE_HT32_CHIP=HT32F54231_41) + DCD _RESERVED ; 07, 23, 0x05C, + ENDIF + IF (USE_HT32_CHIP=HT32F54243_53) + DCD COMP_IRQHandler ; 07, 23, 0x05C, + ENDIF + DCD ADC_IRQHandler ; 08, 24, 0x060, + IF (USE_HT32_CHIP=HT32F54231_41) + DCD _RESERVED ; 09, 25, 0x064, + ENDIF + IF (USE_HT32_CHIP=HT32F54243_53) + DCD I2C2_IRQHandler ; 09, 25, 0x064, + ENDIF + DCD MCTM0_IRQHandler ; 10, 26, 0x068, + DCD TKEY_IRQHandler ; 11, 27, 0x06C, + DCD GPTM0_IRQHandler ; 12, 28, 0x070, + DCD SCTM0_IRQHandler ; 13, 29, 0x074, + DCD SCTM1_IRQHandler ; 14, 30, 0x078, + IF (USE_HT32_CHIP=HT32F54231_41) + DCD _RESERVED ; 15, 31, 0x07C, + DCD _RESERVED ; 16, 32, 0x080, + ENDIF + IF (USE_HT32_CHIP=HT32F54243_53) + DCD SCTM2_IRQHandler ; 15, 31, 0x07C, + DCD SCTM3_IRQHandler ; 16, 32, 0x080, + ENDIF + DCD BFTM0_IRQHandler ; 17, 33, 0x084, + DCD BFTM1_IRQHandler ; 18, 34, 0x088, + DCD I2C0_IRQHandler ; 19, 35, 0x08C, + DCD I2C1_IRQHandler ; 20, 36, 0x090, + DCD SPI0_IRQHandler ; 21, 37, 0x094, + DCD SPI1_IRQHandler ; 22, 38, 0x098, + DCD USART0_IRQHandler ; 23, 39, 0x09C, + IF (USE_HT32_CHIP=HT32F54231_41) + DCD _RESERVED ; 24, 40, 0x0A0, + ENDIF + IF (USE_HT32_CHIP=HT32F54243_53) + DCD USART1_IRQHandler ; 24, 40, 0x0A0, + ENDIF + DCD UART0_IRQHandler ; 25, 41, 0x0A4, + DCD UART1_IRQHandler ; 26, 42, 0x0A8, + IF (USE_HT32_CHIP=HT32F54231_41) + DCD _RESERVED ; 27, 43, 0x0AC, + DCD _RESERVED ; 28, 44, 0x0B0, + ENDIF + IF (USE_HT32_CHIP=HT32F54243_53) + DCD UART2_IRQHandler ; 27, 43, 0x0AC, + DCD UART3_IRQHandler ; 28, 44, 0x0B0, + ENDIF + DCD LEDC_IRQHandler ; 29, 45, 0x0B4, + IF (USE_HT32_CHIP=HT32F54243_53) + DCD PDMA_CH0_1_IRQHandler ; 30, 46, 0x0B8, + DCD PDMA_CH2_5_IRQHandler ; 31, 47, 0x0BC, + ENDIF + +; Reset handler routine +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + LDR R0, =BootProcess + BLX R0 + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +BootProcess PROC + LDR R0, =0x40080300 + LDR R1,[R0, #0x10] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x14] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x18] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x1C] + CMP R1, #0 + BEQ BP2 +BP1 LDR R0, =0x40080180 + LDR R1,[R0, #0xC] + LSLS R1, R1, #4 + LSRS R1, R1, #20 + CMP R1, #0 + BEQ BP3 + CMP R1, #5 + BEQ BP3 + CMP R1, #6 + BEQ BP3 +BP2 DSB + LDR R0, =0x20000000 + LDR R1, =0x05fa0004 + STR R1, [R0] + LDR R1, =0xe000ed00 + LDR R0, =0x05fa0004 + STR R0, [R1, #0xC] + DSB + B . +BP3 LDR R0, =0x20000000 + LDR R1, [R0] + LDR R0, =0x05fa0004 + CMP R0, R1 + BEQ BP4 + BX LR +BP4 LDR R0, =0x40088100 + LDR R1, =0x00000001 + STR R1, [R0] + LDR R0, =0x20000000 + LDR R1, =0x0 + STR R1, [R0] + BX LR + ENDP + +; Dummy Exception Handlers +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP + +HardFault_Handler PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP + +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP + +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP + +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + EXPORT LVD_BOD_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT EVWUP_IRQHandler [WEAK] + EXPORT EXTI0_1_IRQHandler [WEAK] + EXPORT EXTI2_3_IRQHandler [WEAK] + EXPORT EXTI4_15_IRQHandler [WEAK] + EXPORT COMP_IRQHandler [WEAK] + EXPORT ADC_IRQHandler [WEAK] + EXPORT I2C2_IRQHandler [WEAK] + EXPORT MCTM0_IRQHandler [WEAK] + EXPORT TKEY_IRQHandler [WEAK] + EXPORT GPTM0_IRQHandler [WEAK] + EXPORT SCTM0_IRQHandler [WEAK] + EXPORT SCTM1_IRQHandler [WEAK] + EXPORT SCTM2_IRQHandler [WEAK] + EXPORT SCTM3_IRQHandler [WEAK] + EXPORT BFTM0_IRQHandler [WEAK] + EXPORT BFTM1_IRQHandler [WEAK] + EXPORT I2C0_IRQHandler [WEAK] + EXPORT I2C1_IRQHandler [WEAK] + EXPORT SPI0_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT USART0_IRQHandler [WEAK] + EXPORT USART1_IRQHandler [WEAK] + EXPORT UART0_IRQHandler [WEAK] + EXPORT UART1_IRQHandler [WEAK] + EXPORT UART2_IRQHandler [WEAK] + EXPORT UART3_IRQHandler [WEAK] + EXPORT LEDC_IRQHandler [WEAK] + EXPORT PDMA_CH0_1_IRQHandler [WEAK] + EXPORT PDMA_CH2_5_IRQHandler [WEAK] + +LVD_BOD_IRQHandler +RTC_IRQHandler +FLASH_IRQHandler +EVWUP_IRQHandler +EXTI0_1_IRQHandler +EXTI2_3_IRQHandler +EXTI4_15_IRQHandler +COMP_IRQHandler +ADC_IRQHandler +I2C2_IRQHandler +MCTM0_IRQHandler +TKEY_IRQHandler +GPTM0_IRQHandler +SCTM0_IRQHandler +SCTM1_IRQHandler +SCTM2_IRQHandler +SCTM3_IRQHandler +BFTM0_IRQHandler +BFTM1_IRQHandler +I2C0_IRQHandler +I2C1_IRQHandler +SPI0_IRQHandler +SPI1_IRQHandler +USART0_IRQHandler +USART1_IRQHandler +UART0_IRQHandler +UART1_IRQHandler +UART2_IRQHandler +UART3_IRQHandler +LEDC_IRQHandler +PDMA_CH0_1_IRQHandler +PDMA_CH2_5_IRQHandler + B . + ENDP + + ALIGN + +;******************************************************************************* +; User Stack and Heap initialization +;******************************************************************************* + IF :DEF:__MICROLIB + + EXPORT __HT_check_heap + EXPORT __HT_check_sp + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, = (Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + + ENDIF + + END diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f5xxxx_10.s b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f5xxxx_10.s new file mode 100644 index 0000000000..57fb44e314 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f5xxxx_10.s @@ -0,0 +1,235 @@ +;/*---------------------------------------------------------------------------------------------------------*/ +;/* Holtek Semiconductor Inc. */ +;/* */ +;/* Copyright (C) Holtek Semiconductor Inc. */ +;/* All rights reserved. */ +;/* */ +;/*----------------------------------------------------------------------------------------------------------- +; File Name : startup_ht32f5xxxx_10.s +; Version : $Rev:: 5783 $ +; Date : $Date:: 2022-03-30 #$ +; Description : Startup code. +;-----------------------------------------------------------------------------------------------------------*/ + +; Supported Device +; ======================================== +; HT32F61244, HT32F61245 + +;/* <<< Use Configuration Wizard in Context Menu >>> */ + +;// HT32 Device +;// Select HT32 Device for the assembly setting. +;// Notice that the project's Asm Define has the higher priority. +;// <0=> By Project Asm Define +;// <24=> HT32F61244/45 +USE_HT32_CHIP_SET EQU 0 ; Notice that the project's Asm Define has the higher priority. + +_HT32FWID EQU 0xFFFFFFFF +;_HT32FWID EQU 0x00061244 +;_HT32FWID EQU 0x00061245 + +HT32F61244_45 EQU 24 + + IF USE_HT32_CHIP_SET=0 + ; Use project's Asm Define setting (default) + ELSE + IF :DEF:USE_HT32_CHIP + ; Use project's Asm Define setting (higher priority than the "USE_HT32_CHIP_SET") + ELSE + ; Use "USE_HT32_CHIP_SET" in the "startup_ht32xxxxx_xx.s" file +USE_HT32_CHIP EQU USE_HT32_CHIP_SET + ENDIF + ENDIF + +; Amount of memory (in bytes) allocated for Stack and Heap +; Tailor those values to your application needs +;// Stack Size (in Bytes, must 8 byte aligned) <0-8192:8> +Stack_Size EQU 512 + + AREA STACK, NOINIT, READWRITE, ALIGN = 3 +__HT_check_sp +Stack_Mem SPACE Stack_Size +__initial_sp + +;// Heap Size (in Bytes) <0-8192:8> +Heap_Size EQU 0 + + AREA HEAP, NOINIT, READWRITE, ALIGN = 3 +__HT_check_heap +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + PRESERVE8 + THUMB + +;******************************************************************************* +; Fill-up the Vector Table entries with the exceptions ISR address +;******************************************************************************* + AREA RESET, CODE, READONLY + EXPORT __Vectors +_RESERVED EQU 0xFFFFFFFF +__Vectors + DCD __initial_sp ; ---, 00, 0x000, Top address of Stack + DCD Reset_Handler ; ---, 01, 0x004, Reset Handler + DCD NMI_Handler ; -14, 02, 0x008, NMI Handler + DCD HardFault_Handler ; -13, 03, 0x00C, Hard Fault Handler + DCD _RESERVED ; ---, 04, 0x010, Reserved + DCD _RESERVED ; ---, 05, 0x014, Reserved + DCD _RESERVED ; ---, 06, 0x018, Reserved + DCD _RESERVED ; ---, 07, 0x01C, Reserved + DCD _HT32FWID ; ---, 08, 0x020, Reserved + DCD _RESERVED ; ---, 09, 0x024, Reserved + DCD _RESERVED ; ---, 10, 0x028, Reserved + DCD SVC_Handler ; -05, 11, 0x02C, SVC Handler + DCD _RESERVED ; ---, 12, 0x030, Reserved + DCD _RESERVED ; ---, 13, 0x034, Reserved + DCD PendSV_Handler ; -02, 14, 0x038, PendSV Handler + DCD SysTick_Handler ; -01, 15, 0x03C, SysTick Handler + + ; External Interrupt Handler + DCD LVD_BOD_IRQHandler ; 00, 16, 0x040, + DCD RTC_IRQHandler ; 01, 17, 0x044, + DCD FLASH_IRQHandler ; 02, 18, 0x048, + DCD EVWUP_IRQHandler ; 03, 19, 0x04C, + DCD EXTI0_1_IRQHandler ; 04, 20, 0x050, + DCD EXTI2_3_IRQHandler ; 05, 21, 0x054, + DCD EXTI4_15_IRQHandler ; 06, 22, 0x058, + DCD _RESERVED ; 07, 23, 0x05C, + DCD ADC_IRQHandler ; 08, 24, 0x060, + DCD _RESERVED ; 09, 25, 0x064, + DCD _RESERVED ; 10, 26, 0x068, + DCD _RESERVED ; 11, 27, 0x06C, + DCD GPTM0_IRQHandler ; 12, 28, 0x070, + DCD SCTM0_IRQHandler ; 13, 29, 0x074, + DCD SCTM1_IRQHandler ; 14, 30, 0x078, + DCD _RESERVED ; 15, 31, 0x07C, + DCD _RESERVED ; 16, 32, 0x080, + DCD BFTM0_IRQHandler ; 17, 33, 0x084, + DCD BFTM1_IRQHandler ; 18, 34, 0x088, + DCD I2C0_IRQHandler ; 19, 35, 0x08C, + DCD _RESERVED ; 20, 36, 0x090, + DCD SPI0_IRQHandler ; 21, 37, 0x094, + DCD QSPI_IRQHandler ; 22, 38, 0x098, + DCD _RESERVED ; 23, 39, 0x09C, + DCD _RESERVED ; 24, 40, 0x0A0, + DCD UART0_IRQHandler ; 25, 41, 0x0A4, + DCD _RESERVED ; 26, 42, 0x0A8, + DCD MIDI_IRQHandler ; 27, 43, 0x0AC, + DCD _RESERVED ; 28, 44, 0x0B0, + DCD _RESERVED ; 29, 45, 0x0B4, + DCD PDMA_CH0_1_IRQHandler ; 30, 46, 0x0B8, + DCD PDMA_CH2_5_IRQHandler ; 31, 47, 0x0BC, + +; Reset handler routine +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception Handlers +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP + +HardFault_Handler PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP + +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP + +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP + +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + EXPORT LVD_BOD_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT EVWUP_IRQHandler [WEAK] + EXPORT EXTI0_1_IRQHandler [WEAK] + EXPORT EXTI2_3_IRQHandler [WEAK] + EXPORT EXTI4_15_IRQHandler [WEAK] + EXPORT ADC_IRQHandler [WEAK] + EXPORT GPTM0_IRQHandler [WEAK] + EXPORT SCTM0_IRQHandler [WEAK] + EXPORT SCTM1_IRQHandler [WEAK] + EXPORT BFTM0_IRQHandler [WEAK] + EXPORT BFTM1_IRQHandler [WEAK] + EXPORT I2C0_IRQHandler [WEAK] + EXPORT SPI0_IRQHandler [WEAK] + EXPORT QSPI_IRQHandler [WEAK] + EXPORT UART0_IRQHandler [WEAK] + EXPORT MIDI_IRQHandler [WEAK] + EXPORT PDMA_CH0_1_IRQHandler [WEAK] + EXPORT PDMA_CH2_5_IRQHandler [WEAK] + +LVD_BOD_IRQHandler +RTC_IRQHandler +FLASH_IRQHandler +EVWUP_IRQHandler +EXTI0_1_IRQHandler +EXTI2_3_IRQHandler +EXTI4_15_IRQHandler +ADC_IRQHandler +GPTM0_IRQHandler +SCTM0_IRQHandler +SCTM1_IRQHandler +BFTM0_IRQHandler +BFTM1_IRQHandler +I2C0_IRQHandler +SPI0_IRQHandler +QSPI_IRQHandler +UART0_IRQHandler +MIDI_IRQHandler +PDMA_CH0_1_IRQHandler +PDMA_CH2_5_IRQHandler + B . + ENDP + + ALIGN + +;******************************************************************************* +; User Stack and Heap initialization +;******************************************************************************* + IF :DEF:__MICROLIB + + EXPORT __HT_check_heap + EXPORT __HT_check_sp + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, = (Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + + ENDIF + + END diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f5xxxx_11.s b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f5xxxx_11.s new file mode 100644 index 0000000000..784096cf66 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f5xxxx_11.s @@ -0,0 +1,245 @@ +;/*---------------------------------------------------------------------------------------------------------*/ +;/* Holtek Semiconductor Inc. */ +;/* */ +;/* Copyright (C) Holtek Semiconductor Inc. */ +;/* All rights reserved. */ +;/* */ +;/*----------------------------------------------------------------------------------------------------------- +; File Name : startup_ht32f5xxxx_11.s +; Version : $Rev:: 5991 $ +; Date : $Date:: 2022-06-23 #$ +; Description : Startup code. +;-----------------------------------------------------------------------------------------------------------*/ + +; Supported Device +; ======================================== +; HT32F67041, HT32F67051 + +;/* <<< Use Configuration Wizard in Context Menu >>> */ + +;// HT32 Device +;// Select HT32 Device for the assembly setting. +;// Notice that the project's Asm Define has the higher priority. +;// <0=> By Project Asm Define +;// <22=> HT32F67041/51 +USE_HT32_CHIP_SET EQU 0 ; Notice that the project's Asm Define has the higher priority. + +_HT32FWID EQU 0xFFFFFFFF +;_HT32FWID EQU 0x00067041 +;_HT32FWID EQU 0x00067051 + +HT32F67041_51 EQU 22 + + IF USE_HT32_CHIP_SET=0 + ; Use project's Asm Define setting (default) + ELSE + IF :DEF:USE_HT32_CHIP + ; Use project's Asm Define setting (higher priority than the "USE_HT32_CHIP_SET") + ELSE + ; Use "USE_HT32_CHIP_SET" in the "startup_ht32xxxxx_xx.s" file +USE_HT32_CHIP EQU USE_HT32_CHIP_SET + ENDIF + ENDIF + +; Amount of memory (in bytes) allocated for Stack and Heap +; Tailor those values to your application needs +;// Stack Size (in Bytes, must 8 byte aligned) <0-8192:8> +Stack_Size EQU 512 + + AREA STACK, NOINIT, READWRITE, ALIGN = 3 +__HT_check_sp +Stack_Mem SPACE Stack_Size +__initial_sp + +;// Heap Size (in Bytes) <0-8192:8> +Heap_Size EQU 0 + + AREA HEAP, NOINIT, READWRITE, ALIGN = 3 +__HT_check_heap +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + PRESERVE8 + THUMB + +;******************************************************************************* +; Fill-up the Vector Table entries with the exceptions ISR address +;******************************************************************************* + AREA RESET, CODE, READONLY + EXPORT __Vectors +_RESERVED EQU 0xFFFFFFFF +__Vectors + DCD __initial_sp ; ---, 00, 0x000, Top address of Stack + DCD Reset_Handler ; ---, 01, 0x004, Reset Handler + DCD NMI_Handler ; -14, 02, 0x008, NMI Handler + DCD HardFault_Handler ; -13, 03, 0x00C, Hard Fault Handler + DCD _RESERVED ; ---, 04, 0x010, Reserved + DCD _RESERVED ; ---, 05, 0x014, Reserved + DCD _RESERVED ; ---, 06, 0x018, Reserved + DCD _RESERVED ; ---, 07, 0x01C, Reserved + DCD _HT32FWID ; ---, 08, 0x020, Reserved + DCD _RESERVED ; ---, 09, 0x024, Reserved + DCD _RESERVED ; ---, 10, 0x028, Reserved + DCD SVC_Handler ; -05, 11, 0x02C, SVC Handler + DCD _RESERVED ; ---, 12, 0x030, Reserved + DCD _RESERVED ; ---, 13, 0x034, Reserved + DCD PendSV_Handler ; -02, 14, 0x038, PendSV Handler + DCD SysTick_Handler ; -01, 15, 0x03C, SysTick Handler + + ; External Interrupt Handler + DCD LVD_BOD_IRQHandler ; 00, 16, 0x040, + DCD RTC_IRQHandler ; 01, 17, 0x044, + DCD FLASH_IRQHandler ; 02, 18, 0x048, + DCD EVWUP_IRQHandler ; 03, 19, 0x04C, + DCD EXTI0_1_IRQHandler ; 04, 20, 0x050, + DCD EXTI2_3_IRQHandler ; 05, 21, 0x054, + DCD EXTI4_15_IRQHandler ; 06, 22, 0x058, + DCD _RESERVED ; 07, 23, 0x05C, + DCD ADC_IRQHandler ; 08, 24, 0x060, + DCD AES_IRQHandler ; 09, 25, 0x064, + DCD _RESERVED ; 10, 26, 0x068, + DCD RF_IRQHandler ; 11, 27, 0x06C, + DCD GPTM0_IRQHandler ; 12, 28, 0x070, + DCD SCTM0_IRQHandler ; 13, 29, 0x074, + DCD SCTM1_IRQHandler ; 14, 30, 0x078, + DCD SCTM2_IRQHandler ; 15, 31, 0x07C, + DCD SCTM3_IRQHandler ; 16, 32, 0x080, + DCD BFTM0_IRQHandler ; 17, 33, 0x084, + DCD BFTM1_IRQHandler ; 18, 34, 0x088, + DCD I2C0_IRQHandler ; 19, 35, 0x08C, + DCD I2C1_IRQHandler ; 20, 36, 0x090, + DCD SPI0_IRQHandler ; 21, 37, 0x094, + DCD SPI1_IRQHandler ; 22, 38, 0x098, + DCD _RESERVED ; 23, 39, 0x09C, + DCD _RESERVED ; 24, 40, 0x0A0, + DCD UART0_IRQHandler ; 25, 41, 0x0A4, + DCD UART1_IRQHandler ; 26, 42, 0x0A8, + DCD _RESERVED ; 27, 43, 0x0AC, + DCD _RESERVED ; 28, 44, 0x0B0, + DCD _RESERVED ; 29, 45, 0x0B4, + DCD PDMA_CH0_1_IRQHandler ; 30, 46, 0x0B8, + DCD PDMA_CH2_5_IRQHandler ; 31, 47, 0x0BC, + +; Reset handler routine +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception Handlers +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP + +HardFault_Handler PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP + +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP + +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP + +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + EXPORT LVD_BOD_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT EVWUP_IRQHandler [WEAK] + EXPORT EXTI0_1_IRQHandler [WEAK] + EXPORT EXTI2_3_IRQHandler [WEAK] + EXPORT EXTI4_15_IRQHandler [WEAK] + EXPORT ADC_IRQHandler [WEAK] + EXPORT AES_IRQHandler [WEAK] + EXPORT RF_IRQHandler [WEAK] + EXPORT GPTM0_IRQHandler [WEAK] + EXPORT SCTM0_IRQHandler [WEAK] + EXPORT SCTM1_IRQHandler [WEAK] + EXPORT SCTM2_IRQHandler [WEAK] + EXPORT SCTM3_IRQHandler [WEAK] + EXPORT BFTM0_IRQHandler [WEAK] + EXPORT BFTM1_IRQHandler [WEAK] + EXPORT I2C0_IRQHandler [WEAK] + EXPORT I2C1_IRQHandler [WEAK] + EXPORT SPI0_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT UART0_IRQHandler [WEAK] + EXPORT UART1_IRQHandler [WEAK] + EXPORT PDMA_CH0_1_IRQHandler [WEAK] + EXPORT PDMA_CH2_5_IRQHandler [WEAK] + +LVD_BOD_IRQHandler +RTC_IRQHandler +FLASH_IRQHandler +EVWUP_IRQHandler +EXTI0_1_IRQHandler +EXTI2_3_IRQHandler +EXTI4_15_IRQHandler +ADC_IRQHandler +AES_IRQHandler +RF_IRQHandler +GPTM0_IRQHandler +SCTM0_IRQHandler +SCTM1_IRQHandler +SCTM2_IRQHandler +SCTM3_IRQHandler +BFTM0_IRQHandler +BFTM1_IRQHandler +I2C0_IRQHandler +I2C1_IRQHandler +SPI0_IRQHandler +SPI1_IRQHandler +UART0_IRQHandler +UART1_IRQHandler +PDMA_CH0_1_IRQHandler +PDMA_CH2_5_IRQHandler + B . + ENDP + + ALIGN + +;******************************************************************************* +; User Stack and Heap initialization +;******************************************************************************* + IF :DEF:__MICROLIB + + EXPORT __HT_check_heap + EXPORT __HT_check_sp + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, = (Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + + ENDIF + + END diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f5xxxx_12.s b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f5xxxx_12.s new file mode 100644 index 0000000000..45e5c70109 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f5xxxx_12.s @@ -0,0 +1,278 @@ +;/*---------------------------------------------------------------------------------------------------------*/ +;/* Holtek Semiconductor Inc. */ +;/* */ +;/* Copyright (C) Holtek Semiconductor Inc. */ +;/* All rights reserved. */ +;/* */ +;/*----------------------------------------------------------------------------------------------------------- +; File Name : startup_ht32f5xxxx_12.s +; Version : $Rev:: 5740 $ +; Date : $Date:: 2022-02-17 #$ +; Description : Startup code. +;-----------------------------------------------------------------------------------------------------------*/ + +; Supported Device +; ======================================== +; HT32F61141 + +;/* <<< Use Configuration Wizard in Context Menu >>> */ + +;// HT32 Device +;// Select HT32 Device for the assembly setting. +;// Notice that the project's Asm Define has the higher priority. +;// <0=> By Project Asm Define +;// <23=> HT32F61141 +USE_HT32_CHIP_SET EQU 0 ; Notice that the project's Asm Define has the higher priority. + +_HT32FWID EQU 0xFFFFFFFF +;_HT32FWID EQU 0x00061141 + +HT32F61141 EQU 23 + + IF USE_HT32_CHIP_SET=0 + ; Use project's Asm Define setting (default) + ELSE + IF :DEF:USE_HT32_CHIP + ; Use project's Asm Define setting (higher priority than the "USE_HT32_CHIP_SET") + ELSE + ; Use "USE_HT32_CHIP_SET" in the "startup_ht32xxxxx_xx.s" file +USE_HT32_CHIP EQU USE_HT32_CHIP_SET + ENDIF + ENDIF + +; Amount of memory (in bytes) allocated for Stack and Heap +; Tailor those values to your application needs +;// Stack Size (in Bytes, must 8 byte aligned) <0-16384:8> +Stack_Size EQU 512 + + AREA STACK, NOINIT, READWRITE, ALIGN = 3 +__HT_check_sp +Stack_Mem SPACE Stack_Size +__initial_sp + +;// Heap Size (in Bytes) <0-16384:8> +Heap_Size EQU 0 + + AREA HEAP, NOINIT, READWRITE, ALIGN = 3 +__HT_check_heap +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + PRESERVE8 + THUMB + +;******************************************************************************* +; Fill-up the Vector Table entries with the exceptions ISR address +;******************************************************************************* + AREA RESET, CODE, READONLY + EXPORT __Vectors +_RESERVED EQU 0xFFFFFFFF +__Vectors + DCD __initial_sp ; ---, 00, 0x000, Top address of Stack + DCD Reset_Handler ; ---, 01, 0x004, Reset Handler + DCD NMI_Handler ; -14, 02, 0x008, NMI Handler + DCD HardFault_Handler ; -13, 03, 0x00C, Hard Fault Handler + DCD _RESERVED ; ---, 04, 0x010, Reserved + DCD _RESERVED ; ---, 05, 0x014, Reserved + DCD _RESERVED ; ---, 06, 0x018, Reserved + DCD _RESERVED ; ---, 07, 0x01C, Reserved + DCD _HT32FWID ; ---, 08, 0x020, Reserved + DCD _RESERVED ; ---, 09, 0x024, Reserved + DCD _RESERVED ; ---, 10, 0x028, Reserved + DCD SVC_Handler ; -05, 11, 0x02C, SVC Handler + DCD _RESERVED ; ---, 12, 0x030, Reserved + DCD _RESERVED ; ---, 13, 0x034, Reserved + DCD PendSV_Handler ; -02, 14, 0x038, PendSV Handler + DCD SysTick_Handler ; -01, 15, 0x03C, SysTick Handler + + ; External Interrupt Handler + DCD LVD_BOD_IRQHandler ; 00, 16, 0x040, + DCD RTC_IRQHandler ; 01, 17, 0x044, + DCD FLASH_IRQHandler ; 02, 18, 0x048, + DCD EVWUP_IRQHandler ; 03, 19, 0x04C, + DCD EXTI0_1_IRQHandler ; 04, 20, 0x050, + DCD EXTI2_3_IRQHandler ; 05, 21, 0x054, + DCD EXTI4_15_IRQHandler ; 06, 22, 0x058, + DCD _RESERVED ; 07, 23, 0x05C, + DCD _RESERVED ; 08, 24, 0x060, + DCD _RESERVED ; 09, 25, 0x064, + DCD _RESERVED ; 10, 26, 0x068, + DCD _RESERVED ; 11, 27, 0x06C, + DCD GPTM0_IRQHandler ; 12, 28, 0x070, + DCD SCTM0_IRQHandler ; 13, 29, 0x074, + DCD SCTM1_IRQHandler ; 14, 30, 0x078, + DCD _RESERVED ; 15, 31, 0x07C, + DCD _RESERVED ; 16, 32, 0x080, + DCD BFTM0_IRQHandler ; 17, 33, 0x084, + DCD BFTM1_IRQHandler ; 18, 34, 0x088, + DCD I2C0_IRQHandler ; 19, 35, 0x08C, + DCD _RESERVED ; 20, 36, 0x090, + DCD SPI0_IRQHandler ; 21, 37, 0x094, + DCD _RESERVED ; 22, 38, 0x098, + DCD _RESERVED ; 23, 39, 0x09C, + DCD _RESERVED ; 24, 40, 0x0A0, + DCD UART0_IRQHandler ; 25, 41, 0x0A4, + DCD UART1_IRQHandler ; 26, 42, 0x0A8, + DCD SCI_IRQHandler ; 27, 43, 0x0AC, + DCD _RESERVED ; 28, 44, 0x0B0, + DCD USB_IRQHandler ; 29, 45, 0x0B4, + +; Reset handler routine +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + LDR R0, =BootProcess + BLX R0 + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +BootProcess PROC + LDR R0, =0x40080300 + LDR R1,[R0, #0x10] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x14] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x18] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x1C] + CMP R1, #0 + BEQ BP2 +BP1 LDR R0, =0x40080180 + LDR R1,[R0, #0xC] + LSLS R1, R1, #4 + LSRS R1, R1, #20 + CMP R1, #0 + BEQ BP3 + CMP R1, #5 + BEQ BP3 + CMP R1, #6 + BEQ BP3 +BP2 DSB + LDR R0, =0x20000000 + LDR R1, =0x05fa0004 + STR R1, [R0] + LDR R1, =0xe000ed00 + LDR R0, =0x05fa0004 + STR R0, [R1, #0xC] + DSB + B . +BP3 LDR R0, =0x20000000 + LDR R1, [R0] + LDR R0, =0x05fa0004 + CMP R0, R1 + BEQ BP4 + BX LR +BP4 LDR R0, =0x40088100 + LDR R1, =0x00000001 + STR R1, [R0] + LDR R0, =0x20000000 + LDR R1, =0x0 + STR R1, [R0] + BX LR + ENDP + +; Dummy Exception Handlers +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP + +HardFault_Handler PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP + +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP + +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP + +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + EXPORT LVD_BOD_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT EVWUP_IRQHandler [WEAK] + EXPORT EXTI0_1_IRQHandler [WEAK] + EXPORT EXTI2_3_IRQHandler [WEAK] + EXPORT EXTI4_15_IRQHandler [WEAK] + EXPORT GPTM0_IRQHandler [WEAK] + EXPORT SCTM0_IRQHandler [WEAK] + EXPORT SCTM1_IRQHandler [WEAK] + EXPORT BFTM0_IRQHandler [WEAK] + EXPORT BFTM1_IRQHandler [WEAK] + EXPORT I2C0_IRQHandler [WEAK] + EXPORT SPI0_IRQHandler [WEAK] + EXPORT UART0_IRQHandler [WEAK] + EXPORT UART1_IRQHandler [WEAK] + EXPORT SCI_IRQHandler [WEAK] + EXPORT USB_IRQHandler [WEAK] + +LVD_BOD_IRQHandler +RTC_IRQHandler +FLASH_IRQHandler +EVWUP_IRQHandler +EXTI0_1_IRQHandler +EXTI2_3_IRQHandler +EXTI4_15_IRQHandler +GPTM0_IRQHandler +SCTM0_IRQHandler +SCTM1_IRQHandler +BFTM0_IRQHandler +BFTM1_IRQHandler +I2C0_IRQHandler +SPI0_IRQHandler +UART0_IRQHandler +UART1_IRQHandler +SCI_IRQHandler +USB_IRQHandler + B . + ENDP + + ALIGN + +;******************************************************************************* +; User Stack and Heap initialization +;******************************************************************************* + IF :DEF:__MICROLIB + + EXPORT __HT_check_heap + EXPORT __HT_check_sp + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, = (Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + + ENDIF + + END diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f5xxxx_13.s b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f5xxxx_13.s new file mode 100644 index 0000000000..f03c345a43 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f5xxxx_13.s @@ -0,0 +1,235 @@ +;/*---------------------------------------------------------------------------------------------------------*/ +;/* Holtek Semiconductor Inc. */ +;/* */ +;/* Copyright (C) Holtek Semiconductor Inc. */ +;/* All rights reserved. */ +;/* */ +;/*----------------------------------------------------------------------------------------------------------- +; File Name : startup_ht32f5xxxx_13.s +; Version : $Rev:: 7119 $ +; Date : $Date:: 2023-08-15 #$ +; Description : Startup code. +;-----------------------------------------------------------------------------------------------------------*/ + +; Supported Device +; ======================================== +; HT32F50020, HT32F50030 +; HT32F61630 +; HT32F61030 + +;/* <<< Use Configuration Wizard in Context Menu >>> */ + +;// HT32 Device +;// Select HT32 Device for the assembly setting. +;// Notice that the project's Asm Define has the higher priority. +;// <0=> By Project Asm Define +;// <25=> HT32F50020/30 +;// <25=> HT32F61630 +;// <25=> HT32F61030 +USE_HT32_CHIP_SET EQU 0 ; Notice that the project's Asm Define has the higher priority. + +_HT32FWID EQU 0xFFFFFFFF +;_HT32FWID EQU 0x00050020 +;_HT32FWID EQU 0x00050030 +;_HT32FWID EQU 0x00061630 +;_HT32FWID EQU 0x00061030 + +HT32F50020_30 EQU 25 +HT32F61630 EQU 25 +HT32F61030 EQU 25 + + IF USE_HT32_CHIP_SET=0 + ; Use project's Asm Define setting (default) + ELSE + IF :DEF:USE_HT32_CHIP + ; Use project's Asm Define setting (higher priority than the "USE_HT32_CHIP_SET") + ELSE + ; Use "USE_HT32_CHIP_SET" in the "startup_ht32xxxxx_xx.s" file +USE_HT32_CHIP EQU USE_HT32_CHIP_SET + ENDIF + ENDIF + +; Amount of memory (in bytes) allocated for Stack and Heap +; Tailor those values to your application needs +;// Stack Size (in Bytes, must 8 byte aligned) <0-2048:8> +Stack_Size EQU 512 + + AREA STACK, NOINIT, READWRITE, ALIGN = 3 +__HT_check_sp +Stack_Mem SPACE Stack_Size +__initial_sp + +;// Heap Size (in Bytes) <0-2048:8> +Heap_Size EQU 0 + + AREA HEAP, NOINIT, READWRITE, ALIGN = 3 +__HT_check_heap +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + PRESERVE8 + THUMB + +;******************************************************************************* +; Fill-up the Vector Table entries with the exceptions ISR address +;******************************************************************************* + AREA RESET, CODE, READONLY + EXPORT __Vectors +_RESERVED EQU 0xFFFFFFFF +__Vectors + DCD __initial_sp ; ---, 00, 0x000, Top address of Stack + DCD Reset_Handler ; ---, 01, 0x004, Reset Handler + DCD NMI_Handler ; -14, 02, 0x008, NMI Handler + DCD HardFault_Handler ; -13, 03, 0x00C, Hard Fault Handler + DCD _RESERVED ; ---, 04, 0x010, Reserved + DCD _RESERVED ; ---, 05, 0x014, Reserved + DCD _RESERVED ; ---, 06, 0x018, Reserved + DCD _RESERVED ; ---, 07, 0x01C, Reserved + DCD _HT32FWID ; ---, 08, 0x020, Reserved + DCD _RESERVED ; ---, 09, 0x024, Reserved + DCD _RESERVED ; ---, 10, 0x028, Reserved + DCD SVC_Handler ; -05, 11, 0x02C, SVC Handler + DCD _RESERVED ; ---, 12, 0x030, Reserved + DCD _RESERVED ; ---, 13, 0x034, Reserved + DCD PendSV_Handler ; -02, 14, 0x038, PendSV Handler + DCD SysTick_Handler ; -01, 15, 0x03C, SysTick Handler + + ; External Interrupt Handler + DCD LVD_BOD_IRQHandler ; 00, 16, 0x040, + DCD RTC_IRQHandler ; 01, 17, 0x044, + DCD FLASH_IRQHandler ; 02, 18, 0x048, + DCD EVWUP_IRQHandler ; 03, 19, 0x04C, + DCD EXTI0_1_IRQHandler ; 04, 20, 0x050, + DCD EXTI2_3_IRQHandler ; 05, 21, 0x054, + DCD EXTI4_7_IRQHandler ; 06, 22, 0x058, + DCD _RESERVED ; 07, 23, 0x05C, + DCD ADC_IRQHandler ; 08, 24, 0x060, + DCD _RESERVED ; 09, 25, 0x064, + DCD _RESERVED ; 10, 26, 0x068, + DCD _RESERVED ; 11, 27, 0x06C, + DCD _RESERVED ; 12, 28, 0x070, + DCD SCTM0_IRQHandler ; 13, 29, 0x074, + DCD SCTM1_IRQHandler ; 14, 30, 0x078, + DCD SCTM2_IRQHandler ; 15, 31, 0x07C, + DCD _RESERVED ; 16, 32, 0x080, + DCD BFTM0_IRQHandler ; 17, 33, 0x084, + DCD _RESERVED ; 18, 34, 0x088, + DCD I2C0_IRQHandler ; 19, 35, 0x08C, + DCD _RESERVED ; 20, 36, 0x090, + DCD SPI0_IRQHandler ; 21, 37, 0x094, + DCD _RESERVED ; 22, 38, 0x098, + DCD _RESERVED ; 23, 39, 0x09C, + DCD _RESERVED ; 24, 40, 0x0A0, + DCD UART0_IRQHandler ; 25, 41, 0x0A4, + DCD UART1_IRQHandler ; 26, 42, 0x0A8, + DCD _RESERVED ; 27, 43, 0x0AC, + DCD _RESERVED ; 28, 44, 0x0B0, + DCD LEDC_IRQHandler ; 29, 45, 0x0B4, + +; Reset handler routine +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception Handlers +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP + +HardFault_Handler PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP + +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP + +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP + +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + EXPORT LVD_BOD_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT EVWUP_IRQHandler [WEAK] + EXPORT EXTI0_1_IRQHandler [WEAK] + EXPORT EXTI2_3_IRQHandler [WEAK] + EXPORT EXTI4_7_IRQHandler [WEAK] + EXPORT ADC_IRQHandler [WEAK] + EXPORT SCTM0_IRQHandler [WEAK] + EXPORT SCTM1_IRQHandler [WEAK] + EXPORT SCTM2_IRQHandler [WEAK] + EXPORT BFTM0_IRQHandler [WEAK] + EXPORT I2C0_IRQHandler [WEAK] + EXPORT SPI0_IRQHandler [WEAK] + EXPORT UART0_IRQHandler [WEAK] + EXPORT UART1_IRQHandler [WEAK] + EXPORT LEDC_IRQHandler [WEAK] + +LVD_BOD_IRQHandler +RTC_IRQHandler +FLASH_IRQHandler +EVWUP_IRQHandler +EXTI0_1_IRQHandler +EXTI2_3_IRQHandler +EXTI4_7_IRQHandler +ADC_IRQHandler +SCTM0_IRQHandler +SCTM1_IRQHandler +SCTM2_IRQHandler +BFTM0_IRQHandler +I2C0_IRQHandler +SPI0_IRQHandler +UART0_IRQHandler +UART1_IRQHandler +LEDC_IRQHandler + B . + ENDP + + ALIGN + +;******************************************************************************* +; User Stack and Heap initialization +;******************************************************************************* + IF :DEF:__MICROLIB + + EXPORT __HT_check_heap + EXPORT __HT_check_sp + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, = (Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + + ENDIF + + END diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f5xxxx_14.s b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f5xxxx_14.s new file mode 100644 index 0000000000..a76b5da417 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f5xxxx_14.s @@ -0,0 +1,264 @@ +;/*---------------------------------------------------------------------------------------------------------*/ +;/* Holtek Semiconductor Inc. */ +;/* */ +;/* Copyright (C) Holtek Semiconductor Inc. */ +;/* All rights reserved. */ +;/* */ +;/*----------------------------------------------------------------------------------------------------------- +; File Name : startup_ht32f5xxxx_14.s +; Version : $Rev:: 6793 $ +; Date : $Date:: 2023-03-14 #$ +; Description : Startup code. +;-----------------------------------------------------------------------------------------------------------*/ + +; Supported Device +; ======================================== +; HT32F50442, HT32F50452 +; HT32F50431, HT32F50441 + +;/* <<< Use Configuration Wizard in Context Menu >>> */ + +;// HT32 Device +;// Select HT32 Device for the assembly setting. +;// Notice that the project's Asm Define has the higher priority. +;// <0=> By Project Asm Define +;// <26=> HT32F50442/52 +;// <30=> HT32F50431/41 +USE_HT32_CHIP_SET EQU 0 ; Notice that the project's Asm Define has the higher priority. + +_HT32FWID EQU 0xFFFFFFFF +;_HT32FWID EQU 0x00050442 +;_HT32FWID EQU 0x00050452 +;_HT32FWID EQU 0x00050431 +;_HT32FWID EQU 0x00050441 + +HT32F50442_52 EQU 26 +HT32F50431_41 EQU 30 + + IF USE_HT32_CHIP_SET=0 + ; Use project's Asm Define setting (default) + ELSE + IF :DEF:USE_HT32_CHIP + ; Use project's Asm Define setting (higher priority than the "USE_HT32_CHIP_SET") + ELSE + ; Use "USE_HT32_CHIP_SET" in the "startup_ht32xxxxx_xx.s" file +USE_HT32_CHIP EQU USE_HT32_CHIP_SET + ENDIF + ENDIF + +; Amount of memory (in bytes) allocated for Stack and Heap +; Tailor those values to your application needs +;// Stack Size (in Bytes, must 8 byte aligned) <0-16384:8> +Stack_Size EQU 512 + + AREA STACK, NOINIT, READWRITE, ALIGN = 3 +__HT_check_sp +Stack_Mem SPACE Stack_Size +__initial_sp + +;// Heap Size (in Bytes) <0-16384:8> +Heap_Size EQU 0 + + AREA HEAP, NOINIT, READWRITE, ALIGN = 3 +__HT_check_heap +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + PRESERVE8 + THUMB + +;******************************************************************************* +; Fill-up the Vector Table entries with the exceptions ISR address +;******************************************************************************* + AREA RESET, CODE, READONLY + EXPORT __Vectors +_RESERVED EQU 0xFFFFFFFF +__Vectors + DCD __initial_sp ; ---, 00, 0x000, Top address of Stack + DCD Reset_Handler ; ---, 01, 0x004, Reset Handler + DCD NMI_Handler ; -14, 02, 0x008, NMI Handler + DCD HardFault_Handler ; -13, 03, 0x00C, Hard Fault Handler + DCD _RESERVED ; ---, 04, 0x010, Reserved + DCD _RESERVED ; ---, 05, 0x014, Reserved + DCD _RESERVED ; ---, 06, 0x018, Reserved + DCD _RESERVED ; ---, 07, 0x01C, Reserved + DCD _HT32FWID ; ---, 08, 0x020, Reserved + DCD _RESERVED ; ---, 09, 0x024, Reserved + DCD _RESERVED ; ---, 10, 0x028, Reserved + DCD SVC_Handler ; -05, 11, 0x02C, SVC Handler + DCD _RESERVED ; ---, 12, 0x030, Reserved + DCD _RESERVED ; ---, 13, 0x034, Reserved + DCD PendSV_Handler ; -02, 14, 0x038, PendSV Handler + DCD SysTick_Handler ; -01, 15, 0x03C, SysTick Handler + + ; External Interrupt Handler + DCD LVD_BOD_IRQHandler ; 00, 16, 0x040, + DCD RTC_IRQHandler ; 01, 17, 0x044, + DCD FLASH_IRQHandler ; 02, 18, 0x048, + DCD EVWUP_IRQHandler ; 03, 19, 0x04C, + DCD EXTI0_1_IRQHandler ; 04, 20, 0x050, + DCD EXTI2_3_IRQHandler ; 05, 21, 0x054, + DCD EXTI4_15_IRQHandler ; 06, 22, 0x058, + IF (USE_HT32_CHIP=HT32F50442_52) + DCD COMP_IRQHandler ; 07, 23, 0x05C, + ELSE + DCD _RESERVED ; 07, 23, 0x05C, + ENDIF + DCD ADC_IRQHandler ; 08, 24, 0x060, + DCD _RESERVED ; 09, 25, 0x064, + DCD MCTM0_IRQHandler ; 10, 26, 0x068, + DCD _RESERVED ; 11, 27, 0x06C, + DCD GPTM0_IRQHandler ; 12, 28, 0x070, + DCD _RESERVED ; 13, 29, 0x074, + DCD _RESERVED ; 14, 30, 0x078, + DCD PWM0_IRQHandler ; 15, 31, 0x07C, + IF (USE_HT32_CHIP=HT32F50442_52) + DCD PWM1_IRQHandler ; 16, 32, 0x080, + ELSE + DCD _RESERVED ; 16, 32, 0x080, + ENDIF + DCD BFTM0_IRQHandler ; 17, 33, 0x084, + DCD BFTM1_IRQHandler ; 18, 34, 0x088, + DCD I2C0_IRQHandler ; 19, 35, 0x08C, + DCD I2C1_IRQHandler ; 20, 36, 0x090, + DCD SPI0_IRQHandler ; 21, 37, 0x094, + DCD SPI1_IRQHandler ; 22, 38, 0x098, + DCD USART0_IRQHandler ; 23, 39, 0x09C, + IF (USE_HT32_CHIP=HT32F50442_52) + DCD USART1_IRQHandler ; 24, 40, 0x0A0, + ELSE + DCD _RESERVED ; 24, 40, 0x0A0, + ENDIF + DCD UART0_IRQHandler ; 25, 41, 0x0A4, + DCD UART1_IRQHandler ; 26, 42, 0x0A8, + DCD _RESERVED ; 27, 43, 0x0AC, + DCD _RESERVED ; 28, 44, 0x0B0, + DCD LEDC_IRQHandler ; 29, 45, 0x0B4, + DCD PDMA_CH0_1_IRQHandler ; 30, 46, 0x0B8, + DCD PDMA_CH2_5_IRQHandler ; 31, 47, 0x0BC, + +; Reset handler routine +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception Handlers +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP + +HardFault_Handler PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP + +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP + +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP + +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + EXPORT LVD_BOD_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT EVWUP_IRQHandler [WEAK] + EXPORT EXTI0_1_IRQHandler [WEAK] + EXPORT EXTI2_3_IRQHandler [WEAK] + EXPORT EXTI4_15_IRQHandler [WEAK] + EXPORT COMP_IRQHandler [WEAK] + EXPORT ADC_IRQHandler [WEAK] + EXPORT MCTM0_IRQHandler [WEAK] + EXPORT GPTM0_IRQHandler [WEAK] + EXPORT PWM0_IRQHandler [WEAK] + EXPORT PWM1_IRQHandler [WEAK] + EXPORT BFTM0_IRQHandler [WEAK] + EXPORT BFTM1_IRQHandler [WEAK] + EXPORT I2C0_IRQHandler [WEAK] + EXPORT I2C1_IRQHandler [WEAK] + EXPORT SPI0_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT USART0_IRQHandler [WEAK] + EXPORT USART1_IRQHandler [WEAK] + EXPORT UART0_IRQHandler [WEAK] + EXPORT UART1_IRQHandler [WEAK] + EXPORT LEDC_IRQHandler [WEAK] + EXPORT PDMA_CH0_1_IRQHandler [WEAK] + EXPORT PDMA_CH2_5_IRQHandler [WEAK] + +LVD_BOD_IRQHandler +RTC_IRQHandler +FLASH_IRQHandler +EVWUP_IRQHandler +EXTI0_1_IRQHandler +EXTI2_3_IRQHandler +EXTI4_15_IRQHandler +COMP_IRQHandler +ADC_IRQHandler +MCTM0_IRQHandler +GPTM0_IRQHandler +PWM0_IRQHandler +PWM1_IRQHandler +BFTM0_IRQHandler +BFTM1_IRQHandler +I2C0_IRQHandler +I2C1_IRQHandler +SPI0_IRQHandler +SPI1_IRQHandler +USART0_IRQHandler +USART1_IRQHandler +UART0_IRQHandler +UART1_IRQHandler +LEDC_IRQHandler +PDMA_CH0_1_IRQHandler +PDMA_CH2_5_IRQHandler + B . + ENDP + + ALIGN + +;******************************************************************************* +; User Stack and Heap initialization +;******************************************************************************* + IF :DEF:__MICROLIB + + EXPORT __HT_check_heap + EXPORT __HT_check_sp + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, = (Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + + ENDIF + + END diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f5xxxx_15.s b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f5xxxx_15.s new file mode 100644 index 0000000000..e261fa6021 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f5xxxx_15.s @@ -0,0 +1,266 @@ +;/*---------------------------------------------------------------------------------------------------------*/ +;/* Holtek Semiconductor Inc. */ +;/* */ +;/* Copyright (C) Holtek Semiconductor Inc. */ +;/* All rights reserved. */ +;/* */ +;/*----------------------------------------------------------------------------------------------------------- +; File Name : startup_ht32f5xxxx_15.s +; Version : $Rev:: 6874 $ +; Date : $Date:: 2023-05-03 #$ +; Description : Startup code. +;-----------------------------------------------------------------------------------------------------------*/ + +; Supported Device +; ======================================== +; HT32F53242, HT32F53252 +; HT32F53231, HT32F53241 + +;/* <<< Use Configuration Wizard in Context Menu >>> */ + +;// HT32 Device +;// Select HT32 Device for the assembly setting. +;// Notice that the project's Asm Define has the higher priority. +;// <0=> By Project Asm Define +;// <28=> HT32F53242/52 +;// <29=> HT32F53231/41 +USE_HT32_CHIP_SET EQU 0 ; Notice that the project's Asm Define has the higher priority. + +_HT32FWID EQU 0xFFFFFFFF +;_HT32FWID EQU 0x00053242 +;_HT32FWID EQU 0x00053252 +;_HT32FWID EQU 0x00053231 +;_HT32FWID EQU 0x00053241 + +HT32F53242_52 EQU 28 +HT32F53231_41 EQU 29 + + IF USE_HT32_CHIP_SET=0 + ; Use project's Asm Define setting (default) + ELSE + IF :DEF:USE_HT32_CHIP + ; Use project's Asm Define setting (higher priority than the "USE_HT32_CHIP_SET") + ELSE + ; Use "USE_HT32_CHIP_SET" in the "startup_ht32xxxxx_xx.s" file +USE_HT32_CHIP EQU USE_HT32_CHIP_SET + ENDIF + ENDIF + +; Amount of memory (in bytes) allocated for Stack and Heap +; Tailor those values to your application needs +;// Stack Size (in Bytes, must 8 byte aligned) <0-16384:8> +Stack_Size EQU 512 + + AREA STACK, NOINIT, READWRITE, ALIGN = 3 +__HT_check_sp +Stack_Mem SPACE Stack_Size +__initial_sp + +;// Heap Size (in Bytes) <0-16384:8> +Heap_Size EQU 0 + + AREA HEAP, NOINIT, READWRITE, ALIGN = 3 +__HT_check_heap +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + PRESERVE8 + THUMB + +;******************************************************************************* +; Fill-up the Vector Table entries with the exceptions ISR address +;******************************************************************************* + AREA RESET, CODE, READONLY + EXPORT __Vectors +_RESERVED EQU 0xFFFFFFFF +__Vectors + DCD __initial_sp ; ---, 00, 0x000, Top address of Stack + DCD Reset_Handler ; ---, 01, 0x004, Reset Handler + DCD NMI_Handler ; -14, 02, 0x008, NMI Handler + DCD HardFault_Handler ; -13, 03, 0x00C, Hard Fault Handler + DCD _RESERVED ; ---, 04, 0x010, Reserved + DCD _RESERVED ; ---, 05, 0x014, Reserved + DCD _RESERVED ; ---, 06, 0x018, Reserved + DCD _RESERVED ; ---, 07, 0x01C, Reserved + DCD _HT32FWID ; ---, 08, 0x020, Reserved + DCD _RESERVED ; ---, 09, 0x024, Reserved + DCD _RESERVED ; ---, 10, 0x028, Reserved + DCD SVC_Handler ; -05, 11, 0x02C, SVC Handler + DCD _RESERVED ; ---, 12, 0x030, Reserved + DCD _RESERVED ; ---, 13, 0x034, Reserved + DCD PendSV_Handler ; -02, 14, 0x038, PendSV Handler + DCD SysTick_Handler ; -01, 15, 0x03C, SysTick Handler + + ; External Interrupt Handler + DCD LVD_BOD_IRQHandler ; 00, 16, 0x040, + DCD RTC_IRQHandler ; 01, 17, 0x044, + DCD FLASH_IRQHandler ; 02, 18, 0x048, + DCD EVWUP_IRQHandler ; 03, 19, 0x04C, + DCD EXTI0_1_IRQHandler ; 04, 20, 0x050, + DCD EXTI2_3_IRQHandler ; 05, 21, 0x054, + DCD EXTI4_15_IRQHandler ; 06, 22, 0x058, + IF (USE_HT32_CHIP=HT32F53242_52) + DCD COMP_IRQHandler ; 07, 23, 0x05C, + ELSE + DCD _RESERVED ; 07, 23, 0x05C, + ENDIF + DCD ADC_IRQHandler ; 08, 24, 0x060, + DCD _RESERVED ; 09, 25, 0x064, + DCD MCTM0_IRQHandler ; 10, 26, 0x068, + DCD _RESERVED ; 11, 27, 0x06C, + DCD GPTM0_IRQHandler ; 12, 28, 0x070, + DCD _RESERVED ; 13, 29, 0x074, + DCD _RESERVED ; 14, 30, 0x078, + DCD PWM0_IRQHandler ; 15, 31, 0x07C, + IF (USE_HT32_CHIP=HT32F53242_52) + DCD PWM1_IRQHandler ; 16, 32, 0x080, + ELSE + DCD _RESERVED ; 16, 32, 0x080, + ENDIF + DCD BFTM0_IRQHandler ; 17, 33, 0x084, + DCD BFTM1_IRQHandler ; 18, 34, 0x088, + DCD I2C0_IRQHandler ; 19, 35, 0x08C, + DCD I2C1_IRQHandler ; 20, 36, 0x090, + DCD SPI0_IRQHandler ; 21, 37, 0x094, + DCD SPI1_IRQHandler ; 22, 38, 0x098, + DCD USART0_IRQHandler ; 23, 39, 0x09C, + IF (USE_HT32_CHIP=HT32F53242_52) + DCD USART1_IRQHandler ; 24, 40, 0x0A0, + ELSE + DCD _RESERVED ; 24, 40, 0x0A0, + ENDIF + DCD UART0_IRQHandler ; 25, 41, 0x0A4, + DCD UART1_IRQHandler ; 26, 42, 0x0A8, + DCD CAN0_IRQHandler ; 27, 43, 0x0AC, + DCD _RESERVED ; 28, 44, 0x0B0, + DCD LEDC_IRQHandler ; 29, 45, 0x0B4, + DCD PDMA_CH0_1_IRQHandler ; 30, 46, 0x0B8, + DCD PDMA_CH2_5_IRQHandler ; 31, 47, 0x0BC, + +; Reset handler routine +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception Handlers +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP + +HardFault_Handler PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP + +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP + +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP + +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + EXPORT LVD_BOD_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT EVWUP_IRQHandler [WEAK] + EXPORT EXTI0_1_IRQHandler [WEAK] + EXPORT EXTI2_3_IRQHandler [WEAK] + EXPORT EXTI4_15_IRQHandler [WEAK] + EXPORT COMP_IRQHandler [WEAK] + EXPORT ADC_IRQHandler [WEAK] + EXPORT MCTM0_IRQHandler [WEAK] + EXPORT GPTM0_IRQHandler [WEAK] + EXPORT PWM0_IRQHandler [WEAK] + EXPORT PWM1_IRQHandler [WEAK] + EXPORT BFTM0_IRQHandler [WEAK] + EXPORT BFTM1_IRQHandler [WEAK] + EXPORT I2C0_IRQHandler [WEAK] + EXPORT I2C1_IRQHandler [WEAK] + EXPORT SPI0_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT USART0_IRQHandler [WEAK] + EXPORT USART1_IRQHandler [WEAK] + EXPORT UART0_IRQHandler [WEAK] + EXPORT UART1_IRQHandler [WEAK] + EXPORT CAN0_IRQHandler [WEAK] + EXPORT LEDC_IRQHandler [WEAK] + EXPORT PDMA_CH0_1_IRQHandler [WEAK] + EXPORT PDMA_CH2_5_IRQHandler [WEAK] + +LVD_BOD_IRQHandler +RTC_IRQHandler +FLASH_IRQHandler +EVWUP_IRQHandler +EXTI0_1_IRQHandler +EXTI2_3_IRQHandler +EXTI4_15_IRQHandler +COMP_IRQHandler +ADC_IRQHandler +MCTM0_IRQHandler +GPTM0_IRQHandler +PWM0_IRQHandler +PWM1_IRQHandler +BFTM0_IRQHandler +BFTM1_IRQHandler +I2C0_IRQHandler +I2C1_IRQHandler +SPI0_IRQHandler +SPI1_IRQHandler +USART0_IRQHandler +USART1_IRQHandler +UART0_IRQHandler +UART1_IRQHandler +CAN0_IRQHandler +LEDC_IRQHandler +PDMA_CH0_1_IRQHandler +PDMA_CH2_5_IRQHandler + B . + ENDP + + ALIGN + +;******************************************************************************* +; User Stack and Heap initialization +;******************************************************************************* + IF :DEF:__MICROLIB + + EXPORT __HT_check_heap + EXPORT __HT_check_sp + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, = (Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + + ENDIF + + END diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f5xxxx_16.s b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f5xxxx_16.s new file mode 100644 index 0000000000..23328ec7c4 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f5xxxx_16.s @@ -0,0 +1,275 @@ +;/*---------------------------------------------------------------------------------------------------------*/ +;/* Holtek Semiconductor Inc. */ +;/* */ +;/* Copyright (C) Holtek Semiconductor Inc. */ +;/* All rights reserved. */ +;/* */ +;/*----------------------------------------------------------------------------------------------------------- +; File Name : startup_ht32f5xxxx_16.s +; Version : $Rev:: 7092 $ +; Date : $Date:: 2023-08-02 #$ +; Description : Startup code. +;-----------------------------------------------------------------------------------------------------------*/ + +; Supported Device +; ======================================== +; HT32F66242 +; HT32F66246 + +;/* <<< Use Configuration Wizard in Context Menu >>> */ + + + + + + + +USE_HT32_CHIP_SET EQU 0 ; Notice that the project's Asm Define has the higher priority. + +;_HT32FWID EQU 0xFFFFFFFF +;_HT32FWID EQU 0x00066246 + +HT32F66246 EQU 31 +HT32F66242 EQU 33 + + IF USE_HT32_CHIP_SET=0 + ; Use project's Asm Define setting (default) + ELSE + IF :DEF:USE_HT32_CHIP + ; Use project's Asm Define setting (higher priority than the "USE_HT32_CHIP_SET") + ELSE + ; Use "USE_HT32_CHIP_SET" in the "startup_ht32xxxxx_xx.s" file +USE_HT32_CHIP EQU USE_HT32_CHIP_SET + ENDIF + ENDIF + + IF (USE_HT32_CHIP=0) +_HT32FWID EQU 0x00066246 + ENDIF + IF (USE_HT32_CHIP=HT32F66246) +_HT32FWID EQU 0x00066246 + ENDIF + IF (USE_HT32_CHIP=HT32F66242) +_HT32FWID EQU 0x00066242 + ENDIF + +; Amount of memory (in bytes) allocated for Stack and Heap +; Tailor those values to your application needs +;// Stack Size (in Bytes, must 8 byte aligned) <0-8192:8> +Stack_Size EQU 512 + + AREA STACK, NOINIT, READWRITE, ALIGN = 3 +__HT_check_sp +Stack_Mem SPACE Stack_Size +__initial_sp + +;// Heap Size (in Bytes) <0-8192:8> +Heap_Size EQU 0 + + AREA HEAP, NOINIT, READWRITE, ALIGN = 3 +__HT_check_heap +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + PRESERVE8 + THUMB + +;******************************************************************************* +; Fill-up the Vector Table entries with the exceptions ISR address +;******************************************************************************* + AREA RESET, CODE, READONLY + EXPORT __Vectors +_RESERVED EQU 0xFFFFFFFF +__Vectors + DCD __initial_sp ; ---, 00, 0x000, Top address of Stack + DCD Reset_Handler ; ---, 01, 0x004, Reset Handler + DCD NMI_Handler ; -14, 02, 0x008, NMI Handler + DCD HardFault_Handler ; -13, 03, 0x00C, Hard Fault Handler + DCD _RESERVED ; ---, 04, 0x010, Reserved + DCD _RESERVED ; ---, 05, 0x014, Reserved + DCD _RESERVED ; ---, 06, 0x018, Reserved + DCD _RESERVED ; ---, 07, 0x01C, Reserved + DCD _HT32FWID ; ---, 08, 0x020, Reserved + DCD _RESERVED ; ---, 09, 0x024, Reserved + DCD _RESERVED ; ---, 10, 0x028, Reserved + DCD SVC_Handler ; -05, 11, 0x02C, SVC Handler + DCD _RESERVED ; ---, 12, 0x030, Reserved + DCD _RESERVED ; ---, 13, 0x034, Reserved + DCD PendSV_Handler ; -02, 14, 0x038, PendSV Handler + DCD SysTick_Handler ; -01, 15, 0x03C, SysTick Handler + + ; External Interrupt Handler + DCD LVD_BOD_IRQHandler ; 00, 16, 0x040, + DCD RTC_IRQHandler ; 01, 17, 0x044, + DCD FLASH_IRQHandler ; 02, 18, 0x048, + DCD EVWUP_IRQHandler ; 03, 19, 0x04C, + DCD EXTI0_1_IRQHandler ; 04, 20, 0x050, + DCD EXTI2_3_IRQHandler ; 05, 21, 0x054, + DCD EXTI4_15_IRQHandler ; 06, 22, 0x058, + IF (USE_HT32_CHIP=HT32F66246) + DCD CAN0_IRQHandler ; 07, 23, 0x05C, + ELSE + DCD _RESERVED ; 07, 23, 0x05C, + ENDIF + DCD ADC_IRQHandler ; 08, 24, 0x060, + DCD CORDIC_IRQHandler ; 09, 25, 0x064, + DCD MCTM0_BRK_IRQHandler ; 10, 26, 0x068, + DCD MCTM0_UP_IRQHandler ; 11, 27, 0x06C, + DCD MCTM0_TR_UP2_IRQHandler ; 12, 28, 0x070, + DCD MCTM0_CC_IRQHandler ; 13, 29, 0x074, + DCD GPTM0_G_IRQHandler ; 14, 30, 0x078, + DCD GPTM0_VCLK_IRQHandler ; 15, 31, 0x07C, + DCD BFTM0_IRQHandler ; 16, 32, 0x080, + DCD BFTM1_IRQHandler ; 17, 33, 0x084, + DCD CMP0_IRQHandler ; 18, 34, 0x088, + DCD CMP1_IRQHandler ; 19, 35, 0x08C, + DCD PID_IRQHandler ; 20, 36, 0x090, + DCD I2C0_IRQHandler ; 21, 37, 0x094, + DCD SPI0_IRQHandler ; 22, 38, 0x098, + DCD USART0_IRQHandler ; 23, 39, 0x09C, + DCD UART0_IRQHandler ; 24, 40, 0x0A0, + DCD PDMA_CH0_1_IRQHandler ; 25, 41, 0x0A4, + DCD PDMA_CH2_3_IRQHandler ; 26, 42, 0x0A8, + DCD PDMA_CH4_5_IRQHandler ; 27, 43, 0x0AC, + DCD SCTM0_IRQHandler ; 28, 44, 0x0B0, + DCD SCTM1_IRQHandler ; 29, 45, 0x0B4, + DCD SCTM2_IRQHandler ; 30, 46, 0x0B8, + DCD SCTM3_IRQHandler ; 31, 47, 0x0BC, + +; Reset handler routine +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception Handlers +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP + +HardFault_Handler PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP + +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP + +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP + +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + EXPORT LVD_BOD_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT EVWUP_IRQHandler [WEAK] + EXPORT EXTI0_1_IRQHandler [WEAK] + EXPORT EXTI2_3_IRQHandler [WEAK] + EXPORT EXTI4_15_IRQHandler [WEAK] + EXPORT CAN0_IRQHandler [WEAK] + EXPORT ADC_IRQHandler [WEAK] + EXPORT CORDIC_IRQHandler [WEAK] + EXPORT MCTM0_BRK_IRQHandler [WEAK] + EXPORT MCTM0_UP_IRQHandler [WEAK] + EXPORT MCTM0_TR_UP2_IRQHandler [WEAK] + EXPORT MCTM0_CC_IRQHandler [WEAK] + EXPORT GPTM0_G_IRQHandler [WEAK] + EXPORT GPTM0_VCLK_IRQHandler [WEAK] + EXPORT BFTM0_IRQHandler [WEAK] + EXPORT BFTM1_IRQHandler [WEAK] + EXPORT CMP0_IRQHandler [WEAK] + EXPORT CMP1_IRQHandler [WEAK] + EXPORT PID_IRQHandler [WEAK] + EXPORT I2C0_IRQHandler [WEAK] + EXPORT SPI0_IRQHandler [WEAK] + EXPORT USART0_IRQHandler [WEAK] + EXPORT UART0_IRQHandler [WEAK] + EXPORT PDMA_CH0_1_IRQHandler [WEAK] + EXPORT PDMA_CH2_3_IRQHandler [WEAK] + EXPORT PDMA_CH4_5_IRQHandler [WEAK] + EXPORT SCTM0_IRQHandler [WEAK] + EXPORT SCTM1_IRQHandler [WEAK] + EXPORT SCTM2_IRQHandler [WEAK] + EXPORT SCTM3_IRQHandler [WEAK] + +LVD_BOD_IRQHandler +RTC_IRQHandler +FLASH_IRQHandler +EVWUP_IRQHandler +EXTI0_1_IRQHandler +EXTI2_3_IRQHandler +EXTI4_15_IRQHandler +CAN0_IRQHandler +ADC_IRQHandler +CORDIC_IRQHandler +MCTM0_BRK_IRQHandler +MCTM0_UP_IRQHandler +MCTM0_TR_UP2_IRQHandler +MCTM0_CC_IRQHandler +GPTM0_G_IRQHandler +GPTM0_VCLK_IRQHandler +BFTM0_IRQHandler +BFTM1_IRQHandler +CMP0_IRQHandler +CMP1_IRQHandler +PID_IRQHandler +I2C0_IRQHandler +SPI0_IRQHandler +USART0_IRQHandler +UART0_IRQHandler +PDMA_CH0_1_IRQHandler +PDMA_CH2_3_IRQHandler +PDMA_CH4_5_IRQHandler +SCTM0_IRQHandler +SCTM1_IRQHandler +SCTM2_IRQHandler +SCTM3_IRQHandler + B . + ENDP + + ALIGN + +;******************************************************************************* +; User Stack and Heap initialization +;******************************************************************************* + IF :DEF:__MICROLIB + + EXPORT __HT_check_heap + EXPORT __HT_check_sp + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, = (Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + + ENDIF + + END diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f5xxxx_17.s b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f5xxxx_17.s new file mode 100644 index 0000000000..0829021a82 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f5xxxx_17.s @@ -0,0 +1,239 @@ +;/*---------------------------------------------------------------------------------------------------------*/ +;/* Holtek Semiconductor Inc. */ +;/* */ +;/* Copyright (C) Holtek Semiconductor Inc. */ +;/* All rights reserved. */ +;/* */ +;/*----------------------------------------------------------------------------------------------------------- +; File Name : startup_ht32f5xxxx_17.s +; Version : $Rev:: 7027 $ +; Date : $Date:: 2023-07-18 #$ +; Description : Startup code. +;-----------------------------------------------------------------------------------------------------------*/ + +; Supported Device +; ======================================== +; HT32F52234, HT32F52244 + +;/* <<< Use Configuration Wizard in Context Menu >>> */ + +;// HT32 Device +;// Select HT32 Device for the assembly setting. +;// Notice that the project's Asm Define has the higher priority. +;// <0=> By Project Asm Define +;// <33=> HT32F52234/44 +USE_HT32_CHIP_SET EQU 0 ; Notice that the project's Asm Define has the higher priority. + +_HT32FWID EQU 0xFFFFFFFF +;_HT32FWID EQU 0x00052234 +;_HT32FWID EQU 0x00052244 + +HT32F52234_44 EQU 33 + + IF USE_HT32_CHIP_SET=0 + ; Use project's Asm Define setting (default) + ELSE + IF :DEF:USE_HT32_CHIP + ; Use project's Asm Define setting (higher priority than the "USE_HT32_CHIP_SET") + ELSE + ; Use "USE_HT32_CHIP_SET" in the "startup_ht32xxxxx_xx.s" file +USE_HT32_CHIP EQU USE_HT32_CHIP_SET + ENDIF + ENDIF + +; Amount of memory (in bytes) allocated for Stack and Heap +; Tailor those values to your application needs +;// Stack Size (in Bytes, must 8 byte aligned) <0-8192:8> +Stack_Size EQU 512 + + AREA STACK, NOINIT, READWRITE, ALIGN = 3 +__HT_check_sp +Stack_Mem SPACE Stack_Size +__initial_sp + +;// Heap Size (in Bytes) <0-8192:8> +Heap_Size EQU 0 + + AREA HEAP, NOINIT, READWRITE, ALIGN = 3 +__HT_check_heap +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + PRESERVE8 + THUMB + +;******************************************************************************* +; Fill-up the Vector Table entries with the exceptions ISR address +;******************************************************************************* + AREA RESET, CODE, READONLY + EXPORT __Vectors +_RESERVED EQU 0xFFFFFFFF +__Vectors + DCD __initial_sp ; ---, 00, 0x000, Top address of Stack + DCD Reset_Handler ; ---, 01, 0x004, Reset Handler + DCD NMI_Handler ; -14, 02, 0x008, NMI Handler + DCD HardFault_Handler ; -13, 03, 0x00C, Hard Fault Handler + DCD _RESERVED ; ---, 04, 0x010, Reserved + DCD _RESERVED ; ---, 05, 0x014, Reserved + DCD _RESERVED ; ---, 06, 0x018, Reserved + DCD _RESERVED ; ---, 07, 0x01C, Reserved + DCD _HT32FWID ; ---, 08, 0x020, Reserved + DCD _RESERVED ; ---, 09, 0x024, Reserved + DCD _RESERVED ; ---, 10, 0x028, Reserved + DCD SVC_Handler ; -05, 11, 0x02C, SVC Handler + DCD _RESERVED ; ---, 12, 0x030, Reserved + DCD _RESERVED ; ---, 13, 0x034, Reserved + DCD PendSV_Handler ; -02, 14, 0x038, PendSV Handler + DCD SysTick_Handler ; -01, 15, 0x03C, SysTick Handler + + ; External Interrupt Handler + DCD LVD_BOD_IRQHandler ; 00, 16, 0x040, + DCD RTC_IRQHandler ; 01, 17, 0x044, + DCD FLASH_IRQHandler ; 02, 18, 0x048, + DCD EVWUP_IRQHandler ; 03, 19, 0x04C, + DCD EXTI0_1_IRQHandler ; 04, 20, 0x050, + DCD EXTI2_3_IRQHandler ; 05, 21, 0x054, + DCD EXTI4_15_IRQHandler ; 06, 22, 0x058, + DCD DAC0_1_IRQHandler ; 07, 23, 0x05C, + DCD ADC_IRQHandler ; 08, 24, 0x060, + DCD I2C2_IRQHandler ; 09, 25, 0x064, + DCD _RESERVED ; 10, 26, 0x068, + DCD _RESERVED ; 11, 27, 0x06C, + DCD _RESERVED ; 12, 28, 0x070, + DCD SCTM0_IRQHandler ; 13, 29, 0x074, + DCD SCTM1_IRQHandler ; 14, 30, 0x078, + DCD PWM0_IRQHandler ; 15, 31, 0x07C, + DCD _RESERVED ; 16, 32, 0x080, + DCD BFTM0_IRQHandler ; 17, 33, 0x084, + DCD BFTM1_IRQHandler ; 18, 34, 0x088, + DCD I2C0_IRQHandler ; 19, 35, 0x08C, + DCD I2C1_IRQHandler ; 20, 36, 0x090, + DCD SPI0_IRQHandler ; 21, 37, 0x094, + DCD _RESERVED ; 22, 38, 0x098, + DCD USART0_IRQHandler ; 23, 39, 0x09C, + DCD _RESERVED ; 24, 40, 0x0A0, + DCD UART0_IRQHandler ; 25, 41, 0x0A4, + DCD _RESERVED ; 26, 42, 0x0A8, + DCD _RESERVED ; 27, 43, 0x0AC, + DCD _RESERVED ; 28, 44, 0x0B0, + DCD _RESERVED ; 29, 45, 0x0B4, + DCD PDMA_CH0_1_IRQHandler ; 30, 46, 0x0B8, + DCD PDMA_CH2_5_IRQHandler ; 31, 47, 0x0BC, + +; Reset handler routine +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception Handlers +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP + +HardFault_Handler PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP + +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP + +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP + +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + EXPORT LVD_BOD_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT EVWUP_IRQHandler [WEAK] + EXPORT EXTI0_1_IRQHandler [WEAK] + EXPORT EXTI2_3_IRQHandler [WEAK] + EXPORT EXTI4_15_IRQHandler [WEAK] + EXPORT DAC0_1_IRQHandler [WEAK] + EXPORT ADC_IRQHandler [WEAK] + EXPORT I2C2_IRQHandler [WEAK] + EXPORT SCTM0_IRQHandler [WEAK] + EXPORT SCTM1_IRQHandler [WEAK] + EXPORT PWM0_IRQHandler [WEAK] + EXPORT BFTM0_IRQHandler [WEAK] + EXPORT BFTM1_IRQHandler [WEAK] + EXPORT I2C0_IRQHandler [WEAK] + EXPORT I2C1_IRQHandler [WEAK] + EXPORT SPI0_IRQHandler [WEAK] + EXPORT USART0_IRQHandler [WEAK] + EXPORT UART0_IRQHandler [WEAK] + EXPORT PDMA_CH0_1_IRQHandler [WEAK] + EXPORT PDMA_CH2_5_IRQHandler [WEAK] + +LVD_BOD_IRQHandler +RTC_IRQHandler +FLASH_IRQHandler +EVWUP_IRQHandler +EXTI0_1_IRQHandler +EXTI2_3_IRQHandler +EXTI4_15_IRQHandler +DAC0_1_IRQHandler +ADC_IRQHandler +I2C2_IRQHandler +SCTM0_IRQHandler +SCTM1_IRQHandler +PWM0_IRQHandler +BFTM0_IRQHandler +BFTM1_IRQHandler +I2C0_IRQHandler +I2C1_IRQHandler +SPI0_IRQHandler +USART0_IRQHandler +UART0_IRQHandler +PDMA_CH0_1_IRQHandler +PDMA_CH2_5_IRQHandler + B . + ENDP + + ALIGN + +;******************************************************************************* +; User Stack and Heap initialization +;******************************************************************************* + IF :DEF:__MICROLIB + + EXPORT __HT_check_heap + EXPORT __HT_check_sp + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, = (Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + + ENDIF + + END diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f61030.s b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f61030.s new file mode 100644 index 0000000000..45853e20f1 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f61030.s @@ -0,0 +1,235 @@ +;/*---------------------------------------------------------------------------------------------------------*/ +;/* Holtek Semiconductor Inc. */ +;/* */ +;/* Copyright (C) Holtek Semiconductor Inc. */ +;/* All rights reserved. */ +;/* */ +;/*----------------------------------------------------------------------------------------------------------- +; File Name : startup_ht32f5xxxx_13.s +; Version : $Rev:: 7119 $ +; Date : $Date:: 2023-08-15 #$ +; Description : Startup code. +;-----------------------------------------------------------------------------------------------------------*/ + +; Supported Device +; ======================================== +; HT32F50020, HT32F50030 +; HT32F61630 +; HT32F61030 + +;/* <<< Use Configuration Wizard in Context Menu >>> */ + +;// HT32 Device +;// Select HT32 Device for the assembly setting. +;// Notice that the project's Asm Define has the higher priority. +;// <0=> By Project Asm Define +;// <25=> HT32F50020/30 +;// <25=> HT32F61630 +;// <25=> HT32F61030 +USE_HT32_CHIP_SET EQU 25 ; Notice that the project's Asm Define has the higher priority. + +_HT32FWID EQU 0xFFFFFFFF +;_HT32FWID EQU 0x00050020 +;_HT32FWID EQU 0x00050030 +;_HT32FWID EQU 0x00061630 +;_HT32FWID EQU 0x00061030 + +HT32F50020_30 EQU 25 +HT32F61630 EQU 25 +HT32F61030 EQU 25 + + IF USE_HT32_CHIP_SET=0 + ; Use project's Asm Define setting (default) + ELSE + IF :DEF:USE_HT32_CHIP + ; Use project's Asm Define setting (higher priority than the "USE_HT32_CHIP_SET") + ELSE + ; Use "USE_HT32_CHIP_SET" in the "startup_ht32xxxxx_xx.s" file +USE_HT32_CHIP EQU USE_HT32_CHIP_SET + ENDIF + ENDIF + +; Amount of memory (in bytes) allocated for Stack and Heap +; Tailor those values to your application needs +;// Stack Size (in Bytes, must 8 byte aligned) <0-2048:8> +Stack_Size EQU 512 + + AREA STACK, NOINIT, READWRITE, ALIGN = 3 +__HT_check_sp +Stack_Mem SPACE Stack_Size +__initial_sp + +;// Heap Size (in Bytes) <0-2048:8> +Heap_Size EQU 0 + + AREA HEAP, NOINIT, READWRITE, ALIGN = 3 +__HT_check_heap +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + PRESERVE8 + THUMB + +;******************************************************************************* +; Fill-up the Vector Table entries with the exceptions ISR address +;******************************************************************************* + AREA RESET, CODE, READONLY + EXPORT __Vectors +_RESERVED EQU 0xFFFFFFFF +__Vectors + DCD __initial_sp ; ---, 00, 0x000, Top address of Stack + DCD Reset_Handler ; ---, 01, 0x004, Reset Handler + DCD NMI_Handler ; -14, 02, 0x008, NMI Handler + DCD HardFault_Handler ; -13, 03, 0x00C, Hard Fault Handler + DCD _RESERVED ; ---, 04, 0x010, Reserved + DCD _RESERVED ; ---, 05, 0x014, Reserved + DCD _RESERVED ; ---, 06, 0x018, Reserved + DCD _RESERVED ; ---, 07, 0x01C, Reserved + DCD _HT32FWID ; ---, 08, 0x020, Reserved + DCD _RESERVED ; ---, 09, 0x024, Reserved + DCD _RESERVED ; ---, 10, 0x028, Reserved + DCD SVC_Handler ; -05, 11, 0x02C, SVC Handler + DCD _RESERVED ; ---, 12, 0x030, Reserved + DCD _RESERVED ; ---, 13, 0x034, Reserved + DCD PendSV_Handler ; -02, 14, 0x038, PendSV Handler + DCD SysTick_Handler ; -01, 15, 0x03C, SysTick Handler + + ; External Interrupt Handler + DCD LVD_BOD_IRQHandler ; 00, 16, 0x040, + DCD RTC_IRQHandler ; 01, 17, 0x044, + DCD FLASH_IRQHandler ; 02, 18, 0x048, + DCD EVWUP_IRQHandler ; 03, 19, 0x04C, + DCD EXTI0_1_IRQHandler ; 04, 20, 0x050, + DCD EXTI2_3_IRQHandler ; 05, 21, 0x054, + DCD EXTI4_7_IRQHandler ; 06, 22, 0x058, + DCD _RESERVED ; 07, 23, 0x05C, + DCD ADC_IRQHandler ; 08, 24, 0x060, + DCD _RESERVED ; 09, 25, 0x064, + DCD _RESERVED ; 10, 26, 0x068, + DCD _RESERVED ; 11, 27, 0x06C, + DCD _RESERVED ; 12, 28, 0x070, + DCD SCTM0_IRQHandler ; 13, 29, 0x074, + DCD SCTM1_IRQHandler ; 14, 30, 0x078, + DCD SCTM2_IRQHandler ; 15, 31, 0x07C, + DCD _RESERVED ; 16, 32, 0x080, + DCD BFTM0_IRQHandler ; 17, 33, 0x084, + DCD _RESERVED ; 18, 34, 0x088, + DCD I2C0_IRQHandler ; 19, 35, 0x08C, + DCD _RESERVED ; 20, 36, 0x090, + DCD SPI0_IRQHandler ; 21, 37, 0x094, + DCD _RESERVED ; 22, 38, 0x098, + DCD _RESERVED ; 23, 39, 0x09C, + DCD _RESERVED ; 24, 40, 0x0A0, + DCD UART0_IRQHandler ; 25, 41, 0x0A4, + DCD UART1_IRQHandler ; 26, 42, 0x0A8, + DCD _RESERVED ; 27, 43, 0x0AC, + DCD _RESERVED ; 28, 44, 0x0B0, + DCD LEDC_IRQHandler ; 29, 45, 0x0B4, + +; Reset handler routine +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception Handlers +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP + +HardFault_Handler PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP + +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP + +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP + +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + EXPORT LVD_BOD_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT EVWUP_IRQHandler [WEAK] + EXPORT EXTI0_1_IRQHandler [WEAK] + EXPORT EXTI2_3_IRQHandler [WEAK] + EXPORT EXTI4_7_IRQHandler [WEAK] + EXPORT ADC_IRQHandler [WEAK] + EXPORT SCTM0_IRQHandler [WEAK] + EXPORT SCTM1_IRQHandler [WEAK] + EXPORT SCTM2_IRQHandler [WEAK] + EXPORT BFTM0_IRQHandler [WEAK] + EXPORT I2C0_IRQHandler [WEAK] + EXPORT SPI0_IRQHandler [WEAK] + EXPORT UART0_IRQHandler [WEAK] + EXPORT UART1_IRQHandler [WEAK] + EXPORT LEDC_IRQHandler [WEAK] + +LVD_BOD_IRQHandler +RTC_IRQHandler +FLASH_IRQHandler +EVWUP_IRQHandler +EXTI0_1_IRQHandler +EXTI2_3_IRQHandler +EXTI4_7_IRQHandler +ADC_IRQHandler +SCTM0_IRQHandler +SCTM1_IRQHandler +SCTM2_IRQHandler +BFTM0_IRQHandler +I2C0_IRQHandler +SPI0_IRQHandler +UART0_IRQHandler +UART1_IRQHandler +LEDC_IRQHandler + B . + ENDP + + ALIGN + +;******************************************************************************* +; User Stack and Heap initialization +;******************************************************************************* + IF :DEF:__MICROLIB + + EXPORT __HT_check_heap + EXPORT __HT_check_sp + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, = (Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + + ENDIF + + END diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f61041.s b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f61041.s new file mode 100644 index 0000000000..8e68952909 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f61041.s @@ -0,0 +1,327 @@ +;/*---------------------------------------------------------------------------------------------------------*/ +;/* Holtek Semiconductor Inc. */ +;/* */ +;/* Copyright (C) Holtek Semiconductor Inc. */ +;/* All rights reserved. */ +;/* */ +;/*----------------------------------------------------------------------------------------------------------- +; File Name : startup_ht32f5xxxx_02.s +; Version : $Rev:: 7119 $ +; Date : $Date:: 2023-08-15 #$ +; Description : Startup code. +;-----------------------------------------------------------------------------------------------------------*/ + +; Supported Device +; ======================================== +; HT32F50220, HT32F50230 +; HT32F50231, HT32F50241 +; HT50F32002 +; HT32F59041 +; HF5032 +; HT32F61641 +; HT32F59046 +; HT32F61041 + +;/* <<< Use Configuration Wizard in Context Menu >>> */ + +;// HT32 Device +;// Select HT32 Device for the assembly setting. +;// Notice that the project's Asm Define has the higher priority. +;// <0=> By Project Asm Define +;// <7=> HT32F50220/30 +;// <8=> HT32F50231/41 +;// <7=> HT50F32002 +;// <8=> HT32F59041 +;// <7=> HF5032 +;// <8=> HT32F61641 +;// <8=> HT32F59046 +;// <8=> HT32F61041 +USE_HT32_CHIP_SET EQU 8 ; Notice that the project's Asm Define has the higher priority. + +_HT32FWID EQU 0xFFFFFFFF +;_HT32FWID EQU 0x00050220 +;_HT32FWID EQU 0x00050230 +;_HT32FWID EQU 0x00050231 +;_HT32FWID EQU 0x00050241 +;_HT32FWID EQU 0x00032002 +;_HT32FWID EQU 0x00059041 +;_HT32FWID EQU 0x000F5032 +;_HT32FWID EQU 0x00061641 +;_HT32FWID EQU 0x00059046 +;_HT32FWID EQU 0x00061041 + +HT32F50220_30 EQU 7 +HT32F50231_41 EQU 8 +HT50F32002 EQU 7 +HT32F59041 EQU 8 +HF5032 EQU 7 +HT32F61641 EQU 8 +HT32F59046 EQU 8 +HT32F61041 EQU 8 + + IF USE_HT32_CHIP_SET=0 + ; Use project's Asm Define setting (default) + ELSE + IF :DEF:USE_HT32_CHIP + ; Use project's Asm Define setting (higher priority than the "USE_HT32_CHIP_SET") + ELSE + ; Use "USE_HT32_CHIP_SET" in the "startup_ht32xxxxx_xx.s" file +USE_HT32_CHIP EQU USE_HT32_CHIP_SET + ENDIF + ENDIF + +; Amount of memory (in bytes) allocated for Stack and Heap +; Tailor those values to your application needs +;// Stack Size (in Bytes, must 8 byte aligned) <0-4096:8> +Stack_Size EQU 512 + + AREA STACK, NOINIT, READWRITE, ALIGN = 3 +__HT_check_sp +Stack_Mem SPACE Stack_Size +__initial_sp + +;// Heap Size (in Bytes) <0-4096:8> +Heap_Size EQU 0 + + AREA HEAP, NOINIT, READWRITE, ALIGN = 3 +__HT_check_heap +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + PRESERVE8 + THUMB + +;******************************************************************************* +; Fill-up the Vector Table entries with the exceptions ISR address +;******************************************************************************* + AREA RESET, CODE, READONLY + EXPORT __Vectors +_RESERVED EQU 0xFFFFFFFF +__Vectors + DCD __initial_sp ; ---, 00, 0x000, Top address of Stack + DCD Reset_Handler ; ---, 01, 0x004, Reset Handler + DCD NMI_Handler ; -14, 02, 0x008, NMI Handler + DCD HardFault_Handler ; -13, 03, 0x00C, Hard Fault Handler + DCD _RESERVED ; ---, 04, 0x010, Reserved + DCD _RESERVED ; ---, 05, 0x014, Reserved + DCD _RESERVED ; ---, 06, 0x018, Reserved + DCD _RESERVED ; ---, 07, 0x01C, Reserved + DCD _HT32FWID ; ---, 08, 0x020, Reserved + DCD _RESERVED ; ---, 09, 0x024, Reserved + DCD _RESERVED ; ---, 10, 0x028, Reserved + DCD SVC_Handler ; -05, 11, 0x02C, SVC Handler + DCD _RESERVED ; ---, 12, 0x030, Reserved + DCD _RESERVED ; ---, 13, 0x034, Reserved + DCD PendSV_Handler ; -02, 14, 0x038, PendSV Handler + DCD SysTick_Handler ; -01, 15, 0x03C, SysTick Handler + + ; External Interrupt Handler + DCD LVD_BOD_IRQHandler ; 00, 16, 0x040, + DCD RTC_IRQHandler ; 01, 17, 0x044, + DCD FLASH_IRQHandler ; 02, 18, 0x048, + DCD EVWUP_IRQHandler ; 03, 19, 0x04C, + DCD EXTI0_1_IRQHandler ; 04, 20, 0x050, + DCD EXTI2_3_IRQHandler ; 05, 21, 0x054, + DCD EXTI4_15_IRQHandler ; 06, 22, 0x058, + DCD _RESERVED ; 07, 23, 0x05C, + DCD ADC_IRQHandler ; 08, 24, 0x060, + DCD _RESERVED ; 09, 25, 0x064, + IF (USE_HT32_CHIP=HT32F50220_30) + DCD _RESERVED ; 10, 26, 0x068, + ELSE + DCD MCTM0_IRQHandler ; 10, 26, 0x068, + ENDIF + DCD _RESERVED ; 11, 27, 0x06C, + DCD GPTM0_IRQHandler ; 12, 28, 0x070, + DCD _RESERVED ; 13, 29, 0x074, + DCD _RESERVED ; 14, 30, 0x078, + DCD PWM0_IRQHandler ; 15, 31, 0x07C, + DCD PWM1_IRQHandler ; 16, 32, 0x080, + DCD BFTM0_IRQHandler ; 17, 33, 0x084, + IF (USE_HT32_CHIP=HT32F50220_30) + DCD _RESERVED ; 18, 34, 0x088, + ELSE + DCD BFTM1_IRQHandler ; 18, 34, 0x088, + ENDIF + DCD I2C0_IRQHandler ; 19, 35, 0x08C, + IF (USE_HT32_CHIP=HT32F50220_30) + DCD _RESERVED ; 20, 36, 0x090, + ELSE + DCD I2C1_IRQHandler ; 20, 36, 0x090, + ENDIF + DCD SPI0_IRQHandler ; 21, 37, 0x094, + DCD SPI1_IRQHandler ; 22, 38, 0x098, + IF (USE_HT32_CHIP=HT32F50220_30) + DCD _RESERVED ; 23, 39, 0x09C, + ELSE + DCD USART0_IRQHandler ; 23, 39, 0x09C, + ENDIF + DCD _RESERVED ; 24, 40, 0x0A0, + DCD UART0_IRQHandler ; 25, 41, 0x0A4, + DCD UART1_IRQHandler ; 26, 42, 0x0A8, + +; Reset handler routine +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + LDR R0, =BootProcess + BLX R0 + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +BootProcess PROC + LDR R0, =0x40080300 + LDR R1,[R0, #0x10] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x14] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x18] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x1C] + CMP R1, #0 + BEQ BP2 +BP1 LDR R0, =0x40080180 + LDR R1,[R0, #0xC] + LSLS R1, R1, #4 + LSRS R1, R1, #20 + CMP R1, #0 + BEQ BP3 + CMP R1, #5 + BEQ BP3 + CMP R1, #6 + BEQ BP3 +BP2 DSB + LDR R0, =0x20000000 + LDR R1, =0x05fa0004 + STR R1, [R0] + LDR R1, =0xe000ed00 + LDR R0, =0x05fa0004 + STR R0, [R1, #0xC] + DSB + B . +BP3 LDR R0, =0x20000000 + LDR R1, [R0] + LDR R0, =0x05fa0004 + CMP R0, R1 + BEQ BP4 + BX LR +BP4 LDR R0, =0x40088100 + LDR R1, =0x00000001 + STR R1, [R0] + LDR R0, =0x20000000 + LDR R1, =0x0 + STR R1, [R0] + BX LR + ENDP + +; Dummy Exception Handlers +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP + +HardFault_Handler PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP + +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP + +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP + +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + EXPORT LVD_BOD_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT EVWUP_IRQHandler [WEAK] + EXPORT EXTI0_1_IRQHandler [WEAK] + EXPORT EXTI2_3_IRQHandler [WEAK] + EXPORT EXTI4_15_IRQHandler [WEAK] + EXPORT ADC_IRQHandler [WEAK] + EXPORT MCTM0_IRQHandler [WEAK] + EXPORT GPTM0_IRQHandler [WEAK] + EXPORT PWM0_IRQHandler [WEAK] + EXPORT PWM1_IRQHandler [WEAK] + EXPORT BFTM0_IRQHandler [WEAK] + EXPORT BFTM1_IRQHandler [WEAK] + EXPORT I2C0_IRQHandler [WEAK] + EXPORT I2C1_IRQHandler [WEAK] + EXPORT SPI0_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT USART0_IRQHandler [WEAK] + EXPORT UART0_IRQHandler [WEAK] + EXPORT UART1_IRQHandler [WEAK] + +LVD_BOD_IRQHandler +RTC_IRQHandler +FLASH_IRQHandler +EVWUP_IRQHandler +EXTI0_1_IRQHandler +EXTI2_3_IRQHandler +EXTI4_15_IRQHandler +ADC_IRQHandler +MCTM0_IRQHandler +GPTM0_IRQHandler +PWM0_IRQHandler +PWM1_IRQHandler +BFTM0_IRQHandler +BFTM1_IRQHandler +I2C0_IRQHandler +I2C1_IRQHandler +SPI0_IRQHandler +SPI1_IRQHandler +USART0_IRQHandler +UART0_IRQHandler +UART1_IRQHandler + B . + ENDP + + ALIGN + +;******************************************************************************* +; User Stack and Heap initialization +;******************************************************************************* + IF :DEF:__MICROLIB + + EXPORT __HT_check_heap + EXPORT __HT_check_sp + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, = (Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + + ENDIF + + END diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f61141.s b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f61141.s new file mode 100644 index 0000000000..e01651cc14 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f61141.s @@ -0,0 +1,278 @@ +;/*---------------------------------------------------------------------------------------------------------*/ +;/* Holtek Semiconductor Inc. */ +;/* */ +;/* Copyright (C) Holtek Semiconductor Inc. */ +;/* All rights reserved. */ +;/* */ +;/*----------------------------------------------------------------------------------------------------------- +; File Name : startup_ht32f5xxxx_12.s +; Version : $Rev:: 5740 $ +; Date : $Date:: 2022-02-17 #$ +; Description : Startup code. +;-----------------------------------------------------------------------------------------------------------*/ + +; Supported Device +; ======================================== +; HT32F61141 + +;/* <<< Use Configuration Wizard in Context Menu >>> */ + +;// HT32 Device +;// Select HT32 Device for the assembly setting. +;// Notice that the project's Asm Define has the higher priority. +;// <0=> By Project Asm Define +;// <23=> HT32F61141 +USE_HT32_CHIP_SET EQU 23 ; Notice that the project's Asm Define has the higher priority. + +_HT32FWID EQU 0xFFFFFFFF +;_HT32FWID EQU 0x00061141 + +HT32F61141 EQU 23 + + IF USE_HT32_CHIP_SET=0 + ; Use project's Asm Define setting (default) + ELSE + IF :DEF:USE_HT32_CHIP + ; Use project's Asm Define setting (higher priority than the "USE_HT32_CHIP_SET") + ELSE + ; Use "USE_HT32_CHIP_SET" in the "startup_ht32xxxxx_xx.s" file +USE_HT32_CHIP EQU USE_HT32_CHIP_SET + ENDIF + ENDIF + +; Amount of memory (in bytes) allocated for Stack and Heap +; Tailor those values to your application needs +;// Stack Size (in Bytes, must 8 byte aligned) <0-16384:8> +Stack_Size EQU 512 + + AREA STACK, NOINIT, READWRITE, ALIGN = 3 +__HT_check_sp +Stack_Mem SPACE Stack_Size +__initial_sp + +;// Heap Size (in Bytes) <0-16384:8> +Heap_Size EQU 0 + + AREA HEAP, NOINIT, READWRITE, ALIGN = 3 +__HT_check_heap +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + PRESERVE8 + THUMB + +;******************************************************************************* +; Fill-up the Vector Table entries with the exceptions ISR address +;******************************************************************************* + AREA RESET, CODE, READONLY + EXPORT __Vectors +_RESERVED EQU 0xFFFFFFFF +__Vectors + DCD __initial_sp ; ---, 00, 0x000, Top address of Stack + DCD Reset_Handler ; ---, 01, 0x004, Reset Handler + DCD NMI_Handler ; -14, 02, 0x008, NMI Handler + DCD HardFault_Handler ; -13, 03, 0x00C, Hard Fault Handler + DCD _RESERVED ; ---, 04, 0x010, Reserved + DCD _RESERVED ; ---, 05, 0x014, Reserved + DCD _RESERVED ; ---, 06, 0x018, Reserved + DCD _RESERVED ; ---, 07, 0x01C, Reserved + DCD _HT32FWID ; ---, 08, 0x020, Reserved + DCD _RESERVED ; ---, 09, 0x024, Reserved + DCD _RESERVED ; ---, 10, 0x028, Reserved + DCD SVC_Handler ; -05, 11, 0x02C, SVC Handler + DCD _RESERVED ; ---, 12, 0x030, Reserved + DCD _RESERVED ; ---, 13, 0x034, Reserved + DCD PendSV_Handler ; -02, 14, 0x038, PendSV Handler + DCD SysTick_Handler ; -01, 15, 0x03C, SysTick Handler + + ; External Interrupt Handler + DCD LVD_BOD_IRQHandler ; 00, 16, 0x040, + DCD RTC_IRQHandler ; 01, 17, 0x044, + DCD FLASH_IRQHandler ; 02, 18, 0x048, + DCD EVWUP_IRQHandler ; 03, 19, 0x04C, + DCD EXTI0_1_IRQHandler ; 04, 20, 0x050, + DCD EXTI2_3_IRQHandler ; 05, 21, 0x054, + DCD EXTI4_15_IRQHandler ; 06, 22, 0x058, + DCD _RESERVED ; 07, 23, 0x05C, + DCD _RESERVED ; 08, 24, 0x060, + DCD _RESERVED ; 09, 25, 0x064, + DCD _RESERVED ; 10, 26, 0x068, + DCD _RESERVED ; 11, 27, 0x06C, + DCD GPTM0_IRQHandler ; 12, 28, 0x070, + DCD SCTM0_IRQHandler ; 13, 29, 0x074, + DCD SCTM1_IRQHandler ; 14, 30, 0x078, + DCD _RESERVED ; 15, 31, 0x07C, + DCD _RESERVED ; 16, 32, 0x080, + DCD BFTM0_IRQHandler ; 17, 33, 0x084, + DCD BFTM1_IRQHandler ; 18, 34, 0x088, + DCD I2C0_IRQHandler ; 19, 35, 0x08C, + DCD _RESERVED ; 20, 36, 0x090, + DCD SPI0_IRQHandler ; 21, 37, 0x094, + DCD _RESERVED ; 22, 38, 0x098, + DCD _RESERVED ; 23, 39, 0x09C, + DCD _RESERVED ; 24, 40, 0x0A0, + DCD UART0_IRQHandler ; 25, 41, 0x0A4, + DCD UART1_IRQHandler ; 26, 42, 0x0A8, + DCD SCI_IRQHandler ; 27, 43, 0x0AC, + DCD _RESERVED ; 28, 44, 0x0B0, + DCD USB_IRQHandler ; 29, 45, 0x0B4, + +; Reset handler routine +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + LDR R0, =BootProcess + BLX R0 + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +BootProcess PROC + LDR R0, =0x40080300 + LDR R1,[R0, #0x10] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x14] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x18] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x1C] + CMP R1, #0 + BEQ BP2 +BP1 LDR R0, =0x40080180 + LDR R1,[R0, #0xC] + LSLS R1, R1, #4 + LSRS R1, R1, #20 + CMP R1, #0 + BEQ BP3 + CMP R1, #5 + BEQ BP3 + CMP R1, #6 + BEQ BP3 +BP2 DSB + LDR R0, =0x20000000 + LDR R1, =0x05fa0004 + STR R1, [R0] + LDR R1, =0xe000ed00 + LDR R0, =0x05fa0004 + STR R0, [R1, #0xC] + DSB + B . +BP3 LDR R0, =0x20000000 + LDR R1, [R0] + LDR R0, =0x05fa0004 + CMP R0, R1 + BEQ BP4 + BX LR +BP4 LDR R0, =0x40088100 + LDR R1, =0x00000001 + STR R1, [R0] + LDR R0, =0x20000000 + LDR R1, =0x0 + STR R1, [R0] + BX LR + ENDP + +; Dummy Exception Handlers +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP + +HardFault_Handler PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP + +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP + +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP + +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + EXPORT LVD_BOD_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT EVWUP_IRQHandler [WEAK] + EXPORT EXTI0_1_IRQHandler [WEAK] + EXPORT EXTI2_3_IRQHandler [WEAK] + EXPORT EXTI4_15_IRQHandler [WEAK] + EXPORT GPTM0_IRQHandler [WEAK] + EXPORT SCTM0_IRQHandler [WEAK] + EXPORT SCTM1_IRQHandler [WEAK] + EXPORT BFTM0_IRQHandler [WEAK] + EXPORT BFTM1_IRQHandler [WEAK] + EXPORT I2C0_IRQHandler [WEAK] + EXPORT SPI0_IRQHandler [WEAK] + EXPORT UART0_IRQHandler [WEAK] + EXPORT UART1_IRQHandler [WEAK] + EXPORT SCI_IRQHandler [WEAK] + EXPORT USB_IRQHandler [WEAK] + +LVD_BOD_IRQHandler +RTC_IRQHandler +FLASH_IRQHandler +EVWUP_IRQHandler +EXTI0_1_IRQHandler +EXTI2_3_IRQHandler +EXTI4_15_IRQHandler +GPTM0_IRQHandler +SCTM0_IRQHandler +SCTM1_IRQHandler +BFTM0_IRQHandler +BFTM1_IRQHandler +I2C0_IRQHandler +SPI0_IRQHandler +UART0_IRQHandler +UART1_IRQHandler +SCI_IRQHandler +USB_IRQHandler + B . + ENDP + + ALIGN + +;******************************************************************************* +; User Stack and Heap initialization +;******************************************************************************* + IF :DEF:__MICROLIB + + EXPORT __HT_check_heap + EXPORT __HT_check_sp + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, = (Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + + ENDIF + + END diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f61244_45.s b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f61244_45.s new file mode 100644 index 0000000000..5477d2e255 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f61244_45.s @@ -0,0 +1,235 @@ +;/*---------------------------------------------------------------------------------------------------------*/ +;/* Holtek Semiconductor Inc. */ +;/* */ +;/* Copyright (C) Holtek Semiconductor Inc. */ +;/* All rights reserved. */ +;/* */ +;/*----------------------------------------------------------------------------------------------------------- +; File Name : startup_ht32f5xxxx_10.s +; Version : $Rev:: 5783 $ +; Date : $Date:: 2022-03-30 #$ +; Description : Startup code. +;-----------------------------------------------------------------------------------------------------------*/ + +; Supported Device +; ======================================== +; HT32F61244, HT32F61245 + +;/* <<< Use Configuration Wizard in Context Menu >>> */ + +;// HT32 Device +;// Select HT32 Device for the assembly setting. +;// Notice that the project's Asm Define has the higher priority. +;// <0=> By Project Asm Define +;// <24=> HT32F61244/45 +USE_HT32_CHIP_SET EQU 24 ; Notice that the project's Asm Define has the higher priority. + +_HT32FWID EQU 0xFFFFFFFF +;_HT32FWID EQU 0x00061244 +;_HT32FWID EQU 0x00061245 + +HT32F61244_45 EQU 24 + + IF USE_HT32_CHIP_SET=0 + ; Use project's Asm Define setting (default) + ELSE + IF :DEF:USE_HT32_CHIP + ; Use project's Asm Define setting (higher priority than the "USE_HT32_CHIP_SET") + ELSE + ; Use "USE_HT32_CHIP_SET" in the "startup_ht32xxxxx_xx.s" file +USE_HT32_CHIP EQU USE_HT32_CHIP_SET + ENDIF + ENDIF + +; Amount of memory (in bytes) allocated for Stack and Heap +; Tailor those values to your application needs +;// Stack Size (in Bytes, must 8 byte aligned) <0-8192:8> +Stack_Size EQU 512 + + AREA STACK, NOINIT, READWRITE, ALIGN = 3 +__HT_check_sp +Stack_Mem SPACE Stack_Size +__initial_sp + +;// Heap Size (in Bytes) <0-8192:8> +Heap_Size EQU 0 + + AREA HEAP, NOINIT, READWRITE, ALIGN = 3 +__HT_check_heap +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + PRESERVE8 + THUMB + +;******************************************************************************* +; Fill-up the Vector Table entries with the exceptions ISR address +;******************************************************************************* + AREA RESET, CODE, READONLY + EXPORT __Vectors +_RESERVED EQU 0xFFFFFFFF +__Vectors + DCD __initial_sp ; ---, 00, 0x000, Top address of Stack + DCD Reset_Handler ; ---, 01, 0x004, Reset Handler + DCD NMI_Handler ; -14, 02, 0x008, NMI Handler + DCD HardFault_Handler ; -13, 03, 0x00C, Hard Fault Handler + DCD _RESERVED ; ---, 04, 0x010, Reserved + DCD _RESERVED ; ---, 05, 0x014, Reserved + DCD _RESERVED ; ---, 06, 0x018, Reserved + DCD _RESERVED ; ---, 07, 0x01C, Reserved + DCD _HT32FWID ; ---, 08, 0x020, Reserved + DCD _RESERVED ; ---, 09, 0x024, Reserved + DCD _RESERVED ; ---, 10, 0x028, Reserved + DCD SVC_Handler ; -05, 11, 0x02C, SVC Handler + DCD _RESERVED ; ---, 12, 0x030, Reserved + DCD _RESERVED ; ---, 13, 0x034, Reserved + DCD PendSV_Handler ; -02, 14, 0x038, PendSV Handler + DCD SysTick_Handler ; -01, 15, 0x03C, SysTick Handler + + ; External Interrupt Handler + DCD LVD_BOD_IRQHandler ; 00, 16, 0x040, + DCD RTC_IRQHandler ; 01, 17, 0x044, + DCD FLASH_IRQHandler ; 02, 18, 0x048, + DCD EVWUP_IRQHandler ; 03, 19, 0x04C, + DCD EXTI0_1_IRQHandler ; 04, 20, 0x050, + DCD EXTI2_3_IRQHandler ; 05, 21, 0x054, + DCD EXTI4_15_IRQHandler ; 06, 22, 0x058, + DCD _RESERVED ; 07, 23, 0x05C, + DCD ADC_IRQHandler ; 08, 24, 0x060, + DCD _RESERVED ; 09, 25, 0x064, + DCD _RESERVED ; 10, 26, 0x068, + DCD _RESERVED ; 11, 27, 0x06C, + DCD GPTM0_IRQHandler ; 12, 28, 0x070, + DCD SCTM0_IRQHandler ; 13, 29, 0x074, + DCD SCTM1_IRQHandler ; 14, 30, 0x078, + DCD _RESERVED ; 15, 31, 0x07C, + DCD _RESERVED ; 16, 32, 0x080, + DCD BFTM0_IRQHandler ; 17, 33, 0x084, + DCD BFTM1_IRQHandler ; 18, 34, 0x088, + DCD I2C0_IRQHandler ; 19, 35, 0x08C, + DCD _RESERVED ; 20, 36, 0x090, + DCD SPI0_IRQHandler ; 21, 37, 0x094, + DCD QSPI_IRQHandler ; 22, 38, 0x098, + DCD _RESERVED ; 23, 39, 0x09C, + DCD _RESERVED ; 24, 40, 0x0A0, + DCD UART0_IRQHandler ; 25, 41, 0x0A4, + DCD _RESERVED ; 26, 42, 0x0A8, + DCD MIDI_IRQHandler ; 27, 43, 0x0AC, + DCD _RESERVED ; 28, 44, 0x0B0, + DCD _RESERVED ; 29, 45, 0x0B4, + DCD PDMA_CH0_1_IRQHandler ; 30, 46, 0x0B8, + DCD PDMA_CH2_5_IRQHandler ; 31, 47, 0x0BC, + +; Reset handler routine +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception Handlers +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP + +HardFault_Handler PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP + +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP + +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP + +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + EXPORT LVD_BOD_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT EVWUP_IRQHandler [WEAK] + EXPORT EXTI0_1_IRQHandler [WEAK] + EXPORT EXTI2_3_IRQHandler [WEAK] + EXPORT EXTI4_15_IRQHandler [WEAK] + EXPORT ADC_IRQHandler [WEAK] + EXPORT GPTM0_IRQHandler [WEAK] + EXPORT SCTM0_IRQHandler [WEAK] + EXPORT SCTM1_IRQHandler [WEAK] + EXPORT BFTM0_IRQHandler [WEAK] + EXPORT BFTM1_IRQHandler [WEAK] + EXPORT I2C0_IRQHandler [WEAK] + EXPORT SPI0_IRQHandler [WEAK] + EXPORT QSPI_IRQHandler [WEAK] + EXPORT UART0_IRQHandler [WEAK] + EXPORT MIDI_IRQHandler [WEAK] + EXPORT PDMA_CH0_1_IRQHandler [WEAK] + EXPORT PDMA_CH2_5_IRQHandler [WEAK] + +LVD_BOD_IRQHandler +RTC_IRQHandler +FLASH_IRQHandler +EVWUP_IRQHandler +EXTI0_1_IRQHandler +EXTI2_3_IRQHandler +EXTI4_15_IRQHandler +ADC_IRQHandler +GPTM0_IRQHandler +SCTM0_IRQHandler +SCTM1_IRQHandler +BFTM0_IRQHandler +BFTM1_IRQHandler +I2C0_IRQHandler +SPI0_IRQHandler +QSPI_IRQHandler +UART0_IRQHandler +MIDI_IRQHandler +PDMA_CH0_1_IRQHandler +PDMA_CH2_5_IRQHandler + B . + ENDP + + ALIGN + +;******************************************************************************* +; User Stack and Heap initialization +;******************************************************************************* + IF :DEF:__MICROLIB + + EXPORT __HT_check_heap + EXPORT __HT_check_sp + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, = (Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + + ENDIF + + END diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f61352.s b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f61352.s new file mode 100644 index 0000000000..e0b5ba76e2 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f61352.s @@ -0,0 +1,304 @@ +;/*---------------------------------------------------------------------------------------------------------*/ +;/* Holtek Semiconductor Inc. */ +;/* */ +;/* Copyright (C) Holtek Semiconductor Inc. */ +;/* All rights reserved. */ +;/* */ +;/*----------------------------------------------------------------------------------------------------------- +; File Name : startup_ht32f5xxxx_07.s +; Version : $Rev:: 5740 $ +; Date : $Date:: 2022-02-17 #$ +; Description : Startup code. +;-----------------------------------------------------------------------------------------------------------*/ + +; Supported Device +; ======================================== +; HT32F0006 +; HT32F61352 +; HT32F61355, HT32F61356, HT32F61357 + +;/* <<< Use Configuration Wizard in Context Menu >>> */ + +;// HT32 Device +;// Select HT32 Device for the assembly setting. +;// Notice that the project's Asm Define has the higher priority. +;// <0=> By Project Asm Define +;// <10=> HT32F0006 +;// <10=> HT32F61352 +;// <17=> HT32F61355/56/57 +USE_HT32_CHIP_SET EQU 10 ; Notice that the project's Asm Define has the higher priority. + +_HT32FWID EQU 0xFFFFFFFF +;_HT32FWID EQU 0x00000006 +;_HT32FWID EQU 0x00061352 +;_HT32FWID EQU 0x00061355 +;_HT32FWID EQU 0x00061356 +;_HT32FWID EQU 0x00061357 + +HT32F0006 EQU 10 +HT32F61352 EQU 10 +HT32F61355_56_57 EQU 17 + + IF USE_HT32_CHIP_SET=0 + ; Use project's Asm Define setting (default) + ELSE + IF :DEF:USE_HT32_CHIP + ; Use project's Asm Define setting (higher priority than the "USE_HT32_CHIP_SET") + ELSE + ; Use "USE_HT32_CHIP_SET" in the "startup_ht32xxxxx_xx.s" file +USE_HT32_CHIP EQU USE_HT32_CHIP_SET + ENDIF + ENDIF + +; Amount of memory (in bytes) allocated for Stack and Heap +; Tailor those values to your application needs +;// Stack Size (in Bytes, must 8 byte aligned) <0-16384:8> +Stack_Size EQU 512 + + AREA STACK, NOINIT, READWRITE, ALIGN = 3 +__HT_check_sp +Stack_Mem SPACE Stack_Size +__initial_sp + +;// Heap Size (in Bytes) <0-16384:8> +Heap_Size EQU 0 + + AREA HEAP, NOINIT, READWRITE, ALIGN = 3 +__HT_check_heap +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + PRESERVE8 + THUMB + +;******************************************************************************* +; Fill-up the Vector Table entries with the exceptions ISR address +;******************************************************************************* + AREA RESET, CODE, READONLY + EXPORT __Vectors +_RESERVED EQU 0xFFFFFFFF +__Vectors + DCD __initial_sp ; ---, 00, 0x000, Top address of Stack + DCD Reset_Handler ; ---, 01, 0x004, Reset Handler + DCD NMI_Handler ; -14, 02, 0x008, NMI Handler + DCD HardFault_Handler ; -13, 03, 0x00C, Hard Fault Handler + DCD _RESERVED ; ---, 04, 0x010, Reserved + DCD _RESERVED ; ---, 05, 0x014, Reserved + DCD _RESERVED ; ---, 06, 0x018, Reserved + DCD _RESERVED ; ---, 07, 0x01C, Reserved + DCD _HT32FWID ; ---, 08, 0x020, Reserved + DCD _RESERVED ; ---, 09, 0x024, Reserved + DCD _RESERVED ; ---, 10, 0x028, Reserved + DCD SVC_Handler ; -05, 11, 0x02C, SVC Handler + DCD _RESERVED ; ---, 12, 0x030, Reserved + DCD _RESERVED ; ---, 13, 0x034, Reserved + DCD PendSV_Handler ; -02, 14, 0x038, PendSV Handler + DCD SysTick_Handler ; -01, 15, 0x03C, SysTick Handler + + ; External Interrupt Handler + DCD LVD_BOD_IRQHandler ; 00, 16, 0x040, + DCD RTC_IRQHandler ; 01, 17, 0x044, + DCD FLASH_IRQHandler ; 02, 18, 0x048, + DCD EVWUP_IRQHandler ; 03, 19, 0x04C, + DCD EXTI0_1_IRQHandler ; 04, 20, 0x050, + DCD EXTI2_3_IRQHandler ; 05, 21, 0x054, + DCD EXTI4_15_IRQHandler ; 06, 22, 0x058, + DCD _RESERVED ; 07, 23, 0x05C, + DCD ADC_IRQHandler ; 08, 24, 0x060, + DCD _RESERVED ; 09, 25, 0x064, + DCD _RESERVED ; 10, 26, 0x068, + DCD _RESERVED ; 11, 27, 0x06C, + DCD GPTM0_IRQHandler ; 12, 28, 0x070, + DCD SCTM0_IRQHandler ; 13, 29, 0x074, + DCD SCTM1_IRQHandler ; 14, 30, 0x078, + DCD SCTM2_IRQHandler ; 15, 31, 0x07C, + DCD SCTM3_IRQHandler ; 16, 32, 0x080, + DCD BFTM0_IRQHandler ; 17, 33, 0x084, + DCD BFTM1_IRQHandler ; 18, 34, 0x088, + DCD I2C0_IRQHandler ; 19, 35, 0x08C, + DCD _RESERVED ; 20, 36, 0x090, + DCD SPI0_IRQHandler ; 21, 37, 0x094, + DCD QSPI_IRQHandler ; 22, 38, 0x098, + DCD USART0_IRQHandler ; 23, 39, 0x09C, + DCD _RESERVED ; 24, 40, 0x0A0, + DCD UART0_IRQHandler ; 25, 41, 0x0A4, + DCD _RESERVED ; 26, 42, 0x0A8, + DCD MIDI_IRQHandler ; 27, 43, 0x0AC, + DCD I2S_IRQHandler ; 28, 44, 0x0B0, + DCD USB_IRQHandler ; 29, 45, 0x0B4, + DCD PDMA_CH0_1_IRQHandler ; 30, 46, 0x0B8, + DCD PDMA_CH2_5_IRQHandler ; 31, 47, 0x0BC, + +; Reset handler routine +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + LDR R0, =BootProcess + BLX R0 + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +BootProcess PROC + LDR R0, =0x40080300 + LDR R1,[R0, #0x10] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x14] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x18] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x1C] + CMP R1, #0 + BEQ BP2 +BP1 LDR R0, =0x40080180 + LDR R1,[R0, #0xC] + LSLS R1, R1, #4 + LSRS R1, R1, #20 + CMP R1, #0 + BEQ BP3 + CMP R1, #5 + BEQ BP3 + CMP R1, #6 + BEQ BP3 +BP2 DSB + LDR R0, =0x20000000 + LDR R1, =0x05fa0004 + STR R1, [R0] + LDR R1, =0xe000ed00 + LDR R0, =0x05fa0004 + STR R0, [R1, #0xC] + DSB + B . +BP3 LDR R0, =0x20000000 + LDR R1, [R0] + LDR R0, =0x05fa0004 + CMP R0, R1 + BEQ BP4 + BX LR +BP4 LDR R0, =0x40088100 + LDR R1, =0x00000001 + STR R1, [R0] + LDR R0, =0x20000000 + LDR R1, =0x0 + STR R1, [R0] + BX LR + ENDP + +; Dummy Exception Handlers +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP + +HardFault_Handler PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP + +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP + +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP + +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + EXPORT LVD_BOD_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT EVWUP_IRQHandler [WEAK] + EXPORT EXTI0_1_IRQHandler [WEAK] + EXPORT EXTI2_3_IRQHandler [WEAK] + EXPORT EXTI4_15_IRQHandler [WEAK] + EXPORT ADC_IRQHandler [WEAK] + EXPORT GPTM0_IRQHandler [WEAK] + EXPORT SCTM0_IRQHandler [WEAK] + EXPORT SCTM1_IRQHandler [WEAK] + EXPORT SCTM2_IRQHandler [WEAK] + EXPORT SCTM3_IRQHandler [WEAK] + EXPORT BFTM0_IRQHandler [WEAK] + EXPORT BFTM1_IRQHandler [WEAK] + EXPORT I2C0_IRQHandler [WEAK] + EXPORT SPI0_IRQHandler [WEAK] + EXPORT QSPI_IRQHandler [WEAK] + EXPORT USART0_IRQHandler [WEAK] + EXPORT UART0_IRQHandler [WEAK] + EXPORT MIDI_IRQHandler [WEAK] + EXPORT I2S_IRQHandler [WEAK] + EXPORT USB_IRQHandler [WEAK] + EXPORT PDMA_CH0_1_IRQHandler [WEAK] + EXPORT PDMA_CH2_5_IRQHandler [WEAK] + +LVD_BOD_IRQHandler +RTC_IRQHandler +FLASH_IRQHandler +EVWUP_IRQHandler +EXTI0_1_IRQHandler +EXTI2_3_IRQHandler +EXTI4_15_IRQHandler +ADC_IRQHandler +GPTM0_IRQHandler +SCTM0_IRQHandler +SCTM1_IRQHandler +SCTM2_IRQHandler +SCTM3_IRQHandler +BFTM0_IRQHandler +BFTM1_IRQHandler +I2C0_IRQHandler +SPI0_IRQHandler +QSPI_IRQHandler +USART0_IRQHandler +UART0_IRQHandler +MIDI_IRQHandler +I2S_IRQHandler +USB_IRQHandler +PDMA_CH0_1_IRQHandler +PDMA_CH2_5_IRQHandler + B . + ENDP + + ALIGN + +;******************************************************************************* +; User Stack and Heap initialization +;******************************************************************************* + IF :DEF:__MICROLIB + + EXPORT __HT_check_heap + EXPORT __HT_check_sp + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, = (Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + + ENDIF + + END diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f61355_56_57.s b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f61355_56_57.s new file mode 100644 index 0000000000..418bcfd86f --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f61355_56_57.s @@ -0,0 +1,304 @@ +;/*---------------------------------------------------------------------------------------------------------*/ +;/* Holtek Semiconductor Inc. */ +;/* */ +;/* Copyright (C) Holtek Semiconductor Inc. */ +;/* All rights reserved. */ +;/* */ +;/*----------------------------------------------------------------------------------------------------------- +; File Name : startup_ht32f5xxxx_07.s +; Version : $Rev:: 5740 $ +; Date : $Date:: 2022-02-17 #$ +; Description : Startup code. +;-----------------------------------------------------------------------------------------------------------*/ + +; Supported Device +; ======================================== +; HT32F0006 +; HT32F61352 +; HT32F61355, HT32F61356, HT32F61357 + +;/* <<< Use Configuration Wizard in Context Menu >>> */ + +;// HT32 Device +;// Select HT32 Device for the assembly setting. +;// Notice that the project's Asm Define has the higher priority. +;// <0=> By Project Asm Define +;// <10=> HT32F0006 +;// <10=> HT32F61352 +;// <17=> HT32F61355/56/57 +USE_HT32_CHIP_SET EQU 17 ; Notice that the project's Asm Define has the higher priority. + +_HT32FWID EQU 0xFFFFFFFF +;_HT32FWID EQU 0x00000006 +;_HT32FWID EQU 0x00061352 +;_HT32FWID EQU 0x00061355 +;_HT32FWID EQU 0x00061356 +;_HT32FWID EQU 0x00061357 + +HT32F0006 EQU 10 +HT32F61352 EQU 10 +HT32F61355_56_57 EQU 17 + + IF USE_HT32_CHIP_SET=0 + ; Use project's Asm Define setting (default) + ELSE + IF :DEF:USE_HT32_CHIP + ; Use project's Asm Define setting (higher priority than the "USE_HT32_CHIP_SET") + ELSE + ; Use "USE_HT32_CHIP_SET" in the "startup_ht32xxxxx_xx.s" file +USE_HT32_CHIP EQU USE_HT32_CHIP_SET + ENDIF + ENDIF + +; Amount of memory (in bytes) allocated for Stack and Heap +; Tailor those values to your application needs +;// Stack Size (in Bytes, must 8 byte aligned) <0-16384:8> +Stack_Size EQU 512 + + AREA STACK, NOINIT, READWRITE, ALIGN = 3 +__HT_check_sp +Stack_Mem SPACE Stack_Size +__initial_sp + +;// Heap Size (in Bytes) <0-16384:8> +Heap_Size EQU 0 + + AREA HEAP, NOINIT, READWRITE, ALIGN = 3 +__HT_check_heap +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + PRESERVE8 + THUMB + +;******************************************************************************* +; Fill-up the Vector Table entries with the exceptions ISR address +;******************************************************************************* + AREA RESET, CODE, READONLY + EXPORT __Vectors +_RESERVED EQU 0xFFFFFFFF +__Vectors + DCD __initial_sp ; ---, 00, 0x000, Top address of Stack + DCD Reset_Handler ; ---, 01, 0x004, Reset Handler + DCD NMI_Handler ; -14, 02, 0x008, NMI Handler + DCD HardFault_Handler ; -13, 03, 0x00C, Hard Fault Handler + DCD _RESERVED ; ---, 04, 0x010, Reserved + DCD _RESERVED ; ---, 05, 0x014, Reserved + DCD _RESERVED ; ---, 06, 0x018, Reserved + DCD _RESERVED ; ---, 07, 0x01C, Reserved + DCD _HT32FWID ; ---, 08, 0x020, Reserved + DCD _RESERVED ; ---, 09, 0x024, Reserved + DCD _RESERVED ; ---, 10, 0x028, Reserved + DCD SVC_Handler ; -05, 11, 0x02C, SVC Handler + DCD _RESERVED ; ---, 12, 0x030, Reserved + DCD _RESERVED ; ---, 13, 0x034, Reserved + DCD PendSV_Handler ; -02, 14, 0x038, PendSV Handler + DCD SysTick_Handler ; -01, 15, 0x03C, SysTick Handler + + ; External Interrupt Handler + DCD LVD_BOD_IRQHandler ; 00, 16, 0x040, + DCD RTC_IRQHandler ; 01, 17, 0x044, + DCD FLASH_IRQHandler ; 02, 18, 0x048, + DCD EVWUP_IRQHandler ; 03, 19, 0x04C, + DCD EXTI0_1_IRQHandler ; 04, 20, 0x050, + DCD EXTI2_3_IRQHandler ; 05, 21, 0x054, + DCD EXTI4_15_IRQHandler ; 06, 22, 0x058, + DCD _RESERVED ; 07, 23, 0x05C, + DCD ADC_IRQHandler ; 08, 24, 0x060, + DCD _RESERVED ; 09, 25, 0x064, + DCD _RESERVED ; 10, 26, 0x068, + DCD _RESERVED ; 11, 27, 0x06C, + DCD GPTM0_IRQHandler ; 12, 28, 0x070, + DCD SCTM0_IRQHandler ; 13, 29, 0x074, + DCD SCTM1_IRQHandler ; 14, 30, 0x078, + DCD SCTM2_IRQHandler ; 15, 31, 0x07C, + DCD SCTM3_IRQHandler ; 16, 32, 0x080, + DCD BFTM0_IRQHandler ; 17, 33, 0x084, + DCD BFTM1_IRQHandler ; 18, 34, 0x088, + DCD I2C0_IRQHandler ; 19, 35, 0x08C, + DCD _RESERVED ; 20, 36, 0x090, + DCD SPI0_IRQHandler ; 21, 37, 0x094, + DCD QSPI_IRQHandler ; 22, 38, 0x098, + DCD USART0_IRQHandler ; 23, 39, 0x09C, + DCD _RESERVED ; 24, 40, 0x0A0, + DCD UART0_IRQHandler ; 25, 41, 0x0A4, + DCD _RESERVED ; 26, 42, 0x0A8, + DCD MIDI_IRQHandler ; 27, 43, 0x0AC, + DCD I2S_IRQHandler ; 28, 44, 0x0B0, + DCD USB_IRQHandler ; 29, 45, 0x0B4, + DCD PDMA_CH0_1_IRQHandler ; 30, 46, 0x0B8, + DCD PDMA_CH2_5_IRQHandler ; 31, 47, 0x0BC, + +; Reset handler routine +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + LDR R0, =BootProcess + BLX R0 + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +BootProcess PROC + LDR R0, =0x40080300 + LDR R1,[R0, #0x10] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x14] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x18] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x1C] + CMP R1, #0 + BEQ BP2 +BP1 LDR R0, =0x40080180 + LDR R1,[R0, #0xC] + LSLS R1, R1, #4 + LSRS R1, R1, #20 + CMP R1, #0 + BEQ BP3 + CMP R1, #5 + BEQ BP3 + CMP R1, #6 + BEQ BP3 +BP2 DSB + LDR R0, =0x20000000 + LDR R1, =0x05fa0004 + STR R1, [R0] + LDR R1, =0xe000ed00 + LDR R0, =0x05fa0004 + STR R0, [R1, #0xC] + DSB + B . +BP3 LDR R0, =0x20000000 + LDR R1, [R0] + LDR R0, =0x05fa0004 + CMP R0, R1 + BEQ BP4 + BX LR +BP4 LDR R0, =0x40088100 + LDR R1, =0x00000001 + STR R1, [R0] + LDR R0, =0x20000000 + LDR R1, =0x0 + STR R1, [R0] + BX LR + ENDP + +; Dummy Exception Handlers +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP + +HardFault_Handler PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP + +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP + +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP + +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + EXPORT LVD_BOD_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT EVWUP_IRQHandler [WEAK] + EXPORT EXTI0_1_IRQHandler [WEAK] + EXPORT EXTI2_3_IRQHandler [WEAK] + EXPORT EXTI4_15_IRQHandler [WEAK] + EXPORT ADC_IRQHandler [WEAK] + EXPORT GPTM0_IRQHandler [WEAK] + EXPORT SCTM0_IRQHandler [WEAK] + EXPORT SCTM1_IRQHandler [WEAK] + EXPORT SCTM2_IRQHandler [WEAK] + EXPORT SCTM3_IRQHandler [WEAK] + EXPORT BFTM0_IRQHandler [WEAK] + EXPORT BFTM1_IRQHandler [WEAK] + EXPORT I2C0_IRQHandler [WEAK] + EXPORT SPI0_IRQHandler [WEAK] + EXPORT QSPI_IRQHandler [WEAK] + EXPORT USART0_IRQHandler [WEAK] + EXPORT UART0_IRQHandler [WEAK] + EXPORT MIDI_IRQHandler [WEAK] + EXPORT I2S_IRQHandler [WEAK] + EXPORT USB_IRQHandler [WEAK] + EXPORT PDMA_CH0_1_IRQHandler [WEAK] + EXPORT PDMA_CH2_5_IRQHandler [WEAK] + +LVD_BOD_IRQHandler +RTC_IRQHandler +FLASH_IRQHandler +EVWUP_IRQHandler +EXTI0_1_IRQHandler +EXTI2_3_IRQHandler +EXTI4_15_IRQHandler +ADC_IRQHandler +GPTM0_IRQHandler +SCTM0_IRQHandler +SCTM1_IRQHandler +SCTM2_IRQHandler +SCTM3_IRQHandler +BFTM0_IRQHandler +BFTM1_IRQHandler +I2C0_IRQHandler +SPI0_IRQHandler +QSPI_IRQHandler +USART0_IRQHandler +UART0_IRQHandler +MIDI_IRQHandler +I2S_IRQHandler +USB_IRQHandler +PDMA_CH0_1_IRQHandler +PDMA_CH2_5_IRQHandler + B . + ENDP + + ALIGN + +;******************************************************************************* +; User Stack and Heap initialization +;******************************************************************************* + IF :DEF:__MICROLIB + + EXPORT __HT_check_heap + EXPORT __HT_check_sp + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, = (Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + + ENDIF + + END diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f61630.s b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f61630.s new file mode 100644 index 0000000000..45853e20f1 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f61630.s @@ -0,0 +1,235 @@ +;/*---------------------------------------------------------------------------------------------------------*/ +;/* Holtek Semiconductor Inc. */ +;/* */ +;/* Copyright (C) Holtek Semiconductor Inc. */ +;/* All rights reserved. */ +;/* */ +;/*----------------------------------------------------------------------------------------------------------- +; File Name : startup_ht32f5xxxx_13.s +; Version : $Rev:: 7119 $ +; Date : $Date:: 2023-08-15 #$ +; Description : Startup code. +;-----------------------------------------------------------------------------------------------------------*/ + +; Supported Device +; ======================================== +; HT32F50020, HT32F50030 +; HT32F61630 +; HT32F61030 + +;/* <<< Use Configuration Wizard in Context Menu >>> */ + +;// HT32 Device +;// Select HT32 Device for the assembly setting. +;// Notice that the project's Asm Define has the higher priority. +;// <0=> By Project Asm Define +;// <25=> HT32F50020/30 +;// <25=> HT32F61630 +;// <25=> HT32F61030 +USE_HT32_CHIP_SET EQU 25 ; Notice that the project's Asm Define has the higher priority. + +_HT32FWID EQU 0xFFFFFFFF +;_HT32FWID EQU 0x00050020 +;_HT32FWID EQU 0x00050030 +;_HT32FWID EQU 0x00061630 +;_HT32FWID EQU 0x00061030 + +HT32F50020_30 EQU 25 +HT32F61630 EQU 25 +HT32F61030 EQU 25 + + IF USE_HT32_CHIP_SET=0 + ; Use project's Asm Define setting (default) + ELSE + IF :DEF:USE_HT32_CHIP + ; Use project's Asm Define setting (higher priority than the "USE_HT32_CHIP_SET") + ELSE + ; Use "USE_HT32_CHIP_SET" in the "startup_ht32xxxxx_xx.s" file +USE_HT32_CHIP EQU USE_HT32_CHIP_SET + ENDIF + ENDIF + +; Amount of memory (in bytes) allocated for Stack and Heap +; Tailor those values to your application needs +;// Stack Size (in Bytes, must 8 byte aligned) <0-2048:8> +Stack_Size EQU 512 + + AREA STACK, NOINIT, READWRITE, ALIGN = 3 +__HT_check_sp +Stack_Mem SPACE Stack_Size +__initial_sp + +;// Heap Size (in Bytes) <0-2048:8> +Heap_Size EQU 0 + + AREA HEAP, NOINIT, READWRITE, ALIGN = 3 +__HT_check_heap +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + PRESERVE8 + THUMB + +;******************************************************************************* +; Fill-up the Vector Table entries with the exceptions ISR address +;******************************************************************************* + AREA RESET, CODE, READONLY + EXPORT __Vectors +_RESERVED EQU 0xFFFFFFFF +__Vectors + DCD __initial_sp ; ---, 00, 0x000, Top address of Stack + DCD Reset_Handler ; ---, 01, 0x004, Reset Handler + DCD NMI_Handler ; -14, 02, 0x008, NMI Handler + DCD HardFault_Handler ; -13, 03, 0x00C, Hard Fault Handler + DCD _RESERVED ; ---, 04, 0x010, Reserved + DCD _RESERVED ; ---, 05, 0x014, Reserved + DCD _RESERVED ; ---, 06, 0x018, Reserved + DCD _RESERVED ; ---, 07, 0x01C, Reserved + DCD _HT32FWID ; ---, 08, 0x020, Reserved + DCD _RESERVED ; ---, 09, 0x024, Reserved + DCD _RESERVED ; ---, 10, 0x028, Reserved + DCD SVC_Handler ; -05, 11, 0x02C, SVC Handler + DCD _RESERVED ; ---, 12, 0x030, Reserved + DCD _RESERVED ; ---, 13, 0x034, Reserved + DCD PendSV_Handler ; -02, 14, 0x038, PendSV Handler + DCD SysTick_Handler ; -01, 15, 0x03C, SysTick Handler + + ; External Interrupt Handler + DCD LVD_BOD_IRQHandler ; 00, 16, 0x040, + DCD RTC_IRQHandler ; 01, 17, 0x044, + DCD FLASH_IRQHandler ; 02, 18, 0x048, + DCD EVWUP_IRQHandler ; 03, 19, 0x04C, + DCD EXTI0_1_IRQHandler ; 04, 20, 0x050, + DCD EXTI2_3_IRQHandler ; 05, 21, 0x054, + DCD EXTI4_7_IRQHandler ; 06, 22, 0x058, + DCD _RESERVED ; 07, 23, 0x05C, + DCD ADC_IRQHandler ; 08, 24, 0x060, + DCD _RESERVED ; 09, 25, 0x064, + DCD _RESERVED ; 10, 26, 0x068, + DCD _RESERVED ; 11, 27, 0x06C, + DCD _RESERVED ; 12, 28, 0x070, + DCD SCTM0_IRQHandler ; 13, 29, 0x074, + DCD SCTM1_IRQHandler ; 14, 30, 0x078, + DCD SCTM2_IRQHandler ; 15, 31, 0x07C, + DCD _RESERVED ; 16, 32, 0x080, + DCD BFTM0_IRQHandler ; 17, 33, 0x084, + DCD _RESERVED ; 18, 34, 0x088, + DCD I2C0_IRQHandler ; 19, 35, 0x08C, + DCD _RESERVED ; 20, 36, 0x090, + DCD SPI0_IRQHandler ; 21, 37, 0x094, + DCD _RESERVED ; 22, 38, 0x098, + DCD _RESERVED ; 23, 39, 0x09C, + DCD _RESERVED ; 24, 40, 0x0A0, + DCD UART0_IRQHandler ; 25, 41, 0x0A4, + DCD UART1_IRQHandler ; 26, 42, 0x0A8, + DCD _RESERVED ; 27, 43, 0x0AC, + DCD _RESERVED ; 28, 44, 0x0B0, + DCD LEDC_IRQHandler ; 29, 45, 0x0B4, + +; Reset handler routine +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception Handlers +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP + +HardFault_Handler PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP + +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP + +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP + +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + EXPORT LVD_BOD_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT EVWUP_IRQHandler [WEAK] + EXPORT EXTI0_1_IRQHandler [WEAK] + EXPORT EXTI2_3_IRQHandler [WEAK] + EXPORT EXTI4_7_IRQHandler [WEAK] + EXPORT ADC_IRQHandler [WEAK] + EXPORT SCTM0_IRQHandler [WEAK] + EXPORT SCTM1_IRQHandler [WEAK] + EXPORT SCTM2_IRQHandler [WEAK] + EXPORT BFTM0_IRQHandler [WEAK] + EXPORT I2C0_IRQHandler [WEAK] + EXPORT SPI0_IRQHandler [WEAK] + EXPORT UART0_IRQHandler [WEAK] + EXPORT UART1_IRQHandler [WEAK] + EXPORT LEDC_IRQHandler [WEAK] + +LVD_BOD_IRQHandler +RTC_IRQHandler +FLASH_IRQHandler +EVWUP_IRQHandler +EXTI0_1_IRQHandler +EXTI2_3_IRQHandler +EXTI4_7_IRQHandler +ADC_IRQHandler +SCTM0_IRQHandler +SCTM1_IRQHandler +SCTM2_IRQHandler +BFTM0_IRQHandler +I2C0_IRQHandler +SPI0_IRQHandler +UART0_IRQHandler +UART1_IRQHandler +LEDC_IRQHandler + B . + ENDP + + ALIGN + +;******************************************************************************* +; User Stack and Heap initialization +;******************************************************************************* + IF :DEF:__MICROLIB + + EXPORT __HT_check_heap + EXPORT __HT_check_sp + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, = (Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + + ENDIF + + END diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f61641.s b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f61641.s new file mode 100644 index 0000000000..8e68952909 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f61641.s @@ -0,0 +1,327 @@ +;/*---------------------------------------------------------------------------------------------------------*/ +;/* Holtek Semiconductor Inc. */ +;/* */ +;/* Copyright (C) Holtek Semiconductor Inc. */ +;/* All rights reserved. */ +;/* */ +;/*----------------------------------------------------------------------------------------------------------- +; File Name : startup_ht32f5xxxx_02.s +; Version : $Rev:: 7119 $ +; Date : $Date:: 2023-08-15 #$ +; Description : Startup code. +;-----------------------------------------------------------------------------------------------------------*/ + +; Supported Device +; ======================================== +; HT32F50220, HT32F50230 +; HT32F50231, HT32F50241 +; HT50F32002 +; HT32F59041 +; HF5032 +; HT32F61641 +; HT32F59046 +; HT32F61041 + +;/* <<< Use Configuration Wizard in Context Menu >>> */ + +;// HT32 Device +;// Select HT32 Device for the assembly setting. +;// Notice that the project's Asm Define has the higher priority. +;// <0=> By Project Asm Define +;// <7=> HT32F50220/30 +;// <8=> HT32F50231/41 +;// <7=> HT50F32002 +;// <8=> HT32F59041 +;// <7=> HF5032 +;// <8=> HT32F61641 +;// <8=> HT32F59046 +;// <8=> HT32F61041 +USE_HT32_CHIP_SET EQU 8 ; Notice that the project's Asm Define has the higher priority. + +_HT32FWID EQU 0xFFFFFFFF +;_HT32FWID EQU 0x00050220 +;_HT32FWID EQU 0x00050230 +;_HT32FWID EQU 0x00050231 +;_HT32FWID EQU 0x00050241 +;_HT32FWID EQU 0x00032002 +;_HT32FWID EQU 0x00059041 +;_HT32FWID EQU 0x000F5032 +;_HT32FWID EQU 0x00061641 +;_HT32FWID EQU 0x00059046 +;_HT32FWID EQU 0x00061041 + +HT32F50220_30 EQU 7 +HT32F50231_41 EQU 8 +HT50F32002 EQU 7 +HT32F59041 EQU 8 +HF5032 EQU 7 +HT32F61641 EQU 8 +HT32F59046 EQU 8 +HT32F61041 EQU 8 + + IF USE_HT32_CHIP_SET=0 + ; Use project's Asm Define setting (default) + ELSE + IF :DEF:USE_HT32_CHIP + ; Use project's Asm Define setting (higher priority than the "USE_HT32_CHIP_SET") + ELSE + ; Use "USE_HT32_CHIP_SET" in the "startup_ht32xxxxx_xx.s" file +USE_HT32_CHIP EQU USE_HT32_CHIP_SET + ENDIF + ENDIF + +; Amount of memory (in bytes) allocated for Stack and Heap +; Tailor those values to your application needs +;// Stack Size (in Bytes, must 8 byte aligned) <0-4096:8> +Stack_Size EQU 512 + + AREA STACK, NOINIT, READWRITE, ALIGN = 3 +__HT_check_sp +Stack_Mem SPACE Stack_Size +__initial_sp + +;// Heap Size (in Bytes) <0-4096:8> +Heap_Size EQU 0 + + AREA HEAP, NOINIT, READWRITE, ALIGN = 3 +__HT_check_heap +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + PRESERVE8 + THUMB + +;******************************************************************************* +; Fill-up the Vector Table entries with the exceptions ISR address +;******************************************************************************* + AREA RESET, CODE, READONLY + EXPORT __Vectors +_RESERVED EQU 0xFFFFFFFF +__Vectors + DCD __initial_sp ; ---, 00, 0x000, Top address of Stack + DCD Reset_Handler ; ---, 01, 0x004, Reset Handler + DCD NMI_Handler ; -14, 02, 0x008, NMI Handler + DCD HardFault_Handler ; -13, 03, 0x00C, Hard Fault Handler + DCD _RESERVED ; ---, 04, 0x010, Reserved + DCD _RESERVED ; ---, 05, 0x014, Reserved + DCD _RESERVED ; ---, 06, 0x018, Reserved + DCD _RESERVED ; ---, 07, 0x01C, Reserved + DCD _HT32FWID ; ---, 08, 0x020, Reserved + DCD _RESERVED ; ---, 09, 0x024, Reserved + DCD _RESERVED ; ---, 10, 0x028, Reserved + DCD SVC_Handler ; -05, 11, 0x02C, SVC Handler + DCD _RESERVED ; ---, 12, 0x030, Reserved + DCD _RESERVED ; ---, 13, 0x034, Reserved + DCD PendSV_Handler ; -02, 14, 0x038, PendSV Handler + DCD SysTick_Handler ; -01, 15, 0x03C, SysTick Handler + + ; External Interrupt Handler + DCD LVD_BOD_IRQHandler ; 00, 16, 0x040, + DCD RTC_IRQHandler ; 01, 17, 0x044, + DCD FLASH_IRQHandler ; 02, 18, 0x048, + DCD EVWUP_IRQHandler ; 03, 19, 0x04C, + DCD EXTI0_1_IRQHandler ; 04, 20, 0x050, + DCD EXTI2_3_IRQHandler ; 05, 21, 0x054, + DCD EXTI4_15_IRQHandler ; 06, 22, 0x058, + DCD _RESERVED ; 07, 23, 0x05C, + DCD ADC_IRQHandler ; 08, 24, 0x060, + DCD _RESERVED ; 09, 25, 0x064, + IF (USE_HT32_CHIP=HT32F50220_30) + DCD _RESERVED ; 10, 26, 0x068, + ELSE + DCD MCTM0_IRQHandler ; 10, 26, 0x068, + ENDIF + DCD _RESERVED ; 11, 27, 0x06C, + DCD GPTM0_IRQHandler ; 12, 28, 0x070, + DCD _RESERVED ; 13, 29, 0x074, + DCD _RESERVED ; 14, 30, 0x078, + DCD PWM0_IRQHandler ; 15, 31, 0x07C, + DCD PWM1_IRQHandler ; 16, 32, 0x080, + DCD BFTM0_IRQHandler ; 17, 33, 0x084, + IF (USE_HT32_CHIP=HT32F50220_30) + DCD _RESERVED ; 18, 34, 0x088, + ELSE + DCD BFTM1_IRQHandler ; 18, 34, 0x088, + ENDIF + DCD I2C0_IRQHandler ; 19, 35, 0x08C, + IF (USE_HT32_CHIP=HT32F50220_30) + DCD _RESERVED ; 20, 36, 0x090, + ELSE + DCD I2C1_IRQHandler ; 20, 36, 0x090, + ENDIF + DCD SPI0_IRQHandler ; 21, 37, 0x094, + DCD SPI1_IRQHandler ; 22, 38, 0x098, + IF (USE_HT32_CHIP=HT32F50220_30) + DCD _RESERVED ; 23, 39, 0x09C, + ELSE + DCD USART0_IRQHandler ; 23, 39, 0x09C, + ENDIF + DCD _RESERVED ; 24, 40, 0x0A0, + DCD UART0_IRQHandler ; 25, 41, 0x0A4, + DCD UART1_IRQHandler ; 26, 42, 0x0A8, + +; Reset handler routine +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + LDR R0, =BootProcess + BLX R0 + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +BootProcess PROC + LDR R0, =0x40080300 + LDR R1,[R0, #0x10] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x14] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x18] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x1C] + CMP R1, #0 + BEQ BP2 +BP1 LDR R0, =0x40080180 + LDR R1,[R0, #0xC] + LSLS R1, R1, #4 + LSRS R1, R1, #20 + CMP R1, #0 + BEQ BP3 + CMP R1, #5 + BEQ BP3 + CMP R1, #6 + BEQ BP3 +BP2 DSB + LDR R0, =0x20000000 + LDR R1, =0x05fa0004 + STR R1, [R0] + LDR R1, =0xe000ed00 + LDR R0, =0x05fa0004 + STR R0, [R1, #0xC] + DSB + B . +BP3 LDR R0, =0x20000000 + LDR R1, [R0] + LDR R0, =0x05fa0004 + CMP R0, R1 + BEQ BP4 + BX LR +BP4 LDR R0, =0x40088100 + LDR R1, =0x00000001 + STR R1, [R0] + LDR R0, =0x20000000 + LDR R1, =0x0 + STR R1, [R0] + BX LR + ENDP + +; Dummy Exception Handlers +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP + +HardFault_Handler PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP + +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP + +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP + +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + EXPORT LVD_BOD_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT EVWUP_IRQHandler [WEAK] + EXPORT EXTI0_1_IRQHandler [WEAK] + EXPORT EXTI2_3_IRQHandler [WEAK] + EXPORT EXTI4_15_IRQHandler [WEAK] + EXPORT ADC_IRQHandler [WEAK] + EXPORT MCTM0_IRQHandler [WEAK] + EXPORT GPTM0_IRQHandler [WEAK] + EXPORT PWM0_IRQHandler [WEAK] + EXPORT PWM1_IRQHandler [WEAK] + EXPORT BFTM0_IRQHandler [WEAK] + EXPORT BFTM1_IRQHandler [WEAK] + EXPORT I2C0_IRQHandler [WEAK] + EXPORT I2C1_IRQHandler [WEAK] + EXPORT SPI0_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT USART0_IRQHandler [WEAK] + EXPORT UART0_IRQHandler [WEAK] + EXPORT UART1_IRQHandler [WEAK] + +LVD_BOD_IRQHandler +RTC_IRQHandler +FLASH_IRQHandler +EVWUP_IRQHandler +EXTI0_1_IRQHandler +EXTI2_3_IRQHandler +EXTI4_15_IRQHandler +ADC_IRQHandler +MCTM0_IRQHandler +GPTM0_IRQHandler +PWM0_IRQHandler +PWM1_IRQHandler +BFTM0_IRQHandler +BFTM1_IRQHandler +I2C0_IRQHandler +I2C1_IRQHandler +SPI0_IRQHandler +SPI1_IRQHandler +USART0_IRQHandler +UART0_IRQHandler +UART1_IRQHandler + B . + ENDP + + ALIGN + +;******************************************************************************* +; User Stack and Heap initialization +;******************************************************************************* + IF :DEF:__MICROLIB + + EXPORT __HT_check_heap + EXPORT __HT_check_sp + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, = (Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + + ENDIF + + END diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f62030.s b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f62030.s new file mode 100644 index 0000000000..ae562b2a89 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f62030.s @@ -0,0 +1,482 @@ +;/*---------------------------------------------------------------------------------------------------------*/ +;/* Holtek Semiconductor Inc. */ +;/* */ +;/* Copyright (C) Holtek Semiconductor Inc. */ +;/* All rights reserved. */ +;/* */ +;/*----------------------------------------------------------------------------------------------------------- +; File Name : startup_ht32f5xxxx_01.s +; Version : $Rev:: 6953 $ +; Date : $Date:: 2023-05-30 #$ +; Description : Startup code. +;-----------------------------------------------------------------------------------------------------------*/ + +; Supported Device +; ======================================== +; HT32F52220, HT32F52230 +; HT32F52231, HT32F52241 +; HT32F52331, HT32F52341 +; HT32F52342, HT32F52352 +; HT32F52243, HT32F52253 +; HT32F0008 +; HT32F52344, HT32F52354 +; HT32F0006 +; HT32F61352 +; HT50F32003 +; HT32F62030, HT32F62040, HT32F62050 +; HT32F67741 +; HT32F67232 +; HT32F67233 + +;/* <<< Use Configuration Wizard in Context Menu >>> */ + +;// HT32 Device +;// Select HT32 Device for the assembly setting. +;// Notice that the project's Asm Define has the higher priority. +;// <0=> By Project Asm Define +;// <1=> HT32F52220/30 +;// <2=> HT32F52231/41 +;// <3=> HT32F52331/41 +;// <4=> HT32F52342/52 +;// <5=> HT32F52243/53 +;// <6=> HT32F0008 +;// <9=> HT32F52344/54 +;// <10=> HT32F0006 +;// <10=> HT32F61352 +;// <4=> HT50F32003 +;// <2=> HT32F67741 +;// <1=> HT32F67232 +;// <1=> HT32F67233 +;// <1=> HT32F62030 +;// <2=> HT32F62040 +;// <5=> HT32F62050 +USE_HT32_CHIP_SET EQU 1 ; Notice that the project's Asm Define has the higher priority. + +_HT32FWID EQU 0xFFFFFFFF +;_HT32FWID EQU 0x00052220 +;_HT32FWID EQU 0x00052230 +;_HT32FWID EQU 0x00052231 +;_HT32FWID EQU 0x00052241 +;_HT32FWID EQU 0x00052331 +;_HT32FWID EQU 0x00052341 +;_HT32FWID EQU 0x00052342 +;_HT32FWID EQU 0x00052352 +;_HT32FWID EQU 0x00052243 +;_HT32FWID EQU 0x00052253 +;_HT32FWID EQU 0x00000008 +;_HT32FWID EQU 0x00052344 +;_HT32FWID EQU 0x00052354 +;_HT32FWID EQU 0x00000006 +;_HT32FWID EQU 0x00061352 +;_HT32FWID EQU 0x00032003 +;_HT32FWID EQU 0x00062030 +;_HT32FWID EQU 0x00062040 +;_HT32FWID EQU 0x00062050 +;_HT32FWID EQU 0x00067741 +;_HT32FWID EQU 0x00067232 +;_HT32FWID EQU 0x00067233 + +HT32F52220_30 EQU 1 +HT32F52231_41 EQU 2 +HT32F52331_41 EQU 3 +HT32F52342_52 EQU 4 +HT32F52243_53 EQU 5 +HT32F0008 EQU 6 +HT32F52344_54 EQU 9 +HT32F0006 EQU 10 +HT32F61352 EQU 10 +HT50F32003 EQU 4 +HT32F62030 EQU 1 +HT32F62040 EQU 2 +HT32F62050 EQU 5 +HT32F67741 EQU 2 +HT32F67232 EQU 1 +HT32F67233 EQU 1 + + IF USE_HT32_CHIP_SET=0 + ; Use project's Asm Define setting (default) + ELSE + IF :DEF:USE_HT32_CHIP + ; Use project's Asm Define setting (higher priority than the "USE_HT32_CHIP_SET") + ELSE + ; Use "USE_HT32_CHIP_SET" in the "startup_ht32xxxxx_xx.s" file +USE_HT32_CHIP EQU USE_HT32_CHIP_SET + ENDIF + ENDIF + +; Amount of memory (in bytes) allocated for Stack and Heap +; Tailor those values to your application needs +;// Stack Size (in Bytes, must 8 byte aligned) <0-16384:8> +Stack_Size EQU 512 + + AREA STACK, NOINIT, READWRITE, ALIGN = 3 +__HT_check_sp +Stack_Mem SPACE Stack_Size +__initial_sp + +;// Heap Size (in Bytes) <0-16384:8> +Heap_Size EQU 0 + + AREA HEAP, NOINIT, READWRITE, ALIGN = 3 +__HT_check_heap +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + PRESERVE8 + THUMB + +;******************************************************************************* +; Fill-up the Vector Table entries with the exceptions ISR address +;******************************************************************************* + AREA RESET, CODE, READONLY + EXPORT __Vectors +_RESERVED EQU 0xFFFFFFFF +__Vectors + DCD __initial_sp ; ---, 00, 0x000, Top address of Stack + DCD Reset_Handler ; ---, 01, 0x004, Reset Handler + DCD NMI_Handler ; -14, 02, 0x008, NMI Handler + DCD HardFault_Handler ; -13, 03, 0x00C, Hard Fault Handler + DCD _RESERVED ; ---, 04, 0x010, Reserved + DCD _RESERVED ; ---, 05, 0x014, Reserved + DCD _RESERVED ; ---, 06, 0x018, Reserved + DCD _RESERVED ; ---, 07, 0x01C, Reserved + DCD _HT32FWID ; ---, 08, 0x020, Reserved + DCD _RESERVED ; ---, 09, 0x024, Reserved + DCD _RESERVED ; ---, 10, 0x028, Reserved + DCD SVC_Handler ; -05, 11, 0x02C, SVC Handler + DCD _RESERVED ; ---, 12, 0x030, Reserved + DCD _RESERVED ; ---, 13, 0x034, Reserved + DCD PendSV_Handler ; -02, 14, 0x038, PendSV Handler + DCD SysTick_Handler ; -01, 15, 0x03C, SysTick Handler + + ; External Interrupt Handler + DCD LVD_BOD_IRQHandler ; 00, 16, 0x040, + IF (USE_HT32_CHIP=HT32F52220_30) + DCD _RESERVED ; 01, 17, 0x044, + ELSE + DCD RTC_IRQHandler ; 01, 17, 0x044, + ENDIF + DCD FLASH_IRQHandler ; 02, 18, 0x048, + DCD EVWUP_IRQHandler ; 03, 19, 0x04C, + DCD EXTI0_1_IRQHandler ; 04, 20, 0x050, + DCD EXTI2_3_IRQHandler ; 05, 21, 0x054, + DCD EXTI4_15_IRQHandler ; 06, 22, 0x058, + IF (USE_HT32_CHIP=HT32F52342_52) || (USE_HT32_CHIP=HT32F52344_54) + DCD COMP_IRQHandler ; 07, 23, 0x05C, + ELSE + DCD _RESERVED ; 07, 23, 0x05C, + ENDIF + IF (USE_HT32_CHIP=HT32F0008) + DCD _RESERVED ; 08, 24, 0x060, + ELSE + DCD ADC_IRQHandler ; 08, 24, 0x060, + ENDIF + IF (USE_HT32_CHIP=HT32F52243_53) + DCD I2C2_IRQHandler ; 09, 25, 0x064, + ELSE + DCD _RESERVED ; 09, 25, 0x064, + ENDIF + IF (USE_HT32_CHIP=HT32F52220_30) || (USE_HT32_CHIP=HT32F0008) || (USE_HT32_CHIP=HT32F0006) + DCD _RESERVED ; 10, 26, 0x068, + ELSE + DCD MCTM0_IRQHandler ; 10, 26, 0x068, + ENDIF + IF (USE_HT32_CHIP=HT32F52342_52) + DCD GPTM1_IRQHandler ; 11, 27, 0x06C, + ELSE + DCD _RESERVED ; 11, 27, 0x06C, + ENDIF + DCD GPTM0_IRQHandler ; 12, 28, 0x070, + IF (USE_HT32_CHIP=HT32F0008) + DCD _RESERVED ; 13, 29, 0x074, + DCD _RESERVED ; 14, 30, 0x078, + ELSE + DCD SCTM0_IRQHandler ; 13, 29, 0x074, + DCD SCTM1_IRQHandler ; 14, 30, 0x078, + ENDIF + IF (USE_HT32_CHIP=HT32F52231_41) || (USE_HT32_CHIP=HT32F52331_41) || (USE_HT32_CHIP=HT32F52243_53) || (USE_HT32_CHIP=HT32F0006) + DCD SCTM2_IRQHandler ; 15, 31, 0x07C, + DCD SCTM3_IRQHandler ; 16, 32, 0x080, + ENDIF + IF (USE_HT32_CHIP=HT32F0008) + DCD PWM0_IRQHandler ; 15, 31, 0x07C, + DCD PWM1_IRQHandler ; 16, 32, 0x080, + ENDIF + IF (USE_HT32_CHIP=HT32F52220_30) || (USE_HT32_CHIP=HT32F52342_52) || (USE_HT32_CHIP=HT32F52344_54) + DCD _RESERVED ; 15, 31, 0x07C, + DCD _RESERVED ; 16, 32, 0x080, + ENDIF + DCD BFTM0_IRQHandler ; 17, 33, 0x084, + IF (USE_HT32_CHIP=HT32F52220_30) + DCD _RESERVED ; 18, 34, 0x088, + ELSE + DCD BFTM1_IRQHandler ; 18, 34, 0x088, + ENDIF + DCD I2C0_IRQHandler ; 19, 35, 0x08C, + IF (USE_HT32_CHIP=HT32F52220_30) || (USE_HT32_CHIP=HT32F0008) || (USE_HT32_CHIP=HT32F52344_54) || (USE_HT32_CHIP=HT32F0006) + DCD _RESERVED ; 20, 36, 0x090, + ELSE + DCD I2C1_IRQHandler ; 20, 36, 0x090, + ENDIF + DCD SPI0_IRQHandler ; 21, 37, 0x094, + IF (USE_HT32_CHIP=HT32F52220_30) || (USE_HT32_CHIP=HT32F0008) + DCD _RESERVED ; 22, 38, 0x098, + ELSE + IF (USE_HT32_CHIP=HT32F0006) + DCD QSPI_IRQHandler ; 22, 38, 0x098, + ELSE + DCD SPI1_IRQHandler ; 22, 38, 0x098, + ENDIF + ENDIF + IF (USE_HT32_CHIP=HT32F52344_54) + DCD _RESERVED ; 23, 39, 0x09C, + ELSE + DCD USART0_IRQHandler ; 23, 39, 0x09C, + ENDIF + IF (USE_HT32_CHIP=HT32F52342_52) || (USE_HT32_CHIP=HT32F52243_53) + DCD USART1_IRQHandler ; 24, 40, 0x0A0, + ELSE + DCD _RESERVED ; 24, 40, 0x0A0, + ENDIF + DCD UART0_IRQHandler ; 25, 41, 0x0A4, + IF (USE_HT32_CHIP=HT32F52220_30) || (USE_HT32_CHIP=HT32F0008) || (USE_HT32_CHIP=HT32F0006) + DCD _RESERVED ; 26, 42, 0x0A8, + ELSE + DCD UART1_IRQHandler ; 26, 42, 0x0A8, + ENDIF + IF (USE_HT32_CHIP=HT32F52331_41) || (USE_HT32_CHIP=HT32F52342_52) + DCD SCI_IRQHandler ; 27, 43, 0x0AC, + ENDIF + IF (USE_HT32_CHIP=HT32F52243_53) + DCD UART2_IRQHandler ; 27, 43, 0x0AC, + ENDIF + IF (USE_HT32_CHIP=HT32F0006) + DCD MIDI_IRQHandler ; 27, 43, 0x0AC, + ENDIF + IF (USE_HT32_CHIP=HT32F0008) || (USE_HT32_CHIP=HT32F52344_54) + DCD _RESERVED ; 27, 43, 0xAC, + ENDIF + IF (USE_HT32_CHIP=HT32F52342_52) || (USE_HT32_CHIP=HT32F0006) + DCD I2S_IRQHandler ; 28, 44, 0x0B0, + ENDIF + IF (USE_HT32_CHIP=HT32F52331_41) || (USE_HT32_CHIP=HT32F52344_54) + DCD _RESERVED ; 28, 44, 0x0B0, + ENDIF + IF (USE_HT32_CHIP=HT32F52243_53) + DCD UART3_IRQHandler ; 28, 44, 0x0B0, + ENDIF + IF (USE_HT32_CHIP=HT32F0008) + DCD AES_IRQHandler ; 28, 44, 0x0B0, + ENDIF + IF (USE_HT32_CHIP=HT32F52331_41) || (USE_HT32_CHIP=HT32F52342_52) || (USE_HT32_CHIP=HT32F0008) || (USE_HT32_CHIP=HT32F52344_54) || (USE_HT32_CHIP=HT32F0006) + DCD USB_IRQHandler ; 29, 45, 0x0B4, + ENDIF + IF (USE_HT32_CHIP=HT32F52243_53) + DCD _RESERVED ; 29, 45, 0x0B4, + ENDIF + IF (USE_HT32_CHIP=HT32F52342_52) || (USE_HT32_CHIP=HT32F52243_53) || (USE_HT32_CHIP=HT32F0008) || (USE_HT32_CHIP=HT32F52344_54) || (USE_HT32_CHIP=HT32F0006) + DCD PDMA_CH0_1_IRQHandler ; 30, 46, 0x0B8, + DCD PDMA_CH2_5_IRQHandler ; 31, 47, 0x0BC, + ENDIF + +; Reset handler routine +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + LDR R0, =BootProcess + BLX R0 + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +BootProcess PROC + LDR R0, =0x40080300 + LDR R1,[R0, #0x10] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x14] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x18] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x1C] + CMP R1, #0 + BEQ BP2 +BP1 LDR R0, =0x40080180 + LDR R1,[R0, #0xC] + LSLS R1, R1, #4 + LSRS R1, R1, #20 + CMP R1, #0 + BEQ BP3 + CMP R1, #5 + BEQ BP3 + CMP R1, #6 + BEQ BP3 +BP2 DSB + LDR R0, =0x20000000 + LDR R1, =0x05fa0004 + STR R1, [R0] + LDR R1, =0xe000ed00 + LDR R0, =0x05fa0004 + STR R0, [R1, #0xC] + DSB + B . +BP3 LDR R0, =0x20000000 + LDR R1, [R0] + LDR R0, =0x05fa0004 + CMP R0, R1 + BEQ BP4 + BX LR +BP4 LDR R0, =0x40088100 + LDR R1, =0x00000001 + STR R1, [R0] + LDR R0, =0x20000000 + LDR R1, =0x0 + STR R1, [R0] + BX LR + ENDP + +; Dummy Exception Handlers +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP + +HardFault_Handler PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP + +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP + +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP + +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + EXPORT LVD_BOD_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT EVWUP_IRQHandler [WEAK] + EXPORT EXTI0_1_IRQHandler [WEAK] + EXPORT EXTI2_3_IRQHandler [WEAK] + EXPORT EXTI4_15_IRQHandler [WEAK] + EXPORT COMP_IRQHandler [WEAK] + EXPORT ADC_IRQHandler [WEAK] + EXPORT MCTM0_IRQHandler [WEAK] + EXPORT GPTM1_IRQHandler [WEAK] + EXPORT GPTM0_IRQHandler [WEAK] + EXPORT SCTM0_IRQHandler [WEAK] + EXPORT SCTM1_IRQHandler [WEAK] + EXPORT SCTM2_IRQHandler [WEAK] + EXPORT SCTM3_IRQHandler [WEAK] + EXPORT PWM0_IRQHandler [WEAK] + EXPORT PWM1_IRQHandler [WEAK] + EXPORT BFTM0_IRQHandler [WEAK] + EXPORT BFTM1_IRQHandler [WEAK] + EXPORT I2C0_IRQHandler [WEAK] + EXPORT I2C1_IRQHandler [WEAK] + EXPORT I2C2_IRQHandler [WEAK] + EXPORT SPI0_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT QSPI_IRQHandler [WEAK] + EXPORT USART0_IRQHandler [WEAK] + EXPORT USART1_IRQHandler [WEAK] + EXPORT UART0_IRQHandler [WEAK] + EXPORT UART1_IRQHandler [WEAK] + EXPORT UART2_IRQHandler [WEAK] + EXPORT UART3_IRQHandler [WEAK] + EXPORT SCI_IRQHandler [WEAK] + EXPORT MIDI_IRQHandler [WEAK] + EXPORT I2S_IRQHandler [WEAK] + EXPORT AES_IRQHandler [WEAK] + EXPORT USB_IRQHandler [WEAK] + EXPORT PDMA_CH0_1_IRQHandler [WEAK] + EXPORT PDMA_CH2_5_IRQHandler [WEAK] + +LVD_BOD_IRQHandler +RTC_IRQHandler +FLASH_IRQHandler +EVWUP_IRQHandler +EXTI0_1_IRQHandler +EXTI2_3_IRQHandler +EXTI4_15_IRQHandler +COMP_IRQHandler +ADC_IRQHandler +MCTM0_IRQHandler +GPTM1_IRQHandler +GPTM0_IRQHandler +SCTM0_IRQHandler +SCTM1_IRQHandler +SCTM2_IRQHandler +SCTM3_IRQHandler +PWM0_IRQHandler +PWM1_IRQHandler +BFTM0_IRQHandler +BFTM1_IRQHandler +I2C0_IRQHandler +I2C1_IRQHandler +I2C2_IRQHandler +SPI0_IRQHandler +SPI1_IRQHandler +QSPI_IRQHandler +USART0_IRQHandler +USART1_IRQHandler +UART0_IRQHandler +UART1_IRQHandler +UART2_IRQHandler +UART3_IRQHandler +SCI_IRQHandler +MIDI_IRQHandler +I2S_IRQHandler +AES_IRQHandler +USB_IRQHandler +PDMA_CH0_1_IRQHandler +PDMA_CH2_5_IRQHandler + B . + ENDP + + ALIGN + +;******************************************************************************* +; User Stack and Heap initialization +;******************************************************************************* + IF :DEF:__MICROLIB + + EXPORT __HT_check_heap + EXPORT __HT_check_sp + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, = (Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + + ENDIF + + END diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f62040.s b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f62040.s new file mode 100644 index 0000000000..c653285b1f --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f62040.s @@ -0,0 +1,482 @@ +;/*---------------------------------------------------------------------------------------------------------*/ +;/* Holtek Semiconductor Inc. */ +;/* */ +;/* Copyright (C) Holtek Semiconductor Inc. */ +;/* All rights reserved. */ +;/* */ +;/*----------------------------------------------------------------------------------------------------------- +; File Name : startup_ht32f5xxxx_01.s +; Version : $Rev:: 6953 $ +; Date : $Date:: 2023-05-30 #$ +; Description : Startup code. +;-----------------------------------------------------------------------------------------------------------*/ + +; Supported Device +; ======================================== +; HT32F52220, HT32F52230 +; HT32F52231, HT32F52241 +; HT32F52331, HT32F52341 +; HT32F52342, HT32F52352 +; HT32F52243, HT32F52253 +; HT32F0008 +; HT32F52344, HT32F52354 +; HT32F0006 +; HT32F61352 +; HT50F32003 +; HT32F62030, HT32F62040, HT32F62050 +; HT32F67741 +; HT32F67232 +; HT32F67233 + +;/* <<< Use Configuration Wizard in Context Menu >>> */ + +;// HT32 Device +;// Select HT32 Device for the assembly setting. +;// Notice that the project's Asm Define has the higher priority. +;// <0=> By Project Asm Define +;// <1=> HT32F52220/30 +;// <2=> HT32F52231/41 +;// <3=> HT32F52331/41 +;// <4=> HT32F52342/52 +;// <5=> HT32F52243/53 +;// <6=> HT32F0008 +;// <9=> HT32F52344/54 +;// <10=> HT32F0006 +;// <10=> HT32F61352 +;// <4=> HT50F32003 +;// <2=> HT32F67741 +;// <1=> HT32F67232 +;// <1=> HT32F67233 +;// <1=> HT32F62030 +;// <2=> HT32F62040 +;// <5=> HT32F62050 +USE_HT32_CHIP_SET EQU 2 ; Notice that the project's Asm Define has the higher priority. + +_HT32FWID EQU 0xFFFFFFFF +;_HT32FWID EQU 0x00052220 +;_HT32FWID EQU 0x00052230 +;_HT32FWID EQU 0x00052231 +;_HT32FWID EQU 0x00052241 +;_HT32FWID EQU 0x00052331 +;_HT32FWID EQU 0x00052341 +;_HT32FWID EQU 0x00052342 +;_HT32FWID EQU 0x00052352 +;_HT32FWID EQU 0x00052243 +;_HT32FWID EQU 0x00052253 +;_HT32FWID EQU 0x00000008 +;_HT32FWID EQU 0x00052344 +;_HT32FWID EQU 0x00052354 +;_HT32FWID EQU 0x00000006 +;_HT32FWID EQU 0x00061352 +;_HT32FWID EQU 0x00032003 +;_HT32FWID EQU 0x00062030 +;_HT32FWID EQU 0x00062040 +;_HT32FWID EQU 0x00062050 +;_HT32FWID EQU 0x00067741 +;_HT32FWID EQU 0x00067232 +;_HT32FWID EQU 0x00067233 + +HT32F52220_30 EQU 1 +HT32F52231_41 EQU 2 +HT32F52331_41 EQU 3 +HT32F52342_52 EQU 4 +HT32F52243_53 EQU 5 +HT32F0008 EQU 6 +HT32F52344_54 EQU 9 +HT32F0006 EQU 10 +HT32F61352 EQU 10 +HT50F32003 EQU 4 +HT32F62030 EQU 1 +HT32F62040 EQU 2 +HT32F62050 EQU 5 +HT32F67741 EQU 2 +HT32F67232 EQU 1 +HT32F67233 EQU 1 + + IF USE_HT32_CHIP_SET=0 + ; Use project's Asm Define setting (default) + ELSE + IF :DEF:USE_HT32_CHIP + ; Use project's Asm Define setting (higher priority than the "USE_HT32_CHIP_SET") + ELSE + ; Use "USE_HT32_CHIP_SET" in the "startup_ht32xxxxx_xx.s" file +USE_HT32_CHIP EQU USE_HT32_CHIP_SET + ENDIF + ENDIF + +; Amount of memory (in bytes) allocated for Stack and Heap +; Tailor those values to your application needs +;// Stack Size (in Bytes, must 8 byte aligned) <0-16384:8> +Stack_Size EQU 512 + + AREA STACK, NOINIT, READWRITE, ALIGN = 3 +__HT_check_sp +Stack_Mem SPACE Stack_Size +__initial_sp + +;// Heap Size (in Bytes) <0-16384:8> +Heap_Size EQU 0 + + AREA HEAP, NOINIT, READWRITE, ALIGN = 3 +__HT_check_heap +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + PRESERVE8 + THUMB + +;******************************************************************************* +; Fill-up the Vector Table entries with the exceptions ISR address +;******************************************************************************* + AREA RESET, CODE, READONLY + EXPORT __Vectors +_RESERVED EQU 0xFFFFFFFF +__Vectors + DCD __initial_sp ; ---, 00, 0x000, Top address of Stack + DCD Reset_Handler ; ---, 01, 0x004, Reset Handler + DCD NMI_Handler ; -14, 02, 0x008, NMI Handler + DCD HardFault_Handler ; -13, 03, 0x00C, Hard Fault Handler + DCD _RESERVED ; ---, 04, 0x010, Reserved + DCD _RESERVED ; ---, 05, 0x014, Reserved + DCD _RESERVED ; ---, 06, 0x018, Reserved + DCD _RESERVED ; ---, 07, 0x01C, Reserved + DCD _HT32FWID ; ---, 08, 0x020, Reserved + DCD _RESERVED ; ---, 09, 0x024, Reserved + DCD _RESERVED ; ---, 10, 0x028, Reserved + DCD SVC_Handler ; -05, 11, 0x02C, SVC Handler + DCD _RESERVED ; ---, 12, 0x030, Reserved + DCD _RESERVED ; ---, 13, 0x034, Reserved + DCD PendSV_Handler ; -02, 14, 0x038, PendSV Handler + DCD SysTick_Handler ; -01, 15, 0x03C, SysTick Handler + + ; External Interrupt Handler + DCD LVD_BOD_IRQHandler ; 00, 16, 0x040, + IF (USE_HT32_CHIP=HT32F52220_30) + DCD _RESERVED ; 01, 17, 0x044, + ELSE + DCD RTC_IRQHandler ; 01, 17, 0x044, + ENDIF + DCD FLASH_IRQHandler ; 02, 18, 0x048, + DCD EVWUP_IRQHandler ; 03, 19, 0x04C, + DCD EXTI0_1_IRQHandler ; 04, 20, 0x050, + DCD EXTI2_3_IRQHandler ; 05, 21, 0x054, + DCD EXTI4_15_IRQHandler ; 06, 22, 0x058, + IF (USE_HT32_CHIP=HT32F52342_52) || (USE_HT32_CHIP=HT32F52344_54) + DCD COMP_IRQHandler ; 07, 23, 0x05C, + ELSE + DCD _RESERVED ; 07, 23, 0x05C, + ENDIF + IF (USE_HT32_CHIP=HT32F0008) + DCD _RESERVED ; 08, 24, 0x060, + ELSE + DCD ADC_IRQHandler ; 08, 24, 0x060, + ENDIF + IF (USE_HT32_CHIP=HT32F52243_53) + DCD I2C2_IRQHandler ; 09, 25, 0x064, + ELSE + DCD _RESERVED ; 09, 25, 0x064, + ENDIF + IF (USE_HT32_CHIP=HT32F52220_30) || (USE_HT32_CHIP=HT32F0008) || (USE_HT32_CHIP=HT32F0006) + DCD _RESERVED ; 10, 26, 0x068, + ELSE + DCD MCTM0_IRQHandler ; 10, 26, 0x068, + ENDIF + IF (USE_HT32_CHIP=HT32F52342_52) + DCD GPTM1_IRQHandler ; 11, 27, 0x06C, + ELSE + DCD _RESERVED ; 11, 27, 0x06C, + ENDIF + DCD GPTM0_IRQHandler ; 12, 28, 0x070, + IF (USE_HT32_CHIP=HT32F0008) + DCD _RESERVED ; 13, 29, 0x074, + DCD _RESERVED ; 14, 30, 0x078, + ELSE + DCD SCTM0_IRQHandler ; 13, 29, 0x074, + DCD SCTM1_IRQHandler ; 14, 30, 0x078, + ENDIF + IF (USE_HT32_CHIP=HT32F52231_41) || (USE_HT32_CHIP=HT32F52331_41) || (USE_HT32_CHIP=HT32F52243_53) || (USE_HT32_CHIP=HT32F0006) + DCD SCTM2_IRQHandler ; 15, 31, 0x07C, + DCD SCTM3_IRQHandler ; 16, 32, 0x080, + ENDIF + IF (USE_HT32_CHIP=HT32F0008) + DCD PWM0_IRQHandler ; 15, 31, 0x07C, + DCD PWM1_IRQHandler ; 16, 32, 0x080, + ENDIF + IF (USE_HT32_CHIP=HT32F52220_30) || (USE_HT32_CHIP=HT32F52342_52) || (USE_HT32_CHIP=HT32F52344_54) + DCD _RESERVED ; 15, 31, 0x07C, + DCD _RESERVED ; 16, 32, 0x080, + ENDIF + DCD BFTM0_IRQHandler ; 17, 33, 0x084, + IF (USE_HT32_CHIP=HT32F52220_30) + DCD _RESERVED ; 18, 34, 0x088, + ELSE + DCD BFTM1_IRQHandler ; 18, 34, 0x088, + ENDIF + DCD I2C0_IRQHandler ; 19, 35, 0x08C, + IF (USE_HT32_CHIP=HT32F52220_30) || (USE_HT32_CHIP=HT32F0008) || (USE_HT32_CHIP=HT32F52344_54) || (USE_HT32_CHIP=HT32F0006) + DCD _RESERVED ; 20, 36, 0x090, + ELSE + DCD I2C1_IRQHandler ; 20, 36, 0x090, + ENDIF + DCD SPI0_IRQHandler ; 21, 37, 0x094, + IF (USE_HT32_CHIP=HT32F52220_30) || (USE_HT32_CHIP=HT32F0008) + DCD _RESERVED ; 22, 38, 0x098, + ELSE + IF (USE_HT32_CHIP=HT32F0006) + DCD QSPI_IRQHandler ; 22, 38, 0x098, + ELSE + DCD SPI1_IRQHandler ; 22, 38, 0x098, + ENDIF + ENDIF + IF (USE_HT32_CHIP=HT32F52344_54) + DCD _RESERVED ; 23, 39, 0x09C, + ELSE + DCD USART0_IRQHandler ; 23, 39, 0x09C, + ENDIF + IF (USE_HT32_CHIP=HT32F52342_52) || (USE_HT32_CHIP=HT32F52243_53) + DCD USART1_IRQHandler ; 24, 40, 0x0A0, + ELSE + DCD _RESERVED ; 24, 40, 0x0A0, + ENDIF + DCD UART0_IRQHandler ; 25, 41, 0x0A4, + IF (USE_HT32_CHIP=HT32F52220_30) || (USE_HT32_CHIP=HT32F0008) || (USE_HT32_CHIP=HT32F0006) + DCD _RESERVED ; 26, 42, 0x0A8, + ELSE + DCD UART1_IRQHandler ; 26, 42, 0x0A8, + ENDIF + IF (USE_HT32_CHIP=HT32F52331_41) || (USE_HT32_CHIP=HT32F52342_52) + DCD SCI_IRQHandler ; 27, 43, 0x0AC, + ENDIF + IF (USE_HT32_CHIP=HT32F52243_53) + DCD UART2_IRQHandler ; 27, 43, 0x0AC, + ENDIF + IF (USE_HT32_CHIP=HT32F0006) + DCD MIDI_IRQHandler ; 27, 43, 0x0AC, + ENDIF + IF (USE_HT32_CHIP=HT32F0008) || (USE_HT32_CHIP=HT32F52344_54) + DCD _RESERVED ; 27, 43, 0xAC, + ENDIF + IF (USE_HT32_CHIP=HT32F52342_52) || (USE_HT32_CHIP=HT32F0006) + DCD I2S_IRQHandler ; 28, 44, 0x0B0, + ENDIF + IF (USE_HT32_CHIP=HT32F52331_41) || (USE_HT32_CHIP=HT32F52344_54) + DCD _RESERVED ; 28, 44, 0x0B0, + ENDIF + IF (USE_HT32_CHIP=HT32F52243_53) + DCD UART3_IRQHandler ; 28, 44, 0x0B0, + ENDIF + IF (USE_HT32_CHIP=HT32F0008) + DCD AES_IRQHandler ; 28, 44, 0x0B0, + ENDIF + IF (USE_HT32_CHIP=HT32F52331_41) || (USE_HT32_CHIP=HT32F52342_52) || (USE_HT32_CHIP=HT32F0008) || (USE_HT32_CHIP=HT32F52344_54) || (USE_HT32_CHIP=HT32F0006) + DCD USB_IRQHandler ; 29, 45, 0x0B4, + ENDIF + IF (USE_HT32_CHIP=HT32F52243_53) + DCD _RESERVED ; 29, 45, 0x0B4, + ENDIF + IF (USE_HT32_CHIP=HT32F52342_52) || (USE_HT32_CHIP=HT32F52243_53) || (USE_HT32_CHIP=HT32F0008) || (USE_HT32_CHIP=HT32F52344_54) || (USE_HT32_CHIP=HT32F0006) + DCD PDMA_CH0_1_IRQHandler ; 30, 46, 0x0B8, + DCD PDMA_CH2_5_IRQHandler ; 31, 47, 0x0BC, + ENDIF + +; Reset handler routine +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + LDR R0, =BootProcess + BLX R0 + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +BootProcess PROC + LDR R0, =0x40080300 + LDR R1,[R0, #0x10] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x14] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x18] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x1C] + CMP R1, #0 + BEQ BP2 +BP1 LDR R0, =0x40080180 + LDR R1,[R0, #0xC] + LSLS R1, R1, #4 + LSRS R1, R1, #20 + CMP R1, #0 + BEQ BP3 + CMP R1, #5 + BEQ BP3 + CMP R1, #6 + BEQ BP3 +BP2 DSB + LDR R0, =0x20000000 + LDR R1, =0x05fa0004 + STR R1, [R0] + LDR R1, =0xe000ed00 + LDR R0, =0x05fa0004 + STR R0, [R1, #0xC] + DSB + B . +BP3 LDR R0, =0x20000000 + LDR R1, [R0] + LDR R0, =0x05fa0004 + CMP R0, R1 + BEQ BP4 + BX LR +BP4 LDR R0, =0x40088100 + LDR R1, =0x00000001 + STR R1, [R0] + LDR R0, =0x20000000 + LDR R1, =0x0 + STR R1, [R0] + BX LR + ENDP + +; Dummy Exception Handlers +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP + +HardFault_Handler PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP + +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP + +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP + +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + EXPORT LVD_BOD_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT EVWUP_IRQHandler [WEAK] + EXPORT EXTI0_1_IRQHandler [WEAK] + EXPORT EXTI2_3_IRQHandler [WEAK] + EXPORT EXTI4_15_IRQHandler [WEAK] + EXPORT COMP_IRQHandler [WEAK] + EXPORT ADC_IRQHandler [WEAK] + EXPORT MCTM0_IRQHandler [WEAK] + EXPORT GPTM1_IRQHandler [WEAK] + EXPORT GPTM0_IRQHandler [WEAK] + EXPORT SCTM0_IRQHandler [WEAK] + EXPORT SCTM1_IRQHandler [WEAK] + EXPORT SCTM2_IRQHandler [WEAK] + EXPORT SCTM3_IRQHandler [WEAK] + EXPORT PWM0_IRQHandler [WEAK] + EXPORT PWM1_IRQHandler [WEAK] + EXPORT BFTM0_IRQHandler [WEAK] + EXPORT BFTM1_IRQHandler [WEAK] + EXPORT I2C0_IRQHandler [WEAK] + EXPORT I2C1_IRQHandler [WEAK] + EXPORT I2C2_IRQHandler [WEAK] + EXPORT SPI0_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT QSPI_IRQHandler [WEAK] + EXPORT USART0_IRQHandler [WEAK] + EXPORT USART1_IRQHandler [WEAK] + EXPORT UART0_IRQHandler [WEAK] + EXPORT UART1_IRQHandler [WEAK] + EXPORT UART2_IRQHandler [WEAK] + EXPORT UART3_IRQHandler [WEAK] + EXPORT SCI_IRQHandler [WEAK] + EXPORT MIDI_IRQHandler [WEAK] + EXPORT I2S_IRQHandler [WEAK] + EXPORT AES_IRQHandler [WEAK] + EXPORT USB_IRQHandler [WEAK] + EXPORT PDMA_CH0_1_IRQHandler [WEAK] + EXPORT PDMA_CH2_5_IRQHandler [WEAK] + +LVD_BOD_IRQHandler +RTC_IRQHandler +FLASH_IRQHandler +EVWUP_IRQHandler +EXTI0_1_IRQHandler +EXTI2_3_IRQHandler +EXTI4_15_IRQHandler +COMP_IRQHandler +ADC_IRQHandler +MCTM0_IRQHandler +GPTM1_IRQHandler +GPTM0_IRQHandler +SCTM0_IRQHandler +SCTM1_IRQHandler +SCTM2_IRQHandler +SCTM3_IRQHandler +PWM0_IRQHandler +PWM1_IRQHandler +BFTM0_IRQHandler +BFTM1_IRQHandler +I2C0_IRQHandler +I2C1_IRQHandler +I2C2_IRQHandler +SPI0_IRQHandler +SPI1_IRQHandler +QSPI_IRQHandler +USART0_IRQHandler +USART1_IRQHandler +UART0_IRQHandler +UART1_IRQHandler +UART2_IRQHandler +UART3_IRQHandler +SCI_IRQHandler +MIDI_IRQHandler +I2S_IRQHandler +AES_IRQHandler +USB_IRQHandler +PDMA_CH0_1_IRQHandler +PDMA_CH2_5_IRQHandler + B . + ENDP + + ALIGN + +;******************************************************************************* +; User Stack and Heap initialization +;******************************************************************************* + IF :DEF:__MICROLIB + + EXPORT __HT_check_heap + EXPORT __HT_check_sp + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, = (Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + + ENDIF + + END diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f62050.s b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f62050.s new file mode 100644 index 0000000000..e9b3a2c194 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f62050.s @@ -0,0 +1,482 @@ +;/*---------------------------------------------------------------------------------------------------------*/ +;/* Holtek Semiconductor Inc. */ +;/* */ +;/* Copyright (C) Holtek Semiconductor Inc. */ +;/* All rights reserved. */ +;/* */ +;/*----------------------------------------------------------------------------------------------------------- +; File Name : startup_ht32f5xxxx_01.s +; Version : $Rev:: 6953 $ +; Date : $Date:: 2023-05-30 #$ +; Description : Startup code. +;-----------------------------------------------------------------------------------------------------------*/ + +; Supported Device +; ======================================== +; HT32F52220, HT32F52230 +; HT32F52231, HT32F52241 +; HT32F52331, HT32F52341 +; HT32F52342, HT32F52352 +; HT32F52243, HT32F52253 +; HT32F0008 +; HT32F52344, HT32F52354 +; HT32F0006 +; HT32F61352 +; HT50F32003 +; HT32F62030, HT32F62040, HT32F62050 +; HT32F67741 +; HT32F67232 +; HT32F67233 + +;/* <<< Use Configuration Wizard in Context Menu >>> */ + +;// HT32 Device +;// Select HT32 Device for the assembly setting. +;// Notice that the project's Asm Define has the higher priority. +;// <0=> By Project Asm Define +;// <1=> HT32F52220/30 +;// <2=> HT32F52231/41 +;// <3=> HT32F52331/41 +;// <4=> HT32F52342/52 +;// <5=> HT32F52243/53 +;// <6=> HT32F0008 +;// <9=> HT32F52344/54 +;// <10=> HT32F0006 +;// <10=> HT32F61352 +;// <4=> HT50F32003 +;// <2=> HT32F67741 +;// <1=> HT32F67232 +;// <1=> HT32F67233 +;// <1=> HT32F62030 +;// <2=> HT32F62040 +;// <5=> HT32F62050 +USE_HT32_CHIP_SET EQU 5 ; Notice that the project's Asm Define has the higher priority. + +_HT32FWID EQU 0xFFFFFFFF +;_HT32FWID EQU 0x00052220 +;_HT32FWID EQU 0x00052230 +;_HT32FWID EQU 0x00052231 +;_HT32FWID EQU 0x00052241 +;_HT32FWID EQU 0x00052331 +;_HT32FWID EQU 0x00052341 +;_HT32FWID EQU 0x00052342 +;_HT32FWID EQU 0x00052352 +;_HT32FWID EQU 0x00052243 +;_HT32FWID EQU 0x00052253 +;_HT32FWID EQU 0x00000008 +;_HT32FWID EQU 0x00052344 +;_HT32FWID EQU 0x00052354 +;_HT32FWID EQU 0x00000006 +;_HT32FWID EQU 0x00061352 +;_HT32FWID EQU 0x00032003 +;_HT32FWID EQU 0x00062030 +;_HT32FWID EQU 0x00062040 +;_HT32FWID EQU 0x00062050 +;_HT32FWID EQU 0x00067741 +;_HT32FWID EQU 0x00067232 +;_HT32FWID EQU 0x00067233 + +HT32F52220_30 EQU 1 +HT32F52231_41 EQU 2 +HT32F52331_41 EQU 3 +HT32F52342_52 EQU 4 +HT32F52243_53 EQU 5 +HT32F0008 EQU 6 +HT32F52344_54 EQU 9 +HT32F0006 EQU 10 +HT32F61352 EQU 10 +HT50F32003 EQU 4 +HT32F62030 EQU 1 +HT32F62040 EQU 2 +HT32F62050 EQU 5 +HT32F67741 EQU 2 +HT32F67232 EQU 1 +HT32F67233 EQU 1 + + IF USE_HT32_CHIP_SET=0 + ; Use project's Asm Define setting (default) + ELSE + IF :DEF:USE_HT32_CHIP + ; Use project's Asm Define setting (higher priority than the "USE_HT32_CHIP_SET") + ELSE + ; Use "USE_HT32_CHIP_SET" in the "startup_ht32xxxxx_xx.s" file +USE_HT32_CHIP EQU USE_HT32_CHIP_SET + ENDIF + ENDIF + +; Amount of memory (in bytes) allocated for Stack and Heap +; Tailor those values to your application needs +;// Stack Size (in Bytes, must 8 byte aligned) <0-16384:8> +Stack_Size EQU 512 + + AREA STACK, NOINIT, READWRITE, ALIGN = 3 +__HT_check_sp +Stack_Mem SPACE Stack_Size +__initial_sp + +;// Heap Size (in Bytes) <0-16384:8> +Heap_Size EQU 0 + + AREA HEAP, NOINIT, READWRITE, ALIGN = 3 +__HT_check_heap +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + PRESERVE8 + THUMB + +;******************************************************************************* +; Fill-up the Vector Table entries with the exceptions ISR address +;******************************************************************************* + AREA RESET, CODE, READONLY + EXPORT __Vectors +_RESERVED EQU 0xFFFFFFFF +__Vectors + DCD __initial_sp ; ---, 00, 0x000, Top address of Stack + DCD Reset_Handler ; ---, 01, 0x004, Reset Handler + DCD NMI_Handler ; -14, 02, 0x008, NMI Handler + DCD HardFault_Handler ; -13, 03, 0x00C, Hard Fault Handler + DCD _RESERVED ; ---, 04, 0x010, Reserved + DCD _RESERVED ; ---, 05, 0x014, Reserved + DCD _RESERVED ; ---, 06, 0x018, Reserved + DCD _RESERVED ; ---, 07, 0x01C, Reserved + DCD _HT32FWID ; ---, 08, 0x020, Reserved + DCD _RESERVED ; ---, 09, 0x024, Reserved + DCD _RESERVED ; ---, 10, 0x028, Reserved + DCD SVC_Handler ; -05, 11, 0x02C, SVC Handler + DCD _RESERVED ; ---, 12, 0x030, Reserved + DCD _RESERVED ; ---, 13, 0x034, Reserved + DCD PendSV_Handler ; -02, 14, 0x038, PendSV Handler + DCD SysTick_Handler ; -01, 15, 0x03C, SysTick Handler + + ; External Interrupt Handler + DCD LVD_BOD_IRQHandler ; 00, 16, 0x040, + IF (USE_HT32_CHIP=HT32F52220_30) + DCD _RESERVED ; 01, 17, 0x044, + ELSE + DCD RTC_IRQHandler ; 01, 17, 0x044, + ENDIF + DCD FLASH_IRQHandler ; 02, 18, 0x048, + DCD EVWUP_IRQHandler ; 03, 19, 0x04C, + DCD EXTI0_1_IRQHandler ; 04, 20, 0x050, + DCD EXTI2_3_IRQHandler ; 05, 21, 0x054, + DCD EXTI4_15_IRQHandler ; 06, 22, 0x058, + IF (USE_HT32_CHIP=HT32F52342_52) || (USE_HT32_CHIP=HT32F52344_54) + DCD COMP_IRQHandler ; 07, 23, 0x05C, + ELSE + DCD _RESERVED ; 07, 23, 0x05C, + ENDIF + IF (USE_HT32_CHIP=HT32F0008) + DCD _RESERVED ; 08, 24, 0x060, + ELSE + DCD ADC_IRQHandler ; 08, 24, 0x060, + ENDIF + IF (USE_HT32_CHIP=HT32F52243_53) + DCD I2C2_IRQHandler ; 09, 25, 0x064, + ELSE + DCD _RESERVED ; 09, 25, 0x064, + ENDIF + IF (USE_HT32_CHIP=HT32F52220_30) || (USE_HT32_CHIP=HT32F0008) || (USE_HT32_CHIP=HT32F0006) + DCD _RESERVED ; 10, 26, 0x068, + ELSE + DCD MCTM0_IRQHandler ; 10, 26, 0x068, + ENDIF + IF (USE_HT32_CHIP=HT32F52342_52) + DCD GPTM1_IRQHandler ; 11, 27, 0x06C, + ELSE + DCD _RESERVED ; 11, 27, 0x06C, + ENDIF + DCD GPTM0_IRQHandler ; 12, 28, 0x070, + IF (USE_HT32_CHIP=HT32F0008) + DCD _RESERVED ; 13, 29, 0x074, + DCD _RESERVED ; 14, 30, 0x078, + ELSE + DCD SCTM0_IRQHandler ; 13, 29, 0x074, + DCD SCTM1_IRQHandler ; 14, 30, 0x078, + ENDIF + IF (USE_HT32_CHIP=HT32F52231_41) || (USE_HT32_CHIP=HT32F52331_41) || (USE_HT32_CHIP=HT32F52243_53) || (USE_HT32_CHIP=HT32F0006) + DCD SCTM2_IRQHandler ; 15, 31, 0x07C, + DCD SCTM3_IRQHandler ; 16, 32, 0x080, + ENDIF + IF (USE_HT32_CHIP=HT32F0008) + DCD PWM0_IRQHandler ; 15, 31, 0x07C, + DCD PWM1_IRQHandler ; 16, 32, 0x080, + ENDIF + IF (USE_HT32_CHIP=HT32F52220_30) || (USE_HT32_CHIP=HT32F52342_52) || (USE_HT32_CHIP=HT32F52344_54) + DCD _RESERVED ; 15, 31, 0x07C, + DCD _RESERVED ; 16, 32, 0x080, + ENDIF + DCD BFTM0_IRQHandler ; 17, 33, 0x084, + IF (USE_HT32_CHIP=HT32F52220_30) + DCD _RESERVED ; 18, 34, 0x088, + ELSE + DCD BFTM1_IRQHandler ; 18, 34, 0x088, + ENDIF + DCD I2C0_IRQHandler ; 19, 35, 0x08C, + IF (USE_HT32_CHIP=HT32F52220_30) || (USE_HT32_CHIP=HT32F0008) || (USE_HT32_CHIP=HT32F52344_54) || (USE_HT32_CHIP=HT32F0006) + DCD _RESERVED ; 20, 36, 0x090, + ELSE + DCD I2C1_IRQHandler ; 20, 36, 0x090, + ENDIF + DCD SPI0_IRQHandler ; 21, 37, 0x094, + IF (USE_HT32_CHIP=HT32F52220_30) || (USE_HT32_CHIP=HT32F0008) + DCD _RESERVED ; 22, 38, 0x098, + ELSE + IF (USE_HT32_CHIP=HT32F0006) + DCD QSPI_IRQHandler ; 22, 38, 0x098, + ELSE + DCD SPI1_IRQHandler ; 22, 38, 0x098, + ENDIF + ENDIF + IF (USE_HT32_CHIP=HT32F52344_54) + DCD _RESERVED ; 23, 39, 0x09C, + ELSE + DCD USART0_IRQHandler ; 23, 39, 0x09C, + ENDIF + IF (USE_HT32_CHIP=HT32F52342_52) || (USE_HT32_CHIP=HT32F52243_53) + DCD USART1_IRQHandler ; 24, 40, 0x0A0, + ELSE + DCD _RESERVED ; 24, 40, 0x0A0, + ENDIF + DCD UART0_IRQHandler ; 25, 41, 0x0A4, + IF (USE_HT32_CHIP=HT32F52220_30) || (USE_HT32_CHIP=HT32F0008) || (USE_HT32_CHIP=HT32F0006) + DCD _RESERVED ; 26, 42, 0x0A8, + ELSE + DCD UART1_IRQHandler ; 26, 42, 0x0A8, + ENDIF + IF (USE_HT32_CHIP=HT32F52331_41) || (USE_HT32_CHIP=HT32F52342_52) + DCD SCI_IRQHandler ; 27, 43, 0x0AC, + ENDIF + IF (USE_HT32_CHIP=HT32F52243_53) + DCD UART2_IRQHandler ; 27, 43, 0x0AC, + ENDIF + IF (USE_HT32_CHIP=HT32F0006) + DCD MIDI_IRQHandler ; 27, 43, 0x0AC, + ENDIF + IF (USE_HT32_CHIP=HT32F0008) || (USE_HT32_CHIP=HT32F52344_54) + DCD _RESERVED ; 27, 43, 0xAC, + ENDIF + IF (USE_HT32_CHIP=HT32F52342_52) || (USE_HT32_CHIP=HT32F0006) + DCD I2S_IRQHandler ; 28, 44, 0x0B0, + ENDIF + IF (USE_HT32_CHIP=HT32F52331_41) || (USE_HT32_CHIP=HT32F52344_54) + DCD _RESERVED ; 28, 44, 0x0B0, + ENDIF + IF (USE_HT32_CHIP=HT32F52243_53) + DCD UART3_IRQHandler ; 28, 44, 0x0B0, + ENDIF + IF (USE_HT32_CHIP=HT32F0008) + DCD AES_IRQHandler ; 28, 44, 0x0B0, + ENDIF + IF (USE_HT32_CHIP=HT32F52331_41) || (USE_HT32_CHIP=HT32F52342_52) || (USE_HT32_CHIP=HT32F0008) || (USE_HT32_CHIP=HT32F52344_54) || (USE_HT32_CHIP=HT32F0006) + DCD USB_IRQHandler ; 29, 45, 0x0B4, + ENDIF + IF (USE_HT32_CHIP=HT32F52243_53) + DCD _RESERVED ; 29, 45, 0x0B4, + ENDIF + IF (USE_HT32_CHIP=HT32F52342_52) || (USE_HT32_CHIP=HT32F52243_53) || (USE_HT32_CHIP=HT32F0008) || (USE_HT32_CHIP=HT32F52344_54) || (USE_HT32_CHIP=HT32F0006) + DCD PDMA_CH0_1_IRQHandler ; 30, 46, 0x0B8, + DCD PDMA_CH2_5_IRQHandler ; 31, 47, 0x0BC, + ENDIF + +; Reset handler routine +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + LDR R0, =BootProcess + BLX R0 + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +BootProcess PROC + LDR R0, =0x40080300 + LDR R1,[R0, #0x10] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x14] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x18] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x1C] + CMP R1, #0 + BEQ BP2 +BP1 LDR R0, =0x40080180 + LDR R1,[R0, #0xC] + LSLS R1, R1, #4 + LSRS R1, R1, #20 + CMP R1, #0 + BEQ BP3 + CMP R1, #5 + BEQ BP3 + CMP R1, #6 + BEQ BP3 +BP2 DSB + LDR R0, =0x20000000 + LDR R1, =0x05fa0004 + STR R1, [R0] + LDR R1, =0xe000ed00 + LDR R0, =0x05fa0004 + STR R0, [R1, #0xC] + DSB + B . +BP3 LDR R0, =0x20000000 + LDR R1, [R0] + LDR R0, =0x05fa0004 + CMP R0, R1 + BEQ BP4 + BX LR +BP4 LDR R0, =0x40088100 + LDR R1, =0x00000001 + STR R1, [R0] + LDR R0, =0x20000000 + LDR R1, =0x0 + STR R1, [R0] + BX LR + ENDP + +; Dummy Exception Handlers +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP + +HardFault_Handler PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP + +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP + +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP + +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + EXPORT LVD_BOD_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT EVWUP_IRQHandler [WEAK] + EXPORT EXTI0_1_IRQHandler [WEAK] + EXPORT EXTI2_3_IRQHandler [WEAK] + EXPORT EXTI4_15_IRQHandler [WEAK] + EXPORT COMP_IRQHandler [WEAK] + EXPORT ADC_IRQHandler [WEAK] + EXPORT MCTM0_IRQHandler [WEAK] + EXPORT GPTM1_IRQHandler [WEAK] + EXPORT GPTM0_IRQHandler [WEAK] + EXPORT SCTM0_IRQHandler [WEAK] + EXPORT SCTM1_IRQHandler [WEAK] + EXPORT SCTM2_IRQHandler [WEAK] + EXPORT SCTM3_IRQHandler [WEAK] + EXPORT PWM0_IRQHandler [WEAK] + EXPORT PWM1_IRQHandler [WEAK] + EXPORT BFTM0_IRQHandler [WEAK] + EXPORT BFTM1_IRQHandler [WEAK] + EXPORT I2C0_IRQHandler [WEAK] + EXPORT I2C1_IRQHandler [WEAK] + EXPORT I2C2_IRQHandler [WEAK] + EXPORT SPI0_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT QSPI_IRQHandler [WEAK] + EXPORT USART0_IRQHandler [WEAK] + EXPORT USART1_IRQHandler [WEAK] + EXPORT UART0_IRQHandler [WEAK] + EXPORT UART1_IRQHandler [WEAK] + EXPORT UART2_IRQHandler [WEAK] + EXPORT UART3_IRQHandler [WEAK] + EXPORT SCI_IRQHandler [WEAK] + EXPORT MIDI_IRQHandler [WEAK] + EXPORT I2S_IRQHandler [WEAK] + EXPORT AES_IRQHandler [WEAK] + EXPORT USB_IRQHandler [WEAK] + EXPORT PDMA_CH0_1_IRQHandler [WEAK] + EXPORT PDMA_CH2_5_IRQHandler [WEAK] + +LVD_BOD_IRQHandler +RTC_IRQHandler +FLASH_IRQHandler +EVWUP_IRQHandler +EXTI0_1_IRQHandler +EXTI2_3_IRQHandler +EXTI4_15_IRQHandler +COMP_IRQHandler +ADC_IRQHandler +MCTM0_IRQHandler +GPTM1_IRQHandler +GPTM0_IRQHandler +SCTM0_IRQHandler +SCTM1_IRQHandler +SCTM2_IRQHandler +SCTM3_IRQHandler +PWM0_IRQHandler +PWM1_IRQHandler +BFTM0_IRQHandler +BFTM1_IRQHandler +I2C0_IRQHandler +I2C1_IRQHandler +I2C2_IRQHandler +SPI0_IRQHandler +SPI1_IRQHandler +QSPI_IRQHandler +USART0_IRQHandler +USART1_IRQHandler +UART0_IRQHandler +UART1_IRQHandler +UART2_IRQHandler +UART3_IRQHandler +SCI_IRQHandler +MIDI_IRQHandler +I2S_IRQHandler +AES_IRQHandler +USB_IRQHandler +PDMA_CH0_1_IRQHandler +PDMA_CH2_5_IRQHandler + B . + ENDP + + ALIGN + +;******************************************************************************* +; User Stack and Heap initialization +;******************************************************************************* + IF :DEF:__MICROLIB + + EXPORT __HT_check_heap + EXPORT __HT_check_sp + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, = (Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + + ENDIF + + END diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f65230_40.s b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f65230_40.s new file mode 100644 index 0000000000..b986536809 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f65230_40.s @@ -0,0 +1,278 @@ +;/*---------------------------------------------------------------------------------------------------------*/ +;/* Holtek Semiconductor Inc. */ +;/* */ +;/* Copyright (C) Holtek Semiconductor Inc. */ +;/* All rights reserved. */ +;/* */ +;/*----------------------------------------------------------------------------------------------------------- +; File Name : startup_ht32f5xxxx_08.s +; Version : $Rev:: 6877 $ +; Date : $Date:: 2023-05-04 #$ +; Description : Startup code. +;-----------------------------------------------------------------------------------------------------------*/ + +; Supported Device +; ======================================== +; HT32F65230, HT32F65240 +; HT32F65232 +; MXTX6306 +; HT50F3200S + +;/* <<< Use Configuration Wizard in Context Menu >>> */ + +;// HT32 Device +;// Select HT32 Device for the assembly setting. +;// Notice that the project's Asm Define has the higher priority. +;// <0=> By Project Asm Define +;// <12=> HT32F65230_40 +;// <18=> HT32F65232 +;// <12=> MXTX6306 +;// <12=> HT50F3200S +USE_HT32_CHIP_SET EQU 12 ; Notice that the project's Asm Define has the higher priority. + +_HT32FWID EQU 0xFFFFFFFF +;_HT32FWID EQU 0x00065230 +;_HT32FWID EQU 0x00065240 +;_HT32FWID EQU 0x00065232 +;_HT32FWID EQU 0x00006306 +;_HT32FWID EQU 0x0003200F + +HT32F65230_40 EQU 12 +HT32F65232 EQU 18 +MXTX6306 EQU 12 +HT50F3200S EQU 12 + + IF USE_HT32_CHIP_SET=0 + ; Use project's Asm Define setting (default) + ELSE + IF :DEF:USE_HT32_CHIP + ; Use project's Asm Define setting (higher priority than the "USE_HT32_CHIP_SET") + ELSE + ; Use "USE_HT32_CHIP_SET" in the "startup_ht32xxxxx_xx.s" file +USE_HT32_CHIP EQU USE_HT32_CHIP_SET + ENDIF + ENDIF + +; Amount of memory (in bytes) allocated for Stack and Heap +; Tailor those values to your application needs +;// Stack Size (in Bytes, must 8 byte aligned) <0-8192:8> +Stack_Size EQU 512 + + AREA STACK, NOINIT, READWRITE, ALIGN = 3 +__HT_check_sp +Stack_Mem SPACE Stack_Size +__initial_sp + +;// Heap Size (in Bytes) <0-8192:8> +Heap_Size EQU 0 + + AREA HEAP, NOINIT, READWRITE, ALIGN = 3 +__HT_check_heap +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + PRESERVE8 + THUMB + +;******************************************************************************* +; Fill-up the Vector Table entries with the exceptions ISR address +;******************************************************************************* + AREA RESET, CODE, READONLY + EXPORT __Vectors +_RESERVED EQU 0xFFFFFFFF +__Vectors + DCD __initial_sp ; ---, 00, 0x000, Top address of Stack + DCD Reset_Handler ; ---, 01, 0x004, Reset Handler + DCD NMI_Handler ; -14, 02, 0x008, NMI Handler + DCD HardFault_Handler ; -13, 03, 0x00C, Hard Fault Handler + DCD _RESERVED ; ---, 04, 0x010, Reserved + DCD _RESERVED ; ---, 05, 0x014, Reserved + DCD _RESERVED ; ---, 06, 0x018, Reserved + DCD _RESERVED ; ---, 07, 0x01C, Reserved + DCD _HT32FWID ; ---, 08, 0x020, Reserved + DCD _RESERVED ; ---, 09, 0x024, Reserved + DCD _RESERVED ; ---, 10, 0x028, Reserved + DCD SVC_Handler ; -05, 11, 0x02C, SVC Handler + DCD _RESERVED ; ---, 12, 0x030, Reserved + DCD _RESERVED ; ---, 13, 0x034, Reserved + DCD PendSV_Handler ; -02, 14, 0x038, PendSV Handler + DCD SysTick_Handler ; -01, 15, 0x03C, SysTick Handler + + ; External Interrupt Handler + DCD LVD_BOD_IRQHandler ; 00, 16, 0x040, + DCD RTC_IRQHandler ; 01, 17, 0x044, + DCD FLASH_IRQHandler ; 02, 18, 0x048, + DCD EVWUP_IRQHandler ; 03, 19, 0x04C, + DCD EXTI0_1_IRQHandler ; 04, 20, 0x050, + DCD EXTI2_3_IRQHandler ; 05, 21, 0x054, + DCD EXTI4_9_IRQHandler ; 06, 22, 0x058, + DCD EXTI10_15_IRQHandler ; 07, 23, 0x05C, + DCD ADC0_IRQHandler ; 08, 24, 0x060, + IF (USE_HT32_CHIP=HT32F65230_40) + DCD ADC1_IRQHandler ; 09, 25, 0x064, + ELSE + DCD _RESERVED ; 09, 25, 0x064, + ENDIF + DCD MCTM0_BRK_IRQHandler ; 10, 26, 0x068, + DCD MCTM0_UP_IRQHandler ; 11, 27, 0x06C, + DCD MCTM0_TR_UP2_IRQHandler ; 12, 28, 0x070, + DCD MCTM0_CC_IRQHandler ; 13, 29, 0x074, + DCD GPTM0_G_IRQHandler ; 14, 30, 0x078, + DCD GPTM0_VCLK_IRQHandler ; 15, 31, 0x07C, + DCD BFTM0_IRQHandler ; 16, 32, 0x080, + DCD BFTM1_IRQHandler ; 17, 33, 0x084, + DCD CMP0_IRQHandler ; 18, 34, 0x088, + DCD CMP1_IRQHandler ; 19, 35, 0x08C, + IF (USE_HT32_CHIP=HT32F65230_40) + DCD CMP2_IRQHandler ; 20, 36, 0x090, + ELSE + DCD _RESERVED ; 20, 36, 0x090, + ENDIF + DCD I2C0_IRQHandler ; 21, 37, 0x094, + DCD SPI0_IRQHandler ; 22, 38, 0x098, + DCD USART0_IRQHandler ; 23, 39, 0x09C, + DCD UART0_IRQHandler ; 24, 40, 0x0A0, + DCD PDMA_CH0_1_IRQHandler ; 25, 41, 0x0A4, + DCD PDMA_CH2_3_IRQHandler ; 26, 42, 0x0A8, + DCD PDMA_CH4_5_IRQHandler ; 27, 43, 0x0AC, + DCD SCTM0_IRQHandler ; 28, 44, 0x0B0, + DCD SCTM1_IRQHandler ; 29, 45, 0x0B4, + DCD SCTM2_IRQHandler ; 30, 46, 0x0B8, + DCD SCTM3_IRQHandler ; 31, 47, 0x0BC, + +; Reset handler routine +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception Handlers +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP + +HardFault_Handler PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP + +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP + +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP + +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + EXPORT LVD_BOD_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT EVWUP_IRQHandler [WEAK] + EXPORT EXTI0_1_IRQHandler [WEAK] + EXPORT EXTI2_3_IRQHandler [WEAK] + EXPORT EXTI4_9_IRQHandler [WEAK] + EXPORT EXTI10_15_IRQHandler [WEAK] + EXPORT ADC0_IRQHandler [WEAK] + EXPORT ADC1_IRQHandler [WEAK] + EXPORT MCTM0_BRK_IRQHandler [WEAK] + EXPORT MCTM0_UP_IRQHandler [WEAK] + EXPORT MCTM0_TR_UP2_IRQHandler [WEAK] + EXPORT MCTM0_CC_IRQHandler [WEAK] + EXPORT GPTM0_G_IRQHandler [WEAK] + EXPORT GPTM0_VCLK_IRQHandler [WEAK] + EXPORT BFTM0_IRQHandler [WEAK] + EXPORT BFTM1_IRQHandler [WEAK] + EXPORT CMP0_IRQHandler [WEAK] + EXPORT CMP1_IRQHandler [WEAK] + EXPORT CMP2_IRQHandler [WEAK] + EXPORT I2C0_IRQHandler [WEAK] + EXPORT SPI0_IRQHandler [WEAK] + EXPORT USART0_IRQHandler [WEAK] + EXPORT UART0_IRQHandler [WEAK] + EXPORT PDMA_CH0_1_IRQHandler [WEAK] + EXPORT PDMA_CH2_3_IRQHandler [WEAK] + EXPORT PDMA_CH4_5_IRQHandler [WEAK] + EXPORT SCTM0_IRQHandler [WEAK] + EXPORT SCTM1_IRQHandler [WEAK] + EXPORT SCTM2_IRQHandler [WEAK] + EXPORT SCTM3_IRQHandler [WEAK] +LVD_BOD_IRQHandler +RTC_IRQHandler +FLASH_IRQHandler +EVWUP_IRQHandler +EXTI0_1_IRQHandler +EXTI2_3_IRQHandler +EXTI4_9_IRQHandler +EXTI10_15_IRQHandler +ADC0_IRQHandler +ADC1_IRQHandler +MCTM0_BRK_IRQHandler +MCTM0_UP_IRQHandler +MCTM0_TR_UP2_IRQHandler +MCTM0_CC_IRQHandler +GPTM0_G_IRQHandler +GPTM0_VCLK_IRQHandler +BFTM0_IRQHandler +BFTM1_IRQHandler +CMP0_IRQHandler +CMP1_IRQHandler +CMP2_IRQHandler +I2C0_IRQHandler +SPI0_IRQHandler +USART0_IRQHandler +UART0_IRQHandler +PDMA_CH0_1_IRQHandler +PDMA_CH2_3_IRQHandler +PDMA_CH4_5_IRQHandler +SCTM0_IRQHandler +SCTM1_IRQHandler +SCTM2_IRQHandler +SCTM3_IRQHandler + B . + ENDP + + ALIGN + +;******************************************************************************* +; User Stack and Heap initialization +;******************************************************************************* + IF :DEF:__MICROLIB + + EXPORT __HT_check_heap + EXPORT __HT_check_sp + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, = (Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + + ENDIF + + END diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f65232.s b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f65232.s new file mode 100644 index 0000000000..0ec4ece850 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f65232.s @@ -0,0 +1,278 @@ +;/*---------------------------------------------------------------------------------------------------------*/ +;/* Holtek Semiconductor Inc. */ +;/* */ +;/* Copyright (C) Holtek Semiconductor Inc. */ +;/* All rights reserved. */ +;/* */ +;/*----------------------------------------------------------------------------------------------------------- +; File Name : startup_ht32f5xxxx_08.s +; Version : $Rev:: 6877 $ +; Date : $Date:: 2023-05-04 #$ +; Description : Startup code. +;-----------------------------------------------------------------------------------------------------------*/ + +; Supported Device +; ======================================== +; HT32F65230, HT32F65240 +; HT32F65232 +; MXTX6306 +; HT50F3200S + +;/* <<< Use Configuration Wizard in Context Menu >>> */ + +;// HT32 Device +;// Select HT32 Device for the assembly setting. +;// Notice that the project's Asm Define has the higher priority. +;// <0=> By Project Asm Define +;// <12=> HT32F65230_40 +;// <18=> HT32F65232 +;// <12=> MXTX6306 +;// <12=> HT50F3200S +USE_HT32_CHIP_SET EQU 18 ; Notice that the project's Asm Define has the higher priority. + +_HT32FWID EQU 0xFFFFFFFF +;_HT32FWID EQU 0x00065230 +;_HT32FWID EQU 0x00065240 +;_HT32FWID EQU 0x00065232 +;_HT32FWID EQU 0x00006306 +;_HT32FWID EQU 0x0003200F + +HT32F65230_40 EQU 12 +HT32F65232 EQU 18 +MXTX6306 EQU 12 +HT50F3200S EQU 12 + + IF USE_HT32_CHIP_SET=0 + ; Use project's Asm Define setting (default) + ELSE + IF :DEF:USE_HT32_CHIP + ; Use project's Asm Define setting (higher priority than the "USE_HT32_CHIP_SET") + ELSE + ; Use "USE_HT32_CHIP_SET" in the "startup_ht32xxxxx_xx.s" file +USE_HT32_CHIP EQU USE_HT32_CHIP_SET + ENDIF + ENDIF + +; Amount of memory (in bytes) allocated for Stack and Heap +; Tailor those values to your application needs +;// Stack Size (in Bytes, must 8 byte aligned) <0-8192:8> +Stack_Size EQU 512 + + AREA STACK, NOINIT, READWRITE, ALIGN = 3 +__HT_check_sp +Stack_Mem SPACE Stack_Size +__initial_sp + +;// Heap Size (in Bytes) <0-8192:8> +Heap_Size EQU 0 + + AREA HEAP, NOINIT, READWRITE, ALIGN = 3 +__HT_check_heap +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + PRESERVE8 + THUMB + +;******************************************************************************* +; Fill-up the Vector Table entries with the exceptions ISR address +;******************************************************************************* + AREA RESET, CODE, READONLY + EXPORT __Vectors +_RESERVED EQU 0xFFFFFFFF +__Vectors + DCD __initial_sp ; ---, 00, 0x000, Top address of Stack + DCD Reset_Handler ; ---, 01, 0x004, Reset Handler + DCD NMI_Handler ; -14, 02, 0x008, NMI Handler + DCD HardFault_Handler ; -13, 03, 0x00C, Hard Fault Handler + DCD _RESERVED ; ---, 04, 0x010, Reserved + DCD _RESERVED ; ---, 05, 0x014, Reserved + DCD _RESERVED ; ---, 06, 0x018, Reserved + DCD _RESERVED ; ---, 07, 0x01C, Reserved + DCD _HT32FWID ; ---, 08, 0x020, Reserved + DCD _RESERVED ; ---, 09, 0x024, Reserved + DCD _RESERVED ; ---, 10, 0x028, Reserved + DCD SVC_Handler ; -05, 11, 0x02C, SVC Handler + DCD _RESERVED ; ---, 12, 0x030, Reserved + DCD _RESERVED ; ---, 13, 0x034, Reserved + DCD PendSV_Handler ; -02, 14, 0x038, PendSV Handler + DCD SysTick_Handler ; -01, 15, 0x03C, SysTick Handler + + ; External Interrupt Handler + DCD LVD_BOD_IRQHandler ; 00, 16, 0x040, + DCD RTC_IRQHandler ; 01, 17, 0x044, + DCD FLASH_IRQHandler ; 02, 18, 0x048, + DCD EVWUP_IRQHandler ; 03, 19, 0x04C, + DCD EXTI0_1_IRQHandler ; 04, 20, 0x050, + DCD EXTI2_3_IRQHandler ; 05, 21, 0x054, + DCD EXTI4_9_IRQHandler ; 06, 22, 0x058, + DCD EXTI10_15_IRQHandler ; 07, 23, 0x05C, + DCD ADC0_IRQHandler ; 08, 24, 0x060, + IF (USE_HT32_CHIP=HT32F65230_40) + DCD ADC1_IRQHandler ; 09, 25, 0x064, + ELSE + DCD _RESERVED ; 09, 25, 0x064, + ENDIF + DCD MCTM0_BRK_IRQHandler ; 10, 26, 0x068, + DCD MCTM0_UP_IRQHandler ; 11, 27, 0x06C, + DCD MCTM0_TR_UP2_IRQHandler ; 12, 28, 0x070, + DCD MCTM0_CC_IRQHandler ; 13, 29, 0x074, + DCD GPTM0_G_IRQHandler ; 14, 30, 0x078, + DCD GPTM0_VCLK_IRQHandler ; 15, 31, 0x07C, + DCD BFTM0_IRQHandler ; 16, 32, 0x080, + DCD BFTM1_IRQHandler ; 17, 33, 0x084, + DCD CMP0_IRQHandler ; 18, 34, 0x088, + DCD CMP1_IRQHandler ; 19, 35, 0x08C, + IF (USE_HT32_CHIP=HT32F65230_40) + DCD CMP2_IRQHandler ; 20, 36, 0x090, + ELSE + DCD _RESERVED ; 20, 36, 0x090, + ENDIF + DCD I2C0_IRQHandler ; 21, 37, 0x094, + DCD SPI0_IRQHandler ; 22, 38, 0x098, + DCD USART0_IRQHandler ; 23, 39, 0x09C, + DCD UART0_IRQHandler ; 24, 40, 0x0A0, + DCD PDMA_CH0_1_IRQHandler ; 25, 41, 0x0A4, + DCD PDMA_CH2_3_IRQHandler ; 26, 42, 0x0A8, + DCD PDMA_CH4_5_IRQHandler ; 27, 43, 0x0AC, + DCD SCTM0_IRQHandler ; 28, 44, 0x0B0, + DCD SCTM1_IRQHandler ; 29, 45, 0x0B4, + DCD SCTM2_IRQHandler ; 30, 46, 0x0B8, + DCD SCTM3_IRQHandler ; 31, 47, 0x0BC, + +; Reset handler routine +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception Handlers +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP + +HardFault_Handler PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP + +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP + +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP + +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + EXPORT LVD_BOD_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT EVWUP_IRQHandler [WEAK] + EXPORT EXTI0_1_IRQHandler [WEAK] + EXPORT EXTI2_3_IRQHandler [WEAK] + EXPORT EXTI4_9_IRQHandler [WEAK] + EXPORT EXTI10_15_IRQHandler [WEAK] + EXPORT ADC0_IRQHandler [WEAK] + EXPORT ADC1_IRQHandler [WEAK] + EXPORT MCTM0_BRK_IRQHandler [WEAK] + EXPORT MCTM0_UP_IRQHandler [WEAK] + EXPORT MCTM0_TR_UP2_IRQHandler [WEAK] + EXPORT MCTM0_CC_IRQHandler [WEAK] + EXPORT GPTM0_G_IRQHandler [WEAK] + EXPORT GPTM0_VCLK_IRQHandler [WEAK] + EXPORT BFTM0_IRQHandler [WEAK] + EXPORT BFTM1_IRQHandler [WEAK] + EXPORT CMP0_IRQHandler [WEAK] + EXPORT CMP1_IRQHandler [WEAK] + EXPORT CMP2_IRQHandler [WEAK] + EXPORT I2C0_IRQHandler [WEAK] + EXPORT SPI0_IRQHandler [WEAK] + EXPORT USART0_IRQHandler [WEAK] + EXPORT UART0_IRQHandler [WEAK] + EXPORT PDMA_CH0_1_IRQHandler [WEAK] + EXPORT PDMA_CH2_3_IRQHandler [WEAK] + EXPORT PDMA_CH4_5_IRQHandler [WEAK] + EXPORT SCTM0_IRQHandler [WEAK] + EXPORT SCTM1_IRQHandler [WEAK] + EXPORT SCTM2_IRQHandler [WEAK] + EXPORT SCTM3_IRQHandler [WEAK] +LVD_BOD_IRQHandler +RTC_IRQHandler +FLASH_IRQHandler +EVWUP_IRQHandler +EXTI0_1_IRQHandler +EXTI2_3_IRQHandler +EXTI4_9_IRQHandler +EXTI10_15_IRQHandler +ADC0_IRQHandler +ADC1_IRQHandler +MCTM0_BRK_IRQHandler +MCTM0_UP_IRQHandler +MCTM0_TR_UP2_IRQHandler +MCTM0_CC_IRQHandler +GPTM0_G_IRQHandler +GPTM0_VCLK_IRQHandler +BFTM0_IRQHandler +BFTM1_IRQHandler +CMP0_IRQHandler +CMP1_IRQHandler +CMP2_IRQHandler +I2C0_IRQHandler +SPI0_IRQHandler +USART0_IRQHandler +UART0_IRQHandler +PDMA_CH0_1_IRQHandler +PDMA_CH2_3_IRQHandler +PDMA_CH4_5_IRQHandler +SCTM0_IRQHandler +SCTM1_IRQHandler +SCTM2_IRQHandler +SCTM3_IRQHandler + B . + ENDP + + ALIGN + +;******************************************************************************* +; User Stack and Heap initialization +;******************************************************************************* + IF :DEF:__MICROLIB + + EXPORT __HT_check_heap + EXPORT __HT_check_sp + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, = (Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + + ENDIF + + END diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f66242.s b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f66242.s new file mode 100644 index 0000000000..d2f753c115 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f66242.s @@ -0,0 +1,275 @@ +;/*---------------------------------------------------------------------------------------------------------*/ +;/* Holtek Semiconductor Inc. */ +;/* */ +;/* Copyright (C) Holtek Semiconductor Inc. */ +;/* All rights reserved. */ +;/* */ +;/*----------------------------------------------------------------------------------------------------------- +; File Name : startup_ht32f5xxxx_16.s +; Version : $Rev:: 7092 $ +; Date : $Date:: 2023-08-02 #$ +; Description : Startup code. +;-----------------------------------------------------------------------------------------------------------*/ + +; Supported Device +; ======================================== +; HT32F66242 +; HT32F66246 + +;/* <<< Use Configuration Wizard in Context Menu >>> */ + + + + + + + +USE_HT32_CHIP_SET EQU 33 ; Notice that the project's Asm Define has the higher priority. + +;_HT32FWID EQU 0xFFFFFFFF +;_HT32FWID EQU 0x00066246 + +HT32F66246 EQU 31 +HT32F66242 EQU 33 + + IF USE_HT32_CHIP_SET=0 + ; Use project's Asm Define setting (default) + ELSE + IF :DEF:USE_HT32_CHIP + ; Use project's Asm Define setting (higher priority than the "USE_HT32_CHIP_SET") + ELSE + ; Use "USE_HT32_CHIP_SET" in the "startup_ht32xxxxx_xx.s" file +USE_HT32_CHIP EQU USE_HT32_CHIP_SET + ENDIF + ENDIF + + IF (USE_HT32_CHIP=0) +_HT32FWID EQU 0x00066246 + ENDIF + IF (USE_HT32_CHIP=HT32F66246) +_HT32FWID EQU 0x00066246 + ENDIF + IF (USE_HT32_CHIP=HT32F66242) +_HT32FWID EQU 0x00066242 + ENDIF + +; Amount of memory (in bytes) allocated for Stack and Heap +; Tailor those values to your application needs +;// Stack Size (in Bytes, must 8 byte aligned) <0-8192:8> +Stack_Size EQU 512 + + AREA STACK, NOINIT, READWRITE, ALIGN = 3 +__HT_check_sp +Stack_Mem SPACE Stack_Size +__initial_sp + +;// Heap Size (in Bytes) <0-8192:8> +Heap_Size EQU 0 + + AREA HEAP, NOINIT, READWRITE, ALIGN = 3 +__HT_check_heap +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + PRESERVE8 + THUMB + +;******************************************************************************* +; Fill-up the Vector Table entries with the exceptions ISR address +;******************************************************************************* + AREA RESET, CODE, READONLY + EXPORT __Vectors +_RESERVED EQU 0xFFFFFFFF +__Vectors + DCD __initial_sp ; ---, 00, 0x000, Top address of Stack + DCD Reset_Handler ; ---, 01, 0x004, Reset Handler + DCD NMI_Handler ; -14, 02, 0x008, NMI Handler + DCD HardFault_Handler ; -13, 03, 0x00C, Hard Fault Handler + DCD _RESERVED ; ---, 04, 0x010, Reserved + DCD _RESERVED ; ---, 05, 0x014, Reserved + DCD _RESERVED ; ---, 06, 0x018, Reserved + DCD _RESERVED ; ---, 07, 0x01C, Reserved + DCD _HT32FWID ; ---, 08, 0x020, Reserved + DCD _RESERVED ; ---, 09, 0x024, Reserved + DCD _RESERVED ; ---, 10, 0x028, Reserved + DCD SVC_Handler ; -05, 11, 0x02C, SVC Handler + DCD _RESERVED ; ---, 12, 0x030, Reserved + DCD _RESERVED ; ---, 13, 0x034, Reserved + DCD PendSV_Handler ; -02, 14, 0x038, PendSV Handler + DCD SysTick_Handler ; -01, 15, 0x03C, SysTick Handler + + ; External Interrupt Handler + DCD LVD_BOD_IRQHandler ; 00, 16, 0x040, + DCD RTC_IRQHandler ; 01, 17, 0x044, + DCD FLASH_IRQHandler ; 02, 18, 0x048, + DCD EVWUP_IRQHandler ; 03, 19, 0x04C, + DCD EXTI0_1_IRQHandler ; 04, 20, 0x050, + DCD EXTI2_3_IRQHandler ; 05, 21, 0x054, + DCD EXTI4_15_IRQHandler ; 06, 22, 0x058, + IF (USE_HT32_CHIP=HT32F66246) + DCD CAN0_IRQHandler ; 07, 23, 0x05C, + ELSE + DCD _RESERVED ; 07, 23, 0x05C, + ENDIF + DCD ADC_IRQHandler ; 08, 24, 0x060, + DCD CORDIC_IRQHandler ; 09, 25, 0x064, + DCD MCTM0_BRK_IRQHandler ; 10, 26, 0x068, + DCD MCTM0_UP_IRQHandler ; 11, 27, 0x06C, + DCD MCTM0_TR_UP2_IRQHandler ; 12, 28, 0x070, + DCD MCTM0_CC_IRQHandler ; 13, 29, 0x074, + DCD GPTM0_G_IRQHandler ; 14, 30, 0x078, + DCD GPTM0_VCLK_IRQHandler ; 15, 31, 0x07C, + DCD BFTM0_IRQHandler ; 16, 32, 0x080, + DCD BFTM1_IRQHandler ; 17, 33, 0x084, + DCD CMP0_IRQHandler ; 18, 34, 0x088, + DCD CMP1_IRQHandler ; 19, 35, 0x08C, + DCD PID_IRQHandler ; 20, 36, 0x090, + DCD I2C0_IRQHandler ; 21, 37, 0x094, + DCD SPI0_IRQHandler ; 22, 38, 0x098, + DCD USART0_IRQHandler ; 23, 39, 0x09C, + DCD UART0_IRQHandler ; 24, 40, 0x0A0, + DCD PDMA_CH0_1_IRQHandler ; 25, 41, 0x0A4, + DCD PDMA_CH2_3_IRQHandler ; 26, 42, 0x0A8, + DCD PDMA_CH4_5_IRQHandler ; 27, 43, 0x0AC, + DCD SCTM0_IRQHandler ; 28, 44, 0x0B0, + DCD SCTM1_IRQHandler ; 29, 45, 0x0B4, + DCD SCTM2_IRQHandler ; 30, 46, 0x0B8, + DCD SCTM3_IRQHandler ; 31, 47, 0x0BC, + +; Reset handler routine +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception Handlers +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP + +HardFault_Handler PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP + +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP + +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP + +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + EXPORT LVD_BOD_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT EVWUP_IRQHandler [WEAK] + EXPORT EXTI0_1_IRQHandler [WEAK] + EXPORT EXTI2_3_IRQHandler [WEAK] + EXPORT EXTI4_15_IRQHandler [WEAK] + EXPORT CAN0_IRQHandler [WEAK] + EXPORT ADC_IRQHandler [WEAK] + EXPORT CORDIC_IRQHandler [WEAK] + EXPORT MCTM0_BRK_IRQHandler [WEAK] + EXPORT MCTM0_UP_IRQHandler [WEAK] + EXPORT MCTM0_TR_UP2_IRQHandler [WEAK] + EXPORT MCTM0_CC_IRQHandler [WEAK] + EXPORT GPTM0_G_IRQHandler [WEAK] + EXPORT GPTM0_VCLK_IRQHandler [WEAK] + EXPORT BFTM0_IRQHandler [WEAK] + EXPORT BFTM1_IRQHandler [WEAK] + EXPORT CMP0_IRQHandler [WEAK] + EXPORT CMP1_IRQHandler [WEAK] + EXPORT PID_IRQHandler [WEAK] + EXPORT I2C0_IRQHandler [WEAK] + EXPORT SPI0_IRQHandler [WEAK] + EXPORT USART0_IRQHandler [WEAK] + EXPORT UART0_IRQHandler [WEAK] + EXPORT PDMA_CH0_1_IRQHandler [WEAK] + EXPORT PDMA_CH2_3_IRQHandler [WEAK] + EXPORT PDMA_CH4_5_IRQHandler [WEAK] + EXPORT SCTM0_IRQHandler [WEAK] + EXPORT SCTM1_IRQHandler [WEAK] + EXPORT SCTM2_IRQHandler [WEAK] + EXPORT SCTM3_IRQHandler [WEAK] + +LVD_BOD_IRQHandler +RTC_IRQHandler +FLASH_IRQHandler +EVWUP_IRQHandler +EXTI0_1_IRQHandler +EXTI2_3_IRQHandler +EXTI4_15_IRQHandler +CAN0_IRQHandler +ADC_IRQHandler +CORDIC_IRQHandler +MCTM0_BRK_IRQHandler +MCTM0_UP_IRQHandler +MCTM0_TR_UP2_IRQHandler +MCTM0_CC_IRQHandler +GPTM0_G_IRQHandler +GPTM0_VCLK_IRQHandler +BFTM0_IRQHandler +BFTM1_IRQHandler +CMP0_IRQHandler +CMP1_IRQHandler +PID_IRQHandler +I2C0_IRQHandler +SPI0_IRQHandler +USART0_IRQHandler +UART0_IRQHandler +PDMA_CH0_1_IRQHandler +PDMA_CH2_3_IRQHandler +PDMA_CH4_5_IRQHandler +SCTM0_IRQHandler +SCTM1_IRQHandler +SCTM2_IRQHandler +SCTM3_IRQHandler + B . + ENDP + + ALIGN + +;******************************************************************************* +; User Stack and Heap initialization +;******************************************************************************* + IF :DEF:__MICROLIB + + EXPORT __HT_check_heap + EXPORT __HT_check_sp + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, = (Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + + ENDIF + + END diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f66246.s b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f66246.s new file mode 100644 index 0000000000..9a02335cc6 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f66246.s @@ -0,0 +1,275 @@ +;/*---------------------------------------------------------------------------------------------------------*/ +;/* Holtek Semiconductor Inc. */ +;/* */ +;/* Copyright (C) Holtek Semiconductor Inc. */ +;/* All rights reserved. */ +;/* */ +;/*----------------------------------------------------------------------------------------------------------- +; File Name : startup_ht32f5xxxx_16.s +; Version : $Rev:: 7092 $ +; Date : $Date:: 2023-08-02 #$ +; Description : Startup code. +;-----------------------------------------------------------------------------------------------------------*/ + +; Supported Device +; ======================================== +; HT32F66242 +; HT32F66246 + +;/* <<< Use Configuration Wizard in Context Menu >>> */ + + + + + + + +USE_HT32_CHIP_SET EQU 31 ; Notice that the project's Asm Define has the higher priority. + +;_HT32FWID EQU 0xFFFFFFFF +;_HT32FWID EQU 0x00066246 + +HT32F66246 EQU 31 +HT32F66242 EQU 33 + + IF USE_HT32_CHIP_SET=0 + ; Use project's Asm Define setting (default) + ELSE + IF :DEF:USE_HT32_CHIP + ; Use project's Asm Define setting (higher priority than the "USE_HT32_CHIP_SET") + ELSE + ; Use "USE_HT32_CHIP_SET" in the "startup_ht32xxxxx_xx.s" file +USE_HT32_CHIP EQU USE_HT32_CHIP_SET + ENDIF + ENDIF + + IF (USE_HT32_CHIP=0) +_HT32FWID EQU 0x00066246 + ENDIF + IF (USE_HT32_CHIP=HT32F66246) +_HT32FWID EQU 0x00066246 + ENDIF + IF (USE_HT32_CHIP=HT32F66242) +_HT32FWID EQU 0x00066242 + ENDIF + +; Amount of memory (in bytes) allocated for Stack and Heap +; Tailor those values to your application needs +;// Stack Size (in Bytes, must 8 byte aligned) <0-8192:8> +Stack_Size EQU 512 + + AREA STACK, NOINIT, READWRITE, ALIGN = 3 +__HT_check_sp +Stack_Mem SPACE Stack_Size +__initial_sp + +;// Heap Size (in Bytes) <0-8192:8> +Heap_Size EQU 0 + + AREA HEAP, NOINIT, READWRITE, ALIGN = 3 +__HT_check_heap +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + PRESERVE8 + THUMB + +;******************************************************************************* +; Fill-up the Vector Table entries with the exceptions ISR address +;******************************************************************************* + AREA RESET, CODE, READONLY + EXPORT __Vectors +_RESERVED EQU 0xFFFFFFFF +__Vectors + DCD __initial_sp ; ---, 00, 0x000, Top address of Stack + DCD Reset_Handler ; ---, 01, 0x004, Reset Handler + DCD NMI_Handler ; -14, 02, 0x008, NMI Handler + DCD HardFault_Handler ; -13, 03, 0x00C, Hard Fault Handler + DCD _RESERVED ; ---, 04, 0x010, Reserved + DCD _RESERVED ; ---, 05, 0x014, Reserved + DCD _RESERVED ; ---, 06, 0x018, Reserved + DCD _RESERVED ; ---, 07, 0x01C, Reserved + DCD _HT32FWID ; ---, 08, 0x020, Reserved + DCD _RESERVED ; ---, 09, 0x024, Reserved + DCD _RESERVED ; ---, 10, 0x028, Reserved + DCD SVC_Handler ; -05, 11, 0x02C, SVC Handler + DCD _RESERVED ; ---, 12, 0x030, Reserved + DCD _RESERVED ; ---, 13, 0x034, Reserved + DCD PendSV_Handler ; -02, 14, 0x038, PendSV Handler + DCD SysTick_Handler ; -01, 15, 0x03C, SysTick Handler + + ; External Interrupt Handler + DCD LVD_BOD_IRQHandler ; 00, 16, 0x040, + DCD RTC_IRQHandler ; 01, 17, 0x044, + DCD FLASH_IRQHandler ; 02, 18, 0x048, + DCD EVWUP_IRQHandler ; 03, 19, 0x04C, + DCD EXTI0_1_IRQHandler ; 04, 20, 0x050, + DCD EXTI2_3_IRQHandler ; 05, 21, 0x054, + DCD EXTI4_15_IRQHandler ; 06, 22, 0x058, + IF (USE_HT32_CHIP=HT32F66246) + DCD CAN0_IRQHandler ; 07, 23, 0x05C, + ELSE + DCD _RESERVED ; 07, 23, 0x05C, + ENDIF + DCD ADC_IRQHandler ; 08, 24, 0x060, + DCD CORDIC_IRQHandler ; 09, 25, 0x064, + DCD MCTM0_BRK_IRQHandler ; 10, 26, 0x068, + DCD MCTM0_UP_IRQHandler ; 11, 27, 0x06C, + DCD MCTM0_TR_UP2_IRQHandler ; 12, 28, 0x070, + DCD MCTM0_CC_IRQHandler ; 13, 29, 0x074, + DCD GPTM0_G_IRQHandler ; 14, 30, 0x078, + DCD GPTM0_VCLK_IRQHandler ; 15, 31, 0x07C, + DCD BFTM0_IRQHandler ; 16, 32, 0x080, + DCD BFTM1_IRQHandler ; 17, 33, 0x084, + DCD CMP0_IRQHandler ; 18, 34, 0x088, + DCD CMP1_IRQHandler ; 19, 35, 0x08C, + DCD PID_IRQHandler ; 20, 36, 0x090, + DCD I2C0_IRQHandler ; 21, 37, 0x094, + DCD SPI0_IRQHandler ; 22, 38, 0x098, + DCD USART0_IRQHandler ; 23, 39, 0x09C, + DCD UART0_IRQHandler ; 24, 40, 0x0A0, + DCD PDMA_CH0_1_IRQHandler ; 25, 41, 0x0A4, + DCD PDMA_CH2_3_IRQHandler ; 26, 42, 0x0A8, + DCD PDMA_CH4_5_IRQHandler ; 27, 43, 0x0AC, + DCD SCTM0_IRQHandler ; 28, 44, 0x0B0, + DCD SCTM1_IRQHandler ; 29, 45, 0x0B4, + DCD SCTM2_IRQHandler ; 30, 46, 0x0B8, + DCD SCTM3_IRQHandler ; 31, 47, 0x0BC, + +; Reset handler routine +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception Handlers +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP + +HardFault_Handler PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP + +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP + +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP + +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + EXPORT LVD_BOD_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT EVWUP_IRQHandler [WEAK] + EXPORT EXTI0_1_IRQHandler [WEAK] + EXPORT EXTI2_3_IRQHandler [WEAK] + EXPORT EXTI4_15_IRQHandler [WEAK] + EXPORT CAN0_IRQHandler [WEAK] + EXPORT ADC_IRQHandler [WEAK] + EXPORT CORDIC_IRQHandler [WEAK] + EXPORT MCTM0_BRK_IRQHandler [WEAK] + EXPORT MCTM0_UP_IRQHandler [WEAK] + EXPORT MCTM0_TR_UP2_IRQHandler [WEAK] + EXPORT MCTM0_CC_IRQHandler [WEAK] + EXPORT GPTM0_G_IRQHandler [WEAK] + EXPORT GPTM0_VCLK_IRQHandler [WEAK] + EXPORT BFTM0_IRQHandler [WEAK] + EXPORT BFTM1_IRQHandler [WEAK] + EXPORT CMP0_IRQHandler [WEAK] + EXPORT CMP1_IRQHandler [WEAK] + EXPORT PID_IRQHandler [WEAK] + EXPORT I2C0_IRQHandler [WEAK] + EXPORT SPI0_IRQHandler [WEAK] + EXPORT USART0_IRQHandler [WEAK] + EXPORT UART0_IRQHandler [WEAK] + EXPORT PDMA_CH0_1_IRQHandler [WEAK] + EXPORT PDMA_CH2_3_IRQHandler [WEAK] + EXPORT PDMA_CH4_5_IRQHandler [WEAK] + EXPORT SCTM0_IRQHandler [WEAK] + EXPORT SCTM1_IRQHandler [WEAK] + EXPORT SCTM2_IRQHandler [WEAK] + EXPORT SCTM3_IRQHandler [WEAK] + +LVD_BOD_IRQHandler +RTC_IRQHandler +FLASH_IRQHandler +EVWUP_IRQHandler +EXTI0_1_IRQHandler +EXTI2_3_IRQHandler +EXTI4_15_IRQHandler +CAN0_IRQHandler +ADC_IRQHandler +CORDIC_IRQHandler +MCTM0_BRK_IRQHandler +MCTM0_UP_IRQHandler +MCTM0_TR_UP2_IRQHandler +MCTM0_CC_IRQHandler +GPTM0_G_IRQHandler +GPTM0_VCLK_IRQHandler +BFTM0_IRQHandler +BFTM1_IRQHandler +CMP0_IRQHandler +CMP1_IRQHandler +PID_IRQHandler +I2C0_IRQHandler +SPI0_IRQHandler +USART0_IRQHandler +UART0_IRQHandler +PDMA_CH0_1_IRQHandler +PDMA_CH2_3_IRQHandler +PDMA_CH4_5_IRQHandler +SCTM0_IRQHandler +SCTM1_IRQHandler +SCTM2_IRQHandler +SCTM3_IRQHandler + B . + ENDP + + ALIGN + +;******************************************************************************* +; User Stack and Heap initialization +;******************************************************************************* + IF :DEF:__MICROLIB + + EXPORT __HT_check_heap + EXPORT __HT_check_sp + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, = (Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + + ENDIF + + END diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f67041_51.s b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f67041_51.s new file mode 100644 index 0000000000..13c68a18ec --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f67041_51.s @@ -0,0 +1,245 @@ +;/*---------------------------------------------------------------------------------------------------------*/ +;/* Holtek Semiconductor Inc. */ +;/* */ +;/* Copyright (C) Holtek Semiconductor Inc. */ +;/* All rights reserved. */ +;/* */ +;/*----------------------------------------------------------------------------------------------------------- +; File Name : startup_ht32f5xxxx_11.s +; Version : $Rev:: 5991 $ +; Date : $Date:: 2022-06-23 #$ +; Description : Startup code. +;-----------------------------------------------------------------------------------------------------------*/ + +; Supported Device +; ======================================== +; HT32F67041, HT32F67051 + +;/* <<< Use Configuration Wizard in Context Menu >>> */ + +;// HT32 Device +;// Select HT32 Device for the assembly setting. +;// Notice that the project's Asm Define has the higher priority. +;// <0=> By Project Asm Define +;// <22=> HT32F67041/51 +USE_HT32_CHIP_SET EQU 22 ; Notice that the project's Asm Define has the higher priority. + +_HT32FWID EQU 0xFFFFFFFF +;_HT32FWID EQU 0x00067041 +;_HT32FWID EQU 0x00067051 + +HT32F67041_51 EQU 22 + + IF USE_HT32_CHIP_SET=0 + ; Use project's Asm Define setting (default) + ELSE + IF :DEF:USE_HT32_CHIP + ; Use project's Asm Define setting (higher priority than the "USE_HT32_CHIP_SET") + ELSE + ; Use "USE_HT32_CHIP_SET" in the "startup_ht32xxxxx_xx.s" file +USE_HT32_CHIP EQU USE_HT32_CHIP_SET + ENDIF + ENDIF + +; Amount of memory (in bytes) allocated for Stack and Heap +; Tailor those values to your application needs +;// Stack Size (in Bytes, must 8 byte aligned) <0-8192:8> +Stack_Size EQU 512 + + AREA STACK, NOINIT, READWRITE, ALIGN = 3 +__HT_check_sp +Stack_Mem SPACE Stack_Size +__initial_sp + +;// Heap Size (in Bytes) <0-8192:8> +Heap_Size EQU 0 + + AREA HEAP, NOINIT, READWRITE, ALIGN = 3 +__HT_check_heap +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + PRESERVE8 + THUMB + +;******************************************************************************* +; Fill-up the Vector Table entries with the exceptions ISR address +;******************************************************************************* + AREA RESET, CODE, READONLY + EXPORT __Vectors +_RESERVED EQU 0xFFFFFFFF +__Vectors + DCD __initial_sp ; ---, 00, 0x000, Top address of Stack + DCD Reset_Handler ; ---, 01, 0x004, Reset Handler + DCD NMI_Handler ; -14, 02, 0x008, NMI Handler + DCD HardFault_Handler ; -13, 03, 0x00C, Hard Fault Handler + DCD _RESERVED ; ---, 04, 0x010, Reserved + DCD _RESERVED ; ---, 05, 0x014, Reserved + DCD _RESERVED ; ---, 06, 0x018, Reserved + DCD _RESERVED ; ---, 07, 0x01C, Reserved + DCD _HT32FWID ; ---, 08, 0x020, Reserved + DCD _RESERVED ; ---, 09, 0x024, Reserved + DCD _RESERVED ; ---, 10, 0x028, Reserved + DCD SVC_Handler ; -05, 11, 0x02C, SVC Handler + DCD _RESERVED ; ---, 12, 0x030, Reserved + DCD _RESERVED ; ---, 13, 0x034, Reserved + DCD PendSV_Handler ; -02, 14, 0x038, PendSV Handler + DCD SysTick_Handler ; -01, 15, 0x03C, SysTick Handler + + ; External Interrupt Handler + DCD LVD_BOD_IRQHandler ; 00, 16, 0x040, + DCD RTC_IRQHandler ; 01, 17, 0x044, + DCD FLASH_IRQHandler ; 02, 18, 0x048, + DCD EVWUP_IRQHandler ; 03, 19, 0x04C, + DCD EXTI0_1_IRQHandler ; 04, 20, 0x050, + DCD EXTI2_3_IRQHandler ; 05, 21, 0x054, + DCD EXTI4_15_IRQHandler ; 06, 22, 0x058, + DCD _RESERVED ; 07, 23, 0x05C, + DCD ADC_IRQHandler ; 08, 24, 0x060, + DCD AES_IRQHandler ; 09, 25, 0x064, + DCD _RESERVED ; 10, 26, 0x068, + DCD RF_IRQHandler ; 11, 27, 0x06C, + DCD GPTM0_IRQHandler ; 12, 28, 0x070, + DCD SCTM0_IRQHandler ; 13, 29, 0x074, + DCD SCTM1_IRQHandler ; 14, 30, 0x078, + DCD SCTM2_IRQHandler ; 15, 31, 0x07C, + DCD SCTM3_IRQHandler ; 16, 32, 0x080, + DCD BFTM0_IRQHandler ; 17, 33, 0x084, + DCD BFTM1_IRQHandler ; 18, 34, 0x088, + DCD I2C0_IRQHandler ; 19, 35, 0x08C, + DCD I2C1_IRQHandler ; 20, 36, 0x090, + DCD SPI0_IRQHandler ; 21, 37, 0x094, + DCD SPI1_IRQHandler ; 22, 38, 0x098, + DCD _RESERVED ; 23, 39, 0x09C, + DCD _RESERVED ; 24, 40, 0x0A0, + DCD UART0_IRQHandler ; 25, 41, 0x0A4, + DCD UART1_IRQHandler ; 26, 42, 0x0A8, + DCD _RESERVED ; 27, 43, 0x0AC, + DCD _RESERVED ; 28, 44, 0x0B0, + DCD _RESERVED ; 29, 45, 0x0B4, + DCD PDMA_CH0_1_IRQHandler ; 30, 46, 0x0B8, + DCD PDMA_CH2_5_IRQHandler ; 31, 47, 0x0BC, + +; Reset handler routine +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception Handlers +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP + +HardFault_Handler PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP + +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP + +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP + +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + EXPORT LVD_BOD_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT EVWUP_IRQHandler [WEAK] + EXPORT EXTI0_1_IRQHandler [WEAK] + EXPORT EXTI2_3_IRQHandler [WEAK] + EXPORT EXTI4_15_IRQHandler [WEAK] + EXPORT ADC_IRQHandler [WEAK] + EXPORT AES_IRQHandler [WEAK] + EXPORT RF_IRQHandler [WEAK] + EXPORT GPTM0_IRQHandler [WEAK] + EXPORT SCTM0_IRQHandler [WEAK] + EXPORT SCTM1_IRQHandler [WEAK] + EXPORT SCTM2_IRQHandler [WEAK] + EXPORT SCTM3_IRQHandler [WEAK] + EXPORT BFTM0_IRQHandler [WEAK] + EXPORT BFTM1_IRQHandler [WEAK] + EXPORT I2C0_IRQHandler [WEAK] + EXPORT I2C1_IRQHandler [WEAK] + EXPORT SPI0_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT UART0_IRQHandler [WEAK] + EXPORT UART1_IRQHandler [WEAK] + EXPORT PDMA_CH0_1_IRQHandler [WEAK] + EXPORT PDMA_CH2_5_IRQHandler [WEAK] + +LVD_BOD_IRQHandler +RTC_IRQHandler +FLASH_IRQHandler +EVWUP_IRQHandler +EXTI0_1_IRQHandler +EXTI2_3_IRQHandler +EXTI4_15_IRQHandler +ADC_IRQHandler +AES_IRQHandler +RF_IRQHandler +GPTM0_IRQHandler +SCTM0_IRQHandler +SCTM1_IRQHandler +SCTM2_IRQHandler +SCTM3_IRQHandler +BFTM0_IRQHandler +BFTM1_IRQHandler +I2C0_IRQHandler +I2C1_IRQHandler +SPI0_IRQHandler +SPI1_IRQHandler +UART0_IRQHandler +UART1_IRQHandler +PDMA_CH0_1_IRQHandler +PDMA_CH2_5_IRQHandler + B . + ENDP + + ALIGN + +;******************************************************************************* +; User Stack and Heap initialization +;******************************************************************************* + IF :DEF:__MICROLIB + + EXPORT __HT_check_heap + EXPORT __HT_check_sp + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, = (Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + + ENDIF + + END diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f67232.s b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f67232.s new file mode 100644 index 0000000000..ae562b2a89 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f67232.s @@ -0,0 +1,482 @@ +;/*---------------------------------------------------------------------------------------------------------*/ +;/* Holtek Semiconductor Inc. */ +;/* */ +;/* Copyright (C) Holtek Semiconductor Inc. */ +;/* All rights reserved. */ +;/* */ +;/*----------------------------------------------------------------------------------------------------------- +; File Name : startup_ht32f5xxxx_01.s +; Version : $Rev:: 6953 $ +; Date : $Date:: 2023-05-30 #$ +; Description : Startup code. +;-----------------------------------------------------------------------------------------------------------*/ + +; Supported Device +; ======================================== +; HT32F52220, HT32F52230 +; HT32F52231, HT32F52241 +; HT32F52331, HT32F52341 +; HT32F52342, HT32F52352 +; HT32F52243, HT32F52253 +; HT32F0008 +; HT32F52344, HT32F52354 +; HT32F0006 +; HT32F61352 +; HT50F32003 +; HT32F62030, HT32F62040, HT32F62050 +; HT32F67741 +; HT32F67232 +; HT32F67233 + +;/* <<< Use Configuration Wizard in Context Menu >>> */ + +;// HT32 Device +;// Select HT32 Device for the assembly setting. +;// Notice that the project's Asm Define has the higher priority. +;// <0=> By Project Asm Define +;// <1=> HT32F52220/30 +;// <2=> HT32F52231/41 +;// <3=> HT32F52331/41 +;// <4=> HT32F52342/52 +;// <5=> HT32F52243/53 +;// <6=> HT32F0008 +;// <9=> HT32F52344/54 +;// <10=> HT32F0006 +;// <10=> HT32F61352 +;// <4=> HT50F32003 +;// <2=> HT32F67741 +;// <1=> HT32F67232 +;// <1=> HT32F67233 +;// <1=> HT32F62030 +;// <2=> HT32F62040 +;// <5=> HT32F62050 +USE_HT32_CHIP_SET EQU 1 ; Notice that the project's Asm Define has the higher priority. + +_HT32FWID EQU 0xFFFFFFFF +;_HT32FWID EQU 0x00052220 +;_HT32FWID EQU 0x00052230 +;_HT32FWID EQU 0x00052231 +;_HT32FWID EQU 0x00052241 +;_HT32FWID EQU 0x00052331 +;_HT32FWID EQU 0x00052341 +;_HT32FWID EQU 0x00052342 +;_HT32FWID EQU 0x00052352 +;_HT32FWID EQU 0x00052243 +;_HT32FWID EQU 0x00052253 +;_HT32FWID EQU 0x00000008 +;_HT32FWID EQU 0x00052344 +;_HT32FWID EQU 0x00052354 +;_HT32FWID EQU 0x00000006 +;_HT32FWID EQU 0x00061352 +;_HT32FWID EQU 0x00032003 +;_HT32FWID EQU 0x00062030 +;_HT32FWID EQU 0x00062040 +;_HT32FWID EQU 0x00062050 +;_HT32FWID EQU 0x00067741 +;_HT32FWID EQU 0x00067232 +;_HT32FWID EQU 0x00067233 + +HT32F52220_30 EQU 1 +HT32F52231_41 EQU 2 +HT32F52331_41 EQU 3 +HT32F52342_52 EQU 4 +HT32F52243_53 EQU 5 +HT32F0008 EQU 6 +HT32F52344_54 EQU 9 +HT32F0006 EQU 10 +HT32F61352 EQU 10 +HT50F32003 EQU 4 +HT32F62030 EQU 1 +HT32F62040 EQU 2 +HT32F62050 EQU 5 +HT32F67741 EQU 2 +HT32F67232 EQU 1 +HT32F67233 EQU 1 + + IF USE_HT32_CHIP_SET=0 + ; Use project's Asm Define setting (default) + ELSE + IF :DEF:USE_HT32_CHIP + ; Use project's Asm Define setting (higher priority than the "USE_HT32_CHIP_SET") + ELSE + ; Use "USE_HT32_CHIP_SET" in the "startup_ht32xxxxx_xx.s" file +USE_HT32_CHIP EQU USE_HT32_CHIP_SET + ENDIF + ENDIF + +; Amount of memory (in bytes) allocated for Stack and Heap +; Tailor those values to your application needs +;// Stack Size (in Bytes, must 8 byte aligned) <0-16384:8> +Stack_Size EQU 512 + + AREA STACK, NOINIT, READWRITE, ALIGN = 3 +__HT_check_sp +Stack_Mem SPACE Stack_Size +__initial_sp + +;// Heap Size (in Bytes) <0-16384:8> +Heap_Size EQU 0 + + AREA HEAP, NOINIT, READWRITE, ALIGN = 3 +__HT_check_heap +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + PRESERVE8 + THUMB + +;******************************************************************************* +; Fill-up the Vector Table entries with the exceptions ISR address +;******************************************************************************* + AREA RESET, CODE, READONLY + EXPORT __Vectors +_RESERVED EQU 0xFFFFFFFF +__Vectors + DCD __initial_sp ; ---, 00, 0x000, Top address of Stack + DCD Reset_Handler ; ---, 01, 0x004, Reset Handler + DCD NMI_Handler ; -14, 02, 0x008, NMI Handler + DCD HardFault_Handler ; -13, 03, 0x00C, Hard Fault Handler + DCD _RESERVED ; ---, 04, 0x010, Reserved + DCD _RESERVED ; ---, 05, 0x014, Reserved + DCD _RESERVED ; ---, 06, 0x018, Reserved + DCD _RESERVED ; ---, 07, 0x01C, Reserved + DCD _HT32FWID ; ---, 08, 0x020, Reserved + DCD _RESERVED ; ---, 09, 0x024, Reserved + DCD _RESERVED ; ---, 10, 0x028, Reserved + DCD SVC_Handler ; -05, 11, 0x02C, SVC Handler + DCD _RESERVED ; ---, 12, 0x030, Reserved + DCD _RESERVED ; ---, 13, 0x034, Reserved + DCD PendSV_Handler ; -02, 14, 0x038, PendSV Handler + DCD SysTick_Handler ; -01, 15, 0x03C, SysTick Handler + + ; External Interrupt Handler + DCD LVD_BOD_IRQHandler ; 00, 16, 0x040, + IF (USE_HT32_CHIP=HT32F52220_30) + DCD _RESERVED ; 01, 17, 0x044, + ELSE + DCD RTC_IRQHandler ; 01, 17, 0x044, + ENDIF + DCD FLASH_IRQHandler ; 02, 18, 0x048, + DCD EVWUP_IRQHandler ; 03, 19, 0x04C, + DCD EXTI0_1_IRQHandler ; 04, 20, 0x050, + DCD EXTI2_3_IRQHandler ; 05, 21, 0x054, + DCD EXTI4_15_IRQHandler ; 06, 22, 0x058, + IF (USE_HT32_CHIP=HT32F52342_52) || (USE_HT32_CHIP=HT32F52344_54) + DCD COMP_IRQHandler ; 07, 23, 0x05C, + ELSE + DCD _RESERVED ; 07, 23, 0x05C, + ENDIF + IF (USE_HT32_CHIP=HT32F0008) + DCD _RESERVED ; 08, 24, 0x060, + ELSE + DCD ADC_IRQHandler ; 08, 24, 0x060, + ENDIF + IF (USE_HT32_CHIP=HT32F52243_53) + DCD I2C2_IRQHandler ; 09, 25, 0x064, + ELSE + DCD _RESERVED ; 09, 25, 0x064, + ENDIF + IF (USE_HT32_CHIP=HT32F52220_30) || (USE_HT32_CHIP=HT32F0008) || (USE_HT32_CHIP=HT32F0006) + DCD _RESERVED ; 10, 26, 0x068, + ELSE + DCD MCTM0_IRQHandler ; 10, 26, 0x068, + ENDIF + IF (USE_HT32_CHIP=HT32F52342_52) + DCD GPTM1_IRQHandler ; 11, 27, 0x06C, + ELSE + DCD _RESERVED ; 11, 27, 0x06C, + ENDIF + DCD GPTM0_IRQHandler ; 12, 28, 0x070, + IF (USE_HT32_CHIP=HT32F0008) + DCD _RESERVED ; 13, 29, 0x074, + DCD _RESERVED ; 14, 30, 0x078, + ELSE + DCD SCTM0_IRQHandler ; 13, 29, 0x074, + DCD SCTM1_IRQHandler ; 14, 30, 0x078, + ENDIF + IF (USE_HT32_CHIP=HT32F52231_41) || (USE_HT32_CHIP=HT32F52331_41) || (USE_HT32_CHIP=HT32F52243_53) || (USE_HT32_CHIP=HT32F0006) + DCD SCTM2_IRQHandler ; 15, 31, 0x07C, + DCD SCTM3_IRQHandler ; 16, 32, 0x080, + ENDIF + IF (USE_HT32_CHIP=HT32F0008) + DCD PWM0_IRQHandler ; 15, 31, 0x07C, + DCD PWM1_IRQHandler ; 16, 32, 0x080, + ENDIF + IF (USE_HT32_CHIP=HT32F52220_30) || (USE_HT32_CHIP=HT32F52342_52) || (USE_HT32_CHIP=HT32F52344_54) + DCD _RESERVED ; 15, 31, 0x07C, + DCD _RESERVED ; 16, 32, 0x080, + ENDIF + DCD BFTM0_IRQHandler ; 17, 33, 0x084, + IF (USE_HT32_CHIP=HT32F52220_30) + DCD _RESERVED ; 18, 34, 0x088, + ELSE + DCD BFTM1_IRQHandler ; 18, 34, 0x088, + ENDIF + DCD I2C0_IRQHandler ; 19, 35, 0x08C, + IF (USE_HT32_CHIP=HT32F52220_30) || (USE_HT32_CHIP=HT32F0008) || (USE_HT32_CHIP=HT32F52344_54) || (USE_HT32_CHIP=HT32F0006) + DCD _RESERVED ; 20, 36, 0x090, + ELSE + DCD I2C1_IRQHandler ; 20, 36, 0x090, + ENDIF + DCD SPI0_IRQHandler ; 21, 37, 0x094, + IF (USE_HT32_CHIP=HT32F52220_30) || (USE_HT32_CHIP=HT32F0008) + DCD _RESERVED ; 22, 38, 0x098, + ELSE + IF (USE_HT32_CHIP=HT32F0006) + DCD QSPI_IRQHandler ; 22, 38, 0x098, + ELSE + DCD SPI1_IRQHandler ; 22, 38, 0x098, + ENDIF + ENDIF + IF (USE_HT32_CHIP=HT32F52344_54) + DCD _RESERVED ; 23, 39, 0x09C, + ELSE + DCD USART0_IRQHandler ; 23, 39, 0x09C, + ENDIF + IF (USE_HT32_CHIP=HT32F52342_52) || (USE_HT32_CHIP=HT32F52243_53) + DCD USART1_IRQHandler ; 24, 40, 0x0A0, + ELSE + DCD _RESERVED ; 24, 40, 0x0A0, + ENDIF + DCD UART0_IRQHandler ; 25, 41, 0x0A4, + IF (USE_HT32_CHIP=HT32F52220_30) || (USE_HT32_CHIP=HT32F0008) || (USE_HT32_CHIP=HT32F0006) + DCD _RESERVED ; 26, 42, 0x0A8, + ELSE + DCD UART1_IRQHandler ; 26, 42, 0x0A8, + ENDIF + IF (USE_HT32_CHIP=HT32F52331_41) || (USE_HT32_CHIP=HT32F52342_52) + DCD SCI_IRQHandler ; 27, 43, 0x0AC, + ENDIF + IF (USE_HT32_CHIP=HT32F52243_53) + DCD UART2_IRQHandler ; 27, 43, 0x0AC, + ENDIF + IF (USE_HT32_CHIP=HT32F0006) + DCD MIDI_IRQHandler ; 27, 43, 0x0AC, + ENDIF + IF (USE_HT32_CHIP=HT32F0008) || (USE_HT32_CHIP=HT32F52344_54) + DCD _RESERVED ; 27, 43, 0xAC, + ENDIF + IF (USE_HT32_CHIP=HT32F52342_52) || (USE_HT32_CHIP=HT32F0006) + DCD I2S_IRQHandler ; 28, 44, 0x0B0, + ENDIF + IF (USE_HT32_CHIP=HT32F52331_41) || (USE_HT32_CHIP=HT32F52344_54) + DCD _RESERVED ; 28, 44, 0x0B0, + ENDIF + IF (USE_HT32_CHIP=HT32F52243_53) + DCD UART3_IRQHandler ; 28, 44, 0x0B0, + ENDIF + IF (USE_HT32_CHIP=HT32F0008) + DCD AES_IRQHandler ; 28, 44, 0x0B0, + ENDIF + IF (USE_HT32_CHIP=HT32F52331_41) || (USE_HT32_CHIP=HT32F52342_52) || (USE_HT32_CHIP=HT32F0008) || (USE_HT32_CHIP=HT32F52344_54) || (USE_HT32_CHIP=HT32F0006) + DCD USB_IRQHandler ; 29, 45, 0x0B4, + ENDIF + IF (USE_HT32_CHIP=HT32F52243_53) + DCD _RESERVED ; 29, 45, 0x0B4, + ENDIF + IF (USE_HT32_CHIP=HT32F52342_52) || (USE_HT32_CHIP=HT32F52243_53) || (USE_HT32_CHIP=HT32F0008) || (USE_HT32_CHIP=HT32F52344_54) || (USE_HT32_CHIP=HT32F0006) + DCD PDMA_CH0_1_IRQHandler ; 30, 46, 0x0B8, + DCD PDMA_CH2_5_IRQHandler ; 31, 47, 0x0BC, + ENDIF + +; Reset handler routine +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + LDR R0, =BootProcess + BLX R0 + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +BootProcess PROC + LDR R0, =0x40080300 + LDR R1,[R0, #0x10] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x14] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x18] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x1C] + CMP R1, #0 + BEQ BP2 +BP1 LDR R0, =0x40080180 + LDR R1,[R0, #0xC] + LSLS R1, R1, #4 + LSRS R1, R1, #20 + CMP R1, #0 + BEQ BP3 + CMP R1, #5 + BEQ BP3 + CMP R1, #6 + BEQ BP3 +BP2 DSB + LDR R0, =0x20000000 + LDR R1, =0x05fa0004 + STR R1, [R0] + LDR R1, =0xe000ed00 + LDR R0, =0x05fa0004 + STR R0, [R1, #0xC] + DSB + B . +BP3 LDR R0, =0x20000000 + LDR R1, [R0] + LDR R0, =0x05fa0004 + CMP R0, R1 + BEQ BP4 + BX LR +BP4 LDR R0, =0x40088100 + LDR R1, =0x00000001 + STR R1, [R0] + LDR R0, =0x20000000 + LDR R1, =0x0 + STR R1, [R0] + BX LR + ENDP + +; Dummy Exception Handlers +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP + +HardFault_Handler PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP + +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP + +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP + +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + EXPORT LVD_BOD_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT EVWUP_IRQHandler [WEAK] + EXPORT EXTI0_1_IRQHandler [WEAK] + EXPORT EXTI2_3_IRQHandler [WEAK] + EXPORT EXTI4_15_IRQHandler [WEAK] + EXPORT COMP_IRQHandler [WEAK] + EXPORT ADC_IRQHandler [WEAK] + EXPORT MCTM0_IRQHandler [WEAK] + EXPORT GPTM1_IRQHandler [WEAK] + EXPORT GPTM0_IRQHandler [WEAK] + EXPORT SCTM0_IRQHandler [WEAK] + EXPORT SCTM1_IRQHandler [WEAK] + EXPORT SCTM2_IRQHandler [WEAK] + EXPORT SCTM3_IRQHandler [WEAK] + EXPORT PWM0_IRQHandler [WEAK] + EXPORT PWM1_IRQHandler [WEAK] + EXPORT BFTM0_IRQHandler [WEAK] + EXPORT BFTM1_IRQHandler [WEAK] + EXPORT I2C0_IRQHandler [WEAK] + EXPORT I2C1_IRQHandler [WEAK] + EXPORT I2C2_IRQHandler [WEAK] + EXPORT SPI0_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT QSPI_IRQHandler [WEAK] + EXPORT USART0_IRQHandler [WEAK] + EXPORT USART1_IRQHandler [WEAK] + EXPORT UART0_IRQHandler [WEAK] + EXPORT UART1_IRQHandler [WEAK] + EXPORT UART2_IRQHandler [WEAK] + EXPORT UART3_IRQHandler [WEAK] + EXPORT SCI_IRQHandler [WEAK] + EXPORT MIDI_IRQHandler [WEAK] + EXPORT I2S_IRQHandler [WEAK] + EXPORT AES_IRQHandler [WEAK] + EXPORT USB_IRQHandler [WEAK] + EXPORT PDMA_CH0_1_IRQHandler [WEAK] + EXPORT PDMA_CH2_5_IRQHandler [WEAK] + +LVD_BOD_IRQHandler +RTC_IRQHandler +FLASH_IRQHandler +EVWUP_IRQHandler +EXTI0_1_IRQHandler +EXTI2_3_IRQHandler +EXTI4_15_IRQHandler +COMP_IRQHandler +ADC_IRQHandler +MCTM0_IRQHandler +GPTM1_IRQHandler +GPTM0_IRQHandler +SCTM0_IRQHandler +SCTM1_IRQHandler +SCTM2_IRQHandler +SCTM3_IRQHandler +PWM0_IRQHandler +PWM1_IRQHandler +BFTM0_IRQHandler +BFTM1_IRQHandler +I2C0_IRQHandler +I2C1_IRQHandler +I2C2_IRQHandler +SPI0_IRQHandler +SPI1_IRQHandler +QSPI_IRQHandler +USART0_IRQHandler +USART1_IRQHandler +UART0_IRQHandler +UART1_IRQHandler +UART2_IRQHandler +UART3_IRQHandler +SCI_IRQHandler +MIDI_IRQHandler +I2S_IRQHandler +AES_IRQHandler +USB_IRQHandler +PDMA_CH0_1_IRQHandler +PDMA_CH2_5_IRQHandler + B . + ENDP + + ALIGN + +;******************************************************************************* +; User Stack and Heap initialization +;******************************************************************************* + IF :DEF:__MICROLIB + + EXPORT __HT_check_heap + EXPORT __HT_check_sp + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, = (Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + + ENDIF + + END diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f67233.s b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f67233.s new file mode 100644 index 0000000000..ae562b2a89 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f67233.s @@ -0,0 +1,482 @@ +;/*---------------------------------------------------------------------------------------------------------*/ +;/* Holtek Semiconductor Inc. */ +;/* */ +;/* Copyright (C) Holtek Semiconductor Inc. */ +;/* All rights reserved. */ +;/* */ +;/*----------------------------------------------------------------------------------------------------------- +; File Name : startup_ht32f5xxxx_01.s +; Version : $Rev:: 6953 $ +; Date : $Date:: 2023-05-30 #$ +; Description : Startup code. +;-----------------------------------------------------------------------------------------------------------*/ + +; Supported Device +; ======================================== +; HT32F52220, HT32F52230 +; HT32F52231, HT32F52241 +; HT32F52331, HT32F52341 +; HT32F52342, HT32F52352 +; HT32F52243, HT32F52253 +; HT32F0008 +; HT32F52344, HT32F52354 +; HT32F0006 +; HT32F61352 +; HT50F32003 +; HT32F62030, HT32F62040, HT32F62050 +; HT32F67741 +; HT32F67232 +; HT32F67233 + +;/* <<< Use Configuration Wizard in Context Menu >>> */ + +;// HT32 Device +;// Select HT32 Device for the assembly setting. +;// Notice that the project's Asm Define has the higher priority. +;// <0=> By Project Asm Define +;// <1=> HT32F52220/30 +;// <2=> HT32F52231/41 +;// <3=> HT32F52331/41 +;// <4=> HT32F52342/52 +;// <5=> HT32F52243/53 +;// <6=> HT32F0008 +;// <9=> HT32F52344/54 +;// <10=> HT32F0006 +;// <10=> HT32F61352 +;// <4=> HT50F32003 +;// <2=> HT32F67741 +;// <1=> HT32F67232 +;// <1=> HT32F67233 +;// <1=> HT32F62030 +;// <2=> HT32F62040 +;// <5=> HT32F62050 +USE_HT32_CHIP_SET EQU 1 ; Notice that the project's Asm Define has the higher priority. + +_HT32FWID EQU 0xFFFFFFFF +;_HT32FWID EQU 0x00052220 +;_HT32FWID EQU 0x00052230 +;_HT32FWID EQU 0x00052231 +;_HT32FWID EQU 0x00052241 +;_HT32FWID EQU 0x00052331 +;_HT32FWID EQU 0x00052341 +;_HT32FWID EQU 0x00052342 +;_HT32FWID EQU 0x00052352 +;_HT32FWID EQU 0x00052243 +;_HT32FWID EQU 0x00052253 +;_HT32FWID EQU 0x00000008 +;_HT32FWID EQU 0x00052344 +;_HT32FWID EQU 0x00052354 +;_HT32FWID EQU 0x00000006 +;_HT32FWID EQU 0x00061352 +;_HT32FWID EQU 0x00032003 +;_HT32FWID EQU 0x00062030 +;_HT32FWID EQU 0x00062040 +;_HT32FWID EQU 0x00062050 +;_HT32FWID EQU 0x00067741 +;_HT32FWID EQU 0x00067232 +;_HT32FWID EQU 0x00067233 + +HT32F52220_30 EQU 1 +HT32F52231_41 EQU 2 +HT32F52331_41 EQU 3 +HT32F52342_52 EQU 4 +HT32F52243_53 EQU 5 +HT32F0008 EQU 6 +HT32F52344_54 EQU 9 +HT32F0006 EQU 10 +HT32F61352 EQU 10 +HT50F32003 EQU 4 +HT32F62030 EQU 1 +HT32F62040 EQU 2 +HT32F62050 EQU 5 +HT32F67741 EQU 2 +HT32F67232 EQU 1 +HT32F67233 EQU 1 + + IF USE_HT32_CHIP_SET=0 + ; Use project's Asm Define setting (default) + ELSE + IF :DEF:USE_HT32_CHIP + ; Use project's Asm Define setting (higher priority than the "USE_HT32_CHIP_SET") + ELSE + ; Use "USE_HT32_CHIP_SET" in the "startup_ht32xxxxx_xx.s" file +USE_HT32_CHIP EQU USE_HT32_CHIP_SET + ENDIF + ENDIF + +; Amount of memory (in bytes) allocated for Stack and Heap +; Tailor those values to your application needs +;// Stack Size (in Bytes, must 8 byte aligned) <0-16384:8> +Stack_Size EQU 512 + + AREA STACK, NOINIT, READWRITE, ALIGN = 3 +__HT_check_sp +Stack_Mem SPACE Stack_Size +__initial_sp + +;// Heap Size (in Bytes) <0-16384:8> +Heap_Size EQU 0 + + AREA HEAP, NOINIT, READWRITE, ALIGN = 3 +__HT_check_heap +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + PRESERVE8 + THUMB + +;******************************************************************************* +; Fill-up the Vector Table entries with the exceptions ISR address +;******************************************************************************* + AREA RESET, CODE, READONLY + EXPORT __Vectors +_RESERVED EQU 0xFFFFFFFF +__Vectors + DCD __initial_sp ; ---, 00, 0x000, Top address of Stack + DCD Reset_Handler ; ---, 01, 0x004, Reset Handler + DCD NMI_Handler ; -14, 02, 0x008, NMI Handler + DCD HardFault_Handler ; -13, 03, 0x00C, Hard Fault Handler + DCD _RESERVED ; ---, 04, 0x010, Reserved + DCD _RESERVED ; ---, 05, 0x014, Reserved + DCD _RESERVED ; ---, 06, 0x018, Reserved + DCD _RESERVED ; ---, 07, 0x01C, Reserved + DCD _HT32FWID ; ---, 08, 0x020, Reserved + DCD _RESERVED ; ---, 09, 0x024, Reserved + DCD _RESERVED ; ---, 10, 0x028, Reserved + DCD SVC_Handler ; -05, 11, 0x02C, SVC Handler + DCD _RESERVED ; ---, 12, 0x030, Reserved + DCD _RESERVED ; ---, 13, 0x034, Reserved + DCD PendSV_Handler ; -02, 14, 0x038, PendSV Handler + DCD SysTick_Handler ; -01, 15, 0x03C, SysTick Handler + + ; External Interrupt Handler + DCD LVD_BOD_IRQHandler ; 00, 16, 0x040, + IF (USE_HT32_CHIP=HT32F52220_30) + DCD _RESERVED ; 01, 17, 0x044, + ELSE + DCD RTC_IRQHandler ; 01, 17, 0x044, + ENDIF + DCD FLASH_IRQHandler ; 02, 18, 0x048, + DCD EVWUP_IRQHandler ; 03, 19, 0x04C, + DCD EXTI0_1_IRQHandler ; 04, 20, 0x050, + DCD EXTI2_3_IRQHandler ; 05, 21, 0x054, + DCD EXTI4_15_IRQHandler ; 06, 22, 0x058, + IF (USE_HT32_CHIP=HT32F52342_52) || (USE_HT32_CHIP=HT32F52344_54) + DCD COMP_IRQHandler ; 07, 23, 0x05C, + ELSE + DCD _RESERVED ; 07, 23, 0x05C, + ENDIF + IF (USE_HT32_CHIP=HT32F0008) + DCD _RESERVED ; 08, 24, 0x060, + ELSE + DCD ADC_IRQHandler ; 08, 24, 0x060, + ENDIF + IF (USE_HT32_CHIP=HT32F52243_53) + DCD I2C2_IRQHandler ; 09, 25, 0x064, + ELSE + DCD _RESERVED ; 09, 25, 0x064, + ENDIF + IF (USE_HT32_CHIP=HT32F52220_30) || (USE_HT32_CHIP=HT32F0008) || (USE_HT32_CHIP=HT32F0006) + DCD _RESERVED ; 10, 26, 0x068, + ELSE + DCD MCTM0_IRQHandler ; 10, 26, 0x068, + ENDIF + IF (USE_HT32_CHIP=HT32F52342_52) + DCD GPTM1_IRQHandler ; 11, 27, 0x06C, + ELSE + DCD _RESERVED ; 11, 27, 0x06C, + ENDIF + DCD GPTM0_IRQHandler ; 12, 28, 0x070, + IF (USE_HT32_CHIP=HT32F0008) + DCD _RESERVED ; 13, 29, 0x074, + DCD _RESERVED ; 14, 30, 0x078, + ELSE + DCD SCTM0_IRQHandler ; 13, 29, 0x074, + DCD SCTM1_IRQHandler ; 14, 30, 0x078, + ENDIF + IF (USE_HT32_CHIP=HT32F52231_41) || (USE_HT32_CHIP=HT32F52331_41) || (USE_HT32_CHIP=HT32F52243_53) || (USE_HT32_CHIP=HT32F0006) + DCD SCTM2_IRQHandler ; 15, 31, 0x07C, + DCD SCTM3_IRQHandler ; 16, 32, 0x080, + ENDIF + IF (USE_HT32_CHIP=HT32F0008) + DCD PWM0_IRQHandler ; 15, 31, 0x07C, + DCD PWM1_IRQHandler ; 16, 32, 0x080, + ENDIF + IF (USE_HT32_CHIP=HT32F52220_30) || (USE_HT32_CHIP=HT32F52342_52) || (USE_HT32_CHIP=HT32F52344_54) + DCD _RESERVED ; 15, 31, 0x07C, + DCD _RESERVED ; 16, 32, 0x080, + ENDIF + DCD BFTM0_IRQHandler ; 17, 33, 0x084, + IF (USE_HT32_CHIP=HT32F52220_30) + DCD _RESERVED ; 18, 34, 0x088, + ELSE + DCD BFTM1_IRQHandler ; 18, 34, 0x088, + ENDIF + DCD I2C0_IRQHandler ; 19, 35, 0x08C, + IF (USE_HT32_CHIP=HT32F52220_30) || (USE_HT32_CHIP=HT32F0008) || (USE_HT32_CHIP=HT32F52344_54) || (USE_HT32_CHIP=HT32F0006) + DCD _RESERVED ; 20, 36, 0x090, + ELSE + DCD I2C1_IRQHandler ; 20, 36, 0x090, + ENDIF + DCD SPI0_IRQHandler ; 21, 37, 0x094, + IF (USE_HT32_CHIP=HT32F52220_30) || (USE_HT32_CHIP=HT32F0008) + DCD _RESERVED ; 22, 38, 0x098, + ELSE + IF (USE_HT32_CHIP=HT32F0006) + DCD QSPI_IRQHandler ; 22, 38, 0x098, + ELSE + DCD SPI1_IRQHandler ; 22, 38, 0x098, + ENDIF + ENDIF + IF (USE_HT32_CHIP=HT32F52344_54) + DCD _RESERVED ; 23, 39, 0x09C, + ELSE + DCD USART0_IRQHandler ; 23, 39, 0x09C, + ENDIF + IF (USE_HT32_CHIP=HT32F52342_52) || (USE_HT32_CHIP=HT32F52243_53) + DCD USART1_IRQHandler ; 24, 40, 0x0A0, + ELSE + DCD _RESERVED ; 24, 40, 0x0A0, + ENDIF + DCD UART0_IRQHandler ; 25, 41, 0x0A4, + IF (USE_HT32_CHIP=HT32F52220_30) || (USE_HT32_CHIP=HT32F0008) || (USE_HT32_CHIP=HT32F0006) + DCD _RESERVED ; 26, 42, 0x0A8, + ELSE + DCD UART1_IRQHandler ; 26, 42, 0x0A8, + ENDIF + IF (USE_HT32_CHIP=HT32F52331_41) || (USE_HT32_CHIP=HT32F52342_52) + DCD SCI_IRQHandler ; 27, 43, 0x0AC, + ENDIF + IF (USE_HT32_CHIP=HT32F52243_53) + DCD UART2_IRQHandler ; 27, 43, 0x0AC, + ENDIF + IF (USE_HT32_CHIP=HT32F0006) + DCD MIDI_IRQHandler ; 27, 43, 0x0AC, + ENDIF + IF (USE_HT32_CHIP=HT32F0008) || (USE_HT32_CHIP=HT32F52344_54) + DCD _RESERVED ; 27, 43, 0xAC, + ENDIF + IF (USE_HT32_CHIP=HT32F52342_52) || (USE_HT32_CHIP=HT32F0006) + DCD I2S_IRQHandler ; 28, 44, 0x0B0, + ENDIF + IF (USE_HT32_CHIP=HT32F52331_41) || (USE_HT32_CHIP=HT32F52344_54) + DCD _RESERVED ; 28, 44, 0x0B0, + ENDIF + IF (USE_HT32_CHIP=HT32F52243_53) + DCD UART3_IRQHandler ; 28, 44, 0x0B0, + ENDIF + IF (USE_HT32_CHIP=HT32F0008) + DCD AES_IRQHandler ; 28, 44, 0x0B0, + ENDIF + IF (USE_HT32_CHIP=HT32F52331_41) || (USE_HT32_CHIP=HT32F52342_52) || (USE_HT32_CHIP=HT32F0008) || (USE_HT32_CHIP=HT32F52344_54) || (USE_HT32_CHIP=HT32F0006) + DCD USB_IRQHandler ; 29, 45, 0x0B4, + ENDIF + IF (USE_HT32_CHIP=HT32F52243_53) + DCD _RESERVED ; 29, 45, 0x0B4, + ENDIF + IF (USE_HT32_CHIP=HT32F52342_52) || (USE_HT32_CHIP=HT32F52243_53) || (USE_HT32_CHIP=HT32F0008) || (USE_HT32_CHIP=HT32F52344_54) || (USE_HT32_CHIP=HT32F0006) + DCD PDMA_CH0_1_IRQHandler ; 30, 46, 0x0B8, + DCD PDMA_CH2_5_IRQHandler ; 31, 47, 0x0BC, + ENDIF + +; Reset handler routine +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + LDR R0, =BootProcess + BLX R0 + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +BootProcess PROC + LDR R0, =0x40080300 + LDR R1,[R0, #0x10] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x14] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x18] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x1C] + CMP R1, #0 + BEQ BP2 +BP1 LDR R0, =0x40080180 + LDR R1,[R0, #0xC] + LSLS R1, R1, #4 + LSRS R1, R1, #20 + CMP R1, #0 + BEQ BP3 + CMP R1, #5 + BEQ BP3 + CMP R1, #6 + BEQ BP3 +BP2 DSB + LDR R0, =0x20000000 + LDR R1, =0x05fa0004 + STR R1, [R0] + LDR R1, =0xe000ed00 + LDR R0, =0x05fa0004 + STR R0, [R1, #0xC] + DSB + B . +BP3 LDR R0, =0x20000000 + LDR R1, [R0] + LDR R0, =0x05fa0004 + CMP R0, R1 + BEQ BP4 + BX LR +BP4 LDR R0, =0x40088100 + LDR R1, =0x00000001 + STR R1, [R0] + LDR R0, =0x20000000 + LDR R1, =0x0 + STR R1, [R0] + BX LR + ENDP + +; Dummy Exception Handlers +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP + +HardFault_Handler PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP + +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP + +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP + +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + EXPORT LVD_BOD_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT EVWUP_IRQHandler [WEAK] + EXPORT EXTI0_1_IRQHandler [WEAK] + EXPORT EXTI2_3_IRQHandler [WEAK] + EXPORT EXTI4_15_IRQHandler [WEAK] + EXPORT COMP_IRQHandler [WEAK] + EXPORT ADC_IRQHandler [WEAK] + EXPORT MCTM0_IRQHandler [WEAK] + EXPORT GPTM1_IRQHandler [WEAK] + EXPORT GPTM0_IRQHandler [WEAK] + EXPORT SCTM0_IRQHandler [WEAK] + EXPORT SCTM1_IRQHandler [WEAK] + EXPORT SCTM2_IRQHandler [WEAK] + EXPORT SCTM3_IRQHandler [WEAK] + EXPORT PWM0_IRQHandler [WEAK] + EXPORT PWM1_IRQHandler [WEAK] + EXPORT BFTM0_IRQHandler [WEAK] + EXPORT BFTM1_IRQHandler [WEAK] + EXPORT I2C0_IRQHandler [WEAK] + EXPORT I2C1_IRQHandler [WEAK] + EXPORT I2C2_IRQHandler [WEAK] + EXPORT SPI0_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT QSPI_IRQHandler [WEAK] + EXPORT USART0_IRQHandler [WEAK] + EXPORT USART1_IRQHandler [WEAK] + EXPORT UART0_IRQHandler [WEAK] + EXPORT UART1_IRQHandler [WEAK] + EXPORT UART2_IRQHandler [WEAK] + EXPORT UART3_IRQHandler [WEAK] + EXPORT SCI_IRQHandler [WEAK] + EXPORT MIDI_IRQHandler [WEAK] + EXPORT I2S_IRQHandler [WEAK] + EXPORT AES_IRQHandler [WEAK] + EXPORT USB_IRQHandler [WEAK] + EXPORT PDMA_CH0_1_IRQHandler [WEAK] + EXPORT PDMA_CH2_5_IRQHandler [WEAK] + +LVD_BOD_IRQHandler +RTC_IRQHandler +FLASH_IRQHandler +EVWUP_IRQHandler +EXTI0_1_IRQHandler +EXTI2_3_IRQHandler +EXTI4_15_IRQHandler +COMP_IRQHandler +ADC_IRQHandler +MCTM0_IRQHandler +GPTM1_IRQHandler +GPTM0_IRQHandler +SCTM0_IRQHandler +SCTM1_IRQHandler +SCTM2_IRQHandler +SCTM3_IRQHandler +PWM0_IRQHandler +PWM1_IRQHandler +BFTM0_IRQHandler +BFTM1_IRQHandler +I2C0_IRQHandler +I2C1_IRQHandler +I2C2_IRQHandler +SPI0_IRQHandler +SPI1_IRQHandler +QSPI_IRQHandler +USART0_IRQHandler +USART1_IRQHandler +UART0_IRQHandler +UART1_IRQHandler +UART2_IRQHandler +UART3_IRQHandler +SCI_IRQHandler +MIDI_IRQHandler +I2S_IRQHandler +AES_IRQHandler +USB_IRQHandler +PDMA_CH0_1_IRQHandler +PDMA_CH2_5_IRQHandler + B . + ENDP + + ALIGN + +;******************************************************************************* +; User Stack and Heap initialization +;******************************************************************************* + IF :DEF:__MICROLIB + + EXPORT __HT_check_heap + EXPORT __HT_check_sp + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, = (Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + + ENDIF + + END diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f67741.s b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f67741.s new file mode 100644 index 0000000000..c653285b1f --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f67741.s @@ -0,0 +1,482 @@ +;/*---------------------------------------------------------------------------------------------------------*/ +;/* Holtek Semiconductor Inc. */ +;/* */ +;/* Copyright (C) Holtek Semiconductor Inc. */ +;/* All rights reserved. */ +;/* */ +;/*----------------------------------------------------------------------------------------------------------- +; File Name : startup_ht32f5xxxx_01.s +; Version : $Rev:: 6953 $ +; Date : $Date:: 2023-05-30 #$ +; Description : Startup code. +;-----------------------------------------------------------------------------------------------------------*/ + +; Supported Device +; ======================================== +; HT32F52220, HT32F52230 +; HT32F52231, HT32F52241 +; HT32F52331, HT32F52341 +; HT32F52342, HT32F52352 +; HT32F52243, HT32F52253 +; HT32F0008 +; HT32F52344, HT32F52354 +; HT32F0006 +; HT32F61352 +; HT50F32003 +; HT32F62030, HT32F62040, HT32F62050 +; HT32F67741 +; HT32F67232 +; HT32F67233 + +;/* <<< Use Configuration Wizard in Context Menu >>> */ + +;// HT32 Device +;// Select HT32 Device for the assembly setting. +;// Notice that the project's Asm Define has the higher priority. +;// <0=> By Project Asm Define +;// <1=> HT32F52220/30 +;// <2=> HT32F52231/41 +;// <3=> HT32F52331/41 +;// <4=> HT32F52342/52 +;// <5=> HT32F52243/53 +;// <6=> HT32F0008 +;// <9=> HT32F52344/54 +;// <10=> HT32F0006 +;// <10=> HT32F61352 +;// <4=> HT50F32003 +;// <2=> HT32F67741 +;// <1=> HT32F67232 +;// <1=> HT32F67233 +;// <1=> HT32F62030 +;// <2=> HT32F62040 +;// <5=> HT32F62050 +USE_HT32_CHIP_SET EQU 2 ; Notice that the project's Asm Define has the higher priority. + +_HT32FWID EQU 0xFFFFFFFF +;_HT32FWID EQU 0x00052220 +;_HT32FWID EQU 0x00052230 +;_HT32FWID EQU 0x00052231 +;_HT32FWID EQU 0x00052241 +;_HT32FWID EQU 0x00052331 +;_HT32FWID EQU 0x00052341 +;_HT32FWID EQU 0x00052342 +;_HT32FWID EQU 0x00052352 +;_HT32FWID EQU 0x00052243 +;_HT32FWID EQU 0x00052253 +;_HT32FWID EQU 0x00000008 +;_HT32FWID EQU 0x00052344 +;_HT32FWID EQU 0x00052354 +;_HT32FWID EQU 0x00000006 +;_HT32FWID EQU 0x00061352 +;_HT32FWID EQU 0x00032003 +;_HT32FWID EQU 0x00062030 +;_HT32FWID EQU 0x00062040 +;_HT32FWID EQU 0x00062050 +;_HT32FWID EQU 0x00067741 +;_HT32FWID EQU 0x00067232 +;_HT32FWID EQU 0x00067233 + +HT32F52220_30 EQU 1 +HT32F52231_41 EQU 2 +HT32F52331_41 EQU 3 +HT32F52342_52 EQU 4 +HT32F52243_53 EQU 5 +HT32F0008 EQU 6 +HT32F52344_54 EQU 9 +HT32F0006 EQU 10 +HT32F61352 EQU 10 +HT50F32003 EQU 4 +HT32F62030 EQU 1 +HT32F62040 EQU 2 +HT32F62050 EQU 5 +HT32F67741 EQU 2 +HT32F67232 EQU 1 +HT32F67233 EQU 1 + + IF USE_HT32_CHIP_SET=0 + ; Use project's Asm Define setting (default) + ELSE + IF :DEF:USE_HT32_CHIP + ; Use project's Asm Define setting (higher priority than the "USE_HT32_CHIP_SET") + ELSE + ; Use "USE_HT32_CHIP_SET" in the "startup_ht32xxxxx_xx.s" file +USE_HT32_CHIP EQU USE_HT32_CHIP_SET + ENDIF + ENDIF + +; Amount of memory (in bytes) allocated for Stack and Heap +; Tailor those values to your application needs +;// Stack Size (in Bytes, must 8 byte aligned) <0-16384:8> +Stack_Size EQU 512 + + AREA STACK, NOINIT, READWRITE, ALIGN = 3 +__HT_check_sp +Stack_Mem SPACE Stack_Size +__initial_sp + +;// Heap Size (in Bytes) <0-16384:8> +Heap_Size EQU 0 + + AREA HEAP, NOINIT, READWRITE, ALIGN = 3 +__HT_check_heap +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + PRESERVE8 + THUMB + +;******************************************************************************* +; Fill-up the Vector Table entries with the exceptions ISR address +;******************************************************************************* + AREA RESET, CODE, READONLY + EXPORT __Vectors +_RESERVED EQU 0xFFFFFFFF +__Vectors + DCD __initial_sp ; ---, 00, 0x000, Top address of Stack + DCD Reset_Handler ; ---, 01, 0x004, Reset Handler + DCD NMI_Handler ; -14, 02, 0x008, NMI Handler + DCD HardFault_Handler ; -13, 03, 0x00C, Hard Fault Handler + DCD _RESERVED ; ---, 04, 0x010, Reserved + DCD _RESERVED ; ---, 05, 0x014, Reserved + DCD _RESERVED ; ---, 06, 0x018, Reserved + DCD _RESERVED ; ---, 07, 0x01C, Reserved + DCD _HT32FWID ; ---, 08, 0x020, Reserved + DCD _RESERVED ; ---, 09, 0x024, Reserved + DCD _RESERVED ; ---, 10, 0x028, Reserved + DCD SVC_Handler ; -05, 11, 0x02C, SVC Handler + DCD _RESERVED ; ---, 12, 0x030, Reserved + DCD _RESERVED ; ---, 13, 0x034, Reserved + DCD PendSV_Handler ; -02, 14, 0x038, PendSV Handler + DCD SysTick_Handler ; -01, 15, 0x03C, SysTick Handler + + ; External Interrupt Handler + DCD LVD_BOD_IRQHandler ; 00, 16, 0x040, + IF (USE_HT32_CHIP=HT32F52220_30) + DCD _RESERVED ; 01, 17, 0x044, + ELSE + DCD RTC_IRQHandler ; 01, 17, 0x044, + ENDIF + DCD FLASH_IRQHandler ; 02, 18, 0x048, + DCD EVWUP_IRQHandler ; 03, 19, 0x04C, + DCD EXTI0_1_IRQHandler ; 04, 20, 0x050, + DCD EXTI2_3_IRQHandler ; 05, 21, 0x054, + DCD EXTI4_15_IRQHandler ; 06, 22, 0x058, + IF (USE_HT32_CHIP=HT32F52342_52) || (USE_HT32_CHIP=HT32F52344_54) + DCD COMP_IRQHandler ; 07, 23, 0x05C, + ELSE + DCD _RESERVED ; 07, 23, 0x05C, + ENDIF + IF (USE_HT32_CHIP=HT32F0008) + DCD _RESERVED ; 08, 24, 0x060, + ELSE + DCD ADC_IRQHandler ; 08, 24, 0x060, + ENDIF + IF (USE_HT32_CHIP=HT32F52243_53) + DCD I2C2_IRQHandler ; 09, 25, 0x064, + ELSE + DCD _RESERVED ; 09, 25, 0x064, + ENDIF + IF (USE_HT32_CHIP=HT32F52220_30) || (USE_HT32_CHIP=HT32F0008) || (USE_HT32_CHIP=HT32F0006) + DCD _RESERVED ; 10, 26, 0x068, + ELSE + DCD MCTM0_IRQHandler ; 10, 26, 0x068, + ENDIF + IF (USE_HT32_CHIP=HT32F52342_52) + DCD GPTM1_IRQHandler ; 11, 27, 0x06C, + ELSE + DCD _RESERVED ; 11, 27, 0x06C, + ENDIF + DCD GPTM0_IRQHandler ; 12, 28, 0x070, + IF (USE_HT32_CHIP=HT32F0008) + DCD _RESERVED ; 13, 29, 0x074, + DCD _RESERVED ; 14, 30, 0x078, + ELSE + DCD SCTM0_IRQHandler ; 13, 29, 0x074, + DCD SCTM1_IRQHandler ; 14, 30, 0x078, + ENDIF + IF (USE_HT32_CHIP=HT32F52231_41) || (USE_HT32_CHIP=HT32F52331_41) || (USE_HT32_CHIP=HT32F52243_53) || (USE_HT32_CHIP=HT32F0006) + DCD SCTM2_IRQHandler ; 15, 31, 0x07C, + DCD SCTM3_IRQHandler ; 16, 32, 0x080, + ENDIF + IF (USE_HT32_CHIP=HT32F0008) + DCD PWM0_IRQHandler ; 15, 31, 0x07C, + DCD PWM1_IRQHandler ; 16, 32, 0x080, + ENDIF + IF (USE_HT32_CHIP=HT32F52220_30) || (USE_HT32_CHIP=HT32F52342_52) || (USE_HT32_CHIP=HT32F52344_54) + DCD _RESERVED ; 15, 31, 0x07C, + DCD _RESERVED ; 16, 32, 0x080, + ENDIF + DCD BFTM0_IRQHandler ; 17, 33, 0x084, + IF (USE_HT32_CHIP=HT32F52220_30) + DCD _RESERVED ; 18, 34, 0x088, + ELSE + DCD BFTM1_IRQHandler ; 18, 34, 0x088, + ENDIF + DCD I2C0_IRQHandler ; 19, 35, 0x08C, + IF (USE_HT32_CHIP=HT32F52220_30) || (USE_HT32_CHIP=HT32F0008) || (USE_HT32_CHIP=HT32F52344_54) || (USE_HT32_CHIP=HT32F0006) + DCD _RESERVED ; 20, 36, 0x090, + ELSE + DCD I2C1_IRQHandler ; 20, 36, 0x090, + ENDIF + DCD SPI0_IRQHandler ; 21, 37, 0x094, + IF (USE_HT32_CHIP=HT32F52220_30) || (USE_HT32_CHIP=HT32F0008) + DCD _RESERVED ; 22, 38, 0x098, + ELSE + IF (USE_HT32_CHIP=HT32F0006) + DCD QSPI_IRQHandler ; 22, 38, 0x098, + ELSE + DCD SPI1_IRQHandler ; 22, 38, 0x098, + ENDIF + ENDIF + IF (USE_HT32_CHIP=HT32F52344_54) + DCD _RESERVED ; 23, 39, 0x09C, + ELSE + DCD USART0_IRQHandler ; 23, 39, 0x09C, + ENDIF + IF (USE_HT32_CHIP=HT32F52342_52) || (USE_HT32_CHIP=HT32F52243_53) + DCD USART1_IRQHandler ; 24, 40, 0x0A0, + ELSE + DCD _RESERVED ; 24, 40, 0x0A0, + ENDIF + DCD UART0_IRQHandler ; 25, 41, 0x0A4, + IF (USE_HT32_CHIP=HT32F52220_30) || (USE_HT32_CHIP=HT32F0008) || (USE_HT32_CHIP=HT32F0006) + DCD _RESERVED ; 26, 42, 0x0A8, + ELSE + DCD UART1_IRQHandler ; 26, 42, 0x0A8, + ENDIF + IF (USE_HT32_CHIP=HT32F52331_41) || (USE_HT32_CHIP=HT32F52342_52) + DCD SCI_IRQHandler ; 27, 43, 0x0AC, + ENDIF + IF (USE_HT32_CHIP=HT32F52243_53) + DCD UART2_IRQHandler ; 27, 43, 0x0AC, + ENDIF + IF (USE_HT32_CHIP=HT32F0006) + DCD MIDI_IRQHandler ; 27, 43, 0x0AC, + ENDIF + IF (USE_HT32_CHIP=HT32F0008) || (USE_HT32_CHIP=HT32F52344_54) + DCD _RESERVED ; 27, 43, 0xAC, + ENDIF + IF (USE_HT32_CHIP=HT32F52342_52) || (USE_HT32_CHIP=HT32F0006) + DCD I2S_IRQHandler ; 28, 44, 0x0B0, + ENDIF + IF (USE_HT32_CHIP=HT32F52331_41) || (USE_HT32_CHIP=HT32F52344_54) + DCD _RESERVED ; 28, 44, 0x0B0, + ENDIF + IF (USE_HT32_CHIP=HT32F52243_53) + DCD UART3_IRQHandler ; 28, 44, 0x0B0, + ENDIF + IF (USE_HT32_CHIP=HT32F0008) + DCD AES_IRQHandler ; 28, 44, 0x0B0, + ENDIF + IF (USE_HT32_CHIP=HT32F52331_41) || (USE_HT32_CHIP=HT32F52342_52) || (USE_HT32_CHIP=HT32F0008) || (USE_HT32_CHIP=HT32F52344_54) || (USE_HT32_CHIP=HT32F0006) + DCD USB_IRQHandler ; 29, 45, 0x0B4, + ENDIF + IF (USE_HT32_CHIP=HT32F52243_53) + DCD _RESERVED ; 29, 45, 0x0B4, + ENDIF + IF (USE_HT32_CHIP=HT32F52342_52) || (USE_HT32_CHIP=HT32F52243_53) || (USE_HT32_CHIP=HT32F0008) || (USE_HT32_CHIP=HT32F52344_54) || (USE_HT32_CHIP=HT32F0006) + DCD PDMA_CH0_1_IRQHandler ; 30, 46, 0x0B8, + DCD PDMA_CH2_5_IRQHandler ; 31, 47, 0x0BC, + ENDIF + +; Reset handler routine +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + LDR R0, =BootProcess + BLX R0 + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +BootProcess PROC + LDR R0, =0x40080300 + LDR R1,[R0, #0x10] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x14] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x18] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x1C] + CMP R1, #0 + BEQ BP2 +BP1 LDR R0, =0x40080180 + LDR R1,[R0, #0xC] + LSLS R1, R1, #4 + LSRS R1, R1, #20 + CMP R1, #0 + BEQ BP3 + CMP R1, #5 + BEQ BP3 + CMP R1, #6 + BEQ BP3 +BP2 DSB + LDR R0, =0x20000000 + LDR R1, =0x05fa0004 + STR R1, [R0] + LDR R1, =0xe000ed00 + LDR R0, =0x05fa0004 + STR R0, [R1, #0xC] + DSB + B . +BP3 LDR R0, =0x20000000 + LDR R1, [R0] + LDR R0, =0x05fa0004 + CMP R0, R1 + BEQ BP4 + BX LR +BP4 LDR R0, =0x40088100 + LDR R1, =0x00000001 + STR R1, [R0] + LDR R0, =0x20000000 + LDR R1, =0x0 + STR R1, [R0] + BX LR + ENDP + +; Dummy Exception Handlers +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP + +HardFault_Handler PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP + +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP + +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP + +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + EXPORT LVD_BOD_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT EVWUP_IRQHandler [WEAK] + EXPORT EXTI0_1_IRQHandler [WEAK] + EXPORT EXTI2_3_IRQHandler [WEAK] + EXPORT EXTI4_15_IRQHandler [WEAK] + EXPORT COMP_IRQHandler [WEAK] + EXPORT ADC_IRQHandler [WEAK] + EXPORT MCTM0_IRQHandler [WEAK] + EXPORT GPTM1_IRQHandler [WEAK] + EXPORT GPTM0_IRQHandler [WEAK] + EXPORT SCTM0_IRQHandler [WEAK] + EXPORT SCTM1_IRQHandler [WEAK] + EXPORT SCTM2_IRQHandler [WEAK] + EXPORT SCTM3_IRQHandler [WEAK] + EXPORT PWM0_IRQHandler [WEAK] + EXPORT PWM1_IRQHandler [WEAK] + EXPORT BFTM0_IRQHandler [WEAK] + EXPORT BFTM1_IRQHandler [WEAK] + EXPORT I2C0_IRQHandler [WEAK] + EXPORT I2C1_IRQHandler [WEAK] + EXPORT I2C2_IRQHandler [WEAK] + EXPORT SPI0_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT QSPI_IRQHandler [WEAK] + EXPORT USART0_IRQHandler [WEAK] + EXPORT USART1_IRQHandler [WEAK] + EXPORT UART0_IRQHandler [WEAK] + EXPORT UART1_IRQHandler [WEAK] + EXPORT UART2_IRQHandler [WEAK] + EXPORT UART3_IRQHandler [WEAK] + EXPORT SCI_IRQHandler [WEAK] + EXPORT MIDI_IRQHandler [WEAK] + EXPORT I2S_IRQHandler [WEAK] + EXPORT AES_IRQHandler [WEAK] + EXPORT USB_IRQHandler [WEAK] + EXPORT PDMA_CH0_1_IRQHandler [WEAK] + EXPORT PDMA_CH2_5_IRQHandler [WEAK] + +LVD_BOD_IRQHandler +RTC_IRQHandler +FLASH_IRQHandler +EVWUP_IRQHandler +EXTI0_1_IRQHandler +EXTI2_3_IRQHandler +EXTI4_15_IRQHandler +COMP_IRQHandler +ADC_IRQHandler +MCTM0_IRQHandler +GPTM1_IRQHandler +GPTM0_IRQHandler +SCTM0_IRQHandler +SCTM1_IRQHandler +SCTM2_IRQHandler +SCTM3_IRQHandler +PWM0_IRQHandler +PWM1_IRQHandler +BFTM0_IRQHandler +BFTM1_IRQHandler +I2C0_IRQHandler +I2C1_IRQHandler +I2C2_IRQHandler +SPI0_IRQHandler +SPI1_IRQHandler +QSPI_IRQHandler +USART0_IRQHandler +USART1_IRQHandler +UART0_IRQHandler +UART1_IRQHandler +UART2_IRQHandler +UART3_IRQHandler +SCI_IRQHandler +MIDI_IRQHandler +I2S_IRQHandler +AES_IRQHandler +USB_IRQHandler +PDMA_CH0_1_IRQHandler +PDMA_CH2_5_IRQHandler + B . + ENDP + + ALIGN + +;******************************************************************************* +; User Stack and Heap initialization +;******************************************************************************* + IF :DEF:__MICROLIB + + EXPORT __HT_check_heap + EXPORT __HT_check_sp + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, = (Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + + ENDIF + + END diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f67742.s b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f67742.s new file mode 100644 index 0000000000..cbaf7f3ee1 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f67742.s @@ -0,0 +1,350 @@ +;/*---------------------------------------------------------------------------------------------------------*/ +;/* Holtek Semiconductor Inc. */ +;/* */ +;/* Copyright (C) Holtek Semiconductor Inc. */ +;/* All rights reserved. */ +;/* */ +;/*----------------------------------------------------------------------------------------------------------- +; File Name : startup_ht32f5xxxx_05.s +; Version : $Rev:: 6993 $ +; Date : $Date:: 2023-06-26 #$ +; Description : Startup code. +;-----------------------------------------------------------------------------------------------------------*/ + +; Supported Device +; ======================================== +; HT32F57331, HT32F57341 +; HT32F57342, HT32F57352 +; HT32F59741 +; HT32F5828 +; HT32F67742 +; HT32F59746 + +;/* <<< Use Configuration Wizard in Context Menu >>> */ + +;// HT32 Device +;// Select HT32 Device for the assembly setting. +;// Notice that the project's Asm Define has the higher priority. +;// <0=> By Project Asm Define +;// <13=> HT32F57331/41 +;// <14=> HT32F57342/52 +;// <13=> HT32F59741 +;// <14=> HT32F5828 +;// <13=> HT32F67742 +;// <13=> HT32F59746 +USE_HT32_CHIP_SET EQU 13 ; Notice that the project's Asm Define has the higher priority. + +_HT32FWID EQU 0xFFFFFFFF +;_HT32FWID EQU 0x00057331 +;_HT32FWID EQU 0x00057341 +;_HT32FWID EQU 0x00057342 +;_HT32FWID EQU 0x00057352 +;_HT32FWID EQU 0x00059741 +;_HT32FWID EQU 0x00005828 +;_HT32FWID EQU 0x00067742 +;_HT32FWID EQU 0x00059746 + +HT32F57331_41 EQU 13 +HT32F57342_52 EQU 14 +HT32F59741 EQU 13 +HT32F5828 EQU 14 +HT32F67742 EQU 13 +HT32F59746 EQU 13 + + IF USE_HT32_CHIP_SET=0 + ; Use project's Asm Define setting (default) + ELSE + IF :DEF:USE_HT32_CHIP + ; Use project's Asm Define setting (higher priority than the "USE_HT32_CHIP_SET") + ELSE + ; Use "USE_HT32_CHIP_SET" in the "startup_ht32xxxxx_xx.s" file +USE_HT32_CHIP EQU USE_HT32_CHIP_SET + ENDIF + ENDIF + +; Amount of memory (in bytes) allocated for Stack and Heap +; Tailor those values to your application needs +;// Stack Size (in Bytes, must 8 byte aligned) <0-16384:8> +Stack_Size EQU 512 + + AREA STACK, NOINIT, READWRITE, ALIGN = 3 +__HT_check_sp +Stack_Mem SPACE Stack_Size +__initial_sp + +;// Heap Size (in Bytes) <0-16384:8> +Heap_Size EQU 0 + + AREA HEAP, NOINIT, READWRITE, ALIGN = 3 +__HT_check_heap +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + PRESERVE8 + THUMB + +;******************************************************************************* +; Fill-up the Vector Table entries with the exceptions ISR address +;******************************************************************************* + AREA RESET, CODE, READONLY + EXPORT __Vectors +_RESERVED EQU 0xFFFFFFFF +__Vectors + DCD __initial_sp ; ---, 00, 0x000, Top address of Stack + DCD Reset_Handler ; ---, 01, 0x004, Reset Handler + DCD NMI_Handler ; -14, 02, 0x008, NMI Handler + DCD HardFault_Handler ; -13, 03, 0x00C, Hard Fault Handler + DCD _RESERVED ; ---, 04, 0x010, Reserved + DCD _RESERVED ; ---, 05, 0x014, Reserved + DCD _RESERVED ; ---, 06, 0x018, Reserved + DCD _RESERVED ; ---, 07, 0x01C, Reserved + DCD _HT32FWID ; ---, 08, 0x020, Reserved + DCD _RESERVED ; ---, 09, 0x024, Reserved + DCD _RESERVED ; ---, 10, 0x028, Reserved + DCD SVC_Handler ; -05, 11, 0x02C, SVC Handler + DCD _RESERVED ; ---, 12, 0x030, Reserved + DCD _RESERVED ; ---, 13, 0x034, Reserved + DCD PendSV_Handler ; -02, 14, 0x038, PendSV Handler + DCD SysTick_Handler ; -01, 15, 0x03C, SysTick Handler + + ; External Interrupt Handler + DCD LVD_BOD_IRQHandler ; 00, 16, 0x040, + DCD RTC_IRQHandler ; 01, 17, 0x044, + DCD FLASH_IRQHandler ; 02, 18, 0x048, + DCD EVWUP_IRQHandler ; 03, 19, 0x04C, + DCD EXTI0_1_IRQHandler ; 04, 20, 0x050, + DCD EXTI2_3_IRQHandler ; 05, 21, 0x054, + DCD EXTI4_15_IRQHandler ; 06, 22, 0x058, + IF (USE_HT32_CHIP=HT32F57331_41) + DCD _RESERVED ; 07, 23, 0x05C, + ENDIF + IF (USE_HT32_CHIP=HT32F57342_52) + DCD COMP_DAC_IRQHandler ; 07, 23, 0x05C, + ENDIF + DCD ADC_IRQHandler ; 08, 24, 0x060, + IF (USE_HT32_CHIP=HT32F57331_41) + DCD _RESERVED ; 09, 25, 0x064, + ENDIF + IF (USE_HT32_CHIP=HT32F57342_52) + DCD AES_IRQHandler ; 09, 25, 0x064, + ENDIF + DCD _RESERVED ; 10, 26, 0x068, + DCD LCD_IRQHandler ; 11, 27, 0x06C, + DCD GPTM0_IRQHandler ; 12, 28, 0x070, + IF (USE_HT32_CHIP=HT32F57331_41) + DCD _RESERVED ; 13, 29, 0x074, + DCD _RESERVED ; 14, 30, 0x078, + ENDIF + IF (USE_HT32_CHIP=HT32F57342_52) + DCD SCTM0_IRQHandler ; 13, 29, 0x074, + DCD SCTM1_IRQHandler ; 14, 30, 0x078, + ENDIF + DCD PWM0_IRQHandler ; 15, 31, 0x07C, + DCD PWM1_IRQHandler ; 16, 32, 0x080, + DCD BFTM0_IRQHandler ; 17, 33, 0x084, + DCD BFTM1_IRQHandler ; 18, 34, 0x088, + DCD I2C0_IRQHandler ; 19, 35, 0x08C, + DCD I2C1_IRQHandler ; 20, 36, 0x090, + DCD SPI0_IRQHandler ; 21, 37, 0x094, + DCD SPI1_IRQHandler ; 22, 38, 0x098, + DCD USART0_IRQHandler ; 23, 39, 0x09C, + DCD _RESERVED ; 24, 40, 0x0A0, + DCD UART0_IRQHandler ; 25, 41, 0x0A4, + DCD UART1_IRQHandler ; 26, 42, 0x0A8, + DCD SCI_IRQHandler ; 27, 43, 0x0AC, + DCD I2S_IRQHandler ; 28, 44, 0x0B0, + DCD USB_IRQHandler ; 29, 45, 0x0B4, + IF (USE_HT32_CHIP=HT32F57331_41) + DCD _RESERVED ; 30, 46, 0x0B8, + DCD _RESERVED ; 31, 47, 0x0BC, + ENDIF + IF (USE_HT32_CHIP=HT32F57342_52) + DCD PDMA_CH0_1_IRQHandler ; 30, 46, 0x0B8, + DCD PDMA_CH2_5_IRQHandler ; 31, 47, 0x0BC, + ENDIF + +; Reset handler routine +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + LDR R0, =BootProcess + BLX R0 + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +BootProcess PROC + LDR R0, =0x40080300 + LDR R1,[R0, #0x10] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x14] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x18] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x1C] + CMP R1, #0 + BEQ BP2 +BP1 LDR R0, =0x40080180 + LDR R1,[R0, #0xC] + LSLS R1, R1, #4 + LSRS R1, R1, #20 + CMP R1, #0 + BEQ BP3 + CMP R1, #5 + BEQ BP3 + CMP R1, #6 + BEQ BP3 +BP2 DSB + LDR R0, =0x20000000 + LDR R1, =0x05fa0004 + STR R1, [R0] + LDR R1, =0xe000ed00 + LDR R0, =0x05fa0004 + STR R0, [R1, #0xC] + DSB + B . +BP3 LDR R0, =0x20000000 + LDR R1, [R0] + LDR R0, =0x05fa0004 + CMP R0, R1 + BEQ BP4 + BX LR +BP4 LDR R0, =0x40088100 + LDR R1, =0x00000001 + STR R1, [R0] + LDR R0, =0x20000000 + LDR R1, =0x0 + STR R1, [R0] + BX LR + ENDP + +; Dummy Exception Handlers +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP + +HardFault_Handler PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP + +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP + +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP + +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + EXPORT LVD_BOD_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT EVWUP_IRQHandler [WEAK] + EXPORT EXTI0_1_IRQHandler [WEAK] + EXPORT EXTI2_3_IRQHandler [WEAK] + EXPORT EXTI4_15_IRQHandler [WEAK] + EXPORT COMP_DAC_IRQHandler [WEAK] + EXPORT ADC_IRQHandler [WEAK] + EXPORT AES_IRQHandler [WEAK] + EXPORT LCD_IRQHandler [WEAK] + EXPORT GPTM0_IRQHandler [WEAK] + EXPORT SCTM0_IRQHandler [WEAK] + EXPORT SCTM1_IRQHandler [WEAK] + EXPORT PWM0_IRQHandler [WEAK] + EXPORT PWM1_IRQHandler [WEAK] + EXPORT BFTM0_IRQHandler [WEAK] + EXPORT BFTM1_IRQHandler [WEAK] + EXPORT I2C0_IRQHandler [WEAK] + EXPORT I2C1_IRQHandler [WEAK] + EXPORT SPI0_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT USART0_IRQHandler [WEAK] + EXPORT USART1_IRQHandler [WEAK] + EXPORT UART0_IRQHandler [WEAK] + EXPORT UART1_IRQHandler [WEAK] + EXPORT SCI_IRQHandler [WEAK] + EXPORT I2S_IRQHandler [WEAK] + EXPORT USB_IRQHandler [WEAK] + EXPORT PDMA_CH0_1_IRQHandler [WEAK] + EXPORT PDMA_CH2_5_IRQHandler [WEAK] + +LVD_BOD_IRQHandler +RTC_IRQHandler +FLASH_IRQHandler +EVWUP_IRQHandler +EXTI0_1_IRQHandler +EXTI2_3_IRQHandler +EXTI4_15_IRQHandler +COMP_DAC_IRQHandler +ADC_IRQHandler +AES_IRQHandler +LCD_IRQHandler +GPTM0_IRQHandler +SCTM0_IRQHandler +SCTM1_IRQHandler +PWM0_IRQHandler +PWM1_IRQHandler +BFTM0_IRQHandler +BFTM1_IRQHandler +I2C0_IRQHandler +I2C1_IRQHandler +SPI0_IRQHandler +SPI1_IRQHandler +USART0_IRQHandler +USART1_IRQHandler +UART0_IRQHandler +UART1_IRQHandler +SCI_IRQHandler +I2S_IRQHandler +USB_IRQHandler +PDMA_CH0_1_IRQHandler +PDMA_CH2_5_IRQHandler + B . + ENDP + + ALIGN + +;******************************************************************************* +; User Stack and Heap initialization +;******************************************************************************* + IF :DEF:__MICROLIB + + EXPORT __HT_check_heap + EXPORT __HT_check_sp + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, = (Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + + ENDIF + + END diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht50f32002.s b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht50f32002.s new file mode 100644 index 0000000000..a86606d966 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht50f32002.s @@ -0,0 +1,327 @@ +;/*---------------------------------------------------------------------------------------------------------*/ +;/* Holtek Semiconductor Inc. */ +;/* */ +;/* Copyright (C) Holtek Semiconductor Inc. */ +;/* All rights reserved. */ +;/* */ +;/*----------------------------------------------------------------------------------------------------------- +; File Name : startup_ht32f5xxxx_02.s +; Version : $Rev:: 7119 $ +; Date : $Date:: 2023-08-15 #$ +; Description : Startup code. +;-----------------------------------------------------------------------------------------------------------*/ + +; Supported Device +; ======================================== +; HT32F50220, HT32F50230 +; HT32F50231, HT32F50241 +; HT50F32002 +; HT32F59041 +; HF5032 +; HT32F61641 +; HT32F59046 +; HT32F61041 + +;/* <<< Use Configuration Wizard in Context Menu >>> */ + +;// HT32 Device +;// Select HT32 Device for the assembly setting. +;// Notice that the project's Asm Define has the higher priority. +;// <0=> By Project Asm Define +;// <7=> HT32F50220/30 +;// <8=> HT32F50231/41 +;// <7=> HT50F32002 +;// <8=> HT32F59041 +;// <7=> HF5032 +;// <8=> HT32F61641 +;// <8=> HT32F59046 +;// <8=> HT32F61041 +USE_HT32_CHIP_SET EQU 7 ; Notice that the project's Asm Define has the higher priority. + +_HT32FWID EQU 0xFFFFFFFF +;_HT32FWID EQU 0x00050220 +;_HT32FWID EQU 0x00050230 +;_HT32FWID EQU 0x00050231 +;_HT32FWID EQU 0x00050241 +;_HT32FWID EQU 0x00032002 +;_HT32FWID EQU 0x00059041 +;_HT32FWID EQU 0x000F5032 +;_HT32FWID EQU 0x00061641 +;_HT32FWID EQU 0x00059046 +;_HT32FWID EQU 0x00061041 + +HT32F50220_30 EQU 7 +HT32F50231_41 EQU 8 +HT50F32002 EQU 7 +HT32F59041 EQU 8 +HF5032 EQU 7 +HT32F61641 EQU 8 +HT32F59046 EQU 8 +HT32F61041 EQU 8 + + IF USE_HT32_CHIP_SET=0 + ; Use project's Asm Define setting (default) + ELSE + IF :DEF:USE_HT32_CHIP + ; Use project's Asm Define setting (higher priority than the "USE_HT32_CHIP_SET") + ELSE + ; Use "USE_HT32_CHIP_SET" in the "startup_ht32xxxxx_xx.s" file +USE_HT32_CHIP EQU USE_HT32_CHIP_SET + ENDIF + ENDIF + +; Amount of memory (in bytes) allocated for Stack and Heap +; Tailor those values to your application needs +;// Stack Size (in Bytes, must 8 byte aligned) <0-4096:8> +Stack_Size EQU 512 + + AREA STACK, NOINIT, READWRITE, ALIGN = 3 +__HT_check_sp +Stack_Mem SPACE Stack_Size +__initial_sp + +;// Heap Size (in Bytes) <0-4096:8> +Heap_Size EQU 0 + + AREA HEAP, NOINIT, READWRITE, ALIGN = 3 +__HT_check_heap +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + PRESERVE8 + THUMB + +;******************************************************************************* +; Fill-up the Vector Table entries with the exceptions ISR address +;******************************************************************************* + AREA RESET, CODE, READONLY + EXPORT __Vectors +_RESERVED EQU 0xFFFFFFFF +__Vectors + DCD __initial_sp ; ---, 00, 0x000, Top address of Stack + DCD Reset_Handler ; ---, 01, 0x004, Reset Handler + DCD NMI_Handler ; -14, 02, 0x008, NMI Handler + DCD HardFault_Handler ; -13, 03, 0x00C, Hard Fault Handler + DCD _RESERVED ; ---, 04, 0x010, Reserved + DCD _RESERVED ; ---, 05, 0x014, Reserved + DCD _RESERVED ; ---, 06, 0x018, Reserved + DCD _RESERVED ; ---, 07, 0x01C, Reserved + DCD _HT32FWID ; ---, 08, 0x020, Reserved + DCD _RESERVED ; ---, 09, 0x024, Reserved + DCD _RESERVED ; ---, 10, 0x028, Reserved + DCD SVC_Handler ; -05, 11, 0x02C, SVC Handler + DCD _RESERVED ; ---, 12, 0x030, Reserved + DCD _RESERVED ; ---, 13, 0x034, Reserved + DCD PendSV_Handler ; -02, 14, 0x038, PendSV Handler + DCD SysTick_Handler ; -01, 15, 0x03C, SysTick Handler + + ; External Interrupt Handler + DCD LVD_BOD_IRQHandler ; 00, 16, 0x040, + DCD RTC_IRQHandler ; 01, 17, 0x044, + DCD FLASH_IRQHandler ; 02, 18, 0x048, + DCD EVWUP_IRQHandler ; 03, 19, 0x04C, + DCD EXTI0_1_IRQHandler ; 04, 20, 0x050, + DCD EXTI2_3_IRQHandler ; 05, 21, 0x054, + DCD EXTI4_15_IRQHandler ; 06, 22, 0x058, + DCD _RESERVED ; 07, 23, 0x05C, + DCD ADC_IRQHandler ; 08, 24, 0x060, + DCD _RESERVED ; 09, 25, 0x064, + IF (USE_HT32_CHIP=HT32F50220_30) + DCD _RESERVED ; 10, 26, 0x068, + ELSE + DCD MCTM0_IRQHandler ; 10, 26, 0x068, + ENDIF + DCD _RESERVED ; 11, 27, 0x06C, + DCD GPTM0_IRQHandler ; 12, 28, 0x070, + DCD _RESERVED ; 13, 29, 0x074, + DCD _RESERVED ; 14, 30, 0x078, + DCD PWM0_IRQHandler ; 15, 31, 0x07C, + DCD PWM1_IRQHandler ; 16, 32, 0x080, + DCD BFTM0_IRQHandler ; 17, 33, 0x084, + IF (USE_HT32_CHIP=HT32F50220_30) + DCD _RESERVED ; 18, 34, 0x088, + ELSE + DCD BFTM1_IRQHandler ; 18, 34, 0x088, + ENDIF + DCD I2C0_IRQHandler ; 19, 35, 0x08C, + IF (USE_HT32_CHIP=HT32F50220_30) + DCD _RESERVED ; 20, 36, 0x090, + ELSE + DCD I2C1_IRQHandler ; 20, 36, 0x090, + ENDIF + DCD SPI0_IRQHandler ; 21, 37, 0x094, + DCD SPI1_IRQHandler ; 22, 38, 0x098, + IF (USE_HT32_CHIP=HT32F50220_30) + DCD _RESERVED ; 23, 39, 0x09C, + ELSE + DCD USART0_IRQHandler ; 23, 39, 0x09C, + ENDIF + DCD _RESERVED ; 24, 40, 0x0A0, + DCD UART0_IRQHandler ; 25, 41, 0x0A4, + DCD UART1_IRQHandler ; 26, 42, 0x0A8, + +; Reset handler routine +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + LDR R0, =BootProcess + BLX R0 + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +BootProcess PROC + LDR R0, =0x40080300 + LDR R1,[R0, #0x10] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x14] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x18] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x1C] + CMP R1, #0 + BEQ BP2 +BP1 LDR R0, =0x40080180 + LDR R1,[R0, #0xC] + LSLS R1, R1, #4 + LSRS R1, R1, #20 + CMP R1, #0 + BEQ BP3 + CMP R1, #5 + BEQ BP3 + CMP R1, #6 + BEQ BP3 +BP2 DSB + LDR R0, =0x20000000 + LDR R1, =0x05fa0004 + STR R1, [R0] + LDR R1, =0xe000ed00 + LDR R0, =0x05fa0004 + STR R0, [R1, #0xC] + DSB + B . +BP3 LDR R0, =0x20000000 + LDR R1, [R0] + LDR R0, =0x05fa0004 + CMP R0, R1 + BEQ BP4 + BX LR +BP4 LDR R0, =0x40088100 + LDR R1, =0x00000001 + STR R1, [R0] + LDR R0, =0x20000000 + LDR R1, =0x0 + STR R1, [R0] + BX LR + ENDP + +; Dummy Exception Handlers +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP + +HardFault_Handler PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP + +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP + +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP + +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + EXPORT LVD_BOD_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT EVWUP_IRQHandler [WEAK] + EXPORT EXTI0_1_IRQHandler [WEAK] + EXPORT EXTI2_3_IRQHandler [WEAK] + EXPORT EXTI4_15_IRQHandler [WEAK] + EXPORT ADC_IRQHandler [WEAK] + EXPORT MCTM0_IRQHandler [WEAK] + EXPORT GPTM0_IRQHandler [WEAK] + EXPORT PWM0_IRQHandler [WEAK] + EXPORT PWM1_IRQHandler [WEAK] + EXPORT BFTM0_IRQHandler [WEAK] + EXPORT BFTM1_IRQHandler [WEAK] + EXPORT I2C0_IRQHandler [WEAK] + EXPORT I2C1_IRQHandler [WEAK] + EXPORT SPI0_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT USART0_IRQHandler [WEAK] + EXPORT UART0_IRQHandler [WEAK] + EXPORT UART1_IRQHandler [WEAK] + +LVD_BOD_IRQHandler +RTC_IRQHandler +FLASH_IRQHandler +EVWUP_IRQHandler +EXTI0_1_IRQHandler +EXTI2_3_IRQHandler +EXTI4_15_IRQHandler +ADC_IRQHandler +MCTM0_IRQHandler +GPTM0_IRQHandler +PWM0_IRQHandler +PWM1_IRQHandler +BFTM0_IRQHandler +BFTM1_IRQHandler +I2C0_IRQHandler +I2C1_IRQHandler +SPI0_IRQHandler +SPI1_IRQHandler +USART0_IRQHandler +UART0_IRQHandler +UART1_IRQHandler + B . + ENDP + + ALIGN + +;******************************************************************************* +; User Stack and Heap initialization +;******************************************************************************* + IF :DEF:__MICROLIB + + EXPORT __HT_check_heap + EXPORT __HT_check_sp + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, = (Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + + ENDIF + + END diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht50f32003.s b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht50f32003.s new file mode 100644 index 0000000000..2285fed9c8 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht50f32003.s @@ -0,0 +1,482 @@ +;/*---------------------------------------------------------------------------------------------------------*/ +;/* Holtek Semiconductor Inc. */ +;/* */ +;/* Copyright (C) Holtek Semiconductor Inc. */ +;/* All rights reserved. */ +;/* */ +;/*----------------------------------------------------------------------------------------------------------- +; File Name : startup_ht32f5xxxx_01.s +; Version : $Rev:: 6953 $ +; Date : $Date:: 2023-05-30 #$ +; Description : Startup code. +;-----------------------------------------------------------------------------------------------------------*/ + +; Supported Device +; ======================================== +; HT32F52220, HT32F52230 +; HT32F52231, HT32F52241 +; HT32F52331, HT32F52341 +; HT32F52342, HT32F52352 +; HT32F52243, HT32F52253 +; HT32F0008 +; HT32F52344, HT32F52354 +; HT32F0006 +; HT32F61352 +; HT50F32003 +; HT32F62030, HT32F62040, HT32F62050 +; HT32F67741 +; HT32F67232 +; HT32F67233 + +;/* <<< Use Configuration Wizard in Context Menu >>> */ + +;// HT32 Device +;// Select HT32 Device for the assembly setting. +;// Notice that the project's Asm Define has the higher priority. +;// <0=> By Project Asm Define +;// <1=> HT32F52220/30 +;// <2=> HT32F52231/41 +;// <3=> HT32F52331/41 +;// <4=> HT32F52342/52 +;// <5=> HT32F52243/53 +;// <6=> HT32F0008 +;// <9=> HT32F52344/54 +;// <10=> HT32F0006 +;// <10=> HT32F61352 +;// <4=> HT50F32003 +;// <2=> HT32F67741 +;// <1=> HT32F67232 +;// <1=> HT32F67233 +;// <1=> HT32F62030 +;// <2=> HT32F62040 +;// <5=> HT32F62050 +USE_HT32_CHIP_SET EQU 4 ; Notice that the project's Asm Define has the higher priority. + +_HT32FWID EQU 0xFFFFFFFF +;_HT32FWID EQU 0x00052220 +;_HT32FWID EQU 0x00052230 +;_HT32FWID EQU 0x00052231 +;_HT32FWID EQU 0x00052241 +;_HT32FWID EQU 0x00052331 +;_HT32FWID EQU 0x00052341 +;_HT32FWID EQU 0x00052342 +;_HT32FWID EQU 0x00052352 +;_HT32FWID EQU 0x00052243 +;_HT32FWID EQU 0x00052253 +;_HT32FWID EQU 0x00000008 +;_HT32FWID EQU 0x00052344 +;_HT32FWID EQU 0x00052354 +;_HT32FWID EQU 0x00000006 +;_HT32FWID EQU 0x00061352 +;_HT32FWID EQU 0x00032003 +;_HT32FWID EQU 0x00062030 +;_HT32FWID EQU 0x00062040 +;_HT32FWID EQU 0x00062050 +;_HT32FWID EQU 0x00067741 +;_HT32FWID EQU 0x00067232 +;_HT32FWID EQU 0x00067233 + +HT32F52220_30 EQU 1 +HT32F52231_41 EQU 2 +HT32F52331_41 EQU 3 +HT32F52342_52 EQU 4 +HT32F52243_53 EQU 5 +HT32F0008 EQU 6 +HT32F52344_54 EQU 9 +HT32F0006 EQU 10 +HT32F61352 EQU 10 +HT50F32003 EQU 4 +HT32F62030 EQU 1 +HT32F62040 EQU 2 +HT32F62050 EQU 5 +HT32F67741 EQU 2 +HT32F67232 EQU 1 +HT32F67233 EQU 1 + + IF USE_HT32_CHIP_SET=0 + ; Use project's Asm Define setting (default) + ELSE + IF :DEF:USE_HT32_CHIP + ; Use project's Asm Define setting (higher priority than the "USE_HT32_CHIP_SET") + ELSE + ; Use "USE_HT32_CHIP_SET" in the "startup_ht32xxxxx_xx.s" file +USE_HT32_CHIP EQU USE_HT32_CHIP_SET + ENDIF + ENDIF + +; Amount of memory (in bytes) allocated for Stack and Heap +; Tailor those values to your application needs +;// Stack Size (in Bytes, must 8 byte aligned) <0-16384:8> +Stack_Size EQU 512 + + AREA STACK, NOINIT, READWRITE, ALIGN = 3 +__HT_check_sp +Stack_Mem SPACE Stack_Size +__initial_sp + +;// Heap Size (in Bytes) <0-16384:8> +Heap_Size EQU 0 + + AREA HEAP, NOINIT, READWRITE, ALIGN = 3 +__HT_check_heap +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + PRESERVE8 + THUMB + +;******************************************************************************* +; Fill-up the Vector Table entries with the exceptions ISR address +;******************************************************************************* + AREA RESET, CODE, READONLY + EXPORT __Vectors +_RESERVED EQU 0xFFFFFFFF +__Vectors + DCD __initial_sp ; ---, 00, 0x000, Top address of Stack + DCD Reset_Handler ; ---, 01, 0x004, Reset Handler + DCD NMI_Handler ; -14, 02, 0x008, NMI Handler + DCD HardFault_Handler ; -13, 03, 0x00C, Hard Fault Handler + DCD _RESERVED ; ---, 04, 0x010, Reserved + DCD _RESERVED ; ---, 05, 0x014, Reserved + DCD _RESERVED ; ---, 06, 0x018, Reserved + DCD _RESERVED ; ---, 07, 0x01C, Reserved + DCD _HT32FWID ; ---, 08, 0x020, Reserved + DCD _RESERVED ; ---, 09, 0x024, Reserved + DCD _RESERVED ; ---, 10, 0x028, Reserved + DCD SVC_Handler ; -05, 11, 0x02C, SVC Handler + DCD _RESERVED ; ---, 12, 0x030, Reserved + DCD _RESERVED ; ---, 13, 0x034, Reserved + DCD PendSV_Handler ; -02, 14, 0x038, PendSV Handler + DCD SysTick_Handler ; -01, 15, 0x03C, SysTick Handler + + ; External Interrupt Handler + DCD LVD_BOD_IRQHandler ; 00, 16, 0x040, + IF (USE_HT32_CHIP=HT32F52220_30) + DCD _RESERVED ; 01, 17, 0x044, + ELSE + DCD RTC_IRQHandler ; 01, 17, 0x044, + ENDIF + DCD FLASH_IRQHandler ; 02, 18, 0x048, + DCD EVWUP_IRQHandler ; 03, 19, 0x04C, + DCD EXTI0_1_IRQHandler ; 04, 20, 0x050, + DCD EXTI2_3_IRQHandler ; 05, 21, 0x054, + DCD EXTI4_15_IRQHandler ; 06, 22, 0x058, + IF (USE_HT32_CHIP=HT32F52342_52) || (USE_HT32_CHIP=HT32F52344_54) + DCD COMP_IRQHandler ; 07, 23, 0x05C, + ELSE + DCD _RESERVED ; 07, 23, 0x05C, + ENDIF + IF (USE_HT32_CHIP=HT32F0008) + DCD _RESERVED ; 08, 24, 0x060, + ELSE + DCD ADC_IRQHandler ; 08, 24, 0x060, + ENDIF + IF (USE_HT32_CHIP=HT32F52243_53) + DCD I2C2_IRQHandler ; 09, 25, 0x064, + ELSE + DCD _RESERVED ; 09, 25, 0x064, + ENDIF + IF (USE_HT32_CHIP=HT32F52220_30) || (USE_HT32_CHIP=HT32F0008) || (USE_HT32_CHIP=HT32F0006) + DCD _RESERVED ; 10, 26, 0x068, + ELSE + DCD MCTM0_IRQHandler ; 10, 26, 0x068, + ENDIF + IF (USE_HT32_CHIP=HT32F52342_52) + DCD GPTM1_IRQHandler ; 11, 27, 0x06C, + ELSE + DCD _RESERVED ; 11, 27, 0x06C, + ENDIF + DCD GPTM0_IRQHandler ; 12, 28, 0x070, + IF (USE_HT32_CHIP=HT32F0008) + DCD _RESERVED ; 13, 29, 0x074, + DCD _RESERVED ; 14, 30, 0x078, + ELSE + DCD SCTM0_IRQHandler ; 13, 29, 0x074, + DCD SCTM1_IRQHandler ; 14, 30, 0x078, + ENDIF + IF (USE_HT32_CHIP=HT32F52231_41) || (USE_HT32_CHIP=HT32F52331_41) || (USE_HT32_CHIP=HT32F52243_53) || (USE_HT32_CHIP=HT32F0006) + DCD SCTM2_IRQHandler ; 15, 31, 0x07C, + DCD SCTM3_IRQHandler ; 16, 32, 0x080, + ENDIF + IF (USE_HT32_CHIP=HT32F0008) + DCD PWM0_IRQHandler ; 15, 31, 0x07C, + DCD PWM1_IRQHandler ; 16, 32, 0x080, + ENDIF + IF (USE_HT32_CHIP=HT32F52220_30) || (USE_HT32_CHIP=HT32F52342_52) || (USE_HT32_CHIP=HT32F52344_54) + DCD _RESERVED ; 15, 31, 0x07C, + DCD _RESERVED ; 16, 32, 0x080, + ENDIF + DCD BFTM0_IRQHandler ; 17, 33, 0x084, + IF (USE_HT32_CHIP=HT32F52220_30) + DCD _RESERVED ; 18, 34, 0x088, + ELSE + DCD BFTM1_IRQHandler ; 18, 34, 0x088, + ENDIF + DCD I2C0_IRQHandler ; 19, 35, 0x08C, + IF (USE_HT32_CHIP=HT32F52220_30) || (USE_HT32_CHIP=HT32F0008) || (USE_HT32_CHIP=HT32F52344_54) || (USE_HT32_CHIP=HT32F0006) + DCD _RESERVED ; 20, 36, 0x090, + ELSE + DCD I2C1_IRQHandler ; 20, 36, 0x090, + ENDIF + DCD SPI0_IRQHandler ; 21, 37, 0x094, + IF (USE_HT32_CHIP=HT32F52220_30) || (USE_HT32_CHIP=HT32F0008) + DCD _RESERVED ; 22, 38, 0x098, + ELSE + IF (USE_HT32_CHIP=HT32F0006) + DCD QSPI_IRQHandler ; 22, 38, 0x098, + ELSE + DCD SPI1_IRQHandler ; 22, 38, 0x098, + ENDIF + ENDIF + IF (USE_HT32_CHIP=HT32F52344_54) + DCD _RESERVED ; 23, 39, 0x09C, + ELSE + DCD USART0_IRQHandler ; 23, 39, 0x09C, + ENDIF + IF (USE_HT32_CHIP=HT32F52342_52) || (USE_HT32_CHIP=HT32F52243_53) + DCD USART1_IRQHandler ; 24, 40, 0x0A0, + ELSE + DCD _RESERVED ; 24, 40, 0x0A0, + ENDIF + DCD UART0_IRQHandler ; 25, 41, 0x0A4, + IF (USE_HT32_CHIP=HT32F52220_30) || (USE_HT32_CHIP=HT32F0008) || (USE_HT32_CHIP=HT32F0006) + DCD _RESERVED ; 26, 42, 0x0A8, + ELSE + DCD UART1_IRQHandler ; 26, 42, 0x0A8, + ENDIF + IF (USE_HT32_CHIP=HT32F52331_41) || (USE_HT32_CHIP=HT32F52342_52) + DCD SCI_IRQHandler ; 27, 43, 0x0AC, + ENDIF + IF (USE_HT32_CHIP=HT32F52243_53) + DCD UART2_IRQHandler ; 27, 43, 0x0AC, + ENDIF + IF (USE_HT32_CHIP=HT32F0006) + DCD MIDI_IRQHandler ; 27, 43, 0x0AC, + ENDIF + IF (USE_HT32_CHIP=HT32F0008) || (USE_HT32_CHIP=HT32F52344_54) + DCD _RESERVED ; 27, 43, 0xAC, + ENDIF + IF (USE_HT32_CHIP=HT32F52342_52) || (USE_HT32_CHIP=HT32F0006) + DCD I2S_IRQHandler ; 28, 44, 0x0B0, + ENDIF + IF (USE_HT32_CHIP=HT32F52331_41) || (USE_HT32_CHIP=HT32F52344_54) + DCD _RESERVED ; 28, 44, 0x0B0, + ENDIF + IF (USE_HT32_CHIP=HT32F52243_53) + DCD UART3_IRQHandler ; 28, 44, 0x0B0, + ENDIF + IF (USE_HT32_CHIP=HT32F0008) + DCD AES_IRQHandler ; 28, 44, 0x0B0, + ENDIF + IF (USE_HT32_CHIP=HT32F52331_41) || (USE_HT32_CHIP=HT32F52342_52) || (USE_HT32_CHIP=HT32F0008) || (USE_HT32_CHIP=HT32F52344_54) || (USE_HT32_CHIP=HT32F0006) + DCD USB_IRQHandler ; 29, 45, 0x0B4, + ENDIF + IF (USE_HT32_CHIP=HT32F52243_53) + DCD _RESERVED ; 29, 45, 0x0B4, + ENDIF + IF (USE_HT32_CHIP=HT32F52342_52) || (USE_HT32_CHIP=HT32F52243_53) || (USE_HT32_CHIP=HT32F0008) || (USE_HT32_CHIP=HT32F52344_54) || (USE_HT32_CHIP=HT32F0006) + DCD PDMA_CH0_1_IRQHandler ; 30, 46, 0x0B8, + DCD PDMA_CH2_5_IRQHandler ; 31, 47, 0x0BC, + ENDIF + +; Reset handler routine +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + LDR R0, =BootProcess + BLX R0 + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +BootProcess PROC + LDR R0, =0x40080300 + LDR R1,[R0, #0x10] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x14] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x18] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x1C] + CMP R1, #0 + BEQ BP2 +BP1 LDR R0, =0x40080180 + LDR R1,[R0, #0xC] + LSLS R1, R1, #4 + LSRS R1, R1, #20 + CMP R1, #0 + BEQ BP3 + CMP R1, #5 + BEQ BP3 + CMP R1, #6 + BEQ BP3 +BP2 DSB + LDR R0, =0x20000000 + LDR R1, =0x05fa0004 + STR R1, [R0] + LDR R1, =0xe000ed00 + LDR R0, =0x05fa0004 + STR R0, [R1, #0xC] + DSB + B . +BP3 LDR R0, =0x20000000 + LDR R1, [R0] + LDR R0, =0x05fa0004 + CMP R0, R1 + BEQ BP4 + BX LR +BP4 LDR R0, =0x40088100 + LDR R1, =0x00000001 + STR R1, [R0] + LDR R0, =0x20000000 + LDR R1, =0x0 + STR R1, [R0] + BX LR + ENDP + +; Dummy Exception Handlers +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP + +HardFault_Handler PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP + +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP + +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP + +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + EXPORT LVD_BOD_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT EVWUP_IRQHandler [WEAK] + EXPORT EXTI0_1_IRQHandler [WEAK] + EXPORT EXTI2_3_IRQHandler [WEAK] + EXPORT EXTI4_15_IRQHandler [WEAK] + EXPORT COMP_IRQHandler [WEAK] + EXPORT ADC_IRQHandler [WEAK] + EXPORT MCTM0_IRQHandler [WEAK] + EXPORT GPTM1_IRQHandler [WEAK] + EXPORT GPTM0_IRQHandler [WEAK] + EXPORT SCTM0_IRQHandler [WEAK] + EXPORT SCTM1_IRQHandler [WEAK] + EXPORT SCTM2_IRQHandler [WEAK] + EXPORT SCTM3_IRQHandler [WEAK] + EXPORT PWM0_IRQHandler [WEAK] + EXPORT PWM1_IRQHandler [WEAK] + EXPORT BFTM0_IRQHandler [WEAK] + EXPORT BFTM1_IRQHandler [WEAK] + EXPORT I2C0_IRQHandler [WEAK] + EXPORT I2C1_IRQHandler [WEAK] + EXPORT I2C2_IRQHandler [WEAK] + EXPORT SPI0_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT QSPI_IRQHandler [WEAK] + EXPORT USART0_IRQHandler [WEAK] + EXPORT USART1_IRQHandler [WEAK] + EXPORT UART0_IRQHandler [WEAK] + EXPORT UART1_IRQHandler [WEAK] + EXPORT UART2_IRQHandler [WEAK] + EXPORT UART3_IRQHandler [WEAK] + EXPORT SCI_IRQHandler [WEAK] + EXPORT MIDI_IRQHandler [WEAK] + EXPORT I2S_IRQHandler [WEAK] + EXPORT AES_IRQHandler [WEAK] + EXPORT USB_IRQHandler [WEAK] + EXPORT PDMA_CH0_1_IRQHandler [WEAK] + EXPORT PDMA_CH2_5_IRQHandler [WEAK] + +LVD_BOD_IRQHandler +RTC_IRQHandler +FLASH_IRQHandler +EVWUP_IRQHandler +EXTI0_1_IRQHandler +EXTI2_3_IRQHandler +EXTI4_15_IRQHandler +COMP_IRQHandler +ADC_IRQHandler +MCTM0_IRQHandler +GPTM1_IRQHandler +GPTM0_IRQHandler +SCTM0_IRQHandler +SCTM1_IRQHandler +SCTM2_IRQHandler +SCTM3_IRQHandler +PWM0_IRQHandler +PWM1_IRQHandler +BFTM0_IRQHandler +BFTM1_IRQHandler +I2C0_IRQHandler +I2C1_IRQHandler +I2C2_IRQHandler +SPI0_IRQHandler +SPI1_IRQHandler +QSPI_IRQHandler +USART0_IRQHandler +USART1_IRQHandler +UART0_IRQHandler +UART1_IRQHandler +UART2_IRQHandler +UART3_IRQHandler +SCI_IRQHandler +MIDI_IRQHandler +I2S_IRQHandler +AES_IRQHandler +USB_IRQHandler +PDMA_CH0_1_IRQHandler +PDMA_CH2_5_IRQHandler + B . + ENDP + + ALIGN + +;******************************************************************************* +; User Stack and Heap initialization +;******************************************************************************* + IF :DEF:__MICROLIB + + EXPORT __HT_check_heap + EXPORT __HT_check_sp + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, = (Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + + ENDIF + + END diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht50f3200s.s b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht50f3200s.s new file mode 100644 index 0000000000..b986536809 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht50f3200s.s @@ -0,0 +1,278 @@ +;/*---------------------------------------------------------------------------------------------------------*/ +;/* Holtek Semiconductor Inc. */ +;/* */ +;/* Copyright (C) Holtek Semiconductor Inc. */ +;/* All rights reserved. */ +;/* */ +;/*----------------------------------------------------------------------------------------------------------- +; File Name : startup_ht32f5xxxx_08.s +; Version : $Rev:: 6877 $ +; Date : $Date:: 2023-05-04 #$ +; Description : Startup code. +;-----------------------------------------------------------------------------------------------------------*/ + +; Supported Device +; ======================================== +; HT32F65230, HT32F65240 +; HT32F65232 +; MXTX6306 +; HT50F3200S + +;/* <<< Use Configuration Wizard in Context Menu >>> */ + +;// HT32 Device +;// Select HT32 Device for the assembly setting. +;// Notice that the project's Asm Define has the higher priority. +;// <0=> By Project Asm Define +;// <12=> HT32F65230_40 +;// <18=> HT32F65232 +;// <12=> MXTX6306 +;// <12=> HT50F3200S +USE_HT32_CHIP_SET EQU 12 ; Notice that the project's Asm Define has the higher priority. + +_HT32FWID EQU 0xFFFFFFFF +;_HT32FWID EQU 0x00065230 +;_HT32FWID EQU 0x00065240 +;_HT32FWID EQU 0x00065232 +;_HT32FWID EQU 0x00006306 +;_HT32FWID EQU 0x0003200F + +HT32F65230_40 EQU 12 +HT32F65232 EQU 18 +MXTX6306 EQU 12 +HT50F3200S EQU 12 + + IF USE_HT32_CHIP_SET=0 + ; Use project's Asm Define setting (default) + ELSE + IF :DEF:USE_HT32_CHIP + ; Use project's Asm Define setting (higher priority than the "USE_HT32_CHIP_SET") + ELSE + ; Use "USE_HT32_CHIP_SET" in the "startup_ht32xxxxx_xx.s" file +USE_HT32_CHIP EQU USE_HT32_CHIP_SET + ENDIF + ENDIF + +; Amount of memory (in bytes) allocated for Stack and Heap +; Tailor those values to your application needs +;// Stack Size (in Bytes, must 8 byte aligned) <0-8192:8> +Stack_Size EQU 512 + + AREA STACK, NOINIT, READWRITE, ALIGN = 3 +__HT_check_sp +Stack_Mem SPACE Stack_Size +__initial_sp + +;// Heap Size (in Bytes) <0-8192:8> +Heap_Size EQU 0 + + AREA HEAP, NOINIT, READWRITE, ALIGN = 3 +__HT_check_heap +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + PRESERVE8 + THUMB + +;******************************************************************************* +; Fill-up the Vector Table entries with the exceptions ISR address +;******************************************************************************* + AREA RESET, CODE, READONLY + EXPORT __Vectors +_RESERVED EQU 0xFFFFFFFF +__Vectors + DCD __initial_sp ; ---, 00, 0x000, Top address of Stack + DCD Reset_Handler ; ---, 01, 0x004, Reset Handler + DCD NMI_Handler ; -14, 02, 0x008, NMI Handler + DCD HardFault_Handler ; -13, 03, 0x00C, Hard Fault Handler + DCD _RESERVED ; ---, 04, 0x010, Reserved + DCD _RESERVED ; ---, 05, 0x014, Reserved + DCD _RESERVED ; ---, 06, 0x018, Reserved + DCD _RESERVED ; ---, 07, 0x01C, Reserved + DCD _HT32FWID ; ---, 08, 0x020, Reserved + DCD _RESERVED ; ---, 09, 0x024, Reserved + DCD _RESERVED ; ---, 10, 0x028, Reserved + DCD SVC_Handler ; -05, 11, 0x02C, SVC Handler + DCD _RESERVED ; ---, 12, 0x030, Reserved + DCD _RESERVED ; ---, 13, 0x034, Reserved + DCD PendSV_Handler ; -02, 14, 0x038, PendSV Handler + DCD SysTick_Handler ; -01, 15, 0x03C, SysTick Handler + + ; External Interrupt Handler + DCD LVD_BOD_IRQHandler ; 00, 16, 0x040, + DCD RTC_IRQHandler ; 01, 17, 0x044, + DCD FLASH_IRQHandler ; 02, 18, 0x048, + DCD EVWUP_IRQHandler ; 03, 19, 0x04C, + DCD EXTI0_1_IRQHandler ; 04, 20, 0x050, + DCD EXTI2_3_IRQHandler ; 05, 21, 0x054, + DCD EXTI4_9_IRQHandler ; 06, 22, 0x058, + DCD EXTI10_15_IRQHandler ; 07, 23, 0x05C, + DCD ADC0_IRQHandler ; 08, 24, 0x060, + IF (USE_HT32_CHIP=HT32F65230_40) + DCD ADC1_IRQHandler ; 09, 25, 0x064, + ELSE + DCD _RESERVED ; 09, 25, 0x064, + ENDIF + DCD MCTM0_BRK_IRQHandler ; 10, 26, 0x068, + DCD MCTM0_UP_IRQHandler ; 11, 27, 0x06C, + DCD MCTM0_TR_UP2_IRQHandler ; 12, 28, 0x070, + DCD MCTM0_CC_IRQHandler ; 13, 29, 0x074, + DCD GPTM0_G_IRQHandler ; 14, 30, 0x078, + DCD GPTM0_VCLK_IRQHandler ; 15, 31, 0x07C, + DCD BFTM0_IRQHandler ; 16, 32, 0x080, + DCD BFTM1_IRQHandler ; 17, 33, 0x084, + DCD CMP0_IRQHandler ; 18, 34, 0x088, + DCD CMP1_IRQHandler ; 19, 35, 0x08C, + IF (USE_HT32_CHIP=HT32F65230_40) + DCD CMP2_IRQHandler ; 20, 36, 0x090, + ELSE + DCD _RESERVED ; 20, 36, 0x090, + ENDIF + DCD I2C0_IRQHandler ; 21, 37, 0x094, + DCD SPI0_IRQHandler ; 22, 38, 0x098, + DCD USART0_IRQHandler ; 23, 39, 0x09C, + DCD UART0_IRQHandler ; 24, 40, 0x0A0, + DCD PDMA_CH0_1_IRQHandler ; 25, 41, 0x0A4, + DCD PDMA_CH2_3_IRQHandler ; 26, 42, 0x0A8, + DCD PDMA_CH4_5_IRQHandler ; 27, 43, 0x0AC, + DCD SCTM0_IRQHandler ; 28, 44, 0x0B0, + DCD SCTM1_IRQHandler ; 29, 45, 0x0B4, + DCD SCTM2_IRQHandler ; 30, 46, 0x0B8, + DCD SCTM3_IRQHandler ; 31, 47, 0x0BC, + +; Reset handler routine +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception Handlers +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP + +HardFault_Handler PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP + +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP + +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP + +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + EXPORT LVD_BOD_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT EVWUP_IRQHandler [WEAK] + EXPORT EXTI0_1_IRQHandler [WEAK] + EXPORT EXTI2_3_IRQHandler [WEAK] + EXPORT EXTI4_9_IRQHandler [WEAK] + EXPORT EXTI10_15_IRQHandler [WEAK] + EXPORT ADC0_IRQHandler [WEAK] + EXPORT ADC1_IRQHandler [WEAK] + EXPORT MCTM0_BRK_IRQHandler [WEAK] + EXPORT MCTM0_UP_IRQHandler [WEAK] + EXPORT MCTM0_TR_UP2_IRQHandler [WEAK] + EXPORT MCTM0_CC_IRQHandler [WEAK] + EXPORT GPTM0_G_IRQHandler [WEAK] + EXPORT GPTM0_VCLK_IRQHandler [WEAK] + EXPORT BFTM0_IRQHandler [WEAK] + EXPORT BFTM1_IRQHandler [WEAK] + EXPORT CMP0_IRQHandler [WEAK] + EXPORT CMP1_IRQHandler [WEAK] + EXPORT CMP2_IRQHandler [WEAK] + EXPORT I2C0_IRQHandler [WEAK] + EXPORT SPI0_IRQHandler [WEAK] + EXPORT USART0_IRQHandler [WEAK] + EXPORT UART0_IRQHandler [WEAK] + EXPORT PDMA_CH0_1_IRQHandler [WEAK] + EXPORT PDMA_CH2_3_IRQHandler [WEAK] + EXPORT PDMA_CH4_5_IRQHandler [WEAK] + EXPORT SCTM0_IRQHandler [WEAK] + EXPORT SCTM1_IRQHandler [WEAK] + EXPORT SCTM2_IRQHandler [WEAK] + EXPORT SCTM3_IRQHandler [WEAK] +LVD_BOD_IRQHandler +RTC_IRQHandler +FLASH_IRQHandler +EVWUP_IRQHandler +EXTI0_1_IRQHandler +EXTI2_3_IRQHandler +EXTI4_9_IRQHandler +EXTI10_15_IRQHandler +ADC0_IRQHandler +ADC1_IRQHandler +MCTM0_BRK_IRQHandler +MCTM0_UP_IRQHandler +MCTM0_TR_UP2_IRQHandler +MCTM0_CC_IRQHandler +GPTM0_G_IRQHandler +GPTM0_VCLK_IRQHandler +BFTM0_IRQHandler +BFTM1_IRQHandler +CMP0_IRQHandler +CMP1_IRQHandler +CMP2_IRQHandler +I2C0_IRQHandler +SPI0_IRQHandler +USART0_IRQHandler +UART0_IRQHandler +PDMA_CH0_1_IRQHandler +PDMA_CH2_3_IRQHandler +PDMA_CH4_5_IRQHandler +SCTM0_IRQHandler +SCTM1_IRQHandler +SCTM2_IRQHandler +SCTM3_IRQHandler + B . + ENDP + + ALIGN + +;******************************************************************************* +; User Stack and Heap initialization +;******************************************************************************* + IF :DEF:__MICROLIB + + EXPORT __HT_check_heap + EXPORT __HT_check_sp + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, = (Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + + ENDIF + + END diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht50f3200t.s b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht50f3200t.s new file mode 100644 index 0000000000..4533138d12 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht50f3200t.s @@ -0,0 +1,403 @@ +;/*---------------------------------------------------------------------------------------------------------*/ +;/* Holtek Semiconductor Inc. */ +;/* */ +;/* Copyright (C) Holtek Semiconductor Inc. */ +;/* All rights reserved. */ +;/* */ +;/*----------------------------------------------------------------------------------------------------------- +; File Name : startup_ht32f5xxxx_03.s +; Version : $Rev:: 6877 $ +; Date : $Date:: 2023-05-04 #$ +; Description : Startup code. +;-----------------------------------------------------------------------------------------------------------*/ + +; Supported Device +; ======================================== +; HT32F0008 +; HT32F52142 +; HT32F52344, HT32F52354 +; HT32F52357, HT32F52367 +; HT50F3200T + +;/* <<< Use Configuration Wizard in Context Menu >>> */ + +;// HT32 Device +;// Select HT32 Device for the assembly setting. +;// Notice that the project's Asm Define has the higher priority. +;// <0=> By Project Asm Define +;// <6=> HT32F0008 +;// <6=> HT32F52142 +;// <9=> HT32F52344/54 +;// <11=> HT32F52357/67 +;// <11=> HT50F3200T +USE_HT32_CHIP_SET EQU 11 ; Notice that the project's Asm Define has the higher priority. + +_HT32FWID EQU 0xFFFFFFFF +;_HT32FWID EQU 0x00000008 +;_HT32FWID EQU 0x00052142 +;_HT32FWID EQU 0x00052344 +;_HT32FWID EQU 0x00052354 +;_HT32FWID EQU 0x00052357 +;_HT32FWID EQU 0x00052367 +;_HT32FWID EQU 0x0003200F + +HT32F0008 EQU 6 +HT32F52142 EQU 6 +HT32F52344_54 EQU 9 +HT32F52357_67 EQU 11 +HT50F3200T EQU 11 + + IF USE_HT32_CHIP_SET=0 + ; Use project's Asm Define setting (default) + ELSE + IF :DEF:USE_HT32_CHIP + ; Use project's Asm Define setting (higher priority than the "USE_HT32_CHIP_SET") + ELSE + ; Use "USE_HT32_CHIP_SET" in the "startup_ht32xxxxx_xx.s" file +USE_HT32_CHIP EQU USE_HT32_CHIP_SET + ENDIF + ENDIF + +; Amount of memory (in bytes) allocated for Stack and Heap +; Tailor those values to your application needs +;// Stack Size (in Bytes, must 8 byte aligned) <0-16384:8> +Stack_Size EQU 512 + + AREA STACK, NOINIT, READWRITE, ALIGN = 3 +__HT_check_sp +Stack_Mem SPACE Stack_Size +__initial_sp + +;// Heap Size (in Bytes) <0-16384:8> +Heap_Size EQU 0 + + AREA HEAP, NOINIT, READWRITE, ALIGN = 3 +__HT_check_heap +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + PRESERVE8 + THUMB + +;******************************************************************************* +; Fill-up the Vector Table entries with the exceptions ISR address +;******************************************************************************* + AREA RESET, CODE, READONLY + EXPORT __Vectors +_RESERVED EQU 0xFFFFFFFF +__Vectors + DCD __initial_sp ; ---, 00, 0x000, Top address of Stack + DCD Reset_Handler ; ---, 01, 0x004, Reset Handler + DCD NMI_Handler ; -14, 02, 0x008, NMI Handler + DCD HardFault_Handler ; -13, 03, 0x00C, Hard Fault Handler + DCD _RESERVED ; ---, 04, 0x010, Reserved + DCD _RESERVED ; ---, 05, 0x014, Reserved + DCD _RESERVED ; ---, 06, 0x018, Reserved + DCD _RESERVED ; ---, 07, 0x01C, Reserved + DCD _HT32FWID ; ---, 08, 0x020, Reserved + DCD _RESERVED ; ---, 09, 0x024, Reserved + DCD _RESERVED ; ---, 10, 0x028, Reserved + DCD SVC_Handler ; -05, 11, 0x02C, SVC Handler + DCD _RESERVED ; ---, 12, 0x030, Reserved + DCD _RESERVED ; ---, 13, 0x034, Reserved + DCD PendSV_Handler ; -02, 14, 0x038, PendSV Handler + DCD SysTick_Handler ; -01, 15, 0x03C, SysTick Handler + + ; External Interrupt Handler + DCD LVD_BOD_IRQHandler ; 00, 16, 0x040, + DCD RTC_IRQHandler ; 01, 17, 0x044, + DCD FLASH_IRQHandler ; 02, 18, 0x048, + DCD EVWUP_IRQHandler ; 03, 19, 0x04C, + DCD EXTI0_1_IRQHandler ; 04, 20, 0x050, + DCD EXTI2_3_IRQHandler ; 05, 21, 0x054, + DCD EXTI4_15_IRQHandler ; 06, 22, 0x058, + IF (USE_HT32_CHIP=HT32F0008) + DCD _RESERVED ; 07, 23, 0x05C, + ENDIF + IF (USE_HT32_CHIP=HT32F52344_54) + DCD COMP_IRQHandler ; 07, 23, 0x05C, + ENDIF + IF (USE_HT32_CHIP=HT32F52357_67) + DCD COMP_DAC_IRQHandler ; 07, 23, 0x05C, + ENDIF + IF (USE_HT32_CHIP=HT32F0008) + DCD _RESERVED ; 08, 24, 0x060, + ELSE + DCD ADC_IRQHandler ; 08, 24, 0x060, + ENDIF + IF (USE_HT32_CHIP=HT32F52357_67) + DCD AES_IRQHandler ; 09, 25, 0x064, + ELSE + DCD _RESERVED ; 09, 25, 0x064, + ENDIF + IF (USE_HT32_CHIP=HT32F0008) + DCD _RESERVED ; 10, 26, 0x068, + ELSE + DCD MCTM0_IRQHandler ; 10, 26, 0x068, + ENDIF + IF (USE_HT32_CHIP=HT32F52357_67) + DCD QSPI_IRQHandler ; 11, 27, 0x06C, + ELSE + DCD _RESERVED ; 11, 27, 0x06C, + ENDIF + DCD GPTM0_IRQHandler ; 12, 28, 0x070, + IF (USE_HT32_CHIP=HT32F0008) + DCD _RESERVED ; 13, 29, 0x074, + DCD _RESERVED ; 14, 30, 0x078, + ELSE + DCD SCTM0_IRQHandler ; 13, 29, 0x074, + DCD SCTM1_IRQHandler ; 14, 30, 0x078, + ENDIF + IF (USE_HT32_CHIP=HT32F0008) || (USE_HT32_CHIP=HT32F52357_67) + DCD PWM0_IRQHandler ; 15, 31, 0x07C, + DCD PWM1_IRQHandler ; 16, 32, 0x080, + ENDIF + IF (USE_HT32_CHIP=HT32F52344_54) + DCD _RESERVED ; 15, 31, 0x07C, + DCD _RESERVED ; 16, 32, 0x080, + ENDIF + DCD BFTM0_IRQHandler ; 17, 33, 0x084, + DCD BFTM1_IRQHandler ; 18, 34, 0x088, + DCD I2C0_IRQHandler ; 19, 35, 0x08C, + IF (USE_HT32_CHIP=HT32F0008) || (USE_HT32_CHIP=HT32F52344_54) + DCD _RESERVED ; 20, 36, 0x090, + ELSE + DCD I2C1_IRQHandler ; 20, 36, 0x090, + ENDIF + DCD SPI0_IRQHandler ; 21, 37, 0x094, + IF (USE_HT32_CHIP=HT32F0008) + DCD _RESERVED ; 22, 38, 0x098, + ELSE + DCD SPI1_IRQHandler ; 22, 38, 0x098, + ENDIF + IF (USE_HT32_CHIP=HT32F52344_54) + DCD _RESERVED ; 23, 39, 0x09C, + ELSE + DCD USART0_IRQHandler ; 23, 39, 0x09C, + ENDIF + IF (USE_HT32_CHIP=HT32F0008) + DCD _RESERVED ; 24, 40, 0x0A0, + DCD UART0_IRQHandler ; 25, 41, 0x0A4, + DCD _RESERVED ; 26, 42, 0x0A8, + ENDIF + IF (USE_HT32_CHIP=HT32F52344_54) + DCD _RESERVED ; 24, 40, 0x0A0, + DCD UART0_IRQHandler ; 25, 41, 0x0A4, + DCD UART1_IRQHandler ; 26, 42, 0x0A8, + ENDIF + IF (USE_HT32_CHIP=HT32F52357_67) + DCD USART1_IRQHandler ; 24, 40, 0x0A0, + DCD UART0_UART2_IRQHandler ; 25, 41, 0x0A4, + DCD UART1_UART3_IRQHandler ; 26, 42, 0x0A8, + ENDIF + IF (USE_HT32_CHIP=HT32F52357_67) + DCD SCI_IRQHandler ; 27, 43, 0xAC, + ELSE + DCD _RESERVED ; 27, 43, 0xAC, + ENDIF + IF (USE_HT32_CHIP=HT32F0008) + DCD AES_IRQHandler ; 28, 44, 0x0B0, + ENDIF + IF (USE_HT32_CHIP=HT32F52344_54) + DCD _RESERVED ; 28, 44, 0x0B0, + ENDIF + IF (USE_HT32_CHIP=HT32F52357_67) + DCD I2S_IRQHandler ; 28, 44, 0x0B0, + ENDIF + DCD USB_IRQHandler ; 29, 45, 0x0B4, + DCD PDMA_CH0_1_IRQHandler ; 30, 46, 0x0B8, + DCD PDMA_CH2_5_IRQHandler ; 31, 47, 0x0BC, + +; Reset handler routine +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + LDR R0, =BootProcess + BLX R0 + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +BootProcess PROC + LDR R0, =0x40080300 + LDR R1,[R0, #0x10] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x14] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x18] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x1C] + CMP R1, #0 + BEQ BP2 +BP1 LDR R0, =0x40080180 + LDR R1,[R0, #0xC] + LSLS R1, R1, #4 + LSRS R1, R1, #20 + CMP R1, #0 + BEQ BP3 + CMP R1, #5 + BEQ BP3 + CMP R1, #6 + BEQ BP3 +BP2 DSB + LDR R0, =0x20000000 + LDR R1, =0x05fa0004 + STR R1, [R0] + LDR R1, =0xe000ed00 + LDR R0, =0x05fa0004 + STR R0, [R1, #0xC] + DSB + B . +BP3 LDR R0, =0x20000000 + LDR R1, [R0] + LDR R0, =0x05fa0004 + CMP R0, R1 + BEQ BP4 + BX LR +BP4 LDR R0, =0x40088100 + LDR R1, =0x00000001 + STR R1, [R0] + LDR R0, =0x20000000 + LDR R1, =0x0 + STR R1, [R0] + BX LR + ENDP + +; Dummy Exception Handlers +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP + +HardFault_Handler PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP + +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP + +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP + +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + EXPORT LVD_BOD_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT EVWUP_IRQHandler [WEAK] + EXPORT EXTI0_1_IRQHandler [WEAK] + EXPORT EXTI2_3_IRQHandler [WEAK] + EXPORT EXTI4_15_IRQHandler [WEAK] + EXPORT COMP_IRQHandler [WEAK] + EXPORT COMP_DAC_IRQHandler [WEAK] + EXPORT ADC_IRQHandler [WEAK] + EXPORT MCTM0_IRQHandler [WEAK] + EXPORT GPTM0_IRQHandler [WEAK] + EXPORT SCTM0_IRQHandler [WEAK] + EXPORT SCTM1_IRQHandler [WEAK] + EXPORT PWM0_IRQHandler [WEAK] + EXPORT PWM1_IRQHandler [WEAK] + EXPORT BFTM0_IRQHandler [WEAK] + EXPORT BFTM1_IRQHandler [WEAK] + EXPORT I2C0_IRQHandler [WEAK] + EXPORT I2C1_IRQHandler [WEAK] + EXPORT SPI0_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT QSPI_IRQHandler [WEAK] + EXPORT USART0_IRQHandler [WEAK] + EXPORT USART1_IRQHandler [WEAK] + EXPORT UART0_IRQHandler [WEAK] + EXPORT UART1_IRQHandler [WEAK] + EXPORT UART0_UART2_IRQHandler [WEAK] + EXPORT UART1_UART3_IRQHandler [WEAK] + EXPORT SCI_IRQHandler [WEAK] + EXPORT I2S_IRQHandler [WEAK] + EXPORT AES_IRQHandler [WEAK] + EXPORT USB_IRQHandler [WEAK] + EXPORT PDMA_CH0_1_IRQHandler [WEAK] + EXPORT PDMA_CH2_5_IRQHandler [WEAK] + +LVD_BOD_IRQHandler +RTC_IRQHandler +FLASH_IRQHandler +EVWUP_IRQHandler +EXTI0_1_IRQHandler +EXTI2_3_IRQHandler +EXTI4_15_IRQHandler +COMP_IRQHandler +COMP_DAC_IRQHandler +ADC_IRQHandler +MCTM0_IRQHandler +GPTM0_IRQHandler +SCTM0_IRQHandler +SCTM1_IRQHandler +PWM0_IRQHandler +PWM1_IRQHandler +BFTM0_IRQHandler +BFTM1_IRQHandler +I2C0_IRQHandler +I2C1_IRQHandler +SPI0_IRQHandler +SPI1_IRQHandler +QSPI_IRQHandler +USART0_IRQHandler +USART1_IRQHandler +UART0_IRQHandler +UART1_IRQHandler +UART0_UART2_IRQHandler +UART1_UART3_IRQHandler +SCI_IRQHandler +I2S_IRQHandler +AES_IRQHandler +USB_IRQHandler +PDMA_CH0_1_IRQHandler +PDMA_CH2_5_IRQHandler + B . + ENDP + + ALIGN + +;******************************************************************************* +; User Stack and Heap initialization +;******************************************************************************* + IF :DEF:__MICROLIB + + EXPORT __HT_check_heap + EXPORT __HT_check_sp + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, = (Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + + ENDIF + + END diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_mxtx6306.s b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_mxtx6306.s new file mode 100644 index 0000000000..b986536809 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_mxtx6306.s @@ -0,0 +1,278 @@ +;/*---------------------------------------------------------------------------------------------------------*/ +;/* Holtek Semiconductor Inc. */ +;/* */ +;/* Copyright (C) Holtek Semiconductor Inc. */ +;/* All rights reserved. */ +;/* */ +;/*----------------------------------------------------------------------------------------------------------- +; File Name : startup_ht32f5xxxx_08.s +; Version : $Rev:: 6877 $ +; Date : $Date:: 2023-05-04 #$ +; Description : Startup code. +;-----------------------------------------------------------------------------------------------------------*/ + +; Supported Device +; ======================================== +; HT32F65230, HT32F65240 +; HT32F65232 +; MXTX6306 +; HT50F3200S + +;/* <<< Use Configuration Wizard in Context Menu >>> */ + +;// HT32 Device +;// Select HT32 Device for the assembly setting. +;// Notice that the project's Asm Define has the higher priority. +;// <0=> By Project Asm Define +;// <12=> HT32F65230_40 +;// <18=> HT32F65232 +;// <12=> MXTX6306 +;// <12=> HT50F3200S +USE_HT32_CHIP_SET EQU 12 ; Notice that the project's Asm Define has the higher priority. + +_HT32FWID EQU 0xFFFFFFFF +;_HT32FWID EQU 0x00065230 +;_HT32FWID EQU 0x00065240 +;_HT32FWID EQU 0x00065232 +;_HT32FWID EQU 0x00006306 +;_HT32FWID EQU 0x0003200F + +HT32F65230_40 EQU 12 +HT32F65232 EQU 18 +MXTX6306 EQU 12 +HT50F3200S EQU 12 + + IF USE_HT32_CHIP_SET=0 + ; Use project's Asm Define setting (default) + ELSE + IF :DEF:USE_HT32_CHIP + ; Use project's Asm Define setting (higher priority than the "USE_HT32_CHIP_SET") + ELSE + ; Use "USE_HT32_CHIP_SET" in the "startup_ht32xxxxx_xx.s" file +USE_HT32_CHIP EQU USE_HT32_CHIP_SET + ENDIF + ENDIF + +; Amount of memory (in bytes) allocated for Stack and Heap +; Tailor those values to your application needs +;// Stack Size (in Bytes, must 8 byte aligned) <0-8192:8> +Stack_Size EQU 512 + + AREA STACK, NOINIT, READWRITE, ALIGN = 3 +__HT_check_sp +Stack_Mem SPACE Stack_Size +__initial_sp + +;// Heap Size (in Bytes) <0-8192:8> +Heap_Size EQU 0 + + AREA HEAP, NOINIT, READWRITE, ALIGN = 3 +__HT_check_heap +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + PRESERVE8 + THUMB + +;******************************************************************************* +; Fill-up the Vector Table entries with the exceptions ISR address +;******************************************************************************* + AREA RESET, CODE, READONLY + EXPORT __Vectors +_RESERVED EQU 0xFFFFFFFF +__Vectors + DCD __initial_sp ; ---, 00, 0x000, Top address of Stack + DCD Reset_Handler ; ---, 01, 0x004, Reset Handler + DCD NMI_Handler ; -14, 02, 0x008, NMI Handler + DCD HardFault_Handler ; -13, 03, 0x00C, Hard Fault Handler + DCD _RESERVED ; ---, 04, 0x010, Reserved + DCD _RESERVED ; ---, 05, 0x014, Reserved + DCD _RESERVED ; ---, 06, 0x018, Reserved + DCD _RESERVED ; ---, 07, 0x01C, Reserved + DCD _HT32FWID ; ---, 08, 0x020, Reserved + DCD _RESERVED ; ---, 09, 0x024, Reserved + DCD _RESERVED ; ---, 10, 0x028, Reserved + DCD SVC_Handler ; -05, 11, 0x02C, SVC Handler + DCD _RESERVED ; ---, 12, 0x030, Reserved + DCD _RESERVED ; ---, 13, 0x034, Reserved + DCD PendSV_Handler ; -02, 14, 0x038, PendSV Handler + DCD SysTick_Handler ; -01, 15, 0x03C, SysTick Handler + + ; External Interrupt Handler + DCD LVD_BOD_IRQHandler ; 00, 16, 0x040, + DCD RTC_IRQHandler ; 01, 17, 0x044, + DCD FLASH_IRQHandler ; 02, 18, 0x048, + DCD EVWUP_IRQHandler ; 03, 19, 0x04C, + DCD EXTI0_1_IRQHandler ; 04, 20, 0x050, + DCD EXTI2_3_IRQHandler ; 05, 21, 0x054, + DCD EXTI4_9_IRQHandler ; 06, 22, 0x058, + DCD EXTI10_15_IRQHandler ; 07, 23, 0x05C, + DCD ADC0_IRQHandler ; 08, 24, 0x060, + IF (USE_HT32_CHIP=HT32F65230_40) + DCD ADC1_IRQHandler ; 09, 25, 0x064, + ELSE + DCD _RESERVED ; 09, 25, 0x064, + ENDIF + DCD MCTM0_BRK_IRQHandler ; 10, 26, 0x068, + DCD MCTM0_UP_IRQHandler ; 11, 27, 0x06C, + DCD MCTM0_TR_UP2_IRQHandler ; 12, 28, 0x070, + DCD MCTM0_CC_IRQHandler ; 13, 29, 0x074, + DCD GPTM0_G_IRQHandler ; 14, 30, 0x078, + DCD GPTM0_VCLK_IRQHandler ; 15, 31, 0x07C, + DCD BFTM0_IRQHandler ; 16, 32, 0x080, + DCD BFTM1_IRQHandler ; 17, 33, 0x084, + DCD CMP0_IRQHandler ; 18, 34, 0x088, + DCD CMP1_IRQHandler ; 19, 35, 0x08C, + IF (USE_HT32_CHIP=HT32F65230_40) + DCD CMP2_IRQHandler ; 20, 36, 0x090, + ELSE + DCD _RESERVED ; 20, 36, 0x090, + ENDIF + DCD I2C0_IRQHandler ; 21, 37, 0x094, + DCD SPI0_IRQHandler ; 22, 38, 0x098, + DCD USART0_IRQHandler ; 23, 39, 0x09C, + DCD UART0_IRQHandler ; 24, 40, 0x0A0, + DCD PDMA_CH0_1_IRQHandler ; 25, 41, 0x0A4, + DCD PDMA_CH2_3_IRQHandler ; 26, 42, 0x0A8, + DCD PDMA_CH4_5_IRQHandler ; 27, 43, 0x0AC, + DCD SCTM0_IRQHandler ; 28, 44, 0x0B0, + DCD SCTM1_IRQHandler ; 29, 45, 0x0B4, + DCD SCTM2_IRQHandler ; 30, 46, 0x0B8, + DCD SCTM3_IRQHandler ; 31, 47, 0x0BC, + +; Reset handler routine +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception Handlers +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP + +HardFault_Handler PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP + +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP + +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP + +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + EXPORT LVD_BOD_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT EVWUP_IRQHandler [WEAK] + EXPORT EXTI0_1_IRQHandler [WEAK] + EXPORT EXTI2_3_IRQHandler [WEAK] + EXPORT EXTI4_9_IRQHandler [WEAK] + EXPORT EXTI10_15_IRQHandler [WEAK] + EXPORT ADC0_IRQHandler [WEAK] + EXPORT ADC1_IRQHandler [WEAK] + EXPORT MCTM0_BRK_IRQHandler [WEAK] + EXPORT MCTM0_UP_IRQHandler [WEAK] + EXPORT MCTM0_TR_UP2_IRQHandler [WEAK] + EXPORT MCTM0_CC_IRQHandler [WEAK] + EXPORT GPTM0_G_IRQHandler [WEAK] + EXPORT GPTM0_VCLK_IRQHandler [WEAK] + EXPORT BFTM0_IRQHandler [WEAK] + EXPORT BFTM1_IRQHandler [WEAK] + EXPORT CMP0_IRQHandler [WEAK] + EXPORT CMP1_IRQHandler [WEAK] + EXPORT CMP2_IRQHandler [WEAK] + EXPORT I2C0_IRQHandler [WEAK] + EXPORT SPI0_IRQHandler [WEAK] + EXPORT USART0_IRQHandler [WEAK] + EXPORT UART0_IRQHandler [WEAK] + EXPORT PDMA_CH0_1_IRQHandler [WEAK] + EXPORT PDMA_CH2_3_IRQHandler [WEAK] + EXPORT PDMA_CH4_5_IRQHandler [WEAK] + EXPORT SCTM0_IRQHandler [WEAK] + EXPORT SCTM1_IRQHandler [WEAK] + EXPORT SCTM2_IRQHandler [WEAK] + EXPORT SCTM3_IRQHandler [WEAK] +LVD_BOD_IRQHandler +RTC_IRQHandler +FLASH_IRQHandler +EVWUP_IRQHandler +EXTI0_1_IRQHandler +EXTI2_3_IRQHandler +EXTI4_9_IRQHandler +EXTI10_15_IRQHandler +ADC0_IRQHandler +ADC1_IRQHandler +MCTM0_BRK_IRQHandler +MCTM0_UP_IRQHandler +MCTM0_TR_UP2_IRQHandler +MCTM0_CC_IRQHandler +GPTM0_G_IRQHandler +GPTM0_VCLK_IRQHandler +BFTM0_IRQHandler +BFTM1_IRQHandler +CMP0_IRQHandler +CMP1_IRQHandler +CMP2_IRQHandler +I2C0_IRQHandler +SPI0_IRQHandler +USART0_IRQHandler +UART0_IRQHandler +PDMA_CH0_1_IRQHandler +PDMA_CH2_3_IRQHandler +PDMA_CH4_5_IRQHandler +SCTM0_IRQHandler +SCTM1_IRQHandler +SCTM2_IRQHandler +SCTM3_IRQHandler + B . + ENDP + + ALIGN + +;******************************************************************************* +; User Stack and Heap initialization +;******************************************************************************* + IF :DEF:__MICROLIB + + EXPORT __HT_check_heap + EXPORT __HT_check_sp + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, = (Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + + ENDIF + + END diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/CodeSourcery/startup_ht32f5xxxx_cs3_01.s b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/CodeSourcery/startup_ht32f5xxxx_cs3_01.s new file mode 100644 index 0000000000..13adc8cdcc --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/CodeSourcery/startup_ht32f5xxxx_cs3_01.s @@ -0,0 +1,461 @@ +/*---------------------------------------------------------------------------------------------------------*/ +/* Holtek Semiconductor Inc. */ +/* */ +/* Copyright (C) Holtek Semiconductor Inc. */ +/* All rights reserved. */ +/* */ +/*----------------------------------------------------------------------------------------------------------- +; File Name : startup_ht32f5xxxx_cs3_01.s +; Version : $Rev:: 6953 $ +; Date : $Date:: 2023-05-30 #$ +; Description : Startup code. +;-----------------------------------------------------------------------------------------------------------*/ + +/* +; Supported Device +; ======================================== +; HT32F52220, HT32F52230 +; HT32F52231, HT32F52241 +; HT32F52331, HT32F52341 +; HT32F52342, HT32F52352 +; HT32F52243, HT32F52253 +; HT32F0008 +; HT32F52344, HT32F52354 +; HT32F0006 +; HT32F61352 +; HT50F32003 +; HT32F62030, HT32F62040, HT32F62050 +; HT32F67741 +; HT32F67232 +; HT32F67233 +*/ + +;/* <<< Use Configuration Wizard in Context Menu >>> */ +/* +;// HT32 Device +;// <0=> By Project Asm Define +;// <1=> HT32F52220/30 +;// <2=> HT32F52231/41 +;// <3=> HT32F52331/41 +;// <4=> HT32F52342/52 +;// <5=> HT32F52243/53 +;// <6=> HT32F0008 +;// <9=> HT32F52344/54 +;// <10=> HT32F0006 +;// <10=> HT32F61352 +;// <4=> HT50F32003 +;// <2=> HT32F67741 +;// <1=> HT32F67232 +;// <1=> HT32F67233 +;// <1=> HT32F62030 +;// <2=> HT32F62040 +;// <5=> HT32F62050 +*/ + .equ USE_HT32_CHIP_SET, 0 + + .equ _HT32FWID, 0xFFFFFFFF +/* + .equ _HT32FWID, 0x00052220 + .equ _HT32FWID, 0x00052230 + .equ _HT32FWID, 0x00052231 + .equ _HT32FWID, 0x00052241 + .equ _HT32FWID, 0x00052331 + .equ _HT32FWID, 0x00052341 + .equ _HT32FWID, 0x00052342 + .equ _HT32FWID, 0x00052352 + .equ _HT32FWID, 0x00052243 + .equ _HT32FWID, 0x00052253 + .equ _HT32FWID, 0x00000008 + .equ _HT32FWID, 0x00052344 + .equ _HT32FWID, 0x00052354 + .equ _HT32FWID, 0x00000006 + .equ _HT32FWID, 0x00061352 + .equ _HT32FWID, 0x00032003 + .equ _HT32FWID, 0x00062030 + .equ _HT32FWID, 0x00062040 + .equ _HT32FWID, 0x00062050 + .equ _HT32FWID, 0x00067741 + .equ _HT32FWID, 0x00067232 + .equ _HT32FWID, 0x00067233 +*/ + + .equ HT32F52220_30, 1 + .equ HT32F52231_41, 2 + .equ HT32F52331_41, 3 + .equ HT32F52342_52, 4 + .equ HT32F52243_53, 5 + .equ HT32F0008, 6 + .equ HT32F52344_54, 9 + .equ HT32F0006, 10 + .equ HT32F61352, 10 + .equ HT50F32003, 4 + .equ HT32F62030, 1 + .equ HT32F62040, 2 + .equ HT32F62050, 5 + .equ HT32F67741, 2 + .equ HT32F67232, 1 + .equ HT32F67233, 1 + + .if USE_HT32_CHIP_SET == 0 + .else + .equ USE_HT32_CHIP, USE_HT32_CHIP_SET + .endif + +/* +; Amount of memory (in bytes) allocated for Stack and Heap +; Tailor those values to your application needs +;// Stack Size (in Bytes, must 8 byte aligned) <:8> +*/ + .equ Stack_Size, 512 + .section ".stack", "w" + .align 3 + .globl __cs3_stack_mem + .globl __cs3_stack + .globl __cs3_stack_size + .globl __HT_check_sp +__HT_check_sp: +__cs3_stack_mem: + .if Stack_Size + .space Stack_Size + .endif +__cs3_stack: + .size __cs3_stack_mem, . - __cs3_stack_mem + .set __cs3_stack_size, . - __cs3_stack_mem + +/* +;// Heap Size (in Bytes) <:8> +*/ + .equ Heap_Size, 0 + .section ".heap", "w" + .align 3 + .globl __cs3_heap_start + .globl __cs3_heap_end + .globl __HT_check_heap +__HT_check_heap: +__cs3_heap_start: + .if Heap_Size + .space Heap_Size + .endif +__cs3_heap_end: + + .equ _RESERVED, 0xFFFFFFFF +/* +;******************************************************************************* +; Fill-up the Vector Table entries with the exceptions ISR address +;********************************************************************************/ + .section ".cs3.interrupt_vector" + .globl __cs3_interrupt_vector_cortex_m + .type __cs3_interrupt_vector_cortex_m, %object +__cs3_interrupt_vector_cortex_m: + .long __cs3_stack /* ---, 00, 0x000, Top address of Stack */ + .long __cs3_reset /* ---, 01, 0x004, Reset Handler */ + .long NMI_Handler /* -14, 02, 0x008, NMI Handler */ + .long HardFault_Handler /* -13, 03, 0x00C, Hard Fault Handler */ + .long _RESERVED /* ---, 04, 0x010, Reserved */ + .long _RESERVED /* ---, 05, 0x014, Reserved */ + .long _RESERVED /* ---, 06, 0x018, Reserved */ + .long _RESERVED /* ---, 07, 0x01C, Reserved */ + .long _HT32FWID /* ---, 08, 0x020, Reserved */ + .long _RESERVED /* ---, 09, 0x024, Reserved */ + .long _RESERVED /* ---, 10, 0x028, Reserved */ + .long SVC_Handler /* -05, 11, 0x02C, SVC Handler */ + .long _RESERVED /* ---, 12, 0x030, Reserved */ + .long _RESERVED /* ---, 13, 0x034, Reserved */ + .long PendSV_Handler /* -02, 14, 0x038, PendSV Handler */ + .long SysTick_Handler /* -01, 15, 0x03C, SysTick Handler */ + + /* External Interrupt Handler */ + .long LVD_BOD_IRQHandler /* 00, 16, 0x040, */ + .if (USE_HT32_CHIP==HT32F52220_30) + .long _RESERVED /* 01, 17, 0x044, */ + .else + .long RTC_IRQHandler /* 01, 17, 0x044, */ + .endif + .long FLASH_IRQHandler /* 02, 18, 0x048, */ + .long EVWUP_IRQHandler /* 03, 19, 0x04C, */ + .long EXTI0_1_IRQHandler /* 04, 20, 0x050, */ + .long EXTI2_3_IRQHandler /* 05, 21, 0x054, */ + .long EXTI4_15_IRQHandler /* 06, 22, 0x058, */ + .if (USE_HT32_CHIP==HT32F52342_52) || (USE_HT32_CHIP==HT32F52344_54) + .long COMP_IRQHandler /* 07, 23, 0x05C, */ + .else + .long _RESERVED /* 07, 23, 0x05C, */ + .endif + .if (USE_HT32_CHIP==HT32F0008) + .long _RESERVED /* 08, 24, 0x060, */ + .else + .long ADC_IRQHandler /* 08, 24, 0x060, */ + .endif + .if (USE_HT32_CHIP==HT32F52243_53) + .long I2C2_IRQHandler /* 09, 25, 0x064, */ + .else + .long _RESERVED /* 09, 25, 0x064, */ + .endif + .if (USE_HT32_CHIP==HT32F52220_30) || (USE_HT32_CHIP==HT32F0008) || (USE_HT32_CHIP==HT32F0006) + .long _RESERVED /* 10, 26, 0x068, */ + .else + .long MCTM0_IRQHandler /* 10, 26, 0x068, */ + .endif + .if (USE_HT32_CHIP==HT32F52342_52) + .long GPTM1_IRQHandler /* 11, 27, 0x06C, */ + .else + .long _RESERVED /* 11, 27, 0x06C, */ + .endif + .long GPTM0_IRQHandler /* 12, 28, 0x070, */ + .if (USE_HT32_CHIP==HT32F0008) + .long _RESERVED /* 13, 29, 0x074, */ + .long _RESERVED /* 14, 30, 0x078, */ + .else + .long SCTM0_IRQHandler /* 13, 29, 0x074, */ + .long SCTM1_IRQHandler /* 14, 30, 0x078, */ + .endif + .if (USE_HT32_CHIP==HT32F52231_41) || (USE_HT32_CHIP==HT32F52331_41) || (USE_HT32_CHIP==HT32F52243_53) || (USE_HT32_CHIP==HT32F0006) + .long SCTM2_IRQHandler /* 15, 31, 0x07C, */ + .long SCTM3_IRQHandler /* 16, 32, 0x080, */ + .endif + .if (USE_HT32_CHIP==HT32F0008) + .long PWM0_IRQHandler /* 15, 31, 0x07C, */ + .long PWM1_IRQHandler /* 16, 32, 0x080, */ + .endif + .if (USE_HT32_CHIP==HT32F52220_30) || (USE_HT32_CHIP==HT32F52342_52) || (USE_HT32_CHIP==HT32F52344_54) + .long _RESERVED /* 15, 31, 0x07C, */ + .long _RESERVED /* 16, 32, 0x080, */ + .endif + .long BFTM0_IRQHandler /* 17, 33, 0x084, */ + .if (USE_HT32_CHIP==HT32F52220_30) + .long _RESERVED /* 18, 34, 0x088, */ + .else + .long BFTM1_IRQHandler /* 18, 34, 0x088, */ + .endif + .long I2C0_IRQHandler /* 19, 35, 0x08C, */ + .if (USE_HT32_CHIP==HT32F52220_30) || (USE_HT32_CHIP==HT32F0008) || (USE_HT32_CHIP==HT32F52344_54) || (USE_HT32_CHIP==HT32F0006) + .long _RESERVED /* 20, 36, 0x090, */ + .else + .long I2C1_IRQHandler /* 20, 36, 0x090, */ + .endif + .long SPI0_IRQHandler /* 21, 37, 0x094, */ + .if (USE_HT32_CHIP==HT32F52220_30) || (USE_HT32_CHIP==HT32F0008) + .long _RESERVED /* 22, 38, 0x098, */ + .else + .if (USE_HT32_CHIP==HT32F0006) + .long QSPI_IRQHandler /* 22, 38, 0x098, */ + .else + .long SPI1_IRQHandler /* 22, 38, 0x098, */ + .endif + .endif + .if (USE_HT32_CHIP==HT32F52344_54) + .long _RESERVED /* 23, 39, 0x09C, */ + .else + .long USART0_IRQHandler /* 23, 39, 0x09C, */ + .endif + .if (USE_HT32_CHIP==HT32F52342_52) || (USE_HT32_CHIP==HT32F52243_53) + .long USART1_IRQHandler /* 24, 40, 0x0A0, */ + .else + .long _RESERVED /* 24, 40, 0x0A0, */ + .endif + .long UART0_IRQHandler /* 25, 41, 0x0A4, */ + .if (USE_HT32_CHIP==HT32F52220_30) || (USE_HT32_CHIP==HT32F0008) || (USE_HT32_CHIP==HT32F0006) + .long _RESERVED /* 26, 42, 0x0A8, */ + .else + .long UART1_IRQHandler /* 26, 42, 0x0A8, */ + .endif + .if (USE_HT32_CHIP==HT32F52331_41) || (USE_HT32_CHIP==HT32F52342_52) + .long SCI_IRQHandler /* 27, 43, 0x0AC, */ + .endif + .if (USE_HT32_CHIP==HT32F52243_53) + .long UART2_IRQHandler /* 27, 43, 0x0AC, */ + .endif + .if (USE_HT32_CHIP==HT32F0006) + .long MIDI_IRQHandler /* 27, 43, 0x0AC, */ + .endif + .if (USE_HT32_CHIP==HT32F0008) || (USE_HT32_CHIP==HT32F52344_54) + .long _RESERVED /* 27, 43, 0xAC, */ + .endif + .if (USE_HT32_CHIP==HT32F52342_52) || (USE_HT32_CHIP==HT32F0006) + .long I2S_IRQHandler /* 28, 44, 0x0B0, */ + .endif + .if (USE_HT32_CHIP==HT32F52331_41) || (USE_HT32_CHIP==HT32F52344_54) + .long _RESERVED /* 28, 44, 0x0B0, */ + .endif + .if (USE_HT32_CHIP==HT32F52243_53) + .long UART3_IRQHandler /* 28, 44, 0x0B0, */ + .endif + .if (USE_HT32_CHIP==HT32F0008) + .long AES_IRQHandler /* 28, 44, 0x0B0, */ + .endif + .if (USE_HT32_CHIP==HT32F52331_41) || (USE_HT32_CHIP==HT32F52342_52) || (USE_HT32_CHIP==HT32F0008) || (USE_HT32_CHIP==HT32F52344_54) || (USE_HT32_CHIP==HT32F0006) + .long USB_IRQHandler /* 29, 45, 0x0B4, */ + .endif + .if (USE_HT32_CHIP==HT32F52243_53) + .long _RESERVED /* 29, 45, 0x0B4, */ + .endif + .if (USE_HT32_CHIP==HT32F52342_52) || (USE_HT32_CHIP==HT32F52243_53) || (USE_HT32_CHIP==HT32F0008) || (USE_HT32_CHIP==HT32F52344_54) || (USE_HT32_CHIP==HT32F0006) + .long PDMA_CH0_1_IRQHandler /* 30, 46, 0x0B8, */ + .long PDMA_CH2_5_IRQHandler /* 31, 47, 0x0BC, */ + .endif + + .size __cs3_interrupt_vector_cortex_m, . - __cs3_interrupt_vector_cortex_m + + + .thumb + + +/* Reset Handler */ + + .section .cs3.reset,"x",%progbits + .thumb_func + .globl __cs3_reset_cortex_m + .type __cs3_reset_cortex_m, %function +__cs3_reset_cortex_m: + .fnstart + LDR R0, =BootProcess + BLX R0 + LDR R0, =SystemInit + BLX R0 + LDR R0, =_start + BX R0 + .thumb_func +BootProcess: + LDR R0, =0x40080300 + LDR R1,[R0, #0x10] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x14] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x18] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x1C] + CMP R1, #0 + BEQ BP2 +BP1: + LDR R0, =0x40080180 + LDR R1,[R0, #0xC] + LSL R1, R1, #4 + LSR R1, R1, #20 + CMP R1, #0 + BEQ BP3 + CMP R1, #5 + BEQ BP3 + CMP R1, #6 + BEQ BP3 +BP2: + DSB + LDR R0, =0x20000000 + LDR R1, =0x05fa0004 + STR R1, [R0] + LDR R1, =0xe000ed00 + LDR R0, =0x05fa0004 + STR R0, [R1, #0xC] + DSB + B . +BP3: + LDR R0, =0x20000000 + LDR R1, [R0] + LDR R0, =0x05fa0004 + CMP R0, R1 + BEQ BP4 + BX LR +BP4: + LDR R0, =0x40088100 + LDR R1, =0x00000001 + STR R1, [R0] + LDR R0, =0x20000000 + LDR R1, =0x0 + STR R1, [R0] + BX LR + .pool + .cantunwind + .fnend + .size __cs3_reset_cortex_m,.-__cs3_reset_cortex_m + + .section ".text" + +/* Exception Handlers */ + + .weak NMI_Handler + .type NMI_Handler, %function +NMI_Handler: + B . + .size NMI_Handler, . - NMI_Handler + + .weak HardFault_Handler + .type HardFault_Handler, %function +HardFault_Handler: + B . + .size HardFault_Handler, . - HardFault_Handler + + .weak SVC_Handler + .type SVC_Handler, %function +SVC_Handler: + B . + .size SVC_Handler, . - SVC_Handler + + .weak PendSV_Handler + .type PendSV_Handler, %function +PendSV_Handler: + B . + .size PendSV_Handler, . - PendSV_Handler + + .weak SysTick_Handler + .type SysTick_Handler, %function +SysTick_Handler: + B . + .size SysTick_Handler, . - SysTick_Handler + + +/* IRQ Handlers */ + + .globl Default_Handler + .type Default_Handler, %function +Default_Handler: + B . + .size Default_Handler, . - Default_Handler + + .macro IRQ handler + .weak \handler + .set \handler, Default_Handler + .endm + + IRQ LVD_BOD_IRQHandler + IRQ RTC_IRQHandler + IRQ FLASH_IRQHandler + IRQ EVWUP_IRQHandler + IRQ EXTI0_1_IRQHandler + IRQ EXTI2_3_IRQHandler + IRQ EXTI4_15_IRQHandler + IRQ COMP_IRQHandler + IRQ ADC_IRQHandler + IRQ MCTM0_IRQHandler + IRQ GPTM1_IRQHandler + IRQ GPTM0_IRQHandler + IRQ SCTM0_IRQHandler + IRQ SCTM1_IRQHandler + IRQ SCTM2_IRQHandler + IRQ SCTM3_IRQHandler + IRQ PWM0_IRQHandler + IRQ PWM1_IRQHandler + IRQ BFTM0_IRQHandler + IRQ BFTM1_IRQHandler + IRQ I2C0_IRQHandler + IRQ I2C1_IRQHandler + IRQ I2C2_IRQHandler + IRQ SPI0_IRQHandler + IRQ SPI1_IRQHandler + IRQ QSPI_IRQHandler + IRQ USART0_IRQHandler + IRQ USART1_IRQHandler + IRQ UART0_IRQHandler + IRQ UART1_IRQHandler + IRQ UART2_IRQHandler + IRQ UART3_IRQHandler + IRQ SCI_IRQHandler + IRQ MIDI_IRQHandler + IRQ I2S_IRQHandler + IRQ AES_IRQHandler + IRQ USB_IRQHandler + IRQ PDMA_CH0_1_IRQHandler + IRQ PDMA_CH2_5_IRQHandler + + .end diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/CodeSourcery/startup_ht32f5xxxx_cs3_02.s b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/CodeSourcery/startup_ht32f5xxxx_cs3_02.s new file mode 100644 index 0000000000..1521f84226 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/CodeSourcery/startup_ht32f5xxxx_cs3_02.s @@ -0,0 +1,324 @@ +/*---------------------------------------------------------------------------------------------------------*/ +/* Holtek Semiconductor Inc. */ +/* */ +/* Copyright (C) Holtek Semiconductor Inc. */ +/* All rights reserved. */ +/* */ +/*----------------------------------------------------------------------------------------------------------- +; File Name : startup_ht32f5xxxx_cs3_02.s +; Version : $Rev:: 7119 $ +; Date : $Date:: 2023-08-15 #$ +; Description : Startup code. +;-----------------------------------------------------------------------------------------------------------*/ + +/* +; Supported Device +; ======================================== +; HT32F50220, HT32F50230 +; HT32F50231, HT32F50241 +; HT50F32002 +; HT32F59041 +; HF5032 +; HT32F61641 +; HT32F59046 +; HT32F61041 +*/ + +;/* <<< Use Configuration Wizard in Context Menu >>> */ +/* +;// HT32 Device +;// <0=> By Project Asm Define +;// <7=> HT32F50220/30 +;// <8=> HT32F50231/41 +;// <7=> HT50F32002 +;// <8=> HT32F59041 +;// <7=> HF5032 +;// <8=> HT32F61641 +;// <8=> HT32F59046 +;// <8=> HT32F61041 +*/ + .equ USE_HT32_CHIP_SET, 0 + + .equ _HT32FWID, 0xFFFFFFFF +/* + .equ _HT32FWID, 0x00050220 + .equ _HT32FWID, 0x00050230 + .equ _HT32FWID, 0x00050231 + .equ _HT32FWID, 0x00050241 + .equ _HT32FWID, 0x00032002 + .equ _HT32FWID, 0x00059041 + .equ _HT32FWID, 0x000F5032 + .equ _HT32FWID, 0x00061641 + .equ _HT32FWID, 0x00059046 + .equ _HT32FWID, 0x00061041 +*/ + + .equ HT32F50220_30, 7 + .equ HT32F50231_41, 8 + .equ HT50F32002, 7 + .equ HT32F59041, 8 + .equ HF5032, 7 + .equ HT32F61641, 8 + .equ HT32F59046, 8 + .equ HT32F61041, 8 + + .if USE_HT32_CHIP_SET == 0 + .else + .equ USE_HT32_CHIP, USE_HT32_CHIP_SET + .endif + +/* +; Amount of memory (in bytes) allocated for Stack and Heap +; Tailor those values to your application needs +;// Stack Size (in Bytes, must 8 byte aligned) <:8> +*/ + .equ Stack_Size, 512 + .section ".stack", "w" + .align 3 + .globl __cs3_stack_mem + .globl __cs3_stack + .globl __cs3_stack_size + .globl __HT_check_sp +__HT_check_sp: +__cs3_stack_mem: + .if Stack_Size + .space Stack_Size + .endif +__cs3_stack: + .size __cs3_stack_mem, . - __cs3_stack_mem + .set __cs3_stack_size, . - __cs3_stack_mem + +/* +;// Heap Size (in Bytes) <:8> +*/ + .equ Heap_Size, 0 + .section ".heap", "w" + .align 3 + .globl __cs3_heap_start + .globl __cs3_heap_end + .globl __HT_check_heap +__HT_check_heap: +__cs3_heap_start: + .if Heap_Size + .space Heap_Size + .endif +__cs3_heap_end: + + .equ _RESERVED, 0xFFFFFFFF +/* +;******************************************************************************* +; Fill-up the Vector Table entries with the exceptions ISR address +;********************************************************************************/ + .section ".cs3.interrupt_vector" + .globl __cs3_interrupt_vector_cortex_m + .type __cs3_interrupt_vector_cortex_m, %object +__cs3_interrupt_vector_cortex_m: + .long __cs3_stack /* ---, 00, 0x000, Top address of Stack */ + .long __cs3_reset /* ---, 01, 0x004, Reset Handler */ + .long NMI_Handler /* -14, 02, 0x008, NMI Handler */ + .long HardFault_Handler /* -13, 03, 0x00C, Hard Fault Handler */ + .long _RESERVED /* ---, 04, 0x010, Reserved */ + .long _RESERVED /* ---, 05, 0x014, Reserved */ + .long _RESERVED /* ---, 06, 0x018, Reserved */ + .long _RESERVED /* ---, 07, 0x01C, Reserved */ + .long _HT32FWID /* ---, 08, 0x020, Reserved */ + .long _RESERVED /* ---, 09, 0x024, Reserved */ + .long _RESERVED /* ---, 10, 0x028, Reserved */ + .long SVC_Handler /* -05, 11, 0x02C, SVC Handler */ + .long _RESERVED /* ---, 12, 0x030, Reserved */ + .long _RESERVED /* ---, 13, 0x034, Reserved */ + .long PendSV_Handler /* -02, 14, 0x038, PendSV Handler */ + .long SysTick_Handler /* -01, 15, 0x03C, SysTick Handler */ + + /* External Interrupt Handler */ + .long LVD_BOD_IRQHandler /* 00, 16, 0x040, */ + .long RTC_IRQHandler /* 01, 17, 0x044, */ + .long FLASH_IRQHandler /* 02, 18, 0x048, */ + .long EVWUP_IRQHandler /* 03, 19, 0x04C, */ + .long EXTI0_1_IRQHandler /* 04, 20, 0x050, */ + .long EXTI2_3_IRQHandler /* 05, 21, 0x054, */ + .long EXTI4_15_IRQHandler /* 06, 22, 0x058, */ + .long _RESERVED /* 07, 23, 0x05C, */ + .long ADC_IRQHandler /* 08, 24, 0x060, */ + .long _RESERVED /* 09, 25, 0x064, */ + .if (USE_HT32_CHIP==HT32F50220_30) + .long _RESERVED /* 10, 26, 0x068, */ + .else + .long MCTM0_IRQHandler /* 10, 26, 0x068, */ + .endif + .long _RESERVED /* 11, 27, 0x06C, */ + .long GPTM0_IRQHandler /* 12, 28, 0x070, */ + .long _RESERVED /* 13, 29, 0x074, */ + .long _RESERVED /* 14, 30, 0x078, */ + .long PWM0_IRQHandler /* 15, 31, 0x07C, */ + .long PWM1_IRQHandler /* 16, 32, 0x080, */ + .long BFTM0_IRQHandler /* 17, 33, 0x084, */ + .if (USE_HT32_CHIP==HT32F50220_30) + .long _RESERVED /* 18, 34, 0x088, */ + .else + .long BFTM1_IRQHandler /* 18, 34, 0x088, */ + .endif + .long I2C0_IRQHandler /* 19, 35, 0x08C, */ + .if (USE_HT32_CHIP==HT32F50220_30) + .long _RESERVED /* 20, 36, 0x090, */ + .else + .long I2C1_IRQHandler /* 20, 36, 0x090, */ + .endif + .long SPI0_IRQHandler /* 21, 37, 0x094, */ + .long SPI1_IRQHandler /* 22, 38, 0x098, */ + .if (USE_HT32_CHIP==HT32F50220_30) + .long _RESERVED /* 23, 39, 0x09C, */ + .else + .long USART0_IRQHandler /* 23, 39, 0x09C, */ + .endif + .long _RESERVED /* 24, 40, 0x0A0, */ + .long UART0_IRQHandler /* 25, 41, 0x0A4, */ + .long UART1_IRQHandler /* 26, 42, 0x0A8, */ + + .size __cs3_interrupt_vector_cortex_m, . - __cs3_interrupt_vector_cortex_m + + + .thumb + + +/* Reset Handler */ + + .section .cs3.reset,"x",%progbits + .thumb_func + .globl __cs3_reset_cortex_m + .type __cs3_reset_cortex_m, %function +__cs3_reset_cortex_m: + .fnstart + LDR R0, =BootProcess + BLX R0 + LDR R0, =SystemInit + BLX R0 + LDR R0, =_start + BX R0 + .thumb_func +BootProcess: + LDR R0, =0x40080300 + LDR R1,[R0, #0x10] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x14] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x18] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x1C] + CMP R1, #0 + BEQ BP2 +BP1: + LDR R0, =0x40080180 + LDR R1,[R0, #0xC] + LSL R1, R1, #4 + LSR R1, R1, #20 + CMP R1, #0 + BEQ BP3 + CMP R1, #5 + BEQ BP3 + CMP R1, #6 + BEQ BP3 +BP2: + DSB + LDR R0, =0x20000000 + LDR R1, =0x05fa0004 + STR R1, [R0] + LDR R1, =0xe000ed00 + LDR R0, =0x05fa0004 + STR R0, [R1, #0xC] + DSB + B . +BP3: + LDR R0, =0x20000000 + LDR R1, [R0] + LDR R0, =0x05fa0004 + CMP R0, R1 + BEQ BP4 + BX LR +BP4: + LDR R0, =0x40088100 + LDR R1, =0x00000001 + STR R1, [R0] + LDR R0, =0x20000000 + LDR R1, =0x0 + STR R1, [R0] + BX LR + .pool + .cantunwind + .fnend + .size __cs3_reset_cortex_m,.-__cs3_reset_cortex_m + + .section ".text" + +/* Exception Handlers */ + + .weak NMI_Handler + .type NMI_Handler, %function +NMI_Handler: + B . + .size NMI_Handler, . - NMI_Handler + + .weak HardFault_Handler + .type HardFault_Handler, %function +HardFault_Handler: + B . + .size HardFault_Handler, . - HardFault_Handler + + .weak SVC_Handler + .type SVC_Handler, %function +SVC_Handler: + B . + .size SVC_Handler, . - SVC_Handler + + .weak PendSV_Handler + .type PendSV_Handler, %function +PendSV_Handler: + B . + .size PendSV_Handler, . - PendSV_Handler + + .weak SysTick_Handler + .type SysTick_Handler, %function +SysTick_Handler: + B . + .size SysTick_Handler, . - SysTick_Handler + + +/* IRQ Handlers */ + + .globl Default_Handler + .type Default_Handler, %function +Default_Handler: + B . + .size Default_Handler, . - Default_Handler + + .macro IRQ handler + .weak \handler + .set \handler, Default_Handler + .endm + + IRQ LVD_BOD_IRQHandler + IRQ RTC_IRQHandler + IRQ FLASH_IRQHandler + IRQ EVWUP_IRQHandler + IRQ EXTI0_1_IRQHandler + IRQ EXTI2_3_IRQHandler + IRQ EXTI4_15_IRQHandler + IRQ ADC_IRQHandler + IRQ MCTM0_IRQHandler + IRQ GPTM0_IRQHandler + IRQ PWM0_IRQHandler + IRQ PWM1_IRQHandler + IRQ BFTM0_IRQHandler + IRQ BFTM1_IRQHandler + IRQ I2C0_IRQHandler + IRQ I2C1_IRQHandler + IRQ SPI0_IRQHandler + IRQ SPI1_IRQHandler + IRQ USART0_IRQHandler + IRQ UART0_IRQHandler + IRQ UART1_IRQHandler + + .end diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/CodeSourcery/startup_ht32f5xxxx_cs3_03.s b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/CodeSourcery/startup_ht32f5xxxx_cs3_03.s new file mode 100644 index 0000000000..1f2906d760 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/CodeSourcery/startup_ht32f5xxxx_cs3_03.s @@ -0,0 +1,386 @@ +/*---------------------------------------------------------------------------------------------------------*/ +/* Holtek Semiconductor Inc. */ +/* */ +/* Copyright (C) Holtek Semiconductor Inc. */ +/* All rights reserved. */ +/* */ +/*----------------------------------------------------------------------------------------------------------- +; File Name : startup_ht32f5xxxx_cs3_03.s +; Version : $Rev:: 6887 $ +; Date : $Date:: 2023-05-05 #$ +; Description : Startup code. +;-----------------------------------------------------------------------------------------------------------*/ + +/* +; Supported Device +; ======================================== +; HT32F0008 +; HT32F52142 +; HT32F52344, HT32F52354 +; HT32F52357, HT32F52367 +; HT50F3200T +*/ + +;/* <<< Use Configuration Wizard in Context Menu >>> */ +/* +;// HT32 Device +;// <0=> By Project Asm Define +;// <6=> HT32F0008 +;// <6=> HT32F52142 +;// <9=> HT32F52344/54 +;// <11=> HT32F52357/67 +;// <11=> HT50F3200T +*/ + .equ USE_HT32_CHIP_SET, 0 + + .equ _HT32FWID, 0xFFFFFFFF +/* + .equ _HT32FWID, 0x00000008 + .equ _HT32FWID, 0x00052142 + .equ _HT32FWID, 0x00052344 + .equ _HT32FWID, 0x00052354 + .equ _HT32FWID, 0x00052357 + .equ _HT32FWID, 0x00052367 + .equ _HT32FWID, 0x0003200F +*/ + + .equ HT32F0008, 6 + .equ HT32F52142, 6 + .equ HT32F52344_54, 9 + .equ HT32F52357_67, 11 + .equ HT50F3200T, 11 + + .if USE_HT32_CHIP_SET == 0 + .else + .equ USE_HT32_CHIP, USE_HT32_CHIP_SET + .endif + +/* +; Amount of memory (in bytes) allocated for Stack and Heap +; Tailor those values to your application needs +;// Stack Size (in Bytes, must 8 byte aligned) <:8> +*/ + .equ Stack_Size, 512 + .section ".stack", "w" + .align 3 + .globl __cs3_stack_mem + .globl __cs3_stack + .globl __cs3_stack_size + .globl __HT_check_sp +__HT_check_sp: +__cs3_stack_mem: + .if Stack_Size + .space Stack_Size + .endif +__cs3_stack: + .size __cs3_stack_mem, . - __cs3_stack_mem + .set __cs3_stack_size, . - __cs3_stack_mem + +/* +;// Heap Size (in Bytes) <:8> +*/ + .equ Heap_Size, 0 + .section ".heap", "w" + .align 3 + .globl __cs3_heap_start + .globl __cs3_heap_end + .globl __HT_check_heap +__HT_check_heap: +__cs3_heap_start: + .if Heap_Size + .space Heap_Size + .endif +__cs3_heap_end: + + .equ _RESERVED, 0xFFFFFFFF +/* +;******************************************************************************* +; Fill-up the Vector Table entries with the exceptions ISR address +;********************************************************************************/ + .section ".cs3.interrupt_vector" + .globl __cs3_interrupt_vector_cortex_m + .type __cs3_interrupt_vector_cortex_m, %object +__cs3_interrupt_vector_cortex_m: + .long __cs3_stack /* ---, 00, 0x000, Top address of Stack */ + .long __cs3_reset /* ---, 01, 0x004, Reset Handler */ + .long NMI_Handler /* -14, 02, 0x008, NMI Handler */ + .long HardFault_Handler /* -13, 03, 0x00C, Hard Fault Handler */ + .long _RESERVED /* ---, 04, 0x010, Reserved */ + .long _RESERVED /* ---, 05, 0x014, Reserved */ + .long _RESERVED /* ---, 06, 0x018, Reserved */ + .long _RESERVED /* ---, 07, 0x01C, Reserved */ + .long _HT32FWID /* ---, 08, 0x020, Reserved */ + .long _RESERVED /* ---, 09, 0x024, Reserved */ + .long _RESERVED /* ---, 10, 0x028, Reserved */ + .long SVC_Handler /* -05, 11, 0x02C, SVC Handler */ + .long _RESERVED /* ---, 12, 0x030, Reserved */ + .long _RESERVED /* ---, 13, 0x034, Reserved */ + .long PendSV_Handler /* -02, 14, 0x038, PendSV Handler */ + .long SysTick_Handler /* -01, 15, 0x03C, SysTick Handler */ + + /* External Interrupt Handler */ + .long LVD_BOD_IRQHandler /* 00, 16, 0x040, */ + .long RTC_IRQHandler /* 01, 17, 0x044, */ + .long FLASH_IRQHandler /* 02, 18, 0x048, */ + .long EVWUP_IRQHandler /* 03, 19, 0x04C, */ + .long EXTI0_1_IRQHandler /* 04, 20, 0x050, */ + .long EXTI2_3_IRQHandler /* 05, 21, 0x054, */ + .long EXTI4_15_IRQHandler /* 06, 22, 0x058, */ + .if (USE_HT32_CHIP==HT32F0008) + .long _RESERVED /* 07, 23, 0x05C, */ + .endif + .if (USE_HT32_CHIP==HT32F52344_54) + .long COMP_IRQHandler /* 07, 23, 0x05C, */ + .endif + .if (USE_HT32_CHIP==HT32F52357_67) + .long COMP_DAC_IRQHandler /* 07, 23, 0x05C, */ + .endif + .if (USE_HT32_CHIP==HT32F0008) + .long _RESERVED /* 08, 24, 0x060, */ + .else + .long ADC_IRQHandler /* 08, 24, 0x060, */ + .endif + .if (USE_HT32_CHIP==HT32F52357_67) + .long AES_IRQHandler /* 09, 25, 0x064, */ + .else + .long _RESERVED /* 09, 25, 0x064, */ + .endif + .if (USE_HT32_CHIP==HT32F0008) + .long _RESERVED /* 10, 26, 0x068, */ + .else + .long MCTM0_IRQHandler /* 10, 26, 0x068, */ + .endif + .if (USE_HT32_CHIP==HT32F52357_67) + .long QSPI_IRQHandler /* 11, 27, 0x06C, */ + .else + .long _RESERVED /* 11, 27, 0x06C, */ + .endif + .long GPTM0_IRQHandler /* 12, 28, 0x070, */ + .if (USE_HT32_CHIP==HT32F0008) + .long _RESERVED /* 13, 29, 0x074, */ + .long _RESERVED /* 14, 30, 0x078, */ + .else + .long SCTM0_IRQHandler /* 13, 29, 0x074, */ + .long SCTM1_IRQHandler /* 14, 30, 0x078, */ + .endif + .if (USE_HT32_CHIP==HT32F0008) || (USE_HT32_CHIP==HT32F52357_67) + .long PWM0_IRQHandler /* 15, 31, 0x07C, */ + .long PWM1_IRQHandler /* 16, 32, 0x080, */ + .endif + .if (USE_HT32_CHIP==HT32F52344_54) + .long _RESERVED /* 15, 31, 0x07C, */ + .long _RESERVED /* 16, 32, 0x080, */ + .endif + .long BFTM0_IRQHandler /* 17, 33, 0x084, */ + .long BFTM1_IRQHandler /* 18, 34, 0x088, */ + .long I2C0_IRQHandler /* 19, 35, 0x08C, */ + .if (USE_HT32_CHIP==HT32F0008) || (USE_HT32_CHIP==HT32F52344_54) + .long _RESERVED /* 20, 36, 0x090, */ + .else + .long I2C1_IRQHandler /* 20, 36, 0x090, */ + .endif + .long SPI0_IRQHandler /* 21, 37, 0x094, */ + .if (USE_HT32_CHIP==HT32F0008) + .long _RESERVED /* 22, 38, 0x098, */ + .else + .long SPI1_IRQHandler /* 22, 38, 0x098, */ + .endif + .if (USE_HT32_CHIP==HT32F52344_54) + .long _RESERVED /* 23, 39, 0x09C, */ + .else + .long USART0_IRQHandler /* 23, 39, 0x09C, */ + .endif + .if (USE_HT32_CHIP==HT32F0008) + .long _RESERVED /* 24, 40, 0x0A0, */ + .long UART0_IRQHandler /* 25, 41, 0x0A4, */ + .long _RESERVED /* 26, 42, 0x0A8, */ + .endif + .if (USE_HT32_CHIP==HT32F52344_54) + .long _RESERVED /* 24, 40, 0x0A0, */ + .long UART0_IRQHandler /* 25, 41, 0x0A4, */ + .long UART1_IRQHandler /* 26, 42, 0x0A8, */ + .endif + .if (USE_HT32_CHIP==HT32F52357_67) + .long USART1_IRQHandler /* 24, 40, 0x0A0, */ + .long UART0_UART2_IRQHandler /* 25, 41, 0x0A4, */ + .long UART1_UART3_IRQHandler /* 26, 42, 0x0A8, */ + .endif + .if (USE_HT32_CHIP==HT32F52357_67) + .long SCI_IRQHandler /* 27, 43, 0x0AC, */ + .else + .long _RESERVED /* 27, 43, 0x0AC, */ + .endif + .if (USE_HT32_CHIP==HT32F0008) + .long AES_IRQHandler /* 28, 44, 0x0B0, */ + .endif + .if (USE_HT32_CHIP==HT32F52344_54) + .long _RESERVED /* 28, 44, 0x0B0, */ + .endif + .if (USE_HT32_CHIP==HT32F52357_67) + .long I2S_IRQHandler /* 28, 44, 0x0B0, */ + .endif + .long USB_IRQHandler /* 29, 45, 0x0B4, */ + .long PDMA_CH0_1_IRQHandler /* 30, 46, 0x0B8, */ + .long PDMA_CH2_5_IRQHandler /* 31, 47, 0x0BC, */ + + .size __cs3_interrupt_vector_cortex_m, . - __cs3_interrupt_vector_cortex_m + + + .thumb + + +/* Reset Handler */ + + .section .cs3.reset,"x",%progbits + .thumb_func + .globl __cs3_reset_cortex_m + .type __cs3_reset_cortex_m, %function +__cs3_reset_cortex_m: + .fnstart + LDR R0, =BootProcess + BLX R0 + LDR R0, =SystemInit + BLX R0 + LDR R0, =_start + BX R0 + .thumb_func +BootProcess: + LDR R0, =0x40080300 + LDR R1,[R0, #0x10] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x14] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x18] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x1C] + CMP R1, #0 + BEQ BP2 +BP1: + LDR R0, =0x40080180 + LDR R1,[R0, #0xC] + LSL R1, R1, #4 + LSR R1, R1, #20 + CMP R1, #0 + BEQ BP3 + CMP R1, #5 + BEQ BP3 + CMP R1, #6 + BEQ BP3 +BP2: + DSB + LDR R0, =0x20000000 + LDR R1, =0x05fa0004 + STR R1, [R0] + LDR R1, =0xe000ed00 + LDR R0, =0x05fa0004 + STR R0, [R1, #0xC] + DSB + B . +BP3: + LDR R0, =0x20000000 + LDR R1, [R0] + LDR R0, =0x05fa0004 + CMP R0, R1 + BEQ BP4 + BX LR +BP4: + LDR R0, =0x40088100 + LDR R1, =0x00000001 + STR R1, [R0] + LDR R0, =0x20000000 + LDR R1, =0x0 + STR R1, [R0] + BX LR + .pool + .cantunwind + .fnend + .size __cs3_reset_cortex_m,.-__cs3_reset_cortex_m + + .section ".text" + +/* Exception Handlers */ + + .weak NMI_Handler + .type NMI_Handler, %function +NMI_Handler: + B . + .size NMI_Handler, . - NMI_Handler + + .weak HardFault_Handler + .type HardFault_Handler, %function +HardFault_Handler: + B . + .size HardFault_Handler, . - HardFault_Handler + + .weak SVC_Handler + .type SVC_Handler, %function +SVC_Handler: + B . + .size SVC_Handler, . - SVC_Handler + + .weak PendSV_Handler + .type PendSV_Handler, %function +PendSV_Handler: + B . + .size PendSV_Handler, . - PendSV_Handler + + .weak SysTick_Handler + .type SysTick_Handler, %function +SysTick_Handler: + B . + .size SysTick_Handler, . - SysTick_Handler + + +/* IRQ Handlers */ + + .globl Default_Handler + .type Default_Handler, %function +Default_Handler: + B . + .size Default_Handler, . - Default_Handler + + .macro IRQ handler + .weak \handler + .set \handler, Default_Handler + .endm + + IRQ LVD_BOD_IRQHandler + IRQ RTC_IRQHandler + IRQ FLASH_IRQHandler + IRQ EVWUP_IRQHandler + IRQ EXTI0_1_IRQHandler + IRQ EXTI2_3_IRQHandler + IRQ EXTI4_15_IRQHandler + IRQ COMP_IRQHandler + IRQ COMP_DAC_IRQHandler + IRQ ADC_IRQHandler + IRQ MCTM0_IRQHandler + IRQ GPTM0_IRQHandler + IRQ SCTM0_IRQHandler + IRQ SCTM1_IRQHandler + IRQ PWM0_IRQHandler + IRQ PWM1_IRQHandler + IRQ BFTM0_IRQHandler + IRQ BFTM1_IRQHandler + IRQ I2C0_IRQHandler + IRQ I2C1_IRQHandler + IRQ SPI0_IRQHandler + IRQ SPI1_IRQHandler + IRQ QSPI_IRQHandler + IRQ USART0_IRQHandler + IRQ USART1_IRQHandler + IRQ UART0_IRQHandler + IRQ UART1_IRQHandler + IRQ UART0_UART2_IRQHandler + IRQ UART1_UART3_IRQHandler + IRQ SCI_IRQHandler + IRQ I2S_IRQHandler + IRQ AES_IRQHandler + IRQ USB_IRQHandler + IRQ PDMA_CH0_1_IRQHandler + IRQ PDMA_CH2_5_IRQHandler + + .end diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/CodeSourcery/startup_ht32f5xxxx_cs3_05.s b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/CodeSourcery/startup_ht32f5xxxx_cs3_05.s new file mode 100644 index 0000000000..1618d4b1c0 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/CodeSourcery/startup_ht32f5xxxx_cs3_05.s @@ -0,0 +1,338 @@ +/*---------------------------------------------------------------------------------------------------------*/ +/* Holtek Semiconductor Inc. */ +/* */ +/* Copyright (C) Holtek Semiconductor Inc. */ +/* All rights reserved. */ +/* */ +/*----------------------------------------------------------------------------------------------------------- +; File Name : startup_ht32f5xxxx_cs3_05.s +; Version : $Rev:: 6993 $ +; Date : $Date:: 2023-06-26 #$ +; Description : Startup code. +;-----------------------------------------------------------------------------------------------------------*/ + +/* +; Supported Device +; ======================================== +; HT32F57331, HT32F57341 +; HT32F57342, HT32F57352 +; HT32F59741 +; HT32F5828 +; HT32F67742 +; HT32F59746 +*/ + +;/* <<< Use Configuration Wizard in Context Menu >>> */ +/* +;// HT32 Device +;// <0=> By Project Asm Define +;// <13=> HT32F57331/41 +;// <14=> HT32F57342/52 +;// <13=> HT32F59741 +;// <14=> HT32F5828 +;// <13=> HT32F67742 +;// <13=> HT32F59746 +*/ + .equ USE_HT32_CHIP_SET, 0 + + .equ _HT32FWID, 0xFFFFFFFF +/* + .equ _HT32FWID, 0x00057331 + .equ _HT32FWID, 0x00057341 + .equ _HT32FWID, 0x00057342 + .equ _HT32FWID, 0x00057352 + .equ _HT32FWID, 0x00059741 + .equ _HT32FWID, 0x00005828 + .equ _HT32FWID, 0x00067742 + .equ _HT32FWID, 0x00059746 +*/ + + .equ HT32F57331_41, 13 + .equ HT32F57342_52, 14 + .equ HT32F59741, 13 + .equ HT32F5828, 14 + .equ HT32F67742, 13 + .equ HT32F59746, 13 + + .if USE_HT32_CHIP_SET == 0 + .else + .equ USE_HT32_CHIP, USE_HT32_CHIP_SET + .endif + +/* +; Amount of memory (in bytes) allocated for Stack and Heap +; Tailor those values to your application needs +;// Stack Size (in Bytes, must 8 byte aligned) <:8> +*/ + .equ Stack_Size, 512 + .section ".stack", "w" + .align 3 + .globl __cs3_stack_mem + .globl __cs3_stack + .globl __cs3_stack_size + .globl __HT_check_sp +__HT_check_sp: +__cs3_stack_mem: + .if Stack_Size + .space Stack_Size + .endif +__cs3_stack: + .size __cs3_stack_mem, . - __cs3_stack_mem + .set __cs3_stack_size, . - __cs3_stack_mem + +/* +;// Heap Size (in Bytes) <:8> +*/ + .equ Heap_Size, 0 + .section ".heap", "w" + .align 3 + .globl __cs3_heap_start + .globl __cs3_heap_end + .globl __HT_check_heap +__HT_check_heap: +__cs3_heap_start: + .if Heap_Size + .space Heap_Size + .endif +__cs3_heap_end: + + .equ _RESERVED, 0xFFFFFFFF +/* +;******************************************************************************* +; Fill-up the Vector Table entries with the exceptions ISR address +;********************************************************************************/ + .section ".cs3.interrupt_vector" + .globl __cs3_interrupt_vector_cortex_m + .type __cs3_interrupt_vector_cortex_m, %object +__cs3_interrupt_vector_cortex_m: + .long __cs3_stack /* ---, 00, 0x000, Top address of Stack */ + .long __cs3_reset /* ---, 01, 0x004, Reset Handler */ + .long NMI_Handler /* -14, 02, 0x008, NMI Handler */ + .long HardFault_Handler /* -13, 03, 0x00C, Hard Fault Handler */ + .long _RESERVED /* ---, 04, 0x010, Reserved */ + .long _RESERVED /* ---, 05, 0x014, Reserved */ + .long _RESERVED /* ---, 06, 0x018, Reserved */ + .long _RESERVED /* ---, 07, 0x01C, Reserved */ + .long _HT32FWID /* ---, 08, 0x020, Reserved */ + .long _RESERVED /* ---, 09, 0x024, Reserved */ + .long _RESERVED /* ---, 10, 0x028, Reserved */ + .long SVC_Handler /* -05, 11, 0x02C, SVC Handler */ + .long _RESERVED /* ---, 12, 0x030, Reserved */ + .long _RESERVED /* ---, 13, 0x034, Reserved */ + .long PendSV_Handler /* -02, 14, 0x038, PendSV Handler */ + .long SysTick_Handler /* -01, 15, 0x03C, SysTick Handler */ + + /* External Interrupt Handler */ + .long LVD_BOD_IRQHandler /* 00, 16, 0x040, */ + .long RTC_IRQHandler /* 01, 17, 0x044, */ + .long FLASH_IRQHandler /* 02, 18, 0x048, */ + .long EVWUP_IRQHandler /* 03, 19, 0x04C, */ + .long EXTI0_1_IRQHandler /* 04, 20, 0x050, */ + .long EXTI2_3_IRQHandler /* 05, 21, 0x054, */ + .long EXTI4_15_IRQHandler /* 06, 22, 0x058, */ + .if (USE_HT32_CHIP==HT32F57331_41) + .long _RESERVED /* 07, 23, 0x05C, */ + .endif + .if (USE_HT32_CHIP==HT32F57342_52) + .long COMP_DAC_IRQHandler /* 07, 23, 0x05C, */ + .endif + .long ADC_IRQHandler /* 08, 24, 0x060, */ + .if (USE_HT32_CHIP==HT32F57331_41) + .long _RESERVED /* 09, 25, 0x064, */ + .endif + .if (USE_HT32_CHIP==HT32F57342_52) + .long AES_IRQHandler /* 09, 25, 0x064, */ + .endif + .long _RESERVED /* 10, 26, 0x068, */ + .long LCD_IRQHandler /* 11, 27, 0x06C, */ + .long GPTM0_IRQHandler /* 12, 28, 0x070, */ + .if (USE_HT32_CHIP==HT32F57331_41) + .long _RESERVED /* 13, 29, 0x074, */ + .long _RESERVED /* 14, 30, 0x078, */ + .endif + .if (USE_HT32_CHIP==HT32F57342_52) + .long SCTM0_IRQHandler /* 13, 29, 0x074, */ + .long SCTM1_IRQHandler /* 14, 30, 0x078, */ + .endif + .long PWM0_IRQHandler /* 15, 31, 0x07C, */ + .long PWM1_IRQHandler /* 16, 32, 0x080, */ + .long BFTM0_IRQHandler /* 17, 33, 0x084, */ + .long BFTM1_IRQHandler /* 18, 34, 0x088, */ + .long I2C0_IRQHandler /* 19, 35, 0x08C, */ + .long I2C1_IRQHandler /* 20, 36, 0x090, */ + .long SPI0_IRQHandler /* 21, 37, 0x094, */ + .long SPI1_IRQHandler /* 22, 38, 0x098, */ + .long USART0_IRQHandler /* 23, 39, 0x09C, */ + .long _RESERVED /* 24, 40, 0x0A0, */ + .long UART0_IRQHandler /* 25, 41, 0x0A4, */ + .long UART1_IRQHandler /* 26, 42, 0x0A8, */ + .long SCI_IRQHandler /* 27, 43, 0x0AC, */ + .long I2S_IRQHandler /* 28, 44, 0x0B0, */ + .long USB_IRQHandler /* 29, 45, 0x0B4, */ + .if (USE_HT32_CHIP==HT32F57331_41) + .long _RESERVED /* 30, 46, 0x0B8, */ + .long _RESERVED /* 31, 47, 0x0BC, */ + .endif + .if (USE_HT32_CHIP==HT32F57342_52) + .long PDMA_CH0_1_IRQHandler /* 30, 46, 0x0B8, */ + .long PDMA_CH2_5_IRQHandler /* 31, 47, 0x0BC, */ + .endif + + .size __cs3_interrupt_vector_cortex_m, . - __cs3_interrupt_vector_cortex_m + + + .thumb + + +/* Reset Handler */ + + .section .cs3.reset,"x",%progbits + .thumb_func + .globl __cs3_reset_cortex_m + .type __cs3_reset_cortex_m, %function +__cs3_reset_cortex_m: + .fnstart + LDR R0, =BootProcess + BLX R0 + LDR R0, =SystemInit + BLX R0 + LDR R0, =_start + BX R0 + .thumb_func +BootProcess: + LDR R0, =0x40080300 + LDR R1,[R0, #0x10] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x14] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x18] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x1C] + CMP R1, #0 + BEQ BP2 +BP1: + LDR R0, =0x40080180 + LDR R1,[R0, #0xC] + LSL R1, R1, #4 + LSR R1, R1, #20 + CMP R1, #0 + BEQ BP3 + CMP R1, #5 + BEQ BP3 + CMP R1, #6 + BEQ BP3 +BP2: + DSB + LDR R0, =0x20000000 + LDR R1, =0x05fa0004 + STR R1, [R0] + LDR R1, =0xe000ed00 + LDR R0, =0x05fa0004 + STR R0, [R1, #0xC] + DSB + B . +BP3: + LDR R0, =0x20000000 + LDR R1, [R0] + LDR R0, =0x05fa0004 + CMP R0, R1 + BEQ BP4 + BX LR +BP4: + LDR R0, =0x40088100 + LDR R1, =0x00000001 + STR R1, [R0] + LDR R0, =0x20000000 + LDR R1, =0x0 + STR R1, [R0] + BX LR + .pool + .cantunwind + .fnend + .size __cs3_reset_cortex_m,.-__cs3_reset_cortex_m + + .section ".text" + +/* Exception Handlers */ + + .weak NMI_Handler + .type NMI_Handler, %function +NMI_Handler: + B . + .size NMI_Handler, . - NMI_Handler + + .weak HardFault_Handler + .type HardFault_Handler, %function +HardFault_Handler: + B . + .size HardFault_Handler, . - HardFault_Handler + + .weak SVC_Handler + .type SVC_Handler, %function +SVC_Handler: + B . + .size SVC_Handler, . - SVC_Handler + + .weak PendSV_Handler + .type PendSV_Handler, %function +PendSV_Handler: + B . + .size PendSV_Handler, . - PendSV_Handler + + .weak SysTick_Handler + .type SysTick_Handler, %function +SysTick_Handler: + B . + .size SysTick_Handler, . - SysTick_Handler + + +/* IRQ Handlers */ + + .globl Default_Handler + .type Default_Handler, %function +Default_Handler: + B . + .size Default_Handler, . - Default_Handler + + .macro IRQ handler + .weak \handler + .set \handler, Default_Handler + .endm + + IRQ LVD_BOD_IRQHandler + IRQ RTC_IRQHandler + IRQ FLASH_IRQHandler + IRQ EVWUP_IRQHandler + IRQ EXTI0_1_IRQHandler + IRQ EXTI2_3_IRQHandler + IRQ EXTI4_15_IRQHandler + IRQ COMP_IRQHandler + IRQ COMP_DAC_IRQHandler + IRQ ADC_IRQHandler + IRQ AES_IRQHandler + IRQ LCD_IRQHandler + IRQ GPTM0_IRQHandler + IRQ SCTM0_IRQHandler + IRQ SCTM1_IRQHandler + IRQ PWM0_IRQHandler + IRQ PWM1_IRQHandler + IRQ BFTM0_IRQHandler + IRQ BFTM1_IRQHandler + IRQ I2C0_IRQHandler + IRQ I2C1_IRQHandler + IRQ SPI0_IRQHandler + IRQ SPI1_IRQHandler + IRQ USART0_IRQHandler + IRQ USART1_IRQHandler + IRQ UART0_IRQHandler + IRQ UART1_IRQHandler + IRQ SCI_IRQHandler + IRQ I2S_IRQHandler + IRQ USB_IRQHandler + IRQ PDMA_CH0_1_IRQHandler + IRQ PDMA_CH2_5_IRQHandler + + .end diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/CodeSourcery/startup_ht32f5xxxx_cs3_06.s b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/CodeSourcery/startup_ht32f5xxxx_cs3_06.s new file mode 100644 index 0000000000..f7788dc217 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/CodeSourcery/startup_ht32f5xxxx_cs3_06.s @@ -0,0 +1,289 @@ +/*---------------------------------------------------------------------------------------------------------*/ +/* Holtek Semiconductor Inc. */ +/* */ +/* Copyright (C) Holtek Semiconductor Inc. */ +/* All rights reserved. */ +/* */ +/*----------------------------------------------------------------------------------------------------------- +; File Name : startup_ht32f5xxxx_cs3_06.s +; Version : $Rev:: 4141 $ +; Date : $Date:: 2019-07-24 #$ +; Description : Startup code. +;-----------------------------------------------------------------------------------------------------------*/ + +/* +; Supported Device +; ======================================== +; HT32F50343 +*/ + +;/* <<< Use Configuration Wizard in Context Menu >>> */ +/* +;// HT32 Device +;// <0=> By Project Asm Define +;// <15=> HT32F50343 +*/ + .equ USE_HT32_CHIP_SET, 0 + + .equ _HT32FWID, 0xFFFFFFFF +/* + .equ _HT32FWID, 0x00050343 +*/ + + .equ HT32F50343, 15 + + .if USE_HT32_CHIP_SET == 0 + .else + .equ USE_HT32_CHIP, USE_HT32_CHIP_SET + .endif + +/* +; Amount of memory (in bytes) allocated for Stack and Heap +; Tailor those values to your application needs +;// Stack Size (in Bytes, must 8 byte aligned) <:8> +*/ + .equ Stack_Size, 512 + .section ".stack", "w" + .align 3 + .globl __cs3_stack_mem + .globl __cs3_stack + .globl __cs3_stack_size + .globl __HT_check_sp +__HT_check_sp: +__cs3_stack_mem: + .if Stack_Size + .space Stack_Size + .endif +__cs3_stack: + .size __cs3_stack_mem, . - __cs3_stack_mem + .set __cs3_stack_size, . - __cs3_stack_mem + +/* +;// Heap Size (in Bytes) <:8> +*/ + .equ Heap_Size, 0 + .section ".heap", "w" + .align 3 + .globl __cs3_heap_start + .globl __cs3_heap_end + .globl __HT_check_heap +__HT_check_heap: +__cs3_heap_start: + .if Heap_Size + .space Heap_Size + .endif +__cs3_heap_end: + + .equ _RESERVED, 0xFFFFFFFF +/* +;******************************************************************************* +; Fill-up the Vector Table entries with the exceptions ISR address +;********************************************************************************/ + .section ".cs3.interrupt_vector" + .globl __cs3_interrupt_vector_cortex_m + .type __cs3_interrupt_vector_cortex_m, %object +__cs3_interrupt_vector_cortex_m: + .long __cs3_stack /* ---, 00, 0x000, Top address of Stack */ + .long __cs3_reset /* ---, 01, 0x004, Reset Handler */ + .long NMI_Handler /* -14, 02, 0x008, NMI Handler */ + .long HardFault_Handler /* -13, 03, 0x00C, Hard Fault Handler */ + .long _RESERVED /* ---, 04, 0x010, Reserved */ + .long _RESERVED /* ---, 05, 0x014, Reserved */ + .long _RESERVED /* ---, 06, 0x018, Reserved */ + .long _RESERVED /* ---, 07, 0x01C, Reserved */ + .long _HT32FWID /* ---, 08, 0x020, Reserved */ + .long _RESERVED /* ---, 09, 0x024, Reserved */ + .long _RESERVED /* ---, 10, 0x028, Reserved */ + .long SVC_Handler /* -05, 11, 0x02C, SVC Handler */ + .long _RESERVED /* ---, 12, 0x030, Reserved */ + .long _RESERVED /* ---, 13, 0x034, Reserved */ + .long PendSV_Handler /* -02, 14, 0x038, PendSV Handler */ + .long SysTick_Handler /* -01, 15, 0x03C, SysTick Handler */ + + /* External Interrupt Handler */ + .long LVD_BOD_IRQHandler /* 00, 16, 0x040, */ + .long RTC_IRQHandler /* 01, 17, 0x044, */ + .long FLASH_IRQHandler /* 02, 18, 0x048, */ + .long EVWUP_IRQHandler /* 03, 19, 0x04C, */ + .long EXTI0_1_IRQHandler /* 04, 20, 0x050, */ + .long EXTI2_3_IRQHandler /* 05, 21, 0x054, */ + .long EXTI4_15_IRQHandler /* 06, 22, 0x058, */ + .long _RESERVED /* 07, 23, 0x05C, */ + .long ADC_IRQHandler /* 08, 24, 0x060, */ + .long _RESERVED /* 09, 25, 0x064, */ + .long PWM2_IRQHandler /* 10, 26, 0x068, */ + .long _RESERVED /* 11, 27, 0x06C, */ + .long GPTM0_IRQHandler /* 12, 28, 0x070, */ + .long SCTM0_IRQHandler /* 13, 29, 0x074, */ + .long SCTM1_IRQHandler /* 14, 30, 0x078, */ + .long PWM0_IRQHandler /* 15, 31, 0x07C, */ + .long PWM1_IRQHandler /* 16, 32, 0x080, */ + .long BFTM0_IRQHandler /* 17, 33, 0x084, */ + .long BFTM1_IRQHandler /* 18, 34, 0x088, */ + .long I2C0_IRQHandler /* 19, 35, 0x08C, */ + .long I2C1_IRQHandler /* 20, 36, 0x090, */ + .long SPI0_IRQHandler /* 21, 37, 0x094, */ + .long SPI1_IRQHandler /* 22, 38, 0x098, */ + .long _RESERVED /* 23, 39, 0x09C, */ + .long _RESERVED /* 24, 40, 0x0A0, */ + .long UART0_IRQHandler /* 25, 41, 0x0A4, */ + .long UART1_IRQHandler /* 26, 42, 0x0A8, */ + .long SLED0_IRQHandler /* 27, 43, 0x0AC, */ + .long SLED1_IRQHandler /* 28, 44, 0x0B0, */ + .long USB_IRQHandler /* 29, 45, 0x0B4, */ + .long PDMA_CH0_1_IRQHandler /* 30, 46, 0x0B8, */ + .long PDMA_CH2_5_IRQHandler /* 31, 47, 0x0BC, */ + + .size __cs3_interrupt_vector_cortex_m, . - __cs3_interrupt_vector_cortex_m + + + .thumb + + +/* Reset Handler */ + + .section .cs3.reset,"x",%progbits + .thumb_func + .globl __cs3_reset_cortex_m + .type __cs3_reset_cortex_m, %function +__cs3_reset_cortex_m: + .fnstart + LDR R0, =BootProcess + BLX R0 + LDR R0, =SystemInit + BLX R0 + LDR R0, =_start + BX R0 + .thumb_func +BootProcess: + LDR R0, =0x40080300 + LDR R1,[R0, #0x10] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x14] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x18] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x1C] + CMP R1, #0 + BEQ BP2 +BP1: + LDR R0, =0x40080180 + LDR R1,[R0, #0xC] + LSL R1, R1, #4 + LSR R1, R1, #20 + CMP R1, #0 + BEQ BP3 + CMP R1, #5 + BEQ BP3 + CMP R1, #6 + BEQ BP3 +BP2: + DSB + LDR R0, =0x20000000 + LDR R1, =0x05fa0004 + STR R1, [R0] + LDR R1, =0xe000ed00 + LDR R0, =0x05fa0004 + STR R0, [R1, #0xC] + DSB + B . +BP3: + LDR R0, =0x20000000 + LDR R1, [R0] + LDR R0, =0x05fa0004 + CMP R0, R1 + BEQ BP4 + BX LR +BP4: + LDR R0, =0x40088100 + LDR R1, =0x00000001 + STR R1, [R0] + LDR R0, =0x20000000 + LDR R1, =0x0 + STR R1, [R0] + BX LR + .pool + .cantunwind + .fnend + .size __cs3_reset_cortex_m,.-__cs3_reset_cortex_m + + .section ".text" + +/* Exception Handlers */ + + .weak NMI_Handler + .type NMI_Handler, %function +NMI_Handler: + B . + .size NMI_Handler, . - NMI_Handler + + .weak HardFault_Handler + .type HardFault_Handler, %function +HardFault_Handler: + B . + .size HardFault_Handler, . - HardFault_Handler + + .weak SVC_Handler + .type SVC_Handler, %function +SVC_Handler: + B . + .size SVC_Handler, . - SVC_Handler + + .weak PendSV_Handler + .type PendSV_Handler, %function +PendSV_Handler: + B . + .size PendSV_Handler, . - PendSV_Handler + + .weak SysTick_Handler + .type SysTick_Handler, %function +SysTick_Handler: + B . + .size SysTick_Handler, . - SysTick_Handler + + +/* IRQ Handlers */ + + .globl Default_Handler + .type Default_Handler, %function +Default_Handler: + B . + .size Default_Handler, . - Default_Handler + + .macro IRQ handler + .weak \handler + .set \handler, Default_Handler + .endm + + IRQ LVD_BOD_IRQHandler + IRQ RTC_IRQHandler + IRQ FLASH_IRQHandler + IRQ EVWUP_IRQHandler + IRQ EXTI0_1_IRQHandler + IRQ EXTI2_3_IRQHandler + IRQ EXTI4_15_IRQHandler + IRQ ADC_IRQHandler + IRQ PWM2_IRQHandler + IRQ GPTM0_IRQHandler + IRQ SCTM0_IRQHandler + IRQ SCTM1_IRQHandler + IRQ PWM0_IRQHandler + IRQ PWM1_IRQHandler + IRQ BFTM0_IRQHandler + IRQ BFTM1_IRQHandler + IRQ I2C0_IRQHandler + IRQ I2C1_IRQHandler + IRQ SPI0_IRQHandler + IRQ SPI1_IRQHandler + IRQ UART0_IRQHandler + IRQ UART1_IRQHandler + IRQ SLED0_IRQHandler + IRQ SLED1_IRQHandler + IRQ USB_IRQHandler + IRQ PDMA_CH0_1_IRQHandler + IRQ PDMA_CH2_5_IRQHandler + + .end diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/CodeSourcery/startup_ht32f5xxxx_cs3_07.s b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/CodeSourcery/startup_ht32f5xxxx_cs3_07.s new file mode 100644 index 0000000000..2ecf758757 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/CodeSourcery/startup_ht32f5xxxx_cs3_07.s @@ -0,0 +1,296 @@ +/*---------------------------------------------------------------------------------------------------------*/ +/* Holtek Semiconductor Inc. */ +/* */ +/* Copyright (C) Holtek Semiconductor Inc. */ +/* All rights reserved. */ +/* */ +/*----------------------------------------------------------------------------------------------------------- +; File Name : startup_ht32f5xxxx_cs3_07.s +; Version : $Rev:: 5157 $ +; Date : $Date:: 2021-01-18 #$ +; Description : Startup code. +;-----------------------------------------------------------------------------------------------------------*/ + +/* +; Supported Device +; ======================================== +; HT32F0006 +; HT32F61352 +; HT32F61355, HT32F61356, HT32F61357 + +;/* <<< Use Configuration Wizard in Context Menu >>> */ +/* +;// HT32 Device +;// <0=> By Project Asm Define +;// <10=> HT32F0006 +;// <10=> HT32F61352 +;// <17=> HT32F61355/56/57 +*/ + .equ USE_HT32_CHIP_SET, 0 + + .equ _HT32FWID, 0xFFFFFFFF +/* + .equ _HT32FWID, 0x00000006 + .equ _HT32FWID, 0x00061352 + .equ _HT32FWID, 0x00061355 + .equ _HT32FWID, 0x00061356 + .equ _HT32FWID, 0x00061357 +*/ + + .equ HT32F0006, 10 + .equ HT32F61352, 10 + .equ HT32F61355_56_57, 17 + + .if USE_HT32_CHIP_SET == 0 + .else + .equ USE_HT32_CHIP, USE_HT32_CHIP_SET + .endif + +/* +; Amount of memory (in bytes) allocated for Stack and Heap +; Tailor those values to your application needs +;// Stack Size (in Bytes, must 8 byte aligned) <:8> +*/ + .equ Stack_Size, 512 + .section ".stack", "w" + .align 3 + .globl __cs3_stack_mem + .globl __cs3_stack + .globl __cs3_stack_size + .globl __HT_check_sp +__HT_check_sp: +__cs3_stack_mem: + .if Stack_Size + .space Stack_Size + .endif +__cs3_stack: + .size __cs3_stack_mem, . - __cs3_stack_mem + .set __cs3_stack_size, . - __cs3_stack_mem + +/* +;// Heap Size (in Bytes) <:8> +*/ + .equ Heap_Size, 0 + .section ".heap", "w" + .align 3 + .globl __cs3_heap_start + .globl __cs3_heap_end + .globl __HT_check_heap +__HT_check_heap: +__cs3_heap_start: + .if Heap_Size + .space Heap_Size + .endif +__cs3_heap_end: + + .equ _RESERVED, 0xFFFFFFFF +/* +;******************************************************************************* +; Fill-up the Vector Table entries with the exceptions ISR address +;********************************************************************************/ + .section ".cs3.interrupt_vector" + .globl __cs3_interrupt_vector_cortex_m + .type __cs3_interrupt_vector_cortex_m, %object +__cs3_interrupt_vector_cortex_m: + .long __cs3_stack /* ---, 00, 0x000, Top address of Stack */ + .long __cs3_reset /* ---, 01, 0x004, Reset Handler */ + .long NMI_Handler /* -14, 02, 0x008, NMI Handler */ + .long HardFault_Handler /* -13, 03, 0x00C, Hard Fault Handler */ + .long _RESERVED /* ---, 04, 0x010, Reserved */ + .long _RESERVED /* ---, 05, 0x014, Reserved */ + .long _RESERVED /* ---, 06, 0x018, Reserved */ + .long _RESERVED /* ---, 07, 0x01C, Reserved */ + .long _HT32FWID /* ---, 08, 0x020, Reserved */ + .long _RESERVED /* ---, 09, 0x024, Reserved */ + .long _RESERVED /* ---, 10, 0x028, Reserved */ + .long SVC_Handler /* -05, 11, 0x02C, SVC Handler */ + .long _RESERVED /* ---, 12, 0x030, Reserved */ + .long _RESERVED /* ---, 13, 0x034, Reserved */ + .long PendSV_Handler /* -02, 14, 0x038, PendSV Handler */ + .long SysTick_Handler /* -01, 15, 0x03C, SysTick Handler */ + + /* External Interrupt Handler */ + .long LVD_BOD_IRQHandler /* 00, 16, 0x040, */ + .long RTC_IRQHandler /* 01, 17, 0x044, */ + .long FLASH_IRQHandler /* 02, 18, 0x048, */ + .long EVWUP_IRQHandler /* 03, 19, 0x04C, */ + .long EXTI0_1_IRQHandler /* 04, 20, 0x050, */ + .long EXTI2_3_IRQHandler /* 05, 21, 0x054, */ + .long EXTI4_15_IRQHandler /* 06, 22, 0x058, */ + .long _RESERVED /* 07, 23, 0x05C, */ + .long ADC_IRQHandler /* 08, 24, 0x060, */ + .long _RESERVED /* 09, 25, 0x064, */ + .long _RESERVED /* 10, 26, 0x068, */ + .long _RESERVED /* 11, 27, 0x06C, */ + .long GPTM0_IRQHandler /* 12, 28, 0x070, */ + .long SCTM0_IRQHandler /* 13, 29, 0x074, */ + .long SCTM1_IRQHandler /* 14, 30, 0x078, */ + .long SCTM2_IRQHandler /* 15, 31, 0x07C, */ + .long SCTM3_IRQHandler /* 16, 32, 0x080, */ + .long BFTM0_IRQHandler /* 17, 33, 0x084, */ + .long BFTM1_IRQHandler /* 18, 34, 0x088, */ + .long I2C0_IRQHandler /* 19, 35, 0x08C, */ + .long _RESERVED /* 20, 36, 0x090, */ + .long SPI0_IRQHandler /* 21, 37, 0x094, */ + .long QSPI_IRQHandler /* 22, 38, 0x098, */ + .long USART0_IRQHandler /* 23, 39, 0x09C, */ + .long _RESERVED /* 24, 40, 0x0A0, */ + .long UART0_IRQHandler /* 25, 41, 0x0A4, */ + .long _RESERVED /* 26, 42, 0x0A8, */ + .long MIDI_IRQHandler /* 27, 43, 0x0AC, */ + .long I2S_IRQHandler /* 28, 44, 0x0B0, */ + .long USB_IRQHandler /* 29, 45, 0x0B4, */ + .long PDMA_CH0_1_IRQHandler /* 30, 46, 0x0B8, */ + .long PDMA_CH2_5_IRQHandler /* 31, 47, 0x0BC, */ + + .size __cs3_interrupt_vector_cortex_m, . - __cs3_interrupt_vector_cortex_m + + + .thumb + + +/* Reset Handler */ + + .section .cs3.reset,"x",%progbits + .thumb_func + .globl __cs3_reset_cortex_m + .type __cs3_reset_cortex_m, %function +__cs3_reset_cortex_m: + .fnstart + LDR R0, =BootProcess + BLX R0 + LDR R0, =SystemInit + BLX R0 + LDR R0, =_start + BX R0 + .thumb_func +BootProcess: + LDR R0, =0x40080300 + LDR R1,[R0, #0x10] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x14] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x18] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x1C] + CMP R1, #0 + BEQ BP2 +BP1: + LDR R0, =0x40080180 + LDR R1,[R0, #0xC] + LSL R1, R1, #4 + LSR R1, R1, #20 + CMP R1, #0 + BEQ BP3 + CMP R1, #5 + BEQ BP3 + CMP R1, #6 + BEQ BP3 +BP2: + DSB + LDR R0, =0x20000000 + LDR R1, =0x05fa0004 + STR R1, [R0] + LDR R1, =0xe000ed00 + LDR R0, =0x05fa0004 + STR R0, [R1, #0xC] + DSB + B . +BP3: + LDR R0, =0x20000000 + LDR R1, [R0] + LDR R0, =0x05fa0004 + CMP R0, R1 + BEQ BP4 + BX LR +BP4: + LDR R0, =0x40088100 + LDR R1, =0x00000001 + STR R1, [R0] + LDR R0, =0x20000000 + LDR R1, =0x0 + STR R1, [R0] + BX LR + .pool + .cantunwind + .fnend + .size __cs3_reset_cortex_m,.-__cs3_reset_cortex_m + + .section ".text" + +/* Exception Handlers */ + + .weak NMI_Handler + .type NMI_Handler, %function +NMI_Handler: + B . + .size NMI_Handler, . - NMI_Handler + + .weak HardFault_Handler + .type HardFault_Handler, %function +HardFault_Handler: + B . + .size HardFault_Handler, . - HardFault_Handler + + .weak SVC_Handler + .type SVC_Handler, %function +SVC_Handler: + B . + .size SVC_Handler, . - SVC_Handler + + .weak PendSV_Handler + .type PendSV_Handler, %function +PendSV_Handler: + B . + .size PendSV_Handler, . - PendSV_Handler + + .weak SysTick_Handler + .type SysTick_Handler, %function +SysTick_Handler: + B . + .size SysTick_Handler, . - SysTick_Handler + + +/* IRQ Handlers */ + + .globl Default_Handler + .type Default_Handler, %function +Default_Handler: + B . + .size Default_Handler, . - Default_Handler + + .macro IRQ handler + .weak \handler + .set \handler, Default_Handler + .endm + + IRQ LVD_BOD_IRQHandler + IRQ RTC_IRQHandler + IRQ FLASH_IRQHandler + IRQ EVWUP_IRQHandler + IRQ EXTI0_1_IRQHandler + IRQ EXTI2_3_IRQHandler + IRQ EXTI4_15_IRQHandler + IRQ ADC_IRQHandler + IRQ GPTM0_IRQHandler + IRQ SCTM0_IRQHandler + IRQ SCTM1_IRQHandler + IRQ SCTM2_IRQHandler + IRQ SCTM3_IRQHandler + IRQ BFTM0_IRQHandler + IRQ BFTM1_IRQHandler + IRQ I2C0_IRQHandler + IRQ SPI0_IRQHandler + IRQ QSPI_IRQHandler + IRQ USART0_IRQHandler + IRQ UART0_IRQHandler + IRQ MIDI_IRQHandler + IRQ I2S_IRQHandler + IRQ USB_IRQHandler + IRQ PDMA_CH0_1_IRQHandler + IRQ PDMA_CH2_5_IRQHandler + + .end diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/CodeSourcery/startup_ht32f5xxxx_cs3_08.s b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/CodeSourcery/startup_ht32f5xxxx_cs3_08.s new file mode 100644 index 0000000000..3c0ee31039 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/CodeSourcery/startup_ht32f5xxxx_cs3_08.s @@ -0,0 +1,258 @@ +/*---------------------------------------------------------------------------------------------------------*/ +/* Holtek Semiconductor Inc. */ +/* */ +/* Copyright (C) Holtek Semiconductor Inc. */ +/* All rights reserved. */ +/* */ +/*----------------------------------------------------------------------------------------------------------- +; File Name : startup_ht32f5xxxx_cs3_08.s +; Version : $Rev:: 6887 $ +; Date : $Date:: 2023-05-05 #$ +; Description : Startup code. +;-----------------------------------------------------------------------------------------------------------*/ + +/* +; Supported Device +; ======================================== +; HT32F65230, HT32F65240 +; HT32F65232 +; HT50F3200S +*/ + +;/* <<< Use Configuration Wizard in Context Menu >>> */ +/* +;// HT32 Device +;// <0=> By Project Asm Define +;// <12=> HT32F65230_40 +;// <18=> HT32F65232 +;// <12=> HT50F3200S +*/ + .equ USE_HT32_CHIP_SET, 0 + + .equ _HT32FWID, 0xFFFFFFFF +/* + .equ _HT32FWID, 0x00065230 + .equ _HT32FWID, 0x00065240 + .equ _HT32FWID, 0x00065232 + .equ _HT32FWID, 0x0003200F +*/ + + .equ HT32F65230_40, 12 + .equ HT32F65232, 18 + .equ HT50F3200S, 12 + + .if USE_HT32_CHIP_SET == 0 + .else + .equ USE_HT32_CHIP, USE_HT32_CHIP_SET + .endif + +/* +; Amount of memory (in bytes) allocated for Stack and Heap +; Tailor those values to your application needs +;// Stack Size (in Bytes, must 8 byte aligned) <:8> +*/ + .equ Stack_Size, 512 + .section ".stack", "w" + .align 3 + .globl __cs3_stack_mem + .globl __cs3_stack + .globl __cs3_stack_size + .globl __HT_check_sp +__HT_check_sp: +__cs3_stack_mem: + .if Stack_Size + .space Stack_Size + .endif +__cs3_stack: + .size __cs3_stack_mem, . - __cs3_stack_mem + .set __cs3_stack_size, . - __cs3_stack_mem + +/* +;// Heap Size (in Bytes) <:8> +*/ + .equ Heap_Size, 0 + .section ".heap", "w" + .align 3 + .globl __cs3_heap_start + .globl __cs3_heap_end + .globl __HT_check_heap +__HT_check_heap: +__cs3_heap_start: + .if Heap_Size + .space Heap_Size + .endif +__cs3_heap_end: + + .equ _RESERVED, 0xFFFFFFFF +/* +;******************************************************************************* +; Fill-up the Vector Table entries with the exceptions ISR address +;********************************************************************************/ + .section ".cs3.interrupt_vector" + .globl __cs3_interrupt_vector_cortex_m + .type __cs3_interrupt_vector_cortex_m, %object +__cs3_interrupt_vector_cortex_m: + .long __cs3_stack /* ---, 00, 0x000, Top address of Stack */ + .long __cs3_reset /* ---, 01, 0x004, Reset Handler */ + .long NMI_Handler /* -14, 02, 0x008, NMI Handler */ + .long HardFault_Handler /* -13, 03, 0x00C, Hard Fault Handler */ + .long _RESERVED /* ---, 04, 0x010, Reserved */ + .long _RESERVED /* ---, 05, 0x014, Reserved */ + .long _RESERVED /* ---, 06, 0x018, Reserved */ + .long _RESERVED /* ---, 07, 0x01C, Reserved */ + .long _HT32FWID /* ---, 08, 0x020, Reserved */ + .long _RESERVED /* ---, 09, 0x024, Reserved */ + .long _RESERVED /* ---, 10, 0x028, Reserved */ + .long SVC_Handler /* -05, 11, 0x02C, SVC Handler */ + .long _RESERVED /* ---, 12, 0x030, Reserved */ + .long _RESERVED /* ---, 13, 0x034, Reserved */ + .long PendSV_Handler /* -02, 14, 0x038, PendSV Handler */ + .long SysTick_Handler /* -01, 15, 0x03C, SysTick Handler */ + + /* External Interrupt Handler */ + .long LVD_BOD_IRQHandler /* 00, 16, 0x040, */ + .long RTC_IRQHandler /* 01, 17, 0x044, */ + .long FLASH_IRQHandler /* 02, 18, 0x048, */ + .long EVWUP_IRQHandler /* 03, 19, 0x04C, */ + .long EXTI0_1_IRQHandler /* 04, 20, 0x050, */ + .long EXTI2_3_IRQHandler /* 05, 21, 0x054, */ + .long EXTI4_9_IRQHandler /* 06, 22, 0x058, */ + .long EXTI10_15_IRQHandler /* 07, 23, 0x05C, */ + .long ADC0_IRQHandler /* 08, 24, 0x060, */ + .if (USE_HT32_CHIP==HT32F65230_40) + .long ADC1_IRQHandler /* 09, 25, 0x064, */ + .else + .long _RESERVED /* 09, 25, 0x064, */ + .endif + .long MCTM0_BRK_IRQHandler /* 10, 26, 0x068, */ + .long MCTM0_UP_IRQHandler /* 11, 27, 0x06C, */ + .long MCTM0_TR_UP2_IRQHandler /* 12, 28, 0x070, */ + .long MCTM0_CC_IRQHandler /* 13, 29, 0x074, */ + .long GPTM0_G_IRQHandler /* 14, 30, 0x078, */ + .long GPTM0_VCLK_IRQHandler /* 15, 31, 0x07C, */ + .long BFTM0_IRQHandler /* 16, 32, 0x080, */ + .long BFTM1_IRQHandler /* 17, 33, 0x084, */ + .long CMP0_IRQHandler /* 18, 34, 0x088, */ + .long CMP1_IRQHandler /* 19, 35, 0x08C, */ + .if (USE_HT32_CHIP==HT32F65230_40) + .long CMP2_IRQHandler /* 20, 36, 0x090, */ + .else + .long _RESERVED /* 20, 36, 0x090, */ + .endif + .long I2C0_IRQHandler /* 21, 37, 0x094, */ + .long SPI0_IRQHandler /* 22, 38, 0x098, */ + .long USART0_IRQHandler /* 23, 39, 0x09C, */ + .long UART0_IRQHandler /* 24, 40, 0x0A0, */ + .long PDMA_CH0_1_IRQHandler /* 25, 41, 0x0A4, */ + .long PDMA_CH2_3_IRQHandler /* 26, 42, 0x0A8, */ + .long PDMA_CH4_5_IRQHandler /* 27, 43, 0x0AC, */ + .long SCTM0_IRQHandler /* 28, 44, 0x0B0, */ + .long SCTM1_IRQHandler /* 29, 45, 0x0B4, */ + .long SCTM2_IRQHandler /* 30, 46, 0x0B8, */ + .long SCTM3_IRQHandler /* 31, 47, 0x0BC, */ + + .size __cs3_interrupt_vector_cortex_m, . - __cs3_interrupt_vector_cortex_m + + + .thumb + + +/* Reset Handler */ + + .section .cs3.reset,"x",%progbits + .thumb_func + .globl __cs3_reset_cortex_m + .type __cs3_reset_cortex_m, %function +__cs3_reset_cortex_m: + .fnstart + LDR R0, =SystemInit + BLX R0 + LDR R0, =_start + BX R0 + .pool + .cantunwind + .fnend + .size __cs3_reset_cortex_m,.-__cs3_reset_cortex_m + + .section ".text" + +/* Exception Handlers */ + + .weak NMI_Handler + .type NMI_Handler, %function +NMI_Handler: + B . + .size NMI_Handler, . - NMI_Handler + + .weak HardFault_Handler + .type HardFault_Handler, %function +HardFault_Handler: + B . + .size HardFault_Handler, . - HardFault_Handler + + .weak SVC_Handler + .type SVC_Handler, %function +SVC_Handler: + B . + .size SVC_Handler, . - SVC_Handler + + .weak PendSV_Handler + .type PendSV_Handler, %function +PendSV_Handler: + B . + .size PendSV_Handler, . - PendSV_Handler + + .weak SysTick_Handler + .type SysTick_Handler, %function +SysTick_Handler: + B . + .size SysTick_Handler, . - SysTick_Handler + + +/* IRQ Handlers */ + + .globl Default_Handler + .type Default_Handler, %function +Default_Handler: + B . + .size Default_Handler, . - Default_Handler + + .macro IRQ handler + .weak \handler + .set \handler, Default_Handler + .endm + + IRQ LVD_BOD_IRQHandler + IRQ RTC_IRQHandler + IRQ FLASH_IRQHandler + IRQ EVWUP_IRQHandler + IRQ EXTI0_1_IRQHandler + IRQ EXTI2_3_IRQHandler + IRQ EXTI4_9_IRQHandler + IRQ EXTI10_15_IRQHandler + IRQ ADC0_IRQHandler + IRQ ADC1_IRQHandler + IRQ MCTM0_BRK_IRQHandler + IRQ MCTM0_UP_IRQHandler + IRQ MCTM0_TR_UP2_IRQHandler + IRQ MCTM0_CC_IRQHandler + IRQ GPTM0_G_IRQHandler + IRQ GPTM0_VCLK_IRQHandler + IRQ BFTM0_IRQHandler + IRQ BFTM1_IRQHandler + IRQ CMP0_IRQHandler + IRQ CMP1_IRQHandler + IRQ CMP2_IRQHandler + IRQ I2C0_IRQHandler + IRQ SPI0_IRQHandler + IRQ USART0_IRQHandler + IRQ UART0_IRQHandler + IRQ PDMA_CH0_1_IRQHandler + IRQ PDMA_CH2_3_IRQHandler + IRQ PDMA_CH4_5_IRQHandler + IRQ SCTM0_IRQHandler + IRQ SCTM1_IRQHandler + IRQ SCTM2_IRQHandler + IRQ SCTM3_IRQHandler + + .end diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/CodeSourcery/startup_ht32f5xxxx_cs3_09.s b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/CodeSourcery/startup_ht32f5xxxx_cs3_09.s new file mode 100644 index 0000000000..f30b6881fb --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/CodeSourcery/startup_ht32f5xxxx_cs3_09.s @@ -0,0 +1,329 @@ +/*---------------------------------------------------------------------------------------------------------*/ +/* Holtek Semiconductor Inc. */ +/* */ +/* Copyright (C) Holtek Semiconductor Inc. */ +/* All rights reserved. */ +/* */ +/*----------------------------------------------------------------------------------------------------------- +; File Name : startup_ht32f5xxxx_cs3_09.s +; Version : $Rev:: 6206 $ +; Date : $Date:: 2022-10-05 #$ +; Description : Startup code. +;-----------------------------------------------------------------------------------------------------------*/ + +/* +; Supported Device +; ======================================== +; HT32F54231, HT32F54241 +; HT32F54243, HT32F54253 +*/ + +;/* <<< Use Configuration Wizard in Context Menu >>> */ +/* +;// HT32 Device +;// <0=> By Project Asm Define +;// <19=> HT32F54231/41 +;// <20=> HT32F54243/53 +*/ + .equ USE_HT32_CHIP_SET, 0 + + .equ _HT32FWID, 0xFFFFFFFF +/* + .equ _HT32FWID, 0x00054231 + .equ _HT32FWID, 0x00054241 + .equ _HT32FWID, 0x00054243 + .equ _HT32FWID, 0x00054253 +*/ + + .equ HT32F54231_41, 19 + .equ HT32F54243_53, 20 + + .if USE_HT32_CHIP_SET == 0 + .else + .equ USE_HT32_CHIP, USE_HT32_CHIP_SET + .endif + +/* +; Amount of memory (in bytes) allocated for Stack and Heap +; Tailor those values to your application needs +;// Stack Size (in Bytes, must 8 byte aligned) <:8> +*/ + .equ Stack_Size, 512 + .section ".stack", "w" + .align 3 + .globl __cs3_stack_mem + .globl __cs3_stack + .globl __cs3_stack_size + .globl __HT_check_sp +__HT_check_sp: +__cs3_stack_mem: + .if Stack_Size + .space Stack_Size + .endif +__cs3_stack: + .size __cs3_stack_mem, . - __cs3_stack_mem + .set __cs3_stack_size, . - __cs3_stack_mem + +/* +;// Heap Size (in Bytes) <:8> +*/ + .equ Heap_Size, 0 + .section ".heap", "w" + .align 3 + .globl __cs3_heap_start + .globl __cs3_heap_end + .globl __HT_check_heap +__HT_check_heap: +__cs3_heap_start: + .if Heap_Size + .space Heap_Size + .endif +__cs3_heap_end: + + .equ _RESERVED, 0xFFFFFFFF +/* +;******************************************************************************* +; Fill-up the Vector Table entries with the exceptions ISR address +;********************************************************************************/ + .section ".cs3.interrupt_vector" + .globl __cs3_interrupt_vector_cortex_m + .type __cs3_interrupt_vector_cortex_m, %object +__cs3_interrupt_vector_cortex_m: + .long __cs3_stack /* ---, 00, 0x000, Top address of Stack */ + .long __cs3_reset /* ---, 01, 0x004, Reset Handler */ + .long NMI_Handler /* -14, 02, 0x008, NMI Handler */ + .long HardFault_Handler /* -13, 03, 0x00C, Hard Fault Handler */ + .long _RESERVED /* ---, 04, 0x010, Reserved */ + .long _RESERVED /* ---, 05, 0x014, Reserved */ + .long _RESERVED /* ---, 06, 0x018, Reserved */ + .long _RESERVED /* ---, 07, 0x01C, Reserved */ + .long _HT32FWID /* ---, 08, 0x020, Reserved */ + .long _RESERVED /* ---, 09, 0x024, Reserved */ + .long _RESERVED /* ---, 10, 0x028, Reserved */ + .long SVC_Handler /* -05, 11, 0x02C, SVC Handler */ + .long _RESERVED /* ---, 12, 0x030, Reserved */ + .long _RESERVED /* ---, 13, 0x034, Reserved */ + .long PendSV_Handler /* -02, 14, 0x038, PendSV Handler */ + .long SysTick_Handler /* -01, 15, 0x03C, SysTick Handler */ + + /* External Interrupt Handler */ + .long LVD_BOD_IRQHandler /* 00, 16, 0x040, */ + .long RTC_IRQHandler /* 01, 17, 0x044, */ + .long FLASH_IRQHandler /* 02, 18, 0x048, */ + .long EVWUP_IRQHandler /* 03, 19, 0x04C, */ + .long EXTI0_1_IRQHandler /* 04, 20, 0x050, */ + .long EXTI2_3_IRQHandler /* 05, 21, 0x054, */ + .long EXTI4_15_IRQHandler /* 06, 22, 0x058, */ + .if (USE_HT32_CHIP==HT32F54231_41) + .long _RESERVED /* 07, 23, 0x05C, */ + .endif + .if (USE_HT32_CHIP==HT32F54243_53) + .long COMP_IRQHandler /* 07, 23, 0x05C, */ + .endif + .long ADC_IRQHandler /* 08, 24, 0x060, */ + .if (USE_HT32_CHIP==HT32F54231_41) + .long _RESERVED /* 09, 25, 0x064, */ + .endif + .if (USE_HT32_CHIP==HT32F54243_53) + .long I2C2_IRQHandler /* 09, 25, 0x064, */ + .endif + .long MCTM0_IRQHandler /* 10, 26, 0x068, */ + .long TKEY_IRQHandler /* 11, 27, 0x06C, */ + .long GPTM0_IRQHandler /* 12, 28, 0x070, */ + .long SCTM0_IRQHandler /* 13, 29, 0x074, */ + .long SCTM1_IRQHandler /* 14, 30, 0x078, */ + .if (USE_HT32_CHIP==HT32F54231_41) + .long _RESERVED /* 15, 31, 0x07C, */ + .long _RESERVED /* 16, 32, 0x080, */ + .endif + .if (USE_HT32_CHIP==HT32F54243_53) + .long SCTM2_IRQHandler /* 15, 31, 0x07C, */ + .long SCTM3_IRQHandler /* 16, 32, 0x080, */ + .endif + .long BFTM0_IRQHandler /* 17, 33, 0x084, */ + .long BFTM1_IRQHandler /* 18, 34, 0x088, */ + .long I2C0_IRQHandler /* 19, 35, 0x08C, */ + .long I2C1_IRQHandler /* 20, 36, 0x090, */ + .long SPI0_IRQHandler /* 21, 37, 0x094, */ + .long SPI1_IRQHandler /* 22, 38, 0x098, */ + .long USART0_IRQHandler /* 23, 39, 0x09C, */ + .if (USE_HT32_CHIP==HT32F54231_41) + .long _RESERVED /* 24, 40, 0x0A0, */ + .endif + .if (USE_HT32_CHIP==HT32F54243_53) + .long USART1_IRQHandler /* 24, 40, 0x0A0, */ + .endif + .long UART0_IRQHandler /* 25, 41, 0x0A4, */ + .long UART1_IRQHandler /* 26, 42, 0x0A8, */ + .if (USE_HT32_CHIP==HT32F54231_41) + .long _RESERVED /* 27, 43, 0x0AC, */ + .long _RESERVED /* 28, 44, 0x0B0, */ + .endif + .if (USE_HT32_CHIP==HT32F54243_53) + .long UART2_IRQHandler /* 27, 43, 0x0AC, */ + .long UART3_IRQHandler /* 28, 44, 0x0B0, */ + .endif + .long LEDC_IRQHandler /* 29, 45, 0x0B4, */ + .if (USE_HT32_CHIP==HT32F54243_53) + .long PDMA_CH0_1_IRQHandler /* 30, 46, 0x0B8, */ + .long PDMA_CH2_5_IRQHandler /* 31, 47, 0x0BC, */ + .endif + + .size __cs3_interrupt_vector_cortex_m, . - __cs3_interrupt_vector_cortex_m + + + .thumb + + +/* Reset Handler */ + + .section .cs3.reset,"x",%progbits + .thumb_func + .globl __cs3_reset_cortex_m + .type __cs3_reset_cortex_m, %function +__cs3_reset_cortex_m: + .fnstart + LDR R0, =BootProcess + BLX R0 + LDR R0, =SystemInit + BLX R0 + LDR R0, =_start + BX R0 + .thumb_func +BootProcess: + LDR R0, =0x40080300 + LDR R1,[R0, #0x10] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x14] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x18] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x1C] + CMP R1, #0 + BEQ BP2 +BP1: + LDR R0, =0x40080180 + LDR R1,[R0, #0xC] + LSL R1, R1, #4 + LSR R1, R1, #20 + CMP R1, #0 + BEQ BP3 + CMP R1, #5 + BEQ BP3 + CMP R1, #6 + BEQ BP3 +BP2: + DSB + LDR R0, =0x20000000 + LDR R1, =0x05fa0004 + STR R1, [R0] + LDR R1, =0xe000ed00 + LDR R0, =0x05fa0004 + STR R0, [R1, #0xC] + DSB + B . +BP3: + LDR R0, =0x20000000 + LDR R1, [R0] + LDR R0, =0x05fa0004 + CMP R0, R1 + BEQ BP4 + BX LR +BP4: + LDR R0, =0x40088100 + LDR R1, =0x00000001 + STR R1, [R0] + LDR R0, =0x20000000 + LDR R1, =0x0 + STR R1, [R0] + BX LR + .pool + .cantunwind + .fnend + .size __cs3_reset_cortex_m,.-__cs3_reset_cortex_m + + .section ".text" + +/* Exception Handlers */ + + .weak NMI_Handler + .type NMI_Handler, %function +NMI_Handler: + B . + .size NMI_Handler, . - NMI_Handler + + .weak HardFault_Handler + .type HardFault_Handler, %function +HardFault_Handler: + B . + .size HardFault_Handler, . - HardFault_Handler + + .weak SVC_Handler + .type SVC_Handler, %function +SVC_Handler: + B . + .size SVC_Handler, . - SVC_Handler + + .weak PendSV_Handler + .type PendSV_Handler, %function +PendSV_Handler: + B . + .size PendSV_Handler, . - PendSV_Handler + + .weak SysTick_Handler + .type SysTick_Handler, %function +SysTick_Handler: + B . + .size SysTick_Handler, . - SysTick_Handler + + +/* IRQ Handlers */ + + .globl Default_Handler + .type Default_Handler, %function +Default_Handler: + B . + .size Default_Handler, . - Default_Handler + + .macro IRQ handler + .weak \handler + .set \handler, Default_Handler + .endm + + IRQ LVD_BOD_IRQHandler + IRQ RTC_IRQHandler + IRQ FLASH_IRQHandler + IRQ EVWUP_IRQHandler + IRQ EXTI0_1_IRQHandler + IRQ EXTI2_3_IRQHandler + IRQ EXTI4_15_IRQHandler + IRQ COMP_IRQHandler + IRQ ADC_IRQHandler + IRQ I2C2_IRQHandler + IRQ MCTM0_IRQHandler + IRQ TKEY_IRQHandler + IRQ GPTM0_IRQHandler + IRQ SCTM0_IRQHandler + IRQ SCTM1_IRQHandler + IRQ SCTM2_IRQHandler + IRQ SCTM3_IRQHandler + IRQ BFTM0_IRQHandler + IRQ BFTM1_IRQHandler + IRQ I2C0_IRQHandler + IRQ I2C1_IRQHandler + IRQ SPI0_IRQHandler + IRQ SPI1_IRQHandler + IRQ USART0_IRQHandler + IRQ USART1_IRQHandler + IRQ UART0_IRQHandler + IRQ UART1_IRQHandler + IRQ UART2_IRQHandler + IRQ UART3_IRQHandler + IRQ LEDC_IRQHandler + IRQ PDMA_CH0_1_IRQHandler + IRQ PDMA_CH2_5_IRQHandler + + .end diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/CodeSourcery/startup_ht32f5xxxx_cs3_10.s b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/CodeSourcery/startup_ht32f5xxxx_cs3_10.s new file mode 100644 index 0000000000..c2fb7bd028 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/CodeSourcery/startup_ht32f5xxxx_cs3_10.s @@ -0,0 +1,230 @@ +/*---------------------------------------------------------------------------------------------------------*/ +/* Holtek Semiconductor Inc. */ +/* */ +/* Copyright (C) Holtek Semiconductor Inc. */ +/* All rights reserved. */ +/* */ +/*----------------------------------------------------------------------------------------------------------- +; File Name : startup_ht32f5xxxx_cs3_10.s +; Version : $Rev:: 6601 $ +; Date : $Date:: 2022-12-27 #$ +; Description : Startup code. +;-----------------------------------------------------------------------------------------------------------*/ + +/* +; Supported Device +; ======================================== +; HT32F61244, HT32F61245 +*/ + +;/* <<< Use Configuration Wizard in Context Menu >>> */ +/* +;// HT32 Device +;// <0=> By Project Asm Define +;// <24=> HT32F61244/45 +*/ + .equ USE_HT32_CHIP_SET, 0 + + .equ _HT32FWID, 0xFFFFFFFF +/* + .equ _HT32FWID, 0x00061244 + .equ _HT32FWID, 0x00061245 +*/ + + .equ HT32F61244_45, 24 + + .if USE_HT32_CHIP_SET == 0 + .else + .equ USE_HT32_CHIP, USE_HT32_CHIP_SET + .endif + +/* +; Amount of memory (in bytes) allocated for Stack and Heap +; Tailor those values to your application needs +;// Stack Size (in Bytes, must 8 byte aligned) <:8> +*/ + .equ Stack_Size, 512 + .section ".stack", "w" + .align 3 + .globl __cs3_stack_mem + .globl __cs3_stack + .globl __cs3_stack_size + .globl __HT_check_sp +__HT_check_sp: +__cs3_stack_mem: + .if Stack_Size + .space Stack_Size + .endif +__cs3_stack: + .size __cs3_stack_mem, . - __cs3_stack_mem + .set __cs3_stack_size, . - __cs3_stack_mem + +/* +;// Heap Size (in Bytes) <:8> +*/ + .equ Heap_Size, 0 + .section ".heap", "w" + .align 3 + .globl __cs3_heap_start + .globl __cs3_heap_end + .globl __HT_check_heap +__HT_check_heap: +__cs3_heap_start: + .if Heap_Size + .space Heap_Size + .endif +__cs3_heap_end: + + .equ _RESERVED, 0xFFFFFFFF +/* +;******************************************************************************* +; Fill-up the Vector Table entries with the exceptions ISR address +;********************************************************************************/ + .section ".cs3.interrupt_vector" + .globl __cs3_interrupt_vector_cortex_m + .type __cs3_interrupt_vector_cortex_m, %object +__cs3_interrupt_vector_cortex_m: + .long __cs3_stack /* ---, 00, 0x000, Top address of Stack */ + .long __cs3_reset /* ---, 01, 0x004, Reset Handler */ + .long NMI_Handler /* -14, 02, 0x008, NMI Handler */ + .long HardFault_Handler /* -13, 03, 0x00C, Hard Fault Handler */ + .long _RESERVED /* ---, 04, 0x010, Reserved */ + .long _RESERVED /* ---, 05, 0x014, Reserved */ + .long _RESERVED /* ---, 06, 0x018, Reserved */ + .long _RESERVED /* ---, 07, 0x01C, Reserved */ + .long _HT32FWID /* ---, 08, 0x020, Reserved */ + .long _RESERVED /* ---, 09, 0x024, Reserved */ + .long _RESERVED /* ---, 10, 0x028, Reserved */ + .long SVC_Handler /* -05, 11, 0x02C, SVC Handler */ + .long _RESERVED /* ---, 12, 0x030, Reserved */ + .long _RESERVED /* ---, 13, 0x034, Reserved */ + .long PendSV_Handler /* -02, 14, 0x038, PendSV Handler */ + .long SysTick_Handler /* -01, 15, 0x03C, SysTick Handler */ + + /* External Interrupt Handler */ + .long LVD_BOD_IRQHandler /* 00, 16, 0x040, */ + .long RTC_IRQHandler /* 01, 17, 0x044, */ + .long FLASH_IRQHandler /* 02, 18, 0x048, */ + .long EVWUP_IRQHandler /* 03, 19, 0x04C, */ + .long EXTI0_1_IRQHandler /* 04, 20, 0x050, */ + .long EXTI2_3_IRQHandler /* 05, 21, 0x054, */ + .long EXTI4_15_IRQHandler /* 06, 22, 0x058, */ + .long _RESERVED /* 07, 23, 0x05C, */ + .long ADC_IRQHandler /* 08, 24, 0x060, */ + .long _RESERVED /* 09, 25, 0x064, */ + .long _RESERVED /* 10, 26, 0x068, */ + .long _RESERVED /* 11, 27, 0x06C, */ + .long GPTM0_IRQHandler /* 12, 28, 0x070, */ + .long SCTM0_IRQHandler /* 13, 29, 0x074, */ + .long SCTM1_IRQHandler /* 14, 30, 0x078, */ + .long _RESERVED /* 15, 31, 0x07C, */ + .long _RESERVED /* 16, 32, 0x080, */ + .long BFTM0_IRQHandler /* 17, 33, 0x084, */ + .long BFTM1_IRQHandler /* 18, 34, 0x088, */ + .long I2C0_IRQHandler /* 19, 35, 0x08C, */ + .long _RESERVED /* 20, 36, 0x090, */ + .long SPI0_IRQHandler /* 21, 37, 0x094, */ + .long QSPI_IRQHandler /* 22, 38, 0x098, */ + .long _RESERVED /* 23, 39, 0x09C, */ + .long _RESERVED /* 24, 40, 0x0A0, */ + .long UART0_IRQHandler /* 25, 41, 0x0A4, */ + .long _RESERVED /* 26, 42, 0x0A8, */ + .long MIDI_IRQHandler /* 27, 43, 0x0AC, */ + .long _RESERVED /* 28, 44, 0x0B0, */ + .long _RESERVED /* 29, 45, 0x0B4, */ + .long PDMA_CH0_1_IRQHandler /* 30, 46, 0x0B8, */ + .long PDMA_CH2_5_IRQHandler /* 31, 47, 0x0BC, */ + + .size __cs3_interrupt_vector_cortex_m, . - __cs3_interrupt_vector_cortex_m + + + .thumb + + +/* Reset Handler */ + + .section .cs3.reset,"x",%progbits + .thumb_func + .globl __cs3_reset_cortex_m + .type __cs3_reset_cortex_m, %function +__cs3_reset_cortex_m: + .fnstart + LDR R0, =SystemInit + BLX R0 + LDR R0, =_start + BX R0 + .pool + .cantunwind + .fnend + .size __cs3_reset_cortex_m,.-__cs3_reset_cortex_m + + .section ".text" + +/* Exception Handlers */ + + .weak NMI_Handler + .type NMI_Handler, %function +NMI_Handler: + B . + .size NMI_Handler, . - NMI_Handler + + .weak HardFault_Handler + .type HardFault_Handler, %function +HardFault_Handler: + B . + .size HardFault_Handler, . - HardFault_Handler + + .weak SVC_Handler + .type SVC_Handler, %function +SVC_Handler: + B . + .size SVC_Handler, . - SVC_Handler + + .weak PendSV_Handler + .type PendSV_Handler, %function +PendSV_Handler: + B . + .size PendSV_Handler, . - PendSV_Handler + + .weak SysTick_Handler + .type SysTick_Handler, %function +SysTick_Handler: + B . + .size SysTick_Handler, . - SysTick_Handler + + +/* IRQ Handlers */ + + .globl Default_Handler + .type Default_Handler, %function +Default_Handler: + B . + .size Default_Handler, . - Default_Handler + + .macro IRQ handler + .weak \handler + .set \handler, Default_Handler + .endm + + IRQ LVD_BOD_IRQHandler + IRQ RTC_IRQHandler + IRQ FLASH_IRQHandler + IRQ EVWUP_IRQHandler + IRQ EXTI0_1_IRQHandler + IRQ EXTI2_3_IRQHandler + IRQ EXTI4_15_IRQHandler + IRQ ADC_IRQHandler + IRQ GPTM0_IRQHandler + IRQ SCTM0_IRQHandler + IRQ SCTM1_IRQHandler + IRQ BFTM0_IRQHandler + IRQ BFTM1_IRQHandler + IRQ I2C0_IRQHandler + IRQ SPI0_IRQHandler + IRQ QSPI_IRQHandler + IRQ UART0_IRQHandler + IRQ MIDI_IRQHandler + IRQ PDMA_CH0_1_IRQHandler + IRQ PDMA_CH2_5_IRQHandler + + .end diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/CodeSourcery/startup_ht32f5xxxx_cs3_11.s b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/CodeSourcery/startup_ht32f5xxxx_cs3_11.s new file mode 100644 index 0000000000..465d0db99d --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/CodeSourcery/startup_ht32f5xxxx_cs3_11.s @@ -0,0 +1,235 @@ +/*---------------------------------------------------------------------------------------------------------*/ +/* Holtek Semiconductor Inc. */ +/* */ +/* Copyright (C) Holtek Semiconductor Inc. */ +/* All rights reserved. */ +/* */ +/*----------------------------------------------------------------------------------------------------------- +; File Name : startup_ht32f5xxxx_cs3_11.s +; Version : $Rev:: 6206 $ +; Date : $Date:: 2022-10-05 #$ +; Description : Startup code. +;-----------------------------------------------------------------------------------------------------------*/ + +/* +; Supported Device +; ======================================== +; HT32F67041, HT32F67051 +*/ + +;/* <<< Use Configuration Wizard in Context Menu >>> */ +/* +;// HT32 Device +;// <0=> By Project Asm Define +;// <22=> HT32F67041/51 +*/ + .equ USE_HT32_CHIP_SET, 0 + + .equ _HT32FWID, 0xFFFFFFFF +/* + .equ _HT32FWID, 0x00067041 + .equ _HT32FWID, 0x00067051 +*/ + + .equ HT32F67041_51, 22 + + .if USE_HT32_CHIP_SET == 0 + .else + .equ USE_HT32_CHIP, USE_HT32_CHIP_SET + .endif + +/* +; Amount of memory (in bytes) allocated for Stack and Heap +; Tailor those values to your application needs +;// Stack Size (in Bytes, must 8 byte aligned) <:8> +*/ + .equ Stack_Size, 512 + .section ".stack", "w" + .align 3 + .globl __cs3_stack_mem + .globl __cs3_stack + .globl __cs3_stack_size + .globl __HT_check_sp +__HT_check_sp: +__cs3_stack_mem: + .if Stack_Size + .space Stack_Size + .endif +__cs3_stack: + .size __cs3_stack_mem, . - __cs3_stack_mem + .set __cs3_stack_size, . - __cs3_stack_mem + +/* +;// Heap Size (in Bytes) <:8> +*/ + .equ Heap_Size, 0 + .section ".heap", "w" + .align 3 + .globl __cs3_heap_start + .globl __cs3_heap_end + .globl __HT_check_heap +__HT_check_heap: +__cs3_heap_start: + .if Heap_Size + .space Heap_Size + .endif +__cs3_heap_end: + + .equ _RESERVED, 0xFFFFFFFF +/* +;******************************************************************************* +; Fill-up the Vector Table entries with the exceptions ISR address +;********************************************************************************/ + .section ".cs3.interrupt_vector" + .globl __cs3_interrupt_vector_cortex_m + .type __cs3_interrupt_vector_cortex_m, %object +__cs3_interrupt_vector_cortex_m: + .long __cs3_stack /* ---, 00, 0x000, Top address of Stack */ + .long __cs3_reset /* ---, 01, 0x004, Reset Handler */ + .long NMI_Handler /* -14, 02, 0x008, NMI Handler */ + .long HardFault_Handler /* -13, 03, 0x00C, Hard Fault Handler */ + .long _RESERVED /* ---, 04, 0x010, Reserved */ + .long _RESERVED /* ---, 05, 0x014, Reserved */ + .long _RESERVED /* ---, 06, 0x018, Reserved */ + .long _RESERVED /* ---, 07, 0x01C, Reserved */ + .long _HT32FWID /* ---, 08, 0x020, Reserved */ + .long _RESERVED /* ---, 09, 0x024, Reserved */ + .long _RESERVED /* ---, 10, 0x028, Reserved */ + .long SVC_Handler /* -05, 11, 0x02C, SVC Handler */ + .long _RESERVED /* ---, 12, 0x030, Reserved */ + .long _RESERVED /* ---, 13, 0x034, Reserved */ + .long PendSV_Handler /* -02, 14, 0x038, PendSV Handler */ + .long SysTick_Handler /* -01, 15, 0x03C, SysTick Handler */ + + /* External Interrupt Handler */ + .long LVD_BOD_IRQHandler /* 00, 16, 0x040, */ + .long RTC_IRQHandler /* 01, 17, 0x044, */ + .long FLASH_IRQHandler /* 02, 18, 0x048, */ + .long EVWUP_IRQHandler /* 03, 19, 0x04C, */ + .long EXTI0_1_IRQHandler /* 04, 20, 0x050, */ + .long EXTI2_3_IRQHandler /* 05, 21, 0x054, */ + .long EXTI4_15_IRQHandler /* 06, 22, 0x058, */ + .long _RESERVED /* 07, 23, 0x05C, */ + .long ADC_IRQHandler /* 08, 24, 0x060, */ + .long AES_IRQHandler /* 09, 25, 0x064, */ + .long _RESERVED /* 10, 26, 0x068, */ + .long RF_IRQHandler /* 11, 27, 0x06C, */ + .long GPTM0_IRQHandler /* 12, 28, 0x070, */ + .long SCTM0_IRQHandler /* 13, 29, 0x074, */ + .long SCTM1_IRQHandler /* 14, 30, 0x078, */ + .long SCTM2_IRQHandler /* 15, 31, 0x07C, */ + .long SCTM3_IRQHandler /* 16, 32, 0x080, */ + .long BFTM0_IRQHandler /* 17, 33, 0x084, */ + .long BFTM1_IRQHandler /* 18, 34, 0x088, */ + .long I2C0_IRQHandler /* 19, 35, 0x08C, */ + .long I2C1_IRQHandler /* 20, 36, 0x090, */ + .long SPI0_IRQHandler /* 21, 37, 0x094, */ + .long SPI1_IRQHandler /* 22, 38, 0x098, */ + .long _RESERVED /* 23, 39, 0x09C, */ + .long _RESERVED /* 24, 40, 0x0A0, */ + .long UART0_IRQHandler /* 25, 41, 0x0A4, */ + .long UART1_IRQHandler /* 26, 42, 0x0A8, */ + .long _RESERVED /* 27, 43, 0x0AC, */ + .long _RESERVED /* 28, 44, 0x0B0, */ + .long _RESERVED /* 29, 45, 0x0B4, */ + .long PDMA_CH0_1_IRQHandler /* 30, 46, 0x0B8, */ + .long PDMA_CH2_5_IRQHandler /* 31, 47, 0x0BC, */ + + .size __cs3_interrupt_vector_cortex_m, . - __cs3_interrupt_vector_cortex_m + + + .thumb + + +/* Reset Handler */ + + .section .cs3.reset,"x",%progbits + .thumb_func + .globl __cs3_reset_cortex_m + .type __cs3_reset_cortex_m, %function +__cs3_reset_cortex_m: + .fnstart + LDR R0, =SystemInit + BLX R0 + LDR R0, =_start + BX R0 + .pool + .cantunwind + .fnend + .size __cs3_reset_cortex_m,.-__cs3_reset_cortex_m + + .section ".text" + +/* Exception Handlers */ + + .weak NMI_Handler + .type NMI_Handler, %function +NMI_Handler: + B . + .size NMI_Handler, . - NMI_Handler + + .weak HardFault_Handler + .type HardFault_Handler, %function +HardFault_Handler: + B . + .size HardFault_Handler, . - HardFault_Handler + + .weak SVC_Handler + .type SVC_Handler, %function +SVC_Handler: + B . + .size SVC_Handler, . - SVC_Handler + + .weak PendSV_Handler + .type PendSV_Handler, %function +PendSV_Handler: + B . + .size PendSV_Handler, . - PendSV_Handler + + .weak SysTick_Handler + .type SysTick_Handler, %function +SysTick_Handler: + B . + .size SysTick_Handler, . - SysTick_Handler + + +/* IRQ Handlers */ + + .globl Default_Handler + .type Default_Handler, %function +Default_Handler: + B . + .size Default_Handler, . - Default_Handler + + .macro IRQ handler + .weak \handler + .set \handler, Default_Handler + .endm + + IRQ LVD_BOD_IRQHandler + IRQ RTC_IRQHandler + IRQ FLASH_IRQHandler + IRQ EVWUP_IRQHandler + IRQ EXTI0_1_IRQHandler + IRQ EXTI2_3_IRQHandler + IRQ EXTI4_15_IRQHandler + IRQ ADC_IRQHandler + IRQ AES_IRQHandler + IRQ RF_IRQHandler + IRQ GPTM0_IRQHandler + IRQ SCTM0_IRQHandler + IRQ SCTM1_IRQHandler + IRQ SCTM2_IRQHandler + IRQ SCTM3_IRQHandler + IRQ BFTM0_IRQHandler + IRQ BFTM1_IRQHandler + IRQ I2C0_IRQHandler + IRQ I2C1_IRQHandler + IRQ SPI0_IRQHandler + IRQ SPI1_IRQHandler + IRQ UART0_IRQHandler + IRQ UART1_IRQHandler + IRQ PDMA_CH0_1_IRQHandler + IRQ PDMA_CH2_5_IRQHandler + + .end diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/CodeSourcery/startup_ht32f5xxxx_cs3_12.s b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/CodeSourcery/startup_ht32f5xxxx_cs3_12.s new file mode 100644 index 0000000000..0e1001014c --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/CodeSourcery/startup_ht32f5xxxx_cs3_12.s @@ -0,0 +1,278 @@ +/*---------------------------------------------------------------------------------------------------------*/ +/* Holtek Semiconductor Inc. */ +/* */ +/* Copyright (C) Holtek Semiconductor Inc. */ +/* All rights reserved. */ +/* */ +/*----------------------------------------------------------------------------------------------------------- +; File Name : startup_ht32f5xxxx_cs3_12.s +; Version : $Rev:: 6206 $ +; Date : $Date:: 2022-10-05 #$ +; Description : Startup code. +;-----------------------------------------------------------------------------------------------------------*/ + +/* +; Supported Device +; ======================================== +; HT32F61141 +*/ + +;/* <<< Use Configuration Wizard in Context Menu >>> */ +/* +;// HT32 Device +;// <0=> By Project Asm Define +;// <23=> HT32F61141 +*/ + .equ USE_HT32_CHIP_SET, 0 + + .equ _HT32FWID, 0xFFFFFFFF +/* + .equ _HT32FWID, 0x00061141 +*/ + + .equ HT32F61141, 23 + + .if USE_HT32_CHIP_SET == 0 + .else + .equ USE_HT32_CHIP, USE_HT32_CHIP_SET + .endif + +/* +; Amount of memory (in bytes) allocated for Stack and Heap +; Tailor those values to your application needs +;// Stack Size (in Bytes, must 8 byte aligned) <:8> +*/ + .equ Stack_Size, 512 + .section ".stack", "w" + .align 3 + .globl __cs3_stack_mem + .globl __cs3_stack + .globl __cs3_stack_size + .globl __HT_check_sp +__HT_check_sp: +__cs3_stack_mem: + .if Stack_Size + .space Stack_Size + .endif +__cs3_stack: + .size __cs3_stack_mem, . - __cs3_stack_mem + .set __cs3_stack_size, . - __cs3_stack_mem + +/* +;// Heap Size (in Bytes) <:8> +*/ + .equ Heap_Size, 0 + .section ".heap", "w" + .align 3 + .globl __cs3_heap_start + .globl __cs3_heap_end + .globl __HT_check_heap +__HT_check_heap: +__cs3_heap_start: + .if Heap_Size + .space Heap_Size + .endif +__cs3_heap_end: + + .equ _RESERVED, 0xFFFFFFFF +/* +;******************************************************************************* +; Fill-up the Vector Table entries with the exceptions ISR address +;********************************************************************************/ + .section ".cs3.interrupt_vector" + .globl __cs3_interrupt_vector_cortex_m + .type __cs3_interrupt_vector_cortex_m, %object +__cs3_interrupt_vector_cortex_m: + .long __cs3_stack /* ---, 00, 0x000, Top address of Stack */ + .long __cs3_reset /* ---, 01, 0x004, Reset Handler */ + .long NMI_Handler /* -14, 02, 0x008, NMI Handler */ + .long HardFault_Handler /* -13, 03, 0x00C, Hard Fault Handler */ + .long _RESERVED /* ---, 04, 0x010, Reserved */ + .long _RESERVED /* ---, 05, 0x014, Reserved */ + .long _RESERVED /* ---, 06, 0x018, Reserved */ + .long _RESERVED /* ---, 07, 0x01C, Reserved */ + .long _HT32FWID /* ---, 08, 0x020, Reserved */ + .long _RESERVED /* ---, 09, 0x024, Reserved */ + .long _RESERVED /* ---, 10, 0x028, Reserved */ + .long SVC_Handler /* -05, 11, 0x02C, SVC Handler */ + .long _RESERVED /* ---, 12, 0x030, Reserved */ + .long _RESERVED /* ---, 13, 0x034, Reserved */ + .long PendSV_Handler /* -02, 14, 0x038, PendSV Handler */ + .long SysTick_Handler /* -01, 15, 0x03C, SysTick Handler */ + + /* External Interrupt Handler */ + .long LVD_BOD_IRQHandler /* 00, 16, 0x040, */ + .long RTC_IRQHandler /* 01, 17, 0x044, */ + .long FLASH_IRQHandler /* 02, 18, 0x048, */ + .long EVWUP_IRQHandler /* 03, 19, 0x04C, */ + .long EXTI0_1_IRQHandler /* 04, 20, 0x050, */ + .long EXTI2_3_IRQHandler /* 05, 21, 0x054, */ + .long EXTI4_15_IRQHandler /* 06, 22, 0x058, */ + .long _RESERVED /* 07, 23, 0x05C, */ + .long _RESERVED /* 08, 24, 0x060, */ + .long _RESERVED /* 09, 25, 0x064, */ + .long _RESERVED /* 10, 26, 0x068, */ + .long _RESERVED /* 11, 27, 0x06C, */ + .long GPTM0_IRQHandler /* 12, 28, 0x070, */ + .long SCTM0_IRQHandler /* 13, 29, 0x074, */ + .long SCTM1_IRQHandler /* 14, 30, 0x078, */ + .long _RESERVED /* 15, 31, 0x07C, */ + .long _RESERVED /* 16, 32, 0x080, */ + .long BFTM0_IRQHandler /* 17, 33, 0x084, */ + .long BFTM1_IRQHandler /* 18, 34, 0x088, */ + .long I2C0_IRQHandler /* 19, 35, 0x08C, */ + .long _RESERVED /* 20, 36, 0x090, */ + .long SPI0_IRQHandler /* 21, 37, 0x094, */ + .long _RESERVED /* 22, 38, 0x098, */ + .long _RESERVED /* 23, 39, 0x09C, */ + .long _RESERVED /* 24, 40, 0x0A0, */ + .long UART0_IRQHandler /* 25, 41, 0x0A4, */ + .long UART1_IRQHandler /* 26, 42, 0x0A8, */ + .long SCI_IRQHandler /* 27, 43, 0x0AC, */ + .long _RESERVED /* 28, 44, 0x0B0, */ + .long USB_IRQHandler /* 29, 45, 0x0B4, */ + + .size __cs3_interrupt_vector_cortex_m, . - __cs3_interrupt_vector_cortex_m + + + .thumb + + +/* Reset Handler */ + + .section .cs3.reset,"x",%progbits + .thumb_func + .globl __cs3_reset_cortex_m + .type __cs3_reset_cortex_m, %function +__cs3_reset_cortex_m: + .fnstart + LDR R0, =BootProcess + BLX R0 + LDR R0, =SystemInit + BLX R0 + LDR R0, =_start + BX R0 + .thumb_func +BootProcess: + LDR R0, =0x40080300 + LDR R1,[R0, #0x10] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x14] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x18] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x1C] + CMP R1, #0 + BEQ BP2 +BP1: + LDR R0, =0x40080180 + LDR R1,[R0, #0xC] + LSL R1, R1, #4 + LSR R1, R1, #20 + CMP R1, #0 + BEQ BP3 + CMP R1, #5 + BEQ BP3 + CMP R1, #6 + BEQ BP3 +BP2: + DSB + LDR R0, =0x20000000 + LDR R1, =0x05fa0004 + STR R1, [R0] + LDR R1, =0xe000ed00 + LDR R0, =0x05fa0004 + STR R0, [R1, #0xC] + DSB + B . +BP3: + LDR R0, =0x20000000 + LDR R1, [R0] + LDR R0, =0x05fa0004 + CMP R0, R1 + BEQ BP4 + BX LR +BP4: + LDR R0, =0x40088100 + LDR R1, =0x00000001 + STR R1, [R0] + LDR R0, =0x20000000 + LDR R1, =0x0 + STR R1, [R0] + BX LR + .pool + .cantunwind + .fnend + .size __cs3_reset_cortex_m,.-__cs3_reset_cortex_m + + .section ".text" + +/* Exception Handlers */ + + .weak NMI_Handler + .type NMI_Handler, %function +NMI_Handler: + B . + .size NMI_Handler, . - NMI_Handler + + .weak HardFault_Handler + .type HardFault_Handler, %function +HardFault_Handler: + B . + .size HardFault_Handler, . - HardFault_Handler + + .weak SVC_Handler + .type SVC_Handler, %function +SVC_Handler: + B . + .size SVC_Handler, . - SVC_Handler + + .weak PendSV_Handler + .type PendSV_Handler, %function +PendSV_Handler: + B . + .size PendSV_Handler, . - PendSV_Handler + + .weak SysTick_Handler + .type SysTick_Handler, %function +SysTick_Handler: + B . + .size SysTick_Handler, . - SysTick_Handler + + +/* IRQ Handlers */ + + .globl Default_Handler + .type Default_Handler, %function +Default_Handler: + B . + .size Default_Handler, . - Default_Handler + + .macro IRQ handler + .weak \handler + .set \handler, Default_Handler + .endm + + IRQ LVD_BOD_IRQHandler + IRQ RTC_IRQHandler + IRQ FLASH_IRQHandler + IRQ EVWUP_IRQHandler + IRQ EXTI0_1_IRQHandler + IRQ EXTI2_3_IRQHandler + IRQ EXTI4_15_IRQHandler + IRQ GPTM0_IRQHandler + IRQ SCTM0_IRQHandler + IRQ SCTM1_IRQHandler + IRQ BFTM0_IRQHandler + IRQ BFTM1_IRQHandler + IRQ I2C0_IRQHandler + IRQ SPI0_IRQHandler + IRQ UART0_IRQHandler + IRQ UART1_IRQHandler + IRQ SCI_IRQHandler + IRQ USB_IRQHandler + + .end diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/CodeSourcery/startup_ht32f5xxxx_cs3_13.s b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/CodeSourcery/startup_ht32f5xxxx_cs3_13.s new file mode 100644 index 0000000000..649b402684 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/CodeSourcery/startup_ht32f5xxxx_cs3_13.s @@ -0,0 +1,234 @@ +/*---------------------------------------------------------------------------------------------------------*/ +/* Holtek Semiconductor Inc. */ +/* */ +/* Copyright (C) Holtek Semiconductor Inc. */ +/* All rights reserved. */ +/* */ +/*----------------------------------------------------------------------------------------------------------- +; File Name : startup_ht32f5xxxx_cs3_13.s +; Version : $Rev:: 7119 $ +; Date : $Date:: 2023-08-15 #$ +; Description : Startup code. +;-----------------------------------------------------------------------------------------------------------*/ + +/* +; Supported Device +; ======================================== +; HT32F50020, HT32F50030 +; HT32F61630 +; HT32F61030 +*/ + +;/* <<< Use Configuration Wizard in Context Menu >>> */ +/* +;// HT32 Device +;// <0=> By Project Asm Define +;// <25=> HT32F50020/30 +;// <25=> HT32F61630 +;// <25=> HT32F61030 +*/ + .equ USE_HT32_CHIP_SET, 0 + + .equ _HT32FWID, 0xFFFFFFFF +/* + .equ _HT32FWID, 0x00050020 + .equ _HT32FWID, 0x00050030 + .equ _HT32FWID, 0x00061630 + .equ _HT32FWID, 0x00061030 +*/ + + .equ HT32F50020_30, 25 + .equ HT32F61630, 25 + .equ HT32F61030, 25 + + .if USE_HT32_CHIP_SET == 0 + .else + .equ USE_HT32_CHIP, USE_HT32_CHIP_SET + .endif + +/* +; Amount of memory (in bytes) allocated for Stack and Heap +; Tailor those values to your application needs +;// Stack Size (in Bytes, must 8 byte aligned) <:8> +*/ + .equ Stack_Size, 512 + .section ".stack", "w" + .align 3 + .globl __cs3_stack_mem + .globl __cs3_stack + .globl __cs3_stack_size + .globl __HT_check_sp +__HT_check_sp: +__cs3_stack_mem: + .if Stack_Size + .space Stack_Size + .endif +__cs3_stack: + .size __cs3_stack_mem, . - __cs3_stack_mem + .set __cs3_stack_size, . - __cs3_stack_mem + +/* +;// Heap Size (in Bytes) <:8> +*/ + .equ Heap_Size, 0 + .section ".heap", "w" + .align 3 + .globl __cs3_heap_start + .globl __cs3_heap_end + .globl __HT_check_heap +__HT_check_heap: +__cs3_heap_start: + .if Heap_Size + .space Heap_Size + .endif +__cs3_heap_end: + + .equ _RESERVED, 0xFFFFFFFF +/* +;******************************************************************************* +; Fill-up the Vector Table entries with the exceptions ISR address +;********************************************************************************/ + .section ".cs3.interrupt_vector" + .globl __cs3_interrupt_vector_cortex_m + .type __cs3_interrupt_vector_cortex_m, %object +__cs3_interrupt_vector_cortex_m: + .long __cs3_stack /* ---, 00, 0x000, Top address of Stack */ + .long __cs3_reset /* ---, 01, 0x004, Reset Handler */ + .long NMI_Handler /* -14, 02, 0x008, NMI Handler */ + .long HardFault_Handler /* -13, 03, 0x00C, Hard Fault Handler */ + .long _RESERVED /* ---, 04, 0x010, Reserved */ + .long _RESERVED /* ---, 05, 0x014, Reserved */ + .long _RESERVED /* ---, 06, 0x018, Reserved */ + .long _RESERVED /* ---, 07, 0x01C, Reserved */ + .long _HT32FWID /* ---, 08, 0x020, Reserved */ + .long _RESERVED /* ---, 09, 0x024, Reserved */ + .long _RESERVED /* ---, 10, 0x028, Reserved */ + .long SVC_Handler /* -05, 11, 0x02C, SVC Handler */ + .long _RESERVED /* ---, 12, 0x030, Reserved */ + .long _RESERVED /* ---, 13, 0x034, Reserved */ + .long PendSV_Handler /* -02, 14, 0x038, PendSV Handler */ + .long SysTick_Handler /* -01, 15, 0x03C, SysTick Handler */ + + /* External Interrupt Handler */ + .long LVD_BOD_IRQHandler /* 00, 16, 0x040, */ + .long RTC_IRQHandler /* 01, 17, 0x044, */ + .long FLASH_IRQHandler /* 02, 18, 0x048, */ + .long EVWUP_IRQHandler /* 03, 19, 0x04C, */ + .long EXTI0_1_IRQHandler /* 04, 20, 0x050, */ + .long EXTI2_3_IRQHandler /* 05, 21, 0x054, */ + .long EXTI4_7_IRQHandler /* 06, 22, 0x058, */ + .long _RESERVED /* 07, 23, 0x05C, */ + .long ADC_IRQHandler /* 08, 24, 0x060, */ + .long _RESERVED /* 09, 25, 0x064, */ + .long _RESERVED /* 10, 26, 0x068, */ + .long _RESERVED /* 11, 27, 0x06C, */ + .long _RESERVED /* 12, 28, 0x070, */ + .long SCTM0_IRQHandler /* 13, 29, 0x074, */ + .long SCTM1_IRQHandler /* 14, 30, 0x078, */ + .long SCTM2_IRQHandler /* 15, 31, 0x07C, */ + .long _RESERVED /* 16, 32, 0x080, */ + .long BFTM0_IRQHandler /* 17, 33, 0x084, */ + .long _RESERVED /* 18, 34, 0x088, */ + .long I2C0_IRQHandler /* 19, 35, 0x08C, */ + .long _RESERVED /* 20, 36, 0x090, */ + .long SPI0_IRQHandler /* 21, 37, 0x094, */ + .long _RESERVED /* 22, 38, 0x098, */ + .long _RESERVED /* 23, 39, 0x09C, */ + .long _RESERVED /* 24, 40, 0x0A0, */ + .long UART0_IRQHandler /* 25, 41, 0x0A4, */ + .long UART1_IRQHandler /* 26, 42, 0x0A8, */ + .long _RESERVED /* 27, 43, 0x0AC, */ + .long _RESERVED /* 28, 44, 0x0B0, */ + .long LEDC_IRQHandler /* 29, 45, 0x0B4, */ + + .size __cs3_interrupt_vector_cortex_m, . - __cs3_interrupt_vector_cortex_m + + + .thumb + + +/* Reset Handler */ + + .section .cs3.reset,"x",%progbits + .thumb_func + .globl __cs3_reset_cortex_m + .type __cs3_reset_cortex_m, %function +__cs3_reset_cortex_m: + .fnstart + LDR R0, =SystemInit + BLX R0 + LDR R0, =_start + BX R0 + .thumb_func + .pool + .cantunwind + .fnend + .size __cs3_reset_cortex_m,.-__cs3_reset_cortex_m + + .section ".text" + +/* Exception Handlers */ + + .weak NMI_Handler + .type NMI_Handler, %function +NMI_Handler: + B . + .size NMI_Handler, . - NMI_Handler + + .weak HardFault_Handler + .type HardFault_Handler, %function +HardFault_Handler: + B . + .size HardFault_Handler, . - HardFault_Handler + + .weak SVC_Handler + .type SVC_Handler, %function +SVC_Handler: + B . + .size SVC_Handler, . - SVC_Handler + + .weak PendSV_Handler + .type PendSV_Handler, %function +PendSV_Handler: + B . + .size PendSV_Handler, . - PendSV_Handler + + .weak SysTick_Handler + .type SysTick_Handler, %function +SysTick_Handler: + B . + .size SysTick_Handler, . - SysTick_Handler + + +/* IRQ Handlers */ + + .globl Default_Handler + .type Default_Handler, %function +Default_Handler: + B . + .size Default_Handler, . - Default_Handler + + .macro IRQ handler + .weak \handler + .set \handler, Default_Handler + .endm + + IRQ LVD_BOD_IRQHandler + IRQ RTC_IRQHandler + IRQ FLASH_IRQHandler + IRQ EVWUP_IRQHandler + IRQ EXTI0_1_IRQHandler + IRQ EXTI2_3_IRQHandler + IRQ EXTI4_7_IRQHandler + IRQ ADC_IRQHandler + IRQ SCTM0_IRQHandler + IRQ SCTM1_IRQHandler + IRQ SCTM2_IRQHandler + IRQ BFTM0_IRQHandler + IRQ I2C0_IRQHandler + IRQ SPI0_IRQHandler + IRQ UART0_IRQHandler + IRQ UART1_IRQHandler + IRQ LEDC_IRQHandler + + .end diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/CodeSourcery/startup_ht32f5xxxx_cs3_14.s b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/CodeSourcery/startup_ht32f5xxxx_cs3_14.s new file mode 100644 index 0000000000..335d485622 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/CodeSourcery/startup_ht32f5xxxx_cs3_14.s @@ -0,0 +1,254 @@ +/*---------------------------------------------------------------------------------------------------------*/ +/* Holtek Semiconductor Inc. */ +/* */ +/* Copyright (C) Holtek Semiconductor Inc. */ +/* All rights reserved. */ +/* */ +/*----------------------------------------------------------------------------------------------------------- +; File Name : startup_ht32f5xxxx_cs3_14.s +; Version : $Rev:: 6793 $ +; Date : $Date:: 2023-03-14 #$ +; Description : Startup code. +;-----------------------------------------------------------------------------------------------------------*/ + +/* +; Supported Device +; ======================================== +; HT32F50442, HT32F50452 +; HT32F50431, HT32F50441 +*/ + +;/* <<< Use Configuration Wizard in Context Menu >>> */ +/* +;// HT32 Device +;// <0=> By Project Asm Define +;// <26=> HT32F50442/52 +;// <30=> HT32F50431/41 +*/ + .equ USE_HT32_CHIP_SET, 0 + + .equ _HT32FWID, 0xFFFFFFFF +/* + .equ _HT32FWID, 0x00050442 + .equ _HT32FWID, 0x00050452 + .equ _HT32FWID, 0x00050431 + .equ _HT32FWID, 0x00050441 +*/ + + .equ HT32F50442_52, 26 + .equ HT32F50431_41, 30 + + .if USE_HT32_CHIP_SET == 0 + .else + .equ USE_HT32_CHIP, USE_HT32_CHIP_SET + .endif + +/* +; Amount of memory (in bytes) allocated for Stack and Heap +; Tailor those values to your application needs +;// Stack Size (in Bytes, must 8 byte aligned) <:8> +*/ + .equ Stack_Size, 512 + .section ".stack", "w" + .align 3 + .globl __cs3_stack_mem + .globl __cs3_stack + .globl __cs3_stack_size + .globl __HT_check_sp +__HT_check_sp: +__cs3_stack_mem: + .if Stack_Size + .space Stack_Size + .endif +__cs3_stack: + .size __cs3_stack_mem, . - __cs3_stack_mem + .set __cs3_stack_size, . - __cs3_stack_mem + +/* +;// Heap Size (in Bytes) <:8> +*/ + .equ Heap_Size, 0 + .section ".heap", "w" + .align 3 + .globl __cs3_heap_start + .globl __cs3_heap_end + .globl __HT_check_heap +__HT_check_heap: +__cs3_heap_start: + .if Heap_Size + .space Heap_Size + .endif +__cs3_heap_end: + + .equ _RESERVED, 0xFFFFFFFF +/* +;******************************************************************************* +; Fill-up the Vector Table entries with the exceptions ISR address +;********************************************************************************/ + .section ".cs3.interrupt_vector" + .globl __cs3_interrupt_vector_cortex_m + .type __cs3_interrupt_vector_cortex_m, %object +__cs3_interrupt_vector_cortex_m: + .long __cs3_stack /* ---, 00, 0x000, Top address of Stack */ + .long __cs3_reset /* ---, 01, 0x004, Reset Handler */ + .long NMI_Handler /* -14, 02, 0x008, NMI Handler */ + .long HardFault_Handler /* -13, 03, 0x00C, Hard Fault Handler */ + .long _RESERVED /* ---, 04, 0x010, Reserved */ + .long _RESERVED /* ---, 05, 0x014, Reserved */ + .long _RESERVED /* ---, 06, 0x018, Reserved */ + .long _RESERVED /* ---, 07, 0x01C, Reserved */ + .long _HT32FWID /* ---, 08, 0x020, Reserved */ + .long _RESERVED /* ---, 09, 0x024, Reserved */ + .long _RESERVED /* ---, 10, 0x028, Reserved */ + .long SVC_Handler /* -05, 11, 0x02C, SVC Handler */ + .long _RESERVED /* ---, 12, 0x030, Reserved */ + .long _RESERVED /* ---, 13, 0x034, Reserved */ + .long PendSV_Handler /* -02, 14, 0x038, PendSV Handler */ + .long SysTick_Handler /* -01, 15, 0x03C, SysTick Handler */ + + /* External Interrupt Handler */ + .long LVD_BOD_IRQHandler /* 00, 16, 0x040, */ + .long RTC_IRQHandler /* 01, 17, 0x044, */ + .long FLASH_IRQHandler /* 02, 18, 0x048, */ + .long EVWUP_IRQHandler /* 03, 19, 0x04C, */ + .long EXTI0_1_IRQHandler /* 04, 20, 0x050, */ + .long EXTI2_3_IRQHandler /* 05, 21, 0x054, */ + .if (USE_HT32_CHIP==HT32F50442_52) + .long COMP_IRQHandler /* 07, 23, 0x05C, */ + .else + .long _RESERVED /* 07, 23, 0x05C, */ + .endif + .long COMP_IRQHandler /* 07, 23, 0x05C, */ + .long ADC_IRQHandler /* 08, 24, 0x060, */ + .long _RESERVED /* 09, 25, 0x064, */ + .long MCTM0_IRQHandler /* 10, 26, 0x068, */ + .long _RESERVED /* 11, 27, 0x06C, */ + .long GPTM0_IRQHandler /* 12, 28, 0x070, */ + .long _RESERVED /* 13, 29, 0x074, */ + .long _RESERVED /* 14, 30, 0x078, */ + .long PWM0_IRQHandler /* 15, 31, 0x07C, */ + .if (USE_HT32_CHIP==HT32F50442_52) + .long PWM1_IRQHandler /* 16, 32, 0x080, */ + .else + .long _RESERVED /* 16, 32, 0x080, */ + .endif + .long BFTM0_IRQHandler /* 17, 33, 0x084, */ + .long BFTM1_IRQHandler /* 18, 34, 0x088, */ + .long I2C0_IRQHandler /* 19, 35, 0x08C, */ + .long I2C1_IRQHandler /* 20, 36, 0x090, */ + .long SPI0_IRQHandler /* 21, 37, 0x094, */ + .long SPI1_IRQHandler /* 22, 38, 0x098, */ + .long USART0_IRQHandler /* 23, 39, 0x09C, */ + .if (USE_HT32_CHIP==HT32F50442_52) + .long USART1_IRQHandler /* 24, 40, 0x0A0, */ + .else + .long _RESERVED /* 24, 40, 0x0A0, */ + .endif + .long UART0_IRQHandler /* 25, 41, 0x0A4, */ + .long UART1_IRQHandler /* 26, 42, 0x0A8, */ + .long _RESERVED /* 27, 43, 0x0AC, */ + .long _RESERVED /* 28, 44, 0x0B0, */ + .long LEDC_IRQHandler /* 29, 45, 0x0B4, */ + .long PDMA_CH0_1_IRQHandler /* 30, 46, 0x0B8, */ + .long PDMA_CH2_5_IRQHandler /* 31, 47, 0x0BC, */ + + .size __cs3_interrupt_vector_cortex_m, . - __cs3_interrupt_vector_cortex_m + + + .thumb + + +/* Reset Handler */ + + .section .cs3.reset,"x",%progbits + .thumb_func + .globl __cs3_reset_cortex_m + .type __cs3_reset_cortex_m, %function +__cs3_reset_cortex_m: + .fnstart + LDR R0, =SystemInit + BLX R0 + LDR R0, =_start + BX R0 + .thumb_func + .pool + .cantunwind + .fnend + .size __cs3_reset_cortex_m,.-__cs3_reset_cortex_m + + .section ".text" + +/* Exception Handlers */ + + .weak NMI_Handler + .type NMI_Handler, %function +NMI_Handler: + B . + .size NMI_Handler, . - NMI_Handler + + .weak HardFault_Handler + .type HardFault_Handler, %function +HardFault_Handler: + B . + .size HardFault_Handler, . - HardFault_Handler + + .weak SVC_Handler + .type SVC_Handler, %function +SVC_Handler: + B . + .size SVC_Handler, . - SVC_Handler + + .weak PendSV_Handler + .type PendSV_Handler, %function +PendSV_Handler: + B . + .size PendSV_Handler, . - PendSV_Handler + + .weak SysTick_Handler + .type SysTick_Handler, %function +SysTick_Handler: + B . + .size SysTick_Handler, . - SysTick_Handler + + +/* IRQ Handlers */ + + .globl Default_Handler + .type Default_Handler, %function +Default_Handler: + B . + .size Default_Handler, . - Default_Handler + + .macro IRQ handler + .weak \handler + .set \handler, Default_Handler + .endm + + IRQ LVD_BOD_IRQHandler + IRQ RTC_IRQHandler + IRQ FLASH_IRQHandler + IRQ EVWUP_IRQHandler + IRQ EXTI0_1_IRQHandler + IRQ EXTI2_3_IRQHandler + IRQ EXTI4_15_IRQHandler + IRQ COMP_IRQHandler + IRQ ADC_IRQHandler + IRQ MCTM0_IRQHandler + IRQ GPTM0_IRQHandler + IRQ PWM0_IRQHandler + IRQ PWM1_IRQHandler + IRQ BFTM0_IRQHandler + IRQ BFTM1_IRQHandler + IRQ I2C0_IRQHandler + IRQ I2C1_IRQHandler + IRQ SPI0_IRQHandler + IRQ SPI1_IRQHandler + IRQ USART0_IRQHandler + IRQ USART1_IRQHandler + IRQ UART0_IRQHandler + IRQ UART1_IRQHandler + IRQ LEDC_IRQHandler + IRQ PDMA_CH0_1_IRQHandler + IRQ PDMA_CH2_5_IRQHandler + + .end diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/CodeSourcery/startup_ht32f5xxxx_cs3_15.s b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/CodeSourcery/startup_ht32f5xxxx_cs3_15.s new file mode 100644 index 0000000000..304bfbd803 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/CodeSourcery/startup_ht32f5xxxx_cs3_15.s @@ -0,0 +1,255 @@ +/*---------------------------------------------------------------------------------------------------------*/ +/* Holtek Semiconductor Inc. */ +/* */ +/* Copyright (C) Holtek Semiconductor Inc. */ +/* All rights reserved. */ +/* */ +/*----------------------------------------------------------------------------------------------------------- +; File Name : startup_ht32f5xxxx_cs3_15.s +; Version : $Rev:: 6902 $ +; Date : $Date:: 2023-05-08 #$ +; Description : Startup code. +;-----------------------------------------------------------------------------------------------------------*/ + +/* +; Supported Device +; ======================================== +; HT32F53242, HT32F53252 +; HT32F53231, HT32F53241 +*/ + +;/* <<< Use Configuration Wizard in Context Menu >>> */ +/* +;// HT32 Device +;// <0=> By Project Asm Define +;// <28=> HT32F53242/52 +;// <29=> HT32F53231/41 +*/ + .equ USE_HT32_CHIP_SET, 0 + + .equ _HT32FWID, 0xFFFFFFFF +/* + .equ _HT32FWID, 0x00053242 + .equ _HT32FWID, 0x00053252 + .equ _HT32FWID, 0x00053231 + .equ _HT32FWID, 0x00053241 +*/ + + .equ HT32F53242_52, 28 + .equ HT32F53231_41, 29 + + .if USE_HT32_CHIP_SET == 0 + .else + .equ USE_HT32_CHIP, USE_HT32_CHIP_SET + .endif + +/* +; Amount of memory (in bytes) allocated for Stack and Heap +; Tailor those values to your application needs +;// Stack Size (in Bytes, must 8 byte aligned) <:8> +*/ + .equ Stack_Size, 512 + .section ".stack", "w" + .align 3 + .globl __cs3_stack_mem + .globl __cs3_stack + .globl __cs3_stack_size + .globl __HT_check_sp +__HT_check_sp: +__cs3_stack_mem: + .if Stack_Size + .space Stack_Size + .endif +__cs3_stack: + .size __cs3_stack_mem, . - __cs3_stack_mem + .set __cs3_stack_size, . - __cs3_stack_mem + +/* +;// Heap Size (in Bytes) <:8> +*/ + .equ Heap_Size, 0 + .section ".heap", "w" + .align 3 + .globl __cs3_heap_start + .globl __cs3_heap_end + .globl __HT_check_heap +__HT_check_heap: +__cs3_heap_start: + .if Heap_Size + .space Heap_Size + .endif +__cs3_heap_end: + + .equ _RESERVED, 0xFFFFFFFF +/* +;******************************************************************************* +; Fill-up the Vector Table entries with the exceptions ISR address +;********************************************************************************/ + .section ".cs3.interrupt_vector" + .globl __cs3_interrupt_vector_cortex_m + .type __cs3_interrupt_vector_cortex_m, %object +__cs3_interrupt_vector_cortex_m: + .long __cs3_stack /* ---, 00, 0x000, Top address of Stack */ + .long __cs3_reset /* ---, 01, 0x004, Reset Handler */ + .long NMI_Handler /* -14, 02, 0x008, NMI Handler */ + .long HardFault_Handler /* -13, 03, 0x00C, Hard Fault Handler */ + .long _RESERVED /* ---, 04, 0x010, Reserved */ + .long _RESERVED /* ---, 05, 0x014, Reserved */ + .long _RESERVED /* ---, 06, 0x018, Reserved */ + .long _RESERVED /* ---, 07, 0x01C, Reserved */ + .long _HT32FWID /* ---, 08, 0x020, Reserved */ + .long _RESERVED /* ---, 09, 0x024, Reserved */ + .long _RESERVED /* ---, 10, 0x028, Reserved */ + .long SVC_Handler /* -05, 11, 0x02C, SVC Handler */ + .long _RESERVED /* ---, 12, 0x030, Reserved */ + .long _RESERVED /* ---, 13, 0x034, Reserved */ + .long PendSV_Handler /* -02, 14, 0x038, PendSV Handler */ + .long SysTick_Handler /* -01, 15, 0x03C, SysTick Handler */ + + /* External Interrupt Handler */ + .long LVD_BOD_IRQHandler /* 00, 16, 0x040, */ + .long RTC_IRQHandler /* 01, 17, 0x044, */ + .long FLASH_IRQHandler /* 02, 18, 0x048, */ + .long EVWUP_IRQHandler /* 03, 19, 0x04C, */ + .long EXTI0_1_IRQHandler /* 04, 20, 0x050, */ + .long EXTI2_3_IRQHandler /* 05, 21, 0x054, */ + .long EXTI4_15_IRQHandler /* 06, 22, 0x058, */ + .if (USE_HT32_CHIP==HT32F53242_52) + .long COMP_IRQHandler /* 07, 23, 0x05C, */ + .else + .long _RESERVED /* 07, 23, 0x05C, */ + .endif + .long ADC_IRQHandler /* 08, 24, 0x060, */ + .long _RESERVED /* 09, 25, 0x064, */ + .long MCTM0_IRQHandler /* 10, 26, 0x068, */ + .long _RESERVED /* 11, 27, 0x06C, */ + .long GPTM0_IRQHandler /* 12, 28, 0x070, */ + .long _RESERVED /* 13, 29, 0x074, */ + .long _RESERVED /* 14, 30, 0x078, */ + .long PWM0_IRQHandler /* 15, 31, 0x07C, */ + .if (USE_HT32_CHIP==HT32F53242_52) + .long PWM1_IRQHandler /* 16, 32, 0x080, */ + .else + .long _RESERVED /* 16, 32, 0x080, */ + .endif + .long BFTM0_IRQHandler /* 17, 33, 0x084, */ + .long BFTM1_IRQHandler /* 18, 34, 0x088, */ + .long I2C0_IRQHandler /* 19, 35, 0x08C, */ + .long I2C1_IRQHandler /* 20, 36, 0x090, */ + .long SPI0_IRQHandler /* 21, 37, 0x094, */ + .long SPI1_IRQHandler /* 22, 38, 0x098, */ + .long USART0_IRQHandler /* 23, 39, 0x09C, */ + .if (USE_HT32_CHIP==HT32F53242_52) + .long USART1_IRQHandler /* 24, 40, 0x0A0, */ + .else + .long _RESERVED /* 24, 40, 0x0A0, */ + .endif + .long UART0_IRQHandler /* 25, 41, 0x0A4, */ + .long UART1_IRQHandler /* 26, 42, 0x0A8, */ + .long CAN0_IRQHandler /* 27, 43, 0x0AC, */ + .long _RESERVED /* 28, 44, 0x0B0, */ + .long LEDC_IRQHandler /* 29, 45, 0x0B4, */ + .long PDMA_CH0_1_IRQHandler /* 30, 46, 0x0B8, */ + .long PDMA_CH2_5_IRQHandler /* 31, 47, 0x0BC, */ + + .size __cs3_interrupt_vector_cortex_m, . - __cs3_interrupt_vector_cortex_m + + + .thumb + + +/* Reset Handler */ + + .section .cs3.reset,"x",%progbits + .thumb_func + .globl __cs3_reset_cortex_m + .type __cs3_reset_cortex_m, %function +__cs3_reset_cortex_m: + .fnstart + LDR R0, =SystemInit + BLX R0 + LDR R0, =_start + BX R0 + .thumb_func + .pool + .cantunwind + .fnend + .size __cs3_reset_cortex_m,.-__cs3_reset_cortex_m + + .section ".text" + +/* Exception Handlers */ + + .weak NMI_Handler + .type NMI_Handler, %function +NMI_Handler: + B . + .size NMI_Handler, . - NMI_Handler + + .weak HardFault_Handler + .type HardFault_Handler, %function +HardFault_Handler: + B . + .size HardFault_Handler, . - HardFault_Handler + + .weak SVC_Handler + .type SVC_Handler, %function +SVC_Handler: + B . + .size SVC_Handler, . - SVC_Handler + + .weak PendSV_Handler + .type PendSV_Handler, %function +PendSV_Handler: + B . + .size PendSV_Handler, . - PendSV_Handler + + .weak SysTick_Handler + .type SysTick_Handler, %function +SysTick_Handler: + B . + .size SysTick_Handler, . - SysTick_Handler + + +/* IRQ Handlers */ + + .globl Default_Handler + .type Default_Handler, %function +Default_Handler: + B . + .size Default_Handler, . - Default_Handler + + .macro IRQ handler + .weak \handler + .set \handler, Default_Handler + .endm + + IRQ LVD_BOD_IRQHandler + IRQ RTC_IRQHandler + IRQ FLASH_IRQHandler + IRQ EVWUP_IRQHandler + IRQ EXTI0_1_IRQHandler + IRQ EXTI2_3_IRQHandler + IRQ EXTI4_15_IRQHandler + IRQ COMP_IRQHandler + IRQ ADC_IRQHandler + IRQ MCTM0_IRQHandler + IRQ GPTM0_IRQHandler + IRQ PWM0_IRQHandler + IRQ PWM1_IRQHandler + IRQ BFTM0_IRQHandler + IRQ BFTM1_IRQHandler + IRQ I2C0_IRQHandler + IRQ I2C1_IRQHandler + IRQ SPI0_IRQHandler + IRQ SPI1_IRQHandler + IRQ USART0_IRQHandler + IRQ USART1_IRQHandler + IRQ UART0_IRQHandler + IRQ UART1_IRQHandler + IRQ CAN0_IRQHandler + IRQ LEDC_IRQHandler + IRQ PDMA_CH0_1_IRQHandler + IRQ PDMA_CH2_5_IRQHandler + + .end diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/CodeSourcery/startup_ht32f5xxxx_cs3_16.s b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/CodeSourcery/startup_ht32f5xxxx_cs3_16.s new file mode 100644 index 0000000000..01f644a0a3 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/CodeSourcery/startup_ht32f5xxxx_cs3_16.s @@ -0,0 +1,259 @@ +/*---------------------------------------------------------------------------------------------------------*/ +/* Holtek Semiconductor Inc. */ +/* */ +/* Copyright (C) Holtek Semiconductor Inc. */ +/* All rights reserved. */ +/* */ +/*----------------------------------------------------------------------------------------------------------- +; File Name : startup_ht32f5xxxx_cs3_16.s +; Version : $Rev:: 7094 $ +; Date : $Date:: 2023-08-02 #$ +; Description : Startup code. +;-----------------------------------------------------------------------------------------------------------*/ + +/* +; Supported Device +; ======================================== +; HT32F66242 +; HT32F66246 +*/ + +;/* <<< Use Configuration Wizard in Context Menu >>> */ +/* + + + + +*/ + .equ USE_HT32_CHIP_SET, 0 + +/* + .equ _HT32FWID, 0xFFFFFFFF + .equ _HT32FWID, 0x00066246 +*/ + + .equ HT32F66246, 31 + .equ HT32F66242, 33 + + .if USE_HT32_CHIP_SET == 0 + .else + .equ USE_HT32_CHIP, USE_HT32_CHIP_SET + .endif + + .if USE_HT32_CHIP == 0 + .equ _HT32FWID, 0x00066246 + .endif + .if USE_HT32_CHIP == HT32F66246 + .equ _HT32FWID, 0x00066246 + .endif + .if USE_HT32_CHIP == HT32F66242 + .equ _HT32FWID, 0x00066242 + .endif + +/* +; Amount of memory (in bytes) allocated for Stack and Heap +; Tailor those values to your application needs +;// Stack Size (in Bytes, must 8 byte aligned) <:8> +*/ + .equ Stack_Size, 512 + .section ".stack", "w" + .align 3 + .globl __cs3_stack_mem + .globl __cs3_stack + .globl __cs3_stack_size + .globl __HT_check_sp +__HT_check_sp: +__cs3_stack_mem: + .if Stack_Size + .space Stack_Size + .endif +__cs3_stack: + .size __cs3_stack_mem, . - __cs3_stack_mem + .set __cs3_stack_size, . - __cs3_stack_mem + +/* +;// Heap Size (in Bytes) <:8> +*/ + .equ Heap_Size, 0 + .section ".heap", "w" + .align 3 + .globl __cs3_heap_start + .globl __cs3_heap_end + .globl __HT_check_heap +__HT_check_heap: +__cs3_heap_start: + .if Heap_Size + .space Heap_Size + .endif +__cs3_heap_end: + + .equ _RESERVED, 0xFFFFFFFF +/* +;******************************************************************************* +; Fill-up the Vector Table entries with the exceptions ISR address +;********************************************************************************/ + .section ".cs3.interrupt_vector" + .globl __cs3_interrupt_vector_cortex_m + .type __cs3_interrupt_vector_cortex_m, %object +__cs3_interrupt_vector_cortex_m: + .long __cs3_stack /* ---, 00, 0x000, Top address of Stack */ + .long __cs3_reset /* ---, 01, 0x004, Reset Handler */ + .long NMI_Handler /* -14, 02, 0x008, NMI Handler */ + .long HardFault_Handler /* -13, 03, 0x00C, Hard Fault Handler */ + .long _RESERVED /* ---, 04, 0x010, Reserved */ + .long _RESERVED /* ---, 05, 0x014, Reserved */ + .long _RESERVED /* ---, 06, 0x018, Reserved */ + .long _RESERVED /* ---, 07, 0x01C, Reserved */ + .long _HT32FWID /* ---, 08, 0x020, Reserved */ + .long _RESERVED /* ---, 09, 0x024, Reserved */ + .long _RESERVED /* ---, 10, 0x028, Reserved */ + .long SVC_Handler /* -05, 11, 0x02C, SVC Handler */ + .long _RESERVED /* ---, 12, 0x030, Reserved */ + .long _RESERVED /* ---, 13, 0x034, Reserved */ + .long PendSV_Handler /* -02, 14, 0x038, PendSV Handler */ + .long SysTick_Handler /* -01, 15, 0x03C, SysTick Handler */ + + /* External Interrupt Handler */ + .long LVD_BOD_IRQHandler /* 00, 16, 0x040, */ + .long RTC_IRQHandler /* 01, 17, 0x044, */ + .long FLASH_IRQHandler /* 02, 18, 0x048, */ + .long EVWUP_IRQHandler /* 03, 19, 0x04C, */ + .long EXTI0_1_IRQHandler /* 04, 20, 0x050, */ + .long EXTI2_3_IRQHandler /* 05, 21, 0x054, */ + .long EXTI4_15_IRQHandler /* 06, 22, 0x058, */ + .if (USE_HT32_CHIP==HT32F66246) + .long CAN0_IRQHandler /* 07, 23, 0x05C, */ + .else + .long _RESERVED /* 07, 23, 0x05C, */ + .endif + .long ADC_IRQHandler /* 08, 24, 0x060, */ + .long CORDIC_IRQHandler /* 09, 25, 0x064, */ + .long MCTM0_BRK_IRQHandler /* 10, 26, 0x068, */ + .long MCTM0_UP_IRQHandler /* 11, 27, 0x06C, */ + .long MCTM0_TR_UP2_IRQHandler /* 12, 28, 0x070, */ + .long MCTM0_CC_IRQHandler /* 13, 29, 0x074, */ + .long GPTM0_G_IRQHandler /* 14, 30, 0x078, */ + .long GPTM0_VCLK_IRQHandler /* 15, 31, 0x07C, */ + .long BFTM0_IRQHandler /* 16, 32, 0x080, */ + .long BFTM1_IRQHandler /* 17, 33, 0x084, */ + .long CMP0_IRQHandler /* 18, 34, 0x088, */ + .long CMP1_IRQHandler /* 19, 35, 0x08C, */ + .long PID_IRQHandler /* 20, 36, 0x090, */ + .long I2C0_IRQHandler /* 21, 37, 0x094, */ + .long SPI0_IRQHandler /* 22, 38, 0x098, */ + .long USART0_IRQHandler /* 23, 39, 0x09C, */ + .long UART0_IRQHandler /* 24, 40, 0x0A0, */ + .long PDMA_CH0_1_IRQHandler /* 25, 41, 0x0A4, */ + .long PDMA_CH2_3_IRQHandler /* 26, 42, 0x0A8, */ + .long PDMA_CH4_5_IRQHandler /* 27, 43, 0x0AC, */ + .long SCTM0_IRQHandler /* 28, 44, 0x0B0, */ + .long SCTM1_IRQHandler /* 29, 45, 0x0B4, */ + .long SCTM2_IRQHandler /* 30, 46, 0x0B8, */ + .long SCTM3_IRQHandler /* 31, 47, 0x0BC, */ + + .size __cs3_interrupt_vector_cortex_m, . - __cs3_interrupt_vector_cortex_m + + + .thumb + + +/* Reset Handler */ + + .section .cs3.reset,"x",%progbits + .thumb_func + .globl __cs3_reset_cortex_m + .type __cs3_reset_cortex_m, %function +__cs3_reset_cortex_m: + .fnstart + LDR R0, =SystemInit + BLX R0 + LDR R0, =_start + BX R0 + .thumb_func + .pool + .cantunwind + .fnend + .size __cs3_reset_cortex_m,.-__cs3_reset_cortex_m + + .section ".text" + +/* Exception Handlers */ + + .weak NMI_Handler + .type NMI_Handler, %function +NMI_Handler: + B . + .size NMI_Handler, . - NMI_Handler + + .weak HardFault_Handler + .type HardFault_Handler, %function +HardFault_Handler: + B . + .size HardFault_Handler, . - HardFault_Handler + + .weak SVC_Handler + .type SVC_Handler, %function +SVC_Handler: + B . + .size SVC_Handler, . - SVC_Handler + + .weak PendSV_Handler + .type PendSV_Handler, %function +PendSV_Handler: + B . + .size PendSV_Handler, . - PendSV_Handler + + .weak SysTick_Handler + .type SysTick_Handler, %function +SysTick_Handler: + B . + .size SysTick_Handler, . - SysTick_Handler + + +/* IRQ Handlers */ + + .globl Default_Handler + .type Default_Handler, %function +Default_Handler: + B . + .size Default_Handler, . - Default_Handler + + .macro IRQ handler + .weak \handler + .set \handler, Default_Handler + .endm + + IRQ LVD_BOD_IRQHandler + IRQ RTC_IRQHandler + IRQ FLASH_IRQHandler + IRQ EVWUP_IRQHandler + IRQ EXTI0_1_IRQHandler + IRQ EXTI2_3_IRQHandler + IRQ EXTI4_15_IRQHandler + IRQ CAN0_IRQHandler + IRQ ADC_IRQHandler + IRQ CORDIC_IRQHandler + IRQ MCTM0_BRK_IRQHandler + IRQ MCTM0_UP_IRQHandler + IRQ MCTM0_TR_UP2_IRQHandler + IRQ MCTM0_CC_IRQHandler + IRQ GPTM0_G_IRQHandler + IRQ GPTM0_VCLK_IRQHandler + IRQ BFTM0_IRQHandler + IRQ BFTM1_IRQHandler + IRQ CMP0_IRQHandler + IRQ CMP1_IRQHandler + IRQ PID_IRQHandler + IRQ I2C0_IRQHandler + IRQ SPI0_IRQHandler + IRQ USART0_IRQHandler + IRQ UART0_IRQHandler + IRQ PDMA_CH0_1_IRQHandler + IRQ PDMA_CH2_3_IRQHandler + IRQ PDMA_CH4_5_IRQHandler + IRQ SCTM0_IRQHandler + IRQ SCTM1_IRQHandler + IRQ SCTM2_IRQHandler + IRQ SCTM3_IRQHandler + + .end diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/CodeSourcery/startup_ht32f5xxxx_cs3_17.s b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/CodeSourcery/startup_ht32f5xxxx_cs3_17.s new file mode 100644 index 0000000000..47dac68db7 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/CodeSourcery/startup_ht32f5xxxx_cs3_17.s @@ -0,0 +1,233 @@ +/*---------------------------------------------------------------------------------------------------------*/ +/* Holtek Semiconductor Inc. */ +/* */ +/* Copyright (C) Holtek Semiconductor Inc. */ +/* All rights reserved. */ +/* */ +/*----------------------------------------------------------------------------------------------------------- +; File Name : startup_ht32f5xxxx_cs3_17.s +; Version : $Rev:: 7030 $ +; Date : $Date:: 2023-07-18 #$ +; Description : Startup code. +;-----------------------------------------------------------------------------------------------------------*/ + +/* +; Supported Device +; ======================================== +; HT32F52234, HT32F52244 +*/ + +;/* <<< Use Configuration Wizard in Context Menu >>> */ +/* +;// HT32 Device +;// <0=> By Project Asm Define +;// <33=> HT32F52234/44 +*/ + .equ USE_HT32_CHIP_SET, 0 + + .equ _HT32FWID, 0xFFFFFFFF +/* + .equ _HT32FWID, 0x00052234 + .equ _HT32FWID, 0x00052244 +*/ + + .equ HT32F52234_44, 33 + + .if USE_HT32_CHIP_SET == 0 + .else + .equ USE_HT32_CHIP, USE_HT32_CHIP_SET + .endif + +/* +; Amount of memory (in bytes) allocated for Stack and Heap +; Tailor those values to your application needs +;// Stack Size (in Bytes, must 8 byte aligned) <:8> +*/ + .equ Stack_Size, 512 + .section ".stack", "w" + .align 3 + .globl __cs3_stack_mem + .globl __cs3_stack + .globl __cs3_stack_size + .globl __HT_check_sp +__HT_check_sp: +__cs3_stack_mem: + .if Stack_Size + .space Stack_Size + .endif +__cs3_stack: + .size __cs3_stack_mem, . - __cs3_stack_mem + .set __cs3_stack_size, . - __cs3_stack_mem + +/* +;// Heap Size (in Bytes) <:8> +*/ + .equ Heap_Size, 0 + .section ".heap", "w" + .align 3 + .globl __cs3_heap_start + .globl __cs3_heap_end + .globl __HT_check_heap +__HT_check_heap: +__cs3_heap_start: + .if Heap_Size + .space Heap_Size + .endif +__cs3_heap_end: + + .equ _RESERVED, 0xFFFFFFFF +/* +;******************************************************************************* +; Fill-up the Vector Table entries with the exceptions ISR address +;********************************************************************************/ + .section ".cs3.interrupt_vector" + .globl __cs3_interrupt_vector_cortex_m + .type __cs3_interrupt_vector_cortex_m, %object +__cs3_interrupt_vector_cortex_m: + .long __cs3_stack /* ---, 00, 0x000, Top address of Stack */ + .long __cs3_reset /* ---, 01, 0x004, Reset Handler */ + .long NMI_Handler /* -14, 02, 0x008, NMI Handler */ + .long HardFault_Handler /* -13, 03, 0x00C, Hard Fault Handler */ + .long _RESERVED /* ---, 04, 0x010, Reserved */ + .long _RESERVED /* ---, 05, 0x014, Reserved */ + .long _RESERVED /* ---, 06, 0x018, Reserved */ + .long _RESERVED /* ---, 07, 0x01C, Reserved */ + .long _HT32FWID /* ---, 08, 0x020, Reserved */ + .long _RESERVED /* ---, 09, 0x024, Reserved */ + .long _RESERVED /* ---, 10, 0x028, Reserved */ + .long SVC_Handler /* -05, 11, 0x02C, SVC Handler */ + .long _RESERVED /* ---, 12, 0x030, Reserved */ + .long _RESERVED /* ---, 13, 0x034, Reserved */ + .long PendSV_Handler /* -02, 14, 0x038, PendSV Handler */ + .long SysTick_Handler /* -01, 15, 0x03C, SysTick Handler */ + + /* External Interrupt Handler */ + .long LVD_BOD_IRQHandler /* 00, 16, 0x040, */ + .long RTC_IRQHandler /* 01, 17, 0x044, */ + .long FLASH_IRQHandler /* 02, 18, 0x048, */ + .long EVWUP_IRQHandler /* 03, 19, 0x04C, */ + .long EXTI0_1_IRQHandler /* 04, 20, 0x050, */ + .long EXTI2_3_IRQHandler /* 05, 21, 0x054, */ + .long EXTI4_15_IRQHandler /* 06, 22, 0x058, */ + .long DAC0_1_IRQHandler /* 07, 23, 0x05C, */ + .long ADC_IRQHandler /* 08, 24, 0x060, */ + .long I2C2_IRQHandler /* 09, 25, 0x064, */ + .long _RESERVED /* 10, 26, 0x068, */ + .long _RESERVED /* 11, 27, 0x06C, */ + .long _RESERVED /* 12, 28, 0x070, */ + .long SCTM0_IRQHandler /* 13, 29, 0x074, */ + .long SCTM1_IRQHandler /* 14, 30, 0x078, */ + .long PWM0_IRQHandler /* 15, 31, 0x07C, */ + .long _RESERVED /* 16, 32, 0x080, */ + .long BFTM0_IRQHandler /* 17, 33, 0x084, */ + .long BFTM1_IRQHandler /* 18, 34, 0x088, */ + .long I2C0_IRQHandler /* 19, 35, 0x08C, */ + .long I2C1_IRQHandler /* 20, 36, 0x090, */ + .long SPI0_IRQHandler /* 21, 37, 0x094, */ + .long _RESERVED /* 22, 38, 0x098, */ + .long USART0_IRQHandler /* 23, 39, 0x09C, */ + .long _RESERVED /* 24, 40, 0x0A0, */ + .long UART0_IRQHandler /* 25, 41, 0x0A4, */ + .long _RESERVED /* 26, 42, 0x0A8, */ + .long _RESERVED /* 27, 43, 0x0AC, */ + .long _RESERVED /* 28, 44, 0x0B0, */ + .long _RESERVED /* 29, 45, 0x0B4, */ + .long PDMA_CH0_1_IRQHandler /* 30, 46, 0x0B8, */ + .long PDMA_CH2_5_IRQHandler /* 31, 47, 0x0BC, */ + + .size __cs3_interrupt_vector_cortex_m, . - __cs3_interrupt_vector_cortex_m + + + .thumb + + +/* Reset Handler */ + + .section .cs3.reset,"x",%progbits + .thumb_func + .globl __cs3_reset_cortex_m + .type __cs3_reset_cortex_m, %function +__cs3_reset_cortex_m: + .fnstart + LDR R0, =SystemInit + BLX R0 + LDR R0, =_start + BX R0 + .thumb_func + .pool + .cantunwind + .fnend + .size __cs3_reset_cortex_m,.-__cs3_reset_cortex_m + + .section ".text" + +/* Exception Handlers */ + + .weak NMI_Handler + .type NMI_Handler, %function +NMI_Handler: + B . + .size NMI_Handler, . - NMI_Handler + + .weak HardFault_Handler + .type HardFault_Handler, %function +HardFault_Handler: + B . + .size HardFault_Handler, . - HardFault_Handler + + .weak SVC_Handler + .type SVC_Handler, %function +SVC_Handler: + B . + .size SVC_Handler, . - SVC_Handler + + .weak PendSV_Handler + .type PendSV_Handler, %function +PendSV_Handler: + B . + .size PendSV_Handler, . - PendSV_Handler + + .weak SysTick_Handler + .type SysTick_Handler, %function +SysTick_Handler: + B . + .size SysTick_Handler, . - SysTick_Handler + + +/* IRQ Handlers */ + + .globl Default_Handler + .type Default_Handler, %function +Default_Handler: + B . + .size Default_Handler, . - Default_Handler + + .macro IRQ handler + .weak \handler + .set \handler, Default_Handler + .endm + + IRQ LVD_BOD_IRQHandler + IRQ RTC_IRQHandler + IRQ FLASH_IRQHandler + IRQ EVWUP_IRQHandler + IRQ EXTI0_1_IRQHandler + IRQ EXTI2_3_IRQHandler + IRQ EXTI4_15_IRQHandler + IRQ DAC0_1_IRQHandler + IRQ ADC_IRQHandler + IRQ I2C2_IRQHandler + IRQ SCTM0_IRQHandler + IRQ SCTM1_IRQHandler + IRQ PWM0_IRQHandler + IRQ BFTM0_IRQHandler + IRQ BFTM1_IRQHandler + IRQ I2C0_IRQHandler + IRQ I2C1_IRQHandler + IRQ SPI0_IRQHandler + IRQ USART0_IRQHandler + IRQ UART0_IRQHandler + IRQ PDMA_CH0_1_IRQHandler + IRQ PDMA_CH2_5_IRQHandler + + .end diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/GCC/startup_ht32f5xxxx_gcc_01.s b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/GCC/startup_ht32f5xxxx_gcc_01.s new file mode 100644 index 0000000000..6ef935fb93 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/GCC/startup_ht32f5xxxx_gcc_01.s @@ -0,0 +1,519 @@ +/*---------------------------------------------------------------------------------------------------------*/ +/* Holtek Semiconductor Inc. */ +/* */ +/* Copyright (C) Holtek Semiconductor Inc. */ +/* All rights reserved. */ +/* */ +/*----------------------------------------------------------------------------------------------------------- +; File Name : startup_ht32f5xxxx_gcc_01.s +; Version : $Rev:: 6953 $ +; Date : $Date:: 2023-05-30 #$ +; Description : Startup code. +;-----------------------------------------------------------------------------------------------------------*/ + +/* +; Supported Device +; ======================================== +; HT32F52220, HT32F52230 +; HT32F52231, HT32F52241 +; HT32F52331, HT32F52341 +; HT32F52342, HT32F52352 +; HT32F52243, HT32F52253 +; HT32F0008 +; HT32F52344, HT32F52354 +; HT32F0006 +; HT32F61352 +; HT50F32003 +; HT32F62030, HT32F62040, HT32F62050 +; HT32F67741 +; HT32F67232 +; HT32F67233 +*/ + +;/* <<< Use Configuration Wizard in Context Menu >>> */ +/* +;// HT32 Device +;// <0=> By Project Asm Define +;// <1=> HT32F52220/30 +;// <2=> HT32F52231/41 +;// <3=> HT32F52331/41 +;// <4=> HT32F52342/52 +;// <5=> HT32F52243/53 +;// <6=> HT32F0008 +;// <9=> HT32F52344/54 +;// <10=> HT32F0006 +;// <10=> HT32F61352 +;// <4=> HT50F32003 +;// <2=> HT32F67741 +;// <1=> HT32F67232 +;// <1=> HT32F67233 +;// <1=> HT32F62030 +;// <2=> HT32F62040 +;// <5=> HT32F62050 +*/ + .equ USE_HT32_CHIP_SET, 0 + + .equ _HT32FWID, 0xFFFFFFFF +/* + .equ _HT32FWID, 0x00052220 + .equ _HT32FWID, 0x00052230 + .equ _HT32FWID, 0x00052231 + .equ _HT32FWID, 0x00052241 + .equ _HT32FWID, 0x00052331 + .equ _HT32FWID, 0x00052341 + .equ _HT32FWID, 0x00052342 + .equ _HT32FWID, 0x00052352 + .equ _HT32FWID, 0x00052243 + .equ _HT32FWID, 0x00052253 + .equ _HT32FWID, 0x00000008 + .equ _HT32FWID, 0x00052344 + .equ _HT32FWID, 0x00052354 + .equ _HT32FWID, 0x00000006 + .equ _HT32FWID, 0x00061352 + .equ _HT32FWID, 0x00032003 + .equ _HT32FWID, 0x00062030 + .equ _HT32FWID, 0x00062040 + .equ _HT32FWID, 0x00062050 + .equ _HT32FWID, 0x00067741 + .equ _HT32FWID, 0x00067232 + .equ _HT32FWID, 0x00067233 +*/ + + .equ HT32F52220_30, 1 + .equ HT32F52231_41, 2 + .equ HT32F52331_41, 3 + .equ HT32F52342_52, 4 + .equ HT32F52243_53, 5 + .equ HT32F0008, 6 + .equ HT32F52344_54, 9 + .equ HT32F0006, 10 + .equ HT32F61352, 10 + .equ HT50F32003, 4 + .equ HT32F62030, 1 + .equ HT32F62040, 2 + .equ HT32F62050, 5 + .equ HT32F67741, 2 + .equ HT32F67232, 1 + .equ HT32F67233, 1 + + .if USE_HT32_CHIP_SET == 0 + .else + .equ USE_HT32_CHIP, USE_HT32_CHIP_SET + .endif + + .syntax unified + .cpu cortex-m0plus + .fpu softvfp + .thumb + +/* start address for the initialization values of the .data section. defined in linker script */ +.word _sidata + +/* start address for the .data section. defined in linker script */ +.word _sdata + +/* end address for the .data section. defined in linker script */ +.word _edata + +/* start address for the .bss section. defined in linker script */ +.word _sbss + +/* end address for the .bss section. defined in linker script */ +.word _ebss + + +/* +; Amount of memory (in bytes) allocated for Stack and Heap +; Tailor those values to your application needs +;// Stack Size (in Bytes, must 8 byte aligned) <:8> +*/ + .equ Stack_Size, 512 + .section ".stack", "w" + .align 3 + .globl __StackTop + .globl __StackLimit + .globl __HT_check_sp +__HT_check_sp: +__StackLimit: + .if Stack_Size + .space Stack_Size + .endif + .size __StackLimit, . - __StackLimit +__StackTop: + .size __StackTop, . - __StackTop + +/* +;// Heap Size (in Bytes) <:8> +*/ + .equ Heap_Size, 0 + .section ".heap", "w" + .align 3 + .globl __HeapBase + .globl _end + .globl __HeapLimit + .globl __HT_check_heap +__HT_check_heap: +__HeapBase: +_end: + .if Heap_Size + .space Heap_Size + .endif + .size __HeapBase, . - __HeapBase +__HeapLimit: + .size __HeapLimit, . - __HeapLimit + + .equ _RESERVED, 0xFFFFFFFF +/* +;******************************************************************************* +; Fill-up the Vector Table entries with the exceptions ISR address +;********************************************************************************/ + .section .isr_vector,"a",%progbits + .global __interrupt_vector_cortex_m + .type __interrupt_vector_cortex_m, %object +__interrupt_vector_cortex_m: + .long __StackTop /* ---, 00, 0x000, Top address of Stack */ + .long Reset_Handler /* ---, 01, 0x004, Reset Handler */ + .long NMI_Handler /* -14, 02, 0x008, NMI Handler */ + .long HardFault_Handler /* -13, 03, 0x00C, Hard Fault Handler */ + .long _RESERVED /* ---, 04, 0x010, Reserved */ + .long _RESERVED /* ---, 05, 0x014, Reserved */ + .long _RESERVED /* ---, 06, 0x018, Reserved */ + .long _RESERVED /* ---, 07, 0x01C, Reserved */ + .long _HT32FWID /* ---, 08, 0x020, Reserved */ + .long _RESERVED /* ---, 09, 0x024, Reserved */ + .long _RESERVED /* ---, 10, 0x028, Reserved */ + .long SVC_Handler /* -05, 11, 0x02C, SVC Handler */ + .long _RESERVED /* ---, 12, 0x030, Reserved */ + .long _RESERVED /* ---, 13, 0x034, Reserved */ + .long PendSV_Handler /* -02, 14, 0x038, PendSV Handler */ + .long SysTick_Handler /* -01, 15, 0x03C, SysTick Handler */ + + /* External Interrupt Handler */ + .long LVD_BOD_IRQHandler /* 00, 16, 0x040, */ + .if (USE_HT32_CHIP==HT32F52220_30) + .long _RESERVED /* 01, 17, 0x044, */ + .else + .long RTC_IRQHandler /* 01, 17, 0x044, */ + .endif + .long FLASH_IRQHandler /* 02, 18, 0x048, */ + .long EVWUP_IRQHandler /* 03, 19, 0x04C, */ + .long EXTI0_1_IRQHandler /* 04, 20, 0x050, */ + .long EXTI2_3_IRQHandler /* 05, 21, 0x054, */ + .long EXTI4_15_IRQHandler /* 06, 22, 0x058, */ + .if (USE_HT32_CHIP==HT32F52342_52) || (USE_HT32_CHIP==HT32F52344_54) + .long COMP_IRQHandler /* 07, 23, 0x05C, */ + .else + .long _RESERVED /* 07, 23, 0x05C, */ + .endif + .if (USE_HT32_CHIP==HT32F0008) + .long _RESERVED /* 08, 24, 0x060, */ + .else + .long ADC_IRQHandler /* 08, 24, 0x060, */ + .endif + .if (USE_HT32_CHIP==HT32F52243_53) + .long I2C2_IRQHandler /* 09, 25, 0x064, */ + .else + .long _RESERVED /* 09, 25, 0x064, */ + .endif + .if (USE_HT32_CHIP==HT32F52220_30) || (USE_HT32_CHIP==HT32F0008) || (USE_HT32_CHIP==HT32F0006) + .long _RESERVED /* 10, 26, 0x068, */ + .else + .long MCTM0_IRQHandler /* 10, 26, 0x068, */ + .endif + .if (USE_HT32_CHIP==HT32F52342_52) + .long GPTM1_IRQHandler /* 11, 27, 0x06C, */ + .else + .long _RESERVED /* 11, 27, 0x06C, */ + .endif + .long GPTM0_IRQHandler /* 12, 28, 0x070, */ + .if (USE_HT32_CHIP==HT32F0008) + .long _RESERVED /* 13, 29, 0x074, */ + .long _RESERVED /* 14, 30, 0x078, */ + .else + .long SCTM0_IRQHandler /* 13, 29, 0x074, */ + .long SCTM1_IRQHandler /* 14, 30, 0x078, */ + .endif + .if (USE_HT32_CHIP==HT32F52231_41) || (USE_HT32_CHIP==HT32F52331_41) || (USE_HT32_CHIP==HT32F52243_53) || (USE_HT32_CHIP==HT32F0006) + .long SCTM2_IRQHandler /* 15, 31, 0x07C, */ + .long SCTM3_IRQHandler /* 16, 32, 0x080, */ + .endif + .if (USE_HT32_CHIP==HT32F0008) + .long PWM0_IRQHandler /* 15, 31, 0x07C, */ + .long PWM1_IRQHandler /* 16, 32, 0x080, */ + .endif + .if (USE_HT32_CHIP==HT32F52220_30) || (USE_HT32_CHIP==HT32F52342_52) || (USE_HT32_CHIP==HT32F52344_54) + .long _RESERVED /* 15, 31, 0x07C, */ + .long _RESERVED /* 16, 32, 0x080, */ + .endif + .long BFTM0_IRQHandler /* 17, 33, 0x084, */ + .if (USE_HT32_CHIP==HT32F52220_30) + .long _RESERVED /* 18, 34, 0x088, */ + .else + .long BFTM1_IRQHandler /* 18, 34, 0x088, */ + .endif + .long I2C0_IRQHandler /* 19, 35, 0x08C, */ + .if (USE_HT32_CHIP==HT32F52220_30) || (USE_HT32_CHIP==HT32F0008) || (USE_HT32_CHIP==HT32F52344_54) || (USE_HT32_CHIP==HT32F0006) + .long _RESERVED /* 20, 36, 0x090, */ + .else + .long I2C1_IRQHandler /* 20, 36, 0x090, */ + .endif + .long SPI0_IRQHandler /* 21, 37, 0x094, */ + .if (USE_HT32_CHIP==HT32F52220_30) || (USE_HT32_CHIP==HT32F0008) + .long _RESERVED /* 22, 38, 0x098, */ + .else + .if (USE_HT32_CHIP==HT32F0006) + .long QSPI_IRQHandler /* 22, 38, 0x098, */ + .else + .long SPI1_IRQHandler /* 22, 38, 0x098, */ + .endif + .endif + .if (USE_HT32_CHIP==HT32F52344_54) + .long _RESERVED /* 23, 39, 0x09C, */ + .else + .long USART0_IRQHandler /* 23, 39, 0x09C, */ + .endif + .if (USE_HT32_CHIP==HT32F52342_52) || (USE_HT32_CHIP==HT32F52243_53) + .long USART1_IRQHandler /* 24, 40, 0x0A0, */ + .else + .long _RESERVED /* 24, 40, 0x0A0, */ + .endif + .long UART0_IRQHandler /* 25, 41, 0x0A4, */ + .if (USE_HT32_CHIP==HT32F52220_30) || (USE_HT32_CHIP==HT32F0008) || (USE_HT32_CHIP==HT32F0006) + .long _RESERVED /* 26, 42, 0x0A8, */ + .else + .long UART1_IRQHandler /* 26, 42, 0x0A8, */ + .endif + .if (USE_HT32_CHIP==HT32F52331_41) || (USE_HT32_CHIP==HT32F52342_52) + .long SCI_IRQHandler /* 27, 43, 0x0AC, */ + .endif + .if (USE_HT32_CHIP==HT32F52243_53) + .long UART2_IRQHandler /* 27, 43, 0x0AC, */ + .endif + .if (USE_HT32_CHIP==HT32F0006) + .long MIDI_IRQHandler /* 27, 43, 0x0AC, */ + .endif + .if (USE_HT32_CHIP==HT32F0008) || (USE_HT32_CHIP==HT32F52344_54) + .long _RESERVED /* 27, 43, 0xAC, */ + .endif + .if (USE_HT32_CHIP==HT32F52342_52) || (USE_HT32_CHIP==HT32F0006) + .long I2S_IRQHandler /* 28, 44, 0x0B0, */ + .endif + .if (USE_HT32_CHIP==HT32F52331_41) || (USE_HT32_CHIP==HT32F52344_54) + .long _RESERVED /* 28, 44, 0x0B0, */ + .endif + .if (USE_HT32_CHIP==HT32F52243_53) + .long UART3_IRQHandler /* 28, 44, 0x0B0, */ + .endif + .if (USE_HT32_CHIP==HT32F0008) + .long AES_IRQHandler /* 28, 44, 0x0B0, */ + .endif + .if (USE_HT32_CHIP==HT32F52331_41) || (USE_HT32_CHIP==HT32F52342_52) || (USE_HT32_CHIP==HT32F0008) || (USE_HT32_CHIP==HT32F52344_54) || (USE_HT32_CHIP==HT32F0006) + .long USB_IRQHandler /* 29, 45, 0x0B4, */ + .endif + .if (USE_HT32_CHIP==HT32F52243_53) + .long _RESERVED /* 29, 45, 0x0B4, */ + .endif + .if (USE_HT32_CHIP==HT32F52342_52) || (USE_HT32_CHIP==HT32F52243_53) || (USE_HT32_CHIP==HT32F0008) || (USE_HT32_CHIP==HT32F52344_54) || (USE_HT32_CHIP==HT32F0006) + .long PDMA_CH0_1_IRQHandler /* 30, 46, 0x0B8, */ + .long PDMA_CH2_5_IRQHandler /* 31, 47, 0x0BC, */ + .endif + + .size __interrupt_vector_cortex_m, . - __interrupt_vector_cortex_m + + + .thumb + + +/* Reset Handler */ + + .section .text.Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + LDR R0, =__StackTop /* set stack pointer */ + MOV SP, R0 + LDR R0, =BootProcess + BLX R0 + LDR R0, =SystemInit + BLX R0 + + /* Copy the data segment initializers from flash to SRAM */ + MOVS R1, #0 + B LoopCopyDataInit + +CopyDataInit: + LDR R3, =_sidata + LDR R3, [R3, R1] + STR R3, [R0, R1] + ADDS R1, R1, #4 + +LoopCopyDataInit: + LDR R0, =_sdata + LDR R3, =_edata + ADDS R2, R0, R1 + CMP R2, R3 + BCC CopyDataInit + LDR R2, =_sbss + B LoopFillZerobss + +/* Zero fill the bss segment. */ +FillZerobss: + MOVS R3, #0 + STR R3, [R2] + ADDS R2, R2, #4 + +LoopFillZerobss: + LDR R3, =_ebss + CMP R2, R3 + BCC FillZerobss + + /* Call static constructors */ + BL __libc_init_array + + /* Call the application's entry point.*/ + BL main + +LoopForever: + B LoopForever + + .thumb_func +BootProcess: + LDR R0, =0x40080300 + LDR R1,[R0, #0x10] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x14] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x18] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x1C] + CMP R1, #0 + BEQ BP2 +BP1: + LDR R0, =0x40080180 + LDR R1,[R0, #0xC] + LSLS R1, R1, #4 + LSRS R1, R1, #20 + CMP R1, #0 + BEQ BP3 + CMP R1, #5 + BEQ BP3 + CMP R1, #6 + BEQ BP3 +BP2: + DSB + LDR R0, =0x20000000 + LDR R1, =0x05fa0004 + STR R1, [R0] + LDR R1, =0xe000ed00 + LDR R0, =0x05fa0004 + STR R0, [R1, #0xC] + DSB + B . +BP3: + LDR R0, =0x20000000 + LDR R1, [R0] + LDR R0, =0x05fa0004 + CMP R0, R1 + BEQ BP4 + BX LR +BP4: + LDR R0, =0x40088100 + LDR R1, =0x00000001 + STR R1, [R0] + LDR R0, =0x20000000 + LDR R1, =0x0 + STR R1, [R0] + BX LR + + .size Reset_Handler, .-Reset_Handler + +/* Exception Handlers */ + + .weak NMI_Handler + .type NMI_Handler, %function +NMI_Handler: + B . + .size NMI_Handler, . - NMI_Handler + + .weak HardFault_Handler + .type HardFault_Handler, %function +HardFault_Handler: + B . + .size HardFault_Handler, . - HardFault_Handler + + .weak SVC_Handler + .type SVC_Handler, %function +SVC_Handler: + B . + .size SVC_Handler, . - SVC_Handler + + .weak PendSV_Handler + .type PendSV_Handler, %function +PendSV_Handler: + B . + .size PendSV_Handler, . - PendSV_Handler + + .weak SysTick_Handler + .type SysTick_Handler, %function +SysTick_Handler: + B . + .size SysTick_Handler, . - SysTick_Handler + + +/* IRQ Handlers */ + + .globl Default_Handler + .type Default_Handler, %function +Default_Handler: + B . + .size Default_Handler, . - Default_Handler + + .macro IRQ handler + .weak \handler + .set \handler, Default_Handler + .endm + + IRQ LVD_BOD_IRQHandler + IRQ RTC_IRQHandler + IRQ FLASH_IRQHandler + IRQ EVWUP_IRQHandler + IRQ EXTI0_1_IRQHandler + IRQ EXTI2_3_IRQHandler + IRQ EXTI4_15_IRQHandler + IRQ COMP_IRQHandler + IRQ ADC_IRQHandler + IRQ MCTM0_IRQHandler + IRQ GPTM1_IRQHandler + IRQ GPTM0_IRQHandler + IRQ SCTM0_IRQHandler + IRQ SCTM1_IRQHandler + IRQ SCTM2_IRQHandler + IRQ SCTM3_IRQHandler + IRQ PWM0_IRQHandler + IRQ PWM1_IRQHandler + IRQ BFTM0_IRQHandler + IRQ BFTM1_IRQHandler + IRQ I2C0_IRQHandler + IRQ I2C1_IRQHandler + IRQ I2C2_IRQHandler + IRQ SPI0_IRQHandler + IRQ SPI1_IRQHandler + IRQ QSPI_IRQHandler + IRQ USART0_IRQHandler + IRQ USART1_IRQHandler + IRQ UART0_IRQHandler + IRQ UART1_IRQHandler + IRQ UART2_IRQHandler + IRQ UART3_IRQHandler + IRQ SCI_IRQHandler + IRQ MIDI_IRQHandler + IRQ I2S_IRQHandler + IRQ AES_IRQHandler + IRQ USB_IRQHandler + IRQ PDMA_CH0_1_IRQHandler + IRQ PDMA_CH2_5_IRQHandler + + .end diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/GCC/startup_ht32f5xxxx_gcc_02.s b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/GCC/startup_ht32f5xxxx_gcc_02.s new file mode 100644 index 0000000000..784c9cef99 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/GCC/startup_ht32f5xxxx_gcc_02.s @@ -0,0 +1,382 @@ +/*---------------------------------------------------------------------------------------------------------*/ +/* Holtek Semiconductor Inc. */ +/* */ +/* Copyright (C) Holtek Semiconductor Inc. */ +/* All rights reserved. */ +/* */ +/*----------------------------------------------------------------------------------------------------------- +; File Name : startup_ht32f5xxxx_gcc_02.s +; Version : $Rev:: 7119 $ +; Date : $Date:: 2023-08-15 #$ +; Description : Startup code. +;-----------------------------------------------------------------------------------------------------------*/ + +/* +; Supported Device +; ======================================== +; HT32F50220, HT32F50230 +; HT32F50231, HT32F50241 +; HT50F32002 +; HT32F59041 +; HF5032 +; HT32F61641 +; HT32F59046 +; HT32F61041 +*/ + +;/* <<< Use Configuration Wizard in Context Menu >>> */ +/* +;// HT32 Device +;// <0=> By Project Asm Define +;// <7=> HT32F50220/30 +;// <8=> HT32F50231/41 +;// <7=> HT50F32002 +;// <8=> HT32F59041 +;// <7=> HF5032 +;// <8=> HT32F61641 +;// <8=> HT32F59046 +;// <8=> HT32F61041 +*/ + .equ USE_HT32_CHIP_SET, 0 + + .equ _HT32FWID, 0xFFFFFFFF +/* + .equ _HT32FWID, 0x00050220 + .equ _HT32FWID, 0x00050230 + .equ _HT32FWID, 0x00050231 + .equ _HT32FWID, 0x00050241 + .equ _HT32FWID, 0x00032002 + .equ _HT32FWID, 0x00059041 + .equ _HT32FWID, 0x000F5032 + .equ _HT32FWID, 0x00061641 + .equ _HT32FWID, 0x00059046 + .equ _HT32FWID, 0x00061041 +*/ + + .equ HT32F50220_30, 7 + .equ HT32F50231_41, 8 + .equ HT50F32002, 7 + .equ HT32F59041, 8 + .equ HF5032, 7 + .equ HT32F61641, 8 + .equ HT32F59046, 8 + .equ HT32F61041, 8 + + .if USE_HT32_CHIP_SET == 0 + .else + .equ USE_HT32_CHIP, USE_HT32_CHIP_SET + .endif + + .syntax unified + .cpu cortex-m0plus + .fpu softvfp + .thumb + +/* start address for the initialization values of the .data section. defined in linker script */ +.word _sidata + +/* start address for the .data section. defined in linker script */ +.word _sdata + +/* end address for the .data section. defined in linker script */ +.word _edata + +/* start address for the .bss section. defined in linker script */ +.word _sbss + +/* end address for the .bss section. defined in linker script */ +.word _ebss + + +/* +; Amount of memory (in bytes) allocated for Stack and Heap +; Tailor those values to your application needs +;// Stack Size (in Bytes, must 8 byte aligned) <:8> +*/ + .equ Stack_Size, 512 + .section ".stack", "w" + .align 3 + .globl __StackTop + .globl __StackLimit + .globl __HT_check_sp +__HT_check_sp: +__StackLimit: + .if Stack_Size + .space Stack_Size + .endif + .size __StackLimit, . - __StackLimit +__StackTop: + .size __StackTop, . - __StackTop + +/* +;// Heap Size (in Bytes) <:8> +*/ + .equ Heap_Size, 0 + .section ".heap", "w" + .align 3 + .globl __HeapBase + .globl _end + .globl __HeapLimit + .globl __HT_check_heap +__HT_check_heap: +__HeapBase: +_end: + .if Heap_Size + .space Heap_Size + .endif + .size __HeapBase, . - __HeapBase +__HeapLimit: + .size __HeapLimit, . - __HeapLimit + + .equ _RESERVED, 0xFFFFFFFF +/* +;******************************************************************************* +; Fill-up the Vector Table entries with the exceptions ISR address +;********************************************************************************/ + .section .isr_vector,"a",%progbits + .global __interrupt_vector_cortex_m + .type __interrupt_vector_cortex_m, %object +__interrupt_vector_cortex_m: + .long __StackTop /* ---, 00, 0x000, Top address of Stack */ + .long Reset_Handler /* ---, 01, 0x004, Reset Handler */ + .long NMI_Handler /* -14, 02, 0x008, NMI Handler */ + .long HardFault_Handler /* -13, 03, 0x00C, Hard Fault Handler */ + .long _RESERVED /* ---, 04, 0x010, Reserved */ + .long _RESERVED /* ---, 05, 0x014, Reserved */ + .long _RESERVED /* ---, 06, 0x018, Reserved */ + .long _RESERVED /* ---, 07, 0x01C, Reserved */ + .long _HT32FWID /* ---, 08, 0x020, Reserved */ + .long _RESERVED /* ---, 09, 0x024, Reserved */ + .long _RESERVED /* ---, 10, 0x028, Reserved */ + .long SVC_Handler /* -05, 11, 0x02C, SVC Handler */ + .long _RESERVED /* ---, 12, 0x030, Reserved */ + .long _RESERVED /* ---, 13, 0x034, Reserved */ + .long PendSV_Handler /* -02, 14, 0x038, PendSV Handler */ + .long SysTick_Handler /* -01, 15, 0x03C, SysTick Handler */ + + /* External Interrupt Handler */ + .long LVD_BOD_IRQHandler /* 00, 16, 0x040, */ + .long RTC_IRQHandler /* 01, 17, 0x044, */ + .long FLASH_IRQHandler /* 02, 18, 0x048, */ + .long EVWUP_IRQHandler /* 03, 19, 0x04C, */ + .long EXTI0_1_IRQHandler /* 04, 20, 0x050, */ + .long EXTI2_3_IRQHandler /* 05, 21, 0x054, */ + .long EXTI4_15_IRQHandler /* 06, 22, 0x058, */ + .long _RESERVED /* 07, 23, 0x05C, */ + .long ADC_IRQHandler /* 08, 24, 0x060, */ + .long _RESERVED /* 09, 25, 0x064, */ + .if (USE_HT32_CHIP==HT32F50220_30) + .long _RESERVED /* 10, 26, 0x068, */ + .else + .long MCTM0_IRQHandler /* 10, 26, 0x068, */ + .endif + .long _RESERVED /* 11, 27, 0x06C, */ + .long GPTM0_IRQHandler /* 12, 28, 0x070, */ + .long _RESERVED /* 13, 29, 0x074, */ + .long _RESERVED /* 14, 30, 0x078, */ + .long PWM0_IRQHandler /* 15, 31, 0x07C, */ + .long PWM1_IRQHandler /* 16, 32, 0x080, */ + .long BFTM0_IRQHandler /* 17, 33, 0x084, */ + .if (USE_HT32_CHIP==HT32F50220_30) + .long _RESERVED /* 18, 34, 0x088, */ + .else + .long BFTM1_IRQHandler /* 18, 34, 0x088, */ + .endif + .long I2C0_IRQHandler /* 19, 35, 0x08C, */ + .if (USE_HT32_CHIP==HT32F50220_30) + .long _RESERVED /* 20, 36, 0x090, */ + .else + .long I2C1_IRQHandler /* 20, 36, 0x090, */ + .endif + .long SPI0_IRQHandler /* 21, 37, 0x094, */ + .long SPI1_IRQHandler /* 22, 38, 0x098, */ + .if (USE_HT32_CHIP==HT32F50220_30) + .long _RESERVED /* 23, 39, 0x09C, */ + .else + .long USART0_IRQHandler /* 23, 39, 0x09C, */ + .endif + .long _RESERVED /* 24, 40, 0x0A0, */ + .long UART0_IRQHandler /* 25, 41, 0x0A4, */ + .long UART1_IRQHandler /* 26, 42, 0x0A8, */ + + .size __interrupt_vector_cortex_m, . - __interrupt_vector_cortex_m + + + .thumb + + +/* Reset Handler */ + + .section .text.Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + LDR R0, =__StackTop /* set stack pointer */ + MOV SP, R0 + LDR R0, =BootProcess + BLX R0 + LDR R0, =SystemInit + BLX R0 + + /* Copy the data segment initializers from flash to SRAM */ + MOVS R1, #0 + B LoopCopyDataInit + +CopyDataInit: + LDR R3, =_sidata + LDR R3, [R3, R1] + STR R3, [R0, R1] + ADDS R1, R1, #4 + +LoopCopyDataInit: + LDR R0, =_sdata + LDR R3, =_edata + ADDS R2, R0, R1 + CMP R2, R3 + BCC CopyDataInit + LDR R2, =_sbss + B LoopFillZerobss + +/* Zero fill the bss segment. */ +FillZerobss: + MOVS R3, #0 + STR R3, [R2] + ADDS R2, R2, #4 + +LoopFillZerobss: + LDR R3, =_ebss + CMP R2, R3 + BCC FillZerobss + + /* Call static constructors */ + BL __libc_init_array + + /* Call the application's entry point.*/ + BL main + +LoopForever: + B LoopForever + + .thumb_func +BootProcess: + LDR R0, =0x40080300 + LDR R1,[R0, #0x10] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x14] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x18] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x1C] + CMP R1, #0 + BEQ BP2 +BP1: + LDR R0, =0x40080180 + LDR R1,[R0, #0xC] + LSLS R1, R1, #4 + LSRS R1, R1, #20 + CMP R1, #0 + BEQ BP3 + CMP R1, #5 + BEQ BP3 + CMP R1, #6 + BEQ BP3 +BP2: + DSB + LDR R0, =0x20000000 + LDR R1, =0x05fa0004 + STR R1, [R0] + LDR R1, =0xe000ed00 + LDR R0, =0x05fa0004 + STR R0, [R1, #0xC] + DSB + B . +BP3: + LDR R0, =0x20000000 + LDR R1, [R0] + LDR R0, =0x05fa0004 + CMP R0, R1 + BEQ BP4 + BX LR +BP4: + LDR R0, =0x40088100 + LDR R1, =0x00000001 + STR R1, [R0] + LDR R0, =0x20000000 + LDR R1, =0x0 + STR R1, [R0] + BX LR + + .size Reset_Handler, .-Reset_Handler + +/* Exception Handlers */ + + .weak NMI_Handler + .type NMI_Handler, %function +NMI_Handler: + B . + .size NMI_Handler, . - NMI_Handler + + .weak HardFault_Handler + .type HardFault_Handler, %function +HardFault_Handler: + B . + .size HardFault_Handler, . - HardFault_Handler + + .weak SVC_Handler + .type SVC_Handler, %function +SVC_Handler: + B . + .size SVC_Handler, . - SVC_Handler + + .weak PendSV_Handler + .type PendSV_Handler, %function +PendSV_Handler: + B . + .size PendSV_Handler, . - PendSV_Handler + + .weak SysTick_Handler + .type SysTick_Handler, %function +SysTick_Handler: + B . + .size SysTick_Handler, . - SysTick_Handler + + +/* IRQ Handlers */ + + .globl Default_Handler + .type Default_Handler, %function +Default_Handler: + B . + .size Default_Handler, . - Default_Handler + + .macro IRQ handler + .weak \handler + .set \handler, Default_Handler + .endm + + IRQ LVD_BOD_IRQHandler + IRQ RTC_IRQHandler + IRQ FLASH_IRQHandler + IRQ EVWUP_IRQHandler + IRQ EXTI0_1_IRQHandler + IRQ EXTI2_3_IRQHandler + IRQ EXTI4_15_IRQHandler + IRQ ADC_IRQHandler + IRQ MCTM0_IRQHandler + IRQ GPTM0_IRQHandler + IRQ PWM0_IRQHandler + IRQ PWM1_IRQHandler + IRQ BFTM0_IRQHandler + IRQ BFTM1_IRQHandler + IRQ I2C0_IRQHandler + IRQ I2C1_IRQHandler + IRQ SPI0_IRQHandler + IRQ SPI1_IRQHandler + IRQ USART0_IRQHandler + IRQ UART0_IRQHandler + IRQ UART1_IRQHandler + + .end diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/GCC/startup_ht32f5xxxx_gcc_03.s b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/GCC/startup_ht32f5xxxx_gcc_03.s new file mode 100644 index 0000000000..e00f3d2618 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/GCC/startup_ht32f5xxxx_gcc_03.s @@ -0,0 +1,444 @@ +/*---------------------------------------------------------------------------------------------------------*/ +/* Holtek Semiconductor Inc. */ +/* */ +/* Copyright (C) Holtek Semiconductor Inc. */ +/* All rights reserved. */ +/* */ +/*----------------------------------------------------------------------------------------------------------- +; File Name : startup_ht32f5xxxx_gcc_03.s +; Version : $Rev:: 6887 $ +; Date : $Date:: 2023-05-05 #$ +; Description : Startup code. +;-----------------------------------------------------------------------------------------------------------*/ + +/* +; Supported Device +; ======================================== +; HT32F0008 +; HT32F52142 +; HT32F52344, HT32F52354 +; HT32F52357, HT32F52367 +; HT50F3200T +*/ + +;/* <<< Use Configuration Wizard in Context Menu >>> */ +/* +;// HT32 Device +;// <0=> By Project Asm Define +;// <6=> HT32F0008 +;// <6=> HT32F52142 +;// <9=> HT32F52344/54 +;// <11=> HT32F52357/67 +;// <11=> HT50F3200T +*/ + .equ USE_HT32_CHIP_SET, 0 + + .equ _HT32FWID, 0xFFFFFFFF +/* + .equ _HT32FWID, 0x00000008 + .equ _HT32FWID, 0x00052142 + .equ _HT32FWID, 0x00052344 + .equ _HT32FWID, 0x00052354 + .equ _HT32FWID, 0x00052357 + .equ _HT32FWID, 0x00052367 + .equ _HT32FWID, 0x0003200F +*/ + + .equ HT32F0008, 6 + .equ HT32F52142, 6 + .equ HT32F52344_54, 9 + .equ HT32F52357_67, 11 + .equ HT50F3200T, 11 + + .if USE_HT32_CHIP_SET == 0 + .else + .equ USE_HT32_CHIP, USE_HT32_CHIP_SET + .endif + + .syntax unified + .cpu cortex-m0plus + .fpu softvfp + .thumb + +/* start address for the initialization values of the .data section. defined in linker script */ +.word _sidata + +/* start address for the .data section. defined in linker script */ +.word _sdata + +/* end address for the .data section. defined in linker script */ +.word _edata + +/* start address for the .bss section. defined in linker script */ +.word _sbss + +/* end address for the .bss section. defined in linker script */ +.word _ebss + + +/* +; Amount of memory (in bytes) allocated for Stack and Heap +; Tailor those values to your application needs +;// Stack Size (in Bytes, must 8 byte aligned) <:8> +*/ + .equ Stack_Size, 512 + .section ".stack", "w" + .align 3 + .globl __StackTop + .globl __StackLimit + .globl __HT_check_sp +__HT_check_sp: +__StackLimit: + .if Stack_Size + .space Stack_Size + .endif + .size __StackLimit, . - __StackLimit +__StackTop: + .size __StackTop, . - __StackTop + +/* +;// Heap Size (in Bytes) <:8> +*/ + .equ Heap_Size, 0 + .section ".heap", "w" + .align 3 + .globl __HeapBase + .globl _end + .globl __HeapLimit + .globl __HT_check_heap +__HT_check_heap: +__HeapBase: +_end: + .if Heap_Size + .space Heap_Size + .endif + .size __HeapBase, . - __HeapBase +__HeapLimit: + .size __HeapLimit, . - __HeapLimit + + .equ _RESERVED, 0xFFFFFFFF +/* +;******************************************************************************* +; Fill-up the Vector Table entries with the exceptions ISR address +;********************************************************************************/ + .section .isr_vector,"a",%progbits + .global __interrupt_vector_cortex_m + .type __interrupt_vector_cortex_m, %object +__interrupt_vector_cortex_m: + .long __StackTop /* ---, 00, 0x000, Top address of Stack */ + .long Reset_Handler /* ---, 01, 0x004, Reset Handler */ + .long NMI_Handler /* -14, 02, 0x008, NMI Handler */ + .long HardFault_Handler /* -13, 03, 0x00C, Hard Fault Handler */ + .long _RESERVED /* ---, 04, 0x010, Reserved */ + .long _RESERVED /* ---, 05, 0x014, Reserved */ + .long _RESERVED /* ---, 06, 0x018, Reserved */ + .long _RESERVED /* ---, 07, 0x01C, Reserved */ + .long _HT32FWID /* ---, 08, 0x020, Reserved */ + .long _RESERVED /* ---, 09, 0x024, Reserved */ + .long _RESERVED /* ---, 10, 0x028, Reserved */ + .long SVC_Handler /* -05, 11, 0x02C, SVC Handler */ + .long _RESERVED /* ---, 12, 0x030, Reserved */ + .long _RESERVED /* ---, 13, 0x034, Reserved */ + .long PendSV_Handler /* -02, 14, 0x038, PendSV Handler */ + .long SysTick_Handler /* -01, 15, 0x03C, SysTick Handler */ + + /* External Interrupt Handler */ + .long LVD_BOD_IRQHandler /* 00, 16, 0x040, */ + .long RTC_IRQHandler /* 01, 17, 0x044, */ + .long FLASH_IRQHandler /* 02, 18, 0x048, */ + .long EVWUP_IRQHandler /* 03, 19, 0x04C, */ + .long EXTI0_1_IRQHandler /* 04, 20, 0x050, */ + .long EXTI2_3_IRQHandler /* 05, 21, 0x054, */ + .long EXTI4_15_IRQHandler /* 06, 22, 0x058, */ + .if (USE_HT32_CHIP==HT32F0008) + .long _RESERVED /* 07, 23, 0x05C, */ + .endif + .if (USE_HT32_CHIP==HT32F52344_54) + .long COMP_IRQHandler /* 07, 23, 0x05C, */ + .endif + .if (USE_HT32_CHIP==HT32F52357_67) + .long COMP_DAC_IRQHandler /* 07, 23, 0x05C, */ + .endif + .if (USE_HT32_CHIP==HT32F0008) + .long _RESERVED /* 08, 24, 0x060, */ + .else + .long ADC_IRQHandler /* 08, 24, 0x060, */ + .endif + .if (USE_HT32_CHIP==HT32F52357_67) + .long AES_IRQHandler /* 09, 25, 0x064, */ + .else + .long _RESERVED /* 09, 25, 0x064, */ + .endif + .if (USE_HT32_CHIP==HT32F0008) + .long _RESERVED /* 10, 26, 0x068, */ + .else + .long MCTM0_IRQHandler /* 10, 26, 0x068, */ + .endif + .if (USE_HT32_CHIP==HT32F52357_67) + .long QSPI_IRQHandler /* 11, 27, 0x06C, */ + .else + .long _RESERVED /* 11, 27, 0x06C, */ + .endif + .long GPTM0_IRQHandler /* 12, 28, 0x070, */ + .if (USE_HT32_CHIP==HT32F0008) + .long _RESERVED /* 13, 29, 0x074, */ + .long _RESERVED /* 14, 30, 0x078, */ + .else + .long SCTM0_IRQHandler /* 13, 29, 0x074, */ + .long SCTM1_IRQHandler /* 14, 30, 0x078, */ + .endif + .if (USE_HT32_CHIP==HT32F0008) || (USE_HT32_CHIP==HT32F52357_67) + .long PWM0_IRQHandler /* 15, 31, 0x07C, */ + .long PWM1_IRQHandler /* 16, 32, 0x080, */ + .endif + .if (USE_HT32_CHIP==HT32F52344_54) + .long _RESERVED /* 15, 31, 0x07C, */ + .long _RESERVED /* 16, 32, 0x080, */ + .endif + .long BFTM0_IRQHandler /* 17, 33, 0x084, */ + .long BFTM1_IRQHandler /* 18, 34, 0x088, */ + .long I2C0_IRQHandler /* 19, 35, 0x08C, */ + .if (USE_HT32_CHIP==HT32F0008) || (USE_HT32_CHIP==HT32F52344_54) + .long _RESERVED /* 20, 36, 0x090, */ + .else + .long I2C1_IRQHandler /* 20, 36, 0x090, */ + .endif + .long SPI0_IRQHandler /* 21, 37, 0x094, */ + .if (USE_HT32_CHIP==HT32F0008) + .long _RESERVED /* 22, 38, 0x098, */ + .else + .long SPI1_IRQHandler /* 22, 38, 0x098, */ + .endif + .if (USE_HT32_CHIP==HT32F52344_54) + .long _RESERVED /* 23, 39, 0x09C, */ + .else + .long USART0_IRQHandler /* 23, 39, 0x09C, */ + .endif + .if (USE_HT32_CHIP==HT32F0008) + .long _RESERVED /* 24, 40, 0x0A0, */ + .long UART0_IRQHandler /* 25, 41, 0x0A4, */ + .long _RESERVED /* 26, 42, 0x0A8, */ + .endif + .if (USE_HT32_CHIP==HT32F52344_54) + .long _RESERVED /* 24, 40, 0x0A0, */ + .long UART0_IRQHandler /* 25, 41, 0x0A4, */ + .long UART1_IRQHandler /* 26, 42, 0x0A8, */ + .endif + .if (USE_HT32_CHIP==HT32F52357_67) + .long USART1_IRQHandler /* 24, 40, 0x0A0, */ + .long UART0_UART2_IRQHandler /* 25, 41, 0x0A4, */ + .long UART1_UART3_IRQHandler /* 26, 42, 0x0A8, */ + .endif + .if (USE_HT32_CHIP==HT32F52357_67) + .long SCI_IRQHandler /* 27, 43, 0x0AC, */ + .else + .long _RESERVED /* 27, 43, 0x0AC, */ + .endif + .if (USE_HT32_CHIP==HT32F0008) + .long AES_IRQHandler /* 28, 44, 0x0B0, */ + .endif + .if (USE_HT32_CHIP==HT32F52344_54) + .long _RESERVED /* 28, 44, 0x0B0, */ + .endif + .if (USE_HT32_CHIP==HT32F52357_67) + .long I2S_IRQHandler /* 28, 44, 0x0B0, */ + .endif + .long USB_IRQHandler /* 29, 45, 0x0B4, */ + .long PDMA_CH0_1_IRQHandler /* 30, 46, 0x0B8, */ + .long PDMA_CH2_5_IRQHandler /* 31, 47, 0x0BC, */ + + .size __interrupt_vector_cortex_m, . - __interrupt_vector_cortex_m + + + .thumb + + +/* Reset Handler */ + + .section .text.Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + LDR R0, =__StackTop /* set stack pointer */ + MOV SP, R0 + LDR R0, =BootProcess + BLX R0 + LDR R0, =SystemInit + BLX R0 + + /* Copy the data segment initializers from flash to SRAM */ + MOVS R1, #0 + B LoopCopyDataInit + +CopyDataInit: + LDR R3, =_sidata + LDR R3, [R3, R1] + STR R3, [R0, R1] + ADDS R1, R1, #4 + +LoopCopyDataInit: + LDR R0, =_sdata + LDR R3, =_edata + ADDS R2, R0, R1 + CMP R2, R3 + BCC CopyDataInit + LDR R2, =_sbss + B LoopFillZerobss + +/* Zero fill the bss segment. */ +FillZerobss: + MOVS R3, #0 + STR R3, [R2] + ADDS R2, R2, #4 + +LoopFillZerobss: + LDR R3, =_ebss + CMP R2, R3 + BCC FillZerobss + + /* Call static constructors */ + BL __libc_init_array + + /* Call the application's entry point.*/ + BL main + +LoopForever: + B LoopForever + + .thumb_func +BootProcess: + LDR R0, =0x40080300 + LDR R1,[R0, #0x10] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x14] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x18] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x1C] + CMP R1, #0 + BEQ BP2 +BP1: + LDR R0, =0x40080180 + LDR R1,[R0, #0xC] + LSLS R1, R1, #4 + LSRS R1, R1, #20 + CMP R1, #0 + BEQ BP3 + CMP R1, #5 + BEQ BP3 + CMP R1, #6 + BEQ BP3 +BP2: + DSB + LDR R0, =0x20000000 + LDR R1, =0x05fa0004 + STR R1, [R0] + LDR R1, =0xe000ed00 + LDR R0, =0x05fa0004 + STR R0, [R1, #0xC] + DSB + B . +BP3: + LDR R0, =0x20000000 + LDR R1, [R0] + LDR R0, =0x05fa0004 + CMP R0, R1 + BEQ BP4 + BX LR +BP4: + LDR R0, =0x40088100 + LDR R1, =0x00000001 + STR R1, [R0] + LDR R0, =0x20000000 + LDR R1, =0x0 + STR R1, [R0] + BX LR + + .size Reset_Handler, .-Reset_Handler + +/* Exception Handlers */ + + .weak NMI_Handler + .type NMI_Handler, %function +NMI_Handler: + B . + .size NMI_Handler, . - NMI_Handler + + .weak HardFault_Handler + .type HardFault_Handler, %function +HardFault_Handler: + B . + .size HardFault_Handler, . - HardFault_Handler + + .weak SVC_Handler + .type SVC_Handler, %function +SVC_Handler: + B . + .size SVC_Handler, . - SVC_Handler + + .weak PendSV_Handler + .type PendSV_Handler, %function +PendSV_Handler: + B . + .size PendSV_Handler, . - PendSV_Handler + + .weak SysTick_Handler + .type SysTick_Handler, %function +SysTick_Handler: + B . + .size SysTick_Handler, . - SysTick_Handler + + +/* IRQ Handlers */ + + .globl Default_Handler + .type Default_Handler, %function +Default_Handler: + B . + .size Default_Handler, . - Default_Handler + + .macro IRQ handler + .weak \handler + .set \handler, Default_Handler + .endm + + IRQ LVD_BOD_IRQHandler + IRQ RTC_IRQHandler + IRQ FLASH_IRQHandler + IRQ EVWUP_IRQHandler + IRQ EXTI0_1_IRQHandler + IRQ EXTI2_3_IRQHandler + IRQ EXTI4_15_IRQHandler + IRQ COMP_IRQHandler + IRQ COMP_DAC_IRQHandler + IRQ ADC_IRQHandler + IRQ MCTM0_IRQHandler + IRQ GPTM0_IRQHandler + IRQ SCTM0_IRQHandler + IRQ SCTM1_IRQHandler + IRQ PWM0_IRQHandler + IRQ PWM1_IRQHandler + IRQ BFTM0_IRQHandler + IRQ BFTM1_IRQHandler + IRQ I2C0_IRQHandler + IRQ I2C1_IRQHandler + IRQ SPI0_IRQHandler + IRQ SPI1_IRQHandler + IRQ QSPI_IRQHandler + IRQ USART0_IRQHandler + IRQ USART1_IRQHandler + IRQ UART0_IRQHandler + IRQ UART1_IRQHandler + IRQ UART0_UART2_IRQHandler + IRQ UART1_UART3_IRQHandler + IRQ SCI_IRQHandler + IRQ I2S_IRQHandler + IRQ AES_IRQHandler + IRQ USB_IRQHandler + IRQ PDMA_CH0_1_IRQHandler + IRQ PDMA_CH2_5_IRQHandler + + .end diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/GCC/startup_ht32f5xxxx_gcc_05.s b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/GCC/startup_ht32f5xxxx_gcc_05.s new file mode 100644 index 0000000000..5aba9e9f48 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/GCC/startup_ht32f5xxxx_gcc_05.s @@ -0,0 +1,396 @@ +/*---------------------------------------------------------------------------------------------------------*/ +/* Holtek Semiconductor Inc. */ +/* */ +/* Copyright (C) Holtek Semiconductor Inc. */ +/* All rights reserved. */ +/* */ +/*----------------------------------------------------------------------------------------------------------- +; File Name : startup_ht32f5xxxx_gcc_05.s +; Version : $Rev:: 6993 $ +; Date : $Date:: 2023-06-26 #$ +; Description : Startup code. +;-----------------------------------------------------------------------------------------------------------*/ + +/* +; Supported Device +; ======================================== +; HT32F57331, HT32F57341 +; HT32F57342, HT32F57352 +; HT32F59741 +; HT32F5828 +; HT32F67742 +; HT32F59746 +*/ + +;/* <<< Use Configuration Wizard in Context Menu >>> */ +/* +;// HT32 Device +;// <0=> By Project Asm Define +;// <13=> HT32F57331/41 +;// <14=> HT32F57342/52 +;// <13=> HT32F59741 +;// <14=> HT32F5828 +;// <13=> HT32F67742 +;// <13=> HT32F59746 +*/ + .equ USE_HT32_CHIP_SET, 0 + + .equ _HT32FWID, 0xFFFFFFFF +/* + .equ _HT32FWID, 0x00057331 + .equ _HT32FWID, 0x00057341 + .equ _HT32FWID, 0x00057342 + .equ _HT32FWID, 0x00057352 + .equ _HT32FWID, 0x00059741 + .equ _HT32FWID, 0x00005828 + .equ _HT32FWID, 0x00067742 + .equ _HT32FWID, 0x00059746 +*/ + + .equ HT32F57331_41, 13 + .equ HT32F57342_52, 14 + .equ HT32F59741, 13 + .equ HT32F5828, 14 + .equ HT32F67742, 13 + .equ HT32F59746, 13 + + .if USE_HT32_CHIP_SET == 0 + .else + .equ USE_HT32_CHIP, USE_HT32_CHIP_SET + .endif + + .syntax unified + .cpu cortex-m0plus + .fpu softvfp + .thumb + +/* start address for the initialization values of the .data section. defined in linker script */ +.word _sidata + +/* start address for the .data section. defined in linker script */ +.word _sdata + +/* end address for the .data section. defined in linker script */ +.word _edata + +/* start address for the .bss section. defined in linker script */ +.word _sbss + +/* end address for the .bss section. defined in linker script */ +.word _ebss + + +/* +; Amount of memory (in bytes) allocated for Stack and Heap +; Tailor those values to your application needs +;// Stack Size (in Bytes, must 8 byte aligned) <:8> +*/ + .equ Stack_Size, 512 + .section ".stack", "w" + .align 3 + .globl __StackTop + .globl __StackLimit + .globl __HT_check_sp +__HT_check_sp: +__StackLimit: + .if Stack_Size + .space Stack_Size + .endif + .size __StackLimit, . - __StackLimit +__StackTop: + .size __StackTop, . - __StackTop + +/* +;// Heap Size (in Bytes) <:8> +*/ + .equ Heap_Size, 0 + .section ".heap", "w" + .align 3 + .globl __HeapBase + .globl _end + .globl __HeapLimit + .globl __HT_check_heap +__HT_check_heap: +__HeapBase: +_end: + .if Heap_Size + .space Heap_Size + .endif + .size __HeapBase, . - __HeapBase +__HeapLimit: + .size __HeapLimit, . - __HeapLimit + + .equ _RESERVED, 0xFFFFFFFF +/* +;******************************************************************************* +; Fill-up the Vector Table entries with the exceptions ISR address +;********************************************************************************/ + .section .isr_vector,"a",%progbits + .global __interrupt_vector_cortex_m + .type __interrupt_vector_cortex_m, %object +__interrupt_vector_cortex_m: + .long __StackTop /* ---, 00, 0x000, Top address of Stack */ + .long Reset_Handler /* ---, 01, 0x004, Reset Handler */ + .long NMI_Handler /* -14, 02, 0x008, NMI Handler */ + .long HardFault_Handler /* -13, 03, 0x00C, Hard Fault Handler */ + .long _RESERVED /* ---, 04, 0x010, Reserved */ + .long _RESERVED /* ---, 05, 0x014, Reserved */ + .long _RESERVED /* ---, 06, 0x018, Reserved */ + .long _RESERVED /* ---, 07, 0x01C, Reserved */ + .long _HT32FWID /* ---, 08, 0x020, Reserved */ + .long _RESERVED /* ---, 09, 0x024, Reserved */ + .long _RESERVED /* ---, 10, 0x028, Reserved */ + .long SVC_Handler /* -05, 11, 0x02C, SVC Handler */ + .long _RESERVED /* ---, 12, 0x030, Reserved */ + .long _RESERVED /* ---, 13, 0x034, Reserved */ + .long PendSV_Handler /* -02, 14, 0x038, PendSV Handler */ + .long SysTick_Handler /* -01, 15, 0x03C, SysTick Handler */ + + /* External Interrupt Handler */ + .long LVD_BOD_IRQHandler /* 00, 16, 0x040, */ + .long RTC_IRQHandler /* 01, 17, 0x044, */ + .long FLASH_IRQHandler /* 02, 18, 0x048, */ + .long EVWUP_IRQHandler /* 03, 19, 0x04C, */ + .long EXTI0_1_IRQHandler /* 04, 20, 0x050, */ + .long EXTI2_3_IRQHandler /* 05, 21, 0x054, */ + .long EXTI4_15_IRQHandler /* 06, 22, 0x058, */ + .if (USE_HT32_CHIP==HT32F57331_41) + .long _RESERVED /* 07, 23, 0x05C, */ + .endif + .if (USE_HT32_CHIP==HT32F57342_52) + .long COMP_DAC_IRQHandler /* 07, 23, 0x05C, */ + .endif + .long ADC_IRQHandler /* 08, 24, 0x060, */ + .if (USE_HT32_CHIP==HT32F57331_41) + .long _RESERVED /* 09, 25, 0x064, */ + .endif + .if (USE_HT32_CHIP==HT32F57342_52) + .long AES_IRQHandler /* 09, 25, 0x064, */ + .endif + .long _RESERVED /* 10, 26, 0x068, */ + .long LCD_IRQHandler /* 11, 27, 0x06C, */ + .long GPTM0_IRQHandler /* 12, 28, 0x070, */ + .if (USE_HT32_CHIP==HT32F57331_41) + .long _RESERVED /* 13, 29, 0x074, */ + .long _RESERVED /* 14, 30, 0x078, */ + .endif + .if (USE_HT32_CHIP==HT32F57342_52) + .long SCTM0_IRQHandler /* 13, 29, 0x074, */ + .long SCTM1_IRQHandler /* 14, 30, 0x078, */ + .endif + .long PWM0_IRQHandler /* 15, 31, 0x07C, */ + .long PWM1_IRQHandler /* 16, 32, 0x080, */ + .long BFTM0_IRQHandler /* 17, 33, 0x084, */ + .long BFTM1_IRQHandler /* 18, 34, 0x088, */ + .long I2C0_IRQHandler /* 19, 35, 0x08C, */ + .long I2C1_IRQHandler /* 20, 36, 0x090, */ + .long SPI0_IRQHandler /* 21, 37, 0x094, */ + .long SPI1_IRQHandler /* 22, 38, 0x098, */ + .long USART0_IRQHandler /* 23, 39, 0x09C, */ + .long _RESERVED /* 24, 40, 0x0A0, */ + .long UART0_IRQHandler /* 25, 41, 0x0A4, */ + .long UART1_IRQHandler /* 26, 42, 0x0A8, */ + .long SCI_IRQHandler /* 27, 43, 0x0AC, */ + .long I2S_IRQHandler /* 28, 44, 0x0B0, */ + .long USB_IRQHandler /* 29, 45, 0x0B4, */ + .if (USE_HT32_CHIP==HT32F57331_41) + .long _RESERVED /* 30, 46, 0x0B8, */ + .long _RESERVED /* 31, 47, 0x0BC, */ + .endif + .if (USE_HT32_CHIP==HT32F57342_52) + .long PDMA_CH0_1_IRQHandler /* 30, 46, 0x0B8, */ + .long PDMA_CH2_5_IRQHandler /* 31, 47, 0x0BC, */ + .endif + + .size __interrupt_vector_cortex_m, . - __interrupt_vector_cortex_m + + + .thumb + + +/* Reset Handler */ + + .section .text.Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + LDR R0, =__StackTop /* set stack pointer */ + MOV SP, R0 + LDR R0, =BootProcess + BLX R0 + LDR R0, =SystemInit + BLX R0 + + /* Copy the data segment initializers from flash to SRAM */ + MOVS R1, #0 + B LoopCopyDataInit + +CopyDataInit: + LDR R3, =_sidata + LDR R3, [R3, R1] + STR R3, [R0, R1] + ADDS R1, R1, #4 + +LoopCopyDataInit: + LDR R0, =_sdata + LDR R3, =_edata + ADDS R2, R0, R1 + CMP R2, R3 + BCC CopyDataInit + LDR R2, =_sbss + B LoopFillZerobss + +/* Zero fill the bss segment. */ +FillZerobss: + MOVS R3, #0 + STR R3, [R2] + ADDS R2, R2, #4 + +LoopFillZerobss: + LDR R3, =_ebss + CMP R2, R3 + BCC FillZerobss + + /* Call static constructors */ + BL __libc_init_array + + /* Call the application's entry point.*/ + BL main + +LoopForever: + B LoopForever + + .thumb_func +BootProcess: + LDR R0, =0x40080300 + LDR R1,[R0, #0x10] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x14] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x18] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x1C] + CMP R1, #0 + BEQ BP2 +BP1: + LDR R0, =0x40080180 + LDR R1,[R0, #0xC] + LSLS R1, R1, #4 + LSRS R1, R1, #20 + CMP R1, #0 + BEQ BP3 + CMP R1, #5 + BEQ BP3 + CMP R1, #6 + BEQ BP3 +BP2: + DSB + LDR R0, =0x20000000 + LDR R1, =0x05fa0004 + STR R1, [R0] + LDR R1, =0xe000ed00 + LDR R0, =0x05fa0004 + STR R0, [R1, #0xC] + DSB + B . +BP3: + LDR R0, =0x20000000 + LDR R1, [R0] + LDR R0, =0x05fa0004 + CMP R0, R1 + BEQ BP4 + BX LR +BP4: + LDR R0, =0x40088100 + LDR R1, =0x00000001 + STR R1, [R0] + LDR R0, =0x20000000 + LDR R1, =0x0 + STR R1, [R0] + BX LR + + .size Reset_Handler, .-Reset_Handler + +/* Exception Handlers */ + + .weak NMI_Handler + .type NMI_Handler, %function +NMI_Handler: + B . + .size NMI_Handler, . - NMI_Handler + + .weak HardFault_Handler + .type HardFault_Handler, %function +HardFault_Handler: + B . + .size HardFault_Handler, . - HardFault_Handler + + .weak SVC_Handler + .type SVC_Handler, %function +SVC_Handler: + B . + .size SVC_Handler, . - SVC_Handler + + .weak PendSV_Handler + .type PendSV_Handler, %function +PendSV_Handler: + B . + .size PendSV_Handler, . - PendSV_Handler + + .weak SysTick_Handler + .type SysTick_Handler, %function +SysTick_Handler: + B . + .size SysTick_Handler, . - SysTick_Handler + + +/* IRQ Handlers */ + + .globl Default_Handler + .type Default_Handler, %function +Default_Handler: + B . + .size Default_Handler, . - Default_Handler + + .macro IRQ handler + .weak \handler + .set \handler, Default_Handler + .endm + + IRQ LVD_BOD_IRQHandler + IRQ RTC_IRQHandler + IRQ FLASH_IRQHandler + IRQ EVWUP_IRQHandler + IRQ EXTI0_1_IRQHandler + IRQ EXTI2_3_IRQHandler + IRQ EXTI4_15_IRQHandler + IRQ COMP_IRQHandler + IRQ COMP_DAC_IRQHandler + IRQ ADC_IRQHandler + IRQ AES_IRQHandler + IRQ LCD_IRQHandler + IRQ GPTM0_IRQHandler + IRQ SCTM0_IRQHandler + IRQ SCTM1_IRQHandler + IRQ PWM0_IRQHandler + IRQ PWM1_IRQHandler + IRQ BFTM0_IRQHandler + IRQ BFTM1_IRQHandler + IRQ I2C0_IRQHandler + IRQ I2C1_IRQHandler + IRQ SPI0_IRQHandler + IRQ SPI1_IRQHandler + IRQ USART0_IRQHandler + IRQ USART1_IRQHandler + IRQ UART0_IRQHandler + IRQ UART1_IRQHandler + IRQ SCI_IRQHandler + IRQ I2S_IRQHandler + IRQ USB_IRQHandler + IRQ PDMA_CH0_1_IRQHandler + IRQ PDMA_CH2_5_IRQHandler + + .end diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/GCC/startup_ht32f5xxxx_gcc_06.s b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/GCC/startup_ht32f5xxxx_gcc_06.s new file mode 100644 index 0000000000..8d21e6d900 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/GCC/startup_ht32f5xxxx_gcc_06.s @@ -0,0 +1,347 @@ +/*---------------------------------------------------------------------------------------------------------*/ +/* Holtek Semiconductor Inc. */ +/* */ +/* Copyright (C) Holtek Semiconductor Inc. */ +/* All rights reserved. */ +/* */ +/*----------------------------------------------------------------------------------------------------------- +; File Name : startup_ht32f5xxxx_gcc_06.s +; Version : $Rev:: 4143 $ +; Date : $Date:: 2019-07-24 #$ +; Description : Startup code. +;-----------------------------------------------------------------------------------------------------------*/ + +/* +; Supported Device +; ======================================== +; HT32F50343 +*/ + +;/* <<< Use Configuration Wizard in Context Menu >>> */ +/* +;// HT32 Device +;// <0=> By Project Asm Define +;// <15=> HT32F50343 +*/ + .equ USE_HT32_CHIP_SET, 0 + + .equ _HT32FWID, 0xFFFFFFFF +/* + .equ _HT32FWID, 0x00050343 +*/ + + .equ HT32F50343, 15 + + .if USE_HT32_CHIP_SET == 0 + .else + .equ USE_HT32_CHIP, USE_HT32_CHIP_SET + .endif + + .syntax unified + .cpu cortex-m0plus + .fpu softvfp + .thumb + +/* start address for the initialization values of the .data section. defined in linker script */ +.word _sidata + +/* start address for the .data section. defined in linker script */ +.word _sdata + +/* end address for the .data section. defined in linker script */ +.word _edata + +/* start address for the .bss section. defined in linker script */ +.word _sbss + +/* end address for the .bss section. defined in linker script */ +.word _ebss + + +/* +; Amount of memory (in bytes) allocated for Stack and Heap +; Tailor those values to your application needs +;// Stack Size (in Bytes, must 8 byte aligned) <:8> +*/ + .equ Stack_Size, 512 + .section ".stack", "w" + .align 3 + .globl __StackTop + .globl __StackLimit + .globl __HT_check_sp +__HT_check_sp: +__StackLimit: + .if Stack_Size + .space Stack_Size + .endif + .size __StackLimit, . - __StackLimit +__StackTop: + .size __StackTop, . - __StackTop + +/* +;// Heap Size (in Bytes) <:8> +*/ + .equ Heap_Size, 0 + .section ".heap", "w" + .align 3 + .globl __HeapBase + .globl _end + .globl __HeapLimit + .globl __HT_check_heap +__HT_check_heap: +__HeapBase: +_end: + .if Heap_Size + .space Heap_Size + .endif + .size __HeapBase, . - __HeapBase +__HeapLimit: + .size __HeapLimit, . - __HeapLimit + + .equ _RESERVED, 0xFFFFFFFF +/* +;******************************************************************************* +; Fill-up the Vector Table entries with the exceptions ISR address +;********************************************************************************/ + .section .isr_vector,"a",%progbits + .global __interrupt_vector_cortex_m + .type __interrupt_vector_cortex_m, %object +__interrupt_vector_cortex_m: + .long __StackTop /* ---, 00, 0x000, Top address of Stack */ + .long Reset_Handler /* ---, 01, 0x004, Reset Handler */ + .long NMI_Handler /* -14, 02, 0x008, NMI Handler */ + .long HardFault_Handler /* -13, 03, 0x00C, Hard Fault Handler */ + .long _RESERVED /* ---, 04, 0x010, Reserved */ + .long _RESERVED /* ---, 05, 0x014, Reserved */ + .long _RESERVED /* ---, 06, 0x018, Reserved */ + .long _RESERVED /* ---, 07, 0x01C, Reserved */ + .long _HT32FWID /* ---, 08, 0x020, Reserved */ + .long _RESERVED /* ---, 09, 0x024, Reserved */ + .long _RESERVED /* ---, 10, 0x028, Reserved */ + .long SVC_Handler /* -05, 11, 0x02C, SVC Handler */ + .long _RESERVED /* ---, 12, 0x030, Reserved */ + .long _RESERVED /* ---, 13, 0x034, Reserved */ + .long PendSV_Handler /* -02, 14, 0x038, PendSV Handler */ + .long SysTick_Handler /* -01, 15, 0x03C, SysTick Handler */ + + /* External Interrupt Handler */ + .long LVD_BOD_IRQHandler /* 00, 16, 0x040, */ + .long RTC_IRQHandler /* 01, 17, 0x044, */ + .long FLASH_IRQHandler /* 02, 18, 0x048, */ + .long EVWUP_IRQHandler /* 03, 19, 0x04C, */ + .long EXTI0_1_IRQHandler /* 04, 20, 0x050, */ + .long EXTI2_3_IRQHandler /* 05, 21, 0x054, */ + .long EXTI4_15_IRQHandler /* 06, 22, 0x058, */ + .long _RESERVED /* 07, 23, 0x05C, */ + .long ADC_IRQHandler /* 08, 24, 0x060, */ + .long _RESERVED /* 09, 25, 0x064, */ + .long PWM2_IRQHandler /* 10, 26, 0x068, */ + .long _RESERVED /* 11, 27, 0x06C, */ + .long GPTM0_IRQHandler /* 12, 28, 0x070, */ + .long SCTM0_IRQHandler /* 13, 29, 0x074, */ + .long SCTM1_IRQHandler /* 14, 30, 0x078, */ + .long PWM0_IRQHandler /* 15, 31, 0x07C, */ + .long PWM1_IRQHandler /* 16, 32, 0x080, */ + .long BFTM0_IRQHandler /* 17, 33, 0x084, */ + .long BFTM1_IRQHandler /* 18, 34, 0x088, */ + .long I2C0_IRQHandler /* 19, 35, 0x08C, */ + .long I2C1_IRQHandler /* 20, 36, 0x090, */ + .long SPI0_IRQHandler /* 21, 37, 0x094, */ + .long SPI1_IRQHandler /* 22, 38, 0x098, */ + .long _RESERVED /* 23, 39, 0x09C, */ + .long _RESERVED /* 24, 40, 0x0A0, */ + .long UART0_IRQHandler /* 25, 41, 0x0A4, */ + .long UART1_IRQHandler /* 26, 42, 0x0A8, */ + .long SLED0_IRQHandler /* 27, 43, 0x0AC, */ + .long SLED1_IRQHandler /* 28, 44, 0x0B0, */ + .long USB_IRQHandler /* 29, 45, 0x0B4, */ + .long PDMA_CH0_1_IRQHandler /* 30, 46, 0x0B8, */ + .long PDMA_CH2_5_IRQHandler /* 31, 47, 0x0BC, */ + + .size __interrupt_vector_cortex_m, . - __interrupt_vector_cortex_m + + + .thumb + + +/* Reset Handler */ + + .section .text.Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + LDR R0, =__StackTop /* set stack pointer */ + MOV SP, R0 + LDR R0, =BootProcess + BLX R0 + LDR R0, =SystemInit + BLX R0 + + /* Copy the data segment initializers from flash to SRAM */ + MOVS R1, #0 + B LoopCopyDataInit + +CopyDataInit: + LDR R3, =_sidata + LDR R3, [R3, R1] + STR R3, [R0, R1] + ADDS R1, R1, #4 + +LoopCopyDataInit: + LDR R0, =_sdata + LDR R3, =_edata + ADDS R2, R0, R1 + CMP R2, R3 + BCC CopyDataInit + LDR R2, =_sbss + B LoopFillZerobss + +/* Zero fill the bss segment. */ +FillZerobss: + MOVS R3, #0 + STR R3, [R2] + ADDS R2, R2, #4 + +LoopFillZerobss: + LDR R3, =_ebss + CMP R2, R3 + BCC FillZerobss + + /* Call static constructors */ + BL __libc_init_array + + /* Call the application's entry point.*/ + BL main + +LoopForever: + B LoopForever + + .thumb_func +BootProcess: + LDR R0, =0x40080300 + LDR R1,[R0, #0x10] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x14] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x18] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x1C] + CMP R1, #0 + BEQ BP2 +BP1: + LDR R0, =0x40080180 + LDR R1,[R0, #0xC] + LSLS R1, R1, #4 + LSRS R1, R1, #20 + CMP R1, #0 + BEQ BP3 + CMP R1, #5 + BEQ BP3 + CMP R1, #6 + BEQ BP3 +BP2: + DSB + LDR R0, =0x20000000 + LDR R1, =0x05fa0004 + STR R1, [R0] + LDR R1, =0xe000ed00 + LDR R0, =0x05fa0004 + STR R0, [R1, #0xC] + DSB + B . +BP3: + LDR R0, =0x20000000 + LDR R1, [R0] + LDR R0, =0x05fa0004 + CMP R0, R1 + BEQ BP4 + BX LR +BP4: + LDR R0, =0x40088100 + LDR R1, =0x00000001 + STR R1, [R0] + LDR R0, =0x20000000 + LDR R1, =0x0 + STR R1, [R0] + BX LR + + .size Reset_Handler, .-Reset_Handler + +/* Exception Handlers */ + + .weak NMI_Handler + .type NMI_Handler, %function +NMI_Handler: + B . + .size NMI_Handler, . - NMI_Handler + + .weak HardFault_Handler + .type HardFault_Handler, %function +HardFault_Handler: + B . + .size HardFault_Handler, . - HardFault_Handler + + .weak SVC_Handler + .type SVC_Handler, %function +SVC_Handler: + B . + .size SVC_Handler, . - SVC_Handler + + .weak PendSV_Handler + .type PendSV_Handler, %function +PendSV_Handler: + B . + .size PendSV_Handler, . - PendSV_Handler + + .weak SysTick_Handler + .type SysTick_Handler, %function +SysTick_Handler: + B . + .size SysTick_Handler, . - SysTick_Handler + + +/* IRQ Handlers */ + + .globl Default_Handler + .type Default_Handler, %function +Default_Handler: + B . + .size Default_Handler, . - Default_Handler + + .macro IRQ handler + .weak \handler + .set \handler, Default_Handler + .endm + + IRQ LVD_BOD_IRQHandler + IRQ RTC_IRQHandler + IRQ FLASH_IRQHandler + IRQ EVWUP_IRQHandler + IRQ EXTI0_1_IRQHandler + IRQ EXTI2_3_IRQHandler + IRQ EXTI4_15_IRQHandler + IRQ ADC_IRQHandler + IRQ PWM2_IRQHandler + IRQ GPTM0_IRQHandler + IRQ SCTM0_IRQHandler + IRQ SCTM1_IRQHandler + IRQ PWM0_IRQHandler + IRQ PWM1_IRQHandler + IRQ BFTM0_IRQHandler + IRQ BFTM1_IRQHandler + IRQ I2C0_IRQHandler + IRQ I2C1_IRQHandler + IRQ SPI0_IRQHandler + IRQ SPI1_IRQHandler + IRQ UART0_IRQHandler + IRQ UART1_IRQHandler + IRQ SLED0_IRQHandler + IRQ SLED1_IRQHandler + IRQ USB_IRQHandler + IRQ PDMA_CH0_1_IRQHandler + IRQ PDMA_CH2_5_IRQHandler + + .end diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/GCC/startup_ht32f5xxxx_gcc_07.s b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/GCC/startup_ht32f5xxxx_gcc_07.s new file mode 100644 index 0000000000..f6702bded7 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/GCC/startup_ht32f5xxxx_gcc_07.s @@ -0,0 +1,355 @@ +/*---------------------------------------------------------------------------------------------------------*/ +/* Holtek Semiconductor Inc. */ +/* */ +/* Copyright (C) Holtek Semiconductor Inc. */ +/* All rights reserved. */ +/* */ +/*----------------------------------------------------------------------------------------------------------- +; File Name : startup_ht32f5xxxx_gcc_07.s +; Version : $Rev:: 5157 $ +; Date : $Date:: 2021-01-18 #$ +; Description : Startup code. +;-----------------------------------------------------------------------------------------------------------*/ + +/* +; Supported Device +; ======================================== +; HT32F0006 +; HT32F61352 +; HT32F61355, HT32F61356, HT32F61357 +*/ + +;/* <<< Use Configuration Wizard in Context Menu >>> */ +/* +;// HT32 Device +;// <0=> By Project Asm Define +;// <10=> HT32F0006 +;// <10=> HT32F61352 +;// <17=> HT32F61355/56/57 +*/ + .equ USE_HT32_CHIP_SET, 0 + + .equ _HT32FWID, 0xFFFFFFFF +/* + .equ _HT32FWID, 0x00000006 + .equ _HT32FWID, 0x00061352 + .equ _HT32FWID, 0x00061355 + .equ _HT32FWID, 0x00061356 + .equ _HT32FWID, 0x00061357 +*/ + + .equ HT32F0006, 10 + .equ HT32F61352, 10 + .equ HT32F61355_56_57, 17 + + .if USE_HT32_CHIP_SET == 0 + .else + .equ USE_HT32_CHIP, USE_HT32_CHIP_SET + .endif + + .syntax unified + .cpu cortex-m0plus + .fpu softvfp + .thumb + +/* start address for the initialization values of the .data section. defined in linker script */ +.word _sidata + +/* start address for the .data section. defined in linker script */ +.word _sdata + +/* end address for the .data section. defined in linker script */ +.word _edata + +/* start address for the .bss section. defined in linker script */ +.word _sbss + +/* end address for the .bss section. defined in linker script */ +.word _ebss + + +/* +; Amount of memory (in bytes) allocated for Stack and Heap +; Tailor those values to your application needs +;// Stack Size (in Bytes, must 8 byte aligned) <:8> +*/ + .equ Stack_Size, 512 + .section ".stack", "w" + .align 3 + .globl __StackTop + .globl __StackLimit + .globl __HT_check_sp +__HT_check_sp: +__StackLimit: + .if Stack_Size + .space Stack_Size + .endif + .size __StackLimit, . - __StackLimit +__StackTop: + .size __StackTop, . - __StackTop + +/* +;// Heap Size (in Bytes) <:8> +*/ + .equ Heap_Size, 0 + .section ".heap", "w" + .align 3 + .globl __HeapBase + .globl _end + .globl __HeapLimit + .globl __HT_check_heap +__HT_check_heap: +__HeapBase: +_end: + .if Heap_Size + .space Heap_Size + .endif + .size __HeapBase, . - __HeapBase +__HeapLimit: + .size __HeapLimit, . - __HeapLimit + + .equ _RESERVED, 0xFFFFFFFF +/* +;******************************************************************************* +; Fill-up the Vector Table entries with the exceptions ISR address +;********************************************************************************/ + .section .isr_vector,"a",%progbits + .global __interrupt_vector_cortex_m + .type __interrupt_vector_cortex_m, %object +__interrupt_vector_cortex_m: + .long __StackTop /* ---, 00, 0x000, Top address of Stack */ + .long Reset_Handler /* ---, 01, 0x004, Reset Handler */ + .long NMI_Handler /* -14, 02, 0x008, NMI Handler */ + .long HardFault_Handler /* -13, 03, 0x00C, Hard Fault Handler */ + .long _RESERVED /* ---, 04, 0x010, Reserved */ + .long _RESERVED /* ---, 05, 0x014, Reserved */ + .long _RESERVED /* ---, 06, 0x018, Reserved */ + .long _RESERVED /* ---, 07, 0x01C, Reserved */ + .long _HT32FWID /* ---, 08, 0x020, Reserved */ + .long _RESERVED /* ---, 09, 0x024, Reserved */ + .long _RESERVED /* ---, 10, 0x028, Reserved */ + .long SVC_Handler /* -05, 11, 0x02C, SVC Handler */ + .long _RESERVED /* ---, 12, 0x030, Reserved */ + .long _RESERVED /* ---, 13, 0x034, Reserved */ + .long PendSV_Handler /* -02, 14, 0x038, PendSV Handler */ + .long SysTick_Handler /* -01, 15, 0x03C, SysTick Handler */ + + /* External Interrupt Handler */ + .long LVD_BOD_IRQHandler /* 00, 16, 0x040, */ + .long RTC_IRQHandler /* 01, 17, 0x044, */ + .long FLASH_IRQHandler /* 02, 18, 0x048, */ + .long EVWUP_IRQHandler /* 03, 19, 0x04C, */ + .long EXTI0_1_IRQHandler /* 04, 20, 0x050, */ + .long EXTI2_3_IRQHandler /* 05, 21, 0x054, */ + .long EXTI4_15_IRQHandler /* 06, 22, 0x058, */ + .long _RESERVED /* 07, 23, 0x05C, */ + .long ADC_IRQHandler /* 08, 24, 0x060, */ + .long _RESERVED /* 09, 25, 0x064, */ + .long _RESERVED /* 10, 26, 0x068, */ + .long _RESERVED /* 11, 27, 0x06C, */ + .long GPTM0_IRQHandler /* 12, 28, 0x070, */ + .long SCTM0_IRQHandler /* 13, 29, 0x074, */ + .long SCTM1_IRQHandler /* 14, 30, 0x078, */ + .long SCTM2_IRQHandler /* 15, 31, 0x07C, */ + .long SCTM3_IRQHandler /* 16, 32, 0x080, */ + .long BFTM0_IRQHandler /* 17, 33, 0x084, */ + .long BFTM1_IRQHandler /* 18, 34, 0x088, */ + .long I2C0_IRQHandler /* 19, 35, 0x08C, */ + .long _RESERVED /* 20, 36, 0x090, */ + .long SPI0_IRQHandler /* 21, 37, 0x094, */ + .long QSPI_IRQHandler /* 22, 38, 0x098, */ + .long USART0_IRQHandler /* 23, 39, 0x09C, */ + .long _RESERVED /* 24, 40, 0x0A0, */ + .long UART0_IRQHandler /* 25, 41, 0x0A4, */ + .long _RESERVED /* 26, 42, 0x0A8, */ + .long MIDI_IRQHandler /* 27, 43, 0x0AC, */ + .long I2S_IRQHandler /* 28, 44, 0x0B0, */ + .long USB_IRQHandler /* 29, 45, 0x0B4, */ + .long PDMA_CH0_1_IRQHandler /* 30, 46, 0x0B8, */ + .long PDMA_CH2_5_IRQHandler /* 31, 47, 0x0BC, */ + + .size __interrupt_vector_cortex_m, . - __interrupt_vector_cortex_m + + + .thumb + + +/* Reset Handler */ + + .section .text.Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + LDR R0, =__StackTop /* set stack pointer */ + MOV SP, R0 + LDR R0, =BootProcess + BLX R0 + LDR R0, =SystemInit + BLX R0 + + /* Copy the data segment initializers from flash to SRAM */ + MOVS R1, #0 + B LoopCopyDataInit + +CopyDataInit: + LDR R3, =_sidata + LDR R3, [R3, R1] + STR R3, [R0, R1] + ADDS R1, R1, #4 + +LoopCopyDataInit: + LDR R0, =_sdata + LDR R3, =_edata + ADDS R2, R0, R1 + CMP R2, R3 + BCC CopyDataInit + LDR R2, =_sbss + B LoopFillZerobss + +/* Zero fill the bss segment. */ +FillZerobss: + MOVS R3, #0 + STR R3, [R2] + ADDS R2, R2, #4 + +LoopFillZerobss: + LDR R3, =_ebss + CMP R2, R3 + BCC FillZerobss + + /* Call static constructors */ + BL __libc_init_array + + /* Call the application's entry point.*/ + BL main + +LoopForever: + B LoopForever + + .thumb_func +BootProcess: + LDR R0, =0x40080300 + LDR R1,[R0, #0x10] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x14] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x18] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x1C] + CMP R1, #0 + BEQ BP2 +BP1: + LDR R0, =0x40080180 + LDR R1,[R0, #0xC] + LSLS R1, R1, #4 + LSRS R1, R1, #20 + CMP R1, #0 + BEQ BP3 + CMP R1, #5 + BEQ BP3 + CMP R1, #6 + BEQ BP3 +BP2: + DSB + LDR R0, =0x20000000 + LDR R1, =0x05fa0004 + STR R1, [R0] + LDR R1, =0xe000ed00 + LDR R0, =0x05fa0004 + STR R0, [R1, #0xC] + DSB + B . +BP3: + LDR R0, =0x20000000 + LDR R1, [R0] + LDR R0, =0x05fa0004 + CMP R0, R1 + BEQ BP4 + BX LR +BP4: + LDR R0, =0x40088100 + LDR R1, =0x00000001 + STR R1, [R0] + LDR R0, =0x20000000 + LDR R1, =0x0 + STR R1, [R0] + BX LR + + .size Reset_Handler, .-Reset_Handler + +/* Exception Handlers */ + + .weak NMI_Handler + .type NMI_Handler, %function +NMI_Handler: + B . + .size NMI_Handler, . - NMI_Handler + + .weak HardFault_Handler + .type HardFault_Handler, %function +HardFault_Handler: + B . + .size HardFault_Handler, . - HardFault_Handler + + .weak SVC_Handler + .type SVC_Handler, %function +SVC_Handler: + B . + .size SVC_Handler, . - SVC_Handler + + .weak PendSV_Handler + .type PendSV_Handler, %function +PendSV_Handler: + B . + .size PendSV_Handler, . - PendSV_Handler + + .weak SysTick_Handler + .type SysTick_Handler, %function +SysTick_Handler: + B . + .size SysTick_Handler, . - SysTick_Handler + + +/* IRQ Handlers */ + + .globl Default_Handler + .type Default_Handler, %function +Default_Handler: + B . + .size Default_Handler, . - Default_Handler + + .macro IRQ handler + .weak \handler + .set \handler, Default_Handler + .endm + + IRQ LVD_BOD_IRQHandler + IRQ RTC_IRQHandler + IRQ FLASH_IRQHandler + IRQ EVWUP_IRQHandler + IRQ EXTI0_1_IRQHandler + IRQ EXTI2_3_IRQHandler + IRQ EXTI4_15_IRQHandler + IRQ ADC_IRQHandler + IRQ GPTM0_IRQHandler + IRQ SCTM0_IRQHandler + IRQ SCTM1_IRQHandler + IRQ SCTM2_IRQHandler + IRQ SCTM3_IRQHandler + IRQ BFTM0_IRQHandler + IRQ BFTM1_IRQHandler + IRQ I2C0_IRQHandler + IRQ SPI0_IRQHandler + IRQ QSPI_IRQHandler + IRQ USART0_IRQHandler + IRQ UART0_IRQHandler + IRQ MIDI_IRQHandler + IRQ I2S_IRQHandler + IRQ USB_IRQHandler + IRQ PDMA_CH0_1_IRQHandler + IRQ PDMA_CH2_5_IRQHandler + + .end diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/GCC/startup_ht32f5xxxx_gcc_08.s b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/GCC/startup_ht32f5xxxx_gcc_08.s new file mode 100644 index 0000000000..eef814945f --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/GCC/startup_ht32f5xxxx_gcc_08.s @@ -0,0 +1,315 @@ +/*---------------------------------------------------------------------------------------------------------*/ +/* Holtek Semiconductor Inc. */ +/* */ +/* Copyright (C) Holtek Semiconductor Inc. */ +/* All rights reserved. */ +/* */ +/*----------------------------------------------------------------------------------------------------------- +; File Name : startup_ht32f5xxxx_gcc_08.s +; Version : $Rev:: 6887 $ +; Date : $Date:: 2023-05-05 #$ +; Description : Startup code. +;-----------------------------------------------------------------------------------------------------------*/ + +/* +; Supported Device +; ======================================== +; HT32F65230, HT32F65240 +; HT32F65232 +; HT50F3200S +*/ + +;/* <<< Use Configuration Wizard in Context Menu >>> */ +/* +;// HT32 Device +;// <0=> By Project Asm Define +;// <12=> HT32F65230_40 +;// <18=> HT32F65232 +;// <12=> HT50F3200S +*/ + .equ USE_HT32_CHIP_SET, 0 + + .equ _HT32FWID, 0xFFFFFFFF +/* + .equ _HT32FWID, 0x00065230 + .equ _HT32FWID, 0x00065240 + .equ _HT32FWID, 0x00065232 + .equ _HT32FWID, 0x0003200F +*/ + + .equ HT32F65230_40, 12 + .equ HT32F65232, 18 + .equ HT50F3200S, 12 + + .if USE_HT32_CHIP_SET == 0 + .else + .equ USE_HT32_CHIP, USE_HT32_CHIP_SET + .endif + + .syntax unified + .cpu cortex-m0plus + .fpu softvfp + .thumb + +/* start address for the initialization values of the .data section. defined in linker script */ +.word _sidata + +/* start address for the .data section. defined in linker script */ +.word _sdata + +/* end address for the .data section. defined in linker script */ +.word _edata + +/* start address for the .bss section. defined in linker script */ +.word _sbss + +/* end address for the .bss section. defined in linker script */ +.word _ebss + + +/* +; Amount of memory (in bytes) allocated for Stack and Heap +; Tailor those values to your application needs +;// Stack Size (in Bytes, must 8 byte aligned) <:8> +*/ + .equ Stack_Size, 512 + .section ".stack", "w" + .align 3 + .globl __StackTop + .globl __StackLimit + .globl __HT_check_sp +__HT_check_sp: +__StackLimit: + .if Stack_Size + .space Stack_Size + .endif + .size __StackLimit, . - __StackLimit +__StackTop: + .size __StackTop, . - __StackTop + +/* +;// Heap Size (in Bytes) <:8> +*/ + .equ Heap_Size, 0 + .section ".heap", "w" + .align 3 + .globl __HeapBase + .globl _end + .globl __HeapLimit + .globl __HT_check_heap +__HT_check_heap: +__HeapBase: +_end: + .if Heap_Size + .space Heap_Size + .endif + .size __HeapBase, . - __HeapBase +__HeapLimit: + .size __HeapLimit, . - __HeapLimit + + .equ _RESERVED, 0xFFFFFFFF +/* +;******************************************************************************* +; Fill-up the Vector Table entries with the exceptions ISR address +;********************************************************************************/ + .section .isr_vector,"a",%progbits + .global __interrupt_vector_cortex_m + .type __interrupt_vector_cortex_m, %object +__interrupt_vector_cortex_m: + .long __StackTop /* ---, 00, 0x000, Top address of Stack */ + .long Reset_Handler /* ---, 01, 0x004, Reset Handler */ + .long NMI_Handler /* -14, 02, 0x008, NMI Handler */ + .long HardFault_Handler /* -13, 03, 0x00C, Hard Fault Handler */ + .long _RESERVED /* ---, 04, 0x010, Reserved */ + .long _RESERVED /* ---, 05, 0x014, Reserved */ + .long _RESERVED /* ---, 06, 0x018, Reserved */ + .long _RESERVED /* ---, 07, 0x01C, Reserved */ + .long _HT32FWID /* ---, 08, 0x020, Reserved */ + .long _RESERVED /* ---, 09, 0x024, Reserved */ + .long _RESERVED /* ---, 10, 0x028, Reserved */ + .long SVC_Handler /* -05, 11, 0x02C, SVC Handler */ + .long _RESERVED /* ---, 12, 0x030, Reserved */ + .long _RESERVED /* ---, 13, 0x034, Reserved */ + .long PendSV_Handler /* -02, 14, 0x038, PendSV Handler */ + .long SysTick_Handler /* -01, 15, 0x03C, SysTick Handler */ + + /* External Interrupt Handler */ + .long LVD_BOD_IRQHandler /* 00, 16, 0x040, */ + .long RTC_IRQHandler /* 01, 17, 0x044, */ + .long FLASH_IRQHandler /* 02, 18, 0x048, */ + .long EVWUP_IRQHandler /* 03, 19, 0x04C, */ + .long EXTI0_1_IRQHandler /* 04, 20, 0x050, */ + .long EXTI2_3_IRQHandler /* 05, 21, 0x054, */ + .long EXTI4_9_IRQHandler /* 06, 22, 0x058, */ + .long EXTI10_15_IRQHandler /* 07, 23, 0x05C, */ + .long ADC0_IRQHandler /* 08, 24, 0x060, */ + .if (USE_HT32_CHIP==HT32F65230_40) + .long ADC1_IRQHandler /* 09, 25, 0x064, */ + .else + .long _RESERVED /* 09, 25, 0x064, */ + .endif + .long MCTM0_BRK_IRQHandler /* 10, 26, 0x068, */ + .long MCTM0_UP_IRQHandler /* 11, 27, 0x06C, */ + .long MCTM0_TR_UP2_IRQHandler /* 12, 28, 0x070, */ + .long MCTM0_CC_IRQHandler /* 13, 29, 0x074, */ + .long GPTM0_G_IRQHandler /* 14, 30, 0x078, */ + .long GPTM0_VCLK_IRQHandler /* 15, 31, 0x07C, */ + .long BFTM0_IRQHandler /* 16, 32, 0x080, */ + .long BFTM1_IRQHandler /* 17, 33, 0x084, */ + .long CMP0_IRQHandler /* 18, 34, 0x088, */ + .long CMP1_IRQHandler /* 19, 35, 0x08C, */ + .if (USE_HT32_CHIP==HT32F65230_40) + .long CMP2_IRQHandler /* 20, 36, 0x090, */ + .else + .long _RESERVED /* 20, 36, 0x090, */ + .endif + .long I2C0_IRQHandler /* 21, 37, 0x094, */ + .long SPI0_IRQHandler /* 22, 38, 0x098, */ + .long USART0_IRQHandler /* 23, 39, 0x09C, */ + .long UART0_IRQHandler /* 24, 40, 0x0A0, */ + .long PDMA_CH0_1_IRQHandler /* 25, 41, 0x0A4, */ + .long PDMA_CH2_3_IRQHandler /* 26, 42, 0x0A8, */ + .long PDMA_CH4_5_IRQHandler /* 27, 43, 0x0AC, */ + .long SCTM0_IRQHandler /* 28, 44, 0x0B0, */ + .long SCTM1_IRQHandler /* 29, 45, 0x0B4, */ + .long SCTM2_IRQHandler /* 30, 46, 0x0B8, */ + .long SCTM3_IRQHandler /* 31, 47, 0x0BC, */ + + .size __interrupt_vector_cortex_m, . - __interrupt_vector_cortex_m + + + .thumb + + +/* Reset Handler */ + + .section .text.Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + LDR R0, =__StackTop /* set stack pointer */ + MOV SP, R0 + LDR R0, =SystemInit + BLX R0 + + /* Copy the data segment initializers from flash to SRAM */ + MOVS R1, #0 + B LoopCopyDataInit + +CopyDataInit: + LDR R3, =_sidata + LDR R3, [R3, R1] + STR R3, [R0, R1] + ADDS R1, R1, #4 + +LoopCopyDataInit: + LDR R0, =_sdata + LDR R3, =_edata + ADDS R2, R0, R1 + CMP R2, R3 + BCC CopyDataInit + LDR R2, =_sbss + B LoopFillZerobss + +/* Zero fill the bss segment. */ +FillZerobss: + MOVS R3, #0 + STR R3, [R2] + ADDS R2, R2, #4 + +LoopFillZerobss: + LDR R3, =_ebss + CMP R2, R3 + BCC FillZerobss + + /* Call static constructors */ + BL __libc_init_array + + /* Call the application's entry point.*/ + BL main + +LoopForever: + B LoopForever + + .size Reset_Handler, .-Reset_Handler + +/* Exception Handlers */ + + .weak NMI_Handler + .type NMI_Handler, %function +NMI_Handler: + B . + .size NMI_Handler, . - NMI_Handler + + .weak HardFault_Handler + .type HardFault_Handler, %function +HardFault_Handler: + B . + .size HardFault_Handler, . - HardFault_Handler + + .weak SVC_Handler + .type SVC_Handler, %function +SVC_Handler: + B . + .size SVC_Handler, . - SVC_Handler + + .weak PendSV_Handler + .type PendSV_Handler, %function +PendSV_Handler: + B . + .size PendSV_Handler, . - PendSV_Handler + + .weak SysTick_Handler + .type SysTick_Handler, %function +SysTick_Handler: + B . + .size SysTick_Handler, . - SysTick_Handler + + +/* IRQ Handlers */ + + .globl Default_Handler + .type Default_Handler, %function +Default_Handler: + B . + .size Default_Handler, . - Default_Handler + + .macro IRQ handler + .weak \handler + .set \handler, Default_Handler + .endm + + IRQ LVD_BOD_IRQHandler + IRQ RTC_IRQHandler + IRQ FLASH_IRQHandler + IRQ EVWUP_IRQHandler + IRQ EXTI0_1_IRQHandler + IRQ EXTI2_3_IRQHandler + IRQ EXTI4_9_IRQHandler + IRQ EXTI10_15_IRQHandler + IRQ ADC0_IRQHandler + IRQ ADC1_IRQHandler + IRQ MCTM0_BRK_IRQHandler + IRQ MCTM0_UP_IRQHandler + IRQ MCTM0_TR_UP2_IRQHandler + IRQ MCTM0_CC_IRQHandler + IRQ GPTM0_G_IRQHandler + IRQ GPTM0_VCLK_IRQHandler + IRQ BFTM0_IRQHandler + IRQ BFTM1_IRQHandler + IRQ CMP0_IRQHandler + IRQ CMP1_IRQHandler + IRQ CMP2_IRQHandler + IRQ I2C0_IRQHandler + IRQ SPI0_IRQHandler + IRQ USART0_IRQHandler + IRQ UART0_IRQHandler + IRQ PDMA_CH0_1_IRQHandler + IRQ PDMA_CH2_3_IRQHandler + IRQ PDMA_CH4_5_IRQHandler + IRQ SCTM0_IRQHandler + IRQ SCTM1_IRQHandler + IRQ SCTM2_IRQHandler + IRQ SCTM3_IRQHandler + + .end diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/GCC/startup_ht32f5xxxx_gcc_09.s b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/GCC/startup_ht32f5xxxx_gcc_09.s new file mode 100644 index 0000000000..1a2be14682 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/GCC/startup_ht32f5xxxx_gcc_09.s @@ -0,0 +1,387 @@ +/*---------------------------------------------------------------------------------------------------------*/ +/* Holtek Semiconductor Inc. */ +/* */ +/* Copyright (C) Holtek Semiconductor Inc. */ +/* All rights reserved. */ +/* */ +/*----------------------------------------------------------------------------------------------------------- +; File Name : startup_ht32f5xxxx_gcc_09.s +; Version : $Rev:: 5410 $ +; Date : $Date:: 2021-06-04 #$ +; Description : Startup code. +;-----------------------------------------------------------------------------------------------------------*/ + +/* +; Supported Device +; ======================================== +; HT32F54231, HT32F54241 +; HT32F54243, HT32F54253 +*/ + +;/* <<< Use Configuration Wizard in Context Menu >>> */ +/* +;// HT32 Device +;// <0=> By Project Asm Define +;// <19=> HT32F54231/41 +;// <20=> HT32F54243/53 +*/ + .equ USE_HT32_CHIP_SET, 0 + + .equ _HT32FWID, 0xFFFFFFFF +/* + .equ _HT32FWID, 0x00054231 + .equ _HT32FWID, 0x00054241 + .equ _HT32FWID, 0x00054243 + .equ _HT32FWID, 0x00054253 +*/ + + .equ HT32F54231_41, 19 + .equ HT32F54243_53, 20 + + .if USE_HT32_CHIP_SET == 0 + .else + .equ USE_HT32_CHIP, USE_HT32_CHIP_SET + .endif + + .syntax unified + .cpu cortex-m0plus + .fpu softvfp + .thumb + +/* start address for the initialization values of the .data section. defined in linker script */ +.word _sidata + +/* start address for the .data section. defined in linker script */ +.word _sdata + +/* end address for the .data section. defined in linker script */ +.word _edata + +/* start address for the .bss section. defined in linker script */ +.word _sbss + +/* end address for the .bss section. defined in linker script */ +.word _ebss + + +/* +; Amount of memory (in bytes) allocated for Stack and Heap +; Tailor those values to your application needs +;// Stack Size (in Bytes, must 8 byte aligned) <:8> +*/ + .equ Stack_Size, 512 + .section ".stack", "w" + .align 3 + .globl __StackTop + .globl __StackLimit + .globl __HT_check_sp +__HT_check_sp: +__StackLimit: + .if Stack_Size + .space Stack_Size + .endif + .size __StackLimit, . - __StackLimit +__StackTop: + .size __StackTop, . - __StackTop + +/* +;// Heap Size (in Bytes) <:8> +*/ + .equ Heap_Size, 0 + .section ".heap", "w" + .align 3 + .globl __HeapBase + .globl _end + .globl __HeapLimit + .globl __HT_check_heap +__HT_check_heap: +__HeapBase: +_end: + .if Heap_Size + .space Heap_Size + .endif + .size __HeapBase, . - __HeapBase +__HeapLimit: + .size __HeapLimit, . - __HeapLimit + + .equ _RESERVED, 0xFFFFFFFF +/* +;******************************************************************************* +; Fill-up the Vector Table entries with the exceptions ISR address +;********************************************************************************/ + .section .isr_vector,"a",%progbits + .global __interrupt_vector_cortex_m + .type __interrupt_vector_cortex_m, %object +__interrupt_vector_cortex_m: + .long __StackTop /* ---, 00, 0x000, Top address of Stack */ + .long Reset_Handler /* ---, 01, 0x004, Reset Handler */ + .long NMI_Handler /* -14, 02, 0x008, NMI Handler */ + .long HardFault_Handler /* -13, 03, 0x00C, Hard Fault Handler */ + .long _RESERVED /* ---, 04, 0x010, Reserved */ + .long _RESERVED /* ---, 05, 0x014, Reserved */ + .long _RESERVED /* ---, 06, 0x018, Reserved */ + .long _RESERVED /* ---, 07, 0x01C, Reserved */ + .long _HT32FWID /* ---, 08, 0x020, Reserved */ + .long _RESERVED /* ---, 09, 0x024, Reserved */ + .long _RESERVED /* ---, 10, 0x028, Reserved */ + .long SVC_Handler /* -05, 11, 0x02C, SVC Handler */ + .long _RESERVED /* ---, 12, 0x030, Reserved */ + .long _RESERVED /* ---, 13, 0x034, Reserved */ + .long PendSV_Handler /* -02, 14, 0x038, PendSV Handler */ + .long SysTick_Handler /* -01, 15, 0x03C, SysTick Handler */ + + /* External Interrupt Handler */ + .long LVD_BOD_IRQHandler /* 00, 16, 0x040, */ + .long RTC_IRQHandler /* 01, 17, 0x044, */ + .long FLASH_IRQHandler /* 02, 18, 0x048, */ + .long EVWUP_IRQHandler /* 03, 19, 0x04C, */ + .long EXTI0_1_IRQHandler /* 04, 20, 0x050, */ + .long EXTI2_3_IRQHandler /* 05, 21, 0x054, */ + .long EXTI4_15_IRQHandler /* 06, 22, 0x058, */ + .if (USE_HT32_CHIP==HT32F54231_41) + .long _RESERVED /* 07, 23, 0x05C, */ + .endif + .if (USE_HT32_CHIP==HT32F54243_53) + .long COMP_IRQHandler /* 07, 23, 0x05C, */ + .endif + .long ADC_IRQHandler /* 08, 24, 0x060, */ + .if (USE_HT32_CHIP==HT32F54231_41) + .long _RESERVED /* 09, 25, 0x064, */ + .endif + .if (USE_HT32_CHIP==HT32F54243_53) + .long I2C2_IRQHandler /* 09, 25, 0x064, */ + .endif + .long MCTM0_IRQHandler /* 10, 26, 0x068, */ + .long TKEY_IRQHandler /* 11, 27, 0x06C, */ + .long GPTM0_IRQHandler /* 12, 28, 0x070, */ + .long SCTM0_IRQHandler /* 13, 29, 0x074, */ + .long SCTM1_IRQHandler /* 14, 30, 0x078, */ + .if (USE_HT32_CHIP==HT32F54231_41) + .long _RESERVED /* 15, 31, 0x07C, */ + .long _RESERVED /* 16, 32, 0x080, */ + .endif + .if (USE_HT32_CHIP==HT32F54243_53) + .long SCTM2_IRQHandler /* 15, 31, 0x07C, */ + .long SCTM3_IRQHandler /* 16, 32, 0x080, */ + .endif + .long BFTM0_IRQHandler /* 17, 33, 0x084, */ + .long BFTM1_IRQHandler /* 18, 34, 0x088, */ + .long I2C0_IRQHandler /* 19, 35, 0x08C, */ + .long I2C1_IRQHandler /* 20, 36, 0x090, */ + .long SPI0_IRQHandler /* 21, 37, 0x094, */ + .long SPI1_IRQHandler /* 22, 38, 0x098, */ + .long USART0_IRQHandler /* 23, 39, 0x09C, */ + .if (USE_HT32_CHIP==HT32F54231_41) + .long _RESERVED /* 24, 40, 0x0A0, */ + .endif + .if (USE_HT32_CHIP==HT32F54243_53) + .long USART1_IRQHandler /* 24, 40, 0x0A0, */ + .endif + .long UART0_IRQHandler /* 25, 41, 0x0A4, */ + .long UART1_IRQHandler /* 26, 42, 0x0A8, */ + .if (USE_HT32_CHIP==HT32F54231_41) + .long _RESERVED /* 27, 43, 0x0AC, */ + .long _RESERVED /* 28, 44, 0x0B0, */ + .endif + .if (USE_HT32_CHIP==HT32F54243_53) + .long UART2_IRQHandler /* 27, 43, 0x0AC, */ + .long UART3_IRQHandler /* 28, 44, 0x0B0, */ + .endif + .long LEDC_IRQHandler /* 29, 45, 0x0B4, */ + .if (USE_HT32_CHIP==HT32F54243_53) + .long PDMA_CH0_1_IRQHandler /* 30, 46, 0x0B8, */ + .long PDMA_CH2_5_IRQHandler /* 31, 47, 0x0BC, */ + .endif + + .size __interrupt_vector_cortex_m, . - __interrupt_vector_cortex_m + + + .thumb + + +/* Reset Handler */ + + .section .text.Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + LDR R0, =__StackTop /* set stack pointer */ + MOV SP, R0 + LDR R0, =BootProcess + BLX R0 + LDR R0, =SystemInit + BLX R0 + + /* Copy the data segment initializers from flash to SRAM */ + MOVS R1, #0 + B LoopCopyDataInit + +CopyDataInit: + LDR R3, =_sidata + LDR R3, [R3, R1] + STR R3, [R0, R1] + ADDS R1, R1, #4 + +LoopCopyDataInit: + LDR R0, =_sdata + LDR R3, =_edata + ADDS R2, R0, R1 + CMP R2, R3 + BCC CopyDataInit + LDR R2, =_sbss + B LoopFillZerobss + +/* Zero fill the bss segment. */ +FillZerobss: + MOVS R3, #0 + STR R3, [R2] + ADDS R2, R2, #4 + +LoopFillZerobss: + LDR R3, =_ebss + CMP R2, R3 + BCC FillZerobss + + /* Call static constructors */ + BL __libc_init_array + + /* Call the application's entry point.*/ + BL main + +LoopForever: + B LoopForever + + .thumb_func +BootProcess: + LDR R0, =0x40080300 + LDR R1,[R0, #0x10] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x14] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x18] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x1C] + CMP R1, #0 + BEQ BP2 +BP1: + LDR R0, =0x40080180 + LDR R1,[R0, #0xC] + LSLS R1, R1, #4 + LSRS R1, R1, #20 + CMP R1, #0 + BEQ BP3 + CMP R1, #5 + BEQ BP3 + CMP R1, #6 + BEQ BP3 +BP2: + DSB + LDR R0, =0x20000000 + LDR R1, =0x05fa0004 + STR R1, [R0] + LDR R1, =0xe000ed00 + LDR R0, =0x05fa0004 + STR R0, [R1, #0xC] + DSB + B . +BP3: + LDR R0, =0x20000000 + LDR R1, [R0] + LDR R0, =0x05fa0004 + CMP R0, R1 + BEQ BP4 + BX LR +BP4: + LDR R0, =0x40088100 + LDR R1, =0x00000001 + STR R1, [R0] + LDR R0, =0x20000000 + LDR R1, =0x0 + STR R1, [R0] + BX LR + + .size Reset_Handler, .-Reset_Handler + +/* Exception Handlers */ + + .weak NMI_Handler + .type NMI_Handler, %function +NMI_Handler: + B . + .size NMI_Handler, . - NMI_Handler + + .weak HardFault_Handler + .type HardFault_Handler, %function +HardFault_Handler: + B . + .size HardFault_Handler, . - HardFault_Handler + + .weak SVC_Handler + .type SVC_Handler, %function +SVC_Handler: + B . + .size SVC_Handler, . - SVC_Handler + + .weak PendSV_Handler + .type PendSV_Handler, %function +PendSV_Handler: + B . + .size PendSV_Handler, . - PendSV_Handler + + .weak SysTick_Handler + .type SysTick_Handler, %function +SysTick_Handler: + B . + .size SysTick_Handler, . - SysTick_Handler + + +/* IRQ Handlers */ + + .globl Default_Handler + .type Default_Handler, %function +Default_Handler: + B . + .size Default_Handler, . - Default_Handler + + .macro IRQ handler + .weak \handler + .set \handler, Default_Handler + .endm + + IRQ LVD_BOD_IRQHandler + IRQ RTC_IRQHandler + IRQ FLASH_IRQHandler + IRQ EVWUP_IRQHandler + IRQ EXTI0_1_IRQHandler + IRQ EXTI2_3_IRQHandler + IRQ EXTI4_15_IRQHandler + IRQ COMP_IRQHandler + IRQ ADC_IRQHandler + IRQ I2C2_IRQHandler + IRQ MCTM0_IRQHandler + IRQ TKEY_IRQHandler + IRQ GPTM0_IRQHandler + IRQ SCTM0_IRQHandler + IRQ SCTM1_IRQHandler + IRQ SCTM2_IRQHandler + IRQ SCTM3_IRQHandler + IRQ BFTM0_IRQHandler + IRQ BFTM1_IRQHandler + IRQ I2C0_IRQHandler + IRQ I2C1_IRQHandler + IRQ SPI0_IRQHandler + IRQ SPI1_IRQHandler + IRQ USART0_IRQHandler + IRQ USART1_IRQHandler + IRQ UART0_IRQHandler + IRQ UART1_IRQHandler + IRQ UART2_IRQHandler + IRQ UART3_IRQHandler + IRQ LEDC_IRQHandler + IRQ PDMA_CH0_1_IRQHandler + IRQ PDMA_CH2_5_IRQHandler + + .end diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/GCC/startup_ht32f5xxxx_gcc_10.s b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/GCC/startup_ht32f5xxxx_gcc_10.s new file mode 100644 index 0000000000..d6688b4441 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/GCC/startup_ht32f5xxxx_gcc_10.s @@ -0,0 +1,289 @@ +/*---------------------------------------------------------------------------------------------------------*/ +/* Holtek Semiconductor Inc. */ +/* */ +/* Copyright (C) Holtek Semiconductor Inc. */ +/* All rights reserved. */ +/* */ +/*----------------------------------------------------------------------------------------------------------- +; File Name : startup_ht32f5xxxx_gcc_10.s +; Version : $Rev:: 6601 $ +; Date : $Date:: 2022-12-27 #$ +; Description : Startup code. +;-----------------------------------------------------------------------------------------------------------*/ + +/* +; Supported Device +; ======================================== +; HT32F61244, HT32F61245 +*/ + +;/* <<< Use Configuration Wizard in Context Menu >>> */ +/* +;// HT32 Device +;// <0=> By Project Asm Define +;// <24=> HT32F61244/45 +*/ + .equ USE_HT32_CHIP_SET, 0 + + .equ _HT32FWID, 0xFFFFFFFF +/* + .equ _HT32FWID, 0x00061244 + .equ _HT32FWID, 0x00061245 +*/ + + .equ HT32F61244_45, 24 + + .if USE_HT32_CHIP_SET == 0 + .else + .equ USE_HT32_CHIP, USE_HT32_CHIP_SET + .endif + + .syntax unified + .cpu cortex-m0plus + .fpu softvfp + .thumb + +/* start address for the initialization values of the .data section. defined in linker script */ +.word _sidata + +/* start address for the .data section. defined in linker script */ +.word _sdata + +/* end address for the .data section. defined in linker script */ +.word _edata + +/* start address for the .bss section. defined in linker script */ +.word _sbss + +/* end address for the .bss section. defined in linker script */ +.word _ebss + + +/* +; Amount of memory (in bytes) allocated for Stack and Heap +; Tailor those values to your application needs +;// Stack Size (in Bytes, must 8 byte aligned) <:8> +*/ + .equ Stack_Size, 512 + .section ".stack", "w" + .align 3 + .globl __StackTop + .globl __StackLimit + .globl __HT_check_sp +__HT_check_sp: +__StackLimit: + .if Stack_Size + .space Stack_Size + .endif + .size __StackLimit, . - __StackLimit +__StackTop: + .size __StackTop, . - __StackTop + +/* +;// Heap Size (in Bytes) <:8> +*/ + .equ Heap_Size, 0 + .section ".heap", "w" + .align 3 + .globl __HeapBase + .globl _end + .globl __HeapLimit + .globl __HT_check_heap +__HT_check_heap: +__HeapBase: +_end: + .if Heap_Size + .space Heap_Size + .endif + .size __HeapBase, . - __HeapBase +__HeapLimit: + .size __HeapLimit, . - __HeapLimit + + .equ _RESERVED, 0xFFFFFFFF +/* +;******************************************************************************* +; Fill-up the Vector Table entries with the exceptions ISR address +;********************************************************************************/ + .section .isr_vector,"a",%progbits + .global __interrupt_vector_cortex_m + .type __interrupt_vector_cortex_m, %object +__interrupt_vector_cortex_m: + .long __StackTop /* ---, 00, 0x000, Top address of Stack */ + .long Reset_Handler /* ---, 01, 0x004, Reset Handler */ + .long NMI_Handler /* -14, 02, 0x008, NMI Handler */ + .long HardFault_Handler /* -13, 03, 0x00C, Hard Fault Handler */ + .long _RESERVED /* ---, 04, 0x010, Reserved */ + .long _RESERVED /* ---, 05, 0x014, Reserved */ + .long _RESERVED /* ---, 06, 0x018, Reserved */ + .long _RESERVED /* ---, 07, 0x01C, Reserved */ + .long _HT32FWID /* ---, 08, 0x020, Reserved */ + .long _RESERVED /* ---, 09, 0x024, Reserved */ + .long _RESERVED /* ---, 10, 0x028, Reserved */ + .long SVC_Handler /* -05, 11, 0x02C, SVC Handler */ + .long _RESERVED /* ---, 12, 0x030, Reserved */ + .long _RESERVED /* ---, 13, 0x034, Reserved */ + .long PendSV_Handler /* -02, 14, 0x038, PendSV Handler */ + .long SysTick_Handler /* -01, 15, 0x03C, SysTick Handler */ + + /* External Interrupt Handler */ + .long LVD_BOD_IRQHandler /* 00, 16, 0x040, */ + .long RTC_IRQHandler /* 01, 17, 0x044, */ + .long FLASH_IRQHandler /* 02, 18, 0x048, */ + .long EVWUP_IRQHandler /* 03, 19, 0x04C, */ + .long EXTI0_1_IRQHandler /* 04, 20, 0x050, */ + .long EXTI2_3_IRQHandler /* 05, 21, 0x054, */ + .long EXTI4_15_IRQHandler /* 06, 22, 0x058, */ + .long _RESERVED /* 07, 23, 0x05C, */ + .long ADC_IRQHandler /* 08, 24, 0x060, */ + .long _RESERVED /* 09, 25, 0x064, */ + .long _RESERVED /* 10, 26, 0x068, */ + .long _RESERVED /* 11, 27, 0x06C, */ + .long GPTM0_IRQHandler /* 12, 28, 0x070, */ + .long SCTM0_IRQHandler /* 13, 29, 0x074, */ + .long SCTM1_IRQHandler /* 14, 30, 0x078, */ + .long _RESERVED /* 15, 31, 0x07C, */ + .long _RESERVED /* 16, 32, 0x080, */ + .long BFTM0_IRQHandler /* 17, 33, 0x084, */ + .long BFTM1_IRQHandler /* 18, 34, 0x088, */ + .long I2C0_IRQHandler /* 19, 35, 0x08C, */ + .long _RESERVED /* 20, 36, 0x090, */ + .long SPI0_IRQHandler /* 21, 37, 0x094, */ + .long QSPI_IRQHandler /* 22, 38, 0x098, */ + .long _RESERVED /* 23, 39, 0x09C, */ + .long _RESERVED /* 24, 40, 0x0A0, */ + .long UART0_IRQHandler /* 25, 41, 0x0A4, */ + .long _RESERVED /* 26, 42, 0x0A8, */ + .long MIDI_IRQHandler /* 27, 43, 0x0AC, */ + .long _RESERVED /* 28, 44, 0x0B0, */ + .long _RESERVED /* 29, 45, 0x0B4, */ + .long PDMA_CH0_1_IRQHandler /* 30, 46, 0x0B8, */ + .long PDMA_CH2_5_IRQHandler /* 31, 47, 0x0BC, */ + + .size __interrupt_vector_cortex_m, . - __interrupt_vector_cortex_m + + + .thumb + + +/* Reset Handler */ + + .section .text.Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + LDR R0, =__StackTop /* set stack pointer */ + MOV SP, R0 + LDR R0, =SystemInit + BLX R0 + + /* Copy the data segment initializers from flash to SRAM */ + MOVS R1, #0 + B LoopCopyDataInit + +CopyDataInit: + LDR R3, =_sidata + LDR R3, [R3, R1] + STR R3, [R0, R1] + ADDS R1, R1, #4 + +LoopCopyDataInit: + LDR R0, =_sdata + LDR R3, =_edata + ADDS R2, R0, R1 + CMP R2, R3 + BCC CopyDataInit + LDR R2, =_sbss + B LoopFillZerobss + +/* Zero fill the bss segment. */ +FillZerobss: + MOVS R3, #0 + STR R3, [R2] + ADDS R2, R2, #4 + +LoopFillZerobss: + LDR R3, =_ebss + CMP R2, R3 + BCC FillZerobss + + /* Call static constructors */ + BL __libc_init_array + + /* Call the application's entry point.*/ + BL main + +LoopForever: + B LoopForever + + .thumb_func + + .size Reset_Handler, .-Reset_Handler + +/* Exception Handlers */ + + .weak NMI_Handler + .type NMI_Handler, %function +NMI_Handler: + B . + .size NMI_Handler, . - NMI_Handler + + .weak HardFault_Handler + .type HardFault_Handler, %function +HardFault_Handler: + B . + .size HardFault_Handler, . - HardFault_Handler + + .weak SVC_Handler + .type SVC_Handler, %function +SVC_Handler: + B . + .size SVC_Handler, . - SVC_Handler + + .weak PendSV_Handler + .type PendSV_Handler, %function +PendSV_Handler: + B . + .size PendSV_Handler, . - PendSV_Handler + + .weak SysTick_Handler + .type SysTick_Handler, %function +SysTick_Handler: + B . + .size SysTick_Handler, . - SysTick_Handler + + +/* IRQ Handlers */ + + .globl Default_Handler + .type Default_Handler, %function +Default_Handler: + B . + .size Default_Handler, . - Default_Handler + + .macro IRQ handler + .weak \handler + .set \handler, Default_Handler + .endm + + IRQ LVD_BOD_IRQHandler + IRQ RTC_IRQHandler + IRQ FLASH_IRQHandler + IRQ EVWUP_IRQHandler + IRQ EXTI0_1_IRQHandler + IRQ EXTI2_3_IRQHandler + IRQ EXTI4_15_IRQHandler + IRQ ADC_IRQHandler + IRQ GPTM0_IRQHandler + IRQ SCTM0_IRQHandler + IRQ SCTM1_IRQHandler + IRQ BFTM0_IRQHandler + IRQ BFTM1_IRQHandler + IRQ I2C0_IRQHandler + IRQ SPI0_IRQHandler + IRQ QSPI_IRQHandler + IRQ UART0_IRQHandler + IRQ MIDI_IRQHandler + IRQ PDMA_CH0_1_IRQHandler + IRQ PDMA_CH2_5_IRQHandler + + .end diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/GCC/startup_ht32f5xxxx_gcc_11.s b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/GCC/startup_ht32f5xxxx_gcc_11.s new file mode 100644 index 0000000000..f5b5d9585e --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/GCC/startup_ht32f5xxxx_gcc_11.s @@ -0,0 +1,294 @@ +/*---------------------------------------------------------------------------------------------------------*/ +/* Holtek Semiconductor Inc. */ +/* */ +/* Copyright (C) Holtek Semiconductor Inc. */ +/* All rights reserved. */ +/* */ +/*----------------------------------------------------------------------------------------------------------- +; File Name : startup_ht32f5xxxx_gcc_11.s +; Version : $Rev:: 6206 $ +; Date : $Date:: 2022-10-05 #$ +; Description : Startup code. +;-----------------------------------------------------------------------------------------------------------*/ + +/* +; Supported Device +; ======================================== +; HT32F67041, HT32F67051 +*/ + +;/* <<< Use Configuration Wizard in Context Menu >>> */ +/* +;// HT32 Device +;// <0=> By Project Asm Define +;// <22=> HT32F67041/51 +*/ + .equ USE_HT32_CHIP_SET, 0 + + .equ _HT32FWID, 0xFFFFFFFF +/* + .equ _HT32FWID, 0x00067041 + .equ _HT32FWID, 0x00067051 +*/ + + .equ HT32F67041_51, 22 + + .if USE_HT32_CHIP_SET == 0 + .else + .equ USE_HT32_CHIP, USE_HT32_CHIP_SET + .endif + + .syntax unified + .cpu cortex-m0plus + .fpu softvfp + .thumb + +/* start address for the initialization values of the .data section. defined in linker script */ +.word _sidata + +/* start address for the .data section. defined in linker script */ +.word _sdata + +/* end address for the .data section. defined in linker script */ +.word _edata + +/* start address for the .bss section. defined in linker script */ +.word _sbss + +/* end address for the .bss section. defined in linker script */ +.word _ebss + + +/* +; Amount of memory (in bytes) allocated for Stack and Heap +; Tailor those values to your application needs +;// Stack Size (in Bytes, must 8 byte aligned) <:8> +*/ + .equ Stack_Size, 512 + .section ".stack", "w" + .align 3 + .globl __StackTop + .globl __StackLimit + .globl __HT_check_sp +__HT_check_sp: +__StackLimit: + .if Stack_Size + .space Stack_Size + .endif + .size __StackLimit, . - __StackLimit +__StackTop: + .size __StackTop, . - __StackTop + +/* +;// Heap Size (in Bytes) <:8> +*/ + .equ Heap_Size, 0 + .section ".heap", "w" + .align 3 + .globl __HeapBase + .globl _end + .globl __HeapLimit + .globl __HT_check_heap +__HT_check_heap: +__HeapBase: +_end: + .if Heap_Size + .space Heap_Size + .endif + .size __HeapBase, . - __HeapBase +__HeapLimit: + .size __HeapLimit, . - __HeapLimit + + .equ _RESERVED, 0xFFFFFFFF +/* +;******************************************************************************* +; Fill-up the Vector Table entries with the exceptions ISR address +;********************************************************************************/ + .section .isr_vector,"a",%progbits + .global __interrupt_vector_cortex_m + .type __interrupt_vector_cortex_m, %object +__interrupt_vector_cortex_m: + .long __StackTop /* ---, 00, 0x000, Top address of Stack */ + .long Reset_Handler /* ---, 01, 0x004, Reset Handler */ + .long NMI_Handler /* -14, 02, 0x008, NMI Handler */ + .long HardFault_Handler /* -13, 03, 0x00C, Hard Fault Handler */ + .long _RESERVED /* ---, 04, 0x010, Reserved */ + .long _RESERVED /* ---, 05, 0x014, Reserved */ + .long _RESERVED /* ---, 06, 0x018, Reserved */ + .long _RESERVED /* ---, 07, 0x01C, Reserved */ + .long _HT32FWID /* ---, 08, 0x020, Reserved */ + .long _RESERVED /* ---, 09, 0x024, Reserved */ + .long _RESERVED /* ---, 10, 0x028, Reserved */ + .long SVC_Handler /* -05, 11, 0x02C, SVC Handler */ + .long _RESERVED /* ---, 12, 0x030, Reserved */ + .long _RESERVED /* ---, 13, 0x034, Reserved */ + .long PendSV_Handler /* -02, 14, 0x038, PendSV Handler */ + .long SysTick_Handler /* -01, 15, 0x03C, SysTick Handler */ + + /* External Interrupt Handler */ + .long LVD_BOD_IRQHandler /* 00, 16, 0x040, */ + .long RTC_IRQHandler /* 01, 17, 0x044, */ + .long FLASH_IRQHandler /* 02, 18, 0x048, */ + .long EVWUP_IRQHandler /* 03, 19, 0x04C, */ + .long EXTI0_1_IRQHandler /* 04, 20, 0x050, */ + .long EXTI2_3_IRQHandler /* 05, 21, 0x054, */ + .long EXTI4_15_IRQHandler /* 06, 22, 0x058, */ + .long _RESERVED /* 07, 23, 0x05C, */ + .long ADC_IRQHandler /* 08, 24, 0x060, */ + .long AES_IRQHandler /* 09, 25, 0x064, */ + .long _RESERVED /* 10, 26, 0x068, */ + .long RF_IRQHandler /* 11, 27, 0x06C, */ + .long GPTM0_IRQHandler /* 12, 28, 0x070, */ + .long SCTM0_IRQHandler /* 13, 29, 0x074, */ + .long SCTM1_IRQHandler /* 14, 30, 0x078, */ + .long SCTM2_IRQHandler /* 15, 31, 0x07C, */ + .long SCTM3_IRQHandler /* 16, 32, 0x080, */ + .long BFTM0_IRQHandler /* 17, 33, 0x084, */ + .long BFTM1_IRQHandler /* 18, 34, 0x088, */ + .long I2C0_IRQHandler /* 19, 35, 0x08C, */ + .long I2C1_IRQHandler /* 20, 36, 0x090, */ + .long SPI0_IRQHandler /* 21, 37, 0x094, */ + .long SPI1_IRQHandler /* 22, 38, 0x098, */ + .long _RESERVED /* 23, 39, 0x09C, */ + .long _RESERVED /* 24, 40, 0x0A0, */ + .long UART0_IRQHandler /* 25, 41, 0x0A4, */ + .long UART1_IRQHandler /* 26, 42, 0x0A8, */ + .long _RESERVED /* 27, 43, 0x0AC, */ + .long _RESERVED /* 28, 44, 0x0B0, */ + .long _RESERVED /* 29, 45, 0x0B4, */ + .long PDMA_CH0_1_IRQHandler /* 30, 46, 0x0B8, */ + .long PDMA_CH2_5_IRQHandler /* 31, 47, 0x0BC, */ + + .size __interrupt_vector_cortex_m, . - __interrupt_vector_cortex_m + + + .thumb + + +/* Reset Handler */ + + .section .text.Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + LDR R0, =__StackTop /* set stack pointer */ + MOV SP, R0 + LDR R0, =SystemInit + BLX R0 + + /* Copy the data segment initializers from flash to SRAM */ + MOVS R1, #0 + B LoopCopyDataInit + +CopyDataInit: + LDR R3, =_sidata + LDR R3, [R3, R1] + STR R3, [R0, R1] + ADDS R1, R1, #4 + +LoopCopyDataInit: + LDR R0, =_sdata + LDR R3, =_edata + ADDS R2, R0, R1 + CMP R2, R3 + BCC CopyDataInit + LDR R2, =_sbss + B LoopFillZerobss + +/* Zero fill the bss segment. */ +FillZerobss: + MOVS R3, #0 + STR R3, [R2] + ADDS R2, R2, #4 + +LoopFillZerobss: + LDR R3, =_ebss + CMP R2, R3 + BCC FillZerobss + + /* Call static constructors */ + BL __libc_init_array + + /* Call the application's entry point.*/ + BL main + +LoopForever: + B LoopForever + + .thumb_func + + .size Reset_Handler, .-Reset_Handler + +/* Exception Handlers */ + + .weak NMI_Handler + .type NMI_Handler, %function +NMI_Handler: + B . + .size NMI_Handler, . - NMI_Handler + + .weak HardFault_Handler + .type HardFault_Handler, %function +HardFault_Handler: + B . + .size HardFault_Handler, . - HardFault_Handler + + .weak SVC_Handler + .type SVC_Handler, %function +SVC_Handler: + B . + .size SVC_Handler, . - SVC_Handler + + .weak PendSV_Handler + .type PendSV_Handler, %function +PendSV_Handler: + B . + .size PendSV_Handler, . - PendSV_Handler + + .weak SysTick_Handler + .type SysTick_Handler, %function +SysTick_Handler: + B . + .size SysTick_Handler, . - SysTick_Handler + + +/* IRQ Handlers */ + + .globl Default_Handler + .type Default_Handler, %function +Default_Handler: + B . + .size Default_Handler, . - Default_Handler + + .macro IRQ handler + .weak \handler + .set \handler, Default_Handler + .endm + + IRQ LVD_BOD_IRQHandler + IRQ RTC_IRQHandler + IRQ FLASH_IRQHandler + IRQ EVWUP_IRQHandler + IRQ EXTI0_1_IRQHandler + IRQ EXTI2_3_IRQHandler + IRQ EXTI4_15_IRQHandler + IRQ ADC_IRQHandler + IRQ AES_IRQHandler + IRQ RF_IRQHandler + IRQ GPTM0_IRQHandler + IRQ SCTM0_IRQHandler + IRQ SCTM1_IRQHandler + IRQ SCTM2_IRQHandler + IRQ SCTM3_IRQHandler + IRQ BFTM0_IRQHandler + IRQ BFTM1_IRQHandler + IRQ I2C0_IRQHandler + IRQ I2C1_IRQHandler + IRQ SPI0_IRQHandler + IRQ SPI1_IRQHandler + IRQ UART0_IRQHandler + IRQ UART1_IRQHandler + IRQ PDMA_CH0_1_IRQHandler + IRQ PDMA_CH2_5_IRQHandler + + .end diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/GCC/startup_ht32f5xxxx_gcc_12.s b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/GCC/startup_ht32f5xxxx_gcc_12.s new file mode 100644 index 0000000000..91be324717 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/GCC/startup_ht32f5xxxx_gcc_12.s @@ -0,0 +1,336 @@ +/*---------------------------------------------------------------------------------------------------------*/ +/* Holtek Semiconductor Inc. */ +/* */ +/* Copyright (C) Holtek Semiconductor Inc. */ +/* All rights reserved. */ +/* */ +/*----------------------------------------------------------------------------------------------------------- +; File Name : startup_ht32f5xxxx_gcc_12.s +; Version : $Rev:: 5572 $ +; Date : $Date:: 2021-08-18 #$ +; Description : Startup code. +;-----------------------------------------------------------------------------------------------------------*/ + +/* +; Supported Device +; ======================================== +; HT32F61141 +*/ + +;/* <<< Use Configuration Wizard in Context Menu >>> */ +/* +;// HT32 Device +;// <0=> By Project Asm Define +;// <23=> HT32F61141 +*/ + .equ USE_HT32_CHIP_SET, 0 + + .equ _HT32FWID, 0xFFFFFFFF +/* + .equ _HT32FWID, 0x00061141 +*/ + + .equ HT32F61141, 23 + + .if USE_HT32_CHIP_SET == 0 + .else + .equ USE_HT32_CHIP, USE_HT32_CHIP_SET + .endif + + .syntax unified + .cpu cortex-m0plus + .fpu softvfp + .thumb + +/* start address for the initialization values of the .data section. defined in linker script */ +.word _sidata + +/* start address for the .data section. defined in linker script */ +.word _sdata + +/* end address for the .data section. defined in linker script */ +.word _edata + +/* start address for the .bss section. defined in linker script */ +.word _sbss + +/* end address for the .bss section. defined in linker script */ +.word _ebss + + +/* +; Amount of memory (in bytes) allocated for Stack and Heap +; Tailor those values to your application needs +;// Stack Size (in Bytes, must 8 byte aligned) <:8> +*/ + .equ Stack_Size, 512 + .section ".stack", "w" + .align 3 + .globl __StackTop + .globl __StackLimit + .globl __HT_check_sp +__HT_check_sp: +__StackLimit: + .if Stack_Size + .space Stack_Size + .endif + .size __StackLimit, . - __StackLimit +__StackTop: + .size __StackTop, . - __StackTop + +/* +;// Heap Size (in Bytes) <:8> +*/ + .equ Heap_Size, 0 + .section ".heap", "w" + .align 3 + .globl __HeapBase + .globl _end + .globl __HeapLimit + .globl __HT_check_heap +__HT_check_heap: +__HeapBase: +_end: + .if Heap_Size + .space Heap_Size + .endif + .size __HeapBase, . - __HeapBase +__HeapLimit: + .size __HeapLimit, . - __HeapLimit + + .equ _RESERVED, 0xFFFFFFFF +/* +;******************************************************************************* +; Fill-up the Vector Table entries with the exceptions ISR address +;********************************************************************************/ + .section .isr_vector,"a",%progbits + .global __interrupt_vector_cortex_m + .type __interrupt_vector_cortex_m, %object +__interrupt_vector_cortex_m: + .long __StackTop /* ---, 00, 0x000, Top address of Stack */ + .long Reset_Handler /* ---, 01, 0x004, Reset Handler */ + .long NMI_Handler /* -14, 02, 0x008, NMI Handler */ + .long HardFault_Handler /* -13, 03, 0x00C, Hard Fault Handler */ + .long _RESERVED /* ---, 04, 0x010, Reserved */ + .long _RESERVED /* ---, 05, 0x014, Reserved */ + .long _RESERVED /* ---, 06, 0x018, Reserved */ + .long _RESERVED /* ---, 07, 0x01C, Reserved */ + .long _HT32FWID /* ---, 08, 0x020, Reserved */ + .long _RESERVED /* ---, 09, 0x024, Reserved */ + .long _RESERVED /* ---, 10, 0x028, Reserved */ + .long SVC_Handler /* -05, 11, 0x02C, SVC Handler */ + .long _RESERVED /* ---, 12, 0x030, Reserved */ + .long _RESERVED /* ---, 13, 0x034, Reserved */ + .long PendSV_Handler /* -02, 14, 0x038, PendSV Handler */ + .long SysTick_Handler /* -01, 15, 0x03C, SysTick Handler */ + + /* External Interrupt Handler */ + .long LVD_BOD_IRQHandler /* 00, 16, 0x040, */ + .long RTC_IRQHandler /* 01, 17, 0x044, */ + .long FLASH_IRQHandler /* 02, 18, 0x048, */ + .long EVWUP_IRQHandler /* 03, 19, 0x04C, */ + .long EXTI0_1_IRQHandler /* 04, 20, 0x050, */ + .long EXTI2_3_IRQHandler /* 05, 21, 0x054, */ + .long EXTI4_15_IRQHandler /* 06, 22, 0x058, */ + .long _RESERVED /* 07, 23, 0x05C, */ + .long _RESERVED /* 08, 24, 0x060, */ + .long _RESERVED /* 09, 25, 0x064, */ + .long _RESERVED /* 10, 26, 0x068, */ + .long _RESERVED /* 11, 27, 0x06C, */ + .long GPTM0_IRQHandler /* 12, 28, 0x070, */ + .long SCTM0_IRQHandler /* 13, 29, 0x074, */ + .long SCTM1_IRQHandler /* 14, 30, 0x078, */ + .long _RESERVED /* 15, 31, 0x07C, */ + .long _RESERVED /* 16, 32, 0x080, */ + .long BFTM0_IRQHandler /* 17, 33, 0x084, */ + .long BFTM1_IRQHandler /* 18, 34, 0x088, */ + .long I2C0_IRQHandler /* 19, 35, 0x08C, */ + .long _RESERVED /* 20, 36, 0x090, */ + .long SPI0_IRQHandler /* 21, 37, 0x094, */ + .long _RESERVED /* 22, 38, 0x098, */ + .long _RESERVED /* 23, 39, 0x09C, */ + .long _RESERVED /* 24, 40, 0x0A0, */ + .long UART0_IRQHandler /* 25, 41, 0x0A4, */ + .long UART1_IRQHandler /* 26, 42, 0x0A8, */ + .long SCI_IRQHandler /* 27, 43, 0x0AC, */ + .long _RESERVED /* 28, 44, 0x0B0, */ + .long USB_IRQHandler /* 29, 45, 0x0B4, */ + + .size __interrupt_vector_cortex_m, . - __interrupt_vector_cortex_m + + + .thumb + + +/* Reset Handler */ + + .section .text.Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + LDR R0, =__StackTop /* set stack pointer */ + MOV SP, R0 + LDR R0, =BootProcess + BLX R0 + LDR R0, =SystemInit + BLX R0 + + /* Copy the data segment initializers from flash to SRAM */ + MOVS R1, #0 + B LoopCopyDataInit + +CopyDataInit: + LDR R3, =_sidata + LDR R3, [R3, R1] + STR R3, [R0, R1] + ADDS R1, R1, #4 + +LoopCopyDataInit: + LDR R0, =_sdata + LDR R3, =_edata + ADDS R2, R0, R1 + CMP R2, R3 + BCC CopyDataInit + LDR R2, =_sbss + B LoopFillZerobss + +/* Zero fill the bss segment. */ +FillZerobss: + MOVS R3, #0 + STR R3, [R2] + ADDS R2, R2, #4 + +LoopFillZerobss: + LDR R3, =_ebss + CMP R2, R3 + BCC FillZerobss + + /* Call static constructors */ + BL __libc_init_array + + /* Call the application's entry point.*/ + BL main + +LoopForever: + B LoopForever + + .thumb_func +BootProcess: + LDR R0, =0x40080300 + LDR R1,[R0, #0x10] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x14] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x18] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x1C] + CMP R1, #0 + BEQ BP2 +BP1: + LDR R0, =0x40080180 + LDR R1,[R0, #0xC] + LSLS R1, R1, #4 + LSRS R1, R1, #20 + CMP R1, #0 + BEQ BP3 + CMP R1, #5 + BEQ BP3 + CMP R1, #6 + BEQ BP3 +BP2: + DSB + LDR R0, =0x20000000 + LDR R1, =0x05fa0004 + STR R1, [R0] + LDR R1, =0xe000ed00 + LDR R0, =0x05fa0004 + STR R0, [R1, #0xC] + DSB + B . +BP3: + LDR R0, =0x20000000 + LDR R1, [R0] + LDR R0, =0x05fa0004 + CMP R0, R1 + BEQ BP4 + BX LR +BP4: + LDR R0, =0x40088100 + LDR R1, =0x00000001 + STR R1, [R0] + LDR R0, =0x20000000 + LDR R1, =0x0 + STR R1, [R0] + BX LR + + .size Reset_Handler, .-Reset_Handler + +/* Exception Handlers */ + + .weak NMI_Handler + .type NMI_Handler, %function +NMI_Handler: + B . + .size NMI_Handler, . - NMI_Handler + + .weak HardFault_Handler + .type HardFault_Handler, %function +HardFault_Handler: + B . + .size HardFault_Handler, . - HardFault_Handler + + .weak SVC_Handler + .type SVC_Handler, %function +SVC_Handler: + B . + .size SVC_Handler, . - SVC_Handler + + .weak PendSV_Handler + .type PendSV_Handler, %function +PendSV_Handler: + B . + .size PendSV_Handler, . - PendSV_Handler + + .weak SysTick_Handler + .type SysTick_Handler, %function +SysTick_Handler: + B . + .size SysTick_Handler, . - SysTick_Handler + + +/* IRQ Handlers */ + + .globl Default_Handler + .type Default_Handler, %function +Default_Handler: + B . + .size Default_Handler, . - Default_Handler + + .macro IRQ handler + .weak \handler + .set \handler, Default_Handler + .endm + + IRQ LVD_BOD_IRQHandler + IRQ RTC_IRQHandler + IRQ FLASH_IRQHandler + IRQ EVWUP_IRQHandler + IRQ EXTI0_1_IRQHandler + IRQ EXTI2_3_IRQHandler + IRQ EXTI4_15_IRQHandler + IRQ GPTM0_IRQHandler + IRQ SCTM0_IRQHandler + IRQ SCTM1_IRQHandler + IRQ BFTM0_IRQHandler + IRQ BFTM1_IRQHandler + IRQ I2C0_IRQHandler + IRQ SPI0_IRQHandler + IRQ UART0_IRQHandler + IRQ UART1_IRQHandler + IRQ SCI_IRQHandler + IRQ USB_IRQHandler + + .end diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/GCC/startup_ht32f5xxxx_gcc_13.s b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/GCC/startup_ht32f5xxxx_gcc_13.s new file mode 100644 index 0000000000..1d5b8a33b1 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/GCC/startup_ht32f5xxxx_gcc_13.s @@ -0,0 +1,292 @@ +/*---------------------------------------------------------------------------------------------------------*/ +/* Holtek Semiconductor Inc. */ +/* */ +/* Copyright (C) Holtek Semiconductor Inc. */ +/* All rights reserved. */ +/* */ +/*----------------------------------------------------------------------------------------------------------- +; File Name : startup_ht32f5xxxx_gcc_13.s +; Version : $Rev:: 7119 $ +; Date : $Date:: 2023-08-15 #$ +; Description : Startup code. +;-----------------------------------------------------------------------------------------------------------*/ + +/* +; Supported Device +; ======================================== +; HT32F50020, HT32F50030 +; HT32F61630 +; HT32F61030 +*/ + +;/* <<< Use Configuration Wizard in Context Menu >>> */ +/* +;// HT32 Device +;// <0=> By Project Asm Define +;// <25=> HT32F50020/30 +;// <25=> HT32F61630 +;// <25=> HT32F61030 +*/ + .equ USE_HT32_CHIP_SET, 0 + + .equ _HT32FWID, 0xFFFFFFFF +/* + .equ _HT32FWID, 0x00050020 + .equ _HT32FWID, 0x00050030 + .equ _HT32FWID, 0x00061630 + .equ _HT32FWID, 0x00061030 +*/ + + .equ HT32F50020_30, 25 + .equ HT32F61630, 25 + .equ HT32F61030, 25 + + .if USE_HT32_CHIP_SET == 0 + .else + .equ USE_HT32_CHIP, USE_HT32_CHIP_SET + .endif + + .syntax unified + .cpu cortex-m0plus + .fpu softvfp + .thumb + +/* start address for the initialization values of the .data section. defined in linker script */ +.word _sidata + +/* start address for the .data section. defined in linker script */ +.word _sdata + +/* end address for the .data section. defined in linker script */ +.word _edata + +/* start address for the .bss section. defined in linker script */ +.word _sbss + +/* end address for the .bss section. defined in linker script */ +.word _ebss + + +/* +; Amount of memory (in bytes) allocated for Stack and Heap +; Tailor those values to your application needs +;// Stack Size (in Bytes, must 8 byte aligned) <:8> +*/ + .equ Stack_Size, 512 + .section ".stack", "w" + .align 3 + .globl __StackTop + .globl __StackLimit + .globl __HT_check_sp +__HT_check_sp: +__StackLimit: + .if Stack_Size + .space Stack_Size + .endif + .size __StackLimit, . - __StackLimit +__StackTop: + .size __StackTop, . - __StackTop + +/* +;// Heap Size (in Bytes) <:8> +*/ + .equ Heap_Size, 0 + .section ".heap", "w" + .align 3 + .globl __HeapBase + .globl _end + .globl __HeapLimit + .globl __HT_check_heap +__HT_check_heap: +__HeapBase: +_end: + .if Heap_Size + .space Heap_Size + .endif + .size __HeapBase, . - __HeapBase +__HeapLimit: + .size __HeapLimit, . - __HeapLimit + + .equ _RESERVED, 0xFFFFFFFF +/* +;******************************************************************************* +; Fill-up the Vector Table entries with the exceptions ISR address +;********************************************************************************/ + .section .isr_vector,"a",%progbits + .global __interrupt_vector_cortex_m + .type __interrupt_vector_cortex_m, %object +__interrupt_vector_cortex_m: + .long __StackTop /* ---, 00, 0x000, Top address of Stack */ + .long Reset_Handler /* ---, 01, 0x004, Reset Handler */ + .long NMI_Handler /* -14, 02, 0x008, NMI Handler */ + .long HardFault_Handler /* -13, 03, 0x00C, Hard Fault Handler */ + .long _RESERVED /* ---, 04, 0x010, Reserved */ + .long _RESERVED /* ---, 05, 0x014, Reserved */ + .long _RESERVED /* ---, 06, 0x018, Reserved */ + .long _RESERVED /* ---, 07, 0x01C, Reserved */ + .long _HT32FWID /* ---, 08, 0x020, Reserved */ + .long _RESERVED /* ---, 09, 0x024, Reserved */ + .long _RESERVED /* ---, 10, 0x028, Reserved */ + .long SVC_Handler /* -05, 11, 0x02C, SVC Handler */ + .long _RESERVED /* ---, 12, 0x030, Reserved */ + .long _RESERVED /* ---, 13, 0x034, Reserved */ + .long PendSV_Handler /* -02, 14, 0x038, PendSV Handler */ + .long SysTick_Handler /* -01, 15, 0x03C, SysTick Handler */ + + /* External Interrupt Handler */ + .long LVD_BOD_IRQHandler /* 00, 16, 0x040, */ + .long RTC_IRQHandler /* 01, 17, 0x044, */ + .long FLASH_IRQHandler /* 02, 18, 0x048, */ + .long EVWUP_IRQHandler /* 03, 19, 0x04C, */ + .long EXTI0_1_IRQHandler /* 04, 20, 0x050, */ + .long EXTI2_3_IRQHandler /* 05, 21, 0x054, */ + .long EXTI4_7_IRQHandler /* 06, 22, 0x058, */ + .long _RESERVED /* 07, 23, 0x05C, */ + .long ADC_IRQHandler /* 08, 24, 0x060, */ + .long _RESERVED /* 09, 25, 0x064, */ + .long _RESERVED /* 10, 26, 0x068, */ + .long _RESERVED /* 11, 27, 0x06C, */ + .long _RESERVED /* 12, 28, 0x070, */ + .long SCTM0_IRQHandler /* 13, 29, 0x074, */ + .long SCTM1_IRQHandler /* 14, 30, 0x078, */ + .long SCTM2_IRQHandler /* 15, 31, 0x07C, */ + .long _RESERVED /* 16, 32, 0x080, */ + .long BFTM0_IRQHandler /* 17, 33, 0x084, */ + .long _RESERVED /* 18, 34, 0x088, */ + .long I2C0_IRQHandler /* 19, 35, 0x08C, */ + .long _RESERVED /* 20, 36, 0x090, */ + .long SPI0_IRQHandler /* 21, 37, 0x094, */ + .long _RESERVED /* 22, 38, 0x098, */ + .long _RESERVED /* 23, 39, 0x09C, */ + .long _RESERVED /* 24, 40, 0x0A0, */ + .long UART0_IRQHandler /* 25, 41, 0x0A4, */ + .long UART1_IRQHandler /* 26, 42, 0x0A8, */ + .long _RESERVED /* 27, 43, 0x0AC, */ + .long _RESERVED /* 28, 44, 0x0B0, */ + .long LEDC_IRQHandler /* 29, 45, 0x0B4, */ + + .size __interrupt_vector_cortex_m, . - __interrupt_vector_cortex_m + + + .thumb + + +/* Reset Handler */ + + .section .text.Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + LDR R0, =__StackTop /* set stack pointer */ + MOV SP, R0 + LDR R0, =SystemInit + BLX R0 + + /* Copy the data segment initializers from flash to SRAM */ + MOVS R1, #0 + B LoopCopyDataInit + +CopyDataInit: + LDR R3, =_sidata + LDR R3, [R3, R1] + STR R3, [R0, R1] + ADDS R1, R1, #4 + +LoopCopyDataInit: + LDR R0, =_sdata + LDR R3, =_edata + ADDS R2, R0, R1 + CMP R2, R3 + BCC CopyDataInit + LDR R2, =_sbss + B LoopFillZerobss + +/* Zero fill the bss segment. */ +FillZerobss: + MOVS R3, #0 + STR R3, [R2] + ADDS R2, R2, #4 + +LoopFillZerobss: + LDR R3, =_ebss + CMP R2, R3 + BCC FillZerobss + + /* Call static constructors */ + BL __libc_init_array + + /* Call the application's entry point.*/ + BL main + +LoopForever: + B LoopForever + + .thumb_func + + .size Reset_Handler, .-Reset_Handler + +/* Exception Handlers */ + + .weak NMI_Handler + .type NMI_Handler, %function +NMI_Handler: + B . + .size NMI_Handler, . - NMI_Handler + + .weak HardFault_Handler + .type HardFault_Handler, %function +HardFault_Handler: + B . + .size HardFault_Handler, . - HardFault_Handler + + .weak SVC_Handler + .type SVC_Handler, %function +SVC_Handler: + B . + .size SVC_Handler, . - SVC_Handler + + .weak PendSV_Handler + .type PendSV_Handler, %function +PendSV_Handler: + B . + .size PendSV_Handler, . - PendSV_Handler + + .weak SysTick_Handler + .type SysTick_Handler, %function +SysTick_Handler: + B . + .size SysTick_Handler, . - SysTick_Handler + + +/* IRQ Handlers */ + + .globl Default_Handler + .type Default_Handler, %function +Default_Handler: + B . + .size Default_Handler, . - Default_Handler + + .macro IRQ handler + .weak \handler + .set \handler, Default_Handler + .endm + + IRQ LVD_BOD_IRQHandler + IRQ RTC_IRQHandler + IRQ FLASH_IRQHandler + IRQ EVWUP_IRQHandler + IRQ EXTI0_1_IRQHandler + IRQ EXTI2_3_IRQHandler + IRQ EXTI4_7_IRQHandler + IRQ ADC_IRQHandler + IRQ SCTM0_IRQHandler + IRQ SCTM1_IRQHandler + IRQ SCTM2_IRQHandler + IRQ BFTM0_IRQHandler + IRQ I2C0_IRQHandler + IRQ SPI0_IRQHandler + IRQ UART0_IRQHandler + IRQ UART1_IRQHandler + IRQ LEDC_IRQHandler + + .end diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/GCC/startup_ht32f5xxxx_gcc_14.s b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/GCC/startup_ht32f5xxxx_gcc_14.s new file mode 100644 index 0000000000..9a02b727d9 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/GCC/startup_ht32f5xxxx_gcc_14.s @@ -0,0 +1,312 @@ +/*---------------------------------------------------------------------------------------------------------*/ +/* Holtek Semiconductor Inc. */ +/* */ +/* Copyright (C) Holtek Semiconductor Inc. */ +/* All rights reserved. */ +/* */ +/*----------------------------------------------------------------------------------------------------------- +; File Name : startup_ht32f5xxxx_gcc_14.s +; Version : $Rev:: 6838 $ +; Date : $Date:: 2023-04-06 #$ +; Description : Startup code. +;-----------------------------------------------------------------------------------------------------------*/ + +/* +; Supported Device +; ======================================== +; HT32F50442, HT32F50452 +; HT32F50431, HT32F50441 +*/ + +;/* <<< Use Configuration Wizard in Context Menu >>> */ +/* +;// HT32 Device +;// <0=> By Project Asm Define +;// <26=> HT32F50442/52 +;// <30=> HT32F50431/41 +*/ + .equ USE_HT32_CHIP_SET, 0 + + .equ _HT32FWID, 0xFFFFFFFF +/* + .equ _HT32FWID, 0x00050442 + .equ _HT32FWID, 0x00050452 + .equ _HT32FWID, 0x00050431 + .equ _HT32FWID, 0x00050441 +*/ + + .equ HT32F50442_52, 26 + .equ HT32F50431_41, 30 + + .if USE_HT32_CHIP_SET == 0 + .else + .equ USE_HT32_CHIP, USE_HT32_CHIP_SET + .endif + + .syntax unified + .cpu cortex-m0plus + .fpu softvfp + .thumb + +/* start address for the initialization values of the .data section. defined in linker script */ +.word _sidata + +/* start address for the .data section. defined in linker script */ +.word _sdata + +/* end address for the .data section. defined in linker script */ +.word _edata + +/* start address for the .bss section. defined in linker script */ +.word _sbss + +/* end address for the .bss section. defined in linker script */ +.word _ebss + + +/* +; Amount of memory (in bytes) allocated for Stack and Heap +; Tailor those values to your application needs +;// Stack Size (in Bytes, must 8 byte aligned) <:8> +*/ + .equ Stack_Size, 512 + .section ".stack", "w" + .align 3 + .globl __StackTop + .globl __StackLimit + .globl __HT_check_sp +__HT_check_sp: +__StackLimit: + .if Stack_Size + .space Stack_Size + .endif + .size __StackLimit, . - __StackLimit +__StackTop: + .size __StackTop, . - __StackTop + +/* +;// Heap Size (in Bytes) <:8> +*/ + .equ Heap_Size, 0 + .section ".heap", "w" + .align 3 + .globl __HeapBase + .globl _end + .globl __HeapLimit + .globl __HT_check_heap +__HT_check_heap: +__HeapBase: +_end: + .if Heap_Size + .space Heap_Size + .endif + .size __HeapBase, . - __HeapBase +__HeapLimit: + .size __HeapLimit, . - __HeapLimit + + .equ _RESERVED, 0xFFFFFFFF +/* +;******************************************************************************* +; Fill-up the Vector Table entries with the exceptions ISR address +;********************************************************************************/ + .section .isr_vector,"a",%progbits + .global __interrupt_vector_cortex_m + .type __interrupt_vector_cortex_m, %object +__interrupt_vector_cortex_m: + .long __StackTop /* ---, 00, 0x000, Top address of Stack */ + .long Reset_Handler /* ---, 01, 0x004, Reset Handler */ + .long NMI_Handler /* -14, 02, 0x008, NMI Handler */ + .long HardFault_Handler /* -13, 03, 0x00C, Hard Fault Handler */ + .long _RESERVED /* ---, 04, 0x010, Reserved */ + .long _RESERVED /* ---, 05, 0x014, Reserved */ + .long _RESERVED /* ---, 06, 0x018, Reserved */ + .long _RESERVED /* ---, 07, 0x01C, Reserved */ + .long _HT32FWID /* ---, 08, 0x020, Reserved */ + .long _RESERVED /* ---, 09, 0x024, Reserved */ + .long _RESERVED /* ---, 10, 0x028, Reserved */ + .long SVC_Handler /* -05, 11, 0x02C, SVC Handler */ + .long _RESERVED /* ---, 12, 0x030, Reserved */ + .long _RESERVED /* ---, 13, 0x034, Reserved */ + .long PendSV_Handler /* -02, 14, 0x038, PendSV Handler */ + .long SysTick_Handler /* -01, 15, 0x03C, SysTick Handler */ + + /* External Interrupt Handler */ + .long LVD_BOD_IRQHandler /* 00, 16, 0x040, */ + .long RTC_IRQHandler /* 01, 17, 0x044, */ + .long FLASH_IRQHandler /* 02, 18, 0x048, */ + .long EVWUP_IRQHandler /* 03, 19, 0x04C, */ + .long EXTI0_1_IRQHandler /* 04, 20, 0x050, */ + .long EXTI2_3_IRQHandler /* 05, 21, 0x054, */ + .long EXTI4_15_IRQHandler /* 06, 22, 0x058, */ + .if (USE_HT32_CHIP==HT32F50442_52) + .long COMP_IRQHandler /* 07, 23, 0x05C, */ + .else + .long _RESERVED /* 07, 23, 0x05C, */ + .endif + .long ADC_IRQHandler /* 08, 24, 0x060, */ + .long _RESERVED /* 09, 25, 0x064, */ + .long MCTM0_IRQHandler /* 10, 26, 0x068, */ + .long _RESERVED /* 11, 27, 0x06C, */ + .long GPTM0_IRQHandler /* 12, 28, 0x070, */ + .long _RESERVED /* 13, 29, 0x074, */ + .long _RESERVED /* 14, 30, 0x078, */ + .long PWM0_IRQHandler /* 15, 31, 0x07C, */ + .if (USE_HT32_CHIP==HT32F50442_52) + .long PWM1_IRQHandler /* 16, 32, 0x080, */ + .else + .long _RESERVED /* 16, 32, 0x080, */ + .endif + .long BFTM0_IRQHandler /* 17, 33, 0x084, */ + .long BFTM1_IRQHandler /* 18, 34, 0x088, */ + .long I2C0_IRQHandler /* 19, 35, 0x08C, */ + .long I2C1_IRQHandler /* 20, 36, 0x090, */ + .long SPI0_IRQHandler /* 21, 37, 0x094, */ + .long SPI1_IRQHandler /* 22, 38, 0x098, */ + .long USART0_IRQHandler /* 23, 39, 0x09C, */ + .if (USE_HT32_CHIP==HT32F50442_52) + .long USART1_IRQHandler /* 24, 40, 0x0A0, */ + .else + .long _RESERVED /* 24, 40, 0x0A0, */ + .endif + .long UART0_IRQHandler /* 25, 41, 0x0A4, */ + .long UART1_IRQHandler /* 26, 42, 0x0A8, */ + .long _RESERVED /* 27, 43, 0x0AC, */ + .long _RESERVED /* 28, 44, 0x0B0, */ + .long LEDC_IRQHandler /* 29, 45, 0x0B4, */ + .long PDMA_CH0_1_IRQHandler /* 30, 46, 0x0B8, */ + .long PDMA_CH2_5_IRQHandler /* 31, 47, 0x0BC, */ + + .size __interrupt_vector_cortex_m, . - __interrupt_vector_cortex_m + + + .thumb + + +/* Reset Handler */ + + .section .text.Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + LDR R0, =__StackTop /* set stack pointer */ + MOV SP, R0 + LDR R0, =SystemInit + BLX R0 + + /* Copy the data segment initializers from flash to SRAM */ + MOVS R1, #0 + B LoopCopyDataInit + +CopyDataInit: + LDR R3, =_sidata + LDR R3, [R3, R1] + STR R3, [R0, R1] + ADDS R1, R1, #4 + +LoopCopyDataInit: + LDR R0, =_sdata + LDR R3, =_edata + ADDS R2, R0, R1 + CMP R2, R3 + BCC CopyDataInit + LDR R2, =_sbss + B LoopFillZerobss + +/* Zero fill the bss segment. */ +FillZerobss: + MOVS R3, #0 + STR R3, [R2] + ADDS R2, R2, #4 + +LoopFillZerobss: + LDR R3, =_ebss + CMP R2, R3 + BCC FillZerobss + + /* Call static constructors */ + BL __libc_init_array + + /* Call the application's entry point.*/ + BL main + +LoopForever: + B LoopForever + + .thumb_func + + .size Reset_Handler, .-Reset_Handler + +/* Exception Handlers */ + + .weak NMI_Handler + .type NMI_Handler, %function +NMI_Handler: + B . + .size NMI_Handler, . - NMI_Handler + + .weak HardFault_Handler + .type HardFault_Handler, %function +HardFault_Handler: + B . + .size HardFault_Handler, . - HardFault_Handler + + .weak SVC_Handler + .type SVC_Handler, %function +SVC_Handler: + B . + .size SVC_Handler, . - SVC_Handler + + .weak PendSV_Handler + .type PendSV_Handler, %function +PendSV_Handler: + B . + .size PendSV_Handler, . - PendSV_Handler + + .weak SysTick_Handler + .type SysTick_Handler, %function +SysTick_Handler: + B . + .size SysTick_Handler, . - SysTick_Handler + + +/* IRQ Handlers */ + + .globl Default_Handler + .type Default_Handler, %function +Default_Handler: + B . + .size Default_Handler, . - Default_Handler + + .macro IRQ handler + .weak \handler + .set \handler, Default_Handler + .endm + + IRQ LVD_BOD_IRQHandler + IRQ RTC_IRQHandler + IRQ FLASH_IRQHandler + IRQ EVWUP_IRQHandler + IRQ EXTI0_1_IRQHandler + IRQ EXTI2_3_IRQHandler + IRQ EXTI4_15_IRQHandler + IRQ COMP_IRQHandler + IRQ ADC_IRQHandler + IRQ MCTM0_IRQHandler + IRQ GPTM0_IRQHandler + IRQ PWM0_IRQHandler + IRQ PWM1_IRQHandler + IRQ BFTM0_IRQHandler + IRQ BFTM1_IRQHandler + IRQ I2C0_IRQHandler + IRQ I2C1_IRQHandler + IRQ SPI0_IRQHandler + IRQ SPI1_IRQHandler + IRQ USART0_IRQHandler + IRQ USART1_IRQHandler + IRQ UART0_IRQHandler + IRQ UART1_IRQHandler + IRQ LEDC_IRQHandler + IRQ PDMA_CH0_1_IRQHandler + IRQ PDMA_CH2_5_IRQHandler + + .end diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/GCC/startup_ht32f5xxxx_gcc_15.s b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/GCC/startup_ht32f5xxxx_gcc_15.s new file mode 100644 index 0000000000..685f83659e --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/GCC/startup_ht32f5xxxx_gcc_15.s @@ -0,0 +1,313 @@ +/*---------------------------------------------------------------------------------------------------------*/ +/* Holtek Semiconductor Inc. */ +/* */ +/* Copyright (C) Holtek Semiconductor Inc. */ +/* All rights reserved. */ +/* */ +/*----------------------------------------------------------------------------------------------------------- +; File Name : startup_ht32f5xxxx_gcc_15.s +; Version : $Rev:: 6902 $ +; Date : $Date:: 2023-05-08 #$ +; Description : Startup code. +;-----------------------------------------------------------------------------------------------------------*/ + +/* +; Supported Device +; ======================================== +; HT32F53242, HT32F53252 +; HT32F53231, HT32F53241 +*/ + +;/* <<< Use Configuration Wizard in Context Menu >>> */ +/* +;// HT32 Device +;// <0=> By Project Asm Define +;// <28=> HT32F53242/52 +;// <29=> HT32F53231/41 +*/ + .equ USE_HT32_CHIP_SET, 0 + + .equ _HT32FWID, 0xFFFFFFFF +/* + .equ _HT32FWID, 0x00053242 + .equ _HT32FWID, 0x00053252 + .equ _HT32FWID, 0x00053231 + .equ _HT32FWID, 0x00053241 +*/ + + .equ HT32F53242_52, 28 + .equ HT32F53231_41, 29 + + .if USE_HT32_CHIP_SET == 0 + .else + .equ USE_HT32_CHIP, USE_HT32_CHIP_SET + .endif + + .syntax unified + .cpu cortex-m0plus + .fpu softvfp + .thumb + +/* start address for the initialization values of the .data section. defined in linker script */ +.word _sidata + +/* start address for the .data section. defined in linker script */ +.word _sdata + +/* end address for the .data section. defined in linker script */ +.word _edata + +/* start address for the .bss section. defined in linker script */ +.word _sbss + +/* end address for the .bss section. defined in linker script */ +.word _ebss + + +/* +; Amount of memory (in bytes) allocated for Stack and Heap +; Tailor those values to your application needs +;// Stack Size (in Bytes, must 8 byte aligned) <:8> +*/ + .equ Stack_Size, 512 + .section ".stack", "w" + .align 3 + .globl __StackTop + .globl __StackLimit + .globl __HT_check_sp +__HT_check_sp: +__StackLimit: + .if Stack_Size + .space Stack_Size + .endif + .size __StackLimit, . - __StackLimit +__StackTop: + .size __StackTop, . - __StackTop + +/* +;// Heap Size (in Bytes) <:8> +*/ + .equ Heap_Size, 0 + .section ".heap", "w" + .align 3 + .globl __HeapBase + .globl _end + .globl __HeapLimit + .globl __HT_check_heap +__HT_check_heap: +__HeapBase: +_end: + .if Heap_Size + .space Heap_Size + .endif + .size __HeapBase, . - __HeapBase +__HeapLimit: + .size __HeapLimit, . - __HeapLimit + + .equ _RESERVED, 0xFFFFFFFF +/* +;******************************************************************************* +; Fill-up the Vector Table entries with the exceptions ISR address +;********************************************************************************/ + .section .isr_vector,"a",%progbits + .global __interrupt_vector_cortex_m + .type __interrupt_vector_cortex_m, %object +__interrupt_vector_cortex_m: + .long __StackTop /* ---, 00, 0x000, Top address of Stack */ + .long Reset_Handler /* ---, 01, 0x004, Reset Handler */ + .long NMI_Handler /* -14, 02, 0x008, NMI Handler */ + .long HardFault_Handler /* -13, 03, 0x00C, Hard Fault Handler */ + .long _RESERVED /* ---, 04, 0x010, Reserved */ + .long _RESERVED /* ---, 05, 0x014, Reserved */ + .long _RESERVED /* ---, 06, 0x018, Reserved */ + .long _RESERVED /* ---, 07, 0x01C, Reserved */ + .long _HT32FWID /* ---, 08, 0x020, Reserved */ + .long _RESERVED /* ---, 09, 0x024, Reserved */ + .long _RESERVED /* ---, 10, 0x028, Reserved */ + .long SVC_Handler /* -05, 11, 0x02C, SVC Handler */ + .long _RESERVED /* ---, 12, 0x030, Reserved */ + .long _RESERVED /* ---, 13, 0x034, Reserved */ + .long PendSV_Handler /* -02, 14, 0x038, PendSV Handler */ + .long SysTick_Handler /* -01, 15, 0x03C, SysTick Handler */ + + /* External Interrupt Handler */ + .long LVD_BOD_IRQHandler /* 00, 16, 0x040, */ + .long RTC_IRQHandler /* 01, 17, 0x044, */ + .long FLASH_IRQHandler /* 02, 18, 0x048, */ + .long EVWUP_IRQHandler /* 03, 19, 0x04C, */ + .long EXTI0_1_IRQHandler /* 04, 20, 0x050, */ + .long EXTI2_3_IRQHandler /* 05, 21, 0x054, */ + .long EXTI4_15_IRQHandler /* 06, 22, 0x058, */ + .if (USE_HT32_CHIP==HT32F53242_52) + .long COMP_IRQHandler /* 07, 23, 0x05C, */ + .else + .long _RESERVED /* 07, 23, 0x05C, */ + .endif + .long ADC_IRQHandler /* 08, 24, 0x060, */ + .long _RESERVED /* 09, 25, 0x064, */ + .long MCTM0_IRQHandler /* 10, 26, 0x068, */ + .long _RESERVED /* 11, 27, 0x06C, */ + .long GPTM0_IRQHandler /* 12, 28, 0x070, */ + .long _RESERVED /* 13, 29, 0x074, */ + .long _RESERVED /* 14, 30, 0x078, */ + .long PWM0_IRQHandler /* 15, 31, 0x07C, */ + .if (USE_HT32_CHIP==HT32F53242_52) + .long PWM1_IRQHandler /* 16, 32, 0x080, */ + .else + .long _RESERVED /* 16, 32, 0x080, */ + .endif + .long BFTM0_IRQHandler /* 17, 33, 0x084, */ + .long BFTM1_IRQHandler /* 18, 34, 0x088, */ + .long I2C0_IRQHandler /* 19, 35, 0x08C, */ + .long I2C1_IRQHandler /* 20, 36, 0x090, */ + .long SPI0_IRQHandler /* 21, 37, 0x094, */ + .long SPI1_IRQHandler /* 22, 38, 0x098, */ + .long USART0_IRQHandler /* 23, 39, 0x09C, */ + .if (USE_HT32_CHIP==HT32F53242_52) + .long USART1_IRQHandler /* 24, 40, 0x0A0, */ + .else + .long _RESERVED /* 24, 40, 0x0A0, */ + .endif + .long UART0_IRQHandler /* 25, 41, 0x0A4, */ + .long UART1_IRQHandler /* 26, 42, 0x0A8, */ + .long CAN0_IRQHandler /* 27, 43, 0x0AC, */ + .long _RESERVED /* 28, 44, 0x0B0, */ + .long LEDC_IRQHandler /* 29, 45, 0x0B4, */ + .long PDMA_CH0_1_IRQHandler /* 30, 46, 0x0B8, */ + .long PDMA_CH2_5_IRQHandler /* 31, 47, 0x0BC, */ + + .size __interrupt_vector_cortex_m, . - __interrupt_vector_cortex_m + + + .thumb + + +/* Reset Handler */ + + .section .text.Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + LDR R0, =__StackTop /* set stack pointer */ + MOV SP, R0 + LDR R0, =SystemInit + BLX R0 + + /* Copy the data segment initializers from flash to SRAM */ + MOVS R1, #0 + B LoopCopyDataInit + +CopyDataInit: + LDR R3, =_sidata + LDR R3, [R3, R1] + STR R3, [R0, R1] + ADDS R1, R1, #4 + +LoopCopyDataInit: + LDR R0, =_sdata + LDR R3, =_edata + ADDS R2, R0, R1 + CMP R2, R3 + BCC CopyDataInit + LDR R2, =_sbss + B LoopFillZerobss + +/* Zero fill the bss segment. */ +FillZerobss: + MOVS R3, #0 + STR R3, [R2] + ADDS R2, R2, #4 + +LoopFillZerobss: + LDR R3, =_ebss + CMP R2, R3 + BCC FillZerobss + + /* Call static constructors */ + BL __libc_init_array + + /* Call the application's entry point.*/ + BL main + +LoopForever: + B LoopForever + + .thumb_func + + .size Reset_Handler, .-Reset_Handler + +/* Exception Handlers */ + + .weak NMI_Handler + .type NMI_Handler, %function +NMI_Handler: + B . + .size NMI_Handler, . - NMI_Handler + + .weak HardFault_Handler + .type HardFault_Handler, %function +HardFault_Handler: + B . + .size HardFault_Handler, . - HardFault_Handler + + .weak SVC_Handler + .type SVC_Handler, %function +SVC_Handler: + B . + .size SVC_Handler, . - SVC_Handler + + .weak PendSV_Handler + .type PendSV_Handler, %function +PendSV_Handler: + B . + .size PendSV_Handler, . - PendSV_Handler + + .weak SysTick_Handler + .type SysTick_Handler, %function +SysTick_Handler: + B . + .size SysTick_Handler, . - SysTick_Handler + + +/* IRQ Handlers */ + + .globl Default_Handler + .type Default_Handler, %function +Default_Handler: + B . + .size Default_Handler, . - Default_Handler + + .macro IRQ handler + .weak \handler + .set \handler, Default_Handler + .endm + + IRQ LVD_BOD_IRQHandler + IRQ RTC_IRQHandler + IRQ FLASH_IRQHandler + IRQ EVWUP_IRQHandler + IRQ EXTI0_1_IRQHandler + IRQ EXTI2_3_IRQHandler + IRQ EXTI4_15_IRQHandler + IRQ COMP_IRQHandler + IRQ ADC_IRQHandler + IRQ MCTM0_IRQHandler + IRQ GPTM0_IRQHandler + IRQ PWM0_IRQHandler + IRQ PWM1_IRQHandler + IRQ BFTM0_IRQHandler + IRQ BFTM1_IRQHandler + IRQ I2C0_IRQHandler + IRQ I2C1_IRQHandler + IRQ SPI0_IRQHandler + IRQ SPI1_IRQHandler + IRQ USART0_IRQHandler + IRQ USART1_IRQHandler + IRQ UART0_IRQHandler + IRQ UART1_IRQHandler + IRQ CAN0_IRQHandler + IRQ LEDC_IRQHandler + IRQ PDMA_CH0_1_IRQHandler + IRQ PDMA_CH2_5_IRQHandler + + .end diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/GCC/startup_ht32f5xxxx_gcc_16.s b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/GCC/startup_ht32f5xxxx_gcc_16.s new file mode 100644 index 0000000000..8cb1f85b48 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/GCC/startup_ht32f5xxxx_gcc_16.s @@ -0,0 +1,317 @@ +/*---------------------------------------------------------------------------------------------------------*/ +/* Holtek Semiconductor Inc. */ +/* */ +/* Copyright (C) Holtek Semiconductor Inc. */ +/* All rights reserved. */ +/* */ +/*----------------------------------------------------------------------------------------------------------- +; File Name : startup_ht32f5xxxx_gcc_16.s +; Version : $Rev:: 7094 $ +; Date : $Date:: 2023-08-02 #$ +; Description : Startup code. +;-----------------------------------------------------------------------------------------------------------*/ + +/* +; Supported Device +; ======================================== +; HT32F66242 +; HT32F66246 +*/ + +;/* <<< Use Configuration Wizard in Context Menu >>> */ +/* + + + + +*/ + .equ USE_HT32_CHIP_SET, 0 + +/* + .equ _HT32FWID, 0xFFFFFFFF + .equ _HT32FWID, 0x00066246 +*/ + + .equ HT32F66246, 31 + .equ HT32F66242, 33 + + .if USE_HT32_CHIP_SET == 0 + .else + .equ USE_HT32_CHIP, USE_HT32_CHIP_SET + .endif + + .if USE_HT32_CHIP == 0 + .equ _HT32FWID, 0x00066246 + .endif + .if USE_HT32_CHIP == HT32F66246 + .equ _HT32FWID, 0x00066246 + .endif + .if USE_HT32_CHIP == HT32F66242 + .equ _HT32FWID, 0x00066242 + .endif + + .syntax unified + .cpu cortex-m0plus + .fpu softvfp + .thumb + +/* start address for the initialization values of the .data section. defined in linker script */ +.word _sidata + +/* start address for the .data section. defined in linker script */ +.word _sdata + +/* end address for the .data section. defined in linker script */ +.word _edata + +/* start address for the .bss section. defined in linker script */ +.word _sbss + +/* end address for the .bss section. defined in linker script */ +.word _ebss + + +/* +; Amount of memory (in bytes) allocated for Stack and Heap +; Tailor those values to your application needs +;// Stack Size (in Bytes, must 8 byte aligned) <:8> +*/ + .equ Stack_Size, 512 + .section ".stack", "w" + .align 3 + .globl __StackTop + .globl __StackLimit + .globl __HT_check_sp +__HT_check_sp: +__StackLimit: + .if Stack_Size + .space Stack_Size + .endif + .size __StackLimit, . - __StackLimit +__StackTop: + .size __StackTop, . - __StackTop + +/* +;// Heap Size (in Bytes) <:8> +*/ + .equ Heap_Size, 0 + .section ".heap", "w" + .align 3 + .globl __HeapBase + .globl _end + .globl __HeapLimit + .globl __HT_check_heap +__HT_check_heap: +__HeapBase: +_end: + .if Heap_Size + .space Heap_Size + .endif + .size __HeapBase, . - __HeapBase +__HeapLimit: + .size __HeapLimit, . - __HeapLimit + + .equ _RESERVED, 0xFFFFFFFF +/* +;******************************************************************************* +; Fill-up the Vector Table entries with the exceptions ISR address +;********************************************************************************/ + .section .isr_vector,"a",%progbits + .global __interrupt_vector_cortex_m + .type __interrupt_vector_cortex_m, %object +__interrupt_vector_cortex_m: + .long __StackTop /* ---, 00, 0x000, Top address of Stack */ + .long Reset_Handler /* ---, 01, 0x004, Reset Handler */ + .long NMI_Handler /* -14, 02, 0x008, NMI Handler */ + .long HardFault_Handler /* -13, 03, 0x00C, Hard Fault Handler */ + .long _RESERVED /* ---, 04, 0x010, Reserved */ + .long _RESERVED /* ---, 05, 0x014, Reserved */ + .long _RESERVED /* ---, 06, 0x018, Reserved */ + .long _RESERVED /* ---, 07, 0x01C, Reserved */ + .long _HT32FWID /* ---, 08, 0x020, Reserved */ + .long _RESERVED /* ---, 09, 0x024, Reserved */ + .long _RESERVED /* ---, 10, 0x028, Reserved */ + .long SVC_Handler /* -05, 11, 0x02C, SVC Handler */ + .long _RESERVED /* ---, 12, 0x030, Reserved */ + .long _RESERVED /* ---, 13, 0x034, Reserved */ + .long PendSV_Handler /* -02, 14, 0x038, PendSV Handler */ + .long SysTick_Handler /* -01, 15, 0x03C, SysTick Handler */ + + /* External Interrupt Handler */ + .long LVD_BOD_IRQHandler /* 00, 16, 0x040, */ + .long RTC_IRQHandler /* 01, 17, 0x044, */ + .long FLASH_IRQHandler /* 02, 18, 0x048, */ + .long EVWUP_IRQHandler /* 03, 19, 0x04C, */ + .long EXTI0_1_IRQHandler /* 04, 20, 0x050, */ + .long EXTI2_3_IRQHandler /* 05, 21, 0x054, */ + .long EXTI4_15_IRQHandler /* 06, 22, 0x058, */ + .if (USE_HT32_CHIP==HT32F66246) + .long CAN0_IRQHandler /* 07, 23, 0x05C, */ + .else + .long _RESERVED /* 07, 23, 0x05C, */ + .endif + .long ADC_IRQHandler /* 08, 24, 0x060, */ + .long CORDIC_IRQHandler /* 09, 25, 0x064, */ + .long MCTM0_BRK_IRQHandler /* 10, 26, 0x068, */ + .long MCTM0_UP_IRQHandler /* 11, 27, 0x06C, */ + .long MCTM0_TR_UP2_IRQHandler /* 12, 28, 0x070, */ + .long MCTM0_CC_IRQHandler /* 13, 29, 0x074, */ + .long GPTM0_G_IRQHandler /* 14, 30, 0x078, */ + .long GPTM0_VCLK_IRQHandler /* 15, 31, 0x07C, */ + .long BFTM0_IRQHandler /* 16, 32, 0x080, */ + .long BFTM1_IRQHandler /* 17, 33, 0x084, */ + .long CMP0_IRQHandler /* 18, 34, 0x088, */ + .long CMP1_IRQHandler /* 19, 35, 0x08C, */ + .long PID_IRQHandler /* 20, 36, 0x090, */ + .long I2C0_IRQHandler /* 21, 37, 0x094, */ + .long SPI0_IRQHandler /* 22, 38, 0x098, */ + .long USART0_IRQHandler /* 23, 39, 0x09C, */ + .long UART0_IRQHandler /* 24, 40, 0x0A0, */ + .long PDMA_CH0_1_IRQHandler /* 25, 41, 0x0A4, */ + .long PDMA_CH2_3_IRQHandler /* 26, 42, 0x0A8, */ + .long PDMA_CH4_5_IRQHandler /* 27, 43, 0x0AC, */ + .long SCTM0_IRQHandler /* 28, 44, 0x0B0, */ + .long SCTM1_IRQHandler /* 29, 45, 0x0B4, */ + .long SCTM2_IRQHandler /* 30, 46, 0x0B8, */ + .long SCTM3_IRQHandler /* 31, 47, 0x0BC, */ + + .size __interrupt_vector_cortex_m, . - __interrupt_vector_cortex_m + + + .thumb + + +/* Reset Handler */ + + .section .text.Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + LDR R0, =__StackTop /* set stack pointer */ + MOV SP, R0 + LDR R0, =SystemInit + BLX R0 + + /* Copy the data segment initializers from flash to SRAM */ + MOVS R1, #0 + B LoopCopyDataInit + +CopyDataInit: + LDR R3, =_sidata + LDR R3, [R3, R1] + STR R3, [R0, R1] + ADDS R1, R1, #4 + +LoopCopyDataInit: + LDR R0, =_sdata + LDR R3, =_edata + ADDS R2, R0, R1 + CMP R2, R3 + BCC CopyDataInit + LDR R2, =_sbss + B LoopFillZerobss + +/* Zero fill the bss segment. */ +FillZerobss: + MOVS R3, #0 + STR R3, [R2] + ADDS R2, R2, #4 + +LoopFillZerobss: + LDR R3, =_ebss + CMP R2, R3 + BCC FillZerobss + + /* Call static constructors */ + BL __libc_init_array + + /* Call the application's entry point.*/ + BL main + +LoopForever: + B LoopForever + + .thumb_func + + .size Reset_Handler, .-Reset_Handler + +/* Exception Handlers */ + + .weak NMI_Handler + .type NMI_Handler, %function +NMI_Handler: + B . + .size NMI_Handler, . - NMI_Handler + + .weak HardFault_Handler + .type HardFault_Handler, %function +HardFault_Handler: + B . + .size HardFault_Handler, . - HardFault_Handler + + .weak SVC_Handler + .type SVC_Handler, %function +SVC_Handler: + B . + .size SVC_Handler, . - SVC_Handler + + .weak PendSV_Handler + .type PendSV_Handler, %function +PendSV_Handler: + B . + .size PendSV_Handler, . - PendSV_Handler + + .weak SysTick_Handler + .type SysTick_Handler, %function +SysTick_Handler: + B . + .size SysTick_Handler, . - SysTick_Handler + + +/* IRQ Handlers */ + + .globl Default_Handler + .type Default_Handler, %function +Default_Handler: + B . + .size Default_Handler, . - Default_Handler + + .macro IRQ handler + .weak \handler + .set \handler, Default_Handler + .endm + + IRQ LVD_BOD_IRQHandler + IRQ RTC_IRQHandler + IRQ FLASH_IRQHandler + IRQ EVWUP_IRQHandler + IRQ EXTI0_1_IRQHandler + IRQ EXTI2_3_IRQHandler + IRQ EXTI4_15_IRQHandler + IRQ CAN0_IRQHandler + IRQ ADC_IRQHandler + IRQ CORDIC_IRQHandler + IRQ MCTM0_BRK_IRQHandler + IRQ MCTM0_UP_IRQHandler + IRQ MCTM0_TR_UP2_IRQHandler + IRQ MCTM0_CC_IRQHandler + IRQ GPTM0_G_IRQHandler + IRQ GPTM0_VCLK_IRQHandler + IRQ BFTM0_IRQHandler + IRQ BFTM1_IRQHandler + IRQ CMP0_IRQHandler + IRQ CMP1_IRQHandler + IRQ PID_IRQHandler + IRQ I2C0_IRQHandler + IRQ SPI0_IRQHandler + IRQ USART0_IRQHandler + IRQ UART0_IRQHandler + IRQ PDMA_CH0_1_IRQHandler + IRQ PDMA_CH2_3_IRQHandler + IRQ PDMA_CH4_5_IRQHandler + IRQ SCTM0_IRQHandler + IRQ SCTM1_IRQHandler + IRQ SCTM2_IRQHandler + IRQ SCTM3_IRQHandler + + .end diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/GCC/startup_ht32f5xxxx_gcc_17.s b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/GCC/startup_ht32f5xxxx_gcc_17.s new file mode 100644 index 0000000000..f19b45b36f --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/GCC/startup_ht32f5xxxx_gcc_17.s @@ -0,0 +1,291 @@ +/*---------------------------------------------------------------------------------------------------------*/ +/* Holtek Semiconductor Inc. */ +/* */ +/* Copyright (C) Holtek Semiconductor Inc. */ +/* All rights reserved. */ +/* */ +/*----------------------------------------------------------------------------------------------------------- +; File Name : startup_ht32f5xxxx_gcc_17.s +; Version : $Rev:: 7030 $ +; Date : $Date:: 2023-07-18 #$ +; Description : Startup code. +;-----------------------------------------------------------------------------------------------------------*/ + +/* +; Supported Device +; ======================================== +; HT32F52234, HT32F52244 +*/ + +;/* <<< Use Configuration Wizard in Context Menu >>> */ +/* +;// HT32 Device +;// <0=> By Project Asm Define +;// <33=> HT32F52234/44 +*/ + .equ USE_HT32_CHIP_SET, 0 + + .equ _HT32FWID, 0xFFFFFFFF +/* + .equ _HT32FWID, 0x00052234 + .equ _HT32FWID, 0x00052244 +*/ + + .equ HT32F52234_44, 33 + + .if USE_HT32_CHIP_SET == 0 + .else + .equ USE_HT32_CHIP, USE_HT32_CHIP_SET + .endif + + .syntax unified + .cpu cortex-m0plus + .fpu softvfp + .thumb + +/* start address for the initialization values of the .data section. defined in linker script */ +.word _sidata + +/* start address for the .data section. defined in linker script */ +.word _sdata + +/* end address for the .data section. defined in linker script */ +.word _edata + +/* start address for the .bss section. defined in linker script */ +.word _sbss + +/* end address for the .bss section. defined in linker script */ +.word _ebss + + +/* +; Amount of memory (in bytes) allocated for Stack and Heap +; Tailor those values to your application needs +;// Stack Size (in Bytes, must 8 byte aligned) <:8> +*/ + .equ Stack_Size, 512 + .section ".stack", "w" + .align 3 + .globl __StackTop + .globl __StackLimit + .globl __HT_check_sp +__HT_check_sp: +__StackLimit: + .if Stack_Size + .space Stack_Size + .endif + .size __StackLimit, . - __StackLimit +__StackTop: + .size __StackTop, . - __StackTop + +/* +;// Heap Size (in Bytes) <:8> +*/ + .equ Heap_Size, 0 + .section ".heap", "w" + .align 3 + .globl __HeapBase + .globl _end + .globl __HeapLimit + .globl __HT_check_heap +__HT_check_heap: +__HeapBase: +_end: + .if Heap_Size + .space Heap_Size + .endif + .size __HeapBase, . - __HeapBase +__HeapLimit: + .size __HeapLimit, . - __HeapLimit + + .equ _RESERVED, 0xFFFFFFFF +/* +;******************************************************************************* +; Fill-up the Vector Table entries with the exceptions ISR address +;********************************************************************************/ + .section .isr_vector,"a",%progbits + .global __interrupt_vector_cortex_m + .type __interrupt_vector_cortex_m, %object +__interrupt_vector_cortex_m: + .long __StackTop /* ---, 00, 0x000, Top address of Stack */ + .long Reset_Handler /* ---, 01, 0x004, Reset Handler */ + .long NMI_Handler /* -14, 02, 0x008, NMI Handler */ + .long HardFault_Handler /* -13, 03, 0x00C, Hard Fault Handler */ + .long _RESERVED /* ---, 04, 0x010, Reserved */ + .long _RESERVED /* ---, 05, 0x014, Reserved */ + .long _RESERVED /* ---, 06, 0x018, Reserved */ + .long _RESERVED /* ---, 07, 0x01C, Reserved */ + .long _HT32FWID /* ---, 08, 0x020, Reserved */ + .long _RESERVED /* ---, 09, 0x024, Reserved */ + .long _RESERVED /* ---, 10, 0x028, Reserved */ + .long SVC_Handler /* -05, 11, 0x02C, SVC Handler */ + .long _RESERVED /* ---, 12, 0x030, Reserved */ + .long _RESERVED /* ---, 13, 0x034, Reserved */ + .long PendSV_Handler /* -02, 14, 0x038, PendSV Handler */ + .long SysTick_Handler /* -01, 15, 0x03C, SysTick Handler */ + + /* External Interrupt Handler */ + .long LVD_BOD_IRQHandler /* 00, 16, 0x040, */ + .long RTC_IRQHandler /* 01, 17, 0x044, */ + .long FLASH_IRQHandler /* 02, 18, 0x048, */ + .long EVWUP_IRQHandler /* 03, 19, 0x04C, */ + .long EXTI0_1_IRQHandler /* 04, 20, 0x050, */ + .long EXTI2_3_IRQHandler /* 05, 21, 0x054, */ + .long EXTI4_15_IRQHandler /* 06, 22, 0x058, */ + .long DAC0_1_IRQHandler /* 07, 23, 0x05C, */ + .long ADC_IRQHandler /* 08, 24, 0x060, */ + .long I2C2_IRQHandler /* 09, 25, 0x064, */ + .long _RESERVED /* 10, 26, 0x068, */ + .long _RESERVED /* 11, 27, 0x06C, */ + .long _RESERVED /* 12, 28, 0x070, */ + .long SCTM0_IRQHandler /* 13, 29, 0x074, */ + .long SCTM1_IRQHandler /* 14, 30, 0x078, */ + .long PWM0_IRQHandler /* 15, 31, 0x07C, */ + .long _RESERVED /* 16, 32, 0x080, */ + .long BFTM0_IRQHandler /* 17, 33, 0x084, */ + .long BFTM1_IRQHandler /* 18, 34, 0x088, */ + .long I2C0_IRQHandler /* 19, 35, 0x08C, */ + .long I2C1_IRQHandler /* 20, 36, 0x090, */ + .long SPI0_IRQHandler /* 21, 37, 0x094, */ + .long _RESERVED /* 22, 38, 0x098, */ + .long USART0_IRQHandler /* 23, 39, 0x09C, */ + .long _RESERVED /* 24, 40, 0x0A0, */ + .long UART0_IRQHandler /* 25, 41, 0x0A4, */ + .long _RESERVED /* 26, 42, 0x0A8, */ + .long _RESERVED /* 27, 43, 0x0AC, */ + .long _RESERVED /* 28, 44, 0x0B0, */ + .long _RESERVED /* 29, 45, 0x0B4, */ + .long PDMA_CH0_1_IRQHandler /* 30, 46, 0x0B8, */ + .long PDMA_CH2_5_IRQHandler /* 31, 47, 0x0BC, */ + + .size __interrupt_vector_cortex_m, . - __interrupt_vector_cortex_m + + + .thumb + + +/* Reset Handler */ + + .section .text.Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + LDR R0, =__StackTop /* set stack pointer */ + MOV SP, R0 + LDR R0, =SystemInit + BLX R0 + + /* Copy the data segment initializers from flash to SRAM */ + MOVS R1, #0 + B LoopCopyDataInit + +CopyDataInit: + LDR R3, =_sidata + LDR R3, [R3, R1] + STR R3, [R0, R1] + ADDS R1, R1, #4 + +LoopCopyDataInit: + LDR R0, =_sdata + LDR R3, =_edata + ADDS R2, R0, R1 + CMP R2, R3 + BCC CopyDataInit + LDR R2, =_sbss + B LoopFillZerobss + +/* Zero fill the bss segment. */ +FillZerobss: + MOVS R3, #0 + STR R3, [R2] + ADDS R2, R2, #4 + +LoopFillZerobss: + LDR R3, =_ebss + CMP R2, R3 + BCC FillZerobss + + /* Call static constructors */ + BL __libc_init_array + + /* Call the application's entry point.*/ + BL main + +LoopForever: + B LoopForever + + .thumb_func + + .size Reset_Handler, .-Reset_Handler + +/* Exception Handlers */ + + .weak NMI_Handler + .type NMI_Handler, %function +NMI_Handler: + B . + .size NMI_Handler, . - NMI_Handler + + .weak HardFault_Handler + .type HardFault_Handler, %function +HardFault_Handler: + B . + .size HardFault_Handler, . - HardFault_Handler + + .weak SVC_Handler + .type SVC_Handler, %function +SVC_Handler: + B . + .size SVC_Handler, . - SVC_Handler + + .weak PendSV_Handler + .type PendSV_Handler, %function +PendSV_Handler: + B . + .size PendSV_Handler, . - PendSV_Handler + + .weak SysTick_Handler + .type SysTick_Handler, %function +SysTick_Handler: + B . + .size SysTick_Handler, . - SysTick_Handler + + +/* IRQ Handlers */ + + .globl Default_Handler + .type Default_Handler, %function +Default_Handler: + B . + .size Default_Handler, . - Default_Handler + + .macro IRQ handler + .weak \handler + .set \handler, Default_Handler + .endm + + IRQ LVD_BOD_IRQHandler + IRQ RTC_IRQHandler + IRQ FLASH_IRQHandler + IRQ EVWUP_IRQHandler + IRQ EXTI0_1_IRQHandler + IRQ EXTI2_3_IRQHandler + IRQ EXTI4_15_IRQHandler + IRQ DAC0_1_IRQHandler + IRQ ADC_IRQHandler + IRQ I2C2_IRQHandler + IRQ SCTM0_IRQHandler + IRQ SCTM1_IRQHandler + IRQ PWM0_IRQHandler + IRQ BFTM0_IRQHandler + IRQ BFTM1_IRQHandler + IRQ I2C0_IRQHandler + IRQ I2C1_IRQHandler + IRQ SPI0_IRQHandler + IRQ USART0_IRQHandler + IRQ UART0_IRQHandler + IRQ PDMA_CH0_1_IRQHandler + IRQ PDMA_CH2_5_IRQHandler + + .end diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/IAR/startup_ht32f5xxxx_iar_01.s b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/IAR/startup_ht32f5xxxx_iar_01.s new file mode 100644 index 0000000000..1fc4bed7a6 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/IAR/startup_ht32f5xxxx_iar_01.s @@ -0,0 +1,430 @@ +;/*---------------------------------------------------------------------------------------------------------*/ +;/* Holtek Semiconductor Inc. */ +;/* */ +;/* Copyright (C) Holtek Semiconductor Inc. */ +;/* All rights reserved. */ +;/* */ +;/*----------------------------------------------------------------------------------------------------------- +; File Name : startup_ht32f5xxxx_iar_01.s +; Version : $Rev:: 6953 $ +; Date : $Date:: 2023-05-30 #$ +; Description : Startup code. +;-----------------------------------------------------------------------------------------------------------*/ + +; Supported Device +; ======================================== +; HT32F52220, HT32F52230 +; HT32F52231, HT32F52241 +; HT32F52331, HT32F52341 +; HT32F52342, HT32F52352 +; HT32F52243, HT32F52253 +; HT32F0008 +; HT32F52344, HT32F52354 +; HT32F0006 +; HT32F61352 +; HT50F32003 +; HT32F62030, HT32F62040, HT32F62050 +; HT32F67741 +; HT32F67232 +; HT32F67233 + +;/* <<< Use Configuration Wizard in Context Menu >>> */ + +;// HT32 Device +;// <0=> By Project Asm Define +;// <1=> HT32F52220/30 +;// <2=> HT32F52231/41 +;// <3=> HT32F52331/41 +;// <4=> HT32F52342/52 +;// <5=> HT32F52243/53 +;// <6=> HT32F0008 +;// <9=> HT32F52344/54 +;// <10=> HT32F0006 +;// <10=> HT32F61352 +;// <4=> HT50F32003 +;// <2=> HT32F67741 +;// <1=> HT32F67232 +;// <1=> HT32F67233 +;// <1=> HT32F62030 +;// <2=> HT32F62040 +;// <5=> HT32F62050 +USE_HT32_CHIP_SET EQU 0 + +_HT32FWID EQU 0xFFFFFFFF +;_HT32FWID EQU 0x00052220 +;_HT32FWID EQU 0x00052230 +;_HT32FWID EQU 0x00052231 +;_HT32FWID EQU 0x00052241 +;_HT32FWID EQU 0x00052331 +;_HT32FWID EQU 0x00052341 +;_HT32FWID EQU 0x00052342 +;_HT32FWID EQU 0x00052352 +;_HT32FWID EQU 0x00052243 +;_HT32FWID EQU 0x00052253 +;_HT32FWID EQU 0x00000008 +;_HT32FWID EQU 0x00052344 +;_HT32FWID EQU 0x00052354 +;_HT32FWID EQU 0x00000006 +;_HT32FWID EQU 0x00061352 +;_HT32FWID EQU 0x00032003 +;_HT32FWID EQU 0x00062030 +;_HT32FWID EQU 0x00062040 +;_HT32FWID EQU 0x00062050 +;_HT32FWID EQU 0x00067741 +;_HT32FWID EQU 0x00067232 +;_HT32FWID EQU 0x00067233 + +HT32F52220_30 EQU 1 +HT32F52231_41 EQU 2 +HT32F52331_41 EQU 3 +HT32F52342_52 EQU 4 +HT32F52243_53 EQU 5 +HT32F0008 EQU 6 +HT32F52344_54 EQU 9 +HT32F0006 EQU 10 +HT32F61352 EQU 10 +HT50F32003 EQU 4 +HT32F62030 EQU 1 +HT32F62040 EQU 2 +HT32F62050 EQU 5 +HT32F67741 EQU 2 +HT32F67232 EQU 1 +HT32F67233 EQU 1 + + IF USE_HT32_CHIP_SET=0 + ELSE + #undef USE_HT32_CHIP + #define USE_HT32_CHIP USE_HT32_CHIP_SET + ENDIF + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + EXTERN SystemInit + PUBLIC __vector_table + +;******************************************************************************* +; Fill-up the Vector Table entries with the exceptions ISR address +;******************************************************************************* + DATA +_RESERVED EQU 0xFFFFFFFF +__vector_table + DCD sfe(CSTACK) ; ---, 00, 0x000, Top address of Stack + DCD Reset_Handler ; ---, 01, 0x004, Reset Handler + DCD NMI_Handler ; -14, 02, 0x008, NMI Handler + DCD HardFault_Handler ; -13, 03, 0x00C, Hard Fault Handler + DCD _RESERVED ; ---, 04, 0x010, Reserved + DCD _RESERVED ; ---, 05, 0x014, Reserved + DCD _RESERVED ; ---, 06, 0x018, Reserved + DCD _RESERVED ; ---, 07, 0x01C, Reserved + DCD _HT32FWID ; ---, 08, 0x020, Reserved + DCD _RESERVED ; ---, 09, 0x024, Reserved + DCD _RESERVED ; ---, 10, 0x028, Reserved + DCD SVC_Handler ; -05, 11, 0x02C, SVC Handler + DCD _RESERVED ; ---, 12, 0x030, Reserved + DCD _RESERVED ; ---, 13, 0x034, Reserved + DCD PendSV_Handler ; -02, 14, 0x038, PendSV Handler + DCD SysTick_Handler ; -01, 15, 0x03C, SysTick Handler + + ; External Interrupt Handler + DCD LVD_BOD_IRQHandler ; 00, 16, 0x040, + IF (USE_HT32_CHIP=HT32F52220_30) + DCD _RESERVED ; 01, 17, 0x044, + ELSE + DCD RTC_IRQHandler ; 01, 17, 0x044, + ENDIF + DCD FLASH_IRQHandler ; 02, 18, 0x048, + DCD EVWUP_IRQHandler ; 03, 19, 0x04C, + DCD EXTI0_1_IRQHandler ; 04, 20, 0x050, + DCD EXTI2_3_IRQHandler ; 05, 21, 0x054, + DCD EXTI4_15_IRQHandler ; 06, 22, 0x058, + IF (USE_HT32_CHIP=HT32F52342_52) || (USE_HT32_CHIP=HT32F52344_54) + DCD COMP_IRQHandler ; 07, 23, 0x05C, + ELSE + DCD _RESERVED ; 07, 23, 0x05C, + ENDIF + IF (USE_HT32_CHIP=HT32F0008) + DCD _RESERVED ; 08, 24, 0x060, + ELSE + DCD ADC_IRQHandler ; 08, 24, 0x060, + ENDIF + IF (USE_HT32_CHIP=HT32F52243_53) + DCD I2C2_IRQHandler ; 09, 25, 0x064, + ELSE + DCD _RESERVED ; 09, 25, 0x064, + ENDIF + IF (USE_HT32_CHIP=HT32F52220_30) || (USE_HT32_CHIP=HT32F0008) || (USE_HT32_CHIP=HT32F0006) + DCD _RESERVED ; 10, 26, 0x068, + ELSE + DCD MCTM0_IRQHandler ; 10, 26, 0x068, + ENDIF + IF (USE_HT32_CHIP=HT32F52342_52) + DCD GPTM1_IRQHandler ; 11, 27, 0x06C, + ELSE + DCD _RESERVED ; 11, 27, 0x06C, + ENDIF + DCD GPTM0_IRQHandler ; 12, 28, 0x070, + IF (USE_HT32_CHIP=HT32F0008) + DCD _RESERVED ; 13, 29, 0x074, + DCD _RESERVED ; 14, 30, 0x078, + ELSE + DCD SCTM0_IRQHandler ; 13, 29, 0x074, + DCD SCTM1_IRQHandler ; 14, 30, 0x078, + ENDIF + IF (USE_HT32_CHIP=HT32F52231_41) || (USE_HT32_CHIP=HT32F52331_41) || (USE_HT32_CHIP=HT32F52243_53) || (USE_HT32_CHIP=HT32F0006) + DCD SCTM2_IRQHandler ; 15, 31, 0x07C, + DCD SCTM3_IRQHandler ; 16, 32, 0x080, + ENDIF + IF (USE_HT32_CHIP=HT32F0008) + DCD PWM0_IRQHandler ; 15, 31, 0x07C, + DCD PWM1_IRQHandler ; 16, 32, 0x080, + ENDIF + IF (USE_HT32_CHIP=HT32F52220_30) || (USE_HT32_CHIP=HT32F52342_52) || (USE_HT32_CHIP=HT32F52344_54) + DCD _RESERVED ; 15, 31, 0x07C, + DCD _RESERVED ; 16, 32, 0x080, + ENDIF + DCD BFTM0_IRQHandler ; 17, 33, 0x084, + IF (USE_HT32_CHIP=HT32F52220_30) + DCD _RESERVED ; 18, 34, 0x088, + ELSE + DCD BFTM1_IRQHandler ; 18, 34, 0x088, + ENDIF + DCD I2C0_IRQHandler ; 19, 35, 0x08C, + IF (USE_HT32_CHIP=HT32F52220_30) || (USE_HT32_CHIP=HT32F0008) || (USE_HT32_CHIP=HT32F52344_54) || (USE_HT32_CHIP=HT32F0006) + DCD _RESERVED ; 20, 36, 0x090, + ELSE + DCD I2C1_IRQHandler ; 20, 36, 0x090, + ENDIF + DCD SPI0_IRQHandler ; 21, 37, 0x094, + IF (USE_HT32_CHIP=HT32F52220_30) || (USE_HT32_CHIP=HT32F0008) + DCD _RESERVED ; 22, 38, 0x098, + ELSE + IF (USE_HT32_CHIP=HT32F0006) + DCD QSPI_IRQHandler ; 22, 38, 0x098, + ELSE + DCD SPI1_IRQHandler ; 22, 38, 0x098, + ENDIF + ENDIF + IF (USE_HT32_CHIP=HT32F52344_54) + DCD _RESERVED ; 23, 39, 0x09C, + ELSE + DCD USART0_IRQHandler ; 23, 39, 0x09C, + ENDIF + IF (USE_HT32_CHIP=HT32F52342_52) || (USE_HT32_CHIP=HT32F52243_53) + DCD USART1_IRQHandler ; 24, 40, 0x0A0, + ELSE + DCD _RESERVED ; 24, 40, 0x0A0, + ENDIF + DCD UART0_IRQHandler ; 25, 41, 0x0A4, + IF (USE_HT32_CHIP=HT32F52220_30) || (USE_HT32_CHIP=HT32F0008) || (USE_HT32_CHIP=HT32F0006) + DCD _RESERVED ; 26, 42, 0x0A8, + ELSE + DCD UART1_IRQHandler ; 26, 42, 0x0A8, + ENDIF + IF (USE_HT32_CHIP=HT32F52331_41) || (USE_HT32_CHIP=HT32F52342_52) + DCD SCI_IRQHandler ; 27, 43, 0x0AC, + ENDIF + IF (USE_HT32_CHIP=HT32F52243_53) + DCD UART2_IRQHandler ; 27, 43, 0x0AC, + ENDIF + IF (USE_HT32_CHIP=HT32F0006) + DCD MIDI_IRQHandler ; 27, 43, 0x0AC, + ENDIF + IF (USE_HT32_CHIP=HT32F0008) || (USE_HT32_CHIP=HT32F52344_54) + DCD _RESERVED ; 27, 43, 0xAC, + ENDIF + IF (USE_HT32_CHIP=HT32F52342_52) || (USE_HT32_CHIP=HT32F0006) + DCD I2S_IRQHandler ; 28, 44, 0x0B0, + ENDIF + IF (USE_HT32_CHIP=HT32F52331_41) || (USE_HT32_CHIP=HT32F52344_54) + DCD _RESERVED ; 28, 44, 0x0B0, + ENDIF + IF (USE_HT32_CHIP=HT32F52243_53) + DCD UART3_IRQHandler ; 28, 44, 0x0B0, + ENDIF + IF (USE_HT32_CHIP=HT32F0008) + DCD AES_IRQHandler ; 28, 44, 0x0B0, + ENDIF + IF (USE_HT32_CHIP=HT32F52331_41) || (USE_HT32_CHIP=HT32F52342_52) || (USE_HT32_CHIP=HT32F0008) || (USE_HT32_CHIP=HT32F52344_54) || (USE_HT32_CHIP=HT32F0006) + DCD USB_IRQHandler ; 29, 45, 0x0B4, + ENDIF + IF (USE_HT32_CHIP=HT32F52243_53) + DCD _RESERVED ; 29, 45, 0x0B4, + ENDIF + IF (USE_HT32_CHIP=HT32F52342_52) || (USE_HT32_CHIP=HT32F52243_53) || (USE_HT32_CHIP=HT32F0008) || (USE_HT32_CHIP=HT32F52344_54) || (USE_HT32_CHIP=HT32F0006) + DCD PDMA_CH0_1_IRQHandler ; 30, 46, 0x0B8, + DCD PDMA_CH2_5_IRQHandler ; 31, 47, 0x0BC, + ENDIF + + THUMB + + PUBWEAK Reset_Handler + SECTION .text:CODE:REORDER:NOROOT(2) +Reset_Handler + LDR R0, =BootProcess + BLX R0 + LDR R0, =SystemInit + BLX R0 + LDR R0, =__iar_program_start + BX R0 + +BootProcess + LDR R0, =0x40080300 + LDR R1,[R0, #0x10] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x14] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x18] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x1C] + CMP R1, #0 + BEQ BP2 +BP1 LDR R0, =0x40080180 + LDR R1,[R0, #0xC] + LSLS R1, R1, #4 + LSRS R1, R1, #20 + CMP R1, #0 + BEQ BP3 + CMP R1, #5 + BEQ BP3 + CMP R1, #6 + BEQ BP3 +BP2 DSB + LDR R0, =0x20000000 + LDR R1, =0x05fa0004 + STR R1, [R0] + LDR R1, =0xe000ed00 + LDR R0, =0x05fa0004 + STR R0, [R1, #0xC] + DSB + B . +BP3 LDR R0, =0x20000000 + LDR R1, [R0] + LDR R0, =0x05fa0004 + CMP R0, R1 + BEQ BP4 + BX LR +BP4 LDR R0, =0x40088100 + LDR R1, =0x00000001 + STR R1, [R0] + LDR R0, =0x20000000 + LDR R1, =0x0 + STR R1, [R0] + BX LR + + PUBWEAK NMI_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +NMI_Handler + B . + + PUBWEAK HardFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +HardFault_Handler + B . + + PUBWEAK SVC_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SVC_Handler + B . + + PUBWEAK PendSV_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PendSV_Handler + B . + + PUBWEAK SysTick_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SysTick_Handler + B . + + + PUBWEAK LVD_BOD_IRQHandler + PUBWEAK RTC_IRQHandler + PUBWEAK FLASH_IRQHandler + PUBWEAK EVWUP_IRQHandler + PUBWEAK EXTI0_1_IRQHandler + PUBWEAK EXTI2_3_IRQHandler + PUBWEAK EXTI4_15_IRQHandler + PUBWEAK COMP_IRQHandler + PUBWEAK ADC_IRQHandler + PUBWEAK MCTM0_IRQHandler + PUBWEAK GPTM0_IRQHandler + PUBWEAK GPTM1_IRQHandler + PUBWEAK SCTM0_IRQHandler + PUBWEAK SCTM1_IRQHandler + PUBWEAK SCTM2_IRQHandler + PUBWEAK SCTM3_IRQHandler + PUBWEAK PWM0_IRQHandler + PUBWEAK PWM1_IRQHandler + PUBWEAK BFTM0_IRQHandler + PUBWEAK BFTM1_IRQHandler + PUBWEAK I2C0_IRQHandler + PUBWEAK I2C1_IRQHandler + PUBWEAK I2C2_IRQHandler + PUBWEAK SPI0_IRQHandler + PUBWEAK SPI1_IRQHandler + PUBWEAK QSPI_IRQHandler + PUBWEAK USART0_IRQHandler + PUBWEAK USART1_IRQHandler + PUBWEAK UART0_IRQHandler + PUBWEAK UART1_IRQHandler + PUBWEAK UART2_IRQHandler + PUBWEAK UART3_IRQHandler + PUBWEAK SCI_IRQHandler + PUBWEAK MIDI_IRQHandler + PUBWEAK I2S_IRQHandler + PUBWEAK AES_IRQHandler + PUBWEAK USB_IRQHandler + PUBWEAK PDMA_CH0_1_IRQHandler + PUBWEAK PDMA_CH2_5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +LVD_BOD_IRQHandler +RTC_IRQHandler +FLASH_IRQHandler +EVWUP_IRQHandler +EXTI0_1_IRQHandler +EXTI2_3_IRQHandler +EXTI4_15_IRQHandler +COMP_IRQHandler +ADC_IRQHandler +MCTM0_IRQHandler +GPTM1_IRQHandler +GPTM0_IRQHandler +SCTM0_IRQHandler +SCTM1_IRQHandler +SCTM2_IRQHandler +SCTM3_IRQHandler +PWM0_IRQHandler +PWM1_IRQHandler +BFTM0_IRQHandler +BFTM1_IRQHandler +I2C0_IRQHandler +I2C1_IRQHandler +I2C2_IRQHandler +SPI0_IRQHandler +SPI1_IRQHandler +QSPI_IRQHandler +USART0_IRQHandler +USART1_IRQHandler +UART0_IRQHandler +UART1_IRQHandler +UART2_IRQHandler +UART3_IRQHandler +SCI_IRQHandler +MIDI_IRQHandler +I2S_IRQHandler +AES_IRQHandler +USB_IRQHandler +PDMA_CH0_1_IRQHandler +PDMA_CH2_5_IRQHandler + B . + + END diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/IAR/startup_ht32f5xxxx_iar_02.s b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/IAR/startup_ht32f5xxxx_iar_02.s new file mode 100644 index 0000000000..90e0090688 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/IAR/startup_ht32f5xxxx_iar_02.s @@ -0,0 +1,275 @@ +;/*---------------------------------------------------------------------------------------------------------*/ +;/* Holtek Semiconductor Inc. */ +;/* */ +;/* Copyright (C) Holtek Semiconductor Inc. */ +;/* All rights reserved. */ +;/* */ +;/*----------------------------------------------------------------------------------------------------------- +; File Name : startup_ht32f5xxxx_iar_02.s +; Version : $Rev:: 7119 $ +; Date : $Date:: 2023-08-15 #$ +; Description : Startup code. +;-----------------------------------------------------------------------------------------------------------*/ + +; Supported Device +; ======================================== +; HT32F50220, HT32F50230 +; HT32F50231, HT32F50241 +; HT50F32002 +; HT32F59041 +; HF5032 +; HT32F61641 +; HT32F59046 +; HT32F61041 + +;/* <<< Use Configuration Wizard in Context Menu >>> */ + +;// HT32 Device +;// <0=> By Project Asm Define +;// <7=> HT32F50220/30 +;// <8=> HT32F50231/41 +;// <7=> HT50F32002 +;// <8=> HT32F59041 +;// <7=> HF5032 +;// <8=> HT32F61641 +;// <8=> HT32F59046 +;// <8=> HT32F61041 +USE_HT32_CHIP_SET EQU 0 + +_HT32FWID EQU 0xFFFFFFFF +;_HT32FWID EQU 0x00050220 +;_HT32FWID EQU 0x00050230 +;_HT32FWID EQU 0x00050231 +;_HT32FWID EQU 0x00050241 +;_HT32FWID EQU 0x00032002 +;_HT32FWID EQU 0x00059041 +;_HT32FWID EQU 0x000F5032 +;_HT32FWID EQU 0x00061641 +;_HT32FWID EQU 0x00059046 +;_HT32FWID EQU 0x00061041 + +HT32F50220_30 EQU 7 +HT32F50231_41 EQU 8 +HT50F32002 EQU 7 +HT32F59041 EQU 8 +HF5032 EQU 7 +HT32F61641 EQU 8 +HT32F59046 EQU 8 +HT32F61041 EQU 8 + + IF USE_HT32_CHIP_SET=0 + ELSE + #undef USE_HT32_CHIP + #define USE_HT32_CHIP USE_HT32_CHIP_SET + ENDIF + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + EXTERN SystemInit + PUBLIC __vector_table + +;******************************************************************************* +; Fill-up the Vector Table entries with the exceptions ISR address +;******************************************************************************* + DATA +_RESERVED EQU 0xFFFFFFFF +__vector_table + DCD sfe(CSTACK) ; ---, 00, 0x000, Top address of Stack + DCD Reset_Handler ; ---, 01, 0x004, Reset Handler + DCD NMI_Handler ; -14, 02, 0x008, NMI Handler + DCD HardFault_Handler ; -13, 03, 0x00C, Hard Fault Handler + DCD _RESERVED ; ---, 04, 0x010, Reserved + DCD _RESERVED ; ---, 05, 0x014, Reserved + DCD _RESERVED ; ---, 06, 0x018, Reserved + DCD _RESERVED ; ---, 07, 0x01C, Reserved + DCD _HT32FWID ; ---, 08, 0x020, Reserved + DCD _RESERVED ; ---, 09, 0x024, Reserved + DCD _RESERVED ; ---, 10, 0x028, Reserved + DCD SVC_Handler ; -05, 11, 0x02C, SVC Handler + DCD _RESERVED ; ---, 12, 0x030, Reserved + DCD _RESERVED ; ---, 13, 0x034, Reserved + DCD PendSV_Handler ; -02, 14, 0x038, PendSV Handler + DCD SysTick_Handler ; -01, 15, 0x03C, SysTick Handler + + ; External Interrupt Handler + DCD LVD_BOD_IRQHandler ; 00, 16, 0x040, + DCD RTC_IRQHandler ; 01, 17, 0x044, + DCD FLASH_IRQHandler ; 02, 18, 0x048, + DCD EVWUP_IRQHandler ; 03, 19, 0x04C, + DCD EXTI0_1_IRQHandler ; 04, 20, 0x050, + DCD EXTI2_3_IRQHandler ; 05, 21, 0x054, + DCD EXTI4_15_IRQHandler ; 06, 22, 0x058, + DCD _RESERVED ; 07, 23, 0x05C, + DCD ADC_IRQHandler ; 08, 24, 0x060, + DCD _RESERVED ; 09, 25, 0x064, + IF (USE_HT32_CHIP=HT32F50220_30) + DCD _RESERVED ; 10, 26, 0x068, + ELSE + DCD MCTM0_IRQHandler ; 10, 26, 0x068, + ENDIF + DCD _RESERVED ; 11, 27, 0x06C, + DCD GPTM0_IRQHandler ; 12, 28, 0x070, + DCD _RESERVED ; 13, 29, 0x074, + DCD _RESERVED ; 14, 30, 0x078, + DCD PWM0_IRQHandler ; 15, 31, 0x07C, + DCD PWM1_IRQHandler ; 16, 32, 0x080, + DCD BFTM0_IRQHandler ; 17, 33, 0x084, + IF (USE_HT32_CHIP=HT32F50220_30) + DCD _RESERVED ; 18, 34, 0x088, + ELSE + DCD BFTM1_IRQHandler ; 18, 34, 0x088, + ENDIF + DCD I2C0_IRQHandler ; 19, 35, 0x08C, + IF (USE_HT32_CHIP=HT32F50220_30) + DCD _RESERVED ; 20, 36, 0x090, + ELSE + DCD I2C1_IRQHandler ; 20, 36, 0x090, + ENDIF + DCD SPI0_IRQHandler ; 21, 37, 0x094, + DCD SPI1_IRQHandler ; 22, 38, 0x098, + IF (USE_HT32_CHIP=HT32F50220_30) + DCD _RESERVED ; 23, 39, 0x09C, + ELSE + DCD USART0_IRQHandler ; 23, 39, 0x09C, + ENDIF + DCD _RESERVED ; 24, 40, 0x0A0, + DCD UART0_IRQHandler ; 25, 41, 0x0A4, + DCD UART1_IRQHandler ; 26, 42, 0x0A8, + + THUMB + + PUBWEAK Reset_Handler + SECTION .text:CODE:REORDER:NOROOT(2) +Reset_Handler + LDR R0, =BootProcess + BLX R0 + LDR R0, =SystemInit + BLX R0 + LDR R0, =__iar_program_start + BX R0 + +BootProcess + LDR R0, =0x40080300 + LDR R1,[R0, #0x10] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x14] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x18] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x1C] + CMP R1, #0 + BEQ BP2 +BP1 LDR R0, =0x40080180 + LDR R1,[R0, #0xC] + LSLS R1, R1, #4 + LSRS R1, R1, #20 + CMP R1, #0 + BEQ BP3 + CMP R1, #5 + BEQ BP3 + CMP R1, #6 + BEQ BP3 +BP2 DSB + LDR R0, =0x20000000 + LDR R1, =0x05fa0004 + STR R1, [R0] + LDR R1, =0xe000ed00 + LDR R0, =0x05fa0004 + STR R0, [R1, #0xC] + DSB + B . +BP3 LDR R0, =0x20000000 + LDR R1, [R0] + LDR R0, =0x05fa0004 + CMP R0, R1 + BEQ BP4 + BX LR +BP4 LDR R0, =0x40088100 + LDR R1, =0x00000001 + STR R1, [R0] + LDR R0, =0x20000000 + LDR R1, =0x0 + STR R1, [R0] + BX LR + + PUBWEAK NMI_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +NMI_Handler + B . + + PUBWEAK HardFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +HardFault_Handler + B . + + PUBWEAK SVC_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SVC_Handler + B . + + PUBWEAK PendSV_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PendSV_Handler + B . + + PUBWEAK SysTick_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SysTick_Handler + B . + + + PUBWEAK LVD_BOD_IRQHandler + PUBWEAK RTC_IRQHandler + PUBWEAK FLASH_IRQHandler + PUBWEAK EVWUP_IRQHandler + PUBWEAK EXTI0_1_IRQHandler + PUBWEAK EXTI2_3_IRQHandler + PUBWEAK EXTI4_15_IRQHandler + PUBWEAK ADC_IRQHandler + PUBWEAK MCTM0_IRQHandler + PUBWEAK GPTM0_IRQHandler + PUBWEAK PWM0_IRQHandler + PUBWEAK PWM1_IRQHandler + PUBWEAK BFTM0_IRQHandler + PUBWEAK BFTM1_IRQHandler + PUBWEAK I2C0_IRQHandler + PUBWEAK I2C1_IRQHandler + PUBWEAK SPI0_IRQHandler + PUBWEAK SPI1_IRQHandler + PUBWEAK USART0_IRQHandler + PUBWEAK UART0_IRQHandler + PUBWEAK UART1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +LVD_BOD_IRQHandler +RTC_IRQHandler +FLASH_IRQHandler +EVWUP_IRQHandler +EXTI0_1_IRQHandler +EXTI2_3_IRQHandler +EXTI4_15_IRQHandler +ADC_IRQHandler +MCTM0_IRQHandler +GPTM0_IRQHandler +PWM0_IRQHandler +PWM1_IRQHandler +BFTM0_IRQHandler +BFTM1_IRQHandler +I2C0_IRQHandler +I2C1_IRQHandler +SPI0_IRQHandler +SPI1_IRQHandler +USART0_IRQHandler +UART0_IRQHandler +UART1_IRQHandler + B . + + END diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/IAR/startup_ht32f5xxxx_iar_03.s b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/IAR/startup_ht32f5xxxx_iar_03.s new file mode 100644 index 0000000000..d33333bd3a --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/IAR/startup_ht32f5xxxx_iar_03.s @@ -0,0 +1,351 @@ +;/*---------------------------------------------------------------------------------------------------------*/ +;/* Holtek Semiconductor Inc. */ +;/* */ +;/* Copyright (C) Holtek Semiconductor Inc. */ +;/* All rights reserved. */ +;/* */ +;/*----------------------------------------------------------------------------------------------------------- +; File Name : startup_ht32f5xxxx_iar_03.s +; Version : $Rev:: 6887 $ +; Date : $Date:: 2023-05-05 #$ +; Description : Startup code. +;-----------------------------------------------------------------------------------------------------------*/ + +; Supported Device +; ======================================== +; HT32F0008 +; HT32F52142 +; HT32F52344, HT32F52354 +; HT32F52357, HT32F52367 +; HT50F3200T + +;/* <<< Use Configuration Wizard in Context Menu >>> */ + +;// HT32 Device +;// <0=> By Project Asm Define +;// <6=> HT32F0008 +;// <6=> HT32F52142 +;// <9=> HT32F52344/54 +;// <11=> HT32F52357/67 +;// <11=> HT50F3200T +USE_HT32_CHIP_SET EQU 0 + +_HT32FWID EQU 0xFFFFFFFF +;_HT32FWID EQU 0x00000008 +;_HT32FWID EQU 0x00052142 +;_HT32FWID EQU 0x00052344 +;_HT32FWID EQU 0x00052354 +;_HT32FWID EQU 0x00052357 +;_HT32FWID EQU 0x00052367 +;_HT32FWID EQU 0x0003200F + +HT32F0008 EQU 6 +HT32F52142 EQU 6 +HT32F52344_54 EQU 9 +HT32F52357_67 EQU 11 +HT50F3200T EQU 11 + + IF USE_HT32_CHIP_SET=0 + ELSE + #undef USE_HT32_CHIP + #define USE_HT32_CHIP USE_HT32_CHIP_SET + ENDIF + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + EXTERN SystemInit + PUBLIC __vector_table + +;******************************************************************************* +; Fill-up the Vector Table entries with the exceptions ISR address +;******************************************************************************* + DATA +_RESERVED EQU 0xFFFFFFFF +__vector_table + DCD sfe(CSTACK) ; ---, 00, 0x000, Top address of Stack + DCD Reset_Handler ; ---, 01, 0x004, Reset Handler + DCD NMI_Handler ; -14, 02, 0x008, NMI Handler + DCD HardFault_Handler ; -13, 03, 0x00C, Hard Fault Handler + DCD _RESERVED ; ---, 04, 0x010, Reserved + DCD _RESERVED ; ---, 05, 0x014, Reserved + DCD _RESERVED ; ---, 06, 0x018, Reserved + DCD _RESERVED ; ---, 07, 0x01C, Reserved + DCD _HT32FWID ; ---, 08, 0x020, Reserved + DCD _RESERVED ; ---, 09, 0x024, Reserved + DCD _RESERVED ; ---, 10, 0x028, Reserved + DCD SVC_Handler ; -05, 11, 0x02C, SVC Handler + DCD _RESERVED ; ---, 12, 0x030, Reserved + DCD _RESERVED ; ---, 13, 0x034, Reserved + DCD PendSV_Handler ; -02, 14, 0x038, PendSV Handler + DCD SysTick_Handler ; -01, 15, 0x03C, SysTick Handler + + ; External Interrupt Handler + DCD LVD_BOD_IRQHandler ; 00, 16, 0x040, + DCD RTC_IRQHandler ; 01, 17, 0x044, + DCD FLASH_IRQHandler ; 02, 18, 0x048, + DCD EVWUP_IRQHandler ; 03, 19, 0x04C, + DCD EXTI0_1_IRQHandler ; 04, 20, 0x050, + DCD EXTI2_3_IRQHandler ; 05, 21, 0x054, + DCD EXTI4_15_IRQHandler ; 06, 22, 0x058, + IF (USE_HT32_CHIP=HT32F0008) + DCD _RESERVED ; 07, 23, 0x05C, + ENDIF + IF (USE_HT32_CHIP=HT32F52344_54) + DCD COMP_IRQHandler ; 07, 23, 0x05C, + ENDIF + IF (USE_HT32_CHIP=HT32F52357_67) + DCD COMP_DAC_IRQHandler ; 07, 23, 0x05C, + ENDIF + IF (USE_HT32_CHIP=HT32F0008) + DCD _RESERVED ; 08, 24, 0x060, + ELSE + DCD ADC_IRQHandler ; 08, 24, 0x060, + ENDIF + IF (USE_HT32_CHIP=HT32F52357_67) + DCD AES_IRQHandler ; 09, 25, 0x064, + ELSE + DCD _RESERVED ; 09, 25, 0x064, + ENDIF + IF (USE_HT32_CHIP=HT32F0008) + DCD _RESERVED ; 10, 26, 0x068, + ELSE + DCD MCTM0_IRQHandler ; 10, 26, 0x068, + ENDIF + IF (USE_HT32_CHIP=HT32F52357_67) + DCD QSPI_IRQHandler ; 11, 27, 0x06C, + ELSE + DCD _RESERVED ; 11, 27, 0x06C, + ENDIF + DCD GPTM0_IRQHandler ; 12, 28, 0x070, + IF (USE_HT32_CHIP=HT32F0008) + DCD _RESERVED ; 13, 29, 0x074, + DCD _RESERVED ; 14, 30, 0x078, + ELSE + DCD SCTM0_IRQHandler ; 13, 29, 0x074, + DCD SCTM1_IRQHandler ; 14, 30, 0x078, + ENDIF + IF (USE_HT32_CHIP=HT32F0008) || (USE_HT32_CHIP=HT32F52357_67) + DCD PWM0_IRQHandler ; 15, 31, 0x07C, + DCD PWM1_IRQHandler ; 16, 32, 0x080, + ENDIF + IF (USE_HT32_CHIP=HT32F52344_54) + DCD _RESERVED ; 15, 31, 0x07C, + DCD _RESERVED ; 16, 32, 0x080, + ENDIF + DCD BFTM0_IRQHandler ; 17, 33, 0x084, + DCD BFTM1_IRQHandler ; 18, 34, 0x088, + DCD I2C0_IRQHandler ; 19, 35, 0x08C, + IF (USE_HT32_CHIP=HT32F0008) || (USE_HT32_CHIP=HT32F52344_54) + DCD _RESERVED ; 20, 36, 0x090, + ELSE + DCD I2C1_IRQHandler ; 20, 36, 0x090, + ENDIF + DCD SPI0_IRQHandler ; 21, 37, 0x094, + IF (USE_HT32_CHIP=HT32F0008) + DCD _RESERVED ; 22, 38, 0x098, + ELSE + DCD SPI1_IRQHandler ; 22, 38, 0x098, + ENDIF + IF (USE_HT32_CHIP=HT32F52344_54) + DCD _RESERVED ; 23, 39, 0x09C, + ELSE + DCD USART0_IRQHandler ; 23, 39, 0x09C, + ENDIF + IF (USE_HT32_CHIP=HT32F0008) + DCD _RESERVED ; 24, 40, 0x0A0, + DCD UART0_IRQHandler ; 25, 41, 0x0A4, + DCD _RESERVED ; 26, 42, 0x0A8, + ENDIF + IF (USE_HT32_CHIP=HT32F52344_54) + DCD _RESERVED ; 24, 40, 0x0A0, + DCD UART0_IRQHandler ; 25, 41, 0x0A4, + DCD UART1_IRQHandler ; 26, 42, 0x0A8, + ENDIF + IF (USE_HT32_CHIP=HT32F52357_67) + DCD USART1_IRQHandler ; 24, 40, 0x0A0, + DCD UART0_UART2_IRQHandler ; 25, 41, 0x0A4, + DCD UART1_UART3_IRQHandler ; 26, 42, 0x0A8, + ENDIF + IF (USE_HT32_CHIP=HT32F52357_67) + DCD SCI_IRQHandler ; 27, 43, 0xAC, + ELSE + DCD _RESERVED ; 27, 43, 0xAC, + ENDIF + IF (USE_HT32_CHIP=HT32F0008) + DCD AES_IRQHandler ; 28, 44, 0x0B0, + ENDIF + IF (USE_HT32_CHIP=HT32F52344_54) + DCD _RESERVED ; 28, 44, 0x0B0, + ENDIF + IF (USE_HT32_CHIP=HT32F52357_67) + DCD I2S_IRQHandler ; 28, 44, 0x0B0, + ENDIF + DCD USB_IRQHandler ; 29, 45, 0x0B4, + DCD PDMA_CH0_1_IRQHandler ; 30, 46, 0x0B8, + DCD PDMA_CH2_5_IRQHandler ; 31, 47, 0x0BC, + + THUMB + + PUBWEAK Reset_Handler + SECTION .text:CODE:REORDER:NOROOT(2) +Reset_Handler + LDR R0, =BootProcess + BLX R0 + LDR R0, =SystemInit + BLX R0 + LDR R0, =__iar_program_start + BX R0 + +BootProcess + LDR R0, =0x40080300 + LDR R1,[R0, #0x10] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x14] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x18] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x1C] + CMP R1, #0 + BEQ BP2 +BP1 LDR R0, =0x40080180 + LDR R1,[R0, #0xC] + LSLS R1, R1, #4 + LSRS R1, R1, #20 + CMP R1, #0 + BEQ BP3 + CMP R1, #5 + BEQ BP3 + CMP R1, #6 + BEQ BP3 +BP2 DSB + LDR R0, =0x20000000 + LDR R1, =0x05fa0004 + STR R1, [R0] + LDR R1, =0xe000ed00 + LDR R0, =0x05fa0004 + STR R0, [R1, #0xC] + DSB + B . +BP3 LDR R0, =0x20000000 + LDR R1, [R0] + LDR R0, =0x05fa0004 + CMP R0, R1 + BEQ BP4 + BX LR +BP4 LDR R0, =0x40088100 + LDR R1, =0x00000001 + STR R1, [R0] + LDR R0, =0x20000000 + LDR R1, =0x0 + STR R1, [R0] + BX LR + + PUBWEAK NMI_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +NMI_Handler + B . + + PUBWEAK HardFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +HardFault_Handler + B . + + PUBWEAK SVC_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SVC_Handler + B . + + PUBWEAK PendSV_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PendSV_Handler + B . + + PUBWEAK SysTick_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SysTick_Handler + B . + + + PUBWEAK LVD_BOD_IRQHandler + PUBWEAK RTC_IRQHandler + PUBWEAK FLASH_IRQHandler + PUBWEAK EVWUP_IRQHandler + PUBWEAK EXTI0_1_IRQHandler + PUBWEAK EXTI2_3_IRQHandler + PUBWEAK EXTI4_15_IRQHandler + PUBWEAK COMP_IRQHandler + PUBWEAK COMP_DAC_IRQHandler + PUBWEAK ADC_IRQHandler + PUBWEAK MCTM0_IRQHandler + PUBWEAK GPTM0_IRQHandler + PUBWEAK SCTM0_IRQHandler + PUBWEAK SCTM1_IRQHandler + PUBWEAK PWM0_IRQHandler + PUBWEAK PWM1_IRQHandler + PUBWEAK BFTM0_IRQHandler + PUBWEAK BFTM1_IRQHandler + PUBWEAK I2C0_IRQHandler + PUBWEAK I2C1_IRQHandler + PUBWEAK SPI0_IRQHandler + PUBWEAK SPI1_IRQHandler + PUBWEAK QSPI_IRQHandler + PUBWEAK USART0_IRQHandler + PUBWEAK USART1_IRQHandler + PUBWEAK UART0_IRQHandler + PUBWEAK UART1_IRQHandler + PUBWEAK UART0_UART2_IRQHandler + PUBWEAK UART1_UART3_IRQHandler + PUBWEAK SCI_IRQHandler + PUBWEAK I2S_IRQHandler + PUBWEAK AES_IRQHandler + PUBWEAK USB_IRQHandler + PUBWEAK PDMA_CH0_1_IRQHandler + PUBWEAK PDMA_CH2_5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +LVD_BOD_IRQHandler +RTC_IRQHandler +FLASH_IRQHandler +EVWUP_IRQHandler +EXTI0_1_IRQHandler +EXTI2_3_IRQHandler +EXTI4_15_IRQHandler +COMP_IRQHandler +COMP_DAC_IRQHandler +ADC_IRQHandler +MCTM0_IRQHandler +GPTM0_IRQHandler +SCTM0_IRQHandler +SCTM1_IRQHandler +PWM0_IRQHandler +PWM1_IRQHandler +BFTM0_IRQHandler +BFTM1_IRQHandler +I2C0_IRQHandler +I2C1_IRQHandler +SPI0_IRQHandler +SPI1_IRQHandler +QSPI_IRQHandler +USART0_IRQHandler +USART1_IRQHandler +UART0_IRQHandler +UART1_IRQHandler +UART0_UART2_IRQHandler +UART1_UART3_IRQHandler +SCI_IRQHandler +I2S_IRQHandler +AES_IRQHandler +USB_IRQHandler +PDMA_CH0_1_IRQHandler +PDMA_CH2_5_IRQHandler + B . + + END diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/IAR/startup_ht32f5xxxx_iar_05.s b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/IAR/startup_ht32f5xxxx_iar_05.s new file mode 100644 index 0000000000..2d5a99264b --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/IAR/startup_ht32f5xxxx_iar_05.s @@ -0,0 +1,298 @@ +;/*---------------------------------------------------------------------------------------------------------*/ +;/* Holtek Semiconductor Inc. */ +;/* */ +;/* Copyright (C) Holtek Semiconductor Inc. */ +;/* All rights reserved. */ +;/* */ +;/*----------------------------------------------------------------------------------------------------------- +; File Name : startup_ht32f5xxxx_iar_05.s +; Version : $Rev:: 6993 $ +; Date : $Date:: 2023-06-26 #$ +; Description : Startup code. +;-----------------------------------------------------------------------------------------------------------*/ + +; Supported Device +; ======================================== +; HT32F57331, HT32F57341 +; HT32F57342, HT32F57352 +; HT32F59741 +; HT32F5828 +; HT32F67742 +; HT32F59746 + +;/* <<< Use Configuration Wizard in Context Menu >>> */ + +;// HT32 Device +;// <0=> By Project Asm Define +;// <13=> HT32F57331/41 +;// <14=> HT32F57342/52 +;// <13=> HT32F59741 +;// <14=> HT32F5828 +;// <13=> HT32F67742 +;// <13=> HT32F59746 +USE_HT32_CHIP_SET EQU 0 + +_HT32FWID EQU 0xFFFFFFFF +;_HT32FWID EQU 0x00057331 +;_HT32FWID EQU 0x00057341 +;_HT32FWID EQU 0x00057342 +;_HT32FWID EQU 0x00057352 +;_HT32FWID EQU 0x00059741 +;_HT32FWID EQU 0x00005828 +;_HT32FWID EQU 0x00067742 +;_HT32FWID EQU 0x00059746 + +HT32F57331_41 EQU 13 +HT32F57342_52 EQU 14 +HT32F59741 EQU 13 +HT32F5828 EQU 14 +HT32F67742 EQU 13 +HT32F59746 EQU 13 + + IF USE_HT32_CHIP_SET=0 + ELSE + #undef USE_HT32_CHIP + #define USE_HT32_CHIP USE_HT32_CHIP_SET + ENDIF + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + EXTERN SystemInit + PUBLIC __vector_table + +;******************************************************************************* +; Fill-up the Vector Table entries with the exceptions ISR address +;******************************************************************************* + DATA +_RESERVED EQU 0xFFFFFFFF +__vector_table + DCD sfe(CSTACK) ; ---, 00, 0x000, Top address of Stack + DCD Reset_Handler ; ---, 01, 0x004, Reset Handler + DCD NMI_Handler ; -14, 02, 0x008, NMI Handler + DCD HardFault_Handler ; -13, 03, 0x00C, Hard Fault Handler + DCD _RESERVED ; ---, 04, 0x010, Reserved + DCD _RESERVED ; ---, 05, 0x014, Reserved + DCD _RESERVED ; ---, 06, 0x018, Reserved + DCD _RESERVED ; ---, 07, 0x01C, Reserved + DCD _HT32FWID ; ---, 08, 0x020, Reserved + DCD _RESERVED ; ---, 09, 0x024, Reserved + DCD _RESERVED ; ---, 10, 0x028, Reserved + DCD SVC_Handler ; -05, 11, 0x02C, SVC Handler + DCD _RESERVED ; ---, 12, 0x030, Reserved + DCD _RESERVED ; ---, 13, 0x034, Reserved + DCD PendSV_Handler ; -02, 14, 0x038, PendSV Handler + DCD SysTick_Handler ; -01, 15, 0x03C, SysTick Handler + + ; External Interrupt Handler + DCD LVD_BOD_IRQHandler ; 00, 16, 0x040, + DCD RTC_IRQHandler ; 01, 17, 0x044, + DCD FLASH_IRQHandler ; 02, 18, 0x048, + DCD EVWUP_IRQHandler ; 03, 19, 0x04C, + DCD EXTI0_1_IRQHandler ; 04, 20, 0x050, + DCD EXTI2_3_IRQHandler ; 05, 21, 0x054, + DCD EXTI4_15_IRQHandler ; 06, 22, 0x058, + IF (USE_HT32_CHIP=HT32F57331_41) + DCD _RESERVED ; 07, 23, 0x05C, + ENDIF + IF (USE_HT32_CHIP=HT32F57342_52) + DCD COMP_DAC_IRQHandler ; 07, 23, 0x05C, + ENDIF + DCD ADC_IRQHandler ; 08, 24, 0x060, + IF (USE_HT32_CHIP=HT32F57331_41) + DCD _RESERVED ; 09, 25, 0x064, + ENDIF + IF (USE_HT32_CHIP=HT32F57342_52) + DCD AES_IRQHandler ; 09, 25, 0x064, + ENDIF + DCD _RESERVED ; 10, 26, 0x068, + DCD LCD_IRQHandler ; 11, 27, 0x06C, + DCD GPTM0_IRQHandler ; 12, 28, 0x070, + IF (USE_HT32_CHIP=HT32F57331_41) + DCD _RESERVED ; 13, 29, 0x074, + DCD _RESERVED ; 14, 30, 0x078, + ENDIF + IF (USE_HT32_CHIP=HT32F57342_52) + DCD SCTM0_IRQHandler ; 13, 29, 0x074, + DCD SCTM1_IRQHandler ; 14, 30, 0x078, + ENDIF + DCD PWM0_IRQHandler ; 15, 31, 0x07C, + DCD PWM1_IRQHandler ; 16, 32, 0x080, + DCD BFTM0_IRQHandler ; 17, 33, 0x084, + DCD BFTM1_IRQHandler ; 18, 34, 0x088, + DCD I2C0_IRQHandler ; 19, 35, 0x08C, + DCD I2C1_IRQHandler ; 20, 36, 0x090, + DCD SPI0_IRQHandler ; 21, 37, 0x094, + DCD SPI1_IRQHandler ; 22, 38, 0x098, + DCD USART0_IRQHandler ; 23, 39, 0x09C, + DCD _RESERVED ; 24, 40, 0x0A0, + DCD UART0_IRQHandler ; 25, 41, 0x0A4, + DCD UART1_IRQHandler ; 26, 42, 0x0A8, + DCD SCI_IRQHandler ; 27, 43, 0x0AC, + DCD I2S_IRQHandler ; 28, 44, 0x0B0, + DCD USB_IRQHandler ; 29, 45, 0x0B4, + IF (USE_HT32_CHIP=HT32F57331_41) + DCD _RESERVED ; 30, 46, 0x0B8, + DCD _RESERVED ; 31, 47, 0x0BC, + ENDIF + IF (USE_HT32_CHIP=HT32F57342_52) + DCD PDMA_CH0_1_IRQHandler ; 30, 46, 0x0B8, + DCD PDMA_CH2_5_IRQHandler ; 31, 47, 0x0BC, + ENDIF + + THUMB + + PUBWEAK Reset_Handler + SECTION .text:CODE:REORDER:NOROOT(2) +Reset_Handler + LDR R0, =BootProcess + BLX R0 + LDR R0, =SystemInit + BLX R0 + LDR R0, =__iar_program_start + BX R0 + +BootProcess + LDR R0, =0x40080300 + LDR R1,[R0, #0x10] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x14] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x18] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x1C] + CMP R1, #0 + BEQ BP2 +BP1 LDR R0, =0x40080180 + LDR R1,[R0, #0xC] + LSLS R1, R1, #4 + LSRS R1, R1, #20 + CMP R1, #0 + BEQ BP3 + CMP R1, #5 + BEQ BP3 + CMP R1, #6 + BEQ BP3 +BP2 DSB + LDR R0, =0x20000000 + LDR R1, =0x05fa0004 + STR R1, [R0] + LDR R1, =0xe000ed00 + LDR R0, =0x05fa0004 + STR R0, [R1, #0xC] + DSB + B . +BP3 LDR R0, =0x20000000 + LDR R1, [R0] + LDR R0, =0x05fa0004 + CMP R0, R1 + BEQ BP4 + BX LR +BP4 LDR R0, =0x40088100 + LDR R1, =0x00000001 + STR R1, [R0] + LDR R0, =0x20000000 + LDR R1, =0x0 + STR R1, [R0] + BX LR + + PUBWEAK NMI_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +NMI_Handler + B . + + PUBWEAK HardFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +HardFault_Handler + B . + + PUBWEAK SVC_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SVC_Handler + B . + + PUBWEAK PendSV_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PendSV_Handler + B . + + PUBWEAK SysTick_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SysTick_Handler + B . + + + PUBWEAK LVD_BOD_IRQHandler + PUBWEAK RTC_IRQHandler + PUBWEAK FLASH_IRQHandler + PUBWEAK EVWUP_IRQHandler + PUBWEAK EXTI0_1_IRQHandler + PUBWEAK EXTI2_3_IRQHandler + PUBWEAK EXTI4_15_IRQHandler + PUBWEAK COMP_DAC_IRQHandler + PUBWEAK ADC_IRQHandler + PUBWEAK AES_IRQHandler + PUBWEAK LCD_IRQHandler + PUBWEAK GPTM0_IRQHandler + PUBWEAK SCTM0_IRQHandler + PUBWEAK SCTM1_IRQHandler + PUBWEAK PWM0_IRQHandler + PUBWEAK PWM1_IRQHandler + PUBWEAK BFTM0_IRQHandler + PUBWEAK BFTM1_IRQHandler + PUBWEAK I2C0_IRQHandler + PUBWEAK I2C1_IRQHandler + PUBWEAK SPI0_IRQHandler + PUBWEAK SPI1_IRQHandler + PUBWEAK USART0_IRQHandler + PUBWEAK USART1_IRQHandler + PUBWEAK UART0_IRQHandler + PUBWEAK UART1_IRQHandler + PUBWEAK SCI_IRQHandler + PUBWEAK I2S_IRQHandler + PUBWEAK USB_IRQHandler + PUBWEAK PDMA_CH0_1_IRQHandler + PUBWEAK PDMA_CH2_5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +LVD_BOD_IRQHandler +RTC_IRQHandler +FLASH_IRQHandler +EVWUP_IRQHandler +EXTI0_1_IRQHandler +EXTI2_3_IRQHandler +EXTI4_15_IRQHandler +COMP_DAC_IRQHandler +ADC_IRQHandler +AES_IRQHandler +LCD_IRQHandler +GPTM0_IRQHandler +SCTM0_IRQHandler +SCTM1_IRQHandler +PWM0_IRQHandler +PWM1_IRQHandler +BFTM0_IRQHandler +BFTM1_IRQHandler +I2C0_IRQHandler +I2C1_IRQHandler +SPI0_IRQHandler +SPI1_IRQHandler +USART0_IRQHandler +USART1_IRQHandler +UART0_IRQHandler +UART1_IRQHandler +SCI_IRQHandler +I2S_IRQHandler +USB_IRQHandler +PDMA_CH0_1_IRQHandler +PDMA_CH2_5_IRQHandler + B . + + END diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/IAR/startup_ht32f5xxxx_iar_06.s b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/IAR/startup_ht32f5xxxx_iar_06.s new file mode 100644 index 0000000000..fc26530cff --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/IAR/startup_ht32f5xxxx_iar_06.s @@ -0,0 +1,245 @@ +;/*---------------------------------------------------------------------------------------------------------*/ +;/* Holtek Semiconductor Inc. */ +;/* */ +;/* Copyright (C) Holtek Semiconductor Inc. */ +;/* All rights reserved. */ +;/* */ +;/*----------------------------------------------------------------------------------------------------------- +; File Name : startup_ht32f5xxxx_iar_06.s +; Version : $Rev:: 4123 $ +; Date : $Date:: 2019-07-23 #$ +; Description : Startup code. +;-----------------------------------------------------------------------------------------------------------*/ + +; Supported Device +; ======================================== +; HT32F50343 + +;/* <<< Use Configuration Wizard in Context Menu >>> */ + +;// HT32 Device +;// <0=> By Project Asm Define +;// <15=> HT32F50343 +USE_HT32_CHIP_SET EQU 0 + +_HT32FWID EQU 0xFFFFFFFF +;_HT32FWID EQU 0x00050343 + +HT32F50343 EQU 15 + + IF USE_HT32_CHIP_SET=0 + ELSE + #undef USE_HT32_CHIP + #define USE_HT32_CHIP USE_HT32_CHIP_SET + ENDIF + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + EXTERN SystemInit + PUBLIC __vector_table + +;******************************************************************************* +; Fill-up the Vector Table entries with the exceptions ISR address +;******************************************************************************* + DATA +_RESERVED EQU 0xFFFFFFFF +__vector_table + DCD sfe(CSTACK) ; ---, 00, 0x000, Top address of Stack + DCD Reset_Handler ; ---, 01, 0x004, Reset Handler + DCD NMI_Handler ; -14, 02, 0x008, NMI Handler + DCD HardFault_Handler ; -13, 03, 0x00C, Hard Fault Handler + DCD _RESERVED ; ---, 04, 0x010, Reserved + DCD _RESERVED ; ---, 05, 0x014, Reserved + DCD _RESERVED ; ---, 06, 0x018, Reserved + DCD _RESERVED ; ---, 07, 0x01C, Reserved + DCD _HT32FWID ; ---, 08, 0x020, Reserved + DCD _RESERVED ; ---, 09, 0x024, Reserved + DCD _RESERVED ; ---, 10, 0x028, Reserved + DCD SVC_Handler ; -05, 11, 0x02C, SVC Handler + DCD _RESERVED ; ---, 12, 0x030, Reserved + DCD _RESERVED ; ---, 13, 0x034, Reserved + DCD PendSV_Handler ; -02, 14, 0x038, PendSV Handler + DCD SysTick_Handler ; -01, 15, 0x03C, SysTick Handler + + ; External Interrupt Handler + DCD LVD_BOD_IRQHandler ; 00, 16, 0x040, + DCD RTC_IRQHandler ; 01, 17, 0x044, + DCD FLASH_IRQHandler ; 02, 18, 0x048, + DCD EVWUP_IRQHandler ; 03, 19, 0x04C, + DCD EXTI0_1_IRQHandler ; 04, 20, 0x050, + DCD EXTI2_3_IRQHandler ; 05, 21, 0x054, + DCD EXTI4_15_IRQHandler ; 06, 22, 0x058, + DCD _RESERVED ; 07, 23, 0x05C, + DCD ADC_IRQHandler ; 08, 24, 0x060, + DCD _RESERVED ; 09, 25, 0x064, + DCD PWM2_IRQHandler ; 10, 26, 0x068, + DCD _RESERVED ; 11, 27, 0x06C, + DCD GPTM0_IRQHandler ; 12, 28, 0x070, + DCD SCTM0_IRQHandler ; 13, 29, 0x074, + DCD SCTM1_IRQHandler ; 14, 30, 0x078, + DCD PWM0_IRQHandler ; 15, 31, 0x07C, + DCD PWM1_IRQHandler ; 16, 32, 0x080, + DCD BFTM0_IRQHandler ; 17, 33, 0x084, + DCD BFTM1_IRQHandler ; 18, 34, 0x088, + DCD I2C0_IRQHandler ; 19, 35, 0x08C, + DCD I2C1_IRQHandler ; 20, 36, 0x090, + DCD SPI0_IRQHandler ; 21, 37, 0x094, + DCD SPI1_IRQHandler ; 22, 38, 0x098, + DCD _RESERVED ; 23, 39, 0x09C, + DCD _RESERVED ; 24, 40, 0x0A0, + DCD UART0_IRQHandler ; 25, 41, 0x0A4, + DCD UART1_IRQHandler ; 26, 42, 0x0A8, + DCD SLED0_IRQHandler ; 27, 43, 0x0AC, + DCD SLED1_IRQHandler ; 28, 44, 0x0B0, + DCD USB_IRQHandler ; 29, 45, 0x0B4, + DCD PDMA_CH0_1_IRQHandler ; 30, 46, 0x0B8, + DCD PDMA_CH2_5_IRQHandler ; 31, 47, 0x0BC, + + THUMB + + PUBWEAK Reset_Handler + SECTION .text:CODE:REORDER:NOROOT(2) +Reset_Handler + LDR R0, =BootProcess + BLX R0 + LDR R0, =SystemInit + BLX R0 + LDR R0, =__iar_program_start + BX R0 + +BootProcess + LDR R0, =0x40080300 + LDR R1,[R0, #0x10] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x14] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x18] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x1C] + CMP R1, #0 + BEQ BP2 +BP1 LDR R0, =0x40080180 + LDR R1,[R0, #0xC] + LSLS R1, R1, #4 + LSRS R1, R1, #20 + CMP R1, #0 + BEQ BP3 + CMP R1, #5 + BEQ BP3 + CMP R1, #6 + BEQ BP3 +BP2 DSB + LDR R0, =0x20000000 + LDR R1, =0x05fa0004 + STR R1, [R0] + LDR R1, =0xe000ed00 + LDR R0, =0x05fa0004 + STR R0, [R1, #0xC] + DSB + B . +BP3 LDR R0, =0x20000000 + LDR R1, [R0] + LDR R0, =0x05fa0004 + CMP R0, R1 + BEQ BP4 + BX LR +BP4 LDR R0, =0x40088100 + LDR R1, =0x00000001 + STR R1, [R0] + LDR R0, =0x20000000 + LDR R1, =0x0 + STR R1, [R0] + BX LR + + PUBWEAK NMI_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +NMI_Handler + B . + + PUBWEAK HardFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +HardFault_Handler + B . + + PUBWEAK SVC_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SVC_Handler + B . + + PUBWEAK PendSV_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PendSV_Handler + B . + + PUBWEAK SysTick_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SysTick_Handler + B . + + PUBWEAK LVD_BOD_IRQHandler + PUBWEAK RTC_IRQHandler + PUBWEAK FLASH_IRQHandler + PUBWEAK EVWUP_IRQHandler + PUBWEAK EXTI0_1_IRQHandler + PUBWEAK EXTI2_3_IRQHandler + PUBWEAK EXTI4_15_IRQHandler + PUBWEAK ADC_IRQHandler + PUBWEAK PWM2_IRQHandler + PUBWEAK GPTM0_IRQHandler + PUBWEAK SCTM0_IRQHandler + PUBWEAK SCTM1_IRQHandler + PUBWEAK PWM0_IRQHandler + PUBWEAK PWM1_IRQHandler + PUBWEAK BFTM0_IRQHandler + PUBWEAK BFTM1_IRQHandler + PUBWEAK I2C0_IRQHandler + PUBWEAK I2C1_IRQHandler + PUBWEAK SPI0_IRQHandler + PUBWEAK SPI1_IRQHandler + PUBWEAK UART0_IRQHandler + PUBWEAK UART1_IRQHandler + PUBWEAK SLED0_IRQHandler + PUBWEAK SLED1_IRQHandler + PUBWEAK USB_IRQHandler + PUBWEAK PDMA_CH0_1_IRQHandler + PUBWEAK PDMA_CH2_5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +LVD_BOD_IRQHandler +RTC_IRQHandler +FLASH_IRQHandler +EVWUP_IRQHandler +EXTI0_1_IRQHandler +EXTI2_3_IRQHandler +EXTI4_15_IRQHandler +ADC_IRQHandler +PWM2_IRQHandler +GPTM0_IRQHandler +SCTM0_IRQHandler +SCTM1_IRQHandler +PWM0_IRQHandler +PWM1_IRQHandler +BFTM0_IRQHandler +BFTM1_IRQHandler +I2C0_IRQHandler +I2C1_IRQHandler +SPI0_IRQHandler +SPI1_IRQHandler +UART0_IRQHandler +UART1_IRQHandler +SLED0_IRQHandler +SLED1_IRQHandler +USB_IRQHandler +PDMA_CH0_1_IRQHandler +PDMA_CH2_5_IRQHandler + B . + + END diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/IAR/startup_ht32f5xxxx_iar_07.s b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/IAR/startup_ht32f5xxxx_iar_07.s new file mode 100644 index 0000000000..dd22e9e2ed --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/IAR/startup_ht32f5xxxx_iar_07.s @@ -0,0 +1,252 @@ +;/*---------------------------------------------------------------------------------------------------------*/ +;/* Holtek Semiconductor Inc. */ +;/* */ +;/* Copyright (C) Holtek Semiconductor Inc. */ +;/* All rights reserved. */ +;/* */ +;/*----------------------------------------------------------------------------------------------------------- +; File Name : startup_ht32f5xxxx_iar_07.s +; Version : $Rev:: 5157 $ +; Date : $Date:: 2021-01-18 #$ +; Description : Startup code. +;-----------------------------------------------------------------------------------------------------------*/ + +; Supported Device +; ======================================== +; HT32F0006 +; HT32F61352 +; HT32F61355, HT32F61356, HT32F61357 + +;/* <<< Use Configuration Wizard in Context Menu >>> */ + +;// HT32 Device +;// <0=> By Project Asm Define +;// <10=> HT32F0006 +;// <10=> HT32F61352 +;// <17=> HT32F61355/56/57 +USE_HT32_CHIP_SET EQU 0 + +_HT32FWID EQU 0xFFFFFFFF +;_HT32FWID EQU 0x00000006 +;_HT32FWID EQU 0x00061352 +;_HT32FWID EQU 0x00061355 +;_HT32FWID EQU 0x00061356 +;_HT32FWID EQU 0x00061357 + +HT32F0006 EQU 10 +HT32F61352 EQU 10 +HT32F61355_56_57 EQU 17 + + IF USE_HT32_CHIP_SET=0 + ELSE + #undef USE_HT32_CHIP + #define USE_HT32_CHIP USE_HT32_CHIP_SET + ENDIF + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + EXTERN SystemInit + PUBLIC __vector_table + +;******************************************************************************* +; Fill-up the Vector Table entries with the exceptions ISR address +;******************************************************************************* + DATA +_RESERVED EQU 0xFFFFFFFF +__vector_table + DCD sfe(CSTACK) ; ---, 00, 0x000, Top address of Stack + DCD Reset_Handler ; ---, 01, 0x004, Reset Handler + DCD NMI_Handler ; -14, 02, 0x008, NMI Handler + DCD HardFault_Handler ; -13, 03, 0x00C, Hard Fault Handler + DCD _RESERVED ; ---, 04, 0x010, Reserved + DCD _RESERVED ; ---, 05, 0x014, Reserved + DCD _RESERVED ; ---, 06, 0x018, Reserved + DCD _RESERVED ; ---, 07, 0x01C, Reserved + DCD _HT32FWID ; ---, 08, 0x020, Reserved + DCD _RESERVED ; ---, 09, 0x024, Reserved + DCD _RESERVED ; ---, 10, 0x028, Reserved + DCD SVC_Handler ; -05, 11, 0x02C, SVC Handler + DCD _RESERVED ; ---, 12, 0x030, Reserved + DCD _RESERVED ; ---, 13, 0x034, Reserved + DCD PendSV_Handler ; -02, 14, 0x038, PendSV Handler + DCD SysTick_Handler ; -01, 15, 0x03C, SysTick Handler + + ; External Interrupt Handler + DCD LVD_BOD_IRQHandler ; 00, 16, 0x040, + DCD RTC_IRQHandler ; 01, 17, 0x044, + DCD FLASH_IRQHandler ; 02, 18, 0x048, + DCD EVWUP_IRQHandler ; 03, 19, 0x04C, + DCD EXTI0_1_IRQHandler ; 04, 20, 0x050, + DCD EXTI2_3_IRQHandler ; 05, 21, 0x054, + DCD EXTI4_15_IRQHandler ; 06, 22, 0x058, + DCD _RESERVED ; 07, 23, 0x05C, + DCD ADC_IRQHandler ; 08, 24, 0x060, + DCD _RESERVED ; 09, 25, 0x064, + DCD _RESERVED ; 10, 26, 0x068, + DCD _RESERVED ; 11, 27, 0x06C, + DCD GPTM0_IRQHandler ; 12, 28, 0x070, + DCD SCTM0_IRQHandler ; 13, 29, 0x074, + DCD SCTM1_IRQHandler ; 14, 30, 0x078, + DCD SCTM2_IRQHandler ; 15, 31, 0x07C, + DCD SCTM3_IRQHandler ; 16, 32, 0x080, + DCD BFTM0_IRQHandler ; 17, 33, 0x084, + DCD BFTM1_IRQHandler ; 18, 34, 0x088, + DCD I2C0_IRQHandler ; 19, 35, 0x08C, + DCD _RESERVED ; 20, 36, 0x090, + DCD SPI0_IRQHandler ; 21, 37, 0x094, + DCD QSPI_IRQHandler ; 22, 38, 0x098, + DCD USART0_IRQHandler ; 23, 39, 0x09C, + DCD _RESERVED ; 24, 40, 0x0A0, + DCD UART0_IRQHandler ; 25, 41, 0x0A4, + DCD _RESERVED ; 26, 42, 0x0A8, + DCD MIDI_IRQHandler ; 27, 43, 0x0AC, + DCD I2S_IRQHandler ; 28, 44, 0x0B0, + DCD USB_IRQHandler ; 29, 45, 0x0B4, + DCD PDMA_CH0_1_IRQHandler ; 30, 46, 0x0B8, + DCD PDMA_CH2_5_IRQHandler ; 31, 47, 0x0BC, + + THUMB + + PUBWEAK Reset_Handler + SECTION .text:CODE:REORDER:NOROOT(2) +Reset_Handler + LDR R0, =BootProcess + BLX R0 + LDR R0, =SystemInit + BLX R0 + LDR R0, =__iar_program_start + BX R0 + +BootProcess + LDR R0, =0x40080300 + LDR R1,[R0, #0x10] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x14] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x18] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x1C] + CMP R1, #0 + BEQ BP2 +BP1 LDR R0, =0x40080180 + LDR R1,[R0, #0xC] + LSLS R1, R1, #4 + LSRS R1, R1, #20 + CMP R1, #0 + BEQ BP3 + CMP R1, #5 + BEQ BP3 + CMP R1, #6 + BEQ BP3 +BP2 DSB + LDR R0, =0x20000000 + LDR R1, =0x05fa0004 + STR R1, [R0] + LDR R1, =0xe000ed00 + LDR R0, =0x05fa0004 + STR R0, [R1, #0xC] + DSB + B . +BP3 LDR R0, =0x20000000 + LDR R1, [R0] + LDR R0, =0x05fa0004 + CMP R0, R1 + BEQ BP4 + BX LR +BP4 LDR R0, =0x40088100 + LDR R1, =0x00000001 + STR R1, [R0] + LDR R0, =0x20000000 + LDR R1, =0x0 + STR R1, [R0] + BX LR + + PUBWEAK NMI_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +NMI_Handler + B . + + PUBWEAK HardFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +HardFault_Handler + B . + + PUBWEAK SVC_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SVC_Handler + B . + + PUBWEAK PendSV_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PendSV_Handler + B . + + PUBWEAK SysTick_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SysTick_Handler + B . + + + PUBWEAK LVD_BOD_IRQHandler + PUBWEAK RTC_IRQHandler + PUBWEAK FLASH_IRQHandler + PUBWEAK EVWUP_IRQHandler + PUBWEAK EXTI0_1_IRQHandler + PUBWEAK EXTI2_3_IRQHandler + PUBWEAK EXTI4_15_IRQHandler + PUBWEAK ADC_IRQHandler + PUBWEAK GPTM0_IRQHandler + PUBWEAK SCTM0_IRQHandler + PUBWEAK SCTM1_IRQHandler + PUBWEAK SCTM2_IRQHandler + PUBWEAK SCTM3_IRQHandler + PUBWEAK BFTM0_IRQHandler + PUBWEAK BFTM1_IRQHandler + PUBWEAK I2C0_IRQHandler + PUBWEAK SPI0_IRQHandler + PUBWEAK QSPI_IRQHandler + PUBWEAK USART0_IRQHandler + PUBWEAK UART0_IRQHandler + PUBWEAK MIDI_IRQHandler + PUBWEAK I2S_IRQHandler + PUBWEAK USB_IRQHandler + PUBWEAK PDMA_CH0_1_IRQHandler + PUBWEAK PDMA_CH2_5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +LVD_BOD_IRQHandler +RTC_IRQHandler +FLASH_IRQHandler +EVWUP_IRQHandler +EXTI0_1_IRQHandler +EXTI2_3_IRQHandler +EXTI4_15_IRQHandler +ADC_IRQHandler +GPTM0_IRQHandler +SCTM0_IRQHandler +SCTM1_IRQHandler +SCTM2_IRQHandler +SCTM3_IRQHandler +BFTM0_IRQHandler +BFTM1_IRQHandler +I2C0_IRQHandler +SPI0_IRQHandler +QSPI_IRQHandler +USART0_IRQHandler +UART0_IRQHandler +MIDI_IRQHandler +I2S_IRQHandler +USB_IRQHandler +PDMA_CH0_1_IRQHandler +PDMA_CH2_5_IRQHandler + B . + + END diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/IAR/startup_ht32f5xxxx_iar_08.s b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/IAR/startup_ht32f5xxxx_iar_08.s new file mode 100644 index 0000000000..c1c8add3fb --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/IAR/startup_ht32f5xxxx_iar_08.s @@ -0,0 +1,224 @@ +;/*---------------------------------------------------------------------------------------------------------*/ +;/* Holtek Semiconductor Inc. */ +;/* */ +;/* Copyright (C) Holtek Semiconductor Inc. */ +;/* All rights reserved. */ +;/* */ +;/*----------------------------------------------------------------------------------------------------------- +; File Name : startup_ht32f5xxxx_iar_08.s +; Version : $Rev:: 6887 $ +; Date : $Date:: 2023-05-05 #$ +; Description : Startup code. +;-----------------------------------------------------------------------------------------------------------*/ + +; Supported Device +; ======================================== +; HT32F65230, HT32F65240 +; HT32F65232 +; HT50F3200S + +;/* <<< Use Configuration Wizard in Context Menu >>> */ + +;// HT32 Device +;// <0=> By Project Asm Define +;// <12=> HT32F65230_40 +;// <18=> HT32F65232 +;// <12=> HT50F3200S +USE_HT32_CHIP_SET EQU 0 + +_HT32FWID EQU 0xFFFFFFFF +;_HT32FWID EQU 0x00065230 +;_HT32FWID EQU 0x00065240 +;_HT32FWID EQU 0x00065232 +;_HT32FWID EQU 0x0003200F + +HT32F65230_40 EQU 12 +HT32F65232 EQU 18 +HT50F3200S EQU 12 + + IF USE_HT32_CHIP_SET=0 + ELSE + #undef USE_HT32_CHIP + #define USE_HT32_CHIP USE_HT32_CHIP_SET + ENDIF + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + EXTERN SystemInit + PUBLIC __vector_table + +;******************************************************************************* +; Fill-up the Vector Table entries with the exceptions ISR address +;******************************************************************************* + DATA +_RESERVED EQU 0xFFFFFFFF +__vector_table + DCD sfe(CSTACK) ; ---, 00, 0x000, Top address of Stack + DCD Reset_Handler ; ---, 01, 0x004, Reset Handler + DCD NMI_Handler ; -14, 02, 0x008, NMI Handler + DCD HardFault_Handler ; -13, 03, 0x00C, Hard Fault Handler + DCD _RESERVED ; ---, 04, 0x010, Reserved + DCD _RESERVED ; ---, 05, 0x014, Reserved + DCD _RESERVED ; ---, 06, 0x018, Reserved + DCD _RESERVED ; ---, 07, 0x01C, Reserved + DCD _HT32FWID ; ---, 08, 0x020, Reserved + DCD _RESERVED ; ---, 09, 0x024, Reserved + DCD _RESERVED ; ---, 10, 0x028, Reserved + DCD SVC_Handler ; -05, 11, 0x02C, SVC Handler + DCD _RESERVED ; ---, 12, 0x030, Reserved + DCD _RESERVED ; ---, 13, 0x034, Reserved + DCD PendSV_Handler ; -02, 14, 0x038, PendSV Handler + DCD SysTick_Handler ; -01, 15, 0x03C, SysTick Handler + + ; External Interrupt Handler + DCD LVD_BOD_IRQHandler ; 00, 16, 0x040, + DCD RTC_IRQHandler ; 01, 17, 0x044, + DCD FLASH_IRQHandler ; 02, 18, 0x048, + DCD EVWUP_IRQHandler ; 03, 19, 0x04C, + DCD EXTI0_1_IRQHandler ; 04, 20, 0x050, + DCD EXTI2_3_IRQHandler ; 05, 21, 0x054, + DCD EXTI4_9_IRQHandler ; 06, 22, 0x058, + DCD EXTI10_15_IRQHandler ; 07, 23, 0x05C, + DCD ADC0_IRQHandler ; 08, 24, 0x060, + IF (USE_HT32_CHIP=HT32F65230_40) + DCD ADC1_IRQHandler ; 09, 25, 0x064, + ELSE + DCD _RESERVED ; 09, 25, 0x064, + ENDIF + DCD MCTM0_BRK_IRQHandler ; 10, 26, 0x068, + DCD MCTM0_UP_IRQHandler ; 11, 27, 0x06C, + DCD MCTM0_TR_UP2_IRQHandler ; 12, 28, 0x070, + DCD MCTM0_CC_IRQHandler ; 13, 29, 0x074, + DCD GPTM0_G_IRQHandler ; 14, 30, 0x078, + DCD GPTM0_VCLK_IRQHandler ; 15, 31, 0x07C, + DCD BFTM0_IRQHandler ; 16, 32, 0x080, + DCD BFTM1_IRQHandler ; 17, 33, 0x084, + DCD CMP0_IRQHandler ; 18, 34, 0x088, + DCD CMP1_IRQHandler ; 19, 35, 0x08C, + IF (USE_HT32_CHIP=HT32F65230_40) + DCD CMP2_IRQHandler ; 20, 36, 0x090, + ELSE + DCD _RESERVED ; 20, 36, 0x090, + ENDIF + DCD I2C0_IRQHandler ; 21, 37, 0x094, + DCD SPI0_IRQHandler ; 22, 38, 0x098, + DCD USART0_IRQHandler ; 23, 39, 0x09C, + DCD UART0_IRQHandler ; 24, 40, 0x0A0, + DCD PDMA_CH0_1_IRQHandler ; 25, 41, 0x0A4, + DCD PDMA_CH2_3_IRQHandler ; 26, 42, 0x0A8, + DCD PDMA_CH4_5_IRQHandler ; 27, 43, 0x0AC, + DCD SCTM0_IRQHandler ; 28, 44, 0x0B0, + DCD SCTM1_IRQHandler ; 29, 45, 0x0B4, + DCD SCTM2_IRQHandler ; 30, 46, 0x0B8, + DCD SCTM3_IRQHandler ; 31, 47, 0x0BC, + + THUMB + + PUBWEAK Reset_Handler + SECTION .text:CODE:REORDER:NOROOT(2) +Reset_Handler + LDR R0, =SystemInit + BLX R0 + LDR R0, =__iar_program_start + BX R0 + + PUBWEAK NMI_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +NMI_Handler + B . + + PUBWEAK HardFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +HardFault_Handler + B . + + PUBWEAK SVC_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SVC_Handler + B . + + PUBWEAK PendSV_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PendSV_Handler + B . + + PUBWEAK SysTick_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SysTick_Handler + B . + + + PUBWEAK LVD_BOD_IRQHandler + PUBWEAK RTC_IRQHandler + PUBWEAK FLASH_IRQHandler + PUBWEAK EVWUP_IRQHandler + PUBWEAK EXTI0_1_IRQHandler + PUBWEAK EXTI2_3_IRQHandler + PUBWEAK EXTI4_9_IRQHandler + PUBWEAK EXTI10_15_IRQHandler + PUBWEAK ADC0_IRQHandler + PUBWEAK ADC1_IRQHandler + PUBWEAK MCTM0_BRK_IRQHandler + PUBWEAK MCTM0_UP_IRQHandler + PUBWEAK MCTM0_TR_UP2_IRQHandler + PUBWEAK MCTM0_CC_IRQHandler + PUBWEAK GPTM0_G_IRQHandler + PUBWEAK GPTM0_VCLK_IRQHandler + PUBWEAK BFTM0_IRQHandler + PUBWEAK BFTM1_IRQHandler + PUBWEAK CMP0_IRQHandler + PUBWEAK CMP1_IRQHandler + PUBWEAK CMP2_IRQHandler + PUBWEAK I2C0_IRQHandler + PUBWEAK SPI0_IRQHandler + PUBWEAK USART0_IRQHandler + PUBWEAK UART0_IRQHandler + PUBWEAK PDMA_CH0_1_IRQHandler + PUBWEAK PDMA_CH2_3_IRQHandler + PUBWEAK PDMA_CH4_5_IRQHandler + PUBWEAK SCTM0_IRQHandler + PUBWEAK SCTM1_IRQHandler + PUBWEAK SCTM2_IRQHandler + PUBWEAK SCTM3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +LVD_BOD_IRQHandler +RTC_IRQHandler +FLASH_IRQHandler +EVWUP_IRQHandler +EXTI0_1_IRQHandler +EXTI2_3_IRQHandler +EXTI4_9_IRQHandler +EXTI10_15_IRQHandler +ADC0_IRQHandler +ADC1_IRQHandler +MCTM0_BRK_IRQHandler +MCTM0_UP_IRQHandler +MCTM0_TR_UP2_IRQHandler +MCTM0_CC_IRQHandler +GPTM0_G_IRQHandler +GPTM0_VCLK_IRQHandler +BFTM0_IRQHandler +BFTM1_IRQHandler +CMP0_IRQHandler +CMP1_IRQHandler +CMP2_IRQHandler +I2C0_IRQHandler +SPI0_IRQHandler +USART0_IRQHandler +UART0_IRQHandler +PDMA_CH0_1_IRQHandler +PDMA_CH2_3_IRQHandler +PDMA_CH4_5_IRQHandler +SCTM0_IRQHandler +SCTM1_IRQHandler +SCTM2_IRQHandler +SCTM3_IRQHandler + B . + + END diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/IAR/startup_ht32f5xxxx_iar_09.s b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/IAR/startup_ht32f5xxxx_iar_09.s new file mode 100644 index 0000000000..508fb39eaa --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/IAR/startup_ht32f5xxxx_iar_09.s @@ -0,0 +1,291 @@ +;/*---------------------------------------------------------------------------------------------------------*/ +;/* Holtek Semiconductor Inc. */ +;/* */ +;/* Copyright (C) Holtek Semiconductor Inc. */ +;/* All rights reserved. */ +;/* */ +;/*----------------------------------------------------------------------------------------------------------- +; File Name : startup_ht32f5xxxx_iar_09.s +; Version : $Rev:: 5410 $ +; Date : $Date:: 2021-06-04 #$ +; Description : Startup code. +;-----------------------------------------------------------------------------------------------------------*/ + +; Supported Device +; ======================================== +; HT32F54231, HT32F54241 +; HT32F54243, HT32F54253 + +;/* <<< Use Configuration Wizard in Context Menu >>> */ + +;// HT32 Device +;// <0=> By Project Asm Define +;// <19=> HT32F54231/41 +;// <20=> HT32F54243/53 +USE_HT32_CHIP_SET EQU 0 + +_HT32FWID EQU 0xFFFFFFFF +;_HT32FWID EQU 0x00054231 +;_HT32FWID EQU 0x00054241 +;_HT32FWID EQU 0x00054243 +;_HT32FWID EQU 0x00054253 + +HT32F54231_41 EQU 19 +HT32F54243_53 EQU 20 + + IF USE_HT32_CHIP_SET=0 + ELSE + #undef USE_HT32_CHIP + #define USE_HT32_CHIP USE_HT32_CHIP_SET + ENDIF + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + EXTERN SystemInit + PUBLIC __vector_table + +;******************************************************************************* +; Fill-up the Vector Table entries with the exceptions ISR address +;******************************************************************************* + DATA +_RESERVED EQU 0xFFFFFFFF +__vector_table + DCD sfe(CSTACK) ; ---, 00, 0x000, Top address of Stack + DCD Reset_Handler ; ---, 01, 0x004, Reset Handler + DCD NMI_Handler ; -14, 02, 0x008, NMI Handler + DCD HardFault_Handler ; -13, 03, 0x00C, Hard Fault Handler + DCD _RESERVED ; ---, 04, 0x010, Reserved + DCD _RESERVED ; ---, 05, 0x014, Reserved + DCD _RESERVED ; ---, 06, 0x018, Reserved + DCD _RESERVED ; ---, 07, 0x01C, Reserved + DCD _HT32FWID ; ---, 08, 0x020, Reserved + DCD _RESERVED ; ---, 09, 0x024, Reserved + DCD _RESERVED ; ---, 10, 0x028, Reserved + DCD SVC_Handler ; -05, 11, 0x02C, SVC Handler + DCD _RESERVED ; ---, 12, 0x030, Reserved + DCD _RESERVED ; ---, 13, 0x034, Reserved + DCD PendSV_Handler ; -02, 14, 0x038, PendSV Handler + DCD SysTick_Handler ; -01, 15, 0x03C, SysTick Handler + + ; External Interrupt Handler + DCD LVD_BOD_IRQHandler ; 00, 16, 0x040, + DCD RTC_IRQHandler ; 01, 17, 0x044, + DCD FLASH_IRQHandler ; 02, 18, 0x048, + DCD EVWUP_IRQHandler ; 03, 19, 0x04C, + DCD EXTI0_1_IRQHandler ; 04, 20, 0x050, + DCD EXTI2_3_IRQHandler ; 05, 21, 0x054, + DCD EXTI4_15_IRQHandler ; 06, 22, 0x058, + IF (USE_HT32_CHIP=HT32F54231_41) + DCD _RESERVED ; 07, 23, 0x05C, + ENDIF + IF (USE_HT32_CHIP=HT32F54243_53) + DCD COMP_IRQHandler ; 07, 23, 0x05C, + ENDIF + DCD ADC_IRQHandler ; 08, 24, 0x060, + IF (USE_HT32_CHIP=HT32F54231_41) + DCD _RESERVED ; 09, 25, 0x064, + ENDIF + IF (USE_HT32_CHIP=HT32F54243_53) + DCD I2C2_IRQHandler ; 09, 25, 0x064, + ENDIF + DCD MCTM0_IRQHandler ; 10, 26, 0x068, + DCD TKEY_IRQHandler ; 11, 27, 0x06C, + DCD GPTM0_IRQHandler ; 12, 28, 0x070, + DCD SCTM0_IRQHandler ; 13, 29, 0x074, + DCD SCTM1_IRQHandler ; 14, 30, 0x078, + IF (USE_HT32_CHIP=HT32F54231_41) + DCD _RESERVED ; 15, 31, 0x07C, + DCD _RESERVED ; 16, 32, 0x080, + ENDIF + IF (USE_HT32_CHIP=HT32F54243_53) + DCD SCTM2_IRQHandler ; 15, 31, 0x07C, + DCD SCTM3_IRQHandler ; 16, 32, 0x080, + ENDIF + DCD BFTM0_IRQHandler ; 17, 33, 0x084, + DCD BFTM1_IRQHandler ; 18, 34, 0x088, + DCD I2C0_IRQHandler ; 19, 35, 0x08C, + DCD I2C1_IRQHandler ; 20, 36, 0x090, + DCD SPI0_IRQHandler ; 21, 37, 0x094, + DCD SPI1_IRQHandler ; 22, 38, 0x098, + DCD USART0_IRQHandler ; 23, 39, 0x09C, + IF (USE_HT32_CHIP=HT32F54231_41) + DCD _RESERVED ; 24, 40, 0x0A0, + ENDIF + IF (USE_HT32_CHIP=HT32F54243_53) + DCD USART1_IRQHandler ; 24, 40, 0x0A0, + ENDIF + DCD UART0_IRQHandler ; 25, 41, 0x0A4, + DCD UART1_IRQHandler ; 26, 42, 0x0A8, + IF (USE_HT32_CHIP=HT32F54231_41) + DCD _RESERVED ; 27, 43, 0x0AC, + DCD _RESERVED ; 28, 44, 0x0B0, + ENDIF + IF (USE_HT32_CHIP=HT32F54243_53) + DCD UART2_IRQHandler ; 27, 43, 0x0AC, + DCD UART3_IRQHandler ; 28, 44, 0x0B0, + ENDIF + DCD LEDC_IRQHandler ; 29, 45, 0x0B4, + IF (USE_HT32_CHIP=HT32F54243_53) + DCD PDMA_CH0_1_IRQHandler ; 30, 46, 0x0B8, + DCD PDMA_CH2_5_IRQHandler ; 31, 47, 0x0BC, + ENDIF + + THUMB + + PUBWEAK Reset_Handler + SECTION .text:CODE:REORDER:NOROOT(2) +Reset_Handler + LDR R0, =BootProcess + BLX R0 + LDR R0, =SystemInit + BLX R0 + LDR R0, =__iar_program_start + BX R0 + +BootProcess + LDR R0, =0x40080300 + LDR R1,[R0, #0x10] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x14] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x18] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x1C] + CMP R1, #0 + BEQ BP2 +BP1 LDR R0, =0x40080180 + LDR R1,[R0, #0xC] + LSLS R1, R1, #4 + LSRS R1, R1, #20 + CMP R1, #0 + BEQ BP3 + CMP R1, #5 + BEQ BP3 + CMP R1, #6 + BEQ BP3 +BP2 DSB + LDR R0, =0x20000000 + LDR R1, =0x05fa0004 + STR R1, [R0] + LDR R1, =0xe000ed00 + LDR R0, =0x05fa0004 + STR R0, [R1, #0xC] + DSB + B . +BP3 LDR R0, =0x20000000 + LDR R1, [R0] + LDR R0, =0x05fa0004 + CMP R0, R1 + BEQ BP4 + BX LR +BP4 LDR R0, =0x40088100 + LDR R1, =0x00000001 + STR R1, [R0] + LDR R0, =0x20000000 + LDR R1, =0x0 + STR R1, [R0] + BX LR + + PUBWEAK NMI_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +NMI_Handler + B . + + PUBWEAK HardFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +HardFault_Handler + B . + + PUBWEAK SVC_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SVC_Handler + B . + + PUBWEAK PendSV_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PendSV_Handler + B . + + PUBWEAK SysTick_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SysTick_Handler + B . + + + PUBWEAK LVD_BOD_IRQHandler + PUBWEAK RTC_IRQHandler + PUBWEAK FLASH_IRQHandler + PUBWEAK EVWUP_IRQHandler + PUBWEAK EXTI0_1_IRQHandler + PUBWEAK EXTI2_3_IRQHandler + PUBWEAK EXTI4_15_IRQHandler + PUBWEAK COMP_IRQHandler + PUBWEAK ADC_IRQHandler + PUBWEAK I2C2_IRQHandler + PUBWEAK MCTM0_IRQHandler + PUBWEAK TKEY_IRQHandler + PUBWEAK GPTM0_IRQHandler + PUBWEAK SCTM0_IRQHandler + PUBWEAK SCTM1_IRQHandler + PUBWEAK SCTM2_IRQHandler + PUBWEAK SCTM3_IRQHandler + PUBWEAK BFTM0_IRQHandler + PUBWEAK BFTM1_IRQHandler + PUBWEAK I2C0_IRQHandler + PUBWEAK I2C1_IRQHandler + PUBWEAK SPI0_IRQHandler + PUBWEAK SPI1_IRQHandler + PUBWEAK USART0_IRQHandler + PUBWEAK USART1_IRQHandler + PUBWEAK UART0_IRQHandler + PUBWEAK UART1_IRQHandler + PUBWEAK UART2_IRQHandler + PUBWEAK UART3_IRQHandler + PUBWEAK LEDC_IRQHandler + PUBWEAK PDMA_CH0_1_IRQHandler + PUBWEAK PDMA_CH2_5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +LVD_BOD_IRQHandler +RTC_IRQHandler +FLASH_IRQHandler +EVWUP_IRQHandler +EXTI0_1_IRQHandler +EXTI2_3_IRQHandler +EXTI4_15_IRQHandler +COMP_IRQHandler +ADC_IRQHandler +I2C2_IRQHandler +MCTM0_IRQHandler +TKEY_IRQHandler +GPTM0_IRQHandler +SCTM0_IRQHandler +SCTM1_IRQHandler +SCTM2_IRQHandler +SCTM3_IRQHandler +BFTM0_IRQHandler +BFTM1_IRQHandler +I2C0_IRQHandler +I2C1_IRQHandler +SPI0_IRQHandler +SPI1_IRQHandler +USART0_IRQHandler +USART1_IRQHandler +UART0_IRQHandler +UART1_IRQHandler +UART2_IRQHandler +UART3_IRQHandler +LEDC_IRQHandler +PDMA_CH0_1_IRQHandler +PDMA_CH2_5_IRQHandler + B . + + END diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/IAR/startup_ht32f5xxxx_iar_10.s b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/IAR/startup_ht32f5xxxx_iar_10.s new file mode 100644 index 0000000000..a8289bc68e --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/IAR/startup_ht32f5xxxx_iar_10.s @@ -0,0 +1,184 @@ +;/*---------------------------------------------------------------------------------------------------------*/ +;/* Holtek Semiconductor Inc. */ +;/* */ +;/* Copyright (C) Holtek Semiconductor Inc. */ +;/* All rights reserved. */ +;/* */ +;/*----------------------------------------------------------------------------------------------------------- +; File Name : startup_ht32f5xxxx_iar_10.s +; Version : $Rev:: 5780 $ +; Date : $Date:: 2022-03-28 #$ +; Description : Startup code. +;-----------------------------------------------------------------------------------------------------------*/ + +; Supported Device +; ======================================== +; HT32F61244, HT32F61245 + +;/* <<< Use Configuration Wizard in Context Menu >>> */ + +;// HT32 Device +;// <0=> By Project Asm Define +;// <24=> HT32F61244/45 +USE_HT32_CHIP_SET EQU 0 + +_HT32FWID EQU 0xFFFFFFFF +;_HT32FWID EQU 0x00061244 +;_HT32FWID EQU 0x00061245 + +HT32F61244_45 EQU 24 + + IF USE_HT32_CHIP_SET=0 + ELSE + #undef USE_HT32_CHIP + #define USE_HT32_CHIP USE_HT32_CHIP_SET + ENDIF + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + EXTERN SystemInit + PUBLIC __vector_table + +;******************************************************************************* +; Fill-up the Vector Table entries with the exceptions ISR address +;******************************************************************************* + DATA +_RESERVED EQU 0xFFFFFFFF +__vector_table + DCD sfe(CSTACK) ; ---, 00, 0x000, Top address of Stack + DCD Reset_Handler ; ---, 01, 0x004, Reset Handler + DCD NMI_Handler ; -14, 02, 0x008, NMI Handler + DCD HardFault_Handler ; -13, 03, 0x00C, Hard Fault Handler + DCD _RESERVED ; ---, 04, 0x010, Reserved + DCD _RESERVED ; ---, 05, 0x014, Reserved + DCD _RESERVED ; ---, 06, 0x018, Reserved + DCD _RESERVED ; ---, 07, 0x01C, Reserved + DCD _HT32FWID ; ---, 08, 0x020, Reserved + DCD _RESERVED ; ---, 09, 0x024, Reserved + DCD _RESERVED ; ---, 10, 0x028, Reserved + DCD SVC_Handler ; -05, 11, 0x02C, SVC Handler + DCD _RESERVED ; ---, 12, 0x030, Reserved + DCD _RESERVED ; ---, 13, 0x034, Reserved + DCD PendSV_Handler ; -02, 14, 0x038, PendSV Handler + DCD SysTick_Handler ; -01, 15, 0x03C, SysTick Handler + + ; External Interrupt Handler + DCD LVD_BOD_IRQHandler ; 00, 16, 0x040, + DCD RTC_IRQHandler ; 01, 17, 0x044, + DCD FLASH_IRQHandler ; 02, 18, 0x048, + DCD EVWUP_IRQHandler ; 03, 19, 0x04C, + DCD EXTI0_1_IRQHandler ; 04, 20, 0x050, + DCD EXTI2_3_IRQHandler ; 05, 21, 0x054, + DCD EXTI4_15_IRQHandler ; 06, 22, 0x058, + DCD _RESERVED ; 07, 23, 0x05C, + DCD ADC_IRQHandler ; 08, 24, 0x060, + DCD _RESERVED ; 09, 25, 0x064, + DCD _RESERVED ; 10, 26, 0x068, + DCD _RESERVED ; 11, 27, 0x06C, + DCD GPTM0_IRQHandler ; 12, 28, 0x070, + DCD SCTM0_IRQHandler ; 13, 29, 0x074, + DCD SCTM1_IRQHandler ; 14, 30, 0x078, + DCD _RESERVED ; 15, 31, 0x07C, + DCD _RESERVED ; 16, 32, 0x080, + DCD BFTM0_IRQHandler ; 17, 33, 0x084, + DCD BFTM1_IRQHandler ; 18, 34, 0x088, + DCD I2C0_IRQHandler ; 19, 35, 0x08C, + DCD _RESERVED ; 20, 36, 0x090, + DCD SPI0_IRQHandler ; 21, 37, 0x094, + DCD QSPI_IRQHandler ; 22, 38, 0x098, + DCD _RESERVED ; 23, 39, 0x09C, + DCD _RESERVED ; 24, 40, 0x0A0, + DCD UART0_IRQHandler ; 25, 41, 0x0A4, + DCD _RESERVED ; 26, 42, 0x0A8, + DCD MIDI_IRQHandler ; 27, 43, 0x0AC, + DCD _RESERVED ; 28, 44, 0x0B0, + DCD _RESERVED ; 29, 45, 0x0B4, + DCD PDMA_CH0_1_IRQHandler ; 30, 46, 0x0B8, + DCD PDMA_CH2_5_IRQHandler ; 31, 47, 0x0BC, + + THUMB + + PUBWEAK Reset_Handler + SECTION .text:CODE:REORDER:NOROOT(2) +Reset_Handler + LDR R0, =SystemInit + BLX R0 + LDR R0, =__iar_program_start + BX R0 + + PUBWEAK NMI_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +NMI_Handler + B . + + PUBWEAK HardFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +HardFault_Handler + B . + + PUBWEAK SVC_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SVC_Handler + B . + + PUBWEAK PendSV_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PendSV_Handler + B . + + PUBWEAK SysTick_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SysTick_Handler + B . + + + PUBWEAK LVD_BOD_IRQHandler + PUBWEAK RTC_IRQHandler + PUBWEAK FLASH_IRQHandler + PUBWEAK EVWUP_IRQHandler + PUBWEAK EXTI0_1_IRQHandler + PUBWEAK EXTI2_3_IRQHandler + PUBWEAK EXTI4_15_IRQHandler + PUBWEAK ADC_IRQHandler + PUBWEAK GPTM0_IRQHandler + PUBWEAK SCTM0_IRQHandler + PUBWEAK SCTM1_IRQHandler + PUBWEAK BFTM0_IRQHandler + PUBWEAK BFTM1_IRQHandler + PUBWEAK I2C0_IRQHandler + PUBWEAK SPI0_IRQHandler + PUBWEAK QSPI_IRQHandler + PUBWEAK UART0_IRQHandler + PUBWEAK MIDI_IRQHandler + PUBWEAK PDMA_CH0_1_IRQHandler + PUBWEAK PDMA_CH2_5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +LVD_BOD_IRQHandler +RTC_IRQHandler +FLASH_IRQHandler +EVWUP_IRQHandler +EXTI0_1_IRQHandler +EXTI2_3_IRQHandler +EXTI4_15_IRQHandler +ADC_IRQHandler +GPTM0_IRQHandler +SCTM0_IRQHandler +SCTM1_IRQHandler +BFTM0_IRQHandler +BFTM1_IRQHandler +I2C0_IRQHandler +SPI0_IRQHandler +QSPI_IRQHandler +UART0_IRQHandler +MIDI_IRQHandler +PDMA_CH0_1_IRQHandler +PDMA_CH2_5_IRQHandler + B . + + END diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/IAR/startup_ht32f5xxxx_iar_11.s b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/IAR/startup_ht32f5xxxx_iar_11.s new file mode 100644 index 0000000000..e49a6d5643 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/IAR/startup_ht32f5xxxx_iar_11.s @@ -0,0 +1,194 @@ +;/*---------------------------------------------------------------------------------------------------------*/ +;/* Holtek Semiconductor Inc. */ +;/* */ +;/* Copyright (C) Holtek Semiconductor Inc. */ +;/* All rights reserved. */ +;/* */ +;/*----------------------------------------------------------------------------------------------------------- +; File Name : startup_ht32f5xxxx_iar_11.s +; Version : $Rev:: 5991 $ +; Date : $Date:: 2022-06-23 #$ +; Description : Startup code. +;-----------------------------------------------------------------------------------------------------------*/ + +; Supported Device +; ======================================== +; HT32F67041, HT32F67051 + +;/* <<< Use Configuration Wizard in Context Menu >>> */ + +;// HT32 Device +;// <0=> By Project Asm Define +;// <22=> HT32F67041/51 +USE_HT32_CHIP_SET EQU 0 + +_HT32FWID EQU 0xFFFFFFFF +;_HT32FWID EQU 0x00067041 +;_HT32FWID EQU 0x00067051 + +HT32F67041_51 EQU 22 + + IF USE_HT32_CHIP_SET=0 + ELSE + #undef USE_HT32_CHIP + #define USE_HT32_CHIP USE_HT32_CHIP_SET + ENDIF + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + EXTERN SystemInit + PUBLIC __vector_table + +;******************************************************************************* +; Fill-up the Vector Table entries with the exceptions ISR address +;******************************************************************************* + DATA +_RESERVED EQU 0xFFFFFFFF +__vector_table + DCD sfe(CSTACK) ; ---, 00, 0x000, Top address of Stack + DCD Reset_Handler ; ---, 01, 0x004, Reset Handler + DCD NMI_Handler ; -14, 02, 0x008, NMI Handler + DCD HardFault_Handler ; -13, 03, 0x00C, Hard Fault Handler + DCD _RESERVED ; ---, 04, 0x010, Reserved + DCD _RESERVED ; ---, 05, 0x014, Reserved + DCD _RESERVED ; ---, 06, 0x018, Reserved + DCD _RESERVED ; ---, 07, 0x01C, Reserved + DCD _HT32FWID ; ---, 08, 0x020, Reserved + DCD _RESERVED ; ---, 09, 0x024, Reserved + DCD _RESERVED ; ---, 10, 0x028, Reserved + DCD SVC_Handler ; -05, 11, 0x02C, SVC Handler + DCD _RESERVED ; ---, 12, 0x030, Reserved + DCD _RESERVED ; ---, 13, 0x034, Reserved + DCD PendSV_Handler ; -02, 14, 0x038, PendSV Handler + DCD SysTick_Handler ; -01, 15, 0x03C, SysTick Handler + + ; External Interrupt Handler + DCD LVD_BOD_IRQHandler ; 00, 16, 0x040, + DCD RTC_IRQHandler ; 01, 17, 0x044, + DCD FLASH_IRQHandler ; 02, 18, 0x048, + DCD EVWUP_IRQHandler ; 03, 19, 0x04C, + DCD EXTI0_1_IRQHandler ; 04, 20, 0x050, + DCD EXTI2_3_IRQHandler ; 05, 21, 0x054, + DCD EXTI4_15_IRQHandler ; 06, 22, 0x058, + DCD _RESERVED ; 07, 23, 0x05C, + DCD ADC_IRQHandler ; 08, 24, 0x060, + DCD AES_IRQHandler ; 09, 25, 0x064, + DCD _RESERVED ; 10, 26, 0x068, + DCD RF_IRQHandler ; 11, 27, 0x06C, + DCD GPTM0_IRQHandler ; 12, 28, 0x070, + DCD SCTM0_IRQHandler ; 13, 29, 0x074, + DCD SCTM1_IRQHandler ; 14, 30, 0x078, + DCD SCTM2_IRQHandler ; 15, 31, 0x07C, + DCD SCTM3_IRQHandler ; 16, 32, 0x080, + DCD BFTM0_IRQHandler ; 17, 33, 0x084, + DCD BFTM1_IRQHandler ; 18, 34, 0x088, + DCD I2C0_IRQHandler ; 19, 35, 0x08C, + DCD I2C1_IRQHandler ; 20, 36, 0x090, + DCD SPI0_IRQHandler ; 21, 37, 0x094, + DCD SPI1_IRQHandler ; 22, 38, 0x098, + DCD _RESERVED ; 23, 39, 0x09C, + DCD _RESERVED ; 24, 40, 0x0A0, + DCD UART0_IRQHandler ; 25, 41, 0x0A4, + DCD UART1_IRQHandler ; 26, 42, 0x0A8, + DCD _RESERVED ; 27, 43, 0x0AC, + DCD _RESERVED ; 28, 44, 0x0B0, + DCD _RESERVED ; 29, 45, 0x0B4, + DCD PDMA_CH0_1_IRQHandler ; 30, 46, 0x0B8, + DCD PDMA_CH2_5_IRQHandler ; 31, 47, 0x0BC, + + THUMB + + PUBWEAK Reset_Handler + SECTION .text:CODE:REORDER:NOROOT(2) +Reset_Handler + LDR R0, =SystemInit + BLX R0 + LDR R0, =__iar_program_start + BX R0 + + PUBWEAK NMI_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +NMI_Handler + B . + + PUBWEAK HardFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +HardFault_Handler + B . + + PUBWEAK SVC_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SVC_Handler + B . + + PUBWEAK PendSV_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PendSV_Handler + B . + + PUBWEAK SysTick_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SysTick_Handler + B . + + + PUBWEAK LVD_BOD_IRQHandler + PUBWEAK RTC_IRQHandler + PUBWEAK FLASH_IRQHandler + PUBWEAK EVWUP_IRQHandler + PUBWEAK EXTI0_1_IRQHandler + PUBWEAK EXTI2_3_IRQHandler + PUBWEAK EXTI4_15_IRQHandler + PUBWEAK ADC_IRQHandler + PUBWEAK AES_IRQHandler + PUBWEAK RF_IRQHandler + PUBWEAK GPTM0_IRQHandler + PUBWEAK SCTM0_IRQHandler + PUBWEAK SCTM1_IRQHandler + PUBWEAK SCTM2_IRQHandler + PUBWEAK SCTM3_IRQHandler + PUBWEAK BFTM0_IRQHandler + PUBWEAK BFTM1_IRQHandler + PUBWEAK I2C0_IRQHandler + PUBWEAK I2C1_IRQHandler + PUBWEAK SPI0_IRQHandler + PUBWEAK SPI1_IRQHandler + PUBWEAK UART0_IRQHandler + PUBWEAK UART1_IRQHandler + PUBWEAK PDMA_CH0_1_IRQHandler + PUBWEAK PDMA_CH2_5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +LVD_BOD_IRQHandler +RTC_IRQHandler +FLASH_IRQHandler +EVWUP_IRQHandler +EXTI0_1_IRQHandler +EXTI2_3_IRQHandler +EXTI4_15_IRQHandler +ADC_IRQHandler +AES_IRQHandler +RF_IRQHandler +GPTM0_IRQHandler +SCTM0_IRQHandler +SCTM1_IRQHandler +SCTM2_IRQHandler +SCTM3_IRQHandler +BFTM0_IRQHandler +BFTM1_IRQHandler +I2C0_IRQHandler +I2C1_IRQHandler +SPI0_IRQHandler +SPI1_IRQHandler +UART0_IRQHandler +UART1_IRQHandler +PDMA_CH0_1_IRQHandler +PDMA_CH2_5_IRQHandler + B . + + END diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/IAR/startup_ht32f5xxxx_iar_12.s b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/IAR/startup_ht32f5xxxx_iar_12.s new file mode 100644 index 0000000000..90ff940648 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/IAR/startup_ht32f5xxxx_iar_12.s @@ -0,0 +1,226 @@ +;/*---------------------------------------------------------------------------------------------------------*/ +;/* Holtek Semiconductor Inc. */ +;/* */ +;/* Copyright (C) Holtek Semiconductor Inc. */ +;/* All rights reserved. */ +;/* */ +;/*----------------------------------------------------------------------------------------------------------- +; File Name : startup_ht32f5xxxx_iar_12.s +; Version : $Rev:: 5572 $ +; Date : $Date:: 2021-08-18 #$ +; Description : Startup code. +;-----------------------------------------------------------------------------------------------------------*/ + +; Supported Device +; ======================================== +; HT32F61141 + +;/* <<< Use Configuration Wizard in Context Menu >>> */ + +;// HT32 Device +;// <0=> By Project Asm Define +;// <23=> HT32F61141 +USE_HT32_CHIP_SET EQU 0 + +_HT32FWID EQU 0xFFFFFFFF +;_HT32FWID EQU 0x00061141 + +HT32F61141 EQU 23 + + IF USE_HT32_CHIP_SET=0 + ELSE + #undef USE_HT32_CHIP + #define USE_HT32_CHIP USE_HT32_CHIP_SET + ENDIF + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + EXTERN SystemInit + PUBLIC __vector_table + +;******************************************************************************* +; Fill-up the Vector Table entries with the exceptions ISR address +;******************************************************************************* + DATA +_RESERVED EQU 0xFFFFFFFF +__vector_table + DCD sfe(CSTACK) ; ---, 00, 0x000, Top address of Stack + DCD Reset_Handler ; ---, 01, 0x004, Reset Handler + DCD NMI_Handler ; -14, 02, 0x008, NMI Handler + DCD HardFault_Handler ; -13, 03, 0x00C, Hard Fault Handler + DCD _RESERVED ; ---, 04, 0x010, Reserved + DCD _RESERVED ; ---, 05, 0x014, Reserved + DCD _RESERVED ; ---, 06, 0x018, Reserved + DCD _RESERVED ; ---, 07, 0x01C, Reserved + DCD _HT32FWID ; ---, 08, 0x020, Reserved + DCD _RESERVED ; ---, 09, 0x024, Reserved + DCD _RESERVED ; ---, 10, 0x028, Reserved + DCD SVC_Handler ; -05, 11, 0x02C, SVC Handler + DCD _RESERVED ; ---, 12, 0x030, Reserved + DCD _RESERVED ; ---, 13, 0x034, Reserved + DCD PendSV_Handler ; -02, 14, 0x038, PendSV Handler + DCD SysTick_Handler ; -01, 15, 0x03C, SysTick Handler + + ; External Interrupt Handler + DCD LVD_BOD_IRQHandler ; 00, 16, 0x040, + DCD RTC_IRQHandler ; 01, 17, 0x044, + DCD FLASH_IRQHandler ; 02, 18, 0x048, + DCD EVWUP_IRQHandler ; 03, 19, 0x04C, + DCD EXTI0_1_IRQHandler ; 04, 20, 0x050, + DCD EXTI2_3_IRQHandler ; 05, 21, 0x054, + DCD EXTI4_15_IRQHandler ; 06, 22, 0x058, + DCD _RESERVED ; 07, 23, 0x05C, + DCD _RESERVED ; 08, 24, 0x060, + DCD _RESERVED ; 09, 25, 0x064, + DCD _RESERVED ; 10, 26, 0x068, + DCD _RESERVED ; 11, 27, 0x06C, + DCD GPTM0_IRQHandler ; 12, 28, 0x070, + DCD SCTM0_IRQHandler ; 13, 29, 0x074, + DCD SCTM1_IRQHandler ; 14, 30, 0x078, + DCD _RESERVED ; 15, 31, 0x07C, + DCD _RESERVED ; 16, 32, 0x080, + DCD BFTM0_IRQHandler ; 17, 33, 0x084, + DCD BFTM1_IRQHandler ; 18, 34, 0x088, + DCD I2C0_IRQHandler ; 19, 35, 0x08C, + DCD _RESERVED ; 20, 36, 0x090, + DCD SPI0_IRQHandler ; 21, 37, 0x094, + DCD _RESERVED ; 22, 38, 0x098, + DCD _RESERVED ; 23, 39, 0x09C, + DCD _RESERVED ; 24, 40, 0x0A0, + DCD UART0_IRQHandler ; 25, 41, 0x0A4, + DCD UART1_IRQHandler ; 26, 42, 0x0A8, + DCD SCI_IRQHandler ; 27, 43, 0x0AC, + DCD _RESERVED ; 28, 44, 0x0B0, + DCD USB_IRQHandler ; 29, 45, 0x0B4, + + THUMB + + PUBWEAK Reset_Handler + SECTION .text:CODE:REORDER:NOROOT(2) +Reset_Handler + LDR R0, =BootProcess + BLX R0 + LDR R0, =SystemInit + BLX R0 + LDR R0, =__iar_program_start + BX R0 + +BootProcess + LDR R0, =0x40080300 + LDR R1,[R0, #0x10] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x14] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x18] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x1C] + CMP R1, #0 + BEQ BP2 +BP1 LDR R0, =0x40080180 + LDR R1,[R0, #0xC] + LSLS R1, R1, #4 + LSRS R1, R1, #20 + CMP R1, #0 + BEQ BP3 + CMP R1, #5 + BEQ BP3 + CMP R1, #6 + BEQ BP3 +BP2 DSB + LDR R0, =0x20000000 + LDR R1, =0x05fa0004 + STR R1, [R0] + LDR R1, =0xe000ed00 + LDR R0, =0x05fa0004 + STR R0, [R1, #0xC] + DSB + B . +BP3 LDR R0, =0x20000000 + LDR R1, [R0] + LDR R0, =0x05fa0004 + CMP R0, R1 + BEQ BP4 + BX LR +BP4 LDR R0, =0x40088100 + LDR R1, =0x00000001 + STR R1, [R0] + LDR R0, =0x20000000 + LDR R1, =0x0 + STR R1, [R0] + BX LR + + PUBWEAK NMI_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +NMI_Handler + B . + + PUBWEAK HardFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +HardFault_Handler + B . + + PUBWEAK SVC_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SVC_Handler + B . + + PUBWEAK PendSV_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PendSV_Handler + B . + + PUBWEAK SysTick_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SysTick_Handler + B . + + + PUBWEAK LVD_BOD_IRQHandler + PUBWEAK RTC_IRQHandler + PUBWEAK FLASH_IRQHandler + PUBWEAK EVWUP_IRQHandler + PUBWEAK EXTI0_1_IRQHandler + PUBWEAK EXTI2_3_IRQHandler + PUBWEAK EXTI4_15_IRQHandler + PUBWEAK GPTM0_IRQHandler + PUBWEAK SCTM0_IRQHandler + PUBWEAK SCTM1_IRQHandler + PUBWEAK BFTM0_IRQHandler + PUBWEAK BFTM1_IRQHandler + PUBWEAK I2C0_IRQHandler + PUBWEAK SPI0_IRQHandler + PUBWEAK UART0_IRQHandler + PUBWEAK UART1_IRQHandler + PUBWEAK SCI_IRQHandler + PUBWEAK USB_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +LVD_BOD_IRQHandler +RTC_IRQHandler +FLASH_IRQHandler +EVWUP_IRQHandler +EXTI0_1_IRQHandler +EXTI2_3_IRQHandler +EXTI4_15_IRQHandler +GPTM0_IRQHandler +SCTM0_IRQHandler +SCTM1_IRQHandler +BFTM0_IRQHandler +BFTM1_IRQHandler +I2C0_IRQHandler +SPI0_IRQHandler +UART0_IRQHandler +UART1_IRQHandler +SCI_IRQHandler +USB_IRQHandler + B . + + END diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/IAR/startup_ht32f5xxxx_iar_13.s b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/IAR/startup_ht32f5xxxx_iar_13.s new file mode 100644 index 0000000000..b573c7b115 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/IAR/startup_ht32f5xxxx_iar_13.s @@ -0,0 +1,184 @@ +;/*---------------------------------------------------------------------------------------------------------*/ +;/* Holtek Semiconductor Inc. */ +;/* */ +;/* Copyright (C) Holtek Semiconductor Inc. */ +;/* All rights reserved. */ +;/* */ +;/*----------------------------------------------------------------------------------------------------------- +; File Name : startup_ht32f5xxxx_iar_13.s +; Version : $Rev:: 7119 $ +; Date : $Date:: 2023-08-15 #$ +; Description : Startup code. +;-----------------------------------------------------------------------------------------------------------*/ + +; Supported Device +; ======================================== +; HT32F50020, HT32F50030 +; HT32F61630 +; HT32F61030 + +;/* <<< Use Configuration Wizard in Context Menu >>> */ + +;// HT32 Device +;// <0=> By Project Asm Define +;// <25=> HT32F50020/30 +;// <25=> HT32F61630 +;// <25=> HT32F61030 +USE_HT32_CHIP_SET EQU 0 + +_HT32FWID EQU 0xFFFFFFFF +;_HT32FWID EQU 0x00050020 +;_HT32FWID EQU 0x00050030 +;_HT32FWID EQU 0x00061630 +;_HT32FWID EQU 0x00061030 + +HT32F50020_30 EQU 25 +HT32F61630 EQU 25 +HT32F61030 EQU 25 + + IF USE_HT32_CHIP_SET=0 + ELSE + #undef USE_HT32_CHIP + #define USE_HT32_CHIP USE_HT32_CHIP_SET + ENDIF + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + EXTERN SystemInit + PUBLIC __vector_table + +;******************************************************************************* +; Fill-up the Vector Table entries with the exceptions ISR address +;******************************************************************************* + DATA +_RESERVED EQU 0xFFFFFFFF +__vector_table + DCD sfe(CSTACK) ; ---, 00, 0x000, Top address of Stack + DCD Reset_Handler ; ---, 01, 0x004, Reset Handler + DCD NMI_Handler ; -14, 02, 0x008, NMI Handler + DCD HardFault_Handler ; -13, 03, 0x00C, Hard Fault Handler + DCD _RESERVED ; ---, 04, 0x010, Reserved + DCD _RESERVED ; ---, 05, 0x014, Reserved + DCD _RESERVED ; ---, 06, 0x018, Reserved + DCD _RESERVED ; ---, 07, 0x01C, Reserved + DCD _HT32FWID ; ---, 08, 0x020, Reserved + DCD _RESERVED ; ---, 09, 0x024, Reserved + DCD _RESERVED ; ---, 10, 0x028, Reserved + DCD SVC_Handler ; -05, 11, 0x02C, SVC Handler + DCD _RESERVED ; ---, 12, 0x030, Reserved + DCD _RESERVED ; ---, 13, 0x034, Reserved + DCD PendSV_Handler ; -02, 14, 0x038, PendSV Handler + DCD SysTick_Handler ; -01, 15, 0x03C, SysTick Handler + + ; External Interrupt Handler + DCD LVD_BOD_IRQHandler ; 00, 16, 0x040, + DCD RTC_IRQHandler ; 01, 17, 0x044, + DCD FLASH_IRQHandler ; 02, 18, 0x048, + DCD EVWUP_IRQHandler ; 03, 19, 0x04C, + DCD EXTI0_1_IRQHandler ; 04, 20, 0x050, + DCD EXTI2_3_IRQHandler ; 05, 21, 0x054, + DCD EXTI4_7_IRQHandler ; 06, 22, 0x058, + DCD _RESERVED ; 07, 23, 0x05C, + DCD ADC_IRQHandler ; 08, 24, 0x060, + DCD _RESERVED ; 09, 25, 0x064, + DCD _RESERVED ; 10, 26, 0x068, + DCD _RESERVED ; 11, 27, 0x06C, + DCD _RESERVED ; 12, 28, 0x070, + DCD SCTM0_IRQHandler ; 13, 29, 0x074, + DCD SCTM1_IRQHandler ; 14, 30, 0x078, + DCD SCTM2_IRQHandler ; 15, 31, 0x07C, + DCD _RESERVED ; 16, 32, 0x080, + DCD BFTM0_IRQHandler ; 17, 33, 0x084, + DCD _RESERVED ; 18, 34, 0x088, + DCD I2C0_IRQHandler ; 19, 35, 0x08C, + DCD _RESERVED ; 20, 36, 0x090, + DCD SPI0_IRQHandler ; 21, 37, 0x094, + DCD _RESERVED ; 22, 38, 0x098, + DCD _RESERVED ; 23, 39, 0x09C, + DCD _RESERVED ; 24, 40, 0x0A0, + DCD UART0_IRQHandler ; 25, 41, 0x0A4, + DCD UART1_IRQHandler ; 26, 42, 0x0A8, + DCD _RESERVED ; 27, 43, 0x0AC, + DCD _RESERVED ; 28, 44, 0x0B0, + DCD LEDC_IRQHandler ; 29, 45, 0x0B4, + + THUMB + + PUBWEAK Reset_Handler + SECTION .text:CODE:REORDER:NOROOT(2) +Reset_Handler + LDR R0, =SystemInit + BLX R0 + LDR R0, =__iar_program_start + BX R0 + + PUBWEAK NMI_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +NMI_Handler + B . + + PUBWEAK HardFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +HardFault_Handler + B . + + PUBWEAK SVC_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SVC_Handler + B . + + PUBWEAK PendSV_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PendSV_Handler + B . + + PUBWEAK SysTick_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SysTick_Handler + B . + + + PUBWEAK LVD_BOD_IRQHandler + PUBWEAK RTC_IRQHandler + PUBWEAK FLASH_IRQHandler + PUBWEAK EVWUP_IRQHandler + PUBWEAK EXTI0_1_IRQHandler + PUBWEAK EXTI2_3_IRQHandler + PUBWEAK EXTI4_7_IRQHandler + PUBWEAK ADC_IRQHandler + PUBWEAK SCTM0_IRQHandler + PUBWEAK SCTM1_IRQHandler + PUBWEAK SCTM2_IRQHandler + PUBWEAK BFTM0_IRQHandler + PUBWEAK I2C0_IRQHandler + PUBWEAK SPI0_IRQHandler + PUBWEAK UART0_IRQHandler + PUBWEAK UART1_IRQHandler + PUBWEAK LEDC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +LVD_BOD_IRQHandler +RTC_IRQHandler +FLASH_IRQHandler +EVWUP_IRQHandler +EXTI0_1_IRQHandler +EXTI2_3_IRQHandler +EXTI4_7_IRQHandler +ADC_IRQHandler +SCTM0_IRQHandler +SCTM1_IRQHandler +SCTM2_IRQHandler +BFTM0_IRQHandler +I2C0_IRQHandler +SPI0_IRQHandler +UART0_IRQHandler +UART1_IRQHandler +LEDC_IRQHandler + B . + + END diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/IAR/startup_ht32f5xxxx_iar_14.s b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/IAR/startup_ht32f5xxxx_iar_14.s new file mode 100644 index 0000000000..ffd489d97a --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/IAR/startup_ht32f5xxxx_iar_14.s @@ -0,0 +1,213 @@ +;/*---------------------------------------------------------------------------------------------------------*/ +;/* Holtek Semiconductor Inc. */ +;/* */ +;/* Copyright (C) Holtek Semiconductor Inc. */ +;/* All rights reserved. */ +;/* */ +;/*----------------------------------------------------------------------------------------------------------- +; File Name : startup_ht32f5xxxx_iar_14.s +; Version : $Rev:: 6834 $ +; Date : $Date:: 2023-03-31 #$ +; Description : Startup code. +;-----------------------------------------------------------------------------------------------------------*/ + +; Supported Device +; ======================================== +; HT32F50442, HT32F50452 +; HT32F50431, HT32F50441 + +;/* <<< Use Configuration Wizard in Context Menu >>> */ + +;// HT32 Device +;// <0=> By Project Asm Define +;// <26=> HT32F50442/52 +;// <30=> HT32F50431/41 +USE_HT32_CHIP_SET EQU 0 + +_HT32FWID EQU 0xFFFFFFFF +;_HT32FWID EQU 0x00050442 +;_HT32FWID EQU 0x00050452 +;_HT32FWID EQU 0x00050431 +;_HT32FWID EQU 0x00050441 + +HT32F50442_52 EQU 26 +HT32F50431_41 EQU 30 + + IF USE_HT32_CHIP_SET=0 + ELSE + #undef USE_HT32_CHIP + #define USE_HT32_CHIP USE_HT32_CHIP_SET + ENDIF + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + EXTERN SystemInit + PUBLIC __vector_table + +;******************************************************************************* +; Fill-up the Vector Table entries with the exceptions ISR address +;******************************************************************************* + DATA +_RESERVED EQU 0xFFFFFFFF +__vector_table + DCD sfe(CSTACK) ; ---, 00, 0x000, Top address of Stack + DCD Reset_Handler ; ---, 01, 0x004, Reset Handler + DCD NMI_Handler ; -14, 02, 0x008, NMI Handler + DCD HardFault_Handler ; -13, 03, 0x00C, Hard Fault Handler + DCD _RESERVED ; ---, 04, 0x010, Reserved + DCD _RESERVED ; ---, 05, 0x014, Reserved + DCD _RESERVED ; ---, 06, 0x018, Reserved + DCD _RESERVED ; ---, 07, 0x01C, Reserved + DCD _HT32FWID ; ---, 08, 0x020, Reserved + DCD _RESERVED ; ---, 09, 0x024, Reserved + DCD _RESERVED ; ---, 10, 0x028, Reserved + DCD SVC_Handler ; -05, 11, 0x02C, SVC Handler + DCD _RESERVED ; ---, 12, 0x030, Reserved + DCD _RESERVED ; ---, 13, 0x034, Reserved + DCD PendSV_Handler ; -02, 14, 0x038, PendSV Handler + DCD SysTick_Handler ; -01, 15, 0x03C, SysTick Handler + + ; External Interrupt Handler + DCD LVD_BOD_IRQHandler ; 00, 16, 0x040, + DCD RTC_IRQHandler ; 01, 17, 0x044, + DCD FLASH_IRQHandler ; 02, 18, 0x048, + DCD EVWUP_IRQHandler ; 03, 19, 0x04C, + DCD EXTI0_1_IRQHandler ; 04, 20, 0x050, + DCD EXTI2_3_IRQHandler ; 05, 21, 0x054, + DCD EXTI4_15_IRQHandler ; 06, 22, 0x058, + IF (USE_HT32_CHIP=HT32F50442_52) + DCD COMP_IRQHandler ; 07, 23, 0x05C, + ELSE + DCD _RESERVED ; 07, 23, 0x05C, + ENDIF + DCD ADC_IRQHandler ; 08, 24, 0x060, + DCD _RESERVED ; 09, 25, 0x064, + DCD MCTM0_IRQHandler ; 10, 26, 0x068, + DCD _RESERVED ; 11, 27, 0x06C, + DCD GPTM0_IRQHandler ; 12, 28, 0x070, + DCD _RESERVED ; 13, 29, 0x074, + DCD _RESERVED ; 14, 30, 0x078, + DCD PWM0_IRQHandler ; 15, 31, 0x07C, + IF (USE_HT32_CHIP=HT32F50442_52) + DCD PWM1_IRQHandler ; 16, 32, 0x080, + ELSE + DCD _RESERVED ; 16, 32, 0x080, + ENDIF + DCD BFTM0_IRQHandler ; 17, 33, 0x084, + DCD BFTM1_IRQHandler ; 18, 34, 0x088, + DCD I2C0_IRQHandler ; 19, 35, 0x08C, + DCD I2C1_IRQHandler ; 20, 36, 0x090, + DCD SPI0_IRQHandler ; 21, 37, 0x094, + DCD SPI1_IRQHandler ; 22, 38, 0x098, + DCD USART0_IRQHandler ; 23, 39, 0x09C, + IF (USE_HT32_CHIP=HT32F50442_52) + DCD USART1_IRQHandler ; 24, 40, 0x0A0, + ELSE + DCD _RESERVED ; 24, 40, 0x0A0, + ENDIF + DCD UART0_IRQHandler ; 25, 41, 0x0A4, + DCD UART1_IRQHandler ; 26, 42, 0x0A8, + DCD _RESERVED ; 27, 43, 0x0AC, + DCD _RESERVED ; 28, 44, 0x0B0, + DCD LEDC_IRQHandler ; 29, 45, 0x0B4, + DCD PDMA_CH0_1_IRQHandler ; 30, 46, 0x0B8, + DCD PDMA_CH2_5_IRQHandler ; 31, 47, 0x0BC, + + THUMB + + PUBWEAK Reset_Handler + SECTION .text:CODE:REORDER:NOROOT(2) +Reset_Handler + LDR R0, =SystemInit + BLX R0 + LDR R0, =__iar_program_start + BX R0 + + PUBWEAK NMI_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +NMI_Handler + B . + + PUBWEAK HardFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +HardFault_Handler + B . + + PUBWEAK SVC_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SVC_Handler + B . + + PUBWEAK PendSV_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PendSV_Handler + B . + + PUBWEAK SysTick_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SysTick_Handler + B . + + + PUBWEAK LVD_BOD_IRQHandler + PUBWEAK RTC_IRQHandler + PUBWEAK FLASH_IRQHandler + PUBWEAK EVWUP_IRQHandler + PUBWEAK EXTI0_1_IRQHandler + PUBWEAK EXTI2_3_IRQHandler + PUBWEAK EXTI4_15_IRQHandler + PUBWEAK COMP_IRQHandler + PUBWEAK ADC_IRQHandler + PUBWEAK MCTM0_IRQHandler + PUBWEAK GPTM0_IRQHandler + PUBWEAK PWM0_IRQHandler + PUBWEAK PWM1_IRQHandler + PUBWEAK BFTM0_IRQHandler + PUBWEAK BFTM1_IRQHandler + PUBWEAK I2C0_IRQHandler + PUBWEAK I2C1_IRQHandler + PUBWEAK SPI0_IRQHandler + PUBWEAK SPI1_IRQHandler + PUBWEAK USART0_IRQHandler + PUBWEAK USART1_IRQHandler + PUBWEAK UART0_IRQHandler + PUBWEAK UART1_IRQHandler + PUBWEAK LEDC_IRQHandler + PUBWEAK PDMA_CH0_1_IRQHandler + PUBWEAK PDMA_CH2_5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +LVD_BOD_IRQHandler +RTC_IRQHandler +FLASH_IRQHandler +EVWUP_IRQHandler +EXTI0_1_IRQHandler +EXTI2_3_IRQHandler +EXTI4_15_IRQHandler +COMP_IRQHandler +ADC_IRQHandler +MCTM0_IRQHandler +GPTM0_IRQHandler +PWM0_IRQHandler +PWM1_IRQHandler +BFTM0_IRQHandler +BFTM1_IRQHandler +I2C0_IRQHandler +I2C1_IRQHandler +SPI0_IRQHandler +SPI1_IRQHandler +USART0_IRQHandler +USART1_IRQHandler +UART0_IRQHandler +UART1_IRQHandler +LEDC_IRQHandler +PDMA_CH0_1_IRQHandler +PDMA_CH2_5_IRQHandler + B . + + END diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/IAR/startup_ht32f5xxxx_iar_15.s b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/IAR/startup_ht32f5xxxx_iar_15.s new file mode 100644 index 0000000000..cf8b05ac9b --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/IAR/startup_ht32f5xxxx_iar_15.s @@ -0,0 +1,215 @@ +;/*---------------------------------------------------------------------------------------------------------*/ +;/* Holtek Semiconductor Inc. */ +;/* */ +;/* Copyright (C) Holtek Semiconductor Inc. */ +;/* All rights reserved. */ +;/* */ +;/*----------------------------------------------------------------------------------------------------------- +; File Name : startup_ht32f5xxxx_iar_15.s +; Version : $Rev:: 6902 $ +; Date : $Date:: 2023-05-08 #$ +; Description : Startup code. +;-----------------------------------------------------------------------------------------------------------*/ + +; Supported Device +; ======================================== +; HT32F53242, HT32F53252 +; HT32F53231, HT32F53241 + +;/* <<< Use Configuration Wizard in Context Menu >>> */ + +;// HT32 Device +;// <0=> By Project Asm Define +;// <28=> HT32F53242_52 +;// <29=> HT32F53231_41 +USE_HT32_CHIP_SET EQU 0 + +_HT32FWID EQU 0xFFFFFFFF +;_HT32FWID EQU 0x00053242 +;_HT32FWID EQU 0x00053252 +;_HT32FWID EQU 0x00053231 +;_HT32FWID EQU 0x00053241 + +HT32F53242_52 EQU 28 +HT32F53231_41 EQU 29 + + IF USE_HT32_CHIP_SET=0 + ELSE + #undef USE_HT32_CHIP + #define USE_HT32_CHIP USE_HT32_CHIP_SET + ENDIF + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + EXTERN SystemInit + PUBLIC __vector_table + +;******************************************************************************* +; Fill-up the Vector Table entries with the exceptions ISR address +;******************************************************************************* + DATA +_RESERVED EQU 0xFFFFFFFF +__vector_table + DCD sfe(CSTACK) ; ---, 00, 0x000, Top address of Stack + DCD Reset_Handler ; ---, 01, 0x004, Reset Handler + DCD NMI_Handler ; -14, 02, 0x008, NMI Handler + DCD HardFault_Handler ; -13, 03, 0x00C, Hard Fault Handler + DCD _RESERVED ; ---, 04, 0x010, Reserved + DCD _RESERVED ; ---, 05, 0x014, Reserved + DCD _RESERVED ; ---, 06, 0x018, Reserved + DCD _RESERVED ; ---, 07, 0x01C, Reserved + DCD _HT32FWID ; ---, 08, 0x020, Reserved + DCD _RESERVED ; ---, 09, 0x024, Reserved + DCD _RESERVED ; ---, 10, 0x028, Reserved + DCD SVC_Handler ; -05, 11, 0x02C, SVC Handler + DCD _RESERVED ; ---, 12, 0x030, Reserved + DCD _RESERVED ; ---, 13, 0x034, Reserved + DCD PendSV_Handler ; -02, 14, 0x038, PendSV Handler + DCD SysTick_Handler ; -01, 15, 0x03C, SysTick Handler + + ; External Interrupt Handler + DCD LVD_BOD_IRQHandler ; 00, 16, 0x040, + DCD RTC_IRQHandler ; 01, 17, 0x044, + DCD FLASH_IRQHandler ; 02, 18, 0x048, + DCD EVWUP_IRQHandler ; 03, 19, 0x04C, + DCD EXTI0_1_IRQHandler ; 04, 20, 0x050, + DCD EXTI2_3_IRQHandler ; 05, 21, 0x054, + DCD EXTI4_15_IRQHandler ; 06, 22, 0x058, + IF (USE_HT32_CHIP=HT32F53242_52) + DCD COMP_IRQHandler ; 07, 23, 0x05C, + ELSE + DCD _RESERVED ; 07, 23, 0x05C, + ENDIF + DCD ADC_IRQHandler ; 08, 24, 0x060, + DCD _RESERVED ; 09, 25, 0x064, + DCD MCTM0_IRQHandler ; 10, 26, 0x068, + DCD _RESERVED ; 11, 27, 0x06C, + DCD GPTM0_IRQHandler ; 12, 28, 0x070, + DCD _RESERVED ; 13, 29, 0x074, + DCD _RESERVED ; 14, 30, 0x078, + DCD PWM0_IRQHandler ; 15, 31, 0x07C, + IF (USE_HT32_CHIP=HT32F53242_52) + DCD PWM1_IRQHandler ; 16, 32, 0x080, + ELSE + DCD _RESERVED ; 16, 32, 0x080, + ENDIF + DCD BFTM0_IRQHandler ; 17, 33, 0x084, + DCD BFTM1_IRQHandler ; 18, 34, 0x088, + DCD I2C0_IRQHandler ; 19, 35, 0x08C, + DCD I2C1_IRQHandler ; 20, 36, 0x090, + DCD SPI0_IRQHandler ; 21, 37, 0x094, + DCD SPI1_IRQHandler ; 22, 38, 0x098, + DCD USART0_IRQHandler ; 23, 39, 0x09C, + IF (USE_HT32_CHIP=HT32F53242_52) + DCD USART1_IRQHandler ; 24, 40, 0x0A0, + ELSE + DCD _RESERVED ; 24, 40, 0x0A0, + ENDIF + DCD UART0_IRQHandler ; 25, 41, 0x0A4, + DCD UART1_IRQHandler ; 26, 42, 0x0A8, + DCD CAN0_IRQHandler ; 27, 43, 0x0AC, + DCD _RESERVED ; 28, 44, 0x0B0, + DCD LEDC_IRQHandler ; 29, 45, 0x0B4, + DCD PDMA_CH0_1_IRQHandler ; 30, 46, 0x0B8, + DCD PDMA_CH2_5_IRQHandler ; 31, 47, 0x0BC, + + THUMB + + PUBWEAK Reset_Handler + SECTION .text:CODE:REORDER:NOROOT(2) +Reset_Handler + LDR R0, =SystemInit + BLX R0 + LDR R0, =__iar_program_start + BX R0 + + PUBWEAK NMI_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +NMI_Handler + B . + + PUBWEAK HardFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +HardFault_Handler + B . + + PUBWEAK SVC_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SVC_Handler + B . + + PUBWEAK PendSV_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PendSV_Handler + B . + + PUBWEAK SysTick_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SysTick_Handler + B . + + + PUBWEAK LVD_BOD_IRQHandler + PUBWEAK RTC_IRQHandler + PUBWEAK FLASH_IRQHandler + PUBWEAK EVWUP_IRQHandler + PUBWEAK EXTI0_1_IRQHandler + PUBWEAK EXTI2_3_IRQHandler + PUBWEAK EXTI4_15_IRQHandler + PUBWEAK COMP_IRQHandler + PUBWEAK ADC_IRQHandler + PUBWEAK MCTM0_IRQHandler + PUBWEAK GPTM0_IRQHandler + PUBWEAK PWM0_IRQHandler + PUBWEAK PWM1_IRQHandler + PUBWEAK BFTM0_IRQHandler + PUBWEAK BFTM1_IRQHandler + PUBWEAK I2C0_IRQHandler + PUBWEAK I2C1_IRQHandler + PUBWEAK SPI0_IRQHandler + PUBWEAK SPI1_IRQHandler + PUBWEAK USART0_IRQHandler + PUBWEAK USART1_IRQHandler + PUBWEAK UART0_IRQHandler + PUBWEAK UART1_IRQHandler + PUBWEAK CAN0_IRQHandler + PUBWEAK LEDC_IRQHandler + PUBWEAK PDMA_CH0_1_IRQHandler + PUBWEAK PDMA_CH2_5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +LVD_BOD_IRQHandler +RTC_IRQHandler +FLASH_IRQHandler +EVWUP_IRQHandler +EXTI0_1_IRQHandler +EXTI2_3_IRQHandler +EXTI4_15_IRQHandler +COMP_IRQHandler +ADC_IRQHandler +MCTM0_IRQHandler +GPTM0_IRQHandler +PWM0_IRQHandler +PWM1_IRQHandler +BFTM0_IRQHandler +BFTM1_IRQHandler +I2C0_IRQHandler +I2C1_IRQHandler +SPI0_IRQHandler +SPI1_IRQHandler +USART0_IRQHandler +USART1_IRQHandler +UART0_IRQHandler +UART1_IRQHandler +CAN0_IRQHandler +LEDC_IRQHandler +PDMA_CH0_1_IRQHandler +PDMA_CH2_5_IRQHandler + B . + + END diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/IAR/startup_ht32f5xxxx_iar_16.s b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/IAR/startup_ht32f5xxxx_iar_16.s new file mode 100644 index 0000000000..753e6eb165 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/IAR/startup_ht32f5xxxx_iar_16.s @@ -0,0 +1,224 @@ +;/*---------------------------------------------------------------------------------------------------------*/ +;/* Holtek Semiconductor Inc. */ +;/* */ +;/* Copyright (C) Holtek Semiconductor Inc. */ +;/* All rights reserved. */ +;/* */ +;/*----------------------------------------------------------------------------------------------------------- +; File Name : startup_ht32f5xxxx_iar_16.s +; Version : $Rev:: 7212 $ +; Date : $Date:: 2023-09-11 #$ +; Description : Startup code. +;-----------------------------------------------------------------------------------------------------------*/ + +; Supported Device +; ======================================== +; HT32F66242 +; HT32F66246 + +;/* <<< Use Configuration Wizard in Context Menu >>> */ + + + + + +USE_HT32_CHIP_SET EQU 0 + +;_HT32FWID EQU 0xFFFFFFFF +;_HT32FWID EQU 0x00066246 + +HT32F66246 EQU 31 +HT32F66242 EQU 33 + + IF USE_HT32_CHIP_SET=0 + ELSE + #undef USE_HT32_CHIP + #define USE_HT32_CHIP USE_HT32_CHIP_SET + ENDIF + + IF (USE_HT32_CHIP=0) +_HT32FWID EQU 0x00066246 + ENDIF + IF (USE_HT32_CHIP=HT32F66246) +_HT32FWID EQU 0x00066246 + ENDIF + IF (USE_HT32_CHIP=HT32F66242) +_HT32FWID EQU 0x00066242 + ENDIF + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + EXTERN SystemInit + PUBLIC __vector_table + +;******************************************************************************* +; Fill-up the Vector Table entries with the exceptions ISR address +;******************************************************************************* + DATA +_RESERVED EQU 0xFFFFFFFF +__vector_table + DCD sfe(CSTACK) ; ---, 00, 0x000, Top address of Stack + DCD Reset_Handler ; ---, 01, 0x004, Reset Handler + DCD NMI_Handler ; -14, 02, 0x008, NMI Handler + DCD HardFault_Handler ; -13, 03, 0x00C, Hard Fault Handler + DCD _RESERVED ; ---, 04, 0x010, Reserved + DCD _RESERVED ; ---, 05, 0x014, Reserved + DCD _RESERVED ; ---, 06, 0x018, Reserved + DCD _RESERVED ; ---, 07, 0x01C, Reserved + DCD _HT32FWID ; ---, 08, 0x020, Reserved + DCD _RESERVED ; ---, 09, 0x024, Reserved + DCD _RESERVED ; ---, 10, 0x028, Reserved + DCD SVC_Handler ; -05, 11, 0x02C, SVC Handler + DCD _RESERVED ; ---, 12, 0x030, Reserved + DCD _RESERVED ; ---, 13, 0x034, Reserved + DCD PendSV_Handler ; -02, 14, 0x038, PendSV Handler + DCD SysTick_Handler ; -01, 15, 0x03C, SysTick Handler + + ; External Interrupt Handler + DCD LVD_BOD_IRQHandler ; 00, 16, 0x040, + DCD RTC_IRQHandler ; 01, 17, 0x044, + DCD FLASH_IRQHandler ; 02, 18, 0x048, + DCD EVWUP_IRQHandler ; 03, 19, 0x04C, + DCD EXTI0_1_IRQHandler ; 04, 20, 0x050, + DCD EXTI2_3_IRQHandler ; 05, 21, 0x054, + DCD EXTI4_15_IRQHandler ; 06, 22, 0x058, + IF (USE_HT32_CHIP=HT32F66246) + DCD CAN0_IRQHandler ; 07, 23, 0x05C, + ELSE + DCD _RESERVED ; 07, 23, 0x05C, + ENDIF + DCD ADC_IRQHandler ; 08, 24, 0x060, + DCD CORDIC_IRQHandler ; 09, 25, 0x064, + DCD MCTM0_BRK_IRQHandler ; 10, 26, 0x068, + DCD MCTM0_UP_IRQHandler ; 11, 27, 0x06C, + DCD MCTM0_TR_UP2_IRQHandler ; 12, 28, 0x070, + DCD MCTM0_CC_IRQHandler ; 13, 29, 0x074, + DCD GPTM0_G_IRQHandler ; 14, 30, 0x078, + DCD GPTM0_VCLK_IRQHandler ; 15, 31, 0x07C, + DCD BFTM0_IRQHandler ; 16, 32, 0x080, + DCD BFTM1_IRQHandler ; 17, 33, 0x084, + DCD CMP0_IRQHandler ; 18, 34, 0x088, + DCD CMP1_IRQHandler ; 19, 35, 0x08C, + DCD PID_IRQHandler ; 20, 36, 0x090, + DCD I2C0_IRQHandler ; 21, 37, 0x094, + DCD SPI0_IRQHandler ; 22, 38, 0x098, + DCD USART0_IRQHandler ; 23, 39, 0x09C, + DCD UART0_IRQHandler ; 24, 40, 0x0A0, + DCD PDMA_CH0_1_IRQHandler ; 25, 41, 0x0A4, + DCD PDMA_CH2_3_IRQHandler ; 26, 42, 0x0A8, + DCD PDMA_CH4_5_IRQHandler ; 27, 43, 0x0AC, + DCD SCTM0_IRQHandler ; 28, 44, 0x0B0, + DCD SCTM1_IRQHandler ; 29, 45, 0x0B4, + DCD SCTM2_IRQHandler ; 30, 46, 0x0B8, + DCD SCTM3_IRQHandler ; 31, 47, 0x0BC, + + THUMB + + PUBWEAK Reset_Handler + SECTION .text:CODE:REORDER:NOROOT(2) +Reset_Handler + LDR R0, =SystemInit + BLX R0 + LDR R0, =__iar_program_start + BX R0 + + PUBWEAK NMI_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +NMI_Handler + B . + + PUBWEAK HardFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +HardFault_Handler + B . + + PUBWEAK SVC_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SVC_Handler + B . + + PUBWEAK PendSV_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PendSV_Handler + B . + + PUBWEAK SysTick_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SysTick_Handler + B . + + + PUBWEAK LVD_BOD_IRQHandler + PUBWEAK RTC_IRQHandler + PUBWEAK FLASH_IRQHandler + PUBWEAK EVWUP_IRQHandler + PUBWEAK EXTI0_1_IRQHandler + PUBWEAK EXTI2_3_IRQHandler + PUBWEAK EXTI4_15_IRQHandler + PUBWEAK CAN0_IRQHandler + PUBWEAK ADC_IRQHandler + PUBWEAK CORDIC_IRQHandler + PUBWEAK MCTM0_BRK_IRQHandler + PUBWEAK MCTM0_UP_IRQHandler + PUBWEAK MCTM0_TR_UP2_IRQHandler + PUBWEAK MCTM0_CC_IRQHandler + PUBWEAK GPTM0_G_IRQHandler + PUBWEAK GPTM0_VCLK_IRQHandler + PUBWEAK BFTM0_IRQHandler + PUBWEAK BFTM1_IRQHandler + PUBWEAK CMP0_IRQHandler + PUBWEAK CMP1_IRQHandler + PUBWEAK PID_IRQHandler + PUBWEAK I2C0_IRQHandler + PUBWEAK SPI0_IRQHandler + PUBWEAK USART0_IRQHandler + PUBWEAK UART0_IRQHandler + PUBWEAK PDMA_CH0_1_IRQHandler + PUBWEAK PDMA_CH2_3_IRQHandler + PUBWEAK PDMA_CH4_5_IRQHandler + PUBWEAK SCTM0_IRQHandler + PUBWEAK SCTM1_IRQHandler + PUBWEAK SCTM2_IRQHandler + PUBWEAK SCTM3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +LVD_BOD_IRQHandler +RTC_IRQHandler +FLASH_IRQHandler +EVWUP_IRQHandler +EXTI0_1_IRQHandler +EXTI2_3_IRQHandler +EXTI4_15_IRQHandler +CAN0_IRQHandler +ADC_IRQHandler +CORDIC_IRQHandler +MCTM0_BRK_IRQHandler +MCTM0_UP_IRQHandler +MCTM0_TR_UP2_IRQHandler +MCTM0_CC_IRQHandler +GPTM0_G_IRQHandler +GPTM0_VCLK_IRQHandler +BFTM0_IRQHandler +BFTM1_IRQHandler +CMP0_IRQHandler +CMP1_IRQHandler +PID_IRQHandler +I2C0_IRQHandler +SPI0_IRQHandler +USART0_IRQHandler +UART0_IRQHandler +PDMA_CH0_1_IRQHandler +PDMA_CH2_3_IRQHandler +PDMA_CH4_5_IRQHandler +SCTM0_IRQHandler +SCTM1_IRQHandler +SCTM2_IRQHandler +SCTM3_IRQHandler + B . + + END diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/IAR/startup_ht32f5xxxx_iar_17.s b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/IAR/startup_ht32f5xxxx_iar_17.s new file mode 100644 index 0000000000..bfabd93ba9 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/IAR/startup_ht32f5xxxx_iar_17.s @@ -0,0 +1,188 @@ +;/*---------------------------------------------------------------------------------------------------------*/ +;/* Holtek Semiconductor Inc. */ +;/* */ +;/* Copyright (C) Holtek Semiconductor Inc. */ +;/* All rights reserved. */ +;/* */ +;/*----------------------------------------------------------------------------------------------------------- +; File Name : startup_ht32f5xxxx_iar_17.s +; Version : $Rev:: 7212 $ +; Date : $Date:: 2023-09-11 #$ +; Description : Startup code. +;-----------------------------------------------------------------------------------------------------------*/ + +; Supported Device +; ======================================== +; HT32F52234, HT32F52244 + +;/* <<< Use Configuration Wizard in Context Menu >>> */ + +;// HT32 Device +;// <0=> By Project Asm Define +;// <33=> HT32F52234/44 +USE_HT32_CHIP_SET EQU 0 + +_HT32FWID EQU 0xFFFFFFFF +;_HT32FWID EQU 0x00052234 +;_HT32FWID EQU 0x00052244 + +HT32F52234_44 EQU 33 + + IF USE_HT32_CHIP_SET=0 + ELSE + #undef USE_HT32_CHIP + #define USE_HT32_CHIP USE_HT32_CHIP_SET + ENDIF + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + EXTERN SystemInit + PUBLIC __vector_table + +;******************************************************************************* +; Fill-up the Vector Table entries with the exceptions ISR address +;******************************************************************************* + DATA +_RESERVED EQU 0xFFFFFFFF +__vector_table + DCD sfe(CSTACK) ; ---, 00, 0x000, Top address of Stack + DCD Reset_Handler ; ---, 01, 0x004, Reset Handler + DCD NMI_Handler ; -14, 02, 0x008, NMI Handler + DCD HardFault_Handler ; -13, 03, 0x00C, Hard Fault Handler + DCD _RESERVED ; ---, 04, 0x010, Reserved + DCD _RESERVED ; ---, 05, 0x014, Reserved + DCD _RESERVED ; ---, 06, 0x018, Reserved + DCD _RESERVED ; ---, 07, 0x01C, Reserved + DCD _HT32FWID ; ---, 08, 0x020, Reserved + DCD _RESERVED ; ---, 09, 0x024, Reserved + DCD _RESERVED ; ---, 10, 0x028, Reserved + DCD SVC_Handler ; -05, 11, 0x02C, SVC Handler + DCD _RESERVED ; ---, 12, 0x030, Reserved + DCD _RESERVED ; ---, 13, 0x034, Reserved + DCD PendSV_Handler ; -02, 14, 0x038, PendSV Handler + DCD SysTick_Handler ; -01, 15, 0x03C, SysTick Handler + + ; External Interrupt Handler + DCD LVD_BOD_IRQHandler ; 00, 16, 0x040, + DCD RTC_IRQHandler ; 01, 17, 0x044, + DCD FLASH_IRQHandler ; 02, 18, 0x048, + DCD EVWUP_IRQHandler ; 03, 19, 0x04C, + DCD EXTI0_1_IRQHandler ; 04, 20, 0x050, + DCD EXTI2_3_IRQHandler ; 05, 21, 0x054, + DCD EXTI4_15_IRQHandler ; 06, 22, 0x058, + DCD DAC0_1_IRQHandler ; 07, 23, 0x05C, + DCD ADC_IRQHandler ; 08, 24, 0x060, + DCD I2C2_IRQHandler ; 09, 25, 0x064, + DCD _RESERVED ; 10, 26, 0x068, + DCD _RESERVED ; 11, 27, 0x06C, + DCD _RESERVED ; 12, 28, 0x070, + DCD SCTM0_IRQHandler ; 13, 29, 0x074, + DCD SCTM1_IRQHandler ; 14, 30, 0x078, + DCD PWM0_IRQHandler ; 15, 31, 0x07C, + DCD _RESERVED ; 16, 32, 0x080, + DCD BFTM0_IRQHandler ; 17, 33, 0x084, + DCD BFTM1_IRQHandler ; 18, 34, 0x088, + DCD I2C0_IRQHandler ; 19, 35, 0x08C, + DCD I2C1_IRQHandler ; 20, 36, 0x090, + DCD SPI0_IRQHandler ; 21, 37, 0x094, + DCD _RESERVED ; 22, 38, 0x098, + DCD USART0_IRQHandler ; 23, 39, 0x09C, + DCD _RESERVED ; 24, 40, 0x0A0, + DCD UART0_IRQHandler ; 25, 41, 0x0A4, + DCD _RESERVED ; 26, 42, 0x0A8, + DCD _RESERVED ; 27, 43, 0x0AC, + DCD _RESERVED ; 28, 44, 0x0B0, + DCD _RESERVED ; 29, 45, 0x0B4, + DCD PDMA_CH0_1_IRQHandler ; 30, 46, 0x0B8, + DCD PDMA_CH2_5_IRQHandler ; 31, 47, 0x0BC, + + THUMB + + PUBWEAK Reset_Handler + SECTION .text:CODE:REORDER:NOROOT(2) +Reset_Handler + LDR R0, =SystemInit + BLX R0 + LDR R0, =__iar_program_start + BX R0 + + PUBWEAK NMI_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +NMI_Handler + B . + + PUBWEAK HardFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +HardFault_Handler + B . + + PUBWEAK SVC_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SVC_Handler + B . + + PUBWEAK PendSV_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PendSV_Handler + B . + + PUBWEAK SysTick_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SysTick_Handler + B . + + + PUBWEAK LVD_BOD_IRQHandler + PUBWEAK RTC_IRQHandler + PUBWEAK FLASH_IRQHandler + PUBWEAK EVWUP_IRQHandler + PUBWEAK EXTI0_1_IRQHandler + PUBWEAK EXTI2_3_IRQHandler + PUBWEAK EXTI4_15_IRQHandler + PUBWEAK DAC0_1_IRQHandler + PUBWEAK ADC_IRQHandler + PUBWEAK I2C2_IRQHandler + PUBWEAK SCTM0_IRQHandler + PUBWEAK SCTM1_IRQHandler + PUBWEAK PWM0_IRQHandler + PUBWEAK BFTM0_IRQHandler + PUBWEAK BFTM1_IRQHandler + PUBWEAK I2C0_IRQHandler + PUBWEAK I2C1_IRQHandler + PUBWEAK SPI0_IRQHandler + PUBWEAK USART0_IRQHandler + PUBWEAK UART0_IRQHandler + PUBWEAK PDMA_CH0_1_IRQHandler + PUBWEAK PDMA_CH2_5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +LVD_BOD_IRQHandler +RTC_IRQHandler +FLASH_IRQHandler +EVWUP_IRQHandler +EXTI0_1_IRQHandler +EXTI2_3_IRQHandler +EXTI4_15_IRQHandler +DAC0_1_IRQHandler +ADC_IRQHandler +I2C2_IRQHandler +SCTM0_IRQHandler +SCTM1_IRQHandler +PWM0_IRQHandler +BFTM0_IRQHandler +BFTM1_IRQHandler +I2C0_IRQHandler +I2C1_IRQHandler +SPI0_IRQHandler +USART0_IRQHandler +UART0_IRQHandler +PDMA_CH0_1_IRQHandler +PDMA_CH2_5_IRQHandler + B . + + END diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/IAR/startup_ht32f65230_40_iar.s b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/IAR/startup_ht32f65230_40_iar.s new file mode 100644 index 0000000000..695ea54ce5 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/IAR/startup_ht32f65230_40_iar.s @@ -0,0 +1,209 @@ +;/*---------------------------------------------------------------------------------------------------------*/ +;/* Holtek Semiconductor Inc. */ +;/* */ +;/* Copyright (C) Holtek Semiconductor Inc. */ +;/* All rights reserved. */ +;/* */ +;/*----------------------------------------------------------------------------------------------------------- +; File Name : startup_ht32f65230_40_iar.s +; Version : $Rev:: 6877 $ +; Date : $Date:: 2023-05-04 #$ +; Description : Startup code. +;-----------------------------------------------------------------------------------------------------------*/ + +; Supported Device +; ======================================== +; HT32F65230 +; HT32F65240 + +;/* <<< Use Configuration Wizard in Context Menu >>> */ + +;// HT32 Device +;// <0=> By Project Asm Define +;// <12=> HT32F65230_40 +USE_HT32_CHIP_SET EQU 0 + +_HT32FWID EQU 0xFFFFFFFF +;_HT32FWID EQU 0x00065230 +;_HT32FWID EQU 0x00065240 + +HT32F65230_40 EQU 12 + + IF USE_HT32_CHIP_SET=0 + ELSE + #undef USE_HT32_CHIP + #define USE_HT32_CHIP USE_HT32_CHIP_SET + ENDIF + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + EXTERN SystemInit + PUBLIC __vector_table + +;******************************************************************************* +; Fill-up the Vector Table entries with the exceptions ISR address +;******************************************************************************* + DATA +_RESERVED EQU 0xFFFFFFFF +__vector_table + DCD sfe(CSTACK) ; ---, 00, 0x000, Top address of Stack + DCD Reset_Handler ; ---, 01, 0x004, Reset Handler + DCD NMI_Handler ; -14, 02, 0x008, NMI Handler + DCD HardFault_Handler ; -13, 03, 0x00C, Hard Fault Handler + DCD _RESERVED ; ---, 04, 0x010, Reserved + DCD _RESERVED ; ---, 05, 0x014, Reserved + DCD _RESERVED ; ---, 06, 0x018, Reserved + DCD _RESERVED ; ---, 07, 0x01C, Reserved + DCD _HT32FWID ; ---, 08, 0x020, Reserved + DCD _RESERVED ; ---, 09, 0x024, Reserved + DCD _RESERVED ; ---, 10, 0x028, Reserved + DCD SVC_Handler ; -05, 11, 0x02C, SVC Handler + DCD _RESERVED ; ---, 12, 0x030, Reserved + DCD _RESERVED ; ---, 13, 0x034, Reserved + DCD PendSV_Handler ; -02, 14, 0x038, PendSV Handler + DCD SysTick_Handler ; -01, 15, 0x03C, SysTick Handler + + ; External Interrupt Handler + DCD LVD_BOD_IRQHandler ; 00, 16, 0x040, + DCD RTC_IRQHandler ; 01, 17, 0x044, + DCD FLASH_IRQHandler ; 02, 18, 0x048, + DCD EVWUP_IRQHandler ; 03, 19, 0x04C, + DCD EXTI0_1_IRQHandler ; 04, 20, 0x050, + DCD EXTI2_3_IRQHandler ; 05, 21, 0x054, + DCD EXTI4_9_IRQHandler ; 06, 22, 0x058, + DCD EXTI10_15_IRQHandler ; 07, 23, 0x05C, + DCD ADC0_IRQHandler ; 08, 24, 0x060, + DCD ADC1_IRQHandler ; 09, 25, 0x064, + DCD MCTM0_BRK_IRQHandler ; 10, 26, 0x068, + DCD MCTM0_UP_IRQHandler ; 11, 27, 0x06C, + DCD MCTM0_TR_UP2_IRQHandler ; 12, 28, 0x070, + DCD MCTM0_CC_IRQHandler ; 13, 29, 0x074, + DCD GPTM0_G_IRQHandler ; 14, 30, 0x078, + DCD GPTM0_VCLK_IRQHandler ; 15, 31, 0x07C, + DCD BFTM0_IRQHandler ; 16, 32, 0x080, + DCD BFTM1_IRQHandler ; 17, 33, 0x084, + DCD CMP0_IRQHandler ; 18, 34, 0x088, + DCD CMP1_IRQHandler ; 19, 35, 0x08C, + DCD CMP2_IRQHandler ; 20, 36, 0x090, + DCD I2C0_IRQHandler ; 21, 37, 0x094, + DCD SPI0_IRQHandler ; 22, 38, 0x098, + DCD USART0_IRQHandler ; 23, 39, 0x09C, + DCD UART0_IRQHandler ; 24, 40, 0x0A0, + DCD PDMA_CH0_1_IRQHandler ; 25, 41, 0x0A4, + DCD PDMA_CH2_3_IRQHandler ; 26, 42, 0x0A8, + DCD PDMA_CH4_5_IRQHandler ; 27, 43, 0x0AC, + DCD SCTM0_IRQHandler ; 28, 44, 0x0B0, + DCD SCTM1_IRQHandler ; 29, 45, 0x0B4, + DCD SCTM2_IRQHandler ; 30, 46, 0x0B8, + DCD SCTM3_IRQHandler ; 31, 47, 0x0BC, + + THUMB + + PUBWEAK Reset_Handler + SECTION .text:CODE:REORDER:NOROOT(2) +Reset_Handler + LDR R0, =SystemInit + BLX R0 + LDR R0, =__iar_program_start + BX R0 + + PUBWEAK NMI_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +NMI_Handler + B . + + PUBWEAK HardFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +HardFault_Handler + B . + + PUBWEAK SVC_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SVC_Handler + B . + + PUBWEAK PendSV_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PendSV_Handler + B . + + PUBWEAK SysTick_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SysTick_Handler + B . + + + PUBWEAK LVD_BOD_IRQHandler + PUBWEAK RTC_IRQHandler + PUBWEAK FLASH_IRQHandler + PUBWEAK EVWUP_IRQHandler + PUBWEAK EXTI0_1_IRQHandler + PUBWEAK EXTI2_3_IRQHandler + PUBWEAK EXTI4_9_IRQHandler + PUBWEAK EXTI10_15_IRQHandler + PUBWEAK ADC0_IRQHandler + PUBWEAK ADC1_IRQHandler + PUBWEAK MCTM0_BRK_IRQHandler + PUBWEAK MCTM0_UP_IRQHandler + PUBWEAK MCTM0_TR_UP2_IRQHandler + PUBWEAK MCTM0_CC_IRQHandler + PUBWEAK GPTM0_G_IRQHandler + PUBWEAK GPTM0_VCLK_IRQHandler + PUBWEAK BFTM0_IRQHandler + PUBWEAK BFTM1_IRQHandler + PUBWEAK CMP0_IRQHandler + PUBWEAK CMP1_IRQHandler + PUBWEAK CMP2_IRQHandler + PUBWEAK I2C0_IRQHandler + PUBWEAK SPI0_IRQHandler + PUBWEAK USART0_IRQHandler + PUBWEAK UART0_IRQHandler + PUBWEAK PDMA_CH0_1_IRQHandler + PUBWEAK PDMA_CH2_3_IRQHandler + PUBWEAK PDMA_CH4_5_IRQHandler + PUBWEAK SCTM0_IRQHandler + PUBWEAK SCTM1_IRQHandler + PUBWEAK SCTM2_IRQHandler + PUBWEAK SCTM3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +LVD_BOD_IRQHandler +RTC_IRQHandler +FLASH_IRQHandler +EVWUP_IRQHandler +EXTI0_1_IRQHandler +EXTI2_3_IRQHandler +EXTI4_9_IRQHandler +EXTI10_15_IRQHandler +ADC0_IRQHandler +ADC1_IRQHandler +MCTM0_BRK_IRQHandler +MCTM0_UP_IRQHandler +MCTM0_TR_UP2_IRQHandler +MCTM0_CC_IRQHandler +GPTM0_G_IRQHandler +GPTM0_VCLK_IRQHandler +BFTM0_IRQHandler +BFTM1_IRQHandler +CMP0_IRQHandler +CMP1_IRQHandler +CMP2_IRQHandler +I2C0_IRQHandler +SPI0_IRQHandler +USART0_IRQHandler +UART0_IRQHandler +PDMA_CH0_1_IRQHandler +PDMA_CH2_3_IRQHandler +PDMA_CH4_5_IRQHandler +SCTM0_IRQHandler +SCTM1_IRQHandler +SCTM2_IRQHandler +SCTM3_IRQHandler + B . + + END diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/emStudio/SEGGER_THUMB_Startup.s b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/emStudio/SEGGER_THUMB_Startup.s new file mode 100644 index 0000000000..63a379c804 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/emStudio/SEGGER_THUMB_Startup.s @@ -0,0 +1,435 @@ +// ********************************************************************** +// * SEGGER Microcontroller GmbH * +// * The Embedded Experts * +// ********************************************************************** +// * * +// * (c) 2014 - 2018 SEGGER Microcontroller GmbH * +// * (c) 2001 - 2018 Rowley Associates Limited * +// * * +// * www.segger.com Support: support@segger.com * +// * * +// ********************************************************************** +// * * +// * All rights reserved. * +// * * +// * Redistribution and use in source and binary forms, with or * +// * without modification, are permitted provided that the following * +// * conditions are met: * +// * * +// * - Redistributions of source code must retain the above copyright * +// * notice, this list of conditions and the following disclaimer. * +// * * +// * - Neither the name of SEGGER Microcontroller GmbH * +// * nor the names of its contributors may be used to endorse or * +// * promote products derived from this software without specific * +// * prior written permission. * +// * * +// * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND * +// * CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, * +// * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * +// * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * +// * DISCLAIMED. * +// * IN NO EVENT SHALL SEGGER Microcontroller GmbH BE LIABLE FOR * +// * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * +// * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT * +// * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; * +// * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF * +// * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * +// * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE * +// * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH * +// * DAMAGE. * +// * * +// ********************************************************************** +// Preprocessor Definitions +// ------------------------ +// +// FULL_LIBRARY +// +// If defined then +// - argc, argv are setup by the debug_getargs. +// - the exit symbol is defined and executes on return from main. +// - the exit symbol calls destructors, atexit functions and then debug_exit. +// +// If not defined then +// - argc and argv are zero. +// - the exit symbol is defined, executes on return from main and loops +// + + .syntax unified + + .section .segger.init.__SEGGER_init_lzss, "ax" + .code 16 + .balign 2 + .global __SEGGER_init_lzss +.thumb_func +__SEGGER_init_lzss: + ldr r0, [r4] @ destination + ldr r1, [r4, #4] @ source stream + adds r4, r4, #8 +2: + ldrb r2, [r1] + adds r1, r1, #1 + tst r2, r2 + beq 9f @ 0 -> end of table + cmp r2, #0x80 + bcc 1f @ +ve -> literal run +// +// -ve -> copy run +// +// r0 = pointer to output stream +// r1 = pointer to input stream +// r2 = run length +// r3 = copy byte +// r4 = pointer to initialization table +// +3: + subs r2, r2, #0x80 // convert to run length + beq 10f + ldrb r3, [r1] // r3 = first byte of distance + adds r1, r1, #1 + cmp r3, #0x80 + bcc 5f // r3 < 128, short run + subs r3, r3, #0x80 // Adjust to recover true run length high byte + lsls r3, r3, #8 // Prepare to fuse + ldrb r5, [r1] // extract run length low byte + adds r1, r1, #1 + adds r3, r3, r5 // construct run length +5: + subs r5, r0, r3 // source of where to copy from +4: + ldrb r3, [r5] // source byte of run + strb r3, [r0] // store to destination + adds r5, r5, #1 + adds r0, r0, #1 + subs r2, r2, #1 + bne 4b + b 2b +// +// +ve -> literal run +// +// r0 = pointer to output stream +// r1 = pointer to input stream +// r2 = run length +// r3 = copy byte +// r4 = pointer to initialization table +// +1: + ldrb r3, [r1] // source byte of run + adds r1, r1, #1 + strb r3, [r0] // store to destination + adds r0, r0, #1 + subs r2, r2, #1 + bne 1b + b 2b +9: + bx lr +10: + b 10b + + .section .segger.init.__SEGGER_init_zero, "ax" + .code 16 + .balign 2 + .global __SEGGER_init_zero +.thumb_func +__SEGGER_init_zero: + ldr r0, [r4] @ destination + ldr r1, [r4, #4] @ size + adds r4, r4, #8 + tst r1, r1 + beq 2f + movs r2, #0 +1: + strb r2, [r0] + adds r0, r0, #1 + subs r1, r1, #1 + bne 1b +2: + bx lr + + .section .segger.init.__SEGGER_init_copy, "ax" + .code 16 + .balign 2 + .global __SEGGER_init_copy +.thumb_func +__SEGGER_init_copy: + ldr r0, [r4] @ destination + ldr r1, [r4, #4] @ source + ldr r2, [r4, #8] @ size + adds r4, r4, #12 + tst r2, r2 + beq 2f +1: + ldrb r3, [r1] + strb r3, [r0] + adds r0, r0, #1 + adds r1, r1, #1 + subs r2, r2, #1 + bne 1b +2: + bx lr + + .section .segger.init.__SEGGER_init_pack, "ax" + .code 16 + .balign 2 + .global __SEGGER_init_pack +.thumb_func +__SEGGER_init_pack: + ldr r0, [r4] @ destination + ldr r1, [r4, #4] @ source stream + adds r4, r4, #8 +1: + ldrb r2, [r1] + adds r1, r1, #1 + cmp r2, #0x80 + beq 4f + bcc 3f + ldrb r3, [r1] @ byte to replicate + adds r1, r1, #1 + negs r2, r2 + adds r2, r2, #255 + adds r2, r2, #1 +2: + strb r3, [r0] + adds r0, r0, #1 + subs r2, r2, #1 + bpl 2b + b 1b + +3: @ 1+n literal bytes + ldrb r3, [r1] + strb r3, [r0] + adds r0, r0, #1 + adds r1, r1, #1 + subs r2, r2, #1 + bpl 3b + b 1b +4: + bx lr + + .section .segger.init.__SEGGER_init_zpak, "ax" + .code 16 + .balign 2 + .global __SEGGER_init_zpak +.thumb_func +__SEGGER_init_zpak: + ldr r0, [r4] @ destination + ldr r1, [r4, #4] @ source stream + ldr r2, [r4, #8] @ size + adds r4, r4, #12 @ skip table entries +1: + ldrb r3, [r1] @ get control byte from source stream + adds r1, r1, #1 + movs r6, #8 +2: + movs r5, #0 @ prepare zero filler + lsrs r3, r3, #1 @ get byte control flag + bcs 3f @ carry set -> zero filler + ldrb r5, [r1] @ get literal byte from source stream + adds r1, r1, #1 +3: + strb r5, [r0] @ store initialization byte + adds r0, r0, #1 + subs r2, r2, #1 @ size -= 1 + beq 4f @ exit when destination filled + subs r6, r6, #1 @ decrement bit count + bne 2b @ still within this control byte + b 1b @ get next control byte +4: + bx lr + +#ifndef APP_ENTRY_POINT +#define APP_ENTRY_POINT main +#endif + +#ifndef ARGSSPACE +#define ARGSSPACE 128 +#endif + + .global _start + .extern APP_ENTRY_POINT + .global exit + .weak exit + +#ifdef INITIALIZE_USER_SECTIONS + .extern InitializeUserMemorySections +#endif + + .section .init, "ax" + .code 16 + .align 1 + .thumb_func + +_start: + ldr r0, = __stack_end__ + mov sp, r0 + ldr r4, =__SEGGER_init_table__ +1: + ldr r0, [r4] + adds r4, r4, #4 + tst r0, r0 + beq 2f + blx r0 + b 1b +2: + + /* Initialize the heap */ + ldr r0, = __heap_start__ + ldr r1, = __heap_end__ + subs r1, r1, r0 + cmp r1, #8 + blt 1f + movs r2, #0 + str r2, [r0] + adds r0, r0, #4 + str r1, [r0] +1: + +#ifdef INITIALIZE_USER_SECTIONS + ldr r2, =InitializeUserMemorySections + blx r2 +#endif + + /* Call constructors */ + ldr r0, =__ctors_start__ + ldr r1, =__ctors_end__ +ctor_loop: + cmp r0, r1 + beq ctor_end + ldr r2, [r0] + adds r0, #4 + push {r0-r1} + blx r2 + pop {r0-r1} + b ctor_loop +ctor_end: + + /* Setup initial call frame */ + movs r0, #0 + mov lr, r0 + mov r12, sp + + .type start, function +start: + /* Jump to application entry point */ +#ifdef FULL_LIBRARY + movs r0, #ARGSSPACE + ldr r1, =args + ldr r2, =debug_getargs + blx r2 + ldr r1, =args +#else + movs r0, #0 + movs r1, #0 +#endif + ldr r2, =APP_ENTRY_POINT + blx r2 + + .thumb_func +exit: +#ifdef FULL_LIBRARY + mov r5, r0 // save the exit parameter/return result + + /* Call destructors */ + ldr r0, =__dtors_start__ + ldr r1, =__dtors_end__ +dtor_loop: + cmp r0, r1 + beq dtor_end + ldr r2, [r0] + add r0, #4 + push {r0-r1} + blx r2 + pop {r0-r1} + b dtor_loop +dtor_end: + + /* Call atexit functions */ + ldr r2, =_execute_at_exit_fns + blx r2 + + /* Call debug_exit with return result/exit parameter */ + mov r0, r5 + ldr r2, =debug_exit + blx r2 +#endif + + /* Returned from application entry point, loop forever. */ +exit_loop: + b exit_loop + + // default C/C++ library helpers + +.macro HELPER helper_name + .section .text.\helper_name, "ax", %progbits + .global \helper_name + .align 1 + .weak \helper_name +\helper_name: + .thumb_func +.endm + +.macro JUMPTO name +#if defined(__thumb__) && !defined(__thumb2__) + mov r12, r0 + ldr r0, =\name + push {r0} + mov r0, r12 + pop {pc} +#else + b \name +#endif +.endm + +HELPER __aeabi_read_tp + ldr r0, =__tbss_start__-8 + bx lr +HELPER abort + b . +HELPER __assert + b . +HELPER __aeabi_assert + b . +HELPER __sync_synchronize + bx lr +HELPER __getchar + JUMPTO debug_getchar +HELPER __putchar + JUMPTO debug_putchar +HELPER __open + JUMPTO debug_fopen +HELPER __close + JUMPTO debug_fclose +HELPER __write + mov r3, r0 + mov r0, r1 + movs r1, #1 + JUMPTO debug_fwrite +HELPER __read + mov r3, r0 + mov r0, r1 + movs r1, #1 + JUMPTO debug_fread +HELPER __seek + push {r4, lr} + mov r4, r0 + bl debug_fseek + cmp r0, #0 + bne 1f + mov r0, r4 + bl debug_ftell + pop {r4, pc} +1: + ldr r0, =-1 + pop {r4, pc} + // char __user_locale_name_buffer[]; + .section .bss.__user_locale_name_buffer, "aw", %nobits + .global __user_locale_name_buffer + .weak __user_locale_name_buffer + __user_locale_name_buffer: + .word 0x0 + +#ifdef FULL_LIBRARY + .bss +args: + .space ARGSSPACE +#endif diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/emStudio/startup_ht32f5xxxx_es_01.s b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/emStudio/startup_ht32f5xxxx_es_01.s new file mode 100644 index 0000000000..a667619b58 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/emStudio/startup_ht32f5xxxx_es_01.s @@ -0,0 +1,426 @@ +/*---------------------------------------------------------------------------------------------------------*/ +/* Holtek Semiconductor Inc. */ +/* */ +/* Copyright (C) Holtek Semiconductor Inc. */ +/* All rights reserved. */ +/* */ +/*----------------------------------------------------------------------------------------------------------- +; File Name : startup_ht32f5xxxx_es_01.s +; Version : $Rev:: 6953 $ +; Date : $Date:: 2023-05-30 #$ +; Description : Startup code. +;-----------------------------------------------------------------------------------------------------------*/ + +/* +; Supported Device +; ======================================== +; HT32F52220, HT32F52230 +; HT32F52231, HT32F52241 +; HT32F52331, HT32F52341 +; HT32F52342, HT32F52352 +; HT32F52243, HT32F52253 +; HT32F0008 +; HT32F52344, HT32F52354 +; HT32F0006 +; HT32F61352 +; HT50F32003 +; HT32F62030, HT32F62040, HT32F62050 +; HT32F67741 +; HT32F67232 +; HT32F67233 +*/ + +;/* <<< Use Configuration Wizard in Context Menu >>> */ +/* +;// HT32 Device +;// <0=> By Project Asm Define +;// <1=> HT32F52220/30 +;// <2=> HT32F52231/41 +;// <3=> HT32F52331/41 +;// <4=> HT32F52342/52 +;// <5=> HT32F52243/53 +;// <6=> HT32F0008 +;// <9=> HT32F52344/54 +;// <10=> HT32F0006 +;// <10=> HT32F61352 +;// <4=> HT50F32003 +;// <2=> HT32F67741 +;// <1=> HT32F67232 +;// <1=> HT32F67233 +;// <1=> HT32F62030 +;// <2=> HT32F62040 +;// <5=> HT32F62050 +*/ + .equ USE_HT32_CHIP_SET, 0 + + .equ _HT32FWID, 0xFFFFFFFF +/* + .equ _HT32FWID, 0x00052220 + .equ _HT32FWID, 0x00052230 + .equ _HT32FWID, 0x00052231 + .equ _HT32FWID, 0x00052241 + .equ _HT32FWID, 0x00052331 + .equ _HT32FWID, 0x00052341 + .equ _HT32FWID, 0x00052342 + .equ _HT32FWID, 0x00052352 + .equ _HT32FWID, 0x00052243 + .equ _HT32FWID, 0x00052253 + .equ _HT32FWID, 0x00000008 + .equ _HT32FWID, 0x00052344 + .equ _HT32FWID, 0x00052354 + .equ _HT32FWID, 0x00000006 + .equ _HT32FWID, 0x00061352 + .equ _HT32FWID, 0x00032003 + .equ _HT32FWID, 0x00062030 + .equ _HT32FWID, 0x00062040 + .equ _HT32FWID, 0x00062050 + .equ _HT32FWID, 0x00067741 + .equ _HT32FWID, 0x00067232 + .equ _HT32FWID, 0x00067233 +*/ + + .equ HT32F52220_30, 1 + .equ HT32F52231_41, 2 + .equ HT32F52331_41, 3 + .equ HT32F52342_52, 4 + .equ HT32F52243_53, 5 + .equ HT32F0008, 6 + .equ HT32F52344_54, 9 + .equ HT32F0006, 10 + .equ HT32F61352, 10 + .equ HT50F32003, 4 + .equ HT32F62030, 1 + .equ HT32F62040, 2 + .equ HT32F62050, 5 + .equ HT32F67741, 2 + .equ HT32F67232, 1 + .equ HT32F67233, 1 + + .if USE_HT32_CHIP_SET == 0 + .else + .equ USE_HT32_CHIP, USE_HT32_CHIP_SET + .endif + + .equ _RESERVED, 0xFFFFFFFF +/* +;******************************************************************************* +; Fill-up the Vector Table entries with the exceptions ISR address +;********************************************************************************/ + .syntax unified + .global reset_handler + .global Reset_Handler + .equ Reset_Handler, reset_handler + + .section .vectors, "ax" + .section .vectors, "ax" + .code 16 + .balign 2 + .global _vectors +_vectors: + .long __stack_end__ /* ---, 00, 0x000, Top address of Stack */ + .long reset_handler /* ---, 01, 0x004, Reset Handler */ + .long NMI_Handler /* -14, 02, 0x008, NMI Handler */ + .long HardFault_Handler /* -13, 03, 0x00C, Hard Fault Handler */ + .long _RESERVED /* ---, 04, 0x010, Reserved */ + .long _RESERVED /* ---, 05, 0x014, Reserved */ + .long _RESERVED /* ---, 06, 0x018, Reserved */ + .long _RESERVED /* ---, 07, 0x01C, Reserved */ + .long _HT32FWID /* ---, 08, 0x020, Reserved */ + .long _RESERVED /* ---, 09, 0x024, Reserved */ + .long _RESERVED /* ---, 10, 0x028, Reserved */ + .long SVC_Handler /* -05, 11, 0x02C, SVC Handler */ + .long _RESERVED /* ---, 12, 0x030, Reserved */ + .long _RESERVED /* ---, 13, 0x034, Reserved */ + .long PendSV_Handler /* -02, 14, 0x038, PendSV Handler */ + .long SysTick_Handler /* -01, 15, 0x03C, SysTick Handler */ + + /* External Interrupt Handler */ + .long LVD_BOD_IRQHandler /* 00, 16, 0x040, */ + .if (USE_HT32_CHIP==HT32F52220_30) + .long _RESERVED /* 01, 17, 0x044, */ + .else + .long RTC_IRQHandler /* 01, 17, 0x044, */ + .endif + .long FLASH_IRQHandler /* 02, 18, 0x048, */ + .long EVWUP_IRQHandler /* 03, 19, 0x04C, */ + .long EXTI0_1_IRQHandler /* 04, 20, 0x050, */ + .long EXTI2_3_IRQHandler /* 05, 21, 0x054, */ + .long EXTI4_15_IRQHandler /* 06, 22, 0x058, */ + .if (USE_HT32_CHIP==HT32F52342_52) || (USE_HT32_CHIP==HT32F52344_54) + .long COMP_IRQHandler /* 07, 23, 0x05C, */ + .else + .long _RESERVED /* 07, 23, 0x05C, */ + .endif + .if (USE_HT32_CHIP==HT32F0008) + .long _RESERVED /* 08, 24, 0x060, */ + .else + .long ADC_IRQHandler /* 08, 24, 0x060, */ + .endif + .if (USE_HT32_CHIP==HT32F52243_53) + .long I2C2_IRQHandler /* 09, 25, 0x064, */ + .else + .long _RESERVED /* 09, 25, 0x064, */ + .endif + .if (USE_HT32_CHIP==HT32F52220_30) || (USE_HT32_CHIP==HT32F0008) || (USE_HT32_CHIP==HT32F0006) + .long _RESERVED /* 10, 26, 0x068, */ + .else + .long MCTM0_IRQHandler /* 10, 26, 0x068, */ + .endif + .if (USE_HT32_CHIP==HT32F52342_52) + .long GPTM1_IRQHandler /* 11, 27, 0x06C, */ + .else + .long _RESERVED /* 11, 27, 0x06C, */ + .endif + .long GPTM0_IRQHandler /* 12, 28, 0x070, */ + .if (USE_HT32_CHIP==HT32F0008) + .long _RESERVED /* 13, 29, 0x074, */ + .long _RESERVED /* 14, 30, 0x078, */ + .else + .long SCTM0_IRQHandler /* 13, 29, 0x074, */ + .long SCTM1_IRQHandler /* 14, 30, 0x078, */ + .endif + .if (USE_HT32_CHIP==HT32F52231_41) || (USE_HT32_CHIP==HT32F52331_41) || (USE_HT32_CHIP==HT32F52243_53) || (USE_HT32_CHIP==HT32F0006) + .long SCTM2_IRQHandler /* 15, 31, 0x07C, */ + .long SCTM3_IRQHandler /* 16, 32, 0x080, */ + .endif + .if (USE_HT32_CHIP==HT32F0008) + .long PWM0_IRQHandler /* 15, 31, 0x07C, */ + .long PWM1_IRQHandler /* 16, 32, 0x080, */ + .endif + .if (USE_HT32_CHIP==HT32F52220_30) || (USE_HT32_CHIP==HT32F52342_52) || (USE_HT32_CHIP==HT32F52344_54) + .long _RESERVED /* 15, 31, 0x07C, */ + .long _RESERVED /* 16, 32, 0x080, */ + .endif + .long BFTM0_IRQHandler /* 17, 33, 0x084, */ + .if (USE_HT32_CHIP==HT32F52220_30) + .long _RESERVED /* 18, 34, 0x088, */ + .else + .long BFTM1_IRQHandler /* 18, 34, 0x088, */ + .endif + .long I2C0_IRQHandler /* 19, 35, 0x08C, */ + .if (USE_HT32_CHIP==HT32F52220_30) || (USE_HT32_CHIP==HT32F0008) || (USE_HT32_CHIP==HT32F52344_54) || (USE_HT32_CHIP==HT32F0006) + .long _RESERVED /* 20, 36, 0x090, */ + .else + .long I2C1_IRQHandler /* 20, 36, 0x090, */ + .endif + .long SPI0_IRQHandler /* 21, 37, 0x094, */ + .if (USE_HT32_CHIP==HT32F52220_30) || (USE_HT32_CHIP==HT32F0008) + .long _RESERVED /* 22, 38, 0x098, */ + .else + .if (USE_HT32_CHIP==HT32F0006) + .long QSPI_IRQHandler /* 22, 38, 0x098, */ + .else + .long SPI1_IRQHandler /* 22, 38, 0x098, */ + .endif + .endif + .if (USE_HT32_CHIP==HT32F52344_54) + .long _RESERVED /* 23, 39, 0x09C, */ + .else + .long USART0_IRQHandler /* 23, 39, 0x09C, */ + .endif + .if (USE_HT32_CHIP==HT32F52342_52) || (USE_HT32_CHIP==HT32F52243_53) + .long USART1_IRQHandler /* 24, 40, 0x0A0, */ + .else + .long _RESERVED /* 24, 40, 0x0A0, */ + .endif + .long UART0_IRQHandler /* 25, 41, 0x0A4, */ + .if (USE_HT32_CHIP==HT32F52220_30) || (USE_HT32_CHIP==HT32F0008) || (USE_HT32_CHIP==HT32F0006) + .long _RESERVED /* 26, 42, 0x0A8, */ + .else + .long UART1_IRQHandler /* 26, 42, 0x0A8, */ + .endif + .if (USE_HT32_CHIP==HT32F52331_41) || (USE_HT32_CHIP==HT32F52342_52) + .long SCI_IRQHandler /* 27, 43, 0x0AC, */ + .endif + .if (USE_HT32_CHIP==HT32F52243_53) + .long UART2_IRQHandler /* 27, 43, 0x0AC, */ + .endif + .if (USE_HT32_CHIP==HT32F0006) + .long MIDI_IRQHandler /* 27, 43, 0x0AC, */ + .endif + .if (USE_HT32_CHIP==HT32F0008) || (USE_HT32_CHIP==HT32F52344_54) + .long _RESERVED /* 27, 43, 0xAC, */ + .endif + .if (USE_HT32_CHIP==HT32F52342_52) || (USE_HT32_CHIP==HT32F0006) + .long I2S_IRQHandler /* 28, 44, 0x0B0, */ + .endif + .if (USE_HT32_CHIP==HT32F52331_41) || (USE_HT32_CHIP==HT32F52344_54) + .long _RESERVED /* 28, 44, 0x0B0, */ + .endif + .if (USE_HT32_CHIP==HT32F52243_53) + .long UART3_IRQHandler /* 28, 44, 0x0B0, */ + .endif + .if (USE_HT32_CHIP==HT32F0008) + .long AES_IRQHandler /* 28, 44, 0x0B0, */ + .endif + .if (USE_HT32_CHIP==HT32F52331_41) || (USE_HT32_CHIP==HT32F52342_52) || (USE_HT32_CHIP==HT32F0008) || (USE_HT32_CHIP==HT32F52344_54) || (USE_HT32_CHIP==HT32F0006) + .long USB_IRQHandler /* 29, 45, 0x0B4, */ + .endif + .if (USE_HT32_CHIP==HT32F52243_53) + .long _RESERVED /* 29, 45, 0x0B4, */ + .endif + .if (USE_HT32_CHIP==HT32F52342_52) || (USE_HT32_CHIP==HT32F52243_53) || (USE_HT32_CHIP==HT32F0008) || (USE_HT32_CHIP==HT32F52344_54) || (USE_HT32_CHIP==HT32F0006) + .long PDMA_CH0_1_IRQHandler /* 30, 46, 0x0B8, */ + .long PDMA_CH2_5_IRQHandler /* 31, 47, 0x0BC, */ + .endif + + + + .thumb + + +/* Reset Handler */ + + .section .text.reset_handler + .weak reset_handler + .type reset_handler, %function +reset_handler: + LDR R0, =__stack_end__ /* set stack pointer */ + MOV SP, R0 + LDR R0, =BootProcess + BLX R0 + LDR R0, =SystemInit + BLX R0 + BL _start + + .thumb_func +BootProcess: + LDR R0, =0x40080300 + LDR R1,[R0, #0x10] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x14] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x18] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x1C] + CMP R1, #0 + BEQ BP2 +BP1: + LDR R0, =0x40080180 + LDR R1,[R0, #0xC] + LSLS R1, R1, #4 + LSRS R1, R1, #20 + CMP R1, #0 + BEQ BP3 + CMP R1, #5 + BEQ BP3 + CMP R1, #6 + BEQ BP3 +BP2: + DSB + LDR R0, =0x20000000 + LDR R1, =0x05fa0004 + STR R1, [R0] + LDR R1, =0xe000ed00 + LDR R0, =0x05fa0004 + STR R0, [R1, #0xC] + DSB + B . +BP3: + LDR R0, =0x20000000 + LDR R1, [R0] + LDR R0, =0x05fa0004 + CMP R0, R1 + BEQ BP4 + BX LR +BP4: + LDR R0, =0x40088100 + LDR R1, =0x00000001 + STR R1, [R0] + LDR R0, =0x20000000 + LDR R1, =0x0 + STR R1, [R0] + BX LR + + .size Reset_Handler, .-Reset_Handler + +/* Exception Handlers */ + + .weak NMI_Handler + .type NMI_Handler, %function +NMI_Handler: + B . + .size NMI_Handler, . - NMI_Handler + + .weak HardFault_Handler + .type HardFault_Handler, %function +HardFault_Handler: + B . + .size HardFault_Handler, . - HardFault_Handler + + .weak SVC_Handler + .type SVC_Handler, %function +SVC_Handler: + B . + .size SVC_Handler, . - SVC_Handler + + .weak PendSV_Handler + .type PendSV_Handler, %function +PendSV_Handler: + B . + .size PendSV_Handler, . - PendSV_Handler + + .weak SysTick_Handler + .type SysTick_Handler, %function +SysTick_Handler: + B . + .size SysTick_Handler, . - SysTick_Handler + + +/* IRQ Handlers */ + + .globl Default_Handler + .type Default_Handler, %function +Default_Handler: + B . + .size Default_Handler, . - Default_Handler + + .macro IRQ handler + .weak \handler + .set \handler, Default_Handler + .endm + + IRQ LVD_BOD_IRQHandler + IRQ RTC_IRQHandler + IRQ FLASH_IRQHandler + IRQ EVWUP_IRQHandler + IRQ EXTI0_1_IRQHandler + IRQ EXTI2_3_IRQHandler + IRQ EXTI4_15_IRQHandler + IRQ COMP_IRQHandler + IRQ ADC_IRQHandler + IRQ MCTM0_IRQHandler + IRQ GPTM1_IRQHandler + IRQ GPTM0_IRQHandler + IRQ SCTM0_IRQHandler + IRQ SCTM1_IRQHandler + IRQ SCTM2_IRQHandler + IRQ SCTM3_IRQHandler + IRQ PWM0_IRQHandler + IRQ PWM1_IRQHandler + IRQ BFTM0_IRQHandler + IRQ BFTM1_IRQHandler + IRQ I2C0_IRQHandler + IRQ I2C1_IRQHandler + IRQ I2C2_IRQHandler + IRQ SPI0_IRQHandler + IRQ SPI1_IRQHandler + IRQ QSPI_IRQHandler + IRQ USART0_IRQHandler + IRQ USART1_IRQHandler + IRQ UART0_IRQHandler + IRQ UART1_IRQHandler + IRQ UART2_IRQHandler + IRQ UART3_IRQHandler + IRQ SCI_IRQHandler + IRQ MIDI_IRQHandler + IRQ I2S_IRQHandler + IRQ AES_IRQHandler + IRQ USB_IRQHandler + IRQ PDMA_CH0_1_IRQHandler + IRQ PDMA_CH2_5_IRQHandler + + .end diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/emStudio/startup_ht32f5xxxx_es_02.s b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/emStudio/startup_ht32f5xxxx_es_02.s new file mode 100644 index 0000000000..5b5110f922 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/emStudio/startup_ht32f5xxxx_es_02.s @@ -0,0 +1,289 @@ +/*---------------------------------------------------------------------------------------------------------*/ +/* Holtek Semiconductor Inc. */ +/* */ +/* Copyright (C) Holtek Semiconductor Inc. */ +/* All rights reserved. */ +/* */ +/*----------------------------------------------------------------------------------------------------------- +; File Name : startup_ht32f5xxxx_es_02.s +; Version : $Rev:: 7119 $ +; Date : $Date:: 2023-08-15 #$ +; Description : Startup code. +;-----------------------------------------------------------------------------------------------------------*/ + +/* +; Supported Device +; ======================================== +; HT32F50220, HT32F50230 +; HT32F50231, HT32F50241 +; HT50F32002 +; HT32F59041 +; HF5032 +; HT32F61641 +; HT32F59046 +; HT32F61041 +*/ + +;/* <<< Use Configuration Wizard in Context Menu >>> */ +/* +;// HT32 Device +;// <0=> By Project Asm Define +;// <7=> HT32F50220/30 +;// <8=> HT32F50231/41 +;// <7=> HT50F32002 +;// <8=> HT32F59041 +;// <7=> HF5032 +;// <8=> HT32F61641 +;// <8=> HT32F59046 +;// <8=> HT32F61041 +*/ + .equ USE_HT32_CHIP_SET, 0 + + .equ _HT32FWID, 0xFFFFFFFF +/* + .equ _HT32FWID, 0x00050220 + .equ _HT32FWID, 0x00050230 + .equ _HT32FWID, 0x00050231 + .equ _HT32FWID, 0x00050241 + .equ _HT32FWID, 0x00032002 + .equ _HT32FWID, 0x00059041 + .equ _HT32FWID, 0x000F5032 + .equ _HT32FWID, 0x00061641 + .equ _HT32FWID, 0x00059046 + .equ _HT32FWID, 0x00061041 +*/ + + .equ HT32F50220_30, 7 + .equ HT32F50231_41, 8 + .equ HT50F32002, 7 + .equ HT32F59041, 8 + .equ HF5032, 7 + .equ HT32F61641, 8 + .equ HT32F59046, 8 + .equ HT32F61041, 8 + + .if USE_HT32_CHIP_SET == 0 + .else + .equ USE_HT32_CHIP, USE_HT32_CHIP_SET + .endif + + .equ _RESERVED, 0xFFFFFFFF +/* +;******************************************************************************* +; Fill-up the Vector Table entries with the exceptions ISR address +;********************************************************************************/ + .syntax unified + .global reset_handler + .global Reset_Handler + .equ Reset_Handler, reset_handler + + .section .vectors, "ax" + .section .vectors, "ax" + .code 16 + .balign 2 + .global _vectors +_vectors: + .long __stack_end__ /* ---, 00, 0x000, Top address of Stack */ + .long reset_handler /* ---, 01, 0x004, Reset Handler */ + .long NMI_Handler /* -14, 02, 0x008, NMI Handler */ + .long HardFault_Handler /* -13, 03, 0x00C, Hard Fault Handler */ + .long _RESERVED /* ---, 04, 0x010, Reserved */ + .long _RESERVED /* ---, 05, 0x014, Reserved */ + .long _RESERVED /* ---, 06, 0x018, Reserved */ + .long _RESERVED /* ---, 07, 0x01C, Reserved */ + .long _HT32FWID /* ---, 08, 0x020, Reserved */ + .long _RESERVED /* ---, 09, 0x024, Reserved */ + .long _RESERVED /* ---, 10, 0x028, Reserved */ + .long SVC_Handler /* -05, 11, 0x02C, SVC Handler */ + .long _RESERVED /* ---, 12, 0x030, Reserved */ + .long _RESERVED /* ---, 13, 0x034, Reserved */ + .long PendSV_Handler /* -02, 14, 0x038, PendSV Handler */ + .long SysTick_Handler /* -01, 15, 0x03C, SysTick Handler */ + + /* External Interrupt Handler */ + .long LVD_BOD_IRQHandler /* 00, 16, 0x040, */ + .long RTC_IRQHandler /* 01, 17, 0x044, */ + .long FLASH_IRQHandler /* 02, 18, 0x048, */ + .long EVWUP_IRQHandler /* 03, 19, 0x04C, */ + .long EXTI0_1_IRQHandler /* 04, 20, 0x050, */ + .long EXTI2_3_IRQHandler /* 05, 21, 0x054, */ + .long EXTI4_15_IRQHandler /* 06, 22, 0x058, */ + .long _RESERVED /* 07, 23, 0x05C, */ + .long ADC_IRQHandler /* 08, 24, 0x060, */ + .long _RESERVED /* 09, 25, 0x064, */ + .if (USE_HT32_CHIP==HT32F50220_30) + .long _RESERVED /* 10, 26, 0x068, */ + .else + .long MCTM0_IRQHandler /* 10, 26, 0x068, */ + .endif + .long _RESERVED /* 11, 27, 0x06C, */ + .long GPTM0_IRQHandler /* 12, 28, 0x070, */ + .long _RESERVED /* 13, 29, 0x074, */ + .long _RESERVED /* 14, 30, 0x078, */ + .long PWM0_IRQHandler /* 15, 31, 0x07C, */ + .long PWM1_IRQHandler /* 16, 32, 0x080, */ + .long BFTM0_IRQHandler /* 17, 33, 0x084, */ + .if (USE_HT32_CHIP==HT32F50220_30) + .long _RESERVED /* 18, 34, 0x088, */ + .else + .long BFTM1_IRQHandler /* 18, 34, 0x088, */ + .endif + .long I2C0_IRQHandler /* 19, 35, 0x08C, */ + .if (USE_HT32_CHIP==HT32F50220_30) + .long _RESERVED /* 20, 36, 0x090, */ + .else + .long I2C1_IRQHandler /* 20, 36, 0x090, */ + .endif + .long SPI0_IRQHandler /* 21, 37, 0x094, */ + .long SPI1_IRQHandler /* 22, 38, 0x098, */ + .if (USE_HT32_CHIP==HT32F50220_30) + .long _RESERVED /* 23, 39, 0x09C, */ + .else + .long USART0_IRQHandler /* 23, 39, 0x09C, */ + .endif + .long _RESERVED /* 24, 40, 0x0A0, */ + .long UART0_IRQHandler /* 25, 41, 0x0A4, */ + .long UART1_IRQHandler /* 26, 42, 0x0A8, */ + + + + .thumb + + +/* Reset Handler */ + + .section .text.reset_handler + .weak reset_handler + .type reset_handler, %function +reset_handler: + LDR R0, =__stack_end__ /* set stack pointer */ + MOV SP, R0 + LDR R0, =BootProcess + BLX R0 + LDR R0, =SystemInit + BLX R0 + BL _start + + .thumb_func +BootProcess: + LDR R0, =0x40080300 + LDR R1,[R0, #0x10] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x14] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x18] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x1C] + CMP R1, #0 + BEQ BP2 +BP1: + LDR R0, =0x40080180 + LDR R1,[R0, #0xC] + LSLS R1, R1, #4 + LSRS R1, R1, #20 + CMP R1, #0 + BEQ BP3 + CMP R1, #5 + BEQ BP3 + CMP R1, #6 + BEQ BP3 +BP2: + DSB + LDR R0, =0x20000000 + LDR R1, =0x05fa0004 + STR R1, [R0] + LDR R1, =0xe000ed00 + LDR R0, =0x05fa0004 + STR R0, [R1, #0xC] + DSB + B . +BP3: + LDR R0, =0x20000000 + LDR R1, [R0] + LDR R0, =0x05fa0004 + CMP R0, R1 + BEQ BP4 + BX LR +BP4: + LDR R0, =0x40088100 + LDR R1, =0x00000001 + STR R1, [R0] + LDR R0, =0x20000000 + LDR R1, =0x0 + STR R1, [R0] + BX LR + + .size Reset_Handler, .-Reset_Handler + +/* Exception Handlers */ + + .weak NMI_Handler + .type NMI_Handler, %function +NMI_Handler: + B . + .size NMI_Handler, . - NMI_Handler + + .weak HardFault_Handler + .type HardFault_Handler, %function +HardFault_Handler: + B . + .size HardFault_Handler, . - HardFault_Handler + + .weak SVC_Handler + .type SVC_Handler, %function +SVC_Handler: + B . + .size SVC_Handler, . - SVC_Handler + + .weak PendSV_Handler + .type PendSV_Handler, %function +PendSV_Handler: + B . + .size PendSV_Handler, . - PendSV_Handler + + .weak SysTick_Handler + .type SysTick_Handler, %function +SysTick_Handler: + B . + .size SysTick_Handler, . - SysTick_Handler + + +/* IRQ Handlers */ + + .globl Default_Handler + .type Default_Handler, %function +Default_Handler: + B . + .size Default_Handler, . - Default_Handler + + .macro IRQ handler + .weak \handler + .set \handler, Default_Handler + .endm + + IRQ LVD_BOD_IRQHandler + IRQ RTC_IRQHandler + IRQ FLASH_IRQHandler + IRQ EVWUP_IRQHandler + IRQ EXTI0_1_IRQHandler + IRQ EXTI2_3_IRQHandler + IRQ EXTI4_15_IRQHandler + IRQ ADC_IRQHandler + IRQ MCTM0_IRQHandler + IRQ GPTM0_IRQHandler + IRQ PWM0_IRQHandler + IRQ PWM1_IRQHandler + IRQ BFTM0_IRQHandler + IRQ BFTM1_IRQHandler + IRQ I2C0_IRQHandler + IRQ I2C1_IRQHandler + IRQ SPI0_IRQHandler + IRQ SPI1_IRQHandler + IRQ USART0_IRQHandler + IRQ UART0_IRQHandler + IRQ UART1_IRQHandler + + .end diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/emStudio/startup_ht32f5xxxx_es_03.s b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/emStudio/startup_ht32f5xxxx_es_03.s new file mode 100644 index 0000000000..e004b72345 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/emStudio/startup_ht32f5xxxx_es_03.s @@ -0,0 +1,351 @@ +/*---------------------------------------------------------------------------------------------------------*/ +/* Holtek Semiconductor Inc. */ +/* */ +/* Copyright (C) Holtek Semiconductor Inc. */ +/* All rights reserved. */ +/* */ +/*----------------------------------------------------------------------------------------------------------- +; File Name : startup_ht32f5xxxx_es_03.s +; Version : $Rev:: 6887 $ +; Date : $Date:: 2023-05-05 #$ +; Description : Startup code. +;-----------------------------------------------------------------------------------------------------------*/ + +/* +; Supported Device +; ======================================== +; HT32F0008 +; HT32F52142 +; HT32F52344, HT32F52354 +; HT32F52357, HT32F52367 +; HT50F3200T +*/ + +;/* <<< Use Configuration Wizard in Context Menu >>> */ +/* +;// HT32 Device +;// <0=> By Project Asm Define +;// <6=> HT32F0008 +;// <6=> HT32F52142 +;// <9=> HT32F52344/54 +;// <11=> HT32F52357/67 +;// <11=> HT50F3200T +*/ + .equ USE_HT32_CHIP_SET, 0 + + .equ _HT32FWID, 0xFFFFFFFF +/* + .equ _HT32FWID, 0x00000008 + .equ _HT32FWID, 0x00052142 + .equ _HT32FWID, 0x00052344 + .equ _HT32FWID, 0x00052354 + .equ _HT32FWID, 0x00052357 + .equ _HT32FWID, 0x00052367 + .equ _HT32FWID, 0x0003200F +*/ + + .equ HT32F0008, 6 + .equ HT32F52142, 6 + .equ HT32F52344_54, 9 + .equ HT32F52357_67, 11 + .equ HT50F3200T, 11 + + .if USE_HT32_CHIP_SET == 0 + .else + .equ USE_HT32_CHIP, USE_HT32_CHIP_SET + .endif + + .equ _RESERVED, 0xFFFFFFFF +/* +;******************************************************************************* +; Fill-up the Vector Table entries with the exceptions ISR address +;********************************************************************************/ + .syntax unified + .global reset_handler + .global Reset_Handler + .equ Reset_Handler, reset_handler + + .section .vectors, "ax" + .section .vectors, "ax" + .code 16 + .balign 2 + .global _vectors +_vectors: + .long __stack_end__ /* ---, 00, 0x000, Top address of Stack */ + .long reset_handler /* ---, 01, 0x004, Reset Handler */ + .long NMI_Handler /* -14, 02, 0x008, NMI Handler */ + .long HardFault_Handler /* -13, 03, 0x00C, Hard Fault Handler */ + .long _RESERVED /* ---, 04, 0x010, Reserved */ + .long _RESERVED /* ---, 05, 0x014, Reserved */ + .long _RESERVED /* ---, 06, 0x018, Reserved */ + .long _RESERVED /* ---, 07, 0x01C, Reserved */ + .long _HT32FWID /* ---, 08, 0x020, Reserved */ + .long _RESERVED /* ---, 09, 0x024, Reserved */ + .long _RESERVED /* ---, 10, 0x028, Reserved */ + .long SVC_Handler /* -05, 11, 0x02C, SVC Handler */ + .long _RESERVED /* ---, 12, 0x030, Reserved */ + .long _RESERVED /* ---, 13, 0x034, Reserved */ + .long PendSV_Handler /* -02, 14, 0x038, PendSV Handler */ + .long SysTick_Handler /* -01, 15, 0x03C, SysTick Handler */ + + /* External Interrupt Handler */ + .long LVD_BOD_IRQHandler /* 00, 16, 0x040, */ + .long RTC_IRQHandler /* 01, 17, 0x044, */ + .long FLASH_IRQHandler /* 02, 18, 0x048, */ + .long EVWUP_IRQHandler /* 03, 19, 0x04C, */ + .long EXTI0_1_IRQHandler /* 04, 20, 0x050, */ + .long EXTI2_3_IRQHandler /* 05, 21, 0x054, */ + .long EXTI4_15_IRQHandler /* 06, 22, 0x058, */ + .if (USE_HT32_CHIP==HT32F0008) + .long _RESERVED /* 07, 23, 0x05C, */ + .endif + .if (USE_HT32_CHIP==HT32F52344_54) + .long COMP_IRQHandler /* 07, 23, 0x05C, */ + .endif + .if (USE_HT32_CHIP==HT32F52357_67) + .long COMP_DAC_IRQHandler /* 07, 23, 0x05C, */ + .endif + .if (USE_HT32_CHIP==HT32F0008) + .long _RESERVED /* 08, 24, 0x060, */ + .else + .long ADC_IRQHandler /* 08, 24, 0x060, */ + .endif + .if (USE_HT32_CHIP==HT32F52357_67) + .long AES_IRQHandler /* 09, 25, 0x064, */ + .else + .long _RESERVED /* 09, 25, 0x064, */ + .endif + .if (USE_HT32_CHIP==HT32F0008) + .long _RESERVED /* 10, 26, 0x068, */ + .else + .long MCTM0_IRQHandler /* 10, 26, 0x068, */ + .endif + .if (USE_HT32_CHIP==HT32F52357_67) + .long QSPI_IRQHandler /* 11, 27, 0x06C, */ + .else + .long _RESERVED /* 11, 27, 0x06C, */ + .endif + .long GPTM0_IRQHandler /* 12, 28, 0x070, */ + .if (USE_HT32_CHIP==HT32F0008) + .long _RESERVED /* 13, 29, 0x074, */ + .long _RESERVED /* 14, 30, 0x078, */ + .else + .long SCTM0_IRQHandler /* 13, 29, 0x074, */ + .long SCTM1_IRQHandler /* 14, 30, 0x078, */ + .endif + .if (USE_HT32_CHIP==HT32F0008) || (USE_HT32_CHIP==HT32F52357_67) + .long PWM0_IRQHandler /* 15, 31, 0x07C, */ + .long PWM1_IRQHandler /* 16, 32, 0x080, */ + .endif + .if (USE_HT32_CHIP==HT32F52344_54) + .long _RESERVED /* 15, 31, 0x07C, */ + .long _RESERVED /* 16, 32, 0x080, */ + .endif + .long BFTM0_IRQHandler /* 17, 33, 0x084, */ + .long BFTM1_IRQHandler /* 18, 34, 0x088, */ + .long I2C0_IRQHandler /* 19, 35, 0x08C, */ + .if (USE_HT32_CHIP==HT32F0008) || (USE_HT32_CHIP==HT32F52344_54) + .long _RESERVED /* 20, 36, 0x090, */ + .else + .long I2C1_IRQHandler /* 20, 36, 0x090, */ + .endif + .long SPI0_IRQHandler /* 21, 37, 0x094, */ + .if (USE_HT32_CHIP==HT32F0008) + .long _RESERVED /* 22, 38, 0x098, */ + .else + .long SPI1_IRQHandler /* 22, 38, 0x098, */ + .endif + .if (USE_HT32_CHIP==HT32F52344_54) + .long _RESERVED /* 23, 39, 0x09C, */ + .else + .long USART0_IRQHandler /* 23, 39, 0x09C, */ + .endif + .if (USE_HT32_CHIP==HT32F0008) + .long _RESERVED /* 24, 40, 0x0A0, */ + .long UART0_IRQHandler /* 25, 41, 0x0A4, */ + .long _RESERVED /* 26, 42, 0x0A8, */ + .endif + .if (USE_HT32_CHIP==HT32F52344_54) + .long _RESERVED /* 24, 40, 0x0A0, */ + .long UART0_IRQHandler /* 25, 41, 0x0A4, */ + .long UART1_IRQHandler /* 26, 42, 0x0A8, */ + .endif + .if (USE_HT32_CHIP==HT32F52357_67) + .long USART1_IRQHandler /* 24, 40, 0x0A0, */ + .long UART0_UART2_IRQHandler /* 25, 41, 0x0A4, */ + .long UART1_UART3_IRQHandler /* 26, 42, 0x0A8, */ + .endif + .if (USE_HT32_CHIP==HT32F52357_67) + .long SCI_IRQHandler /* 27, 43, 0x0AC, */ + .else + .long _RESERVED /* 27, 43, 0x0AC, */ + .endif + .if (USE_HT32_CHIP==HT32F0008) + .long AES_IRQHandler /* 28, 44, 0x0B0, */ + .endif + .if (USE_HT32_CHIP==HT32F52344_54) + .long _RESERVED /* 28, 44, 0x0B0, */ + .endif + .if (USE_HT32_CHIP==HT32F52357_67) + .long I2S_IRQHandler /* 28, 44, 0x0B0, */ + .endif + .long USB_IRQHandler /* 29, 45, 0x0B4, */ + .long PDMA_CH0_1_IRQHandler /* 30, 46, 0x0B8, */ + .long PDMA_CH2_5_IRQHandler /* 31, 47, 0x0BC, */ + + + + .thumb + + +/* Reset Handler */ + + .section .text.reset_handler + .weak reset_handler + .type reset_handler, %function +reset_handler: + LDR R0, =__stack_end__ /* set stack pointer */ + MOV SP, R0 + LDR R0, =BootProcess + BLX R0 + LDR R0, =SystemInit + BLX R0 + BL _start + + .thumb_func +BootProcess: + LDR R0, =0x40080300 + LDR R1,[R0, #0x10] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x14] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x18] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x1C] + CMP R1, #0 + BEQ BP2 +BP1: + LDR R0, =0x40080180 + LDR R1,[R0, #0xC] + LSLS R1, R1, #4 + LSRS R1, R1, #20 + CMP R1, #0 + BEQ BP3 + CMP R1, #5 + BEQ BP3 + CMP R1, #6 + BEQ BP3 +BP2: + DSB + LDR R0, =0x20000000 + LDR R1, =0x05fa0004 + STR R1, [R0] + LDR R1, =0xe000ed00 + LDR R0, =0x05fa0004 + STR R0, [R1, #0xC] + DSB + B . +BP3: + LDR R0, =0x20000000 + LDR R1, [R0] + LDR R0, =0x05fa0004 + CMP R0, R1 + BEQ BP4 + BX LR +BP4: + LDR R0, =0x40088100 + LDR R1, =0x00000001 + STR R1, [R0] + LDR R0, =0x20000000 + LDR R1, =0x0 + STR R1, [R0] + BX LR + + .size Reset_Handler, .-Reset_Handler + +/* Exception Handlers */ + + .weak NMI_Handler + .type NMI_Handler, %function +NMI_Handler: + B . + .size NMI_Handler, . - NMI_Handler + + .weak HardFault_Handler + .type HardFault_Handler, %function +HardFault_Handler: + B . + .size HardFault_Handler, . - HardFault_Handler + + .weak SVC_Handler + .type SVC_Handler, %function +SVC_Handler: + B . + .size SVC_Handler, . - SVC_Handler + + .weak PendSV_Handler + .type PendSV_Handler, %function +PendSV_Handler: + B . + .size PendSV_Handler, . - PendSV_Handler + + .weak SysTick_Handler + .type SysTick_Handler, %function +SysTick_Handler: + B . + .size SysTick_Handler, . - SysTick_Handler + + +/* IRQ Handlers */ + + .globl Default_Handler + .type Default_Handler, %function +Default_Handler: + B . + .size Default_Handler, . - Default_Handler + + .macro IRQ handler + .weak \handler + .set \handler, Default_Handler + .endm + + IRQ LVD_BOD_IRQHandler + IRQ RTC_IRQHandler + IRQ FLASH_IRQHandler + IRQ EVWUP_IRQHandler + IRQ EXTI0_1_IRQHandler + IRQ EXTI2_3_IRQHandler + IRQ EXTI4_15_IRQHandler + IRQ COMP_IRQHandler + IRQ COMP_DAC_IRQHandler + IRQ ADC_IRQHandler + IRQ MCTM0_IRQHandler + IRQ GPTM0_IRQHandler + IRQ SCTM0_IRQHandler + IRQ SCTM1_IRQHandler + IRQ PWM0_IRQHandler + IRQ PWM1_IRQHandler + IRQ BFTM0_IRQHandler + IRQ BFTM1_IRQHandler + IRQ I2C0_IRQHandler + IRQ I2C1_IRQHandler + IRQ SPI0_IRQHandler + IRQ SPI1_IRQHandler + IRQ QSPI_IRQHandler + IRQ USART0_IRQHandler + IRQ USART1_IRQHandler + IRQ UART0_IRQHandler + IRQ UART1_IRQHandler + IRQ UART0_UART2_IRQHandler + IRQ UART1_UART3_IRQHandler + IRQ SCI_IRQHandler + IRQ I2S_IRQHandler + IRQ AES_IRQHandler + IRQ USB_IRQHandler + IRQ PDMA_CH0_1_IRQHandler + IRQ PDMA_CH2_5_IRQHandler + + .end diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/emStudio/startup_ht32f5xxxx_es_05.s b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/emStudio/startup_ht32f5xxxx_es_05.s new file mode 100644 index 0000000000..25447b9b1f --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/emStudio/startup_ht32f5xxxx_es_05.s @@ -0,0 +1,303 @@ +/*---------------------------------------------------------------------------------------------------------*/ +/* Holtek Semiconductor Inc. */ +/* */ +/* Copyright (C) Holtek Semiconductor Inc. */ +/* All rights reserved. */ +/* */ +/*----------------------------------------------------------------------------------------------------------- +; File Name : startup_ht32f5xxxx_es_05.s +; Version : $Rev:: 6993 $ +; Date : $Date:: 2023-06-26 #$ +; Description : Startup code. +;-----------------------------------------------------------------------------------------------------------*/ + +/* +; Supported Device +; ======================================== +; HT32F57331, HT32F57341 +; HT32F57342, HT32F57352 +; HT32F59741 +; HT32F5828 +; HT32F67742 +; HT32F59746 +*/ + +;/* <<< Use Configuration Wizard in Context Menu >>> */ +/* +;// HT32 Device +;// <0=> By Project Asm Define +;// <13=> HT32F57331/41 +;// <14=> HT32F57342/52 +;// <13=> HT32F59741 +;// <14=> HT32F5828 +;// <13=> HT32F67742 +;// <13=> HT32F59746 +*/ + .equ USE_HT32_CHIP_SET, 0 + + .equ _HT32FWID, 0xFFFFFFFF +/* + .equ _HT32FWID, 0x00057331 + .equ _HT32FWID, 0x00057341 + .equ _HT32FWID, 0x00057342 + .equ _HT32FWID, 0x00057352 + .equ _HT32FWID, 0x00059741 + .equ _HT32FWID, 0x00005828 + .equ _HT32FWID, 0x00067742 + .equ _HT32FWID, 0x00059746 +*/ + + .equ HT32F57331_41, 13 + .equ HT32F57342_52, 14 + .equ HT32F59741, 13 + .equ HT32F5828, 14 + .equ HT32F67742, 13 + .equ HT32F59746, 13 + + .if USE_HT32_CHIP_SET == 0 + .else + .equ USE_HT32_CHIP, USE_HT32_CHIP_SET + .endif + + .equ _RESERVED, 0xFFFFFFFF +/* +;******************************************************************************* +; Fill-up the Vector Table entries with the exceptions ISR address +;********************************************************************************/ + .syntax unified + .global reset_handler + .global Reset_Handler + .equ Reset_Handler, reset_handler + + .section .vectors, "ax" + .section .vectors, "ax" + .code 16 + .balign 2 + .global _vectors +_vectors: + .long __stack_end__ /* ---, 00, 0x000, Top address of Stack */ + .long reset_handler /* ---, 01, 0x004, Reset Handler */ + .long NMI_Handler /* -14, 02, 0x008, NMI Handler */ + .long HardFault_Handler /* -13, 03, 0x00C, Hard Fault Handler */ + .long _RESERVED /* ---, 04, 0x010, Reserved */ + .long _RESERVED /* ---, 05, 0x014, Reserved */ + .long _RESERVED /* ---, 06, 0x018, Reserved */ + .long _RESERVED /* ---, 07, 0x01C, Reserved */ + .long _HT32FWID /* ---, 08, 0x020, Reserved */ + .long _RESERVED /* ---, 09, 0x024, Reserved */ + .long _RESERVED /* ---, 10, 0x028, Reserved */ + .long SVC_Handler /* -05, 11, 0x02C, SVC Handler */ + .long _RESERVED /* ---, 12, 0x030, Reserved */ + .long _RESERVED /* ---, 13, 0x034, Reserved */ + .long PendSV_Handler /* -02, 14, 0x038, PendSV Handler */ + .long SysTick_Handler /* -01, 15, 0x03C, SysTick Handler */ + + /* External Interrupt Handler */ + .long LVD_BOD_IRQHandler /* 00, 16, 0x040, */ + .long RTC_IRQHandler /* 01, 17, 0x044, */ + .long FLASH_IRQHandler /* 02, 18, 0x048, */ + .long EVWUP_IRQHandler /* 03, 19, 0x04C, */ + .long EXTI0_1_IRQHandler /* 04, 20, 0x050, */ + .long EXTI2_3_IRQHandler /* 05, 21, 0x054, */ + .long EXTI4_15_IRQHandler /* 06, 22, 0x058, */ + .if (USE_HT32_CHIP==HT32F57331_41) + .long _RESERVED /* 07, 23, 0x05C, */ + .endif + .if (USE_HT32_CHIP==HT32F57342_52) + .long COMP_DAC_IRQHandler /* 07, 23, 0x05C, */ + .endif + .long ADC_IRQHandler /* 08, 24, 0x060, */ + .if (USE_HT32_CHIP==HT32F57331_41) + .long _RESERVED /* 09, 25, 0x064, */ + .endif + .if (USE_HT32_CHIP==HT32F57342_52) + .long AES_IRQHandler /* 09, 25, 0x064, */ + .endif + .long _RESERVED /* 10, 26, 0x068, */ + .long LCD_IRQHandler /* 11, 27, 0x06C, */ + .long GPTM0_IRQHandler /* 12, 28, 0x070, */ + .if (USE_HT32_CHIP==HT32F57331_41) + .long _RESERVED /* 13, 29, 0x074, */ + .long _RESERVED /* 14, 30, 0x078, */ + .endif + .if (USE_HT32_CHIP==HT32F57342_52) + .long SCTM0_IRQHandler /* 13, 29, 0x074, */ + .long SCTM1_IRQHandler /* 14, 30, 0x078, */ + .endif + .long PWM0_IRQHandler /* 15, 31, 0x07C, */ + .long PWM1_IRQHandler /* 16, 32, 0x080, */ + .long BFTM0_IRQHandler /* 17, 33, 0x084, */ + .long BFTM1_IRQHandler /* 18, 34, 0x088, */ + .long I2C0_IRQHandler /* 19, 35, 0x08C, */ + .long I2C1_IRQHandler /* 20, 36, 0x090, */ + .long SPI0_IRQHandler /* 21, 37, 0x094, */ + .long SPI1_IRQHandler /* 22, 38, 0x098, */ + .long USART0_IRQHandler /* 23, 39, 0x09C, */ + .long _RESERVED /* 24, 40, 0x0A0, */ + .long UART0_IRQHandler /* 25, 41, 0x0A4, */ + .long UART1_IRQHandler /* 26, 42, 0x0A8, */ + .long SCI_IRQHandler /* 27, 43, 0x0AC, */ + .long I2S_IRQHandler /* 28, 44, 0x0B0, */ + .long USB_IRQHandler /* 29, 45, 0x0B4, */ + .if (USE_HT32_CHIP==HT32F57331_41) + .long _RESERVED /* 30, 46, 0x0B8, */ + .long _RESERVED /* 31, 47, 0x0BC, */ + .endif + .if (USE_HT32_CHIP==HT32F57342_52) + .long PDMA_CH0_1_IRQHandler /* 30, 46, 0x0B8, */ + .long PDMA_CH2_5_IRQHandler /* 31, 47, 0x0BC, */ + .endif + + + + .thumb + + +/* Reset Handler */ + + .section .text.reset_handler + .weak reset_handler + .type reset_handler, %function +reset_handler: + LDR R0, =__stack_end__ /* set stack pointer */ + MOV SP, R0 + LDR R0, =BootProcess + BLX R0 + LDR R0, =SystemInit + BLX R0 + BL _start + + .thumb_func +BootProcess: + LDR R0, =0x40080300 + LDR R1,[R0, #0x10] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x14] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x18] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x1C] + CMP R1, #0 + BEQ BP2 +BP1: + LDR R0, =0x40080180 + LDR R1,[R0, #0xC] + LSLS R1, R1, #4 + LSRS R1, R1, #20 + CMP R1, #0 + BEQ BP3 + CMP R1, #5 + BEQ BP3 + CMP R1, #6 + BEQ BP3 +BP2: + DSB + LDR R0, =0x20000000 + LDR R1, =0x05fa0004 + STR R1, [R0] + LDR R1, =0xe000ed00 + LDR R0, =0x05fa0004 + STR R0, [R1, #0xC] + DSB + B . +BP3: + LDR R0, =0x20000000 + LDR R1, [R0] + LDR R0, =0x05fa0004 + CMP R0, R1 + BEQ BP4 + BX LR +BP4: + LDR R0, =0x40088100 + LDR R1, =0x00000001 + STR R1, [R0] + LDR R0, =0x20000000 + LDR R1, =0x0 + STR R1, [R0] + BX LR + + .size Reset_Handler, .-Reset_Handler + +/* Exception Handlers */ + + .weak NMI_Handler + .type NMI_Handler, %function +NMI_Handler: + B . + .size NMI_Handler, . - NMI_Handler + + .weak HardFault_Handler + .type HardFault_Handler, %function +HardFault_Handler: + B . + .size HardFault_Handler, . - HardFault_Handler + + .weak SVC_Handler + .type SVC_Handler, %function +SVC_Handler: + B . + .size SVC_Handler, . - SVC_Handler + + .weak PendSV_Handler + .type PendSV_Handler, %function +PendSV_Handler: + B . + .size PendSV_Handler, . - PendSV_Handler + + .weak SysTick_Handler + .type SysTick_Handler, %function +SysTick_Handler: + B . + .size SysTick_Handler, . - SysTick_Handler + + +/* IRQ Handlers */ + + .globl Default_Handler + .type Default_Handler, %function +Default_Handler: + B . + .size Default_Handler, . - Default_Handler + + .macro IRQ handler + .weak \handler + .set \handler, Default_Handler + .endm + + IRQ LVD_BOD_IRQHandler + IRQ RTC_IRQHandler + IRQ FLASH_IRQHandler + IRQ EVWUP_IRQHandler + IRQ EXTI0_1_IRQHandler + IRQ EXTI2_3_IRQHandler + IRQ EXTI4_15_IRQHandler + IRQ COMP_IRQHandler + IRQ COMP_DAC_IRQHandler + IRQ ADC_IRQHandler + IRQ AES_IRQHandler + IRQ LCD_IRQHandler + IRQ GPTM0_IRQHandler + IRQ SCTM0_IRQHandler + IRQ SCTM1_IRQHandler + IRQ PWM0_IRQHandler + IRQ PWM1_IRQHandler + IRQ BFTM0_IRQHandler + IRQ BFTM1_IRQHandler + IRQ I2C0_IRQHandler + IRQ I2C1_IRQHandler + IRQ SPI0_IRQHandler + IRQ SPI1_IRQHandler + IRQ USART0_IRQHandler + IRQ USART1_IRQHandler + IRQ UART0_IRQHandler + IRQ UART1_IRQHandler + IRQ SCI_IRQHandler + IRQ I2S_IRQHandler + IRQ USB_IRQHandler + IRQ PDMA_CH0_1_IRQHandler + IRQ PDMA_CH2_5_IRQHandler + + .end diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/emStudio/startup_ht32f5xxxx_es_06.s b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/emStudio/startup_ht32f5xxxx_es_06.s new file mode 100644 index 0000000000..00dc85d233 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/emStudio/startup_ht32f5xxxx_es_06.s @@ -0,0 +1,254 @@ +/*---------------------------------------------------------------------------------------------------------*/ +/* Holtek Semiconductor Inc. */ +/* */ +/* Copyright (C) Holtek Semiconductor Inc. */ +/* All rights reserved. */ +/* */ +/*----------------------------------------------------------------------------------------------------------- +; File Name : startup_ht32f5xxxx_es_06.s +; Version : $Rev:: 4142 $ +; Date : $Date:: 2019-07-24 #$ +; Description : Startup code. +;-----------------------------------------------------------------------------------------------------------*/ + +/* +; Supported Device +; ======================================== +; HT32F50343 +*/ + +;/* <<< Use Configuration Wizard in Context Menu >>> */ +/* +;// HT32 Device +;// <0=> By Project Asm Define +;// <15=> HT32F50343 +*/ + .equ USE_HT32_CHIP_SET, 0 + + .equ _HT32FWID, 0xFFFFFFFF +/* + .equ _HT32FWID, 0x00050343 +*/ + + .equ HT32F50343, 15 + + .if USE_HT32_CHIP_SET == 0 + .else + .equ USE_HT32_CHIP, USE_HT32_CHIP_SET + .endif + + .equ _RESERVED, 0xFFFFFFFF +/* +;******************************************************************************* +; Fill-up the Vector Table entries with the exceptions ISR address +;********************************************************************************/ + .syntax unified + .global reset_handler + .global Reset_Handler + .equ Reset_Handler, reset_handler + + .section .vectors, "ax" + .section .vectors, "ax" + .code 16 + .balign 2 + .global _vectors +_vectors: + .long __stack_end__ /* ---, 00, 0x000, Top address of Stack */ + .long reset_handler /* ---, 01, 0x004, Reset Handler */ + .long NMI_Handler /* -14, 02, 0x008, NMI Handler */ + .long HardFault_Handler /* -13, 03, 0x00C, Hard Fault Handler */ + .long _RESERVED /* ---, 04, 0x010, Reserved */ + .long _RESERVED /* ---, 05, 0x014, Reserved */ + .long _RESERVED /* ---, 06, 0x018, Reserved */ + .long _RESERVED /* ---, 07, 0x01C, Reserved */ + .long _HT32FWID /* ---, 08, 0x020, Reserved */ + .long _RESERVED /* ---, 09, 0x024, Reserved */ + .long _RESERVED /* ---, 10, 0x028, Reserved */ + .long SVC_Handler /* -05, 11, 0x02C, SVC Handler */ + .long _RESERVED /* ---, 12, 0x030, Reserved */ + .long _RESERVED /* ---, 13, 0x034, Reserved */ + .long PendSV_Handler /* -02, 14, 0x038, PendSV Handler */ + .long SysTick_Handler /* -01, 15, 0x03C, SysTick Handler */ + + /* External Interrupt Handler */ + .long LVD_BOD_IRQHandler /* 00, 16, 0x040, */ + .long RTC_IRQHandler /* 01, 17, 0x044, */ + .long FLASH_IRQHandler /* 02, 18, 0x048, */ + .long EVWUP_IRQHandler /* 03, 19, 0x04C, */ + .long EXTI0_1_IRQHandler /* 04, 20, 0x050, */ + .long EXTI2_3_IRQHandler /* 05, 21, 0x054, */ + .long EXTI4_15_IRQHandler /* 06, 22, 0x058, */ + .long _RESERVED /* 07, 23, 0x05C, */ + .long ADC_IRQHandler /* 08, 24, 0x060, */ + .long _RESERVED /* 09, 25, 0x064, */ + .long PWM2_IRQHandler /* 10, 26, 0x068, */ + .long _RESERVED /* 11, 27, 0x06C, */ + .long GPTM0_IRQHandler /* 12, 28, 0x070, */ + .long SCTM0_IRQHandler /* 13, 29, 0x074, */ + .long SCTM1_IRQHandler /* 14, 30, 0x078, */ + .long PWM0_IRQHandler /* 15, 31, 0x07C, */ + .long PWM1_IRQHandler /* 16, 32, 0x080, */ + .long BFTM0_IRQHandler /* 17, 33, 0x084, */ + .long BFTM1_IRQHandler /* 18, 34, 0x088, */ + .long I2C0_IRQHandler /* 19, 35, 0x08C, */ + .long I2C1_IRQHandler /* 20, 36, 0x090, */ + .long SPI0_IRQHandler /* 21, 37, 0x094, */ + .long SPI1_IRQHandler /* 22, 38, 0x098, */ + .long _RESERVED /* 23, 39, 0x09C, */ + .long _RESERVED /* 24, 40, 0x0A0, */ + .long UART0_IRQHandler /* 25, 41, 0x0A4, */ + .long UART1_IRQHandler /* 26, 42, 0x0A8, */ + .long SLED0_IRQHandler /* 27, 43, 0x0AC, */ + .long SLED1_IRQHandler /* 28, 44, 0x0B0, */ + .long USB_IRQHandler /* 29, 45, 0x0B4, */ + .long PDMA_CH0_1_IRQHandler /* 30, 46, 0x0B8, */ + .long PDMA_CH2_5_IRQHandler /* 31, 47, 0x0BC, */ + + + + .thumb + + +/* Reset Handler */ + + .section .text.reset_handler + .weak reset_handler + .type reset_handler, %function +reset_handler: + LDR R0, =__stack_end__ /* set stack pointer */ + MOV SP, R0 + LDR R0, =BootProcess + BLX R0 + LDR R0, =SystemInit + BLX R0 + BL _start + + .thumb_func +BootProcess: + LDR R0, =0x40080300 + LDR R1,[R0, #0x10] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x14] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x18] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x1C] + CMP R1, #0 + BEQ BP2 +BP1: + LDR R0, =0x40080180 + LDR R1,[R0, #0xC] + LSLS R1, R1, #4 + LSRS R1, R1, #20 + CMP R1, #0 + BEQ BP3 + CMP R1, #5 + BEQ BP3 + CMP R1, #6 + BEQ BP3 +BP2: + DSB + LDR R0, =0x20000000 + LDR R1, =0x05fa0004 + STR R1, [R0] + LDR R1, =0xe000ed00 + LDR R0, =0x05fa0004 + STR R0, [R1, #0xC] + DSB + B . +BP3: + LDR R0, =0x20000000 + LDR R1, [R0] + LDR R0, =0x05fa0004 + CMP R0, R1 + BEQ BP4 + BX LR +BP4: + LDR R0, =0x40088100 + LDR R1, =0x00000001 + STR R1, [R0] + LDR R0, =0x20000000 + LDR R1, =0x0 + STR R1, [R0] + BX LR + + .size Reset_Handler, .-Reset_Handler + +/* Exception Handlers */ + + .weak NMI_Handler + .type NMI_Handler, %function +NMI_Handler: + B . + .size NMI_Handler, . - NMI_Handler + + .weak HardFault_Handler + .type HardFault_Handler, %function +HardFault_Handler: + B . + .size HardFault_Handler, . - HardFault_Handler + + .weak SVC_Handler + .type SVC_Handler, %function +SVC_Handler: + B . + .size SVC_Handler, . - SVC_Handler + + .weak PendSV_Handler + .type PendSV_Handler, %function +PendSV_Handler: + B . + .size PendSV_Handler, . - PendSV_Handler + + .weak SysTick_Handler + .type SysTick_Handler, %function +SysTick_Handler: + B . + .size SysTick_Handler, . - SysTick_Handler + + +/* IRQ Handlers */ + + .globl Default_Handler + .type Default_Handler, %function +Default_Handler: + B . + .size Default_Handler, . - Default_Handler + + .macro IRQ handler + .weak \handler + .set \handler, Default_Handler + .endm + + IRQ LVD_BOD_IRQHandler + IRQ RTC_IRQHandler + IRQ FLASH_IRQHandler + IRQ EVWUP_IRQHandler + IRQ EXTI0_1_IRQHandler + IRQ EXTI2_3_IRQHandler + IRQ EXTI4_15_IRQHandler + IRQ ADC_IRQHandler + IRQ PWM2_IRQHandler + IRQ GPTM0_IRQHandler + IRQ SCTM0_IRQHandler + IRQ SCTM1_IRQHandler + IRQ PWM0_IRQHandler + IRQ PWM1_IRQHandler + IRQ BFTM0_IRQHandler + IRQ BFTM1_IRQHandler + IRQ I2C0_IRQHandler + IRQ I2C1_IRQHandler + IRQ SPI0_IRQHandler + IRQ SPI1_IRQHandler + IRQ UART0_IRQHandler + IRQ UART1_IRQHandler + IRQ SLED0_IRQHandler + IRQ SLED1_IRQHandler + IRQ USB_IRQHandler + IRQ PDMA_CH0_1_IRQHandler + IRQ PDMA_CH2_5_IRQHandler + + .end diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/emStudio/startup_ht32f5xxxx_es_07.s b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/emStudio/startup_ht32f5xxxx_es_07.s new file mode 100644 index 0000000000..4f71e6a029 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/emStudio/startup_ht32f5xxxx_es_07.s @@ -0,0 +1,262 @@ +/*---------------------------------------------------------------------------------------------------------*/ +/* Holtek Semiconductor Inc. */ +/* */ +/* Copyright (C) Holtek Semiconductor Inc. */ +/* All rights reserved. */ +/* */ +/*----------------------------------------------------------------------------------------------------------- +; File Name : startup_ht32f5xxxx_es_07.s +; Version : $Rev:: 5157 $ +; Date : $Date:: 2021-01-18 #$ +; Description : Startup code. +;-----------------------------------------------------------------------------------------------------------*/ + +/* +; Supported Device +; ======================================== +; HT32F0006 +; HT32F61352 +; HT32F61355, HT32F61356, HT32F61357 +*/ + +;/* <<< Use Configuration Wizard in Context Menu >>> */ +/* +;// HT32 Device +;// <0=> By Project Asm Define +;// <10=> HT32F0006 +;// <10=> HT32F61352 +;// <17=> HT32F61355/56/57 +*/ + .equ USE_HT32_CHIP_SET, 0 + + .equ _HT32FWID, 0xFFFFFFFF +/* + .equ _HT32FWID, 0x00000006 + .equ _HT32FWID, 0x00061352 + .equ _HT32FWID, 0x00061355 + .equ _HT32FWID, 0x00061356 + .equ _HT32FWID, 0x00061357 +*/ + + .equ HT32F0006, 10 + .equ HT32F61352, 10 + .equ HT32F61355_56_57, 17 + + .if USE_HT32_CHIP_SET == 0 + .else + .equ USE_HT32_CHIP, USE_HT32_CHIP_SET + .endif + + .equ _RESERVED, 0xFFFFFFFF +/* +;******************************************************************************* +; Fill-up the Vector Table entries with the exceptions ISR address +;********************************************************************************/ + .syntax unified + .global reset_handler + .global Reset_Handler + .equ Reset_Handler, reset_handler + + .section .vectors, "ax" + .section .vectors, "ax" + .code 16 + .balign 2 + .global _vectors +_vectors: + .long __stack_end__ /* ---, 00, 0x000, Top address of Stack */ + .long reset_handler /* ---, 01, 0x004, Reset Handler */ + .long NMI_Handler /* -14, 02, 0x008, NMI Handler */ + .long HardFault_Handler /* -13, 03, 0x00C, Hard Fault Handler */ + .long _RESERVED /* ---, 04, 0x010, Reserved */ + .long _RESERVED /* ---, 05, 0x014, Reserved */ + .long _RESERVED /* ---, 06, 0x018, Reserved */ + .long _RESERVED /* ---, 07, 0x01C, Reserved */ + .long _HT32FWID /* ---, 08, 0x020, Reserved */ + .long _RESERVED /* ---, 09, 0x024, Reserved */ + .long _RESERVED /* ---, 10, 0x028, Reserved */ + .long SVC_Handler /* -05, 11, 0x02C, SVC Handler */ + .long _RESERVED /* ---, 12, 0x030, Reserved */ + .long _RESERVED /* ---, 13, 0x034, Reserved */ + .long PendSV_Handler /* -02, 14, 0x038, PendSV Handler */ + .long SysTick_Handler /* -01, 15, 0x03C, SysTick Handler */ + + /* External Interrupt Handler */ + .long LVD_BOD_IRQHandler /* 00, 16, 0x040, */ + .long RTC_IRQHandler /* 01, 17, 0x044, */ + .long FLASH_IRQHandler /* 02, 18, 0x048, */ + .long EVWUP_IRQHandler /* 03, 19, 0x04C, */ + .long EXTI0_1_IRQHandler /* 04, 20, 0x050, */ + .long EXTI2_3_IRQHandler /* 05, 21, 0x054, */ + .long EXTI4_15_IRQHandler /* 06, 22, 0x058, */ + .long _RESERVED /* 07, 23, 0x05C, */ + .long ADC_IRQHandler /* 08, 24, 0x060, */ + .long _RESERVED /* 09, 25, 0x064, */ + .long _RESERVED /* 10, 26, 0x068, */ + .long _RESERVED /* 11, 27, 0x06C, */ + .long GPTM0_IRQHandler /* 12, 28, 0x070, */ + .long SCTM0_IRQHandler /* 13, 29, 0x074, */ + .long SCTM1_IRQHandler /* 14, 30, 0x078, */ + .long SCTM2_IRQHandler /* 15, 31, 0x07C, */ + .long SCTM3_IRQHandler /* 16, 32, 0x080, */ + .long BFTM0_IRQHandler /* 17, 33, 0x084, */ + .long BFTM1_IRQHandler /* 18, 34, 0x088, */ + .long I2C0_IRQHandler /* 19, 35, 0x08C, */ + .long _RESERVED /* 20, 36, 0x090, */ + .long SPI0_IRQHandler /* 21, 37, 0x094, */ + .long QSPI_IRQHandler /* 22, 38, 0x098, */ + .long USART0_IRQHandler /* 23, 39, 0x09C, */ + .long _RESERVED /* 24, 40, 0x0A0, */ + .long UART0_IRQHandler /* 25, 41, 0x0A4, */ + .long _RESERVED /* 26, 42, 0x0A8, */ + .long MIDI_IRQHandler /* 27, 43, 0x0AC, */ + .long I2S_IRQHandler /* 28, 44, 0x0B0, */ + .long USB_IRQHandler /* 29, 45, 0x0B4, */ + .long PDMA_CH0_1_IRQHandler /* 30, 46, 0x0B8, */ + .long PDMA_CH2_5_IRQHandler /* 31, 47, 0x0BC, */ + + + + .thumb + + +/* Reset Handler */ + + .section .text.reset_handler + .weak reset_handler + .type reset_handler, %function +reset_handler: + LDR R0, =__stack_end__ /* set stack pointer */ + MOV SP, R0 + LDR R0, =BootProcess + BLX R0 + LDR R0, =SystemInit + BLX R0 + BL _start + + .thumb_func +BootProcess: + LDR R0, =0x40080300 + LDR R1,[R0, #0x10] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x14] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x18] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x1C] + CMP R1, #0 + BEQ BP2 +BP1: + LDR R0, =0x40080180 + LDR R1,[R0, #0xC] + LSLS R1, R1, #4 + LSRS R1, R1, #20 + CMP R1, #0 + BEQ BP3 + CMP R1, #5 + BEQ BP3 + CMP R1, #6 + BEQ BP3 +BP2: + DSB + LDR R0, =0x20000000 + LDR R1, =0x05fa0004 + STR R1, [R0] + LDR R1, =0xe000ed00 + LDR R0, =0x05fa0004 + STR R0, [R1, #0xC] + DSB + B . +BP3: + LDR R0, =0x20000000 + LDR R1, [R0] + LDR R0, =0x05fa0004 + CMP R0, R1 + BEQ BP4 + BX LR +BP4: + LDR R0, =0x40088100 + LDR R1, =0x00000001 + STR R1, [R0] + LDR R0, =0x20000000 + LDR R1, =0x0 + STR R1, [R0] + BX LR + + .size Reset_Handler, .-Reset_Handler + +/* Exception Handlers */ + + .weak NMI_Handler + .type NMI_Handler, %function +NMI_Handler: + B . + .size NMI_Handler, . - NMI_Handler + + .weak HardFault_Handler + .type HardFault_Handler, %function +HardFault_Handler: + B . + .size HardFault_Handler, . - HardFault_Handler + + .weak SVC_Handler + .type SVC_Handler, %function +SVC_Handler: + B . + .size SVC_Handler, . - SVC_Handler + + .weak PendSV_Handler + .type PendSV_Handler, %function +PendSV_Handler: + B . + .size PendSV_Handler, . - PendSV_Handler + + .weak SysTick_Handler + .type SysTick_Handler, %function +SysTick_Handler: + B . + .size SysTick_Handler, . - SysTick_Handler + + +/* IRQ Handlers */ + + .globl Default_Handler + .type Default_Handler, %function +Default_Handler: + B . + .size Default_Handler, . - Default_Handler + + .macro IRQ handler + .weak \handler + .set \handler, Default_Handler + .endm + + IRQ LVD_BOD_IRQHandler + IRQ RTC_IRQHandler + IRQ FLASH_IRQHandler + IRQ EVWUP_IRQHandler + IRQ EXTI0_1_IRQHandler + IRQ EXTI2_3_IRQHandler + IRQ EXTI4_15_IRQHandler + IRQ ADC_IRQHandler + IRQ GPTM0_IRQHandler + IRQ SCTM0_IRQHandler + IRQ SCTM1_IRQHandler + IRQ SCTM2_IRQHandler + IRQ SCTM3_IRQHandler + IRQ BFTM0_IRQHandler + IRQ BFTM1_IRQHandler + IRQ I2C0_IRQHandler + IRQ SPI0_IRQHandler + IRQ QSPI_IRQHandler + IRQ USART0_IRQHandler + IRQ UART0_IRQHandler + IRQ MIDI_IRQHandler + IRQ I2S_IRQHandler + IRQ USB_IRQHandler + IRQ PDMA_CH0_1_IRQHandler + IRQ PDMA_CH2_5_IRQHandler + + .end diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/emStudio/startup_ht32f5xxxx_es_08.s b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/emStudio/startup_ht32f5xxxx_es_08.s new file mode 100644 index 0000000000..afbbdcd115 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/emStudio/startup_ht32f5xxxx_es_08.s @@ -0,0 +1,222 @@ +/*---------------------------------------------------------------------------------------------------------*/ +/* Holtek Semiconductor Inc. */ +/* */ +/* Copyright (C) Holtek Semiconductor Inc. */ +/* All rights reserved. */ +/* */ +/*----------------------------------------------------------------------------------------------------------- +; File Name : startup_ht32f5xxxx_es_08.s +; Version : $Rev:: 6887 $ +; Date : $Date:: 2023-05-05 #$ +; Description : Startup code. +;-----------------------------------------------------------------------------------------------------------*/ + +/* +; Supported Device +; ======================================== +; HT32F65230, HT32F65240 +; HT32F65232 +; HT50F3200S +*/ + +;/* <<< Use Configuration Wizard in Context Menu >>> */ +/* +;// HT32 Device +;// <0=> By Project Asm Define +;// <12=> HT32F65230_40 +;// <18=> HT32F65232 +;// <12=> HT50F3200S +*/ + .equ USE_HT32_CHIP_SET, 0 + + .equ _HT32FWID, 0xFFFFFFFF +/* + .equ _HT32FWID, 0x00065230 + .equ _HT32FWID, 0x00065240 + .equ _HT32FWID, 0x00065232 + .equ _HT32FWID, 0x0003200F +*/ + + .equ HT32F65230_40, 12 + .equ HT32F65232, 18 + .equ HT50F3200S, 12 + + .if USE_HT32_CHIP_SET == 0 + .else + .equ USE_HT32_CHIP, USE_HT32_CHIP_SET + .endif + + .equ _RESERVED, 0xFFFFFFFF +/* +;******************************************************************************* +; Fill-up the Vector Table entries with the exceptions ISR address +;********************************************************************************/ + .syntax unified + .global reset_handler + .global Reset_Handler + .equ Reset_Handler, reset_handler + + .section .vectors, "ax" + .section .vectors, "ax" + .code 16 + .balign 2 + .global _vectors +_vectors: + .long __stack_end__ /* ---, 00, 0x000, Top address of Stack */ + .long reset_handler /* ---, 01, 0x004, Reset Handler */ + .long NMI_Handler /* -14, 02, 0x008, NMI Handler */ + .long HardFault_Handler /* -13, 03, 0x00C, Hard Fault Handler */ + .long _RESERVED /* ---, 04, 0x010, Reserved */ + .long _RESERVED /* ---, 05, 0x014, Reserved */ + .long _RESERVED /* ---, 06, 0x018, Reserved */ + .long _RESERVED /* ---, 07, 0x01C, Reserved */ + .long _HT32FWID /* ---, 08, 0x020, Reserved */ + .long _RESERVED /* ---, 09, 0x024, Reserved */ + .long _RESERVED /* ---, 10, 0x028, Reserved */ + .long SVC_Handler /* -05, 11, 0x02C, SVC Handler */ + .long _RESERVED /* ---, 12, 0x030, Reserved */ + .long _RESERVED /* ---, 13, 0x034, Reserved */ + .long PendSV_Handler /* -02, 14, 0x038, PendSV Handler */ + .long SysTick_Handler /* -01, 15, 0x03C, SysTick Handler */ + + /* External Interrupt Handler */ + .long LVD_BOD_IRQHandler /* 00, 16, 0x040, */ + .long RTC_IRQHandler /* 01, 17, 0x044, */ + .long FLASH_IRQHandler /* 02, 18, 0x048, */ + .long EVWUP_IRQHandler /* 03, 19, 0x04C, */ + .long EXTI0_1_IRQHandler /* 04, 20, 0x050, */ + .long EXTI2_3_IRQHandler /* 05, 21, 0x054, */ + .long EXTI4_9_IRQHandler /* 06, 22, 0x058, */ + .long EXTI10_15_IRQHandler /* 07, 23, 0x05C, */ + .long ADC0_IRQHandler /* 08, 24, 0x060, */ + .if (USE_HT32_CHIP==HT32F65230_40) + .long ADC1_IRQHandler /* 09, 25, 0x064, */ + .else + .long _RESERVED /* 09, 25, 0x064, */ + .endif + .long MCTM0_BRK_IRQHandler /* 10, 26, 0x068, */ + .long MCTM0_UP_IRQHandler /* 11, 27, 0x06C, */ + .long MCTM0_TR_UP2_IRQHandler /* 12, 28, 0x070, */ + .long MCTM0_CC_IRQHandler /* 13, 29, 0x074, */ + .long GPTM0_G_IRQHandler /* 14, 30, 0x078, */ + .long GPTM0_VCLK_IRQHandler /* 15, 31, 0x07C, */ + .long BFTM0_IRQHandler /* 16, 32, 0x080, */ + .long BFTM1_IRQHandler /* 17, 33, 0x084, */ + .long CMP0_IRQHandler /* 18, 34, 0x088, */ + .long CMP1_IRQHandler /* 19, 35, 0x08C, */ + .if (USE_HT32_CHIP==HT32F65230_40) + .long CMP2_IRQHandler /* 20, 36, 0x090, */ + .else + .long _RESERVED /* 20, 36, 0x090, */ + .endif + .long I2C0_IRQHandler /* 21, 37, 0x094, */ + .long SPI0_IRQHandler /* 22, 38, 0x098, */ + .long USART0_IRQHandler /* 23, 39, 0x09C, */ + .long UART0_IRQHandler /* 24, 40, 0x0A0, */ + .long PDMA_CH0_1_IRQHandler /* 25, 41, 0x0A4, */ + .long PDMA_CH2_3_IRQHandler /* 26, 42, 0x0A8, */ + .long PDMA_CH4_5_IRQHandler /* 27, 43, 0x0AC, */ + .long SCTM0_IRQHandler /* 28, 44, 0x0B0, */ + .long SCTM1_IRQHandler /* 29, 45, 0x0B4, */ + .long SCTM2_IRQHandler /* 30, 46, 0x0B8, */ + .long SCTM3_IRQHandler /* 31, 47, 0x0BC, */ + + + + .thumb + + +/* Reset Handler */ + + .section .text.reset_handler + .weak reset_handler + .type reset_handler, %function +reset_handler: + LDR R0, =__stack_end__ /* set stack pointer */ + MOV SP, R0 + LDR R0, =SystemInit + BLX R0 + BL _start + + .size Reset_Handler, .-Reset_Handler + +/* Exception Handlers */ + + .weak NMI_Handler + .type NMI_Handler, %function +NMI_Handler: + B . + .size NMI_Handler, . - NMI_Handler + + .weak HardFault_Handler + .type HardFault_Handler, %function +HardFault_Handler: + B . + .size HardFault_Handler, . - HardFault_Handler + + .weak SVC_Handler + .type SVC_Handler, %function +SVC_Handler: + B . + .size SVC_Handler, . - SVC_Handler + + .weak PendSV_Handler + .type PendSV_Handler, %function +PendSV_Handler: + B . + .size PendSV_Handler, . - PendSV_Handler + + .weak SysTick_Handler + .type SysTick_Handler, %function +SysTick_Handler: + B . + .size SysTick_Handler, . - SysTick_Handler + + +/* IRQ Handlers */ + + .globl Default_Handler + .type Default_Handler, %function +Default_Handler: + B . + .size Default_Handler, . - Default_Handler + + .macro IRQ handler + .weak \handler + .set \handler, Default_Handler + .endm + + IRQ LVD_BOD_IRQHandler + IRQ RTC_IRQHandler + IRQ FLASH_IRQHandler + IRQ EVWUP_IRQHandler + IRQ EXTI0_1_IRQHandler + IRQ EXTI2_3_IRQHandler + IRQ EXTI4_9_IRQHandler + IRQ EXTI10_15_IRQHandler + IRQ ADC0_IRQHandler + IRQ ADC1_IRQHandler + IRQ MCTM0_BRK_IRQHandler + IRQ MCTM0_UP_IRQHandler + IRQ MCTM0_TR_UP2_IRQHandler + IRQ MCTM0_CC_IRQHandler + IRQ GPTM0_G_IRQHandler + IRQ GPTM0_VCLK_IRQHandler + IRQ BFTM0_IRQHandler + IRQ BFTM1_IRQHandler + IRQ CMP0_IRQHandler + IRQ CMP1_IRQHandler + IRQ CMP2_IRQHandler + IRQ I2C0_IRQHandler + IRQ SPI0_IRQHandler + IRQ USART0_IRQHandler + IRQ UART0_IRQHandler + IRQ PDMA_CH0_1_IRQHandler + IRQ PDMA_CH2_3_IRQHandler + IRQ PDMA_CH4_5_IRQHandler + IRQ SCTM0_IRQHandler + IRQ SCTM1_IRQHandler + IRQ SCTM2_IRQHandler + IRQ SCTM3_IRQHandler + + .end diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/emStudio/startup_ht32f5xxxx_es_09.s b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/emStudio/startup_ht32f5xxxx_es_09.s new file mode 100644 index 0000000000..cd8e491fce --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/emStudio/startup_ht32f5xxxx_es_09.s @@ -0,0 +1,294 @@ +/*---------------------------------------------------------------------------------------------------------*/ +/* Holtek Semiconductor Inc. */ +/* */ +/* Copyright (C) Holtek Semiconductor Inc. */ +/* All rights reserved. */ +/* */ +/*----------------------------------------------------------------------------------------------------------- +; File Name : startup_ht32f5xxxx_es_09.s +; Version : $Rev:: 5410 $ +; Date : $Date:: 2021-06-04 #$ +; Description : Startup code. +;-----------------------------------------------------------------------------------------------------------*/ + +/* +; Supported Device +; ======================================== +; HT32F54231, HT32F54241 +; HT32F54243, HT32F54253 +*/ + +;/* <<< Use Configuration Wizard in Context Menu >>> */ +/* +;// HT32 Device +;// <0=> By Project Asm Define +;// <19=> HT32F54231/41 +;// <20=> HT32F54243/53 +*/ + .equ USE_HT32_CHIP_SET, 0 + + .equ _HT32FWID, 0xFFFFFFFF +/* + .equ _HT32FWID, 0x00054231 + .equ _HT32FWID, 0x00054241 + .equ _HT32FWID, 0x00054243 + .equ _HT32FWID, 0x00054253 +*/ + + .equ HT32F54231_41, 19 + .equ HT32F54243_53, 20 + + .if USE_HT32_CHIP_SET == 0 + .else + .equ USE_HT32_CHIP, USE_HT32_CHIP_SET + .endif + + .equ _RESERVED, 0xFFFFFFFF +/* +;******************************************************************************* +; Fill-up the Vector Table entries with the exceptions ISR address +;********************************************************************************/ + .syntax unified + .global reset_handler + .global Reset_Handler + .equ Reset_Handler, reset_handler + + .section .vectors, "ax" + .section .vectors, "ax" + .code 16 + .balign 2 + .global _vectors +_vectors: + .long __stack_end__ /* ---, 00, 0x000, Top address of Stack */ + .long reset_handler /* ---, 01, 0x004, Reset Handler */ + .long NMI_Handler /* -14, 02, 0x008, NMI Handler */ + .long HardFault_Handler /* -13, 03, 0x00C, Hard Fault Handler */ + .long _RESERVED /* ---, 04, 0x010, Reserved */ + .long _RESERVED /* ---, 05, 0x014, Reserved */ + .long _RESERVED /* ---, 06, 0x018, Reserved */ + .long _RESERVED /* ---, 07, 0x01C, Reserved */ + .long _HT32FWID /* ---, 08, 0x020, Reserved */ + .long _RESERVED /* ---, 09, 0x024, Reserved */ + .long _RESERVED /* ---, 10, 0x028, Reserved */ + .long SVC_Handler /* -05, 11, 0x02C, SVC Handler */ + .long _RESERVED /* ---, 12, 0x030, Reserved */ + .long _RESERVED /* ---, 13, 0x034, Reserved */ + .long PendSV_Handler /* -02, 14, 0x038, PendSV Handler */ + .long SysTick_Handler /* -01, 15, 0x03C, SysTick Handler */ + + /* External Interrupt Handler */ + .long LVD_BOD_IRQHandler /* 00, 16, 0x040, */ + .long RTC_IRQHandler /* 01, 17, 0x044, */ + .long FLASH_IRQHandler /* 02, 18, 0x048, */ + .long EVWUP_IRQHandler /* 03, 19, 0x04C, */ + .long EXTI0_1_IRQHandler /* 04, 20, 0x050, */ + .long EXTI2_3_IRQHandler /* 05, 21, 0x054, */ + .long EXTI4_15_IRQHandler /* 06, 22, 0x058, */ + .if (USE_HT32_CHIP==HT32F54231_41) + .long _RESERVED /* 07, 23, 0x05C, */ + .endif + .if (USE_HT32_CHIP==HT32F54243_53) + .long COMP_IRQHandler /* 07, 23, 0x05C, */ + .endif + .long ADC_IRQHandler /* 08, 24, 0x060, */ + .if (USE_HT32_CHIP==HT32F54231_41) + .long _RESERVED /* 09, 25, 0x064, */ + .endif + .if (USE_HT32_CHIP==HT32F54243_53) + .long I2C2_IRQHandler /* 09, 25, 0x064, */ + .endif + .long MCTM0_IRQHandler /* 10, 26, 0x068, */ + .long TKEY_IRQHandler /* 11, 27, 0x06C, */ + .long GPTM0_IRQHandler /* 12, 28, 0x070, */ + .long SCTM0_IRQHandler /* 13, 29, 0x074, */ + .long SCTM1_IRQHandler /* 14, 30, 0x078, */ + .if (USE_HT32_CHIP==HT32F54231_41) + .long _RESERVED /* 15, 31, 0x07C, */ + .long _RESERVED /* 16, 32, 0x080, */ + .endif + .if (USE_HT32_CHIP==HT32F54243_53) + .long SCTM2_IRQHandler /* 15, 31, 0x07C, */ + .long SCTM3_IRQHandler /* 16, 32, 0x080, */ + .endif + .long BFTM0_IRQHandler /* 17, 33, 0x084, */ + .long BFTM1_IRQHandler /* 18, 34, 0x088, */ + .long I2C0_IRQHandler /* 19, 35, 0x08C, */ + .long I2C1_IRQHandler /* 20, 36, 0x090, */ + .long SPI0_IRQHandler /* 21, 37, 0x094, */ + .long SPI1_IRQHandler /* 22, 38, 0x098, */ + .long USART0_IRQHandler /* 23, 39, 0x09C, */ + .if (USE_HT32_CHIP==HT32F54231_41) + .long _RESERVED /* 24, 40, 0x0A0, */ + .endif + .if (USE_HT32_CHIP==HT32F54243_53) + .long USART1_IRQHandler /* 24, 40, 0x0A0, */ + .endif + .long UART0_IRQHandler /* 25, 41, 0x0A4, */ + .long UART1_IRQHandler /* 26, 42, 0x0A8, */ + .if (USE_HT32_CHIP==HT32F54231_41) + .long _RESERVED /* 27, 43, 0x0AC, */ + .long _RESERVED /* 28, 44, 0x0B0, */ + .endif + .if (USE_HT32_CHIP==HT32F54243_53) + .long UART2_IRQHandler /* 27, 43, 0x0AC, */ + .long UART3_IRQHandler /* 28, 44, 0x0B0, */ + .endif + .long LEDC_IRQHandler /* 29, 45, 0x0B4, */ + .if (USE_HT32_CHIP==HT32F54243_53) + .long PDMA_CH0_1_IRQHandler /* 30, 46, 0x0B8, */ + .long PDMA_CH2_5_IRQHandler /* 31, 47, 0x0BC, */ + .endif + + + + .thumb + + +/* Reset Handler */ + + .section .text.reset_handler + .weak reset_handler + .type reset_handler, %function +reset_handler: + LDR R0, =__stack_end__ /* set stack pointer */ + MOV SP, R0 + LDR R0, =BootProcess + BLX R0 + LDR R0, =SystemInit + BLX R0 + BL _start + + .thumb_func +BootProcess: + LDR R0, =0x40080300 + LDR R1,[R0, #0x10] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x14] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x18] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x1C] + CMP R1, #0 + BEQ BP2 +BP1: + LDR R0, =0x40080180 + LDR R1,[R0, #0xC] + LSLS R1, R1, #4 + LSRS R1, R1, #20 + CMP R1, #0 + BEQ BP3 + CMP R1, #5 + BEQ BP3 + CMP R1, #6 + BEQ BP3 +BP2: + DSB + LDR R0, =0x20000000 + LDR R1, =0x05fa0004 + STR R1, [R0] + LDR R1, =0xe000ed00 + LDR R0, =0x05fa0004 + STR R0, [R1, #0xC] + DSB + B . +BP3: + LDR R0, =0x20000000 + LDR R1, [R0] + LDR R0, =0x05fa0004 + CMP R0, R1 + BEQ BP4 + BX LR +BP4: + LDR R0, =0x40088100 + LDR R1, =0x00000001 + STR R1, [R0] + LDR R0, =0x20000000 + LDR R1, =0x0 + STR R1, [R0] + BX LR + + .size Reset_Handler, .-Reset_Handler + +/* Exception Handlers */ + + .weak NMI_Handler + .type NMI_Handler, %function +NMI_Handler: + B . + .size NMI_Handler, . - NMI_Handler + + .weak HardFault_Handler + .type HardFault_Handler, %function +HardFault_Handler: + B . + .size HardFault_Handler, . - HardFault_Handler + + .weak SVC_Handler + .type SVC_Handler, %function +SVC_Handler: + B . + .size SVC_Handler, . - SVC_Handler + + .weak PendSV_Handler + .type PendSV_Handler, %function +PendSV_Handler: + B . + .size PendSV_Handler, . - PendSV_Handler + + .weak SysTick_Handler + .type SysTick_Handler, %function +SysTick_Handler: + B . + .size SysTick_Handler, . - SysTick_Handler + + +/* IRQ Handlers */ + + .globl Default_Handler + .type Default_Handler, %function +Default_Handler: + B . + .size Default_Handler, . - Default_Handler + + .macro IRQ handler + .weak \handler + .set \handler, Default_Handler + .endm + + IRQ LVD_BOD_IRQHandler + IRQ RTC_IRQHandler + IRQ FLASH_IRQHandler + IRQ EVWUP_IRQHandler + IRQ EXTI0_1_IRQHandler + IRQ EXTI2_3_IRQHandler + IRQ EXTI4_15_IRQHandler + IRQ COMP_IRQHandler + IRQ ADC_IRQHandler + IRQ I2C2_IRQHandler + IRQ MCTM0_IRQHandler + IRQ TKEY_IRQHandler + IRQ GPTM0_IRQHandler + IRQ SCTM0_IRQHandler + IRQ SCTM1_IRQHandler + IRQ SCTM2_IRQHandler + IRQ SCTM3_IRQHandler + IRQ BFTM0_IRQHandler + IRQ BFTM1_IRQHandler + IRQ I2C0_IRQHandler + IRQ I2C1_IRQHandler + IRQ SPI0_IRQHandler + IRQ SPI1_IRQHandler + IRQ USART0_IRQHandler + IRQ USART1_IRQHandler + IRQ UART0_IRQHandler + IRQ UART1_IRQHandler + IRQ UART2_IRQHandler + IRQ UART3_IRQHandler + IRQ LEDC_IRQHandler + IRQ PDMA_CH0_1_IRQHandler + IRQ PDMA_CH2_5_IRQHandler + + .end diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/emStudio/startup_ht32f5xxxx_es_10.s b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/emStudio/startup_ht32f5xxxx_es_10.s new file mode 100644 index 0000000000..d9253dcbca --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/emStudio/startup_ht32f5xxxx_es_10.s @@ -0,0 +1,194 @@ +/*---------------------------------------------------------------------------------------------------------*/ +/* Holtek Semiconductor Inc. */ +/* */ +/* Copyright (C) Holtek Semiconductor Inc. */ +/* All rights reserved. */ +/* */ +/*----------------------------------------------------------------------------------------------------------- +; File Name : startup_ht32f5xxxx_es_10.s +; Version : $Rev:: 6601 $ +; Date : $Date:: 2022-12-27 #$ +; Description : Startup code. +;-----------------------------------------------------------------------------------------------------------*/ + +/* +; Supported Device +; ======================================== +; HT32F61244, HT32F61245 +*/ + +;/* <<< Use Configuration Wizard in Context Menu >>> */ +/* +;// HT32 Device +;// <0=> By Project Asm Define +;// <24=> HT32F61244/45 +*/ + .equ USE_HT32_CHIP_SET, 0 + + .equ _HT32FWID, 0xFFFFFFFF +/* + .equ _HT32FWID, 0x00061244 + .equ _HT32FWID, 0x00061245 +*/ + + .equ HT32F61244_45, 24 + + .if USE_HT32_CHIP_SET == 0 + .else + .equ USE_HT32_CHIP, USE_HT32_CHIP_SET + .endif + + .equ _RESERVED, 0xFFFFFFFF +/* +;******************************************************************************* +; Fill-up the Vector Table entries with the exceptions ISR address +;********************************************************************************/ + .syntax unified + .global reset_handler + .global Reset_Handler + .equ Reset_Handler, reset_handler + + .section .vectors, "ax" + .section .vectors, "ax" + .code 16 + .balign 2 + .global _vectors +_vectors: + .long __stack_end__ /* ---, 00, 0x000, Top address of Stack */ + .long reset_handler /* ---, 01, 0x004, Reset Handler */ + .long NMI_Handler /* -14, 02, 0x008, NMI Handler */ + .long HardFault_Handler /* -13, 03, 0x00C, Hard Fault Handler */ + .long _RESERVED /* ---, 04, 0x010, Reserved */ + .long _RESERVED /* ---, 05, 0x014, Reserved */ + .long _RESERVED /* ---, 06, 0x018, Reserved */ + .long _RESERVED /* ---, 07, 0x01C, Reserved */ + .long _HT32FWID /* ---, 08, 0x020, Reserved */ + .long _RESERVED /* ---, 09, 0x024, Reserved */ + .long _RESERVED /* ---, 10, 0x028, Reserved */ + .long SVC_Handler /* -05, 11, 0x02C, SVC Handler */ + .long _RESERVED /* ---, 12, 0x030, Reserved */ + .long _RESERVED /* ---, 13, 0x034, Reserved */ + .long PendSV_Handler /* -02, 14, 0x038, PendSV Handler */ + .long SysTick_Handler /* -01, 15, 0x03C, SysTick Handler */ + + /* External Interrupt Handler */ + .long LVD_BOD_IRQHandler /* 00, 16, 0x040, */ + .long RTC_IRQHandler /* 01, 17, 0x044, */ + .long FLASH_IRQHandler /* 02, 18, 0x048, */ + .long EVWUP_IRQHandler /* 03, 19, 0x04C, */ + .long EXTI0_1_IRQHandler /* 04, 20, 0x050, */ + .long EXTI2_3_IRQHandler /* 05, 21, 0x054, */ + .long EXTI4_15_IRQHandler /* 06, 22, 0x058, */ + .long _RESERVED /* 07, 23, 0x05C, */ + .long ADC_IRQHandler /* 08, 24, 0x060, */ + .long _RESERVED /* 09, 25, 0x064, */ + .long _RESERVED /* 10, 26, 0x068, */ + .long _RESERVED /* 11, 27, 0x06C, */ + .long GPTM0_IRQHandler /* 12, 28, 0x070, */ + .long SCTM0_IRQHandler /* 13, 29, 0x074, */ + .long SCTM1_IRQHandler /* 14, 30, 0x078, */ + .long _RESERVED /* 15, 31, 0x07C, */ + .long _RESERVED /* 16, 32, 0x080, */ + .long BFTM0_IRQHandler /* 17, 33, 0x084, */ + .long BFTM1_IRQHandler /* 18, 34, 0x088, */ + .long I2C0_IRQHandler /* 19, 35, 0x08C, */ + .long _RESERVED /* 20, 36, 0x090, */ + .long SPI0_IRQHandler /* 21, 37, 0x094, */ + .long QSPI_IRQHandler /* 22, 38, 0x098, */ + .long _RESERVED /* 23, 39, 0x09C, */ + .long _RESERVED /* 24, 40, 0x0A0, */ + .long UART0_IRQHandler /* 25, 41, 0x0A4, */ + .long _RESERVED /* 26, 42, 0x0A8, */ + .long MIDI_IRQHandler /* 27, 43, 0x0AC, */ + .long _RESERVED /* 28, 44, 0x0B0, */ + .long _RESERVED /* 29, 45, 0x0B4, */ + .long PDMA_CH0_1_IRQHandler /* 30, 46, 0x0B8, */ + .long PDMA_CH2_5_IRQHandler /* 31, 47, 0x0BC, */ + + + + .thumb + + +/* Reset Handler */ + + .section .text.reset_handler + .weak reset_handler + .type reset_handler, %function +reset_handler: + LDR R0, =__stack_end__ /* set stack pointer */ + MOV SP, R0 + LDR R0, =SystemInit + BLX R0 + BL _start + + .size Reset_Handler, .-Reset_Handler + +/* Exception Handlers */ + + .weak NMI_Handler + .type NMI_Handler, %function +NMI_Handler: + B . + .size NMI_Handler, . - NMI_Handler + + .weak HardFault_Handler + .type HardFault_Handler, %function +HardFault_Handler: + B . + .size HardFault_Handler, . - HardFault_Handler + + .weak SVC_Handler + .type SVC_Handler, %function +SVC_Handler: + B . + .size SVC_Handler, . - SVC_Handler + + .weak PendSV_Handler + .type PendSV_Handler, %function +PendSV_Handler: + B . + .size PendSV_Handler, . - PendSV_Handler + + .weak SysTick_Handler + .type SysTick_Handler, %function +SysTick_Handler: + B . + .size SysTick_Handler, . - SysTick_Handler + + +/* IRQ Handlers */ + + .globl Default_Handler + .type Default_Handler, %function +Default_Handler: + B . + .size Default_Handler, . - Default_Handler + + .macro IRQ handler + .weak \handler + .set \handler, Default_Handler + .endm + + IRQ LVD_BOD_IRQHandler + IRQ RTC_IRQHandler + IRQ FLASH_IRQHandler + IRQ EVWUP_IRQHandler + IRQ EXTI0_1_IRQHandler + IRQ EXTI2_3_IRQHandler + IRQ EXTI4_15_IRQHandler + IRQ ADC_IRQHandler + IRQ GPTM0_IRQHandler + IRQ SCTM0_IRQHandler + IRQ SCTM1_IRQHandler + IRQ BFTM0_IRQHandler + IRQ BFTM1_IRQHandler + IRQ I2C0_IRQHandler + IRQ SPI0_IRQHandler + IRQ QSPI_IRQHandler + IRQ UART0_IRQHandler + IRQ MIDI_IRQHandler + IRQ PDMA_CH0_1_IRQHandler + IRQ PDMA_CH2_5_IRQHandler + + .end diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/emStudio/startup_ht32f5xxxx_es_11.s b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/emStudio/startup_ht32f5xxxx_es_11.s new file mode 100644 index 0000000000..176c685784 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/emStudio/startup_ht32f5xxxx_es_11.s @@ -0,0 +1,199 @@ +/*---------------------------------------------------------------------------------------------------------*/ +/* Holtek Semiconductor Inc. */ +/* */ +/* Copyright (C) Holtek Semiconductor Inc. */ +/* All rights reserved. */ +/* */ +/*----------------------------------------------------------------------------------------------------------- +; File Name : startup_ht32f5xxxx_es_11.s +; Version : $Rev:: 6206 $ +; Date : $Date:: 2022-10-05 #$ +; Description : Startup code. +;-----------------------------------------------------------------------------------------------------------*/ + +/* +; Supported Device +; ======================================== +; HT32F67041, HT32F67051 +*/ + +;/* <<< Use Configuration Wizard in Context Menu >>> */ +/* +;// HT32 Device +;// <0=> By Project Asm Define +;// <22=> HT32F67041/51 +*/ + .equ USE_HT32_CHIP_SET, 0 + + .equ _HT32FWID, 0xFFFFFFFF +/* + .equ _HT32FWID, 0x00067041 + .equ _HT32FWID, 0x00067051 +*/ + + .equ HT32F67041_51, 22 + + .if USE_HT32_CHIP_SET == 0 + .else + .equ USE_HT32_CHIP, USE_HT32_CHIP_SET + .endif + + .equ _RESERVED, 0xFFFFFFFF +/* +;******************************************************************************* +; Fill-up the Vector Table entries with the exceptions ISR address +;********************************************************************************/ + .syntax unified + .global reset_handler + .global Reset_Handler + .equ Reset_Handler, reset_handler + + .section .vectors, "ax" + .section .vectors, "ax" + .code 16 + .balign 2 + .global _vectors +_vectors: + .long __stack_end__ /* ---, 00, 0x000, Top address of Stack */ + .long reset_handler /* ---, 01, 0x004, Reset Handler */ + .long NMI_Handler /* -14, 02, 0x008, NMI Handler */ + .long HardFault_Handler /* -13, 03, 0x00C, Hard Fault Handler */ + .long _RESERVED /* ---, 04, 0x010, Reserved */ + .long _RESERVED /* ---, 05, 0x014, Reserved */ + .long _RESERVED /* ---, 06, 0x018, Reserved */ + .long _RESERVED /* ---, 07, 0x01C, Reserved */ + .long _HT32FWID /* ---, 08, 0x020, Reserved */ + .long _RESERVED /* ---, 09, 0x024, Reserved */ + .long _RESERVED /* ---, 10, 0x028, Reserved */ + .long SVC_Handler /* -05, 11, 0x02C, SVC Handler */ + .long _RESERVED /* ---, 12, 0x030, Reserved */ + .long _RESERVED /* ---, 13, 0x034, Reserved */ + .long PendSV_Handler /* -02, 14, 0x038, PendSV Handler */ + .long SysTick_Handler /* -01, 15, 0x03C, SysTick Handler */ + + /* External Interrupt Handler */ + .long LVD_BOD_IRQHandler /* 00, 16, 0x040, */ + .long RTC_IRQHandler /* 01, 17, 0x044, */ + .long FLASH_IRQHandler /* 02, 18, 0x048, */ + .long EVWUP_IRQHandler /* 03, 19, 0x04C, */ + .long EXTI0_1_IRQHandler /* 04, 20, 0x050, */ + .long EXTI2_3_IRQHandler /* 05, 21, 0x054, */ + .long EXTI4_15_IRQHandler /* 06, 22, 0x058, */ + .long _RESERVED /* 07, 23, 0x05C, */ + .long ADC_IRQHandler /* 08, 24, 0x060, */ + .long AES_IRQHandler /* 09, 25, 0x064, */ + .long _RESERVED /* 10, 26, 0x068, */ + .long RF_IRQHandler /* 11, 27, 0x06C, */ + .long GPTM0_IRQHandler /* 12, 28, 0x070, */ + .long SCTM0_IRQHandler /* 13, 29, 0x074, */ + .long SCTM1_IRQHandler /* 14, 30, 0x078, */ + .long SCTM2_IRQHandler /* 15, 31, 0x07C, */ + .long SCTM3_IRQHandler /* 16, 32, 0x080, */ + .long BFTM0_IRQHandler /* 17, 33, 0x084, */ + .long BFTM1_IRQHandler /* 18, 34, 0x088, */ + .long I2C0_IRQHandler /* 19, 35, 0x08C, */ + .long I2C1_IRQHandler /* 20, 36, 0x090, */ + .long SPI0_IRQHandler /* 21, 37, 0x094, */ + .long SPI1_IRQHandler /* 22, 38, 0x098, */ + .long _RESERVED /* 23, 39, 0x09C, */ + .long _RESERVED /* 24, 40, 0x0A0, */ + .long UART0_IRQHandler /* 25, 41, 0x0A4, */ + .long UART1_IRQHandler /* 26, 42, 0x0A8, */ + .long _RESERVED /* 27, 43, 0x0AC, */ + .long _RESERVED /* 28, 44, 0x0B0, */ + .long _RESERVED /* 29, 45, 0x0B4, */ + .long PDMA_CH0_1_IRQHandler /* 30, 46, 0x0B8, */ + .long PDMA_CH2_5_IRQHandler /* 31, 47, 0x0BC, */ + + + + .thumb + + +/* Reset Handler */ + + .section .text.reset_handler + .weak reset_handler + .type reset_handler, %function +reset_handler: + LDR R0, =__stack_end__ /* set stack pointer */ + MOV SP, R0 + LDR R0, =SystemInit + BLX R0 + BL _start + + .size Reset_Handler, .-Reset_Handler + +/* Exception Handlers */ + + .weak NMI_Handler + .type NMI_Handler, %function +NMI_Handler: + B . + .size NMI_Handler, . - NMI_Handler + + .weak HardFault_Handler + .type HardFault_Handler, %function +HardFault_Handler: + B . + .size HardFault_Handler, . - HardFault_Handler + + .weak SVC_Handler + .type SVC_Handler, %function +SVC_Handler: + B . + .size SVC_Handler, . - SVC_Handler + + .weak PendSV_Handler + .type PendSV_Handler, %function +PendSV_Handler: + B . + .size PendSV_Handler, . - PendSV_Handler + + .weak SysTick_Handler + .type SysTick_Handler, %function +SysTick_Handler: + B . + .size SysTick_Handler, . - SysTick_Handler + + +/* IRQ Handlers */ + + .globl Default_Handler + .type Default_Handler, %function +Default_Handler: + B . + .size Default_Handler, . - Default_Handler + + .macro IRQ handler + .weak \handler + .set \handler, Default_Handler + .endm + + IRQ LVD_BOD_IRQHandler + IRQ RTC_IRQHandler + IRQ FLASH_IRQHandler + IRQ EVWUP_IRQHandler + IRQ EXTI0_1_IRQHandler + IRQ EXTI2_3_IRQHandler + IRQ EXTI4_15_IRQHandler + IRQ ADC_IRQHandler + IRQ AES_IRQHandler + IRQ RF_IRQHandler + IRQ GPTM0_IRQHandler + IRQ SCTM0_IRQHandler + IRQ SCTM1_IRQHandler + IRQ SCTM2_IRQHandler + IRQ SCTM3_IRQHandler + IRQ BFTM0_IRQHandler + IRQ BFTM1_IRQHandler + IRQ I2C0_IRQHandler + IRQ I2C1_IRQHandler + IRQ SPI0_IRQHandler + IRQ SPI1_IRQHandler + IRQ UART0_IRQHandler + IRQ UART1_IRQHandler + IRQ PDMA_CH0_1_IRQHandler + IRQ PDMA_CH2_5_IRQHandler + + .end diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/emStudio/startup_ht32f5xxxx_es_12.s b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/emStudio/startup_ht32f5xxxx_es_12.s new file mode 100644 index 0000000000..b1dc8ca860 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/emStudio/startup_ht32f5xxxx_es_12.s @@ -0,0 +1,243 @@ +/*---------------------------------------------------------------------------------------------------------*/ +/* Holtek Semiconductor Inc. */ +/* */ +/* Copyright (C) Holtek Semiconductor Inc. */ +/* All rights reserved. */ +/* */ +/*----------------------------------------------------------------------------------------------------------- +; File Name : startup_ht32f5xxxx_es_12.s +; Version : $Rev:: 5572 $ +; Date : $Date:: 2021-08-18 #$ +; Description : Startup code. +;-----------------------------------------------------------------------------------------------------------*/ + +/* +; Supported Device +; ======================================== +; HT32F61141 +*/ + +;/* <<< Use Configuration Wizard in Context Menu >>> */ +/* +;// HT32 Device +;// <0=> By Project Asm Define +;// <23=> HT32F61141 +*/ + .equ USE_HT32_CHIP_SET, 0 + + .equ _HT32FWID, 0xFFFFFFFF +/* + .equ _HT32FWID, 0x00061141 +*/ + + .equ HT32F61141, 23 + + .if USE_HT32_CHIP_SET == 0 + .else + .equ USE_HT32_CHIP, USE_HT32_CHIP_SET + .endif + + .equ _RESERVED, 0xFFFFFFFF +/* +;******************************************************************************* +; Fill-up the Vector Table entries with the exceptions ISR address +;********************************************************************************/ + .syntax unified + .global reset_handler + .global Reset_Handler + .equ Reset_Handler, reset_handler + + .section .vectors, "ax" + .section .vectors, "ax" + .code 16 + .balign 2 + .global _vectors +_vectors: + .long __stack_end__ /* ---, 00, 0x000, Top address of Stack */ + .long reset_handler /* ---, 01, 0x004, Reset Handler */ + .long NMI_Handler /* -14, 02, 0x008, NMI Handler */ + .long HardFault_Handler /* -13, 03, 0x00C, Hard Fault Handler */ + .long _RESERVED /* ---, 04, 0x010, Reserved */ + .long _RESERVED /* ---, 05, 0x014, Reserved */ + .long _RESERVED /* ---, 06, 0x018, Reserved */ + .long _RESERVED /* ---, 07, 0x01C, Reserved */ + .long _HT32FWID /* ---, 08, 0x020, Reserved */ + .long _RESERVED /* ---, 09, 0x024, Reserved */ + .long _RESERVED /* ---, 10, 0x028, Reserved */ + .long SVC_Handler /* -05, 11, 0x02C, SVC Handler */ + .long _RESERVED /* ---, 12, 0x030, Reserved */ + .long _RESERVED /* ---, 13, 0x034, Reserved */ + .long PendSV_Handler /* -02, 14, 0x038, PendSV Handler */ + .long SysTick_Handler /* -01, 15, 0x03C, SysTick Handler */ + + /* External Interrupt Handler */ + .long LVD_BOD_IRQHandler /* 00, 16, 0x040, */ + .long RTC_IRQHandler /* 01, 17, 0x044, */ + .long FLASH_IRQHandler /* 02, 18, 0x048, */ + .long EVWUP_IRQHandler /* 03, 19, 0x04C, */ + .long EXTI0_1_IRQHandler /* 04, 20, 0x050, */ + .long EXTI2_3_IRQHandler /* 05, 21, 0x054, */ + .long EXTI4_15_IRQHandler /* 06, 22, 0x058, */ + .long _RESERVED /* 07, 23, 0x05C, */ + .long _RESERVED /* 08, 24, 0x060, */ + .long _RESERVED /* 09, 25, 0x064, */ + .long _RESERVED /* 10, 26, 0x068, */ + .long _RESERVED /* 11, 27, 0x06C, */ + .long GPTM0_IRQHandler /* 12, 28, 0x070, */ + .long SCTM0_IRQHandler /* 13, 29, 0x074, */ + .long SCTM1_IRQHandler /* 14, 30, 0x078, */ + .long _RESERVED /* 15, 31, 0x07C, */ + .long _RESERVED /* 16, 32, 0x080, */ + .long BFTM0_IRQHandler /* 17, 33, 0x084, */ + .long BFTM1_IRQHandler /* 18, 34, 0x088, */ + .long I2C0_IRQHandler /* 19, 35, 0x08C, */ + .long _RESERVED /* 20, 36, 0x090, */ + .long SPI0_IRQHandler /* 21, 37, 0x094, */ + .long _RESERVED /* 22, 38, 0x098, */ + .long _RESERVED /* 23, 39, 0x09C, */ + .long _RESERVED /* 24, 40, 0x0A0, */ + .long UART0_IRQHandler /* 25, 41, 0x0A4, */ + .long UART1_IRQHandler /* 26, 42, 0x0A8, */ + .long SCI_IRQHandler /* 27, 43, 0x0AC, */ + .long _RESERVED /* 28, 44, 0x0B0, */ + .long USB_IRQHandler /* 29, 45, 0x0B4, */ + + + + .thumb + + +/* Reset Handler */ + + .section .text.reset_handler + .weak reset_handler + .type reset_handler, %function +reset_handler: + LDR R0, =__stack_end__ /* set stack pointer */ + MOV SP, R0 + LDR R0, =BootProcess + BLX R0 + LDR R0, =SystemInit + BLX R0 + BL _start + + .thumb_func +BootProcess: + LDR R0, =0x40080300 + LDR R1,[R0, #0x10] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x14] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x18] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x1C] + CMP R1, #0 + BEQ BP2 +BP1: + LDR R0, =0x40080180 + LDR R1,[R0, #0xC] + LSLS R1, R1, #4 + LSRS R1, R1, #20 + CMP R1, #0 + BEQ BP3 + CMP R1, #5 + BEQ BP3 + CMP R1, #6 + BEQ BP3 +BP2: + DSB + LDR R0, =0x20000000 + LDR R1, =0x05fa0004 + STR R1, [R0] + LDR R1, =0xe000ed00 + LDR R0, =0x05fa0004 + STR R0, [R1, #0xC] + DSB + B . +BP3: + LDR R0, =0x20000000 + LDR R1, [R0] + LDR R0, =0x05fa0004 + CMP R0, R1 + BEQ BP4 + BX LR +BP4: + LDR R0, =0x40088100 + LDR R1, =0x00000001 + STR R1, [R0] + LDR R0, =0x20000000 + LDR R1, =0x0 + STR R1, [R0] + BX LR + + .size Reset_Handler, .-Reset_Handler + +/* Exception Handlers */ + + .weak NMI_Handler + .type NMI_Handler, %function +NMI_Handler: + B . + .size NMI_Handler, . - NMI_Handler + + .weak HardFault_Handler + .type HardFault_Handler, %function +HardFault_Handler: + B . + .size HardFault_Handler, . - HardFault_Handler + + .weak SVC_Handler + .type SVC_Handler, %function +SVC_Handler: + B . + .size SVC_Handler, . - SVC_Handler + + .weak PendSV_Handler + .type PendSV_Handler, %function +PendSV_Handler: + B . + .size PendSV_Handler, . - PendSV_Handler + + .weak SysTick_Handler + .type SysTick_Handler, %function +SysTick_Handler: + B . + .size SysTick_Handler, . - SysTick_Handler + + +/* IRQ Handlers */ + + .globl Default_Handler + .type Default_Handler, %function +Default_Handler: + B . + .size Default_Handler, . - Default_Handler + + .macro IRQ handler + .weak \handler + .set \handler, Default_Handler + .endm + + IRQ LVD_BOD_IRQHandler + IRQ RTC_IRQHandler + IRQ FLASH_IRQHandler + IRQ EVWUP_IRQHandler + IRQ EXTI0_1_IRQHandler + IRQ EXTI2_3_IRQHandler + IRQ EXTI4_15_IRQHandler + IRQ GPTM0_IRQHandler + IRQ SCTM0_IRQHandler + IRQ SCTM1_IRQHandler + IRQ BFTM0_IRQHandler + IRQ BFTM1_IRQHandler + IRQ I2C0_IRQHandler + IRQ SPI0_IRQHandler + IRQ UART0_IRQHandler + IRQ UART1_IRQHandler + IRQ SCI_IRQHandler + IRQ USB_IRQHandler + + .end diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/emStudio/startup_ht32f5xxxx_es_13.s b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/emStudio/startup_ht32f5xxxx_es_13.s new file mode 100644 index 0000000000..8c3a524ef1 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/emStudio/startup_ht32f5xxxx_es_13.s @@ -0,0 +1,197 @@ +/*---------------------------------------------------------------------------------------------------------*/ +/* Holtek Semiconductor Inc. */ +/* */ +/* Copyright (C) Holtek Semiconductor Inc. */ +/* All rights reserved. */ +/* */ +/*----------------------------------------------------------------------------------------------------------- +; File Name : startup_ht32f5xxxx_es_13.s +; Version : $Rev:: 7119 $ +; Date : $Date:: 2023-08-15 #$ +; Description : Startup code. +;-----------------------------------------------------------------------------------------------------------*/ + +/* +; Supported Device +; ======================================== +; HT32F50020, HT32F50030 +; HT32F61630 +; HT32F61030 +*/ + +;/* <<< Use Configuration Wizard in Context Menu >>> */ +/* +;// HT32 Device +;// <0=> By Project Asm Define +;// <25=> HT32F50020/30 +;// <25=> HT32F61630 +;// <25=> HT32F61030 +*/ + .equ USE_HT32_CHIP_SET, 0 + + .equ _HT32FWID, 0xFFFFFFFF +/* + .equ _HT32FWID, 0x00050020 + .equ _HT32FWID, 0x00050030 + .equ _HT32FWID, 0x00061630 + .equ _HT32FWID, 0x00061030 +*/ + + .equ HT32F50020_30, 25 + .equ HT32F61630, 25 + .equ HT32F61030, 25 + + .if USE_HT32_CHIP_SET == 0 + .else + .equ USE_HT32_CHIP, USE_HT32_CHIP_SET + .endif + + .equ _RESERVED, 0xFFFFFFFF +/* +;******************************************************************************* +; Fill-up the Vector Table entries with the exceptions ISR address +;********************************************************************************/ + .syntax unified + .global reset_handler + .global Reset_Handler + .equ Reset_Handler, reset_handler + + .section .vectors, "ax" + .section .vectors, "ax" + .code 16 + .balign 2 + .global _vectors +_vectors: + .long __stack_end__ /* ---, 00, 0x000, Top address of Stack */ + .long reset_handler /* ---, 01, 0x004, Reset Handler */ + .long NMI_Handler /* -14, 02, 0x008, NMI Handler */ + .long HardFault_Handler /* -13, 03, 0x00C, Hard Fault Handler */ + .long _RESERVED /* ---, 04, 0x010, Reserved */ + .long _RESERVED /* ---, 05, 0x014, Reserved */ + .long _RESERVED /* ---, 06, 0x018, Reserved */ + .long _RESERVED /* ---, 07, 0x01C, Reserved */ + .long _HT32FWID /* ---, 08, 0x020, Reserved */ + .long _RESERVED /* ---, 09, 0x024, Reserved */ + .long _RESERVED /* ---, 10, 0x028, Reserved */ + .long SVC_Handler /* -05, 11, 0x02C, SVC Handler */ + .long _RESERVED /* ---, 12, 0x030, Reserved */ + .long _RESERVED /* ---, 13, 0x034, Reserved */ + .long PendSV_Handler /* -02, 14, 0x038, PendSV Handler */ + .long SysTick_Handler /* -01, 15, 0x03C, SysTick Handler */ + + /* External Interrupt Handler */ + .long LVD_BOD_IRQHandler /* 00, 16, 0x040, */ + .long RTC_IRQHandler /* 01, 17, 0x044, */ + .long FLASH_IRQHandler /* 02, 18, 0x048, */ + .long EVWUP_IRQHandler /* 03, 19, 0x04C, */ + .long EXTI0_1_IRQHandler /* 04, 20, 0x050, */ + .long EXTI2_3_IRQHandler /* 05, 21, 0x054, */ + .long EXTI4_7_IRQHandler /* 06, 22, 0x058, */ + .long _RESERVED /* 07, 23, 0x05C, */ + .long ADC_IRQHandler /* 08, 24, 0x060, */ + .long _RESERVED /* 09, 25, 0x064, */ + .long _RESERVED /* 10, 26, 0x068, */ + .long _RESERVED /* 11, 27, 0x06C, */ + .long _RESERVED /* 12, 28, 0x070, */ + .long SCTM0_IRQHandler /* 13, 29, 0x074, */ + .long SCTM1_IRQHandler /* 14, 30, 0x078, */ + .long SCTM2_IRQHandler /* 15, 31, 0x07C, */ + .long _RESERVED /* 16, 32, 0x080, */ + .long BFTM0_IRQHandler /* 17, 33, 0x084, */ + .long _RESERVED /* 18, 34, 0x088, */ + .long I2C0_IRQHandler /* 19, 35, 0x08C, */ + .long _RESERVED /* 20, 36, 0x090, */ + .long SPI0_IRQHandler /* 21, 37, 0x094, */ + .long _RESERVED /* 22, 38, 0x098, */ + .long _RESERVED /* 23, 39, 0x09C, */ + .long _RESERVED /* 24, 40, 0x0A0, */ + .long UART0_IRQHandler /* 25, 41, 0x0A4, */ + .long UART1_IRQHandler /* 26, 42, 0x0A8, */ + .long _RESERVED /* 27, 43, 0x0AC, */ + .long _RESERVED /* 28, 44, 0x0B0, */ + .long LEDC_IRQHandler /* 29, 45, 0x0B4, */ + + + + .thumb + + +/* Reset Handler */ + + .section .text.reset_handler + .weak reset_handler + .type reset_handler, %function +reset_handler: + LDR R0, =__stack_end__ /* set stack pointer */ + MOV SP, R0 + LDR R0, =SystemInit + BLX R0 + BL _start + + .size Reset_Handler, .-Reset_Handler + +/* Exception Handlers */ + + .weak NMI_Handler + .type NMI_Handler, %function +NMI_Handler: + B . + .size NMI_Handler, . - NMI_Handler + + .weak HardFault_Handler + .type HardFault_Handler, %function +HardFault_Handler: + B . + .size HardFault_Handler, . - HardFault_Handler + + .weak SVC_Handler + .type SVC_Handler, %function +SVC_Handler: + B . + .size SVC_Handler, . - SVC_Handler + + .weak PendSV_Handler + .type PendSV_Handler, %function +PendSV_Handler: + B . + .size PendSV_Handler, . - PendSV_Handler + + .weak SysTick_Handler + .type SysTick_Handler, %function +SysTick_Handler: + B . + .size SysTick_Handler, . - SysTick_Handler + + +/* IRQ Handlers */ + + .globl Default_Handler + .type Default_Handler, %function +Default_Handler: + B . + .size Default_Handler, . - Default_Handler + + .macro IRQ handler + .weak \handler + .set \handler, Default_Handler + .endm + + IRQ LVD_BOD_IRQHandler + IRQ RTC_IRQHandler + IRQ FLASH_IRQHandler + IRQ EVWUP_IRQHandler + IRQ EXTI0_1_IRQHandler + IRQ EXTI2_3_IRQHandler + IRQ EXTI4_7_IRQHandler + IRQ ADC_IRQHandler + IRQ SCTM0_IRQHandler + IRQ SCTM1_IRQHandler + IRQ SCTM2_IRQHandler + IRQ BFTM0_IRQHandler + IRQ I2C0_IRQHandler + IRQ SPI0_IRQHandler + IRQ UART0_IRQHandler + IRQ UART1_IRQHandler + IRQ LEDC_IRQHandler + + .end diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/emStudio/startup_ht32f5xxxx_es_14.s b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/emStudio/startup_ht32f5xxxx_es_14.s new file mode 100644 index 0000000000..530eb0949f --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/emStudio/startup_ht32f5xxxx_es_14.s @@ -0,0 +1,216 @@ +/*---------------------------------------------------------------------------------------------------------*/ +/* Holtek Semiconductor Inc. */ +/* */ +/* Copyright (C) Holtek Semiconductor Inc. */ +/* All rights reserved. */ +/* */ +/*----------------------------------------------------------------------------------------------------------- +; File Name : startup_ht32f5xxxx_es_14.s +; Version : $Rev:: 6793 $ +; Date : $Date:: 2023-03-14 #$ +; Description : Startup code. +;-----------------------------------------------------------------------------------------------------------*/ + +/* +; Supported Device +; ======================================== +; HT32F50442, HT32F50452 +; HT32F50431, HT32F50441 +*/ + +;/* <<< Use Configuration Wizard in Context Menu >>> */ +/* +;// HT32 Device +;// <0=> By Project Asm Define +;// <26=> HT32F50442/52 +;// <30=> HT32F50431/41 +*/ + .equ USE_HT32_CHIP_SET, 0 + + .equ _HT32FWID, 0xFFFFFFFF +/* + .equ _HT32FWID, 0x00050442 + .equ _HT32FWID, 0x00050452 + .equ _HT32FWID, 0x00050431 + .equ _HT32FWID, 0x00050441 +*/ + + .equ HT32F50442_52, 26 + .equ HT32F50431_41, 30 + + .if USE_HT32_CHIP_SET == 0 + .else + .equ USE_HT32_CHIP, USE_HT32_CHIP_SET + .endif + + .equ _RESERVED, 0xFFFFFFFF +/* +;******************************************************************************* +; Fill-up the Vector Table entries with the exceptions ISR address +;********************************************************************************/ + .syntax unified + .global reset_handler + .global Reset_Handler + .equ Reset_Handler, reset_handler + + .section .vectors, "ax" + .section .vectors, "ax" + .code 16 + .balign 2 + .global _vectors +_vectors: + .long __stack_end__ /* ---, 00, 0x000, Top address of Stack */ + .long reset_handler /* ---, 01, 0x004, Reset Handler */ + .long NMI_Handler /* -14, 02, 0x008, NMI Handler */ + .long HardFault_Handler /* -13, 03, 0x00C, Hard Fault Handler */ + .long _RESERVED /* ---, 04, 0x010, Reserved */ + .long _RESERVED /* ---, 05, 0x014, Reserved */ + .long _RESERVED /* ---, 06, 0x018, Reserved */ + .long _RESERVED /* ---, 07, 0x01C, Reserved */ + .long _HT32FWID /* ---, 08, 0x020, Reserved */ + .long _RESERVED /* ---, 09, 0x024, Reserved */ + .long _RESERVED /* ---, 10, 0x028, Reserved */ + .long SVC_Handler /* -05, 11, 0x02C, SVC Handler */ + .long _RESERVED /* ---, 12, 0x030, Reserved */ + .long _RESERVED /* ---, 13, 0x034, Reserved */ + .long PendSV_Handler /* -02, 14, 0x038, PendSV Handler */ + .long SysTick_Handler /* -01, 15, 0x03C, SysTick Handler */ + + /* External Interrupt Handler */ + .long LVD_BOD_IRQHandler /* 00, 16, 0x040, */ + .long RTC_IRQHandler /* 01, 17, 0x044, */ + .long FLASH_IRQHandler /* 02, 18, 0x048, */ + .long EVWUP_IRQHandler /* 03, 19, 0x04C, */ + .long EXTI0_1_IRQHandler /* 04, 20, 0x050, */ + .long EXTI2_3_IRQHandler /* 05, 21, 0x054, */ + .long EXTI4_15_IRQHandler /* 06, 22, 0x058, */ + .if (USE_HT32_CHIP==HT32F50442_52) + .long COMP_IRQHandler /* 07, 23, 0x05C, */ + .else + .long _RESERVED /* 07, 23, 0x05C, */ + .endif + .long ADC_IRQHandler /* 08, 24, 0x060, */ + .long _RESERVED /* 09, 25, 0x064, */ + .long MCTM0_IRQHandler /* 10, 26, 0x068, */ + .long _RESERVED /* 11, 27, 0x06C, */ + .long GPTM0_IRQHandler /* 12, 28, 0x070, */ + .long _RESERVED /* 13, 29, 0x074, */ + .long _RESERVED /* 14, 30, 0x078, */ + .long PWM0_IRQHandler /* 15, 31, 0x07C, */ + .if (USE_HT32_CHIP==HT32F50442_52) + .long PWM1_IRQHandler /* 16, 32, 0x080, */ + .else + .long _RESERVED /* 16, 32, 0x080, */ + .endif + .long BFTM0_IRQHandler /* 17, 33, 0x084, */ + .long BFTM1_IRQHandler /* 18, 34, 0x088, */ + .long I2C0_IRQHandler /* 19, 35, 0x08C, */ + .long I2C1_IRQHandler /* 20, 36, 0x090, */ + .long SPI0_IRQHandler /* 21, 37, 0x094, */ + .long SPI1_IRQHandler /* 22, 38, 0x098, */ + .long USART0_IRQHandler /* 23, 39, 0x09C, */ + .if (USE_HT32_CHIP==HT32F50442_52) + .long USART1_IRQHandler /* 24, 40, 0x0A0, */ + .else + .long _RESERVED /* 24, 40, 0x0A0, */ + .endif + .long UART0_IRQHandler /* 25, 41, 0x0A4, */ + .long UART1_IRQHandler /* 26, 42, 0x0A8, */ + .long _RESERVED /* 27, 43, 0x0AC, */ + .long _RESERVED /* 28, 44, 0x0B0, */ + .long LEDC_IRQHandler /* 29, 45, 0x0B4, */ + .long PDMA_CH0_1_IRQHandler /* 30, 46, 0x0B8, */ + .long PDMA_CH2_5_IRQHandler /* 31, 47, 0x0BC, */ + + + + .thumb + + +/* Reset Handler */ + + .section .text.reset_handler + .weak reset_handler + .type reset_handler, %function +reset_handler: + LDR R0, =__stack_end__ /* set stack pointer */ + MOV SP, R0 + LDR R0, =SystemInit + BLX R0 + BL _start + .size Reset_Handler, .-Reset_Handler + +/* Exception Handlers */ + + .weak NMI_Handler + .type NMI_Handler, %function +NMI_Handler: + B . + .size NMI_Handler, . - NMI_Handler + + .weak HardFault_Handler + .type HardFault_Handler, %function +HardFault_Handler: + B . + .size HardFault_Handler, . - HardFault_Handler + + .weak SVC_Handler + .type SVC_Handler, %function +SVC_Handler: + B . + .size SVC_Handler, . - SVC_Handler + + .weak PendSV_Handler + .type PendSV_Handler, %function +PendSV_Handler: + B . + .size PendSV_Handler, . - PendSV_Handler + + .weak SysTick_Handler + .type SysTick_Handler, %function +SysTick_Handler: + B . + .size SysTick_Handler, . - SysTick_Handler + + +/* IRQ Handlers */ + + .globl Default_Handler + .type Default_Handler, %function +Default_Handler: + B . + .size Default_Handler, . - Default_Handler + + .macro IRQ handler + .weak \handler + .set \handler, Default_Handler + .endm + + IRQ LVD_BOD_IRQHandler + IRQ RTC_IRQHandler + IRQ FLASH_IRQHandler + IRQ EVWUP_IRQHandler + IRQ EXTI0_1_IRQHandler + IRQ EXTI2_3_IRQHandler + IRQ EXTI4_15_IRQHandler + IRQ COMP_IRQHandler + IRQ ADC_IRQHandler + IRQ MCTM0_IRQHandler + IRQ GPTM0_IRQHandler + IRQ PWM0_IRQHandler + IRQ PWM1_IRQHandler + IRQ BFTM0_IRQHandler + IRQ BFTM1_IRQHandler + IRQ I2C0_IRQHandler + IRQ I2C1_IRQHandler + IRQ SPI0_IRQHandler + IRQ SPI1_IRQHandler + IRQ USART0_IRQHandler + IRQ USART1_IRQHandler + IRQ UART0_IRQHandler + IRQ UART1_IRQHandler + IRQ LEDC_IRQHandler + IRQ PDMA_CH0_1_IRQHandler + IRQ PDMA_CH2_5_IRQHandler + + .end diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/emStudio/startup_ht32f5xxxx_es_15.s b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/emStudio/startup_ht32f5xxxx_es_15.s new file mode 100644 index 0000000000..732e674b45 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/emStudio/startup_ht32f5xxxx_es_15.s @@ -0,0 +1,217 @@ +/*---------------------------------------------------------------------------------------------------------*/ +/* Holtek Semiconductor Inc. */ +/* */ +/* Copyright (C) Holtek Semiconductor Inc. */ +/* All rights reserved. */ +/* */ +/*----------------------------------------------------------------------------------------------------------- +; File Name : startup_ht32f5xxxx_es_15.s +; Version : $Rev:: 6902 $ +; Date : $Date:: 2023-05-08 #$ +; Description : Startup code. +;-----------------------------------------------------------------------------------------------------------*/ + +/* +; Supported Device +; ======================================== +; HT32F53242, HT32F53252 +; HT32F53231, HT32F53241 +*/ + +;/* <<< Use Configuration Wizard in Context Menu >>> */ +/* +;// HT32 Device +;// <0=> By Project Asm Define +;// <28=> HT32F53242/52 +;// <29=> HT32F53231/41 +*/ + .equ USE_HT32_CHIP_SET, 0 + + .equ _HT32FWID, 0xFFFFFFFF +/* + .equ _HT32FWID, 0x00053242 + .equ _HT32FWID, 0x00053252 + .equ _HT32FWID, 0x00053231 + .equ _HT32FWID, 0x00053241 +*/ + + .equ HT32F53242_52, 28 + .equ HT32F53231_41, 29 + + .if USE_HT32_CHIP_SET == 0 + .else + .equ USE_HT32_CHIP, USE_HT32_CHIP_SET + .endif + + .equ _RESERVED, 0xFFFFFFFF +/* +;******************************************************************************* +; Fill-up the Vector Table entries with the exceptions ISR address +;********************************************************************************/ + .syntax unified + .global reset_handler + .global Reset_Handler + .equ Reset_Handler, reset_handler + + .section .vectors, "ax" + .section .vectors, "ax" + .code 16 + .balign 2 + .global _vectors +_vectors: + .long __stack_end__ /* ---, 00, 0x000, Top address of Stack */ + .long reset_handler /* ---, 01, 0x004, Reset Handler */ + .long NMI_Handler /* -14, 02, 0x008, NMI Handler */ + .long HardFault_Handler /* -13, 03, 0x00C, Hard Fault Handler */ + .long _RESERVED /* ---, 04, 0x010, Reserved */ + .long _RESERVED /* ---, 05, 0x014, Reserved */ + .long _RESERVED /* ---, 06, 0x018, Reserved */ + .long _RESERVED /* ---, 07, 0x01C, Reserved */ + .long _HT32FWID /* ---, 08, 0x020, Reserved */ + .long _RESERVED /* ---, 09, 0x024, Reserved */ + .long _RESERVED /* ---, 10, 0x028, Reserved */ + .long SVC_Handler /* -05, 11, 0x02C, SVC Handler */ + .long _RESERVED /* ---, 12, 0x030, Reserved */ + .long _RESERVED /* ---, 13, 0x034, Reserved */ + .long PendSV_Handler /* -02, 14, 0x038, PendSV Handler */ + .long SysTick_Handler /* -01, 15, 0x03C, SysTick Handler */ + + /* External Interrupt Handler */ + .long LVD_BOD_IRQHandler /* 00, 16, 0x040, */ + .long RTC_IRQHandler /* 01, 17, 0x044, */ + .long FLASH_IRQHandler /* 02, 18, 0x048, */ + .long EVWUP_IRQHandler /* 03, 19, 0x04C, */ + .long EXTI0_1_IRQHandler /* 04, 20, 0x050, */ + .long EXTI2_3_IRQHandler /* 05, 21, 0x054, */ + .long EXTI4_15_IRQHandler /* 06, 22, 0x058, */ + .if (USE_HT32_CHIP==HT32F53242_52) + .long COMP_IRQHandler /* 07, 23, 0x05C, */ + .else + .long _RESERVED /* 07, 23, 0x05C, */ + .endif + .long ADC_IRQHandler /* 08, 24, 0x060, */ + .long _RESERVED /* 09, 25, 0x064, */ + .long MCTM0_IRQHandler /* 10, 26, 0x068, */ + .long _RESERVED /* 11, 27, 0x06C, */ + .long GPTM0_IRQHandler /* 12, 28, 0x070, */ + .long _RESERVED /* 13, 29, 0x074, */ + .long _RESERVED /* 14, 30, 0x078, */ + .long PWM0_IRQHandler /* 15, 31, 0x07C, */ + .if (USE_HT32_CHIP==HT32F53242_52) + .long PWM1_IRQHandler /* 16, 32, 0x080, */ + .else + .long _RESERVED /* 16, 32, 0x080, */ + .endif + .long BFTM0_IRQHandler /* 17, 33, 0x084, */ + .long BFTM1_IRQHandler /* 18, 34, 0x088, */ + .long I2C0_IRQHandler /* 19, 35, 0x08C, */ + .long I2C1_IRQHandler /* 20, 36, 0x090, */ + .long SPI0_IRQHandler /* 21, 37, 0x094, */ + .long SPI1_IRQHandler /* 22, 38, 0x098, */ + .long USART0_IRQHandler /* 23, 39, 0x09C, */ + .if (USE_HT32_CHIP==HT32F53242_52) + .long USART1_IRQHandler /* 24, 40, 0x0A0, */ + .else + .long _RESERVED /* 24, 40, 0x0A0, */ + .endif + .long UART0_IRQHandler /* 25, 41, 0x0A4, */ + .long UART1_IRQHandler /* 26, 42, 0x0A8, */ + .long CAN0_IRQHandler /* 27, 43, 0x0AC, */ + .long _RESERVED /* 28, 44, 0x0B0, */ + .long LEDC_IRQHandler /* 29, 45, 0x0B4, */ + .long PDMA_CH0_1_IRQHandler /* 30, 46, 0x0B8, */ + .long PDMA_CH2_5_IRQHandler /* 31, 47, 0x0BC, */ + + + + .thumb + + +/* Reset Handler */ + + .section .text.reset_handler + .weak reset_handler + .type reset_handler, %function +reset_handler: + LDR R0, =__stack_end__ /* set stack pointer */ + MOV SP, R0 + LDR R0, =SystemInit + BLX R0 + BL _start + .size Reset_Handler, .-Reset_Handler + +/* Exception Handlers */ + + .weak NMI_Handler + .type NMI_Handler, %function +NMI_Handler: + B . + .size NMI_Handler, . - NMI_Handler + + .weak HardFault_Handler + .type HardFault_Handler, %function +HardFault_Handler: + B . + .size HardFault_Handler, . - HardFault_Handler + + .weak SVC_Handler + .type SVC_Handler, %function +SVC_Handler: + B . + .size SVC_Handler, . - SVC_Handler + + .weak PendSV_Handler + .type PendSV_Handler, %function +PendSV_Handler: + B . + .size PendSV_Handler, . - PendSV_Handler + + .weak SysTick_Handler + .type SysTick_Handler, %function +SysTick_Handler: + B . + .size SysTick_Handler, . - SysTick_Handler + + +/* IRQ Handlers */ + + .globl Default_Handler + .type Default_Handler, %function +Default_Handler: + B . + .size Default_Handler, . - Default_Handler + + .macro IRQ handler + .weak \handler + .set \handler, Default_Handler + .endm + + IRQ LVD_BOD_IRQHandler + IRQ RTC_IRQHandler + IRQ FLASH_IRQHandler + IRQ EVWUP_IRQHandler + IRQ EXTI0_1_IRQHandler + IRQ EXTI2_3_IRQHandler + IRQ EXTI4_15_IRQHandler + IRQ COMP_IRQHandler + IRQ ADC_IRQHandler + IRQ MCTM0_IRQHandler + IRQ GPTM0_IRQHandler + IRQ PWM0_IRQHandler + IRQ PWM1_IRQHandler + IRQ BFTM0_IRQHandler + IRQ BFTM1_IRQHandler + IRQ I2C0_IRQHandler + IRQ I2C1_IRQHandler + IRQ SPI0_IRQHandler + IRQ SPI1_IRQHandler + IRQ USART0_IRQHandler + IRQ USART1_IRQHandler + IRQ UART0_IRQHandler + IRQ UART1_IRQHandler + IRQ CAN0_IRQHandler + IRQ LEDC_IRQHandler + IRQ PDMA_CH0_1_IRQHandler + IRQ PDMA_CH2_5_IRQHandler + + .end diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/emStudio/startup_ht32f5xxxx_es_16.s b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/emStudio/startup_ht32f5xxxx_es_16.s new file mode 100644 index 0000000000..81260f6c78 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/emStudio/startup_ht32f5xxxx_es_16.s @@ -0,0 +1,221 @@ +/*---------------------------------------------------------------------------------------------------------*/ +/* Holtek Semiconductor Inc. */ +/* */ +/* Copyright (C) Holtek Semiconductor Inc. */ +/* All rights reserved. */ +/* */ +/*----------------------------------------------------------------------------------------------------------- +; File Name : startup_ht32f5xxxx_es_16.s +; Version : $Rev:: 7094 $ +; Date : $Date:: 2023-08-02 #$ +; Description : Startup code. +;-----------------------------------------------------------------------------------------------------------*/ + +/* +; Supported Device +; ======================================== +; HT32F66242 +; HT32F66246 +*/ + +;/* <<< Use Configuration Wizard in Context Menu >>> */ +/* + + + + +*/ + .equ USE_HT32_CHIP_SET, 0 + +/* + .equ _HT32FWID, 0xFFFFFFFF + .equ _HT32FWID, 0x00066246 +*/ + + .equ HT32F66246, 31 + .equ HT32F66242, 33 + + .if USE_HT32_CHIP_SET == 0 + .else + .equ USE_HT32_CHIP, USE_HT32_CHIP_SET + .endif + + .if USE_HT32_CHIP == 0 + .equ _HT32FWID, 0x00066246 + .endif + .if USE_HT32_CHIP == HT32F66246 + .equ _HT32FWID, 0x00066246 + .endif + .if USE_HT32_CHIP == HT32F66242 + .equ _HT32FWID, 0x00066242 + .endif + + .equ _RESERVED, 0xFFFFFFFF +/* +;******************************************************************************* +; Fill-up the Vector Table entries with the exceptions ISR address +;********************************************************************************/ + .syntax unified + .global reset_handler + .global Reset_Handler + .equ Reset_Handler, reset_handler + + .section .vectors, "ax" + .section .vectors, "ax" + .code 16 + .balign 2 + .global _vectors +_vectors: + .long __stack_end__ /* ---, 00, 0x000, Top address of Stack */ + .long reset_handler /* ---, 01, 0x004, Reset Handler */ + .long NMI_Handler /* -14, 02, 0x008, NMI Handler */ + .long HardFault_Handler /* -13, 03, 0x00C, Hard Fault Handler */ + .long _RESERVED /* ---, 04, 0x010, Reserved */ + .long _RESERVED /* ---, 05, 0x014, Reserved */ + .long _RESERVED /* ---, 06, 0x018, Reserved */ + .long _RESERVED /* ---, 07, 0x01C, Reserved */ + .long _HT32FWID /* ---, 08, 0x020, Reserved */ + .long _RESERVED /* ---, 09, 0x024, Reserved */ + .long _RESERVED /* ---, 10, 0x028, Reserved */ + .long SVC_Handler /* -05, 11, 0x02C, SVC Handler */ + .long _RESERVED /* ---, 12, 0x030, Reserved */ + .long _RESERVED /* ---, 13, 0x034, Reserved */ + .long PendSV_Handler /* -02, 14, 0x038, PendSV Handler */ + .long SysTick_Handler /* -01, 15, 0x03C, SysTick Handler */ + + /* External Interrupt Handler */ + .long LVD_BOD_IRQHandler /* 00, 16, 0x040, */ + .long RTC_IRQHandler /* 01, 17, 0x044, */ + .long FLASH_IRQHandler /* 02, 18, 0x048, */ + .long EVWUP_IRQHandler /* 03, 19, 0x04C, */ + .long EXTI0_1_IRQHandler /* 04, 20, 0x050, */ + .long EXTI2_3_IRQHandler /* 05, 21, 0x054, */ + .long EXTI4_15_IRQHandler /* 06, 22, 0x058, */ + .if (USE_HT32_CHIP==HT32F66246) + .long CAN0_IRQHandler /* 07, 23, 0x05C, */ + .else + .long _RESERVED /* 07, 23, 0x05C, */ + .endif + .long ADC_IRQHandler /* 08, 24, 0x060, */ + .long CORDIC_IRQHandler /* 09, 25, 0x064, */ + .long MCTM0_BRK_IRQHandler /* 10, 26, 0x068, */ + .long MCTM0_UP_IRQHandler /* 11, 27, 0x06C, */ + .long MCTM0_TR_UP2_IRQHandler /* 12, 28, 0x070, */ + .long MCTM0_CC_IRQHandler /* 13, 29, 0x074, */ + .long GPTM0_G_IRQHandler /* 14, 30, 0x078, */ + .long GPTM0_VCLK_IRQHandler /* 15, 31, 0x07C, */ + .long BFTM0_IRQHandler /* 16, 32, 0x080, */ + .long BFTM1_IRQHandler /* 17, 33, 0x084, */ + .long CMP0_IRQHandler /* 18, 34, 0x088, */ + .long CMP1_IRQHandler /* 19, 35, 0x08C, */ + .long PID_IRQHandler /* 20, 36, 0x090, */ + .long I2C0_IRQHandler /* 21, 37, 0x094, */ + .long SPI0_IRQHandler /* 22, 38, 0x098, */ + .long USART0_IRQHandler /* 23, 39, 0x09C, */ + .long UART0_IRQHandler /* 24, 40, 0x0A0, */ + .long PDMA_CH0_1_IRQHandler /* 25, 41, 0x0A4, */ + .long PDMA_CH2_3_IRQHandler /* 26, 42, 0x0A8, */ + .long PDMA_CH4_5_IRQHandler /* 27, 43, 0x0AC, */ + .long SCTM0_IRQHandler /* 28, 44, 0x0B0, */ + .long SCTM1_IRQHandler /* 29, 45, 0x0B4, */ + .long SCTM2_IRQHandler /* 30, 46, 0x0B8, */ + .long SCTM3_IRQHandler /* 31, 47, 0x0BC, */ + + + + .thumb + + +/* Reset Handler */ + + .section .text.reset_handler + .weak reset_handler + .type reset_handler, %function +reset_handler: + LDR R0, =__stack_end__ /* set stack pointer */ + MOV SP, R0 + LDR R0, =SystemInit + BLX R0 + BL _start + .size Reset_Handler, .-Reset_Handler + +/* Exception Handlers */ + + .weak NMI_Handler + .type NMI_Handler, %function +NMI_Handler: + B . + .size NMI_Handler, . - NMI_Handler + + .weak HardFault_Handler + .type HardFault_Handler, %function +HardFault_Handler: + B . + .size HardFault_Handler, . - HardFault_Handler + + .weak SVC_Handler + .type SVC_Handler, %function +SVC_Handler: + B . + .size SVC_Handler, . - SVC_Handler + + .weak PendSV_Handler + .type PendSV_Handler, %function +PendSV_Handler: + B . + .size PendSV_Handler, . - PendSV_Handler + + .weak SysTick_Handler + .type SysTick_Handler, %function +SysTick_Handler: + B . + .size SysTick_Handler, . - SysTick_Handler + + +/* IRQ Handlers */ + + .globl Default_Handler + .type Default_Handler, %function +Default_Handler: + B . + .size Default_Handler, . - Default_Handler + + .macro IRQ handler + .weak \handler + .set \handler, Default_Handler + .endm + + IRQ LVD_BOD_IRQHandler + IRQ RTC_IRQHandler + IRQ FLASH_IRQHandler + IRQ EVWUP_IRQHandler + IRQ EXTI0_1_IRQHandler + IRQ EXTI2_3_IRQHandler + IRQ EXTI4_15_IRQHandler + IRQ CAN0_IRQHandler + IRQ ADC_IRQHandler + IRQ CORDIC_IRQHandler + IRQ MCTM0_BRK_IRQHandler + IRQ MCTM0_UP_IRQHandler + IRQ MCTM0_TR_UP2_IRQHandler + IRQ MCTM0_CC_IRQHandler + IRQ GPTM0_G_IRQHandler + IRQ GPTM0_VCLK_IRQHandler + IRQ BFTM0_IRQHandler + IRQ BFTM1_IRQHandler + IRQ CMP0_IRQHandler + IRQ CMP1_IRQHandler + IRQ PID_IRQHandler + IRQ I2C0_IRQHandler + IRQ SPI0_IRQHandler + IRQ USART0_IRQHandler + IRQ UART0_IRQHandler + IRQ PDMA_CH0_1_IRQHandler + IRQ PDMA_CH2_3_IRQHandler + IRQ PDMA_CH4_5_IRQHandler + IRQ SCTM0_IRQHandler + IRQ SCTM1_IRQHandler + IRQ SCTM2_IRQHandler + IRQ SCTM3_IRQHandler + + .end diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/emStudio/startup_ht32f5xxxx_es_17.s b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/emStudio/startup_ht32f5xxxx_es_17.s new file mode 100644 index 0000000000..d5be1f4cd5 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/emStudio/startup_ht32f5xxxx_es_17.s @@ -0,0 +1,195 @@ +/*---------------------------------------------------------------------------------------------------------*/ +/* Holtek Semiconductor Inc. */ +/* */ +/* Copyright (C) Holtek Semiconductor Inc. */ +/* All rights reserved. */ +/* */ +/*----------------------------------------------------------------------------------------------------------- +; File Name : startup_ht32f5xxxx_es_17.s +; Version : $Rev:: 7030 $ +; Date : $Date:: 2023-07-18 #$ +; Description : Startup code. +;-----------------------------------------------------------------------------------------------------------*/ + +/* +; Supported Device +; ======================================== +; HT32F52234, HT32F52244 +*/ + +;/* <<< Use Configuration Wizard in Context Menu >>> */ +/* +;// HT32 Device +;// <0=> By Project Asm Define +;// <33=> HT32F52234/44 +*/ + .equ USE_HT32_CHIP_SET, 0 + + .equ _HT32FWID, 0xFFFFFFFF +/* + .equ _HT32FWID, 0x00052234 + .equ _HT32FWID, 0x00052244 +*/ + + .equ HT32F52234_44, 33 + + .if USE_HT32_CHIP_SET == 0 + .else + .equ USE_HT32_CHIP, USE_HT32_CHIP_SET + .endif + + .equ _RESERVED, 0xFFFFFFFF +/* +;******************************************************************************* +; Fill-up the Vector Table entries with the exceptions ISR address +;********************************************************************************/ + .syntax unified + .global reset_handler + .global Reset_Handler + .equ Reset_Handler, reset_handler + + .section .vectors, "ax" + .section .vectors, "ax" + .code 16 + .balign 2 + .global _vectors +_vectors: + .long __stack_end__ /* ---, 00, 0x000, Top address of Stack */ + .long reset_handler /* ---, 01, 0x004, Reset Handler */ + .long NMI_Handler /* -14, 02, 0x008, NMI Handler */ + .long HardFault_Handler /* -13, 03, 0x00C, Hard Fault Handler */ + .long _RESERVED /* ---, 04, 0x010, Reserved */ + .long _RESERVED /* ---, 05, 0x014, Reserved */ + .long _RESERVED /* ---, 06, 0x018, Reserved */ + .long _RESERVED /* ---, 07, 0x01C, Reserved */ + .long _HT32FWID /* ---, 08, 0x020, Reserved */ + .long _RESERVED /* ---, 09, 0x024, Reserved */ + .long _RESERVED /* ---, 10, 0x028, Reserved */ + .long SVC_Handler /* -05, 11, 0x02C, SVC Handler */ + .long _RESERVED /* ---, 12, 0x030, Reserved */ + .long _RESERVED /* ---, 13, 0x034, Reserved */ + .long PendSV_Handler /* -02, 14, 0x038, PendSV Handler */ + .long SysTick_Handler /* -01, 15, 0x03C, SysTick Handler */ + + /* External Interrupt Handler */ + .long LVD_BOD_IRQHandler /* 00, 16, 0x040, */ + .long RTC_IRQHandler /* 01, 17, 0x044, */ + .long FLASH_IRQHandler /* 02, 18, 0x048, */ + .long EVWUP_IRQHandler /* 03, 19, 0x04C, */ + .long EXTI0_1_IRQHandler /* 04, 20, 0x050, */ + .long EXTI2_3_IRQHandler /* 05, 21, 0x054, */ + .long EXTI4_15_IRQHandler /* 06, 22, 0x058, */ + .long DAC0_1_IRQHandler /* 07, 23, 0x05C, */ + .long ADC_IRQHandler /* 08, 24, 0x060, */ + .long I2C2_IRQHandler /* 09, 25, 0x064, */ + .long _RESERVED /* 10, 26, 0x068, */ + .long _RESERVED /* 11, 27, 0x06C, */ + .long _RESERVED /* 12, 28, 0x070, */ + .long SCTM0_IRQHandler /* 13, 29, 0x074, */ + .long SCTM1_IRQHandler /* 14, 30, 0x078, */ + .long PWM0_IRQHandler /* 15, 31, 0x07C, */ + .long _RESERVED /* 16, 32, 0x080, */ + .long BFTM0_IRQHandler /* 17, 33, 0x084, */ + .long BFTM1_IRQHandler /* 18, 34, 0x088, */ + .long I2C0_IRQHandler /* 19, 35, 0x08C, */ + .long I2C1_IRQHandler /* 20, 36, 0x090, */ + .long SPI0_IRQHandler /* 21, 37, 0x094, */ + .long _RESERVED /* 22, 38, 0x098, */ + .long USART0_IRQHandler /* 23, 39, 0x09C, */ + .long _RESERVED /* 24, 40, 0x0A0, */ + .long UART0_IRQHandler /* 25, 41, 0x0A4, */ + .long _RESERVED /* 26, 42, 0x0A8, */ + .long _RESERVED /* 27, 43, 0x0AC, */ + .long _RESERVED /* 28, 44, 0x0B0, */ + .long _RESERVED /* 29, 45, 0x0B4, */ + .long PDMA_CH0_1_IRQHandler /* 30, 46, 0x0B8, */ + .long PDMA_CH2_5_IRQHandler /* 31, 47, 0x0BC, */ + + + + .thumb + + +/* Reset Handler */ + + .section .text.reset_handler + .weak reset_handler + .type reset_handler, %function +reset_handler: + LDR R0, =__stack_end__ /* set stack pointer */ + MOV SP, R0 + LDR R0, =SystemInit + BLX R0 + BL _start + .size Reset_Handler, .-Reset_Handler + +/* Exception Handlers */ + + .weak NMI_Handler + .type NMI_Handler, %function +NMI_Handler: + B . + .size NMI_Handler, . - NMI_Handler + + .weak HardFault_Handler + .type HardFault_Handler, %function +HardFault_Handler: + B . + .size HardFault_Handler, . - HardFault_Handler + + .weak SVC_Handler + .type SVC_Handler, %function +SVC_Handler: + B . + .size SVC_Handler, . - SVC_Handler + + .weak PendSV_Handler + .type PendSV_Handler, %function +PendSV_Handler: + B . + .size PendSV_Handler, . - PendSV_Handler + + .weak SysTick_Handler + .type SysTick_Handler, %function +SysTick_Handler: + B . + .size SysTick_Handler, . - SysTick_Handler + + +/* IRQ Handlers */ + + .globl Default_Handler + .type Default_Handler, %function +Default_Handler: + B . + .size Default_Handler, . - Default_Handler + + .macro IRQ handler + .weak \handler + .set \handler, Default_Handler + .endm + + IRQ LVD_BOD_IRQHandler + IRQ RTC_IRQHandler + IRQ FLASH_IRQHandler + IRQ EVWUP_IRQHandler + IRQ EXTI0_1_IRQHandler + IRQ EXTI2_3_IRQHandler + IRQ EXTI4_15_IRQHandler + IRQ DAC0_1_IRQHandler + IRQ ADC_IRQHandler + IRQ I2C2_IRQHandler + IRQ SCTM0_IRQHandler + IRQ SCTM1_IRQHandler + IRQ PWM0_IRQHandler + IRQ BFTM0_IRQHandler + IRQ BFTM1_IRQHandler + IRQ I2C0_IRQHandler + IRQ I2C1_IRQHandler + IRQ SPI0_IRQHandler + IRQ USART0_IRQHandler + IRQ UART0_IRQHandler + IRQ PDMA_CH0_1_IRQHandler + IRQ PDMA_CH2_5_IRQHandler + + .end diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/system_ht32f0006.c b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/system_ht32f0006.c new file mode 100644 index 0000000000..aa9578190f --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/system_ht32f0006.c @@ -0,0 +1,478 @@ +/**************************************************************************//** + * @file library/Device/Holtek/HT32F5xxxx/Source/system_ht32f0006.c + * @brief CMSIS Cortex-M0+ Device Peripheral Access Layer Source File + * for the Holtek HT32F5xxxx Device Series + * @version $Rev:: 6597 $ + * @date $Date:: 2022-12-27 #$ + * + * @note + * Copyright (C) Holtek Semiconductor Inc. All rights reserved. + * + * @par + * ARM Limited (ARM) supplies this software for Cortex-M processor-based + * microcontrollers. This file can be freely distributed within development + * tools that are supporting such ARM based processors. + * + * @par + * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR + * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + ******************************************************************************/ + +// Supported Device +// ======================================== +// HT32F0006 +// HT32F61352 + +//#define USE_HT32F0006 +//#define USE_HT32F61352 + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup HT32F5xxxx_system HT32F5xxxx System + * @{ + */ + + +#include "ht32f5xxxx_01.h" + +/** @addtogroup HT32F5xxxx_System_Private_Defines + * @{ + */ +/* +//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ +*/ + +/*--------------------- Clock Configuration ---------------------------------- +// +// Enable High Speed External Crystal Oscillator (HSE) +// Default HSE = DISABLE +// +// Enable Low Speed External Crystal Oscillator (LSE) +// Default LSE = DISABLE +// +// Enable PLL +// Default PLL = DISABLE +// PLL Clock Source +// <0=> CK_HSE +// <1=> CK_HSI +// Default PLL clock source = CK_HSI +// PLL source clock must be in the range of 4 MHz to 16 MHz +// PLL Feedback Clock Divider (NF2): 1 ~ 16 +// <1-16:1> +// PLL feedback clock = PLL clock source x NF2 +// PLL feedback clock must be in the range of 24 MHz to 48 MHz +// PLL Output Clock Divider (NO2) +// <0=> 1 +// <1=> 2 +// <2=> 4 +// <3=> 8 +// PLL output clock = PLL feedback clock / NO2 +// PLL output clock must be in the range of 4 MHz to 48 MHz +// +// +// SystemCoreClock Configuration (CK_AHB) +// SystemCoreClock Source +// <1=> CK_PLL +// <2=> CK_HSE +// <3=> CK_HSI +// <6=> CK_LSE +// <7=> CK_LSI +// Default SystemCoreClock source = CK_HSI +// SystemCoreClock Source Divider +// <0=> 1 +// <1=> 2 +// <2=> 4 +// <3=> 8 +// <4=> 16 +// <5=> 32 +// Default SystemCoreClock source divider = 1 +// +// +// FLASH Configuration +// Wait state +// <0=> 0 WS +// <1=> 1 WS +// <9=> AUTO +// 0 WS: 1 kHz <= CK_AHB <= 24 MHz +// 1 WS: 24 MHz < CK_AHB <= 48 MHz +// Pre-fetch Buffer Enable +// Default pre-fetch buffer = ENABLE +// Branch cache Enable +// Default branch cache = ENABLE +// +*/ + +/* !!! NOTICE !!! + HSI must keep turn on when doing the Flash operation (Erase/Program). +*/ + +/* !!! NOTICE !!! + * How to adjust the value of High Speed External oscillator (HSE)? + The default value of HSE is define by "HSE_VALUE" in "ht32fxxxxx_nn.h". + If your board uses a different HSE speed, please add a new compiler preprocessor + C define, "HSE_VALUE=n000000" ("n" represents n MHz) in the toolchain/IDE, + or edit the "HSE_VALUE" in the "ht32f5xxxx_conf.h" file. + Take Keil MDK-ARM for instance, to set HSE as 16 MHz: + "Option of Taret -> C/C++ > Preprocessor Symbols" + Define: USE_HT32_DRIVER, USE_HT32Fxxxxx_SK, USE_HT32Fxxxxx_xx, USE_MEM_HT32Fxxxxx, HSE_VALUE=16000000 + ^^ Add "HSE_VALUE" + define as above. +*/ +#define HSI_ENABLE (1) /*!< 0: DISABLE, 1: ENABLE */ +#define HSE_ENABLE (1) /*!< 0: DISABLE, 1: ENABLE */ +#define LSI_ENABLE (1) /*!< 0: DISABLE, 1: ENABLE */ +#define LSE_ENABLE (0) /*!< 0: DISABLE, 1: ENABLE */ +#define PLL_ENABLE (1) /*!< 0: DISABLE, 1: ENABLE */ +#define PLL_CLK_SRC (0) /*!< 0: HSE, 1: HSI */ +#define PLL_NF2_DIV (4) /*!< 1~16: DIV1~DIV16 */ +#define PLL_NO2_DIV (0) /*!< 0: DIV1, 1: DIV2, 2: DIV4, 3: DIV8 */ +#define HCLK_SRC (1) /*!< 0: PLL, 1: PLL, 2: HSE, 3: HSI 6: LSE, 7: LSI */ +#define HCLK_DIV (0) /*!< 0: DIV1, 1: DIV2, 2: DIV4, 3: DIV8, 4: DIV16, 5: DIV32 */ +#define WAIT_STATE (9) /*!< 0: WS = 0, 1: WS = 1, 9: WS = AUTO */ +#define PRE_FETCH_ENABLE (1) /*!< 0: DISABLE, 1: ENABLE */ +#define BCACHE_ENABLE (1) /*!< 0: DISABLE, 1: ENABLE */ +#define DEINIT_ENABLE (1) /* Set 0 for reduce code size */ + +/*----------------------------------------------------------------------------------------------------------*/ +/* PLL Out = ((HSE or HSI) x PLL_NF2) / PLL_NO2 */ +/*----------------------------------------------------------------------------------------------------------*/ + + +/*--------------------- WDT Configuration ---------------------------------- +// +// Enable WDT Configuration +// WDT Prescaler Selection +// <0=> CK_WDT / 1 +// <1=> CK_WDT / 2 +// <2=> CK_WDT / 4 +// <3=> CK_WDT / 8 +// <4=> CK_WDT / 16 +// <5=> CK_WDT / 32 +// <6=> CK_WDT / 64 +// <7=> CK_WDT / 128 +// WDT Reload Value <1-4095:1> +// Enable WDT Reset function +// WDT Sleep Halt mode +// <0=> No halt +// <1=> Halt in DeepSleep1 +// <2=> Halt in Sleep & DeepSleep1 +// +*/ +#define WDT_ENABLE (0) /*!< 0: DISABLE, 1: ENABLE */ +#define WDT_PRESCALER (5) /*!< 0: 1/1, 1: 1/2, 2: 1/4, 3: 1/8, 4: 1/16, 5: 1/32, 6: 1/64, 7: 1/128 */ +#define WDT_RELOAD (2000) /*!< 0 ~ 4095, 12 bit */ +#define WDT_RESET_ENABLE (1) /*!< 0: No Reset, 1: Reset when WDT over flow */ +#define WDT_SLEEP_HALT (2) /*!< 0: No halt, 1: Halt in DeepSleep1, 2: Halt in Sleep & DeepSleep1 */ + +/** + * @brief Check HSI frequency + */ +#if (HSI_VALUE != 8000000UL) + #error "CK_HSI clock issue: must be 8 MHz!" +#endif + +/** + * @brief Check HSE frequency + */ +#if ((HSE_VALUE < 4000000UL) || (HSE_VALUE > 16000000UL)) + #error "CK_HSE clock issue: must be in the range of 4 MHz to 16 MHz!" +#endif + +/** + * @brief Check LSI frequency + */ +#if (LSI_VALUE != 32000UL) + #error "CK_LSI clock issue: must be 32 kHz!" +#endif + +/** + * @brief Check LSE frequency + */ +#if (LSE_VALUE != 32768UL) + #error "CK_LSE clock issue: must be 32.768 kHz!" +#endif + +/** + * @brief CK_PLL definition + */ +#if (PLL_ENABLE == 1) + /* Get CK_VCO frequency */ + #if (PLL_CLK_SRC == 1) + #if (HSI_ENABLE == 0) + #error "CK_PLL clock source issue: HSI has not been enabled" + #else + #define __CK_VCO (HSI_VALUE * PLL_NF2_DIV) /*!< Select HSI as PLL source */ + #endif + #else + #if (HSE_ENABLE == 0) + #error "CK_PLL clock source issue: HSE has not been enabled!" + #else + #define __CK_VCO (HSE_VALUE * PLL_NF2_DIV) /*!< Select HSE as PLL source */ + #endif + #endif + + #define VCO_MIN 24000000UL + #define VCO_MAX 48000000UL + #define PLL_MIN 4000000UL + #define PLL_MAX 48000000UL + + /* Check CK_VCO frequency */ + #if ((__CK_VCO < VCO_MIN) || (__CK_VCO > VCO_MAX)) + #error "CK_VCO clock issue: must be in the range!" + #endif + + #define __CK_PLL (__CK_VCO >> PLL_NO2_DIV) /*!< Get CK_PLL frequency */ + + /* Check CK_PLL frequency */ + #if ((__CK_PLL < PLL_MIN) || (__CK_PLL > PLL_MAX)) + #error "CK_PLL clock issue: must be in the range!" + #endif +#endif + +/** + * @brief CK_SYS definition + */ +#if (HCLK_SRC == 1) + #if (PLL_ENABLE == 1) + #define __CK_SYS __CK_PLL /*!< Select PLL as CK_SYS source */ + #else + #error "CK_SYS clock source issue: PLL is not enable!" + #endif +#elif (HCLK_SRC == 2) + #if (HSE_ENABLE == 1) + #define __CK_SYS HSE_VALUE /*!< Select HSE as CK_SYS source */ + #else + #error "CK_SYS clock source issue: HSE is not enable!" + #endif +#elif (HCLK_SRC == 3) + #if (HSI_ENABLE == 1) + #define __CK_SYS HSI_VALUE /*!< Select HSI as CK_SYS source */ + #else + #error "CK_SYS clock source issue: HSI is not enable!" + #endif +#elif (HCLK_SRC == 6) + #if (LSE_ENABLE == 1) + #define __CK_SYS LSE_VALUE /*!< Select LSE as CK_SYS source */ + #else + #error "CK_SYS clock source issue: LSE is not enable!" + #endif +#elif (HCLK_SRC == 7) + #if (LSI_ENABLE == 1) + #define __CK_SYS LSI_VALUE /*!< Select LSI as CK_SYS source */ + #else + #error "CK_SYS clock source issue: LSI is not enable!" + #endif +#else + #error "CK_SYS clock source issue: No clock source is selected!" +#endif + +/** + * @brief CK_AHB definition + */ +#define __CK_AHB (__CK_SYS >> HCLK_DIV) /*!< Get CK_AHB frequency */ + +#define CKAHB_MIN 1000UL +#define CKAHB_MAX 48000000UL +#define WS0_CLK 24000000UL + +/* Check CK_AHB frequency */ +#if ((__CK_AHB < CKAHB_MIN) || (__CK_AHB > CKAHB_MAX)) + #error "CK_AHB clock issue: must be in the range!" +#endif + +/* Check FLASH wait-state setting */ +#if ((__CK_AHB > WS0_CLK) && (WAIT_STATE < 1)) + #error "FLASH wait state configuration issue!" +#endif +/** + * @} + */ + +/** @addtogroup HT32F5xxxx_System_Private_Variables + * @{ + */ +__IO uint32_t SystemCoreClock = __CK_AHB; /*!< SystemCoreClock = CK_AHB */ +/** + * @} + */ + +/** @addtogroup HT32F5xxxx_System_Private_Functions + * @{ + */ + +/** + * @brief Setup the microcontroller system. + * Initializes the system clocks and the embedded Flash. + * @note This function should be used after reset. + * @retval None + */ +void SystemInit(void) +{ +#if (WDT_ENABLE == 1) + HT_CKCU->APBCCR1 |= (0x1 << 4); + HT_WDT->PR = 0x35CA; + HT_WDT->MR0 = 0; + HT_WDT->MR1 = ((HT_WDT->MR1 & 0xFFF) | (WDT_PRESCALER << 12)); + HT_WDT->MR0 = WDT_RELOAD | (WDT_RESET_ENABLE << 13) | (WDT_SLEEP_HALT << 14) | (0x1 << 16); + HT_WDT->CR = 0x5FA00001; +#else + #if (DEINIT_ENABLE == 1) + HT_RSTCU->APBPRST1 = (1 << 4); + #endif +#endif + + HT_CKCU->LPCR = 1; /* configure Backup domain isolation */ + SetBit_BB((u32)(&HT_CKCU->APBCCR1), 6); /* enable Backup domain register clock */ + while (HT_PWRCU->TEST != 0x27); /* wait for Backup domain register ready */ + + #if (DEINIT_ENABLE == 1) + /* De-init the setting */ + HT_CKCU->AHBCCR &= ~(0x3 << 10); /* disable IP who may use PLL as source */ + SetBit_BB((u32)(&HT_CKCU->GCCR), 11); /* enable HSI */ + while (!GetBit_BB((u32)(&HT_CKCU->GCSR), 3)); /* wait for HSI ready */ + HT_CKCU->GCCR = ((HT_CKCU->GCCR & ~7UL) | 3UL); /* select CK_SYS source */ + while ((HT_CKCU->CKST & 7UL) != 3UL); /* wait for clock switch complete */ + HT_FLASH->CFCR = (((HT_FLASH->CFCR) & ~7UL) | 1UL); /* set Wait State as 0 WS */ + HT_CKCU->AHBCFGR = 0; /* set CK_AHB prescaler */ + ResetBit_BB((u32)(&HT_CKCU->GCCR), 9); /* disable PLL */ + SetBit_BB((u32)(&HT_CKCU->GCFGR), 8); /* select PLL source as HSI */ + #endif + + /* HSE initiation */ +#if (HSE_ENABLE == 1) + SetBit_BB((u32)(&HT_CKCU->GCCR), 10); /* enable HSE */ + while (!GetBit_BB((u32)(&HT_CKCU->GCSR), 2)){}; /* wait for HSE ready */ +#endif + + /* LSE initiation */ +#if (LSE_ENABLE == 1) + do { + SetBit_BB((u32)(&HT_RTC->CR), 3); /* enable LSE */ + } while (!GetBit_BB((u32)(&HT_RTC->CR), 3)); + while (!GetBit_BB((u32)(&HT_CKCU->GCSR), 4)); /* wait for LSE ready */ +#endif + + ResetBit_BB((u32)(&HT_CKCU->APBCCR1), 6); /* disable Backup domain register clock */ + + /* LSI initiation */ +#if (HCLK_SRC == 7) + while (!GetBit_BB((u32)(&HT_CKCU->GCSR), 5)){}; /* wait for LSI ready */ +#endif + + /* PLL initiation */ +#if (PLL_ENABLE == 1) + #if (PLL_CLK_SRC == 0) + ResetBit_BB((u32)(&HT_CKCU->GCFGR), 8); /* select PLL source as HSE */ + #else + SetBit_BB((u32)(&HT_CKCU->GCFGR), 8); /* select PLL source as HSI */ + #endif + HT_CKCU->PLLCFGR = ((PLL_NF2_DIV & 0x0F) << 23) | (PLL_NO2_DIV << 21); /* set PLL divider */ + SetBit_BB((u32)(&HT_CKCU->GCCR), 9); /* enable PLL */ + while (!GetBit_BB((u32)(&HT_CKCU->GCSR), 1)){}; /* wait for PLL ready */ +#endif + + /* CK_AHB initiation */ +#if (WAIT_STATE == 9) + #if (__CK_AHB > WS0_CLK) + HT_FLASH->CFCR = (((HT_FLASH->CFCR) & ~7UL) | 2UL); /* auto-select wait state */ + #endif +#else + HT_FLASH->CFCR = (((HT_FLASH->CFCR) & ~7UL) | (WAIT_STATE + 1)); /* manual wait state */ +#endif + + HT_CKCU->AHBCFGR = HCLK_DIV; /* set CK_AHB prescaler */ + HT_CKCU->GCCR = ((HT_CKCU->GCCR & ~7UL) | HCLK_SRC); /* select CK_SYS source */ + while ((HT_CKCU->CKST & 7UL) != HCLK_SRC); /* wait for clock switch complete */ + + /* Pre-fetch buffer configuration */ +#if (PRE_FETCH_ENABLE == 0) + ResetBit_BB((u32)(&HT_FLASH->CFCR), 4); /* 0: pre-fetch disable, 1: pre-fetch enable */ +#else + SetBit_BB((u32)(&HT_FLASH->CFCR), 4); /* 0: pre-fetch disable, 1: pre-fetch enable */ +#endif + + /* Branch cache configuration */ +#if (BCACHE_ENABLE == 0) + ResetBit_BB((u32)(&HT_FLASH->CFCR), 12); /* 0: branch cache disable, 1: branch cache enable */ +#else + SetBit_BB((u32)(&HT_FLASH->CFCR), 12); /* 0: branch cache disable, 1: branch cache enable */ +#endif + + /* HSE power down */ +#if ((HSE_ENABLE == 0) && (HCLK_SRC != 2) && ((PLL_ENABLE == 0) || (PLL_CLK_SRC == 1))) + ResetBit_BB((u32)(&HT_CKCU->GCCR), 10); +#endif + + /* HSI power down */ +#if ((HSI_ENABLE == 0) && (HCLK_SRC != 3) && ((PLL_ENABLE == 0) || (PLL_CLK_SRC == 0))) + ResetBit_BB((u32)(&HT_CKCU->GCCR), 11); +#endif +} + +/** + * @brief Update SystemCoreClock + * @retval None + */ +void SystemCoreClockUpdate(void) +{ + u32 SystemCoreClockDiv = HT_CKCU->AHBCFGR & 7UL; + u32 PllFeedbackClockDiv = ((HT_CKCU->PLLCFGR >> 23) == 0) ? (16) : (HT_CKCU->PLLCFGR >> 23); + u32 PllOutputClockDiv = (HT_CKCU->PLLCFGR >> 21) & 3UL; + u32 SystemCoreClockSrc = HT_CKCU->CKST & 7UL; + + /* Get system core clock according to global clock control & configuration registers */ + if (SystemCoreClockSrc == 1) + { + if (GetBit_BB((u32)(&HT_CKCU->PLLCR), 31)) + { + PllFeedbackClockDiv = 1; + PllOutputClockDiv = 0; + } + + if (GetBit_BB((u32)(&HT_CKCU->GCFGR), 8)) + { + SystemCoreClock = ((HSI_VALUE * PllFeedbackClockDiv) >> PllOutputClockDiv) >> SystemCoreClockDiv; + } + else + { + SystemCoreClock = ((HSE_VALUE * PllFeedbackClockDiv) >> PllOutputClockDiv) >> SystemCoreClockDiv; + } + } + else if (SystemCoreClockSrc == 2) + { + SystemCoreClock = HSE_VALUE >> SystemCoreClockDiv; + } + else if (SystemCoreClockSrc == 3) + { + SystemCoreClock = HSI_VALUE >> SystemCoreClockDiv; + } + else if (SystemCoreClockSrc == 6) + { + SystemCoreClock = LSE_VALUE >> SystemCoreClockDiv; + } + else if (SystemCoreClockSrc == 7) + { + SystemCoreClock = LSI_VALUE >> SystemCoreClockDiv; + } +} + +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ + +/******************* (C) COPYRIGHT Holtek Semiconductor Inc. *****END OF FILE*** */ diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/system_ht32f5826.c b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/system_ht32f5826.c new file mode 100644 index 0000000000..9e59781925 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/system_ht32f5826.c @@ -0,0 +1,508 @@ +/**************************************************************************//** + * @file library/Device/Holtek/HT32F5xxxx/Source/system_ht32f5826.c + * @brief CMSIS Cortex-M0+ Device Peripheral Access Layer Source File + * for the Holtek HT32F5xxxx Device Series + * @version $Rev:: 6597 $ + * @date $Date:: 2022-12-27 #$ + * + * @note + * Copyright (C) Holtek Semiconductor Inc. All rights reserved. + * + * @par + * ARM Limited (ARM) supplies this software for Cortex-M processor-based + * microcontrollers. This file can be freely distributed within development + * tools that are supporting such ARM based processors. + * + * @par + * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR + * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + ******************************************************************************/ + +// Supported Device +// ======================================== +// HT32F5826 + +//#define USE_HT32F5826 + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup HT32F5xxxx_system HT32F5xxxx System + * @{ + */ + + +#include "ht32f5xxxx_01.h" + +/** @addtogroup HT32F5xxxx_System_Private_Defines + * @{ + */ +/* +//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ +*/ + +/*--------------------- Clock Configuration ---------------------------------- +// +// Enable High Speed External Crystal Oscillator (HSE) +// Default HSE = DISABLE +// +// Enable Low Speed External Crystal Oscillator (LSE) +// Default LSE = DISABLE +// Not apply to HT32F52220/30 +// +// Enable PLL +// Default PLL = DISABLE +// PLL Out = ((HSE or HSI) x NF2 ) / NO2 +// PLL Clock Source +// <0=> CK_HSE +// <1=> CK_HSI +// Default PLL clock source = CK_HSI +// PLL source clock must be in the range of 4 MHz to 16 MHz +// PLL Feedback Clock Divider (NF2): 1 ~ 16 +// <1-16:1> +// PLL feedback clock = PLL clock source x NF2 +// PLL feedback clock must be in the range of 24 MHz to 48 MHz +// PLL Output Clock Divider (NO2) +// <0=> 1 +// <1=> 2 +// <2=> 4 +// <3=> 8 +// PLL output clock = PLL feedback clock / NO2 +// PLL output clock must be in the range of 4 MHz to 48 MHz +// +// +// SystemCoreClock Configuration (CK_AHB) +// SystemCoreClock Source +// <1=> CK_PLL +// <2=> CK_HSE +// <3=> CK_HSI +// <6=> CK_LSE (Not apply to HT32F52220/30) +// <7=> CK_LSI +// Default SystemCoreClock source = CK_HSI +// SystemCoreClock Source Divider +// <0=> 1 +// <1=> 2 +// <2=> 4 +// <3=> 8 +// <4=> 16 +// <5=> 32 +// Default SystemCoreClock source divider = 1 +// +// +// FLASH Configuration +// Wait state +// <0=> 0 WS +// <1=> 1 WS +// <9=> AUTO +// HT32F52331/41/42/52, HT32F5826 +// 0 WS: 1 kHz <= CK_AHB <= 24 MHz +// 1 WS: 24 MHz < CK_AHB <= 48 MHz +// HT32F52220/30/31/41/43/53 +// 0 WS: 1 kHz <= CK_AHB <= 20 MHz +// 1 WS: 20 MHz < CK_AHB <= 40 MHz +// Pre-fetch Buffer Enable +// Default pre-fetch buffer = ENABLE +// Branch cache Enable (HT3F52342/52, HT32F5826 Only) +// Default branch cache = ENABLE +// +*/ + +/* !!! NOTICE !!! + HSI must keep turn on when doing the Flash operation (Erase/Program). +*/ + +/* !!! NOTICE !!! + * How to adjust the value of High Speed External oscillator (HSE)? + The default value of HSE is define by "HSE_VALUE" in "ht32fxxxxx_nn.h". + If your board uses a different HSE speed, please add a new compiler preprocessor + C define, "HSE_VALUE=n000000" ("n" represents n MHz) in the toolchain/IDE, + or edit the "HSE_VALUE" in the "ht32f5xxxx_conf.h" file. + Take Keil MDK-ARM for instance, to set HSE as 16 MHz: + "Option of Taret -> C/C++ > Preprocessor Symbols" + Define: USE_HT32_DRIVER, USE_HT32Fxxxxx_SK, USE_HT32Fxxxxx_xx, USE_MEM_HT32Fxxxxx, HSE_VALUE=16000000 + ^^ Add "HSE_VALUE" + define as above. +*/ +#define HSI_ENABLE (1) /*!< 0: DISABLE, 1: ENABLE */ +#define HSE_ENABLE (1) /*!< 0: DISABLE, 1: ENABLE */ +#define LSI_ENABLE (1) /*!< 0: DISABLE, 1: ENABLE */ +#define LSE_ENABLE (0) /*!< 0: DISABLE, 1: ENABLE */ +#define PLL_ENABLE (1) /*!< 0: DISABLE, 1: ENABLE */ +#define PLL_CLK_SRC (0) /*!< 0: HSE, 1: HSI */ +#define PLL_NF2_DIV (6) /*!< 1~16: DIV1~DIV16 */ +#define PLL_NO2_DIV (0) /*!< 0: DIV1, 1: DIV2, 2: DIV4, 3: DIV8 */ +#define HCLK_SRC (1) /*!< 0: PLL, 1: PLL, 2: HSE, 3: HSI 6: LSE, 7: LSI */ +#define HCLK_DIV (0) /*!< 0: DIV1, 1: DIV2, 2: DIV4, 3: DIV8, 4: DIV16, 5: DIV32 */ +#define WAIT_STATE (9) /*!< 0: WS = 0, 1: WS = 1, 9: WS = AUTO */ +#define PRE_FETCH_ENABLE (1) /*!< 0: DISABLE, 1: ENABLE */ +#define BCACHE_ENABLE (1) /*!< 0: DISABLE, 1: ENABLE */ +#define DEINIT_ENABLE (1) /* Set 0 for reduce code size */ + +/*----------------------------------------------------------------------------------------------------------*/ +/* PLL Out = ((HSE or HSI) x PLL_NF2) / PLL_NO2 */ +/*----------------------------------------------------------------------------------------------------------*/ + + +/*--------------------- WDT Configuration ---------------------------------- +// +// Enable WDT Configuration +// WDT Prescaler Selection +// <0=> CK_WDT / 1 +// <1=> CK_WDT / 2 +// <2=> CK_WDT / 4 +// <3=> CK_WDT / 8 +// <4=> CK_WDT / 16 +// <5=> CK_WDT / 32 +// <6=> CK_WDT / 64 +// <7=> CK_WDT / 128 +// WDT Reload Value <1-4095:1> +// Enable WDT Reset function +// WDT Sleep Halt mode +// <0=> No halt +// <1=> Halt in DeepSleep1 +// <2=> Halt in Sleep & DeepSleep1 +// +*/ +#define WDT_ENABLE (0) /*!< 0: DISABLE, 1: ENABLE */ +#define WDT_PRESCALER (5) /*!< 0: 1/1, 1: 1/2, 2: 1/4, 3: 1/8, 4: 1/16, 5: 1/32, 6: 1/64, 7: 1/128 */ +#define WDT_RELOAD (2000) /*!< 0 ~ 4095, 12 bit */ +#define WDT_RESET_ENABLE (1) /*!< 0: No Reset, 1: Reset when WDT over flow */ +#define WDT_SLEEP_HALT (2) /*!< 0: No halt, 1: Halt in DeepSleep1, 2: Halt in Sleep & DeepSleep1 */ + +/** + * @brief Check HSI frequency + */ +#if (HSI_VALUE != 8000000UL) + #error "CK_HSI clock issue: must be 8 MHz!" +#endif + +/** + * @brief Check HSE frequency + */ +#if ((HSE_VALUE < 4000000UL) || (HSE_VALUE > 16000000UL)) + #error "CK_HSE clock issue: must be in the range of 4 MHz to 16 MHz!" +#endif + +/** + * @brief Check LSI frequency + */ +#if (LSI_VALUE != 32000UL) + #error "CK_LSI clock issue: must be 32 kHz!" +#endif + +/** + * @brief Check LSE frequency + */ +#if !defined(USE_HT32F52220_30) +#if (LSE_VALUE != 32768UL) + #error "CK_LSE clock issue: must be 32.768 kHz!" +#endif +#endif + +/** + * @brief CK_PLL definition + */ +#if (PLL_ENABLE == 1) + /* Get CK_VCO frequency */ + #if (PLL_CLK_SRC == 1) + #if (HSI_ENABLE == 0) + #error "CK_PLL clock source issue: HSI has not been enabled" + #else + #define __CK_VCO (HSI_VALUE * PLL_NF2_DIV) /*!< Select HSI as PLL source */ + #endif + #else + #if (HSE_ENABLE == 0) + #error "CK_PLL clock source issue: HSE has not been enabled!" + #else + #define __CK_VCO (HSE_VALUE * PLL_NF2_DIV) /*!< Select HSE as PLL source */ + #endif + #endif + + #define VCO_MIN 24000000UL + #define VCO_MAX 48000000UL + #define PLL_MIN 4000000UL + #define PLL_MAX 48000000UL + + /* Check CK_VCO frequency */ + #if ((__CK_VCO < VCO_MIN) || (__CK_VCO > VCO_MAX)) + #error "CK_VCO clock issue: must be in the range!" + #endif + + #define __CK_PLL (__CK_VCO >> PLL_NO2_DIV) /*!< Get CK_PLL frequency */ + + /* Check CK_PLL frequency */ + #if ((__CK_PLL < PLL_MIN) || (__CK_PLL > PLL_MAX)) + #error "CK_PLL clock issue: must be in the range!" + #endif +#endif + +/** + * @brief CK_SYS definition + */ +#if (HCLK_SRC == 1) + #if (PLL_ENABLE == 1) + #define __CK_SYS __CK_PLL /*!< Select PLL as CK_SYS source */ + #else + #error "CK_SYS clock source issue: PLL is not enable!" + #endif +#elif (HCLK_SRC == 2) + #if (HSE_ENABLE == 1) + #define __CK_SYS HSE_VALUE /*!< Select HSE as CK_SYS source */ + #else + #error "CK_SYS clock source issue: HSE is not enable!" + #endif +#elif (HCLK_SRC == 3) + #if (HSI_ENABLE == 1) + #define __CK_SYS HSI_VALUE /*!< Select HSI as CK_SYS source */ + #else + #error "CK_SYS clock source issue: HSI is not enable!" + #endif +#elif (HCLK_SRC == 6) + #ifdef USE_HT32F52220_30 + #error "CK_LSE can not be the source of SystemCoreClock for HT32F52220/30" + #else + #if (LSE_ENABLE == 1) + #define __CK_SYS LSE_VALUE /*!< Select LSE as CK_SYS source */ + #else + #error "CK_SYS clock source issue: LSE is not enable!" + #endif + #endif +#elif (HCLK_SRC == 7) + #if (LSI_ENABLE == 1) + #define __CK_SYS LSI_VALUE /*!< Select LSI as CK_SYS source */ + #else + #error "CK_SYS clock source issue: LSI is not enable!" + #endif +#else + #error "CK_SYS clock source issue: No clock source is selected!" +#endif + +/** + * @brief CK_AHB definition + */ +#define __CK_AHB (__CK_SYS >> HCLK_DIV) /*!< Get CK_AHB frequency */ + +#if defined(USE_HT32F52331_41) || defined(USE_HT32F52342_52) || defined(USE_HT32F5826) + #define CKAHB_MIN 1000UL + #define CKAHB_MAX 48000000UL + #define WS0_CLK 24000000UL +#endif + +#if defined(USE_HT32F52220_30) || defined(USE_HT32F52231_41) || defined(USE_HT32F52243_53) + #define CKAHB_MIN 1000UL + #define CKAHB_MAX 40000000UL + #define WS0_CLK 20000000UL +#endif + +/* Check CK_AHB frequency */ +#if ((__CK_AHB < CKAHB_MIN) || (__CK_AHB > CKAHB_MAX)) + #error "CK_AHB clock issue: must be in the range!" +#endif + +/* Check FLASH wait-state setting */ +#if ((__CK_AHB > WS0_CLK) && (WAIT_STATE < 1)) + #error "FLASH wait state configuration issue!" +#endif +/** + * @} + */ + +/** @addtogroup HT32F5xxxx_System_Private_Variables + * @{ + */ +__IO uint32_t SystemCoreClock = __CK_AHB; /*!< SystemCoreClock = CK_AHB */ +/** + * @} + */ + +/** @addtogroup HT32F5xxxx_System_Private_Functions + * @{ + */ + +/** + * @brief Setup the microcontroller system. + * Initializes the system clocks and the embedded Flash. + * @note This function should be used after reset. + * @retval None + */ +void SystemInit(void) +{ +#if (WDT_ENABLE == 1) + HT_CKCU->APBCCR1 |= (0x1 << 4); + HT_WDT->PR = 0x35CA; + HT_WDT->MR0 = 0; + HT_WDT->MR1 = ((HT_WDT->MR1 & 0xFFF) | (WDT_PRESCALER << 12)); + HT_WDT->MR0 = WDT_RELOAD | (WDT_RESET_ENABLE << 13) | (WDT_SLEEP_HALT << 14) | (0x1 << 16); + HT_WDT->CR = 0x5FA00001; +#else + #if (DEINIT_ENABLE == 1) + HT_RSTCU->APBPRST1 = (1 << 4); + #endif +#endif + + HT_CKCU->LPCR = 1; /* configure Backup domain isolation */ + SetBit_BB((u32)(&HT_CKCU->APBCCR1), 6); /* enable Backup domain register clock */ + while (HT_PWRCU->TEST != 0x27); /* wait for Backup domain register ready */ + + while ((HT_PWRCU->CR & 0x00000200) != 0x00000200) /* Backup domain register access test */ + HT_PWRCU->CR = 0x00000200; + while ((HT_PWRCU->CR & 0x00000200) != 0x00000000) + HT_PWRCU->CR = 0x00000000; + HT_CKCU->LPCR = 0; + + #if (DEINIT_ENABLE == 1) + /* De-init the setting */ + HT_CKCU->AHBCCR &= ~(0x3 << 10); /* disable IP who may use PLL as source */ + SetBit_BB((u32)(&HT_CKCU->GCCR), 11); /* enable HSI */ + while (!GetBit_BB((u32)(&HT_CKCU->GCSR), 3)); /* wait for HSI ready */ + HT_CKCU->GCCR = ((HT_CKCU->GCCR & ~7UL) | 3UL); /* select CK_SYS source */ + while ((HT_CKCU->CKST & 7UL) != 3UL); /* wait for clock switch complete */ + HT_FLASH->CFCR = (((HT_FLASH->CFCR) & ~7UL) | 1UL); /* set Wait State as 0 WS */ + HT_CKCU->AHBCFGR = 0; /* set CK_AHB prescaler */ + ResetBit_BB((u32)(&HT_CKCU->GCCR), 9); /* disable PLL */ + SetBit_BB((u32)(&HT_CKCU->GCFGR), 8); /* select PLL source as HSI */ + #endif + + /* HSE initiation */ +#if (HSE_ENABLE == 1) + SetBit_BB((u32)(&HT_CKCU->GCCR), 10); /* enable HSE */ + while (!GetBit_BB((u32)(&HT_CKCU->GCSR), 2)){}; /* wait for HSE ready */ +#endif + + /* LSE initiation */ +#if !defined(USE_HT32F52220_30) +#if (LSE_ENABLE == 1) + do { + SetBit_BB((u32)(&HT_RTC->CR), 3); /* enable LSE */ + } while (!GetBit_BB((u32)(&HT_RTC->CR), 3)); + while (!GetBit_BB((u32)(&HT_CKCU->GCSR), 4)); /* wait for LSE ready */ +#endif +#endif + + ResetBit_BB((u32)(&HT_CKCU->APBCCR1), 6); /* disable Backup domain register clock */ + + /* LSI initiation */ +#if (HCLK_SRC == 7) + while (!GetBit_BB((u32)(&HT_CKCU->GCSR), 5)){}; /* wait for LSI ready */ +#endif + + /* PLL initiation */ +#if (PLL_ENABLE == 1) + #if (PLL_CLK_SRC == 0) + ResetBit_BB((u32)(&HT_CKCU->GCFGR), 8); /* select PLL source as HSE */ + #else + SetBit_BB((u32)(&HT_CKCU->GCFGR), 8); /* select PLL source as HSI */ + #endif + HT_CKCU->PLLCFGR = ((PLL_NF2_DIV & 0x0F) << 23) | (PLL_NO2_DIV << 21); /* set PLL divider */ + SetBit_BB((u32)(&HT_CKCU->GCCR), 9); /* enable PLL */ + while (!GetBit_BB((u32)(&HT_CKCU->GCSR), 1)){}; /* wait for PLL ready */ +#endif + + /* CK_AHB initiation */ +#if (WAIT_STATE == 9) + #if (__CK_AHB > WS0_CLK) + HT_FLASH->CFCR = (((HT_FLASH->CFCR) & ~7UL) | 2UL); /* auto-select wait state */ + #endif +#else + HT_FLASH->CFCR = (((HT_FLASH->CFCR) & ~7UL) | (WAIT_STATE + 1)); /* manual wait state */ +#endif + + HT_CKCU->AHBCFGR = HCLK_DIV; /* set CK_AHB prescaler */ + HT_CKCU->GCCR = ((HT_CKCU->GCCR & ~7UL) | HCLK_SRC); /* select CK_SYS source */ + while ((HT_CKCU->CKST & 7UL) != HCLK_SRC); /* wait for clock switch complete */ + + /* Pre-fetch buffer configuration */ +#if (PRE_FETCH_ENABLE == 0) + ResetBit_BB((u32)(&HT_FLASH->CFCR), 4); /* 0: pre-fetch disable, 1: pre-fetch enable */ +#else + SetBit_BB((u32)(&HT_FLASH->CFCR), 4); /* 0: pre-fetch disable, 1: pre-fetch enable */ +#endif + + /* Branch cache configuration */ +#if defined(USE_HT32F52342_52) || defined(USE_HT32F5826) +#if (BCACHE_ENABLE == 0) + ResetBit_BB((u32)(&HT_FLASH->CFCR), 12); /* 0: branch cache disable, 1: branch cache enable */ +#else + SetBit_BB((u32)(&HT_FLASH->CFCR), 12); /* 0: branch cache disable, 1: branch cache enable */ +#endif +#endif + + /* HSE power down */ +#if ((HSE_ENABLE == 0) && (HCLK_SRC != 2) && ((PLL_ENABLE == 0) || (PLL_CLK_SRC == 1))) + ResetBit_BB((u32)(&HT_CKCU->GCCR), 10); +#endif + + /* HSI power down */ +#if ((HSI_ENABLE == 0) && (HCLK_SRC != 3) && ((PLL_ENABLE == 0) || (PLL_CLK_SRC == 0))) + ResetBit_BB((u32)(&HT_CKCU->GCCR), 11); +#endif +} + +/** + * @brief Update SystemCoreClock + * @retval None + */ +void SystemCoreClockUpdate(void) +{ + u32 SystemCoreClockDiv = HT_CKCU->AHBCFGR & 7UL; + u32 PllFeedbackClockDiv = ((HT_CKCU->PLLCFGR >> 23) == 0) ? (16) : (HT_CKCU->PLLCFGR >> 23); + u32 PllOutputClockDiv = (HT_CKCU->PLLCFGR >> 21) & 3UL; + u32 SystemCoreClockSrc = HT_CKCU->CKST & 7UL; + + /* Get system core clock according to global clock control & configuration registers */ + if (SystemCoreClockSrc == 1) + { + if (GetBit_BB((u32)(&HT_CKCU->PLLCR), 31)) + { + PllFeedbackClockDiv = 1; + PllOutputClockDiv = 0; + } + + if (GetBit_BB((u32)(&HT_CKCU->GCFGR), 8)) + { + SystemCoreClock = ((HSI_VALUE * PllFeedbackClockDiv) >> PllOutputClockDiv) >> SystemCoreClockDiv; + } + else + { + SystemCoreClock = ((HSE_VALUE * PllFeedbackClockDiv) >> PllOutputClockDiv) >> SystemCoreClockDiv; + } + } + else if (SystemCoreClockSrc == 2) + { + SystemCoreClock = HSE_VALUE >> SystemCoreClockDiv; + } + else if (SystemCoreClockSrc == 3) + { + SystemCoreClock = HSI_VALUE >> SystemCoreClockDiv; + } + #ifndef USE_HT32F52220_30 + else if (SystemCoreClockSrc == 6) + { + SystemCoreClock = LSE_VALUE >> SystemCoreClockDiv; + } + #endif + else if (SystemCoreClockSrc == 7) + { + SystemCoreClock = LSI_VALUE >> SystemCoreClockDiv; + } +} + +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ + +/******************* (C) COPYRIGHT Holtek Semiconductor Inc. *****END OF FILE*** */ diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/system_ht32f5xxxx_01.c b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/system_ht32f5xxxx_01.c new file mode 100644 index 0000000000..e6f4c361e5 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/system_ht32f5xxxx_01.c @@ -0,0 +1,518 @@ +/**************************************************************************//** + * @file library/Device/Holtek/HT32F5xxxx/Source/system_ht32f5xxxx_01.c + * @brief CMSIS Cortex-M0+ Device Peripheral Access Layer Source File + * for the Holtek HT32F5xxxx Device Series + * @version $Rev:: 6597 $ + * @date $Date:: 2022-12-27 #$ + * + * @note + * Copyright (C) Holtek Semiconductor Inc. All rights reserved. + * + * @par + * ARM Limited (ARM) supplies this software for Cortex-M processor-based + * microcontrollers. This file can be freely distributed within development + * tools that are supporting such ARM based processors. + * + * @par + * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR + * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + ******************************************************************************/ + +// Supported Device +// ======================================== +// HT32F52220, HT32F52230 +// HT32F52231, HT32F52241 +// HT32F52331, HT32F52341 +// HT32F52342, HT32F52352 +// HT32F52243, HT32F52253 +// HT50F32003 + +//#define USE_HT32F52220_30 +//#define USE_HT32F52231_41 +//#define USE_HT32F52331_41 +//#define USE_HT32F52342_52 +//#define USE_HT32F52243_53 +//#define USE_HT50F32003 + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup HT32F5xxxx_system HT32F5xxxx System + * @{ + */ + + +#include "ht32f5xxxx_01.h" + +/** @addtogroup HT32F5xxxx_System_Private_Defines + * @{ + */ +/* +//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ +*/ + +/*--------------------- Clock Configuration ---------------------------------- +// +// Enable High Speed External Crystal Oscillator (HSE) +// Default HSE = DISABLE +// +// Enable Low Speed External Crystal Oscillator (LSE) +// Default LSE = DISABLE +// Not apply to HT32F52220/30 +// +// Enable PLL +// Default PLL = DISABLE +// PLL Out = ((HSE or HSI) x NF2 ) / NO2 +// PLL Clock Source +// <0=> CK_HSE +// <1=> CK_HSI +// Default PLL clock source = CK_HSI +// PLL source clock must be in the range of 4 MHz to 16 MHz +// PLL Feedback Clock Divider (NF2): 1 ~ 16 +// <1-16:1> +// PLL feedback clock = PLL clock source x NF2 +// PLL feedback clock must be in the range of 24 MHz to 48 MHz +// PLL Output Clock Divider (NO2) +// <0=> 1 +// <1=> 2 +// <2=> 4 +// <3=> 8 +// PLL output clock = PLL feedback clock / NO2 +// PLL output clock must be in the range of 4 MHz to 48 MHz +// +// +// SystemCoreClock Configuration (CK_AHB) +// SystemCoreClock Source +// <1=> CK_PLL +// <2=> CK_HSE +// <3=> CK_HSI +// <6=> CK_LSE (Not apply to HT32F52220/30) +// <7=> CK_LSI +// Default SystemCoreClock source = CK_HSI +// SystemCoreClock Source Divider +// <0=> 1 +// <1=> 2 +// <2=> 4 +// <3=> 8 +// <4=> 16 +// <5=> 32 +// Default SystemCoreClock source divider = 1 +// +// +// FLASH Configuration +// Wait state +// <0=> 0 WS +// <1=> 1 WS +// <9=> AUTO +// HT32F52331/41/42/52 +// 0 WS: 1 kHz <= CK_AHB <= 24 MHz +// 1 WS: 24 MHz < CK_AHB <= 48 MHz +// HT32F52220/30/31/41/43/53 +// 0 WS: 1 kHz <= CK_AHB <= 20 MHz +// 1 WS: 20 MHz < CK_AHB <= 40 MHz +// Pre-fetch Buffer Enable +// Default pre-fetch buffer = ENABLE +// Branch cache Enable (HT3F52342/52 Only) +// Default branch cache = ENABLE +// +*/ + +/* !!! NOTICE !!! + HSI must keep turn on when doing the Flash operation (Erase/Program). +*/ + +/* !!! NOTICE !!! + * How to adjust the value of High Speed External oscillator (HSE)? + The default value of HSE is define by "HSE_VALUE" in "ht32fxxxxx_nn.h". + If your board uses a different HSE speed, please add a new compiler preprocessor + C define, "HSE_VALUE=n000000" ("n" represents n MHz) in the toolchain/IDE, + or edit the "HSE_VALUE" in the "ht32f5xxxx_conf.h" file. + Take Keil MDK-ARM for instance, to set HSE as 16 MHz: + "Option of Taret -> C/C++ > Preprocessor Symbols" + Define: USE_HT32_DRIVER, USE_HT32Fxxxxx_SK, USE_HT32Fxxxxx_xx, USE_MEM_HT32Fxxxxx, HSE_VALUE=16000000 + ^^ Add "HSE_VALUE" + define as above. +*/ +#define HSI_ENABLE (1) /*!< 0: DISABLE, 1: ENABLE */ +#define HSE_ENABLE (1) /*!< 0: DISABLE, 1: ENABLE */ +#define LSI_ENABLE (1) /*!< 0: DISABLE, 1: ENABLE */ +#define LSE_ENABLE (0) /*!< 0: DISABLE, 1: ENABLE */ +#define PLL_ENABLE (1) /*!< 0: DISABLE, 1: ENABLE */ +#define PLL_CLK_SRC (0) /*!< 0: HSE, 1: HSI */ +#define PLL_NF2_DIV (6) /*!< 1~16: DIV1~DIV16 */ +#define PLL_NO2_DIV (0) /*!< 0: DIV1, 1: DIV2, 2: DIV4, 3: DIV8 */ +#define HCLK_SRC (1) /*!< 0: PLL, 1: PLL, 2: HSE, 3: HSI 6: LSE, 7: LSI */ +#define HCLK_DIV (0) /*!< 0: DIV1, 1: DIV2, 2: DIV4, 3: DIV8, 4: DIV16, 5: DIV32 */ +#define WAIT_STATE (9) /*!< 0: WS = 0, 1: WS = 1, 9: WS = AUTO */ +#define PRE_FETCH_ENABLE (1) /*!< 0: DISABLE, 1: ENABLE */ +#define BCACHE_ENABLE (1) /*!< 0: DISABLE, 1: ENABLE */ +#define DEINIT_ENABLE (1) /* Set 0 for reduce code size */ + +/*----------------------------------------------------------------------------------------------------------*/ +/* PLL Out = ((HSE or HSI) x PLL_NF2) / PLL_NO2 */ +/*----------------------------------------------------------------------------------------------------------*/ + + +/*--------------------- WDT Configuration ---------------------------------- +// +// Enable WDT Configuration +// WDT Prescaler Selection +// <0=> CK_WDT / 1 +// <1=> CK_WDT / 2 +// <2=> CK_WDT / 4 +// <3=> CK_WDT / 8 +// <4=> CK_WDT / 16 +// <5=> CK_WDT / 32 +// <6=> CK_WDT / 64 +// <7=> CK_WDT / 128 +// WDT Reload Value <1-4095:1> +// Enable WDT Reset function +// WDT Sleep Halt mode +// <0=> No halt +// <1=> Halt in DeepSleep1 +// <2=> Halt in Sleep & DeepSleep1 +// +*/ +#define WDT_ENABLE (0) /*!< 0: DISABLE, 1: ENABLE */ +#define WDT_PRESCALER (5) /*!< 0: 1/1, 1: 1/2, 2: 1/4, 3: 1/8, 4: 1/16, 5: 1/32, 6: 1/64, 7: 1/128 */ +#define WDT_RELOAD (2000) /*!< 0 ~ 4095, 12 bit */ +#define WDT_RESET_ENABLE (1) /*!< 0: No Reset, 1: Reset when WDT over flow */ +#define WDT_SLEEP_HALT (2) /*!< 0: No halt, 1: Halt in DeepSleep1, 2: Halt in Sleep & DeepSleep1 */ + +/** + * @brief Check HSI frequency + */ +#if (HSI_VALUE != 8000000UL) + #error "CK_HSI clock issue: must be 8 MHz!" +#endif + +/** + * @brief Check HSE frequency + */ +#if ((HSE_VALUE < 4000000UL) || (HSE_VALUE > 16000000UL)) + #error "CK_HSE clock issue: must be in the range of 4 MHz to 16 MHz!" +#endif + +/** + * @brief Check LSI frequency + */ +#if (LSI_VALUE != 32000UL) + #error "CK_LSI clock issue: must be 32 kHz!" +#endif + +/** + * @brief Check LSE frequency + */ +#if !defined(USE_HT32F52220_30) +#if (LSE_VALUE != 32768UL) + #error "CK_LSE clock issue: must be 32.768 kHz!" +#endif +#endif + +/** + * @brief CK_PLL definition + */ +#if (PLL_ENABLE == 1) + /* Get CK_VCO frequency */ + #if (PLL_CLK_SRC == 1) + #if (HSI_ENABLE == 0) + #error "CK_PLL clock source issue: HSI has not been enabled" + #else + #define __CK_VCO (HSI_VALUE * PLL_NF2_DIV) /*!< Select HSI as PLL source */ + #endif + #else + #if (HSE_ENABLE == 0) + #error "CK_PLL clock source issue: HSE has not been enabled!" + #else + #define __CK_VCO (HSE_VALUE * PLL_NF2_DIV) /*!< Select HSE as PLL source */ + #endif + #endif + + #define VCO_MIN 24000000UL + #define VCO_MAX 48000000UL + #define PLL_MIN 4000000UL + #define PLL_MAX 48000000UL + + /* Check CK_VCO frequency */ + #if ((__CK_VCO < VCO_MIN) || (__CK_VCO > VCO_MAX)) + #error "CK_VCO clock issue: must be in the range!" + #endif + + #define __CK_PLL (__CK_VCO >> PLL_NO2_DIV) /*!< Get CK_PLL frequency */ + + /* Check CK_PLL frequency */ + #if ((__CK_PLL < PLL_MIN) || (__CK_PLL > PLL_MAX)) + #error "CK_PLL clock issue: must be in the range!" + #endif +#endif + +/** + * @brief CK_SYS definition + */ +#if (HCLK_SRC == 1) + #if (PLL_ENABLE == 1) + #define __CK_SYS __CK_PLL /*!< Select PLL as CK_SYS source */ + #else + #error "CK_SYS clock source issue: PLL is not enable!" + #endif +#elif (HCLK_SRC == 2) + #if (HSE_ENABLE == 1) + #define __CK_SYS HSE_VALUE /*!< Select HSE as CK_SYS source */ + #else + #error "CK_SYS clock source issue: HSE is not enable!" + #endif +#elif (HCLK_SRC == 3) + #if (HSI_ENABLE == 1) + #define __CK_SYS HSI_VALUE /*!< Select HSI as CK_SYS source */ + #else + #error "CK_SYS clock source issue: HSI is not enable!" + #endif +#elif (HCLK_SRC == 6) + #ifdef USE_HT32F52220_30 + #error "CK_LSE can not be the source of SystemCoreClock for HT32F52220/30" + #else + #if (LSE_ENABLE == 1) + #define __CK_SYS LSE_VALUE /*!< Select LSE as CK_SYS source */ + #else + #error "CK_SYS clock source issue: LSE is not enable!" + #endif + #endif +#elif (HCLK_SRC == 7) + #if (LSI_ENABLE == 1) + #define __CK_SYS LSI_VALUE /*!< Select LSI as CK_SYS source */ + #else + #error "CK_SYS clock source issue: LSI is not enable!" + #endif +#else + #error "CK_SYS clock source issue: No clock source is selected!" +#endif + +/** + * @brief CK_AHB definition + */ +#define __CK_AHB (__CK_SYS >> HCLK_DIV) /*!< Get CK_AHB frequency */ + +#if defined(USE_HT32F52331_41) || defined(USE_HT32F52342_52) + #define CKAHB_MIN 1000UL + #define CKAHB_MAX 48000000UL + #define WS0_CLK 24000000UL +#endif + +#if defined(USE_HT32F52220_30) || defined(USE_HT32F52231_41) || defined(USE_HT32F52243_53) + #define CKAHB_MIN 1000UL + #define CKAHB_MAX 40000000UL + #define WS0_CLK 20000000UL +#endif + +/* Check CK_AHB frequency */ +#if ((__CK_AHB < CKAHB_MIN) || (__CK_AHB > CKAHB_MAX)) + #error "CK_AHB clock issue: must be in the range!" +#endif + +/* Check FLASH wait-state setting */ +#if ((__CK_AHB > WS0_CLK) && (WAIT_STATE < 1)) + #error "FLASH wait state configuration issue!" +#endif +/** + * @} + */ + +/** @addtogroup HT32F5xxxx_System_Private_Variables + * @{ + */ +__IO uint32_t SystemCoreClock = __CK_AHB; /*!< SystemCoreClock = CK_AHB */ +/** + * @} + */ + +/** @addtogroup HT32F5xxxx_System_Private_Functions + * @{ + */ + +/** + * @brief Setup the microcontroller system. + * Initializes the system clocks and the embedded Flash. + * @note This function should be used after reset. + * @retval None + */ +void SystemInit(void) +{ +#if (WDT_ENABLE == 1) + HT_CKCU->APBCCR1 |= (0x1 << 4); + HT_WDT->PR = 0x35CA; + HT_WDT->MR0 = 0; + HT_WDT->MR1 = ((HT_WDT->MR1 & 0xFFF) | (WDT_PRESCALER << 12)); + HT_WDT->MR0 = WDT_RELOAD | (WDT_RESET_ENABLE << 13) | (WDT_SLEEP_HALT << 14) | (0x1 << 16); + HT_WDT->CR = 0x5FA00001; +#else + #if (DEINIT_ENABLE == 1) + HT_RSTCU->APBPRST1 = (1 << 4); + #endif +#endif + + HT_CKCU->LPCR = 1; /* configure Backup domain isolation */ + SetBit_BB((u32)(&HT_CKCU->APBCCR1), 6); /* enable Backup domain register clock */ + while (HT_PWRCU->TEST != 0x27); /* wait for Backup domain register ready */ + + while ((HT_PWRCU->CR & 0x00000200) != 0x00000200) /* Backup domain register access test */ + HT_PWRCU->CR = 0x00000200; + while ((HT_PWRCU->CR & 0x00000200) != 0x00000000) + HT_PWRCU->CR = 0x00000000; + HT_CKCU->LPCR = 0; + + #if (DEINIT_ENABLE == 1) + /* De-init the setting */ + HT_CKCU->AHBCCR &= ~(0x3 << 10); /* disable IP who may use PLL as source */ + SetBit_BB((u32)(&HT_CKCU->GCCR), 11); /* enable HSI */ + while (!GetBit_BB((u32)(&HT_CKCU->GCSR), 3)); /* wait for HSI ready */ + HT_CKCU->GCCR = ((HT_CKCU->GCCR & ~7UL) | 3UL); /* select CK_SYS source */ + while ((HT_CKCU->CKST & 7UL) != 3UL); /* wait for clock switch complete */ + HT_FLASH->CFCR = (((HT_FLASH->CFCR) & ~7UL) | 1UL); /* set Wait State as 0 WS */ + HT_CKCU->AHBCFGR = 0; /* set CK_AHB prescaler */ + ResetBit_BB((u32)(&HT_CKCU->GCCR), 9); /* disable PLL */ + SetBit_BB((u32)(&HT_CKCU->GCFGR), 8); /* select PLL source as HSI */ + #endif + + /* HSE initiation */ +#if (HSE_ENABLE == 1) + SetBit_BB((u32)(&HT_CKCU->GCCR), 10); /* enable HSE */ + while (!GetBit_BB((u32)(&HT_CKCU->GCSR), 2)){}; /* wait for HSE ready */ +#endif + + /* LSE initiation */ +#if !defined(USE_HT32F52220_30) +#if (LSE_ENABLE == 1) + do { + SetBit_BB((u32)(&HT_RTC->CR), 3); /* enable LSE */ + } while (!GetBit_BB((u32)(&HT_RTC->CR), 3)); + while (!GetBit_BB((u32)(&HT_CKCU->GCSR), 4)); /* wait for LSE ready */ +#endif +#endif + + ResetBit_BB((u32)(&HT_CKCU->APBCCR1), 6); /* disable Backup domain register clock */ + + /* LSI initiation */ +#if (HCLK_SRC == 7) + while (!GetBit_BB((u32)(&HT_CKCU->GCSR), 5)){}; /* wait for LSI ready */ +#endif + + /* PLL initiation */ +#if (PLL_ENABLE == 1) + #if (PLL_CLK_SRC == 0) + ResetBit_BB((u32)(&HT_CKCU->GCFGR), 8); /* select PLL source as HSE */ + #else + SetBit_BB((u32)(&HT_CKCU->GCFGR), 8); /* select PLL source as HSI */ + #endif + HT_CKCU->PLLCFGR = ((PLL_NF2_DIV & 0x0F) << 23) | (PLL_NO2_DIV << 21); /* set PLL divider */ + SetBit_BB((u32)(&HT_CKCU->GCCR), 9); /* enable PLL */ + while (!GetBit_BB((u32)(&HT_CKCU->GCSR), 1)){}; /* wait for PLL ready */ +#endif + + /* CK_AHB initiation */ +#if (WAIT_STATE == 9) + #if (__CK_AHB > WS0_CLK) + HT_FLASH->CFCR = (((HT_FLASH->CFCR) & ~7UL) | 2UL); /* auto-select wait state */ + #endif +#else + HT_FLASH->CFCR = (((HT_FLASH->CFCR) & ~7UL) | (WAIT_STATE + 1)); /* manual wait state */ +#endif + + HT_CKCU->AHBCFGR = HCLK_DIV; /* set CK_AHB prescaler */ + HT_CKCU->GCCR = ((HT_CKCU->GCCR & ~7UL) | HCLK_SRC); /* select CK_SYS source */ + while ((HT_CKCU->CKST & 7UL) != HCLK_SRC); /* wait for clock switch complete */ + + /* Pre-fetch buffer configuration */ +#if (PRE_FETCH_ENABLE == 0) + ResetBit_BB((u32)(&HT_FLASH->CFCR), 4); /* 0: pre-fetch disable, 1: pre-fetch enable */ +#else + SetBit_BB((u32)(&HT_FLASH->CFCR), 4); /* 0: pre-fetch disable, 1: pre-fetch enable */ +#endif + + /* Branch cache configuration */ +#ifdef USE_HT32F52342_52 +#if (BCACHE_ENABLE == 0) + ResetBit_BB((u32)(&HT_FLASH->CFCR), 12); /* 0: branch cache disable, 1: branch cache enable */ +#else + SetBit_BB((u32)(&HT_FLASH->CFCR), 12); /* 0: branch cache disable, 1: branch cache enable */ +#endif +#endif + + /* HSE power down */ +#if ((HSE_ENABLE == 0) && (HCLK_SRC != 2) && ((PLL_ENABLE == 0) || (PLL_CLK_SRC == 1))) + ResetBit_BB((u32)(&HT_CKCU->GCCR), 10); +#endif + + /* HSI power down */ +#if ((HSI_ENABLE == 0) && (HCLK_SRC != 3) && ((PLL_ENABLE == 0) || (PLL_CLK_SRC == 0))) + ResetBit_BB((u32)(&HT_CKCU->GCCR), 11); +#endif +} + +/** + * @brief Update SystemCoreClock + * @retval None + */ +void SystemCoreClockUpdate(void) +{ + u32 SystemCoreClockDiv = HT_CKCU->AHBCFGR & 7UL; + u32 PllFeedbackClockDiv = ((HT_CKCU->PLLCFGR >> 23) == 0) ? (16) : (HT_CKCU->PLLCFGR >> 23); + u32 PllOutputClockDiv = (HT_CKCU->PLLCFGR >> 21) & 3UL; + u32 SystemCoreClockSrc = HT_CKCU->CKST & 7UL; + + /* Get system core clock according to global clock control & configuration registers */ + if (SystemCoreClockSrc == 1) + { + if (GetBit_BB((u32)(&HT_CKCU->PLLCR), 31)) + { + PllFeedbackClockDiv = 1; + PllOutputClockDiv = 0; + } + + if (GetBit_BB((u32)(&HT_CKCU->GCFGR), 8)) + { + SystemCoreClock = ((HSI_VALUE * PllFeedbackClockDiv) >> PllOutputClockDiv) >> SystemCoreClockDiv; + } + else + { + SystemCoreClock = ((HSE_VALUE * PllFeedbackClockDiv) >> PllOutputClockDiv) >> SystemCoreClockDiv; + } + } + else if (SystemCoreClockSrc == 2) + { + SystemCoreClock = HSE_VALUE >> SystemCoreClockDiv; + } + else if (SystemCoreClockSrc == 3) + { + SystemCoreClock = HSI_VALUE >> SystemCoreClockDiv; + } + #ifndef USE_HT32F52220_30 + else if (SystemCoreClockSrc == 6) + { + SystemCoreClock = LSE_VALUE >> SystemCoreClockDiv; + } + #endif + else if (SystemCoreClockSrc == 7) + { + SystemCoreClock = LSI_VALUE >> SystemCoreClockDiv; + } +} + +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ + +/******************* (C) COPYRIGHT Holtek Semiconductor Inc. *****END OF FILE*** */ diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/system_ht32f5xxxx_02.c b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/system_ht32f5xxxx_02.c new file mode 100644 index 0000000000..f864735544 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/system_ht32f5xxxx_02.c @@ -0,0 +1,525 @@ +/**************************************************************************//** + * @file library/Device/Holtek/HT32F5xxxx/Source/system_ht32f5xxxx_02.c + * @brief CMSIS Cortex-M0+ Device Peripheral Access Layer Source File + * for the Holtek HT32F5xxxx Device Series + * @version $Rev:: 6953 $ + * @date $Date:: 2023-05-30 #$ + * + * @note + * Copyright (C) Holtek Semiconductor Inc. All rights reserved. + * + * @par + * ARM Limited (ARM) supplies this software for Cortex-M processor-based + * microcontrollers. This file can be freely distributed within development + * tools that are supporting such ARM based processors. + * + * @par + * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR + * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + ******************************************************************************/ + +// Supported Device +// ======================================== +// HT32F52220, HT32F52230 +// HT32F52231, HT32F52241 +// HT32F52331, HT32F52341 +// HT32F52342, HT32F52352 +// HT32F52243, HT32F52253 +// HT32F62030, HT32F62040, HT32F62050 +// HT32F67232, HT32F67233 +// HT32F67741, + +//#define USE_HT32F52220_30 +//#define USE_HT32F52231_41 +//#define USE_HT32F52331_41 +//#define USE_HT32F52342_52 +//#define USE_HT32F52243_53 +//#define USE_HT32F62030 +//#define USE_HT32F62040 +//#define USE_HT32F62050 +//#define USE_HT32F67232 +//#define USE_HT32F67233 +//#define USE_HT32F67741 + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup HT32F5xxxx_system HT32F5xxxx System + * @{ + */ + + +#include "ht32f5xxxx_01.h" + +/** @addtogroup HT32F5xxxx_System_Private_Defines + * @{ + */ +/* +//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ +*/ + +/*--------------------- Clock Configuration ---------------------------------- +// +// Enable High Speed External Crystal Oscillator (HSE) +// Default HSE = DISABLE +// +// Enable Low Speed External Crystal Oscillator (LSE) +// Default LSE = DISABLE +// Not apply to HT32F52220/30 +// +// Enable PLL +// Default PLL = DISABLE +// PLL Out = ((HSE or HSI) x NF2 ) / NO2 +// PLL Clock Source +// <0=> CK_HSE +// <1=> CK_HSI +// Default PLL clock source = CK_HSI +// PLL source clock must be in the range of 4 MHz to 16 MHz +// PLL Feedback Clock Divider (NF2): 1 ~ 16 +// <1-16:1> +// PLL feedback clock = PLL clock source x NF2 +// PLL feedback clock must be in the range of 24 MHz to 48 MHz +// PLL Output Clock Divider (NO2) +// <0=> 1 +// <1=> 2 +// <2=> 4 +// <3=> 8 +// PLL output clock = PLL feedback clock / NO2 +// PLL output clock must be in the range of 4 MHz to 48 MHz +// +// +// SystemCoreClock Configuration (CK_AHB) +// SystemCoreClock Source +// <1=> CK_PLL +// <2=> CK_HSE +// <3=> CK_HSI +// <6=> CK_LSE (Not apply to HT32F52220/30) +// <7=> CK_LSI +// Default SystemCoreClock source = CK_HSI +// SystemCoreClock Source Divider +// <0=> 1 +// <1=> 2 +// <2=> 4 +// <3=> 8 +// <4=> 16 +// <5=> 32 +// Default SystemCoreClock source divider = 1 +// +// +// FLASH Configuration +// Wait state +// <0=> 0 WS +// <1=> 1 WS +// <9=> AUTO +// HT32F52331/41/42/52 +// 0 WS: 1 kHz <= CK_AHB <= 24 MHz +// 1 WS: 24 MHz < CK_AHB <= 48 MHz +// HT32F52220/30/31/41/43/53 +// 0 WS: 1 kHz <= CK_AHB <= 20 MHz +// 1 WS: 20 MHz < CK_AHB <= 40 MHz +// Pre-fetch Buffer Enable +// Default pre-fetch buffer = ENABLE +// Branch cache Enable (HT3F52342/52 Only) +// Default branch cache = ENABLE +// +*/ + +/* !!! NOTICE !!! + HSI must keep turn on when doing the Flash operation (Erase/Program). +*/ + +/* !!! NOTICE !!! + * How to adjust the value of High Speed External oscillator (HSE)? + The default value of HSE is define by "HSE_VALUE" in "ht32fxxxxx_nn.h". + If your board uses a different HSE speed, please add a new compiler preprocessor + C define, "HSE_VALUE=n000000" ("n" represents n MHz) in the toolchain/IDE, + or edit the "HSE_VALUE" in the "ht32f5xxxx_conf.h" file. + Take Keil MDK-ARM for instance, to set HSE as 16 MHz: + "Option of Taret -> C/C++ > Preprocessor Symbols" + Define: USE_HT32_DRIVER, USE_HT32Fxxxxx_SK, USE_HT32Fxxxxx_xx, USE_MEM_HT32Fxxxxx, HSE_VALUE=16000000 + ^^ Add "HSE_VALUE" + define as above. +*/ +#define HSI_ENABLE (1) /*!< 0: DISABLE, 1: ENABLE */ +#define HSE_ENABLE (1) /*!< 0: DISABLE, 1: ENABLE */ +#define LSI_ENABLE (1) /*!< 0: DISABLE, 1: ENABLE */ +#define LSE_ENABLE (0) /*!< 0: DISABLE, 1: ENABLE */ +#define PLL_ENABLE (1) /*!< 0: DISABLE, 1: ENABLE */ +#define PLL_CLK_SRC (0) /*!< 0: HSE, 1: HSI */ +#define PLL_NF2_DIV (5) /*!< 1~16: DIV1~DIV16 */ +#define PLL_NO2_DIV (0) /*!< 0: DIV1, 1: DIV2, 2: DIV4, 3: DIV8 */ +#define HCLK_SRC (1) /*!< 0: PLL, 1: PLL, 2: HSE, 3: HSI 6: LSE, 7: LSI */ +#define HCLK_DIV (0) /*!< 0: DIV1, 1: DIV2, 2: DIV4, 3: DIV8, 4: DIV16, 5: DIV32 */ +#define WAIT_STATE (9) /*!< 0: WS = 0, 1: WS = 1, 9: WS = AUTO */ +#define PRE_FETCH_ENABLE (1) /*!< 0: DISABLE, 1: ENABLE */ +#define BCACHE_ENABLE (1) /*!< 0: DISABLE, 1: ENABLE */ +#define DEINIT_ENABLE (1) /* Set 0 for reduce code size */ + +/*----------------------------------------------------------------------------------------------------------*/ +/* PLL Out = ((HSE or HSI) x PLL_NF2) / PLL_NO2 */ +/*----------------------------------------------------------------------------------------------------------*/ + + +/*--------------------- WDT Configuration ---------------------------------- +// +// Enable WDT Configuration +// WDT Prescaler Selection +// <0=> CK_WDT / 1 +// <1=> CK_WDT / 2 +// <2=> CK_WDT / 4 +// <3=> CK_WDT / 8 +// <4=> CK_WDT / 16 +// <5=> CK_WDT / 32 +// <6=> CK_WDT / 64 +// <7=> CK_WDT / 128 +// WDT Reload Value <1-4095:1> +// Enable WDT Reset function +// WDT Sleep Halt mode +// <0=> No halt +// <1=> Halt in DeepSleep1 +// <2=> Halt in Sleep & DeepSleep1 +// +*/ +#define WDT_ENABLE (0) /*!< 0: DISABLE, 1: ENABLE */ +#define WDT_PRESCALER (5) /*!< 0: 1/1, 1: 1/2, 2: 1/4, 3: 1/8, 4: 1/16, 5: 1/32, 6: 1/64, 7: 1/128 */ +#define WDT_RELOAD (2000) /*!< 0 ~ 4095, 12 bit */ +#define WDT_RESET_ENABLE (1) /*!< 0: No Reset, 1: Reset when WDT over flow */ +#define WDT_SLEEP_HALT (2) /*!< 0: No halt, 1: Halt in DeepSleep1, 2: Halt in Sleep & DeepSleep1 */ + +/** + * @brief Check HSI frequency + */ +#if (HSI_VALUE != 8000000UL) + #error "CK_HSI clock issue: must be 8 MHz!" +#endif + +/** + * @brief Check HSE frequency + */ +#if ((HSE_VALUE < 4000000UL) || (HSE_VALUE > 16000000UL)) + #error "CK_HSE clock issue: must be in the range of 4 MHz to 16 MHz!" +#endif + +/** + * @brief Check LSI frequency + */ +#if (LSI_VALUE != 32000UL) + #error "CK_LSI clock issue: must be 32 kHz!" +#endif + +/** + * @brief Check LSE frequency + */ +#if !defined(USE_HT32F52220_30) +#if (LSE_VALUE != 32768UL) + #error "CK_LSE clock issue: must be 32.768 kHz!" +#endif +#endif + +/** + * @brief CK_PLL definition + */ +#if (PLL_ENABLE == 1) + /* Get CK_VCO frequency */ + #if (PLL_CLK_SRC == 1) + #if (HSI_ENABLE == 0) + #error "CK_PLL clock source issue: HSI has not been enabled" + #else + #define __CK_VCO (HSI_VALUE * PLL_NF2_DIV) /*!< Select HSI as PLL source */ + #endif + #else + #if (HSE_ENABLE == 0) + #error "CK_PLL clock source issue: HSE has not been enabled!" + #else + #define __CK_VCO (HSE_VALUE * PLL_NF2_DIV) /*!< Select HSE as PLL source */ + #endif + #endif + + #define VCO_MIN 24000000UL + #define VCO_MAX 48000000UL + #define PLL_MIN 4000000UL + #define PLL_MAX 48000000UL + + /* Check CK_VCO frequency */ + #if ((__CK_VCO < VCO_MIN) || (__CK_VCO > VCO_MAX)) + #error "CK_VCO clock issue: must be in the range!" + #endif + + #define __CK_PLL (__CK_VCO >> PLL_NO2_DIV) /*!< Get CK_PLL frequency */ + + /* Check CK_PLL frequency */ + #if ((__CK_PLL < PLL_MIN) || (__CK_PLL > PLL_MAX)) + #error "CK_PLL clock issue: must be in the range!" + #endif +#endif + +/** + * @brief CK_SYS definition + */ +#if (HCLK_SRC == 1) + #if (PLL_ENABLE == 1) + #define __CK_SYS __CK_PLL /*!< Select PLL as CK_SYS source */ + #else + #error "CK_SYS clock source issue: PLL is not enable!" + #endif +#elif (HCLK_SRC == 2) + #if (HSE_ENABLE == 1) + #define __CK_SYS HSE_VALUE /*!< Select HSE as CK_SYS source */ + #else + #error "CK_SYS clock source issue: HSE is not enable!" + #endif +#elif (HCLK_SRC == 3) + #if (HSI_ENABLE == 1) + #define __CK_SYS HSI_VALUE /*!< Select HSI as CK_SYS source */ + #else + #error "CK_SYS clock source issue: HSI is not enable!" + #endif +#elif (HCLK_SRC == 6) + #ifdef USE_HT32F52220_30 + #error "CK_LSE can not be the source of SystemCoreClock for HT32F52220/30" + #else + #if (LSE_ENABLE == 1) + #define __CK_SYS LSE_VALUE /*!< Select LSE as CK_SYS source */ + #else + #error "CK_SYS clock source issue: LSE is not enable!" + #endif + #endif +#elif (HCLK_SRC == 7) + #if (LSI_ENABLE == 1) + #define __CK_SYS LSI_VALUE /*!< Select LSI as CK_SYS source */ + #else + #error "CK_SYS clock source issue: LSI is not enable!" + #endif +#else + #error "CK_SYS clock source issue: No clock source is selected!" +#endif + +/** + * @brief CK_AHB definition + */ +#define __CK_AHB (__CK_SYS >> HCLK_DIV) /*!< Get CK_AHB frequency */ + +#if defined(USE_HT32F52331_41) || defined(USE_HT32F52342_52) + #define CKAHB_MIN 1000UL + #define CKAHB_MAX 48000000UL + #define WS0_CLK 24000000UL +#endif + +#if defined(USE_HT32F52220_30) || defined(USE_HT32F52231_41) || defined(USE_HT32F52243_53) + #define CKAHB_MIN 1000UL + #define CKAHB_MAX 40000000UL + #define WS0_CLK 20000000UL +#endif + +/* Check CK_AHB frequency */ +#if ((__CK_AHB < CKAHB_MIN) || (__CK_AHB > CKAHB_MAX)) + #error "CK_AHB clock issue: must be in the range!" +#endif + +/* Check FLASH wait-state setting */ +#if ((__CK_AHB > WS0_CLK) && (WAIT_STATE < 1)) + #error "FLASH wait state configuration issue!" +#endif +/** + * @} + */ + +/** @addtogroup HT32F5xxxx_System_Private_Variables + * @{ + */ +__IO uint32_t SystemCoreClock = __CK_AHB; /*!< SystemCoreClock = CK_AHB */ +/** + * @} + */ + +/** @addtogroup HT32F5xxxx_System_Private_Functions + * @{ + */ + +/** + * @brief Setup the microcontroller system. + * Initializes the system clocks and the embedded Flash. + * @note This function should be used after reset. + * @retval None + */ +void SystemInit(void) +{ +#if (WDT_ENABLE == 1) + HT_CKCU->APBCCR1 |= (0x1 << 4); + HT_WDT->PR = 0x35CA; + HT_WDT->MR0 = 0; + HT_WDT->MR1 = ((HT_WDT->MR1 & 0xFFF) | (WDT_PRESCALER << 12)); + HT_WDT->MR0 = WDT_RELOAD | (WDT_RESET_ENABLE << 13) | (WDT_SLEEP_HALT << 14) | (0x1 << 16); + HT_WDT->CR = 0x5FA00001; +#else + #if (DEINIT_ENABLE == 1) + HT_RSTCU->APBPRST1 = (1 << 4); + #endif +#endif + + HT_CKCU->LPCR = 1; /* configure Backup domain isolation */ + SetBit_BB((u32)(&HT_CKCU->APBCCR1), 6); /* enable Backup domain register clock */ + while (HT_PWRCU->TEST != 0x27); /* wait for Backup domain register ready */ + + while ((HT_PWRCU->CR & 0x00000200) != 0x00000200) /* Backup domain register access test */ + HT_PWRCU->CR = 0x00000200; + while ((HT_PWRCU->CR & 0x00000200) != 0x00000000) + HT_PWRCU->CR = 0x00000000; + HT_CKCU->LPCR = 0; + + #if (DEINIT_ENABLE == 1) + /* De-init the setting */ + HT_CKCU->AHBCCR &= ~(0x3 << 10); /* disable IP who may use PLL as source */ + SetBit_BB((u32)(&HT_CKCU->GCCR), 11); /* enable HSI */ + while (!GetBit_BB((u32)(&HT_CKCU->GCSR), 3)); /* wait for HSI ready */ + HT_CKCU->GCCR = ((HT_CKCU->GCCR & ~7UL) | 3UL); /* select CK_SYS source */ + while ((HT_CKCU->CKST & 7UL) != 3UL); /* wait for clock switch complete */ + HT_FLASH->CFCR = (((HT_FLASH->CFCR) & ~7UL) | 1UL); /* set Wait State as 0 WS */ + HT_CKCU->AHBCFGR = 0; /* set CK_AHB prescaler */ + ResetBit_BB((u32)(&HT_CKCU->GCCR), 9); /* disable PLL */ + SetBit_BB((u32)(&HT_CKCU->GCFGR), 8); /* select PLL source as HSI */ + #endif + + /* HSE initiation */ +#if (HSE_ENABLE == 1) + SetBit_BB((u32)(&HT_CKCU->GCCR), 10); /* enable HSE */ + while (!GetBit_BB((u32)(&HT_CKCU->GCSR), 2)){}; /* wait for HSE ready */ +#endif + + /* LSE initiation */ +#if !defined(USE_HT32F52220_30) +#if (LSE_ENABLE == 1) + do { + SetBit_BB((u32)(&HT_RTC->CR), 3); /* enable LSE */ + } while (!GetBit_BB((u32)(&HT_RTC->CR), 3)); + while (!GetBit_BB((u32)(&HT_CKCU->GCSR), 4)); /* wait for LSE ready */ +#endif +#endif + + ResetBit_BB((u32)(&HT_CKCU->APBCCR1), 6); /* disable Backup domain register clock */ + + /* LSI initiation */ +#if (HCLK_SRC == 7) + while (!GetBit_BB((u32)(&HT_CKCU->GCSR), 5)){}; /* wait for LSI ready */ +#endif + + /* PLL initiation */ +#if (PLL_ENABLE == 1) + #if (PLL_CLK_SRC == 0) + ResetBit_BB((u32)(&HT_CKCU->GCFGR), 8); /* select PLL source as HSE */ + #else + SetBit_BB((u32)(&HT_CKCU->GCFGR), 8); /* select PLL source as HSI */ + #endif + HT_CKCU->PLLCFGR = ((PLL_NF2_DIV & 0x0F) << 23) | (PLL_NO2_DIV << 21); /* set PLL divider */ + SetBit_BB((u32)(&HT_CKCU->GCCR), 9); /* enable PLL */ + while (!GetBit_BB((u32)(&HT_CKCU->GCSR), 1)){}; /* wait for PLL ready */ +#endif + + /* CK_AHB initiation */ +#if (WAIT_STATE == 9) + #if (__CK_AHB > WS0_CLK) + HT_FLASH->CFCR = (((HT_FLASH->CFCR) & ~7UL) | 2UL); /* auto-select wait state */ + #endif +#else + HT_FLASH->CFCR = (((HT_FLASH->CFCR) & ~7UL) | (WAIT_STATE + 1)); /* manual wait state */ +#endif + + HT_CKCU->AHBCFGR = HCLK_DIV; /* set CK_AHB prescaler */ + HT_CKCU->GCCR = ((HT_CKCU->GCCR & ~7UL) | HCLK_SRC); /* select CK_SYS source */ + while ((HT_CKCU->CKST & 7UL) != HCLK_SRC); /* wait for clock switch complete */ + + /* Pre-fetch buffer configuration */ +#if (PRE_FETCH_ENABLE == 0) + ResetBit_BB((u32)(&HT_FLASH->CFCR), 4); /* 0: pre-fetch disable, 1: pre-fetch enable */ +#else + SetBit_BB((u32)(&HT_FLASH->CFCR), 4); /* 0: pre-fetch disable, 1: pre-fetch enable */ +#endif + + /* Branch cache configuration */ +#ifdef USE_HT32F52342_52 +#if (BCACHE_ENABLE == 0) + ResetBit_BB((u32)(&HT_FLASH->CFCR), 12); /* 0: branch cache disable, 1: branch cache enable */ +#else + SetBit_BB((u32)(&HT_FLASH->CFCR), 12); /* 0: branch cache disable, 1: branch cache enable */ +#endif +#endif + + /* HSE power down */ +#if ((HSE_ENABLE == 0) && (HCLK_SRC != 2) && ((PLL_ENABLE == 0) || (PLL_CLK_SRC == 1))) + ResetBit_BB((u32)(&HT_CKCU->GCCR), 10); +#endif + + /* HSI power down */ +#if ((HSI_ENABLE == 0) && (HCLK_SRC != 3) && ((PLL_ENABLE == 0) || (PLL_CLK_SRC == 0))) + ResetBit_BB((u32)(&HT_CKCU->GCCR), 11); +#endif +} + +/** + * @brief Update SystemCoreClock + * @retval None + */ +void SystemCoreClockUpdate(void) +{ + u32 SystemCoreClockDiv = HT_CKCU->AHBCFGR & 7UL; + u32 PllFeedbackClockDiv = ((HT_CKCU->PLLCFGR >> 23) == 0) ? (16) : (HT_CKCU->PLLCFGR >> 23); + u32 PllOutputClockDiv = (HT_CKCU->PLLCFGR >> 21) & 3UL; + u32 SystemCoreClockSrc = HT_CKCU->CKST & 7UL; + + /* Get system core clock according to global clock control & configuration registers */ + if (SystemCoreClockSrc == 1) + { + if (GetBit_BB((u32)(&HT_CKCU->PLLCR), 31)) + { + PllFeedbackClockDiv = 1; + PllOutputClockDiv = 0; + } + + if (GetBit_BB((u32)(&HT_CKCU->GCFGR), 8)) + { + SystemCoreClock = ((HSI_VALUE * PllFeedbackClockDiv) >> PllOutputClockDiv) >> SystemCoreClockDiv; + } + else + { + SystemCoreClock = ((HSE_VALUE * PllFeedbackClockDiv) >> PllOutputClockDiv) >> SystemCoreClockDiv; + } + } + else if (SystemCoreClockSrc == 2) + { + SystemCoreClock = HSE_VALUE >> SystemCoreClockDiv; + } + else if (SystemCoreClockSrc == 3) + { + SystemCoreClock = HSI_VALUE >> SystemCoreClockDiv; + } + #ifndef USE_HT32F52220_30 + else if (SystemCoreClockSrc == 6) + { + SystemCoreClock = LSE_VALUE >> SystemCoreClockDiv; + } + #endif + else if (SystemCoreClockSrc == 7) + { + SystemCoreClock = LSI_VALUE >> SystemCoreClockDiv; + } +} + +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ + +/******************* (C) COPYRIGHT Holtek Semiconductor Inc. *****END OF FILE*** */ diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/system_ht32f5xxxx_03.c b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/system_ht32f5xxxx_03.c new file mode 100644 index 0000000000..4da04c838a --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/system_ht32f5xxxx_03.c @@ -0,0 +1,518 @@ +/**************************************************************************//** + * @file library/Device/Holtek/HT32F5xxxx/Source/system_ht32f5xxxx_03.c + * @brief CMSIS Cortex-M0+ Device Peripheral Access Layer Source File + * for the Holtek HT32F5xxxx Device Series + * @version $Rev:: 7370 $ + * @date $Date:: 2023-12-06 #$ + * + * @note + * Copyright (C) Holtek Semiconductor Inc. All rights reserved. + * + * @par + * ARM Limited (ARM) supplies this software for Cortex-M processor-based + * microcontrollers. This file can be freely distributed within development + * tools that are supporting such ARM based processors. + * + * @par + * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR + * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + ******************************************************************************/ + +// Supported Device +// ======================================== +// HT32F0008 +// HT32F52142 +// HT32F52344, HT32F52354 +// HT32F52357, HT32F52367 +// HT32F65230, HT32F65240 +// HT50F3200T + +//#define USE_HT32F0008 +//#define USE_HT32F52142 +//#define USE_HT32F52344_54 +//#define USE_HT32F52357_67 +//#define USE_HT32F65230_40 +//#define USE_HT50F3200T + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup HT32F5xxxx_system HT32F5xxxx System + * @{ + */ + + +#include "ht32f5xxxx_01.h" + +/** @addtogroup HT32F5xxxx_System_Private_Defines + * @{ + */ +/* +//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ +*/ + +/*--------------------- Clock Configuration ---------------------------------- +// +// Enable High Speed External Crystal Oscillator (HSE) +// Default HSE = DISABLE +// +// Enable Low Speed External Crystal Oscillator (LSE) +// Default LSE = DISABLE +// Enable Waiting LSE Clock Ready +// Default Waiting LSE Clock Ready = ENABLE +// +// +// Enable PLL +// Default PLL = DISABLE +// PLL Out = (((HSE or HSI) / SRC_DIV) x NF2 ) / NO2 +// PLL Clock Source +// <0=> CK_HSE +// <1=> CK_HSI +// Default PLL clock source = CK_HSI +// PLL source clock must be in the range of 4 MHz to 16 MHz +// PLL Clock Source Divider (SRC_DIV) +// <0=> 1 +// <1=> 2 +// PLL input clock = PLL Clock Source / (SRC_DIV) +// PLL Feedback Clock Divider (NF2): 1 ~ 16 +// <1-16:1> +// PLL feedback clock = PLL input clock x NF2 +// PLL feedback clock must be in the range of 24 MHz to 60 MHz +// PLL Output Clock Divider (NO2) +// <0=> 1 +// <1=> 2 +// <2=> 4 +// <3=> 8 +// PLL output clock = PLL feedback clock / NO2 +// PLL output clock must be in the range of 4 MHz to 60 MHz +// +// +// SystemCoreClock Configuration (CK_AHB) +// SystemCoreClock Source +// <1=> CK_PLL +// <2=> CK_HSE +// <3=> CK_HSI +// <6=> CK_LSE +// <7=> CK_LSI +// Default SystemCoreClock source = CK_HSI +// SystemCoreClock Source Divider +// <0=> 1 +// <1=> 2 +// <2=> 4 +// <3=> 8 +// <4=> 16 +// <5=> 32 +// Default SystemCoreClock source divider = 1 +// +// +// FLASH Configuration +// Wait state +// <0=> 0 WS +// <1=> 1 WS +// <2=> 2 WS +// <9=> AUTO +// 0 WS: 1 kHz <= CK_AHB <= 20 MHz +// 1 WS: 20 MHz < CK_AHB <= 40 MHz +// 2 WS: 40 MHz < CK_AHB <= 60 MHz +// Pre-fetch Buffer Enable +// Default pre-fetch buffer = ENABLE +// Branch cache Enable (HT32F52357/67, HT32F65230/40, HT50F3200T Only) +// Default branch cache = ENABLE +// +*/ + +/* !!! NOTICE !!! + HSI must keep turn on when doing the Flash operation (Erase/Program). +*/ + +/* !!! NOTICE !!! + * How to adjust the value of High Speed External oscillator (HSE)? + The default value of HSE is define by "HSE_VALUE" in "ht32fxxxxx_nn.h". + If your board uses a different HSE speed, please add a new compiler preprocessor + C define, "HSE_VALUE=n000000" ("n" represents n MHz) in the toolchain/IDE, + or edit the "HSE_VALUE" in the "ht32f5xxxx_conf.h" file. + Take Keil MDK-ARM for instance, to set HSE as 16 MHz: + "Option of Taret -> C/C++ > Preprocessor Symbols" + Define: USE_HT32_DRIVER, USE_HT32Fxxxxx_SK, USE_HT32Fxxxxx_xx, USE_MEM_HT32Fxxxxx, HSE_VALUE=16000000 + ^^ Add "HSE_VALUE" + define as above. +*/ +#define HSI_ENABLE (1) /*!< 0: DISABLE, 1: ENABLE */ +#define HSE_ENABLE (1) /*!< 0: DISABLE, 1: ENABLE */ +#define LSI_ENABLE (1) /*!< 0: DISABLE, 1: ENABLE */ +#define LSE_ENABLE (0) /*!< 0: DISABLE, 1: ENABLE */ +#define LSE_WAIT_READY (1) /*!< 0: DISABLE, 1: ENABLE */ +#define PLL_ENABLE (1) /*!< 0: DISABLE, 1: ENABLE */ +#define PLL_CLK_SRC (0) /*!< 0: HSE, 1: HSI */ +#define PLL_CLK_SRC_DIV (1) /*!< 0: DIV1, 1: DIV2 */ +#define PLL_NF2_DIV (15) /*!< 1~16: DIV1~DIV16 */ +#define PLL_NO2_DIV (0) /*!< 0: DIV1, 1: DIV2, 2: DIV4, 3: DIV8 */ +#define HCLK_SRC (1) /*!< 0: PLL, 1: PLL, 2: HSE, 3: HSI 6: LSE, 7: LSI */ +#define HCLK_DIV (0) /*!< 0: DIV1, 1: DIV2, 2: DIV4, 3: DIV8, 4: DIV16, 5: DIV32 */ +#define WAIT_STATE (9) /*!< 0: WS = 0, 1: WS = 1, 2: WS = 2, 9: AUTO */ +#define PRE_FETCH_ENABLE (1) /*!< 0: DISABLE, 1: ENABLE */ +#define BCACHE_ENABLE (1) /*!< 0: DISABLE, 1: ENABLE */ +#define DEINIT_ENABLE (1) /* Set 0 for reduce code size */ + +/*----------------------------------------------------------------------------------------------------------*/ +/* PLL Out = (((HSE or HSI) / (PLL_CLK_SRC_DIV + 1)) x PLL_NF2) / PLL_NO2 */ +/*----------------------------------------------------------------------------------------------------------*/ + + +/*--------------------- WDT Configuration ---------------------------------- +// +// Enable WDT Configuration +// WDT Prescaler Selection +// <0=> CK_WDT / 1 +// <1=> CK_WDT / 2 +// <2=> CK_WDT / 4 +// <3=> CK_WDT / 8 +// <4=> CK_WDT / 16 +// <5=> CK_WDT / 32 +// <6=> CK_WDT / 64 +// <7=> CK_WDT / 128 +// WDT Reload Value <1-4095:1> +// Enable WDT Reset function +// WDT Sleep Halt mode +// <0=> No halt +// <1=> Halt in DeepSleep1 +// <2=> Halt in Sleep & DeepSleep1 +// +*/ +#define WDT_ENABLE (0) /*!< 0: DISABLE, 1: ENABLE */ +#define WDT_PRESCALER (5) /*!< 0: 1/1, 1: 1/2, 2: 1/4, 3: 1/8, 4: 1/16, 5: 1/32, 6: 1/64, 7: 1/128 */ +#define WDT_RELOAD (2000) /*!< 0 ~ 4095, 12 bit */ +#define WDT_RESET_ENABLE (1) /*!< 0: No Reset, 1: Reset when WDT over flow */ +#define WDT_SLEEP_HALT (2) /*!< 0: No halt, 1: Halt in DeepSleep1, 2: Halt in Sleep & DeepSleep1 */ + +/** + * @brief Check HSI frequency + */ +#if (HSI_VALUE != 8000000UL) + #error "CK_HSI clock issue: must be 8 MHz!" +#endif + +/** + * @brief Check HSE frequency + */ +#if ((HSE_VALUE < 4000000UL) || (HSE_VALUE > 16000000UL)) + #error "CK_HSE clock issue: must be in the range of 4 MHz to 16 MHz!" +#endif + +/** + * @brief Check LSI frequency + */ +#if (LSI_VALUE != 32000UL) + #error "CK_LSI clock issue: must be 32 kHz!" +#endif + +/** + * @brief Check LSE frequency + */ +#if (LSE_VALUE != 32768UL) + #error "CK_LSE clock issue: must be 32.768 kHz!" +#endif + +/** + * @brief CK_PLL definition + */ +#if (PLL_ENABLE == 1) + /* Get CK_VCO frequency */ + #if (PLL_CLK_SRC == 1) + #if (HSI_ENABLE == 0) + #error "CK_PLL clock source issue: HSI has not been enabled" + #else + #define __CK_VCO ((HSI_VALUE >> PLL_CLK_SRC_DIV) * PLL_NF2_DIV) /*!< Select HSI as PLL source */ + #endif + #else + #if (HSE_ENABLE == 0) + #error "CK_PLL clock source issue: HSE has not been enabled!" + #else + #define __CK_VCO ((HSE_VALUE >> PLL_CLK_SRC_DIV) * PLL_NF2_DIV) /*!< Select HSE as PLL source */ + #endif + #endif + + #define VCO_MIN 24000000UL + #define VCO_MAX 60000000UL + #define PLL_MIN 4000000UL + #define PLL_MAX 60000000UL + + /* Check CK_VCO frequency */ + #if ((__CK_VCO < VCO_MIN) || (__CK_VCO > VCO_MAX)) + #error "CK_VCO clock issue: must be in the range!" + #endif + + #define __CK_PLL (__CK_VCO >> PLL_NO2_DIV) /*!< Get CK_PLL frequency */ + + /* Check CK_PLL frequency */ + #if ((__CK_PLL < PLL_MIN) || (__CK_PLL > PLL_MAX)) + #error "CK_PLL clock issue: must be in the range!" + #endif +#endif + +/** + * @brief CK_SYS definition + */ +#if (HCLK_SRC == 1) + #if (PLL_ENABLE == 1) + #define __CK_SYS __CK_PLL /*!< Select PLL as CK_SYS source */ + #else + #error "CK_SYS clock source issue: PLL is not enable!" + #endif +#elif (HCLK_SRC == 2) + #if (HSE_ENABLE == 1) + #define __CK_SYS HSE_VALUE /*!< Select HSE as CK_SYS source */ + #else + #error "CK_SYS clock source issue: HSE is not enable!" + #endif +#elif (HCLK_SRC == 3) + #if (HSI_ENABLE == 1) + #define __CK_SYS HSI_VALUE /*!< Select HSI as CK_SYS source */ + #else + #error "CK_SYS clock source issue: HSI is not enable!" + #endif +#elif (HCLK_SRC == 6) + #if (LSE_ENABLE == 1) + #define __CK_SYS LSE_VALUE /*!< Select LSE as CK_SYS source */ + #else + #error "CK_SYS clock source issue: LSE is not enable!" + #endif +#elif (HCLK_SRC == 7) + #if (LSI_ENABLE == 1) + #define __CK_SYS LSI_VALUE /*!< Select LSI as CK_SYS source */ + #else + #error "CK_SYS clock source issue: LSI is not enable!" + #endif +#else + #error "CK_SYS clock source issue: No clock source is selected!" +#endif + +/** + * @brief CK_AHB definition + */ +#define __CK_AHB (__CK_SYS >> HCLK_DIV) /*!< Get CK_AHB frequency */ + +#define CKAHB_MIN 1000UL +#define CKAHB_MAX 60000000UL +#define WS0_CLK 20000000UL +#define WS1_CLK 40000000UL + +/* Check CK_AHB frequency */ +#if ((__CK_AHB < CKAHB_MIN) || (__CK_AHB > CKAHB_MAX)) + #error "CK_AHB clock issue: must be in the range!" +#endif + +/* Check FLASH wait-state setting */ +#if ((__CK_AHB > WS1_CLK) && (WAIT_STATE < 2) || \ + (__CK_AHB > WS0_CLK) && (WAIT_STATE < 1)) + #error "FLASH wait state configuration issue!" +#endif +/** + * @} + */ + +/** @addtogroup HT32F5xxxx_System_Private_Variables + * @{ + */ +__IO uint32_t SystemCoreClock = __CK_AHB; /*!< SystemCoreClock = CK_AHB */ +/** + * @} + */ + +/** @addtogroup HT32F5xxxx_System_Private_Functions + * @{ + */ + +/** + * @brief Setup the microcontroller system. + * Initializes the system clocks and the embedded Flash. + * @note This function should be used after reset. + * @retval None + */ +void SystemInit(void) +{ +#if (WDT_ENABLE == 1) + HT_CKCU->APBCCR1 |= (0x1 << 4); + HT_WDT->PR = 0x35CA; + HT_WDT->MR0 = 0; + HT_WDT->MR1 = ((HT_WDT->MR1 & 0xFFF) | (WDT_PRESCALER << 12)); + HT_WDT->MR0 = WDT_RELOAD | (WDT_RESET_ENABLE << 13) | (WDT_SLEEP_HALT << 14) | (0x1 << 16); + HT_WDT->CR = 0x5FA00001; +#else + #if (DEINIT_ENABLE == 1) + HT_RSTCU->APBPRST1 = (1 << 4); + #endif +#endif + + SetBit_BB((u32)(&HT_CKCU->APBCCR1), 6); /* enable Backup domain register clock */ + while (HT_PWRCU->TEST != 0x27); /* wait for Backup domain register ready */ + + #if (DEINIT_ENABLE == 1) + /* De-init the setting */ + HT_CKCU->AHBCCR &= ~(0x3 << 10); /* disable IP who may use PLL as source */ + SetBit_BB((u32)(&HT_CKCU->GCCR), 11); /* enable HSI */ + while (!GetBit_BB((u32)(&HT_CKCU->GCSR), 3)); /* wait for HSI ready */ + HT_CKCU->GCCR = ((HT_CKCU->GCCR & ~7UL) | 3UL); /* select CK_SYS source */ + while ((HT_CKCU->CKST & 7UL) != 3UL); /* wait for clock switch complete */ + HT_FLASH->CFCR = (((HT_FLASH->CFCR) & ~7UL) | 1UL); /* set Wait State as 0 WS */ + HT_CKCU->AHBCFGR = 0; /* set CK_AHB prescaler */ + ResetBit_BB((u32)(&HT_CKCU->GCCR), 9); /* disable PLL */ + SetBit_BB((u32)(&HT_CKCU->GCFGR), 8); /* select PLL source as HSI */ + #ifndef USE_HT32F65230_40 + ResetBit_BB((u32)(&HT_CKCU->GCCR), 3); /* disable USB PLL */ + SetBit_BB((u32)(&HT_CKCU->GCFGR), 9); /* select USB PLL source as HSI */ + #endif + #endif + + /* HSE initiation */ +#if (HSE_ENABLE == 1) + SetBit_BB((u32)(&HT_CKCU->GCCR), 10); /* enable HSE */ + while (!GetBit_BB((u32)(&HT_CKCU->GCSR), 2)){}; /* wait for HSE ready */ +#endif + + /* LSE initiation */ +#if (LSE_ENABLE == 1) + do { + SetBit_BB((u32)(&HT_RTC->CR), 3); /* enable LSE */ + } while (!GetBit_BB((u32)(&HT_RTC->CR), 3)); + #if (LSE_WAIT_READY == 1) + while (!GetBit_BB((u32)(&HT_CKCU->GCSR), 4)); /* wait for LSE ready */ + #endif +#endif + + ResetBit_BB((u32)(&HT_CKCU->APBCCR1), 6); /* disable Backup domain register clock */ + + /* LSI initiation */ +#if (HCLK_SRC == 7) + while (!GetBit_BB((u32)(&HT_CKCU->GCSR), 5)){}; /* wait for LSI ready */ +#endif + + /* PLL initiation */ +#if (PLL_ENABLE == 1) + HT_CKCU->PLLCFGR = ((PLL_NF2_DIV & 0x0F) << 23) | (PLL_NO2_DIV << 21); /* set PLL divider */ + + #if (PLL_CLK_SRC_DIV == 1) + SetBit_BB((u32)(&HT_CKCU->PLLCFGR), 28); /* set PLL clock source divider */ + #else + ResetBit_BB((u32)(&HT_CKCU->PLLCFGR), 28); /* reset PLL clock source divider */ + #endif + + #if (PLL_CLK_SRC == 0) + ResetBit_BB((u32)(&HT_CKCU->GCFGR), 8); /* select PLL source as HSE */ + #else + SetBit_BB((u32)(&HT_CKCU->GCFGR), 8); /* select PLL source as HSI */ + #endif + + SetBit_BB((u32)(&HT_CKCU->GCCR), 9); /* enable PLL */ + while (!GetBit_BB((u32)(&HT_CKCU->GCSR), 1)){}; /* wait for PLL ready */ +#endif + + /* CK_AHB initiation */ +#if (WAIT_STATE == 9) + #if (__CK_AHB > WS1_CLK) + HT_FLASH->CFCR = (((HT_FLASH->CFCR) & ~7UL) | 3UL); /* auto-select wait state */ + #elif (__CK_AHB > WS0_CLK) + HT_FLASH->CFCR = (((HT_FLASH->CFCR) & ~7UL) | 2UL); /* auto-select wait state */ + #endif +#else + HT_FLASH->CFCR = (((HT_FLASH->CFCR) & ~7UL) | (WAIT_STATE + 1)); /* manual wait state */ +#endif + + HT_CKCU->AHBCFGR = HCLK_DIV; /* set CK_AHB prescaler */ + HT_CKCU->GCCR = ((HT_CKCU->GCCR & ~7UL) | HCLK_SRC); /* select CK_SYS source */ + while ((HT_CKCU->CKST & 7UL) != HCLK_SRC); /* wait for clock switch complete */ + + /* Pre-fetch buffer configuration */ +#if (PRE_FETCH_ENABLE == 0) + ResetBit_BB((u32)(&HT_FLASH->CFCR), 4); /* 0: pre-fetch disable, 1: pre-fetch enable */ +#else + SetBit_BB((u32)(&HT_FLASH->CFCR), 4); /* 0: pre-fetch disable, 1: pre-fetch enable */ +#endif + + /* Branch cache configuration */ +#if defined(USE_HT32F52357_67) || defined(USE_HT32F65230_40) +#if (BCACHE_ENABLE == 0) + ResetBit_BB((u32)(&HT_FLASH->CFCR), 12); /* 0: branch cache disable, 1: branch cache enable */ +#else + SetBit_BB((u32)(&HT_FLASH->CFCR), 12); /* 0: branch cache disable, 1: branch cache enable */ +#endif +#endif + + /* HSE power down */ +#if ((HSE_ENABLE == 0) && (HCLK_SRC != 2) && ((PLL_ENABLE == 0) || (PLL_CLK_SRC == 1))) + ResetBit_BB((u32)(&HT_CKCU->GCCR), 10); +#endif + + /* HSI power down */ +#if ((HSI_ENABLE == 0) && (HCLK_SRC != 3) && ((PLL_ENABLE == 0) || (PLL_CLK_SRC == 0))) + ResetBit_BB((u32)(&HT_CKCU->GCCR), 11); +#endif +} + +/** + * @brief Update SystemCoreClock + * @retval None + */ +void SystemCoreClockUpdate(void) +{ + u32 SystemCoreClockDiv = HT_CKCU->AHBCFGR & 7UL; + u32 PllSourceClockDiv = (HT_CKCU->PLLCFGR >> 28) & 1UL; + u32 PllFeedbackClockDiv = (((HT_CKCU->PLLCFGR >> 23) & 15UL) == 0) ? (16) : ((HT_CKCU->PLLCFGR >> 23) & 15UL); + u32 PllOutputClockDiv = (HT_CKCU->PLLCFGR >> 21) & 3UL; + u32 SystemCoreClockSrc = HT_CKCU->CKST & 7UL; + + /* Get system core clock according to global clock control & configuration registers */ + if (SystemCoreClockSrc == 1) + { + if (GetBit_BB((u32)(&HT_CKCU->PLLCR), 31)) + { + PllFeedbackClockDiv = 1; + PllOutputClockDiv = 0; + } + + if (GetBit_BB((u32)(&HT_CKCU->GCFGR), 8)) + { + SystemCoreClock = (((HSI_VALUE >> PllSourceClockDiv) * PllFeedbackClockDiv) >> PllOutputClockDiv) >> SystemCoreClockDiv; + } + else + { + SystemCoreClock = (((HSE_VALUE >> PllSourceClockDiv) * PllFeedbackClockDiv) >> PllOutputClockDiv) >> SystemCoreClockDiv; + } + } + else if (SystemCoreClockSrc == 2) + { + SystemCoreClock = HSE_VALUE >> SystemCoreClockDiv; + } + else if (SystemCoreClockSrc == 3) + { + SystemCoreClock = HSI_VALUE >> SystemCoreClockDiv; + } + else if (SystemCoreClockSrc == 6) + { + SystemCoreClock = LSE_VALUE >> SystemCoreClockDiv; + } + else if (SystemCoreClockSrc == 7) + { + SystemCoreClock = LSI_VALUE >> SystemCoreClockDiv; + } +} + +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ + +/******************* (C) COPYRIGHT Holtek Semiconductor Inc. *****END OF FILE*** */ diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/system_ht32f5xxxx_04.c b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/system_ht32f5xxxx_04.c new file mode 100644 index 0000000000..b709d27c6f --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/system_ht32f5xxxx_04.c @@ -0,0 +1,335 @@ +/**************************************************************************//** + * @file library/Device/Holtek/HT32F5xxxx/Source/system_ht32f5xxxx_04.c + * @brief CMSIS Cortex-M0+ Device Peripheral Access Layer Source File + * for the Holtek HT32F5xxxx Device Series + * @version $Rev:: 7119 $ + * @date $Date:: 2023-08-15 #$ + * + * @note + * Copyright (C) Holtek Semiconductor Inc. All rights reserved. + * + * @par + * ARM Limited (ARM) supplies this software for Cortex-M processor-based + * microcontrollers. This file can be freely distributed within development + * tools that are supporting such ARM based processors. + * + * @par + * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR + * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + ******************************************************************************/ + +// Supported Device +// ======================================== +// HT32F50220, HT32F50230 +// HT32F50231, HT32F50241 +// HT50F32002 +// HT32F59041 +// HF5032 +// HT32F61641 +// HT32F59046 +// HT32F61041 + +//#define USE_HT32F50220_30 +//#define USE_HT32F50231_41 +//#define USE_HT50F32002 +//#define USE_HT32F59041 +//#define USE_HF5032 +//#define USE_HT32F61641 +//#define USE_HT32F59046 +//#define USE_HT32F61041 + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup HT32F5xxxx_system HT32F5xxxx System + * @{ + */ + + +#include "ht32f5xxxx_01.h" + +/** @addtogroup HT32F5xxxx_System_Private_Defines + * @{ + */ +/* +//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ +*/ + +/*--------------------- Clock Configuration ---------------------------------- +// +// Enable High Speed External Crystal Oscillator (HSE) +// Default HSE = DISABLE +// +// Enable Low Speed External Crystal Oscillator (LSE) +// Default LSE = DISABLE +// +// SystemCoreClock Configuration (CK_AHB) +// SystemCoreClock Source +// <2=> CK_HSE +// <3=> CK_HSI +// <6=> CK_LSE +// <7=> CK_LSI +// Default SystemCoreClock source = CK_HSI +// SystemCoreClock Source Divider +// <0=> 1 +// <1=> 2 +// <2=> 4 +// <3=> 8 +// <4=> 16 +// <5=> 32 +// Default SystemCoreClock source divider = 2 +// +*/ + +/* !!! NOTICE !!! + HSI must keep turn on when doing the Flash operation (Erase/Program). +*/ + +/* !!! NOTICE !!! + * How to adjust the value of High Speed External oscillator (HSE)? + The default value of HSE is define by "HSE_VALUE" in "ht32fxxxxx_nn.h". + If your board uses a different HSE speed, please add a new compiler preprocessor + C define, "HSE_VALUE=n000000" ("n" represents n MHz) in the toolchain/IDE, + or edit the "HSE_VALUE" in the "ht32f5xxxx_conf.h" file. + Take Keil MDK-ARM for instance, to set HSE as 16 MHz: + "Option of Taret -> C/C++ > Preprocessor Symbols" + Define: USE_HT32_DRIVER, USE_HT32Fxxxxx_SK, USE_HT32Fxxxxx_xx, USE_MEM_HT32Fxxxxx, HSE_VALUE=16000000 + ^^ Add "HSE_VALUE" + define as above. +*/ +#define HSI_ENABLE (1) /*!< 0: DISABLE, 1: ENABLE */ +#define HSE_ENABLE (1) /*!< 0: DISABLE, 1: ENABLE */ +#define LSI_ENABLE (1) /*!< 0: DISABLE, 1: ENABLE */ +#define LSE_ENABLE (0) /*!< 0: DISABLE, 1: ENABLE */ +#define HCLK_SRC (2) /*!< 0: N/A 1: N/A 2: HSE, 3: HSI 6: LSE, 7: LSI */ +#define HCLK_DIV (0) /*!< 0: DIV1, 1: DIV2, 2: DIV4, 3: DIV8, 4: DIV16, 5: DIV32 */ +#define DEINIT_ENABLE (1) /* Set 0 for reduce code size */ + +/*--------------------- WDT Configuration ---------------------------------- +// +// Enable WDT Configuration +// WDT Prescaler Selection +// <0=> CK_WDT / 1 +// <1=> CK_WDT / 2 +// <2=> CK_WDT / 4 +// <3=> CK_WDT / 8 +// <4=> CK_WDT / 16 +// <5=> CK_WDT / 32 +// <6=> CK_WDT / 64 +// <7=> CK_WDT / 128 +// WDT Reload Value <1-4095:1> +// Enable WDT Reset function +// WDT Sleep Halt mode +// <0=> No halt +// <1=> Halt in DeepSleep1 +// <2=> Halt in Sleep & DeepSleep1 +// +*/ +#define WDT_ENABLE (0) /*!< 0: DISABLE, 1: ENABLE */ +#define WDT_PRESCALER (5) /*!< 0: 1/1, 1: 1/2, 2: 1/4, 3: 1/8, 4: 1/16, 5: 1/32, 6: 1/64, 7: 1/128 */ +#define WDT_RELOAD (2000) /*!< 0 ~ 4095, 12 bit */ +#define WDT_RESET_ENABLE (1) /*!< 0: No Reset, 1: Reset when WDT over flow */ +#define WDT_SLEEP_HALT (2) /*!< 0: No halt, 1: Halt in DeepSleep1, 2: Halt in Sleep & DeepSleep1 */ + +/** + * @brief Check HSI frequency + */ +#if (HSI_VALUE != 20000000UL) + #error "CK_HSI clock issue: must be 20 MHz!" +#endif + +/** + * @brief Check HSE frequency + */ +#if ((HSE_VALUE < 4000000UL) || (HSE_VALUE > 20000000UL)) + #error "CK_HSE clock issue: must be in the range of 4 MHz to 20 MHz!" +#endif + +/** + * @brief Check LSI frequency + */ +#if (LSI_VALUE != 32000UL) + #error "CK_LSI clock issue: must be 32 kHz!" +#endif + +/** + * @brief Check LSE frequency + */ +#if (LSE_VALUE != 32768UL) + #error "CK_LSE clock issue: must be 32.768 kHz!" +#endif + +/** + * @brief CK_SYS definition + */ +#if (HCLK_SRC == 2) + #if (HSE_ENABLE == 1) + #define __CK_SYS HSE_VALUE /*!< Select HSE as CK_SYS source */ + #else + #error "CK_SYS clock source issue: HSE is not enable!" + #endif +#elif (HCLK_SRC == 3) + #if (HSI_ENABLE == 1) + #define __CK_SYS HSI_VALUE /*!< Select HSI as CK_SYS source */ + #else + #error "CK_SYS clock source issue: HSI is not enable!" + #endif +#elif (HCLK_SRC == 6) + #if (LSE_ENABLE == 1) + #define __CK_SYS LSE_VALUE /*!< Select LSE as CK_SYS source */ + #else + #error "CK_SYS clock source issue: LSE is not enable!" + #endif +#elif (HCLK_SRC == 7) + #if (LSI_ENABLE == 1) + #define __CK_SYS LSI_VALUE /*!< Select LSI as CK_SYS source */ + #else + #error "CK_SYS clock source issue: LSI is not enable!" + #endif +#else + #error "CK_SYS clock source issue: No clock source is selected!" +#endif + +/** + * @brief CK_AHB definition + */ +#define __CK_AHB (__CK_SYS >> HCLK_DIV) /*!< Get CK_AHB frequency */ + +#define CKAHB_MIN 1000UL +#define CKAHB_MAX 20000000UL + +/* Check CK_AHB frequency */ +#if ((__CK_AHB < CKAHB_MIN) || (__CK_AHB > CKAHB_MAX)) + #error "CK_AHB clock issue: must be in the range!" +#endif +/** + * @} + */ + +/** @addtogroup HT32F5xxxx_System_Private_Variables + * @{ + */ +__IO uint32_t SystemCoreClock = __CK_AHB; /*!< SystemCoreClock = CK_AHB */ +/** + * @} + */ + +/** @addtogroup HT32F5xxxx_System_Private_Functions + * @{ + */ + +/** + * @brief Setup the microcontroller system. + * Initializes the system clocks and the embedded Flash. + * @note This function should be used after reset. + * @retval None + */ +void SystemInit(void) +{ +#if (WDT_ENABLE == 1) + HT_CKCU->APBCCR1 |= (0x1 << 4); + HT_WDT->PR = 0x35CA; + HT_WDT->MR0 = 0; + HT_WDT->MR1 = ((HT_WDT->MR1 & 0xFFF) | (WDT_PRESCALER << 12)); + HT_WDT->MR0 = WDT_RELOAD | (WDT_RESET_ENABLE << 13) | (WDT_SLEEP_HALT << 14) | (0x1 << 16); + HT_WDT->CR = 0x5FA00001; +#else + #if (DEINIT_ENABLE == 1) + HT_RSTCU->APBPRST1 = (1 << 4); + #endif +#endif + + SetBit_BB((u32)(&HT_CKCU->APBCCR1), 6); /* enable VDD power domain register clock */ + + #if (DEINIT_ENABLE == 1) + /* De-init the setting */ + SetBit_BB((u32)(&HT_CKCU->GCCR), 11); /* enable HSI */ + while (!GetBit_BB((u32)(&HT_CKCU->GCSR), 3)); /* wait for HSI ready */ + HT_CKCU->GCCR = ((HT_CKCU->GCCR & ~7UL) | 3UL); /* select CK_SYS source */ + while ((HT_CKCU->CKST & 7UL) != 3UL); /* wait for clock switch complete */ + HT_CKCU->AHBCFGR = 1; /* set CK_AHB prescaler */ + #endif + + /* HSE initiation */ +#if (HSE_ENABLE == 1) + SetBit_BB((u32)(&HT_CKCU->GCCR), 10); /* enable HSE */ + while (!GetBit_BB((u32)(&HT_CKCU->GCSR), 2)){}; /* wait for HSE ready */ +#endif + + /* LSE initiation */ +#if (LSE_ENABLE == 1) + do { + SetBit_BB((u32)(&HT_RTC->CR), 3); /* enable LSE */ + } while (!GetBit_BB((u32)(&HT_RTC->CR), 3)); + while (!GetBit_BB((u32)(&HT_CKCU->GCSR), 4)); /* wait for LSE ready */ +#endif + + ResetBit_BB((u32)(&HT_CKCU->APBCCR1), 6); /* disable Backup domain register clock */ + + /* LSI initiation */ +#if (HCLK_SRC == 7) + while (!GetBit_BB((u32)(&HT_CKCU->GCSR), 5)){}; /* wait for LSI ready */ +#endif + + HT_CKCU->AHBCFGR = HCLK_DIV; /* set CK_AHB prescaler */ + HT_CKCU->GCCR = ((HT_CKCU->GCCR & ~7UL) | HCLK_SRC); /* select CK_SYS source */ + while ((HT_CKCU->CKST & 7UL) != HCLK_SRC); /* wait for clock switch complete */ + + /* HSE power down */ +#if ((HSE_ENABLE == 0) && (HCLK_SRC != 2)) + ResetBit_BB((u32)(&HT_CKCU->GCCR), 10); +#endif + + /* HSI power down */ +#if ((HSI_ENABLE == 0) && (HCLK_SRC != 3)) + ResetBit_BB((u32)(&HT_CKCU->GCCR), 11); +#endif +} + +/** + * @brief Update SystemCoreClock + * @retval None + */ +void SystemCoreClockUpdate(void) +{ + u32 SystemCoreClockDiv = HT_CKCU->AHBCFGR & 7UL; + u32 SystemCoreClockSrc = HT_CKCU->CKST & 7UL; + + /* Get system core clock according to global clock control & configuration registers */ + if (SystemCoreClockSrc == 2) + { + SystemCoreClock = HSE_VALUE >> SystemCoreClockDiv; + } + else if (SystemCoreClockSrc == 3) + { + SystemCoreClock = HSI_VALUE >> SystemCoreClockDiv; + } + else if (SystemCoreClockSrc == 6) + { + SystemCoreClock = LSE_VALUE >> SystemCoreClockDiv; + } + else if (SystemCoreClockSrc == 7) + { + SystemCoreClock = LSI_VALUE >> SystemCoreClockDiv; + } +} + +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ + +/******************* (C) COPYRIGHT Holtek Semiconductor Inc. *****END OF FILE*** */ diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/system_ht32f5xxxx_05.c b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/system_ht32f5xxxx_05.c new file mode 100644 index 0000000000..e0460f199e --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/system_ht32f5xxxx_05.c @@ -0,0 +1,497 @@ +/**************************************************************************//** + * @file library/Device/Holtek/HT32F5xxxx/Source/system_ht32f5xxxx_05.c + * @brief CMSIS Cortex-M0+ Device Peripheral Access Layer Source File + * for the Holtek HT32F5xxxx Device Series + * @version $Rev:: 6993 $ + * @date $Date:: 2023-06-26 #$ + * + * @note + * Copyright (C) Holtek Semiconductor Inc. All rights reserved. + * + * @par + * ARM Limited (ARM) supplies this software for Cortex-M processor-based + * microcontrollers. This file can be freely distributed within development + * tools that are supporting such ARM based processors. + * + * @par + * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR + * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + ******************************************************************************/ + +// Supported Device +// ======================================== +// HT32F57331, HT32F57341 +// HT32F57342, HT32F57352 +// HT32F59741 +// HT32F5828 +// HT32F67742 +// HT32F59746 + +//#define USE_HT32F57331_41 +//#define USE_HT32F57342_52 +//#define USE_HT32F59741 +//#define USE_HT32F5828 +//#define USE_HT32F67742 +//#define USE_HT32F59746 + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup HT32F5xxxx_system HT32F5xxxx System + * @{ + */ + + +#include "ht32f5xxxx_01.h" + +/** @addtogroup HT32F5xxxx_System_Private_Defines + * @{ + */ +/* +//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ +*/ + +/*--------------------- Clock Configuration ---------------------------------- +// +// Enable High Speed External Crystal Oscillator (HSE) +// Default HSE = DISABLE +// +// Enable Low Speed External Crystal Oscillator (LSE) +// Default LSE = DISABLE +// +// Enable PLL +// Default PLL = DISABLE +// PLL Out = (((HSE or HSI) / SRC_DIV) x NF2 ) / NO2 +// PLL Clock Source +// <0=> CK_HSE +// <1=> CK_HSI +// Default PLL clock source = CK_HSI +// PLL source clock must be in the range of 4 MHz to 16 MHz +// PLL Clock Source Divider (SRC_DIV) +// <0=> 1 +// <1=> 2 +// PLL input clock = PLL Clock Source / (SRC_DIV) +// PLL Feedback Clock Divider (NF2): 1 ~ 16 +// <1-16:1> +// PLL feedback clock = PLL input clock x NF2 +// PLL feedback clock must be in the range of 24 MHz to 60 MHz +// PLL Output Clock Divider (NO2) +// <0=> 1 +// <1=> 2 +// <2=> 4 +// <3=> 8 +// PLL output clock = PLL feedback clock / NO2 +// PLL output clock must be in the range of 4 MHz to 60 MHz +// +// +// SystemCoreClock Configuration (CK_AHB) +// SystemCoreClock Source +// <1=> CK_PLL +// <2=> CK_HSE +// <3=> CK_HSI +// <6=> CK_LSE +// <7=> CK_LSI +// Default SystemCoreClock source = CK_HSI +// SystemCoreClock Source Divider +// <0=> 1 +// <1=> 2 +// <2=> 4 +// <3=> 8 +// <4=> 16 +// <5=> 32 +// Default SystemCoreClock source divider = 1 +// +// +// FLASH Configuration +// Wait state +// <0=> 0 WS +// <1=> 1 WS +// <2=> 2 WS +// <9=> AUTO +// 0 WS: 1 kHz <= CK_AHB <= 20 MHz +// 1 WS: 20 MHz < CK_AHB <= 40 MHz +// 2 WS: 40 MHz < CK_AHB <= 60 MHz +// Pre-fetch Buffer Enable +// Default pre-fetch buffer = ENABLE +// +*/ + +/* !!! NOTICE !!! + HSI must keep turn on when doing the Flash operation (Erase/Program). +*/ + +/* !!! NOTICE !!! + * How to adjust the value of High Speed External oscillator (HSE)? + The default value of HSE is define by "HSE_VALUE" in "ht32fxxxxx_nn.h". + If your board uses a different HSE speed, please add a new compiler preprocessor + C define, "HSE_VALUE=n000000" ("n" represents n MHz) in the toolchain/IDE, + or edit the "HSE_VALUE" in the "ht32f5xxxx_conf.h" file. + Take Keil MDK-ARM for instance, to set HSE as 16 MHz: + "Option of Taret -> C/C++ > Preprocessor Symbols" + Define: USE_HT32_DRIVER, USE_HT32Fxxxxx_SK, USE_HT32Fxxxxx_xx, USE_MEM_HT32Fxxxxx, HSE_VALUE=16000000 + ^^ Add "HSE_VALUE" + define as above. +*/ +#define HSI_ENABLE (1) /*!< 0: DISABLE, 1: ENABLE */ +#define HSE_ENABLE (1) /*!< 0: DISABLE, 1: ENABLE */ +#define LSI_ENABLE (1) /*!< 0: DISABLE, 1: ENABLE */ +#define LSE_ENABLE (0) /*!< 0: DISABLE, 1: ENABLE */ +#define PLL_ENABLE (1) /*!< 0: DISABLE, 1: ENABLE */ +#define PLL_CLK_SRC (0) /*!< 0: HSE, 1: HSI */ +#define PLL_CLK_SRC_DIV (1) /*!< 0: DIV1, 1: DIV2 */ +#define PLL_NF2_DIV (15) /*!< 1~16: DIV1~DIV16 */ +#define PLL_NO2_DIV (0) /*!< 0: DIV1, 1: DIV2, 2: DIV4, 3: DIV8 */ +#define HCLK_SRC (1) /*!< 0: PLL, 1: PLL, 2: HSE, 3: HSI 6: LSE, 7: LSI */ +#define HCLK_DIV (0) /*!< 0: DIV1, 1: DIV2, 2: DIV4, 3: DIV8, 4: DIV16, 5: DIV32 */ +#define WAIT_STATE (9) /*!< 0: WS = 0, 1: WS = 1, 2: WS = 2, 9: AUTO */ +#define PRE_FETCH_ENABLE (1) /*!< 0: DISABLE, 1: ENABLE */ +#define DEINIT_ENABLE (1) /* Set 0 for reduce code size */ + +/*----------------------------------------------------------------------------------------------------------*/ +/* PLL Out = (((HSE or HSI) / (PLL_CLK_SRC_DIV + 1)) x PLL_NF2) / PLL_NO2 */ +/*----------------------------------------------------------------------------------------------------------*/ + + +/*--------------------- WDT Configuration ---------------------------------- +// +// Enable WDT Configuration +// WDT Prescaler Selection +// <0=> CK_WDT / 1 +// <1=> CK_WDT / 2 +// <2=> CK_WDT / 4 +// <3=> CK_WDT / 8 +// <4=> CK_WDT / 16 +// <5=> CK_WDT / 32 +// <6=> CK_WDT / 64 +// <7=> CK_WDT / 128 +// WDT Reload Value <1-4095:1> +// Enable WDT Reset function +// WDT Sleep Halt mode +// <0=> No halt +// <1=> Halt in DeepSleep1 +// <2=> Halt in Sleep & DeepSleep1 +// +*/ +#define WDT_ENABLE (0) /*!< 0: DISABLE, 1: ENABLE */ +#define WDT_PRESCALER (5) /*!< 0: 1/1, 1: 1/2, 2: 1/4, 3: 1/8, 4: 1/16, 5: 1/32, 6: 1/64, 7: 1/128 */ +#define WDT_RELOAD (2000) /*!< 0 ~ 4095, 12 bit */ +#define WDT_RESET_ENABLE (1) /*!< 0: No Reset, 1: Reset when WDT over flow */ +#define WDT_SLEEP_HALT (2) /*!< 0: No halt, 1: Halt in DeepSleep1, 2: Halt in Sleep & DeepSleep1 */ + +/** + * @brief Check HSI frequency + */ +#if (HSI_VALUE != 8000000UL) + #error "CK_HSI clock issue: must be 8 MHz!" +#endif + +/** + * @brief Check HSE frequency + */ +#if ((HSE_VALUE < 4000000UL) || (HSE_VALUE > 16000000UL)) + #error "CK_HSE clock issue: must be in the range of 4 MHz to 16 MHz!" +#endif + +/** + * @brief Check LSI frequency + */ +#if (LSI_VALUE != 32000UL) + #error "CK_LSI clock issue: must be 32 kHz!" +#endif + +/** + * @brief Check LSE frequency + */ +#if (LSE_VALUE != 32768UL) + #error "CK_LSE clock issue: must be 32.768 kHz!" +#endif + +/** + * @brief CK_PLL definition + */ +#if (PLL_ENABLE == 1) + /* Get CK_VCO frequency */ + #if (PLL_CLK_SRC == 1) + #if (HSI_ENABLE == 0) + #error "CK_PLL clock source issue: HSI has not been enabled" + #else + #define __CK_VCO ((HSI_VALUE >> PLL_CLK_SRC_DIV) * PLL_NF2_DIV) /*!< Select HSI as PLL source */ + #endif + #else + #if (HSE_ENABLE == 0) + #error "CK_PLL clock source issue: HSE has not been enabled!" + #else + #define __CK_VCO ((HSE_VALUE >> PLL_CLK_SRC_DIV) * PLL_NF2_DIV) /*!< Select HSE as PLL source */ + #endif + #endif + + #define VCO_MIN 24000000UL + #define VCO_MAX 60000000UL + #define PLL_MIN 4000000UL + #define PLL_MAX 60000000UL + + /* Check CK_VCO frequency */ + #if ((__CK_VCO < VCO_MIN) || (__CK_VCO > VCO_MAX)) + #error "CK_VCO clock issue: must be in the range!" + #endif + + #define __CK_PLL (__CK_VCO >> PLL_NO2_DIV) /*!< Get CK_PLL frequency */ + + /* Check CK_PLL frequency */ + #if ((__CK_PLL < PLL_MIN) || (__CK_PLL > PLL_MAX)) + #error "CK_PLL clock issue: must be in the range!" + #endif +#endif + +/** + * @brief CK_SYS definition + */ +#if (HCLK_SRC == 1) + #if (PLL_ENABLE == 1) + #define __CK_SYS __CK_PLL /*!< Select PLL as CK_SYS source */ + #else + #error "CK_SYS clock source issue: PLL is not enable!" + #endif +#elif (HCLK_SRC == 2) + #if (HSE_ENABLE == 1) + #define __CK_SYS HSE_VALUE /*!< Select HSE as CK_SYS source */ + #else + #error "CK_SYS clock source issue: HSE is not enable!" + #endif +#elif (HCLK_SRC == 3) + #if (HSI_ENABLE == 1) + #define __CK_SYS HSI_VALUE /*!< Select HSI as CK_SYS source */ + #else + #error "CK_SYS clock source issue: HSI is not enable!" + #endif +#elif (HCLK_SRC == 6) + #if (LSE_ENABLE == 1) + #define __CK_SYS LSE_VALUE /*!< Select LSE as CK_SYS source */ + #else + #error "CK_SYS clock source issue: LSE is not enable!" + #endif +#elif (HCLK_SRC == 7) + #if (LSI_ENABLE == 1) + #define __CK_SYS LSI_VALUE /*!< Select LSI as CK_SYS source */ + #else + #error "CK_SYS clock source issue: LSI is not enable!" + #endif +#else + #error "CK_SYS clock source issue: No clock source is selected!" +#endif + +/** + * @brief CK_AHB definition + */ +#define __CK_AHB (__CK_SYS >> HCLK_DIV) /*!< Get CK_AHB frequency */ + +#define CKAHB_MIN 1000UL +#define CKAHB_MAX 60000000UL +#define WS0_CLK 20000000UL +#define WS1_CLK 40000000UL + +/* Check CK_AHB frequency */ +#if ((__CK_AHB < CKAHB_MIN) || (__CK_AHB > CKAHB_MAX)) + #error "CK_AHB clock issue: must be in the range!" +#endif + +/* Check FLASH wait-state setting */ +#if ((__CK_AHB > WS1_CLK) && (WAIT_STATE < 2) || \ + (__CK_AHB > WS0_CLK) && (WAIT_STATE < 1)) + #error "FLASH wait state configuration issue!" +#endif +/** + * @} + */ + +/** @addtogroup HT32F5xxxx_System_Private_Variables + * @{ + */ +__IO uint32_t SystemCoreClock = __CK_AHB; /*!< SystemCoreClock = CK_AHB */ +/** + * @} + */ + +/** @addtogroup HT32F5xxxx_System_Private_Functions + * @{ + */ + +/** + * @brief Setup the microcontroller system. + * Initializes the system clocks and the embedded Flash. + * @note This function should be used after reset. + * @retval None + */ +void SystemInit(void) +{ +#if (WDT_ENABLE == 1) + HT_CKCU->APBCCR1 |= (0x1 << 4); + HT_WDT->PR = 0x35CA; + HT_WDT->MR0 = 0; + HT_WDT->MR1 = ((HT_WDT->MR1 & 0xFFF) | (WDT_PRESCALER << 12)); + HT_WDT->MR0 = WDT_RELOAD | (WDT_RESET_ENABLE << 13) | (WDT_SLEEP_HALT << 14) | (0x1 << 16); + HT_WDT->CR = 0x5FA00001; +#else + #if (DEINIT_ENABLE == 1) + HT_RSTCU->APBPRST1 = (1 << 4); + #endif +#endif + + SetBit_BB((u32)(&HT_CKCU->APBCCR1), 6); /* enable Backup domain register clock */ + + #if (DEINIT_ENABLE == 1) + /* De-init the setting */ + HT_CKCU->AHBCCR &= ~(0x3 << 10); /* disable IP who may use PLL as source */ + SetBit_BB((u32)(&HT_CKCU->GCCR), 11); /* enable HSI */ + while (!GetBit_BB((u32)(&HT_CKCU->GCSR), 3)); /* wait for HSI ready */ + HT_CKCU->GCCR = ((HT_CKCU->GCCR & ~7UL) | 3UL); /* select CK_SYS source */ + while ((HT_CKCU->CKST & 7UL) != 3UL); /* wait for clock switch complete */ + HT_FLASH->CFCR = (((HT_FLASH->CFCR) & ~7UL) | 1UL); /* set Wait State as 0 WS */ + HT_CKCU->AHBCFGR = 0; /* set CK_AHB prescaler */ + ResetBit_BB((u32)(&HT_CKCU->GCCR), 9); /* disable PLL */ + SetBit_BB((u32)(&HT_CKCU->GCFGR), 8); /* select PLL source as HSI */ + ResetBit_BB((u32)(&HT_CKCU->GCCR), 3); /* disable USB PLL */ + SetBit_BB((u32)(&HT_CKCU->GCFGR), 9); /* select USB PLL source as HSI */ + #endif + + /* HSE initiation */ +#if (HSE_ENABLE == 1) + SetBit_BB((u32)(&HT_CKCU->GCCR), 10); /* enable HSE */ + while (!GetBit_BB((u32)(&HT_CKCU->GCSR), 2)){}; /* wait for HSE ready */ +#endif + + /* LSE initiation */ +#if (LSE_ENABLE == 1) + do { + SetBit_BB((u32)(&HT_RTC->CR), 3); /* enable LSE */ + } while (!GetBit_BB((u32)(&HT_RTC->CR), 3)); + while (!GetBit_BB((u32)(&HT_CKCU->GCSR), 4)); /* wait for LSE ready */ +#endif + + ResetBit_BB((u32)(&HT_CKCU->APBCCR1), 6); /* disable Backup domain register clock */ + + /* LSI initiation */ +#if (HCLK_SRC == 7) + while (!GetBit_BB((u32)(&HT_CKCU->GCSR), 5)){}; /* wait for LSI ready */ +#endif + + /* PLL initiation */ +#if (PLL_ENABLE == 1) + HT_CKCU->PLLCFGR = ((PLL_NF2_DIV & 0x0F) << 23) | (PLL_NO2_DIV << 21); /* set PLL divider */ + + #if (PLL_CLK_SRC_DIV == 1) + SetBit_BB((u32)(&HT_CKCU->PLLCFGR), 28); /* set PLL clock source divider */ + #else + ResetBit_BB((u32)(&HT_CKCU->PLLCFGR), 28); /* reset PLL clock source divider */ + #endif + + #if (PLL_CLK_SRC == 0) + ResetBit_BB((u32)(&HT_CKCU->GCFGR), 8); /* select PLL source as HSE */ + #else + SetBit_BB((u32)(&HT_CKCU->GCFGR), 8); /* select PLL source as HSI */ + #endif + + SetBit_BB((u32)(&HT_CKCU->GCCR), 9); /* enable PLL */ + while (!GetBit_BB((u32)(&HT_CKCU->GCSR), 1)){}; /* wait for PLL ready */ +#endif + + /* CK_AHB initiation */ +#if (WAIT_STATE == 9) + #if (__CK_AHB > WS1_CLK) + HT_FLASH->CFCR = (((HT_FLASH->CFCR) & ~7UL) | 3UL); /* auto-select wait state */ + #elif (__CK_AHB > WS0_CLK) + HT_FLASH->CFCR = (((HT_FLASH->CFCR) & ~7UL) | 2UL); /* auto-select wait state */ + #endif +#else + HT_FLASH->CFCR = (((HT_FLASH->CFCR) & ~7UL) | (WAIT_STATE + 1)); /* manual wait state */ +#endif + + HT_CKCU->AHBCFGR = HCLK_DIV; /* set CK_AHB prescaler */ + HT_CKCU->GCCR = ((HT_CKCU->GCCR & ~7UL) | HCLK_SRC); /* select CK_SYS source */ + while ((HT_CKCU->CKST & 7UL) != HCLK_SRC); /* wait for clock switch complete */ + + /* Pre-fetch buffer configuration */ +#if (PRE_FETCH_ENABLE == 0) + ResetBit_BB((u32)(&HT_FLASH->CFCR), 4); /* 0: pre-fetch disable, 1: pre-fetch enable */ +#else + SetBit_BB((u32)(&HT_FLASH->CFCR), 4); /* 0: pre-fetch disable, 1: pre-fetch enable */ +#endif + + /* HSE power down */ +#if ((HSE_ENABLE == 0) && (HCLK_SRC != 2) && ((PLL_ENABLE == 0) || (PLL_CLK_SRC == 1))) + ResetBit_BB((u32)(&HT_CKCU->GCCR), 10); +#endif + + /* HSI power down */ +#if ((HSI_ENABLE == 0) && (HCLK_SRC != 3) && ((PLL_ENABLE == 0) || (PLL_CLK_SRC == 0))) + ResetBit_BB((u32)(&HT_CKCU->GCCR), 11); +#endif +} + +/** + * @brief Update SystemCoreClock + * @retval None + */ +void SystemCoreClockUpdate(void) +{ + u32 SystemCoreClockDiv = HT_CKCU->AHBCFGR & 7UL; + u32 PllSourceClockDiv = (HT_CKCU->PLLCFGR >> 28) & 1UL; + u32 PllFeedbackClockDiv = (((HT_CKCU->PLLCFGR >> 23) & 15UL) == 0) ? (16) : ((HT_CKCU->PLLCFGR >> 23) & 15UL); + u32 PllOutputClockDiv = (HT_CKCU->PLLCFGR >> 21) & 3UL; + u32 SystemCoreClockSrc = HT_CKCU->CKST & 7UL; + + /* Get system core clock according to global clock control & configuration registers */ + if (SystemCoreClockSrc == 1) + { + if (GetBit_BB((u32)(&HT_CKCU->PLLCR), 31)) + { + PllFeedbackClockDiv = 1; + PllOutputClockDiv = 0; + } + + if (GetBit_BB((u32)(&HT_CKCU->GCFGR), 8)) + { + SystemCoreClock = (((HSI_VALUE >> PllSourceClockDiv) * PllFeedbackClockDiv) >> PllOutputClockDiv) >> SystemCoreClockDiv; + } + else + { + SystemCoreClock = (((HSE_VALUE >> PllSourceClockDiv) * PllFeedbackClockDiv) >> PllOutputClockDiv) >> SystemCoreClockDiv; + } + } + else if (SystemCoreClockSrc == 2) + { + SystemCoreClock = HSE_VALUE >> SystemCoreClockDiv; + } + else if (SystemCoreClockSrc == 3) + { + SystemCoreClock = HSI_VALUE >> SystemCoreClockDiv; + } + else if (SystemCoreClockSrc == 6) + { + SystemCoreClock = LSE_VALUE >> SystemCoreClockDiv; + } + else if (SystemCoreClockSrc == 7) + { + SystemCoreClock = LSI_VALUE >> SystemCoreClockDiv; + } +} + +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ + +/******************* (C) COPYRIGHT Holtek Semiconductor Inc. *****END OF FILE*** */ diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/system_ht32f5xxxx_06.c b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/system_ht32f5xxxx_06.c new file mode 100644 index 0000000000..3be16d5319 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/system_ht32f5xxxx_06.c @@ -0,0 +1,488 @@ +/**************************************************************************//** + * @file library/Device/Holtek/HT32F5xxxx/Source/system_ht32f5xxxx_06.c + * @brief CMSIS Cortex-M0+ Device Peripheral Access Layer Source File + * for the Holtek HT32F5xxxx Device Series + * @version $Rev:: 6597 $ + * @date $Date:: 2022-12-27 #$ + * + * @note + * Copyright (C) Holtek Semiconductor Inc. All rights reserved. + * + * @par + * ARM Limited (ARM) supplies this software for Cortex-M processor-based + * microcontrollers. This file can be freely distributed within development + * tools that are supporting such ARM based processors. + * + * @par + * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR + * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + ******************************************************************************/ + +// Supported Device +// ======================================== +// HT32F50343 + + +//#define USE_HT32F50343 + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup HT32F5xxxx_system HT32F5xxxx System + * @{ + */ + + +#include "ht32f5xxxx_01.h" + +/** @addtogroup HT32F5xxxx_System_Private_Defines + * @{ + */ +/* +//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ +*/ + +/*--------------------- Clock Configuration ---------------------------------- +// +// Enable High Speed External Crystal Oscillator (HSE) +// Default HSE = DISABLE +// +// Enable Low Speed External Crystal Oscillator (LSE) +// Default LSE = DISABLE +// +// Enable PLL +// Default PLL = DISABLE +// PLL Out = (((HSE or HSI) / SRC_DIV) x NF2 ) / NO2 +// PLL Clock Source +// <0=> CK_HSE +// <1=> CK_HSI +// Default PLL clock source = CK_HSI +// PLL source clock must be in the range of 4 MHz to 16 MHz +// PLL Clock Source Divider (SRC_DIV) +// <0=> 1 +// <1=> 2 +// PLL input clock = PLL Clock Source / (SRC_DIV) +// PLL Feedback Clock Divider (NF2): 1 ~ 16 +// <1-16:1> +// PLL feedback clock = PLL input clock x NF2 +// PLL feedback clock must be in the range of 24 MHz to 60 MHz +// PLL Output Clock Divider (NO2) +// <0=> 1 +// <1=> 2 +// <2=> 4 +// <3=> 8 +// PLL output clock = PLL feedback clock / NO2 +// PLL output clock must be in the range of 4 MHz to 60 MHz +// +// +// SystemCoreClock Configuration (CK_AHB) +// SystemCoreClock Source +// <1=> CK_PLL +// <2=> CK_HSE +// <3=> CK_HSI +// <6=> CK_LSE +// <7=> CK_LSI +// Default SystemCoreClock source = CK_HSI +// SystemCoreClock Source Divider +// <0=> 1 +// <1=> 2 +// <2=> 4 +// <3=> 8 +// <4=> 16 +// <5=> 32 +// Default SystemCoreClock source divider = 1 +// +// +// FLASH Configuration +// Wait state +// <0=> 0 WS +// <1=> 1 WS +// <2=> 2 WS +// <9=> AUTO +// 0 WS: 1 kHz <= CK_AHB <= 20 MHz +// 1 WS: 20 MHz < CK_AHB <= 40 MHz +// 2 WS: 40 MHz < CK_AHB <= 60 MHz +// Pre-fetch Buffer Enable +// Default pre-fetch buffer = ENABLE +// +*/ + +/* !!! NOTICE !!! + HSI must keep turn on when doing the Flash operation (Erase/Program). +*/ + +/* !!! NOTICE !!! + * How to adjust the value of High Speed External oscillator (HSE)? + The default value of HSE is define by "HSE_VALUE" in "ht32fxxxxx_nn.h". + If your board uses a different HSE speed, please add a new compiler preprocessor + C define, "HSE_VALUE=n000000" ("n" represents n MHz) in the toolchain/IDE, + or edit the "HSE_VALUE" in the "ht32f5xxxx_conf.h" file. + Take Keil MDK-ARM for instance, to set HSE as 16 MHz: + "Option of Taret -> C/C++ > Preprocessor Symbols" + Define: USE_HT32_DRIVER, USE_HT32Fxxxxx_SK, USE_HT32Fxxxxx_xx, USE_MEM_HT32Fxxxxx, HSE_VALUE=16000000 + ^^ Add "HSE_VALUE" + define as above. +*/ +#define HSI_ENABLE (1) /*!< 0: DISABLE, 1: ENABLE */ +#define HSE_ENABLE (1) /*!< 0: DISABLE, 1: ENABLE */ +#define LSI_ENABLE (1) /*!< 0: DISABLE, 1: ENABLE */ +#define LSE_ENABLE (0) /*!< 0: DISABLE, 1: ENABLE */ +#define PLL_ENABLE (1) /*!< 0: DISABLE, 1: ENABLE */ +#define PLL_CLK_SRC (0) /*!< 0: HSE, 1: HSI */ +#define PLL_CLK_SRC_DIV (1) /*!< 0: DIV1, 1: DIV2 */ +#define PLL_NF2_DIV (15) /*!< 1~16: DIV1~DIV16 */ +#define PLL_NO2_DIV (0) /*!< 0: DIV1, 1: DIV2, 2: DIV4, 3: DIV8 */ +#define HCLK_SRC (1) /*!< 0: PLL, 1: PLL, 2: HSE, 3: HSI 6: LSE, 7: LSI */ +#define HCLK_DIV (0) /*!< 0: DIV1, 1: DIV2, 2: DIV4, 3: DIV8, 4: DIV16, 5: DIV32 */ +#define WAIT_STATE (9) /*!< 0: WS = 0, 1: WS = 1, 2: WS = 2, 9: AUTO */ +#define PRE_FETCH_ENABLE (1) /*!< 0: DISABLE, 1: ENABLE */ +#define DEINIT_ENABLE (1) /* Set 0 for reduce code size */ + +/*----------------------------------------------------------------------------------------------------------*/ +/* PLL Out = (((HSE or HSI) / (PLL_CLK_SRC_DIV + 1)) x PLL_NF2) / PLL_NO2 */ +/*----------------------------------------------------------------------------------------------------------*/ + + +/*--------------------- WDT Configuration ---------------------------------- +// +// Enable WDT Configuration +// WDT Prescaler Selection +// <0=> CK_WDT / 1 +// <1=> CK_WDT / 2 +// <2=> CK_WDT / 4 +// <3=> CK_WDT / 8 +// <4=> CK_WDT / 16 +// <5=> CK_WDT / 32 +// <6=> CK_WDT / 64 +// <7=> CK_WDT / 128 +// WDT Reload Value <1-4095:1> +// Enable WDT Reset function +// WDT Sleep Halt mode +// <0=> No halt +// <1=> Halt in DeepSleep1 +// <2=> Halt in Sleep & DeepSleep1 +// +*/ +#define WDT_ENABLE (0) /*!< 0: DISABLE, 1: ENABLE */ +#define WDT_PRESCALER (5) /*!< 0: 1/1, 1: 1/2, 2: 1/4, 3: 1/8, 4: 1/16, 5: 1/32, 6: 1/64, 7: 1/128 */ +#define WDT_RELOAD (2000) /*!< 0 ~ 4095, 12 bit */ +#define WDT_RESET_ENABLE (1) /*!< 0: No Reset, 1: Reset when WDT over flow */ +#define WDT_SLEEP_HALT (2) /*!< 0: No halt, 1: Halt in DeepSleep1, 2: Halt in Sleep & DeepSleep1 */ + +/** + * @brief Check HSI frequency + */ +#if (HSI_VALUE != 8000000UL) + #error "CK_HSI clock issue: must be 8 MHz!" +#endif + +/** + * @brief Check HSE frequency + */ +#if ((HSE_VALUE < 4000000UL) || (HSE_VALUE > 16000000UL)) + #error "CK_HSE clock issue: must be in the range of 4 MHz to 16 MHz!" +#endif + +/** + * @brief Check LSI frequency + */ +#if (LSI_VALUE != 32000UL) + #error "CK_LSI clock issue: must be 32 kHz!" +#endif + +/** + * @brief Check LSE frequency + */ +#if (LSE_VALUE != 32768UL) + #error "CK_LSE clock issue: must be 32.768 kHz!" +#endif + +/** + * @brief CK_PLL definition + */ +#if (PLL_ENABLE == 1) + /* Get CK_VCO frequency */ + #if (PLL_CLK_SRC == 1) + #if (HSI_ENABLE == 0) + #error "CK_PLL clock source issue: HSI has not been enabled" + #else + #define __CK_VCO ((HSI_VALUE >> PLL_CLK_SRC_DIV) * PLL_NF2_DIV) /*!< Select HSI as PLL source */ + #endif + #else + #if (HSE_ENABLE == 0) + #error "CK_PLL clock source issue: HSE has not been enabled!" + #else + #define __CK_VCO ((HSE_VALUE >> PLL_CLK_SRC_DIV) * PLL_NF2_DIV) /*!< Select HSE as PLL source */ + #endif + #endif + + #define VCO_MIN 24000000UL + #define VCO_MAX 60000000UL + #define PLL_MIN 4000000UL + #define PLL_MAX 60000000UL + + /* Check CK_VCO frequency */ + #if ((__CK_VCO < VCO_MIN) || (__CK_VCO > VCO_MAX)) + #error "CK_VCO clock issue: must be in the range!" + #endif + + #define __CK_PLL (__CK_VCO >> PLL_NO2_DIV) /*!< Get CK_PLL frequency */ + + /* Check CK_PLL frequency */ + #if ((__CK_PLL < PLL_MIN) || (__CK_PLL > PLL_MAX)) + #error "CK_PLL clock issue: must be in the range!" + #endif +#endif + +/** + * @brief CK_SYS definition + */ +#if (HCLK_SRC == 1) + #if (PLL_ENABLE == 1) + #define __CK_SYS __CK_PLL /*!< Select PLL as CK_SYS source */ + #else + #error "CK_SYS clock source issue: PLL is not enable!" + #endif +#elif (HCLK_SRC == 2) + #if (HSE_ENABLE == 1) + #define __CK_SYS HSE_VALUE /*!< Select HSE as CK_SYS source */ + #else + #error "CK_SYS clock source issue: HSE is not enable!" + #endif +#elif (HCLK_SRC == 3) + #if (HSI_ENABLE == 1) + #define __CK_SYS HSI_VALUE /*!< Select HSI as CK_SYS source */ + #else + #error "CK_SYS clock source issue: HSI is not enable!" + #endif +#elif (HCLK_SRC == 6) + #if (LSE_ENABLE == 1) + #define __CK_SYS LSE_VALUE /*!< Select LSE as CK_SYS source */ + #else + #error "CK_SYS clock source issue: LSE is not enable!" + #endif +#elif (HCLK_SRC == 7) + #if (LSI_ENABLE == 1) + #define __CK_SYS LSI_VALUE /*!< Select LSI as CK_SYS source */ + #else + #error "CK_SYS clock source issue: LSI is not enable!" + #endif +#else + #error "CK_SYS clock source issue: No clock source is selected!" +#endif + +/** + * @brief CK_AHB definition + */ +#define __CK_AHB (__CK_SYS >> HCLK_DIV) /*!< Get CK_AHB frequency */ + +#define CKAHB_MIN 1000UL +#define CKAHB_MAX 60000000UL +#define WS0_CLK 20000000UL +#define WS1_CLK 40000000UL + +/* Check CK_AHB frequency */ +#if ((__CK_AHB < CKAHB_MIN) || (__CK_AHB > CKAHB_MAX)) + #error "CK_AHB clock issue: must be in the range!" +#endif + +/* Check FLASH wait-state setting */ +#if ((__CK_AHB > WS1_CLK) && (WAIT_STATE < 2) || \ + (__CK_AHB > WS0_CLK) && (WAIT_STATE < 1)) + #error "FLASH wait state configuration issue!" +#endif +/** + * @} + */ + +/** @addtogroup HT32F5xxxx_System_Private_Variables + * @{ + */ +__IO uint32_t SystemCoreClock = __CK_AHB; /*!< SystemCoreClock = CK_AHB */ +/** + * @} + */ + +/** @addtogroup HT32F5xxxx_System_Private_Functions + * @{ + */ + +/** + * @brief Setup the microcontroller system. + * Initializes the system clocks and the embedded Flash. + * @note This function should be used after reset. + * @retval None + */ +void SystemInit(void) +{ +#if (WDT_ENABLE == 1) + HT_CKCU->APBCCR1 |= (0x1 << 4); + HT_WDT->PR = 0x35CA; + HT_WDT->MR0 = 0; + HT_WDT->MR1 = ((HT_WDT->MR1 & 0xFFF) | (WDT_PRESCALER << 12)); + HT_WDT->MR0 = WDT_RELOAD | (WDT_RESET_ENABLE << 13) | (WDT_SLEEP_HALT << 14) | (0x1 << 16); + HT_WDT->CR = 0x5FA00001; +#else + #if (DEINIT_ENABLE == 1) + HT_RSTCU->APBPRST1 = (1 << 4); + #endif +#endif + + SetBit_BB((u32)(&HT_CKCU->APBCCR1), 6); /* enable Backup domain register clock */ + + #if (DEINIT_ENABLE == 1) + /* De-init the setting */ + HT_CKCU->AHBCCR &= ~(0x3 << 10); /* disable IP who may use PLL as source */ + SetBit_BB((u32)(&HT_CKCU->GCCR), 11); /* enable HSI */ + while (!GetBit_BB((u32)(&HT_CKCU->GCSR), 3)); /* wait for HSI ready */ + HT_CKCU->GCCR = ((HT_CKCU->GCCR & ~7UL) | 3UL); /* select CK_SYS source */ + while ((HT_CKCU->CKST & 7UL) != 3UL); /* wait for clock switch complete */ + HT_FLASH->CFCR = (((HT_FLASH->CFCR) & ~7UL) | 1UL); /* set Wait State as 0 WS */ + HT_CKCU->AHBCFGR = 0; /* set CK_AHB prescaler */ + ResetBit_BB((u32)(&HT_CKCU->GCCR), 9); /* disable PLL */ + SetBit_BB((u32)(&HT_CKCU->GCFGR), 8); /* select PLL source as HSI */ + ResetBit_BB((u32)(&HT_CKCU->GCCR), 3); /* disable USB PLL */ + SetBit_BB((u32)(&HT_CKCU->GCFGR), 9); /* select USB PLL source as HSI */ + #endif + + /* HSE initiation */ +#if (HSE_ENABLE == 1) + SetBit_BB((u32)(&HT_CKCU->GCCR), 10); /* enable HSE */ + while (!GetBit_BB((u32)(&HT_CKCU->GCSR), 2)){}; /* wait for HSE ready */ +#endif + + /* LSE initiation */ +#if (LSE_ENABLE == 1) + do { + SetBit_BB((u32)(&HT_RTC->CR), 3); /* enable LSE */ + } while (!GetBit_BB((u32)(&HT_RTC->CR), 3)); + while (!GetBit_BB((u32)(&HT_CKCU->GCSR), 4)); /* wait for LSE ready */ +#endif + + ResetBit_BB((u32)(&HT_CKCU->APBCCR1), 6); /* disable Backup domain register clock */ + + /* LSI initiation */ +#if (HCLK_SRC == 7) + while (!GetBit_BB((u32)(&HT_CKCU->GCSR), 5)){}; /* wait for LSI ready */ +#endif + + /* PLL initiation */ +#if (PLL_ENABLE == 1) + HT_CKCU->PLLCFGR = ((PLL_NF2_DIV & 0x0F) << 23) | (PLL_NO2_DIV << 21); /* set PLL divider */ + + #if (PLL_CLK_SRC_DIV == 1) + SetBit_BB((u32)(&HT_CKCU->PLLCFGR), 28); /* set PLL clock source divider */ + #else + ResetBit_BB((u32)(&HT_CKCU->PLLCFGR), 28); /* reset PLL clock source divider */ + #endif + + #if (PLL_CLK_SRC == 0) + ResetBit_BB((u32)(&HT_CKCU->GCFGR), 8); /* select PLL source as HSE */ + #else + SetBit_BB((u32)(&HT_CKCU->GCFGR), 8); /* select PLL source as HSI */ + #endif + + SetBit_BB((u32)(&HT_CKCU->GCCR), 9); /* enable PLL */ + while (!GetBit_BB((u32)(&HT_CKCU->GCSR), 1)){}; /* wait for PLL ready */ +#endif + + /* CK_AHB initiation */ +#if (WAIT_STATE == 9) + #if (__CK_AHB > WS1_CLK) + HT_FLASH->CFCR = (((HT_FLASH->CFCR) & ~7UL) | 3UL); /* auto-select wait state */ + #elif (__CK_AHB > WS0_CLK) + HT_FLASH->CFCR = (((HT_FLASH->CFCR) & ~7UL) | 2UL); /* auto-select wait state */ + #endif +#else + HT_FLASH->CFCR = (((HT_FLASH->CFCR) & ~7UL) | (WAIT_STATE + 1)); /* manual wait state */ +#endif + + HT_CKCU->AHBCFGR = HCLK_DIV; /* set CK_AHB prescaler */ + HT_CKCU->GCCR = ((HT_CKCU->GCCR & ~7UL) | HCLK_SRC); /* select CK_SYS source */ + while ((HT_CKCU->CKST & 7UL) != HCLK_SRC); /* wait for clock switch complete */ + + /* Pre-fetch buffer configuration */ +#if (PRE_FETCH_ENABLE == 0) + ResetBit_BB((u32)(&HT_FLASH->CFCR), 4); /* 0: pre-fetch disable, 1: pre-fetch enable */ +#else + SetBit_BB((u32)(&HT_FLASH->CFCR), 4); /* 0: pre-fetch disable, 1: pre-fetch enable */ +#endif + + /* HSE power down */ +#if ((HSE_ENABLE == 0) && (HCLK_SRC != 2) && ((PLL_ENABLE == 0) || (PLL_CLK_SRC == 1))) + ResetBit_BB((u32)(&HT_CKCU->GCCR), 10); +#endif + + /* HSI power down */ +#if ((HSI_ENABLE == 0) && (HCLK_SRC != 3) && ((PLL_ENABLE == 0) || (PLL_CLK_SRC == 0))) + ResetBit_BB((u32)(&HT_CKCU->GCCR), 11); +#endif +} + +/** + * @brief Update SystemCoreClock + * @retval None + */ +void SystemCoreClockUpdate(void) +{ + u32 SystemCoreClockDiv = HT_CKCU->AHBCFGR & 7UL; + u32 PllSourceClockDiv = (HT_CKCU->PLLCFGR >> 28) & 1UL; + u32 PllFeedbackClockDiv = (((HT_CKCU->PLLCFGR >> 23) & 15UL) == 0) ? (16) : ((HT_CKCU->PLLCFGR >> 23) & 15UL); + u32 PllOutputClockDiv = (HT_CKCU->PLLCFGR >> 21) & 3UL; + u32 SystemCoreClockSrc = HT_CKCU->CKST & 7UL; + + /* Get system core clock according to global clock control & configuration registers */ + if (SystemCoreClockSrc == 1) + { + if (GetBit_BB((u32)(&HT_CKCU->PLLCR), 31)) + { + PllFeedbackClockDiv = 1; + PllOutputClockDiv = 0; + } + + if (GetBit_BB((u32)(&HT_CKCU->GCFGR), 8)) + { + SystemCoreClock = (((HSI_VALUE >> PllSourceClockDiv) * PllFeedbackClockDiv) >> PllOutputClockDiv) >> SystemCoreClockDiv; + } + else + { + SystemCoreClock = (((HSE_VALUE >> PllSourceClockDiv) * PllFeedbackClockDiv) >> PllOutputClockDiv) >> SystemCoreClockDiv; + } + } + else if (SystemCoreClockSrc == 2) + { + SystemCoreClock = HSE_VALUE >> SystemCoreClockDiv; + } + else if (SystemCoreClockSrc == 3) + { + SystemCoreClock = HSI_VALUE >> SystemCoreClockDiv; + } + else if (SystemCoreClockSrc == 6) + { + SystemCoreClock = LSE_VALUE >> SystemCoreClockDiv; + } + else if (SystemCoreClockSrc == 7) + { + SystemCoreClock = LSI_VALUE >> SystemCoreClockDiv; + } +} + +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ + +/******************* (C) COPYRIGHT Holtek Semiconductor Inc. *****END OF FILE*** */ diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/system_ht32f5xxxx_07.c b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/system_ht32f5xxxx_07.c new file mode 100644 index 0000000000..3eb3d41a9c --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/system_ht32f5xxxx_07.c @@ -0,0 +1,482 @@ +/**************************************************************************//** + * @file library/Device/Holtek/HT32F5xxxx/Source/system_ht32f5xxxx_07.c + * @brief CMSIS Cortex-M0+ Device Peripheral Access Layer Source File + * for the Holtek HT32F5xxxx Device Series + * @version $Rev:: 6597 $ + * @date $Date:: 2022-12-27 #$ + * + * @note + * Copyright (C) Holtek Semiconductor Inc. All rights reserved. + * + * @par + * ARM Limited (ARM) supplies this software for Cortex-M processor-based + * microcontrollers. This file can be freely distributed within development + * tools that are supporting such ARM based processors. + * + * @par + * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR + * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + ******************************************************************************/ + +// Supported Device +// ======================================== +// HT32F0006 +// HT32F61352 +// HT32F61355 +// HT32F61356 +// HT32F61357 + +//#define USE_HT32F0006 +//#define USE_HT32F61352 +//#define USE_HT32F61355_56_57 + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup HT32F5xxxx_system HT32F5xxxx System + * @{ + */ + + +#include "ht32f5xxxx_01.h" + +/** @addtogroup HT32F5xxxx_System_Private_Defines + * @{ + */ +/* +//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ +*/ + +/*--------------------- Clock Configuration ---------------------------------- +// +// Enable High Speed External Crystal Oscillator (HSE) +// Default HSE = DISABLE +// +// Enable Low Speed External Crystal Oscillator (LSE) +// Default LSE = DISABLE +// +// Enable PLL +// Default PLL = DISABLE +// PLL Clock Source +// <0=> CK_HSE +// <1=> CK_HSI +// Default PLL clock source = CK_HSI +// PLL source clock must be in the range of 4 MHz to 16 MHz +// PLL Feedback Clock Divider (NF2): 1 ~ 16 +// <1-16:1> +// PLL feedback clock = PLL clock source x NF2 +// PLL feedback clock must be in the range of 24 MHz to 48 MHz +// PLL Output Clock Divider (NO2) +// <0=> 1 +// <1=> 2 +// <2=> 4 +// <3=> 8 +// PLL output clock = PLL feedback clock / NO2 +// PLL output clock must be in the range of 4 MHz to 48 MHz +// +// +// SystemCoreClock Configuration (CK_AHB) +// SystemCoreClock Source +// <1=> CK_PLL +// <2=> CK_HSE +// <3=> CK_HSI +// <6=> CK_LSE +// <7=> CK_LSI +// Default SystemCoreClock source = CK_HSI +// SystemCoreClock Source Divider +// <0=> 1 +// <1=> 2 +// <2=> 4 +// <3=> 8 +// <4=> 16 +// <5=> 32 +// Default SystemCoreClock source divider = 1 +// +// +// FLASH Configuration +// Wait state +// <0=> 0 WS +// <1=> 1 WS +// <9=> AUTO +// 0 WS: 1 kHz <= CK_AHB <= 24 MHz +// 1 WS: 24 MHz < CK_AHB <= 48 MHz +// Pre-fetch Buffer Enable +// Default pre-fetch buffer = ENABLE +// Branch cache Enable +// Default branch cache = ENABLE +// +*/ + +/* !!! NOTICE !!! + HSI must keep turn on when doing the Flash operation (Erase/Program). +*/ + +/* !!! NOTICE !!! + * How to adjust the value of High Speed External oscillator (HSE)? + The default value of HSE is define by "HSE_VALUE" in "ht32fxxxxx_nn.h". + If your board uses a different HSE speed, please add a new compiler preprocessor + C define, "HSE_VALUE=n000000" ("n" represents n MHz) in the toolchain/IDE, + or edit the "HSE_VALUE" in the "ht32f5xxxx_conf.h" file. + Take Keil MDK-ARM for instance, to set HSE as 16 MHz: + "Option of Taret -> C/C++ > Preprocessor Symbols" + Define: USE_HT32_DRIVER, USE_HT32Fxxxxx_SK, USE_HT32Fxxxxx_xx, USE_MEM_HT32Fxxxxx, HSE_VALUE=16000000 + ^^ Add "HSE_VALUE" + define as above. +*/ +#define HSI_ENABLE (1) /*!< 0: DISABLE, 1: ENABLE */ +#define HSE_ENABLE (1) /*!< 0: DISABLE, 1: ENABLE */ +#define LSI_ENABLE (1) /*!< 0: DISABLE, 1: ENABLE */ +#define LSE_ENABLE (0) /*!< 0: DISABLE, 1: ENABLE */ +#define PLL_ENABLE (1) /*!< 0: DISABLE, 1: ENABLE */ +#define PLL_CLK_SRC (0) /*!< 0: HSE, 1: HSI */ +#define PLL_NF2_DIV (4) /*!< 1~16: DIV1~DIV16 */ +#define PLL_NO2_DIV (0) /*!< 0: DIV1, 1: DIV2, 2: DIV4, 3: DIV8 */ +#define HCLK_SRC (1) /*!< 0: PLL, 1: PLL, 2: HSE, 3: HSI 6: LSE, 7: LSI */ +#define HCLK_DIV (0) /*!< 0: DIV1, 1: DIV2, 2: DIV4, 3: DIV8, 4: DIV16, 5: DIV32 */ +#define WAIT_STATE (9) /*!< 0: WS = 0, 1: WS = 1, 9: WS = AUTO */ +#define PRE_FETCH_ENABLE (1) /*!< 0: DISABLE, 1: ENABLE */ +#define BCACHE_ENABLE (1) /*!< 0: DISABLE, 1: ENABLE */ +#define DEINIT_ENABLE (1) /* Set 0 for reduce code size */ + +/*----------------------------------------------------------------------------------------------------------*/ +/* PLL Out = ((HSE or HSI) x PLL_NF2) / PLL_NO2 */ +/*----------------------------------------------------------------------------------------------------------*/ + + +/*--------------------- WDT Configuration ---------------------------------- +// +// Enable WDT Configuration +// WDT Prescaler Selection +// <0=> CK_WDT / 1 +// <1=> CK_WDT / 2 +// <2=> CK_WDT / 4 +// <3=> CK_WDT / 8 +// <4=> CK_WDT / 16 +// <5=> CK_WDT / 32 +// <6=> CK_WDT / 64 +// <7=> CK_WDT / 128 +// WDT Reload Value <1-4095:1> +// Enable WDT Reset function +// WDT Sleep Halt mode +// <0=> No halt +// <1=> Halt in DeepSleep1 +// <2=> Halt in Sleep & DeepSleep1 +// +*/ +#define WDT_ENABLE (0) /*!< 0: DISABLE, 1: ENABLE */ +#define WDT_PRESCALER (5) /*!< 0: 1/1, 1: 1/2, 2: 1/4, 3: 1/8, 4: 1/16, 5: 1/32, 6: 1/64, 7: 1/128 */ +#define WDT_RELOAD (2000) /*!< 0 ~ 4095, 12 bit */ +#define WDT_RESET_ENABLE (1) /*!< 0: No Reset, 1: Reset when WDT over flow */ +#define WDT_SLEEP_HALT (2) /*!< 0: No halt, 1: Halt in DeepSleep1, 2: Halt in Sleep & DeepSleep1 */ + +/** + * @brief Check HSI frequency + */ +#if (HSI_VALUE != 8000000UL) + #error "CK_HSI clock issue: must be 8 MHz!" +#endif + +/** + * @brief Check HSE frequency + */ +#if ((HSE_VALUE < 4000000UL) || (HSE_VALUE > 16000000UL)) + #error "CK_HSE clock issue: must be in the range of 4 MHz to 16 MHz!" +#endif + +/** + * @brief Check LSI frequency + */ +#if (LSI_VALUE != 32000UL) + #error "CK_LSI clock issue: must be 32 kHz!" +#endif + +/** + * @brief Check LSE frequency + */ +#if (LSE_VALUE != 32768UL) + #error "CK_LSE clock issue: must be 32.768 kHz!" +#endif + +/** + * @brief CK_PLL definition + */ +#if (PLL_ENABLE == 1) + /* Get CK_VCO frequency */ + #if (PLL_CLK_SRC == 1) + #if (HSI_ENABLE == 0) + #error "CK_PLL clock source issue: HSI has not been enabled" + #else + #define __CK_VCO (HSI_VALUE * PLL_NF2_DIV) /*!< Select HSI as PLL source */ + #endif + #else + #if (HSE_ENABLE == 0) + #error "CK_PLL clock source issue: HSE has not been enabled!" + #else + #define __CK_VCO (HSE_VALUE * PLL_NF2_DIV) /*!< Select HSE as PLL source */ + #endif + #endif + + #define VCO_MIN 24000000UL + #define VCO_MAX 48000000UL + #define PLL_MIN 4000000UL + #define PLL_MAX 48000000UL + + /* Check CK_VCO frequency */ + #if ((__CK_VCO < VCO_MIN) || (__CK_VCO > VCO_MAX)) + #error "CK_VCO clock issue: must be in the range!" + #endif + + #define __CK_PLL (__CK_VCO >> PLL_NO2_DIV) /*!< Get CK_PLL frequency */ + + /* Check CK_PLL frequency */ + #if ((__CK_PLL < PLL_MIN) || (__CK_PLL > PLL_MAX)) + #error "CK_PLL clock issue: must be in the range!" + #endif +#endif + +/** + * @brief CK_SYS definition + */ +#if (HCLK_SRC == 1) + #if (PLL_ENABLE == 1) + #define __CK_SYS __CK_PLL /*!< Select PLL as CK_SYS source */ + #else + #error "CK_SYS clock source issue: PLL is not enable!" + #endif +#elif (HCLK_SRC == 2) + #if (HSE_ENABLE == 1) + #define __CK_SYS HSE_VALUE /*!< Select HSE as CK_SYS source */ + #else + #error "CK_SYS clock source issue: HSE is not enable!" + #endif +#elif (HCLK_SRC == 3) + #if (HSI_ENABLE == 1) + #define __CK_SYS HSI_VALUE /*!< Select HSI as CK_SYS source */ + #else + #error "CK_SYS clock source issue: HSI is not enable!" + #endif +#elif (HCLK_SRC == 6) + #if (LSE_ENABLE == 1) + #define __CK_SYS LSE_VALUE /*!< Select LSE as CK_SYS source */ + #else + #error "CK_SYS clock source issue: LSE is not enable!" + #endif +#elif (HCLK_SRC == 7) + #if (LSI_ENABLE == 1) + #define __CK_SYS LSI_VALUE /*!< Select LSI as CK_SYS source */ + #else + #error "CK_SYS clock source issue: LSI is not enable!" + #endif +#else + #error "CK_SYS clock source issue: No clock source is selected!" +#endif + +/** + * @brief CK_AHB definition + */ +#define __CK_AHB (__CK_SYS >> HCLK_DIV) /*!< Get CK_AHB frequency */ + +#define CKAHB_MIN 1000UL +#define CKAHB_MAX 48000000UL +#define WS0_CLK 24000000UL + +/* Check CK_AHB frequency */ +#if ((__CK_AHB < CKAHB_MIN) || (__CK_AHB > CKAHB_MAX)) + #error "CK_AHB clock issue: must be in the range!" +#endif + +/* Check FLASH wait-state setting */ +#if ((__CK_AHB > WS0_CLK) && (WAIT_STATE < 1)) + #error "FLASH wait state configuration issue!" +#endif +/** + * @} + */ + +/** @addtogroup HT32F5xxxx_System_Private_Variables + * @{ + */ +__IO uint32_t SystemCoreClock = __CK_AHB; /*!< SystemCoreClock = CK_AHB */ +/** + * @} + */ + +/** @addtogroup HT32F5xxxx_System_Private_Functions + * @{ + */ + +/** + * @brief Setup the microcontroller system. + * Initializes the system clocks and the embedded Flash. + * @note This function should be used after reset. + * @retval None + */ +void SystemInit(void) +{ +#if (WDT_ENABLE == 1) + HT_CKCU->APBCCR1 |= (0x1 << 4); + HT_WDT->PR = 0x35CA; + HT_WDT->MR0 = 0; + HT_WDT->MR1 = ((HT_WDT->MR1 & 0xFFF) | (WDT_PRESCALER << 12)); + HT_WDT->MR0 = WDT_RELOAD | (WDT_RESET_ENABLE << 13) | (WDT_SLEEP_HALT << 14) | (0x1 << 16); + HT_WDT->CR = 0x5FA00001; +#else + #if (DEINIT_ENABLE == 1) + HT_RSTCU->APBPRST1 = (1 << 4); + #endif +#endif + + HT_CKCU->LPCR = 1; /* configure Backup domain isolation */ + SetBit_BB((u32)(&HT_CKCU->APBCCR1), 6); /* enable Backup domain register clock */ + while (HT_PWRCU->TEST != 0x27); /* wait for Backup domain register ready */ + + #if (DEINIT_ENABLE == 1) + /* De-init the setting */ + HT_CKCU->AHBCCR &= ~(0x3 << 10); /* disable IP who may use PLL as source */ + SetBit_BB((u32)(&HT_CKCU->GCCR), 11); /* enable HSI */ + while (!GetBit_BB((u32)(&HT_CKCU->GCSR), 3)); /* wait for HSI ready */ + HT_CKCU->GCCR = ((HT_CKCU->GCCR & ~7UL) | 3UL); /* select CK_SYS source */ + while ((HT_CKCU->CKST & 7UL) != 3UL); /* wait for clock switch complete */ + HT_FLASH->CFCR = (((HT_FLASH->CFCR) & ~7UL) | 1UL); /* set Wait State as 0 WS */ + HT_CKCU->AHBCFGR = 0; /* set CK_AHB prescaler */ + ResetBit_BB((u32)(&HT_CKCU->GCCR), 9); /* disable PLL */ + SetBit_BB((u32)(&HT_CKCU->GCFGR), 8); /* select PLL source as HSI */ + #endif + + /* HSE initiation */ +#if (HSE_ENABLE == 1) + SetBit_BB((u32)(&HT_CKCU->GCCR), 10); /* enable HSE */ + while (!GetBit_BB((u32)(&HT_CKCU->GCSR), 2)){}; /* wait for HSE ready */ +#endif + + /* LSE initiation */ +#if (LSE_ENABLE == 1) + do { + SetBit_BB((u32)(&HT_RTC->CR), 3); /* enable LSE */ + } while (!GetBit_BB((u32)(&HT_RTC->CR), 3)); + while (!GetBit_BB((u32)(&HT_CKCU->GCSR), 4)); /* wait for LSE ready */ +#endif + + ResetBit_BB((u32)(&HT_CKCU->APBCCR1), 6); /* disable Backup domain register clock */ + + /* LSI initiation */ +#if (HCLK_SRC == 7) + while (!GetBit_BB((u32)(&HT_CKCU->GCSR), 5)){}; /* wait for LSI ready */ +#endif + + /* PLL initiation */ +#if (PLL_ENABLE == 1) + #if (PLL_CLK_SRC == 0) + ResetBit_BB((u32)(&HT_CKCU->GCFGR), 8); /* select PLL source as HSE */ + #else + SetBit_BB((u32)(&HT_CKCU->GCFGR), 8); /* select PLL source as HSI */ + #endif + HT_CKCU->PLLCFGR = ((PLL_NF2_DIV & 0x0F) << 23) | (PLL_NO2_DIV << 21); /* set PLL divider */ + SetBit_BB((u32)(&HT_CKCU->GCCR), 9); /* enable PLL */ + while (!GetBit_BB((u32)(&HT_CKCU->GCSR), 1)){}; /* wait for PLL ready */ +#endif + + /* CK_AHB initiation */ +#if (WAIT_STATE == 9) + #if (__CK_AHB > WS0_CLK) + HT_FLASH->CFCR = (((HT_FLASH->CFCR) & ~7UL) | 2UL); /* auto-select wait state */ + #endif +#else + HT_FLASH->CFCR = (((HT_FLASH->CFCR) & ~7UL) | (WAIT_STATE + 1)); /* manual wait state */ +#endif + + HT_CKCU->AHBCFGR = HCLK_DIV; /* set CK_AHB prescaler */ + HT_CKCU->GCCR = ((HT_CKCU->GCCR & ~7UL) | HCLK_SRC); /* select CK_SYS source */ + while ((HT_CKCU->CKST & 7UL) != HCLK_SRC); /* wait for clock switch complete */ + + /* Pre-fetch buffer configuration */ +#if (PRE_FETCH_ENABLE == 0) + ResetBit_BB((u32)(&HT_FLASH->CFCR), 4); /* 0: pre-fetch disable, 1: pre-fetch enable */ +#else + SetBit_BB((u32)(&HT_FLASH->CFCR), 4); /* 0: pre-fetch disable, 1: pre-fetch enable */ +#endif + + /* Branch cache configuration */ +#if (BCACHE_ENABLE == 0) + ResetBit_BB((u32)(&HT_FLASH->CFCR), 12); /* 0: branch cache disable, 1: branch cache enable */ +#else + SetBit_BB((u32)(&HT_FLASH->CFCR), 12); /* 0: branch cache disable, 1: branch cache enable */ +#endif + + /* HSE power down */ +#if ((HSE_ENABLE == 0) && (HCLK_SRC != 2) && ((PLL_ENABLE == 0) || (PLL_CLK_SRC == 1))) + ResetBit_BB((u32)(&HT_CKCU->GCCR), 10); +#endif + + /* HSI power down */ +#if ((HSI_ENABLE == 0) && (HCLK_SRC != 3) && ((PLL_ENABLE == 0) || (PLL_CLK_SRC == 0))) + ResetBit_BB((u32)(&HT_CKCU->GCCR), 11); +#endif +} + +/** + * @brief Update SystemCoreClock + * @retval None + */ +void SystemCoreClockUpdate(void) +{ + u32 SystemCoreClockDiv = HT_CKCU->AHBCFGR & 7UL; + u32 PllFeedbackClockDiv = ((HT_CKCU->PLLCFGR >> 23) == 0) ? (16) : (HT_CKCU->PLLCFGR >> 23); + u32 PllOutputClockDiv = (HT_CKCU->PLLCFGR >> 21) & 3UL; + u32 SystemCoreClockSrc = HT_CKCU->CKST & 7UL; + + /* Get system core clock according to global clock control & configuration registers */ + if (SystemCoreClockSrc == 1) + { + if (GetBit_BB((u32)(&HT_CKCU->PLLCR), 31)) + { + PllFeedbackClockDiv = 1; + PllOutputClockDiv = 0; + } + + if (GetBit_BB((u32)(&HT_CKCU->GCFGR), 8)) + { + SystemCoreClock = ((HSI_VALUE * PllFeedbackClockDiv) >> PllOutputClockDiv) >> SystemCoreClockDiv; + } + else + { + SystemCoreClock = ((HSE_VALUE * PllFeedbackClockDiv) >> PllOutputClockDiv) >> SystemCoreClockDiv; + } + } + else if (SystemCoreClockSrc == 2) + { + SystemCoreClock = HSE_VALUE >> SystemCoreClockDiv; + } + else if (SystemCoreClockSrc == 3) + { + SystemCoreClock = HSI_VALUE >> SystemCoreClockDiv; + } + else if (SystemCoreClockSrc == 6) + { + SystemCoreClock = LSE_VALUE >> SystemCoreClockDiv; + } + else if (SystemCoreClockSrc == 7) + { + SystemCoreClock = LSI_VALUE >> SystemCoreClockDiv; + } +} + +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ + +/******************* (C) COPYRIGHT Holtek Semiconductor Inc. *****END OF FILE*** */ diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/system_ht32f5xxxx_08.c b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/system_ht32f5xxxx_08.c new file mode 100644 index 0000000000..e20480f1ed --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/system_ht32f5xxxx_08.c @@ -0,0 +1,518 @@ +/**************************************************************************//** + * @file library/Device/Holtek/HT32F5xxxx/Source/system_ht32f5xxxx_08.c + * @brief CMSIS Cortex-M0+ Device Peripheral Access Layer Source File + * for the Holtek HT32F5xxxx Device Series + * @version $Rev:: 6877 $ + * @date $Date:: 2023-05-04 #$ + * + * @note + * Copyright (C) Holtek Semiconductor Inc. All rights reserved. + * + * @par + * ARM Limited (ARM) supplies this software for Cortex-M processor-based + * microcontrollers. This file can be freely distributed within development + * tools that are supporting such ARM based processors. + * + * @par + * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR + * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + ******************************************************************************/ + +// Supported Device +// ======================================== +// HT32F65230, HT32F65240 +// HT32F65232 +// MXTX6306 +// HT50F3200S + +//#define USE_HT32F65230_40 +//#define USE_HT32F65232 +//#define USE_MXTX6306 +//#define USE_HT50F3200S + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup HT32F5xxxx_system HT32F5xxxx System + * @{ + */ + + +#include "ht32f5xxxx_01.h" + +/** @addtogroup HT32F5xxxx_System_Private_Defines + * @{ + */ +/* +//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ +*/ + +/*--------------------- Clock Configuration ---------------------------------- +// +// Enable High Speed External Crystal Oscillator (HSE) +// Default HSE = DISABLE +// +// Enable Low Speed External Crystal Oscillator (LSE) +// Default LSE = DISABLE +// HT32F65230/65240, MXTX6306, HT50F3200S Only +// +// Enable PLL +// Default PLL = DISABLE +// PLL Out = (((HSE or HSI) / SRC_DIV) x NF2 ) / NO2 +// PLL Clock Source +// <0=> CK_HSE +// <1=> CK_HSI +// Default PLL clock source = CK_HSI +// PLL source clock must be in the range of 4 MHz to 16 MHz +// PLL Clock Source Divider (SRC_DIV) +// <0=> 1 +// <1=> 2 +// PLL input clock = PLL Clock Source / (SRC_DIV) +// PLL Feedback Clock Divider (NF2): 1 ~ 16 +// <1-16:1> +// PLL feedback clock = PLL input clock x NF2 +// PLL feedback clock must be in the range of 24 MHz to 60 MHz +// PLL Output Clock Divider (NO2) +// <0=> 1 +// <1=> 2 +// <2=> 4 +// <3=> 8 +// PLL output clock = PLL feedback clock / NO2 +// PLL output clock must be in the range of 4 MHz to 60 MHz +// +// +// SystemCoreClock Configuration (CK_AHB) +// SystemCoreClock Source +// <1=> CK_PLL +// <2=> CK_HSE +// <3=> CK_HSI +// <6=> CK_LSE (HT32F65230/65240, MXTX6306, HT50F3200S Only) +// <7=> CK_LSI +// Default SystemCoreClock source = CK_HSI +// SystemCoreClock Source Divider +// <0=> 1 +// <1=> 2 +// <2=> 4 +// <3=> 8 +// <4=> 16 +// <5=> 32 +// Default SystemCoreClock source divider = 1 +// +// +// FLASH Configuration +// Wait state +// <0=> 0 WS +// <1=> 1 WS +// <2=> 2 WS +// <9=> AUTO +// 0 WS: 1 kHz <= CK_AHB <= 20 MHz +// 1 WS: 20 MHz < CK_AHB <= 40 MHz +// 2 WS: 40 MHz < CK_AHB <= 60 MHz +// Pre-fetch Buffer Enable +// Default pre-fetch buffer = ENABLE +// Branch cache Enable (HT32F52357/67, HT32F65230/40, MXTX6306, HT50F3200S Only) +// Default branch cache = ENABLE +// +*/ + +/* !!! NOTICE !!! + HSI must keep turn on when doing the Flash operation (Erase/Program). +*/ + +/* !!! NOTICE !!! + * How to adjust the value of High Speed External oscillator (HSE)? + The default value of HSE is define by "HSE_VALUE" in "ht32fxxxxx_nn.h". + If your board uses a different HSE speed, please add a new compiler preprocessor + C define, "HSE_VALUE=n000000" ("n" represents n MHz) in the toolchain/IDE, + or edit the "HSE_VALUE" in the "ht32f5xxxx_conf.h" file. + Take Keil MDK-ARM for instance, to set HSE as 16 MHz: + "Option of Taret -> C/C++ > Preprocessor Symbols" + Define: USE_HT32_DRIVER, USE_HT32Fxxxxx_SK, USE_HT32Fxxxxx_xx, USE_MEM_HT32Fxxxxx, HSE_VALUE=16000000 + ^^ Add "HSE_VALUE" + define as above. +*/ +#define HSI_ENABLE (1) /*!< 0: DISABLE, 1: ENABLE */ +#define HSE_ENABLE (1) /*!< 0: DISABLE, 1: ENABLE */ +#define LSI_ENABLE (1) /*!< 0: DISABLE, 1: ENABLE */ +#define LSE_ENABLE (0) /*!< 0: DISABLE, 1: ENABLE */ +#define PLL_ENABLE (1) /*!< 0: DISABLE, 1: ENABLE */ +#define PLL_CLK_SRC (0) /*!< 0: HSE, 1: HSI */ +#define PLL_CLK_SRC_DIV (1) /*!< 0: DIV1, 1: DIV2 */ +#define PLL_NF2_DIV (15) /*!< 1~16: DIV1~DIV16 */ +#define PLL_NO2_DIV (0) /*!< 0: DIV1, 1: DIV2, 2: DIV4, 3: DIV8 */ +#define HCLK_SRC (1) /*!< 0: PLL, 1: PLL, 2: HSE, 3: HSI 6: LSE, 7: LSI */ +#define HCLK_DIV (0) /*!< 0: DIV1, 1: DIV2, 2: DIV4, 3: DIV8, 4: DIV16, 5: DIV32 */ +#define WAIT_STATE (9) /*!< 0: WS = 0, 1: WS = 1, 2: WS = 2, 9: AUTO */ +#define PRE_FETCH_ENABLE (1) /*!< 0: DISABLE, 1: ENABLE */ +#define BCACHE_ENABLE (1) /*!< 0: DISABLE, 1: ENABLE */ +#define DEINIT_ENABLE (1) /* Set 0 for reduce code size */ + +/*----------------------------------------------------------------------------------------------------------*/ +/* PLL Out = (((HSE or HSI) / (PLL_CLK_SRC_DIV + 1)) x PLL_NF2) / PLL_NO2 */ +/*----------------------------------------------------------------------------------------------------------*/ + + +/*--------------------- WDT Configuration ---------------------------------- +// +// Enable WDT Configuration +// WDT Prescaler Selection +// <0=> CK_WDT / 1 +// <1=> CK_WDT / 2 +// <2=> CK_WDT / 4 +// <3=> CK_WDT / 8 +// <4=> CK_WDT / 16 +// <5=> CK_WDT / 32 +// <6=> CK_WDT / 64 +// <7=> CK_WDT / 128 +// WDT Reload Value <1-4095:1> +// Enable WDT Reset function +// WDT Sleep Halt mode +// <0=> No halt +// <1=> Halt in DeepSleep1 +// <2=> Halt in Sleep & DeepSleep1 +// +*/ +#define WDT_ENABLE (0) /*!< 0: DISABLE, 1: ENABLE */ +#define WDT_PRESCALER (5) /*!< 0: 1/1, 1: 1/2, 2: 1/4, 3: 1/8, 4: 1/16, 5: 1/32, 6: 1/64, 7: 1/128 */ +#define WDT_RELOAD (2000) /*!< 0 ~ 4095, 12 bit */ +#define WDT_RESET_ENABLE (1) /*!< 0: No Reset, 1: Reset when WDT over flow */ +#define WDT_SLEEP_HALT (2) /*!< 0: No halt, 1: Halt in DeepSleep1, 2: Halt in Sleep & DeepSleep1 */ + +/** + * @brief Check HSI frequency + */ +#if (HSI_VALUE != 8000000UL) + #error "CK_HSI clock issue: must be 8 MHz!" +#endif + +/** + * @brief Check HSE frequency + */ +#if ((HSE_VALUE < 4000000UL) || (HSE_VALUE > 16000000UL)) + #error "CK_HSE clock issue: must be in the range of 4 MHz to 16 MHz!" +#endif + +/** + * @brief Check LSI frequency + */ +#if (LSI_VALUE != 32000UL) + #error "CK_LSI clock issue: must be 32 kHz!" +#endif + +/** + * @brief Check LSE frequency + */ +#if defined(USE_HT32F65230_40) +#if (LSE_VALUE != 32768UL) + #error "CK_LSE clock issue: must be 32.768 kHz!" +#endif +#endif +#if defined(USE_HT32F65232) + #if (LSE_ENABLE == 1) + #error "Dose not support LSE!" + #endif +#endif + +/** + * @brief CK_PLL definition + */ +#if (PLL_ENABLE == 1) + /* Get CK_VCO frequency */ + #if (PLL_CLK_SRC == 1) + #if (HSI_ENABLE == 0) + #error "CK_PLL clock source issue: HSI has not been enabled" + #else + #define __CK_VCO ((HSI_VALUE >> PLL_CLK_SRC_DIV) * PLL_NF2_DIV) /*!< Select HSI as PLL source */ + #endif + #else + #if (HSE_ENABLE == 0) + #error "CK_PLL clock source issue: HSE has not been enabled!" + #else + #define __CK_VCO ((HSE_VALUE >> PLL_CLK_SRC_DIV) * PLL_NF2_DIV) /*!< Select HSE as PLL source */ + #endif + #endif + + #define VCO_MIN 24000000UL + #define VCO_MAX 60000000UL + #define PLL_MIN 4000000UL + #define PLL_MAX 60000000UL + + /* Check CK_VCO frequency */ + #if ((__CK_VCO < VCO_MIN) || (__CK_VCO > VCO_MAX)) + #error "CK_VCO clock issue: must be in the range!" + #endif + + #define __CK_PLL (__CK_VCO >> PLL_NO2_DIV) /*!< Get CK_PLL frequency */ + + /* Check CK_PLL frequency */ + #if ((__CK_PLL < PLL_MIN) || (__CK_PLL > PLL_MAX)) + #error "CK_PLL clock issue: must be in the range!" + #endif +#endif + +/** + * @brief CK_SYS definition + */ +#if (HCLK_SRC == 1) + #if (PLL_ENABLE == 1) + #define __CK_SYS __CK_PLL /*!< Select PLL as CK_SYS source */ + #else + #error "CK_SYS clock source issue: PLL is not enable!" + #endif +#elif (HCLK_SRC == 2) + #if (HSE_ENABLE == 1) + #define __CK_SYS HSE_VALUE /*!< Select HSE as CK_SYS source */ + #else + #error "CK_SYS clock source issue: HSE is not enable!" + #endif +#elif (HCLK_SRC == 3) + #if (HSI_ENABLE == 1) + #define __CK_SYS HSI_VALUE /*!< Select HSI as CK_SYS source */ + #else + #error "CK_SYS clock source issue: HSI is not enable!" + #endif +#elif (HCLK_SRC == 6) + #if defined(USE_HT32F65230_40) + #if (LSE_ENABLE == 1) + #define __CK_SYS LSE_VALUE /*!< Select LSE as CK_SYS source */ + #else + #error "CK_SYS clock source issue: LSE is not enable!" + #endif + #if defined(USE_HT32F65232) + #error "Dose not support LSE!" + #endif + #endif +#elif (HCLK_SRC == 7) + #if (LSI_ENABLE == 1) + #define __CK_SYS LSI_VALUE /*!< Select LSI as CK_SYS source */ + #else + #error "CK_SYS clock source issue: LSI is not enable!" + #endif +#else + #error "CK_SYS clock source issue: No clock source is selected!" +#endif + +/** + * @brief CK_AHB definition + */ +#define __CK_AHB (__CK_SYS >> HCLK_DIV) /*!< Get CK_AHB frequency */ + +#define CKAHB_MIN 1000UL +#define CKAHB_MAX 60000000UL +#define WS0_CLK 20000000UL +#define WS1_CLK 40000000UL + +/* Check CK_AHB frequency */ +#if ((__CK_AHB < CKAHB_MIN) || (__CK_AHB > CKAHB_MAX)) + #error "CK_AHB clock issue: must be in the range!" +#endif + +/* Check FLASH wait-state setting */ +#if ((__CK_AHB > WS1_CLK) && (WAIT_STATE < 2) || \ + (__CK_AHB > WS0_CLK) && (WAIT_STATE < 1)) + #error "FLASH wait state configuration issue!" +#endif +/** + * @} + */ + +/** @addtogroup HT32F5xxxx_System_Private_Variables + * @{ + */ +__IO uint32_t SystemCoreClock = __CK_AHB; /*!< SystemCoreClock = CK_AHB */ +/** + * @} + */ + +/** @addtogroup HT32F5xxxx_System_Private_Functions + * @{ + */ + +/** + * @brief Setup the microcontroller system. + * Initializes the system clocks and the embedded Flash. + * @note This function should be used after reset. + * @retval None + */ +void SystemInit(void) +{ +#if (WDT_ENABLE == 1) + HT_CKCU->APBCCR1 |= (0x1 << 4); + HT_WDT->PR = 0x35CA; + HT_WDT->MR0 = 0; + HT_WDT->MR1 = ((HT_WDT->MR1 & 0xFFF) | (WDT_PRESCALER << 12)); + HT_WDT->MR0 = WDT_RELOAD | (WDT_RESET_ENABLE << 13) | (WDT_SLEEP_HALT << 14) | (0x1 << 16); + HT_WDT->CR = 0x5FA00001; +#else + #if (DEINIT_ENABLE == 1) + HT_RSTCU->APBPRST1 = (1 << 4); + #endif +#endif + + SetBit_BB((u32)(&HT_CKCU->APBCCR1), 6); /* enable VDD power domain register clock */ + + #if (DEINIT_ENABLE == 1) + /* De-init the setting */ + HT_CKCU->AHBCCR &= ~(0x3 << 10); /* disable IP who may use PLL as source */ + SetBit_BB((u32)(&HT_CKCU->GCCR), 11); /* enable HSI */ + while (!GetBit_BB((u32)(&HT_CKCU->GCSR), 3)); /* wait for HSI ready */ + HT_CKCU->GCCR = ((HT_CKCU->GCCR & ~7UL) | 3UL); /* select CK_SYS source */ + while ((HT_CKCU->CKST & 7UL) != 3UL); /* wait for clock switch complete */ + HT_FLASH->CFCR = (((HT_FLASH->CFCR) & ~7UL) | 1UL); /* set Wait State as 0 WS */ + HT_CKCU->AHBCFGR = 0; /* set CK_AHB prescaler */ + ResetBit_BB((u32)(&HT_CKCU->GCCR), 9); /* disable PLL */ + SetBit_BB((u32)(&HT_CKCU->GCFGR), 8); /* select PLL source as HSI */ + #endif + + /* HSE initiation */ +#if (HSE_ENABLE == 1) + SetBit_BB((u32)(&HT_CKCU->GCCR), 10); /* enable HSE */ + while (!GetBit_BB((u32)(&HT_CKCU->GCSR), 2)){}; /* wait for HSE ready */ +#endif + + /* LSE initiation */ +#if defined(USE_HT32F65230_40) +#if (LSE_ENABLE == 1) + do { + SetBit_BB((u32)(&HT_RTC->CR), 3); /* enable LSE */ + } while (!GetBit_BB((u32)(&HT_RTC->CR), 3)); + while (!GetBit_BB((u32)(&HT_CKCU->GCSR), 4)); /* wait for LSE ready */ +#endif +#endif + + ResetBit_BB((u32)(&HT_CKCU->APBCCR1), 6); /* disable VDD power domain register clock */ + + /* LSI initiation */ +#if (HCLK_SRC == 7) + while (!GetBit_BB((u32)(&HT_CKCU->GCSR), 5)){}; /* wait for LSI ready */ +#endif + + /* PLL initiation */ +#if (PLL_ENABLE == 1) + HT_CKCU->PLLCFGR = ((PLL_NF2_DIV & 0x0F) << 23) | (PLL_NO2_DIV << 21); /* set PLL divider */ + + #if (PLL_CLK_SRC_DIV == 1) + SetBit_BB((u32)(&HT_CKCU->PLLCFGR), 28); /* set PLL clock source divider */ + #else + ResetBit_BB((u32)(&HT_CKCU->PLLCFGR), 28); /* reset PLL clock source divider */ + #endif + + #if (PLL_CLK_SRC == 0) + ResetBit_BB((u32)(&HT_CKCU->GCFGR), 8); /* select PLL source as HSE */ + #else + SetBit_BB((u32)(&HT_CKCU->GCFGR), 8); /* select PLL source as HSI */ + #endif + + SetBit_BB((u32)(&HT_CKCU->GCCR), 9); /* enable PLL */ + while (!GetBit_BB((u32)(&HT_CKCU->GCSR), 1)){}; /* wait for PLL ready */ +#endif + + /* CK_AHB initiation */ +#if (WAIT_STATE == 9) + #if (__CK_AHB > WS1_CLK) + HT_FLASH->CFCR = (((HT_FLASH->CFCR) & ~7UL) | 3UL); /* auto-select wait state */ + #elif (__CK_AHB > WS0_CLK) + HT_FLASH->CFCR = (((HT_FLASH->CFCR) & ~7UL) | 2UL); /* auto-select wait state */ + #endif +#else + HT_FLASH->CFCR = (((HT_FLASH->CFCR) & ~7UL) | (WAIT_STATE + 1)); /* manual wait state */ +#endif + + HT_CKCU->AHBCFGR = HCLK_DIV; /* set CK_AHB prescaler */ + HT_CKCU->GCCR = ((HT_CKCU->GCCR & ~7UL) | HCLK_SRC); /* select CK_SYS source */ + while ((HT_CKCU->CKST & 7UL) != HCLK_SRC); /* wait for clock switch complete */ + + /* Pre-fetch buffer configuration */ +#if (PRE_FETCH_ENABLE == 0) + ResetBit_BB((u32)(&HT_FLASH->CFCR), 4); /* 0: pre-fetch disable, 1: pre-fetch enable */ +#else + SetBit_BB((u32)(&HT_FLASH->CFCR), 4); /* 0: pre-fetch disable, 1: pre-fetch enable */ +#endif + + /* Branch cache configuration */ +#if (BCACHE_ENABLE == 0) + ResetBit_BB((u32)(&HT_FLASH->CFCR), 12); /* 0: branch cache disable, 1: branch cache enable */ +#else + SetBit_BB((u32)(&HT_FLASH->CFCR), 12); /* 0: branch cache disable, 1: branch cache enable */ +#endif + + /* HSE power down */ +#if ((HSE_ENABLE == 0) && (HCLK_SRC != 2) && ((PLL_ENABLE == 0) || (PLL_CLK_SRC == 1))) + ResetBit_BB((u32)(&HT_CKCU->GCCR), 10); +#endif + + /* HSI power down */ +#if ((HSI_ENABLE == 0) && (HCLK_SRC != 3) && ((PLL_ENABLE == 0) || (PLL_CLK_SRC == 0))) + ResetBit_BB((u32)(&HT_CKCU->GCCR), 11); +#endif +} + +/** + * @brief Update SystemCoreClock + * @retval None + */ +void SystemCoreClockUpdate(void) +{ + u32 SystemCoreClockDiv = HT_CKCU->AHBCFGR & 7UL; + u32 PllSourceClockDiv = (HT_CKCU->PLLCFGR >> 28) & 1UL; + u32 PllFeedbackClockDiv = (((HT_CKCU->PLLCFGR >> 23) & 15UL) == 0) ? (16) : ((HT_CKCU->PLLCFGR >> 23) & 15UL); + u32 PllOutputClockDiv = (HT_CKCU->PLLCFGR >> 21) & 3UL; + u32 SystemCoreClockSrc = HT_CKCU->CKST & 7UL; + + /* Get system core clock according to global clock control & configuration registers */ + if (SystemCoreClockSrc == 1) + { + if (GetBit_BB((u32)(&HT_CKCU->PLLCR), 31)) + { + PllFeedbackClockDiv = 1; + PllOutputClockDiv = 0; + } + + if (GetBit_BB((u32)(&HT_CKCU->GCFGR), 8)) + { + SystemCoreClock = (((HSI_VALUE >> PllSourceClockDiv) * PllFeedbackClockDiv) >> PllOutputClockDiv) >> SystemCoreClockDiv; + } + else + { + SystemCoreClock = (((HSE_VALUE >> PllSourceClockDiv) * PllFeedbackClockDiv) >> PllOutputClockDiv) >> SystemCoreClockDiv; + } + } + else if (SystemCoreClockSrc == 2) + { + SystemCoreClock = HSE_VALUE >> SystemCoreClockDiv; + } + else if (SystemCoreClockSrc == 3) + { + SystemCoreClock = HSI_VALUE >> SystemCoreClockDiv; + } + #if defined(USE_HT32F65230_40) + else if (SystemCoreClockSrc == 6) + { + SystemCoreClock = LSE_VALUE >> SystemCoreClockDiv; + } + #endif + else if (SystemCoreClockSrc == 7) + { + SystemCoreClock = LSI_VALUE >> SystemCoreClockDiv; + } +} + +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ + +/******************* (C) COPYRIGHT Holtek Semiconductor Inc. *****END OF FILE*** */ diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/system_ht32f5xxxx_09.c b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/system_ht32f5xxxx_09.c new file mode 100644 index 0000000000..a7b5f24091 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/system_ht32f5xxxx_09.c @@ -0,0 +1,489 @@ +/**************************************************************************//** + * @file library/Device/Holtek/HT32F5xxxx/Source/system_ht32f5xxxx_09.c + * @brief CMSIS Cortex-M0+ Device Peripheral Access Layer Source File + * for the Holtek HT32F5xxxx Device Series + * @version $Rev:: 6597 $ + * @date $Date:: 2022-12-27 #$ + * + * @note + * Copyright (C) Holtek Semiconductor Inc. All rights reserved. + * + * @par + * ARM Limited (ARM) supplies this software for Cortex-M processor-based + * microcontrollers. This file can be freely distributed within development + * tools that are supporting such ARM based processors. + * + * @par + * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR + * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + ******************************************************************************/ + +// Supported Device +// ======================================== +// HT32F54231, HT32F54241 +// HT32F54243, HT32F54253 + +//#define USE_HT32F54231_41 +//#define USE_HT32F54243_53 + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup HT32F5xxxx_system HT32F5xxxx System + * @{ + */ + + +#include "ht32f5xxxx_01.h" + +/** @addtogroup HT32F5xxxx_System_Private_Defines + * @{ + */ +/* +//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ +*/ + +/*--------------------- Clock Configuration ---------------------------------- +// +// Enable High Speed External Crystal Oscillator (HSE) +// Default HSE = DISABLE +// +// Enable Low Speed External Crystal Oscillator (LSE) +// Default LSE = DISABLE +// +// Enable PLL +// Default PLL = DISABLE +// PLL Out = (((HSE or HSI) / SRC_DIV) x NF2 ) / NO2 +// PLL Clock Source +// <0=> CK_HSE +// <1=> CK_HSI +// Default PLL clock source = CK_HSI +// PLL source clock must be in the range of 4 MHz to 16 MHz +// PLL Clock Source Divider (SRC_DIV) +// <0=> 1 +// <1=> 2 +// PLL input clock = PLL Clock Source / (SRC_DIV) +// PLL Feedback Clock Divider (NF2): 1 ~ 16 +// <1-16:1> +// PLL feedback clock = PLL input clock x NF2 +// PLL feedback clock must be in the range of 24 MHz to 60 MHz +// PLL Output Clock Divider (NO2) +// <0=> 1 +// <1=> 2 +// <2=> 4 +// <3=> 8 +// PLL output clock = PLL feedback clock / NO2 +// PLL output clock must be in the range of 4 MHz to 60 MHz +// +// +// SystemCoreClock Configuration (CK_AHB) +// SystemCoreClock Source +// <1=> CK_PLL +// <2=> CK_HSE +// <3=> CK_HSI +// <6=> CK_LSE +// <7=> CK_LSI +// Default SystemCoreClock source = CK_HSI +// SystemCoreClock Source Divider +// <0=> 1 +// <1=> 2 +// <2=> 4 +// <3=> 8 +// <4=> 16 +// <5=> 32 +// Default SystemCoreClock source divider = 1 +// +// +// FLASH Configuration +// Wait state +// <0=> 0 WS +// <1=> 1 WS +// <2=> 2 WS +// <9=> AUTO +// 0 WS: 1 kHz <= CK_AHB <= 20 MHz +// 1 WS: 20 MHz < CK_AHB <= 40 MHz +// 2 WS: 40 MHz < CK_AHB <= 60 MHz +// Pre-fetch Buffer Enable +// Default pre-fetch buffer = ENABLE +// +*/ + +/* !!! NOTICE !!! + HSI must keep turn on when doing the Flash operation (Erase/Program). +*/ + +/* !!! NOTICE !!! + * How to adjust the value of High Speed External oscillator (HSE)? + The default value of HSE is define by "HSE_VALUE" in "ht32fxxxxx_nn.h". + If your board uses a different HSE speed, please add a new compiler preprocessor + C define, "HSE_VALUE=n000000" ("n" represents n MHz) in the toolchain/IDE, + or edit the "HSE_VALUE" in the "ht32f5xxxx_conf.h" file. + Take Keil MDK-ARM for instance, to set HSE as 16 MHz: + "Option of Taret -> C/C++ > Preprocessor Symbols" + Define: USE_HT32_DRIVER, USE_HT32Fxxxxx_SK, USE_HT32Fxxxxx_xx, USE_MEM_HT32Fxxxxx, HSE_VALUE=16000000 + ^^ Add "HSE_VALUE" + define as above. +*/ +#define HSI_ENABLE (1) /*!< 0: DISABLE, 1: ENABLE */ +#define HSE_ENABLE (1) /*!< 0: DISABLE, 1: ENABLE */ +#define LSI_ENABLE (1) /*!< 0: DISABLE, 1: ENABLE */ +#define LSE_ENABLE (0) /*!< 0: DISABLE, 1: ENABLE */ +#define PLL_ENABLE (1) /*!< 0: DISABLE, 1: ENABLE */ +#define PLL_CLK_SRC (0) /*!< 0: HSE, 1: HSI */ +#define PLL_CLK_SRC_DIV (1) /*!< 0: DIV1, 1: DIV2 */ +#define PLL_NF2_DIV (15) /*!< 1~16: DIV1~DIV16 */ +#define PLL_NO2_DIV (0) /*!< 0: DIV1, 1: DIV2, 2: DIV4, 3: DIV8 */ +#define HCLK_SRC (1) /*!< 0: PLL, 1: PLL, 2: HSE, 3: HSI 6: LSE, 7: LSI */ +#define HCLK_DIV (0) /*!< 0: DIV1, 1: DIV2, 2: DIV4, 3: DIV8, 4: DIV16, 5: DIV32 */ +#define WAIT_STATE (9) /*!< 0: WS = 0, 1: WS = 1, 2: WS = 2, 9: AUTO */ +#define PRE_FETCH_ENABLE (1) /*!< 0: DISABLE, 1: ENABLE */ +#define DEINIT_ENABLE (1) /* Set 0 for reduce code size */ + +/*----------------------------------------------------------------------------------------------------------*/ +/* PLL Out = (((HSE or HSI) / (PLL_CLK_SRC_DIV + 1)) x PLL_NF2) / PLL_NO2 */ +/*----------------------------------------------------------------------------------------------------------*/ + + +/*--------------------- WDT Configuration ---------------------------------- +// +// Enable WDT Configuration +// WDT Prescaler Selection +// <0=> CK_WDT / 1 +// <1=> CK_WDT / 2 +// <2=> CK_WDT / 4 +// <3=> CK_WDT / 8 +// <4=> CK_WDT / 16 +// <5=> CK_WDT / 32 +// <6=> CK_WDT / 64 +// <7=> CK_WDT / 128 +// WDT Reload Value <1-4095:1> +// Enable WDT Reset function +// WDT Sleep Halt mode +// <0=> No halt +// <1=> Halt in DeepSleep1 +// <2=> Halt in Sleep & DeepSleep1 +// +*/ +#define WDT_ENABLE (0) /*!< 0: DISABLE, 1: ENABLE */ +#define WDT_PRESCALER (5) /*!< 0: 1/1, 1: 1/2, 2: 1/4, 3: 1/8, 4: 1/16, 5: 1/32, 6: 1/64, 7: 1/128 */ +#define WDT_RELOAD (2000) /*!< 0 ~ 4095, 12 bit */ +#define WDT_RESET_ENABLE (1) /*!< 0: No Reset, 1: Reset when WDT over flow */ +#define WDT_SLEEP_HALT (2) /*!< 0: No halt, 1: Halt in DeepSleep1, 2: Halt in Sleep & DeepSleep1 */ + +/** + * @brief Check HSI frequency + */ +#if (HSI_VALUE != 8000000UL) + #error "CK_HSI clock issue: must be 8 MHz!" +#endif + +/** + * @brief Check HSE frequency + */ +#if ((HSE_VALUE < 4000000UL) || (HSE_VALUE > 16000000UL)) + #error "CK_HSE clock issue: must be in the range of 4 MHz to 16 MHz!" +#endif + +/** + * @brief Check LSI frequency + */ +#if (LSI_VALUE != 32000UL) + #error "CK_LSI clock issue: must be 32 kHz!" +#endif + +/** + * @brief Check LSE frequency + */ +#if (LSE_VALUE != 32768UL) + #error "CK_LSE clock issue: must be 32.768 kHz!" +#endif + +/** + * @brief CK_PLL definition + */ +#if (PLL_ENABLE == 1) + /* Get CK_VCO frequency */ + #if (PLL_CLK_SRC == 1) + #if (HSI_ENABLE == 0) + #error "CK_PLL clock source issue: HSI has not been enabled" + #else + #define __CK_VCO ((HSI_VALUE >> PLL_CLK_SRC_DIV) * PLL_NF2_DIV) /*!< Select HSI as PLL source */ + #endif + #else + #if (HSE_ENABLE == 0) + #error "CK_PLL clock source issue: HSE has not been enabled!" + #else + #define __CK_VCO ((HSE_VALUE >> PLL_CLK_SRC_DIV) * PLL_NF2_DIV) /*!< Select HSE as PLL source */ + #endif + #endif + + #define VCO_MIN 24000000UL + #define VCO_MAX 60000000UL + #define PLL_MIN 4000000UL + #define PLL_MAX 60000000UL + + /* Check CK_VCO frequency */ + #if ((__CK_VCO < VCO_MIN) || (__CK_VCO > VCO_MAX)) + #error "CK_VCO clock issue: must be in the range!" + #endif + + #define __CK_PLL (__CK_VCO >> PLL_NO2_DIV) /*!< Get CK_PLL frequency */ + + /* Check CK_PLL frequency */ + #if ((__CK_PLL < PLL_MIN) || (__CK_PLL > PLL_MAX)) + #error "CK_PLL clock issue: must be in the range!" + #endif +#endif + +/** + * @brief CK_SYS definition + */ +#if (HCLK_SRC == 1) + #if (PLL_ENABLE == 1) + #define __CK_SYS __CK_PLL /*!< Select PLL as CK_SYS source */ + #else + #error "CK_SYS clock source issue: PLL is not enable!" + #endif +#elif (HCLK_SRC == 2) + #if (HSE_ENABLE == 1) + #define __CK_SYS HSE_VALUE /*!< Select HSE as CK_SYS source */ + #else + #error "CK_SYS clock source issue: HSE is not enable!" + #endif +#elif (HCLK_SRC == 3) + #if (HSI_ENABLE == 1) + #define __CK_SYS HSI_VALUE /*!< Select HSI as CK_SYS source */ + #else + #error "CK_SYS clock source issue: HSI is not enable!" + #endif +#elif (HCLK_SRC == 6) + #if (LSE_ENABLE == 1) + #define __CK_SYS LSE_VALUE /*!< Select LSE as CK_SYS source */ + #else + #error "CK_SYS clock source issue: LSE is not enable!" + #endif +#elif (HCLK_SRC == 7) + #if (LSI_ENABLE == 1) + #define __CK_SYS LSI_VALUE /*!< Select LSI as CK_SYS source */ + #else + #error "CK_SYS clock source issue: LSI is not enable!" + #endif +#else + #error "CK_SYS clock source issue: No clock source is selected!" +#endif + +/** + * @brief CK_AHB definition + */ +#define __CK_AHB (__CK_SYS >> HCLK_DIV) /*!< Get CK_AHB frequency */ + +#define CKAHB_MIN 1000UL +#define CKAHB_MAX 60000000UL +#define WS0_CLK 20000000UL +#define WS1_CLK 40000000UL + +/* Check CK_AHB frequency */ +#if ((__CK_AHB < CKAHB_MIN) || (__CK_AHB > CKAHB_MAX)) + #error "CK_AHB clock issue: must be in the range!" +#endif + +/* Check FLASH wait-state setting */ +#if ((__CK_AHB > WS1_CLK) && (WAIT_STATE < 2) || \ + (__CK_AHB > WS0_CLK) && (WAIT_STATE < 1)) + #error "FLASH wait state configuration issue!" +#endif +/** + * @} + */ + +/** @addtogroup HT32F5xxxx_System_Private_Variables + * @{ + */ +__IO uint32_t SystemCoreClock = __CK_AHB; /*!< SystemCoreClock = CK_AHB */ +/** + * @} + */ + +/** @addtogroup HT32F5xxxx_System_Private_Functions + * @{ + */ + +/** + * @brief Setup the microcontroller system. + * Initializes the system clocks and the embedded Flash. + * @note This function should be used after reset. + * @retval None + */ +void SystemInit(void) +{ +#if (WDT_ENABLE == 1) + HT_CKCU->APBCCR1 |= (0x1 << 4); + HT_WDT->PR = 0x35CA; + HT_WDT->MR0 = 0; + HT_WDT->MR1 = ((HT_WDT->MR1 & 0xFFF) | (WDT_PRESCALER << 12)); + HT_WDT->MR0 = WDT_RELOAD | (WDT_RESET_ENABLE << 13) | (WDT_SLEEP_HALT << 14) | (0x1 << 16); + HT_WDT->CR = 0x5FA00001; +#else + #if (DEINIT_ENABLE == 1) + HT_RSTCU->APBPRST1 = (1 << 4); + #endif +#endif + + SetBit_BB((u32)(&HT_CKCU->APBCCR1), 6); /* enable Backup domain register clock */ + + #if (DEINIT_ENABLE == 1) + /* De-init the setting */ + HT_CKCU->AHBCCR &= ~(0x1 << 11); /* disable IP who may use PLL as source */ + SetBit_BB((u32)(&HT_CKCU->GCCR), 11); /* enable HSI */ + while (!GetBit_BB((u32)(&HT_CKCU->GCSR), 3)); /* wait for HSI ready */ + HT_CKCU->GCCR = ((HT_CKCU->GCCR & ~7UL) | 3UL); /* select CK_SYS source */ + while ((HT_CKCU->CKST & 7UL) != 3UL); /* wait for clock switch complete */ + HT_FLASH->CFCR = (((HT_FLASH->CFCR) & ~7UL) | 1UL); /* set Wait State as 0 WS */ + HT_CKCU->AHBCFGR = 0; /* set CK_AHB prescaler */ + ResetBit_BB((u32)(&HT_CKCU->GCCR), 9); /* disable PLL */ + SetBit_BB((u32)(&HT_CKCU->GCFGR), 8); /* select PLL source as HSI */ + ResetBit_BB((u32)(&HT_CKCU->GCCR), 3); /* disable USB PLL */ + SetBit_BB((u32)(&HT_CKCU->GCFGR), 9); /* select USB PLL source as HSI */ + #endif + + /* HSE initiation */ +#if (HSE_ENABLE == 1) + SetBit_BB((u32)(&HT_CKCU->GCCR), 10); /* enable HSE */ + while (!GetBit_BB((u32)(&HT_CKCU->GCSR), 2)){}; /* wait for HSE ready */ +#endif + + /* LSE initiation */ +#if (LSE_ENABLE == 1) + do { + SetBit_BB((u32)(&HT_RTC->CR), 3); /* enable LSE */ + } while (!GetBit_BB((u32)(&HT_RTC->CR), 3)); + while (!GetBit_BB((u32)(&HT_CKCU->GCSR), 4)); /* wait for LSE ready */ +#endif + + ResetBit_BB((u32)(&HT_CKCU->APBCCR1), 6); /* disable Backup domain register clock */ + + /* LSI initiation */ +#if (HCLK_SRC == 7) + while (!GetBit_BB((u32)(&HT_CKCU->GCSR), 5)){}; /* wait for LSI ready */ +#endif + + /* PLL initiation */ +#if (PLL_ENABLE == 1) + HT_CKCU->PLLCFGR = ((PLL_NF2_DIV & 0x0F) << 23) | (PLL_NO2_DIV << 21); /* set PLL divider */ + + #if (PLL_CLK_SRC_DIV == 1) + SetBit_BB((u32)(&HT_CKCU->PLLCFGR), 28); /* set PLL clock source divider */ + #else + ResetBit_BB((u32)(&HT_CKCU->PLLCFGR), 28); /* reset PLL clock source divider */ + #endif + + #if (PLL_CLK_SRC == 0) + ResetBit_BB((u32)(&HT_CKCU->GCFGR), 8); /* select PLL source as HSE */ + #else + SetBit_BB((u32)(&HT_CKCU->GCFGR), 8); /* select PLL source as HSI */ + #endif + + SetBit_BB((u32)(&HT_CKCU->GCCR), 9); /* enable PLL */ + while (!GetBit_BB((u32)(&HT_CKCU->GCSR), 1)){}; /* wait for PLL ready */ +#endif + + /* CK_AHB initiation */ +#if (WAIT_STATE == 9) + #if (__CK_AHB > WS1_CLK) + HT_FLASH->CFCR = (((HT_FLASH->CFCR) & ~7UL) | 3UL); /* auto-select wait state */ + #elif (__CK_AHB > WS0_CLK) + HT_FLASH->CFCR = (((HT_FLASH->CFCR) & ~7UL) | 2UL); /* auto-select wait state */ + #endif +#else + HT_FLASH->CFCR = (((HT_FLASH->CFCR) & ~7UL) | (WAIT_STATE + 1)); /* manual wait state */ +#endif + + HT_CKCU->AHBCFGR = HCLK_DIV; /* set CK_AHB prescaler */ + HT_CKCU->GCCR = ((HT_CKCU->GCCR & ~7UL) | HCLK_SRC); /* select CK_SYS source */ + while ((HT_CKCU->CKST & 7UL) != HCLK_SRC); /* wait for clock switch complete */ + + /* Pre-fetch buffer configuration */ +#if (PRE_FETCH_ENABLE == 0) + ResetBit_BB((u32)(&HT_FLASH->CFCR), 4); /* 0: pre-fetch disable, 1: pre-fetch enable */ +#else + SetBit_BB((u32)(&HT_FLASH->CFCR), 4); /* 0: pre-fetch disable, 1: pre-fetch enable */ +#endif + + /* HSE power down */ +#if ((HSE_ENABLE == 0) && (HCLK_SRC != 2) && ((PLL_ENABLE == 0) || (PLL_CLK_SRC == 1))) + ResetBit_BB((u32)(&HT_CKCU->GCCR), 10); +#endif + + /* HSI power down */ +#if ((HSI_ENABLE == 0) && (HCLK_SRC != 3) && ((PLL_ENABLE == 0) || (PLL_CLK_SRC == 0))) + ResetBit_BB((u32)(&HT_CKCU->GCCR), 11); +#endif +} + +/** + * @brief Update SystemCoreClock + * @retval None + */ +void SystemCoreClockUpdate(void) +{ + u32 SystemCoreClockDiv = HT_CKCU->AHBCFGR & 7UL; + u32 PllSourceClockDiv = (HT_CKCU->PLLCFGR >> 28) & 1UL; + u32 PllFeedbackClockDiv = (((HT_CKCU->PLLCFGR >> 23) & 15UL) == 0) ? (16) : ((HT_CKCU->PLLCFGR >> 23) & 15UL); + u32 PllOutputClockDiv = (HT_CKCU->PLLCFGR >> 21) & 3UL; + u32 SystemCoreClockSrc = HT_CKCU->CKST & 7UL; + + /* Get system core clock according to global clock control & configuration registers */ + if (SystemCoreClockSrc == 1) + { + if (GetBit_BB((u32)(&HT_CKCU->PLLCR), 31)) + { + PllFeedbackClockDiv = 1; + PllOutputClockDiv = 0; + } + + if (GetBit_BB((u32)(&HT_CKCU->GCFGR), 8)) + { + SystemCoreClock = (((HSI_VALUE >> PllSourceClockDiv) * PllFeedbackClockDiv) >> PllOutputClockDiv) >> SystemCoreClockDiv; + } + else + { + SystemCoreClock = (((HSE_VALUE >> PllSourceClockDiv) * PllFeedbackClockDiv) >> PllOutputClockDiv) >> SystemCoreClockDiv; + } + } + else if (SystemCoreClockSrc == 2) + { + SystemCoreClock = HSE_VALUE >> SystemCoreClockDiv; + } + else if (SystemCoreClockSrc == 3) + { + SystemCoreClock = HSI_VALUE >> SystemCoreClockDiv; + } + else if (SystemCoreClockSrc == 6) + { + SystemCoreClock = LSE_VALUE >> SystemCoreClockDiv; + } + else if (SystemCoreClockSrc == 7) + { + SystemCoreClock = LSI_VALUE >> SystemCoreClockDiv; + } +} + +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ + +/******************* (C) COPYRIGHT Holtek Semiconductor Inc. *****END OF FILE*** */ diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/system_ht32f5xxxx_10.c b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/system_ht32f5xxxx_10.c new file mode 100644 index 0000000000..704ebb5730 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/system_ht32f5xxxx_10.c @@ -0,0 +1,455 @@ +/**************************************************************************//** + * @file library/Device/Holtek/HT32F5xxxx/Source/system_ht32f5xxxx_10.c + * @brief CMSIS Cortex-M0+ Device Peripheral Access Layer Source File + * for the Holtek HT32F5xxxx Device Series + * @version $Rev:: 6597 $ + * @date $Date:: 2022-12-27 #$ + * + * @note + * Copyright (C) Holtek Semiconductor Inc. All rights reserved. + * + * @par + * ARM Limited (ARM) supplies this software for Cortex-M processor-based + * microcontrollers. This file can be freely distributed within development + * tools that are supporting such ARM based processors. + * + * @par + * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR + * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + ******************************************************************************/ + +// Supported Device +// ======================================== +// HT32F61244, HT32F61245 + +//#define USE_HT32F61244_45 + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup HT32F5xxxx_system HT32F5xxxx System + * @{ + */ + + +#include "ht32f5xxxx_01.h" + +/** @addtogroup HT32F5xxxx_System_Private_Defines + * @{ + */ +/* +//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ +*/ + +/*--------------------- Clock Configuration ---------------------------------- +// +// Enable High Speed External Crystal Oscillator (HSE) +// Default HSE = DISABLE +// +// Enable PLL +// Default PLL = DISABLE +// PLL Out = (((HSE or HSI) / SRC_DIV) x NF2 ) / NO2 +// PLL Clock Source +// <0=> CK_HSE +// <1=> CK_HSI +// Default PLL clock source = CK_HSI +// PLL source clock must be in the range of 4 MHz to 16 MHz +// PLL Clock Source Divider (SRC_DIV) +// <0=> 1 +// <1=> 2 +// PLL input clock = PLL Clock Source / (SRC_DIV) +// PLL Feedback Clock Divider (NF2): 1 ~ 16 +// <1-16:1> +// PLL feedback clock = PLL input clock x NF2 +// PLL feedback clock must be in the range of 24 MHz to 48 MHz +// PLL Output Clock Divider (NO2) +// <0=> 1 +// <1=> 2 +// <2=> 4 +// <3=> 8 +// PLL output clock = PLL feedback clock / NO2 +// PLL output clock must be in the range of 4 MHz to 48 MHz +// +// +// SystemCoreClock Configuration (CK_AHB) +// SystemCoreClock Source +// <1=> CK_PLL +// <2=> CK_HSE +// <3=> CK_HSI +// <7=> CK_LSI +// Default SystemCoreClock source = CK_HSI +// SystemCoreClock Source Divider +// <0=> 1 +// <1=> 2 +// <2=> 4 +// <3=> 8 +// <4=> 16 +// <5=> 32 +// Default SystemCoreClock source divider = 1 +// +// +// FLASH Configuration +// Wait state +// <0=> 0 WS +// <1=> 1 WS +// <2=> 2 WS +// <9=> AUTO +// 0 WS: 1 kHz <= CK_AHB <= 20 MHz +// 1 WS: 20 MHz < CK_AHB <= 40 MHz +// 2 WS: 40 MHz < CK_AHB <= 48 MHz +// Pre-fetch Buffer Enable +// Default pre-fetch buffer = ENABLE +// +*/ + +/* !!! NOTICE !!! + HSI must keep turn on when doing the Flash operation (Erase/Program). +*/ + +/* !!! NOTICE !!! + * How to adjust the value of High Speed External oscillator (HSE)? + The default value of HSE is define by "HSE_VALUE" in "ht32fxxxxx_nn.h". + If your board uses a different HSE speed, please add a new compiler preprocessor + C define, "HSE_VALUE=n000000" ("n" represents n MHz) in the toolchain/IDE, + or edit the "HSE_VALUE" in the "ht32f5xxxx_conf.h" file. + Take Keil MDK-ARM for instance, to set HSE as 16 MHz: + "Option of Taret -> C/C++ > Preprocessor Symbols" + Define: USE_HT32_DRIVER, USE_HT32Fxxxxx_SK, USE_HT32Fxxxxx_xx, USE_MEM_HT32Fxxxxx, HSE_VALUE=16000000 + ^^ Add "HSE_VALUE" + define as above. +*/ +#define HSI_ENABLE (1) /*!< 0: DISABLE, 1: ENABLE */ +#define HSE_ENABLE (1) /*!< 0: DISABLE, 1: ENABLE */ +#define LSI_ENABLE (1) /*!< 0: DISABLE, 1: ENABLE */ +#define PLL_ENABLE (1) /*!< 0: DISABLE, 1: ENABLE */ +#define PLL_CLK_SRC (0) /*!< 0: HSE, 1: HSI */ +#define PLL_CLK_SRC_DIV (0) /*!< 0: DIV1, 1: DIV2 */ +#define PLL_NF2_DIV (4) /*!< 1~16: DIV1~DIV16 */ +#define PLL_NO2_DIV (0) /*!< 0: DIV1, 1: DIV2, 2: DIV4, 3: DIV8 */ +#define HCLK_SRC (1) /*!< 0: PLL, 1: PLL, 2: HSE, 3: HSI 7: LSI */ +#define HCLK_DIV (0) /*!< 0: DIV1, 1: DIV2, 2: DIV4, 3: DIV8, 4: DIV16, 5: DIV32 */ +#define WAIT_STATE (9) /*!< 0: WS = 0, 1: WS = 1, 2: WS = 2, 9: AUTO */ +#define PRE_FETCH_ENABLE (1) /*!< 0: DISABLE, 1: ENABLE */ +#define DEINIT_ENABLE (1) /* Set 0 for reduce code size */ + +/*----------------------------------------------------------------------------------------------------------*/ +/* PLL Out = (((HSE or HSI) / (PLL_CLK_SRC_DIV + 1)) x PLL_NF2) / PLL_NO2 */ +/*----------------------------------------------------------------------------------------------------------*/ + + +/*--------------------- WDT Configuration ---------------------------------- +// +// Enable WDT Configuration +// WDT Prescaler Selection +// <0=> CK_WDT / 1 +// <1=> CK_WDT / 2 +// <2=> CK_WDT / 4 +// <3=> CK_WDT / 8 +// <4=> CK_WDT / 16 +// <5=> CK_WDT / 32 +// <6=> CK_WDT / 64 +// <7=> CK_WDT / 128 +// WDT Reload Value <1-4095:1> +// Enable WDT Reset function +// WDT Sleep Halt mode +// <0=> No halt +// <1=> Halt in DeepSleep1 +// <2=> Halt in Sleep & DeepSleep1 +// +*/ +#define WDT_ENABLE (0) /*!< 0: DISABLE, 1: ENABLE */ +#define WDT_PRESCALER (5) /*!< 0: 1/1, 1: 1/2, 2: 1/4, 3: 1/8, 4: 1/16, 5: 1/32, 6: 1/64, 7: 1/128 */ +#define WDT_RELOAD (2000) /*!< 0 ~ 4095, 12 bit */ +#define WDT_RESET_ENABLE (1) /*!< 0: No Reset, 1: Reset when WDT over flow */ +#define WDT_SLEEP_HALT (2) /*!< 0: No halt, 1: Halt in DeepSleep1, 2: Halt in Sleep & DeepSleep1 */ + +/** + * @brief Check HSI frequency + */ +#if (HSI_VALUE != 8000000UL) + #error "CK_HSI clock issue: must be 8 MHz!" +#endif + +/** + * @brief Check HSE frequency + */ +#if ((HSE_VALUE < 4000000UL) || (HSE_VALUE > 16000000UL)) + #error "CK_HSE clock issue: must be in the range of 4 MHz to 16 MHz!" +#endif + +/** + * @brief Check LSI frequency + */ +#if (LSI_VALUE != 32000UL) + #error "CK_LSI clock issue: must be 32 kHz!" +#endif + +/** + * @brief CK_PLL definition + */ +#if (PLL_ENABLE == 1) + /* Get CK_VCO frequency */ + #if (PLL_CLK_SRC == 1) + #if (HSI_ENABLE == 0) + #error "CK_PLL clock source issue: HSI has not been enabled" + #else + #define __CK_VCO ((HSI_VALUE >> PLL_CLK_SRC_DIV) * PLL_NF2_DIV) /*!< Select HSI as PLL source */ + #endif + #else + #if (HSE_ENABLE == 0) + #error "CK_PLL clock source issue: HSE has not been enabled!" + #else + #define __CK_VCO ((HSE_VALUE >> PLL_CLK_SRC_DIV) * PLL_NF2_DIV) /*!< Select HSE as PLL source */ + #endif + #endif + + #define VCO_MIN 24000000UL + #define VCO_MAX 48000000UL + #define PLL_MIN 4000000UL + #define PLL_MAX 48000000UL + + /* Check CK_VCO frequency */ + #if ((__CK_VCO < VCO_MIN) || (__CK_VCO > VCO_MAX)) + #error "CK_VCO clock issue: must be in the range!" + #endif + + #define __CK_PLL (__CK_VCO >> PLL_NO2_DIV) /*!< Get CK_PLL frequency */ + + /* Check CK_PLL frequency */ + #if ((__CK_PLL < PLL_MIN) || (__CK_PLL > PLL_MAX)) + #error "CK_PLL clock issue: must be in the range!" + #endif +#endif + +/** + * @brief CK_SYS definition + */ +#if (HCLK_SRC == 1) + #if (PLL_ENABLE == 1) + #define __CK_SYS __CK_PLL /*!< Select PLL as CK_SYS source */ + #else + #error "CK_SYS clock source issue: PLL is not enable!" + #endif +#elif (HCLK_SRC == 2) + #if (HSE_ENABLE == 1) + #define __CK_SYS HSE_VALUE /*!< Select HSE as CK_SYS source */ + #else + #error "CK_SYS clock source issue: HSE is not enable!" + #endif +#elif (HCLK_SRC == 3) + #if (HSI_ENABLE == 1) + #define __CK_SYS HSI_VALUE /*!< Select HSI as CK_SYS source */ + #else + #error "CK_SYS clock source issue: HSI is not enable!" + #endif +#elif (HCLK_SRC == 7) + #if (LSI_ENABLE == 1) + #define __CK_SYS LSI_VALUE /*!< Select LSI as CK_SYS source */ + #else + #error "CK_SYS clock source issue: LSI is not enable!" + #endif +#else + #error "CK_SYS clock source issue: No clock source is selected!" +#endif + +/** + * @brief CK_AHB definition + */ +#define __CK_AHB (__CK_SYS >> HCLK_DIV) /*!< Get CK_AHB frequency */ + +#define CKAHB_MIN 1000UL +#define CKAHB_MAX 48000000UL +#define WS0_CLK 20000000UL +#define WS1_CLK 40000000UL + +/* Check CK_AHB frequency */ +#if ((__CK_AHB < CKAHB_MIN) || (__CK_AHB > CKAHB_MAX)) + #error "CK_AHB clock issue: must be in the range!" +#endif + +/* Check FLASH wait-state setting */ +#if ((__CK_AHB > WS1_CLK) && (WAIT_STATE < 2) || \ + (__CK_AHB > WS0_CLK) && (WAIT_STATE < 1)) + #error "FLASH wait state configuration issue!" +#endif +/** + * @} + */ + +/** @addtogroup HT32F5xxxx_System_Private_Variables + * @{ + */ +__IO uint32_t SystemCoreClock = __CK_AHB; /*!< SystemCoreClock = CK_AHB */ +/** + * @} + */ + +/** @addtogroup HT32F5xxxx_System_Private_Functions + * @{ + */ + +/** + * @brief Setup the microcontroller system. + * Initializes the system clocks and the embedded Flash. + * @note This function should be used after reset. + * @retval None + */ +void SystemInit(void) +{ +#if (WDT_ENABLE == 1) + HT_CKCU->APBCCR1 |= (0x1 << 4); + HT_WDT->PR = 0x35CA; + HT_WDT->MR0 = 0; + HT_WDT->MR1 = ((HT_WDT->MR1 & 0xFFF) | (WDT_PRESCALER << 12)); + HT_WDT->MR0 = WDT_RELOAD | (WDT_RESET_ENABLE << 13) | (WDT_SLEEP_HALT << 14) | (0x1 << 16); + HT_WDT->CR = 0x5FA00001; +#else + #if (DEINIT_ENABLE == 1) + HT_RSTCU->APBPRST1 = (1 << 4); + #endif +#endif + + SetBit_BB((u32)(&HT_CKCU->APBCCR1), 6); /* enable VDD power domain register clock */ + + #if (DEINIT_ENABLE == 1) + /* De-init the setting */ + ResetBit_BB((u32)(&HT_CKCU->AHBCCR), 11); /* disable IP who may use PLL as source */ + SetBit_BB((u32)(&HT_CKCU->GCCR), 11); /* enable HSI */ + while (!GetBit_BB((u32)(&HT_CKCU->GCSR), 3)); /* wait for HSI ready */ + HT_CKCU->GCCR = ((HT_CKCU->GCCR & ~7UL) | 3UL); /* select CK_SYS source */ + while ((HT_CKCU->CKST & 7UL) != 3UL); /* wait for clock switch complete */ + HT_FLASH->CFCR = (((HT_FLASH->CFCR) & ~7UL) | 1UL); /* set Wait State as 0 WS */ + HT_CKCU->AHBCFGR = 0; /* set CK_AHB prescaler */ + ResetBit_BB((u32)(&HT_CKCU->GCCR), 9); /* disable PLL */ + SetBit_BB((u32)(&HT_CKCU->GCFGR), 8); /* select PLL source as HSI */ + #endif + + /* HSE initiation */ +#if (HSE_ENABLE == 1) + SetBit_BB((u32)(&HT_CKCU->GCCR), 10); /* enable HSE */ + while (!GetBit_BB((u32)(&HT_CKCU->GCSR), 2)){}; /* wait for HSE ready */ +#endif + + ResetBit_BB((u32)(&HT_CKCU->APBCCR1), 6); /* disable VDD power domain register clock */ + + /* LSI initiation */ +#if (HCLK_SRC == 7) + while (!GetBit_BB((u32)(&HT_CKCU->GCSR), 5)){}; /* wait for LSI ready */ +#endif + + /* PLL initiation */ +#if (PLL_ENABLE == 1) + HT_CKCU->PLLCFGR = ((PLL_NF2_DIV & 0x0F) << 23) | (PLL_NO2_DIV << 21); /* set PLL divider */ + + #if (PLL_CLK_SRC_DIV == 1) + SetBit_BB((u32)(&HT_CKCU->PLLCFGR), 28); /* set PLL clock source divider */ + #else + ResetBit_BB((u32)(&HT_CKCU->PLLCFGR), 28); /* reset PLL clock source divider */ + #endif + + #if (PLL_CLK_SRC == 0) + ResetBit_BB((u32)(&HT_CKCU->GCFGR), 8); /* select PLL source as HSE */ + #else + SetBit_BB((u32)(&HT_CKCU->GCFGR), 8); /* select PLL source as HSI */ + #endif + + SetBit_BB((u32)(&HT_CKCU->GCCR), 9); /* enable PLL */ + while (!GetBit_BB((u32)(&HT_CKCU->GCSR), 1)){}; /* wait for PLL ready */ +#endif + + /* CK_AHB initiation */ +#if (WAIT_STATE == 9) + #if (__CK_AHB > WS1_CLK) + HT_FLASH->CFCR = (((HT_FLASH->CFCR) & ~7UL) | 3UL); /* auto-select wait state */ + #elif (__CK_AHB > WS0_CLK) + HT_FLASH->CFCR = (((HT_FLASH->CFCR) & ~7UL) | 2UL); /* auto-select wait state */ + #endif +#else + HT_FLASH->CFCR = (((HT_FLASH->CFCR) & ~7UL) | (WAIT_STATE + 1)); /* manual wait state */ +#endif + + HT_CKCU->AHBCFGR = HCLK_DIV; /* set CK_AHB prescaler */ + HT_CKCU->GCCR = ((HT_CKCU->GCCR & ~7UL) | HCLK_SRC); /* select CK_SYS source */ + while ((HT_CKCU->CKST & 7UL) != HCLK_SRC); /* wait for clock switch complete */ + + /* Pre-fetch buffer configuration */ +#if (PRE_FETCH_ENABLE == 0) + ResetBit_BB((u32)(&HT_FLASH->CFCR), 4); /* 0: pre-fetch disable, 1: pre-fetch enable */ +#else + SetBit_BB((u32)(&HT_FLASH->CFCR), 4); /* 0: pre-fetch disable, 1: pre-fetch enable */ +#endif + + /* HSE power down */ +#if ((HSE_ENABLE == 0) && (HCLK_SRC != 2) && ((PLL_ENABLE == 0) || (PLL_CLK_SRC == 1))) + ResetBit_BB((u32)(&HT_CKCU->GCCR), 10); +#endif + + /* HSI power down */ +#if ((HSI_ENABLE == 0) && (HCLK_SRC != 3) && ((PLL_ENABLE == 0) || (PLL_CLK_SRC == 0))) + ResetBit_BB((u32)(&HT_CKCU->GCCR), 11); +#endif +} + +/** + * @brief Update SystemCoreClock + * @retval None + */ +void SystemCoreClockUpdate(void) +{ + u32 SystemCoreClockDiv = HT_CKCU->AHBCFGR & 7UL; + u32 PllSourceClockDiv = (HT_CKCU->PLLCFGR >> 28) & 1UL; + u32 PllFeedbackClockDiv = (((HT_CKCU->PLLCFGR >> 23) & 15UL) == 0) ? (16) : ((HT_CKCU->PLLCFGR >> 23) & 15UL); + u32 PllOutputClockDiv = (HT_CKCU->PLLCFGR >> 21) & 3UL; + u32 SystemCoreClockSrc = HT_CKCU->CKST & 7UL; + + /* Get system core clock according to global clock control & configuration registers */ + if (SystemCoreClockSrc == 1) + { + if (GetBit_BB((u32)(&HT_CKCU->PLLCR), 31)) + { + PllFeedbackClockDiv = 1; + PllOutputClockDiv = 0; + } + + if (GetBit_BB((u32)(&HT_CKCU->GCFGR), 8)) + { + SystemCoreClock = (((HSI_VALUE >> PllSourceClockDiv) * PllFeedbackClockDiv) >> PllOutputClockDiv) >> SystemCoreClockDiv; + } + else + { + SystemCoreClock = (((HSE_VALUE >> PllSourceClockDiv) * PllFeedbackClockDiv) >> PllOutputClockDiv) >> SystemCoreClockDiv; + } + } + else if (SystemCoreClockSrc == 2) + { + SystemCoreClock = HSE_VALUE >> SystemCoreClockDiv; + } + else if (SystemCoreClockSrc == 3) + { + SystemCoreClock = HSI_VALUE >> SystemCoreClockDiv; + } + else if (SystemCoreClockSrc == 7) + { + SystemCoreClock = LSI_VALUE >> SystemCoreClockDiv; + } +} + +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ + +/******************* (C) COPYRIGHT Holtek Semiconductor Inc. *****END OF FILE*** */ diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/system_ht32f5xxxx_11.c b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/system_ht32f5xxxx_11.c new file mode 100644 index 0000000000..d1b2c20be4 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/system_ht32f5xxxx_11.c @@ -0,0 +1,511 @@ +/**************************************************************************//** + * @file library/Device/Holtek/HT32F5xxxx/Source/system_ht32f5xxxx_11.c + * @brief CMSIS Cortex-M0+ Device Peripheral Access Layer Source File + * for the Holtek HT32F5xxxx Device Series + * @version $Rev:: 6597 $ + * @date $Date:: 2022-12-27 #$ + * + * @note + * Copyright (C) Holtek Semiconductor Inc. All rights reserved. + * + * @par + * ARM Limited (ARM) supplies this software for Cortex-M processor-based + * microcontrollers. This file can be freely distributed within development + * tools that are supporting such ARM based processors. + * + * @par + * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR + * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + ******************************************************************************/ + +// Supported Device +// ======================================== +// HT32F67041, HT32F67051 + +//#define USE_HT32F67041_51 + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup HT32F5xxxx_system HT32F5xxxx System + * @{ + */ + + +#include "ht32f5xxxx_01.h" + +/** @addtogroup HT32F5xxxx_System_Private_Defines + * @{ + */ +/* +//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ +*/ + +/*--------------------- Clock Configuration ---------------------------------- +// +// Enable High Speed External Crystal Oscillator (HSE) +// Default HSE = DISABLE +// HSE Output Clock Divider +// <0=> 1 +// <1=> 2 +// <2=> 4 +// <3=> 8 +// Default HSE output clock divider = 1 +// +// +// Enable Low Speed External Crystal Oscillator (LSE) +// Default LSE = DISABLE +// +// Enable PLL +// Default PLL = DISABLE +// PLL Out = (((HSE or HSI) / SRC_DIV) x NF2 ) / NO2 +// PLL Clock Source +// <0=> CK_HSE +// <1=> CK_HSI +// Default PLL clock source = CK_HSI +// PLL source clock must be in the range of 4 MHz to 16 MHz +// PLL Clock Source Divider (SRC_DIV) +// <0=> 1 +// <1=> 2 +// PLL input clock = PLL Clock Source / (SRC_DIV) +// PLL Feedback Clock Divider (NF2): 1 ~ 16 +// <1-16:1> +// PLL feedback clock = PLL input clock x NF2 +// PLL feedback clock must be in the range of 24 MHz to 60 MHz +// PLL Output Clock Divider (NO2) +// <0=> 1 +// <1=> 2 +// <2=> 4 +// <3=> 8 +// PLL output clock = PLL feedback clock / NO2 +// PLL output clock must be in the range of 4 MHz to 60 MHz +// +// +// SystemCoreClock Configuration (CK_AHB) +// SystemCoreClock Source +// <1=> CK_PLL +// <2=> CK_HSE +// <3=> CK_HSI +// <6=> CK_LSE +// <7=> CK_LSI +// Default SystemCoreClock source = CK_HSI +// SystemCoreClock Source Divider +// <0=> 1 +// <1=> 2 +// <2=> 4 +// <3=> 8 +// <4=> 16 +// <5=> 32 +// Default SystemCoreClock source divider = 1 +// +// +// FLASH Configuration +// Wait state +// <0=> 0 WS +// <1=> 1 WS +// <2=> 2 WS +// <9=> AUTO +// 0 WS: 1 kHz <= CK_AHB <= 20 MHz +// 1 WS: 20 MHz < CK_AHB <= 40 MHz +// 2 WS: 40 MHz < CK_AHB <= 60 MHz +// Pre-fetch Buffer Enable +// Default pre-fetch buffer = ENABLE +// +*/ + +/* !!! NOTICE !!! + HSI must keep turn on when doing the Flash operation (Erase/Program). +*/ + +/* !!! NOTICE !!! + * How to adjust the value of High Speed External oscillator (HSE)? + The default value of HSE is define by "HSE_VALUE" in "ht32fxxxxx_nn.h". + If your board uses a different HSE speed, please add a new compiler preprocessor + C define, "HSE_VALUE=n000000" ("n" represents n MHz) in the toolchain/IDE, + or edit the "HSE_VALUE" in the "ht32f5xxxx_conf.h" file. + Take Keil MDK-ARM for instance, to set HSE as 16 MHz: + "Option of Taret -> C/C++ > Preprocessor Symbols" + Define: USE_HT32_DRIVER, USE_HT32Fxxxxx_SK, USE_HT32Fxxxxx_xx, USE_MEM_HT32Fxxxxx, HSE_VALUE=16000000 + ^^ Add "HSE_VALUE" + define as above. +*/ +#define HSI_ENABLE (1) /*!< 0: DISABLE, 1: ENABLE */ +#define HSE_ENABLE (1) /*!< 0: DISABLE, 1: ENABLE */ +#define HSE_CLK_DIV (1) /*!< 0: DIV1, 1: DIV2, 2: DIV4, 3: DIV8 */ +#define LSI_ENABLE (1) /*!< 0: DISABLE, 1: ENABLE */ +#define LSE_ENABLE (0) /*!< 0: DISABLE, 1: ENABLE */ +#define PLL_ENABLE (1) /*!< 0: DISABLE, 1: ENABLE */ +#define PLL_CLK_SRC (0) /*!< 0: HSE, 1: HSI */ +#define PLL_CLK_SRC_DIV (1) /*!< 0: DIV1, 1: DIV2 */ +#define PLL_NF2_DIV (15) /*!< 1~16: DIV1~DIV16 */ +#define PLL_NO2_DIV (0) /*!< 0: DIV1, 1: DIV2, 2: DIV4, 3: DIV8 */ +#define HCLK_SRC (1) /*!< 0: PLL, 1: PLL, 2: HSE, 3: HSI 6: LSE, 7: LSI */ +#define HCLK_DIV (0) /*!< 0: DIV1, 1: DIV2, 2: DIV4, 3: DIV8, 4: DIV16, 5: DIV32 */ +#define WAIT_STATE (9) /*!< 0: WS = 0, 1: WS = 1, 2: WS = 2, 9: AUTO */ +#define PRE_FETCH_ENABLE (1) /*!< 0: DISABLE, 1: ENABLE */ +#define DEINIT_ENABLE (1) /* Set 0 for reduce code size */ + +/*----------------------------------------------------------------------------------------------------------*/ +/* PLL Out = (((HSE or HSI) / (PLL_CLK_SRC_DIV + 1)) x PLL_NF2) / PLL_NO2 */ +/*----------------------------------------------------------------------------------------------------------*/ + + +/*--------------------- WDT Configuration ---------------------------------- +// +// Enable WDT Configuration +// WDT Prescaler Selection +// <0=> CK_WDT / 1 +// <1=> CK_WDT / 2 +// <2=> CK_WDT / 4 +// <3=> CK_WDT / 8 +// <4=> CK_WDT / 16 +// <5=> CK_WDT / 32 +// <6=> CK_WDT / 64 +// <7=> CK_WDT / 128 +// WDT Reload Value <1-4095:1> +// Enable WDT Reset function +// WDT Sleep Halt mode +// <0=> No halt +// <1=> Halt in DeepSleep1 +// <2=> Halt in Sleep & DeepSleep1 +// +*/ +#define WDT_ENABLE (0) /*!< 0: DISABLE, 1: ENABLE */ +#define WDT_PRESCALER (5) /*!< 0: 1/1, 1: 1/2, 2: 1/4, 3: 1/8, 4: 1/16, 5: 1/32, 6: 1/64, 7: 1/128 */ +#define WDT_RELOAD (2000) /*!< 0 ~ 4095, 12 bit */ +#define WDT_RESET_ENABLE (1) /*!< 0: No Reset, 1: Reset when WDT over flow */ +#define WDT_SLEEP_HALT (2) /*!< 0: No halt, 1: Halt in DeepSleep1, 2: Halt in Sleep & DeepSleep1 */ + +/** + * @brief Check HSI frequency + */ +#if (HSI_VALUE != 8000000UL) + #error "CK_HSI clock issue: must be 8 MHz!" +#endif + +/** + * @brief Check HSE frequency + */ +#if (HSE_VALUE != 16000000UL) + #error "CK_HSE clock issue: must be 16 MHz!" +#endif + +/** + * @brief Check LSI frequency + */ +#if (LSI_VALUE != 32000UL) + #error "CK_LSI clock issue: must be 32 kHz!" +#endif + +/** + * @brief Check LSE frequency + */ +#if (LSE_VALUE != 32768UL) + #error "CK_LSE clock issue: must be 32.768 kHz!" +#endif + +/** + * @brief CK_HSE definition + */ +#define __CK_HSE (HSE_VALUE >> HSE_CLK_DIV) /*!< Get CK_HSE frequency */ + +/** + * @brief CK_PLL definition + */ +#if (PLL_ENABLE == 1) + /* Get CK_PLL_IN frequency */ + #if (PLL_CLK_SRC == 1) + #if (HSI_ENABLE == 0) + #error "CK_PLL clock source issue: HSI has not been enabled" + #else + #define __CK_PLL_SRC (HSI_VALUE >> PLL_CLK_SRC_DIV) /*!< Select HSI as PLL source */ + #endif + #else + #if (HSE_ENABLE == 0) + #error "CK_PLL clock source issue: HSE has not been enabled!" + #else + #define __CK_PLL_SRC (__CK_HSE >> PLL_CLK_SRC_DIV) /*!< Select HSE as PLL source */ + #endif + #endif + + #define PLL_SRC_MIN 4000000UL + #define PLL_SRC_MAX 16000000UL + #define VCO_MIN 24000000UL + #define VCO_MAX 60000000UL + #define PLL_MIN 4000000UL + #define PLL_MAX 60000000UL + + /* Check CK_PLL_IN frequency */ + #if ((__CK_PLL_SRC < PLL_SRC_MIN) || (__CK_PLL_SRC > PLL_SRC_MAX)) + #error "CK_PLL_SRC clock issue: must be in the range!" + #endif + + /* Get CK_VCO frequency */ + #define __CK_VCO (__CK_PLL_SRC * PLL_NF2_DIV) /*!< Get CK_VCO frequency */ + + /* Check CK_VCO frequency */ + #if ((__CK_VCO < VCO_MIN) || (__CK_VCO > VCO_MAX)) + #error "CK_VCO clock issue: must be in the range!" + #endif + + #define __CK_PLL (__CK_VCO >> PLL_NO2_DIV) /*!< Get CK_PLL frequency */ + + /* Check CK_PLL frequency */ + #if ((__CK_PLL < PLL_MIN) || (__CK_PLL > PLL_MAX)) + #error "CK_PLL clock issue: must be in the range!" + #endif +#endif + +/** + * @brief CK_SYS definition + */ +#if (HCLK_SRC == 1) + #if (PLL_ENABLE == 1) + #define __CK_SYS __CK_PLL /*!< Select PLL as CK_SYS source */ + #else + #error "CK_SYS clock source issue: PLL is not enable!" + #endif +#elif (HCLK_SRC == 2) + #if (HSE_ENABLE == 1) + #define __CK_SYS __CK_HSE /*!< Select HSE as CK_SYS source */ + #else + #error "CK_SYS clock source issue: HSE is not enable!" + #endif +#elif (HCLK_SRC == 3) + #if (HSI_ENABLE == 1) + #define __CK_SYS HSI_VALUE /*!< Select HSI as CK_SYS source */ + #else + #error "CK_SYS clock source issue: HSI is not enable!" + #endif +#elif (HCLK_SRC == 6) + #if (LSE_ENABLE == 1) + #define __CK_SYS LSE_VALUE /*!< Select LSE as CK_SYS source */ + #else + #error "CK_SYS clock source issue: LSE is not enable!" + #endif +#elif (HCLK_SRC == 7) + #if (LSI_ENABLE == 1) + #define __CK_SYS LSI_VALUE /*!< Select LSI as CK_SYS source */ + #else + #error "CK_SYS clock source issue: LSI is not enable!" + #endif +#else + #error "CK_SYS clock source issue: No clock source is selected!" +#endif + +/** + * @brief CK_AHB definition + */ +#define __CK_AHB (__CK_SYS >> HCLK_DIV) /*!< Get CK_AHB frequency */ + +#define CKAHB_MIN 1000UL +#define CKAHB_MAX 60000000UL +#define WS0_CLK 20000000UL +#define WS1_CLK 40000000UL + +/* Check CK_AHB frequency */ +#if ((__CK_AHB < CKAHB_MIN) || (__CK_AHB > CKAHB_MAX)) + #error "CK_AHB clock issue: must be in the range!" +#endif + +/* Check FLASH wait-state setting */ +#if ((__CK_AHB > WS1_CLK) && (WAIT_STATE < 2) || \ + (__CK_AHB > WS0_CLK) && (WAIT_STATE < 1)) + #error "FLASH wait state configuration issue!" +#endif +/** + * @} + */ + +/** @addtogroup HT32F5xxxx_System_Private_Variables + * @{ + */ +__IO uint32_t SystemCoreClock = __CK_AHB; /*!< SystemCoreClock = CK_AHB */ +/** + * @} + */ + +/** @addtogroup HT32F5xxxx_System_Private_Functions + * @{ + */ + +/** + * @brief Setup the microcontroller system. + * Initializes the system clocks and the embedded Flash. + * @note This function should be used after reset. + * @retval None + */ +void SystemInit(void) +{ +#if (WDT_ENABLE == 1) + HT_CKCU->APBCCR1 |= (0x1 << 4); + HT_WDT->PR = 0x35CA; + HT_WDT->MR0 = 0; + HT_WDT->MR1 = ((HT_WDT->MR1 & 0xFFF) | (WDT_PRESCALER << 12)); + HT_WDT->MR0 = WDT_RELOAD | (WDT_RESET_ENABLE << 13) | (WDT_SLEEP_HALT << 14) | (0x1 << 16); + HT_WDT->CR = 0x5FA00001; +#else + #if (DEINIT_ENABLE == 1) + HT_RSTCU->APBPRST1 = (1 << 4); + #endif +#endif + + SetBit_BB((u32)(&HT_CKCU->APBCCR1), 6); /* enable VDD power domain register clock */ + + #if (DEINIT_ENABLE == 1) + /* De-init the setting */ + ResetBit_BB((u32)(&HT_CKCU->AHBCCR), 11); /* disable IP who may use PLL as source */ + SetBit_BB((u32)(&HT_CKCU->GCCR), 11); /* enable HSI */ + while (!GetBit_BB((u32)(&HT_CKCU->GCSR), 3)); /* wait for HSI ready */ + HT_CKCU->GCCR = ((HT_CKCU->GCCR & ~7UL) | 3UL); /* select CK_SYS source */ + while ((HT_CKCU->CKST & 7UL) != 3UL); /* wait for clock switch complete */ + HT_FLASH->CFCR = (((HT_FLASH->CFCR) & ~7UL) | 1UL); /* set Wait State as 0 WS */ + HT_CKCU->AHBCFGR = 0; /* set CK_AHB prescaler */ + ResetBit_BB((u32)(&HT_CKCU->GCCR), 9); /* disable PLL */ + SetBit_BB((u32)(&HT_CKCU->GCFGR), 8); /* select PLL source as HSI */ + #endif + + /* HSE initiation */ +#if (HSE_ENABLE == 1) + HT_CKCU->GCFGR = (HT_CKCU->GCFGR & ~(3UL << 16)) | (HSE_CLK_DIV << 16); /* set HSE divider */ + + SetBit_BB((u32)(&HT_CKCU->GCCR), 10); /* enable HSE */ + while (!GetBit_BB((u32)(&HT_CKCU->GCSR), 2)){}; /* wait for HSE ready */ +#endif + + /* LSE initiation */ +#if (LSE_ENABLE == 1) + do { + SetBit_BB((u32)(&HT_RTC->CR), 3); /* enable LSE */ + } while (!GetBit_BB((u32)(&HT_RTC->CR), 3)); + while (!GetBit_BB((u32)(&HT_CKCU->GCSR), 4)); /* wait for LSE ready */ +#endif + + ResetBit_BB((u32)(&HT_CKCU->APBCCR1), 6); /* disable Backup domain register clock */ + + /* LSI initiation */ +#if (HCLK_SRC == 7) + while (!GetBit_BB((u32)(&HT_CKCU->GCSR), 5)){}; /* wait for LSI ready */ +#endif + + /* PLL initiation */ +#if (PLL_ENABLE == 1) + HT_CKCU->PLLCFGR = ((PLL_NF2_DIV & 0x0F) << 23) | (PLL_NO2_DIV << 21); /* set PLL divider */ + + #if (PLL_CLK_SRC_DIV == 1) + SetBit_BB((u32)(&HT_CKCU->PLLCFGR), 28); /* set PLL clock source divider */ + #else + ResetBit_BB((u32)(&HT_CKCU->PLLCFGR), 28); /* reset PLL clock source divider */ + #endif + + #if (PLL_CLK_SRC == 0) + ResetBit_BB((u32)(&HT_CKCU->GCFGR), 8); /* select PLL source as HSE */ + #else + SetBit_BB((u32)(&HT_CKCU->GCFGR), 8); /* select PLL source as HSI */ + #endif + + SetBit_BB((u32)(&HT_CKCU->GCCR), 9); /* enable PLL */ + while (!GetBit_BB((u32)(&HT_CKCU->GCSR), 1)){}; /* wait for PLL ready */ +#endif + + /* CK_AHB initiation */ +#if (WAIT_STATE == 9) + #if (__CK_AHB > WS1_CLK) + HT_FLASH->CFCR = (((HT_FLASH->CFCR) & ~7UL) | 3UL); /* auto-select wait state */ + #elif (__CK_AHB > WS0_CLK) + HT_FLASH->CFCR = (((HT_FLASH->CFCR) & ~7UL) | 2UL); /* auto-select wait state */ + #endif +#else + HT_FLASH->CFCR = (((HT_FLASH->CFCR) & ~7UL) | (WAIT_STATE + 1)); /* manual wait state */ +#endif + + HT_CKCU->AHBCFGR = HCLK_DIV; /* set CK_AHB prescaler */ + HT_CKCU->GCCR = ((HT_CKCU->GCCR & ~7UL) | HCLK_SRC); /* select CK_SYS source */ + while ((HT_CKCU->CKST & 7UL) != HCLK_SRC); /* wait for clock switch complete */ + + /* Pre-fetch buffer configuration */ +#if (PRE_FETCH_ENABLE == 0) + ResetBit_BB((u32)(&HT_FLASH->CFCR), 4); /* 0: pre-fetch disable, 1: pre-fetch enable */ +#else + SetBit_BB((u32)(&HT_FLASH->CFCR), 4); /* 0: pre-fetch disable, 1: pre-fetch enable */ +#endif + + /* HSE power down */ +#if ((HSE_ENABLE == 0) && (HCLK_SRC != 2) && ((PLL_ENABLE == 0) || (PLL_CLK_SRC == 1))) + ResetBit_BB((u32)(&HT_CKCU->GCCR), 10); +#endif + + /* HSI power down */ +#if ((HSI_ENABLE == 0) && (HCLK_SRC != 3) && ((PLL_ENABLE == 0) || (PLL_CLK_SRC == 0))) + ResetBit_BB((u32)(&HT_CKCU->GCCR), 11); +#endif +} + +/** + * @brief Update SystemCoreClock + * @retval None + */ +void SystemCoreClockUpdate(void) +{ + u32 SystemCoreClockDiv = HT_CKCU->AHBCFGR & 7UL; + u32 PllSourceClockDiv = (HT_CKCU->PLLCFGR >> 28) & 1UL; + u32 PllFeedbackClockDiv = (((HT_CKCU->PLLCFGR >> 23) & 15UL) == 0) ? (16) : ((HT_CKCU->PLLCFGR >> 23) & 15UL); + u32 PllOutputClockDiv = (HT_CKCU->PLLCFGR >> 21) & 3UL; + u32 SystemCoreClockSrc = HT_CKCU->CKST & 7UL; + u32 HseClockDiv = (HT_CKCU->GCFGR >> 16) & 3UL; + + /* Get system core clock according to global clock control & configuration registers */ + if (SystemCoreClockSrc == 1) + { + if (GetBit_BB((u32)(&HT_CKCU->PLLCR), 31)) + { + PllFeedbackClockDiv = 1; + PllOutputClockDiv = 0; + } + + if (GetBit_BB((u32)(&HT_CKCU->GCFGR), 8)) + { + SystemCoreClock = (((HSI_VALUE >> PllSourceClockDiv) * PllFeedbackClockDiv) >> PllOutputClockDiv) >> SystemCoreClockDiv; + } + else + { + SystemCoreClock = ((((HSE_VALUE >> HseClockDiv) >> PllSourceClockDiv) * PllFeedbackClockDiv) >> PllOutputClockDiv) >> SystemCoreClockDiv; + } + } + else if (SystemCoreClockSrc == 2) + { + SystemCoreClock = (HSE_VALUE >> HseClockDiv) >> SystemCoreClockDiv; + } + else if (SystemCoreClockSrc == 3) + { + SystemCoreClock = HSI_VALUE >> SystemCoreClockDiv; + } + else if (SystemCoreClockSrc == 6) + { + SystemCoreClock = LSE_VALUE >> SystemCoreClockDiv; + } + else if (SystemCoreClockSrc == 7) + { + SystemCoreClock = LSI_VALUE >> SystemCoreClockDiv; + } +} + +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ + +/******************* (C) COPYRIGHT Holtek Semiconductor Inc. *****END OF FILE*** */ diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/system_ht32f5xxxx_12.c b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/system_ht32f5xxxx_12.c new file mode 100644 index 0000000000..feca9dca25 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/system_ht32f5xxxx_12.c @@ -0,0 +1,485 @@ +/***************************************************************************//** + * @file library/Device/Holtek/HT32F5xxxx/Source/system_ht32f5xxxx_12.c + * @brief CMSIS Cortex-M0+ Device Peripheral Access Layer Source File + * for the Holtek HT32F5xxxx Device Series + * @version $Rev:: 6597 $ + * @date $Date:: 2022-12-27 #$ + * + * @note + * Copyright (C) Holtek Semiconductor Inc. All rights reserved. + * + * @par + * ARM Limited (ARM) supplies this software for Cortex-M processor-based + * microcontrollers. This file can be freely distributed within development + * tools that are supporting such ARM based processors. + * + * @par + * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR + * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + ******************************************************************************/ + +// Supported Device +// ======================================== +// HT32F61141 + +//#define USE_HT32F61141 + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup HT32F5xxxx_system HT32F5xxxx System + * @{ + */ + + +#include "ht32f5xxxx_01.h" + +/** @addtogroup HT32F5xxxx_System_Private_Defines + * @{ + */ +/* +//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ +*/ + +/*--------------------- Clock Configuration ---------------------------------- +// +// Enable High Speed External Crystal Oscillator (HSE) +// Default HSE = DISABLE +// +// Enable Low Speed External Crystal Oscillator (LSE) +// Default LSE = DISABLE +// +// Enable PLL +// Default PLL = DISABLE +// PLL Out = (((HSE or HSI) / SRC_DIV) x NF2 ) / NO2 +// PLL Clock Source +// <0=> CK_HSE +// <1=> CK_HSI +// Default PLL clock source = CK_HSI +// PLL source clock must be in the range of 4 MHz to 16 MHz +// PLL Clock Source Divider (SRC_DIV) +// <0=> 1 +// <1=> 2 +// PLL input clock = PLL Clock Source / (SRC_DIV) +// PLL Feedback Clock Divider (NF2): 1 ~ 16 +// <1-16:1> +// PLL feedback clock = PLL input clock x NF2 +// PLL feedback clock must be in the range of 24 MHz to 48 MHz +// PLL Output Clock Divider (NO2) +// <0=> 1 +// <1=> 2 +// <2=> 4 +// <3=> 8 +// PLL output clock = PLL feedback clock / NO2 +// PLL output clock must be in the range of 4 MHz to 48 MHz +// +// +// SystemCoreClock Configuration (CK_AHB) +// SystemCoreClock Source +// <1=> CK_PLL +// <2=> CK_HSE +// <3=> CK_HSI +// <6=> CK_LSE +// <7=> CK_LSI +// Default SystemCoreClock source = CK_HSI +// SystemCoreClock Source Divider +// <0=> 1 +// <1=> 2 +// <2=> 4 +// <3=> 8 +// <4=> 16 +// <5=> 32 +// Default SystemCoreClock source divider = 1 +// +// +// FLASH Configuration +// Wait state +// <0=> 0 WS +// <1=> 1 WS +// <2=> 2 WS +// <9=> AUTO +// 0 WS: 1 kHz <= CK_AHB <= 20 MHz +// 1 WS: 20 MHz < CK_AHB <= 40 MHz +// 2 WS: 40 MHz < CK_AHB <= 48 MHz +// Pre-fetch Buffer Enable +// Default pre-fetch buffer = ENABLE +// +*/ + +/* !!! NOTICE !!! + HSI must keep turn on when doing the Flash operation (Erase/Program). +*/ + +/* !!! NOTICE !!! + * How to adjust the value of High Speed External oscillator (HSE)? + The default value of HSE is define by "HSE_VALUE" in "ht32fxxxxx_nn.h". + If your board uses a different HSE speed, please add a new compiler preprocessor + C define, "HSE_VALUE=n000000" ("n" represents n MHz) in the toolchain/IDE, + or edit the "HSE_VALUE" in the "ht32f5xxxx_conf.h" file. + Take Keil MDK-ARM for instance, to set HSE as 16 MHz: + "Option of Taret -> C/C++ > Preprocessor Symbols" + Define: USE_HT32_DRIVER, USE_HT32Fxxxxx_SK, USE_HT32Fxxxxx_xx, USE_MEM_HT32Fxxxxx, HSE_VALUE=16000000 + ^^ Add "HSE_VALUE" + define as above. +*/ +#define HSI_ENABLE (1) /*!< 0: DISABLE, 1: ENABLE */ +#define HSE_ENABLE (1) /*!< 0: DISABLE, 1: ENABLE */ +#define LSI_ENABLE (1) /*!< 0: DISABLE, 1: ENABLE */ +#define LSE_ENABLE (0) /*!< 0: DISABLE, 1: ENABLE */ +#define PLL_ENABLE (1) /*!< 0: DISABLE, 1: ENABLE */ +#define PLL_CLK_SRC (0) /*!< 0: HSE, 1: HSI */ +#define PLL_CLK_SRC_DIV (0) /*!< 0: DIV1, 1: DIV2 */ +#define PLL_NF2_DIV (6) /*!< 1~16: DIV1~DIV16 */ +#define PLL_NO2_DIV (0) /*!< 0: DIV1, 1: DIV2, 2: DIV4, 3: DIV8 */ +#define HCLK_SRC (1) /*!< 0: PLL, 1: PLL, 2: HSE, 3: HSI 6: LSE, 7: LSI */ +#define HCLK_DIV (0) /*!< 0: DIV1, 1: DIV2, 2: DIV4, 3: DIV8, 4: DIV16, 5: DIV32 */ +#define WAIT_STATE (9) /*!< 0: WS = 0, 1: WS = 1, 2: WS = 2, 9: AUTO */ +#define PRE_FETCH_ENABLE (1) /*!< 0: DISABLE, 1: ENABLE */ +#define DEINIT_ENABLE (1) /* Set 0 for reduce code size */ + +/*----------------------------------------------------------------------------------------------------------*/ +/* PLL Out = (((HSE or HSI) / (PLL_CLK_SRC_DIV + 1)) x PLL_NF2) / PLL_NO2 */ +/*----------------------------------------------------------------------------------------------------------*/ + + +/*--------------------- WDT Configuration ---------------------------------- +// +// Enable WDT Configuration +// WDT Prescaler Selection +// <0=> CK_WDT / 1 +// <1=> CK_WDT / 2 +// <2=> CK_WDT / 4 +// <3=> CK_WDT / 8 +// <4=> CK_WDT / 16 +// <5=> CK_WDT / 32 +// <6=> CK_WDT / 64 +// <7=> CK_WDT / 128 +// WDT Reload Value <1-4095:1> +// Enable WDT Reset function +// WDT Sleep Halt mode +// <0=> No halt +// <1=> Halt in DeepSleep1 +// <2=> Halt in Sleep & DeepSleep1 +// +*/ +#define WDT_ENABLE (0) /*!< 0: DISABLE, 1: ENABLE */ +#define WDT_PRESCALER (5) /*!< 0: 1/1, 1: 1/2, 2: 1/4, 3: 1/8, 4: 1/16, 5: 1/32, 6: 1/64, 7: 1/128 */ +#define WDT_RELOAD (2000) /*!< 0 ~ 4095, 12 bit */ +#define WDT_RESET_ENABLE (1) /*!< 0: No Reset, 1: Reset when WDT over flow */ +#define WDT_SLEEP_HALT (2) /*!< 0: No halt, 1: Halt in DeepSleep1, 2: Halt in Sleep & DeepSleep1 */ + +/** + * @brief Check HSI frequency + */ +#if (HSI_VALUE != 8000000UL) + #error "CK_HSI clock issue: must be 8 MHz!" +#endif + +/** + * @brief Check HSE frequency + */ +#if ((HSE_VALUE < 4000000UL) || (HSE_VALUE > 16000000UL)) + #error "CK_HSE clock issue: must be in the range of 4 MHz to 16 MHz!" +#endif + +/** + * @brief Check LSI frequency + */ +#if (LSI_VALUE != 32000UL) + #error "CK_LSI clock issue: must be 32 kHz!" +#endif + +/** + * @brief Check LSE frequency + */ +#if (LSE_VALUE != 32768UL) + #error "CK_LSE clock issue: must be 32.768 kHz!" +#endif + +/** + * @brief CK_PLL definition + */ +#if (PLL_ENABLE == 1) + /* Get CK_VCO frequency */ + #if (PLL_CLK_SRC == 1) + #if (HSI_ENABLE == 0) + #error "CK_PLL clock source issue: HSI has not been enabled" + #else + #define __CK_VCO ((HSI_VALUE >> PLL_CLK_SRC_DIV) * PLL_NF2_DIV) /*!< Select HSI as PLL source */ + #endif + #else + #if (HSE_ENABLE == 0) + #error "CK_PLL clock source issue: HSE has not been enabled!" + #else + #define __CK_VCO ((HSE_VALUE >> PLL_CLK_SRC_DIV) * PLL_NF2_DIV) /*!< Select HSE as PLL source */ + #endif + #endif + + #define VCO_MIN 24000000UL + #define VCO_MAX 48000000UL + #define PLL_MIN 4000000UL + #define PLL_MAX 48000000UL + + /* Check CK_VCO frequency */ + #if ((__CK_VCO < VCO_MIN) || (__CK_VCO > VCO_MAX)) + #error "CK_VCO clock issue: must be in the range!" + #endif + + #define __CK_PLL (__CK_VCO >> PLL_NO2_DIV) /*!< Get CK_PLL frequency */ + + /* Check CK_PLL frequency */ + #if ((__CK_PLL < PLL_MIN) || (__CK_PLL > PLL_MAX)) + #error "CK_PLL clock issue: must be in the range!" + #endif +#endif + +/** + * @brief CK_SYS definition + */ +#if (HCLK_SRC == 1) + #if (PLL_ENABLE == 1) + #define __CK_SYS __CK_PLL /*!< Select PLL as CK_SYS source */ + #else + #error "CK_SYS clock source issue: PLL is not enable!" + #endif +#elif (HCLK_SRC == 2) + #if (HSE_ENABLE == 1) + #define __CK_SYS HSE_VALUE /*!< Select HSE as CK_SYS source */ + #else + #error "CK_SYS clock source issue: HSE is not enable!" + #endif +#elif (HCLK_SRC == 3) + #if (HSI_ENABLE == 1) + #define __CK_SYS HSI_VALUE /*!< Select HSI as CK_SYS source */ + #else + #error "CK_SYS clock source issue: HSI is not enable!" + #endif +#elif (HCLK_SRC == 6) + #if (LSE_ENABLE == 1) + #define __CK_SYS LSE_VALUE /*!< Select LSE as CK_SYS source */ + #else + #error "CK_SYS clock source issue: LSE is not enable!" + #endif +#elif (HCLK_SRC == 7) + #if (LSI_ENABLE == 1) + #define __CK_SYS LSI_VALUE /*!< Select LSI as CK_SYS source */ + #else + #error "CK_SYS clock source issue: LSI is not enable!" + #endif +#else + #error "CK_SYS clock source issue: No clock source is selected!" +#endif + +/** + * @brief CK_AHB definition + */ +#define __CK_AHB (__CK_SYS >> HCLK_DIV) /*!< Get CK_AHB frequency */ + +#define CKAHB_MIN 1000UL +#define CKAHB_MAX 48000000UL +#define WS0_CLK 20000000UL +#define WS1_CLK 40000000UL + +/* Check CK_AHB frequency */ +#if ((__CK_AHB < CKAHB_MIN) || (__CK_AHB > CKAHB_MAX)) + #error "CK_AHB clock issue: must be in the range!" +#endif + +/* Check FLASH wait-state setting */ +#if ((__CK_AHB > WS1_CLK) && (WAIT_STATE < 2) || \ + (__CK_AHB > WS0_CLK) && (WAIT_STATE < 1)) + #error "FLASH wait state configuration issue!" +#endif +/** + * @} + */ + +/** @addtogroup HT32F5xxxx_System_Private_Variables + * @{ + */ +__IO uint32_t SystemCoreClock = __CK_AHB; /*!< SystemCoreClock = CK_AHB */ +/** + * @} + */ + +/** @addtogroup HT32F5xxxx_System_Private_Functions + * @{ + */ + +/** + * @brief Setup the microcontroller system. + * Initializes the system clocks and the embedded Flash. + * @note This function should be used after reset. + * @retval None + */ +void SystemInit(void) +{ +#if (WDT_ENABLE == 1) + HT_CKCU->APBCCR1 |= (0x1 << 4); + HT_WDT->PR = 0x35CA; + HT_WDT->MR0 = 0; + HT_WDT->MR1 = ((HT_WDT->MR1 & 0xFFF) | (WDT_PRESCALER << 12)); + HT_WDT->MR0 = WDT_RELOAD | (WDT_RESET_ENABLE << 13) | (WDT_SLEEP_HALT << 14) | (0x1 << 16); + HT_WDT->CR = 0x5FA00001; +#else + #if (DEINIT_ENABLE == 1) + HT_RSTCU->APBPRST1 = (1 << 4); + #endif +#endif + + SetBit_BB((u32)(&HT_CKCU->APBCCR1), 6); /* enable VDD power domain register clock */ + + #if (DEINIT_ENABLE == 1) + /* De-init the setting */ + HT_CKCU->AHBCCR &= ~(0x3 << 10); /* disable IP who may use PLL as source */ + SetBit_BB((u32)(&HT_CKCU->GCCR), 11); /* enable HSI */ + while (!GetBit_BB((u32)(&HT_CKCU->GCSR), 3)); /* wait for HSI ready */ + HT_CKCU->GCCR = ((HT_CKCU->GCCR & ~7UL) | 3UL); /* select CK_SYS source */ + while ((HT_CKCU->CKST & 7UL) != 3UL); /* wait for clock switch complete */ + HT_FLASH->CFCR = (((HT_FLASH->CFCR) & ~7UL) | 1UL); /* set Wait State as 0 WS */ + HT_CKCU->AHBCFGR = 0; /* set CK_AHB prescaler */ + ResetBit_BB((u32)(&HT_CKCU->GCCR), 9); /* disable PLL */ + SetBit_BB((u32)(&HT_CKCU->GCFGR), 8); /* select PLL source as HSI */ + #endif + + /* HSE initiation */ +#if (HSE_ENABLE == 1) + SetBit_BB((u32)(&HT_CKCU->GCCR), 10); /* enable HSE */ + while (!GetBit_BB((u32)(&HT_CKCU->GCSR), 2)){}; /* wait for HSE ready */ +#endif + + /* LSE initiation */ +#if (LSE_ENABLE == 1) + do { + SetBit_BB((u32)(&HT_RTC->CR), 3); /* enable LSE */ + } while (!GetBit_BB((u32)(&HT_RTC->CR), 3)); + while (!GetBit_BB((u32)(&HT_CKCU->GCSR), 4)); /* wait for LSE ready */ +#endif + + ResetBit_BB((u32)(&HT_CKCU->APBCCR1), 6); /* disable VDD power domain register clock */ + + /* LSI initiation */ +#if (HCLK_SRC == 7) + while (!GetBit_BB((u32)(&HT_CKCU->GCSR), 5)){}; /* wait for LSI ready */ +#endif + + /* PLL initiation */ +#if (PLL_ENABLE == 1) + HT_CKCU->PLLCFGR = ((PLL_NF2_DIV & 0x0F) << 23) | (PLL_NO2_DIV << 21); /* set PLL divider */ + + #if (PLL_CLK_SRC_DIV == 1) + SetBit_BB((u32)(&HT_CKCU->PLLCFGR), 28); /* set PLL clock source divider */ + #else + ResetBit_BB((u32)(&HT_CKCU->PLLCFGR), 28); /* reset PLL clock source divider */ + #endif + + #if (PLL_CLK_SRC == 0) + ResetBit_BB((u32)(&HT_CKCU->GCFGR), 8); /* select PLL source as HSE */ + #else + SetBit_BB((u32)(&HT_CKCU->GCFGR), 8); /* select PLL source as HSI */ + #endif + + SetBit_BB((u32)(&HT_CKCU->GCCR), 9); /* enable PLL */ + while (!GetBit_BB((u32)(&HT_CKCU->GCSR), 1)){}; /* wait for PLL ready */ +#endif + + /* CK_AHB initiation */ +#if (WAIT_STATE == 9) + #if (__CK_AHB > WS1_CLK) + HT_FLASH->CFCR = (((HT_FLASH->CFCR) & ~7UL) | 3UL); /* auto-select wait state */ + #elif (__CK_AHB > WS0_CLK) + HT_FLASH->CFCR = (((HT_FLASH->CFCR) & ~7UL) | 2UL); /* auto-select wait state */ + #endif +#else + HT_FLASH->CFCR = (((HT_FLASH->CFCR) & ~7UL) | (WAIT_STATE + 1)); /* manual wait state */ +#endif + + HT_CKCU->AHBCFGR = HCLK_DIV; /* set CK_AHB prescaler */ + HT_CKCU->GCCR = ((HT_CKCU->GCCR & ~7UL) | HCLK_SRC); /* select CK_SYS source */ + while ((HT_CKCU->CKST & 7UL) != HCLK_SRC); /* wait for clock switch complete */ + + /* Pre-fetch buffer configuration */ +#if (PRE_FETCH_ENABLE == 0) + ResetBit_BB((u32)(&HT_FLASH->CFCR), 4); /* 0: pre-fetch disable, 1: pre-fetch enable */ +#else + SetBit_BB((u32)(&HT_FLASH->CFCR), 4); /* 0: pre-fetch disable, 1: pre-fetch enable */ +#endif + + /* HSE power down */ +#if ((HSE_ENABLE == 0) && (HCLK_SRC != 2) && ((PLL_ENABLE == 0) || (PLL_CLK_SRC == 1))) + ResetBit_BB((u32)(&HT_CKCU->GCCR), 10); +#endif + + /* HSI power down */ +#if ((HSI_ENABLE == 0) && (HCLK_SRC != 3) && ((PLL_ENABLE == 0) || (PLL_CLK_SRC == 0))) + ResetBit_BB((u32)(&HT_CKCU->GCCR), 11); +#endif +} + +/** + * @brief Update SystemCoreClock + * @retval None + */ +void SystemCoreClockUpdate(void) +{ + u32 SystemCoreClockDiv = HT_CKCU->AHBCFGR & 7UL; + u32 PllSourceClockDiv = (HT_CKCU->PLLCFGR >> 28) & 1UL; + u32 PllFeedbackClockDiv = (((HT_CKCU->PLLCFGR >> 23) & 15UL) == 0) ? (16) : ((HT_CKCU->PLLCFGR >> 23) & 15UL); + u32 PllOutputClockDiv = (HT_CKCU->PLLCFGR >> 21) & 3UL; + u32 SystemCoreClockSrc = HT_CKCU->CKST & 7UL; + + /* Get system core clock according to global clock control & configuration registers */ + if (SystemCoreClockSrc == 1) + { + if (GetBit_BB((u32)(&HT_CKCU->PLLCR), 31)) + { + PllFeedbackClockDiv = 1; + PllOutputClockDiv = 0; + } + + if (GetBit_BB((u32)(&HT_CKCU->GCFGR), 8)) + { + SystemCoreClock = (((HSI_VALUE >> PllSourceClockDiv) * PllFeedbackClockDiv) >> PllOutputClockDiv) >> SystemCoreClockDiv; + } + else + { + SystemCoreClock = (((HSE_VALUE >> PllSourceClockDiv) * PllFeedbackClockDiv) >> PllOutputClockDiv) >> SystemCoreClockDiv; + } + } + else if (SystemCoreClockSrc == 2) + { + SystemCoreClock = HSE_VALUE >> SystemCoreClockDiv; + } + else if (SystemCoreClockSrc == 3) + { + SystemCoreClock = HSI_VALUE >> SystemCoreClockDiv; + } + else if (SystemCoreClockSrc == 6) + { + SystemCoreClock = LSE_VALUE >> SystemCoreClockDiv; + } + else if (SystemCoreClockSrc == 7) + { + SystemCoreClock = LSI_VALUE >> SystemCoreClockDiv; + } +} + +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ + +/******************* (C) COPYRIGHT Holtek Semiconductor Inc. *****END OF FILE*** */ diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/system_ht32f5xxxx_13.c b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/system_ht32f5xxxx_13.c new file mode 100644 index 0000000000..c906eb1640 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/system_ht32f5xxxx_13.c @@ -0,0 +1,325 @@ +/**************************************************************************//** + * @file library/Device/Holtek/HT32F5xxxx/Source/system_ht32f5xxxx_13.c + * @brief CMSIS Cortex-M0+ Device Peripheral Access Layer Source File + * for the Holtek HT32F5xxxx Device Series + * @version $Rev:: 7119 $ + * @date $Date:: 2023-08-15 #$ + * + * @note + * Copyright (C) Holtek Semiconductor Inc. All rights reserved. + * + * @par + * ARM Limited (ARM) supplies this software for Cortex-M processor-based + * microcontrollers. This file can be freely distributed within development + * tools that are supporting such ARM based processors. + * + * @par + * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR + * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + ******************************************************************************/ + +// Supported Device +// ======================================== +// HT32F50020, HT32F50030 +// HT32F61630 +// HT32F61030 + +//#define USE_HT32F50020_30 +//#define USE_HT32F61630 +//#define USE_HT32F61030 + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup HT32F5xxxx_system HT32F5xxxx System + * @{ + */ + + +#include "ht32f5xxxx_01.h" + +/** @addtogroup HT32F5xxxx_System_Private_Defines + * @{ + */ +/* +//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ +*/ + +/*--------------------- Clock Configuration ---------------------------------- +// +// Enable High Speed External Crystal Oscillator (HSE) +// Default HSE = DISABLE +// +// Enable Low Speed External Crystal Oscillator (LSE) +// Default LSE = DISABLE +// +// SystemCoreClock Configuration (CK_AHB) +// SystemCoreClock Source +// <2=> CK_HSE +// <3=> CK_HSI +// <6=> CK_LSE +// <7=> CK_LSI +// Default SystemCoreClock source = CK_HSI +// SystemCoreClock Source Divider +// <0=> 1 +// <1=> 2 +// <2=> 4 +// <3=> 8 +// <4=> 16 +// <5=> 32 +// Default SystemCoreClock source divider = 2 +// +*/ + +/* !!! NOTICE !!! + HSI must keep turn on when doing the Flash operation (Erase/Program). +*/ + +/* !!! NOTICE !!! + * How to adjust the value of High Speed External oscillator (HSE)? + The default value of HSE is define by "HSE_VALUE" in "ht32fxxxxx_nn.h". + If your board uses a different HSE speed, please add a new compiler preprocessor + C define, "HSE_VALUE=n000000" ("n" represents n MHz) in the toolchain/IDE, + or edit the "HSE_VALUE" in the "ht32f5xxxx_conf.h" file. + Take Keil MDK-ARM for instance, to set HSE as 16 MHz: + "Option of Taret -> C/C++ > Preprocessor Symbols" + Define: USE_HT32_DRIVER, USE_HT32Fxxxxx_SK, USE_HT32Fxxxxx_xx, USE_MEM_HT32Fxxxxx, HSE_VALUE=16000000 + ^^ Add "HSE_VALUE" + define as above. +*/ +#define HSI_ENABLE (1) /*!< 0: DISABLE, 1: ENABLE */ +#define HSE_ENABLE (1) /*!< 0: DISABLE, 1: ENABLE */ +#define LSI_ENABLE (1) /*!< 0: DISABLE, 1: ENABLE */ +#define LSE_ENABLE (0) /*!< 0: DISABLE, 1: ENABLE */ +#define HCLK_SRC (2) /*!< 0: N/A 1: N/A 2: HSE, 3: HSI 6: LSE, 7: LSI */ +#define HCLK_DIV (0) /*!< 0: DIV1, 1: DIV2, 2: DIV4, 3: DIV8, 4: DIV16, 5: DIV32 */ +#define DEINIT_ENABLE (1) /* Set 0 for reduce code size */ + +/*--------------------- WDT Configuration ---------------------------------- +// +// Enable WDT Configuration +// WDT Prescaler Selection +// <0=> CK_WDT / 1 +// <1=> CK_WDT / 2 +// <2=> CK_WDT / 4 +// <3=> CK_WDT / 8 +// <4=> CK_WDT / 16 +// <5=> CK_WDT / 32 +// <6=> CK_WDT / 64 +// <7=> CK_WDT / 128 +// WDT Reload Value <1-4095:1> +// Enable WDT Reset function +// WDT Sleep Halt mode +// <0=> No halt +// <1=> Halt in DeepSleep1 +// <2=> Halt in Sleep & DeepSleep1 +// +*/ +#define WDT_ENABLE (0) /*!< 0: DISABLE, 1: ENABLE */ +#define WDT_PRESCALER (5) /*!< 0: 1/1, 1: 1/2, 2: 1/4, 3: 1/8, 4: 1/16, 5: 1/32, 6: 1/64, 7: 1/128 */ +#define WDT_RELOAD (2000) /*!< 0 ~ 4095, 12 bit */ +#define WDT_RESET_ENABLE (1) /*!< 0: No Reset, 1: Reset when WDT over flow */ +#define WDT_SLEEP_HALT (2) /*!< 0: No halt, 1: Halt in DeepSleep1, 2: Halt in Sleep & DeepSleep1 */ + +/** + * @brief Check HSI frequency + */ +#if (HSI_VALUE != 16000000UL) + #error "CK_HSI clock issue: must be 16 MHz!" +#endif + +/** + * @brief Check HSE frequency + */ +#if ((HSE_VALUE < 4000000UL) || (HSE_VALUE > 16000000UL)) + #error "CK_HSE clock issue: must be in the range of 4 MHz to 16 MHz!" +#endif + +/** + * @brief Check LSI frequency + */ +#if (LSI_VALUE != 32000UL) + #error "CK_LSI clock issue: must be 32 kHz!" +#endif + +/** + * @brief Check LSE frequency + */ +#if (LSE_VALUE != 32768UL) + #error "CK_LSE clock issue: must be 32.768 kHz!" +#endif + +/** + * @brief CK_SYS definition + */ +#if (HCLK_SRC == 2) + #if (HSE_ENABLE == 1) + #define __CK_SYS HSE_VALUE /*!< Select HSE as CK_SYS source */ + #else + #error "CK_SYS clock source issue: HSE is not enable!" + #endif +#elif (HCLK_SRC == 3) + #if (HSI_ENABLE == 1) + #define __CK_SYS HSI_VALUE /*!< Select HSI as CK_SYS source */ + #else + #error "CK_SYS clock source issue: HSI is not enable!" + #endif +#elif (HCLK_SRC == 6) + #if (LSE_ENABLE == 1) + #define __CK_SYS LSE_VALUE /*!< Select LSE as CK_SYS source */ + #else + #error "CK_SYS clock source issue: LSE is not enable!" + #endif +#elif (HCLK_SRC == 7) + #if (LSI_ENABLE == 1) + #define __CK_SYS LSI_VALUE /*!< Select LSI as CK_SYS source */ + #else + #error "CK_SYS clock source issue: LSI is not enable!" + #endif +#else + #error "CK_SYS clock source issue: No clock source is selected!" +#endif + +/** + * @brief CK_AHB definition + */ +#define __CK_AHB (__CK_SYS >> HCLK_DIV) /*!< Get CK_AHB frequency */ + +#define CKAHB_MIN 1000UL +#define CKAHB_MAX 16000000UL + +/* Check CK_AHB frequency */ +#if ((__CK_AHB < CKAHB_MIN) || (__CK_AHB > CKAHB_MAX)) + #error "CK_AHB clock issue: must be in the range!" +#endif +/** + * @} + */ + +/** @addtogroup HT32F5xxxx_System_Private_Variables + * @{ + */ +__IO uint32_t SystemCoreClock = __CK_AHB; /*!< SystemCoreClock = CK_AHB */ +/** + * @} + */ + +/** @addtogroup HT32F5xxxx_System_Private_Functions + * @{ + */ + +/** + * @brief Setup the microcontroller system. + * Initializes the system clocks and the embedded Flash. + * @note This function should be used after reset. + * @retval None + */ +void SystemInit(void) +{ +#if (WDT_ENABLE == 1) + HT_CKCU->APBCCR1 |= (0x1 << 4); + HT_WDT->PR = 0x35CA; + HT_WDT->MR0 = 0; + HT_WDT->MR1 = ((HT_WDT->MR1 & 0xFFF) | (WDT_PRESCALER << 12)); + HT_WDT->MR0 = WDT_RELOAD | (WDT_RESET_ENABLE << 13) | (WDT_SLEEP_HALT << 14) | (0x1 << 16); + HT_WDT->CR = 0x5FA00001; +#else + #if (DEINIT_ENABLE == 1) + HT_RSTCU->APBPRST1 = (1 << 4); + #endif +#endif + + SetBit_BB((u32)(&HT_CKCU->APBCCR1), 6); /* enable VDD power domain register clock */ + + #if (DEINIT_ENABLE == 1) + /* De-init the setting */ + SetBit_BB((u32)(&HT_CKCU->GCCR), 11); /* enable HSI */ + while (!GetBit_BB((u32)(&HT_CKCU->GCSR), 3)); /* wait for HSI ready */ + HT_CKCU->GCCR = ((HT_CKCU->GCCR & ~7UL) | 3UL); /* select CK_SYS source */ + while ((HT_CKCU->CKST & 7UL) != 3UL); /* wait for clock switch complete */ + HT_CKCU->AHBCFGR = 1; /* set CK_AHB prescaler */ + #endif + + /* HSE initiation */ +#if (HSE_ENABLE == 1) + SetBit_BB((u32)(&HT_CKCU->GCCR), 10); /* enable HSE */ + while (!GetBit_BB((u32)(&HT_CKCU->GCSR), 2)){}; /* wait for HSE ready */ +#endif + + /* LSE initiation */ +#if (LSE_ENABLE == 1) + do { + SetBit_BB((u32)(&HT_RTC->CR), 3); /* enable LSE */ + } while (!GetBit_BB((u32)(&HT_RTC->CR), 3)); + while (!GetBit_BB((u32)(&HT_CKCU->GCSR), 4)); /* wait for LSE ready */ +#endif + + ResetBit_BB((u32)(&HT_CKCU->APBCCR1), 6); /* disable Backup domain register clock */ + + /* LSI initiation */ +#if (HCLK_SRC == 7) + while (!GetBit_BB((u32)(&HT_CKCU->GCSR), 5)){}; /* wait for LSI ready */ +#endif + + HT_CKCU->AHBCFGR = HCLK_DIV; /* set CK_AHB prescaler */ + HT_CKCU->GCCR = ((HT_CKCU->GCCR & ~7UL) | HCLK_SRC); /* select CK_SYS source */ + while ((HT_CKCU->CKST & 7UL) != HCLK_SRC); /* wait for clock switch complete */ + + /* HSE power down */ +#if ((HSE_ENABLE == 0) && (HCLK_SRC != 2)) + ResetBit_BB((u32)(&HT_CKCU->GCCR), 10); +#endif + + /* HSI power down */ +#if ((HSI_ENABLE == 0) && (HCLK_SRC != 3)) + ResetBit_BB((u32)(&HT_CKCU->GCCR), 11); +#endif +} + +/** + * @brief Update SystemCoreClock + * @retval None + */ +void SystemCoreClockUpdate(void) +{ + u32 SystemCoreClockDiv = HT_CKCU->AHBCFGR & 7UL; + u32 SystemCoreClockSrc = HT_CKCU->CKST & 7UL; + + /* Get system core clock according to global clock control & configuration registers */ + if (SystemCoreClockSrc == 2) + { + SystemCoreClock = HSE_VALUE >> SystemCoreClockDiv; + } + else if (SystemCoreClockSrc == 3) + { + SystemCoreClock = HSI_VALUE >> SystemCoreClockDiv; + } + else if (SystemCoreClockSrc == 6) + { + SystemCoreClock = LSE_VALUE >> SystemCoreClockDiv; + } + else if (SystemCoreClockSrc == 7) + { + SystemCoreClock = LSI_VALUE >> SystemCoreClockDiv; + } +} + +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ + +/******************* (C) COPYRIGHT Holtek Semiconductor Inc. *****END OF FILE*** */ diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/system_ht32f5xxxx_14.c b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/system_ht32f5xxxx_14.c new file mode 100644 index 0000000000..2dc4216f4b --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/system_ht32f5xxxx_14.c @@ -0,0 +1,487 @@ +/**************************************************************************//** + * @file library/Device/Holtek/HT32F5xxxx/Source/system_ht32f5xxxx_14.c + * @brief CMSIS Cortex-M0+ Device Peripheral Access Layer Source File + * for the Holtek HT32F5xxxx Device Series + * @version $Rev:: 6790 $ + * @date $Date:: 2023-03-13 #$ + * + * @note + * Copyright (C) Holtek Semiconductor Inc. All rights reserved. + * + * @par + * ARM Limited (ARM) supplies this software for Cortex-M processor-based + * microcontrollers. This file can be freely distributed within development + * tools that are supporting such ARM based processors. + * + * @par + * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR + * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + ******************************************************************************/ + +// Supported Device +// ======================================== +// HT32F50442, HT32F50452 +// HT32F50431, HT32F50441 + +//#define USE_HT32F50442_52 +//#define USE_HT32F50431_41 + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup HT32F5xxxx_system HT32F5xxxx System + * @{ + */ + + +#include "ht32f5xxxx_01.h" + +/** @addtogroup HT32F5xxxx_System_Private_Defines + * @{ + */ +/* +//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ +*/ + +/*--------------------- Clock Configuration ---------------------------------- +// +// Enable High Speed External Crystal Oscillator (HSE) +// Default HSE = DISABLE +// +// Enable Low Speed External Crystal Oscillator (LSE) +// Default LSE = DISABLE +// +// Enable PLL +// Default PLL = DISABLE +// PLL Out = (((HSE or HSI) / SRC_DIV) x NF2 ) / NO2 +// PLL Clock Source +// <0=> CK_HSE +// <1=> CK_HSI +// Default PLL clock source = CK_HSI +// PLL source clock must be in the range of 4 MHz to 16 MHz +// PLL Clock Source Divider (SRC_DIV) +// <0=> 1 +// <1=> 2 +// PLL input clock = PLL Clock Source / (SRC_DIV) +// PLL Feedback Clock Divider (NF2): 1 ~ 16 +// <1-16:1> +// PLL feedback clock = PLL input clock x NF2 +// PLL feedback clock must be in the range of 24 MHz to 60 MHz +// PLL Output Clock Divider (NO2) +// <0=> 1 +// <1=> 2 +// <2=> 4 +// <3=> 8 +// PLL output clock = PLL feedback clock / NO2 +// PLL output clock must be in the range of 4 MHz to 60 MHz +// +// +// SystemCoreClock Configuration (CK_AHB) +// SystemCoreClock Source +// <1=> CK_PLL +// <2=> CK_HSE +// <3=> CK_HSI +// <6=> CK_LSE +// <7=> CK_LSI +// Default SystemCoreClock source = CK_HSI +// SystemCoreClock Source Divider +// <0=> 1 +// <1=> 2 +// <2=> 4 +// <3=> 8 +// <4=> 16 +// <5=> 32 +// Default SystemCoreClock source divider = 1 +// +// +// FLASH Configuration +// Wait state +// <0=> 0 WS +// <1=> 1 WS +// <2=> 2 WS +// <9=> AUTO +// 0 WS: 1 kHz <= CK_AHB <= 20 MHz +// 1 WS: 20 MHz < CK_AHB <= 40 MHz +// 2 WS: 40 MHz < CK_AHB <= 60 MHz +// Pre-fetch Buffer Enable +// Default pre-fetch buffer = ENABLE +// +*/ + +/* !!! NOTICE !!! + HSI must keep turn on when doing the Flash operation (Erase/Program). +*/ + +/* !!! NOTICE !!! + * How to adjust the value of High Speed External oscillator (HSE)? + The default value of HSE is define by "HSE_VALUE" in "ht32fxxxxx_nn.h". + If your board uses a different HSE speed, please add a new compiler preprocessor + C define, "HSE_VALUE=n000000" ("n" represents n MHz) in the toolchain/IDE, + or edit the "HSE_VALUE" in the "ht32f5xxxx_conf.h" file. + Take Keil MDK-ARM for instance, to set HSE as 16 MHz: + "Option of Taret -> C/C++ > Preprocessor Symbols" + Define: USE_HT32_DRIVER, USE_HT32Fxxxxx_SK, USE_HT32Fxxxxx_xx, USE_MEM_HT32Fxxxxx, HSE_VALUE=16000000 + ^^ Add "HSE_VALUE" + define as above. +*/ +#define HSI_ENABLE (1) /*!< 0: DISABLE, 1: ENABLE */ +#define HSE_ENABLE (1) /*!< 0: DISABLE, 1: ENABLE */ +#define LSI_ENABLE (1) /*!< 0: DISABLE, 1: ENABLE */ +#define LSE_ENABLE (0) /*!< 0: DISABLE, 1: ENABLE */ +#define PLL_ENABLE (1) /*!< 0: DISABLE, 1: ENABLE */ +#define PLL_CLK_SRC (0) /*!< 0: HSE, 1: HSI */ +#define PLL_CLK_SRC_DIV (1) /*!< 0: DIV1, 1: DIV2 */ +#define PLL_NF2_DIV (15) /*!< 1~16: DIV1~DIV16 */ +#define PLL_NO2_DIV (0) /*!< 0: DIV1, 1: DIV2, 2: DIV4, 3: DIV8 */ +#define HCLK_SRC (1) /*!< 0: PLL, 1: PLL, 2: HSE, 3: HSI 6: LSE, 7: LSI */ +#define HCLK_DIV (0) /*!< 0: DIV1, 1: DIV2, 2: DIV4, 3: DIV8, 4: DIV16, 5: DIV32 */ +#define WAIT_STATE (9) /*!< 0: WS = 0, 1: WS = 1, 2: WS = 2, 9: AUTO */ +#define PRE_FETCH_ENABLE (1) /*!< 0: DISABLE, 1: ENABLE */ +#define DEINIT_ENABLE (1) /* Set 0 for reduce code size */ + +/*----------------------------------------------------------------------------------------------------------*/ +/* PLL Out = (((HSE or HSI) / (PLL_CLK_SRC_DIV + 1)) x PLL_NF2) / PLL_NO2 */ +/*----------------------------------------------------------------------------------------------------------*/ + + +/*--------------------- WDT Configuration ---------------------------------- +// +// Enable WDT Configuration +// WDT Prescaler Selection +// <0=> CK_WDT / 1 +// <1=> CK_WDT / 2 +// <2=> CK_WDT / 4 +// <3=> CK_WDT / 8 +// <4=> CK_WDT / 16 +// <5=> CK_WDT / 32 +// <6=> CK_WDT / 64 +// <7=> CK_WDT / 128 +// WDT Reload Value <1-4095:1> +// Enable WDT Reset function +// WDT Sleep Halt mode +// <0=> No halt +// <1=> Halt in DeepSleep1 +// <2=> Halt in Sleep & DeepSleep1 +// +*/ +#define WDT_ENABLE (0) /*!< 0: DISABLE, 1: ENABLE */ +#define WDT_PRESCALER (5) /*!< 0: 1/1, 1: 1/2, 2: 1/4, 3: 1/8, 4: 1/16, 5: 1/32, 6: 1/64, 7: 1/128 */ +#define WDT_RELOAD (2000) /*!< 0 ~ 4095, 12 bit */ +#define WDT_RESET_ENABLE (1) /*!< 0: No Reset, 1: Reset when WDT over flow */ +#define WDT_SLEEP_HALT (2) /*!< 0: No halt, 1: Halt in DeepSleep1, 2: Halt in Sleep & DeepSleep1 */ + +/** + * @brief Check HSI frequency + */ +#if (HSI_VALUE != 8000000UL) + #error "CK_HSI clock issue: must be 8 MHz!" +#endif + +/** + * @brief Check HSE frequency + */ +#if ((HSE_VALUE < 4000000UL) || (HSE_VALUE > 16000000UL)) + #error "CK_HSE clock issue: must be in the range of 4 MHz to 16 MHz!" +#endif + +/** + * @brief Check LSI frequency + */ +#if (LSI_VALUE != 32000UL) + #error "CK_LSI clock issue: must be 32 kHz!" +#endif + +/** + * @brief Check LSE frequency + */ +#if (LSE_VALUE != 32768UL) + #error "CK_LSE clock issue: must be 32.768 kHz!" +#endif + +/** + * @brief CK_PLL definition + */ +#if (PLL_ENABLE == 1) + /* Get CK_VCO frequency */ + #if (PLL_CLK_SRC == 1) + #if (HSI_ENABLE == 0) + #error "CK_PLL clock source issue: HSI has not been enabled" + #else + #define __CK_VCO ((HSI_VALUE >> PLL_CLK_SRC_DIV) * PLL_NF2_DIV) /*!< Select HSI as PLL source */ + #endif + #else + #if (HSE_ENABLE == 0) + #error "CK_PLL clock source issue: HSE has not been enabled!" + #else + #define __CK_VCO ((HSE_VALUE >> PLL_CLK_SRC_DIV) * PLL_NF2_DIV) /*!< Select HSE as PLL source */ + #endif + #endif + + #define VCO_MIN 24000000UL + #define VCO_MAX 60000000UL + #define PLL_MIN 4000000UL + #define PLL_MAX 60000000UL + + /* Check CK_VCO frequency */ + #if ((__CK_VCO < VCO_MIN) || (__CK_VCO > VCO_MAX)) + #error "CK_VCO clock issue: must be in the range!" + #endif + + #define __CK_PLL (__CK_VCO >> PLL_NO2_DIV) /*!< Get CK_PLL frequency */ + + /* Check CK_PLL frequency */ + #if ((__CK_PLL < PLL_MIN) || (__CK_PLL > PLL_MAX)) + #error "CK_PLL clock issue: must be in the range!" + #endif +#endif + +/** + * @brief CK_SYS definition + */ +#if (HCLK_SRC == 1) + #if (PLL_ENABLE == 1) + #define __CK_SYS __CK_PLL /*!< Select PLL as CK_SYS source */ + #else + #error "CK_SYS clock source issue: PLL is not enable!" + #endif +#elif (HCLK_SRC == 2) + #if (HSE_ENABLE == 1) + #define __CK_SYS HSE_VALUE /*!< Select HSE as CK_SYS source */ + #else + #error "CK_SYS clock source issue: HSE is not enable!" + #endif +#elif (HCLK_SRC == 3) + #if (HSI_ENABLE == 1) + #define __CK_SYS HSI_VALUE /*!< Select HSI as CK_SYS source */ + #else + #error "CK_SYS clock source issue: HSI is not enable!" + #endif +#elif (HCLK_SRC == 6) + #if (LSE_ENABLE == 1) + #define __CK_SYS LSE_VALUE /*!< Select LSE as CK_SYS source */ + #else + #error "CK_SYS clock source issue: LSE is not enable!" + #endif +#elif (HCLK_SRC == 7) + #if (LSI_ENABLE == 1) + #define __CK_SYS LSI_VALUE /*!< Select LSI as CK_SYS source */ + #else + #error "CK_SYS clock source issue: LSI is not enable!" + #endif +#else + #error "CK_SYS clock source issue: No clock source is selected!" +#endif + +/** + * @brief CK_AHB definition + */ +#define __CK_AHB (__CK_SYS >> HCLK_DIV) /*!< Get CK_AHB frequency */ + +#define CKAHB_MIN 1000UL +#define CKAHB_MAX 60000000UL +#define WS0_CLK 20000000UL +#define WS1_CLK 40000000UL + +/* Check CK_AHB frequency */ +#if ((__CK_AHB < CKAHB_MIN) || (__CK_AHB > CKAHB_MAX)) + #error "CK_AHB clock issue: must be in the range!" +#endif + +/* Check FLASH wait-state setting */ +#if ((__CK_AHB > WS1_CLK) && (WAIT_STATE < 2) || \ + (__CK_AHB > WS0_CLK) && (WAIT_STATE < 1)) + #error "FLASH wait state configuration issue!" +#endif +/** + * @} + */ + +/** @addtogroup HT32F5xxxx_System_Private_Variables + * @{ + */ +__IO uint32_t SystemCoreClock = __CK_AHB; /*!< SystemCoreClock = CK_AHB */ +/** + * @} + */ + +/** @addtogroup HT32F5xxxx_System_Private_Functions + * @{ + */ + +/** + * @brief Setup the microcontroller system. + * Initializes the system clocks and the embedded Flash. + * @note This function should be used after reset. + * @retval None + */ +void SystemInit(void) +{ +#if (WDT_ENABLE == 1) + HT_CKCU->APBCCR1 |= (0x1 << 4); + HT_WDT->PR = 0x35CA; + HT_WDT->MR0 = 0; + HT_WDT->MR1 = ((HT_WDT->MR1 & 0xFFF) | (WDT_PRESCALER << 12)); + HT_WDT->MR0 = WDT_RELOAD | (WDT_RESET_ENABLE << 13) | (WDT_SLEEP_HALT << 14) | (0x1 << 16); + HT_WDT->CR = 0x5FA00001; +#else + #if (DEINIT_ENABLE == 1) + HT_RSTCU->APBPRST1 = (1 << 4); + #endif +#endif + + SetBit_BB((u32)(&HT_CKCU->APBCCR1), 6); /* enable VDD power domain register clock */ + + #if (DEINIT_ENABLE == 1) + /* De-init the setting */ + HT_CKCU->AHBCCR &= ~(0x1 << 11); /* disable IP who may use PLL as source */ + SetBit_BB((u32)(&HT_CKCU->GCCR), 11); /* enable HSI */ + while (!GetBit_BB((u32)(&HT_CKCU->GCSR), 3)); /* wait for HSI ready */ + HT_CKCU->GCCR = ((HT_CKCU->GCCR & ~7UL) | 3UL); /* select CK_SYS source */ + while ((HT_CKCU->CKST & 7UL) != 3UL); /* wait for clock switch complete */ + HT_FLASH->CFCR = (((HT_FLASH->CFCR) & ~7UL) | 1UL); /* set Wait State as 0 WS */ + HT_CKCU->AHBCFGR = 0; /* set CK_AHB prescaler */ + ResetBit_BB((u32)(&HT_CKCU->GCCR), 9); /* disable PLL */ + SetBit_BB((u32)(&HT_CKCU->GCFGR), 8); /* select PLL source as HSI */ + #endif + + /* HSE initiation */ +#if (HSE_ENABLE == 1) + SetBit_BB((u32)(&HT_CKCU->GCCR), 10); /* enable HSE */ + while (!GetBit_BB((u32)(&HT_CKCU->GCSR), 2)){}; /* wait for HSE ready */ +#endif + + /* LSE initiation */ +#if (LSE_ENABLE == 1) + do { + SetBit_BB((u32)(&HT_RTC->CR), 3); /* enable LSE */ + } while (!GetBit_BB((u32)(&HT_RTC->CR), 3)); + while (!GetBit_BB((u32)(&HT_CKCU->GCSR), 4)); /* wait for LSE ready */ +#endif + + ResetBit_BB((u32)(&HT_CKCU->APBCCR1), 6); /* disable VDD power domain register clock */ + + /* LSI initiation */ +#if (HCLK_SRC == 7) + while (!GetBit_BB((u32)(&HT_CKCU->GCSR), 5)){}; /* wait for LSI ready */ +#endif + + /* PLL initiation */ +#if (PLL_ENABLE == 1) + HT_CKCU->PLLCFGR = ((PLL_NF2_DIV & 0x0F) << 23) | (PLL_NO2_DIV << 21); /* set PLL divider */ + + #if (PLL_CLK_SRC_DIV == 1) + SetBit_BB((u32)(&HT_CKCU->PLLCFGR), 28); /* set PLL clock source divider */ + #else + ResetBit_BB((u32)(&HT_CKCU->PLLCFGR), 28); /* reset PLL clock source divider */ + #endif + + #if (PLL_CLK_SRC == 0) + ResetBit_BB((u32)(&HT_CKCU->GCFGR), 8); /* select PLL source as HSE */ + #else + SetBit_BB((u32)(&HT_CKCU->GCFGR), 8); /* select PLL source as HSI */ + #endif + + SetBit_BB((u32)(&HT_CKCU->GCCR), 9); /* enable PLL */ + while (!GetBit_BB((u32)(&HT_CKCU->GCSR), 1)){}; /* wait for PLL ready */ +#endif + + /* CK_AHB initiation */ +#if (WAIT_STATE == 9) + #if (__CK_AHB > WS1_CLK) + HT_FLASH->CFCR = (((HT_FLASH->CFCR) & ~7UL) | 3UL); /* auto-select wait state */ + #elif (__CK_AHB > WS0_CLK) + HT_FLASH->CFCR = (((HT_FLASH->CFCR) & ~7UL) | 2UL); /* auto-select wait state */ + #endif +#else + HT_FLASH->CFCR = (((HT_FLASH->CFCR) & ~7UL) | (WAIT_STATE + 1)); /* manual wait state */ +#endif + + HT_CKCU->AHBCFGR = HCLK_DIV; /* set CK_AHB prescaler */ + HT_CKCU->GCCR = ((HT_CKCU->GCCR & ~7UL) | HCLK_SRC); /* select CK_SYS source */ + while ((HT_CKCU->CKST & 7UL) != HCLK_SRC); /* wait for clock switch complete */ + + /* Pre-fetch buffer configuration */ +#if (PRE_FETCH_ENABLE == 0) + ResetBit_BB((u32)(&HT_FLASH->CFCR), 4); /* 0: pre-fetch disable, 1: pre-fetch enable */ +#else + SetBit_BB((u32)(&HT_FLASH->CFCR), 4); /* 0: pre-fetch disable, 1: pre-fetch enable */ +#endif + + /* HSE power down */ +#if ((HSE_ENABLE == 0) && (HCLK_SRC != 2) && ((PLL_ENABLE == 0) || (PLL_CLK_SRC == 1))) + ResetBit_BB((u32)(&HT_CKCU->GCCR), 10); +#endif + + /* HSI power down */ +#if ((HSI_ENABLE == 0) && (HCLK_SRC != 3) && ((PLL_ENABLE == 0) || (PLL_CLK_SRC == 0))) + ResetBit_BB((u32)(&HT_CKCU->GCCR), 11); +#endif +} + +/** + * @brief Update SystemCoreClock + * @retval None + */ +void SystemCoreClockUpdate(void) +{ + u32 SystemCoreClockDiv = HT_CKCU->AHBCFGR & 7UL; + u32 PllSourceClockDiv = (HT_CKCU->PLLCFGR >> 28) & 1UL; + u32 PllFeedbackClockDiv = (((HT_CKCU->PLLCFGR >> 23) & 15UL) == 0) ? (16) : ((HT_CKCU->PLLCFGR >> 23) & 15UL); + u32 PllOutputClockDiv = (HT_CKCU->PLLCFGR >> 21) & 3UL; + u32 SystemCoreClockSrc = HT_CKCU->CKST & 7UL; + + /* Get system core clock according to global clock control & configuration registers */ + if (SystemCoreClockSrc == 1) + { + if (GetBit_BB((u32)(&HT_CKCU->PLLCR), 31)) + { + PllFeedbackClockDiv = 1; + PllOutputClockDiv = 0; + } + + if (GetBit_BB((u32)(&HT_CKCU->GCFGR), 8)) + { + SystemCoreClock = (((HSI_VALUE >> PllSourceClockDiv) * PllFeedbackClockDiv) >> PllOutputClockDiv) >> SystemCoreClockDiv; + } + else + { + SystemCoreClock = (((HSE_VALUE >> PllSourceClockDiv) * PllFeedbackClockDiv) >> PllOutputClockDiv) >> SystemCoreClockDiv; + } + } + else if (SystemCoreClockSrc == 2) + { + SystemCoreClock = HSE_VALUE >> SystemCoreClockDiv; + } + else if (SystemCoreClockSrc == 3) + { + SystemCoreClock = HSI_VALUE >> SystemCoreClockDiv; + } + else if (SystemCoreClockSrc == 6) + { + SystemCoreClock = LSE_VALUE >> SystemCoreClockDiv; + } + else if (SystemCoreClockSrc == 7) + { + SystemCoreClock = LSI_VALUE >> SystemCoreClockDiv; + } +} + +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ + +/******************* (C) COPYRIGHT Holtek Semiconductor Inc. *****END OF FILE*** */ diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/system_ht32f5xxxx_15.c b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/system_ht32f5xxxx_15.c new file mode 100644 index 0000000000..ad84d9825c --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/system_ht32f5xxxx_15.c @@ -0,0 +1,487 @@ +/**************************************************************************//** + * @file library/Device/Holtek/HT32F5xxxx/Source/system_ht32f5xxxx_15.c + * @brief CMSIS Cortex-M0+ Device Peripheral Access Layer Source File + * for the Holtek HT32F5xxxx Device Series + * @version $Rev:: 6777 $ + * @date $Date:: 2023-03-06 #$ + * + * @note + * Copyright (C) Holtek Semiconductor Inc. All rights reserved. + * + * @par + * ARM Limited (ARM) supplies this software for Cortex-M processor-based + * microcontrollers. This file can be freely distributed within development + * tools that are supporting such ARM based processors. + * + * @par + * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR + * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + ******************************************************************************/ + +// Supported Device +// ======================================== +// HT32F53242, HT32F53252 +// HT32F53231, HT32F53241 + +//#define USE_HT32F53242_52 +//#define USE_HT32F53231_41 + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup HT32F5xxxx_system HT32F5xxxx System + * @{ + */ + + +#include "ht32f5xxxx_01.h" + +/** @addtogroup HT32F5xxxx_System_Private_Defines + * @{ + */ +/* +//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ +*/ + +/*--------------------- Clock Configuration ---------------------------------- +// +// Enable High Speed External Crystal Oscillator (HSE) +// Default HSE = DISABLE +// +// Enable Low Speed External Crystal Oscillator (LSE) +// Default LSE = DISABLE +// +// Enable PLL +// Default PLL = DISABLE +// PLL Out = (((HSE or HSI) / SRC_DIV) x NF2 ) / NO2 +// PLL Clock Source +// <0=> CK_HSE +// <1=> CK_HSI +// Default PLL clock source = CK_HSI +// PLL source clock must be in the range of 4 MHz to 16 MHz +// PLL Clock Source Divider (SRC_DIV) +// <0=> 1 +// <1=> 2 +// PLL input clock = PLL Clock Source / (SRC_DIV) +// PLL Feedback Clock Divider (NF2): 1 ~ 16 +// <1-16:1> +// PLL feedback clock = PLL input clock x NF2 +// PLL feedback clock must be in the range of 24 MHz to 60 MHz +// PLL Output Clock Divider (NO2) +// <0=> 1 +// <1=> 2 +// <2=> 4 +// <3=> 8 +// PLL output clock = PLL feedback clock / NO2 +// PLL output clock must be in the range of 4 MHz to 60 MHz +// +// +// SystemCoreClock Configuration (CK_AHB) +// SystemCoreClock Source +// <1=> CK_PLL +// <2=> CK_HSE +// <3=> CK_HSI +// <6=> CK_LSE +// <7=> CK_LSI +// Default SystemCoreClock source = CK_HSI +// SystemCoreClock Source Divider +// <0=> 1 +// <1=> 2 +// <2=> 4 +// <3=> 8 +// <4=> 16 +// <5=> 32 +// Default SystemCoreClock source divider = 1 +// +// +// FLASH Configuration +// Wait state +// <0=> 0 WS +// <1=> 1 WS +// <2=> 2 WS +// <9=> AUTO +// 0 WS: 1 kHz <= CK_AHB <= 20 MHz +// 1 WS: 20 MHz < CK_AHB <= 40 MHz +// 2 WS: 40 MHz < CK_AHB <= 60 MHz +// Pre-fetch Buffer Enable +// Default pre-fetch buffer = ENABLE +// +*/ + +/* !!! NOTICE !!! + HSI must keep turn on when doing the Flash operation (Erase/Program). +*/ + +/* !!! NOTICE !!! + * How to adjust the value of High Speed External oscillator (HSE)? + The default value of HSE is define by "HSE_VALUE" in "ht32fxxxxx_nn.h". + If your board uses a different HSE speed, please add a new compiler preprocessor + C define, "HSE_VALUE=n000000" ("n" represents n MHz) in the toolchain/IDE, + or edit the "HSE_VALUE" in the "ht32f5xxxx_conf.h" file. + Take Keil MDK-ARM for instance, to set HSE as 16 MHz: + "Option of Taret -> C/C++ > Preprocessor Symbols" + Define: USE_HT32_DRIVER, USE_HT32Fxxxxx_SK, USE_HT32Fxxxxx_xx, USE_MEM_HT32Fxxxxx, HSE_VALUE=16000000 + ^^ Add "HSE_VALUE" + define as above. +*/ +#define HSI_ENABLE (1) /*!< 0: DISABLE, 1: ENABLE */ +#define HSE_ENABLE (1) /*!< 0: DISABLE, 1: ENABLE */ +#define LSI_ENABLE (1) /*!< 0: DISABLE, 1: ENABLE */ +#define LSE_ENABLE (0) /*!< 0: DISABLE, 1: ENABLE */ +#define PLL_ENABLE (1) /*!< 0: DISABLE, 1: ENABLE */ +#define PLL_CLK_SRC (0) /*!< 0: HSE, 1: HSI */ +#define PLL_CLK_SRC_DIV (1) /*!< 0: DIV1, 1: DIV2 */ +#define PLL_NF2_DIV (15) /*!< 1~16: DIV1~DIV16 */ +#define PLL_NO2_DIV (0) /*!< 0: DIV1, 1: DIV2, 2: DIV4, 3: DIV8 */ +#define HCLK_SRC (1) /*!< 0: PLL, 1: PLL, 2: HSE, 3: HSI 6: LSE, 7: LSI */ +#define HCLK_DIV (0) /*!< 0: DIV1, 1: DIV2, 2: DIV4, 3: DIV8, 4: DIV16, 5: DIV32 */ +#define WAIT_STATE (9) /*!< 0: WS = 0, 1: WS = 1, 2: WS = 2, 9: AUTO */ +#define PRE_FETCH_ENABLE (1) /*!< 0: DISABLE, 1: ENABLE */ +#define DEINIT_ENABLE (1) /* Set 0 for reduce code size */ + +/*----------------------------------------------------------------------------------------------------------*/ +/* PLL Out = (((HSE or HSI) / (PLL_CLK_SRC_DIV + 1)) x PLL_NF2) / PLL_NO2 */ +/*----------------------------------------------------------------------------------------------------------*/ + + +/*--------------------- WDT Configuration ---------------------------------- +// +// Enable WDT Configuration +// WDT Prescaler Selection +// <0=> CK_WDT / 1 +// <1=> CK_WDT / 2 +// <2=> CK_WDT / 4 +// <3=> CK_WDT / 8 +// <4=> CK_WDT / 16 +// <5=> CK_WDT / 32 +// <6=> CK_WDT / 64 +// <7=> CK_WDT / 128 +// WDT Reload Value <1-4095:1> +// Enable WDT Reset function +// WDT Sleep Halt mode +// <0=> No halt +// <1=> Halt in DeepSleep1 +// <2=> Halt in Sleep & DeepSleep1 +// +*/ +#define WDT_ENABLE (0) /*!< 0: DISABLE, 1: ENABLE */ +#define WDT_PRESCALER (5) /*!< 0: 1/1, 1: 1/2, 2: 1/4, 3: 1/8, 4: 1/16, 5: 1/32, 6: 1/64, 7: 1/128 */ +#define WDT_RELOAD (2000) /*!< 0 ~ 4095, 12 bit */ +#define WDT_RESET_ENABLE (1) /*!< 0: No Reset, 1: Reset when WDT over flow */ +#define WDT_SLEEP_HALT (2) /*!< 0: No halt, 1: Halt in DeepSleep1, 2: Halt in Sleep & DeepSleep1 */ + +/** + * @brief Check HSI frequency + */ +#if (HSI_VALUE != 8000000UL) + #error "CK_HSI clock issue: must be 8 MHz!" +#endif + +/** + * @brief Check HSE frequency + */ +#if ((HSE_VALUE < 4000000UL) || (HSE_VALUE > 16000000UL)) + #error "CK_HSE clock issue: must be in the range of 4 MHz to 16 MHz!" +#endif + +/** + * @brief Check LSI frequency + */ +#if (LSI_VALUE != 32000UL) + #error "CK_LSI clock issue: must be 32 kHz!" +#endif + +/** + * @brief Check LSE frequency + */ +#if (LSE_VALUE != 32768UL) + #error "CK_LSE clock issue: must be 32.768 kHz!" +#endif + +/** + * @brief CK_PLL definition + */ +#if (PLL_ENABLE == 1) + /* Get CK_VCO frequency */ + #if (PLL_CLK_SRC == 1) + #if (HSI_ENABLE == 0) + #error "CK_PLL clock source issue: HSI has not been enabled" + #else + #define __CK_VCO ((HSI_VALUE >> PLL_CLK_SRC_DIV) * PLL_NF2_DIV) /*!< Select HSI as PLL source */ + #endif + #else + #if (HSE_ENABLE == 0) + #error "CK_PLL clock source issue: HSE has not been enabled!" + #else + #define __CK_VCO ((HSE_VALUE >> PLL_CLK_SRC_DIV) * PLL_NF2_DIV) /*!< Select HSE as PLL source */ + #endif + #endif + + #define VCO_MIN 24000000UL + #define VCO_MAX 60000000UL + #define PLL_MIN 4000000UL + #define PLL_MAX 60000000UL + + /* Check CK_VCO frequency */ + #if ((__CK_VCO < VCO_MIN) || (__CK_VCO > VCO_MAX)) + #error "CK_VCO clock issue: must be in the range!" + #endif + + #define __CK_PLL (__CK_VCO >> PLL_NO2_DIV) /*!< Get CK_PLL frequency */ + + /* Check CK_PLL frequency */ + #if ((__CK_PLL < PLL_MIN) || (__CK_PLL > PLL_MAX)) + #error "CK_PLL clock issue: must be in the range!" + #endif +#endif + +/** + * @brief CK_SYS definition + */ +#if (HCLK_SRC == 1) + #if (PLL_ENABLE == 1) + #define __CK_SYS __CK_PLL /*!< Select PLL as CK_SYS source */ + #else + #error "CK_SYS clock source issue: PLL is not enable!" + #endif +#elif (HCLK_SRC == 2) + #if (HSE_ENABLE == 1) + #define __CK_SYS HSE_VALUE /*!< Select HSE as CK_SYS source */ + #else + #error "CK_SYS clock source issue: HSE is not enable!" + #endif +#elif (HCLK_SRC == 3) + #if (HSI_ENABLE == 1) + #define __CK_SYS HSI_VALUE /*!< Select HSI as CK_SYS source */ + #else + #error "CK_SYS clock source issue: HSI is not enable!" + #endif +#elif (HCLK_SRC == 6) + #if (LSE_ENABLE == 1) + #define __CK_SYS LSE_VALUE /*!< Select LSE as CK_SYS source */ + #else + #error "CK_SYS clock source issue: LSE is not enable!" + #endif +#elif (HCLK_SRC == 7) + #if (LSI_ENABLE == 1) + #define __CK_SYS LSI_VALUE /*!< Select LSI as CK_SYS source */ + #else + #error "CK_SYS clock source issue: LSI is not enable!" + #endif +#else + #error "CK_SYS clock source issue: No clock source is selected!" +#endif + +/** + * @brief CK_AHB definition + */ +#define __CK_AHB (__CK_SYS >> HCLK_DIV) /*!< Get CK_AHB frequency */ + +#define CKAHB_MIN 1000UL +#define CKAHB_MAX 60000000UL +#define WS0_CLK 20000000UL +#define WS1_CLK 40000000UL + +/* Check CK_AHB frequency */ +#if ((__CK_AHB < CKAHB_MIN) || (__CK_AHB > CKAHB_MAX)) + #error "CK_AHB clock issue: must be in the range!" +#endif + +/* Check FLASH wait-state setting */ +#if ((__CK_AHB > WS1_CLK) && (WAIT_STATE < 2) || \ + (__CK_AHB > WS0_CLK) && (WAIT_STATE < 1)) + #error "FLASH wait state configuration issue!" +#endif +/** + * @} + */ + +/** @addtogroup HT32F5xxxx_System_Private_Variables + * @{ + */ +__IO uint32_t SystemCoreClock = __CK_AHB; /*!< SystemCoreClock = CK_AHB */ +/** + * @} + */ + +/** @addtogroup HT32F5xxxx_System_Private_Functions + * @{ + */ + +/** + * @brief Setup the microcontroller system. + * Initializes the system clocks and the embedded Flash. + * @note This function should be used after reset. + * @retval None + */ +void SystemInit(void) +{ +#if (WDT_ENABLE == 1) + HT_CKCU->APBCCR1 |= (0x1 << 4); + HT_WDT->PR = 0x35CA; + HT_WDT->MR0 = 0; + HT_WDT->MR1 = ((HT_WDT->MR1 & 0xFFF) | (WDT_PRESCALER << 12)); + HT_WDT->MR0 = WDT_RELOAD | (WDT_RESET_ENABLE << 13) | (WDT_SLEEP_HALT << 14) | (0x1 << 16); + HT_WDT->CR = 0x5FA00001; +#else + #if (DEINIT_ENABLE == 1) + HT_RSTCU->APBPRST1 = (1 << 4); + #endif +#endif + + SetBit_BB((u32)(&HT_CKCU->APBCCR1), 6); /* enable VDD power domain register clock */ + + #if (DEINIT_ENABLE == 1) + /* De-init the setting */ + HT_CKCU->AHBCCR &= ~(0x1 << 11); /* disable IP who may use PLL as source */ + SetBit_BB((u32)(&HT_CKCU->GCCR), 11); /* enable HSI */ + while (!GetBit_BB((u32)(&HT_CKCU->GCSR), 3)); /* wait for HSI ready */ + HT_CKCU->GCCR = ((HT_CKCU->GCCR & ~7UL) | 3UL); /* select CK_SYS source */ + while ((HT_CKCU->CKST & 7UL) != 3UL); /* wait for clock switch complete */ + HT_FLASH->CFCR = (((HT_FLASH->CFCR) & ~7UL) | 1UL); /* set Wait State as 0 WS */ + HT_CKCU->AHBCFGR = 0; /* set CK_AHB prescaler */ + ResetBit_BB((u32)(&HT_CKCU->GCCR), 9); /* disable PLL */ + SetBit_BB((u32)(&HT_CKCU->GCFGR), 8); /* select PLL source as HSI */ + #endif + + /* HSE initiation */ +#if (HSE_ENABLE == 1) + SetBit_BB((u32)(&HT_CKCU->GCCR), 10); /* enable HSE */ + while (!GetBit_BB((u32)(&HT_CKCU->GCSR), 2)){}; /* wait for HSE ready */ +#endif + + /* LSE initiation */ +#if (LSE_ENABLE == 1) + do { + SetBit_BB((u32)(&HT_RTC->CR), 3); /* enable LSE */ + } while (!GetBit_BB((u32)(&HT_RTC->CR), 3)); + while (!GetBit_BB((u32)(&HT_CKCU->GCSR), 4)); /* wait for LSE ready */ +#endif + + ResetBit_BB((u32)(&HT_CKCU->APBCCR1), 6); /* disable VDD power domain register clock */ + + /* LSI initiation */ +#if (HCLK_SRC == 7) + while (!GetBit_BB((u32)(&HT_CKCU->GCSR), 5)){}; /* wait for LSI ready */ +#endif + + /* PLL initiation */ +#if (PLL_ENABLE == 1) + HT_CKCU->PLLCFGR = ((PLL_NF2_DIV & 0x0F) << 23) | (PLL_NO2_DIV << 21); /* set PLL divider */ + + #if (PLL_CLK_SRC_DIV == 1) + SetBit_BB((u32)(&HT_CKCU->PLLCFGR), 28); /* set PLL clock source divider */ + #else + ResetBit_BB((u32)(&HT_CKCU->PLLCFGR), 28); /* reset PLL clock source divider */ + #endif + + #if (PLL_CLK_SRC == 0) + ResetBit_BB((u32)(&HT_CKCU->GCFGR), 8); /* select PLL source as HSE */ + #else + SetBit_BB((u32)(&HT_CKCU->GCFGR), 8); /* select PLL source as HSI */ + #endif + + SetBit_BB((u32)(&HT_CKCU->GCCR), 9); /* enable PLL */ + while (!GetBit_BB((u32)(&HT_CKCU->GCSR), 1)){}; /* wait for PLL ready */ +#endif + + /* CK_AHB initiation */ +#if (WAIT_STATE == 9) + #if (__CK_AHB > WS1_CLK) + HT_FLASH->CFCR = (((HT_FLASH->CFCR) & ~7UL) | 3UL); /* auto-select wait state */ + #elif (__CK_AHB > WS0_CLK) + HT_FLASH->CFCR = (((HT_FLASH->CFCR) & ~7UL) | 2UL); /* auto-select wait state */ + #endif +#else + HT_FLASH->CFCR = (((HT_FLASH->CFCR) & ~7UL) | (WAIT_STATE + 1)); /* manual wait state */ +#endif + + HT_CKCU->AHBCFGR = HCLK_DIV; /* set CK_AHB prescaler */ + HT_CKCU->GCCR = ((HT_CKCU->GCCR & ~7UL) | HCLK_SRC); /* select CK_SYS source */ + while ((HT_CKCU->CKST & 7UL) != HCLK_SRC); /* wait for clock switch complete */ + + /* Pre-fetch buffer configuration */ +#if (PRE_FETCH_ENABLE == 0) + ResetBit_BB((u32)(&HT_FLASH->CFCR), 4); /* 0: pre-fetch disable, 1: pre-fetch enable */ +#else + SetBit_BB((u32)(&HT_FLASH->CFCR), 4); /* 0: pre-fetch disable, 1: pre-fetch enable */ +#endif + + /* HSE power down */ +#if ((HSE_ENABLE == 0) && (HCLK_SRC != 2) && ((PLL_ENABLE == 0) || (PLL_CLK_SRC == 1))) + ResetBit_BB((u32)(&HT_CKCU->GCCR), 10); +#endif + + /* HSI power down */ +#if ((HSI_ENABLE == 0) && (HCLK_SRC != 3) && ((PLL_ENABLE == 0) || (PLL_CLK_SRC == 0))) + ResetBit_BB((u32)(&HT_CKCU->GCCR), 11); +#endif +} + +/** + * @brief Update SystemCoreClock + * @retval None + */ +void SystemCoreClockUpdate(void) +{ + u32 SystemCoreClockDiv = HT_CKCU->AHBCFGR & 7UL; + u32 PllSourceClockDiv = (HT_CKCU->PLLCFGR >> 28) & 1UL; + u32 PllFeedbackClockDiv = (((HT_CKCU->PLLCFGR >> 23) & 15UL) == 0) ? (16) : ((HT_CKCU->PLLCFGR >> 23) & 15UL); + u32 PllOutputClockDiv = (HT_CKCU->PLLCFGR >> 21) & 3UL; + u32 SystemCoreClockSrc = HT_CKCU->CKST & 7UL; + + /* Get system core clock according to global clock control & configuration registers */ + if (SystemCoreClockSrc == 1) + { + if (GetBit_BB((u32)(&HT_CKCU->PLLCR), 31)) + { + PllFeedbackClockDiv = 1; + PllOutputClockDiv = 0; + } + + if (GetBit_BB((u32)(&HT_CKCU->GCFGR), 8)) + { + SystemCoreClock = (((HSI_VALUE >> PllSourceClockDiv) * PllFeedbackClockDiv) >> PllOutputClockDiv) >> SystemCoreClockDiv; + } + else + { + SystemCoreClock = (((HSE_VALUE >> PllSourceClockDiv) * PllFeedbackClockDiv) >> PllOutputClockDiv) >> SystemCoreClockDiv; + } + } + else if (SystemCoreClockSrc == 2) + { + SystemCoreClock = HSE_VALUE >> SystemCoreClockDiv; + } + else if (SystemCoreClockSrc == 3) + { + SystemCoreClock = HSI_VALUE >> SystemCoreClockDiv; + } + else if (SystemCoreClockSrc == 6) + { + SystemCoreClock = LSE_VALUE >> SystemCoreClockDiv; + } + else if (SystemCoreClockSrc == 7) + { + SystemCoreClock = LSI_VALUE >> SystemCoreClockDiv; + } +} + +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ + +/******************* (C) COPYRIGHT Holtek Semiconductor Inc. *****END OF FILE*** */ diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/system_ht32f5xxxx_16.c b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/system_ht32f5xxxx_16.c new file mode 100644 index 0000000000..5eb90ab190 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/system_ht32f5xxxx_16.c @@ -0,0 +1,472 @@ +/**************************************************************************//** + * @file library/Device/Holtek/HT32F5xxxx/Source/system_ht32f5xxxx_16.c + * @brief CMSIS Cortex-M0+ Device Peripheral Access Layer Source File + * for the Holtek HT32F5xxxx Device Series + * @version $Rev:: 7090 $ + * @date $Date:: 2023-08-02 #$ + * + * @note + * Copyright (C) Holtek Semiconductor Inc. All rights reserved. + * + * @par + * ARM Limited (ARM) supplies this software for Cortex-M processor-based + * microcontrollers. This file can be freely distributed within development + * tools that are supporting such ARM based processors. + * + * @par + * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR + * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + ******************************************************************************/ + +// Supported Device +// ======================================== +// HT32F66242 +// HT32F66246 + +//#define USE_HT32F66246 + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup HT32F5xxxx_system HT32F5xxxx System + * @{ + */ + + +#include "ht32f5xxxx_01.h" + +/** @addtogroup HT32F5xxxx_System_Private_Defines + * @{ + */ +/* +//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ +*/ + +/*--------------------- Clock Configuration ---------------------------------- +// +// Enable High Speed External Crystal Oscillator (HSE) +// Default HSE = DISABLE +// +// Enable PLL +// Default PLL = DISABLE +// PLL Out = (((HSE or HSI) / SRC_DIV) x NF2 ) / NO2 +// PLL Clock Source +// <0=> CK_HSE +// <1=> CK_HSI +// Default PLL clock source = CK_HSI +// PLL source clock must be in the range of 4 MHz to 16 MHz +// PLL Clock Source Divider (SRC_DIV) +// <0=> 1 +// <1=> 2 +// PLL input clock = PLL Clock Source / (SRC_DIV) +// PLL Feedback Clock Divider (NF2): 1 ~ 32 +// <1-32:1> +// PLL feedback clock = PLL input clock x NF2 +// PLL feedback clock must be in the range of 64 MHz to 96 MHz +// PLL Output Clock Divider (NO2) +// <0=> 1 +// <1=> 2 +// <2=> 4 +// <3=> 8 +// PLL output clock = PLL feedback clock / NO2 +// PLL output clock must be in the range of 8 MHz to 96 MHz +// +// +// SystemCoreClock Configuration (CK_AHB) +// SystemCoreClock Source +// <1=> CK_PLL +// <2=> CK_HSE +// <3=> CK_HSI +// <7=> CK_LSI +// Default SystemCoreClock source = CK_HSI +// SystemCoreClock Source Divider +// <0=> 1 +// <1=> 2 +// <2=> 4 +// <3=> 8 +// <4=> 16 +// <5=> 32 +// Default SystemCoreClock source divider = 1 +// +// +// FLASH Configuration +// Wait state +// <0=> 0 WS +// <1=> 1 WS +// <2=> 2 WS +// <3=> 3 WS +// <9=> AUTO +// 0 WS: 1 KHz <= CK_AHB <= 20 MHz +// 1 WS: 20 MHz < CK_AHB <= 40 MHz +// 2 WS: 40 MHz < CK_AHB <= 60 MHz +// 3 WS: 60 MHz < CK_AHB <= 80 MHz +// Pre-fetch Buffer Enable +// Default pre-fetch buffer = ENABLE +// Branch cache Enable +// Default branch cache = ENABLE +// +*/ + +/* !!! NOTICE !!! + HSI must keep turn on when doing the Flash operation (Erase/Program). +*/ + +/* !!! NOTICE !!! + * How to adjust the value of High Speed External oscillator (HSE)? + The default value of HSE is define by "HSE_VALUE" in "ht32fxxxxx_nn.h". + If your board uses a different HSE speed, please add a new compiler preprocessor + C define, "HSE_VALUE=n000000" ("n" represents n MHz) in the toolchain/IDE, + or edit the "HSE_VALUE" in the "ht32f5xxxx_conf.h" file. + Take Keil MDK-ARM for instance, to set HSE as 16 MHz: + "Option of Taret -> C/C++ > Preprocessor Symbols" + Define: USE_HT32_DRIVER, USE_HT32Fxxxxx_SK, USE_HT32Fxxxxx_xx, USE_MEM_HT32Fxxxxx, HSE_VALUE=16000000 + ^^ Add "HSE_VALUE" + define as above. +*/ +#define HSI_ENABLE (1) /*!< 0: DISABLE, 1: ENABLE */ +#define HSE_ENABLE (1) /*!< 0: DISABLE, 1: ENABLE */ +#define LSI_ENABLE (1) /*!< 0: DISABLE, 1: ENABLE */ +#define PLL_ENABLE (1) /*!< 0: DISABLE, 1: ENABLE */ +#define PLL_CLK_SRC (0) /*!< 0: HSE, 1: HSI */ +#define PLL_CLK_SRC_DIV (1) /*!< 0: DIV1, 1: DIV2 */ +#define PLL_NF2_DIV (20) /*!< 1~32: DIV1~DIV32 */ +#define PLL_NO2_DIV (0) /*!< 0: DIV1, 1: DIV2, 2: DIV4, 3: DIV8 */ +#define HCLK_SRC (1) /*!< 0: PLL, 1: PLL, 2: HSE, 3: HSI 7: LSI */ +#define HCLK_DIV (0) /*!< 0: DIV1, 1: DIV2, 2: DIV4, 3: DIV8, 4: DIV16, 5: DIV32 */ +#define WAIT_STATE (9) /*!< 0: WS = 0, 1: WS = 1, 2: WS = 2, 3: WS = 3, 9: AUTO */ +#define PRE_FETCH_ENABLE (1) /*!< 0: DISABLE, 1: ENABLE */ +#define BCACHE_ENABLE (1) /*!< 0: DISABLE, 1: ENABLE */ +#define DEINIT_ENABLE (1) /* Set 0 for reduce code size */ + +/*----------------------------------------------------------------------------------------------------------*/ +/* PLL Out = (((HSE or HSI) / (PLL_CLK_SRC_DIV + 1)) x PLL_NF2) / PLL_NO2 */ +/*----------------------------------------------------------------------------------------------------------*/ + + +/*--------------------- WDT Configuration ---------------------------------- +// +// Enable WDT Configuration +// WDT Prescaler Selection +// <0=> CK_WDT / 1 +// <1=> CK_WDT / 2 +// <2=> CK_WDT / 4 +// <3=> CK_WDT / 8 +// <4=> CK_WDT / 16 +// <5=> CK_WDT / 32 +// <6=> CK_WDT / 64 +// <7=> CK_WDT / 128 +// WDT Reload Value <1-4095:1> +// Enable WDT Reset function +// WDT Sleep Halt mode +// <0=> No halt +// <1=> Halt in DeepSleep1 +// <2=> Halt in Sleep & DeepSleep1 +// +*/ +#define WDT_ENABLE (0) /*!< 0: DISABLE, 1: ENABLE */ +#define WDT_PRESCALER (5) /*!< 0: 1/1, 1: 1/2, 2: 1/4, 3: 1/8, 4: 1/16, 5: 1/32, 6: 1/64, 7: 1/128 */ +#define WDT_RELOAD (2000) /*!< 0 ~ 4095, 12 bit */ +#define WDT_RESET_ENABLE (1) /*!< 0: No Reset, 1: Reset when WDT over flow */ +#define WDT_SLEEP_HALT (2) /*!< 0: No halt, 1: Halt in DeepSleep1, 2: Halt in Sleep & DeepSleep1 */ + +/** + * @brief Check HSI frequency + */ +#if (HSI_VALUE != 8000000UL) + #error "CK_HSI clock issue: must be 8 MHz!" +#endif + +/** + * @brief Check HSE frequency + */ +#if ((HSE_VALUE < 4000000UL) || (HSE_VALUE > 16000000UL)) + #error "CK_HSE clock issue: must be in the range of 4 MHz to 16 MHz!" +#endif + +/** + * @brief Check LSI frequency + */ +#if (LSI_VALUE != 32000UL) + #error "CK_LSI clock issue: must be 32 kHz!" +#endif + +/** + * @brief CK_PLL definition + */ +#if (PLL_ENABLE == 1) + /* Get CK_VCO frequency */ + #if (PLL_CLK_SRC == 1) + #if (HSI_ENABLE == 0) + #error "CK_PLL clock source issue: HSI has not been enabled" + #else + #define __CK_VCO ((HSI_VALUE >> PLL_CLK_SRC_DIV) * PLL_NF2_DIV) /*!< Select HSI as PLL source */ + #endif + #else + #if (HSE_ENABLE == 0) + #error "CK_PLL clock source issue: HSE has not been enabled!" + #else + #define __CK_VCO ((HSE_VALUE >> PLL_CLK_SRC_DIV) * PLL_NF2_DIV) /*!< Select HSE as PLL source */ + #endif + #endif + + #define VCO_MIN 64000000UL + #define VCO_MAX 96000000UL + #define PLL_MIN 8000000UL + #define PLL_MAX 96000000UL + + /* Check CK_VCO frequency */ + #if ((__CK_VCO < VCO_MIN) || (__CK_VCO > VCO_MAX)) + #error "CK_VCO clock issue: must be in the range!" + #endif + + #define __CK_PLL (__CK_VCO >> PLL_NO2_DIV) /*!< Get CK_PLL frequency */ + + /* Check CK_PLL frequency */ + #if ((__CK_PLL < PLL_MIN) || (__CK_PLL > PLL_MAX)) + #error "CK_PLL clock issue: must be in the range!" + #endif +#endif + +/** + * @brief CK_SYS definition + */ +#if (HCLK_SRC == 1) + #if (PLL_ENABLE == 1) + #define __CK_SYS __CK_PLL /*!< Select PLL as CK_SYS source */ + #else + #error "CK_SYS clock source issue: PLL is not enable!" + #endif +#elif (HCLK_SRC == 2) + #if (HSE_ENABLE == 1) + #define __CK_SYS HSE_VALUE /*!< Select HSE as CK_SYS source */ + #else + #error "CK_SYS clock source issue: HSE is not enable!" + #endif +#elif (HCLK_SRC == 3) + #if (HSI_ENABLE == 1) + #define __CK_SYS HSI_VALUE /*!< Select HSI as CK_SYS source */ + #else + #error "CK_SYS clock source issue: HSI is not enable!" + #endif +#elif (HCLK_SRC == 7) + #if (LSI_ENABLE == 1) + #define __CK_SYS LSI_VALUE /*!< Select LSI as CK_SYS source */ + #else + #error "CK_SYS clock source issue: LSI is not enable!" + #endif +#else + #error "CK_SYS clock source issue: No clock source is selected!" +#endif + +/** + * @brief CK_AHB definition + */ +#define __CK_AHB (__CK_SYS >> HCLK_DIV) /*!< Get CK_AHB frequency */ + +#define CKAHB_MIN 1000UL +#define CKAHB_MAX 80000000UL +#define WS0_CLK 20000000UL +#define WS1_CLK 40000000UL +#define WS2_CLK 60000000UL + +/* Check CK_AHB frequency */ +#if ((__CK_AHB < CKAHB_MIN) || (__CK_AHB > CKAHB_MAX)) + #error "CK_AHB clock issue: must be in the range!" +#endif + +/* Check FLASH wait-state setting */ +#if ((__CK_AHB > WS2_CLK) && (WAIT_STATE < 3) || \ + (__CK_AHB > WS1_CLK) && (WAIT_STATE < 2) || \ + (__CK_AHB > WS0_CLK) && (WAIT_STATE < 1)) + #error "FLASH wait state configuration issue!" +#endif +/** + * @} + */ + +/** @addtogroup HT32F5xxxx_System_Private_Variables + * @{ + */ +__IO uint32_t SystemCoreClock = __CK_AHB; /*!< SystemCoreClock = CK_AHB */ +/** + * @} + */ + +/** @addtogroup HT32F5xxxx_System_Private_Functions + * @{ + */ + +/** + * @brief Setup the microcontroller system. + * Initializes the system clocks and the embedded Flash. + * @note This function should be used after reset. + * @retval None + */ +void SystemInit(void) +{ +#if (WDT_ENABLE == 1) + HT_CKCU->APBCCR1 |= (0x1 << 4); + HT_WDT->PR = 0x35CA; + HT_WDT->MR0 = 0; + HT_WDT->MR1 = ((HT_WDT->MR1 & 0xFFF) | (WDT_PRESCALER << 12)); + HT_WDT->MR0 = WDT_RELOAD | (WDT_RESET_ENABLE << 13) | (WDT_SLEEP_HALT << 14) | (0x1 << 16); + HT_WDT->CR = 0x5FA00001; +#else + #if (DEINIT_ENABLE == 1) + HT_RSTCU->APBPRST1 = (1 << 4); + #endif +#endif + + SetBit_BB((u32)(&HT_CKCU->APBCCR1), 6); /* enable Backup domain register clock */ + + #if (DEINIT_ENABLE == 1) + /* De-init the setting */ + HT_CKCU->AHBCCR &= ~(0x1 << 11); /* disable IP who may use PLL as source */ + SetBit_BB((u32)(&HT_CKCU->GCCR), 11); /* enable HSI */ + while (!GetBit_BB((u32)(&HT_CKCU->GCSR), 3)); /* wait for HSI ready */ + HT_CKCU->GCCR = ((HT_CKCU->GCCR & ~7UL) | 3UL); /* select CK_SYS source */ + while ((HT_CKCU->CKST & 7UL) != 3UL); /* wait for clock switch complete */ + HT_FLASH->CFCR = (((HT_FLASH->CFCR) & ~7UL) | 1UL); /* set Wait State as 0 WS */ + HT_CKCU->AHBCFGR = 0; /* set CK_AHB prescaler */ + ResetBit_BB((u32)(&HT_CKCU->GCCR), 9); /* disable PLL */ + SetBit_BB((u32)(&HT_CKCU->GCFGR), 8); /* select PLL source as HSI */ + #endif + + /* HSE initiation */ +#if (HSE_ENABLE == 1) + SetBit_BB((u32)(&HT_CKCU->GCCR), 10); /* enable HSE */ + while (!GetBit_BB((u32)(&HT_CKCU->GCSR), 2)){}; /* wait for HSE ready */ +#endif + + /* LSI initiation */ +#if (HCLK_SRC == 7) + while (!GetBit_BB((u32)(&HT_CKCU->GCSR), 5)){}; /* wait for LSI ready */ +#endif + + /* PLL initiation */ +#if (PLL_ENABLE == 1) + HT_CKCU->PLLCFGR = ((PLL_NF2_DIV & 0x1F) << 23) | (PLL_NO2_DIV << 21); /* set PLL divider */ + + #if (PLL_CLK_SRC_DIV == 1) + SetBit_BB((u32)(&HT_CKCU->PLLCFGR), 28); /* set PLL clock source divider */ + #else + ResetBit_BB((u32)(&HT_CKCU->PLLCFGR), 28); /* reset PLL clock source divider */ + #endif + + #if (PLL_CLK_SRC == 0) + ResetBit_BB((u32)(&HT_CKCU->GCFGR), 8); /* select PLL source as HSE */ + #else + SetBit_BB((u32)(&HT_CKCU->GCFGR), 8); /* select PLL source as HSI */ + #endif + + SetBit_BB((u32)(&HT_CKCU->GCCR), 9); /* enable PLL */ + while (!GetBit_BB((u32)(&HT_CKCU->GCSR), 1)){}; /* wait for PLL ready */ +#endif + + /* CK_AHB initiation */ +#if (WAIT_STATE == 9) + #if (__CK_AHB > WS2_CLK) + HT_FLASH->CFCR = (((HT_FLASH->CFCR) & ~7UL) | 4UL); /* auto-select wait state */ + #elif (__CK_AHB > WS1_CLK) + HT_FLASH->CFCR = (((HT_FLASH->CFCR) & ~7UL) | 3UL); /* auto-select wait state */ + #elif (__CK_AHB > WS0_CLK) + HT_FLASH->CFCR = (((HT_FLASH->CFCR) & ~7UL) | 2UL); /* auto-select wait state */ + #endif +#else + HT_FLASH->CFCR = (((HT_FLASH->CFCR) & ~7UL) | (WAIT_STATE + 1)); /* manual wait state */ +#endif + + HT_CKCU->AHBCFGR = HCLK_DIV; /* set CK_AHB prescaler */ + HT_CKCU->GCCR = ((HT_CKCU->GCCR & ~7UL) | HCLK_SRC); /* select CK_SYS source */ + while ((HT_CKCU->CKST & 7UL) != HCLK_SRC); /* wait for clock switch complete */ + + ResetBit_BB((u32)(&HT_CKCU->APBCCR1), 6); /* disable Backup domain register clock */ + + /* Pre-fetch buffer configuration */ +#if (PRE_FETCH_ENABLE == 0) + ResetBit_BB((u32)(&HT_FLASH->CFCR), 4); /* 0: pre-fetch disable, 1: pre-fetch enable */ +#else + SetBit_BB((u32)(&HT_FLASH->CFCR), 4); /* 0: pre-fetch disable, 1: pre-fetch enable */ +#endif + + /* Branch cache configuration */ +#if (BCACHE_ENABLE == 0) + ResetBit_BB((u32)(&HT_FLASH->CFCR), 12); /* 0: branch cache disable, 1: branch cache enable */ +#else + SetBit_BB((u32)(&HT_FLASH->CFCR), 12); /* 0: branch cache disable, 1: branch cache enable */ +#endif + + /* HSE power down */ +#if ((HSE_ENABLE == 0) && (HCLK_SRC != 2) && ((PLL_ENABLE == 0) || (PLL_CLK_SRC == 1))) + ResetBit_BB((u32)(&HT_CKCU->GCCR), 10); +#endif + + /* HSI power down */ +#if ((HSI_ENABLE == 0) && (HCLK_SRC != 3) && ((PLL_ENABLE == 0) || (PLL_CLK_SRC == 0))) + ResetBit_BB((u32)(&HT_CKCU->GCCR), 11); +#endif +} + +/** + * @brief Update SystemCoreClock + * @retval None + */ +void SystemCoreClockUpdate(void) +{ + u32 SystemCoreClockDiv = HT_CKCU->AHBCFGR & 7UL; + u32 PllSourceClockDiv = (HT_CKCU->PLLCFGR >> 28) & 1UL; + u32 PllFeedbackClockDiv = (((HT_CKCU->PLLCFGR >> 23) & 31UL) == 0) ? (32) : ((HT_CKCU->PLLCFGR >> 23) & 31UL); + u32 PllOutputClockDiv = (HT_CKCU->PLLCFGR >> 21) & 3UL; + u32 SystemCoreClockSrc = HT_CKCU->CKST & 7UL; + + /* Get system core clock according to global clock control & configuration registers */ + if (SystemCoreClockSrc == 1) + { + if (GetBit_BB((u32)(&HT_CKCU->PLLCR), 31)) + { + PllFeedbackClockDiv = 1; + PllOutputClockDiv = 0; + } + + if (GetBit_BB((u32)(&HT_CKCU->GCFGR), 8)) + { + SystemCoreClock = (((HSI_VALUE >> PllSourceClockDiv) * PllFeedbackClockDiv) >> PllOutputClockDiv) >> SystemCoreClockDiv; + } + else + { + SystemCoreClock = (((HSE_VALUE >> PllSourceClockDiv) * PllFeedbackClockDiv) >> PllOutputClockDiv) >> SystemCoreClockDiv; + } + } + else if (SystemCoreClockSrc == 2) + { + SystemCoreClock = HSE_VALUE >> SystemCoreClockDiv; + } + else if (SystemCoreClockSrc == 3) + { + SystemCoreClock = HSI_VALUE >> SystemCoreClockDiv; + } + else if (SystemCoreClockSrc == 7) + { + SystemCoreClock = LSI_VALUE >> SystemCoreClockDiv; + } +} + +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ + +/******************* (C) COPYRIGHT Holtek Semiconductor Inc. *****END OF FILE*** */ diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/system_ht32f5xxxx_17.c b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/system_ht32f5xxxx_17.c new file mode 100644 index 0000000000..9eb200c400 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/system_ht32f5xxxx_17.c @@ -0,0 +1,488 @@ +/**************************************************************************//** + * @file library/Device/Holtek/HT32F5xxxx/Source/system_ht32f5xxxx_17.c + * @brief CMSIS Cortex-M0+ Device Peripheral Access Layer Source File + * for the Holtek HT32F5xxxx Device Series + * @version $Rev:: 7027 $ + * @date $Date:: 2023-07-18 #$ + * + * @note + * Copyright (C) Holtek Semiconductor Inc. All rights reserved. + * + * @par + * ARM Limited (ARM) supplies this software for Cortex-M processor-based + * microcontrollers. This file can be freely distributed within development + * tools that are supporting such ARM based processors. + * + * @par + * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR + * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + ******************************************************************************/ + +// Supported Device +// ======================================== +// HT32F52234, HT32F52244 + +//#define USE_HT32F52234_44 + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup HT32F5xxxx_system HT32F5xxxx System + * @{ + */ + + +#include "ht32f5xxxx_01.h" + +/** @addtogroup HT32F5xxxx_System_Private_Defines + * @{ + */ +/* +//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ +*/ + +/*--------------------- Clock Configuration ---------------------------------- +// +// Enable High Speed Internal RC Oscillator (HSI) +// Default HSI = ENABLE +// +// Enable High Speed External Crystal Oscillator (HSE) +// Default HSE = DISABLE +// +// Enable Low Speed External Crystal Oscillator (LSE) +// Default LSE = DISABLE +// +// Enable PLL +// Default PLL = DISABLE +// PLL Out = (((HSE or HSI) / SRC_DIV) x NF2 ) / NO2 +// PLL Clock Source +// <0=> CK_HSE +// <1=> CK_HSI +// Default PLL clock source = CK_HSI +// PLL source clock must be in the range of 4 MHz to 16 MHz +// PLL Clock Source Divider (SRC_DIV) +// <0=> 1 +// <1=> 2 +// PLL input clock = PLL Clock Source / (SRC_DIV) +// PLL Feedback Clock Divider (NF2): 1 ~ 16 +// <1-16:1> +// PLL feedback clock = PLL input clock x NF2 +// PLL feedback clock must be in the range of 24 MHz to 60 MHz +// PLL Output Clock Divider (NO2) +// <0=> 1 +// <1=> 2 +// <2=> 4 +// <3=> 8 +// PLL output clock = PLL feedback clock / NO2 +// PLL output clock must be in the range of 4 MHz to 60 MHz +// +// +// SystemCoreClock Configuration (CK_AHB) +// SystemCoreClock Source +// <1=> CK_PLL +// <2=> CK_HSE +// <3=> CK_HSI +// <6=> CK_LSE +// <7=> CK_LSI +// Default SystemCoreClock source = CK_HSI +// SystemCoreClock Source Divider +// <0=> 1 +// <1=> 2 +// <2=> 4 +// <3=> 8 +// <4=> 16 +// <5=> 32 +// Default SystemCoreClock source divider = 1 +// +// +// FLASH Configuration +// Wait state +// <0=> 0 WS +// <1=> 1 WS +// <2=> 2 WS +// <9=> AUTO +// 0 WS: 1 kHz <= CK_AHB <= 20 MHz +// 1 WS: 20 MHz < CK_AHB <= 40 MHz +// 2 WS: 40 MHz < CK_AHB <= 60 MHz +// Pre-fetch Buffer Enable +// Default pre-fetch buffer = ENABLE +// +*/ + +/* !!! NOTICE !!! + HSI must keep turn on when doing the Flash operation (Erase/Program). +*/ + +/* !!! NOTICE !!! + * How to adjust the value of High Speed External oscillator (HSE)? + The default value of HSE is define by "HSE_VALUE" in "ht32fxxxxx_nn.h". + If your board uses a different HSE speed, please add a new compiler preprocessor + C define, "HSE_VALUE=n000000" ("n" represents n MHz) in the toolchain/IDE, + or edit the "HSE_VALUE" in the "ht32f5xxxx_conf.h" file. + Take Keil MDK-ARM for instance, to set HSE as 16 MHz: + "Option of Taret -> C/C++ > Preprocessor Symbols" + Define: USE_HT32_DRIVER, USE_HT32Fxxxxx_SK, USE_HT32Fxxxxx_xx, USE_MEM_HT32Fxxxxx, HSE_VALUE=16000000 + ^^ Add "HSE_VALUE" + define as above. +*/ +#define HSI_ENABLE (1) /*!< 0: DISABLE, 1: ENABLE */ +#define HSE_ENABLE (1) /*!< 0: DISABLE, 1: ENABLE */ +#define LSI_ENABLE (1) /*!< 0: DISABLE, 1: ENABLE */ +#define LSE_ENABLE (0) /*!< 0: DISABLE, 1: ENABLE */ +#define PLL_ENABLE (1) /*!< 0: DISABLE, 1: ENABLE */ +#define PLL_CLK_SRC (0) /*!< 0: HSE, 1: HSI */ +#define PLL_CLK_SRC_DIV (1) /*!< 0: DIV1, 1: DIV2 */ +#define PLL_NF2_DIV (15) /*!< 1~16: DIV1~DIV16 */ +#define PLL_NO2_DIV (0) /*!< 0: DIV1, 1: DIV2, 2: DIV4, 3: DIV8 */ +#define HCLK_SRC (1) /*!< 0: PLL, 1: PLL, 2: HSE, 3: HSI 6: LSE, 7: LSI */ +#define HCLK_DIV (0) /*!< 0: DIV1, 1: DIV2, 2: DIV4, 3: DIV8, 4: DIV16, 5: DIV32 */ +#define WAIT_STATE (9) /*!< 0: WS = 0, 1: WS = 1, 2: WS = 2, 9: AUTO */ +#define PRE_FETCH_ENABLE (1) /*!< 0: DISABLE, 1: ENABLE */ +#define DEINIT_ENABLE (1) /* Set 0 for reduce code size */ + +/*----------------------------------------------------------------------------------------------------------*/ +/* PLL Out = (((HSE or HSI) / (PLL_CLK_SRC_DIV + 1)) x PLL_NF2) / PLL_NO2 */ +/*----------------------------------------------------------------------------------------------------------*/ + + +/*--------------------- WDT Configuration ---------------------------------- +// +// Enable WDT Configuration +// WDT Prescaler Selection +// <0=> CK_WDT / 1 +// <1=> CK_WDT / 2 +// <2=> CK_WDT / 4 +// <3=> CK_WDT / 8 +// <4=> CK_WDT / 16 +// <5=> CK_WDT / 32 +// <6=> CK_WDT / 64 +// <7=> CK_WDT / 128 +// WDT Reload Value <1-4095:1> +// Enable WDT Reset function +// WDT Sleep Halt mode +// <0=> No halt +// <1=> Halt in DeepSleep1 +// <2=> Halt in Sleep & DeepSleep1 +// +*/ +#define WDT_ENABLE (0) /*!< 0: DISABLE, 1: ENABLE */ +#define WDT_PRESCALER (5) /*!< 0: 1/1, 1: 1/2, 2: 1/4, 3: 1/8, 4: 1/16, 5: 1/32, 6: 1/64, 7: 1/128 */ +#define WDT_RELOAD (2000) /*!< 0 ~ 4095, 12 bit */ +#define WDT_RESET_ENABLE (1) /*!< 0: No Reset, 1: Reset when WDT over flow */ +#define WDT_SLEEP_HALT (2) /*!< 0: No halt, 1: Halt in DeepSleep1, 2: Halt in Sleep & DeepSleep1 */ + +/** + * @brief Check HSI frequency + */ +#if (HSI_VALUE != 8000000UL) + #error "CK_HSI clock issue: must be 8 MHz!" +#endif + +/** + * @brief Check HSE frequency + */ +#if ((HSE_VALUE < 4000000UL) || (HSE_VALUE > 16000000UL)) + #error "CK_HSE clock issue: must be in the range of 4 MHz to 16 MHz!" +#endif + +/** + * @brief Check LSI frequency + */ +#if (LSI_VALUE != 32000UL) + #error "CK_LSI clock issue: must be 32 kHz!" +#endif + +/** + * @brief Check LSE frequency + */ +#if (LSE_VALUE != 32768UL) + #error "CK_LSE clock issue: must be 32.768 kHz!" +#endif + +/** + * @brief CK_PLL definition + */ +#if (PLL_ENABLE == 1) + /* Get CK_VCO frequency */ + #if (PLL_CLK_SRC == 1) + #if (HSI_ENABLE == 0) + #error "CK_PLL clock source issue: HSI has not been enabled" + #else + #define __CK_VCO ((HSI_VALUE >> PLL_CLK_SRC_DIV) * PLL_NF2_DIV) /*!< Select HSI as PLL source */ + #endif + #else + #if (HSE_ENABLE == 0) + #error "CK_PLL clock source issue: HSE has not been enabled!" + #else + #define __CK_VCO ((HSE_VALUE >> PLL_CLK_SRC_DIV) * PLL_NF2_DIV) /*!< Select HSE as PLL source */ + #endif + #endif + + #define VCO_MIN 24000000UL + #define VCO_MAX 60000000UL + #define PLL_MIN 4000000UL + #define PLL_MAX 60000000UL + + /* Check CK_VCO frequency */ + #if ((__CK_VCO < VCO_MIN) || (__CK_VCO > VCO_MAX)) + #error "CK_VCO clock issue: must be in the range!" + #endif + + #define __CK_PLL (__CK_VCO >> PLL_NO2_DIV) /*!< Get CK_PLL frequency */ + + /* Check CK_PLL frequency */ + #if ((__CK_PLL < PLL_MIN) || (__CK_PLL > PLL_MAX)) + #error "CK_PLL clock issue: must be in the range!" + #endif +#endif + +/** + * @brief CK_SYS definition + */ +#if (HCLK_SRC == 1) + #if (PLL_ENABLE == 1) + #define __CK_SYS __CK_PLL /*!< Select PLL as CK_SYS source */ + #else + #error "CK_SYS clock source issue: PLL is not enable!" + #endif +#elif (HCLK_SRC == 2) + #if (HSE_ENABLE == 1) + #define __CK_SYS HSE_VALUE /*!< Select HSE as CK_SYS source */ + #else + #error "CK_SYS clock source issue: HSE is not enable!" + #endif +#elif (HCLK_SRC == 3) + #if (HSI_ENABLE == 1) + #define __CK_SYS HSI_VALUE /*!< Select HSI as CK_SYS source */ + #else + #error "CK_SYS clock source issue: HSI is not enable!" + #endif +#elif (HCLK_SRC == 6) + #if (LSE_ENABLE == 1) + #define __CK_SYS LSE_VALUE /*!< Select LSE as CK_SYS source */ + #else + #error "CK_SYS clock source issue: LSE is not enable!" + #endif +#elif (HCLK_SRC == 7) + #if (LSI_ENABLE == 1) + #define __CK_SYS LSI_VALUE /*!< Select LSI as CK_SYS source */ + #else + #error "CK_SYS clock source issue: LSI is not enable!" + #endif +#else + #error "CK_SYS clock source issue: No clock source is selected!" +#endif + +/** + * @brief CK_AHB definition + */ +#define __CK_AHB (__CK_SYS >> HCLK_DIV) /*!< Get CK_AHB frequency */ + +#define CKAHB_MIN 1000UL +#define CKAHB_MAX 60000000UL +#define WS0_CLK 20000000UL +#define WS1_CLK 40000000UL + +/* Check CK_AHB frequency */ +#if ((__CK_AHB < CKAHB_MIN) || (__CK_AHB > CKAHB_MAX)) + #error "CK_AHB clock issue: must be in the range!" +#endif + +/* Check FLASH wait-state setting */ +#if ((__CK_AHB > WS1_CLK) && (WAIT_STATE < 2) || \ + (__CK_AHB > WS0_CLK) && (WAIT_STATE < 1)) + #error "FLASH wait state configuration issue!" +#endif +/** + * @} + */ + +/** @addtogroup HT32F5xxxx_System_Private_Variables + * @{ + */ +__IO uint32_t SystemCoreClock = __CK_AHB; /*!< SystemCoreClock = CK_AHB */ +/** + * @} + */ + +/** @addtogroup HT32F5xxxx_System_Private_Functions + * @{ + */ + +/** + * @brief Setup the microcontroller system. + * Initializes the system clocks and the embedded Flash. + * @note This function should be used after reset. + * @retval None + */ +void SystemInit(void) +{ +#if (WDT_ENABLE == 1) + HT_CKCU->APBCCR1 |= (0x1 << 4); + HT_WDT->PR = 0x35CA; + HT_WDT->MR0 = 0; + HT_WDT->MR1 = ((HT_WDT->MR1 & 0xFFF) | (WDT_PRESCALER << 12)); + HT_WDT->MR0 = WDT_RELOAD | (WDT_RESET_ENABLE << 13) | (WDT_SLEEP_HALT << 14) | (0x1 << 16); + HT_WDT->CR = 0x5FA00001; +#else + #if (DEINIT_ENABLE == 1) + HT_RSTCU->APBPRST1 = (1 << 4); + #endif +#endif + + SetBit_BB((u32)(&HT_CKCU->APBCCR1), 6); /* enable VDD power domain register clock */ + + #if (DEINIT_ENABLE == 1) + /* De-init the setting */ + HT_CKCU->AHBCCR &= ~(0x1 << 11); /* disable IP who may use PLL as source */ + SetBit_BB((u32)(&HT_CKCU->GCCR), 11); /* enable HSI */ + while (!GetBit_BB((u32)(&HT_CKCU->GCSR), 3)); /* wait for HSI ready */ + HT_CKCU->GCCR = ((HT_CKCU->GCCR & ~7UL) | 3UL); /* select CK_SYS source */ + while ((HT_CKCU->CKST & 7UL) != 3UL); /* wait for clock switch complete */ + HT_FLASH->CFCR = (((HT_FLASH->CFCR) & ~7UL) | 1UL); /* set Wait State as 0 WS */ + HT_CKCU->AHBCFGR = 0; /* set CK_AHB prescaler */ + ResetBit_BB((u32)(&HT_CKCU->GCCR), 9); /* disable PLL */ + SetBit_BB((u32)(&HT_CKCU->GCFGR), 8); /* select PLL source as HSI */ + #endif + + /* HSE initiation */ +#if (HSE_ENABLE == 1) + SetBit_BB((u32)(&HT_CKCU->GCCR), 10); /* enable HSE */ + while (!GetBit_BB((u32)(&HT_CKCU->GCSR), 2)){}; /* wait for HSE ready */ +#endif + + /* LSE initiation */ +#if (LSE_ENABLE == 1) + do { + SetBit_BB((u32)(&HT_RTC->CR), 3); /* enable LSE */ + } while (!GetBit_BB((u32)(&HT_RTC->CR), 3)); + while (!GetBit_BB((u32)(&HT_CKCU->GCSR), 4)); /* wait for LSE ready */ +#endif + + ResetBit_BB((u32)(&HT_CKCU->APBCCR1), 6); /* disable VDD power domain register clock */ + + /* LSI initiation */ +#if (HCLK_SRC == 7) + while (!GetBit_BB((u32)(&HT_CKCU->GCSR), 5)){}; /* wait for LSI ready */ +#endif + + /* PLL initiation */ +#if (PLL_ENABLE == 1) + HT_CKCU->PLLCFGR = ((PLL_NF2_DIV & 0x0F) << 23) | (PLL_NO2_DIV << 21); /* set PLL divider */ + + #if (PLL_CLK_SRC_DIV == 1) + SetBit_BB((u32)(&HT_CKCU->PLLCFGR), 28); /* set PLL clock source divider */ + #else + ResetBit_BB((u32)(&HT_CKCU->PLLCFGR), 28); /* reset PLL clock source divider */ + #endif + + #if (PLL_CLK_SRC == 0) + ResetBit_BB((u32)(&HT_CKCU->GCFGR), 8); /* select PLL source as HSE */ + #else + SetBit_BB((u32)(&HT_CKCU->GCFGR), 8); /* select PLL source as HSI */ + #endif + + SetBit_BB((u32)(&HT_CKCU->GCCR), 9); /* enable PLL */ + while (!GetBit_BB((u32)(&HT_CKCU->GCSR), 1)){}; /* wait for PLL ready */ +#endif + + /* CK_AHB initiation */ +#if (WAIT_STATE == 9) + #if (__CK_AHB > WS1_CLK) + HT_FLASH->CFCR = (((HT_FLASH->CFCR) & ~7UL) | 3UL); /* auto-select wait state */ + #elif (__CK_AHB > WS0_CLK) + HT_FLASH->CFCR = (((HT_FLASH->CFCR) & ~7UL) | 2UL); /* auto-select wait state */ + #endif +#else + HT_FLASH->CFCR = (((HT_FLASH->CFCR) & ~7UL) | (WAIT_STATE + 1)); /* manual wait state */ +#endif + + HT_CKCU->AHBCFGR = HCLK_DIV; /* set CK_AHB prescaler */ + HT_CKCU->GCCR = ((HT_CKCU->GCCR & ~7UL) | HCLK_SRC); /* select CK_SYS source */ + while ((HT_CKCU->CKST & 7UL) != HCLK_SRC); /* wait for clock switch complete */ + + /* Pre-fetch buffer configuration */ +#if (PRE_FETCH_ENABLE == 0) + ResetBit_BB((u32)(&HT_FLASH->CFCR), 4); /* 0: pre-fetch disable, 1: pre-fetch enable */ +#else + SetBit_BB((u32)(&HT_FLASH->CFCR), 4); /* 0: pre-fetch disable, 1: pre-fetch enable */ +#endif + + /* HSE power down */ +#if ((HSE_ENABLE == 0) && (HCLK_SRC != 2) && ((PLL_ENABLE == 0) || (PLL_CLK_SRC == 1))) + ResetBit_BB((u32)(&HT_CKCU->GCCR), 10); +#endif + + /* HSI power down */ +#if ((HSI_ENABLE == 0) && (HCLK_SRC != 3) && ((PLL_ENABLE == 0) || (PLL_CLK_SRC == 0))) + ResetBit_BB((u32)(&HT_CKCU->GCCR), 11); +#endif +} + +/** + * @brief Update SystemCoreClock + * @retval None + */ +void SystemCoreClockUpdate(void) +{ + u32 SystemCoreClockDiv = HT_CKCU->AHBCFGR & 7UL; + u32 PllSourceClockDiv = (HT_CKCU->PLLCFGR >> 28) & 1UL; + u32 PllFeedbackClockDiv = (((HT_CKCU->PLLCFGR >> 23) & 15UL) == 0) ? (16) : ((HT_CKCU->PLLCFGR >> 23) & 15UL); + u32 PllOutputClockDiv = (HT_CKCU->PLLCFGR >> 21) & 3UL; + u32 SystemCoreClockSrc = HT_CKCU->CKST & 7UL; + + /* Get system core clock according to global clock control & configuration registers */ + if (SystemCoreClockSrc == 1) + { + if (GetBit_BB((u32)(&HT_CKCU->PLLCR), 31)) + { + PllFeedbackClockDiv = 1; + PllOutputClockDiv = 0; + } + + if (GetBit_BB((u32)(&HT_CKCU->GCFGR), 8)) + { + SystemCoreClock = (((HSI_VALUE >> PllSourceClockDiv) * PllFeedbackClockDiv) >> PllOutputClockDiv) >> SystemCoreClockDiv; + } + else + { + SystemCoreClock = (((HSE_VALUE >> PllSourceClockDiv) * PllFeedbackClockDiv) >> PllOutputClockDiv) >> SystemCoreClockDiv; + } + } + else if (SystemCoreClockSrc == 2) + { + SystemCoreClock = HSE_VALUE >> SystemCoreClockDiv; + } + else if (SystemCoreClockSrc == 3) + { + SystemCoreClock = HSI_VALUE >> SystemCoreClockDiv; + } + else if (SystemCoreClockSrc == 6) + { + SystemCoreClock = LSE_VALUE >> SystemCoreClockDiv; + } + else if (SystemCoreClockSrc == 7) + { + SystemCoreClock = LSI_VALUE >> SystemCoreClockDiv; + } +} + +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ + +/******************* (C) COPYRIGHT Holtek Semiconductor Inc. *****END OF FILE*** */ diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/system_ht32f5xxxx_18.c b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/system_ht32f5xxxx_18.c new file mode 100644 index 0000000000..ba5073e76f --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/system_ht32f5xxxx_18.c @@ -0,0 +1,518 @@ +/**************************************************************************//** + * @file library/Device/Holtek/HT32F5xxxx/Source/system_ht32f5xxxx_18.c + * @brief CMSIS Cortex-M0+ Device Peripheral Access Layer Source File + * for the Holtek HT32F5xxxx Device Series + * @version $Rev:: 7413 $ + * @date $Date:: 2023-12-15 #$ + * + * @note + * Copyright (C) Holtek Semiconductor Inc. All rights reserved. + * + * @par + * ARM Limited (ARM) supplies this software for Cortex-M processor-based + * microcontrollers. This file can be freely distributed within development + * tools that are supporting such ARM based processors. + * + * @par + * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR + * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + ******************************************************************************/ + +// Supported Device +// ======================================== +// HT32F0008 +// HT32F52142 +// HT32F52344, HT32F52354 +// HT32F52357, HT32F52367 +// HT32F65230, HT32F65240 +// HT50F3200T + +//#define USE_HT32F0008 +//#define USE_HT32F52142 +//#define USE_HT32F52344_54 +//#define USE_HT32F52357_67 +//#define USE_HT32F65230_40 +//#define USE_HT50F3200T + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup HT32F5xxxx_system HT32F5xxxx System + * @{ + */ + + +#include "ht32f5xxxx_01.h" + +/** @addtogroup HT32F5xxxx_System_Private_Defines + * @{ + */ +/* +//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ +*/ + +/*--------------------- Clock Configuration ---------------------------------- +// +// Enable High Speed External Crystal Oscillator (HSE) +// Default HSE = DISABLE +// +// Enable Low Speed External Crystal Oscillator (LSE) +// Default LSE = DISABLE +// Enable Waiting LSE Clock Ready +// Default Waiting LSE Clock Ready = ENABLE +// +// +// Enable PLL +// Default PLL = DISABLE +// PLL Out = (((HSE or HSI) / SRC_DIV) x NF2 ) / NO2 +// PLL Clock Source +// <0=> CK_HSE +// <1=> CK_HSI +// Default PLL clock source = CK_HSI +// PLL source clock must be in the range of 4 MHz to 16 MHz +// PLL Clock Source Divider (SRC_DIV) +// <0=> 1 +// <1=> 2 +// PLL input clock = PLL Clock Source / (SRC_DIV) +// PLL Feedback Clock Divider (NF2): 1 ~ 16 +// <1-16:1> +// PLL feedback clock = PLL input clock x NF2 +// PLL feedback clock must be in the range of 24 MHz to 60 MHz +// PLL Output Clock Divider (NO2) +// <0=> 1 +// <1=> 2 +// <2=> 4 +// <3=> 8 +// PLL output clock = PLL feedback clock / NO2 +// PLL output clock must be in the range of 4 MHz to 60 MHz +// +// +// SystemCoreClock Configuration (CK_AHB) +// SystemCoreClock Source +// <1=> CK_PLL +// <2=> CK_HSE +// <3=> CK_HSI +// <6=> CK_LSE +// <7=> CK_LSI +// Default SystemCoreClock source = CK_HSI +// SystemCoreClock Source Divider +// <0=> 1 +// <1=> 2 +// <2=> 4 +// <3=> 8 +// <4=> 16 +// <5=> 32 +// Default SystemCoreClock source divider = 1 +// +// +// FLASH Configuration +// Wait state +// <0=> 0 WS +// <1=> 1 WS +// <2=> 2 WS +// <9=> AUTO +// 0 WS: 1 kHz <= CK_AHB <= 20 MHz +// 1 WS: 20 MHz < CK_AHB <= 40 MHz +// 2 WS: 40 MHz < CK_AHB <= 60 MHz +// Pre-fetch Buffer Enable +// Default pre-fetch buffer = ENABLE +// Branch cache Enable (HT32F52357/67, HT32F65230/40, HT50F3200T Only) +// Default branch cache = ENABLE +// +*/ + +/* !!! NOTICE !!! + HSI must keep turn on when doing the Flash operation (Erase/Program). +*/ + +/* !!! NOTICE !!! + * How to adjust the value of High Speed External oscillator (HSE)? + The default value of HSE is define by "HSE_VALUE" in "ht32fxxxxx_nn.h". + If your board uses a different HSE speed, please add a new compiler preprocessor + C define, "HSE_VALUE=n000000" ("n" represents n MHz) in the toolchain/IDE, + or edit the "HSE_VALUE" in the "ht32f5xxxx_conf.h" file. + Take Keil MDK-ARM for instance, to set HSE as 16 MHz: + "Option of Taret -> C/C++ > Preprocessor Symbols" + Define: USE_HT32_DRIVER, USE_HT32Fxxxxx_SK, USE_HT32Fxxxxx_xx, USE_MEM_HT32Fxxxxx, HSE_VALUE=16000000 + ^^ Add "HSE_VALUE" + define as above. +*/ +#define HSI_ENABLE (1) /*!< 0: DISABLE, 1: ENABLE */ +#define HSE_ENABLE (0) /*!< 0: DISABLE, 1: ENABLE */ +#define LSI_ENABLE (1) /*!< 0: DISABLE, 1: ENABLE */ +#define LSE_ENABLE (0) /*!< 0: DISABLE, 1: ENABLE */ +#define LSE_WAIT_READY (1) /*!< 0: DISABLE, 1: ENABLE */ +#define PLL_ENABLE (1) /*!< 0: DISABLE, 1: ENABLE */ +#define PLL_CLK_SRC (1) /*!< 0: HSE, 1: HSI */ +#define PLL_CLK_SRC_DIV (1) /*!< 0: DIV1, 1: DIV2 */ +#define PLL_NF2_DIV (15) /*!< 1~16: DIV1~DIV16 */ +#define PLL_NO2_DIV (0) /*!< 0: DIV1, 1: DIV2, 2: DIV4, 3: DIV8 */ +#define HCLK_SRC (1) /*!< 0: PLL, 1: PLL, 2: HSE, 3: HSI 6: LSE, 7: LSI */ +#define HCLK_DIV (0) /*!< 0: DIV1, 1: DIV2, 2: DIV4, 3: DIV8, 4: DIV16, 5: DIV32 */ +#define WAIT_STATE (9) /*!< 0: WS = 0, 1: WS = 1, 2: WS = 2, 9: AUTO */ +#define PRE_FETCH_ENABLE (1) /*!< 0: DISABLE, 1: ENABLE */ +#define BCACHE_ENABLE (1) /*!< 0: DISABLE, 1: ENABLE */ +#define DEINIT_ENABLE (1) /* Set 0 for reduce code size */ + +/*----------------------------------------------------------------------------------------------------------*/ +/* PLL Out = (((HSE or HSI) / (PLL_CLK_SRC_DIV + 1)) x PLL_NF2) / PLL_NO2 */ +/*----------------------------------------------------------------------------------------------------------*/ + + +/*--------------------- WDT Configuration ---------------------------------- +// +// Enable WDT Configuration +// WDT Prescaler Selection +// <0=> CK_WDT / 1 +// <1=> CK_WDT / 2 +// <2=> CK_WDT / 4 +// <3=> CK_WDT / 8 +// <4=> CK_WDT / 16 +// <5=> CK_WDT / 32 +// <6=> CK_WDT / 64 +// <7=> CK_WDT / 128 +// WDT Reload Value <1-4095:1> +// Enable WDT Reset function +// WDT Sleep Halt mode +// <0=> No halt +// <1=> Halt in DeepSleep1 +// <2=> Halt in Sleep & DeepSleep1 +// +*/ +#define WDT_ENABLE (0) /*!< 0: DISABLE, 1: ENABLE */ +#define WDT_PRESCALER (5) /*!< 0: 1/1, 1: 1/2, 2: 1/4, 3: 1/8, 4: 1/16, 5: 1/32, 6: 1/64, 7: 1/128 */ +#define WDT_RELOAD (2000) /*!< 0 ~ 4095, 12 bit */ +#define WDT_RESET_ENABLE (1) /*!< 0: No Reset, 1: Reset when WDT over flow */ +#define WDT_SLEEP_HALT (2) /*!< 0: No halt, 1: Halt in DeepSleep1, 2: Halt in Sleep & DeepSleep1 */ + +/** + * @brief Check HSI frequency + */ +#if (HSI_VALUE != 8000000UL) + #error "CK_HSI clock issue: must be 8 MHz!" +#endif + +/** + * @brief Check HSE frequency + */ +#if ((HSE_VALUE < 4000000UL) || (HSE_VALUE > 16000000UL)) + #error "CK_HSE clock issue: must be in the range of 4 MHz to 16 MHz!" +#endif + +/** + * @brief Check LSI frequency + */ +#if (LSI_VALUE != 32000UL) + #error "CK_LSI clock issue: must be 32 kHz!" +#endif + +/** + * @brief Check LSE frequency + */ +#if (LSE_VALUE != 32768UL) + #error "CK_LSE clock issue: must be 32.768 kHz!" +#endif + +/** + * @brief CK_PLL definition + */ +#if (PLL_ENABLE == 1) + /* Get CK_VCO frequency */ + #if (PLL_CLK_SRC == 1) + #if (HSI_ENABLE == 0) + #error "CK_PLL clock source issue: HSI has not been enabled" + #else + #define __CK_VCO ((HSI_VALUE >> PLL_CLK_SRC_DIV) * PLL_NF2_DIV) /*!< Select HSI as PLL source */ + #endif + #else + #if (HSE_ENABLE == 0) + #error "CK_PLL clock source issue: HSE has not been enabled!" + #else + #define __CK_VCO ((HSE_VALUE >> PLL_CLK_SRC_DIV) * PLL_NF2_DIV) /*!< Select HSE as PLL source */ + #endif + #endif + + #define VCO_MIN 24000000UL + #define VCO_MAX 60000000UL + #define PLL_MIN 4000000UL + #define PLL_MAX 60000000UL + + /* Check CK_VCO frequency */ + #if ((__CK_VCO < VCO_MIN) || (__CK_VCO > VCO_MAX)) + #error "CK_VCO clock issue: must be in the range!" + #endif + + #define __CK_PLL (__CK_VCO >> PLL_NO2_DIV) /*!< Get CK_PLL frequency */ + + /* Check CK_PLL frequency */ + #if ((__CK_PLL < PLL_MIN) || (__CK_PLL > PLL_MAX)) + #error "CK_PLL clock issue: must be in the range!" + #endif +#endif + +/** + * @brief CK_SYS definition + */ +#if (HCLK_SRC == 1) + #if (PLL_ENABLE == 1) + #define __CK_SYS __CK_PLL /*!< Select PLL as CK_SYS source */ + #else + #error "CK_SYS clock source issue: PLL is not enable!" + #endif +#elif (HCLK_SRC == 2) + #if (HSE_ENABLE == 1) + #define __CK_SYS HSE_VALUE /*!< Select HSE as CK_SYS source */ + #else + #error "CK_SYS clock source issue: HSE is not enable!" + #endif +#elif (HCLK_SRC == 3) + #if (HSI_ENABLE == 1) + #define __CK_SYS HSI_VALUE /*!< Select HSI as CK_SYS source */ + #else + #error "CK_SYS clock source issue: HSI is not enable!" + #endif +#elif (HCLK_SRC == 6) + #if (LSE_ENABLE == 1) + #define __CK_SYS LSE_VALUE /*!< Select LSE as CK_SYS source */ + #else + #error "CK_SYS clock source issue: LSE is not enable!" + #endif +#elif (HCLK_SRC == 7) + #if (LSI_ENABLE == 1) + #define __CK_SYS LSI_VALUE /*!< Select LSI as CK_SYS source */ + #else + #error "CK_SYS clock source issue: LSI is not enable!" + #endif +#else + #error "CK_SYS clock source issue: No clock source is selected!" +#endif + +/** + * @brief CK_AHB definition + */ +#define __CK_AHB (__CK_SYS >> HCLK_DIV) /*!< Get CK_AHB frequency */ + +#define CKAHB_MIN 1000UL +#define CKAHB_MAX 60000000UL +#define WS0_CLK 20000000UL +#define WS1_CLK 40000000UL + +/* Check CK_AHB frequency */ +#if ((__CK_AHB < CKAHB_MIN) || (__CK_AHB > CKAHB_MAX)) + #error "CK_AHB clock issue: must be in the range!" +#endif + +/* Check FLASH wait-state setting */ +#if ((__CK_AHB > WS1_CLK) && (WAIT_STATE < 2) || \ + (__CK_AHB > WS0_CLK) && (WAIT_STATE < 1)) + #error "FLASH wait state configuration issue!" +#endif +/** + * @} + */ + +/** @addtogroup HT32F5xxxx_System_Private_Variables + * @{ + */ +__IO uint32_t SystemCoreClock = __CK_AHB; /*!< SystemCoreClock = CK_AHB */ +/** + * @} + */ + +/** @addtogroup HT32F5xxxx_System_Private_Functions + * @{ + */ + +/** + * @brief Setup the microcontroller system. + * Initializes the system clocks and the embedded Flash. + * @note This function should be used after reset. + * @retval None + */ +void SystemInit(void) +{ +#if (WDT_ENABLE == 1) + HT_CKCU->APBCCR1 |= (0x1 << 4); + HT_WDT->PR = 0x35CA; + HT_WDT->MR0 = 0; + HT_WDT->MR1 = ((HT_WDT->MR1 & 0xFFF) | (WDT_PRESCALER << 12)); + HT_WDT->MR0 = WDT_RELOAD | (WDT_RESET_ENABLE << 13) | (WDT_SLEEP_HALT << 14) | (0x1 << 16); + HT_WDT->CR = 0x5FA00001; +#else + #if (DEINIT_ENABLE == 1) + HT_RSTCU->APBPRST1 = (1 << 4); + #endif +#endif + + SetBit_BB((u32)(&HT_CKCU->APBCCR1), 6); /* enable Backup domain register clock */ + while (HT_PWRCU->TEST != 0x27); /* wait for Backup domain register ready */ + + #if (DEINIT_ENABLE == 1) + /* De-init the setting */ + HT_CKCU->AHBCCR &= ~(0x3 << 10); /* disable IP who may use PLL as source */ + SetBit_BB((u32)(&HT_CKCU->GCCR), 11); /* enable HSI */ + while (!GetBit_BB((u32)(&HT_CKCU->GCSR), 3)); /* wait for HSI ready */ + HT_CKCU->GCCR = ((HT_CKCU->GCCR & ~7UL) | 3UL); /* select CK_SYS source */ + while ((HT_CKCU->CKST & 7UL) != 3UL); /* wait for clock switch complete */ + HT_FLASH->CFCR = (((HT_FLASH->CFCR) & ~7UL) | 1UL); /* set Wait State as 0 WS */ + HT_CKCU->AHBCFGR = 0; /* set CK_AHB prescaler */ + ResetBit_BB((u32)(&HT_CKCU->GCCR), 9); /* disable PLL */ + SetBit_BB((u32)(&HT_CKCU->GCFGR), 8); /* select PLL source as HSI */ + #ifndef USE_HT32F65230_40 + ResetBit_BB((u32)(&HT_CKCU->GCCR), 3); /* disable USB PLL */ + SetBit_BB((u32)(&HT_CKCU->GCFGR), 9); /* select USB PLL source as HSI */ + #endif + #endif + + /* HSE initiation */ +#if (HSE_ENABLE == 1) + SetBit_BB((u32)(&HT_CKCU->GCCR), 10); /* enable HSE */ + while (!GetBit_BB((u32)(&HT_CKCU->GCSR), 2)){}; /* wait for HSE ready */ +#endif + + /* LSE initiation */ +#if (LSE_ENABLE == 1) + do { + SetBit_BB((u32)(&HT_RTC->CR), 3); /* enable LSE */ + } while (!GetBit_BB((u32)(&HT_RTC->CR), 3)); + #if (LSE_WAIT_READY == 1) + while (!GetBit_BB((u32)(&HT_CKCU->GCSR), 4)); /* wait for LSE ready */ + #endif +#endif + + ResetBit_BB((u32)(&HT_CKCU->APBCCR1), 6); /* disable Backup domain register clock */ + + /* LSI initiation */ +#if (HCLK_SRC == 7) + while (!GetBit_BB((u32)(&HT_CKCU->GCSR), 5)){}; /* wait for LSI ready */ +#endif + + /* PLL initiation */ +#if (PLL_ENABLE == 1) + HT_CKCU->PLLCFGR = ((PLL_NF2_DIV & 0x0F) << 23) | (PLL_NO2_DIV << 21); /* set PLL divider */ + + #if (PLL_CLK_SRC_DIV == 1) + SetBit_BB((u32)(&HT_CKCU->PLLCFGR), 28); /* set PLL clock source divider */ + #else + ResetBit_BB((u32)(&HT_CKCU->PLLCFGR), 28); /* reset PLL clock source divider */ + #endif + + #if (PLL_CLK_SRC == 0) + ResetBit_BB((u32)(&HT_CKCU->GCFGR), 8); /* select PLL source as HSE */ + #else + SetBit_BB((u32)(&HT_CKCU->GCFGR), 8); /* select PLL source as HSI */ + #endif + + SetBit_BB((u32)(&HT_CKCU->GCCR), 9); /* enable PLL */ + while (!GetBit_BB((u32)(&HT_CKCU->GCSR), 1)){}; /* wait for PLL ready */ +#endif + + /* CK_AHB initiation */ +#if (WAIT_STATE == 9) + #if (__CK_AHB > WS1_CLK) + HT_FLASH->CFCR = (((HT_FLASH->CFCR) & ~7UL) | 3UL); /* auto-select wait state */ + #elif (__CK_AHB > WS0_CLK) + HT_FLASH->CFCR = (((HT_FLASH->CFCR) & ~7UL) | 2UL); /* auto-select wait state */ + #endif +#else + HT_FLASH->CFCR = (((HT_FLASH->CFCR) & ~7UL) | (WAIT_STATE + 1)); /* manual wait state */ +#endif + + HT_CKCU->AHBCFGR = HCLK_DIV; /* set CK_AHB prescaler */ + HT_CKCU->GCCR = ((HT_CKCU->GCCR & ~7UL) | HCLK_SRC); /* select CK_SYS source */ + while ((HT_CKCU->CKST & 7UL) != HCLK_SRC); /* wait for clock switch complete */ + + /* Pre-fetch buffer configuration */ +#if (PRE_FETCH_ENABLE == 0) + ResetBit_BB((u32)(&HT_FLASH->CFCR), 4); /* 0: pre-fetch disable, 1: pre-fetch enable */ +#else + SetBit_BB((u32)(&HT_FLASH->CFCR), 4); /* 0: pre-fetch disable, 1: pre-fetch enable */ +#endif + + /* Branch cache configuration */ +#if defined(USE_HT32F52357_67) || defined(USE_HT32F65230_40) +#if (BCACHE_ENABLE == 0) + ResetBit_BB((u32)(&HT_FLASH->CFCR), 12); /* 0: branch cache disable, 1: branch cache enable */ +#else + SetBit_BB((u32)(&HT_FLASH->CFCR), 12); /* 0: branch cache disable, 1: branch cache enable */ +#endif +#endif + + /* HSE power down */ +#if ((HSE_ENABLE == 0) && (HCLK_SRC != 2) && ((PLL_ENABLE == 0) || (PLL_CLK_SRC == 1))) + ResetBit_BB((u32)(&HT_CKCU->GCCR), 10); +#endif + + /* HSI power down */ +#if ((HSI_ENABLE == 0) && (HCLK_SRC != 3) && ((PLL_ENABLE == 0) || (PLL_CLK_SRC == 0))) + ResetBit_BB((u32)(&HT_CKCU->GCCR), 11); +#endif +} + +/** + * @brief Update SystemCoreClock + * @retval None + */ +void SystemCoreClockUpdate(void) +{ + u32 SystemCoreClockDiv = HT_CKCU->AHBCFGR & 7UL; + u32 PllSourceClockDiv = (HT_CKCU->PLLCFGR >> 28) & 1UL; + u32 PllFeedbackClockDiv = (((HT_CKCU->PLLCFGR >> 23) & 15UL) == 0) ? (16) : ((HT_CKCU->PLLCFGR >> 23) & 15UL); + u32 PllOutputClockDiv = (HT_CKCU->PLLCFGR >> 21) & 3UL; + u32 SystemCoreClockSrc = HT_CKCU->CKST & 7UL; + + /* Get system core clock according to global clock control & configuration registers */ + if (SystemCoreClockSrc == 1) + { + if (GetBit_BB((u32)(&HT_CKCU->PLLCR), 31)) + { + PllFeedbackClockDiv = 1; + PllOutputClockDiv = 0; + } + + if (GetBit_BB((u32)(&HT_CKCU->GCFGR), 8)) + { + SystemCoreClock = (((HSI_VALUE >> PllSourceClockDiv) * PllFeedbackClockDiv) >> PllOutputClockDiv) >> SystemCoreClockDiv; + } + else + { + SystemCoreClock = (((HSE_VALUE >> PllSourceClockDiv) * PllFeedbackClockDiv) >> PllOutputClockDiv) >> SystemCoreClockDiv; + } + } + else if (SystemCoreClockSrc == 2) + { + SystemCoreClock = HSE_VALUE >> SystemCoreClockDiv; + } + else if (SystemCoreClockSrc == 3) + { + SystemCoreClock = HSI_VALUE >> SystemCoreClockDiv; + } + else if (SystemCoreClockSrc == 6) + { + SystemCoreClock = LSE_VALUE >> SystemCoreClockDiv; + } + else if (SystemCoreClockSrc == 7) + { + SystemCoreClock = LSI_VALUE >> SystemCoreClockDiv; + } +} + +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ + +/******************* (C) COPYRIGHT Holtek Semiconductor Inc. *****END OF FILE*** */ diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32.h b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32.h new file mode 100644 index 0000000000..ccedbb647f --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32.h @@ -0,0 +1,35 @@ +/*********************************************************************************************************//** + * @file ht32.h + * @version $Rev:: 1704 $ + * @date $Date:: 2017-08-17 #$ + * @brief The API between application and HT32FXXXX Firmware Library. + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------------------------------------*/ +#ifndef __HT32_H +#define __HT32_H + +/* Includes ------------------------------------------------------------------------------------------------*/ +#include "ht32f5xxxx_01.h" + +#endif /* __HT32_H -----------------------------------------------------------------------------------------*/ diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32_cm0plus_misc.h b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32_cm0plus_misc.h new file mode 100644 index 0000000000..8919d357bc --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32_cm0plus_misc.h @@ -0,0 +1,132 @@ +/*********************************************************************************************************//** + * @file ht32_cm0plus_misc.h + * @version $Rev:: 750 $ + * @date $Date:: 2016-05-31 #$ + * @brief All the function prototypes for the miscellaneous firmware library. + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------------------------------------*/ +#ifndef __HT32_CM0PLUS_MISC_H +#define __HT32_CM0PLUS_MISC_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------------------------------------*/ +#include "ht32.h" + +/** @addtogroup HT32_Peripheral_Driver + * @{ + */ + +/** @addtogroup MISC + * @{ + */ + + +/* Exported constants --------------------------------------------------------------------------------------*/ +/** @defgroup MISC_Exported_Constants MISC exported constants + * @{ + */ + +/* Vector Table Base */ +#define NVIC_VECTTABLE_RAM ((u32)0x20000000) +#define NVIC_VECTTABLE_FLASH ((u32)0x00000000) + +#define IS_NVIC_VECTTABLE(VECTTABLE) ((VECTTABLE == NVIC_VECTTABLE_RAM) || \ + (VECTTABLE == NVIC_VECTTABLE_FLASH)) + +#define IS_NVIC_OFFSET(OFFSET) (OFFSET < 0x0001FFFF) + +/* System Low Power */ +#define NVIC_LOWPOWER_SEVONPEND ((u8)0x10) +#define NVIC_LOWPOWER_SLEEPDEEP ((u8)0x04) +#define NVIC_LOWPOWER_SLEEPONEXIT ((u8)0x02) + +#define IS_NVIC_LOWPOWER(LOWPOWER) ((LOWPOWER == NVIC_LOWPOWER_SEVONPEND) || \ + (LOWPOWER == NVIC_LOWPOWER_SLEEPDEEP) || \ + (LOWPOWER == NVIC_LOWPOWER_SLEEPONEXIT)) + +/* System Handler */ +#define SYSTEMHANDLER_NMI ((u32)0x80000000) +#define SYSTEMHANDLER_PSV ((u32)0x10000000) +#define SYSTEMHANDLER_SYSTICK ((u32)0x04000000) +#define SYSTEMHANDLER_ALL ((u32)0x94000000) + +#define IS_NVIC_SYSTEMHANDLER(HANDLER) ((HANDLER == SYSTEMHANDLER_NMI) || \ + (HANDLER == SYSTEMHANDLER_PSV) || \ + (HANDLER == SYSTEMHANDLER_SYSTICK) ||\ + (HANDLER == SYSTEMHANDLER_ALL)) + +/* SysTick clock source */ +#define SYSTICK_SRC_STCLK ((u32)0xFFFFFFFB) +#define SYSTICK_SRC_FCLK ((u32)0x00000004) + +#define IS_SYSTICK_CLOCK_SOURCE(SOURCE) ((SOURCE == SYSTICK_SRC_STCLK) || \ + (SOURCE == SYSTICK_SRC_FCLK) ) + +/* SysTick counter state */ +#define SYSTICK_COUNTER_DISABLE ((u32)0xFFFFFFFE) +#define SYSTICK_COUNTER_ENABLE ((u32)0x00000001) +#define SYSTICK_COUNTER_CLEAR ((u32)0x00000000) + +#define IS_SYSTICK_COUNTER(COUNTER) ((COUNTER == SYSTICK_COUNTER_DISABLE) || \ + (COUNTER == SYSTICK_COUNTER_ENABLE) || \ + (COUNTER == SYSTICK_COUNTER_CLEAR)) + +#define IS_SYSTICK_RELOAD(RELOAD) ((RELOAD > 0) && (RELOAD <= 0xFFFFFF)) +/** + * @} + */ + +/* Exported functions --------------------------------------------------------------------------------------*/ +/** @defgroup MISC_Exported_Functions MISC exported functions + * @{ + */ +void NVIC_SetVectorTable(u32 NVIC_VectTable, u32 NVIC_Offset); +void NVIC_LowPowerConfig(u8 NVIC_LowPowerMode, ControlStatus NewState); +void NVIC_SetPendingSystemHandler(u32 SystemHandler); +void SYSTICK_ClockSourceConfig(u32 SysTick_ClockSource); +void SYSTICK_CounterCmd(u32 SysTick_Counter); +void SYSTICK_IntConfig(ControlStatus NewState); +void SYSTICK_SetReloadValue(u32 SysTick_Reload); +u32 RBIT(u32 in); +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32_config.h b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32_config.h new file mode 100644 index 0000000000..bd4e561247 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32_config.h @@ -0,0 +1,307 @@ +/*********************************************************************************************************//** + * @file ht32_config.h + * @version $Rev:: 7125 $ + * @date $Date:: 2023-08-16 #$ + * @brief Configuration file of HT32. + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ +/* Define to prevent recursive inclusion -------------------------------------------------------------------*/ +#ifndef __HT32_CONFIG_H +#define __HT32_CONFIG_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Settings ------------------------------------------------------------------------------------------------*/ +#ifdef USE_HT32F59999_SK + #define USE_HT32F52352_SK +#endif +#ifdef USE_HT32F59999 + #define USE_HT32F52342_52 +#endif +#ifdef USE_MEM_HT32F59999 + #define USE_MEM_HT32F52352 +#endif + +#ifdef USE_HT32F52142_SK + #define USE_HT32F0008_SK +#endif +#ifdef USE_HT32F52142 + #define USE_HT32F0008 +#endif +#ifdef USE_MEM_HT32F52142 + #define USE_MEM_HT32F0008 +#endif + +#ifdef USE_HT32F61352_DVB + #define USE_HT32F0006_DVB +#endif +#ifdef USE_HT32F61352 + #define USE_HT32F0006 +#endif +#ifdef USE_MEM_HT32F61352 + #define USE_MEM_HT32F0006 +#endif +#ifdef USE_HT32F61355_56_57 + #define USE_HT32F0006 +#endif +#ifdef USE_MEM_HT32F61355 + #define USE_MEM_HT32F0006 +#endif +#ifdef USE_MEM_HT32F61356 + #define USE_MEM_HT32F0006 +#endif +#ifdef USE_MEM_HT32F61357 + #define USE_MEM_HT32F0006 +#endif + +#ifdef USE_HT50F32002_SK + #define USE_HT32F50230_SK +#endif +#ifdef USE_HT50F32002 + #define USE_HT32F50220_30 +#endif +#ifdef USE_MEM_HT50F32002 + #define USE_MEM_HT32F50230 +#endif + +#ifdef USE_HT50F32003_SK + #define USE_HT32F52352_SK +#endif +#ifdef USE_HT50F32003 + #define USE_HT32F52342_52 +#endif +#ifdef USE_MEM_HT50F32003 + #define USE_MEM_HT32F52352 +#endif + +#ifdef USE_HT32F59041_SK + #define USE_HT32F50241_SK +#endif +#ifdef USE_HT32F59041 + #define USE_HT32F50231_41 +#endif +#ifdef USE_MEM_HT32F59041 + #define USE_MEM_HT32F50241 +#endif + +#ifdef USE_HT32F59741_SK + #define USE_HT32F57341_SK +#endif +#ifdef USE_HT32F59741 + #define USE_HT32F57331_41 +#endif +#ifdef USE_MEM_HT32F59741 + #define USE_MEM_HT32F57341 +#endif + +#ifdef USE_HT32F67741_SK + #define USE_HT32F52241_SK +#endif +#ifdef USE_HT32F67741 + #define USE_HT32F52231_41 +#endif +#ifdef USE_MEM_HT32F67741 + #define USE_MEM_HT32F52241 +#endif + +#ifdef USE_HF5032_SK + #define USE_HT32F50230_SK +#endif +#ifdef USE_HF5032 + #define USE_HT32F50220_30 +#endif +#ifdef USE_MEM_HF5032 + #define USE_MEM_HT32F50230 +#endif + +#ifdef USE_HT32F65240 + #undef USE_HT32F65230_40 + #define USE_HT32F65230_40 +#elif defined USE_HT32F65230_40 + #undef USE_HT32F65240 + #define USE_HT32F65240 +#endif + +#ifdef USE_HT32F5828_SK + #define USE_HT32F57352_SK +#endif +#ifdef USE_HT32F5828 + #define USE_HT32F57342_52 +#endif +#ifdef USE_MEM_HT32F5828 + #define USE_MEM_HT32F57352 +#endif + +#ifdef USE_MXTX6306_SK + #define USE_HT32F65240_SK +#endif +#ifdef USE_MXTX6306 + #define USE_HT32F65230_40 +#endif +#ifdef USE_MEM_MXTX6306 + #define USE_MEM_HT32F65230 +#endif + +#ifdef USE_HT32F67232_SK + #define USE_HT32F52230_SK +#endif +#ifdef USE_HT32F67232 + #define USE_HT32F52220_30 +#endif +#ifdef USE_MEM_HT32F67232 + #define USE_MEM_HT32F52230 +#endif + +#ifdef USE_HT32F67233 + #define USE_HT32F52220_30 +#endif +#ifdef USE_MEM_HT32F67233 + #define USE_MEM_HT32F52230 +#endif + +#ifdef USE_HT50F3200S_SK + #define USE_HT32F65240_SK +#endif +#ifdef USE_HT50F3200S + #define USE_HT32F65230_40 +#endif +#ifdef USE_MEM_HT50F3200S + #define USE_MEM_HT32F65240 +#endif + +#ifdef USE_HT50F3200T_SK + #define USE_HT32F52367_SK +#endif +#ifdef USE_HT50F3200T + #define USE_HT32F52357_67 +#endif +#ifdef USE_MEM_HT50F3200T + #define USE_MEM_HT32F52367 +#endif + +#ifdef USE_HT32F62030_SK + #define USE_HT32F52230_SK +#endif +#ifdef USE_HT32F62030 + #define USE_HT32F52220_30 +#endif +#ifdef USE_MEM_HT32F62030 + #define USE_MEM_HT32F52230 +#endif + +#ifdef USE_HT32F62040_SK + #define USE_HT32F52241_SK +#endif +#ifdef USE_HT32F62040 + #define USE_HT32F52231_41 +#endif +#ifdef USE_MEM_HT32F62040 + #define USE_MEM_HT32F52241 +#endif + +#ifdef USE_HT32F62050_SK + #define USE_HT32F52253_SK +#endif +#ifdef USE_HT32F62050 + #define USE_HT32F52243_53 +#endif +#ifdef USE_MEM_HT32F62050 + #define USE_MEM_HT32F52253 +#endif + +#ifdef USE_HT32F61630_SK + #define USE_HT32F50030_SK +#endif +#ifdef USE_HT32F61630 + #define USE_HT32F50020_30 +#endif +#ifdef USE_MEM_HT32F61630 + #define USE_MEM_HT32F50030 +#endif + +#ifdef USE_HT32F61641_SK + #define USE_HT32F50241_SK +#endif +#ifdef USE_HT32F61641 + #define USE_HT32F50231_41 +#endif +#ifdef USE_MEM_HT32F61641 + #define USE_MEM_HT32F50241 +#endif + +#ifdef USE_HT32F67742_SK + #define USE_HT32F57341_SK +#endif +#ifdef USE_HT32F67742 + #define USE_HT32F57331_41 +#endif +#ifdef USE_MEM_HT32F67742 + #define USE_MEM_HT32F57341 +#endif + +#ifdef USE_HT32F59046_SK + #define USE_HT32F50241_SK +#endif +#ifdef USE_HT32F59046 + #define USE_HT32F50231_41 +#endif +#ifdef USE_MEM_HT32F59046 + #define USE_MEM_HT32F50241 +#endif + +#ifdef USE_HT32F59746_SK + #define USE_HT32F57341_SK +#endif +#ifdef USE_HT32F59746 + #define USE_HT32F57331_41 +#endif +#ifdef USE_MEM_HT32F59746 + #define USE_MEM_HT32F57341 +#endif + +#ifdef USE_HT32F61030_SK + #define USE_HT32F50030_SK +#endif +#ifdef USE_HT32F61030 + #define USE_HT32F50020_30 +#endif +#ifdef USE_MEM_HT32F61030 + #define USE_MEM_HT32F50030 +#endif + +#ifdef USE_HT32F61041_SK + #define USE_HT32F50241_SK +#endif +#ifdef USE_HT32F61041 + #define USE_HT32F50231_41 +#endif +#ifdef USE_MEM_HT32F61041 + #define USE_MEM_HT32F50241 +#endif + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32_dependency.h b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32_dependency.h new file mode 100644 index 0000000000..d96ecb9c3c --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32_dependency.h @@ -0,0 +1,86 @@ +/*********************************************************************************************************//** + * @file ht32_dependency.h + * @version $Rev:: 5863 $ + * @date $Date:: 2022-05-12 #$ + * @brief The header file of dependency check. + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ +#ifdef __cplusplus + extern "C" { +#endif + + +#if 0 // Version setting example for module + +/* Dependency check ----------------------------------------------------------------------------------------*/ +#define MIN_HT32_FWLIB_VER (0x01000005) //0xmmnnnrrr -> Vm.n.r +#define MIN_HT32_FWLIB_SVN (0x2200) +#include "ht32_dependency.h" // Not exist means the version of HT32 Firmware Library is older than the module required. + +#endif + +#if 0 // Version setting example for module + +/* Dependency check ----------------------------------------------------------------------------------------*/ +#if (__CORTEX_M == 0) +#define MIN_HT32_FWLIB_VER (0x01000024) //0xmmnnnrrr -> Vm.n.r +#define MIN_HT32_FWLIB_SVN (0x5762) +#endif +#if (__CORTEX_M == 3) +#define MIN_HT32_FWLIB_VER (0x01000009) //0xmmnnnrrr -> Vm.n.r +#define MIN_HT32_FWLIB_SVN (0x2556) +#endif +#include "ht32_dependency.h" // Not exist means the version of HT32 Firmware Library is older than the module required. + +#endif + + +#if 0 // Enable for test +#undef HT32_FWLIB_VER +#undef HT32_FWLIB_SVN +#define HT32_FWLIB_VER (0x00000004) +#define HT32_FWLIB_SVN (0x1074) +#endif + + +// Check "ht32fxxxxx_lib.h" for the version of HT32 Firmwar Library +#if (HT32_FWLIB_VER != 999999) +#if HT32_FWLIB_VER < MIN_HT32_FWLIB_VER + #error !!! The version of HT32 Firmware Library is older than the module required. Please update HT32 Firmware Library. +#endif + +#if HT32_FWLIB_SVN < MIN_HT32_FWLIB_SVN + #error !!! The version of HT32 Firmware Library is older than the module required. Please update HT32 Firmware Library. +#endif +#endif + + +// Un-defined for next module of the .C include .C case +#undef MIN_HT32_FWLIB_VER +#undef MIN_HT32_FWLIB_SVN + + +#ifdef __cplusplus +} +#endif + +//#endif diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32_div.h b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32_div.h new file mode 100644 index 0000000000..7fa7c168c1 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32_div.h @@ -0,0 +1,37 @@ +/*********************************************************************************************************//** + * @file ht32_div.h + * @version $Rev:: 220 $ + * @date $Date:: 2016-02-16 #$ + * @brief The header file of division assembly. + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------------------------------------*/ +#ifndef __HT32_DIV_H +#define __HT32_DIV_H + +/* Exported functions --------------------------------------------------------------------------------------*/ +void DIV32_Init(void); +extern u32 (*UDIV32)(u32, u32); +extern s32 (*SDIV32)(s32, s32); + +#endif diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32_rand.h b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32_rand.h new file mode 100644 index 0000000000..46827ba414 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32_rand.h @@ -0,0 +1,43 @@ +/*********************************************************************************************************//** + * @file ht32_rand.h + * @version $Rev:: 957 $ + * @date $Date:: 2016-08-15 #$ + * @brief The header file of random number. + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ +/* Define to prevent recursive inclusion -------------------------------------------------------------------*/ +#ifndef __HT32_RAND_H +#define __HT32_RAND_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Exported functions --------------------------------------------------------------------------------------*/ +void Rand_Init(u32 *uSeed, u32 uCount, u32 a, u32 b); +extern u32 (*Rand_Get)(u32 *, u32); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32_retarget_desc.h b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32_retarget_desc.h new file mode 100644 index 0000000000..9605a27597 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32_retarget_desc.h @@ -0,0 +1,182 @@ +/*********************************************************************************************************//** + * @file ht32_retarget_desc.h + * @version $Rev:: 891 $ + * @date $Date:: 2016-07-14 #$ + * @brief The USB VCP descriptor file of retarget. + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------------------------------------*/ +#ifndef __HT32_RETARGET_DESC_H +#define __HT32_RETARGET_DESC_H + +/* Exported constants --------------------------------------------------------------------------------------*/ + + /*--------------------------------------------------------------------------------------------------------*/ + /* IAD to associate the two CDC interfaces */ + /*--------------------------------------------------------------------------------------------------------*/ + /* Field Size Description */ + 8, // bLength 1 Size of this descriptor in bytes + 11, // bDescriptorType 1 Descriptor Type + 11, // bFirstInterface 1 + 2, // bInterfaceCount 1 + 2, // bFunctionClass 1 + 2, // bFunctionSubClass 1 + 0, // bFunctionProtocol 1 + 0x00, // iFunction 1 Index of string descriptor describing this function. + + /*--------------------------------------------------------------------------------------------------------*/ + /* Interface descriptor */ + /*--------------------------------------------------------------------------------------------------------*/ + /* Field Size Description */ + /*----------------------------------------------------------------------------*/ + DESC_LEN_INF, // bLength 1 Size of this descriptor in bytes + DESC_TYPE_04_INF, // bDescriptorType 1 INTERFACE Descriptor Type + 11, // bInterfaceNumber 1 Number of this interface (Zero-based 0) + 0x00, // bAlternateSetting 1 Value used to select alternate setting + 1, // bNumEndpoints 1 Number of endpoints used by this interface + DESC_CLASS_02_CDC_CTRL, // bInterfaceClass 1 Class code (assigned by USB-IF) + 2, // bInterfaceSubClass 1 Subclass code (assigned by USB-IF) + 0, // bInterfaceProtocol 1 Protocol code (assigned by USB) + 0x00, // iInterface 1 Index of string descriptor describing this interface + + /*--------------------------------------------------------------------------------------------------------*/ + /* Header Functional descriptor */ + /*--------------------------------------------------------------------------------------------------------*/ + /* Field Size Description */ + /*----------------------------------------------------------------------------*/ + 5, // bFunctionLength 1 Size of this descriptor in bytes + 0x24, // bDescriptorType 1 CS_INTERFACE descriptor type + 0, // bDescriptorSubtype 1 header functional descriptor + DESC_H2B(0x0110), // bcdCDC 2 spec release number + + /*--------------------------------------------------------------------------------------------------------*/ + /* Abstract control management Functional */ + /*--------------------------------------------------------------------------------------------------------*/ + /* Field Size Description */ + /*----------------------------------------------------------------------------*/ + 4, // bFunctionLength 1 Size of this descriptor in bytes + 0x24, // bDescriptorType 1 CS_INTERFACE descriptor type + 2, // bDescriptorSubtype 1 Abstract Control Management Functional descriptor + 0x02, // bmCapabilities 1 + + /*--------------------------------------------------------------------------------------------------------*/ + /* Union Functional */ + /*--------------------------------------------------------------------------------------------------------*/ + /* Field Size Description */ + /*----------------------------------------------------------------------------*/ + 5, // bFunctionLength 1 Size of this descriptor in bytes + 0x24, // bDescriptorType 1 CS_INTERFACE descriptor type + 5, // bDescriptorSubtype 1 Union Functional descriptor + 0x00, // bMasterInterface 1 Communication class interface + 0x01, // bSlaveInterface0 1 Data Class Interface + + /*--------------------------------------------------------------------------------------------------------*/ + /* Call Management Functional */ + /*--------------------------------------------------------------------------------------------------------*/ + /* Field Size Description */ + /*----------------------------------------------------------------------------*/ + 5, // bFunctionLength 1 Size of this descriptor in bytes + 0x24, // bDescriptorType 1 CS_INTERFACE descriptor type + 1, // bDescriptorSubtype 1 Call Management Functional descriptor + 0x00, // bmCapabilities 1 + 0x01, // bDataInterface 1 Interface number of Data + + /*--------------------------------------------------------------------------------------------------------*/ + /* Endpoint descriptor */ + /*--------------------------------------------------------------------------------------------------------*/ + /* Field Size Description */ + /*----------------------------------------------------------------------------*/ + DESC_LEN_EPT, // bLengthE 1 Size of this descriptor in bytes + DESC_TYPE_05_EPT, // bDescriptorType 1 ENDPOINT Descriptor Type + (0x80 | RETARGET_CTRL_EPT), // bEndpointAddress 1 The address of the endpoint + // Bit 3..0: The endpoint number + // Bit 6..4: Reserved + // Bit 7 : Direction (0 = Out/1 = In) + 0x03, // bmAttribute 1 Endpoint Attribute + // Bit 1..0: Transfer type + // 00 = Control + // 01 = Isochronous + // 10 = Bulk + // 11 = Interrupt + // All other reserved + DESC_H2B(RETARGET_CTRL_LEN),// wMaxPacketSize 2 Maximum packet size + 0x00, // bInterval 1 Interval for polling endpoint + + /*--------------------------------------------------------------------------------------------------------*/ + /* Data class interface descriptor */ + /*--------------------------------------------------------------------------------------------------------*/ + /* Field Size Description */ + /*----------------------------------------------------------------------------*/ + DESC_LEN_INF, // bLength 1 Endpoint Descriptor size + DESC_TYPE_04_INF, // bDescriptorType 1 + 12, // bInterfaceNumber 1 Number of Interface + 0x00, // bAlternateSetting 1 Alternate setting + 2, // bNumEndpoints 1 Two endpoints used + DESC_CLASS_0A_CDC_DATA, // bInterfaceClass 1 + 0, // bInterfaceSubClass 1 + 0, // bInterfaceProtocol 1 + 0x00, // iInterface 1 + + /*--------------------------------------------------------------------------------------------------------*/ + /* Endpoint n Out descriptor */ + /*--------------------------------------------------------------------------------------------------------*/ + /* Field Size Description */ + /*----------------------------------------------------------------------------*/ + DESC_LEN_EPT, // bLength 1 Size of this descriptor in bytes + DESC_TYPE_05_EPT, // bDescriptorType 1 ENDPOINT Descriptor Type + (0x00 | RETARGET_RX_EPT), // bEndpointAddress 1 The address of the endpoint + // Bit 3..0: The endpoint number + // Bit 6..4: Reserved + // Bit 7 : Direction (0 = Out/1 = In) + 0x02, // bmAttribute 1 Endpoint Attribute + // Bit 1..0: Transfer type + // 00 = Control + // 01 = Isochronous + // 10 = Bulk + // 11 = Interrupt + // All other reserved + DESC_H2B(RETARGET_RX_LEN), // wMaxPacketSize 2 Maximum packet size + 0x00, // bInterval 1 Interval for polling endpoint + + /*--------------------------------------------------------------------------------------------------------*/ + /* Endpoint n In Descriptor */ + /*--------------------------------------------------------------------------------------------------------*/ + /* Field Size Description */ + /*----------------------------------------------------------------------------*/ + DESC_LEN_EPT, // bLength 1 Size of this descriptor in bytes + DESC_TYPE_05_EPT, // bDescriptorType 1 ENDPOINT Descriptor Type + (0x80 | RETARGET_TX_EPT), // bEndpointAddress 1 The address of the endpoint + // Bit 3..0: The endpoint number + // Bit 6..4: Reserved + // Bit 7 : Direction (0 = Out/1 = In) + 0x02, // bmAttribute 1 Endpoint Attribute + // Bit 1..0: Transfer type + // 00 = Control + // 01 = Isochronous + // 10 = Bulk + // 11 = Interrupt + // All other reserved + DESC_H2B(RETARGET_TX_LEN), // wMaxPacketSize 2 Maximum packet size + 0x00, // bInterval 1 Interval for polling endpoint + +#endif /* __HT32_RETARGET_DESC_H ---------------------------------------------------------------------------*/ diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32_retarget_usbdconf.h b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32_retarget_usbdconf.h new file mode 100644 index 0000000000..f06a334604 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32_retarget_usbdconf.h @@ -0,0 +1,321 @@ +/*********************************************************************************************************//** + * @file ht32_retarget_usbdconf.h + * @version $Rev:: 4447 $ + * @date $Date:: 2019-12-27 #$ + * @brief The USB Device configuration of retarget + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------------------------------------*/ +#ifndef __HT32_RETARGET_USBDCONF_H +#define __HT32_RETARGET_USBDCONF_H + +/* Settings ------------------------------------------------------------------------------------------------*/ +#define RETARGET_INF (0) +#define RETARGET_DLEN (0) + +#if (_RETARGET == 1) + + #ifdef RETARGET_IS_USB + + #undef RETARGET_INF + #undef RETARGET_DLEN + #define RETARGET_INF (2) + #define RETARGET_DLEN (8 + DESC_LEN_INF * 2 + 5 + 4 + 5 + 5 + DESC_LEN_EPT * 3) + + #if (_EP1_ENABLE == 0 && _EP2_ENABLE == 0 && _EP3_ENABLE == 0 && _EP4_ENABLE == 0 && \ + _EP5_ENABLE == 0 && _EP6_ENABLE == 0 && _EP7_ENABLE == 0) + #define NON_USB_IN_APP + #undef _UIER + #undef _EP0LEN + #undef _EP0_IER + #define _EP0LEN (64) + #define _EP0_IER (0x212) + #define _UIER (0x011D) + #endif + + #define _UIER_ALL (_UIER | (EP0IE << RETARGET_RX_EPT) | (EP0IE << RETARGET_TX_EPT)) + + #if (RETARGET_RX_EPT == 1 || RETARGET_TX_EPT == 1 || RETARGET_CTRL_EPT == 1) + #if (_EP1_ENABLE == 1) + #define _RERATGET1_ERR + #else + #undef _EP1_ENABLE + #undef _EP1_CFG_EPADR + #undef _EP1_CFG_EPEN_TMP + #undef _EP1_TYPR + #undef _EP1_CFG_EPDIR + #undef _EP1LEN_TMP + #undef _EP1_IER + + #define _EP1_ENABLE (1) + #define _EP1_CFG_EPADR (1) + #define _EP1_CFG_EPEN_TMP (1) + #if (RETARGET_RX_EPT == 1) + #define _EP1_TYPR (2) + #define _EP1_CFG_EPDIR (0) + #define _EP1LEN_TMP (RETARGET_RX_EPTLEN) + #define _EP1_IER (0x02) + #define RETARGET_RX_LEN (_EP1LEN) + #elif (RETARGET_TX_EPT == 1) + #define _EP1_TYPR (2) + #define _EP1_CFG_EPDIR (1) + #define _EP1LEN_TMP (RETARGET_TX_EPTLEN) + #define _EP1_IER (0x10) + #define RETARGET_TX_LEN (_EP1LEN) + #elif (RETARGET_CTRL_EPT == 1) + #define _EP1_TYPR (3) + #define _EP1_CFG_EPDIR (1) + #define _EP1LEN_TMP (RETARGET_CTRL_EPTLEN) + #define _EP1_IER (0x10) + #define RETARGET_CTRL_LEN (_EP1LEN) + #endif + #endif + #endif + + #if (RETARGET_RX_EPT == 2 || RETARGET_TX_EPT == 2 || RETARGET_CTRL_EPT == 2) + #if (_EP2_ENABLE == 1) + #define _RERATGET2_ERR + #else + #undef _EP2_ENABLE + #undef _EP2_CFG_EPADR + #undef _EP2_CFG_EPEN_TMP + #undef _EP2_TYPR + #undef _EP2_CFG_EPDIR + #undef _EP2LEN_TMP + #undef _EP2_IER + + #define _EP2_ENABLE (1) + #define _EP2_CFG_EPADR (2) + #define _EP2_CFG_EPEN_TMP (1) + #if (RETARGET_RX_EPT == 2) + #define _EP2_TYPR (2) + #define _EP2_CFG_EPDIR (0) + #define _EP2LEN_TMP (RETARGET_RX_EPTLEN) + #define _EP2_IER (0x02) + #define RETARGET_RX_LEN (_EP2LEN) + #elif (RETARGET_TX_EPT == 2) + #define _EP2_TYPR (2) + #define _EP2_CFG_EPDIR (1) + #define _EP2LEN_TMP (RETARGET_TX_EPTLEN) + #define _EP2_IER (0x10) + #define RETARGET_TX_LEN (_EP2LEN) + #elif (RETARGET_CTRL_EPT == 2) + #define _EP2_TYPR (3) + #define _EP2_CFG_EPDIR (1) + #define _EP2LEN_TMP (RETARGET_CTRL_EPTLEN) + #define _EP2_IER (0x10) + #define RETARGET_CTRL_LEN (_EP2LEN) + #endif + #endif + #endif + + #if (RETARGET_RX_EPT == 3 || RETARGET_TX_EPT == 3 || RETARGET_CTRL_EPT == 3) + #if (_EP3_ENABLE == 1) + #define _RERATGET3_ERR + #else + #undef _EP3_ENABLE + #undef _EP3_CFG_EPADR + #undef _EP3_CFG_EPEN_TMP + #undef _EP3_TYPR + #undef _EP3_CFG_EPDIR + #undef _EP3LEN_TMP + #undef _EP3_IER + + #define _EP3_ENABLE (1) + #define _EP3_CFG_EPADR (3) + #define _EP3_CFG_EPEN_TMP (1) + #if (RETARGET_RX_EPT == 3) + #define _EP3_TYPR (2) + #define _EP3_CFG_EPDIR (0) + #define _EP3LEN_TMP (RETARGET_RX_EPTLEN) + #define _EP3_IER (0x02) + #define RETARGET_RX_LEN (_EP3LEN) + #elif (RETARGET_TX_EPT == 3) + #define _EP3_TYPR (2) + #define _EP3_CFG_EPDIR (1) + #define _EP3LEN_TMP (RETARGET_TX_EPTLEN) + #define _EP3_IER (0x10) + #define RETARGET_TX_LEN (_EP3LEN) + #elif (RETARGET_CTRL_EPT == 3) + #define _EP3_TYPR (3) + #define _EP3_CFG_EPDIR (1) + #define _EP3LEN_TMP (RETARGET_CTRL_EPTLEN) + #define _EP3_IER (0x10) + #define RETARGET_CTRL_LEN (_EP3LEN) + #endif + #endif + #endif + + #if (RETARGET_RX_EPT == 4 || RETARGET_TX_EPT == 4 || RETARGET_CTRL_EPT == 4) + #if (_EP4_ENABLE == 1) + #define _RERATGET4_ERR + #else + #undef _EP4_ENABLE + #undef _EP4_CFG_EPADR + #undef _EP4_CFG_EPEN_TMP + #undef _EP4_TYPR + #undef _EP4_CFG_EPDIR + #undef _EP4LEN_TMP + #undef _EP4_IER + + #define _EP4_ENABLE (1) + #define _EP4_CFG_EPADR (4) + #define _EP4_CFG_EPEN_TMP (1) + #if (RETARGET_RX_EPT == 4) + #define _EP4_TYPR (2) + #define _EP4_CFG_EPDIR (0) + #define _EP4LEN_TMP (RETARGET_RX_EPTLEN) + #define _EP4_IER (0x02) + #define RETARGET_RX_LEN (_EP4LEN) + #elif (RETARGET_TX_EPT == 4) + #define _EP4_TYPR (2) + #define _EP4_CFG_EPDIR (1) + #define _EP4LEN_TMP (RETARGET_TX_EPTLEN) + #define _EP4_IER (0x10) + #define RETARGET_TX_LEN (_EP4LEN) + #elif (RETARGET_CTRL_EPT == 4) + #define _EP4_TYPR (3) + #define _EP4_CFG_EPDIR (1) + #define _EP4LEN_TMP (RETARGET_CTRL_EPTLEN) + #define _EP4_IER (0x10) + #define RETARGET_CTRL_LEN (_EP4LEN) + #endif + #endif + #endif + + #if (RETARGET_RX_EPT == 5 || RETARGET_TX_EPT == 5 || RETARGET_CTRL_EPT == 5) + #if (_EP5_ENABLE == 1) + #define _RERATGET5_ERR + #else + #undef _EP5_ENABLE + #undef _EP5_CFG_EPADR + #undef _EP5_CFG_EPEN_TMP + #undef _EP5_TYPR + #undef _EP5_CFG_EPDIR + #undef _EP5LEN_TMP + #undef _EP5_IER + + #define _EP5_ENABLE (1) + #define _EP5_CFG_EPADR (5) + #define _EP5_CFG_EPEN_TMP (1) + #if (RETARGET_RX_EPT == 5) + #define _EP5_TYPR (2) + #define _EP5_CFG_EPDIR (0) + #define _EP5LEN_TMP (RETARGET_RX_EPTLEN) + #define _EP5_IER (0x02) + #define RETARGET_RX_LEN (_EP5LEN) + #elif (RETARGET_TX_EPT == 5) + #define _EP5_TYPR (2) + #define _EP5_CFG_EPDIR (1) + #define _EP5LEN_TMP (RETARGET_TX_EPTLEN) + #define _EP5_IER (0x10) + #define RETARGET_TX_LEN (_EP5LEN) + #elif (RETARGET_CTRL_EPT == 5) + #define _EP5_TYPR (3) + #define _EP5_CFG_EPDIR (1) + #define _EP5LEN_TMP (RETARGET_CTRL_EPTLEN) + #define _EP5_IER (0x10) + #define RETARGET_CTRL_LEN (_EP5LEN) + #endif + #endif + #endif + + #if (RETARGET_RX_EPT == 6 || RETARGET_TX_EPT == 6 || RETARGET_CTRL_EPT == 6) + #if (_EP6_ENABLE == 1) + #define _RERATGET6_ERR + #else + #undef _EP6_ENABLE + #undef _EP6_CFG_EPADR + #undef _EP6_CFG_EPEN_TMP + #undef _EP6_TYPR + #undef _EP6_CFG_EPDIR + #undef _EP6LEN_TMP + #undef _EP6_IER + + #define _EP6_ENABLE (1) + #define _EP6_CFG_EPADR (6) + #define _EP6_CFG_EPEN_TMP (1) + #if (RETARGET_RX_EPT == 6) + #define _EP6_TYPR (2) + #define _EP6_CFG_EPDIR (0) + #define _EP6LEN_TMP (RETARGET_RX_EPTLEN) + #define _EP6_IER (0x02) + #define RETARGET_RX_LEN (_EP6LEN) + #elif (RETARGET_TX_EPT == 6) + #define _EP6_TYPR (2) + #define _EP6_CFG_EPDIR (1) + #define _EP6LEN_TMP (RETARGET_TX_EPTLEN) + #define _EP6_IER (0x10) + #define RETARGET_TX_LEN (_EP6LEN) + #elif (RETARGET_CTRL_EPT == 6) + #define _EP6_TYPR (3) + #define _EP6_CFG_EPDIR (1) + #define _EP6LEN_TMP (RETARGET_CTRL_EPTLEN) + #define _EP6_IER (0x10) + #define RETARGET_CTRL_LEN (_EP6LEN) + #endif + #endif + #endif + + #if (RETARGET_RX_EPT == 7 || RETARGET_TX_EPT == 7 || RETARGET_CTRL_EPT == 7) + #if (_EP7_ENABLE == 1) + #define _RERATGET7_ERR + #else + #undef _EP7_ENABLE + #undef _EP7_CFG_EPADR + #undef _EP7_CFG_EPEN_TMP + #undef _EP7_TYPR + #undef _EP7_CFG_EPDIR + #undef _EP7LEN_TMP + #undef _EP7_IER + + #define _EP7_ENABLE (1) + #define _EP7_CFG_EPADR (7) + #define _EP7_CFG_EPEN_TMP (1) + #if (RETARGET_RX_EPT == 7) + #define _EP7_TYPR (2) + #define _EP7_CFG_EPDIR (0) + #define _EP7LEN_TMP (RETARGET_RX_EPTLEN) + #define _EP7_IER (0x02) + #define RETARGET_RX_LEN (_EP7LEN) + #elif (RETARGET_TX_EPT == 7) + #define _EP7_TYPR (2) + #define _EP7_CFG_EPDIR (1) + #define _EP7LEN_TMP (RETARGET_TX_EPTLEN) + #define _EP7_IER (0x10) + #define RETARGET_TX_LEN (_EP7LEN) + #elif (RETARGET_CTRL_EPT == 7) + #define _EP7_TYPR (3) + #define _EP7_CFG_EPDIR (1) + #define _EP7LEN_TMP (RETARGET_CTRL_EPTLEN) + #define _EP7_IER (0x10) + #define RETARGET_CTRL_LEN (_EP7LEN) + #endif + #endif + #endif + + #endif /* #ifdef RETARGET_IS_USB */ + +#endif /* #if (_RETARGET == 1) */ + +#endif /* __HT32_RETARGET_USBDCONF_H -----------------------------------------------------------------------*/ diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32_serial.h b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32_serial.h new file mode 100644 index 0000000000..bea9f04ae3 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32_serial.h @@ -0,0 +1,84 @@ +/*********************************************************************************************************//** + * @file ht32_serial.h + * @version $Rev:: 6444 $ + * @date $Date:: 2022-11-11 #$ + * @brief The header file of the Serial library. + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------------------------------------*/ +#ifndef __HT32_SERIAL_H +#define __HT32_SERIAL_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------------------------------------*/ +#ifdef RETARGET_IS_USB +#include "ht32_usbd_core.h" +#endif + +/** @addtogroup HT32_Peripheral_Driver HT32 Peripheral Driver + * @{ + */ + +/** @addtogroup SERIAL + * @brief Serial related functions + * @{ + */ + + +/* Exported functions --------------------------------------------------------------------------------------*/ +/** @defgroup SERIAL_Exported_Functions Serial exported functions + * @{ + */ +void RETARGET_UART_IRQHandler(void); +u32 SERIAL_GetChar(void); +u32 SERIAL_PutChar(u32 ch); +#ifdef RETARGET_IS_USB +void SERIAL_USBDClass_Request(USBDCore_Device_TypeDef *pDev); +void SERIAL_USBDClass_RXHandler(USBD_EPTn_Enum EPTn); +void SERIAL_USBDClass_TXHandler(USBD_EPTn_Enum EPTn); +void SERIAL_USBDInit(void); +void SERIAL_Flush(void); +#else +#define SERIAL_Flush(...) +#endif +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32_time.h b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32_time.h new file mode 100644 index 0000000000..51aeba2c3e --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32_time.h @@ -0,0 +1,170 @@ +/*********************************************************************************************************//** + * @file ht32_time.h + * @version $Rev:: 6751 $ + * @date $Date:: 2023-03-02 #$ + * @brief The header file of time function. + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ +/* Define to prevent recursive inclusion -------------------------------------------------------------------*/ +#ifndef __HT32_TIME_H +#define __HT32_TIME_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------------------------------------*/ +#include "ht32.h" +#ifndef HTCFG_TIME_IPSEL +#include "ht32_time_conf.h" +#endif + +/* Settings ------------------------------------------------------------------------------------------------*/ +#ifdef HTCFG_TIME_IPSEL +#if (HTCFG_TIME_IPSEL == 0) +#define HTCFG_TIME_IPN BFTM0 +#endif +#if (HTCFG_TIME_IPSEL == 1) +#define HTCFG_TIME_IPN BFTM1 +#endif +#if (HTCFG_TIME_IPSEL == 2) +#define HTCFG_TIME_IPN SCTM0 +#endif +#if (HTCFG_TIME_IPSEL == 3) +#define HTCFG_TIME_IPN SCTM1 +#endif +#if (HTCFG_TIME_IPSEL == 4) +#define HTCFG_TIME_IPN SCTM2 +#endif +#if (HTCFG_TIME_IPSEL == 5) +#define HTCFG_TIME_IPN SCTM3 +#endif +#if (HTCFG_TIME_IPSEL == 6) +#define HTCFG_TIME_IPN PWM0 +#endif +#if (HTCFG_TIME_IPSEL == 7) +#define HTCFG_TIME_IPN PWM1 +#endif +#if (HTCFG_TIME_IPSEL == 8) +#define HTCFG_TIME_IPN PWM2 +#endif +#if (HTCFG_TIME_IPSEL == 9) +#define HTCFG_TIME_IPN GPTM0 +#endif +#if (HTCFG_TIME_IPSEL == 10) +#define HTCFG_TIME_IPN GPTM1 +#endif +#if (HTCFG_TIME_IPSEL == 11) +#define HTCFG_TIME_IPN MCTM0 +#endif +#endif + +/* Exported constants --------------------------------------------------------------------------------------*/ +#ifndef IS_IPN_BFTM +#undef IPN_MCTM0 +#undef IPN_MCTM1 +#undef IPN_GPTM0 +#undef IPN_GPTM1 + +#define IPN_NULL (0) +#define IPN_MCTM0 (0x4002C000) +#define IPN_MCTM1 (0x4002D000) +#define IPN_GPTM0 (0x4006E000) +#define IPN_GPTM1 (0x4006F000) +#define IPN_SCTM0 (0x40034000) +#define IPN_SCTM1 (0x40074000) +#define IPN_SCTM2 (0x40035000) +#define IPN_SCTM3 (0x40075000) +#define IPN_PWM0 (0x40031000) +#define IPN_PWM1 (0x40071000) +#define IPN_PWM2 (0x40031000) +#define IPN_BFTM0 (0x40076000) +#define IPN_BFTM1 (0x40077000) +#define IPN_CHECK(IP) STRCAT2(IPN_, IP) +#define IS_IPN_BFTM(IP) (IPN_CHECK(IP) == IPN_BFTM0) || (IPN_CHECK(IP) == IPN_BFTM1) +#define IS_IPN_MCTM(IP) (IPN_CHECK(IP) == IPN_MCTM0) || (IPN_CHECK(IP) == IPN_MCTM1) +#define IS_IPN_GPTM(IP) (IPN_CHECK(IP) == IPN_GPTM0) || (IPN_CHECK(IP) == IPN_GPTM1) +#define IS_IPN_SCTM(IP) (IPN_CHECK(IP) == IPN_SCTM0) || (IPN_CHECK(IP) == IPN_SCTM1) || (IPN_CHECK(IP) == IPN_SCTM2) || (IPN_CHECK(IP) == IPN_SCTM3) +#define IS_IPN_PWM(IP) (IPN_CHECK(IP) == IPN_PWM0) || (IPN_CHECK(IP) == IPN_PWM1) || (IPN_CHECK(IP) == IPN_PWM2) +#define IS_IPN_TM(IP) (IS_IPN_MCTM(IP) || IS_IPN_GPTM(IP) || IS_IPN_SCTM(IP) || IS_IPN_PWM(IP)) +#endif + +#define _HTCFG_TIME_PORT STRCAT2(HT_, HTCFG_TIME_IPN) + +#if (HTCFG_TIME_CLKSEL == 0) +#define _HTCFG_TIME_CORECLK (LIBCFG_MAX_SPEED) +#else +#define _HTCFG_TIME_CORECLK (HTCFG_TIME_CLK_MANUAL) +#endif + +#if (LIBCFG_CKCU_NO_APB_PRESCALER == 1) +#undef HTCFG_TIME_PCLK_DIV +#define HTCFG_TIME_PCLK_DIV (0) +#endif + +#define HTCFG_TIME_CLKSRC (_HTCFG_TIME_CORECLK >> HTCFG_TIME_PCLK_DIV) + +#if (IS_IPN_BFTM(HTCFG_TIME_IPN)) +#undef HTCFG_TIME_TICKHZ +#define HTCFG_TIME_TICKHZ HTCFG_TIME_CLKSRC +#endif + +/* Exported macro ------------------------------------------------------------------------------------------*/ +#define TIME_TICKDIFF(start, current) ((current >= start) ? (u32)(current - start) : (u32)(0xFFFFFFFF - start + 1 + current)) + +#if (HTCFG_TIME_TICKHZ < 1000000) +#define TIME_US2TICK(us) (us / (1000000UL / HTCFG_TIME_TICKHZ)) +#define TIME_TICK2US(t) (t * (1000000UL / HTCFG_TIME_TICKHZ)) +#else +#define TIME_US2TICK(us) (us * (HTCFG_TIME_TICKHZ / 1000000UL)) +#define TIME_TICK2US(t) (t / (HTCFG_TIME_TICKHZ / 1000000UL)) +#endif + +#if (HTCFG_TIME_TICKHZ < 1000) +#define TIME_MS2TICK(ms) (ms / (1000UL / HTCFG_TIME_TICKHZ)) +#define TIME_TICK2MS(t) (t * (1000UL / HTCFG_TIME_TICKHZ)) +#else +#define TIME_MS2TICK(ms) (ms * (HTCFG_TIME_TICKHZ / 1000UL)) +#define TIME_TICK2MS(t) (t / (HTCFG_TIME_TICKHZ / 1000UL)) +#endif + +#define TIME_S2TICK(s) (s * (u32)(HTCFG_TIME_TICKHZ)) +#define TIME_TICK2S(t) (t / (HTCFG_TIME_TICKHZ)) + + +#define GET_CNT() (_HTCFG_TIME_PORT->CNTR) + +/* Exported functions --------------------------------------------------------------------------------------*/ +void Time_Init(void); +void Time_Delay(u32 delay); +u32 Time_GetTick(void); + +#if (IS_IPN_BFTM(HTCFG_TIME_IPN)) +// BFTM +#define Time_GetTick GET_CNT +#endif + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32_undef_IP.h b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32_undef_IP.h new file mode 100644 index 0000000000..fb67ddcd1f --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32_undef_IP.h @@ -0,0 +1,200 @@ +/*********************************************************************************************************//** + * @file ht32_undef_IP.h + * @version $Rev:: 7309 $ + * @date $Date:: 2023-10-18 #$ + * @brief Header file for undefined IP. + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ +/* Define to prevent recursive inclusion -------------------------------------------------------------------*/ + +#ifndef __HT32_UNDEF_IP_H +#define __HT32_UNDEF_IP_H + +#ifdef __cplusplus + extern "C" { +#endif + +#if _AES +#undef _AES +#endif + +#ifdef _ADC +#undef _ADC +#endif + +#ifdef _BFTM +#undef _BFTM +#endif + +#ifdef _CAN +#undef _CAN +#endif + +#ifdef _CKCU +#undef _CKCU +#endif + +#ifdef _CMP +#undef _CMP +#endif + +#ifdef _CRC +#undef _CRC +#endif + +#ifdef _CSIF +#undef _CSIF +#endif + +#ifdef _DAC +#undef _DAC +#endif + +#ifdef _DIV +#undef _DIV +#endif + +#ifdef _EBI +#undef _EBI +#endif + +#ifdef _EXTI +#undef _EXTI +#endif + +#ifdef _FLASH +#undef _FLASH +#endif + +#ifdef _GPIO +#undef _GPIO +#endif + +#ifdef _GPTM +#undef _GPTM +#endif + +#ifdef _I2C +#undef _I2C +#endif + +#ifdef _I2S +#undef _I2S +#endif + +#ifdef _LCD +#undef _LCD +#endif + +#ifdef _LEDC +#undef _LEDC +#endif + +#ifdef _MCTM +#undef _MCTM +#endif + +#ifdef _MIDI +#undef _MIDI +#endif + +#ifdef _OPA +#undef _OPA +#endif + +#ifdef _PDMA +#undef _PDMA +#endif + +#ifdef _PWRCU +#undef _PWRCU +#endif + +#ifdef _PWM +#undef _PWM +#endif + +#ifdef _RSTCU +#undef _RSTCU +#endif + +#ifdef _RTC +#undef _RTC +#endif + +#ifdef _SCI +#undef _SCI +#endif + +#ifdef _SCTM +#undef _SCTM +#endif + +#ifdef _SDIO +#undef _SDIO +#endif + +#ifdef _SLED +#undef _SLED +#endif + +#ifdef _SPI +#undef _SPI +#endif + +#ifdef _TKEY +#undef _TKEY +#endif + +#ifdef _USART +#undef _USART +#endif + +#ifdef _USB +#undef _USB +#endif + +#ifdef _WDT +#undef _WDT +#endif + +#ifdef _MISC +#undef _MISC +#endif + +#ifdef _SERIAL +#undef _SERIAL +#endif + +#ifdef _SWDIV +#undef _SWDIV +#endif + +#ifdef _SWRAND +#undef _SWRAND +#endif + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f0006_libcfg.h b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f0006_libcfg.h new file mode 100644 index 0000000000..ca5464f977 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f0006_libcfg.h @@ -0,0 +1,73 @@ +/*********************************************************************************************************//** + * @file ht32f0006_libcfg.h + * @version $Rev:: 6657 $ + * @date $Date:: 2023-01-16 #$ + * @brief The library configuration file. + ************************************************************************************************************* +* @attention +* +* Firmware Disclaimer Information +* +* 1. The customer hereby acknowledges and agrees that the program technical documentation, including the +* code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the +* proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and +* other intellectual property laws. +* +* 2. The customer hereby acknowledges and agrees that the program technical documentation, including the +* code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties +* other than HOLTEK and the customer. +* +* 3. The program technical documentation, including the code, is provided "as is" and for customer reference +* only. After delivery by HOLTEK, the customer shall use the program technical documentation, including +* the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including +* the warranties of merchantability, satisfactory quality and fitness for a particular purpose. +* +*

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ +/* Define to prevent recursive inclusion -------------------------------------------------------------------*/ +#ifndef __HT32F0006_LIBCFG_H +#define __HT32F0006_LIBCFG_H + +/* Settings ------------------------------------------------------------------------------------------------*/ + +#if !defined(USE_MEM_HT32F0006) +#define USE_MEM_HT32F0006 +#endif + +#define LIBCFG_MAX_SPEED (48000000) + +#define LIBCFG_FLASH_PAGESIZE (512) + +#ifdef USE_MEM_HT32F0006 + #define LIBCFG_FLASH_SIZE (LIBCFG_FLASH_PAGESIZE * 255) + #define LIBCFG_RAM_SIZE (1024 * 16) + #define LIBCFG_CHIPNAME (0x0006) +#endif + +#define LIBCFG_BFTM1 (1) +#define LIBCFG_CRC (1) +#define LIBCFG_DACDUAL16 (1) +#define LIBCFG_DIV (1) +#define LIBCFG_GPIOC (1) +#define LIBCFG_GPIOD (1) +#define LIBCFG_I2S (1) +#define LIBCFG_LSE (1) +#define LIBCFG_MIDI (1) +#define LIBCFG_PDMA (1) +#define LIBCFG_QSPI (1) +#define LIBCFG_SCTM0 (1) +#define LIBCFG_SCTM1 (1) +#define LIBCFG_SCTM2 (1) +#define LIBCFG_SCTM3 (1) +#define LIBCFG_USBD (1) + +#define LIBCFG_ADC_CH8_11 (1) +#define LIBCFG_ADC_CH12_15 (1) +#define LIBCFG_AFE0006 (1) +#define LIBCFG_FMC_BRANCHCACHE (1) +#define LIBCFG_FMC_PREFETCH (1) +#define LIBCFG_FLASH_2PAGE_PER_WPBIT (1) +#define LIBCFG_PWRCU_VDD_2V0_3V6 (1) +#define LIBCFG_PWRCU_V15_READY_SOURCE (1) + +#endif diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f0008_libcfg.h b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f0008_libcfg.h new file mode 100644 index 0000000000..a53d939bbf --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f0008_libcfg.h @@ -0,0 +1,74 @@ +/*********************************************************************************************************//** + * @file ht32f0008_libcfg.h + * @version $Rev:: 6189 $ + * @date $Date:: 2022-09-27 #$ + * @brief The library configuration file. + ************************************************************************************************************* +* @attention +* +* Firmware Disclaimer Information +* +* 1. The customer hereby acknowledges and agrees that the program technical documentation, including the +* code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the +* proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and +* other intellectual property laws. +* +* 2. The customer hereby acknowledges and agrees that the program technical documentation, including the +* code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties +* other than HOLTEK and the customer. +* +* 3. The program technical documentation, including the code, is provided "as is" and for customer reference +* only. After delivery by HOLTEK, the customer shall use the program technical documentation, including +* the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including +* the warranties of merchantability, satisfactory quality and fitness for a particular purpose. +* +*

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ +/* Define to prevent recursive inclusion -------------------------------------------------------------------*/ +#ifndef __HT32F0008_LIBCFG_H +#define __HT32F0008_LIBCFG_H + +/* Settings ------------------------------------------------------------------------------------------------*/ + +#if !defined(USE_MEM_HT32F0008) +#define USE_MEM_HT32F0008 +#endif + +#define LIBCFG_MAX_SPEED (60000000) + +#define LIBCFG_FLASH_PAGESIZE (1024) + +#ifdef USE_MEM_HT32F0008 + #define LIBCFG_FLASH_SIZE (LIBCFG_FLASH_PAGESIZE * 63) + #define LIBCFG_RAM_SIZE (1024 * 16) + #define LIBCFG_CHIPNAME (0x0008) +#endif + +#define LIBCFG_PDMA (1) + +#define LIBCFG_BFTM1 (1) + +#define LIBCFG_LSE (1) +#define LIBCFG_USBD (1) +#define LIBCFG_CRC (1) +#define LIBCFG_DIV (1) +#define LIBCFG_AES (1) + +#define LIBCFG_GPIOC (1) +#define LIBCFG_GPIOF (1) + +#define LIBCFG_NO_ADC (1) +#define LIBCFG_PWM0 (1) +#define LIBCFG_PWM1 (1) +#define LIBCFG_AFIO_PWM_MODE4 (1) +#define LIBCFG_CKCU_USB_PLL (1) +#define LIBCFG_CKCU_SYS_CK_60M (1) +#define LIBCFG_FMC_PREFETCH (1) +#define LIBCFG_FMC_WAIT_STATE_2 (1) +#define LIBCFG_CKCU_REFCLK_EXT_PIN (1) +#define LIBCFG_CKCU_ATM_V01 (1) +#define LIBCFG_CKCU_PLLSRCDIV (1) +#define LIBCFG_GPIO_DISABLE_DEBUG_PORT (1) +#define LIBCFG_AES_SWAP (1) + +#endif diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f50020_30_libcfg.h b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f50020_30_libcfg.h new file mode 100644 index 0000000000..44d05bdcc9 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f50020_30_libcfg.h @@ -0,0 +1,111 @@ +/*********************************************************************************************************//** + * @file ht32f50020_30_libcfg.h + * @version $Rev:: 6386 $ + * @date $Date:: 2022-10-27 #$ + * @brief The library configuration file. + ************************************************************************************************************* +* @attention +* +* Firmware Disclaimer Information +* +* 1. The customer hereby acknowledges and agrees that the program technical documentation, including the +* code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the +* proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and +* other intellectual property laws. +* +* 2. The customer hereby acknowledges and agrees that the program technical documentation, including the +* code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties +* other than HOLTEK and the customer. +* +* 3. The program technical documentation, including the code, is provided "as is" and for customer reference +* only. After delivery by HOLTEK, the customer shall use the program technical documentation, including +* the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including +* the warranties of merchantability, satisfactory quality and fitness for a particular purpose. +* +*

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ +/* Define to prevent recursive inclusion -------------------------------------------------------------------*/ +#ifndef __ht32f50020_30_LIBCFG_H +#define __ht32f50020_30_LIBCFG_H + +/* Settings ------------------------------------------------------------------------------------------------*/ + +#if !defined(USE_MEM_HT32F50020) && !defined(USE_MEM_HT32F50030) +#define USE_MEM_HT32F50030 +#endif + +#define LIBCFG_MAX_SPEED (16000000) + +#define LIBCFG_FLASH_PAGESIZE (1024) + +#ifdef USE_MEM_HT32F50020 + #define LIBCFG_FLASH_SIZE (LIBCFG_FLASH_PAGESIZE * 16) + #define LIBCFG_RAM_SIZE (1024 * 2) + #define LIBCFG_CHIPNAME (0x50020) +#endif + +#ifdef USE_MEM_HT32F50030 + #define LIBCFG_FLASH_SIZE (LIBCFG_FLASH_PAGESIZE * 31) + #define LIBCFG_RAM_SIZE (1024 * 2) + #define LIBCFG_CHIPNAME (0x50030) +#endif + +#define LIBCFG_GPIOC (1) +#define LIBCFG_GPIOF (1) +#define LIBCFG_LEDC (1) +#define LIBCFG_LSE (1) +#define LIBCFG_SCTM0 (1) +#define LIBCFG_SCTM1 (1) +#define LIBCFG_SCTM2 (1) +#define LIBCFG_UART1 (1) +#define LIBCFG_NO_GPTM0 (1) +#define LIBCFG_NO_USART0 (1) + +#define LIBCFG_ADC_CH8_11 (1) +#define LIBCFG_ADC_IVREF (1) +#define LIBCFG_ADC_IVREF_LEVEL_TYPE2 (1) +#define LIBCFG_ADC_MVDDA (1) +#define LIBCFG_ADC_VREFBUF (1) +#define LIBCFG_ADC_NO_DISCON_MODE (1) +#define LIBCFG_ADC_NO_SEQ_4_7 (1) +#define LIBCFG_ADC_NO_WDT (1) +#define LIBCFG_ADC_SW_TRIGGER_ONLY (1) +#define LIBCFG_AFIO_LEDC_MODE3 (1) +#define LIBCFG_AFIO_MODE_0_7 (1) +#define LIBCFG_AFIO_SCTM_MODE4 (1) +#define LIBCFG_AFIO_SYSTEM_MODE1 (1) +#define LIBCFG_BFTM_16BIT_COUNTER (1) +#define LIBCFG_CKCU_NO_APB_PRESCALER (1) +#define LIBCFG_CKCU_NO_AUTO_TRIM (1) +#define LIBCFG_CKCU_NO_LPCR (1) +#define LIBCFG_EXTI_8BIT_DEBOUNCE_COUNTER (1) +#define LIBCFG_EXTI_8CH (1) +#define LIBCFG_EXTI_DEBCNTPRE (1) +#define LIBCFG_GPIO_PR_STRONG_UP (1) +#define LIBCFG_I2C_PRESCALER_2BIT (1) +#define LIBCFG_I2C_TOUT_COUNT_8BIT (1) +#define LIBCFG_I2C_TWO_DEV_ADDR (1) +#define LIBCFG_I2C_NO_10BIT_MODE (1) +#define LIBCFG_I2C_NO_ADDR_MASK (1) +#define LIBCFG_I2C_NO_ARBLOS (1) +#define LIBCFG_LEDC_NO_COM_8_11 (1) +#define LIBCFG_NO_PLL (1) +#define LIBCFG_NO_PWRCU_TEST_REG (1) +#define LIBCFG_PWRCU_PORF (1) +#define LIBCFG_PWRCU_VDD_5V (1) +#define LIBCFG_PWRCU_WAKEUP_V01 (1) +#define LIBCFG_PWRCU_WAKEUP1 (1) +#define LIBCFG_PWRCU_NO_VDDPORF (1) +#define LIBCFG_PWRCU_NO_PD_MODE (1) +#define LIBCFG_PWRCU_NO_PDF (1) +#define LIBCFG_SPI_CLK_PRE_V01 (1) +#define LIBCFG_SPI_DATA_LENGTH_V01 (1) +#define LIBCFG_SPI_FIFO_DEPTH_V01 (1) +#define LIBCFG_SPI_NO_DUAL (1) +#define LIBCFG_SPI_NO_MULTI_MASTER (1) +#define LIBCFG_SPI_TIMEOUT_LENGTH_V01 (1) +#define LIBCFG_TM_CKDIV_8 (1) +#define LIBCFG_TM_PRESCALER_8BIT (1) +#define LIBCFG_TM_SCTM_2CHANNEL (1) + +#endif diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f50220_30_libcfg.h b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f50220_30_libcfg.h new file mode 100644 index 0000000000..3624e76b7b --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f50220_30_libcfg.h @@ -0,0 +1,75 @@ +/*********************************************************************************************************//** + * @file ht32f50220_30_libcfg.h + * @version $Rev:: 6386 $ + * @date $Date:: 2022-10-27 #$ + * @brief The library configuration file. + ************************************************************************************************************* +* @attention +* +* Firmware Disclaimer Information +* +* 1. The customer hereby acknowledges and agrees that the program technical documentation, including the +* code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the +* proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and +* other intellectual property laws. +* +* 2. The customer hereby acknowledges and agrees that the program technical documentation, including the +* code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties +* other than HOLTEK and the customer. +* +* 3. The program technical documentation, including the code, is provided "as is" and for customer reference +* only. After delivery by HOLTEK, the customer shall use the program technical documentation, including +* the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including +* the warranties of merchantability, satisfactory quality and fitness for a particular purpose. +* +*

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ +/* Define to prevent recursive inclusion -------------------------------------------------------------------*/ +#ifndef __HT32F50220_30_LIBCFG_H +#define __HT32F50220_30_LIBCFG_H + +/* Settings ------------------------------------------------------------------------------------------------*/ + +#if !defined(USE_MEM_HT32F50220) && !defined(USE_MEM_HT32F50230) +#define USE_MEM_HT32F50230 +#endif + +#define LIBCFG_MAX_SPEED (20000000) + +#define LIBCFG_FLASH_PAGESIZE (1024) + +#ifdef USE_MEM_HT32F50220 + #define LIBCFG_FLASH_SIZE (LIBCFG_FLASH_PAGESIZE * 16) + #define LIBCFG_RAM_SIZE (1024 * 4) + #define LIBCFG_CHIPNAME (0x50220) +#endif + +#ifdef USE_MEM_HT32F50230 + #define LIBCFG_FLASH_SIZE (LIBCFG_FLASH_PAGESIZE * 31) + #define LIBCFG_RAM_SIZE (1024 * 4) + #define LIBCFG_CHIPNAME (0x50230) +#endif + +#define LIBCFG_ADC_CH8_11 (1) +#define LIBCFG_LSE (1) +#define LIBCFG_SPI1 (1) +#define LIBCFG_PWM0 (1) +#define LIBCFG_PWM1 (1) +#define LIBCFG_DIV (1) +#define LIBCFG_UART1 (1) +#define LIBCFG_GPIOC (1) +#define LIBCFG_GPIO_SINK_CURRENT_ENHANCED (1) +#define LIBCFG_PWRCU_VDD_5V (1) +#define LIBCFG_PWRCU_WAKEUP_V01 (1) +#define LIBCFG_PWRCU_WAKEUP1 (1) +#define LIBCFG_PWRCU_PORF (1) +#define LIBCFG_CKCU_ATM_V01 (1) +#define LIBCFG_NO_PLL (1) +#define LIBCFG_NO_USART0 (1) +#define LIBCFG_FMC_CMD_READY_WAIT (1) +#define LIBCFG_NO_PWRCU_TEST_REG (1) +#define LIBCFG_PWRCU_NO_PD_MODE (1) +#define LIBCFG_PWRCU_NO_PDF (1) +#define LIBCFG_PWRCU_NO_VDDPORF (1) + +#endif diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f50231_41_libcfg.h b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f50231_41_libcfg.h new file mode 100644 index 0000000000..b7e24634f7 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f50231_41_libcfg.h @@ -0,0 +1,79 @@ +/*********************************************************************************************************//** + * @file ht32f50231_41_libcfg.h + * @version $Rev:: 6386 $ + * @date $Date:: 2022-10-27 #$ + * @brief The library configuration file. + ************************************************************************************************************* +* @attention +* +* Firmware Disclaimer Information +* +* 1. The customer hereby acknowledges and agrees that the program technical documentation, including the +* code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the +* proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and +* other intellectual property laws. +* +* 2. The customer hereby acknowledges and agrees that the program technical documentation, including the +* code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties +* other than HOLTEK and the customer. +* +* 3. The program technical documentation, including the code, is provided "as is" and for customer reference +* only. After delivery by HOLTEK, the customer shall use the program technical documentation, including +* the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including +* the warranties of merchantability, satisfactory quality and fitness for a particular purpose. +* +*

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ +/* Define to prevent recursive inclusion -------------------------------------------------------------------*/ +#ifndef __HT32F50231_41_LIBCFG_H +#define __HT32F50231_41_LIBCFG_H + +/* Settings ------------------------------------------------------------------------------------------------*/ + +#if !defined(USE_MEM_HT32F50231) && !defined(USE_MEM_HT32F50241) +#define USE_MEM_HT32F50241 +#endif + +#define LIBCFG_MAX_SPEED (20000000) + +#define LIBCFG_FLASH_PAGESIZE (1024) + +#ifdef USE_MEM_HT32F50231 + #define LIBCFG_FLASH_SIZE (LIBCFG_FLASH_PAGESIZE * 32) + #define LIBCFG_RAM_SIZE (1024 * 4) + #define LIBCFG_CHIPNAME (0x50231) +#endif + +#ifdef USE_MEM_HT32F50241 + #define LIBCFG_FLASH_SIZE (LIBCFG_FLASH_PAGESIZE * 63) + #define LIBCFG_RAM_SIZE (1024 * 8) + #define LIBCFG_CHIPNAME (0x50241) +#endif + +#define LIBCFG_ADC_CH8_11 (1) +#define LIBCFG_LSE (1) +#define LIBCFG_SPI1 (1) +#define LIBCFG_PWM0 (1) +#define LIBCFG_PWM1 (1) +#define LIBCFG_DIV (1) +#define LIBCFG_UART1 (1) +#define LIBCFG_GPIOC (1) +#define LIBCFG_GPIO_SINK_CURRENT_ENHANCED (1) +#define LIBCFG_PWRCU_VDD_5V (1) +#define LIBCFG_MCTM0 (1) +#define LIBCFG_PWRCU_WAKEUP_V01 (1) +#define LIBCFG_PWRCU_WAKEUP1 (1) +#define LIBCFG_PWRCU_PORF (1) +#define LIBCFG_CKCU_ATM_V01 (1) +#define LIBCFG_CRC (1) +#define LIBCFG_BFTM1 (1) +#define LIBCFG_MCTM0 (1) +#define LIBCFG_I2C1 (1) +#define LIBCFG_NO_PLL (1) +#define LIBCFG_FMC_CMD_READY_WAIT (1) +#define LIBCFG_NO_PWRCU_TEST_REG (1) +#define LIBCFG_PWRCU_NO_PD_MODE (1) +#define LIBCFG_PWRCU_NO_PDF (1) +#define LIBCFG_PWRCU_NO_VDDPORF (1) + +#endif diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f50343_libcfg.h b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f50343_libcfg.h new file mode 100644 index 0000000000..2e13c2bea0 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f50343_libcfg.h @@ -0,0 +1,87 @@ +/*********************************************************************************************************//** + * @file ht32f50343_libcfg.h + * @version $Rev:: 6386 $ + * @date $Date:: 2022-10-27 #$ + * @brief The library configuration file. + ************************************************************************************************************* +* @attention +* +* Firmware Disclaimer Information +* +* 1. The customer hereby acknowledges and agrees that the program technical documentation, including the +* code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the +* proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and +* other intellectual property laws. +* +* 2. The customer hereby acknowledges and agrees that the program technical documentation, including the +* code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties +* other than HOLTEK and the customer. +* +* 3. The program technical documentation, including the code, is provided "as is" and for customer reference +* only. After delivery by HOLTEK, the customer shall use the program technical documentation, including +* the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including +* the warranties of merchantability, satisfactory quality and fitness for a particular purpose. +* +*

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ +/* Define to prevent recursive inclusion -------------------------------------------------------------------*/ +#ifndef __HT32F50343_LIBCFG_H +#define __HT32F50343_LIBCFG_H + +/* Settings ------------------------------------------------------------------------------------------------*/ + +#if !defined(USE_MEM_HT32F50343) +#define USE_MEM_HT32F50343 +#endif + +#define LIBCFG_MAX_SPEED (60000000) + +#define LIBCFG_FLASH_PAGESIZE (1024) + +#ifdef USE_MEM_HT32F50343 + #define LIBCFG_FLASH_SIZE (LIBCFG_FLASH_PAGESIZE * 63) + #define LIBCFG_RAM_SIZE (1024 * 12) + #define LIBCFG_CHIPNAME (0x50343) +#endif + +#define LIBCFG_ADC_CH8_11 (1) +#define LIBCFG_ADC_MVDDA (1) +#define LIBCFG_BFTM1 (1) +#define LIBCFG_CKCU_ATM_V01 (1) +#define LIBCFG_CKCU_PLLSRCDIV (1) +#define LIBCFG_CKCU_REFCLK_EXT_PIN (1) +#define LIBCFG_CKCU_SYS_CK_60M (1) +#define LIBCFG_CKCU_USB_PLL (1) +#define LIBCFG_CRC (1) +#define LIBCFG_DIV (1) +#define LIBCFG_FMC_PREFETCH (1) +#define LIBCFG_FMC_WAIT_STATE_2 (1) +#define LIBCFG_GPIOC (1) +#define LIBCFG_GPIOD (1) +#define LIBCFG_I2C1 (1) +#define LIBCFG_LSE (1) +#define LIBCFG_NO_PWRCU_TEST_REG (1) +#define LIBCFG_NO_USART0 (1) +#define LIBCFG_PDMA (1) +#define LIBCFG_PWRCU_NO_PD_MODE (1) +#define LIBCFG_PWRCU_NO_PDF (1) +#define LIBCFG_PWRCU_NO_VDDPORF (1) +#define LIBCFG_PWRCU_WAKEUP_V01 (1) +#define LIBCFG_PWRCU_WAKEUP1 (1) +#define LIBCFG_PWRCU_PORF (1) +#define LIBCFG_PWRCU_VREG (1) +#define LIBCFG_SCTM0 (1) +#define LIBCFG_SCTM1 (1) +#define LIBCFG_PWM0 (1) +#define LIBCFG_PWM1 (1) +#define LIBCFG_PWM2 (1) +#define LIBCFG_PWM_8_CHANNEL (1) +#define LIBCFG_SLED0 (1) +#define LIBCFG_SLED1 (1) +#define LIBCFG_SPI1 (1) +#define LIBCFG_PWRCU_VDD_5V (1) +#define LIBCFG_UART1 (1) +#define LIBCFG_USBD (1) + + +#endif diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f50431_41_libcfg.h b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f50431_41_libcfg.h new file mode 100644 index 0000000000..9c3bb3bb39 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f50431_41_libcfg.h @@ -0,0 +1,95 @@ +/*********************************************************************************************************//** + * @file ht32f50431_41_libcfg.h + * @version $Rev:: 7265 $ + * @date $Date:: 2023-10-02 #$ + * @brief The library configuration file. + ************************************************************************************************************* +* @attention +* +* Firmware Disclaimer Information +* +* 1. The customer hereby acknowledges and agrees that the program technical documentation, including the +* code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the +* proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and +* other intellectual property laws. +* +* 2. The customer hereby acknowledges and agrees that the program technical documentation, including the +* code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties +* other than HOLTEK and the customer. +* +* 3. The program technical documentation, including the code, is provided "as is" and for customer reference +* only. After delivery by HOLTEK, the customer shall use the program technical documentation, including +* the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including +* the warranties of merchantability, satisfactory quality and fitness for a particular purpose. +* +*

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ +/* Define to prevent recursive inclusion -------------------------------------------------------------------*/ +#ifndef __HT32F50431_41_LIBCFG_H +#define __HT32F50431_41_LIBCFG_H + +/* Settings ------------------------------------------------------------------------------------------------*/ + +#if !defined(USE_MEM_HT32F50431) && !defined(USE_MEM_HT32F50441) +#define USE_MEM_HT32F50441 +#endif + +#define LIBCFG_MAX_SPEED (60000000) + +#define LIBCFG_FLASH_PAGESIZE (1024) + +#ifdef USE_MEM_HT32F50431 + #define LIBCFG_FLASH_SIZE (LIBCFG_FLASH_PAGESIZE * 32) + #define LIBCFG_RAM_SIZE (1024 * 4) + #define LIBCFG_CHIPNAME (0x50431) +#endif + +#ifdef USE_MEM_HT32F50441 + #define LIBCFG_FLASH_SIZE (LIBCFG_FLASH_PAGESIZE * 63) + #define LIBCFG_RAM_SIZE (1024 * 8) + #define LIBCFG_CHIPNAME (0x50441) +#endif + +#define LIBCFG_PDMA (1) +#define LIBCFG_ADC_CH8_11 (1) + +#define LIBCFG_BFTM1 (1) +#define LIBCFG_MCTM0 (1) +#define LIBCFG_PWM0 (1) + +#define LIBCFG_LSE (1) +#define LIBCFG_LEDC (1) +#define LIBCFG_CRC (1) +#define LIBCFG_DIV (1) + +#define LIBCFG_UART1 (1) +#define LIBCFG_SPI1 (1) +#define LIBCFG_I2C1 (1) + +#define LIBCFG_GPIOC (1) +#define LIBCFG_GPIOD (1) + +#define LIBCFG_FMC_WAIT_STATE_2 (1) +#define LIBCFG_FMC_PREFETCH (1) +#define LIBCFG_CKCU_PLLSRCDIV (1) +#define LIBCFG_CKCU_AUTO_TRIM_LEGACY (1) +#define LIBCFG_CKCU_ATM_V01 (1) +#define LIBCFG_CKCU_SYS_CK_60M (1) +#define LIBCFG_CKCU_REFCLK_EXT_PIN (1) +#define LIBCFG_PWRCU_VDD_5V (1) +#define LIBCFG_PWRCU_WAKEUP1 (1) +#define LIBCFG_PWRCU_WAKEUP_V01 (1) +#define LIBCFG_PWRCU_NO_VDDPORF (1) +#define LIBCFG_PWRCU_NO_PDF (1) +#define LIBCFG_PWRCU_PORF (1) +#define LIBCFG_PWRCU_NO_PD_MODE (1) +#define LIBCFG_NO_PWRCU_TEST_REG (1) +#define LIBCFG_LEDC_NO_COM_8_11 (1) +#define LIBCFG_ADC_IVREF (1) +#define LIBCFG_ADC_IVREF_LEVEL_TYPE2 (1) +#define LIBCFG_ADC_MVDDA (1) +#define LIBCFG_USART_LIN (1) +#define LIBCFG_USART_SINGLE_WIRE (1) +#define LIBCFG_GPIO_SINK_CURREMT_ENHANCED (1) + +#endif diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f50442_52_libcfg.h b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f50442_52_libcfg.h new file mode 100644 index 0000000000..6a3cff8ab6 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f50442_52_libcfg.h @@ -0,0 +1,99 @@ +/*********************************************************************************************************//** + * @file ht32f50442_52_libcfg.h + * @version $Rev:: 7265 $ + * @date $Date:: 2023-10-02 #$ + * @brief The library configuration file. + ************************************************************************************************************* +* @attention +* +* Firmware Disclaimer Information +* +* 1. The customer hereby acknowledges and agrees that the program technical documentation, including the +* code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the +* proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and +* other intellectual property laws. +* +* 2. The customer hereby acknowledges and agrees that the program technical documentation, including the +* code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties +* other than HOLTEK and the customer. +* +* 3. The program technical documentation, including the code, is provided "as is" and for customer reference +* only. After delivery by HOLTEK, the customer shall use the program technical documentation, including +* the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including +* the warranties of merchantability, satisfactory quality and fitness for a particular purpose. +* +*

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ +/* Define to prevent recursive inclusion -------------------------------------------------------------------*/ +#ifndef __HT32F50442_52_LIBCFG_H +#define __HT32F50442_52_LIBCFG_H + +/* Settings ------------------------------------------------------------------------------------------------*/ + +#if !defined(USE_MEM_HT32F50442) && !defined(USE_MEM_HT32F50452) +#define USE_MEM_HT32F50452 +#endif + +#define LIBCFG_MAX_SPEED (60000000) + +#define LIBCFG_FLASH_PAGESIZE (1024) + +#ifdef USE_MEM_HT32F50442 + #define LIBCFG_FLASH_SIZE (LIBCFG_FLASH_PAGESIZE * 64) + #define LIBCFG_RAM_SIZE (1024 * 8) + #define LIBCFG_CHIPNAME (0x50442) +#endif + +#ifdef USE_MEM_HT32F50452 + #define LIBCFG_FLASH_SIZE (LIBCFG_FLASH_PAGESIZE * 127) + #define LIBCFG_RAM_SIZE (1024 * 16) + #define LIBCFG_CHIPNAME (0x50452) +#endif + +#define LIBCFG_PDMA (1) +#define LIBCFG_ADC_CH8_11 (1) +#define LIBCFG_CMP (1) + +#define LIBCFG_BFTM1 (1) +#define LIBCFG_MCTM0 (1) +#define LIBCFG_PWM0 (1) +#define LIBCFG_PWM1 (1) + +#define LIBCFG_LSE (1) +#define LIBCFG_EBI (1) +#define LIBCFG_LEDC (1) +#define LIBCFG_CRC (1) +#define LIBCFG_DIV (1) + +#define LIBCFG_USART1 (1) +#define LIBCFG_UART1 (1) +#define LIBCFG_SPI1 (1) +#define LIBCFG_I2C1 (1) + +#define LIBCFG_GPIOC (1) +#define LIBCFG_GPIOD (1) + +#define LIBCFG_FMC_WAIT_STATE_2 (1) +#define LIBCFG_FMC_PREFETCH (1) +#define LIBCFG_CKCU_PLLSRCDIV (1) +#define LIBCFG_CKCU_AUTO_TRIM_LEGACY (1) +#define LIBCFG_CKCU_ATM_V01 (1) +#define LIBCFG_CKCU_SYS_CK_60M (1) +#define LIBCFG_CKCU_REFCLK_EXT_PIN (1) +#define LIBCFG_PWRCU_VDD_5V (1) +#define LIBCFG_PWRCU_WAKEUP1 (1) +#define LIBCFG_PWRCU_WAKEUP_V01 (1) +#define LIBCFG_PWRCU_NO_VDDPORF (1) +#define LIBCFG_PWRCU_NO_PDF (1) +#define LIBCFG_PWRCU_PORF (1) +#define LIBCFG_PWRCU_NO_PD_MODE (1) +#define LIBCFG_NO_PWRCU_TEST_REG (1) +#define LIBCFG_LEDC_NO_COM_8_11 (1) +#define LIBCFG_ADC_IVREF (1) +#define LIBCFG_ADC_IVREF_LEVEL_TYPE2 (1) +#define LIBCFG_ADC_MVDDA (1) +#define LIBCFG_USART_LIN (1) +#define LIBCFG_USART_SINGLE_WIRE (1) +#define LIBCFG_GPIO_SINK_CURREMT_ENHANCED (1) + +#endif diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f52220_30_libcfg.h b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f52220_30_libcfg.h new file mode 100644 index 0000000000..1804c38460 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f52220_30_libcfg.h @@ -0,0 +1,61 @@ +/*********************************************************************************************************//** + * @file ht32f52220_30_libcfg.h + * @version $Rev:: 6189 $ + * @date $Date:: 2022-09-27 #$ + * @brief The library configuration file. + ************************************************************************************************************* +* @attention +* +* Firmware Disclaimer Information +* +* 1. The customer hereby acknowledges and agrees that the program technical documentation, including the +* code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the +* proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and +* other intellectual property laws. +* +* 2. The customer hereby acknowledges and agrees that the program technical documentation, including the +* code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties +* other than HOLTEK and the customer. +* +* 3. The program technical documentation, including the code, is provided "as is" and for customer reference +* only. After delivery by HOLTEK, the customer shall use the program technical documentation, including +* the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including +* the warranties of merchantability, satisfactory quality and fitness for a particular purpose. +* +*

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ +/* Define to prevent recursive inclusion -------------------------------------------------------------------*/ +#ifndef __HT32F52220_30_LIBCFG_H +#define __HT32F52220_30_LIBCFG_H + +/* Settings ------------------------------------------------------------------------------------------------*/ + +#if !defined(USE_MEM_HT32F52220) && !defined(USE_MEM_HT32F52230) +#define USE_MEM_HT32F52230 +#endif + +#define LIBCFG_MAX_SPEED (40000000) + +#define LIBCFG_FLASH_PAGESIZE (1024) + +#ifdef USE_MEM_HT32F52220 + #define LIBCFG_FLASH_SIZE (LIBCFG_FLASH_PAGESIZE * 16) + #define LIBCFG_RAM_SIZE (1024 * 4) + #define LIBCFG_CHIPNAME (0x52220) +#endif + +#ifdef USE_MEM_HT32F52230 + #define LIBCFG_FLASH_SIZE (LIBCFG_FLASH_PAGESIZE * 31) + #define LIBCFG_RAM_SIZE (1024 * 4) + #define LIBCFG_CHIPNAME (0x52230) +#endif + +#define LIBCFG_SCTM0 (1) +#define LIBCFG_SCTM1 (1) + +#define LIBCFG_GPIO_DISABLE_DEBUG_PORT (1) +#define LIBCFG_FMC_PREFETCH (1) +#define LIBCFG_PWRCU_VDD_2V0_3V6 (1) +#define LIBCFG_PWRCU_V15_READY_SOURCE (1) + +#endif diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f52231_41_libcfg.h b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f52231_41_libcfg.h new file mode 100644 index 0000000000..071c8ab1dc --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f52231_41_libcfg.h @@ -0,0 +1,76 @@ +/*********************************************************************************************************//** + * @file ht32f52231_41_libcfg.h + * @version $Rev:: 6189 $ + * @date $Date:: 2022-09-27 #$ + * @brief The library configuration file. + ************************************************************************************************************* +* @attention +* +* Firmware Disclaimer Information +* +* 1. The customer hereby acknowledges and agrees that the program technical documentation, including the +* code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the +* proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and +* other intellectual property laws. +* +* 2. The customer hereby acknowledges and agrees that the program technical documentation, including the +* code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties +* other than HOLTEK and the customer. +* +* 3. The program technical documentation, including the code, is provided "as is" and for customer reference +* only. After delivery by HOLTEK, the customer shall use the program technical documentation, including +* the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including +* the warranties of merchantability, satisfactory quality and fitness for a particular purpose. +* +*

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ +/* Define to prevent recursive inclusion -------------------------------------------------------------------*/ +#ifndef __HT32F52231_41_LIBCFG_H +#define __HT32F52231_41_LIBCFG_H + +/* Settings ------------------------------------------------------------------------------------------------*/ + +#if !defined(USE_MEM_HT32F52231) && !defined(USE_MEM_HT32F52241) +#define USE_MEM_HT32F52241 +#endif + +#define LIBCFG_MAX_SPEED (40000000) + +#define LIBCFG_FLASH_PAGESIZE (1024) + +#ifdef USE_MEM_HT32F52231 + #define LIBCFG_FLASH_SIZE (LIBCFG_FLASH_PAGESIZE * 32) + #define LIBCFG_RAM_SIZE (1024 * 4) + #define LIBCFG_CHIPNAME (0x52231) +#endif + +#ifdef USE_MEM_HT32F52241 + #define LIBCFG_FLASH_SIZE (LIBCFG_FLASH_PAGESIZE * 63) + #define LIBCFG_RAM_SIZE (1024 * 8) + #define LIBCFG_CHIPNAME (0x52241) +#endif + +#define LIBCFG_ADC_CH8_11 (1) + +#define LIBCFG_BFTM1 (1) +#define LIBCFG_SCTM0 (1) +#define LIBCFG_SCTM1 (1) +#define LIBCFG_SCTM2 (1) +#define LIBCFG_SCTM3 (1) +#define LIBCFG_MCTM0 (1) + +#define LIBCFG_LSE (1) +#define LIBCFG_CRC (1) + +#define LIBCFG_UART1 (1) +#define LIBCFG_SPI1 (1) +#define LIBCFG_I2C1 (1) + +#define LIBCFG_GPIOC (1) +#define LIBCFG_GPIO_DISABLE_DEBUG_PORT (1) +#define LIBCFG_CKCU_AUTO_TRIM_LEGACY (1) +#define LIBCFG_FMC_PREFETCH (1) +#define LIBCFG_PWRCU_VDD_2V0_3V6 (1) +#define LIBCFG_PWRCU_V15_READY_SOURCE (1) + +#endif diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f52234_44_libcfg.h b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f52234_44_libcfg.h new file mode 100644 index 0000000000..1ac83f1323 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f52234_44_libcfg.h @@ -0,0 +1,83 @@ +/*********************************************************************************************************//** + * @file ht32f52234_44_libcfg.h + * @version $Rev:: 7265 $ + * @date $Date:: 2023-10-02 #$ + * @brief The library configuration file. + ************************************************************************************************************* +* @attention +* +* Firmware Disclaimer Information +* +* 1. The customer hereby acknowledges and agrees that the program technical documentation, including the +* code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the +* proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and +* other intellectual property laws. +* +* 2. The customer hereby acknowledges and agrees that the program technical documentation, including the +* code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties +* other than HOLTEK and the customer. +* +* 3. The program technical documentation, including the code, is provided "as is" and for customer reference +* only. After delivery by HOLTEK, the customer shall use the program technical documentation, including +* the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including +* the warranties of merchantability, satisfactory quality and fitness for a particular purpose. +* +*

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ +/* Define to prevent recursive inclusion -------------------------------------------------------------------*/ +#ifndef __HT32F52234_44_LIBCFG_H +#define __HT32F52234_44_LIBCFG_H + +/* Settings ------------------------------------------------------------------------------------------------*/ + +#if !defined(USE_MEM_HT32F52234) && !defined(USE_MEM_HT32F52244) +#define USE_MEM_HT32F52244 +#endif + +#define LIBCFG_MAX_SPEED (60000000) + +#define LIBCFG_FLASH_PAGESIZE (1024) + +#ifdef USE_MEM_HT32F52234 + #define LIBCFG_FLASH_SIZE (LIBCFG_FLASH_PAGESIZE * 32) + #define LIBCFG_RAM_SIZE (1024 * 4) + #define LIBCFG_CHIPNAME (0x52234) +#endif + +#ifdef USE_MEM_HT32F52244 + #define LIBCFG_FLASH_SIZE (LIBCFG_FLASH_PAGESIZE * 63) + #define LIBCFG_RAM_SIZE (1024 * 8) + #define LIBCFG_CHIPNAME (0x52244) +#endif + +#define LIBCFG_CRC (1) +#define LIBCFG_DIV (1) +#define LIBCFG_PDMA (1) +#define LIBCFG_ADC_IVREF (1) +#define LIBCFG_ADC_IVREF_DEFAULT_08V (1) +#define LIBCFG_ADC_MVDDA (1) +#define LIBCFG_ADC_CH8_11 (1) +#define LIBCFG_FMC_PREFETCH (1) +#define LIBCFG_FMC_WAIT_STATE_2 (1) +#define LIBCFG_BFTM1 (1) +#define LIBCFG_LSE (1) +#define LIBCFG_PWM0 (1) +#define LIBCFG_I2C1 (1) +#define LIBCFG_I2C2 (1) +#define LIBCFG_CKCU_ATM_V01 (1) +#define LIBCFG_NO_GPTM0 (1) +#define LIBCFG_SCTM0 (1) +#define LIBCFG_SCTM1 (1) +#define LIBCFG_PWM0 (1) +#define LIBCFG_CKCU_PLLSRCDIV (1) +#define LIBCFG_CKCU_SYS_CK_60M (1) +#define LIBCFG_CKCU_HSIRDYCR (1) +#define LIBCFG_CKCU_REFCLK_EXT_PIN (1) +#define LIBCFG_DAC0 (1) +#define LIBCFG_DAC1 (1) +#define LIBCFG_GPIOC (1) +#define LIBCFG_USART_LIN (1) +#define LIBCFG_USART_SINGLE_WIRE (1) +#define LIBCFG_AFIO_DAC_MODE3 (1) + +#endif diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f52243_53_libcfg.h b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f52243_53_libcfg.h new file mode 100644 index 0000000000..38f4675048 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f52243_53_libcfg.h @@ -0,0 +1,84 @@ +/*********************************************************************************************************//** + * @file ht32f52243_53_libcfg.h + * @version $Rev:: 6189 $ + * @date $Date:: 2022-09-27 #$ + * @brief The library configuration file. + ************************************************************************************************************* +* @attention +* +* Firmware Disclaimer Information +* +* 1. The customer hereby acknowledges and agrees that the program technical documentation, including the +* code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the +* proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and +* other intellectual property laws. +* +* 2. The customer hereby acknowledges and agrees that the program technical documentation, including the +* code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties +* other than HOLTEK and the customer. +* +* 3. The program technical documentation, including the code, is provided "as is" and for customer reference +* only. After delivery by HOLTEK, the customer shall use the program technical documentation, including +* the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including +* the warranties of merchantability, satisfactory quality and fitness for a particular purpose. +* +*

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ +/* Define to prevent recursive inclusion -------------------------------------------------------------------*/ +#ifndef __HT32F52243_53_LIBCFG_H +#define __HT32F52243_53_LIBCFG_H + +/* Settings ------------------------------------------------------------------------------------------------*/ + +#if !defined(USE_MEM_HT32F52243) && !defined(USE_MEM_HT32F52253) +#define USE_MEM_HT32F52253 +#endif + +#define LIBCFG_MAX_SPEED (40000000) + +#define LIBCFG_FLASH_PAGESIZE (1024) + +#ifdef USE_MEM_HT32F52243 + #define LIBCFG_FLASH_SIZE (LIBCFG_FLASH_PAGESIZE * 64) + #define LIBCFG_RAM_SIZE (1024 * 8) + #define LIBCFG_CHIPNAME (0x52243) +#endif + +#ifdef USE_MEM_HT32F52253 + #define LIBCFG_FLASH_SIZE (LIBCFG_FLASH_PAGESIZE * 127) + #define LIBCFG_RAM_SIZE (1024 * 16) + #define LIBCFG_CHIPNAME (0x52253) +#endif + +#define LIBCFG_PDMA (1) +#define LIBCFG_PDMA_CH3FIX (1) +#define LIBCFG_ADC_CH8_11 (1) + +#define LIBCFG_BFTM1 (1) +#define LIBCFG_SCTM0 (1) +#define LIBCFG_SCTM1 (1) +#define LIBCFG_SCTM2 (1) +#define LIBCFG_SCTM3 (1) +#define LIBCFG_MCTM0 (1) + +#define LIBCFG_LSE (1) +#define LIBCFG_CRC (1) +#define LIBCFG_DIV (1) + +#define LIBCFG_USART1 (1) +#define LIBCFG_UART1 (1) +#define LIBCFG_UART2 (1) +#define LIBCFG_UART3 (1) +#define LIBCFG_SPI1 (1) +#define LIBCFG_I2C1 (1) +#define LIBCFG_I2C2 (1) + +#define LIBCFG_GPIOC (1) +#define LIBCFG_GPIOD (1) +#define LIBCFG_GPIO_DISABLE_DEBUG_PORT (1) +#define LIBCFG_CKCU_AUTO_TRIM_LEGACY (1) +#define LIBCFG_FMC_PREFETCH (1) +#define LIBCFG_PWRCU_VDD_2V0_3V6 (1) +#define LIBCFG_PWRCU_V15_READY_SOURCE (1) + +#endif diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f52331_41_libcfg.h b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f52331_41_libcfg.h new file mode 100644 index 0000000000..63db24b8f4 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f52331_41_libcfg.h @@ -0,0 +1,78 @@ +/*********************************************************************************************************//** + * @file ht32f52331_41_libcfg.h + * @version $Rev:: 6189 $ + * @date $Date:: 2022-09-27 #$ + * @brief The library configuration file. + ************************************************************************************************************* +* @attention +* +* Firmware Disclaimer Information +* +* 1. The customer hereby acknowledges and agrees that the program technical documentation, including the +* code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the +* proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and +* other intellectual property laws. +* +* 2. The customer hereby acknowledges and agrees that the program technical documentation, including the +* code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties +* other than HOLTEK and the customer. +* +* 3. The program technical documentation, including the code, is provided "as is" and for customer reference +* only. After delivery by HOLTEK, the customer shall use the program technical documentation, including +* the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including +* the warranties of merchantability, satisfactory quality and fitness for a particular purpose. +* +*

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ +/* Define to prevent recursive inclusion -------------------------------------------------------------------*/ +#ifndef __HT32F52331_41_LIBCFG_H +#define __HT32F52331_41_LIBCFG_H + +/* Settings ------------------------------------------------------------------------------------------------*/ + +#if !defined(USE_MEM_HT32F52331) && !defined(USE_MEM_HT32F52341) +#define USE_MEM_HT32F52341 +#endif + +#define LIBCFG_MAX_SPEED (48000000) + +#define LIBCFG_FLASH_PAGESIZE (512) + +#ifdef USE_MEM_HT32F52331 + #define LIBCFG_FLASH_SIZE (LIBCFG_FLASH_PAGESIZE * 64) + #define LIBCFG_RAM_SIZE (1024 * 4) + #define LIBCFG_CHIPNAME (0x52331) +#endif + +#ifdef USE_MEM_HT32F52341 + #define LIBCFG_FLASH_SIZE (LIBCFG_FLASH_PAGESIZE * 127) + #define LIBCFG_RAM_SIZE (1024 * 8) + #define LIBCFG_CHIPNAME (0x52341) +#endif + +#define LIBCFG_ADC_CH8_11 (1) + +#define LIBCFG_BFTM1 (1) +#define LIBCFG_SCTM0 (1) +#define LIBCFG_SCTM1 (1) +#define LIBCFG_SCTM2 (1) +#define LIBCFG_SCTM3 (1) +#define LIBCFG_MCTM0 (1) + +#define LIBCFG_LSE (1) +#define LIBCFG_SCI0 (1) +#define LIBCFG_USBD (1) +#define LIBCFG_CRC (1) + +#define LIBCFG_UART1 (1) +#define LIBCFG_SPI1 (1) +#define LIBCFG_I2C1 (1) + +#define LIBCFG_GPIOC (1) +#define LIBCFG_GPIO_DISABLE_DEBUG_PORT (1) +#define LIBCFG_CKCU_AUTO_TRIM_LEGACY (1) +#define LIBCFG_FMC_PREFETCH (1) +#define LIBCFG_PWRCU_VDD_2V0_3V6 (1) +#define LIBCFG_PWRCU_V15_READY_SOURCE (1) + +#endif diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f52342_52_libcfg.h b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f52342_52_libcfg.h new file mode 100644 index 0000000000..54a148b589 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f52342_52_libcfg.h @@ -0,0 +1,91 @@ +/*********************************************************************************************************//** + * @file ht32f52342_52_libcfg.h + * @version $Rev:: 6189 $ + * @date $Date:: 2022-09-27 #$ + * @brief The library configuration file. + ************************************************************************************************************* +* @attention +* +* Firmware Disclaimer Information +* +* 1. The customer hereby acknowledges and agrees that the program technical documentation, including the +* code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the +* proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and +* other intellectual property laws. +* +* 2. The customer hereby acknowledges and agrees that the program technical documentation, including the +* code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties +* other than HOLTEK and the customer. +* +* 3. The program technical documentation, including the code, is provided "as is" and for customer reference +* only. After delivery by HOLTEK, the customer shall use the program technical documentation, including +* the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including +* the warranties of merchantability, satisfactory quality and fitness for a particular purpose. +* +*

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ +/* Define to prevent recursive inclusion -------------------------------------------------------------------*/ +#ifndef __HT32F52342_52_LIBCFG_H +#define __HT32F52342_52_LIBCFG_H + +/* Settings ------------------------------------------------------------------------------------------------*/ + +#if !defined(USE_MEM_HT32F52342) && !defined(USE_MEM_HT32F52352) +#define USE_MEM_HT32F52352 +#endif + +#define LIBCFG_MAX_SPEED (48000000) + +#define LIBCFG_FLASH_PAGESIZE (512) + +#ifdef USE_MEM_HT32F52342 + #define LIBCFG_FLASH_SIZE (LIBCFG_FLASH_PAGESIZE * 128) + #define LIBCFG_RAM_SIZE (1024 * 8) + #define LIBCFG_CHIPNAME (0x52342) +#endif + +#ifdef USE_MEM_HT32F52352 + #define LIBCFG_FLASH_SIZE (LIBCFG_FLASH_PAGESIZE * 255) + #define LIBCFG_RAM_SIZE (1024 * 16) + #define LIBCFG_CHIPNAME (0x52352) +#endif + +#define LIBCFG_PDMA (1) +#define LIBCFG_PDMA_CH3FIX (1) +#define LIBCFG_ADC_CH8_11 (1) +#define LIBCFG_CMP (1) + +#define LIBCFG_BFTM1 (1) +#define LIBCFG_SCTM0 (1) +#define LIBCFG_SCTM1 (1) +#define LIBCFG_GPTM1 (1) +#define LIBCFG_MCTM0 (1) + +#define LIBCFG_LSE (1) +#define LIBCFG_SCI0 (1) +#define LIBCFG_SCI1 (1) +#define LIBCFG_USBD (1) +#define LIBCFG_EBI (1) +#define LIBCFG_I2S (1) +#define LIBCFG_CRC (1) + +#define LIBCFG_USART1 (1) +#define LIBCFG_UART1 (1) +#define LIBCFG_SPI1 (1) +#define LIBCFG_I2C1 (1) + +#define LIBCFG_GPIOC (1) +#define LIBCFG_GPIOD (1) + +#define LIBCFG_BAKREG (1) + +#define LIBCFG_FMC_BRANCHCACHE (1) +#define LIBCFG_FMC_PREFETCH (1) +#define LIBCFG_FLASH_2PAGE_PER_WPBIT (1) +#define LIBCFG_GPIO_DISABLE_DEBUG_PORT (1) +#define LIBCFG_RTC_LSI_LOAD_TRIM (1) +#define LIBCFG_CKCU_AUTO_TRIM_LEGACY (1) +#define LIBCFG_PWRCU_VDD_2V0_3V6 (1) +#define LIBCFG_PWRCU_V15_READY_SOURCE (1) + +#endif diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f52344_54_libcfg.h b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f52344_54_libcfg.h new file mode 100644 index 0000000000..452a832483 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f52344_54_libcfg.h @@ -0,0 +1,84 @@ +/*********************************************************************************************************//** + * @file ht32f52344_54_libcfg.h + * @version $Rev:: 6189 $ + * @date $Date:: 2022-09-27 #$ + * @brief The library configuration file. + ************************************************************************************************************* +* @attention +* +* Firmware Disclaimer Information +* +* 1. The customer hereby acknowledges and agrees that the program technical documentation, including the +* code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the +* proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and +* other intellectual property laws. +* +* 2. The customer hereby acknowledges and agrees that the program technical documentation, including the +* code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties +* other than HOLTEK and the customer. +* +* 3. The program technical documentation, including the code, is provided "as is" and for customer reference +* only. After delivery by HOLTEK, the customer shall use the program technical documentation, including +* the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including +* the warranties of merchantability, satisfactory quality and fitness for a particular purpose. +* +*

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ +/* Define to prevent recursive inclusion -------------------------------------------------------------------*/ +#ifndef __HT32F52344_54_LIBCFG_H +#define __HT32F52344_54_LIBCFG_H + +/* Settings ------------------------------------------------------------------------------------------------*/ + +#if !defined(USE_MEM_HT32F52344) && !defined(USE_MEM_HT32F52354) +#define USE_MEM_HT32F52354 +#endif + +#define LIBCFG_MAX_SPEED (60000000) + +#define LIBCFG_FLASH_PAGESIZE (1024) + +#ifdef USE_MEM_HT32F52344 + #define LIBCFG_FLASH_SIZE (LIBCFG_FLASH_PAGESIZE * 64) + #define LIBCFG_RAM_SIZE (1024 * 8) + #define LIBCFG_CHIPNAME (0x52344) +#endif + +#ifdef USE_MEM_HT32F52354 + #define LIBCFG_FLASH_SIZE (LIBCFG_FLASH_PAGESIZE * 127) + #define LIBCFG_RAM_SIZE (1024 * 8) + #define LIBCFG_CHIPNAME (0x52354) +#endif + +#define LIBCFG_ADC_CH8_11 (1) +#define LIBCFG_ADC_IVREF (1) +#define LIBCFG_ADC_MVDDA (1) +#define LIBCFG_BFTM1 (1) +#define LIBCFG_CKCU_ATM_V01 (1) +#define LIBCFG_CKCU_PLLSRCDIV (1) +#define LIBCFG_CKCU_REFCLK_EXT_PIN (1) +#define LIBCFG_CKCU_SYS_CK_60M (1) +#define LIBCFG_CKCU_USB_PLL (1) +#define LIBCFG_CKCU_USB_PLL_96M (1) +#define LIBCFG_CKCU_MCTM_SRC (1) +#define LIBCFG_CMP (1) +#define LIBCFG_CMP_IVREF_CN_IN (1) +#define LIBCFG_CRC (1) +#define LIBCFG_DIV (1) +#define LIBCFG_EBI (1) +#define LIBCFG_FMC_PREFETCH (1) +#define LIBCFG_FMC_WAIT_STATE_2 (1) +#define LIBCFG_GPIOC (1) +#define LIBCFG_GPIOD (1) +#define LIBCFG_LSE (1) +#define LIBCFG_MCTM0 (1) +#define LIBCFG_NO_USART0 (1) +#define LIBCFG_PDMA (1) +#define LIBCFG_PDMA_CH3FIX (1) +#define LIBCFG_SCTM0 (1) +#define LIBCFG_SCTM1 (1) +#define LIBCFG_SPI1 (1) +#define LIBCFG_UART1 (1) +#define LIBCFG_USBD (1) + +#endif diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f52357_67_libcfg.h b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f52357_67_libcfg.h new file mode 100644 index 0000000000..1804f46079 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f52357_67_libcfg.h @@ -0,0 +1,102 @@ +/*********************************************************************************************************//** + * @file ht32f52357_67_libcfg.h + * @version $Rev:: 7167 $ + * @date $Date:: 2023-08-25 #$ + * @brief The library configuration file. + ************************************************************************************************************* +* @attention +* +* Firmware Disclaimer Information +* +* 1. The customer hereby acknowledges and agrees that the program technical documentation, including the +* code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the +* proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and +* other intellectual property laws. +* +* 2. The customer hereby acknowledges and agrees that the program technical documentation, including the +* code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties +* other than HOLTEK and the customer. +* +* 3. The program technical documentation, including the code, is provided "as is" and for customer reference +* only. After delivery by HOLTEK, the customer shall use the program technical documentation, including +* the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including +* the warranties of merchantability, satisfactory quality and fitness for a particular purpose. +* +*

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ +/* Define to prevent recursive inclusion -------------------------------------------------------------------*/ +#ifndef __HT32F52357_67_LIBCFG_H +#define __HT32F52357_67_LIBCFG_H + +/* Settings ------------------------------------------------------------------------------------------------*/ + +#if !defined(USE_MEM_HT32F52357) && !defined(USE_MEM_HT32F52367) +#define USE_MEM_HT32F52367 +#endif + +#define LIBCFG_MAX_SPEED (60000000) + +#define LIBCFG_FLASH_PAGESIZE (1024) + +#ifdef USE_MEM_HT32F52357 + #define LIBCFG_FLASH_SIZE (LIBCFG_FLASH_PAGESIZE * 128) + #define LIBCFG_RAM_SIZE (1024 * 16) + #define LIBCFG_CHIPNAME (0x52357) +#endif + +#ifdef USE_MEM_HT32F52367 + #define LIBCFG_FLASH_SIZE (LIBCFG_FLASH_PAGESIZE * 255) + #define LIBCFG_RAM_SIZE (1024 * 32) + #define LIBCFG_CHIPNAME (0x52367) +#endif + +#define LIBCFG_ADC_CH8_11 (1) +#define LIBCFG_ADC_IVREF (1) +#define LIBCFG_ADC_MVDDA (1) +#define LIBCFG_AES (1) +#define LIBCFG_AES_KEYSIZE_256B (1) +#define LIBCFG_BAKREG (1) +#define LIBCFG_BFTM1 (1) +#define LIBCFG_CKCU_ATM_V01 (1) +#define LIBCFG_CKCU_PLLSRCDIV (1) +#define LIBCFG_CKCU_REFCLK_EXT_PIN (1) +#define LIBCFG_CKCU_SYS_CK_60M (1) +#define LIBCFG_CKCU_USB_PLL (1) +#define LIBCFG_CMP (1) +#define LIBCFG_CRC (1) +#define LIBCFG_DAC0 (1) +#define LIBCFG_DIV (1) +#define LIBCFG_EBI (1) +#define LIBCFG_FLASH_2PAGE_PER_WPBIT (1) +#define LIBCFG_FMC_BRANCHCACHE (1) +#define LIBCFG_FMC_PREFETCH (1) +#define LIBCFG_FMC_WAIT_STATE_2 (1) +#define LIBCFG_GPIOC (1) +#define LIBCFG_GPIOD (1) +#define LIBCFG_GPIOE (1) +#define LIBCFG_I2C1 (1) +#define LIBCFG_I2S (1) +#define LIBCFG_LSE (1) +#define LIBCFG_MCTM0 (1) +#define LIBCFG_PDMA (1) +#define LIBCFG_PDMA_CH3FIX (1) +#define LIBCFG_PWM0 (1) +#define LIBCFG_PWM1 (1) +#define LIBCFG_QSPI (1) +#define LIBCFG_SCI0 (1) +#define LIBCFG_SCI1 (1) +#define LIBCFG_SCTM0 (1) +#define LIBCFG_SCTM1 (1) +#define LIBCFG_SPI1 (1) +#define LIBCFG_UART1 (1) +#define LIBCFG_UART2 (1) +#define LIBCFG_UART3 (1) +#define LIBCFG_USART1 (1) +#define LIBCFG_USBD (1) + +#define UART0_IRQHandler UART0_UART2_IRQHandler +#define UART2_IRQHandler UART0_UART2_IRQHandler +#define UART1_IRQHandler UART1_UART3_IRQHandler +#define UART3_IRQHandler UART1_UART3_IRQHandler + +#endif diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f53231_41_libcfg.h b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f53231_41_libcfg.h new file mode 100644 index 0000000000..43068a9c12 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f53231_41_libcfg.h @@ -0,0 +1,96 @@ +/*********************************************************************************************************//** + * @file ht32f53231_41_libcfg.h + * @version $Rev:: 7265 $ + * @date $Date:: 2023-10-02 #$ + * @brief The library configuration file. + ************************************************************************************************************* +* @attention +* +* Firmware Disclaimer Information +* +* 1. The customer hereby acknowledges and agrees that the program technical documentation, including the +* code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the +* proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and +* other intellectual property laws. +* +* 2. The customer hereby acknowledges and agrees that the program technical documentation, including the +* code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties +* other than HOLTEK and the customer. +* +* 3. The program technical documentation, including the code, is provided "as is" and for customer reference +* only. After delivery by HOLTEK, the customer shall use the program technical documentation, including +* the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including +* the warranties of merchantability, satisfactory quality and fitness for a particular purpose. +* +*

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ +/* Define to prevent recursive inclusion -------------------------------------------------------------------*/ +#ifndef __HT32F53231_41_LIBCFG_H +#define __HT32F53231_41_LIBCFG_H + +/* Settings ------------------------------------------------------------------------------------------------*/ + +#if !defined(USE_MEM_HT32F53231) && !defined(USE_MEM_HT32F53241) +#define USE_MEM_HT32F53241 +#endif + +#define LIBCFG_MAX_SPEED (60000000) + +#define LIBCFG_FLASH_PAGESIZE (1024) + +#ifdef USE_MEM_HT32F53231 + #define LIBCFG_FLASH_SIZE (LIBCFG_FLASH_PAGESIZE * 32) + #define LIBCFG_RAM_SIZE (1024 * 4) + #define LIBCFG_CHIPNAME (0x53231) +#endif + +#ifdef USE_MEM_HT32F53241 + #define LIBCFG_FLASH_SIZE (LIBCFG_FLASH_PAGESIZE * 63) + #define LIBCFG_RAM_SIZE (1024 * 8) + #define LIBCFG_CHIPNAME (0x53241) +#endif + +#define LIBCFG_PDMA (1) +#define LIBCFG_ADC_CH8_11 (1) + +#define LIBCFG_BFTM1 (1) +#define LIBCFG_MCTM0 (1) +#define LIBCFG_PWM0 (1) + +#define LIBCFG_LSE (1) +#define LIBCFG_LEDC (1) +#define LIBCFG_CRC (1) +#define LIBCFG_DIV (1) +#define LIBCFG_CAN0 (1) + +#define LIBCFG_UART1 (1) +#define LIBCFG_SPI1 (1) +#define LIBCFG_I2C1 (1) + +#define LIBCFG_GPIOC (1) +#define LIBCFG_GPIOD (1) + +#define LIBCFG_FMC_WAIT_STATE_2 (1) +#define LIBCFG_FMC_PREFETCH (1) +#define LIBCFG_CKCU_PLLSRCDIV (1) +#define LIBCFG_CKCU_AUTO_TRIM_LEGACY (1) +#define LIBCFG_CKCU_ATM_V01 (1) +#define LIBCFG_CKCU_SYS_CK_60M (1) +#define LIBCFG_CKCU_REFCLK_EXT_PIN (1) +#define LIBCFG_PWRCU_VDD_5V (1) +#define LIBCFG_PWRCU_WAKEUP1 (1) +#define LIBCFG_PWRCU_WAKEUP_V01 (1) +#define LIBCFG_PWRCU_NO_VDDPORF (1) +#define LIBCFG_PWRCU_NO_PDF (1) +#define LIBCFG_PWRCU_PORF (1) +#define LIBCFG_PWRCU_NO_PD_MODE (1) +#define LIBCFG_NO_PWRCU_TEST_REG (1) +#define LIBCFG_LEDC_NO_COM_8_11 (1) +#define LIBCFG_ADC_IVREF (1) +#define LIBCFG_ADC_IVREF_LEVEL_TYPE2 (1) +#define LIBCFG_ADC_MVDDA (1) +#define LIBCFG_USART_LIN (1) +#define LIBCFG_USART_SINGLE_WIRE (1) +#define LIBCFG_GPIO_SINK_CURREMT_ENHANCED (1) + +#endif diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f53242_52_libcfg.h b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f53242_52_libcfg.h new file mode 100644 index 0000000000..c2493ba610 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f53242_52_libcfg.h @@ -0,0 +1,100 @@ +/*********************************************************************************************************//** + * @file ht32f53242_52_libcfg.h + * @version $Rev:: 7265 $ + * @date $Date:: 2023-10-02 #$ + * @brief The library configuration file. + ************************************************************************************************************* +* @attention +* +* Firmware Disclaimer Information +* +* 1. The customer hereby acknowledges and agrees that the program technical documentation, including the +* code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the +* proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and +* other intellectual property laws. +* +* 2. The customer hereby acknowledges and agrees that the program technical documentation, including the +* code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties +* other than HOLTEK and the customer. +* +* 3. The program technical documentation, including the code, is provided "as is" and for customer reference +* only. After delivery by HOLTEK, the customer shall use the program technical documentation, including +* the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including +* the warranties of merchantability, satisfactory quality and fitness for a particular purpose. +* +*

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ +/* Define to prevent recursive inclusion -------------------------------------------------------------------*/ +#ifndef __HT32F53242_52_LIBCFG_H +#define __HT32F53242_52_LIBCFG_H + +/* Settings ------------------------------------------------------------------------------------------------*/ + +#if !defined(USE_MEM_HT32F53242) && !defined(USE_MEM_HT32F53252) +#define USE_MEM_HT32F53252 +#endif + +#define LIBCFG_MAX_SPEED (60000000) + +#define LIBCFG_FLASH_PAGESIZE (1024) + +#ifdef USE_MEM_HT32F53242 + #define LIBCFG_FLASH_SIZE (LIBCFG_FLASH_PAGESIZE * 64) + #define LIBCFG_RAM_SIZE (1024 * 8) + #define LIBCFG_CHIPNAME (0x53242) +#endif + +#ifdef USE_MEM_HT32F53252 + #define LIBCFG_FLASH_SIZE (LIBCFG_FLASH_PAGESIZE * 127) + #define LIBCFG_RAM_SIZE (1024 * 16) + #define LIBCFG_CHIPNAME (0x53252) +#endif + +#define LIBCFG_PDMA (1) +#define LIBCFG_ADC_CH8_11 (1) +#define LIBCFG_CMP (1) + +#define LIBCFG_BFTM1 (1) +#define LIBCFG_MCTM0 (1) +#define LIBCFG_PWM0 (1) +#define LIBCFG_PWM1 (1) + +#define LIBCFG_LSE (1) +#define LIBCFG_EBI (1) +#define LIBCFG_LEDC (1) +#define LIBCFG_CRC (1) +#define LIBCFG_DIV (1) +#define LIBCFG_CAN0 (1) + +#define LIBCFG_USART1 (1) +#define LIBCFG_UART1 (1) +#define LIBCFG_SPI1 (1) +#define LIBCFG_I2C1 (1) + +#define LIBCFG_GPIOC (1) +#define LIBCFG_GPIOD (1) + +#define LIBCFG_FMC_WAIT_STATE_2 (1) +#define LIBCFG_FMC_PREFETCH (1) +#define LIBCFG_CKCU_PLLSRCDIV (1) +#define LIBCFG_CKCU_AUTO_TRIM_LEGACY (1) +#define LIBCFG_CKCU_ATM_V01 (1) +#define LIBCFG_CKCU_SYS_CK_60M (1) +#define LIBCFG_CKCU_REFCLK_EXT_PIN (1) +#define LIBCFG_PWRCU_VDD_5V (1) +#define LIBCFG_PWRCU_WAKEUP1 (1) +#define LIBCFG_PWRCU_WAKEUP_V01 (1) +#define LIBCFG_PWRCU_NO_VDDPORF (1) +#define LIBCFG_PWRCU_NO_PDF (1) +#define LIBCFG_PWRCU_PORF (1) +#define LIBCFG_PWRCU_NO_PD_MODE (1) +#define LIBCFG_NO_PWRCU_TEST_REG (1) +#define LIBCFG_LEDC_NO_COM_8_11 (1) +#define LIBCFG_ADC_IVREF (1) +#define LIBCFG_ADC_IVREF_LEVEL_TYPE2 (1) +#define LIBCFG_ADC_MVDDA (1) +#define LIBCFG_USART_LIN (1) +#define LIBCFG_USART_SINGLE_WIRE (1) +#define LIBCFG_GPIO_SINK_CURREMT_ENHANCED (1) + +#endif diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f54231_41_libcfg.h b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f54231_41_libcfg.h new file mode 100644 index 0000000000..671765ef1b --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f54231_41_libcfg.h @@ -0,0 +1,87 @@ +/*********************************************************************************************************//** + * @file ht32f54231_41_libcfg.h + * @version $Rev:: 7184 $ + * @date $Date:: 2023-08-31 #$ + * @brief The library configuration file. + ************************************************************************************************************* +* @attention +* +* Firmware Disclaimer Information +* +* 1. The customer hereby acknowledges and agrees that the program technical documentation, including the +* code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the +* proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and +* other intellectual property laws. +* +* 2. The customer hereby acknowledges and agrees that the program technical documentation, including the +* code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties +* other than HOLTEK and the customer. +* +* 3. The program technical documentation, including the code, is provided "as is" and for customer reference +* only. After delivery by HOLTEK, the customer shall use the program technical documentation, including +* the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including +* the warranties of merchantability, satisfactory quality and fitness for a particular purpose. +* +*

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ +/* Define to prevent recursive inclusion -------------------------------------------------------------------*/ +#ifndef __HT32F54231_41_LIBCFG_H +#define __HT32F54231_41_LIBCFG_H + +/* Settings ------------------------------------------------------------------------------------------------*/ + +#if !defined(USE_MEM_HT32F54231) && !defined(USE_MEM_HT32F54241) +#define USE_MEM_HT32F52352 +#endif + +#define LIBCFG_MAX_SPEED (60000000) + +#define LIBCFG_FLASH_PAGESIZE (1024) + +#ifdef USE_MEM_HT32F54231 + #define LIBCFG_FLASH_SIZE (LIBCFG_FLASH_PAGESIZE * 32) + #define LIBCFG_RAM_SIZE (1024 * 4) + #define LIBCFG_CHIPNAME (0x54231) +#endif + +#ifdef USE_MEM_HT32F54241 + #define LIBCFG_FLASH_SIZE (LIBCFG_FLASH_PAGESIZE * 63) + #define LIBCFG_RAM_SIZE (1024 * 8) + #define LIBCFG_CHIPNAME (0x54241) +#endif + +#define LIBCFG_ADC_CH8_9 (1) +#define LIBCFG_ADC_IVREF (1) +#define LIBCFG_ADC_IVREF_LEVEL_TYPE2 (1) +#define LIBCFG_ADC_MVDDA (1) +#define LIBCFG_BFTM1 (1) +#define LIBCFG_CKCU_ATM_V01 (1) +#define LIBCFG_CKCU_PLLSRCDIV (1) +#define LIBCFG_CKCU_REFCLK_EXT_PIN (1) +#define LIBCFG_CKCU_SYS_CK_60M (1) +#define LIBCFG_CRC (1) +#define LIBCFG_DIV (1) +#define LIBCFG_FMC_PREFETCH (1) +#define LIBCFG_FMC_WAIT_STATE_2 (1) +#define LIBCFG_GPIOC (1) +#define LIBCFG_GPIO_SINK_CURRENT_ENHANCED (1) +#define LIBCFG_I2C1 (1) +#define LIBCFG_LEDC (1) +#define LIBCFG_LEDC_NO_COM_8_11 (1) +#define LIBCFG_LSE (1) +#define LIBCFG_MCTM0 (1) +#define LIBCFG_PWRCU_NO_PD_MODE (1) +#define LIBCFG_PWRCU_NO_PDF (1) +#define LIBCFG_PWRCU_NO_VDDPORF (1) +#define LIBCFG_NO_PWRCU_TEST_REG (1) +#define LIBCFG_PWRCU_PORF (1) +#define LIBCFG_PWRCU_VDD_5V (1) +#define LIBCFG_PWRCU_WAKEUP_V01 (1) +#define LIBCFG_PWRCU_WAKEUP1 (1) +#define LIBCFG_SCTM0 (1) +#define LIBCFG_SCTM1 (1) +#define LIBCFG_SPI1 (1) +#define LIBCFG_TKEY (1) +#define LIBCFG_UART1 (1) + +#endif diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f54243_53_libcfg.h b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f54243_53_libcfg.h new file mode 100644 index 0000000000..750e4fb377 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f54243_53_libcfg.h @@ -0,0 +1,95 @@ +/*********************************************************************************************************//** + * @file ht32f54243_53_libcfg.h + * @version $Rev:: 6896 $ + * @date $Date:: 2023-05-08 #$ + * @brief The library configuration file. + ************************************************************************************************************* +* @attention +* +* Firmware Disclaimer Information +* +* 1. The customer hereby acknowledges and agrees that the program technical documentation, including the +* code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the +* proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and +* other intellectual property laws. +* +* 2. The customer hereby acknowledges and agrees that the program technical documentation, including the +* code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties +* other than HOLTEK and the customer. +* +* 3. The program technical documentation, including the code, is provided "as is" and for customer reference +* only. After delivery by HOLTEK, the customer shall use the program technical documentation, including +* the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including +* the warranties of merchantability, satisfactory quality and fitness for a particular purpose. +* +*

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ +/* Define to prevent recursive inclusion -------------------------------------------------------------------*/ +#ifndef __HT32F54243_53_LIBCFG_H +#define __HT32F54243_53_LIBCFG_H + +/* Settings ------------------------------------------------------------------------------------------------*/ + +#if !defined(USE_MEM_HT32F54243) && !defined(USE_MEM_HT32F54253) +#define USE_MEM_HT32F52352 +#endif + +#define LIBCFG_MAX_SPEED (60000000) + +#define LIBCFG_FLASH_PAGESIZE (1024) + +#ifdef USE_MEM_HT32F54243 + #define LIBCFG_FLASH_SIZE (LIBCFG_FLASH_PAGESIZE * 64) + #define LIBCFG_RAM_SIZE (1024 * 8) + #define LIBCFG_CHIPNAME (0x54243) +#endif + +#ifdef USE_MEM_HT32F54253 + #define LIBCFG_FLASH_SIZE (LIBCFG_FLASH_PAGESIZE * 127) + #define LIBCFG_RAM_SIZE (1024 * 16) + #define LIBCFG_CHIPNAME (0x54253) +#endif + +#define LIBCFG_ADC_CH8_9 (1) +#define LIBCFG_ADC_IVREF (1) +#define LIBCFG_ADC_IVREF_LEVEL_TYPE2 (1) +#define LIBCFG_ADC_MVDDA (1) +#define LIBCFG_BFTM1 (1) +#define LIBCFG_CKCU_ATM_V01 (1) +#define LIBCFG_CKCU_PLLSRCDIV (1) +#define LIBCFG_CKCU_REFCLK_EXT_PIN (1) +#define LIBCFG_CKCU_SYS_CK_60M (1) +#define LIBCFG_CRC (1) +#define LIBCFG_CMP (1) +#define LIBCFG_DIV (1) +#define LIBCFG_FMC_PREFETCH (1) +#define LIBCFG_FMC_WAIT_STATE_2 (1) +#define LIBCFG_GPIOC (1) +#define LIBCFG_GPIOD (1) +#define LIBCFG_GPIO_SINK_CURRENT_ENHANCED (1) +#define LIBCFG_I2C1 (1) +#define LIBCFG_I2C2 (1) +#define LIBCFG_LEDC (1) +#define LIBCFG_LSE (1) +#define LIBCFG_MCTM0 (1) +#define LIBCFG_PWRCU_NO_PD_MODE (1) +#define LIBCFG_PWRCU_NO_PDF (1) +#define LIBCFG_PWRCU_NO_VDDPORF (1) +#define LIBCFG_NO_PWRCU_TEST_REG (1) +#define LIBCFG_PDMA (1) +#define LIBCFG_PWRCU_PORF (1) +#define LIBCFG_PWRCU_VDD_5V (1) +#define LIBCFG_PWRCU_WAKEUP_V01 (1) +#define LIBCFG_PWRCU_WAKEUP1 (1) +#define LIBCFG_SCTM0 (1) +#define LIBCFG_SCTM1 (1) +#define LIBCFG_SCTM2 (1) +#define LIBCFG_SCTM3 (1) +#define LIBCFG_SPI1 (1) +#define LIBCFG_TKEY (1) +#define LIBCFG_UART1 (1) +#define LIBCFG_UART2 (1) +#define LIBCFG_UART3 (1) +#define LIBCFG_USART1 (1) + +#endif diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f57331_41_libcfg.h b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f57331_41_libcfg.h new file mode 100644 index 0000000000..147fdcc041 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f57331_41_libcfg.h @@ -0,0 +1,79 @@ +/*********************************************************************************************************//** + * @file ht32f57331_41_libcfg.h + * @version $Rev:: 6189 $ + * @date $Date:: 2022-09-27 #$ + * @brief The library configuration file. + ************************************************************************************************************* +* @attention +* +* Firmware Disclaimer Information +* +* 1. The customer hereby acknowledges and agrees that the program technical documentation, including the +* code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the +* proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and +* other intellectual property laws. +* +* 2. The customer hereby acknowledges and agrees that the program technical documentation, including the +* code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties +* other than HOLTEK and the customer. +* +* 3. The program technical documentation, including the code, is provided "as is" and for customer reference +* only. After delivery by HOLTEK, the customer shall use the program technical documentation, including +* the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including +* the warranties of merchantability, satisfactory quality and fitness for a particular purpose. +* +*

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ +/* Define to prevent recursive inclusion -------------------------------------------------------------------*/ +#ifndef __HT32F57331_41_LIBCFG_H +#define __HT32F57331_41_LIBCFG_H + +/* Settings ------------------------------------------------------------------------------------------------*/ + +#if !defined(USE_MEM_HT32F57331) && !defined(USE_MEM_HT32F57341) +#define USE_MEM_HT32F57341 +#endif + +#define LIBCFG_MAX_SPEED (60000000) + +#define LIBCFG_FLASH_PAGESIZE (1024) + +#ifdef USE_MEM_HT32F57331 + #define LIBCFG_FLASH_SIZE (LIBCFG_FLASH_PAGESIZE * 32) + #define LIBCFG_RAM_SIZE (1024 * 4) + #define LIBCFG_CHIPNAME (0x57331) +#endif + +#ifdef USE_MEM_HT32F57341 + #define LIBCFG_FLASH_SIZE (LIBCFG_FLASH_PAGESIZE * 63) + #define LIBCFG_RAM_SIZE (1024 * 8) + #define LIBCFG_CHIPNAME (0x57341) +#endif + +#define LIBCFG_ADC_CH8_9 (1) +#define LIBCFG_ADC_IVREF (1) +#define LIBCFG_ADC_MVDDA (1) +#define LIBCFG_BFTM1 (1) +#define LIBCFG_CKCU_ATM_V01 (1) +#define LIBCFG_CKCU_LCD_SRC (1) +#define LIBCFG_CKCU_PLLSRCDIV (1) +#define LIBCFG_CKCU_REFCLK_EXT_PIN (1) +#define LIBCFG_CKCU_SYS_CK_60M (1) +#define LIBCFG_CKCU_USB_PLL (1) +#define LIBCFG_CRC (1) +#define LIBCFG_DIV (1) +#define LIBCFG_FMC_PREFETCH (1) +#define LIBCFG_FMC_WAIT_STATE_2 (1) +#define LIBCFG_GPIOC (1) +#define LIBCFG_GPIOD (1) +#define LIBCFG_I2C1 (1) +#define LIBCFG_LCD (1) +#define LIBCFG_LSE (1) +#define LIBCFG_PWM0 (1) +#define LIBCFG_PWM1 (1) +#define LIBCFG_SCI0 (1) +#define LIBCFG_SPI1 (1) +#define LIBCFG_UART1 (1) +#define LIBCFG_USBD (1) + +#endif diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f57342_52_libcfg.h b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f57342_52_libcfg.h new file mode 100644 index 0000000000..c8740e5f8d --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f57342_52_libcfg.h @@ -0,0 +1,89 @@ +/*********************************************************************************************************//** + * @file ht32f57342_52_libcfg.h + * @version $Rev:: 7167 $ + * @date $Date:: 2023-08-25 #$ + * @brief The library configuration file. + ************************************************************************************************************* +* @attention +* +* Firmware Disclaimer Information +* +* 1. The customer hereby acknowledges and agrees that the program technical documentation, including the +* code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the +* proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and +* other intellectual property laws. +* +* 2. The customer hereby acknowledges and agrees that the program technical documentation, including the +* code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties +* other than HOLTEK and the customer. +* +* 3. The program technical documentation, including the code, is provided "as is" and for customer reference +* only. After delivery by HOLTEK, the customer shall use the program technical documentation, including +* the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including +* the warranties of merchantability, satisfactory quality and fitness for a particular purpose. +* +*

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ +/* Define to prevent recursive inclusion -------------------------------------------------------------------*/ +#ifndef __HT32F57342_52_LIBCFG_H +#define __HT32F57342_52_LIBCFG_H + +/* Settings ------------------------------------------------------------------------------------------------*/ + +#if !defined(USE_MEM_HT32F57342) && !defined(USE_MEM_HT32F57352) +#define USE_MEM_HT32F57352 +#endif + +#define LIBCFG_MAX_SPEED (60000000) + +#define LIBCFG_FLASH_PAGESIZE (1024) + +#ifdef USE_MEM_HT32F57342 + #define LIBCFG_FLASH_SIZE (LIBCFG_FLASH_PAGESIZE * 64) + #define LIBCFG_RAM_SIZE (1024 * 8) + #define LIBCFG_CHIPNAME (0x57342) +#endif + +#ifdef USE_MEM_HT32F57352 + #define LIBCFG_FLASH_SIZE (LIBCFG_FLASH_PAGESIZE * 127) + #define LIBCFG_RAM_SIZE (1024 * 16) + #define LIBCFG_CHIPNAME (0x57352) +#endif + +#define LIBCFG_ADC_CH8_9 (1) +#define LIBCFG_ADC_IVREF (1) +#define LIBCFG_ADC_MVDDA (1) +#define LIBCFG_AES (1) +#define LIBCFG_BFTM1 (1) +#define LIBCFG_CKCU_ATM_V01 (1) +#define LIBCFG_CKCU_LCD_SRC (1) +#define LIBCFG_CKCU_PLLSRCDIV (1) +#define LIBCFG_CKCU_REFCLK_EXT_PIN (1) +#define LIBCFG_CKCU_SYS_CK_60M (1) +#define LIBCFG_CKCU_USB_PLL (1) +#define LIBCFG_CRC (1) +#define LIBCFG_CMP (1) +#define LIBCFG_DAC0 (1) +#define LIBCFG_DIV (1) +#define LIBCFG_FMC_PREFETCH (1) +#define LIBCFG_FMC_WAIT_STATE_2 (1) +#define LIBCFG_GPIOC (1) +#define LIBCFG_GPIOD (1) +#define LIBCFG_GPIOE (1) +#define LIBCFG_I2C1 (1) +#define LIBCFG_I2S (1) +#define LIBCFG_LCD (1) +#define LIBCFG_LSE (1) +#define LIBCFG_PDMA (1) +#define LIBCFG_PDMA_CH3FIX (1) +#define LIBCFG_PWM0 (1) +#define LIBCFG_PWM1 (1) +#define LIBCFG_SCI0 (1) +#define LIBCFG_SCI1 (1) +#define LIBCFG_SCTM0 (1) +#define LIBCFG_SCTM1 (1) +#define LIBCFG_SPI1 (1) +#define LIBCFG_UART1 (1) +#define LIBCFG_USBD (1) + +#endif diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f5826_libcfg.h b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f5826_libcfg.h new file mode 100644 index 0000000000..f2378a22fd --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f5826_libcfg.h @@ -0,0 +1,85 @@ +/*********************************************************************************************************//** + * @file ht32f5826_libcfg.h + * @version $Rev:: 7184 $ + * @date $Date:: 2023-08-31 #$ + * @brief The library configuration file. + ************************************************************************************************************* +* @attention +* +* Firmware Disclaimer Information +* +* 1. The customer hereby acknowledges and agrees that the program technical documentation, including the +* code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the +* proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and +* other intellectual property laws. +* +* 2. The customer hereby acknowledges and agrees that the program technical documentation, including the +* code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties +* other than HOLTEK and the customer. +* +* 3. The program technical documentation, including the code, is provided "as is" and for customer reference +* only. After delivery by HOLTEK, the customer shall use the program technical documentation, including +* the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including +* the warranties of merchantability, satisfactory quality and fitness for a particular purpose. +* +*

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ +/* Define to prevent recursive inclusion -------------------------------------------------------------------*/ +#ifndef __HT32F5826_LIBCFG_H +#define __HT32F5826_LIBCFG_H + +/* Settings ------------------------------------------------------------------------------------------------*/ + +#if !defined(USE_MEM_HT32F5826) +#define USE_MEM_HT32F5826 +#endif + +#define LIBCFG_MAX_SPEED (48000000) + +#define LIBCFG_FLASH_PAGESIZE (512) + +#ifdef USE_MEM_HT32F5826 + #define LIBCFG_FLASH_SIZE (LIBCFG_FLASH_PAGESIZE * 255) + #define LIBCFG_RAM_SIZE (1024 * 16) + #define LIBCFG_CHIPNAME (0x5826) +#endif + +#define LIBCFG_PDMA (1) +#define LIBCFG_PDMA_CH3FIX (1) +#define LIBCFG_ADC_CH8_11 (1) +#define LIBCFG_CMP (1) + +#define LIBCFG_BFTM1 (1) +#define LIBCFG_SCTM0 (1) +#define LIBCFG_SCTM1 (1) +#define LIBCFG_GPTM1 (1) +#define LIBCFG_MCTM0 (1) + +#define LIBCFG_LSE (1) +#define LIBCFG_SCI0 (1) +#define LIBCFG_SCI1 (1) +#define LIBCFG_USBD (1) +#define LIBCFG_EBI (1) +#define LIBCFG_I2S (1) +#define LIBCFG_CRC (1) + +#define LIBCFG_USART1 (1) +#define LIBCFG_UART1 (1) +#define LIBCFG_SPI1 (1) +#define LIBCFG_I2C1 (1) + +#define LIBCFG_GPIOC (1) +#define LIBCFG_GPIOD (1) + +#define LIBCFG_BAKREG (1) + +#define LIBCFG_FMC_BRANCHCACHE (1) +#define LIBCFG_FMC_PREFETCH (1) +#define LIBCFG_FLASH_2PAGE_PER_WPBIT (1) +#define LIBCFG_GPIO_DISABLE_DEBUG_PORT (1) +#define LIBCFG_RTC_LSI_LOAD_TRIM (1) +#define LIBCFG_CKCU_AUTO_TRIM_LEGACY (1) +#define LIBCFG_PWRCU_VDD_2V0_3V6 (1) +#define LIBCFG_PWRCU_V15_READY_SOURCE (1) + +#endif diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f5xxxx_adc.h b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f5xxxx_adc.h new file mode 100644 index 0000000000..c50babaa1a --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f5xxxx_adc.h @@ -0,0 +1,660 @@ +/*********************************************************************************************************//** + * @file ht32f5xxxx_adc.h + * @version $Rev:: 7265 $ + * @date $Date:: 2023-10-02 #$ + * @brief The header file of the ADC library. + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------------------------------------*/ +#ifndef __ht32f5XXXX_ADC_H +#define __ht32f5XXXX_ADC_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------------------------------------*/ +#include "ht32.h" + +/** @addtogroup HT32F5xxxx_Peripheral_Driver HT32F5xxxx Peripheral Driver + * @{ + */ + +/** @addtogroup ADC + * @{ + */ + + +/* Exported constants --------------------------------------------------------------------------------------*/ +/** @defgroup ADC_Exported_Constants ADC exported constants + * @{ + */ +#define IS_ADC(x) (x == HT_ADC0) + +#define ONE_SHOT_MODE (0x00000000) +#define CONTINUOUS_MODE (0x00000002) +#if (LIBCFG_ADC_NO_DISCON_MODE) +#define IS_DISCONTINUOUS_MODE(x) (0) +#else +#define DISCONTINUOUS_MODE (0x00000003) +#define IS_DISCONTINUOUS_MODE(x) (x == DISCONTINUOUS_MODE) +#endif + +#define IS_ADC_CONVERSION_MODE(REGULAR_MODE) ((REGULAR_MODE == ONE_SHOT_MODE) || \ + (REGULAR_MODE == CONTINUOUS_MODE) || \ + (IS_DISCONTINUOUS_MODE(REGULAR_MODE))) + +#define ADC_CH_0 (0) +#define ADC_CH_1 (1) +#define ADC_CH_2 (2) +#define ADC_CH_3 (3) +#define ADC_CH_4 (4) +#define ADC_CH_5 (5) +#define ADC_CH_6 (6) +#define ADC_CH_7 (7) + +#define IS_ADC_CHANNEL1(CHANNEL) (((CHANNEL) == ADC_CH_0) || ((CHANNEL) == ADC_CH_1) || \ + ((CHANNEL) == ADC_CH_2) || ((CHANNEL) == ADC_CH_3) || \ + ((CHANNEL) == ADC_CH_4) || ((CHANNEL) == ADC_CH_5) || \ + ((CHANNEL) == ADC_CH_6) || ((CHANNEL) == ADC_CH_7)) + +#if (LIBCFG_ADC_CH8_9) +#define ADC_CH_8 (8) +#define ADC_CH_9 (9) +#define IS_ADC_CHANNEL2(CHANNEL) (((CHANNEL) == ADC_CH_8) || ((CHANNEL) == ADC_CH_9)) +#elif (LIBCFG_ADC_CH8_11) +#define ADC_CH_8 (8) +#define ADC_CH_9 (9) +#define ADC_CH_10 (10) +#define ADC_CH_11 (11) +#define IS_ADC_CHANNEL2(CHANNEL) (((CHANNEL) == ADC_CH_8) || ((CHANNEL) == ADC_CH_9) || \ + ((CHANNEL) == ADC_CH_10) || ((CHANNEL) == ADC_CH_11)) +#else +#define IS_ADC_CHANNEL2(CHANNEL) (0) +#endif + +#if (LIBCFG_ADC_CH12_15) +#define ADC_CH_12 (12) +#define ADC_CH_13 (13) +#define ADC_CH_14 (14) +#define ADC_CH_15 (15) +#define IS_ADC_CHANNEL3(CHANNEL) (((CHANNEL) == ADC_CH_12) || ((CHANNEL) == ADC_CH_13) || \ + ((CHANNEL) == ADC_CH_14) || ((CHANNEL) == ADC_CH_15)) +#else +#define IS_ADC_CHANNEL3(CHANNEL) (0) +#endif + +#if defined(USE_HT32F50020_30) +#define ADC_CH_BANDGAP (12) +#define ADC_CH_MVDDA (13) +#define IS_ADC_CH_INTERNAL1(CH) (((CH) == ADC_CH_BANDGAP) || ((CH) == ADC_CH_MVDDA)) +#endif + +#if defined(USE_HT32F50220_30) +#define ADC_CH_GND_VREF (12) +#define ADC_CH_VDD_VREF (13) +#define IS_ADC_CH_INTERNAL1(CH) (((CH) == ADC_CH_GND_VREF) || ((CH) == ADC_CH_VDD_VREF)) +#endif + +#if defined(USE_HT32F50231_41) +#define ADC_CH_GND_VREF (12) +#define ADC_CH_VDD_VREF (13) +#define IS_ADC_CH_INTERNAL1(CH) (((CH) == ADC_CH_GND_VREF) || ((CH) == ADC_CH_VDD_VREF)) +#endif + +#if defined(USE_HT32F52220_30) +#define ADC_CH_GND_VREF (16) +#define ADC_CH_VDD_VREF (17) +#define IS_ADC_CH_INTERNAL1(CH) (((CH) == ADC_CH_GND_VREF) || ((CH) == ADC_CH_VDD_VREF)) +#endif + +#if defined(USE_HT32F52231_41) +#define ADC_CH_GND_VREF (16) +#define ADC_CH_VDD_VREF (17) +#define IS_ADC_CH_INTERNAL1(CH) (((CH) == ADC_CH_GND_VREF) || ((CH) == ADC_CH_VDD_VREF)) +#endif + +#if defined(USE_HT32F52243_53) +#define ADC_CH_GND_VREF (16) +#define ADC_CH_VDD_VREF (17) +#define IS_ADC_CH_INTERNAL1(CH) (((CH) == ADC_CH_GND_VREF) || ((CH) == ADC_CH_VDD_VREF)) +#endif + +#if defined(USE_HT32F52331_41) +#define ADC_CH_GND_VREF (16) +#define ADC_CH_VDD_VREF (17) +#define IS_ADC_CH_INTERNAL1(CH) (((CH) == ADC_CH_GND_VREF) || ((CH) == ADC_CH_VDD_VREF)) +#endif + +#if defined(USE_HT32F52342_52) +#define ADC_CH_GND_VREF (16) +#define ADC_CH_VDD_VREF (17) +#define IS_ADC_CH_INTERNAL1(CH) (((CH) == ADC_CH_GND_VREF) || ((CH) == ADC_CH_VDD_VREF)) +#endif + +#if defined(USE_HT32F52344_54) +#define ADC_CH_IVREF (15) +#define ADC_CH_GND_VREF (16) +#define ADC_CH_MVDDA (17) +#define IS_ADC_CH_INTERNAL1(CH) (((CH) == ADC_CH_IVREF) || \ + ((CH) == ADC_CH_GND_VREF) || \ + ((CH) == ADC_CH_MVDDA)) +#endif + +#if defined(USE_HT32F52357_67) +#define ADC_CH_VDD_VREF (12) +#define ADC_CH_DAC0_CH1 (13) +#define ADC_CH_DAC0_CH0 (14) +#define ADC_CH_IVREF (15) +#define ADC_CH_GND_VREF (16) +#define ADC_CH_MVDDA (17) +#define IS_ADC_CH_INTERNAL1(CH) (((CH) == ADC_CH_VDD_VREF) || \ + ((CH) == ADC_CH_DAC0_CH1) || \ + ((CH) == ADC_CH_DAC0_CH0) || \ + ((CH) == ADC_CH_IVREF) || \ + ((CH) == ADC_CH_GND_VREF) || \ + ((CH) == ADC_CH_MVDDA)) +#endif + +#if defined(USE_HT32F57331_41) +#define ADC_CH_VDD_VREF (12) +#define ADC_CH_IVREF (15) +#define ADC_CH_GND_VREF (16) +#define ADC_CH_MVDDA (17) +#define IS_ADC_CH_INTERNAL1(CH) (((CH) == ADC_CH_VDD_VREF) || \ + ((CH) == ADC_CH_IVREF) || \ + ((CH) == ADC_CH_GND_VREF) || \ + ((CH) == ADC_CH_MVDDA)) +#endif + +#if defined(USE_HT32F57342_52) +#define ADC_CH_VDD_VREF (12) +#define ADC_CH_DAC0_CH1 (13) +#define ADC_CH_DAC0_CH0 (14) +#define ADC_CH_IVREF (15) +#define ADC_CH_GND_VREF (16) +#define ADC_CH_MVDDA (17) +#define IS_ADC_CH_INTERNAL1(CH) (((CH) == ADC_CH_VDD_VREF) || \ + ((CH) == ADC_CH_DAC0_CH1) || \ + ((CH) == ADC_CH_DAC0_CH0) || \ + ((CH) == ADC_CH_IVREF) || \ + ((CH) == ADC_CH_GND_VREF) || \ + ((CH) == ADC_CH_MVDDA)) +#endif + +#if defined(USE_HT32F0006) +#define ADC_CH_GND_VREF (16) +#define ADC_CH_VDD_VREF (17) +#define IS_ADC_CH_INTERNAL1(CH) (((CH) == ADC_CH_GND_VREF) || ((CH) == ADC_CH_VDD_VREF)) +#endif + +#if defined(USE_HT32F61244_45) +#define ADC_CH_GND_VREF (16) +#define ADC_CH_VDD_VREF (17) +#define IS_ADC_CH_INTERNAL1(CH) (((CH) == ADC_CH_GND_VREF) || ((CH) == ADC_CH_VDD_VREF)) +#endif + +#if defined(USE_HT32F50343) +#define ADC_CH_MVDDA (17) +#define IS_ADC_CH_INTERNAL1(CH) (((CH) == ADC_CH_MVDDA)) +#endif + +#if defined(USE_HT32F5826) +#define ADC_CH_GND_VREF (16) +#define ADC_CH_VDD_VREF (17) +#define IS_ADC_CH_INTERNAL1(CH) (((CH) == ADC_CH_GND_VREF) || ((CH) == ADC_CH_VDD_VREF)) +#endif + +#if defined(USE_HT32F54231_41) +#define ADC_CH_GND_VREF (10) +#define ADC_CH_VDD_VREF (11) +#define ADC_CH_IVREF (12) +#define ADC_CH_MVDDA (13) +#define IS_ADC_CH_INTERNAL1(CH) (((CH) == ADC_CH_GND_VREF) || \ + ((CH) == ADC_CH_VDD_VREF) || \ + ((CH) == ADC_CH_IVREF) || \ + ((CH) == ADC_CH_MVDDA)) +#endif + +#if defined(USE_HT32F54243_53) +#define ADC_CH_GND_VREF (10) +#define ADC_CH_VDD_VREF (11) +#define ADC_CH_IVREF (12) +#define ADC_CH_MVDDA (13) +#define IS_ADC_CH_INTERNAL1(CH) (((CH) == ADC_CH_GND_VREF) || \ + ((CH) == ADC_CH_VDD_VREF) || \ + ((CH) == ADC_CH_IVREF) || \ + ((CH) == ADC_CH_MVDDA)) +#endif + +#if defined(USE_HT32F67041_51) +#define ADC_CH_IVREF (15) +#define ADC_CH_GND_VREF (16) +#define ADC_CH_MVDDA (17) +#define IS_ADC_CH_INTERNAL1(CH) (((CH) == ADC_CH_IVREF) || \ + ((CH) == ADC_CH_GND_VREF) || \ + ((CH) == ADC_CH_MVDDA)) +#endif + +#if defined(USE_HT32F52234_44) +#define ADC_CH_DAC0_CH0 (12) +#define ADC_CH_DAC0_CH1 (13) +#define ADC_CH_DAC1_CH0 (14) +#define ADC_CH_DAC1_CH1 (15) +#define ADC_CH_IVREF (16) +#define ADC_CH_MVDDA (17) +#define IS_ADC_CH_INTERNAL1(CH) (((CH) == ADC_CH_DAC0_CH0) || \ + ((CH) == ADC_CH_DAC0_CH1) || \ + ((CH) == ADC_CH_DAC1_CH0) || \ + ((CH) == ADC_CH_DAC1_CH1) || \ + ((CH) == ADC_CH_IVREF) || \ + ((CH) == ADC_CH_MVDDA)) +#endif + +#if defined(USE_HT32F53231_41) +#define ADC_CH_IVREF (12) +#define ADC_CH_MVDDA (13) +#define IS_ADC_CH_INTERNAL1(CH) (((CH) == ADC_CH_IVREF) || \ + ((CH) == ADC_CH_MVDDA)) +#endif + +#if defined(USE_HT32F53242_52) +#define ADC_CH_IVREF (12) +#define ADC_CH_MVDDA (13) +#define IS_ADC_CH_INTERNAL1(CH) (((CH) == ADC_CH_IVREF) || \ + ((CH) == ADC_CH_MVDDA)) +#endif + +#if defined(USE_HT32F50431_41) +#define ADC_CH_IVREF (12) +#define ADC_CH_MVDDA (13) +#define IS_ADC_CH_INTERNAL1(CH) (((CH) == ADC_CH_IVREF) || \ + ((CH) == ADC_CH_MVDDA)) +#endif + +#if defined(USE_HT32F50442_52) +#define ADC_CH_IVREF (12) +#define ADC_CH_MVDDA (13) +#define IS_ADC_CH_INTERNAL1(CH) (((CH) == ADC_CH_IVREF) || \ + ((CH) == ADC_CH_MVDDA)) +#endif + +#define IS_ADC_CHANNEL(CHANNEL) (IS_ADC_CHANNEL1(CHANNEL) || \ + IS_ADC_CHANNEL2(CHANNEL) || \ + IS_ADC_CHANNEL3(CHANNEL) || \ + IS_ADC_CH_INTERNAL1(CHANNEL)) + +#define IS_ADC_INPUT_CHANNEL(CHANNEL) (IS_ADC_CHANNEL1(CHANNEL) || IS_ADC_CHANNEL2(CHANNEL) || IS_ADC_CHANNEL3(CHANNEL)) + + +#define ADC_TRIG_SOFTWARE (1UL << 0) + +#if (LIBCFG_ADC_SW_TRIGGER_ONLY) +#define IS_ADC_TRIG(REGTRIG) ((REGTRIG) == ADC_TRIG_SOFTWARE) +#else +/* ((ADCTCR[4] << 4) | (ADCTSR[20] << 20)) */ +#if (LIBCFG_CMP) +#define ADC_TRIG_CMP0 ((1UL << 4) | (0UL << 20)) +#define ADC_TRIG_CMP1 ((1UL << 4) | (1UL << 20)) +#endif + +/* ((ADCTCR[3] << 3) | (ADCTSR[23:22] << 22) | (ADCTSR[19] << 19)) */ +#define ADC_TRIG_BFTM0 ((1UL << 3) | (0UL << 22) | (0UL << 19)) +#if (LIBCFG_BFTM1) +#define ADC_TRIG_BFTM1 ((1UL << 3) | (0UL << 22) | (1UL << 19)) +#endif + +/* ((ADCTCR[3] << 3) | (ADCTSR[29:27]) << 27) | (ADCTSR[23:22] << 22) | (ADCTSR[19] << 19)) */ +#if (LIBCFG_PWM0) +#define ADC_TRIG_PWM0_MTO ((1UL << 3) | (0UL << 27) | (1UL << 22) | (0UL << 19)) +#define ADC_TRIG_PWM0_CH0O ((1UL << 3) | (1UL << 27) | (1UL << 22) | (0UL << 19)) +#define ADC_TRIG_PWM0_CH1O ((1UL << 3) | (2UL << 27) | (1UL << 22) | (0UL << 19)) +#define ADC_TRIG_PWM0_CH2O ((1UL << 3) | (3UL << 27) | (1UL << 22) | (0UL << 19)) +#define ADC_TRIG_PWM0_CH3O ((1UL << 3) | (4UL << 27) | (1UL << 22) | (0UL << 19)) +#endif +#if (LIBCFG_PWM1) +#define ADC_TRIG_PWM1_MTO ((1UL << 3) | (0UL << 27) | (1UL << 22) | (1UL << 19)) +#define ADC_TRIG_PWM1_CH0O ((1UL << 3) | (1UL << 27) | (1UL << 22) | (1UL << 19)) +#define ADC_TRIG_PWM1_CH1O ((1UL << 3) | (2UL << 27) | (1UL << 22) | (1UL << 19)) +#define ADC_TRIG_PWM1_CH2O ((1UL << 3) | (3UL << 27) | (1UL << 22) | (1UL << 19)) +#define ADC_TRIG_PWM1_CH3O ((1UL << 3) | (4UL << 27) | (1UL << 22) | (1UL << 19)) +#endif + +/* ((ADCTCR[2] << 2) | (ADCTSR[26:24] << 24) | (ADCTSR[18:16] << 16)) */ +#if (LIBCFG_MCTM0) +#define ADC_TRIG_MCTM0_MTO ((1UL << 2) | (0UL << 24) | (0UL << 16)) +#define ADC_TRIG_MCTM0_CH0O ((1UL << 2) | (1UL << 24) | (0UL << 16)) +#define ADC_TRIG_MCTM0_CH1O ((1UL << 2) | (2UL << 24) | (0UL << 16)) +#define ADC_TRIG_MCTM0_CH2O ((1UL << 2) | (3UL << 24) | (0UL << 16)) +#define ADC_TRIG_MCTM0_CH3O ((1UL << 2) | (4UL << 24) | (0UL << 16)) +#endif + +#if (LIBCFG_NO_GPTM0) +#define IS_ADC_TRIG_GPTM0(x) (0) +#else +#define ADC_TRIG_GPTM0_MTO ((1UL << 2) | (0UL << 24) | (2UL << 16)) +#define ADC_TRIG_GPTM0_CH0O ((1UL << 2) | (1UL << 24) | (2UL << 16)) +#define ADC_TRIG_GPTM0_CH1O ((1UL << 2) | (2UL << 24) | (2UL << 16)) +#define ADC_TRIG_GPTM0_CH2O ((1UL << 2) | (3UL << 24) | (2UL << 16)) +#define ADC_TRIG_GPTM0_CH3O ((1UL << 2) | (4UL << 24) | (2UL << 16)) + +#define IS_ADC_TRIG_GPTM0(x) (((x) == ADC_TRIG_GPTM0_MTO) || \ + ((x) == ADC_TRIG_GPTM0_CH0O) || \ + ((x) == ADC_TRIG_GPTM0_CH1O) || \ + ((x) == ADC_TRIG_GPTM0_CH2O) || \ + ((x) == ADC_TRIG_GPTM0_CH3O)) +#endif + +#if (LIBCFG_GPTM1) +#define ADC_TRIG_GPTM1_MTO ((1UL << 2) | (0UL << 24) | (3UL << 16)) +#define ADC_TRIG_GPTM1_CH0O ((1UL << 2) | (1UL << 24) | (3UL << 16)) +#define ADC_TRIG_GPTM1_CH1O ((1UL << 2) | (2UL << 24) | (3UL << 16)) +#define ADC_TRIG_GPTM1_CH2O ((1UL << 2) | (3UL << 24) | (3UL << 16)) +#define ADC_TRIG_GPTM1_CH3O ((1UL << 2) | (4UL << 24) | (3UL << 16)) +#endif + +/* (ADCTCR[1] << 1) | (ADCTSR[11:8] << 8) */ +#define ADC_TRIG_EXTI_0 ((1UL << 1) | ( 0UL << 8)) +#define ADC_TRIG_EXTI_1 ((1UL << 1) | ( 1UL << 8)) +#define ADC_TRIG_EXTI_2 ((1UL << 1) | ( 2UL << 8)) +#define ADC_TRIG_EXTI_3 ((1UL << 1) | ( 3UL << 8)) +#define ADC_TRIG_EXTI_4 ((1UL << 1) | ( 4UL << 8)) +#define ADC_TRIG_EXTI_5 ((1UL << 1) | ( 5UL << 8)) +#define ADC_TRIG_EXTI_6 ((1UL << 1) | ( 6UL << 8)) +#define ADC_TRIG_EXTI_7 ((1UL << 1) | ( 7UL << 8)) +#define ADC_TRIG_EXTI_8 ((1UL << 1) | ( 8UL << 8)) +#define ADC_TRIG_EXTI_9 ((1UL << 1) | ( 9UL << 8)) +#define ADC_TRIG_EXTI_10 ((1UL << 1) | (10UL << 8)) +#define ADC_TRIG_EXTI_11 ((1UL << 1) | (11UL << 8)) +#define ADC_TRIG_EXTI_12 ((1UL << 1) | (12UL << 8)) +#define ADC_TRIG_EXTI_13 ((1UL << 1) | (13UL << 8)) +#define ADC_TRIG_EXTI_14 ((1UL << 1) | (14UL << 8)) +#define ADC_TRIG_EXTI_15 ((1UL << 1) | (15UL << 8)) + +#define IS_ADC_TRIG(REGTRIG) (IS_ADC_TRIG1(REGTRIG) || \ + IS_ADC_TRIG2(REGTRIG) || \ + IS_ADC_TRIG3(REGTRIG) || \ + IS_ADC_TRIG4(REGTRIG) || \ + IS_ADC_TRIG5(REGTRIG) || \ + IS_ADC_TRIG6(REGTRIG) || \ + IS_ADC_TRIG7(REGTRIG)) + +#define IS_ADC_TRIG1(REGTRIG) (IS_ADC_TRIG_GPTM0(REGTRIG) || \ + ((REGTRIG) == ADC_TRIG_BFTM0) || \ + ((REGTRIG) == ADC_TRIG_EXTI_0) || \ + ((REGTRIG) == ADC_TRIG_EXTI_1) || \ + ((REGTRIG) == ADC_TRIG_EXTI_2) || \ + ((REGTRIG) == ADC_TRIG_EXTI_3) || \ + ((REGTRIG) == ADC_TRIG_EXTI_4) || \ + ((REGTRIG) == ADC_TRIG_EXTI_5) || \ + ((REGTRIG) == ADC_TRIG_EXTI_6) || \ + ((REGTRIG) == ADC_TRIG_EXTI_7) || \ + ((REGTRIG) == ADC_TRIG_EXTI_8) || \ + ((REGTRIG) == ADC_TRIG_EXTI_9) || \ + ((REGTRIG) == ADC_TRIG_EXTI_10) || \ + ((REGTRIG) == ADC_TRIG_EXTI_11) || \ + ((REGTRIG) == ADC_TRIG_EXTI_12) || \ + ((REGTRIG) == ADC_TRIG_EXTI_13) || \ + ((REGTRIG) == ADC_TRIG_EXTI_14) || \ + ((REGTRIG) == ADC_TRIG_EXTI_15) || \ + ((REGTRIG) == ADC_TRIG_SOFTWARE)) + +#if (LIBCFG_BFTM1) +#define IS_ADC_TRIG2(REGTRIG) ((REGTRIG) == ADC_TRIG_BFTM1) +#else +#define IS_ADC_TRIG2(REGTRIG) (0) +#endif + +#if (LIBCFG_MCTM0) +#define IS_ADC_TRIG3(REGTRIG) (((REGTRIG) == ADC_TRIG_MCTM0_MTO) || \ + ((REGTRIG) == ADC_TRIG_MCTM0_CH0O) || \ + ((REGTRIG) == ADC_TRIG_MCTM0_CH1O) || \ + ((REGTRIG) == ADC_TRIG_MCTM0_CH2O) || \ + ((REGTRIG) == ADC_TRIG_MCTM0_CH3O) || \ + ((REGTRIG) == ADC_TRIG_BFTM1)) +#else +#define IS_ADC_TRIG3(REGTRIG) (0) +#endif + +#if (LIBCFG_GPTM1) +#define IS_ADC_TRIG4(REGTRIG) (((REGTRIG) == ADC_TRIG_GPTM1_MTO) || \ + ((REGTRIG) == ADC_TRIG_GPTM1_CH0O) || \ + ((REGTRIG) == ADC_TRIG_GPTM1_CH1O) || \ + ((REGTRIG) == ADC_TRIG_GPTM1_CH2O) || \ + ((REGTRIG) == ADC_TRIG_GPTM1_CH3O)) +#else +#define IS_ADC_TRIG4(REGTRIG) (0) +#endif + +#if (LIBCFG_PWM0) +#define IS_ADC_TRIG5(REGTRIG) (((REGTRIG) == ADC_TRIG_PWM0_MTO) || \ + ((REGTRIG) == ADC_TRIG_PWM0_CH0O) || \ + ((REGTRIG) == ADC_TRIG_PWM0_CH1O) || \ + ((REGTRIG) == ADC_TRIG_PWM0_CH2O) || \ + ((REGTRIG) == ADC_TRIG_PWM0_CH3O)) +#else +#define IS_ADC_TRIG5(REGTRIG) (0) +#endif + +#if (LIBCFG_PWM1) +#define IS_ADC_TRIG6(REGTRIG) (((REGTRIG) == ADC_TRIG_PWM1_MTO) || \ + ((REGTRIG) == ADC_TRIG_PWM1_CH0O) || \ + ((REGTRIG) == ADC_TRIG_PWM1_CH1O) || \ + ((REGTRIG) == ADC_TRIG_PWM1_CH2O) || \ + ((REGTRIG) == ADC_TRIG_PWM1_CH3O)) +#else +#define IS_ADC_TRIG6(REGTRIG) (0) +#endif + +#if (LIBCFG_CMP) +#define IS_ADC_TRIG7(REGTRIG) (((REGTRIG) == ADC_TRIG_CMP0) || \ + ((REGTRIG) == ADC_TRIG_CMP1)) +#else +#define IS_ADC_TRIG7(REGTRIG) (0) +#endif +#endif + +#define ADC_INT_SINGLE_EOC (0x00000001) +#if (LIBCFG_ADC_NO_DISCON_MODE == 0) +#define ADC_INT_SUB_GROUP_EOC (0x00000002) +#endif +#define ADC_INT_CYCLE_EOC (0x00000004) +#if (LIBCFG_ADC_NO_WDT == 0) +#define ADC_INT_AWD_LOWER (0x00010000) +#define ADC_INT_AWD_UPPER (0x00020000) +#endif +#define ADC_INT_DATA_OVERWRITE (0x01000000) + +#define IS_ADC_INT(INT) ((((INT) & 0xFEFCFFF8) == 0) && ((INT) != 0)) + + +#define ADC_FLAG_SINGLE_EOC (0x00000001) +#if (LIBCFG_ADC_NO_DISCON_MODE == 0) +#define ADC_FLAG_SUB_GROUP_EOC (0x00000002) +#endif +#define ADC_FLAG_CYCLE_EOC (0x00000004) +#if (LIBCFG_ADC_NO_WDT == 0) +#define ADC_FLAG_AWD_LOWER (0x00010000) +#define ADC_FLAG_AWD_UPPER (0x00020000) +#endif +#define ADC_FLAG_DATA_OVERWRITE (0x01000000) + +#define IS_ADC_FLAG(FLAG) ((((FLAG) & 0xFEFCFFF8) == 0) && ((FLAG) != 0)) + + +#define ADC_REGULAR_DATA0 (0) +#define ADC_REGULAR_DATA1 (1) +#define ADC_REGULAR_DATA2 (2) +#define ADC_REGULAR_DATA3 (3) +#if (LIBCFG_ADC_NO_SEQ_4_7 == 0) +#define ADC_REGULAR_DATA4 (4) +#define ADC_REGULAR_DATA5 (5) +#define ADC_REGULAR_DATA6 (6) +#define ADC_REGULAR_DATA7 (7) +#endif + +#if (LIBCFG_ADC_NO_SEQ_4_7) +#define IS_ADC_REGULAR_DATA(DATA) ((DATA) < 4) +#else +#define IS_ADC_REGULAR_DATA(DATA) ((DATA) < 8) +#endif + +#define ADC_AWD_DISABLE (u8)0x00 +#define ADC_AWD_ALL_LOWER (u8)0x05 +#define ADC_AWD_ALL_UPPER (u8)0x06 +#define ADC_AWD_ALL_LOWER_UPPER (u8)0x07 +#define ADC_AWD_SINGLE_LOWER (u8)0x01 +#define ADC_AWD_SINGLE_UPPER (u8)0x02 +#define ADC_AWD_SINGLE_LOWER_UPPER (u8)0x03 + +#define IS_ADC_AWD(AWD) (((AWD) == ADC_AWD_DISABLE) || \ + ((AWD) == ADC_AWD_ALL_LOWER) || \ + ((AWD) == ADC_AWD_ALL_UPPER) || \ + ((AWD) == ADC_AWD_ALL_LOWER_UPPER) || \ + ((AWD) == ADC_AWD_SINGLE_LOWER) || \ + ((AWD) == ADC_AWD_SINGLE_UPPER) || \ + ((AWD) == ADC_AWD_SINGLE_LOWER_UPPER)) + +#define IS_ADC_THRESHOLD(THRESHOLD) ((THRESHOLD) < 4096) + +#if (LIBCFG_PDMA) +#define ADC_PDMA_REGULAR_SINGLE (0x00000001) +#define ADC_PDMA_REGULAR_SUBGROUP (0x00000002) +#define ADC_PDMA_REGULAR_CYCLE (0x00000004) + +#define IS_ADC_PDMA(PDMA) (((PDMA) == ADC_PDMA_REGULAR_SINGLE) || \ + ((PDMA) == ADC_PDMA_REGULAR_SUBGROUP) || \ + ((PDMA) == ADC_PDMA_REGULAR_CYCLE)) +#endif + +#define IS_ADC_INPUT_SAMPLING_TIME(TIME) ((TIME) <= 255) + +#define IS_ADC_OFFSET(OFFSET) ((OFFSET) < 4096) + + +#if (LIBCFG_ADC_NO_SEQ_4_7) +#define IS_ADC_REGULAR_RANK(RANK) ((RANK) < 4) +#define IS_ADC_REGULAR_LENGTH(LENGTH) (((LENGTH) >= 1) && ((LENGTH) <= 4)) +#else +#define IS_ADC_REGULAR_RANK(RANK) ((RANK) < 8) +#define IS_ADC_REGULAR_LENGTH(LENGTH) (((LENGTH) >= 1) && ((LENGTH) <= 8)) +#endif +#define IS_ADC_REGULAR_SUB_LENGTH(SUB_LENGTH) (((SUB_LENGTH) >= 1) && ((SUB_LENGTH) <= 8)) + +#if (LIBCFG_ADC_IVREF) +#if (LIBCFG_ADC_IVREF_LEVEL_TYPE2) +#define ADC_VREF_2V5 (0ul << 4) +#define ADC_VREF_3V0 (1ul << 4) +#define ADC_VREF_4V0 (2ul << 4) +#define ADC_VREF_4V5 (3ul << 4) + +#define IS_ADC_VREF_SEL(SEL) ((SEL == ADC_VREF_2V5) || \ + (SEL == ADC_VREF_3V0) || \ + (SEL == ADC_VREF_4V0) || \ + (SEL == ADC_VREF_4V5)) +#else + #if LIBCFG_ADC_IVREF_DEFAULT_08V + #define ADC_VREF_0V8 (0ul << 4) + #define ADC_VREF_DEFAULT ADC_VREF_0V8 + #else + #define ADC_VREF_1V215 (0ul << 4) + #define ADC_VREF_DEFAULT ADC_VREF_1V215 + #endif +#define ADC_VREF_2V0 (1ul << 4) +#define ADC_VREF_2V5 (2ul << 4) +#define ADC_VREF_2V7 (3ul << 4) + +#define IS_ADC_VREF_SEL(SEL) ((SEL == ADC_VREF_DEFAULT) || \ + (SEL == ADC_VREF_2V0) || \ + (SEL == ADC_VREF_2V5) || \ + (SEL == ADC_VREF_2V7)) +#endif +#endif + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------------------------------------*/ +/** @defgroup ADC_Exported_Functions ADC exported functions + * @{ + */ +void ADC_DeInit(HT_ADC_TypeDef* HT_ADCn); +void ADC_Reset(HT_ADC_TypeDef* HT_ADCn); +void ADC_Cmd(HT_ADC_TypeDef* HT_ADCn, ControlStatus NewState); + +void ADC_SamplingTimeConfig(HT_ADC_TypeDef* HT_ADCn, u8 SampleClock); +void ADC_RegularChannelConfig(HT_ADC_TypeDef* HT_ADCn, u8 ADC_CH_n, u8 Rank, ...); +void ADC_RegularGroupConfig(HT_ADC_TypeDef* HT_ADCn, u8 ADC_MODE, u8 Length, u8 SubLength); +void ADC_RegularTrigConfig(HT_ADC_TypeDef* HT_ADCn, u32 ADC_TRIG_x); + +void ADC_SoftwareStartConvCmd(HT_ADC_TypeDef* HT_ADCn, ControlStatus NewState); + +u16 ADC_GetConversionData(HT_ADC_TypeDef* HT_ADCn, u8 ADC_REGULAR_DATAn); + +void ADC_IntConfig(HT_ADC_TypeDef* HT_ADCn, u32 ADC_INT_x, ControlStatus NewState); +FlagStatus ADC_GetIntStatus(HT_ADC_TypeDef* HT_ADCn, u32 ADC_INT_x); +void ADC_ClearIntPendingBit(HT_ADC_TypeDef* HT_ADCn, u32 ADC_INT_x); +FlagStatus ADC_GetFlagStatus(HT_ADC_TypeDef* HT_ADCn, u32 ADC_FLAG_x); + +#if (LIBCFG_ADC_NO_WDT) +#else +void ADC_AWDConfig(HT_ADC_TypeDef* HT_ADCn, u32 ADC_AWD_x); +void ADC_AWDSingleChannelConfig(HT_ADC_TypeDef* HT_ADCn, u8 ADC_CH_n); +void ADC_AWDThresholdsConfig(HT_ADC_TypeDef* HT_ADCn, u16 UPPER, u16 LOWER); +#endif + +#if (LIBCFG_PDMA) +void ADC_PDMAConfig(HT_ADC_TypeDef* HT_ADCn, u32 ADC_PDMA_x, ControlStatus NewState); +#endif + +#if (LIBCFG_ADC_IVREF) +void ADC_VREFCmd(HT_ADC_TypeDef* HT_ADCn, ControlStatus NewState); +void ADC_VREFConfig(HT_ADC_TypeDef* HT_ADCn, u32 ADC_VREF_x); +#endif + +#if (LIBCFG_ADC_VREFBUF) +void ADC_VREFOutputCmd(HT_ADC_TypeDef* HT_ADCn, ControlStatus NewState); +#endif + +#if (LIBCFG_ADC_MVDDA) +void ADC_MVDDACmd(HT_ADC_TypeDef* HT_ADCn, ControlStatus NewState); +#endif +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f5xxxx_aes.h b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f5xxxx_aes.h new file mode 100644 index 0000000000..ec7db17443 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f5xxxx_aes.h @@ -0,0 +1,209 @@ +/*********************************************************************************************************//** + * @file ht32f5xxxx_aes.h + * @version $Rev:: 7390 $ + * @date $Date:: 2023-12-12 #$ + * @brief The header file of the ADC library. + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------------------------------------*/ +#ifndef __HT32F5XXXX_AES_H +#define __HT32F5XXXX_AES_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------------------------------------*/ +#include "ht32.h" + +/** @addtogroup HT32F5xxxx_Peripheral_Driver HT32F5xxxx Peripheral Driver + * @{ + */ + +/** @addtogroup AES + * @{ + */ + + +/* Exported types ------------------------------------------------------------------------------------------*/ +/** @defgroup AES_Exported_Types AES exported types + * @{ + */ + +/** + * @brief Definition of AES Init Structure + */ +typedef struct +{ + u16 AES_KeySize; + u16 AES_Dir; + u16 AES_Mode; + u16 AES_Swap; +} AES_InitTypeDef; +/** + * @} + */ + +/* Exported constants --------------------------------------------------------------------------------------*/ +/** @defgroup AES_Exported_Constants AES exported constants + * @{ + */ + +#define IS_AES(AES) (AES == HT_AES) + +/* Definitions of AES key size */ +#define AES_KEYSIZE_128B ((u32)0x00000000) +#define IS_AES_KEY_SIZE1(SIZE) (SIZE == AES_KEYSIZE_128B) + +#if (LIBCFG_AES_KEYSIZE_256B) +#define AES_KEYSIZE_192B ((u32)0x00000020) +#define AES_KEYSIZE_256B ((u32)0x00000040) +#define IS_AES_KEY_SIZE2(SIZE) ((SIZE == AES_KEYSIZE_192B) || (SIZE == AES_KEYSIZE_256B)) +#else +#define IS_AES_KEY_SIZE2(SIZE) (0) +#endif + +#define IS_AES_KEY_SIZE(SIZE) (IS_AES_KEY_SIZE1(SIZE) || IS_AES_KEY_SIZE2(SIZE)) + +/* Definitions of AES direction */ +typedef enum +{ + AES_DIR_ENCRYPT =0, + AES_DIR_DECRYPT =2 +} AES_DIR_Enum; + +#define IS_AES_DIR(DIR) ((DIR == AES_DIR_ENCRYPT) || (DIR == AES_DIR_DECRYPT)) + +/* Definitions of AES mode */ +#define AES_MODE_ECB ((u32)0x00000000) +#define AES_MODE_CBC ((u32)0x00000004) +#define AES_MODE_CTR ((u32)0x00000008) + +#define IS_AES_MODE(MODE) ((MODE == AES_MODE_ECB) || (MODE == AES_MODE_CBC) || (MODE == AES_MODE_CTR)) + +/* Definitions of AES key start */ +#define AES_KEYSTART_DISABLE ((u32)0x00000000) +#define AES_KEYSTART_ENABLE ((u32)0x00000010) + +#define IS_AES_KEYSTART(KEYSTART) ((KEYSTART == AES_KEYSTART_DISABLE) || (KEYSTART == AES_KEYSTART_ENABLE)) + +/* Definitions of AES swap */ +#define AES_SWAP_DISABLE ((u32)0x00000000) +#define AES_SWAP_ENABLE ((u32)0x00000100) + +#define IS_AES_SWAP(SWAP) ((SWAP == AES_SWAP_DISABLE) || (SWAP == AES_SWAP_ENABLE)) + +/* Definitions of AES flush */ +#define AES_FLUSH_DISABLE ((u32)0x00000000) +#define AES_FLUSH_ENABLE ((u32)0x00000400) + +#define IS_AES_FLUSH(FLUSH) ((FLUSH == AES_FLUSH_DISABLE) || (FLUSH == AES_FLUSH_ENABLE)) + +/* Definitions of AES Enable */ +#define AES_DISABLE ((u32)0x00000000) +#define AES_ENABLE ((u32)0x00000001) + +#define IS_AES_CMD(CMD) ((CMD == AES_DISABLE) || (CMD == AES_ENABLE)) + +/* Definitions of AES status */ +#define AES_SR_IFEMPTY ((u32)0x00000001) +#define AES_SR_IFNFULL ((u32)0x00000002) +#define AES_SR_OFNEMPTY ((u32)0x00000004) +#define AES_SR_OFFULL ((u32)0x00000008) +#define AES_SR_BUSY ((u32)0x00000010) + +#define IS_AES_STATUS(STATUS) ((STATUS == AES_SR_IFEMPTY) || \ + (STATUS == AES_SR_IFNFULL) || \ + (STATUS == AES_SR_OFNEMPTY) || \ + (STATUS == AES_SR_OFFULL) || \ + (STATUS == AES_SR_BUSY)) + +/* Definitions of AES PDMA */ +#define AES_PDMA_IFDMAEN ((u32)0x00000001) +#define AES_PDMA_OFDMAEN ((u32)0x00000002) + +#define IS_AES_PDMA(AES_PDMA) ((AES_PDMA == AES_PDMA_IFDMAEN) || (AES_PDMA == AES_PDMA_OFDMAEN)) + +/* Definitions of AES Interrupt Status */ +#define AES_INTSR_IFINT ((u32)0x00000001) +#define AES_INTSR_OFINT ((u32)0x00000002) + +#define IS_AES_INTSR(AES_INSR) ((AES_INSR == AES_INTSR_IFINT) || (AES_INSR == AES_INTSR_OFINT)) + +/* Definitions of AES interrupt enable */ +#define AES_IER_IFINTEN ((u32)0x00000001) +#define AES_IER_OFINTEN ((u32)0x00000002) + +#define IS_AES_IER(ARS_IER) ((ARS_IER == AES_IER_IFINTEN) || (ARS_IER == AES_IER_OFINTEN)) +/** + * @} + */ + +/* Exported functions --------------------------------------------------------------------------------------*/ +/** @defgroup AES_Exported_Functions AES exported functions + * @{ + */ +void AES_ECB_Init(HT_AES_TypeDef* HT_AESn, AES_InitTypeDef* AES_InitStruct); +void AES_CBC_Init(HT_AES_TypeDef* HT_AESn, AES_InitTypeDef* AES_InitStruct); +void AES_CTR_Init(HT_AES_TypeDef* HT_AESn, AES_InitTypeDef* AES_InitStruct); +void AES_SetKeyTable(HT_AES_TypeDef* HT_AESn, u32 *Key, u32 keySize); +ErrStatus _AES_CryptData(HT_AES_TypeDef* HT_AESn, AES_DIR_Enum dir, u32 *iv, u32 length, u32 *inputData, u32 *outputData); +#define AES_ECB_CryptData(a, b, c, d, e) _AES_CryptData(a, b, NULL, c, d, e) +#define AES_CBC_CryptData _AES_CryptData +#define AES_CTR_CryptData(a, b, c, d, e) _AES_CryptData(a, AES_DIR_ENCRYPT, b, c, d, e) +#if 0 +ErrStatus AES_ECB_CryptData(HT_AES_TypeDef* HT_AESn, AES_DIR_Enum mode, u32 length, u32 *inputData, u32 *outputData); +ErrStatus AES_CBC_CryptData(HT_AES_TypeDef* HT_AESn, AES_DIR_Enum mode, u32 *iv, u32 length, u32 *inputData, u32 *outputData); +ErrStatus AES_CTR_CryptData(HT_AES_TypeDef* HT_AESn, u32 *iv, u32 length, u32 *inputData, u32 *outputData); +#endif + +void AES_StartKey(HT_AES_TypeDef* HT_AESn); +void AES_DeInit(HT_AES_TypeDef* HT_AESn); +void AES_FIFOFlush(HT_AES_TypeDef* HT_AESn); +void AES_Cmd(HT_AES_TypeDef* HT_AESn, ControlStatus NewState); +FlagStatus AES_GetStatus(HT_AES_TypeDef* HT_AESn, u32 AES_Status); +void AES_PDMACmd(HT_AES_TypeDef* HT_AESn, u32 AES_PDMA_xFDMAEN, ControlStatus NewState); +FlagStatus AES_GetIntStatus(HT_AES_TypeDef* HT_AESn, u32 AES_INTSR_x); +void AES_IntConfig(HT_AES_TypeDef* HT_AESn, u32 AES_IER_x, ControlStatus NewState); +void AES_SetInputData(HT_AES_TypeDef* HT_AESn, uc32 AES_Data); +u32 AES_GetOutputData(HT_AES_TypeDef* HT_AESn); +void AES_SetVectorTable(HT_AES_TypeDef* HT_AESn, u32 *Vector); +void AESCore_IRQHandler(HT_AES_TypeDef* HT_AESn); +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f5xxxx_bftm.h b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f5xxxx_bftm.h new file mode 100644 index 0000000000..5b6e6c904c --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f5xxxx_bftm.h @@ -0,0 +1,111 @@ +/*********************************************************************************************************//** + * @file ht32f5xxxx_bftm.h + * @version $Rev:: 6393 $ + * @date $Date:: 2022-10-27 #$ + * @brief The header file of the BFTM library. + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------------------------------------*/ +#ifndef __HT32F5XXXX_BFTM_H +#define __HT32F5XXXX_BFTM_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------------------------------------*/ +#include "ht32.h" + +/** @addtogroup HT32F5xxxx_Peripheral_Driver HT32F5xxxx Peripheral Driver + * @{ + */ + +/** @addtogroup BFTM + * @{ + */ + +/* Exported types ------------------------------------------------------------------------------------------*/ +/** @defgroup BFTM_Exported_Types BFTM exported types + * @{ + */ +#if (LIBCFG_BFTM_16BIT_COUNTER) +typedef u16 BFTM_DataTypeDef; +#else +typedef u32 BFTM_DataTypeDef; +#endif +/** + * @} + */ + +/* Exported constants --------------------------------------------------------------------------------------*/ +/** @defgroup BFTM_Exported_Constants BFTM exported constants + * @{ + */ +#define IS_BFTM(x) (IS_BFTM0(x) || IS_BFTM1(x)) + +#define IS_BFTM0(x) (x == HT_BFTM0) + +#if (LIBCFG_BFTM1) +#define IS_BFTM1(x) (x == HT_BFTM1) +#else +#define IS_BFTM1(x) (0) +#endif + +#define BFTM_FLAG_MATCH (1UL << 0) +#define BFTM_INT_MATCH (1UL << 0) +/** + * @} + */ + +/* Exported functions --------------------------------------------------------------------------------------*/ +/** @defgroup BFTM_Exported_Functions BFTM exported functions + * @{ + */ +void BFTM_DeInit(HT_BFTM_TypeDef* HT_BFTMn); +void BFTM_EnaCmd(HT_BFTM_TypeDef* HT_BFTMn, ControlStatus NewState); +void BFTM_SetCompare(HT_BFTM_TypeDef* HT_BFTMn, BFTM_DataTypeDef uCompare); +u32 BFTM_GetCompare(HT_BFTM_TypeDef* HT_BFTMn); +void BFTM_SetCounter(HT_BFTM_TypeDef* HT_BFTMn, BFTM_DataTypeDef uCounter); +u32 BFTM_GetCounter(HT_BFTM_TypeDef* HT_BFTMn); +void BFTM_OneShotModeCmd(HT_BFTM_TypeDef* HT_BFTMn, ControlStatus NewState); +void BFTM_IntConfig(HT_BFTM_TypeDef* HT_BFTMn, ControlStatus NewState); +FlagStatus BFTM_GetFlagStatus(HT_BFTM_TypeDef* HT_BFTMn); +void BFTM_ClearFlag(HT_BFTM_TypeDef* HT_BFTMn); +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f5xxxx_can.h b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f5xxxx_can.h new file mode 100644 index 0000000000..a66d141dd7 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f5xxxx_can.h @@ -0,0 +1,498 @@ +/*********************************************************************************************************//** + * @file ht32f5xxxx_can.h + * @version $Rev:: 7188 $ + * @date $Date:: 2023-08-31 #$ + * @brief The header file of the CAN library. + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------------------------------------*/ +#ifndef __HT32F5XXXX_CAN_H +#define __HT32F5XXXX_CAN_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------------------------------------*/ +#include "ht32.h" + +/** @addtogroup HT32F5xxxx_Peripheral_Driver HT32F5xxxx Peripheral Driver + * @{ + */ + +/** @addtogroup CAN + * @{ + */ + +/* Exported types ------------------------------------------------------------------------------------------*/ +/** @defgroup CAN_Exported_Types CAN exported types + * @{ + */ + +/** + * @brief CAN message structure + */ +typedef struct +{ + u32 IdType; + u32 FrameType; + u32 Id; + u32 DLC; +} STR_CANMSG_TypeDef; + +/** + * @brief CAN TX message structure + */ +typedef struct +{ + u32 IdType; + u32 FrameType; + u32 Id; + u32 MCR; + u32 DLC; + u32 EOB; + u32 RMTEN; + u32 UMASK; + u32 Data[8]; +} STR_CANMSG_T_TypeDef; + +/** + * @brief CAN RX message structure + */ +typedef struct +{ + u32 IdType; + u32 Id; + u32 u8Xtd; + u32 u8Dir; + u32 MCR; + u32 MASK0; + u32 MASK1; + u32 EOB; + u32 UMASK; + u32 RMTEN; + u32 DIR; /* For receive remote frame. */ + } STR_CANMSG_R_TypeDef; + +/** + * @brief CAN mask message structure + */ +typedef struct +{ + u32 u8Xtd; + u32 u8Dir; + u32 u32Id; + u32 u8IdType; +} STR_CANMASK_TyprDef; +/** + * @} + */ + +/* Exported constants --------------------------------------------------------------------------------------*/ +/** @defgroup CAN_Exported_Constants CAN exported constants + * @{ + */ +#define IS_CAN(x) IS_CAN0(x) +#define IS_CAN0(x) (x == HT_CAN0) + +/** + * @brief CAN Test Mode Constant Definitions + */ +#define CAN_NORMAL_MODE 0 +#define CAN_BASIC_MODE 0x04 +#define CAN_SILENT_MODE 0x08 +#define CAN_LBACK_MODE 0x10 +#define CAN_LBS_MODE 0x18 + +/** + * @brief DMessage ID Type Constant Definitions + */ +#define CAN_STD_ID 0 +#define CAN_EXT_ID 1 + +/** + * @brief Message Frame Type Constant Definitions + */ +#define CAN_REMOTE_FRAME 0 +#define CAN_DATA_FRAME 1 + +#define CAN_NBR 1 +#define CAN_VECTOR_NBR 1 +#define DATA_NBR 4 + +/** + * @brief CAN CR Bit Field Definitions + */ +#define CAN_CR_TEST_Pos 7 /*!< CAN_T::CR: TEST Position */ +#define CAN_CR_TEST_Msk (1ul << CAN_CR_TEST_Pos) /*!< CAN_T::CR: TEST Mask */ + +#define CAN_CR_CCE_Pos 6 /*!< CAN_T::CR: CCE Position */ +#define CAN_CR_CCE_Msk (1ul << CAN_CR_CCE_Pos) /*!< CAN_T::CR: CCE Mask */ + +#define CAN_CR_DAR_Pos 5 /*!< CAN_T::CR: DAR Position */ +#define CAN_CR_DAR_Msk (1ul << CAN_CR_DAR_Pos) /*!< CAN_T::CR: DAR Mask */ + +#define CAN_CR_EIE_Pos 3 /*!< CAN_T::CR: EIE Position */ +#define CAN_CR_EIE_Msk (1ul << CAN_CR_EIE_Pos) /*!< CAN_T::CR: EIE Mask */ + +#define CAN_CR_SIE_Pos 2 /*!< CAN_T::CR: SIE Position */ +#define CAN_CR_SIE_Msk (1ul << CAN_CR_SIE_Pos) /*!< CAN_T::CR SIE Mask */ + +#define CAN_CR_IE_Pos 1 /*!< CAN_T::CR: IE Position */ +#define CAN_CR_IE_Msk (1ul << CAN_CR_IE_Pos) /*!< CAN_T::CR: IE Mask */ + +#define CAN_CR_INIT_Pos 0 /*!< CAN_T::CR: INIT Position */ +#define CAN_CR_INIT_Msk (1ul << CAN_CR_INIT_Pos) /*!< CAN_T::CR: INIT Mask */ + +/** + * @brief CAN STATUS Bit Field Definitions + */ +#define CAN_SR_BOFF_Pos 7 /*!< CAN_T::STATUS: BOFF Position */ +#define CAN_SR_BOFF_Msk (1ul << CAN_SR_BOFF_Pos) /*!< CAN_T::STATUS: BOFF Mask */ + +#define CAN_SR_EWARN_Pos 6 /*!< CAN_T::STATUS: EWARN Position */ +#define CAN_SR_EWARN_Msk (1ul << CAN_SR_EWARN_Pos) /*!< CAN_T::STATUS: EWARN Mask */ + +#define CAN_SR_EPASS_Pos 5 /*!< CAN_T::STATUS: EPASS Position */ +#define CAN_SR_EPASS_Msk (1ul << CAN_SR_EPASS_Pos) /*!< CAN_T::STATUS: EPASS Mask */ + +#define CAN_SR_RXOK_Pos 4 /*!< CAN_T::STATUS: RXOK Position */ +#define CAN_SR_RXOK_Msk (1ul << CAN_SR_RXOK_Pos) /*!< CAN_T::STATUS: RXOK Mask */ + +#define CAN_SR_TXOK_Pos 3 /*!< CAN_T::STATUS: TXOK Position */ +#define CAN_SR_TXOK_Msk (1ul << CAN_SR_TXOK_Pos) /*!< CAN_T::STATUS: TXOK Mask */ + +#define CAN_SR_LEC_Pos 0 /*!< CAN_T::STATUS: LEC Position */ +#define CAN_SR_LEC_Msk (0x3ul << CAN_SR_LEC_Pos) /*!< CAN_T::STATUS: LEC Mask */ + +/** + * @brief CAN ECR Bit Field Definitions + */ +#define CAN_ECR_RP_Pos 15 /*!< CAN_T::ECR: RP Position */ +#define CAN_ECR_RP_Msk (1ul << CAN_ECR_RP_Pos) /*!< CAN_T::ECR: RP Mask */ + +#define CAN_ECR_REC_Pos 8 /*!< CAN_T::ECR: REC Position */ +#define CAN_ECR_REC_Msk (0x7Ful << CAN_ECR_REC_Pos) /*!< CAN_T::ECR: REC Mask */ + +#define CAN_ECR_TEC_Pos 0 /*!< CAN_T::ECR: TEC Position */ +#define CAN_ECR_TEC_Msk (0xFFul << CAN_ECR_TEC_Pos) /*!< CAN_T::ECR: TEC Mask */ + +/** + * @brief CAN BTR Bit Field Definitions + */ +#define CAN_BTR_TSEG1_Pos 12 /*!< CAN_T::BTR: TSEG1 Position */ +#define CAN_BTR_TSEG1_Msk (0x7ul << CAN_BTR_TSEG1_Pos) /*!< CAN_T::BTR: TSEG1 Mask */ + +#define CAN_BTR_TSEG0_Pos 8 /*!< CAN_T::BTR: TSEG0 Position */ +#define CAN_BTR_TSEG0_Msk (0xFul << CAN_BTR_TSEG0_Pos) /*!< CAN_T::BTR: TSEG0 Mask */ + +#define CAN_BTR_SJW_Pos 6 /*!< CAN_T::BTR: SJW Position */ +#define CAN_BTR_SJW_Msk (0x3ul << CAN_BTR_SJW_Pos) /*!< CAN_T::BTR: SJW Mask */ + +#define CAN_BTR_BRP_Pos 0 /*!< CAN_T::BTR: BRP Position */ +#define CAN_BTR_BRP_Msk (0x3Ful << CAN_BTR_BRP_Pos) /*!< CAN_T::BTR: BRP Mask */ + +/** + * @brief CAN IR Bit Field Definitions + */ +#define CAN_IR_INTID_Pos 0 /*!< CAN_T::IR: INTID Position */ +#define CAN_IR_INTID_Msk (0xFFFFul << CAN_IR_INTID_Pos) /*!< CAN_T::R: INTID Mask */ + +/** + * @brief CAN TEST Bit Field Definitions + */ +#define CAN_TEST_RX_Pos 7 /*!< CAN_T::TEST: RX Position */ +#define CAN_TEST_RX_Msk (1ul << CAN_TEST_RX_Pos) /*!< CAN_T::TEST: RX Mask */ + +#define CAN_TEST_TX_Pos 5 /*!< CAN_T::TEST: TX Position */ +#define CAN_TEST_TX_Msk (0x3ul << CAN_TEST_TX_Pos) /*!< CAN_T::TEST: TX Mask */ + +#define CAN_TEST_LBACK_Pos 4 /*!< CAN_T::TEST: LBACK Position */ +#define CAN_TEST_LBACK_Msk (1ul << CAN_TEST_LBACK_Pos) /*!< CAN_T::TEST: LBACK Mask */ + +#define CAN_TEST_SILENT_Pos 3 /*!< CAN_T::TEST: Silent Position */ +#define CAN_TEST_SILENT_Msk (1ul << CAN_TEST_SILENT_Pos) /*!< CAN_T::TEST: Silent Mask */ + +#define CAN_TEST_BASIC_Pos 2 /*!< CAN_T::TEST: Basic Position */ +#define CAN_TEST_BASIC_Msk (1ul << CAN_TEST_BASIC_Pos) /*!< CAN_T::TEST: Basic Mask */ + +/** + * @brief CAN BPRE Bit Field Definitions + */ +#define CAN_BRPE_BRPE_Pos 0 /*!< CAN_T::BRPE: BRPE Position */ +#define CAN_BRPE_BRPE_Msk (0xFul << CAN_BRPE_BRPE_Pos) /*!< CAN_T::BRPE: BRPE Mask */ + +/** + * @brief CAN IFn_CREQ Bit Field Definitions + */ +#define CAN_IF_CREQ_BUSY_Pos 15 /*!< CAN_T::IFnCREQ: BUSY Position */ +#define CAN_IF_CREQ_BUSY_Msk (1ul << CAN_IF_CREQ_BUSY_Pos) /*!< CAN_T::IFnCREQ: BUSY Mask */ + +#define CAN_IF_CREQ_MSGNUM_Pos 0 /*!< CAN_T::IFnCREQ: MSGNUM Position */ +#define CAN_IF_CREQ_MSGNUM_Msk (0x3Ful << CAN_IF_CREQ_MSGNUM_Pos) /*!< CAN_T::IFnCREQ: MSGNUM Mask */ + +/** + * @brief CAN IFn_CMASK Bit Field Definitions + */ +#define CAN_IF_CMASK_WRRD_Pos 7 /*!< CAN_T::IFnCMASK: WRRD Position */ +#define CAN_IF_CMASK_WRRD_Msk (1ul << CAN_IF_CMASK_WRRD_Pos) /*!< CAN_T::IFnCMASK: WRRD Mask */ + +#define CAN_IF_CMASK_MASK_Pos 6 /*!< CAN_T::IFnCMASK: MASK Position */ +#define CAN_IF_CMASK_MASK_Msk (1ul << CAN_IF_CMASK_MASK_Pos) /*!< CAN_T::IFnCMASK: MASK Mask */ + +#define CAN_IF_CMASK_ARB_Pos 5 /*!< CAN_T::IFnCMASK: ARB Position */ +#define CAN_IF_CMASK_ARB_Msk (1ul << CAN_IF_CMASK_ARB_Pos) /*!< CAN_T::IFnCMASK: ARB Mask */ + +#define CAN_IF_CMASK_CONTROL_Pos 4 /*!< CAN_T::IFnCMASK: CONTROL Position */ +#define CAN_IF_CMASK_CONTROL_Msk (1ul << CAN_IF_CMASK_CONTROL_Pos) /*!< CAN_T::IFnCMASK: CONTROL Mask */ + +#define CAN_IF_CMASK_CLRINTPND_Pos 3 /*!< CAN_T::IFnCMASK: CLRINTPND Position */ +#define CAN_IF_CMASK_CLRINTPND_Msk (1ul << CAN_IF_CMASK_CLRINTPND_Pos) /*!< CAN_T::IFnCMASK: CLRINTPND Mask */ + +#define CAN_IF_CMASK_TXRQSTNEWDAT_Pos 2 /*!< CAN_T::IFnCMASK: TXRQSTNEWDAT Position */ +#define CAN_IF_CMASK_TXRQSTNEWDAT_Msk (1ul << CAN_IF_CMASK_TXRQSTNEWDAT_Pos) /*!< CAN_T::IFnCMASK: TXRQSTNEWDAT Mask */ + +#define CAN_IF_CMASK_DATAA_Pos 1 /*!< CAN_T::IFnCMASK: DATAA Position */ +#define CAN_IF_CMASK_DATAA_Msk (1ul << CAN_IF_CMASK_DATAA_Pos) /*!< CAN_T::IFnCMASK: DATAA Mask */ + +#define CAN_IF_CMASK_DATAB_Pos 0 /*!< CAN_T::IFnCMASK: DATAB Position */ +#define CAN_IF_CMASK_DATAB_Msk (1ul << CAN_IF_CMASK_DATAB_Pos) /*!< CAN_T::IFnCMASK: DATAB Mask */ + +/** + * @brief CAN IFn_MASK0 Bit Field Definitions + */ +#define CAN_IF_MASK0_MSK_Pos 0 /*!< CAN_T::IFnMASK0: MSK Position */ +#define CAN_IF_MASK0_MSK_Msk (0xFFul << CAN_IF_MASK0_MSK_Pos) /*!< CAN_T::IFnMASK0: MSK Mask */ + +/** + * @brief CAN IFn_MASK1 Bit Field Definitions + */ +#define CAN_IF_MASK1_MXTD_Pos 15 /*!< CAN_T::IFnMASK1: MXTD Position */ +#define CAN_IF_MASK1_MXTD_Msk (1ul << CAN_IF_MASK1_MXTD_Pos) /*!< CAN_T::IFnMASK1: MXTD Mask */ + +#define CAN_IF_MASK1_MDIR_Pos 14 /*!< CAN_T::IFnMASK1: MDIR Position */ +#define CAN_IF_MASK1_MDIR_Msk (1ul << CAN_IF_MASK1_MDIR_Pos) /*!< CAN_T::IFnMASK1: MDIR Mask */ + +#define CAN_IF_MASK1_MSK_Pos 0 /*!< CAN_T::IFnMASK1: MSK Position */ +#define CAN_IF_MASK1_MSK_Msk (0x1FFul << CAN_IF_MASK1_MSK_Pos) /*!< CAN_T::IFnMASK1: MSK Mask */ + +/** + * @brief CAN IFn_ARB0 Bit Field Definitions + */ +#define CAN_IF_ARB0_ID_Pos 0 /*!< CAN_T::IFnARB0: ID Position */ +#define CAN_IF_ARB0_ID_Msk (0xFFFFul << CAN_IF_ARB0_ID_Pos) /*!< CAN_T::IFnARB0: ID Mask */ + +/** + * @brief CAN IFn_ARB1 Bit Field Definitions + */ +#define CAN_IF_ARB1_MSGVAL_Pos 15 /*!< CAN_T::IFnARB1: MSGVAL Position */ +#define CAN_IF_ARB1_MSGVAL_Msk (1ul << CAN_IF_ARB1_MSGVAL_Pos) /*!< CAN_T::IFnARB1: MSGVAL Mask */ + +#define CAN_IF_ARB1_XTD_Pos 14 /*!< CAN_T::IFnARB1: XTD Position */ +#define CAN_IF_ARB1_XTD_Msk (1ul << CAN_IF_ARB1_XTD_Pos) /*!< CAN_T::IFnARB1: XTD Mask */ + +#define CAN_IF_ARB1_DIR_Pos 13 /*!< CAN_T::IFnARB1: DIR Position */ +#define CAN_IF_ARB1_DIR_Msk (1ul << CAN_IF_ARB1_DIR_Pos) /*!< CAN_T::IFnARB1: DIR Mask */ + +#define CAN_IF_ARB1_ID_Pos 0 /*!< CAN_T::IFnARB1: ID Position */ +#define CAN_IF_ARB1_ID_Msk (0x1FFFul << CAN_IF_ARB1_ID_Pos) /*!< CAN_T::IFnARB1: ID Mask */ + +/** + * @brief CAN IFn_MCR Bit Field Definitions + */ +#define CAN_IF_MCR_NEWDAT_Pos 15 /*!< CAN_T::IFnMCON: NEWDAT Position */ +#define CAN_IF_MCR_NEWDAT_Msk (1ul << CAN_IF_MCR_NEWDAT_Pos) /*!< CAN_T::IFnMCON: NEWDAT Mask */ + +#define CAN_IF_MCR_MSGLST_Pos 14 /*!< CAN_T::IFnMCON: MSGLST Position */ +#define CAN_IF_MCR_MSGLST_Msk (1ul << CAN_IF_MCR_MSGLST_Pos) /*!< CAN_T::IFnMCON: MSGLST Mask */ + +#define CAN_IF_MCR_INTPND_Pos 13 /*!< CAN_T::IFnMCON: INTPND Position */ +#define CAN_IF_MCR_INTPND_Msk (1ul << CAN_IF_MCR_INTPND_Pos) /*!< CAN_T::IFnMCON: INTPND Mask */ + +#define CAN_IF_MCR_UMASK_Pos 12 /*!< CAN_T::IFnMCON: UMASK Position */ +#define CAN_IF_MCR_UMASK_Msk (1ul << CAN_IF_MCR_UMASK_Pos) /*!< CAN_T::IFnMCON: UMASK Mask */ + +#define CAN_IF_MCR_TXIE_Pos 11 /*!< CAN_T::IFnMCON: TXIE Position */ +#define CAN_IF_MCR_TXIE_Msk (1ul << CAN_IF_MCR_TXIE_Pos) /*!< CAN_T::IFnMCON: TXIE Mask */ + +#define CAN_IF_MCR_RXIE_Pos 10 /*!< CAN_T::IFnMCON: RXIE Position */ +#define CAN_IF_MCR_RXIE_Msk (1ul << CAN_IF_MCR_RXIE_Pos) /*!< CAN_T::IFnMCON: RXIE Mask */ + +#define CAN_IF_MCR_RMTEN_Pos 9 /*!< CAN_T::IFnMCON: RMTEN Position */ +#define CAN_IF_MCR_RMTEN_Msk (1ul << CAN_IF_MCR_RMTEN_Pos) /*!< CAN_T::IFnMCON: RMTEN Mask */ + +#define CAN_IF_MCR_TXRQST_Pos 8 /*!< CAN_T::IFnMCON: TXRQST Position */ +#define CAN_IF_MCR_TXRQST_Msk (1ul << CAN_IF_MCR_TXRQST_Pos) /*!< CAN_T::IFnMCON: TXRQST Mask */ + +#define CAN_IF_MCR_EOB_Pos 7 /*!< CAN_T::IFnMCON: EOB Position */ +#define CAN_IF_MCR_EOB_Msk (1ul << CAN_IF_MCR_EOB_Pos) /*!< CAN_T::IFnMCON: EOB Mask */ + +#define CAN_IF_MCR_DLC_Pos 0 /*!< CAN_T::IFnMCON: DLC Position */ +#define CAN_IF_MCR_DLC_Msk (0xFul << CAN_IF_MCR_DLC_Pos) /*!< CAN_T::IFnMCON: DLC Mask */ + +/** + * @brief CAN IFn_DATA_A0 Bit Field Definitions + */ +#define CAN_IF_DAT_A0_DATA1_Pos 8 /*!< CAN_T::IFnDATAA0: DATA1 Position */ +#define CAN_IF_DAT_A0_DATA1_Msk (0xFFul << CAN_IF_DAT_A0_DATA1_Pos) /*!< CAN_T::IFnDATAA0: DATA1 Mask */ + +#define CAN_IF_DAT_A0_DATA0_Pos 0 /*!< CAN_T::IFnDATAA0: DATA0 Position */ +#define CAN_IF_DAT_A0_DATA0_Msk (0xFFul << CAN_IF_DAT_A0_DATA0_Pos) /*!< CAN_T::IFnDATAA0: DATA0 Mask */ + +/** + * @brief CAN IFn_DATA_A1 Bit Field Definitions + */ +#define CAN_IF_DAT_A1_DATA3_Pos 8 /*!< CAN_T::IFnDATAA1: DATA3 Position */ +#define CAN_IF_DAT_A1_DATA3_Msk (0xFFul << CAN_IF_DAT_A1_DATA3_Pos) /*!< CAN_T::IFnDATAA1: DATA3 Mask */ + +#define CAN_IF_DAT_A1_DATA2_Pos 0 /*!< CAN_T::IFnDATAA1: DATA2 Position */ +#define CAN_IF_DAT_A1_DATA2_Msk (0xFFul << CAN_IF_DAT_A1_DATA2_Pos) /*!< CAN_T::IFnDATAA1: DATA2 Mask */ + +/** + * @brief CAN IFn_DATA_B0 Bit Field Definitions + */ +#define CAN_IF_DAT_B0_DATA5_Pos 8 /*!< CAN_T::IFnDATAB0: DATA5 Position */ +#define CAN_IF_DAT_B0_DATA5_Msk (0xFFul << CAN_IF_DAT_B0_DATA5_Pos) /*!< CAN_T::IFnDATAB0: DATA5 Mask */ + +#define CAN_IF_DAT_B0_DATA4_Pos 0 /*!< CAN_T::IFnDATAB0: DATA4 Position */ +#define CAN_IF_DAT_B0_DATA4_Msk (0xFFul << CAN_IF_DAT_B0_DATA4_Pos) /*!< CAN_T::IFnDATAB0: DATA4 Mask */ + +/** + * @brief CAN IFn_DATA_B1 Bit Field Definitions + */ +#define CAN_IF_DAT_B1_DATA7_Pos 8 /*!< CAN_T::IFnDATAB1: DATA7 Position */ +#define CAN_IF_DAT_B1_DATA7_Msk (0xFFul << CAN_IF_DAT_B1_DATA7_Pos) /*!< CAN_T::IFnDATAB1: DATA7 Mask */ + +#define CAN_IF_DAT_B1_DATA6_Pos 0 /*!< CAN_T::IFnDATAB1: DATA6 Position */ +#define CAN_IF_DAT_B1_DATA6_Msk (0xFFul << CAN_IF_DAT_B1_DATA6_Pos) /*!< CAN_T::IFnDATAB1: DATA6 Mask */ + +/** + * @brief CAN IFn_TXRQST0 Bit Field Definitions + */ +#define CAN_IF_TXRQST0_TXRQST_Pos 0 /*!< CAN_T::IFnTXRQST0: TXRQST Position */ +#define CAN_IF_TXRQST0_TXRQST_Msk (0xFFFFul << CAN_IF_TXRQST0_TXRQST_Pos) /*!< CAN_T::IFnTXRQST0: TXRQST Mask */ + +/** + * @brief CAN IFn_TXRQST1 Bit Field Definitions + */ +#define CAN_IF_TXRQST1_TXRQST_Pos 0 /*!< CAN_T::IFnTXRQST1: TXRQST Position */ +#define CAN_IF_TXRQST1_TXRQST_Msk (0xFFFFul << CAN_IF_TXRQST1_TXRQST_Pos) /*!< CAN_T::IFnTXRQST1: TXRQST Mask */ + +/** + * @brief CAN IFn_NDAT0 Bit Field Definitions + */ +#define CAN_IF_NDAT0_NEWDATA_Pos 0 /*!< CAN_T::IFnNDAT0: NEWDATA Position */ +#define CAN_IF_NDAT0_NEWDATA_Msk (0xFFFFul << CAN_IF_NDAT0_NEWDATA_Pos) /*!< CAN_T::IFnNDAT0: NEWDATA Mask */ + +/** + * @brief CAN IFn_NDAT1 Bit Field Definitions + */ +#define CAN_IF_NDAT1_NEWDATA_Pos 0 /*!< CAN_T::IFnNDAT1: NEWDATA Position */ +#define CAN_IF_NDAT1_NEWDATA_Msk (0xFFFFul << CAN_IF_NDAT1_NEWDATA_Pos) /*!< CAN_T::IFnNDAT1: NEWDATA Mask */ + +/** + * @brief CAN IFn_IPND0 Bit Field Definitions + */ +#define CAN_IF_IPND0_INTPND_Pos 0 /*!< CAN_T::IFnIPND0: INTPND Position */ +#define CAN_IF_IPND0_INTPND_Msk (0xFFFFul << CAN_IF_IPND0_INTPND_Pos) /*!< CAN_T::IFnIPND0: INTPND Mask */ + +/** + * @brief CAN IFn_IPND1 Bit Field Definitions + */ +#define CAN_IF_IPND1_INTPND_Pos 0 /*!< CAN_T::IFnIPND1: INTPND Position */ +#define CAN_IF_IPND1_INTPND_Msk (0xFFFFul << CAN_IF_IPND1_INTPND_Pos) /*!< CAN_T::IFnIPND1: INTPND Mask */ + +/** + * @brief CAN IFn_MVLD0 Bit Field Definitions + */ +#define CAN_IF_MVLD0_MSGVAL_Pos 0 /*!< CAN_T::IFnMVLD0: MSGVAL Position */ +#define CAN_IF_MVLD0_MSGVAL_Msk (0xFFFFul << CAN_IF_MVLD0_MSGVAL_Pos) /*!< CAN_T::IFnMVLD0: MSGVAL Mask */ + +/** + * @brief CAN IFn_MVLD1 Bit Field Definitions + */ +#define CAN_IF_MVLD1_MSGVAL_Pos 0 /*!< CAN_T::IFnMVLD1: MSGVAL Position */ +#define CAN_IF_MVLD1_MSGVAL_Msk (0xFFFFul << CAN_IF_MVLD1_MSGVAL_Pos) /*!< CAN_T::IFnMVLD1: MSGVAL Mask */ + +/** + * @brief CAN WUEN Bit Field Definitions + */ +#define CAN_WUEN_WAKUP_EN_Pos 0 /*!< CAN_T::WUEN: WAKUP_EN Position */ +#define CAN_WUEN_WAKUP_EN_Msk (1ul << CAN_WUEN_WAKUP_EN_Pos) /*!< CAN_T::WUEN: WAKUP_EN Mask */ + +/** + * @brief CAN WUSTATUS Bit Field Definitions + */ +#define CAN_WUSTATUS_WAKUP_STS_Pos 0 /*!< CAN_T::WUSTATUS: WAKUP_STS Position */ +#define CAN_WUSTATUS_WAKUP_STS_Msk (1ul << CAN_WUSTATUS_WAKUP_STS_Pos) /*!< CAN_T::WUSTATUS: WAKUP_STS Mask */ +/** + * @} + */ + +/* Exported functions --------------------------------------------------------------------------------------*/ +/** @defgroup CAN_Exported_Functions CAN exported functions + * @{ + */ +void CAN_DeInit(HT_CAN_TypeDef* CANx); +u32 CAN_SetBaudRate(HT_CAN_TypeDef *CANx, u32 u32BaudRate); +void CAN_Close(HT_CAN_TypeDef *CANx); +u32 CAN_Open(HT_CAN_TypeDef *CANx, u32 u32BaudRate, u32 u32Mode); +void CAN_CLR_INT_PENDING_BIT(HT_CAN_TypeDef *CANx, u32 u32MsgNum); +void CAN_EnableInt(HT_CAN_TypeDef *CANx, u32 u32Mask); +void CAN_DisableInt(HT_CAN_TypeDef *CANx, u32 u32Mask); +s32 CAN_Transmit(HT_CAN_TypeDef *CANx, u32 u32MsgNum , STR_CANMSG_T_TypeDef* pCanMsg); +s32 CAN_Receive(HT_CAN_TypeDef *CANx, u32 u32MsgNum , STR_CANMSG_T_TypeDef* pCanMsg); +s32 CAN_SetRxMsg(HT_CAN_TypeDef *CANx, u32 u32MsgNum , STR_CANMSG_R_TypeDef* pCanMsg); +s32 CAN_SetTxMsg(HT_CAN_TypeDef *CANx, u32 u32MsgNum , STR_CANMSG_T_TypeDef* pCanMsg); +s32 CAN_TriggerTxMsg(HT_CAN_TypeDef *CANx, u32 u32MsgNum); +void CAN_EnterInitMode(HT_CAN_TypeDef *CANx); +void CAN_LeaveInitMode(HT_CAN_TypeDef *CANx); +void CAN_WaitMsg(HT_CAN_TypeDef *CANx); +u32 CAN_GetCANBitRate(HT_CAN_TypeDef *CANx); +void CAN_EnterTestMode(HT_CAN_TypeDef *CANx, u32 u8TestMask); +void CAN_LeaveTestMode(HT_CAN_TypeDef *CANx); +u32 CAN_IsNewDataReceived(HT_CAN_TypeDef *CANx, u32 u8MsgObj); +s32 CAN_BasicSendMsg(HT_CAN_TypeDef *CANx, STR_CANMSG_T_TypeDef* pCanMsg); +s32 CAN_BasicReceiveMsg(HT_CAN_TypeDef *CANx, STR_CANMSG_T_TypeDef* pCanMsg); +s32 CAN_SetRxMsgObj(HT_CAN_TypeDef *CANx, u32 MsgObj, STR_CANMSG_R_TypeDef* pCanMsg); +s32 CAN_ReadMsgObj(HT_CAN_TypeDef *CANx, u32 u8MsgObj, u32 u8Release, STR_CANMSG_T_TypeDef* pCanMsg); +s32 CAN_MsgObjMaskConfig(HT_CAN_TypeDef *tCAN, u32 u8MsgObj, STR_CANMSG_R_TypeDef* MaskMsg); +s32 CAN_SetMultiRxMsg(HT_CAN_TypeDef *CANx, u32 u32MsgNum , u32 u32MsgCount, STR_CANMSG_R_TypeDef* pCanMsg); +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f5xxxx_ckcu.h b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f5xxxx_ckcu.h new file mode 100644 index 0000000000..531078537b --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f5xxxx_ckcu.h @@ -0,0 +1,936 @@ +/*********************************************************************************************************//** + * @file ht32f5xxxx_ckcu.h + * @version $Rev:: 7108 $ + * @date $Date:: 2023-08-09 #$ + * @brief The header file of the Clock Control Unit library. + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------------------------------------*/ +#ifndef __HT32F5XXXX_CKCU_H +#define __HT32F5XXXX_CKCU_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------------------------------------*/ +#include "ht32.h" + +/** @addtogroup HT32F5xxxx_Peripheral_Driver HT32F5xxxx Peripheral Driver + * @{ + */ + +/** @addtogroup CKCU + * @{ + */ + + +/* Exported types ------------------------------------------------------------------------------------------*/ +/** @defgroup CKCU_Exported_Types CKCU exported types + * @{ + */ + +#if (!LIBCFG_CKCU_NO_APB_PRESCALER) +/** + * @brief Enumeration of APB peripheral prescaler. + */ +typedef enum +{ + CKCU_APBCLKPRE_DIV1 = 0, + CKCU_APBCLKPRE_DIV2, + CKCU_APBCLKPRE_DIV4, + CKCU_APBCLKPRE_DIV8, + CKCU_APBCLKPRE_DIV16, + CKCU_APBCLKPRE_DIV32 +} CKCU_APBCLKPRE_TypeDef; +#endif + +/** + * @brief Enumeration of CK_REF prescaler. + */ +typedef enum +{ + CKCU_CKREFPRE_DIV2 = 0, + CKCU_CKREFPRE_DIV4, + CKCU_CKREFPRE_DIV6, + CKCU_CKREFPRE_DIV8, + CKCU_CKREFPRE_DIV10, + CKCU_CKREFPRE_DIV12, + CKCU_CKREFPRE_DIV14, + CKCU_CKREFPRE_DIV16, + CKCU_CKREFPRE_DIV18, + CKCU_CKREFPRE_DIV20, + CKCU_CKREFPRE_DIV22, + CKCU_CKREFPRE_DIV24, + CKCU_CKREFPRE_DIV26, + CKCU_CKREFPRE_DIV28, + CKCU_CKREFPRE_DIV30, + CKCU_CKREFPRE_DIV32, + CKCU_CKREFPRE_DIV34, + CKCU_CKREFPRE_DIV36, + CKCU_CKREFPRE_DIV38, + CKCU_CKREFPRE_DIV40, + CKCU_CKREFPRE_DIV42, + CKCU_CKREFPRE_DIV44, + CKCU_CKREFPRE_DIV46, + CKCU_CKREFPRE_DIV48, + CKCU_CKREFPRE_DIV50, + CKCU_CKREFPRE_DIV52, + CKCU_CKREFPRE_DIV54, + CKCU_CKREFPRE_DIV56, + CKCU_CKREFPRE_DIV58, + CKCU_CKREFPRE_DIV60, + CKCU_CKREFPRE_DIV62, + CKCU_CKREFPRE_DIV64 +} CKCU_CKREFPRE_TypeDef; + +#if (!LIBCFG_NO_PLL) +/** + * @brief Enumeration of PLL clock source. + */ +typedef enum +{ + CKCU_PLLSRC_HSE = 0, + CKCU_PLLSRC_HSI +} CKCU_PLLSRC_TypeDef; + +#define IS_PLL_CLKSRC(SRC) ((SRC == CKCU_PLLSRC_HSE) || \ + (SRC == CKCU_PLLSRC_HSI)) +#endif + +#if (LIBCFG_CKCU_USB_PLL) +/** + * @brief Enumeration of CK_USB clock source. + */ +typedef enum +{ + CKCU_CKPLL = 0, + CKCU_CKUSBPLL +} CKCU_USBSRC_TypeDef; +#endif + +#if (LIBCFG_CKCU_LCD_SRC) +/** + * @brief Enumeration of CK_LCD clock source. + */ +typedef enum +{ + CKCU_LCDSRC_LSI = 0, + #if (LIBCFG_LSE) + CKCU_LCDSRC_LSE, + #endif + CKCU_LCDSRC_HSI, + CKCU_LCDSRC_HSE +} CKCU_LCDSRC_TypeDef; +#endif + +#if (LIBCFG_CKCU_MCTM_SRC) +/** + * @brief Enumeration of MCTM clock source. + */ +typedef enum +{ + CKCU_MCTMSRC_AHB = 0, + CKCU_MCTMSRC_USBPLL +} CKCU_MCTMSRC_TypeDef; + +#define IS_MCTM_SRC(SRC) ((SRC == CKCU_MCTMSRC_AHB) || \ + (SRC == CKCU_MCTMSRC_USBPLL)) +#endif + + +#if (((LIBCFG_LSE) || (LIBCFG_USBD) || (LIBCFG_CKCU_REFCLK_EXT_PIN)) && (!LIBCFG_CKCU_NO_AUTO_TRIM)) +/** + * @brief Enumeration of HSI auto-trim clock source. + */ +typedef enum +{ + #if (LIBCFG_LSE) + CKCU_ATC_LSE = 0, + #endif + #if (LIBCFG_USBD) + CKCU_ATC_USB = 1, + #endif + #if (LIBCFG_CKCU_REFCLK_EXT_PIN) + CKCU_ATC_CKIN = 2, + #endif +} CKCU_ATC_TypeDef; +#endif + +#if (LIBCFG_CKCU_ATM_V01) +/** + * @brief Enumeration of ATC search algorithm. + */ +typedef enum +{ + CKCU_ATC_BINARY_SEARCH = 0, + CKCU_ATC_LINEAR_SEARCH = 8 +} CKCU_ATCSearchAlgorithm_TypeDef; + +/** + * @brief Enumeration of ATC frequency tolerance. + */ +typedef enum +{ + CKCU_ATC_DOUBLE_PRECISION = 0, + CKCU_ATC_SINGLE_PRECISION = 4 +} CKCU_ATCFrqTolerance_TypeDef; +#endif + +/** + * @brief Enumeration of CK_AHB prescaler. + */ +typedef enum +{ + CKCU_SYSCLK_DIV1 = 0, + CKCU_SYSCLK_DIV2, + CKCU_SYSCLK_DIV4, + CKCU_SYSCLK_DIV8, + CKCU_SYSCLK_DIV16, + CKCU_SYSCLK_DIV32 +} CKCU_SYSCLKDIV_TypeDef; + +/** + * @brief Enumeration of CK_ADC prescaler. + */ +typedef enum +{ + #if (LIBCFG_CKCU_NO_ADCPRE_DIV1) + #else + CKCU_ADCPRE_DIV1 = 0, + #endif + CKCU_ADCPRE_DIV2 = 1, + CKCU_ADCPRE_DIV4, + CKCU_ADCPRE_DIV8, + CKCU_ADCPRE_DIV16, + CKCU_ADCPRE_DIV32, + CKCU_ADCPRE_DIV64, + CKCU_ADCPRE_DIV3 +} CKCU_ADCPRE_TypeDef; + +/** + * @brief Enumeration of CK_ADCn. + */ +typedef enum +{ + CKCU_ADCPRE_ADC0 = 16, + #if (LIBCFG_ADC1) + CKCU_ADCPRE_ADC1 = 20, + #endif +} CKCU_ADCPRE_ADCn_TypeDef; + +#if (LIBCFG_LCD) +/** + * @brief Enumeration of CK_LCD prescaler. + */ +typedef enum +{ + CKCU_LCDPRE_DIV1 = 0, + CKCU_LCDPRE_DIV2, + CKCU_LCDPRE_DIV4, + CKCU_LCDPRE_DIV8, + CKCU_LCDPRE_DIV16, +} CKCU_LCDPRE_TypeDef; +#endif + +#if (LIBCFG_MIDI) +/** + * @brief Enumeration of CK_MIDI prescaler. + */ +typedef enum +{ + CKCU_MIDIPRE_DIV16 = 0, + CKCU_MIDIPRE_DIV13, + CKCU_MIDIPRE_DIV11, + CKCU_MIDIPRE_DIV9, + CKCU_MIDIPRE_DIV8, +} CKCU_MIDIPRE_TypeDef; +#endif + +/** + * @brief Enumeration of System clock source. + */ +typedef enum +{ +#if (!LIBCFG_NO_PLL) + CKCU_SW_PLL = 1, +#endif + CKCU_SW_HSE = 2, + CKCU_SW_HSI = 3, + #if (LIBCFG_LSE) + CKCU_SW_LSE = 6, + #endif + CKCU_SW_LSI = 7 +} CKCU_SW_TypeDef; + +/** + * @brief Enumeration of CKOUT clock source. + */ +typedef enum +{ + CKCU_CKOUTSRC_REFCK = 0, + CKCU_CKOUTSRC_HCLK_DIV16 = 1, + CKCU_CKOUTSRC_SYSCK_DIV16 = 2, + CKCU_CKOUTSRC_HSECK_DIV16 = 3, + CKCU_CKOUTSRC_HSICK_DIV16 = 4, + #if (LIBCFG_LSE) + CKCU_CKOUTSRC_LSECK = 5, + #endif + CKCU_CKOUTSRC_LSICK = 6 +} CKCU_CKOUTSRC_TypeDef; + +#if (!LIBCFG_NO_PLL) +/** + * @brief Enumeration of PLL clock source status. + */ +typedef enum +{ + CKCU_PLLST_SYSCK = 1, + #if (LIBCFG_USBD) + CKCU_PLLST_USB = 4, + #endif + CKCU_PLLST_REFCK = 8 +} CKCU_PLLST_TypeDef; +#endif + +/** + * @brief Enumeration of HSI clock source status. + */ +typedef enum +{ + CKCU_HSIST_SYSCK = 1, +#if (!LIBCFG_NO_PLL) + CKCU_HSIST_PLL = 2, +#endif + CKCU_HSIST_CKM = 4 +} CKCU_HSIST_TypeDef; + +/** + * @brief Enumeration of HSE clock source status. + */ +typedef enum +{ + CKCU_HSEST_SYSCK = 1, +#if (!LIBCFG_NO_PLL) + CKCU_HSEST_PLL +#endif +} CKCU_HSEST_TypeDef; + +/** + * @brief Definition of CKOUT Init Structure. + */ +typedef struct +{ + CKCU_CKOUTSRC_TypeDef CKOUTSRC; +} CKCU_CKOUTInitTypeDef; + +#if (!LIBCFG_NO_PLL) +/** + * @brief Definition of PLL Init Structure. + */ +typedef struct +{ + u32 CFG; + CKCU_PLLSRC_TypeDef ClockSource; + ControlStatus BYPASSCmd; +} CKCU_PLLInitTypeDef; +#endif + +/** + * @brief Definition of structure for clock frequency. + */ +typedef struct +{ +#if (!LIBCFG_NO_PLL) + u32 PLL_Freq; +#endif + u32 SYSCK_Freq; + u32 HCLK_Freq; +#if (HT32_LIB_ENABLE_GET_CK_ADC) +#if (!LIBCFG_NO_ADC) + u32 ADC0_Freq; +#endif +#if (LIBCFG_ADC1) + u32 ADC1_Freq; +#endif +#endif +} CKCU_ClocksTypeDef; + +#if (LIBCFG_CKCU_ATM_V01) +/** + * @brief Definition of ATC Init Structure. + */ +typedef struct +{ + CKCU_ATCSearchAlgorithm_TypeDef SearchAlgorithm; + CKCU_ATCFrqTolerance_TypeDef FrqTolerance; +} CKCU_ATCInitTypeDef; +#endif + +/** + * @brief Definition of initial structure of peripheral clock control. + */ +typedef union +{ + struct + { + /* Definitions of AHB clock control */ + unsigned long FMC :1; // Bit 0 + unsigned long :1; // Bit 1 + unsigned long SRAM :1; // Bit 2 + unsigned long :1; // Bit 3 + unsigned long PDMA :1; // Bit 4 + unsigned long BM :1; // Bit 5 + unsigned long APB :1; // Bit 6 + unsigned long :1; // Bit 7 + + unsigned long :1; // Bit 8 + unsigned long :1; // Bit 9 + unsigned long USBD :1; // Bit 10 + unsigned long CKREF :1; // Bit 11 + unsigned long EBI :1; // Bit 12 + unsigned long CRC :1; // Bit 13 + unsigned long :1; // Bit 14 + unsigned long AES :1; // Bit 15 + + unsigned long PA :1; // Bit 16 + unsigned long PB :1; // Bit 17 + unsigned long PC :1; // Bit 18 + unsigned long PD :1; // Bit 19 + unsigned long PE :1; // Bit 20 + unsigned long PF :1; // Bit 21 + unsigned long :1; // Bit 22 + unsigned long :1; // Bit 23 + + unsigned long DIV :1; // Bit 24 + unsigned long QSPI :1; // Bit 25 + unsigned long RF :1; // Bit 26 + unsigned long :1; // Bit 27 + unsigned long :1; // Bit 28 + unsigned long :1; // Bit 29 + unsigned long :1; // Bit 30 + unsigned long :1; // Bit 31 + + /* Definitions of APB0 clock control */ + unsigned long I2C0 :1; // Bit 0 + unsigned long I2C1 :1; // Bit 1 + unsigned long I2C2 :1; // Bit 2 + unsigned long :1; // Bit 3 + unsigned long SPI0 :1; // Bit 4 + unsigned long SPI1 :1; // Bit 5 + unsigned long :1; // Bit 6 + unsigned long :1; // Bit 7 + + unsigned long USART0 :1; // Bit 8 + unsigned long USART1 :1; // Bit 9 + unsigned long UART0 :1; // Bit 10 + unsigned long UART1 :1; // Bit 11 + unsigned long UART2 :1; // Bit 12 + unsigned long UART3 :1; // Bit 13 + unsigned long AFIO :1; // Bit 14 + unsigned long EXTI :1; // Bit 15 + + unsigned long :1; // Bit 16 + unsigned long :1; // Bit 17 + unsigned long :1; // Bit 18 + unsigned long :1; // Bit 19 + unsigned long :1; // Bit 20 + unsigned long :1; // Bit 21 + unsigned long SLED0 :1; // Bit 22 + unsigned long SLED1 :1; // Bit 23 + + unsigned long SCI0 :1; // Bit 24 + unsigned long I2S :1; // Bit 25 + unsigned long :1; // Bit 26 + unsigned long SCI1 :1; // Bit 27 + unsigned long MIDI :1; // Bit 28 + unsigned long LEDC :1; // Bit 29 + unsigned long CAN0 :1; // Bit 30 + unsigned long :1; // Bit 31 + + /* Definitions of APB1 clock control */ + unsigned long MCTM0 :1; // Bit 0 + unsigned long :1; // Bit 1 + unsigned long :1; // Bit 2 + unsigned long :1; // Bit 3 + unsigned long WDT :1; // Bit 4 + unsigned long :1; // Bit 5 + unsigned long BKP :1; // Bit 6 + unsigned long DAC1 :1; // Bit 7 + + unsigned long GPTM0 :1; // Bit 8 + unsigned long GPTM1 :1; // Bit 9 + unsigned long :1; // Bit 10 + unsigned long :1; // Bit 11 + unsigned long PWM0 :1; // Bit 12 + unsigned long PWM1 :1; // Bit 13 + unsigned long PWM2 :1; // Bit 14 + unsigned long :1; // Bit 15 + + unsigned long BFTM0 :1; // Bit 16 + unsigned long BFTM1 :1; // Bit 17 + unsigned long TKEY :1; // Bit 18 + unsigned long LCDR :1; // Bit 19 + unsigned long LCDC :1; // Bit 20 + unsigned long DAC0 :1; // Bit 21 + unsigned long CMP :1; // Bit 22 + unsigned long OPA :1; // Bit 23 + + unsigned long ADC0 :1; // Bit 24 + unsigned long ADC1 :1; // Bit 25 + unsigned long :1; // Bit 26 + unsigned long :1; // Bit 27 + unsigned long SCTM0 :1; // Bit 28 + unsigned long SCTM1 :1; // Bit 29 + unsigned long SCTM2 :1; // Bit 30 + unsigned long SCTM3 :1; // Bit 31 + } Bit; + u32 Reg[3]; +} CKCU_PeripClockConfig_TypeDef; + +#define CKCU_APBPCSR_OFFSET (5) +#define CKCU_APBPCSR0 (0 << CKCU_APBPCSR_OFFSET) +#define CKCU_APBPCSR1 (1 << CKCU_APBPCSR_OFFSET) +#define CKCU_APBPCSR2 (4 << CKCU_APBPCSR_OFFSET) +typedef enum +{ + CKCU_PCLK_I2C0 = (CKCU_APBPCSR0 | 0), + #if (LIBCFG_I2C1) + CKCU_PCLK_I2C1 = (CKCU_APBPCSR0 | 2), + #endif + CKCU_PCLK_SPI0 = (CKCU_APBPCSR0 | 4), + #if (LIBCFG_SPI1) + CKCU_PCLK_SPI1 = (CKCU_APBPCSR0 | 6), + #endif + #if (LIBCFG_UART2) + CKCU_PCLK_UART2 = (CKCU_APBPCSR0 | 8), + #endif + #if (LIBCFG_UART3) + CKCU_PCLK_UART3 = (CKCU_APBPCSR0 | 10), + #endif + CKCU_PCLK_BFTM0 = (CKCU_APBPCSR0 | 12), + #if (LIBCFG_BFTM1) + CKCU_PCLK_BFTM1 = (CKCU_APBPCSR0 | 14), + #endif + #if (LIBCFG_MCTM0) + CKCU_PCLK_MCTM0 = (CKCU_APBPCSR0 | 16), + #endif + #if (!LIBCFG_NO_GPTM0) + CKCU_PCLK_GPTM0 = (CKCU_APBPCSR0 | 20), + #endif + #if (LIBCFG_GPTM1) + CKCU_PCLK_GPTM1 = (CKCU_APBPCSR0 | 22), + #endif + #if (!LIBCFG_NO_USART0) + CKCU_PCLK_USART0 = (CKCU_APBPCSR0 | 24), + #endif + #if (LIBCFG_USART1) + CKCU_PCLK_USART1 = (CKCU_APBPCSR0 | 26), + #endif + CKCU_PCLK_UART0 = (CKCU_APBPCSR0 | 28), + #if (LIBCFG_UART1) + CKCU_PCLK_UART1 = (CKCU_APBPCSR0 | 30), + #endif + CKCU_PCLK_AFIO = (CKCU_APBPCSR1 | 0), + CKCU_PCLK_EXTI = (CKCU_APBPCSR1 | 2), + #if (!LIBCFG_NO_ADC) + CKCU_PCLK_ADC0 = (CKCU_APBPCSR1 | 4), + #endif + #if (LIBCFG_ADC1) + CKCU_PCLK_ADC1 = (CKCU_APBPCSR1 | 6), + #endif + #if (LIBCFG_CMP) + CKCU_PCLK_CMP = (CKCU_APBPCSR1 | 8), + #endif + #if (LIBCFG_OPA) + CKCU_PCLK_OPA = (CKCU_APBPCSR1 | 10), + #endif + CKCU_PCLK_WDTR = (CKCU_APBPCSR1 | 12), + CKCU_PCLK_BKPR = (CKCU_APBPCSR1 | 14), + #if (LIBCFG_SCI0) + CKCU_PCLK_SCI0 = (CKCU_APBPCSR1 | 16), + #endif + #if (LIBCFG_SCI1) + CKCU_PCLK_SCI1 = (CKCU_APBPCSR1 | 18), + #endif + #if (LIBCFG_I2S) + CKCU_PCLK_I2S = (CKCU_APBPCSR1 | 20), + #endif + #if (LIBCFG_I2C2) + CKCU_PCLK_I2C2 = (CKCU_APBPCSR1 | 22), + #endif + #if (LIBCFG_SCTM0) + CKCU_PCLK_SCTM0 = (CKCU_APBPCSR1 | 24), + #endif + #if (LIBCFG_SCTM1) + CKCU_PCLK_SCTM1 = (CKCU_APBPCSR1 | 26), + #endif + #if (LIBCFG_SCTM2) + CKCU_PCLK_SCTM2 = (CKCU_APBPCSR1 | 28), + #endif + #if (LIBCFG_SCTM3) + CKCU_PCLK_SCTM3 = (CKCU_APBPCSR1 | 30), + #endif + #if (LIBCFG_AFE0006) + CKCU_PCLK_AFE = (CKCU_APBPCSR2 | 0), + #endif + #if (LIBCFG_DACDUAL16) || (LIBCFG_DAC0) + CKCU_PCLK_DAC0 = (CKCU_APBPCSR2 | 2), + #endif + #if (LIBCFG_LEDC) + CKCU_PCLK_LEDC = (CKCU_APBPCSR2 | 6), + #endif + #if (LIBCFG_MIDI) + CKCU_PCLK_MIDI = (CKCU_APBPCSR2 | 8), + #endif + #if (LIBCFG_TKEY) + CKCU_PCLK_TKEY = (CKCU_APBPCSR2 | 10), + #endif + #if (LIBCFG_SLED0) + CKCU_PCLK_SLED0 = (CKCU_APBPCSR2 | 12), + #endif + #if (LIBCFG_SLED1) + CKCU_PCLK_SLED1 = (CKCU_APBPCSR2 | 14), + #endif + #if (LIBCFG_PWM0) + CKCU_PCLK_PWM0 = (CKCU_APBPCSR2 | 16), + #endif + #if (LIBCFG_PWM1) + CKCU_PCLK_PWM1 = (CKCU_APBPCSR2 | 18), + #endif + #if (LIBCFG_PWM2) + CKCU_PCLK_PWM2 = (CKCU_APBPCSR2 | 20), + #endif + #if (LIBCFG_CAN0) + CKCU_PCLK_CAN0 = (CKCU_APBPCSR2 | 20), + #endif + #if (LIBCFG_DAC1) + CKCU_PCLK_DAC1 = (CKCU_APBPCSR2 | 24), + #endif +} CKCU_PeripPrescaler_TypeDef; + +#define CKCU_PCLK_ADC CKCU_PCLK_ADC0 +/** + * @} + */ + +/* Exported constants --------------------------------------------------------------------------------------*/ +/** @defgroup CKCU_Exported_Constants CKCU exported constants + * @{ + */ + +/* Definitions of clock ready flag */ +#if (LIBCFG_CKCU_USB_PLL) +#define CKCU_FLAG_USBPLLRDY (1UL) +#endif +#if (!LIBCFG_NO_PLL) +#define CKCU_FLAG_PLLRDY (1UL << 1) +#endif +#define CKCU_FLAG_HSERDY (1UL << 2) +#define CKCU_FLAG_HSIRDY (1UL << 3) +#if (LIBCFG_LSE) +#define CKCU_FLAG_LSERDY (1UL << 4) +#endif +#define CKCU_FLAG_LSIRDY (1UL << 5) + +#define IS_CKCU_FLAG(FLAG) (((FLAG & 0xFFFFFFC0) == 0) && (FLAG != 0)) + +/* Definitions of clock interrupt & flag */ +#define CKCU_INT_CKS (1UL) +#define IS_CKCU_INT_FLAG(FLAG) (FLAG == CKCU_INT_CKS) + +#define CKCU_INT_CKSIE (1UL << 16) +#define IS_CKCU_INT(INT) (((INT & 0xFFFEFFFF) == 0) && (INT != 0)) + +#if (!LIBCFG_NO_PLL) +/* Definitions of PLL frequency */ +#define CKCU_PLL_4M_48M ((12UL << 23) | (0UL << 21)) +#define CKCU_PLL_4M_40M ((10UL << 23) | (0UL << 21)) +#define CKCU_PLL_8M_48M (( 6UL << 23) | (0UL << 21)) +#define CKCU_PLL_8M_40M (( 5UL << 23) | (0UL << 21)) +#define CKCU_PLL_8M_32M (( 4UL << 23) | (0UL << 21)) +#define CKCU_PLL_12M_48M (( 4UL << 23) | (0UL << 21)) +#define CKCU_PLL_16M_48M (( 3UL << 23) | (0UL << 21)) + +#if (LIBCFG_CKCU_SYS_CK_60M) +#define CKCU_PLL_4M_60M ((0UL << 28) | (15UL << 23) | (0UL << 21)) +#define CKCU_PLL_8M_60M ((1UL << 28) | (15UL << 23) | (0UL << 21)) +#define CKCU_PLL_12M_60M ((0UL << 28) | ( 5UL << 23) | (0UL << 21)) +#define CKCU_PLL_16M_56M ((1UL << 28) | ( 7UL << 23) | (0UL << 21)) +#endif + +#define IS_PLL_CFG(CFG) (((CFG & 0xE81FFFFF) == 0x0) && (CFG != 0)) +#endif + +#if (LIBCFG_CKCU_USB_PLL) +/* Definitions of USBPLL frequency */ +#if (LIBCFG_CKCU_USB_PLL_96M) +#define CKCU_USBPLL_4M_96M ((24UL << 7) | (0UL << 5)) +#define CKCU_USBPLL_8M_96M ((12UL << 7) | (0UL << 5)) +#define CKCU_USBPLL_12M_96M (( 8UL << 7) | (0UL << 5)) +#define CKCU_USBPLL_16M_96M (( 6UL << 7) | (0UL << 5)) +#else +#define CKCU_USBPLL_4M_48M ((12UL << 7) | (0UL << 5)) +#define CKCU_USBPLL_8M_48M (( 6UL << 7) | (0UL << 5)) +#define CKCU_USBPLL_12M_48M (( 4UL << 7) | (0UL << 5)) +#define CKCU_USBPLL_16M_48M (( 3UL << 7) | (0UL << 5)) +#endif + +#define IS_USBPLL_CFG(CFG) (((CFG & 0xFFFFF81F) == 0x0) && (CFG != 0)) +#endif + + + + +/* Definitions of MCU debug control */ +#define CKCU_DBG_SLEEP (1UL) +#define CKCU_DBG_DEEPSLEEP1 (1UL << 1) +#define CKCU_DBG_POWERDOWN (1UL << 2) +#define CKCU_DBG_WDT_HALT (1UL << 3) + +#if (LIBCFG_MCTM0) +#define CKCU_DBG_MCTM0_HALT (1UL << 4) +#endif + +#if (!LIBCFG_NO_GPTM0) +#define CKCU_DBG_GPTM0_HALT (1UL << 6) +#endif + +#if (LIBCFG_GPTM1) +#define CKCU_DBG_GPTM1_HALT (1UL << 7) +#endif + +#if (!LIBCFG_NO_USART0) +#define CKCU_DBG_USART0_HALT (1UL << 8) +#endif + +#if (LIBCFG_USART1) +#define CKCU_DBG_USART1_HALT (1UL << 9) +#endif + +#define CKCU_DBG_SPI0_HALT (1UL << 10) + +#if (LIBCFG_SPI1) +#define CKCU_DBG_SPI1_HALT (1UL << 11) +#endif + +#if defined(USE_HT32F0006) || defined(USE_HT32F61244_45) +#define CKCU_DBG_QSPI_HALT (1UL << 11) +#endif + +#define CKCU_DBG_I2C0_HALT (1UL << 12) + +#if (LIBCFG_I2C1) +#define CKCU_DBG_I2C1_HALT (1UL << 13) +#endif + +#define CKCU_DBG_DEEPSLEEP2 (1UL << 14) + +#if (LIBCFG_SCI0) +#define CKCU_DBG_SCI0_HALT (1UL << 15) +#endif + +#define CKCU_DBG_BFTM0_HALT (1UL << 16) + +#if (LIBCFG_BFTM1) +#define CKCU_DBG_BFTM1_HALT (1UL << 17) +#endif + +#define CKCU_DBG_UART0_HALT (1UL << 18) + +#if (LIBCFG_UART1) +#define CKCU_DBG_UART1_HALT (1UL << 19) +#endif + +#if (LIBCFG_SCI1) +#define CKCU_DBG_SCI1_HALT (1UL << 21) +#endif + +#if (LIBCFG_SCTM0) +#define CKCU_DBG_SCTM0_HALT (1UL << 22) +#endif + +#if (LIBCFG_SCTM1) +#define CKCU_DBG_SCTM1_HALT (1UL << 23) +#endif + +#if (LIBCFG_SCTM2) +#define CKCU_DBG_SCTM2_HALT (1UL << 24) +#endif + +#if (LIBCFG_SCTM3) +#define CKCU_DBG_SCTM3_HALT (1UL << 25) +#endif + +#if (LIBCFG_CAN0) +#define CKCU_DBG_CAN0_HALT (1UL << 26) +#endif + +#if (LIBCFG_UART2) +#define CKCU_DBG_UART2_HALT (1UL << 26) +#endif + +#if (LIBCFG_UART3) +#define CKCU_DBG_UART3_HALT (1UL << 27) +#endif + +#if (LIBCFG_I2C2) +#define CKCU_DBG_I2C2_HALT (1UL << 28) +#endif + +#if (LIBCFG_PWM2) +#define CKCU_DBG_PWM2_HALT (1UL << 29) +#endif + +#if defined(USE_HT32F52357_67) +#define CKCU_DBG_QSPI_HALT (1UL << 29) +#endif + +#if (LIBCFG_PWM0) +#define CKCU_DBG_PWM0_HALT (1UL << 30) +#endif + +#if (LIBCFG_PWM1) +#define CKCU_DBG_PWM1_HALT (1UL << 31) +#endif + +#define IS_CKCU_DBG(MODE) (((MODE & ~(0xFFEFFFDF)) == 0) && (MODE != 0)) + +/* Definitions of AHB clock control */ +#define CKCU_AHBEN_SLEEP_FMC (1UL) +#define CKCU_AHBEN_SLEEP_SRAM (1UL << 2) +#define CKCU_AHBEN_SLEEP_BM (1UL << 5) +#define CKCU_AHBEN_SLEEP_APB0 (1UL << 6) + +#define IS_CKCU_SLEEP_AHB(PERIPH) (((PERIPH & 0xFFFFFF9A) == 0) && (PERIPH != 0)) + +/* Definitions of HSI Ready Counter Value */ +#if (LIBCFG_CKCU_HSIRDYCR) +#define IS_COUNTER_VALUE(VALUE) ((VALUE) < 0x20) +#endif +/** + * @} + */ + +/* Exported functions --------------------------------------------------------------------------------------*/ +/** @defgroup CKCU_Exported_Functions CKCU exported functions + * @{ + */ +void CKCU_DeInit(void); + +void CKCU_HSICmd(ControlStatus Cmd); +void CKCU_HSECmd(ControlStatus Cmd); +bool CKCU_IS_HSI_USED(CKCU_HSIST_TypeDef Target); +bool CKCU_IS_HSE_USED(CKCU_HSEST_TypeDef Target); +FlagStatus CKCU_GetClockReadyStatus(u32 CKCU_FLAG); +ErrStatus CKCU_WaitHSEReady(void); + +ErrStatus CKCU_SysClockConfig(CKCU_SW_TypeDef CLKSRC); +u32 CKCU_GetSysClockSource(void); + +void CKCU_PeripClockConfig(CKCU_PeripClockConfig_TypeDef Clock, ControlStatus Cmd); + +#if (LIBCFG_NO_PLL) +#else +void CKCU_PLLInit(CKCU_PLLInitTypeDef *PLL_InitStruct); +void CKCU_PLLCmd(ControlStatus Cmd); +bool CKCU_IS_PLL_USED(CKCU_PLLST_TypeDef Target); +#endif + +#if (LIBCFG_CKCU_USB_PLL) +void CKCU_USBPLLInit(CKCU_PLLInitTypeDef *USBPLL_InitStruct); +void CKCU_USBPLLCmd(ControlStatus Cmd); +void CKCU_USBClockConfig(CKCU_USBSRC_TypeDef USBSRC); +#endif + +#if (LIBCFG_CKCU_LCD_SRC) +void CKCU_LCDClockConfig(CKCU_LCDSRC_TypeDef LCDSRC); +#endif + +#if (LIBCFG_CKCU_MCTM_SRC) +void CKCU_MCTMClockConfig(CKCU_MCTMSRC_TypeDef CKCU_MCTMSRC_x); +#endif + +void CKCU_SleepClockConfig(u32 CKCU_CLK, ControlStatus Cmd); + +void CKCU_SetHCLKPrescaler(CKCU_SYSCLKDIV_TypeDef HCLKPRE); +void CKCU_SetCKREFPrescaler(CKCU_CKREFPRE_TypeDef CKREFPRE); +void CKCU_SetADCnPrescaler(CKCU_ADCPRE_ADCn_TypeDef CKCU_ADCPRE_ADCn, CKCU_ADCPRE_TypeDef CKCU_ADCPRE_DIVn); +#define CKCU_SetADCPrescaler(DIV) CKCU_SetADCnPrescaler(CKCU_ADCPRE_ADC0, DIV) + +#if (LIBCFG_MIDI) +void CKCU_SetMIDIPrescaler(CKCU_MIDIPRE_TypeDef MIDIPRE); +#endif + +#if (!LIBCFG_CKCU_NO_APB_PRESCALER) +void CKCU_SetPeripPrescaler(CKCU_PeripPrescaler_TypeDef Perip, CKCU_APBCLKPRE_TypeDef PCLKPRE); +#endif + +void CKCU_GetClocksFrequency(CKCU_ClocksTypeDef* CKCU_Clk); +u32 CKCU_GetPLLFrequency(void); +u32 CKCU_GetPeripFrequency(CKCU_PeripPrescaler_TypeDef Perip); + +void CKCU_CKMCmd(ControlStatus Cmd); +void CKCU_PSRCWKUPCmd(ControlStatus Cmd); + +#if (!LIBCFG_CKCU_NO_LPCR) +void CKCU_BKISOCmd(ControlStatus Cmd); +#endif + +void CKCU_CKOUTConfig(CKCU_CKOUTInitTypeDef *CKOUTInit); +void CKCU_MCUDBGConfig(u32 CKCU_DBGx, ControlStatus Cmd); + +void CKCU_IntConfig(u32 CKCU_INT, ControlStatus Cmd); +FlagStatus CKCU_GetIntStatus(u32 CKCU_INT); +void CKCU_ClearIntFlag(u32 CKCU_INT); + +#if (((LIBCFG_LSE) || (LIBCFG_USBD)) && (!LIBCFG_CKCU_NO_AUTO_TRIM)) +#if (LIBCFG_CKCU_ATM_V01) +void CKCU_ATCInit(CKCU_ATCInitTypeDef* ATC_InitStruct); +#endif +void CKCU_HSIAutoTrimClkConfig(CKCU_ATC_TypeDef CLKSRC); +void CKCU_HSIAutoTrimCmd(ControlStatus Cmd); +bool CKCU_HSIAutoTrimIsReady(void); +#endif + +#if (LIBCFG_CKCU_HSIRDYCR) +void CKCU_Set_HSIReadyCounter(u8 value); +#endif +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f5xxxx_cmp.h b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f5xxxx_cmp.h new file mode 100644 index 0000000000..5869bcd21c --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f5xxxx_cmp.h @@ -0,0 +1,362 @@ +/*********************************************************************************************************//** + * @file ht32f5xxxx_cmp.h + * @version $Rev:: 7319 $ + * @date $Date:: 2023-10-28 #$ + * @brief The header file of the CMP library. + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------------------------------------*/ +#ifndef __HT32F5XXXX_CMP_H +#define __HT32F5XXXX_CMP_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------------------------------------*/ +#include "ht32.h" + +/** @addtogroup HT32F5xxxx_Peripheral_Driver HT32F5xxxx Peripheral Driver + * @{ + */ + +/** @addtogroup CMP + * @{ + */ + + +/* Exported types ------------------------------------------------------------------------------------------*/ +/** @defgroup CMP_Exported_Types CMP exported types + * @{ + */ + +typedef struct +{ + u32 CMP_Wakeup; + u32 CMP_OutputSelection; + u32 CMP_ScalerSource; + u32 CMP_ScalerOutputBuf; + u32 CMP_ScalerEnable; + u32 CMP_CoutSync; + u32 CMP_OutputPol; + #if (LIBCFG_CMP_65x_VER) + u32 CMP_InputSelection; + #endif + u32 CMP_InvInputSelection; + u32 CMP_Hysteresis; + u32 CMP_Speed; +} CMP_InitTypeDef; + +#if (LIBCFG_CMP_CO) +typedef enum +{ + CMP_SYNCOUT_CMPnO = 0, + CMP_SYNCOUT_MCTM_CH0O = 1, + CMP_SYNCOUT_MCTM_CH0NO = 2, + CMP_SYNCOUT_MCTM_CH1O = 3, + CMP_SYNCOUT_MCTM_CH1NO = 4, + CMP_SYNCOUT_MCTM_CH2O = 5, + CMP_SYNCOUT_MCTM_CH2NO = 6, + CMP_SYNCOUT_MCTM_CH3O = 7, + CMP_SYNCOUT_MCTM_CH3OB = 8, // Inverted of MCTM_CH3O +} CMP_SYNCOUT_Enum; +#endif + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------------------------------------*/ +/** @defgroup CMP_Exported_Constants CMP exported constants + * @{ + */ + +/* Definitions of CMP Protection Key */ +#define CMP_PROTECT_KEY ((u32)0x9C3A0000) + + +/* Definitions of CMP Output Status */ +#define CMP_OUTPUT_HIGH ((u32)0x00008000) +#define CMP_OUTPUT_LOW ((u32)0x00000000) + + +/* Definitions of CMP Wakeup Control Bit */ +#define CMP_WUP_ENABLE ((u32)0x00004000) +#define CMP_WUP_DISABLE ((u32)0x00000000) + +#define IS_CMP_Wakeup_Set(x) ((x == CMP_WUP_ENABLE) || (x == CMP_WUP_DISABLE)) + + +/* Definitions of CMP Output Selection for IP Trigger Source */ +#if (LIBCFG_CMP_65x_VER) +#define CMP_TRIG_NONE ((u32)0x0 << 11) +#define CMP_TRIG_GPTM_CH0 ((u32)0x1 << 11) // CMP0 +#define CMP_TRIG_GPTM_CH1 ((u32)0x1 << 11) // CMP1 + +#define IS_CMP_OutputSelection2(x) (0) +#if (LIBCFG_CMP2) +#define CMP_TRIG_GPTM_CH2 ((u32)0x1 << 11) // CMP2 +#undef IS_CMP_OutputSelection2 +#define IS_CMP_OutputSelection2(x) (x == CMP_TRIG_GPTM_CH2) +#endif + +#define CMP_TRIG_GPTM_CH3 ((u32)0x2 << 11) +#define CMP_TRIG_SCTM ((u32)0x3 << 11) +#define CMP_TRIG_MCTM_CH3 ((u32)0x4 << 11) +#define CMP_TRIG_MCTM_BK0 ((u32)0x5 << 11) +#define CMP_TRIG_MCTM_BK1 ((u32)0x6 << 11) +#define CMP_TRIG_ADC ((u32)0x7 << 11) + +#define IS_CMP_OutputSelection(x) ((x == CMP_TRIG_NONE) || \ + (x == CMP_TRIG_GPTM_CH0) || \ + (x == CMP_TRIG_GPTM_CH1) || \ + IS_CMP_OutputSelection2(x) || \ + (x == CMP_TRIG_GPTM_CH3) || \ + (x == CMP_TRIG_SCTM) || \ + (x == CMP_TRIG_MCTM_CH3) || \ + (x == CMP_TRIG_MCTM_BK0) || \ + (x == CMP_TRIG_MCTM_BK1) || \ + (x == CMP_TRIG_ADC)) +#else +#define CMP_TRIG_NONE ((u32)0x0 << 11) +#define CMP_TRIG_GPTM_CH3 ((u32)0x1 << 11) +#if (LIBCFG_MCTM0) +#define CMP_TRIG_MCTM_CH3 ((u32)0x2 << 11) +#define CMP_TRIG_MCTM_BK1 ((u32)0x3 << 11) +#endif +#define CMP_TRIG_ADC ((u32)0x4 << 11) + +#if (LIBCFG_MCTM0) +#define IS_CMP_OutSelMCTM(x) ((x == CMP_TRIG_MCTM_CH3) || (x == CMP_TRIG_MCTM_BK1)) +#else +#define IS_CMP_OutSelMCTM(x) (0) +#endif + +#define IS_CMP_OutputSelection(x) ((x == CMP_TRIG_NONE) || \ + (x == CMP_TRIG_GPTM_CH3) || \ + IS_CMP_OutSelMCTM(x) || \ + (x == CMP_TRIG_ADC)) +#endif + +/* Definitions of CMP Scaler Source Selection */ +#define CMP_SCALER_SRC_VDDA ((u32)0x00000000) + +#if (LIBCFG_CMP_NOSCALER_SRC) +#define IS_CMP_ScalerSource(x) ((x == CMP_SCALER_SRC_VDDA)) +#else +#define CMP_SCALER_SRC_VREF ((u32)0x00000400) +#define IS_CMP_ScalerSource(x) ((x == CMP_SCALER_SRC_VDDA) || (x == CMP_SCALER_SRC_VREF)) +#endif + + +/* Definitions of CMP Scaler Output Enable Bit */ +#define CMP_SCALER_OBUF_DISABLE ((u32)0x00000000) +#define CMP_SCALER_OBUF_ENABLE ((u32)0x00000200) + +#define IS_CMP_ScalerOutputBuf(x) ((x == CMP_SCALER_OBUF_DISABLE) || (x == CMP_SCALER_OBUF_ENABLE)) + + +/* Definitions of CMP Scaler Enable Bit */ +#define CMP_SCALER_DISABLE ((u32)0x00000000) +#define CMP_SCALER_ENABLE ((u32)0x00000100) + +#define IS_CMP_ScalerEnable(x) ((x == CMP_SCALER_DISABLE) || (x == CMP_SCALER_ENABLE)) + + +/* Definitions of CMP Sync Output Enable bit */ +#define CMP_ASYNC_OUTPUT ((u32)0x00000000) +#define CMP_SYNC_OUTPUT ((u32)0x00000080) + +#define IS_CMP_CoutSynchronized(x) ((x == CMP_ASYNC_OUTPUT) || (x == CMP_SYNC_OUTPUT)) + + +/* Definitions of CMP Output Polarity Selection */ +#define CMP_NONINV_OUTPUT ((u32)0x00000000) +#define CMP_INV_OUTPUT ((u32)0x00000040) + +#define IS_CMP_OutputPol_Set(x) ((x == CMP_NONINV_OUTPUT) || (x == CMP_INV_OUTPUT)) + + +/* Definitions of CMP Inverted Input Source Selection */ +#if (LIBCFG_CMP_65x_VER) +#if (LIBCFG_CMP_POS_INPUT_SEL_V2) +#define CMP_INPUT_CMPnP ((u32)0x00000000) +#define CMP_INPUT_CMPnP0 ((u32)0x00000000) +#define CMP_INPUT_CMPnP1 ((u32)0x00000001) +#define CMP_INPUT_CMPnP2 ((u32)0x00000002) +#define CMP_INPUT_OPA0O ((u32)0x00000003) + +#define IS_CMP_InputSelection(x) ((x == CMP_INPUT_CMPnP) || \ + (x == CMP_INPUT_CMPnP0) || \ + (x == CMP_INPUT_CMPnP1) || \ + (x == CMP_INPUT_CMPnP2) || \ + (x == CMP_INPUT_OPA0O)) +#else +#define CMP_INPUT_CMPnP ((u32)0x00000000) +#define CMP_INPUT_OPA0O ((u32)0x00000001) +#define CMP_INPUT_OPA1O ((u32)0x00000002) + +#define IS_CMP_InputSelection(x) ((x == CMP_INPUT_CMPnP) || (x == CMP_INPUT_OPA0O) || (x == CMP_INPUT_OPA1O)) +#endif +#endif + + +/* Definitions of CMP Inverted Input Source Selection */ +#define CMP_EXTERNAL_CN_IN ((u32)0x00000000) +#define CMP_SCALER_CN_IN ((u32)0x00000010) + +#define IS_CMP_InvInSel2(x) (0) + +#if (LIBCFG_CMP_IVREF_CN_IN) +#define CMP_IVREF_CN_IN ((u32)0x00000020) +#undef IS_CMP_InvInSel2 +#define IS_CMP_InvInSel2(x) ((x == CMP_IVREF_CN_IN)) +#endif + +#if defined(USE_HT32F65230_40) +#define CMP_CMP0N_CN_IN ((u32)0x00000020) +#undef IS_CMP_InvInSel2 +#define IS_CMP_InvInSel2(x) ((x == CMP_CMP0N_CN_IN)) +#endif + +#if defined(USE_HT32F65232) +#define CMP0_CMP1N_CN_IN ((u32)0x00000020) +#define CMP1_CMP0N_CN_IN ((u32)0x00000020) +#undef IS_CMP_InvInSel2 +#define IS_CMP_InvInSel2(x) ((x == CMP0_CMP1N_CN_IN)) +#endif + +#define IS_CMP_InvInputSelection(x) ((x == CMP_EXTERNAL_CN_IN) || (x == CMP_SCALER_CN_IN) || IS_CMP_InvInSel2(x)) + + +/* Definitions of CMP Hysteresis Level Selection */ +#define CMP_NO_HYSTERESIS ((u32)0x00000000) +#define CMP_LOW_HYSTERESIS ((u32)0x00000004) +#define CMP_MID_HYSTERESIS ((u32)0x00000008) +#define CMP_HIGH_HYSTERESIS ((u32)0x0000000C) + +#define IS_CMP_Hysteresis_Set(x) ((x == CMP_NO_HYSTERESIS) || (x == CMP_LOW_HYSTERESIS) || (x == CMP_MID_HYSTERESIS) || \ + (x == CMP_HIGH_HYSTERESIS)) + +/* Definitions of CMP Speed Mode Selection */ +#define CMP_HIGH_SPEED ((u32)0x00000002) +#define CMP_LOW_SPEED ((u32)0x00000000) + +#define IS_CMP_Speed_Set(x) ((x == CMP_HIGH_SPEED) || (x == CMP_LOW_SPEED)) + + +/* Definitions of CMP Enable bit */ +#define CMP_ENABLE ((u32)0x00000001) + + +/* Definitions of CMP Output Edge Interrupt Enable bit */ +#define CMP_INT_RE ((u32)0x00000002) +#define CMP_INT_FE ((u32)0x00000001) + +/* Check the CMP Interrupt Parameter */ +#define IS_CMP_INT(x) ((x & 0xFFFFFF00) != 0x0) + + +/* Definitions of CMP Output Edge Detection Enable bit */ +#define CMP_RE_Detect ((u32)0x00000200) +#define CMP_FE_Detect ((u32)0x00000100) + +#define IS_CMP_EdgeDetect(x) ((x == CMP_RE_Detect) || (x == CMP_FE_Detect)) + + +/* Definitions of CMP Output Edge Flag */ +#define CMP_FLAG_RE ((u32)0x00000002) +#define CMP_FLAG_FE ((u32)0x00000001) + +/* Check the CMP flag Parameter */ +#define IS_CMP_FLAG(x) ((x & 0xFFFFFF00) != 0x0) + + +/* Check the CMPx Parameter */ +#if (LIBCFG_CMP2) +#define IS_CMP2(x) (x == HT_CMP2) +#else +#define IS_CMP2(x) (0) +#endif +#define IS_CMP(x) ((x == HT_CMP0) || (x == HT_CMP1) || IS_CMP2(x)) + + +/* Check the Scaler Value */ +#if (LIBCFG_CMP_SCALER_8BIT) +#define IS_SCALER_VALUE(x) (x <= 0xFF) +#else +#define IS_SCALER_VALUE(x) (x <= 0x3F) +#endif + +#if (LIBCFG_CMP_CO) +#define IS_CMP_SYNC_SOURCE(x) ((x == CMP_SYNCOUT_CMPnO) || \ + (x == CMP_SYNCOUT_MCTM_CH0O) || \ + (x == CMP_SYNCOUT_MCTM_CH0NO) || \ + (x == CMP_SYNCOUT_MCTM_CH1O) || \ + (x == CMP_SYNCOUT_MCTM_CH1NO) || \ + (x == CMP_SYNCOUT_MCTM_CH2O) || \ + (x == CMP_SYNCOUT_MCTM_CH2NO) || \ + (x == CMP_SYNCOUT_MCTM_CH3O) || \ + (x == CMP_SYNCOUT_MCTM_CH3OB)) +#endif + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------------------------------------*/ +/** @defgroup CMP_Exported_Functions CMP exported functions + * @{ + */ +void CMP_DeInit(HT_CMP_TypeDef* HT_CMPn); +void CMP_UnprotectConfig(HT_CMP_TypeDef* HT_CMPn); +void CMP_Init(HT_CMP_TypeDef* HT_CMPn, CMP_InitTypeDef* CMP_InitStruct); +void CMP_StructInit(CMP_InitTypeDef* CMP_InitStruct); +void CMP_Cmd(HT_CMP_TypeDef* HT_CMPn, ControlStatus NewState); +void CMP_IntConfig(HT_CMP_TypeDef* HT_CMPn, u32 CMP_INT_x, ControlStatus NewState); +void CMP_EdgeDetectConfig(HT_CMP_TypeDef* HT_CMPn, u32 CMP_xE_Detect, ControlStatus NewState); +FlagStatus CMP_GetFlagStatus(HT_CMP_TypeDef* HT_CMPn, u32 CMP_FLAG_x); +void CMP_ClearFlag(HT_CMP_TypeDef* HT_CMPn, u32 CMP_FLAG_x); +FlagStatus CMP_GetOutputStatus(HT_CMP_TypeDef* HT_CMPn); +void CMP_SetScalerValue(HT_CMP_TypeDef* HT_CMPn, u8 Scaler_Value); +#if (LIBCFG_CMP_CO) +void CMP_Output_SyncSource_Select(HT_CMP_TypeDef* HT_CMPn, CMP_SYNCOUT_Enum CMP_SYNCOUT_x); +#endif +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f5xxxx_crc.h b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f5xxxx_crc.h new file mode 100644 index 0000000000..d6d763777c --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f5xxxx_crc.h @@ -0,0 +1,124 @@ +/*********************************************************************************************************//** + * @file ht32f5xxxx_crc.h + * @version $Rev:: 5031 $ + * @date $Date:: 2020-11-03 #$ + * @brief The header file of the CRC library. + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------------------------------------*/ +#ifndef __HT32F5XXXX_CRC_H +#define __HT32F5XXXX_CRC_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------------------------------------*/ +#include "ht32.h" + +/** @addtogroup HT32F5xxxx_Peripheral_Driver HT32F5xxxx Peripheral Driver + * @{ + */ + +/** @addtogroup CRC + * @{ + */ + + +/* Exported types ------------------------------------------------------------------------------------------*/ +/** @defgroup CRC_Exported_Types CRC exported types + * @{ + */ + +/* Definition of CRC Init Structure */ +typedef enum +{ + CRC_CCITT_POLY = 0, + CRC_16_POLY = 1, + CRC_32_POLY = 2, + CRC_USER_DEFINE = 0xF +} CRC_Mode; + +typedef struct +{ + CRC_Mode Mode; + u32 uSeed; + u32 uCR; +} CRC_InitTypeDef; +/** + * @} + */ + +/* Exported constants --------------------------------------------------------------------------------------*/ +/** @defgroup CRC_Exported_Constants CRC exported constants + * @{ + */ +#define IS_CRC_POLY(POLY) ((POLY == CRC_CCITT_POLY) || \ + (POLY == CRC_16_POLY) || \ + (POLY == CRC_32_POLY) || \ + (POLY == CRC_USER_DEFINE)) + +#define CRC_NORMAL_WR (0) +#define CRC_BIT_RVS_WR (1UL << 2) +#define CRC_BYTE_RVS_WR (1UL << 3) +#define CRC_CMPL_WR (1UL << 4) + +#define CRC_NORMAL_SUM (0) +#define CRC_BIT_RVS_SUM (1UL << 5) +#define CRC_BYTE_RVS_SUM (1UL << 6) +#define CRC_CMPL_SUM (1UL << 7) + +#define IS_CRC_MOD(MOD) ((MOD & 0xFFFFFF00) == 0) +/** + * @} + */ + +/* Exported functions --------------------------------------------------------------------------------------*/ +/** @defgroup CRC_Exported_Functions CRC exported functions + * @{ + */ +void CRC_DeInit(HT_CRC_TypeDef* HT_CRCn); +void CRC_Init(HT_CRC_TypeDef* HT_CRCn, CRC_InitTypeDef* CRC_InitStruct); +u32 CRC_Process(HT_CRC_TypeDef* HT_CRCn, u8 *buffer, u32 length); + +u16 CRC_CCITT(u16 seed, u8 *buffer, u32 length); +u16 CRC_16(u16 seed, u8 *buffer, u32 length); +u32 CRC_32(u32 seed, u8 *buffer, u32 length); +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f5xxxx_dac.h b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f5xxxx_dac.h new file mode 100644 index 0000000000..50b56ac79c --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f5xxxx_dac.h @@ -0,0 +1,130 @@ +/*********************************************************************************************************//** + * @file ht32f5xxxx_dac.h + * @version $Rev:: 7081 $ + * @date $Date:: 2023-08-01 #$ + * @brief The header file of the DAC library. + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------------------------------------*/ +#ifndef __HT32F5XXXX_DAC_H +#define __HT32F5XXXX_DAC_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------------------------------------*/ +#include "ht32.h" + +/** @addtogroup HT32F5xxxx_Peripheral_Driver HT32F5xxxx Peripheral Driver + * @{ + */ + +/** @addtogroup DAC + * @{ + */ + + +/* Exported types ------------------------------------------------------------------------------------------*/ +/** @defgroup DAC_Exported_Types DAC exported types + * @{ + */ + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------------------------------------*/ +/** @defgroup DAC_Exported_Constants DAC exported constants + * @{ + */ +#define ASYNC_MODE (0x00000000) +#define SYNC_MODE (0x00000001) + +#if (LIBCFG_DAC1) +#define IS_DAC(DAC) (((DAC) == HT_DAC0) || ((DAC) == HT_DAC1)) +#else +#define IS_DAC(DAC) ((DAC) == HT_DAC0) +#endif + + +#define IS_DAC_CONVERSION_MODE(MODE) (((MODE) == ASYNC_MODE) || ((MODE) == SYNC_MODE)) + + +#define DAC_CH0 (0) +#define DAC_CH1 (1) + +#define IS_DAC_CHANNEL(CHANNEL) (((CHANNEL) == DAC_CH0) || ((CHANNEL) == DAC_CH1)) + + + +#define DAC_REFERENCE_VDDA (0) +#define DAC_REFERENCE_VREF (1UL << 14) + +#define IS_DAC_REFERENCE(REF) (((REF) == DAC_REFERENCE_VDDA) || ((REF) == DAC_REFERENCE_VREF)) + + +#define DAC_RESOLUTION_12BIT (0) +#define DAC_RESOLUTION_8BIT (1UL << 2) + +#define IS_DAC_RESOLUTION(RES) (((RES) == DAC_RESOLUTION_8BIT) || ((RES) == DAC_RESOLUTION_12BIT)) + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------------------------------------*/ +/** @defgroup DAC_Exported_Functions DAC exported functions + * @{ + */ +void DAC_DeInit(HT_DAC_TypeDef* HT_DACn); + +void DAC_ModeConfig(HT_DAC_TypeDef* HT_DACn, u8 ModeSel); + +void DAC_ReferenceConfig(HT_DAC_TypeDef* HT_DACn, u8 DAC_Ch, u32 RefSel); +void DAC_ResolutionConfig(HT_DAC_TypeDef* HT_DACn, u8 DAC_Ch, u32 ResoSel); + +void DAC_OutBufCmd(HT_DAC_TypeDef* HT_DACn, u8 DAC_Ch, ControlStatus NewState); +void DAC_Cmd(HT_DAC_TypeDef* HT_DACn, u8 DAC_Ch, ControlStatus NewState); + +void DAC_SetData(HT_DAC_TypeDef* HT_DACn, u8 DAC_Ch, u32 Data); +u16 DAC_GetOutData(HT_DAC_TypeDef* HT_DACn, u8 DAC_Ch); + +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f5xxxx_dac_dual16.h b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f5xxxx_dac_dual16.h new file mode 100644 index 0000000000..306cbb125f --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f5xxxx_dac_dual16.h @@ -0,0 +1,92 @@ +/*********************************************************************************************************//** + * @file ht32f5xxxx_dac_dual16.h + * @version $Rev:: 4282 $ + * @date $Date:: 2019-10-18 #$ + * @brief The header file of the DAC library. + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------------------------------------*/ +#ifndef __HT32F5XXXX_DAC_DUAL16_DAC_H +#define __HT32F5XXXX_DAC_DUAL16_DAC_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------------------------------------*/ +#include "ht32.h" + +/** @addtogroup HT32F5xxxx_Peripheral_Driver HT32F5xxxx Peripheral Driver + * @{ + */ + +/** @addtogroup DAC_DUAL16 + * @{ + */ + + +/* Exported types ------------------------------------------------------------------------------------------*/ +/** @defgroup DAC_Exported_Types DAC exported types + * @{ + */ +typedef enum +{ + DAC_CH_R = 0, + DAC_CH_L = 1, +} DAC_Dual16_Ch; + +typedef enum +{ + DATA_FROM_UC = 0, + DATA_FROM_MIDI = 1, +} DAC_Dual16_Source; +/** + * @} + */ + +/* Exported functions --------------------------------------------------------------------------------------*/ +/** @defgroup DAC_DUAL16_Exported_Functions DAC exported functions + * @{ + */ +void DACD16_DeInit(void); +void DACD16_DataSourceConfig(HT_DAC_DUAL16_TypeDef* DACx, DAC_Dual16_Ch DAC_CH_x, DAC_Dual16_Source DATA_FROM_x); +void DACD16_SetChannelData(HT_DAC_DUAL16_TypeDef* DACx, DAC_Dual16_Ch DAC_CH_x, u16 Data); +void DACD16_SoftwareStartConvCmd(HT_DAC_DUAL16_TypeDef* DACx, DAC_Dual16_Ch DAC_CH_x); +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f5xxxx_div.h b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f5xxxx_div.h new file mode 100644 index 0000000000..9cf23f9c31 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f5xxxx_div.h @@ -0,0 +1,113 @@ +/*********************************************************************************************************//** + * @file ht32f5xxxx_div.h + * @version $Rev:: 4617 $ + * @date $Date:: 2020-02-26 #$ + * @brief The header file of the DIV library. + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------------------------------------*/ +#ifndef __HT32F5XXXX_DIV_H +#define __HT32F5XXXX_DIV_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------------------------------------*/ +#include "ht32.h" + +/** @addtogroup HT32F5xxxx_Peripheral_Driver HT32F5xxxx Peripheral Driver + * @{ + */ + +/** @addtogroup DIV + * @{ + */ + +/* Settings ------------------------------------------------------------------------------------------------*/ +/** @defgroup DIV_Settings DIV settings + * @{ + */ +#define DIV_ENABLE_DIVIDE_BY_ZERO_CHECK (0) +/** + * @} + */ + + +/* Exported types ------------------------------------------------------------------------------------------*/ +/** @defgroup DIV_Exported_Types DIV exported types + * @{ + */ + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------------------------------------*/ +/** @defgroup DIV_Exported_Constants DIV exported constants + * @{ + */ + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------------------------------------*/ +/** @defgroup DIV_Exported_Functions DIV exported functions + * @{ + */ +void DIV_DeInit(void); +s32 DIV_Div32(s32 dividend, s32 divisor); +s32 DIV_Mod(s32 dividend, s32 divisor); +bool DIV_IsDivByZero(void); + +u32 DIV_uDiv32(u32 dividend, u32 divisor); +u32 DIV_uGetLastRemainder(void); + +/*********************************************************************************************************//** + * @brief Retuen the remainder of last dividend/divisor calculatation. + * @retval The remainder of dividend/divisor + ************************************************************************************************************/ +__STATIC_INLINE s32 DIV_GetLastRemainder(void) +{ + return (HT_DIV->RMR); +} + +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f5xxxx_ebi.h b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f5xxxx_ebi.h new file mode 100644 index 0000000000..98e6153146 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f5xxxx_ebi.h @@ -0,0 +1,183 @@ +/*********************************************************************************************************//** + * @file ht32f5xxxx_ebi.h + * @version $Rev:: 2772 $ + * @date $Date:: 2018-05-15 #$ + * @brief The header file of the EBI library. + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------------------------------------*/ +#ifndef __HT32F5XXXX_EBI_H +#define __HT32F5XXXX_EBI_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------------------------------------*/ +#include "ht32.h" + +/** @addtogroup HT32F5xxxx_Peripheral_Driver HT32F5xxxx Peripheral Driver + * @{ + */ + +/** @addtogroup EBI + * @{ + */ + + +/* Exported types ------------------------------------------------------------------------------------------*/ +/** @defgroup EBI_Exported_Types EBI exported types + * @{ + */ +typedef struct +{ + u32 EBI_Bank; + u32 EBI_Mode; + u32 EBI_IdleCycle; + u32 EBI_ChipSelectPolarity; + u32 EBI_AddressLatchPolarity; + u32 EBI_WriteEnablePolarity; + u32 EBI_ReadEnablePolarity; + u32 EBI_IdleCycleTime; + u32 EBI_AddressSetupTime; + u32 EBI_AddressHoldTime; + u32 EBI_WriteSetupTime; + u32 EBI_WriteStrobeTime; + u32 EBI_WriteHoldTime; + u32 EBI_ReadSetupTime; + u32 EBI_ReadStrobeTime; + u32 EBI_ReadHoldTime; +} EBI_InitTypeDef; +/** + * @} + */ + +/* Exported constants --------------------------------------------------------------------------------------*/ +/** @defgroup EBI_Exported_Constants EBI exported constants + * @{ + */ +#define EBI_BANK_0 ((u32)0x00000000) +#define EBI_BANK_1 ((u32)0x00000001) +#define EBI_BANK_2 ((u32)0x00000002) +#define EBI_BANK_3 ((u32)0x00000003) + +#define IS_EBI_BANK(BANK) ((BANK == EBI_BANK_0) || \ + (BANK == EBI_BANK_1) || \ + (BANK == EBI_BANK_2) || \ + (BANK == EBI_BANK_3)) + + +#define EBI_MODE_D8A8 ((u32)0x00000000) +#define EBI_MODE_D16A16ALE ((u32)0x00000001) +#define EBI_MODE_D8A24ALE ((u32)0x00000002) +#define EBI_MODE_D16 ((u32)0x00000003) + +#define IS_EBI_MODE(MODE) ((MODE == EBI_MODE_D8A8) || \ + (MODE == EBI_MODE_D16A16ALE) || \ + (MODE == EBI_MODE_D8A24ALE) || \ + (MODE == EBI_MODE_D16)) + + +#define EBI_IDLECYCLE_ENABLE ((u32)0x00000000) +#define EBI_IDLECYCLE_DISABLE ((u32)0x00001000) + +#define IS_EBI_IDLECYCLE(IDLECYCLE) ((IDLECYCLE == EBI_IDLECYCLE_ENABLE) || \ + (IDLECYCLE == EBI_IDLECYCLE_DISABLE)) + + +#define EBI_CHIPSELECTPOLARITY_LOW ((u32)0x00000000) +#define EBI_CHIPSELECTPOLARITY_HIGH ((u32)0x00000001) + +#define IS_EBI_CS_POLARITY(POLARITY) ((POLARITY == EBI_CHIPSELECTPOLARITY_LOW) || \ + (POLARITY == EBI_CHIPSELECTPOLARITY_HIGH)) + + +#define EBI_ADDRESSLATCHPOLARITY_LOW ((u32)0x00000000) +#define EBI_ADDRESSLATCHPOLARITY_HIGH ((u32)0x00000001) + +#define IS_EBI_ALE_POLARITY(POLARITY) ((POLARITY == EBI_ADDRESSLATCHPOLARITY_LOW) || \ + (POLARITY == EBI_ADDRESSLATCHPOLARITY_HIGH)) + + +#define EBI_WRITEENABLEPOLARITY_LOW ((u32)0x00000000) +#define EBI_WRITEENABLEPOLARITY_HIGH ((u32)0x00000001) + +#define IS_EBI_WE_POLARITY(POLARITY) ((POLARITY == EBI_WRITEENABLEPOLARITY_LOW) || \ + (POLARITY == EBI_WRITEENABLEPOLARITY_HIGH)) + + +#define EBI_READENABLEPOLARITY_LOW ((u32)0x00000000) +#define EBI_READENABLEPOLARITY_HIGH ((u32)0x00000001) + +#define IS_EBI_RE_POLARITY(POLARITY) ((POLARITY == EBI_READENABLEPOLARITY_LOW) || \ + (POLARITY == EBI_READENABLEPOLARITY_HIGH)) + + +#define IS_EBI_IDLE_CYCLE_TIME(TIME) (TIME < 0x10) + +#define IS_EBI_ADDRESS_SETUP_TIME(TIME) (TIME < 0x10) + +#define IS_EBI_ADDRESS_HOLD_TIME(TIME) (TIME < 0x10) + +#define IS_EBI_WRITE_SETUP_TIME(TIME) (TIME < 0x10) + +#define IS_EBI_WRITE_STROBE_TIME(TIME) (TIME < 0x40) + +#define IS_EBI_WRITE_HOLD_TIME(TIME) (TIME < 0x10) + +#define IS_EBI_READ_SETUP_TIME(TIME) (TIME < 0x10) + +#define IS_EBI_READ_STROBE_TIME(TIME) (TIME < 0x40) + +#define IS_EBI_READ_HOLD_TIME(TIME) (TIME < 0x10) +/** + * @} + */ + +/* Exported functions --------------------------------------------------------------------------------------*/ +/** @defgroup EBI_Exported_Functions EBI exported functions + * @{ + */ +void EBI_DeInit(void); +void EBI_Init(EBI_InitTypeDef* EBI_InitStruct); +void EBI_StructInit(EBI_InitTypeDef* EBI_InitStruct); +void EBI_Cmd(u32 EBI_Bank, ControlStatus NewState); +FlagStatus EBI_GetBusyStatus(void); +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f5xxxx_exti.h b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f5xxxx_exti.h new file mode 100644 index 0000000000..bdda2d2442 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f5xxxx_exti.h @@ -0,0 +1,263 @@ +/*********************************************************************************************************//** + * @file ht32f5xxxx_exti.h + * @version $Rev:: 6496 $ + * @date $Date:: 2022-11-28 #$ + * @brief The header file of the EXTI library. + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------------------------------------*/ +#ifndef __HT32F5XXXX_EXTI_H +#define __HT32F5XXXX_EXTI_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------------------------------------*/ +#include "ht32.h" + +/** @addtogroup HT32F5xxxx_Peripheral_Driver HT32F5xxxx Peripheral Driver + * @{ + */ + +/** @addtogroup EXTI + * @{ + */ + +/* Exported macro ------------------------------------------------------------------------------------------*/ +/** @defgroup EXTI_Exported_Macro EXTI exported macros + * @{ + */ +/*********************************************************************************************************//** + * @brief Convert the pin number of GPIO to the channel of EXTI. + * @param n: can be 0, 1 to 15 to select the pin number of GPIO. + ************************************************************************************************************/ +#if (LIBCFG_EXTI_8CH) + #define GPIO2EXTI(n) ((n >= 8) ? (n - 8) : n) +#else + #define GPIO2EXTI(n) (n) +#endif + +#define EXTI_GetIRQn(ch) gEXTIn_IRQn[ch] +/** + * @} + */ + +/* Exported types ------------------------------------------------------------------------------------------*/ +/** @defgroup EXTI_Exported_Types EXTI exported types + * @{ + */ + +/* Definitions of EXTI interrupt line */ +typedef enum +{ + EXTI_CHANNEL_0 = 0, + EXTI_CHANNEL_1, + EXTI_CHANNEL_2, + EXTI_CHANNEL_3, + EXTI_CHANNEL_4, + EXTI_CHANNEL_5, + EXTI_CHANNEL_6, + EXTI_CHANNEL_7, +#if (!LIBCFG_EXTI_8CH) + EXTI_CHANNEL_8, + EXTI_CHANNEL_9, + EXTI_CHANNEL_10, + EXTI_CHANNEL_11, + EXTI_CHANNEL_12, + EXTI_CHANNEL_13, + EXTI_CHANNEL_14, + EXTI_CHANNEL_15, +#endif +} EXTI_Channel_TypeDef; + +#if (LIBCFG_EXTI_8CH) +#define IS_CHANNEL_8(x) (0) +#define IS_CHANNEL_9(x) (0) +#define IS_CHANNEL_10(x) (0) +#define IS_CHANNEL_11(x) (0) +#define IS_CHANNEL_12(x) (0) +#define IS_CHANNEL_13(x) (0) +#define IS_CHANNEL_14(x) (0) +#define IS_CHANNEL_15(x) (0) +#else +#define IS_CHANNEL_8(x) (x == EXTI_CHANNEL_8) +#define IS_CHANNEL_9(x) (x == EXTI_CHANNEL_9) +#define IS_CHANNEL_10(x) (x == EXTI_CHANNEL_10) +#define IS_CHANNEL_11(x) (x == EXTI_CHANNEL_11) +#define IS_CHANNEL_12(x) (x == EXTI_CHANNEL_12) +#define IS_CHANNEL_13(x) (x == EXTI_CHANNEL_13) +#define IS_CHANNEL_14(x) (x == EXTI_CHANNEL_14) +#define IS_CHANNEL_15(x) (x == EXTI_CHANNEL_15) +#endif + + +#define IS_EXTI_CHANNEL(CHANNEL) ((CHANNEL == EXTI_CHANNEL_0) || \ + (CHANNEL == EXTI_CHANNEL_1) || \ + (CHANNEL == EXTI_CHANNEL_2) || \ + (CHANNEL == EXTI_CHANNEL_3) || \ + (CHANNEL == EXTI_CHANNEL_4) || \ + (CHANNEL == EXTI_CHANNEL_5) || \ + (CHANNEL == EXTI_CHANNEL_6) || \ + (CHANNEL == EXTI_CHANNEL_7) || \ + IS_CHANNEL_8(CHANNEL) || \ + IS_CHANNEL_9(CHANNEL) || \ + IS_CHANNEL_10(CHANNEL) || \ + IS_CHANNEL_11(CHANNEL) || \ + IS_CHANNEL_12(CHANNEL) || \ + IS_CHANNEL_13(CHANNEL) || \ + IS_CHANNEL_14(CHANNEL) || \ + IS_CHANNEL_15(CHANNEL)) + + +/* Definitions of EXTI init structure */ +typedef enum +{ + EXTI_LOW_LEVEL = 0x0, + EXTI_HIGH_LEVEL = 0x1, + EXTI_NEGATIVE_EDGE = 0x2, + EXTI_POSITIVE_EDGE = 0x3, + EXTI_BOTH_EDGE = 0x4 +} EXTI_Interrupt_TypeDef; + +#define IS_EXTI_INT_TYPE(TYPE) ((TYPE == EXTI_LOW_LEVEL) || \ + (TYPE == EXTI_HIGH_LEVEL) || \ + (TYPE == EXTI_NEGATIVE_EDGE) || \ + (TYPE == EXTI_POSITIVE_EDGE) || \ + (TYPE == EXTI_BOTH_EDGE)) + +typedef enum +{ + EXTI_DEBOUNCE_DISABLE = 0x0, + EXTI_DEBOUNCE_ENABLE = 0x1 +} EXTI_Deb_TypeDef; + +#define IS_EXTI_DEBOUNCE_TYPE(TYPE) ((TYPE == EXTI_DEBOUNCE_DISABLE) || \ + (TYPE == EXTI_DEBOUNCE_ENABLE)) + +#if (LIBCFG_EXTI_DEBCNTPRE) +typedef enum +{ + EXTI_DBCNTPRE_DIV1 = 0, + EXTI_DBCNTPRE_DIV2, + EXTI_DBCNTPRE_DIV4, + EXTI_DBCNTPRE_DIV8, + EXTI_DBCNTPRE_DIV16, + EXTI_DBCNTPRE_DIV32, + EXTI_DBCNTPRE_DIV64, + EXTI_DBCNTPRE_DIV128, +} EXTI_DebCntPre_TypeDef; + +#define IS_EXTI_DEBOUNCE_COUNTER_PRESCALER(TYPE) ((TYPE == EXTI_DBCNTPRE_DIV1) || \ + (TYPE == EXTI_DBCNTPRE_DIV2) || \ + (TYPE == EXTI_DBCNTPRE_DIV4) || \ + (TYPE == EXTI_DBCNTPRE_DIV8) || \ + (TYPE == EXTI_DBCNTPRE_DIV16) || \ + (TYPE == EXTI_DBCNTPRE_DIV32) || \ + (TYPE == EXTI_DBCNTPRE_DIV64) || \ + (TYPE == EXTI_DBCNTPRE_DIV128)) +#endif + +typedef struct +{ + u32 EXTI_Channel; + EXTI_Deb_TypeDef EXTI_Debounce; + #if (LIBCFG_EXTI_8BIT_DEBOUNCE_COUNTER) + u8 EXTI_DebounceCnt; + #else + u16 EXTI_DebounceCnt; + #endif + EXTI_Interrupt_TypeDef EXTI_IntType; +} EXTI_InitTypeDef; +/** + * @} + */ + +/* Exported constants --------------------------------------------------------------------------------------*/ +/** @defgroup EXTI_Exported_Constants EXTI exported constants + * @{ + */ + +/* Definitions of EXTI wake up polarity */ +#define EXTI_WAKEUP_HIGH_LEVEL ((u8)0x0) +#define EXTI_WAKEUP_LOW_LEVEL ((u8)0x1) + +#define IS_EXTI_WAKEUP_TYPE(TYPE) ((TYPE == EXTI_WAKEUP_HIGH_LEVEL) || \ + (TYPE == EXTI_WAKEUP_LOW_LEVEL)) + + +#define EXTI_EDGE_POSITIVE ((u8)0x0) +#define EXTI_EDGE_NEGATIVE ((u8)0x1) + +#define IS_EXTI_EDGE(EDGE) ((EDGE == EXTI_EDGE_POSITIVE) || \ + (EDGE == EXTI_EDGE_NEGATIVE)) + +#if (LIBCFG_EXTI_8BIT_DEBOUNCE_COUNTER) +#define IS_EXTI_DEBOUNCE_SIZE(SIZE) (SIZE <= 0xFF) +#else +#define IS_EXTI_DEBOUNCE_SIZE(SIZE) (SIZE <= 0xFFFF) +#endif + +extern const IRQn_Type gEXTIn_IRQn[16]; + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------------------------------------*/ +/** @defgroup EXTI_Exported_Functions EXTI exported functions + * @{ + */ +void EXTI_DeInit(u32 EXTI_Channel); +void EXTI_Init(EXTI_InitTypeDef* EXTI_InitStruct); +void EXTI_IntConfig(u32 EXTI_Channel, ControlStatus NewState); +#if (LIBCFG_EXTI_DEBCNTPRE) +void EXTI_SetDebounceCounterPrescaler(EXTI_DebCntPre_TypeDef EXTI_DBCNTPRE_DIVn); +#endif +void EXTI_WakeupEventConfig(u32 EXTI_Channel, u8 EXTI_WakeUpType, ControlStatus NewState); +void EXTI_WakeupEventIntConfig(ControlStatus NewState); +void EXTI_ClearEdgeFlag(u32 EXTI_Channel); +void EXTI_ClearWakeupFlag(u32 EXTI_Channel); +FlagStatus EXTI_GetEdgeFlag(u32 EXTI_Channel); +FlagStatus EXTI_GetEdgeStatus(u32 EXTI_Channel, u32 EXTI_Edge); +FlagStatus EXTI_GetWakeupFlagStatus(u32 EXTI_Channel); +void EXTI_SWIntCmd(u32 EXTI_Channel, ControlStatus NewState); +FlagStatus EXTI_GetSWCmdStatus(u32 EXTI_Channel); +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f5xxxx_flash.h b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f5xxxx_flash.h new file mode 100644 index 0000000000..0ee8ba77d7 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f5xxxx_flash.h @@ -0,0 +1,190 @@ +/*********************************************************************************************************//** + * @file ht32f5xxxx_flash.h + * @version $Rev:: 5496 $ + * @date $Date:: 2021-07-19 #$ + * @brief The header file of the FLASH library. + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------------------------------------*/ +#ifndef __HT32F5XXXX_FLASH_H +#define __HT32F5XXXX_FLASH_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------------------------------------*/ +#include "ht32.h" + +/** @addtogroup HT32F5xxxx_Peripheral_Driver HT32F5xxxx Peripheral Driver + * @{ + */ + +/** @addtogroup FLASH + * @{ + */ + + +/* Exported types ------------------------------------------------------------------------------------------*/ +/** @defgroup FLASH_Exported_Types FLASH exported types + * @{ + */ + +/** + * @brief Enumeration of FLASH return status. + */ +typedef enum +{ + FLASH_COMPLETE = 0, + FLASH_ERR_ADDR_OUT_OF_RANGE, + FLASH_ERR_WRITE_PROTECTED, + FLASH_TIME_OUT +} FLASH_State; + +/** + * @brief Enumeration of FLASH boot mode. + */ +typedef enum +{ + FLASH_BOOT_LOADER = 1, + FLASH_BOOT_MAIN = 2 +} FLASH_Vector; + +typedef struct +{ + u32 WriteProtect[4]; + u32 MainSecurity; + u32 OptionProtect; +} FLASH_OptionByte; + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------------------------------------*/ +/** @defgroup FLASH_Exported_Constants FLASH exported constants + * @{ + */ + +/* Flash Information */ +#define FLASH_PAGE_SIZE (LIBCFG_FLASH_PAGESIZE) /* Flash page size */ + +#if (LIBCFG_FMC_PREFETCH) + +/* Flash Wait State */ +#define FLASH_WAITSTATE_0 (0x00000001) /* FLASH zero wait state */ +#define FLASH_WAITSTATE_1 (0x00000002) /* FLASH one wait state */ +#if (LIBCFG_FMC_WAIT_STATE_2) +#define FLASH_WAITSTATE_2 (0x00000003) /* FLASH two wait state */ +#endif + +#if (LIBCFG_FMC_WAIT_STATE_2) +#define FLASH_WAITSTATE_MAX (FLASH_WAITSTATE_2) +#else +#define FLASH_WAITSTATE_MAX (FLASH_WAITSTATE_1) +#endif + +#endif + +/* FLASH OISR Flags */ +#define FLASH_FLAG_ORFF (0x00000001) /* Operation Finished Flag */ +#define FLASH_FLAG_ITADF (0x00000002) /* Invalid Target Address Flag */ +#define FLASH_FLAG_OBEF (0x00000004) /* Option Byte Check Sum Error Flag */ +#define FLASH_FLAG_IOCMF (0x00000008) /* Invalid Operation Command Flag */ +#define FLASH_FLAG_OREF (0x00000010) /* Operation Error Flag */ +#define FLASH_FLAG_RORFF (0x00010000) /* Raw Operation Finished Flag */ +#define FLASH_FLAG_PPEF (0x00020000) /* Page Erase/Program Protected Error Flag */ + +/* FLASH OIER */ +#define FLASH_INT_ORFIEN (0x00000001) /* Flash Operation Finished Interrupt Enable */ +#define FLASH_INT_ITADIEN (0x00000002) /* Invalid Target Address Interrupt Enable */ +#define FLASH_INT_OBEIEN (0x00000004) /* Option Byte Checksum Error Interrupt Enable */ +#define FLASH_INT_IOCMIEN (0x00000008) /* Invalid Operation Command Interrupt Enable */ +#define FLASH_INT_OREIEN (0x00000010) /* Operation Error Interrupt Enable */ +#define FLASH_INT_ALL (0x0000001F) /* Flash all Interrupt Enable */ + +/* Option Bytes Address */ +#define OPTION_BYTE_BASE (0x1FF00000) /* Option Byte Base Address */ +#define OB_PP0 (0x1FF00000) /* Option Byte: Write Protection 0 */ +#define OB_PP1 (0x1FF00004) /* Option Byte: Write Protection 1 */ +#define OB_PP2 (0x1FF00008) /* Option Byte: Write Protection 2 */ +#define OB_PP3 (0x1FF0000C) /* Option Byte: Write Protection 3 */ +#define OB_CP (0x1FF00010) /* Option Byte: Security Protection */ +#define OB_CHECKSUM (0x1FF00020) /* Option Byte: Checksum */ + +/* Flash Write Protection Page Mask */ +#if (LIBCFG_FLASH_2PAGE_PER_WPBIT) + #define FLASH_WP_PAGE_SET(OP, PAGE) (OP.WriteProtect[PAGE / 64] |= 1 << ((PAGE % 64) / 2)) + #define FLASH_WP_PAGE_CLEAR(OP, PAGE) (OP.WriteProtect[PAGE / 64] &= ~(1 << ((PAGE % 64) / 2))) + #define FLASH_IS_WP_PAGE(OP, PAGE) (OP.WriteProtect[PAGE / 64] & (1 << ((PAGE % 64) / 2))) +#else + #define FLASH_WP_PAGE_SET(OP, PAGE) (OP.WriteProtect[PAGE / 32] |= 1 << (PAGE % 32)) + #define FLASH_WP_PAGE_CLEAR(OP, PAGE) (OP.WriteProtect[PAGE / 32] &= ~(1 << (PAGE % 32))) + #define FLASH_IS_WP_PAGE(OP, PAGE) (OP.WriteProtect[PAGE / 32] & (1 << (PAGE % 32))) +#endif +#define FLASH_WP_ALLPAGE_SET(OP) {u32 i; for (i = 0; i < 4; i++) { OP.WriteProtect[i] = 0xFFFFFFFF; } } + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------------------------------------*/ +/** @defgroup FLASH_Exported_Functions FLASH exported functions + * @{ + */ +#if (LIBCFG_FMC_PREFETCH) +void FLASH_SetWaitState(u32 FLASH_WAITSTATE_n); +void FLASH_PrefetchBufferCmd(ControlStatus NewState); +#endif +#if (LIBCFG_FMC_BRANCHCACHE) +void FLASH_BranchCacheCmd(ControlStatus NewState); +#endif +void FLASH_SetRemappingMode(FLASH_Vector RemapMode); +FLASH_State FLASH_ErasePage(u32 PageAddress); +FLASH_State FLASH_EraseOptionByte(void); +FLASH_State FLASH_MassErase(void); +FLASH_State FLASH_ProgramWordData(u32 Address, u32 Data); +FLASH_State FLASH_ProgramOptionByte(FLASH_OptionByte *Option); +void FLASH_GetOptionByteStatus(FLASH_OptionByte *Option); +void FLASH_IntConfig(u32 FLASH_INT, ControlStatus Cmd); +FlagStatus FLASH_GetIntStatus(u32 FLASH_FLAG_x); +void FLASH_ClearIntFlag(u32 FLASH_FLAG_x); +FLASH_State FLASH_WaitForOperationEnd(void); +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f5xxxx_gpio.h b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f5xxxx_gpio.h new file mode 100644 index 0000000000..42f274c4e7 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f5xxxx_gpio.h @@ -0,0 +1,508 @@ +/*********************************************************************************************************//** + * @file ht32f5xxxx_gpio.h + * @version $Rev:: 7115 $ + * @date $Date:: 2023-08-11 #$ + * @brief The header file of the GPIO and AFIO library. + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------------------------------------*/ +#ifndef __HT32F5XXXX_GPIO_H +#define __HT32F5XXXX_GPIO_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------------------------------------*/ +#include "ht32.h" + +/** @addtogroup HT32F5xxxx_Peripheral_Driver HT32F5xxxx Peripheral Driver + * @{ + */ + +/** @addtogroup GPIO + * @{ + */ + + +/* Settings ------------------------------------------------------------------------------------------------*/ +/** @defgroup GPIO_Settings GPIO settings + * @{ + */ +#ifndef AUTO_CK_CONTROL +#define AUTO_CK_CONTROL (0) +#endif +/** + * @} + */ + +/* Exported types ------------------------------------------------------------------------------------------*/ +/** @defgroup GPIO_Exported_Types GPIO exported types + * @{ + */ + +/** + * @brief Enumeration of GPIO pull resistor. + */ +typedef enum +{ + GPIO_PR_UP = 0, /*!< weak pull-up resistor */ + GPIO_PR_DOWN, /*!< weak pull-down resistor */ + GPIO_PR_DISABLE, /*!< Tri-state */ + #if (LIBCFG_GPIO_PR_STRONG_UP) + GPIO_PR_STRONG_UP, /*!< strong pull-up resistor */ + GPIO_PR_STRONGEST_UP /*!< strongest pull-up resistor */ + #endif +} GPIO_PR_Enum; +/** + * @brief Enumeration of GPIO output drive current. + */ +typedef enum +{ + GPIO_DV_4MA = 0, /*!< 4mA source/sink current */ + GPIO_DV_8MA, /*!< 8mA source/sink current */ + GPIO_DV_12MA, /*!< 12mA source/sink current */ + GPIO_DV_16MA /*!< 16mA source/sink current */ +} GPIO_DV_Enum; +/** + * @brief Enumeration of GPIO direction. + */ +typedef enum +{ + GPIO_DIR_IN = 0, /*!< input mode */ + GPIO_DIR_OUT /*!< output mode */ +} GPIO_DIR_Enum; +/** + * @brief Enumeration of AFIO for EXTI channel. + */ +typedef enum +{ + AFIO_EXTI_CH_0 = 0, /*!< GPIO pin 0 */ + AFIO_EXTI_CH_1, /*!< GPIO pin 1 */ + AFIO_EXTI_CH_2, /*!< GPIO pin 2 */ + AFIO_EXTI_CH_3, /*!< GPIO pin 3 */ + AFIO_EXTI_CH_4, /*!< GPIO pin 4 */ + AFIO_EXTI_CH_5, /*!< GPIO pin 5 */ + AFIO_EXTI_CH_6, /*!< GPIO pin 6 */ + AFIO_EXTI_CH_7, /*!< GPIO pin 7 */ + AFIO_EXTI_CH_8, /*!< GPIO pin 8 */ + AFIO_EXTI_CH_9, /*!< GPIO pin 9 */ + AFIO_EXTI_CH_10, /*!< GPIO pin 10 */ + AFIO_EXTI_CH_11, /*!< GPIO pin 11 */ + AFIO_EXTI_CH_12, /*!< GPIO pin 12 */ + AFIO_EXTI_CH_13, /*!< GPIO pin 13 */ + AFIO_EXTI_CH_14, /*!< GPIO pin 14 */ + AFIO_EXTI_CH_15 /*!< GPIO pin 15 */ +} AFIO_EXTI_CH_Enum; +/** + * @brief Enumeration of AFIO_MODE. + */ +typedef enum +{ + AFIO_MODE_DEFAULT = 0, /*!< Default AFIO mode */ + AFIO_MODE_1, /*!< AFIO mode 1 */ + AFIO_MODE_2, /*!< AFIO mode 2 */ + AFIO_MODE_3, /*!< AFIO mode 3 */ + AFIO_MODE_4, /*!< AFIO mode 4 */ + AFIO_MODE_5, /*!< AFIO mode 5 */ + AFIO_MODE_6, /*!< AFIO mode 6 */ + AFIO_MODE_7, /*!< AFIO mode 7 */ + AFIO_MODE_8, /*!< AFIO mode 8 */ + AFIO_MODE_9, /*!< AFIO mode 9 */ + AFIO_MODE_10, /*!< AFIO mode 10 */ + AFIO_MODE_11, /*!< AFIO mode 11 */ + AFIO_MODE_12, /*!< AFIO mode 12 */ + AFIO_MODE_13, /*!< AFIO mode 13 */ + AFIO_MODE_14, /*!< AFIO mode 14 */ + AFIO_MODE_15 /*!< AFIO mode 15 */ +} AFIO_MODE_Enum; +/** + * @} + */ + +/* Exported constants --------------------------------------------------------------------------------------*/ +/** @defgroup GPIO_Exported_Constants GPIO exported constants + * @{ + */ + +/* Definitions of AFIO_FUN */ +#define AFIO_FUN_DEFAULT AFIO_MODE_DEFAULT /*!< Default AFIO mode */ +#define AFIO_FUN_GPIO AFIO_MODE_1 /*!< AFIO mode GPIO */ +#if (LIBCFG_AFIO_SYSTEM_MODE1) +#define AFIO_FUN_SYSTEM AFIO_MODE_1 /*!< AFIO mode System */ +#else +#define AFIO_FUN_SYSTEM AFIO_MODE_15 /*!< AFIO mode System */ +#endif +#if (LIBCFG_AFIO_DAC_MODE3) +#define AFIO_FUN_DAC0 AFIO_MODE_3 /*!< AFIO mode DAC0 */ +#define AFIO_FUN_DAC1 AFIO_MODE_3 /*!< AFIO mode DAC1 */ +#else +#define AFIO_FUN_DAC0 AFIO_MODE_2 /*!< AFIO mode DAC0 */ +#endif +#define AFIO_FUN_ADC0 AFIO_MODE_2 /*!< AFIO mode ADC0 */ +#define AFIO_FUN_ADC1 AFIO_MODE_3 /*!< AFIO mode ADC1 */ +#if (LIBCFG_AFIO_LEDC_MODE3) +#define AFIO_FUN_LEDC AFIO_MODE_3 /*!< AFIO mode LEDC */ +#else +#define AFIO_FUN_LEDC AFIO_MODE_14 /*!< AFIO mode LEDC */ +#endif +#define AFIO_FUN_CMP AFIO_MODE_3 /*!< AFIO mode CMP */ +#define AFIO_FUN_MCTM_GPTM AFIO_MODE_4 /*!< AFIO mode MCTM/GPTM */ +#if (LIBCFG_AFIO_SCTM_MODE4) +#define AFIO_FUN_SCTM AFIO_MODE_4 /*!< AFIO mode SCTM */ +#elif (LIBCFG_AFIO_SCTM_MODE9) +#define AFIO_FUN_SCTM AFIO_MODE_9 /*!< AFIO mode SCTM */ +#else +#define AFIO_FUN_SCTM AFIO_MODE_13 /*!< AFIO mode SCTM */ +#endif +#if (LIBCFG_AFIO_PWM_MODE4) +#define AFIO_FUN_PWM AFIO_MODE_4 /*!< AFIO mode PWM */ +#else +#define AFIO_FUN_PWM AFIO_MODE_13 /*!< AFIO mode PWM */ +#endif +#define AFIO_FUN_SPI AFIO_MODE_5 /*!< AFIO mode SPI */ +#define AFIO_FUN_USART_UART AFIO_MODE_6 /*!< AFIO mode USART/UART */ +#define AFIO_FUN_I2C AFIO_MODE_7 /*!< AFIO mode I2C */ +#define AFIO_FUN_SCI AFIO_MODE_8 /*!< AFIO mode SCI */ +#define AFIO_FUN_CMP_OPA AFIO_MODE_8 /*!< AFIO mode CMP/OPA */ +#define AFIO_FUN_EBI AFIO_MODE_9 /*!< AFIO mode EBI */ +#define AFIO_FUN_I2S AFIO_MODE_10 /*!< AFIO mode I2S */ +#define AFIO_FUN_CAN AFIO_MODE_12 /*!< AFIO mode CAN */ +#define AFIO_FUN_TEKY AFIO_MODE_12 /*!< AFIO mode TKEY */ +#define AFIO_FUN_LCD AFIO_MODE_14 /*!< AFIO mode LCD */ +#define AFIO_FUN_SLED AFIO_MODE_14 /*!< AFIO mode SLED */ + +/* Definitions of AFIO_FUN alias */ +#define AFIO_FUN_MCTM0 AFIO_FUN_MCTM_GPTM + +#define AFIO_FUN_GPTM0 AFIO_FUN_MCTM_GPTM +#define AFIO_FUN_GPTM1 AFIO_FUN_MCTM_GPTM +#define AFIO_FUN_GPTM2 AFIO_FUN_MCTM_GPTM +#define AFIO_FUN_GPTM3 AFIO_FUN_MCTM_GPTM + +#define AFIO_FUN_PWM0 AFIO_FUN_PWM +#define AFIO_FUN_PWM1 AFIO_FUN_PWM +#define AFIO_FUN_PWM2 AFIO_FUN_PWM +#define AFIO_FUN_PWM3 AFIO_FUN_PWM + +#define AFIO_FUN_SCTM0 AFIO_FUN_SCTM +#define AFIO_FUN_SCTM1 AFIO_FUN_SCTM +#define AFIO_FUN_SCTM2 AFIO_FUN_SCTM +#define AFIO_FUN_SCTM3 AFIO_FUN_SCTM + +#define AFIO_FUN_ADC AFIO_FUN_ADC0 + +/* Definitions of GPIO_Px */ +#define GPIO_PORT_NUM (6) +#define GPIO_PIN_NUM (16) +#define GPIO_PA (0) +#define GPIO_PB (1) +#if (LIBCFG_GPIOC) +#define GPIO_PC (2) +#endif +#if (LIBCFG_GPIOD) +#define GPIO_PD (3) +#endif +#if (LIBCFG_GPIOE) +#define GPIO_PE (4) +#endif +#if (LIBCFG_GPIOF) +#define GPIO_PF (5) +#endif + +/* Definitions of GPIO port source for EXTI channel */ +#define AFIO_ESS_PA GPIO_PA /*!< EXTI channel x source come from GPIO Port A */ +#define AFIO_ESS_PB GPIO_PB /*!< EXTI channel x source come from GPIO Port B */ +#if (LIBCFG_GPIOC) +#define AFIO_ESS_PC GPIO_PC /*!< EXTI channel x source come from GPIO Port C */ +#endif +#if (LIBCFG_GPIOD) +#define AFIO_ESS_PD GPIO_PD /*!< EXTI channel x source come from GPIO Port D */ +#endif +#if (LIBCFG_GPIOE) +#define AFIO_ESS_PE GPIO_PE /*!< EXTI channel x source come from GPIO Port E */ +#endif +#if (LIBCFG_GPIOF) +#define AFIO_ESS_PF GPIO_PF /*!< EXTI channel x source come from GPIO Port F */ +#endif + +/* Definitions of GPIO_PIN */ +#define GPIO_PIN_0 0x0001 /*!< GPIO pin 0 selected */ +#define GPIO_PIN_1 0x0002 /*!< GPIO pin 1 selected */ +#define GPIO_PIN_2 0x0004 /*!< GPIO pin 2 selected */ +#define GPIO_PIN_3 0x0008 /*!< GPIO pin 3 selected */ +#define GPIO_PIN_4 0x0010 /*!< GPIO pin 4 selected */ +#define GPIO_PIN_5 0x0020 /*!< GPIO pin 5 selected */ +#define GPIO_PIN_6 0x0040 /*!< GPIO pin 6 selected */ +#define GPIO_PIN_7 0x0080 /*!< GPIO pin 7 selected */ +#define GPIO_PIN_8 0x0100 /*!< GPIO pin 8 selected */ +#define GPIO_PIN_9 0x0200 /*!< GPIO pin 9 selected */ +#define GPIO_PIN_10 0x0400 /*!< GPIO pin 10 selected */ +#define GPIO_PIN_11 0x0800 /*!< GPIO pin 11 selected */ +#define GPIO_PIN_12 0x1000 /*!< GPIO pin 12 selected */ +#define GPIO_PIN_13 0x2000 /*!< GPIO pin 13 selected */ +#define GPIO_PIN_14 0x4000 /*!< GPIO pin 14 selected */ +#define GPIO_PIN_15 0x8000 /*!< GPIO pin 15 selected */ +#define GPIO_PIN_ALL 0xFFFF /*!< GPIO all pins selected */ + +/* Definitions of AFIO_PIN */ +#define AFIO_PIN_0 0x0001 /*!< AFIO pin 0 selected */ +#define AFIO_PIN_1 0x0002 /*!< AFIO pin 1 selected */ +#define AFIO_PIN_2 0x0004 /*!< AFIO pin 2 selected */ +#define AFIO_PIN_3 0x0008 /*!< AFIO pin 3 selected */ +#define AFIO_PIN_4 0x0010 /*!< AFIO pin 4 selected */ +#define AFIO_PIN_5 0x0020 /*!< AFIO pin 5 selected */ +#define AFIO_PIN_6 0x0040 /*!< AFIO pin 6 selected */ +#define AFIO_PIN_7 0x0080 /*!< AFIO pin 7 selected */ +#define AFIO_PIN_8 0x0100 /*!< AFIO pin 8 selected */ +#define AFIO_PIN_9 0x0200 /*!< AFIO pin 9 selected */ +#define AFIO_PIN_10 0x0400 /*!< AFIO pin 10 selected */ +#define AFIO_PIN_11 0x0800 /*!< AFIO pin 11 selected */ +#define AFIO_PIN_12 0x1000 /*!< AFIO pin 12 selected */ +#define AFIO_PIN_13 0x2000 /*!< AFIO pin 13 selected */ +#define AFIO_PIN_14 0x4000 /*!< AFIO pin 14 selected */ +#define AFIO_PIN_15 0x8000 /*!< AFIO pin 15 selected */ +#define AFIO_PIN_ALL 0xFFFF /*!< All AFIO pins selected */ + +/* Definitions of GPIO_PIN_NUM */ +#define GPIO_PIN_NUM_0 0x00 /*!< GPIO pin number 0 selected */ +#define GPIO_PIN_NUM_1 0x01 /*!< GPIO pin number 1 selected */ +#define GPIO_PIN_NUM_2 0x02 /*!< GPIO pin number 2 selected */ +#define GPIO_PIN_NUM_3 0x03 /*!< GPIO pin number 3 selected */ +#define GPIO_PIN_NUM_4 0x04 /*!< GPIO pin number 4 selected */ +#define GPIO_PIN_NUM_5 0x05 /*!< GPIO pin number 5 selected */ +#define GPIO_PIN_NUM_6 0x06 /*!< GPIO pin number 6 selected */ +#define GPIO_PIN_NUM_7 0x07 /*!< GPIO pin number 7 selected */ +#define GPIO_PIN_NUM_8 0x08 /*!< GPIO pin number 8 selected */ +#define GPIO_PIN_NUM_9 0x09 /*!< GPIO pin number 9 selected */ +#define GPIO_PIN_NUM_10 0x0A /*!< GPIO pin number 10 selected */ +#define GPIO_PIN_NUM_11 0x0B /*!< GPIO pin number 11 selected */ +#define GPIO_PIN_NUM_12 0x0C /*!< GPIO pin number 12 selected */ +#define GPIO_PIN_NUM_13 0x0D /*!< GPIO pin number 13 selected */ +#define GPIO_PIN_NUM_14 0x0E /*!< GPIO pin number 14 selected */ +#define GPIO_PIN_NUM_15 0x0F /*!< GPIO pin number 15 selected */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------------------------------------*/ +/** @defgroup GPIO_Exported_Macro GPIO exported macro + * @{ + */ +/* check parameter of the GPIOx */ +#define IS_GPIO(x) (IS_GPIO1(x) || IS_GPIO2(x) || IS_GPIO3(x) || IS_GPIO4(x) || IS_GPIO5(x)) + +#define IS_GPIO1(x) ((x == HT_GPIOA) || (x == HT_GPIOB) ) + +#if (LIBCFG_GPIOC) +#define IS_GPIO2(x) (x == HT_GPIOC) +#else +#define IS_GPIO2(x) (0) +#endif +#if (LIBCFG_GPIOD) +#define IS_GPIO3(x) (x == HT_GPIOD) +#else +#define IS_GPIO3(x) (0) +#endif +#if (LIBCFG_GPIOE) +#define IS_GPIO4(x) (x == HT_GPIOE) +#else +#define IS_GPIO4(x) (0) + #endif +#if (LIBCFG_GPIOF) +#define IS_GPIO5(x) (x == HT_GPIOF) +#else +#define IS_GPIO5(x) (0) +#endif + +/* check parameter of the GPIO_Px */ +#define IS_GPIO_PORT(x) (IS_GPIO_PORT1(x) || IS_GPIO_PORT2(x) || IS_GPIO_PORT3(x) || IS_GPIO_PORT4(x) || IS_GPIO_PORT5(x)) + +#define IS_GPIO_PORT1(x) ((x == GPIO_PA) || (x == GPIO_PB)) + +#if (LIBCFG_GPIOC) +#define IS_GPIO_PORT2(x) (x == GPIO_PC) +#else +#define IS_GPIO_PORT2(x) (0) +#endif +#if (LIBCFG_GPIOD) +#define IS_GPIO_PORT3(x) (x == GPIO_PD) +#else +#define IS_GPIO_PORT3(x) (0) +#endif +#if (LIBCFG_GPIOE) +#define IS_GPIO_PORT4(x) (x == GPIO_PE) +#else +#define IS_GPIO_PORT4(x) (0) +#endif +#if (LIBCFG_GPIOF) +#define IS_GPIO_PORT5(x) (x == GPIO_PF) +#else +#define IS_GPIO_PORT5(x) (0) +#endif + +/* check parameter of the GPIO_PIN_NUM */ +#define IS_GPIO_PIN_NUM(x) (x < 16) + + +#define IS_GPIO_PR_UP(x) (x == GPIO_PR_UP) +#define IS_GPIO_PR_DOWN(x) (x == GPIO_PR_DOWN) +#define IS_GPIO_PR_DISABLE(x) (x == GPIO_PR_DISABLE) + +#if (LIBCFG_GPIO_PR_STRONG_UP) +#define IS_GPIO_PR_STRONG_UP(x) (x == GPIO_PR_STRONG_UP) +#define IS_GPIO_PR_STRONGEST_UP(x) (x == GPIO_PR_STRONGEST_UP) +#else +#define IS_GPIO_PR_STRONG_UP(x) (0) +#define IS_GPIO_PR_STRONGEST_UP(x) (0) +#endif + +/* check parameter of the GPIOx pull resistor */ +#define IS_GPIO_PR(x) (IS_GPIO_PR_UP(x) || \ + IS_GPIO_PR_DOWN(x) || \ + IS_GPIO_PR_DISABLE(x) || \ + IS_GPIO_PR_STRONG_UP(x) || \ + IS_GPIO_PR_STRONGEST_UP(x)) + +/* check parameter of the GPIOx driving current */ +#define IS_GPIO_DV(x) (((x) == GPIO_DV_4MA) || ((x) == GPIO_DV_8MA) || ((x) == GPIO_DV_12MA) || ((x) == GPIO_DV_16MA) ) + +/* check parameter of the GPIOx input/output direction */ +#define IS_GPIO_DIR(x) (((x) == GPIO_DIR_IN) || ((x) == GPIO_DIR_OUT)) + +/* check parameter of the EXTI source port */ +#define IS_AFIO_ESS(x) (IS_AFIO_ESS1(x) || IS_AFIO_ESS2(x) || IS_AFIO_ESS3(x) || IS_AFIO_ESS4(x) || IS_AFIO_ESS5(x)) + +#define IS_AFIO_ESS1(x) ((x == AFIO_ESS_PA) || (x == AFIO_ESS_PB)) +#if (LIBCFG_GPIOC) +#define IS_AFIO_ESS2(x) (x == AFIO_ESS_PC) +#else +#define IS_AFIO_ESS2(x) (0) +#endif +#if (LIBCFG_GPIOD) +#define IS_AFIO_ESS3(x) (x == AFIO_ESS_PD) +#else +#define IS_AFIO_ESS3(x) (0) +#endif +#if (LIBCFG_GPIOE) +#define IS_AFIO_ESS4(x) (x == AFIO_ESS_PE) +#else +#define IS_AFIO_ESS4(x) (0) +#endif +#if (LIBCFG_GPIOF) +#define IS_AFIO_ESS5(x) (x == AFIO_ESS_PF) +#else +#define IS_AFIO_ESS5(x) (0) +#endif + +/* check parameter of the EXTI channel */ +#if (LIBCFG_EXTI_8CH) +#define IS_AFIO_EXTI_CH(x) ((x == AFIO_EXTI_CH_0) || (x == AFIO_EXTI_CH_1) || \ + (x == AFIO_EXTI_CH_2) || (x == AFIO_EXTI_CH_3) || \ + (x == AFIO_EXTI_CH_4) || (x == AFIO_EXTI_CH_5) || \ + (x == AFIO_EXTI_CH_6) || (x == AFIO_EXTI_CH_7)) +#else +#define IS_AFIO_EXTI_CH(x) ((x == AFIO_EXTI_CH_0) || (x == AFIO_EXTI_CH_1) || \ + (x == AFIO_EXTI_CH_2) || (x == AFIO_EXTI_CH_3) || \ + (x == AFIO_EXTI_CH_4) || (x == AFIO_EXTI_CH_5) || \ + (x == AFIO_EXTI_CH_6) || (x == AFIO_EXTI_CH_7) || \ + (x == AFIO_EXTI_CH_8) || (x == AFIO_EXTI_CH_9) || \ + (x == AFIO_EXTI_CH_10) || (x == AFIO_EXTI_CH_11) || \ + (x == AFIO_EXTI_CH_12) || (x == AFIO_EXTI_CH_13) || \ + (x == AFIO_EXTI_CH_14) || (x == AFIO_EXTI_CH_15)) +#endif + +/* check parameter of the AFIO mode */ +#if (LIBCFG_AFIO_MODE_0_7) +#define IS_AFIO_MODE(x) ((x == AFIO_MODE_DEFAULT) || (x == AFIO_MODE_1) || \ + (x == AFIO_MODE_2) || (x == AFIO_MODE_3) || \ + (x == AFIO_MODE_4) || (x == AFIO_MODE_5) || \ + (x == AFIO_MODE_6) || (x == AFIO_MODE_7)) +#else +#define IS_AFIO_MODE(x) ((x == AFIO_MODE_DEFAULT) || (x == AFIO_MODE_1) || \ + (x == AFIO_MODE_2) || (x == AFIO_MODE_3) || \ + (x == AFIO_MODE_4) || (x == AFIO_MODE_5) || \ + (x == AFIO_MODE_6) || (x == AFIO_MODE_7) || \ + (x == AFIO_MODE_8) || (x == AFIO_MODE_9) || \ + (x == AFIO_MODE_10) || (x == AFIO_MODE_11) || \ + (x == AFIO_MODE_12) || (x == AFIO_MODE_13) || \ + (x == AFIO_MODE_14) || (x == AFIO_MODE_15)) +#endif +/** + * @} + */ + +/* Exported functions --------------------------------------------------------------------------------------*/ +/** @defgroup GPIO_Exported_Functions GPIO exported functions + * @{ + */ + +/* Prototype of related GPIO function */ +void GPIO_DeInit(HT_GPIO_TypeDef* HT_GPIOx); +void GPIO_DirectionConfig(HT_GPIO_TypeDef* HT_GPIOx, u16 GPIO_PIN_nBITMAP, GPIO_DIR_Enum GPIO_DIR_INorOUT); +void GPIO_PullResistorConfig(HT_GPIO_TypeDef* HT_GPIOx, u16 GPIO_PIN_nBITMAP, GPIO_PR_Enum GPIO_PR_x); +void GPIO_InputConfig(HT_GPIO_TypeDef* HT_GPIOx, u16 GPIO_PIN_nBITMAP, ControlStatus Cmd); +void GPIO_DriveConfig(HT_GPIO_TypeDef* HT_GPIOx, u16 GPIO_PIN_nBITMAP, GPIO_DV_Enum GPIO_DV_nMA); +void GPIO_OpenDrainConfig(HT_GPIO_TypeDef* HT_GPIOx, u16 GPIO_PIN_nBITMAP, ControlStatus Cmd); +#if LIBCFG_GPIO_SINK_CURRENT_ENHANCED +void GPIO_SinkConfig(HT_GPIO_TypeDef* HT_GPIOx, u16 GPIO_PIN_n, ControlStatus Cmd); +#endif +FlagStatus GPIO_ReadInBit(HT_GPIO_TypeDef* HT_GPIOx, u16 GPIO_PIN_n); +FlagStatus GPIO_ReadOutBit(HT_GPIO_TypeDef* HT_GPIOx, u16 GPIO_PIN_n); +u16 GPIO_ReadInData(HT_GPIO_TypeDef* HT_GPIOx); +u16 GPIO_ReadOutData(HT_GPIO_TypeDef* HT_GPIOx); +void GPIO_SetOutBits(HT_GPIO_TypeDef* HT_GPIOx, u16 GPIO_PIN_nBITMAP); +void GPIO_ClearOutBits(HT_GPIO_TypeDef* HT_GPIOx, u16 GPIO_PIN_nBITMAP); +void GPIO_WriteOutBits(HT_GPIO_TypeDef* HT_GPIOx, u16 GPIO_PIN_nBITMAP, FlagStatus Status); +void GPIO_WriteOutData(HT_GPIO_TypeDef* HT_GPIOx, u16 Data); +void GPIO_PinLock(HT_GPIO_TypeDef* HT_GPIOx, u16 GPIO_PIN_nBITMAP); +bool GPIO_IsPortLocked(HT_GPIO_TypeDef* HT_GPIOx); +bool GPIO_IsPinLocked(HT_GPIO_TypeDef* HT_GPIOx, u16 GPIO_PIN_n); +#if (LIBCFG_GPIO_DISABLE_DEBUG_PORT) +void GPIO_DisableDebugPort(void); +#endif +u32 GPIO_GetID(HT_GPIO_TypeDef* HT_GPIOx); + +/* Prototype of related AFIO function */ +void AFIO_DeInit(void); +void AFIO_GPxConfig(u32 GPIO_Px, u32 AFIO_PIN_n, AFIO_MODE_Enum AFIO_MODE_n); +void AFIO_EXTISourceConfig(u32 GPIO_PIN_NUM_n, u32 GPIO_Px); +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f5xxxx_i2c.h b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f5xxxx_i2c.h new file mode 100644 index 0000000000..1f822f93d6 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f5xxxx_i2c.h @@ -0,0 +1,412 @@ +/*********************************************************************************************************//** + * @file ht32f5xxxx_i2c.h + * @version $Rev:: 7104 $ + * @date $Date:: 2023-08-08 #$ + * @brief The header file of the I2C library. + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------------------------------------*/ +#ifndef __HT32F5XXXX_I2C_H +#define __HT32F5XXXX_I2C_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------------------------------------*/ +#include "ht32.h" + +/** @addtogroup HT32F5xxxx_Peripheral_Driver HT32F5xxxx Peripheral Driver + * @{ + */ + +/** @addtogroup I2C + * @{ + */ + + +/* Exported types ------------------------------------------------------------------------------------------*/ +/** @defgroup I2C_Exported_Types I2C exported types + * @{ + */ + +#if (LIBCFG_I2C_TWO_DEV_ADDR) +typedef u8 I2C_AddressTypeDef; +#else +typedef u16 I2C_AddressTypeDef; +#endif + +typedef struct +{ + u8 I2C_GeneralCall; + u8 I2C_AddressingMode; + u8 I2C_Acknowledge; + u8 I2C_SpeedOffset; /* Offset value to reach real speed, recommended I2C_SpeedOffset = I2C PCLK/8000000 */ + /* which based on 4.7K Pull up */ + u32 I2C_Speed; + u16 I2C_OwnAddress; +} I2C_InitTypeDef; + +#if (LIBCFG_I2C_TWO_DEV_ADDR) +typedef enum +{ + I2C_DEV_ADDR_0 = 0, + I2C_DEV_ADDR_1 +} I2C_ADDR_Enum; + +#define IS_I2C_ADDR(x) ((x == I2C_DEV_ADDR_0) || (x == I2C_DEV_ADDR_1)) +#endif +/** + * @} + */ + +/* Exported constants --------------------------------------------------------------------------------------*/ +/** @defgroup I2C_Exported_Constants I2C exported constants + * @{ + */ +#define I2C_GENERALCALL_ENABLE ((u32)0x00000004) +#define I2C_GENERALCALL_DISABLE ((u32)0x00000000) + +#define IS_I2C_GENERAL_CALL(CALL) ((CALL == I2C_GENERALCALL_ENABLE) || \ + (CALL == I2C_GENERALCALL_DISABLE)) + +#define I2C_ADDRESSING_7BIT ((u32)0x00000000) +#if (LIBCFG_I2C_NO_10BIT_MODE) +#define IS_I2C_ACKNOWLEDGE_ADDRESS(ADDRESS) ((ADDRESS == I2C_ADDRESSING_7BIT)) +#else +#define I2C_ADDRESSING_10BIT ((u32)0x00000080) + +#define IS_I2C_ACKNOWLEDGE_ADDRESS(ADDRESS) ((ADDRESS == I2C_ADDRESSING_7BIT) || \ + (ADDRESS == I2C_ADDRESSING_10BIT)) +#endif + +#define I2C_ACK_ENABLE ((u32)0x00000001) +#define I2C_ACK_DISABLE ((u32)0x00000000) + +#define IS_I2C_ACKNOWLEDGE(ACKNOWLEDGE) ((ACKNOWLEDGE == I2C_ACK_ENABLE) || \ + (ACKNOWLEDGE == I2C_ACK_DISABLE)) + +#if (LIBCFG_I2C_TWO_DEV_ADDR) +#define I2C_DEV_ADDR0_ENABLE ((u32)0x00008000) +#define I2C_DEV_ADDR0_DISABLE ((u32)0x00000000) + +#define IS_I2C_ADDR0_ENABLE(ADDR) ((ADDR == I2C_ADDR0_ENABLE) || \ + (ADDR == I2C_ADDR0_DISABLE)) + +#define I2C_DEV_ADDR1_ENABLE ((u32)0x80000000) +#define I2C_DEV_ADDR1_DISABLE ((u32)0x00000000) + +#define IS_I2C_ADDR1(ADDR) ((ADDR == I2C_ADDR1_ENABLE) || \ + (ADDR == I2C_ADDR1_DISABLE)) +#endif + +#define I2C_INT_STA ((u32)0x00000001) +#define I2C_INT_STO ((u32)0x00000002) +#define I2C_INT_ADRS ((u32)0x00000004) +#define I2C_INT_GCS ((u32)0x00000008) +#if (LIBCFG_I2C_NO_ARBLOS == 0) +#define I2C_INT_ARBLOS ((u32)0x00000100) +#endif +#define I2C_INT_RXNACK ((u32)0x00000200) +#define I2C_INT_BUSERR ((u32)0x00000400) +#define I2C_INT_TOUT ((u32)0x00000800) +#define I2C_INT_RXDNE ((u32)0x00010000) +#define I2C_INT_TXDE ((u32)0x00020000) +#define I2C_INT_RXBF ((u32)0x00040000) +#if (LIBCFG_I2C_NO_ARBLOS) +#define I2C_INT_ALL ((u32)0x00070E0F) +#else +#define I2C_INT_ALL ((u32)0x00070F0F) +#endif + +#if (LIBCFG_I2C_NO_ARBLOS) +#define IS_I2C_INT(int) (((int & 0xFFF8F1F0) == 0x0) && (int != 0x0)) +#else +#define IS_I2C_INT(int) (((int & 0xFFF8F0F0) == 0x0) && (int != 0x0)) +#endif + +#define I2C_MASTER_READ ((u32)0x00000400) +#define I2C_MASTER_WRITE ((u32)0x00000000) + +#define IS_I2C_DIRECTION(DIRECTION) ((DIRECTION == I2C_MASTER_READ) || \ + (DIRECTION == I2C_MASTER_WRITE)) + + +#define I2C_REGISTER_CR ((u8)0x00) +#define I2C_REGISTER_IER ((u8)0x04) +#define I2C_REGISTER_ADDR ((u8)0x08) +#define I2C_REGISTER_SR ((u8)0x0C) +#define I2C_REGISTER_SHPGR ((u8)0x10) +#define I2C_REGISTER_SLPGR ((u8)0x14) +#define I2C_REGISTER_DR ((u8)0x18) +#define I2C_REGISTER_BFCLR ((u8)0x1C) +#define I2C_REGISTER_TAR ((u8)0x20) + +#define IS_I2C_REGISTER(REGISTER) ((REGISTER == I2C_REGISTER_CR) || \ + (REGISTER == I2C_REGISTER_IER) || \ + (REGISTER == I2C_REGISTER_ADDR) || \ + (REGISTER == I2C_REGISTER_SR) || \ + (REGISTER == I2C_REGISTER_SHPGR) || \ + (REGISTER == I2C_REGISTER_SLPGR) || \ + (REGISTER == I2C_REGISTER_DR) || \ + (REGISTER == I2C_REGISTER_BFCLR) || \ + (REGISTER == I2C_REGISTER_TAR)) + + +#define I2C_FLAG_STA ((u32)0x00000001) +#define I2C_FLAG_STO ((u32)0x00000002) +#define I2C_FLAG_ADRS ((u32)0x00000004) +#define I2C_FLAG_GCS ((u32)0x00000008) +#if (LIBCFG_I2C_NO_ARBLOS) +#define IS_FLAG_ARBLOS(x) (0) +#else +#define I2C_FLAG_ARBLOS ((u32)0x00000100) +#define IS_FLAG_ARBLOS(x) (x == I2C_FLAG_ARBLOS) +#endif +#define I2C_FLAG_RXNACK ((u32)0x00000200) +#define I2C_FLAG_BUSERR ((u32)0x00000400) +#define I2C_FLAG_TOUTF ((u32)0x00000800) +#define I2C_FLAG_RXDNE ((u32)0x00010000) +#define I2C_FLAG_TXDE ((u32)0x00020000) +#define I2C_FLAG_RXBF ((u32)0x00040000) +#define I2C_FLAG_BUSBUSY ((u32)0x00080000) +#define I2C_FLAG_MASTER ((u32)0x00100000) +#define I2C_FLAG_TXNRX ((u32)0x00200000) + +#define IS_I2C_FLAG(FLAG) ((FLAG == I2C_FLAG_STA) || \ + (FLAG == I2C_FLAG_STO) || \ + (FLAG == I2C_FLAG_ADRS) || \ + (FLAG == I2C_FLAG_GCS) || \ + IS_FLAG_ARBLOS(FLAG) || \ + (FLAG == I2C_FLAG_RXNACK) || \ + (FLAG == I2C_FLAG_BUSERR) || \ + (FLAG == I2C_FLAG_TOUTF) || \ + (FLAG == I2C_FLAG_RXDNE) || \ + (FLAG == I2C_FLAG_TXDE) || \ + (FLAG == I2C_FLAG_RXBF) || \ + (FLAG == I2C_FLAG_BUSBUSY)|| \ + (FLAG == I2C_FLAG_MASTER) || \ + (FLAG == I2C_FLAG_TXNRX)) + +#define IS_I2C_CLEAR_FLAG(FLAG) (IS_FLAG_ARBLOS(FLAG) || \ + (FLAG == I2C_FLAG_RXNACK) || \ + (FLAG == I2C_FLAG_BUSERR) || \ + (FLAG == I2C_FLAG_TOUTF)) + +#define I2C_MASTER_SEND_START ((u32)0x00180001) +#define I2C_MASTER_RECEIVER_MODE ((u32)0x00180004) +#define I2C_MASTER_TRANSMITTER_MODE ((u32)0x003A0004) +#define I2C_MASTER_RX_NOT_EMPTY ((u32)0x00190000) +#define I2C_MASTER_RX_NOT_EMPTY_NOBUSY ((u32)0x00010000) +#define I2C_MASTER_TX_EMPTY ((u32)0x003A0000) +#define I2C_MASTER_RX_BUFFER_FULL ((u32)0x001D0000) +#define I2C_SLAVE_ACK_TRANSMITTER_ADDRESS ((u32)0x002A0004) +#define I2C_SLAVE_ACK_RECEIVER_ADDRESS ((u32)0x00080004) +#define I2C_SLAVE_ACK_GCALL_ADDRESS ((u32)0x00080008) +#define I2C_SLAVE_RX_NOT_EMPTY ((u32)0x00090000) +#define I2C_SLAVE_RX_NOT_EMPTY_STOP ((u32)0x00010002) +#define I2C_SLAVE_TX_EMPTY ((u32)0x002A0000) +#define I2C_SLAVE_RX_BUFFER_FULL ((u32)0x000D0000) +#define I2C_SLAVE_RECEIVED_NACK ((u32)0x00080200) +#define I2C_SLAVE_RECEIVED_NACK_STOP ((u32)0x00000202) +#define I2C_SLAVE_STOP_DETECTED ((u32)0x00000002) + + +#define IS_I2C_STATUS(STATUS) ((STATUS == I2C_MASTER_SEND_START) || \ + (STATUS == I2C_MASTER_RECEIVER_MODE) || \ + (STATUS == I2C_MASTER_TRANSMITTER_MODE) || \ + (STATUS == I2C_MASTER_RX_NOT_EMPTY) || \ + (STATUS == I2C_MASTER_RX_NOT_EMPTY_NOBUSY) || \ + (STATUS == I2C_MASTER_TX_EMPTY) || \ + (STATUS == I2C_MASTER_RX_BUFFER_FULL) || \ + (STATUS == I2C_SLAVE_ACK_TRANSMITTER_ADDRESS) || \ + (STATUS == I2C_SLAVE_ACK_RECEIVER_ADDRESS) || \ + (STATUS == I2C_SLAVE_ACK_GCALL_ADDRESS) || \ + (STATUS == I2C_SLAVE_RX_NOT_EMPTY) || \ + (STATUS == I2C_SLAVE_RX_NOT_EMPTY_STOP) || \ + (STATUS == I2C_SLAVE_TX_EMPTY) || \ + (STATUS == I2C_SLAVE_RX_BUFFER_FULL) || \ + (STATUS == I2C_SLAVE_RECEIVED_NACK) || \ + (STATUS == I2C_SLAVE_RECEIVED_NACK_STOP) || \ + (STATUS == I2C_SLAVE_STOP_DETECTED)) + +#if (LIBCFG_PDMA) +#define I2C_PDMAREQ_TX ((u32)0x00000100) +#define I2C_PDMAREQ_RX ((u32)0x00000200) + +#define IS_I2C_PDMA_REQ(REQ) (((REQ & 0xFFFFFCFF) == 0x0) && (REQ != 0x0)) +#endif + +#define I2C_PRESCALER_1 ((u32)0x00000000) +#define I2C_PRESCALER_2 ((u32)0x00010000) +#define I2C_PRESCALER_4 ((u32)0x00020000) +#define I2C_PRESCALER_8 ((u32)0x00030000) +#if (LIBCFG_I2C_PRESCALER_2BIT == 0) +#define I2C_PRESCALER_16 ((u32)0x00040000) +#define I2C_PRESCALER_32 ((u32)0x00050000) +#define I2C_PRESCALER_64 ((u32)0x00060000) +#define I2C_PRESCALER_128 ((u32)0x00070000) +#endif + +#if (LIBCFG_I2C_PRESCALER_2BIT) +#define IS_I2C_PRESCALER(PRESCALER) ((PRESCALER == I2C_PRESCALER_1) || \ + (PRESCALER == I2C_PRESCALER_2) || \ + (PRESCALER == I2C_PRESCALER_4) || \ + (PRESCALER == I2C_PRESCALER_8)) +#else +#define IS_I2C_PRESCALER(PRESCALER) ((PRESCALER == I2C_PRESCALER_1) || \ + (PRESCALER == I2C_PRESCALER_2) || \ + (PRESCALER == I2C_PRESCALER_4) || \ + (PRESCALER == I2C_PRESCALER_8) || \ + (PRESCALER == I2C_PRESCALER_16) || \ + (PRESCALER == I2C_PRESCALER_32) || \ + (PRESCALER == I2C_PRESCALER_64) || \ + (PRESCALER == I2C_PRESCALER_128)) +#endif + +#if (LIBCFG_I2C_NO_ADDR_MASK == 0) +#define I2C_MASKBIT_0 ((u32)0x00000001) +#define I2C_MASKBIT_1 ((u32)0x00000002) +#define I2C_MASKBIT_2 ((u32)0x00000004) +#define I2C_MASKBIT_3 ((u32)0x00000008) +#define I2C_MASKBIT_4 ((u32)0x00000010) +#define I2C_MASKBIT_5 ((u32)0x00000020) +#define I2C_MASKBIT_6 ((u32)0x00000040) +#define I2C_MASKBIT_7 ((u32)0x00000080) +#define I2C_MASKBIT_8 ((u32)0x00000100) +#define I2C_MASKBIT_9 ((u32)0x00000200) + + +#define IS_I2C_ADDRESS_MASK(MASK) ((MASK == I2C_MASKBIT_0) || \ + (MASK == I2C_MASKBIT_1) || \ + (MASK == I2C_MASKBIT_2) || \ + (MASK == I2C_MASKBIT_3) || \ + (MASK == I2C_MASKBIT_4) || \ + (MASK == I2C_MASKBIT_5) || \ + (MASK == I2C_MASKBIT_6) || \ + (MASK == I2C_MASKBIT_7) || \ + (MASK == I2C_MASKBIT_8) || \ + (MASK == I2C_MASKBIT_9)) +#endif + +#define IS_I2C(x) (IS_I2C0(x) || IS_I2C1(x) || IS_I2C2(x)) +#define IS_I2C0(x) (x == HT_I2C0) + +#if (LIBCFG_I2C1) +#define IS_I2C1(x) (x == HT_I2C1) +#else +#define IS_I2C1(x) (0) +#endif + +#if (LIBCFG_I2C2) +#define IS_I2C2(x) (x == HT_I2C2) +#else +#define IS_I2C2(x) (0) +#endif + +#if (LIBCFG_I2C_NO_10BIT_MODE) +#define IS_I2C_ADDRESS(ADDRESS) (ADDRESS <= 0x7F) +#else +#define IS_I2C_ADDRESS(ADDRESS) (ADDRESS <= 0x3FF) +#endif + +#define IS_I2C_SPEED(SPEED) ((SPEED >= 1) && (SPEED <= 1000000)) + +#define IS_I2C_SCL_HIGH(HIGH) (HIGH <= 0xFFFF) + +#define IS_I2C_SCL_LOW(LOW) (LOW <= 0xFFFF) + +#if (LIBCFG_I2C_TOUT_COUNT_8BIT) +#define IS_I2C_TIMEOUT(TIMEOUT) (TIMEOUT <= 0xFF) +#else +#define IS_I2C_TIMEOUT(TIMEOUT) (TIMEOUT <= 0xFFFF) +#endif + +#define SEQ_FILTER_DISABLE ((u32)0x00000000) +#define SEQ_FILTER_1_PCLK ((u32)0x00004000) +#define SEQ_FILTER_2_PCLK ((u32)0x00008000) + +#define IS_I2C_SEQ_FILTER_MASK(CONFIG) ((CONFIG == SEQ_FILTER_DISABLE) || \ + (CONFIG == SEQ_FILTER_1_PCLK) || \ + (CONFIG == SEQ_FILTER_2_PCLK)) +/** + * @} + */ + +/* Exported functions --------------------------------------------------------------------------------------*/ +/** @defgroup I2C_Exported_Functions I2C exported functions + * @{ + */ +void I2C_DeInit(HT_I2C_TypeDef* I2Cx); +void I2C_Init(HT_I2C_TypeDef* I2Cx, I2C_InitTypeDef* I2C_InitStructure); +void I2C_StructInit(I2C_InitTypeDef* I2C_InitStructure); +void I2C_Cmd(HT_I2C_TypeDef* I2Cx, ControlStatus NewState); +void I2C_GenerateSTOP(HT_I2C_TypeDef* I2Cx); +void I2C_IntConfig(HT_I2C_TypeDef* I2Cx, u32 I2C_Int, ControlStatus NewState); +void I2C_GeneralCallCmd(HT_I2C_TypeDef* I2Cx, ControlStatus NewState); +void I2C_AckCmd(HT_I2C_TypeDef* I2Cx, ControlStatus NewState); +void I2C_SetOwnAddress(HT_I2C_TypeDef* I2Cx, I2C_AddressTypeDef I2C_Address); +#if (LIBCFG_I2C_TWO_DEV_ADDR) +void I2C_SetOwnAddress1(HT_I2C_TypeDef* I2Cx, I2C_AddressTypeDef I2C_Address); +void I2C_OwnAddressCmd(HT_I2C_TypeDef* I2Cx, I2C_ADDR_Enum Address, ControlStatus NewState); +#endif +void I2C_TargetAddressConfig(HT_I2C_TypeDef* I2Cx, I2C_AddressTypeDef I2C_Address, u32 I2C_Direction); +void I2C_SendData(HT_I2C_TypeDef* I2Cx, u8 I2C_Data); +u8 I2C_ReceiveData(HT_I2C_TypeDef* I2Cx); +u32 I2C_ReadRegister(HT_I2C_TypeDef* I2Cx, u8 I2C_Register); +FlagStatus I2C_GetFlagStatus(HT_I2C_TypeDef* I2Cx, u32 I2C_Flag); +ErrStatus I2C_CheckStatus(HT_I2C_TypeDef* I2Cx, u32 I2C_Status); +void I2C_ClearFlag(HT_I2C_TypeDef* I2Cx, u32 I2C_Flag); +void I2C_SetSCLHighPeriod(HT_I2C_TypeDef* I2Cx, u32 I2C_HighPeriod); +void I2C_SetSCLLowPeriod(HT_I2C_TypeDef* I2Cx, u32 I2C_LowPeriod); +#if (LIBCFG_PDMA) +void I2C_PDMACmd(HT_I2C_TypeDef* I2Cx, u32 I2C_PDMAREQ, ControlStatus NewState); +void I2C_PDMANACKCmd(HT_I2C_TypeDef* I2Cx, ControlStatus NewState); +#endif +void I2C_TimeOutCmd(HT_I2C_TypeDef* I2Cx, ControlStatus NewState); +void I2C_SetTimeOutValue(HT_I2C_TypeDef* I2Cx, u32 I2C_Timeout); +void I2C_SetTimeOutPrescaler(HT_I2C_TypeDef* I2Cx, u32 I2C_Prescaler); +#if (LIBCFG_I2C_NO_ADDR_MASK == 0) +void I2C_AddressMaskConfig(HT_I2C_TypeDef* I2Cx, u32 I2C_Mask); +#endif +u16 I2C_GetAddressBuffer(HT_I2C_TypeDef* I2Cx); +void I2C_CombFilterCmd(HT_I2C_TypeDef* I2Cx, ControlStatus NewState); +void I2C_SequentialFilterConfig(HT_I2C_TypeDef* I2Cx, u32 Seq_Filter_Select); +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f5xxxx_i2s.h b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f5xxxx_i2s.h new file mode 100644 index 0000000000..2d4646c4d1 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f5xxxx_i2s.h @@ -0,0 +1,240 @@ +/*********************************************************************************************************//** + * @file ht32f5xxxx_i2s.h + * @version $Rev:: 2960 $ + * @date $Date:: 2018-08-02 #$ + * @brief The header file of the I2S library. + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------------------------------------*/ +#ifndef __HT32F5XXXX_I2S_H +#define __HT32F5XXXX_I2S_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------------------------------------*/ +#include "ht32.h" + +/** @addtogroup HT32F5xxxx_Peripheral_Driver HT32F5xxxx Peripheral Driver + * @{ + */ + +/** @addtogroup I2S + * @{ + */ + + +/* Exported types ------------------------------------------------------------------------------------------*/ +/** @defgroup I2S_Exported_Types I2S exported types + * @{ + */ +typedef struct +{ + u32 I2S_Mode; + u32 I2S_Format; + u32 I2S_WordWidth; + u32 I2S_MclkOut; + u32 I2S_MclkInv; + u32 I2S_BclkInv; + u32 I2S_X_Div; + u32 I2S_Y_Div; + u32 I2S_N_Div; +} I2S_InitTypeDef; +/** + * @} + */ + +/* Exported constants --------------------------------------------------------------------------------------*/ +/** @defgroup I2S_Exported_Constants I2S exported constants + * @{ + */ +/* mode */ +#define I2S_MASTER_TX (1UL << 1) +#define I2S_MASTER_RX (1UL << 2) +#define I2S_MASTER_TX_RX ((1UL << 1) | (1UL << 2)) + +#define I2S_SLAVE_TX ((1UL << 3) | (1UL << 1)) +#define I2S_SLAVE_RX ((1UL << 3) | (1UL << 2)) +#define I2S_SLAVE_TX_RX ((1UL << 3) | (1UL << 1) | (1UL << 2)) + +#define IS_I2S_MODE(MOD) ((MOD == I2S_MASTER_TX) || \ + (MOD == I2S_MASTER_RX) || \ + (MOD == I2S_MASTER_TX_RX) || \ + (MOD == I2S_SLAVE_TX) || \ + (MOD == I2S_SLAVE_RX) || \ + (MOD == I2S_SLAVE_TX_RX)) + + +/* format */ +#define I2S_JUSTIFIED_STEREO (0) +#define LEFT_JUSTIFIED_STEREO (1UL << 6) +#define RIGHT_JUSTIFIED_STEREO (2UL << 6) +#define I2S_JUSTIFIED_REPEAT (1UL << 10) + +#define I2S_JUSTIFIED_STEREO_EXT (1UL << 8) +#define LEFT_JUSTIFIED_STEREO_EXT ((1UL << 8) | (1UL << 6)) +#define RIGHT_JUSTIFIED_STEREO_EXT ((1UL << 8) | (2UL << 6)) +#define I2S_JUSTIFIED_REPEAT_EXT ((1UL << 8) | (1UL << 10)) + +#define I2S_JUSTIFIED_MONO (1UL << 11) +#define LEFT_JUSTIFIED_MONO ((1UL << 11) | (1UL << 6)) +#define RIGHT_JUSTIFIED_MONO ((1UL << 11) | (2UL << 6)) + +#define I2S_JUSTIFIED_MONO_EXT ((1UL << 8) | (1UL << 11)) +#define LEFT_JUSTIFIED_MONO_EXT ((1UL << 8) | (1UL << 11) | (1UL << 6)) +#define RIGHT_JUSTIFIED_MONO_EXT ((1UL << 8) | (1UL << 11) | (2UL << 6)) + +#define IS_I2S_FORMAT(FMT) ((FMT == I2S_JUSTIFIED_STEREO) || \ + (FMT == LEFT_JUSTIFIED_STEREO) || \ + (FMT == RIGHT_JUSTIFIED_STEREO) || \ + (FMT == I2S_JUSTIFIED_REPEAT) || \ + (FMT == I2S_JUSTIFIED_STEREO_EXT) || \ + (FMT == LEFT_JUSTIFIED_STEREO_EXT) || \ + (FMT == RIGHT_JUSTIFIED_STEREO_EXT) || \ + (FMT == I2S_JUSTIFIED_REPEAT_EXT) || \ + (FMT == I2S_JUSTIFIED_MONO) || \ + (FMT == LEFT_JUSTIFIED_MONO) || \ + (FMT == RIGHT_JUSTIFIED_MONO) || \ + (FMT == I2S_JUSTIFIED_MONO_EXT) || \ + (FMT == LEFT_JUSTIFIED_MONO_EXT) || \ + (FMT == RIGHT_JUSTIFIED_MONO_EXT)) + + +/* word width */ +#define I2S_WORDWIDTH_8 (0) +#define I2S_WORDWIDTH_16 (1UL << 4) +#define I2S_WORDWIDTH_24 (2UL << 4) +#define I2S_WORDWIDTH_32 (3UL << 4) + +#define IS_I2S_WORD_WIDTH(WIDTH) ((WIDTH == I2S_WORDWIDTH_8) || \ + (WIDTH == I2S_WORDWIDTH_16) || \ + (WIDTH == I2S_WORDWIDTH_24) || \ + (WIDTH == I2S_WORDWIDTH_32)) + + +/* clock divider */ +#define IS_I2S_MCLK_DIV(X, Y) ((X > 0) && (X < 256) && (Y > 0) && (Y < 256) && (X <= Y)) + +#define IS_I2S_BCLK_DIV(N) (N < 256) + + +/* FIFO */ +#define I2S_TX_FIFO (1UL << 8) +#define I2S_RX_FIFO (2UL << 8) + +#define IS_I2S_ONE_FIFO(FIFO) ((FIFO == I2S_TX_FIFO) || (FIFO == I2S_RX_FIFO)) + +#define IS_I2S_TWO_FIFO(FIFO) (((FIFO & 0xFFFFFCFF) == 0) && (FIFO != 0)) + +#define IS_I2S_FIFO_LEVEL(LEVEL) ((LEVEL & 0x0000000F) < 9) + + +/* interrupt */ +#define I2S_INT_TXFIFO_TRI (1UL) +#define I2S_INT_TXFIFO_UDF (1UL << 1) +#define I2S_INT_TXFIFO_OVF (1UL << 2) + +#define I2S_INT_RXFIFO_TRI (1UL << 4) +#define I2S_INT_RXFIFO_UDF (1UL << 5) +#define I2S_INT_RXFIFO_OVF (1UL << 6) + +#define IS_I2S_INT(INT) (((INT & 0xFFFFFF88) == 0) && (INT != 0)) + + +/* flag */ +#define I2S_FLAG_TXFIFO_TRI (1UL) +#define I2S_FLAG_TXFIFO_UDF (1UL << 1) +#define I2S_FLAG_TXFIFO_OVF (1UL << 2) +#define I2S_FLAG_RXFIFO_TRI (1UL << 8) +#define I2S_FLAG_RXFIFO_UDF (1UL << 9) +#define I2S_FLAG_RXFIFO_OVF (1UL << 10) + +#define I2S_FLAG_TXFIFO_EMP (1UL << 3) +#define I2S_FLAG_TXFIFO_FUL (1UL << 4) +#define I2S_FLAG_RXFIFO_EMP (1UL << 11) +#define I2S_FLAG_RXFIFO_FUL (1UL << 12) +#define I2S_FLAG_RIGHT_CH (1UL << 16) +#define I2S_FLAG_TX_BUSY (1UL << 17) +#define I2S_FLAG_CLK_RDY (1UL << 18) + +#define IS_I2S_FLAG_CLEAR(FLAG) (((FLAG & 0xFFFFF8F8) == 0) && (FLAG != 0)) + +#define IS_I2S_FLAG(FLAG) ((FLAG == I2S_FLAG_TXFIFO_TRI) || \ + (FLAG == I2S_FLAG_TXFIFO_UDF) || \ + (FLAG == I2S_FLAG_TXFIFO_OVF) || \ + (FLAG == I2S_FLAG_TXFIFO_EMP) || \ + (FLAG == I2S_FLAG_TXFIFO_FUL) || \ + (FLAG == I2S_FLAG_RXFIFO_TRI) || \ + (FLAG == I2S_FLAG_RXFIFO_UDF) || \ + (FLAG == I2S_FLAG_RXFIFO_OVF) || \ + (FLAG == I2S_FLAG_RXFIFO_EMP) || \ + (FLAG == I2S_FLAG_RXFIFO_FUL) || \ + (FLAG == I2S_FLAG_RIGHT_CH) || \ + (FLAG == I2S_FLAG_TX_BUSY) || \ + (FLAG == I2S_FLAG_CLK_RDY)) + + +/* PDMA request */ +#define I2S_PDMAREQ_TX (1UL << 13) +#define I2S_PDMAREQ_RX (1UL << 14) + +#define IS_I2S_PDMA_REQ(REQ) (((REQ & 0xFFFF9FFF) == 0) && (REQ != 0)) +/** + * @} + */ + +/* Exported functions --------------------------------------------------------------------------------------*/ +/** @defgroup I2S_Exported_Functions I2S exported functions + * @{ + */ +void I2S_DeInit(void); +void I2S_Init(I2S_InitTypeDef* I2S_InitStruct); +void I2S_Cmd(ControlStatus NewState); +void I2S_MclkOutputCmd(ControlStatus NewState); +void I2S_TxMuteCmd(ControlStatus NewState); +void I2S_PDMACmd(u32 I2S_PDMAREQ, ControlStatus NewState); +void I2S_FIFOReset(u32 I2S_FIFO); +void I2S_FIFOTrigLevelConfig(u32 I2S_FIFO, u32 I2S_FIFOLevel); +u8 I2S_GetFIFOStatus(u32 I2S_FIFO); +void I2S_IntConfig(u32 I2S_Int, ControlStatus NewState); +FlagStatus I2S_GetFlagStatus(u32 I2S_Flag); +void I2S_ClearFlag(u32 I2S_Flag); +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f5xxxx_lcd.h b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f5xxxx_lcd.h new file mode 100644 index 0000000000..61070c721e --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f5xxxx_lcd.h @@ -0,0 +1,382 @@ +/*********************************************************************************************************//** + * @file ht32f5xxxx_lcd.h + * @version V1.00 + * @date 11/15/2017 + * @brief The header file of the LCD library. + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------------------------------------*/ +#ifndef __HT32F5XXXX_LCD_H +#define __HT32F5XXXX_LCD_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------------------------------------*/ +#include "ht32.h" + +/** @addtogroup HT32F5xxxx_Peripheral_Driver HT32F5xxxx Peripheral Driver + * @{ + */ + +/** @addtogroup LCD + * @{ + */ + + +/* Exported types ------------------------------------------------------------------------------------------*/ +/** @defgroup LCD_Exported_Types LCD exported types + * @{ + */ +/** + * @brief Enumeration of LCD mask time. + */ +typedef enum { + LCD_MaskTime_25ns = (0x00 << 24), /*!< MCONT mask time = 25 ns */ + LCD_MaskTime_40ns = (0x01 << 24), /*!< MCONT mask time = 40 ns */ +} LCD_MaskTime_Enum; + +/** + * @brief Enumeration of LCD STATIC switch. + */ +typedef enum { + LCD_StaticSwitch_Close = (0x00 << 14), /*!< STATIC switch is closed during dead time */ + LCD_StaticSwitch_Open = (0x01 << 14), /*!< STATIC switch is open during dead time */ +} LCD_StaticSwitch_Enum; + +/** + * @brief Enumeration of LCD MUXCOM7. + */ +typedef enum +{ + /*!< 57341: SEG28/COM7 */ + /*!< 57352: SEG36/COM7 */ + LCD_MUXCOM7_IS_COM7 = (0x00 << 11), + LCD_MUXCOM7_IS_SEGx = (0x01 << 11), +} LCD_MUXCOM7_Enum; + +/** + * @brief Enumeration of LCD MUXCOM6. + */ +typedef enum +{ + /*!< 57341: SEG27/COM6 */ + /*!< 57352: SEG35/COM6 */ + LCD_MUXCOM6_IS_COM6 = (0x00 << 10), + LCD_MUXCOM6_IS_SEGx = (0x01 << 10), +} LCD_MUXCOM6_Enum; + +/** + * @brief Enumeration of LCD MUXCOM5. + */ +typedef enum +{ + /*!< 57341: SEG26/COM5 */ + /*!< 57352: SEG34/COM5 */ + LCD_MUXCOM5_IS_COM5 = (0x00 << 9), + LCD_MUXCOM5_IS_SEGx = (0x01 << 9), +} LCD_MUXCOM5_Enum; + +/** + * @brief Enumeration of LCD MUXCOM4. + */ +typedef enum +{ + /*!< 57341: SEG25/COM4 */ + /*!< 57352: SEG33/COM4 */ + LCD_MUXCOM4_IS_COM4 = (0x00 << 8), + LCD_MUXCOM4_IS_SEGx = (0x01 << 8), +} LCD_MUXCOM4_Enum; + +/** + * @brief Enumeration of LCD waveform. + */ +typedef enum +{ + LCD_Type_A_Waveform = (0x00 << 7), /*!< Type A waveform */ + LCD_Type_B_Waveform = (0x01 << 7), /*!< Type B waveform */ +} LCD_Waveform_Enum; + +/** + * @brief Enumeration of LCD bias. + */ +typedef enum { + LCD_Bias_1_4 = (0x00 << 5), /*!< 1/4 bias */ + LCD_Bias_1_2 = (0x01 << 5), /*!< 1/2 bias */ + LCD_Bias_1_3 = (0x02 << 5), /*!< 1/3 bias */ + LCD_Bias_Static = (0x03 << 5), /*!< Static bias */ +} LCD_Bias_Enum; + +/** + * @brief Enumeration of LCD duty. + */ +typedef enum { + LCD_Duty_Static = (0x00 << 2), /*!< Static duty */ + LCD_Duty_1_2 = (0x01 << 2), /*!< 1/2 duty */ + LCD_Duty_1_3 = (0x02 << 2), /*!< 1/3 duty */ + LCD_Duty_1_4 = (0x03 << 2), /*!< 1/4 duty */ + LCD_Duty_1_6 = (0x04 << 2), /*!< 1/6 duty */ + LCD_Duty_1_8 = (0x05 << 2), /*!< 1/8 duty */ +} LCD_Duty_Enum; + +/** + * @brief Enumeration of LCD voltage source. + */ +typedef enum { + LCD_VoltageSource_External = (0x00 << 1), /*!< External voltage source */ + LCD_VoltageSource_Internal = (0x01 << 1), /*!< Internal voltage source */ +} LCD_VoltageSource_Enum; + +/** + * @brief Enumeration of LCD clock prescaler. + */ +typedef enum { + LCD_Prescaler_1 = (0x00 << 22), /*!< CK_PS = CK_LCD / 1 */ + LCD_Prescaler_2 = (0x01 << 22), /*!< CK_PS = CK_LCD / 2 */ + LCD_Prescaler_4 = (0x02 << 22), /*!< CK_PS = CK_LCD / 4 */ + LCD_Prescaler_8 = (0x03 << 22), /*!< CK_PS = CK_LCD / 8 */ + LCD_Prescaler_16 = (0x04 << 22), /*!< CK_PS = CK_LCD / 16 */ + LCD_Prescaler_32 = (0x05 << 22), /*!< CK_PS = CK_LCD / 32 */ + LCD_Prescaler_64 = (0x06 << 22), /*!< CK_PS = CK_LCD / 64 */ + LCD_Prescaler_128 = (0x07 << 22), /*!< CK_PS = CK_LCD / 128 */ + LCD_Prescaler_256 = (0x08 << 22), /*!< CK_PS = CK_LCD / 256 */ + LCD_Prescaler_512 = (0x09 << 22), /*!< CK_PS = CK_LCD / 512 */ + LCD_Prescaler_1024 = (0x0A << 22), /*!< CK_PS = CK_LCD / 1024 */ + LCD_Prescaler_2048 = (0x0B << 22), /*!< CK_PS = CK_LCD / 2048 */ + LCD_Prescaler_4096 = (0x0C << 22), /*!< CK_PS = CK_LCD / 4096 */ + LCD_Prescaler_8192 = (0x0D << 22), /*!< CK_PS = CK_LCD / 8192 */ + LCD_Prescaler_16384 = (0x0E << 22), /*!< CK_PS = CK_LCD / 16384 */ + LCD_Prescaler_32768 = (0x0F << 22) /*!< CK_PS = CK_LCD / 32768 */ +} LCD_Prescaler_Enum; + +/** + * @brief Enumeration of LCD clock divider. + */ +typedef enum { + LCD_Divider_16 = (0x00 << 18), /*!< CK_DIV = CK_PS / 16 */ + LCD_Divider_17 = (0x01 << 18), /*!< CK_DIV = CK_PS / 17 */ + LCD_Divider_18 = (0x02 << 18), /*!< CK_DIV = CK_PS / 18 */ + LCD_Divider_19 = (0x03 << 18), /*!< CK_DIV = CK_PS / 19 */ + LCD_Divider_20 = (0x04 << 18), /*!< CK_DIV = CK_PS / 20 */ + LCD_Divider_21 = (0x05 << 18), /*!< CK_DIV = CK_PS / 21 */ + LCD_Divider_22 = (0x06 << 18), /*!< CK_DIV = CK_PS / 22 */ + LCD_Divider_23 = (0x07 << 18), /*!< CK_DIV = CK_PS / 23 */ + LCD_Divider_24 = (0x08 << 18), /*!< CK_DIV = CK_PS / 24 */ + LCD_Divider_25 = (0x09 << 18), /*!< CK_DIV = CK_PS / 25 */ + LCD_Divider_26 = (0x0A << 18), /*!< CK_DIV = CK_PS / 26 */ + LCD_Divider_27 = (0x0B << 18), /*!< CK_DIV = CK_PS / 27 */ + LCD_Divider_28 = (0x0C << 18), /*!< CK_DIV = CK_PS / 28 */ + LCD_Divider_29 = (0x0D << 18), /*!< CK_DIV = CK_PS / 29 */ + LCD_Divider_30 = (0x0E << 18), /*!< CK_DIV = CK_PS / 30 */ + LCD_Divider_31 = (0x0F << 18), /*!< CK_DIV = CK_PS / 31 */ +} LCD_Divider_Enum; + +/** + * @brief Enumeration of LCD blink mode. + */ +typedef enum { + LCD_BlinkMode_Off = (0x00 << 16), /*!< Blink inactive */ + LCD_BlinkMode_SEG0_COM0 = (0x01 << 16), /*!< SEG0 on COM0 blink */ + LCD_BlinkMode_SEG0_AllCOM = (0x02 << 16), /*!< SEG0 on All COM blink */ + LCD_BlinkMode_AllSEG_AllCOM = (0x03 << 16), /*!< All SEG on All COM blink */ +} LCD_BlinkMode_Enum; + +/** + * @brief Enumeration of LCD blink frequency. + */ +typedef enum +{ + LCD_BlinkFrequency_Div8 = (0x00 << 13), /*!< Blink frequency = frame rate / 8 */ + LCD_BlinkFrequency_Div16 = (0x01 << 13), /*!< Blink frequency = frame rate / 16 */ + LCD_BlinkFrequency_Div32 = (0x02 << 13), /*!< Blink frequency = frame rate / 32 */ + LCD_BlinkFrequency_Div64 = (0x03 << 13), /*!< Blink frequency = frame rate / 64 */ + LCD_BlinkFrequency_Div128 = (0x04 << 13), /*!< Blink frequency = frame rate / 128 */ + LCD_BlinkFrequency_Div256 = (0x05 << 13), /*!< Blink frequency = frame rate / 256 */ + LCD_BlinkFrequency_Div512 = (0x06 << 13), /*!< Blink frequency = frame rate / 512 */ + LCD_BlinkFrequency_Div1024 = (0x07 << 13), /*!< Blink frequency = frame rate / 1024 */ +} LCD_BlinkFrequency_Enum; + +/** + * @brief Enumeration of LCD charge pump. + */ +typedef enum +{ + LCD_ChargePump_2V65 = (0x00 << 10), /*!< Charge pump voltage = 2.65 V */ + LCD_ChargePump_2V75 = (0x01 << 10), /*!< Charge pump voltage = 2.75 V */ + LCD_ChargePump_2V85 = (0x02 << 10), /*!< Charge pump voltage = 2.85 V */ + LCD_ChargePump_2V95 = (0x03 << 10), /*!< Charge pump voltage = 2.95 V */ + LCD_ChargePump_3V10 = (0x04 << 10), /*!< Charge pump voltage = 3.10 V */ + LCD_ChargePump_3V25 = (0x05 << 10), /*!< Charge pump voltage = 3.25 V */ + LCD_ChargePump_3V40 = (0x06 << 10), /*!< Charge pump voltage = 3.40 V */ + LCD_ChargePump_3V55 = (0x07 << 10), /*!< Charge pump voltage = 3.55 V */ +} LCD_ChargePump_Enum; + +/** + * @brief Enumeration of LCD dead time. + */ +typedef enum +{ + LCD_Deadtime_0 = (0x00 << 7), /*!< No dead time */ + LCD_Deadtime_1 = (0x01 << 7), /*!< Type A: 1/2 phase period; Type B: 1 phase period */ + LCD_Deadtime_2 = (0x02 << 7), /*!< Type A: 2/2 phase period; Type B: 2 phase period */ + LCD_Deadtime_3 = (0x03 << 7), /*!< Type A: 3/2 phase period; Type B: 3 phase period */ + LCD_Deadtime_4 = (0x04 << 7), /*!< Type A: 4/2 phase period; Type B: 4 phase period */ + LCD_Deadtime_5 = (0x05 << 7), /*!< Type A: 5/2 phase period; Type B: 5 phase period */ + LCD_Deadtime_6 = (0x06 << 7), /*!< Type A: 6/2 phase period; Type B: 6 phase period */ + LCD_Deadtime_7 = (0x07 << 7), /*!< Type A: 7/2 phase period; Type B: 7 phase period */ +} LCD_DeadTime_Enum; + +/** + * @brief Enumeration of LCD high drive. + */ +typedef enum +{ + LCD_HighDrive_0 = (0x00 << 4), /*!< No high drive */ + LCD_HighDrive_1 = (0x01 << 4), /*!< High drive duration = 1 CK_PS pulses */ + LCD_HighDrive_2 = (0x02 << 4), /*!< High drive duration = 2 CK_PS pulses */ + LCD_HighDrive_3 = (0x03 << 4), /*!< High drive duration = 3 CK_PS pulses */ + LCD_HighDrive_4 = (0x04 << 4), /*!< High drive duration = 4 CK_PS pulses */ + LCD_HighDrive_5 = (0x05 << 4), /*!< High drive duration = 5 CK_PS pulses */ + LCD_HighDrive_6 = (0x06 << 4), /*!< High drive duration = 6 CK_PS pulses */ + LCD_HighDrive_7 = (0x07 << 4), /*!< High drive duration = 7 CK_PS pulses */ + LCD_HighDrive_Static = (0xff), /*!< Static high drive */ +} LCD_HighDrive_Enum; + +/** + * @brief Definition of LCD Init Structure. + */ +typedef struct +{ + LCD_Prescaler_Enum LCD_Prescaler; + LCD_Divider_Enum LCD_Divider; + LCD_Duty_Enum LCD_Duty; + LCD_Bias_Enum LCD_Bias; + LCD_Waveform_Enum LCD_Waveform; + LCD_VoltageSource_Enum LCD_VoltageSource; +} LCD_InitTypeDef; +/** + * @} + */ + +/* Exported constants --------------------------------------------------------------------------------------*/ +/** @defgroup LCD_Exported_Constants LCD exported constants + * @{ + */ +#define LCD_INT_UDD ((u32)0x00000002) +#define LCD_INT_SOF ((u32)0x00000001) + +#define IS_LCD_INT(INT) ((((INT) & 0xFFFFFFFC) == 0) && ((INT) != 0)) + + +#define LCD_FLAG_FCRSF ((u32)0x00000020) +#define LCD_FLAG_RDY ((u32)0x00000010) +#define LCD_FLAG_UDD ((u32)0x00000008) +#define LCD_FLAG_UDR ((u32)0x00000004) +#define LCD_FLAG_SOF ((u32)0x00000002) +#define LCD_FLAG_ENS ((u32)0x00000001) + +#define IS_LCD_FLAG(FLAG) (((FLAG) == LCD_FLAG_FCRSF) || \ + ((FLAG) == LCD_FLAG_RDY) || \ + ((FLAG) == LCD_FLAG_UDD) || \ + ((FLAG) == LCD_FLAG_UDR) || \ + ((FLAG) == LCD_FLAG_SOF) || \ + ((FLAG) == LCD_FLAG_ENS)) + + +#define LCD_CLR_UDD ((u32)0x00000002) +#define LCD_CLR_SOF ((u32)0x00000001) + +#define IS_LCD_CLEAR(CLR) ((((CLR) & 0xFFFFFFFC) == 0) && ((CLR) != 0)) +/** + * @} + */ + +/* Exported functions --------------------------------------------------------------------------------------*/ +/** @defgroup LCD_Exported_Functions LCD exported functions + * @{ + */ + +/* !!! NOTICE !!! + Before using the following functions, be sure to confirm LCDENS = 0 by "LCD_GetFlagStatus(LCD_FLAG_ENS);", + otherwise the LCD may display abnormally. + LCD_DriverInit() + LCD_MaskTimeConfig() + LCD_StaticSwitchConfig() + LCD_MuxCOM7Config() + LCD_MuxCOM6Config() + LCD_MuxCOM5Config() + LCD_MuxCOM4Config() + LCD_WaveformConfig() + LCD_BiasConfig() + LCD_DutyConfig() + LCD_VoltageSourceConfig() + LCD_ChargePumpConfig() +*/ + +void LCD_DriverDeInit(void); +void LCD_DriverInit(LCD_InitTypeDef* LCD_InitStruct); + +void LCD_MaskTimeConfig(LCD_MaskTime_Enum Sel); +void LCD_HalfRLCmd(ControlStatus NewState); +void LCD_StaticSwitchConfig(LCD_StaticSwitch_Enum Sel); +void LCD_MuxCOM7Config(LCD_MUXCOM7_Enum Sel); +void LCD_MuxCOM6Config(LCD_MUXCOM6_Enum Sel); +void LCD_MuxCOM5Config(LCD_MUXCOM5_Enum Sel); +void LCD_MuxCOM4Config(LCD_MUXCOM4_Enum Sel); +void LCD_WaveformConfig(LCD_Waveform_Enum Sel); +void LCD_BiasConfig(LCD_Bias_Enum Sel); +void LCD_DutyConfig(LCD_Duty_Enum Sel); +void LCD_VoltageSourceConfig(LCD_VoltageSource_Enum Sel); +void LCD_Cmd(ControlStatus NewState); + +void LCD_PrescalerConfig(LCD_Prescaler_Enum Sel); +void LCD_DividerConfig(LCD_Divider_Enum Sel); +void LCD_BlinkModeConfig(LCD_BlinkMode_Enum Sel); +void LCD_BlinkFreqConfig(LCD_BlinkFrequency_Enum Sel); +void LCD_ChargePumpConfig(LCD_ChargePump_Enum Sel); +void LCD_DeadTimeConfig(LCD_DeadTime_Enum Sel); +void LCD_HighDriveConfig(LCD_HighDrive_Enum Sel); + +void LCD_IntConfig(u32 LCD_Int, ControlStatus NewState); +FlagStatus LCD_GetFlagStatus(u32 LCD_Flag); +void LCD_SetUpdateDisplayRequest(void); +void LCD_ClearFlag(u32 LCD_Flag); +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f5xxxx_ledc.h b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f5xxxx_ledc.h new file mode 100644 index 0000000000..c12c2a0b04 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f5xxxx_ledc.h @@ -0,0 +1,209 @@ +/*********************************************************************************************************//** + * @file ht32f5xxxx_ledc.h + * @version $Rev:: 6386 $ + * @date $Date:: 2022-10-27 #$ + * @brief The header file of the LED Controller library. + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------------------------------------*/ +#ifndef __HT32F5XXXX_LEDC_H +#define __HT32F5XXXX_LEDC_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------------------------------------*/ +#include "ht32.h" + +/** @addtogroup HT32F5xxxx_Peripheral_Driver HT32F5xxxx Peripheral Driver + * @{ + */ + +/** @addtogroup LEDC + * @{ + */ + + +/* Exported types ------------------------------------------------------------------------------------------*/ +/** @defgroup LEDC_Exported_Types LEDC exported types + * @{ + */ + +/** + * @brief Selection of LEDC clock source + */ +typedef enum +{ + LEDC_SRC_PCLK = 0, + LEDC_SRC_LSI, /*!< Low speed internal clock, about 32KHz */ + LEDC_SRC_LSE /*!< Low speed external 32768 Hz clock */ +} LEDC_SRC_Enum; + +/** + * @brief Selection of LEDC duty clock numbers + */ +typedef enum +{ + LEDC_DTYNUM_8 = 0, + LEDC_DTYNUM_16, + LEDC_DTYNUM_32, + LEDC_DTYNUM_64 +} LEDC_DTYNUM_Enum; + +/** + * @brief Definition of LEDC Init Structure + */ +typedef struct +{ + LEDC_SRC_Enum LEDC_ClockSource; + LEDC_DTYNUM_Enum LEDC_DutyClockNumber; + u32 LEDC_ClockPrescaler; + u32 LEDC_COMxEN; + u32 LEDC_DeadTime; +} LEDC_InitTypeDef; + +/** + * @brief Enumeration of LED layout mode. + */ +typedef enum +{ + COMMON_CATHODE, /*!< LEDC SEG output polarity is non-inverted. */ + /*!< LEDC COM output polarity is non-inverted.*/ + COMMON_CATHODE_WITH_NPN, /*!< LEDC SEG output polarity is non-inverted. */ + /*!< LEDC COM output polarity is inverted.*/ + COMMON_ANODE_WITH_PNP, /*!< LEDC SEG output polarity is inverted. */ + /*!< LEDC COM output polarity is non-inverted.*/ + COMMON_ANODE_WITH_NPN, /*!< LEDC SEG output polarity is inverted. */ + /*!< LEDC COM output polarity is inverted.*/ +} LEDC_Mode; + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------------------------------------*/ +/** @defgroup LEDC_Exported_Constants LEDC exported constants + * @{ + */ + +/* Definitions of LEDCER */ +#define LEDC_COM0EN 0x0001 /*!< LEDC COM0 enable */ +#define LEDC_COM1EN 0x0002 /*!< LEDC COM1 enable */ +#define LEDC_COM2EN 0x0004 /*!< LEDC COM2 enable */ +#define LEDC_COM3EN 0x0008 /*!< LEDC COM3 enable */ +#define LEDC_COM4EN 0x0010 /*!< LEDC COM4 enable */ +#define LEDC_COM5EN 0x0020 /*!< LEDC COM5 enable */ +#define LEDC_COM6EN 0x0040 /*!< LEDC COM6 enable */ +#define LEDC_COM7EN 0x0080 /*!< LEDC COM7 enable */ +#if (LIBCFG_LEDC_NO_COM_8_11 == 0) +#define LEDC_COM8EN 0x0100 /*!< LEDC COM8 enable */ +#define LEDC_COM9EN 0x0200 /*!< LEDC COM9 enable */ +#define LEDC_COM10EN 0x0400 /*!< LEDC COM10 enable */ +#define LEDC_COM11EN 0x0800 /*!< LEDC COM11 enable */ +#endif + +/* Definitions of COMxPOL */ +#define LEDC_COM0POL 0x00000001 /*!< LEDC COM0 polarity */ +#define LEDC_COM1POL 0x00000002 /*!< LEDC COM1 polarity */ +#define LEDC_COM2POL 0x00000004 /*!< LEDC COM2 polarity */ +#define LEDC_COM3POL 0x00000008 /*!< LEDC COM3 polarity */ +#define LEDC_COM4POL 0x00000010 /*!< LEDC COM4 polarity */ +#define LEDC_COM5POL 0x00000020 /*!< LEDC COM5 polarity */ +#define LEDC_COM6POL 0x00000040 /*!< LEDC COM6 polarity */ +#define LEDC_COM7POL 0x00000080 /*!< LEDC COM7 polarity */ +#if (LIBCFG_LEDC_NO_COM_8_11 == 0) +#define LEDC_COM8POL 0x00000100 /*!< LEDC COM8 polarity */ +#define LEDC_COM9POL 0x00000200 /*!< LEDC COM9 polarity */ +#define LEDC_COM10POL 0x00000400 /*!< LEDC COM10 polarity */ +#define LEDC_COM11POL 0x00000800 /*!< LEDC COM11 polarity */ +#endif + +/* Definitions of SEGxPOL */ +#define LEDC_SEG0POL 0x00010000 /*!< LEDC SEG0 polarity */ +#define LEDC_SEG1POL 0x00020000 /*!< LEDC SEG1 polarity */ +#define LEDC_SEG2POL 0x00040000 /*!< LEDC SEG2 polarity */ +#define LEDC_SEG3POL 0x00080000 /*!< LEDC SEG3 polarity */ +#define LEDC_SEG4POL 0x00100000 /*!< LEDC SEG4 polarity */ +#define LEDC_SEG5POL 0x00200000 /*!< LEDC SEG5 polarity */ +#define LEDC_SEG6POL 0x00400000 /*!< LEDC SEG6 polarity */ +#define LEDC_SEG7POL 0x00800000 /*!< LEDC SEG7 polarity */ + +#define LEDC_FLAG_FRAME (1UL << 0) +#define LEDC_INT_FRAME (1UL << 0) + + +/* check parameter of the LEDC mode */ +#define IS_LEDC_MODE(x) ((x == COMMON_CATHODE) || (x == COMMON_CATHODE_WITH_NPN) || \ + (x == COMMON_ANODE_WITH_PNP) || (x == COMMON_ANODE_WITH_NPN)) + +/** + * @brief Used to check LEDC_SRC_Enum parameter + */ +#define IS_LEDC_SRC(x) ((x == LEDC_SRC_PCLK) || (x == LEDC_SRC_LSI) || (x == LEDC_SRC_LSE)) +#define IS_LEDC_DTYNUM(x) ((x == LEDC_DTYNUM_8) || (x == LEDC_DTYNUM_16) || (x == LEDC_DTYNUM_32) ||\ + (x == LEDC_DTYNUM_64)) +#define IS_LEDC_PSC(x) (x < 4096) +#define IS_LEDC_DTCR(x) (x < 64) +#define IS_LEDC_COMEN(x) (((x & 0xF000) == 0x0) && (x != 0x0)) +#define IS_LEDC_COMPOL(x) (((x & 0xFFFFF000) == 0x0) && (x != 0x0)) +#define IS_LEDC_SEGPOL(x) (((x & 0xFF00FFFF) == 0x0) && (x != 0x0)) + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------------------------------------*/ +/** @defgroup LEDC_Exported_Functions LEDC exported functions + * @{ + */ +void LEDC_DeInit(void); +void LEDC_Init(LEDC_InitTypeDef* LEDC_InitStruct); +void LEDC_ClockSourceConfig(LEDC_SRC_Enum Source); +void LEDC_Cmd(ControlStatus NewState); +void LEDC_IntConfig(ControlStatus NewState); +FlagStatus LEDC_GetFlagStatus(void); +void LEDC_ClearFlagStatus(void); +void LEDC_COMxConfig(u32 LEDC_COMxEN, ControlStatus Cmd); +void LEDC_SetDeadTimeDuty(u32 LEDC_DeadTimeDuty); +void LEDC_SetPolarityMode(u32 LEDC_COMxPOL, u32 LEDC_SEGxPOL , LEDC_Mode mode); +#define LEDC_SetData(COMx, data) HT_LEDC->DR[COMx] = data +#define LEDC_GetData(COMx) HT_LEDC->DR[COMx] +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f5xxxx_lib.h b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f5xxxx_lib.h new file mode 100644 index 0000000000..b04cdb33a4 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f5xxxx_lib.h @@ -0,0 +1,332 @@ +/*********************************************************************************************************//** + * @file ht32f5xxxx_lib.h + * @version $Rev:: 7319 $ + * @date $Date:: 2023-10-28 #$ + * @brief The header file includes all the header files of the libraries. + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------------------------------------*/ +#ifndef __HT32F5XXXX_LIB_H +#define __HT32F5XXXX_LIB_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Settings ------------------------------------------------------------------------------------------------*/ +#define HT32_FWLIB_VER (0x01009001) +#define HT32_FWLIB_SVN (0x7446) + +#if defined(USE_HT32F52220_30) + #include "ht32f52220_30_libcfg.h" +#endif +#if defined(USE_HT32F52231_41) + #include "ht32f52231_41_libcfg.h" +#endif +#if defined(USE_HT32F52331_41) + #include "ht32f52331_41_libcfg.h" +#endif +#if defined(USE_HT32F52342_52) + #include "ht32f52342_52_libcfg.h" +#endif +#if defined(USE_HT32F52243_53) + #include "ht32f52243_53_libcfg.h" +#endif +#if defined(USE_HT32F5826) + #include "ht32f5826_libcfg.h" +#endif +#if defined(USE_HT32F0008) + #include "ht32f0008_libcfg.h" +#endif +#if defined(USE_HT32F50220_30) + #include "ht32f50220_30_libcfg.h" +#endif +#if defined(USE_HT32F50231_41) + #include "ht32f50231_41_libcfg.h" +#endif +#if defined(USE_HT32F52344_54) + #include "ht32f52344_54_libcfg.h" +#endif +#if defined(USE_HT32F0006) + #include "ht32f0006_libcfg.h" +#endif +#if defined(USE_HT32F52357_67) + #include "ht32f52357_67_libcfg.h" +#endif +#if defined(USE_HT32F54231_41) + #include "ht32f54231_41_libcfg.h" +#endif +#if defined(USE_HT32F54243_53) + #include "ht32f54243_53_libcfg.h" +#endif +#if defined(USE_HT32F57342_52) + #include "ht32f57342_52_libcfg.h" +#endif +#if defined(USE_HT32F57331_41) + #include "ht32f57331_41_libcfg.h" +#endif +#if defined(USE_HT32F50343) + #include "ht32f50343_libcfg.h" +#endif +#if defined(USE_HT32F65230_40) + #include "ht32f65230_40_libcfg.h" +#endif +#if defined(USE_HT32F65232) + #include "ht32f65232_libcfg.h" +#endif +#if defined(USE_HT32F61141) + #include "ht32f61141_libcfg.h" +#endif +#if defined(USE_HT32F61244_45) + #include "ht32f61244_45_libcfg.h" +#endif +#if defined(USE_HT32F50020_30) + #include "ht32f50020_30_libcfg.h" +#endif +#if defined(USE_HT32F67041_51) + #include "ht32f67041_51_libcfg.h" +#endif +#if defined(USE_HT32F50442_52) + #include "ht32f50442_52_libcfg.h" +#endif +#if defined(USE_HT32F50431_41) + #include "ht32f50431_41_libcfg.h" +#endif +#if defined(USE_HT32F53242_52) + #include "ht32f53242_52_libcfg.h" +#endif +#if defined(USE_HT32F53231_41) + #include "ht32f53231_41_libcfg.h" +#endif +#if defined(USE_HT32F66242) + #include "ht32f66242_libcfg.h" +#endif +#if defined(USE_HT32F66246) + #include "ht32f66246_libcfg.h" +#endif +#if defined(USE_HT32F52234_44) + #include "ht32f52234_44_libcfg.h" +#endif + +/* Includes ------------------------------------------------------------------------------------------------*/ +#include +#include "ht32f5xxxx_conf.h" + +#if (HT32_LIB_DEBUG == 1) +/** + * @brief The assert_param macro is used for function's parameters check. + * @param expr: If expr is false, it calls assert_failed function + * which reports the name of the source file and the source + * line number of the call that failed. + * If expr is true, it returns no value. + * @retval None + */ +#define Assert_Param(expr) ((expr) ? (void)0 : assert_error((u8 *)__FILE__, __LINE__)) +/* Exported functions ------------------------------------------------------- ------------------------------*/ +void assert_error(u8* file, u32 line); +#else + +#define Assert_Param(expr) ((void)0) + +#endif /* DEBUG --------------------------------------------------------------------------------------------*/ + + +#if _ADC + #if defined(USE_HT32F65230_40) || defined(USE_HT32F65232) || defined(USE_HT32F66242) || defined(USE_HT32F66246) + #include "ht32f65xxx_66xxx_adc.h" + #else + #include "ht32f5xxxx_adc.h" + #endif +#endif + +#if _AES && LIBCFG_AES + #include "ht32f5xxxx_aes.h" +#endif + +#if _BFTM + #include "ht32f5xxxx_bftm.h" +#endif + +#if _CAN && LIBCFG_CAN0 + #include "ht32f5xxxx_can.h" +#endif + +#if _CKCU + #include "ht32f5xxxx_ckcu.h" +#endif + +#if _CMP && LIBCFG_CMP + #include "ht32f5xxxx_cmp.h" +#endif + +#if _CRC && LIBCFG_CRC + #include "ht32f5xxxx_crc.h" +#endif + +#if _DAC && (LIBCFG_DAC0 || LIBCFG_DAC1) + #include "ht32f5xxxx_dac.h" +#endif + +#if _DAC && LIBCFG_DACDUAL16 + #include "ht32f5xxxx_dac_dual16.h" +#endif + +#if _DIV && LIBCFG_DIV + #include "ht32f5xxxx_div.h" +#endif + +#if _EBI && LIBCFG_EBI + #include "ht32f5xxxx_ebi.h" +#endif + +#if _EXTI + #include "ht32f5xxxx_exti.h" +#endif + +#if _FLASH + #include "ht32f5xxxx_flash.h" +#endif + +#if _GPIO + #include "ht32f5xxxx_gpio.h" +#endif + +#if _GPTM + #include "ht32f5xxxx_tm_type.h" + #include "ht32f5xxxx_tm.h" +#endif + +#if _I2C + #include "ht32f5xxxx_i2c.h" +#endif + +#if _I2S && LIBCFG_I2S + #include "ht32f5xxxx_i2s.h" +#endif + +#if _LCD && LIBCFG_LCD + #include "ht32f5xxxx_lcd.h" +#endif + +#if _LEDC && LIBCFG_LEDC + #include "ht32f5xxxx_ledc.h" +#endif + +#if _MCTM && LIBCFG_MCTM0 + #include "ht32f5xxxx_tm_type.h" + #include "ht32f5xxxx_tm.h" + #include "ht32f5xxxx_mctm.h" +#endif + +#if _MIDI && LIBCFG_MIDI + #include "ht32f5xxxx_midi.h" +#endif + +#if _OPA && LIBCFG_OPA + #if defined(USE_HT32F65230_40) || defined(USE_HT32F65232) + #include "ht32f65xxx_66xxx_opa.h" + #else + #endif +#endif + +#if _PDMA && LIBCFG_PDMA + #include "ht32f5xxxx_pdma.h" +#endif + +#if _PWRCU + #include "ht32f5xxxx_pwrcu.h" +#endif + +#if _RSTCU + #include "ht32f5xxxx_rstcu.h" +#endif + +#if _RTC + #include "ht32f5xxxx_rtc.h" +#endif + +#if _SCI && LIBCFG_SCI0 + #include "ht32f5xxxx_sci.h" +#endif + +#if _SCTM + #include "ht32f5xxxx_tm_type.h" + #include "ht32f5xxxx_tm.h" +#endif + +#if _SLED && LIBCFG_SLED0 + #include "ht32f5xxxx_sled.h" +#endif + +#if _SPI + #include "ht32f5xxxx_spi.h" +#endif + +#if _TKEY && LIBCFG_TKEY + #include "ht32f5xxxx_tkey.h" +#endif + +#if _USART + #include "ht32f5xxxx_usart.h" +#endif + +#if _USB && LIBCFG_USBD + #include "ht32f5xxxx_usbd.h" +#endif + +#if _WDT + #include "ht32f5xxxx_wdt.h" +#endif + +#if _MISC + #include "ht32_cm0plus_misc.h" +#endif + +#if _SERIAL + #include "ht32_serial.h" +#endif + +#if _SWDIV + #include "ht32_div.h" +#endif + +#if _SWRAND + #include "ht32_rand.h" +#endif + +#if (_RETARGET) + #if defined (__GNUC__) + #undef getchar + #define getchar SERIAL_GetChar + #endif +#endif + +#ifdef HTCFG_TIME_IPSEL +#include "ht32_time.h" +#endif + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f5xxxx_mctm.h b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f5xxxx_mctm.h new file mode 100644 index 0000000000..cbea7b628b --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f5xxxx_mctm.h @@ -0,0 +1,298 @@ +/*********************************************************************************************************//** + * @file ht32f5xxxx_mctm.h + * @version $Rev:: 5258 $ + * @date $Date:: 2021-02-04 #$ + * @brief The header file of the MCTM library. + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------------------------------------*/ +#ifndef __HT32F5XXXX_MCTM_H +#define __HT32F5XXXX_MCTM_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------------------------------------*/ +#include "ht32f5xxxx_tm.h" +#include "ht32.h" + +/** @addtogroup HT32F5xxxx_Peripheral_Driver HT32F5xxxx Peripheral Driver + * @{ + */ + +/** @addtogroup MCTM + * @{ + */ + + +/* Exported types ------------------------------------------------------------------------------------------*/ +/** @defgroup MCTM_Exported_Types MCTM exported types + * @{ + */ +/** + * @brief Enumeration of MCTM channel output idle state. + */ +/** + * @brief Definition of Break & DeadTime init structure. + */ +typedef struct +{ + u32 OSSRState; + u32 OSSIState; + u32 LockLevel; + u32 Break0; + u32 Break0Polarity; + u32 AutomaticOutput; + u8 DeadTime; + u8 BreakFilter; +} MCTM_CHBRKCTRInitTypeDef; + +typedef union +{ + struct + { + /* Definitions of CHBRKCTR */ + unsigned long Break0 :1; // BK0E + unsigned long Break0Polarity :1; // BK0P + #if (LIBCFG_TM_652XX_V1) + unsigned long Break1 :1; // BK1E + unsigned long Break1Polarity :1; // BK1E + #else + unsigned long :1; + unsigned long :1; + #endif + unsigned long :1; // CHMOE + unsigned long AutomaticOutput :1; // CHAOE + #if (LIBCFG_TM_65232) + unsigned long Break0FromCMP0 :1; // BK0CMP0 + unsigned long Break0FromCMP1 :1; // BK0CMP1 + #else + unsigned long :1; + unsigned long :1; + #endif + + #if (LIBCFG_TM_652XX_V1) + unsigned long Break0EventCount :2; // BK0FN + unsigned long Break0FDiv :2; // BK0FF + unsigned long Break1EventCount :2; // BK1FN + unsigned long Break1FDiv :2; // BK1FF + #else + unsigned long Break0Filter :4; // BK0F + unsigned long :4; + #endif + + unsigned long LockLevel :2; // LOCKLV + unsigned long DeglitchFilte :1; // GFSEL + unsigned long :1; + unsigned long OSSIState :1; // CHOSSI + unsigned long OSSRState :1; // CHOSSR + #if (LIBCFG_TM_65232) + unsigned long Break1FromCMP0 :1; // BK1CMP0 + unsigned long Break1FromCMP1 :1; // BK1CMP1 + #else + unsigned long :1; + unsigned long :1; + #endif + + unsigned long DeadTime :8; // CHDTG + } Bit; + u32 Reg; +} MCTM_CHBRKCTRTypeDef; +/** + * @} + */ + +/* Exported constants --------------------------------------------------------------------------------------*/ +/** @defgroup MCTM_Exported_Constants MCTM exported constants + * @{ + */ + +/** @defgroup MCTM_BKE Definitions of MCTM break control + * @{ + */ +#define MCTM_BREAK_ENABLE 0x00000001 /*!< Break enable */ +#define MCTM_BREAK_DISABLE 0x00000000 /*!< Break disable */ +/** + * @} + */ + +/** @defgroup MCTM_BKP Definitions of MCTM break polarity + * @{ + */ +#define MCTM_BREAK_POLARITY_LOW 0x00000000 /*!< Break input pin active low level */ +#define MCTM_BREAK_POLARITY_HIGH 0x00000002 /*!< Break input pin active high level */ +/** + * @} + */ + +/** @defgroup MCTM_CHMOE Definitions of MCTM main output enable function state + * @{ + */ +#define MCTM_CHMOE_DISABLE 0x00000000 /*!< main output disable */ +#define MCTM_CHMOE_ENABLE 0x00000010 /*!< Main output enable */ +/** + * @} + */ + +/** @defgroup MCTM_CHAOE Definitions of MCTM automatic output enable function state + * @{ + */ +#define MCTM_CHAOE_DISABLE 0x00000000 /*!< Automatic output enable function disable */ +#define MCTM_CHAOE_ENABLE 0x00000020 /*!< Automatic output enable function enable */ +/** + * @} + */ + +/** @defgroup MCTM_LOCK_LEVEL Definitions of MCTM lock level selection + * @{ + */ +#define MCTM_LOCK_LEVEL_OFF 0x00000000 /*!< Lock Off */ +#define MCTM_LOCK_LEVEL_1 0x00010000 /*!< Lock level 1 */ +#define MCTM_LOCK_LEVEL_2 0x00020000 /*!< Lock level 2 */ +#define MCTM_LOCK_LEVEL_3 0x00030000 /*!< Lock level 3 */ +/** + * @} + */ + +/** @defgroup MCTM_OSSI Definitions of Off-State Selection for Idle mode states + * @{ + */ +#define MCTM_OSSI_STATE_ENABLE 0x00100000 +#define MCTM_OSSI_STATE_DISABLE 0x00000000 +/** + * @} + */ + +/** @defgroup MCTM_OSSR Definitions of Off-State Selection for Run mode states + * @{ + */ +#define MCTM_OSSR_STATE_ENABLE 0x00200000 +#define MCTM_OSSR_STATE_DISABLE 0x00000000 +/** + * @} + */ + +/** @defgroup MCTM_Check_Parameter Check parameter + * @{ + */ + +/** + * @brief Used to check parameter of the MCTMx. + */ +#define IS_MCTM(x) (IS_MCTM0(x)) + +#if (LIBCFG_MCTM0) +#define IS_MCTM0(x) (x == HT_MCTM0) +#else +#define IS_MCTM0(x) (0) +#endif + +/** + * @brief Used to check parameter of the complementary output channel. + */ +#define IS_MCTM_COMPLEMENTARY_CH(x) (((x) == TM_CH_0) || ((x) == TM_CH_1) || \ + ((x) == TM_CH_2)) +/** + * @brief Used to check parameter of the COMUS. + */ +#define IS_MCTM_COMUS(x) ((x == MCTM_COMUS_STIOFF) || (x == MCTM_COMUS_STION)) +/** + * @brief Used to check parameter of the channel output idle state. + */ +#define IS_MCTM_OIS(x) ((x == MCTM_OIS_LOW) || (x == MCTM_OIS_HIGH)) +/** + * @brief Used to check value of MCTM break control state. + */ +#define IS_MCTM_BREAK_STATE(STATE) (((STATE) == MCTM_BREAK_ENABLE) || \ + ((STATE) == MCTM_BREAK_DISABLE)) +/** + * @brief Used to check value of MCTM break polarity. + */ +#define IS_MCTM_BREAK_POLARITY(POLARITY) (((POLARITY) == MCTM_BREAK_POLARITY_LOW) || \ + ((POLARITY) == MCTM_BREAK_POLARITY_HIGH)) +/** + * @brief Used to check value of MCTM automatic output enable control state. + */ +#define IS_MCTM_CHAOE_STATE(STATE) (((STATE) == MCTM_CHAOE_ENABLE) || \ + ((STATE) == MCTM_CHAOE_DISABLE)) +/** + * @brief Used to check value of MCTM lock level. + */ +#define IS_MCTM_LOCK_LEVEL(LEVEL) (((LEVEL) == MCTM_LOCK_LEVEL_OFF) || \ + ((LEVEL) == MCTM_LOCK_LEVEL_1) || \ + ((LEVEL) == MCTM_LOCK_LEVEL_2) || \ + ((LEVEL) == MCTM_LOCK_LEVEL_3)) +/** + * @brief Used to check value of MCTM OSSI state. + */ +#define IS_MCTM_OSSI_STATE(STATE) (((STATE) == MCTM_OSSI_STATE_ENABLE) || \ + ((STATE) == MCTM_OSSI_STATE_DISABLE)) +/** + * @brief Used to check value of MCTM OSSR state. + */ +#define IS_MCTM_OSSR_STATE(STATE) (((STATE) == MCTM_OSSR_STATE_ENABLE) || \ + ((STATE) == MCTM_OSSR_STATE_DISABLE)) +/** + * @} + */ + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------------------------------------*/ +/** @defgroup MCTM_Exported_Functions MCTM exported functions + * @{ + */ +void MCTM_ChNPolarityConfig(HT_TM_TypeDef* MCTMx, TM_CH_Enum Channel, TM_CHP_Enum Pol); +void MCTM_ChannelNConfig(HT_TM_TypeDef* MCTMx, TM_CH_Enum Channel, TM_CHCTL_Enum Control); + +void MCTM_CHMOECmd(HT_TM_TypeDef* MCTMx, ControlStatus NewState); +void MCTM_CHBRKCTRConfig(HT_TM_TypeDef* MCTMx, MCTM_CHBRKCTRInitTypeDef *CHBRKCTRInit); +void MCTM_CHBRKCTRConfig2(HT_TM_TypeDef* MCTMx, MCTM_CHBRKCTRTypeDef *CHBRKCTRInit); +void MCTM_CHBRKCTRStructInit(MCTM_CHBRKCTRInitTypeDef* CHBRKCTRInit); +void MCTM_COMPRECmd(HT_TM_TypeDef* MCTMx, ControlStatus NewState); +void MCTM_COMUSConfig(HT_TM_TypeDef* MCTMx, MCTM_COMUS_Enum Sel); + +#if (LIBCFG_MCTM_UEV1DIS) +void MCTM_UpdateEventDisable(HT_TM_TypeDef* MCTMx, MCTM_UEV1DIS_Enum MCTM_UEV1x, FlagStatus NewState); +#endif +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f5xxxx_midi.h b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f5xxxx_midi.h new file mode 100644 index 0000000000..08da134013 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f5xxxx_midi.h @@ -0,0 +1,404 @@ +/*********************************************************************************************************//** + * @file ht32f5xxxx_midi.h + * @version $Rev:: 6684 $ + * @date $Date:: 2023-01-18 #$ + * @brief The header file of the MIDI library. + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------------------------------------*/ +#ifndef __HT32F5XXXX_MIDI_H +#define __HT32F5XXXX_MIDI_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------------------------------------*/ +#include "ht32.h" + + +/** @addtogroup HT32F5xxxx_Peripheral_Driver HT32F5xxxx Peripheral Driver + * @{ + */ + +/** @addtogroup MIDI + * @{ + */ + +/* Exported types ------------------------------------------------------------------------------------------*/ +/** @defgroup MIDI_Exported_Types MIDI exported types + * @{ + */ + +/** + * @brief Enumeration of MIDI CTRL MCUCHEN3. + */ +typedef enum +{ + MCUCHEN3_OFF = DISABLE, + MCUCHEN3_ON = ENABLE, +} MIDI_CTRL_MCUCHEN3_Enum; +/** + * @brief Enumeration of MIDI CTRL MCUCHEN2. + */ +typedef enum +{ + MCUCHEN2_OFF = DISABLE, + MCUCHEN2_ON = ENABLE, +} MIDI_CTRL_MCUCHEN2_Enum; +/** + * @brief Enumeration of MIDI CTRL MCUCHEN1. + */ +typedef enum +{ + MCUCHEN1_OFF = DISABLE, + MCUCHEN1_ON = ENABLE, +} MIDI_CTRL_MCUCHEN1_Enum; +/** + * @brief Enumeration of MIDI CTRL MCUCHEN0. + */ +typedef enum +{ + MCUCHEN0_OFF = DISABLE, + MCUCHEN0_ON = ENABLE, +} MIDI_CTRL_MCUCHEN0_Enum; +/** + * @brief Enumeration of MIDI CTRL MUSIC. + */ +typedef enum +{ + MUSICEN_OFF = DISABLE, + MUSICEN_ON = ENABLE, +} MIDI_CTRL_MUSICEN_Enum; +/** + * @brief Enumeration of MIDI SPI RDEN. + */ +typedef enum +{ + SPIRDEN_OFF = DISABLE, + SPIRDEN_ON = ENABLE, +} MIDI_CTRL_SPIRDEN_Enum; +/** + * @brief Enumeration of MIDI SPI DISLOOP. + */ +typedef enum +{ + SPIDISLOOP_OFF = DISABLE, + SPIDISLOOP_ON = ENABLE, +} MIDI_CTRL_SPIDISLOOP_Enum; +/** + * @brief Enumeration of MIDI CTRL CHS. + */ +typedef enum +{ + CHS16 = 0, /*!< Select 16-Channel */ + CHS20, /*!< Select 20-Channel */ + CHS24, /*!< Select 24-Channel */ + CHS28, /*!< Select 28-Channel */ + CHS32, /*!< Select 32-Channel */ +} MIDI_CTRL_CHS_Enum; + +/** + * @brief Enumeration of MIDI Note. + */ +typedef enum +{ + BL0 = 0, + BL1, + BL2, + BL3, + BL4, + BL5, + BL6, + BL7, + BL8, + BL9, + BL10, + BL11, +} MIDI_FREQ_BL_Enum; + +/** + * @brief Enumeration of MIDI VOL AR. + */ +typedef enum +{ + ENV_RELEASE = RESET, + ENV_ATTACK = SET, +} MIDI_VOL_AR_Enum; +/** + * @brief Enumeration of MIDI VOL ENV. + */ +typedef enum +{ + ENV_TYPE0 = 0, + ENV_TYPE1, + ENV_TYPE2, + ENV_NO, +} MIDI_VOL_ENV_Enum; + +/** + * @brief Enumeration of MIDI RE_NUM WBS. + */ +typedef enum +{ + WBS8 = 0, /*!< WBS 8-bit */ + WBS12, /*!< WBS 12-bit */ + WBS16, /*!< WBS 16-bit */ +} MIDI_RENUM_WBS_Enum; + +/** + * @brief Enumeration of MIDI CHAN ST. + */ +typedef enum +{ + ST_OFF = DISABLE, + ST_ON = ENABLE, +} MIDI_CHAN_ST_Enum; +/** + * @brief Enumeration of MIDI CHAN VM. + */ +typedef enum +{ + VM_OFF = DISABLE, + VM_ON = ENABLE, +} MIDI_CHAN_VM_Enum; +/** + * @brief Enumeration of MIDI CHAN FR. + */ +typedef enum +{ + FR_OFF = DISABLE, + FR_ON = ENABLE, +} MIDI_CHAN_FR_Enum; +/** + * @brief Enumeration of MIDI CHAN CHx. + */ +typedef enum +{ + MIDI_CHx0 = 0, + MIDI_CHx1, + MIDI_CHx2, + MIDI_CHx3, + MIDI_CHx4, + MIDI_CHx5, + MIDI_CHx6, + MIDI_CHx7, + MIDI_CHx8, + MIDI_CHx9, + MIDI_CHx10, + MIDI_CHx11, + MIDI_CHx12, + MIDI_CHx13, + MIDI_CHx14, + MIDI_CHx15, + MIDI_CHx16, + MIDI_CHx17, + MIDI_CHx18, + MIDI_CHx19, + MIDI_CHx20, + MIDI_CHx21, + MIDI_CHx22, + MIDI_CHx23, + MIDI_CHx24, + MIDI_CHx25, + MIDI_CHx26, + MIDI_CHx27, + MIDI_CHx28, + MIDI_CHx29, + MIDI_CHx30, + MIDI_CHx31, +} MIDI_CHAN_CHx_Enum; + +typedef struct +{ + u8 MIDI_CTRL_DACDS; + ControlStatus MIDI_CTRL_MUSICEN; + ControlStatus MIDI_CTRL_SPIDISLOOP; + u8 MIDI_CTRL_CHS; + MIDI_FREQ_BL_Enum MIDI_FREQ_BL; + u16 MIDI_FREQ_FR; + MIDI_VOL_AR_Enum MIDI_VOL_AR; + MIDI_VOL_ENV_Enum MIDI_VOL_ENV; + u16 MIDI_VOL_VL; + u16 MIDI_VOL_VR; + u32 MIDI_STADDR; + MIDI_RENUM_WBS_Enum MIDI_RENUM_WBS; + u16 MIDI_RENUM_RE; + u32 MIDI_ENDADDR; + ControlStatus MIDI_CHAN_ST; + ControlStatus MIDI_CHAN_VM; + ControlStatus MIDI_CHAN_FR; + u8 MIDI_CHAN_CHx; +} MIDI_InitTypeDef; +/** + * @} + */ + +/* Exported constants --------------------------------------------------------------------------------------*/ +/** @defgroup MIDI_Exported_Constants MIDI exported constants + * @{ + */ +/* Definitions of MIDI_FLAG */ +#define MIDI_FLAG_INTF 0x0001 + +/* Definitions of MIDI_INT */ +#define MIDI_INT_INTEN 0x0001 +#define MIDI_INT_MIDII_DMAEN 0x0002 +#define MIDI_INT_MIDIO_DMAEN 0x0004 + +/* Definitions of MIDI_VOL */ +#define VOL_MAX 0 +#define VOL_MID 0x1FF +#define VOL_380 0x380 +#define VOL_MIN 0x3FF +#define VOL_MUTE VOL_MIN + +//#define IS_MIDI(x) ((MIDI == HT_MIDI)) +#define IS_MIDI(x) ((x == HT_MIDI)) + +#define IS_MIDI_INT(x) (((x & 0xFFFFFFF8) == 0x0) && (x != 0)) +#define IS_MIDI_FLAG(x) (x == MIDI_FLAG_INTF) +#define IS_MIDI_FLAG_CLEAR(x) (((x & 0xFFFFFFFE) == 0) && (x != 0)) + +#define IS_MIDI_CTRL_MCUCHEN3(x) ((x == MCUCHEN3_OFF) || (x == MCUCHEN3_ON)) +#define IS_MIDI_CTRL_MCUCHEN2(x) ((x == MCUCHEN2_OFF) || (x == MCUCHEN2_ON)) +#define IS_MIDI_CTRL_MCUCHEN1(x) ((x == MCUCHEN1_OFF) || (x == MCUCHEN1_ON)) +#define IS_MIDI_CTRL_MCUCHEN0(x) ((x == MCUCHEN0_OFF) || (x == MCUCHEN0_ON)) +#define IS_MIDI_CTRL_DACDS(x) (x < 8) +#define IS_MIDI_CTRL_MUSICEN(x) ((x == MUSICEN_OFF) || (x == MUSICEN_ON)) +#define IS_MIDI_CTRL_SPIRDEN(x) ((x == SPIRDEN_OFF) || (x == SPIRDEN_ON)) +#define IS_MIDI_CTRL_SPIDISLOOP(x) ((x == SPIDISLOOP_OFF) || (x == SPIDISLOOP_ON)) +#define IS_MIDI_CTRL_CHS(x) (x < 8) + +#define IS_MIDI_FREQ_BL(x) (x < 12) +#define IS_MIDI_FREQ_FR(x) (x < 0xFFF) + +#define IS_MIDI_VOL_AR(x) (ENV_ATTACK || ENV_RELEASE) +#define IS_MIDI_VOL_ENV(x) (ENV_TYPE0 || ENV_TYPE1 || ENV_TYPE2 || ENV_NO) +#define IS_MIDI_VOL_VL(x) (x < 0x3FF) +#define IS_MIDI_VOL_VR(x) (x < 0x3FF) + +#define IS_MIDI_STADDR(x) (x < 0x7FFFF) + +#define IS_MIDI_RENUM_WBS(x) ((x == WBS8) || (x == WBS12) || (x == WBS16)) +#define IS_MIDI_RENUM_RE(x) (x < 0x7FFF) + +#define IS_MIDI_ENDADDR(x) (x < 0xFFFFFF) + +#define IS_MIDI_CHAN_ST(x) ((x == ST_OFF) || (x == ST_ON)) +#define IS_MIDI_CHAN_VM(x) ((x == VM_OFF) || (x == VM_ON)) +#define IS_MIDI_CHAN_FR(x) ((x == FR_OFF) || (x == FR_ON)) +#define IS_MIDI_CHAN_CHx(x) (x < 32) + +#define IS_MIDI_MCUCHx11_BH(x) (x < 0xFFFF) +#define IS_MIDI_MCUCHx11_BL(x) (x < 0xFFFF) + +#define IS_MIDI_MCUCHx12_CH(x) (x < 0xFFFF) +#define IS_MIDI_MCUCHx12_CL(x) (x < 0xFFFF) + +#define IS_MIDI_MCUCHx13_DH(x) (x < 0xFFFF) +#define IS_MIDI_MCUCHx13_DL(x) (x < 0xFFFF) + +#define IS_MIDI_MCUCHx14_EH(x) (x < 0xFFFF) +#define IS_MIDI_MCUCHx14_EL(x) (x < 0xFFFF) +/** + * @} + */ + +/* Exported functions --------------------------------------------------------------------------------------*/ +/** @defgroup MIDI_Exported_Functions MIDI exported functions + * @{ + */ +void MIDI_DeInit(void); +void MIDI_Init(HT_MIDI_TypeDef* MIDIx, MIDI_InitTypeDef* MIDI_InitStruct); +void MIDI_StructInit(MIDI_InitTypeDef* MIDI_InitStruct); +void MIDI_IntConfig(HT_MIDI_TypeDef* MIDIx, u32 MIDI_Int, ControlStatus NewState); +FlagStatus MIDI_GetFlagStatus(HT_MIDI_TypeDef* MIDIx, u32 MIDI_Flag); +void MIDI_ClearFlag(HT_MIDI_TypeDef* MIDIx, u32 MIDI_Flag); + +void MIDI_CTRL(HT_MIDI_TypeDef* MIDIx, + MIDI_CTRL_MCUCHEN3_Enum MCUCHEN3, MIDI_CTRL_MCUCHEN2_Enum MCUCHEN2, + MIDI_CTRL_MCUCHEN1_Enum MCUCHEN1, MIDI_CTRL_MCUCHEN0_Enum MCUCHEN0, + u8 DACDS, + MIDI_CTRL_MUSICEN_Enum MUSICEN, + MIDI_CTRL_SPIRDEN_Enum SPIRDEN, MIDI_CTRL_SPIDISLOOP_Enum SPIDISLOOP, + MIDI_CTRL_CHS_Enum CHS); +void MIDI_FREQ(HT_MIDI_TypeDef* MIDIx, MIDI_FREQ_BL_Enum BL, u16 FR); +void MIDI_VOL(HT_MIDI_TypeDef* MIDIx, MIDI_VOL_AR_Enum A_R, MIDI_VOL_ENV_Enum ENV, u16 VL, u16 VR); +void MIDI_STADDR(HT_MIDI_TypeDef* MIDIx, u32 ST_ADDR); +void MIDI_RENUM(HT_MIDI_TypeDef* MIDIx, MIDI_RENUM_WBS_Enum WBS, u16 RE); +void MIDI_ENDADDR(HT_MIDI_TypeDef* MIDIx, u32 END_ADDR); +void MIDI_CHAN(HT_MIDI_TypeDef* MIDIx, MIDI_CHAN_ST_Enum ST, MIDI_CHAN_VM_Enum VM, MIDI_CHAN_FR_Enum FR, u8 CHx); + +void MIDI_MCUCH0(HT_MIDI_TypeDef* MIDIx, u16 CH0B, u16 CH0A); +void MIDI_MCUCH1(HT_MIDI_TypeDef* MIDIx, u16 CH1B, u16 CH1A); +void MIDI_MCUCH2(HT_MIDI_TypeDef* MIDIx, u16 CH2B, u16 CH2A); +void MIDI_MCUCH3(HT_MIDI_TypeDef* MIDIx, u16 CH3B, u16 CH3A); + +void MIDI_FREQ_BL(HT_MIDI_TypeDef* MIDIx, MIDI_FREQ_BL_Enum BL); +void MIDI_FREQ_FR(HT_MIDI_TypeDef* MIDIx, u16 FR); +void MIDI_VOL_AR(HT_MIDI_TypeDef* MIDIx, MIDI_VOL_AR_Enum A_R); +void MIDI_VOL_ENV(HT_MIDI_TypeDef* MIDIx, MIDI_VOL_ENV_Enum ENV); +void MIDI_VOL_VL(HT_MIDI_TypeDef* MIDIx, u16 VL); +void MIDI_VOL_VR(HT_MIDI_TypeDef* MIDIx, u16 VR); +void MIDI_RENUM_WBS(HT_MIDI_TypeDef* MIDIx, MIDI_RENUM_WBS_Enum WBS); +void MIDI_RENUM_RE(HT_MIDI_TypeDef* MIDIx, u16 RE); +void MIDI_CHAN_STCmd(HT_MIDI_TypeDef* MIDIx, ControlStatus NewState); +void MIDI_CHAN_VMCmd(HT_MIDI_TypeDef* MIDIx, ControlStatus NewState); +void MIDI_CHAN_FRCmd(HT_MIDI_TypeDef* MIDIx, ControlStatus NewState); +void MIDI_CHAN_CHx(HT_MIDI_TypeDef* MIDIx, u8 CHx); +void MIDI_MCUCH0_CH0B(HT_MIDI_TypeDef* MIDIx, u16 CH0B); +void MIDI_MCUCH0_CH0A(HT_MIDI_TypeDef* MIDIx, u16 CH0A); +void MIDI_MCUCH1_CH1B(HT_MIDI_TypeDef* MIDIx, u16 CH1B); +void MIDI_MCUCH1_CH1A(HT_MIDI_TypeDef* MIDIx, u16 CH1A); +void MIDI_MCUCH2_CH2B(HT_MIDI_TypeDef* MIDIx, u16 CH2B); +void MIDI_MCUCH2_CH2A(HT_MIDI_TypeDef* MIDIx, u16 CH2A); +void MIDI_MCUCH3_CH3B(HT_MIDI_TypeDef* MIDIx, u16 CH3B); +void MIDI_MCUCH3_CH3A(HT_MIDI_TypeDef* MIDIx, u16 CH3A); +void MIDI_CTRL_MCUCHEN3(HT_MIDI_TypeDef* MIDIx, ControlStatus NewState); +void MIDI_CTRL_MCUCHEN2(HT_MIDI_TypeDef* MIDIx, ControlStatus NewState); +void MIDI_CTRL_MCUCHEN1(HT_MIDI_TypeDef* MIDIx, ControlStatus NewState); +void MIDI_CTRL_MCUCHEN0(HT_MIDI_TypeDef* MIDIx, ControlStatus NewState); +void MIDI_CTRL_DACDS(HT_MIDI_TypeDef* MIDIx, u8 DACDS); +void MIDI_CTRL_MUSICENCmd(HT_MIDI_TypeDef* MIDIx, ControlStatus NewState); +void MIDI_CTRL_SPIRDENCmd(HT_MIDI_TypeDef* MIDIx, ControlStatus NewState); +void MIDI_CTRL_SPIDISLOOPCmd(HT_MIDI_TypeDef* MIDIx, ControlStatus NewState); +void MIDI_CTRL_CHS(HT_MIDI_TypeDef* MIDIx, u8 CHS); +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f5xxxx_pdma.h b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f5xxxx_pdma.h new file mode 100644 index 0000000000..1dbea97ba3 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f5xxxx_pdma.h @@ -0,0 +1,377 @@ +/*********************************************************************************************************//** + * @file ht32f5xxxx_pdma.h + * @version $Rev:: 7319 $ + * @date $Date:: 2023-10-28 #$ + * @brief The header file of the PDMA library. + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------------------------------------*/ +#ifndef __HT32F5XXXX_PDMA_H +#define __HT32F5XXXX_PDMA_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------------------------------------*/ +#include "ht32.h" + +/** @addtogroup HT32F5xxxx_Peripheral_Driver HT32F5xxxx Peripheral Driver + * @{ + */ + +/** @addtogroup PDMA + * @{ + */ + + +/* Exported types ------------------------------------------------------------------------------------------*/ +/** @defgroup PDMA_Exported_Types PDMA exported types + * @{ + */ + +/** + * @brief Definition of PDMA channel Init Structure + */ +typedef struct +{ + u32 PDMACH_SrcAddr; /*!< source address */ + u32 PDMACH_DstAddr; /*!< destination address */ + u16 PDMACH_BlkCnt; /*!< number of blocks for a PDMA transfer (1 ~ 65,535) */ + u8 PDMACH_BlkLen; /*!< number of data for a block (1 ~ 255) */ + u8 PDMACH_DataSize; /*!< number of bits for a data (8-bit/16-bit/32-bit) */ + u16 PDMACH_Priority; /*!< software priority for a PDMA transfer (L/M/H/VH) */ + u16 PDMACH_AdrMod; /*!< address mode (LIN_INC/LIN_DEC/CIR_INC/CIR_DEC/FIX/AUTO_RELOAD) */ +} PDMACH_InitTypeDef; +/** + * @} + */ + +/* Exported constants --------------------------------------------------------------------------------------*/ +/** @defgroup PDMA_Exported_Constants PDMA exported constants + * @{ + */ +/* priority */ +#define L_PRIO (0) /*!< low priority */ +#define M_PRIO (1UL << 8) /*!< medium priority */ +#define H_PRIO (2UL << 8) /*!< high priority */ +#define VH_PRIO (3UL << 8) /*!< very high priority */ + +#define IS_PDMA_PRIO(PRIO) ((PRIO >> 8) < 4) /*!< check channel priority parameter */ + +/* address mode */ +#define AUTO_RELOAD (1UL << 11) /*!< enable auto reload */ +#define ADR_FIX (1UL << 10) /*!< enable address fix */ + +#define SRC_ADR_LIN_INC (0) /*!< source address linear increment */ +#define SRC_ADR_LIN_DEC (1UL << 6) /*!< source address linear decrement */ +#define SRC_ADR_CIR_INC (2UL << 6) /*!< source address circular increment */ +#define SRC_ADR_CIR_DEC (3UL << 6) /*!< source address circular decrement */ +#define SRC_ADR_FIX (ADR_FIX | SRC_ADR_CIR_INC) /*!< source address fix */ + +#define DST_ADR_LIN_INC (0) /*!< destination address linear increment */ +#define DST_ADR_LIN_DEC (1UL << 4) /*!< destination address linear decrement */ +#define DST_ADR_CIR_INC (2UL << 4) /*!< destination address circular increment */ +#define DST_ADR_CIR_DEC (3UL << 4) /*!< destination address circular decrement */ +#define DST_ADR_FIX (ADR_FIX | DST_ADR_CIR_INC) /*!< destination address fix */ + +#define IS_PDMA_ADR_MOD(MOD) ((MOD & 0xFFFFF30F) == 0) /*!< check address mode parameters */ + +/* transfer size */ +#define IS_PDMA_BLK_CNT(CNT) ((CNT > 0) && (CNT <= 65535)) /*!< block count per transfer */ +#define IS_PDMA_BLK_LEN(LEN) ((LEN > 0) && (LEN <= 255)) /*!< block size per block count */ + +/* transfer width */ +#define WIDTH_8BIT (0) /*!< 8-bit transfer width */ +#define WIDTH_16BIT (1UL << 2) /*!< 16-bit transfer width */ +#define WIDTH_32BIT (2UL << 2) /*!< 32-bit transfer width */ + +#define IS_PDMA_WIDTH(WIDTH) ((WIDTH >> 2) < 3) /*!< check transfer width parameter */ + +/* channel number */ +#define PDMA_CH0 (0) /*!< channel 0 number */ +#define PDMA_CH1 (1UL) /*!< channel 1 number */ +#define PDMA_CH2 (2UL) /*!< channel 2 number */ +#define PDMA_CH3 (3UL) /*!< channel 3 number */ +#define PDMA_CH4 (4UL) /*!< channel 4 number */ +#define PDMA_CH5 (5UL) /*!< channel 5 number */ + +#define IS_PDMA_CH(CH) (CH < 6) /*!< check channel number parameter */ + +#define PDMA_ADC0 PDMA_CH0 /*!< ADC PDMA channel number */ +#if (LIBCFG_ADC1) +#define PDMA_ADC1 PDMA_CH1 /*!< ADC PDMA channel number */ +#endif +#define PDMA_ADC PDMA_ADC0 + +#if(LIBCFG_DAC0) +#define PDMA_DAC0_CH0 PDMA_CH1 /*!< DAC0 CH0 PDMA channel number */ +#define PDMA_DAC0_CH1 PDMA_CH3 /*!< DAC0 CH1 PDMA channel number */ +#endif + +#if(LIBCFG_DAC1) +#define PDMA_DAC1_CH0 PDMA_CH4 /*!< DAC1 CH0 PDMA channel number */ +#define PDMA_DAC1_CH1 PDMA_CH5 /*!< DAC1 CH1 PDMA channel number */ +#endif + +#if defined(USE_HT32F65230_40) || defined(USE_HT32F65232) || defined(USE_HT32F0006) || defined(USE_HT32F61244_45) +#define PDMA_SPI0_RX PDMA_CH4 /*!< SPI0_RX PDMA channel number */ +#define PDMA_SPI0_TX PDMA_CH5 /*!< SPI0_TX PDMA channel number */ +#elif defined(USE_HT32F57342_52) || defined(USE_HT32F52357_67) || defined(USE_HT32F67041_51) || defined(USE_HT32F52234_44) +#define PDMA_SPI0_RX PDMA_CH2 /*!< SPI0_RX PDMA channel number */ +#define PDMA_SPI0_TX PDMA_CH3 /*!< SPI0_TX PDMA channel number */ +#else +#define PDMA_SPI0_RX PDMA_CH0 /*!< SPI0_RX PDMA channel number */ +#define PDMA_SPI0_TX PDMA_CH1 /*!< SPI0_TX PDMA channel number */ +#endif + +#if (LIBCFG_SPI1) +#define PDMA_SPI1_RX PDMA_CH4 /*!< SPI1_RX PDMA channel number */ +#define PDMA_SPI1_TX PDMA_CH5 /*!< SPI1_TX PDMA channel number */ +#endif + +#if (LIBCFG_QSPI) +#define PDMA_QSPI_TX PDMA_CH1 /*!< QSPI_TX PDMA channel number */ +#define PDMA_QSPI_RX PDMA_CH0 /*!< QSPI_RX PDMA channel number */ +#endif + +#define PDMA_USART0_RX PDMA_CH0 /*!< USART0_RX PDMA channel number */ +#define PDMA_USART0_TX PDMA_CH1 /*!< USART0_TX PDMA channel number */ +#if (LIBCFG_USART1) +#define PDMA_USART1_RX PDMA_CH2 /*!< USART1_RX PDMA channel number */ +#define PDMA_USART1_TX PDMA_CH3 /*!< USART1_TX PDMA channel number */ +#endif + +#if defined(USE_HT32F52243_53) || defined(USE_HT32F52357_67) || defined(USE_HT32F54243_53) +#define PDMA_UART2_RX PDMA_CH0 /*!< UART2_RX PDMA channel number */ +#define PDMA_UART2_TX PDMA_CH1 /*!< UART2_TX PDMA channel number */ +#define PDMA_UART3_RX PDMA_CH4 /*!< UART3_RX PDMA channel number */ +#define PDMA_UART3_TX PDMA_CH5 /*!< UART3_TX PDMA channel number */ +#endif + +#define PDMA_UART0_RX PDMA_CH2 /*!< UART0_RX PDMA channel number */ +#define PDMA_UART0_TX PDMA_CH3 /*!< UART0_TX PDMA channel number */ +#if (LIBCFG_UART1) +#define PDMA_UART1_RX PDMA_CH4 /*!< UART1_RX PDMA channel number */ +#define PDMA_UART1_TX PDMA_CH5 /*!< UART1_TX PDMA channel number */ +#endif + +#if defined(USE_HT32F65230_40) || defined(USE_HT32F65232) +#define PDMA_I2C0_RX PDMA_CH2 /*!< I2C0_RX PDMA channel number */ +#define PDMA_I2C0_TX PDMA_CH3 /*!< I2C0_TX PDMA channel number */ +#elif defined(USE_HT32F52234_44) +#define PDMA_I2C0_RX PDMA_CH2 /*!< I2C0_RX PDMA channel number */ +#define PDMA_I2C0_TX PDMA_CH0 /*!< I2C0_TX PDMA channel number */ +#else +#define PDMA_I2C0_RX PDMA_CH2 /*!< I2C0_RX PDMA channel number */ +#define PDMA_I2C0_TX PDMA_CH4 /*!< I2C0_TX PDMA channel number */ +#endif +#if (LIBCFG_I2C1) +#if defined(USE_HT32F52234_44) +#define PDMA_I2C1_RX PDMA_CH3 /*!< I2C1_RX PDMA channel number */ +#define PDMA_I2C1_TX PDMA_CH1 /*!< I2C1_TX PDMA channel number */ +#else +#define PDMA_I2C1_RX PDMA_CH3 /*!< I2C1_RX PDMA channel number */ +#define PDMA_I2C1_TX PDMA_CH5 /*!< I2C1_TX PDMA channel number */ +#endif +#endif + +#if defined(USE_HT32F52243_53) || defined(USE_HT32F54243_53) +#define PDMA_I2C2_RX PDMA_CH0 /*!< I2C2_RX PDMA channel number */ +#define PDMA_I2C2_TX PDMA_CH1 /*!< I2C2_TX PDMA channel number */ +#elif defined(USE_HT32F52234_44) +#define PDMA_I2C2_RX PDMA_CH4 /*!< I2C2_RX PDMA channel number */ +#define PDMA_I2C2_TX PDMA_CH5 /*!< I2C2_TX PDMA channel number */ +#endif + +#if defined(USE_HT32F52342_52) || defined(USE_HT32F5826) || defined(USE_HT32F57342_52) || defined(USE_HT32F52357_67) +#define PDMA_SCI0_TX PDMA_CH5 /*!< SCI0_TX PDMA channel number */ +#define PDMA_SCI0_RX PDMA_CH4 /*!< SCI0_RX PDMA channel number */ +#define PDMA_SCI1_TX PDMA_CH3 /*!< SCI1_TX PDMA channel number */ +#define PDMA_SCI1_RX PDMA_CH2 /*!< SCI1_RX PDMA channel number */ +#endif + +#if (LIBCFG_I2S) +#define PDMA_I2S_TX PDMA_CH2 /*!< I2S_TX PDMA channel number */ +#define PDMA_I2S_RX PDMA_CH1 /*!< I2S_RX PDMA channel number */ +#endif + +#if (LIBCFG_MCTM0) +#define PDMA_MCTM0_CH0 PDMA_CH0 /*!< MCTM0_CH0 PDMA channel number */ +#define PDMA_MCTM0_TRIG PDMA_CH1 /*!< MCTM0_TRIG PDMA channel number */ +#define PDMA_MCTM0_CH1 PDMA_CH2 /*!< MCTM0_CH1 PDMA channel number */ +#define PDMA_MCTM0_CH2 PDMA_CH3 /*!< MCTM0_CH2 PDMA channel number */ +#define PDMA_MCTM0_CH3 PDMA_CH4 /*!< MCTM0_CH3 PDMA channel number */ +#define PDMA_MCTM0_UEV2 PDMA_CH4 /*!< MCTM0_UEV2 PDMA channel number */ +#define PDMA_MCTM0_UEV1 PDMA_CH5 /*!< MCTM0_UEV1 PDMA channel number */ +#endif + +#if (LIBCFG_NO_GPTM0) +#else +#if defined(USE_HT32F65230_40) || defined(USE_HT32F65232) +#define PDMA_GPTM0_CH1 PDMA_CH0 /*!< GPTM0_CH1 PDMA channel number */ +#define PDMA_GPTM0_CH2 PDMA_CH1 /*!< GPTM0_CH2 PDMA channel number */ +#define PDMA_GPTM0_CH0 PDMA_CH2 /*!< GPTM0_CH0 PDMA channel number */ +#define PDMA_GPTM0_CH3 PDMA_CH3 /*!< GPTM0_CH3 PDMA channel number */ +#define PDMA_GPTM0_UEV PDMA_CH4 /*!< GPTM0_UEV PDMA channel number */ +#define PDMA_GPTM0_TRIG PDMA_CH5 /*!< GPTM0_TRIG PDMA channel number */ +#else +#define PDMA_GPTM0_CH1 PDMA_CH0 /*!< GPTM0_CH1 PDMA channel number */ +#define PDMA_GPTM0_CH3 PDMA_CH0 /*!< GPTM0_CH3 PDMA channel number */ +#define PDMA_GPTM0_CH2 PDMA_CH1 /*!< GPTM0_CH2 PDMA channel number */ +#define PDMA_GPTM0_UEV PDMA_CH1 /*!< GPTM0_UEV PDMA channel number */ +#define PDMA_GPTM0_CH0 PDMA_CH2 /*!< GPTM0_CH0 PDMA channel number */ +#define PDMA_GPTM0_TRIG PDMA_CH2 /*!< GPTM0_TRIG PDMA channel number */ +#endif +#endif + +#if (LIBCFG_GPTM1) +#define PDMA_GPTM1_CH0 PDMA_CH3 /*!< GPTM1_CH0 PDMA channel number */ +#define PDMA_GPTM1_CH3 PDMA_CH3 /*!< GPTM1_CH3 PDMA channel number */ +#define PDMA_GPTM1_CH1 PDMA_CH4 /*!< GPTM1_CH1 PDMA channel number */ +#define PDMA_GPTM1_UEV PDMA_CH4 /*!< GPTM1_UEV PDMA channel number */ +#define PDMA_GPTM1_CH2 PDMA_CH5 /*!< GPTM1_CH2 PDMA channel number */ +#define PDMA_GPTM1_TRIG PDMA_CH5 /*!< GPTM1_TRIG PDMA channel number */ +#endif + +#if defined(USE_HT32F65230_40) || defined(USE_HT32F65232) +#define PDMA_SCTM0_CH0 PDMA_CH0 /*!< SCTM0_CH0 PDMA channel number */ +#define PDMA_SCTM0_CH1 PDMA_CH1 /*!< SCTM0_CH1 PDMA channel number */ +#define PDMA_SCTM1_CH0 PDMA_CH2 /*!< SCTM1_CH0 PDMA channel number */ +#define PDMA_SCTM1_CH1 PDMA_CH3 /*!< SCTM1_CH1 PDMA channel number */ +#define PDMA_SCTM2_CH0 PDMA_CH4 /*!< SCTM2_CH0 PDMA channel number */ +#define PDMA_SCTM2_CH1 PDMA_CH5 /*!< SCTM2_CH1 PDMA channel number */ +#define PDMA_SCTM3_CH0 PDMA_CH4 /*!< SCTM3_CH0 PDMA channel number */ +#define PDMA_SCTM3_CH1 PDMA_CH5 /*!< SCTM3_CH1 PDMA channel number */ +#endif + +#if (LIBCFG_PWM0) +#if defined(USE_HT32F52234_44) +#define PDMA_PWM0_CH0 PDMA_CH5 /*!< PWM0_CH0 PDMA channel number */ +#define PDMA_PWM0_CH1 PDMA_CH3 /*!< PWM0_CH1 PDMA channel number */ +#define PDMA_PWM0_CH2 PDMA_CH4 /*!< PWM0_CH2 PDMA channel number */ +#define PDMA_PWM0_CH3 PDMA_CH3 /*!< PWM0_CH3 PDMA channel number */ +#define PDMA_PWM0_TRIG PDMA_CH5 /*!< PWM0_TRIG PDMA channel number */ +#define PDMA_PWM0_UEV PDMA_CH4 /*!< PWM0_UEV PDMA channel number */ +#else +#define PDMA_PWM0_CH0 PDMA_CH2 /*!< PWM0_CH0 PDMA channel number */ +#define PDMA_PWM0_CH1 PDMA_CH0 /*!< PWM0_CH1 PDMA channel number */ +#define PDMA_PWM0_CH2 PDMA_CH1 /*!< PWM0_CH2 PDMA channel number */ +#define PDMA_PWM0_CH3 PDMA_CH0 /*!< PWM0_CH3 PDMA channel number */ +#define PDMA_PWM0_TRIG PDMA_CH2 /*!< PWM0_TRIG PDMA channel number */ +#define PDMA_PWM0_UEV PDMA_CH1 /*!< PWM0_UEV PDMA channel number */ +#endif +#endif + +#if (LIBCFG_PWM1) +#define PDMA_PWM1_CH0 PDMA_CH5 /*!< PWM1_CH0 PDMA channel number */ +#define PDMA_PWM1_CH1 PDMA_CH3 /*!< PWM1_CH1 PDMA channel number */ +#define PDMA_PWM1_CH2 PDMA_CH4 /*!< PWM1_CH2 PDMA channel number */ +#define PDMA_PWM1_CH3 PDMA_CH3 /*!< PWM1_CH3 PDMA channel number */ +#define PDMA_PWM1_TRIG PDMA_CH5 /*!< PWM1_TRIG PDMA channel number */ +#define PDMA_PWM1_UEV PDMA_CH4 /*!< PWM1_UEV PDMA channel number */ +#endif + +#if (LIBCFG_PWM2) +#define PDMA_PWM2_CH0 PDMA_CH5 /*!< PWM2_CH0 PDMA channel number */ +#define PDMA_PWM2_CH1 PDMA_CH3 /*!< PWM2_CH1 PDMA channel number */ +#define PDMA_PWM2_CH2 PDMA_CH4 /*!< PWM2_CH2 PDMA channel number */ +#define PDMA_PWM2_CH3 PDMA_CH3 /*!< PWM2_CH3 PDMA channel number */ +#define PDMA_PWM2_TRIG PDMA_CH5 /*!< PWM2_TRIG PDMA channel number */ +#define PDMA_PWM2_UEV PDMA_CH4 /*!< PWM2_UEV PDMA channel number */ +#endif + +#if (LIBCFG_SLED0) +#define PDMA_SLED0 PDMA_CH0 /*!< SLED0 PDMA channel number */ +#endif +#if (LIBCFG_SLED1) +#define PDMA_SLED1 PDMA_CH1 /*!< SLED1 PDMA channel number */ +#endif + +#if (LIBCFG_AES) +#define PDMA_AES_OUT PDMA_CH4 /*!< AES_OUT PDMA channel number */ +#define PDMA_AES_IN PDMA_CH5 /*!< AES_IN PDMA channel number */ +#endif + +#if (LIBCFG_MIDI) +#define PDMA_MIDI_IN PDMA_CH3 /*!< MIDI_IN PDMA channel number */ +#define PDMA_MIDI_OUT PDMA_CH4 /*!< MIDI_OUT PDMA channel number */ +#endif + +/* flag */ +#define PDMA_FLAG_GE (1UL << 0) /*!< PDMA channel global event flag */ +#define PDMA_FLAG_BE (1UL << 1) /*!< PDMA channel block end flag */ +#define PDMA_FLAG_HT (1UL << 2) /*!< PDMA channel half transfer flag */ +#define PDMA_FLAG_TC (1UL << 3) /*!< PDMA channel transfer complete flag */ +#define PDMA_FLAG_TE (1UL << 4) /*!< PDMA channel transfer error flag */ + +#define IS_PDMA_FLAG(FLAG) (((FLAG & 0xFFFFFFE0) == 0) && (FLAG != 0)) +#define IS_PDMA_CLEAR_FLAG(FLAG) (((FLAG & 0xFFFFFFE0) == 0) && (FLAG != 0)) + +/* interrupt */ +#define PDMA_INT_GE (1UL << 0) /*!< PDMA channel global event interrupt */ +#define PDMA_INT_BE (1UL << 1) /*!< PDMA channel block end interrupt */ +#define PDMA_INT_HT (1UL << 2) /*!< PDMA channel half transfer interrupt */ +#define PDMA_INT_TC (1UL << 3) /*!< PDMA channel transfer complete interrupt */ +#define PDMA_INT_TE (1UL << 4) /*!< PDMA channel transfer error interrupt */ + +#define IS_PDMA_INT(INT) (((INT & 0xFFFFFFE0) == 0) && (INT != 0)) +/** + * @} + */ + +/* Exported functions --------------------------------------------------------------------------------------*/ +/** @defgroup PDMA_Exported_Functions PDMA exported functions + * @{ + */ +void PDMA_DeInit(void); +void PDMA_Config(u32 PDMA_CHn, PDMACH_InitTypeDef *PDMACH_InitStruct); +void PDMA_AddrConfig(u32 PDMA_CHn, u32 SrcAddr, u32 DstAddr); +void PDMA_SrcAddrConfig(u32 PDMA_CHn, u32 SrcAddr); +void PDMA_DstAddrConfig(u32 PDMA_CHn, u32 DstAddr); +void PDMA_TranSizeConfig(u32 PDMA_CHn, u16 BlkCnt, u16 BlkLen); +void PDMA_EnaCmd(u32 PDMA_CHn, ControlStatus NewState); +void PDMA_SwTrigCmd(u32 PDMA_CHn, ControlStatus NewState); + +void PDMA_IntConfig(u32 PDMA_CHn, u32 PDMA_INT_x, ControlStatus NewState); +FlagStatus PDMA_GetFlagStatus(u32 PDMA_CHn, u32 PDMA_FLAG_x); +void PDMA_ClearFlag(u32 PDMA_CHn, u32 PDMA_FLAG_x); +u16 PDMA_GetRemainBlkCnt(u32 PDMA_CHn); +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f5xxxx_pwrcu.h b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f5xxxx_pwrcu.h new file mode 100644 index 0000000000..a98fb16289 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f5xxxx_pwrcu.h @@ -0,0 +1,376 @@ +/*********************************************************************************************************//** + * @file ht32f5xxxx_pwrcu.h + * @version $Rev:: 7054 $ + * @date $Date:: 2023-07-24 #$ + * @brief The header file of the Power Control Unit library. + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------------------------------------*/ +#ifndef __HT32F5XXXX_PWRCU_H +#define __HT32F5XXXX_PWRCU_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------------------------------------*/ +#include "ht32.h" + +/** @addtogroup HT32F5xxxx_Peripheral_Driver HT32F5xxxx Peripheral Driver + * @{ + */ + +/** @addtogroup PWRCU + * @{ + */ + + +/* Exported types ------------------------------------------------------------------------------------------*/ +/** @defgroup PWRCU_Exported_Types PWRCU exported types + * @{ + */ + +/** + * @brief Status of Power control unit + */ + +/** + * @brief Wakeup pin selection + */ +typedef enum +{ + PWRCU_WAKEUP_PIN_0 = 0, + #if (LIBCFG_PWRCU_WAKEUP1) + PWRCU_WAKEUP_PIN_1 + #endif +} PWRCU_WUP_Enum; +/** + * @brief Wakeup pin trigger type selection + */ +#if (LIBCFG_PWRCU_WAKEUP_V01) +typedef enum +{ + PWRCU_WUP_POSITIVE_EDGE = 0, /*!< Wakeup pin positive_edge triggered */ + PWRCU_WUP_NEGATIVE_EDGE, /*!< Wakeup pin negative_edge triggered */ + PWRCU_WUP_HIGH_LEVEL, /*!< Wakeup pin high-level sensitive */ + PWRCU_WUP_LOW_LEVEL, /*!< Wakeup pin low-level sensitive */ +} PWRCU_WUPTYPE_Enum; +#endif +typedef enum +{ + PWRCU_OK = 0, /*!< Ready for access or VDD power domain power-on reset is released */ + PWRCU_TIMEOUT, /*!< Time out */ + PWRCU_ERROR /*!< Error */ +} PWRCU_Status; +/** + * @brief DMOS status + */ +typedef enum +{ + PWRCU_DMOS_STS_ON = 0, /*!< DMOS on */ + PWRCU_DMOS_STS_OFF, /*!< DMOS off */ + PWRCU_DMOS_STS_OFF_BY_BODRESET /*!< DMOS off caused by brow out reset */ +} PWRCU_DMOSStatus; +/** + * @brief LVD level selection + */ +typedef enum +{ + PWRCU_LVDS_LV1 = 0x00000000, /*!< LVD level 1 */ + PWRCU_LVDS_LV2 = 0x00020000, /*!< LVD level 2 */ + PWRCU_LVDS_LV3 = 0x00040000, /*!< LVD level 3 */ + PWRCU_LVDS_LV4 = 0x00060000, /*!< LVD level 4 */ + PWRCU_LVDS_LV5 = 0x00400000, /*!< LVD level 5 */ + PWRCU_LVDS_LV6 = 0x00420000, /*!< LVD level 6 */ + PWRCU_LVDS_LV7 = 0x00440000, /*!< LVD level 7 */ + PWRCU_LVDS_LV8 = 0x00460000 /*!< LVD level 8 */ +} PWRCU_LVDS_Enum; +#if (LIBCFG_PWRCU_VDD_5V) + #define PWRCU_LVDS_2V65 PWRCU_LVDS_LV1 + #define PWRCU_LVDS_2V85 PWRCU_LVDS_LV2 + #define PWRCU_LVDS_3V05 PWRCU_LVDS_LV3 + #define PWRCU_LVDS_3V25 PWRCU_LVDS_LV4 + #define PWRCU_LVDS_3V45 PWRCU_LVDS_LV5 + #define PWRCU_LVDS_4V25 PWRCU_LVDS_LV6 + #define PWRCU_LVDS_4V45 PWRCU_LVDS_LV7 + #define PWRCU_LVDS_4V65 PWRCU_LVDS_LV8 +#elif (LIBCFG_PWRCU_VDD_2V0_3V6) + #define PWRCU_LVDS_2V25 PWRCU_LVDS_LV1 + #define PWRCU_LVDS_2V4 PWRCU_LVDS_LV2 + #define PWRCU_LVDS_2V55 PWRCU_LVDS_LV3 + #define PWRCU_LVDS_2V7 PWRCU_LVDS_LV4 + #define PWRCU_LVDS_2V85 PWRCU_LVDS_LV5 + #define PWRCU_LVDS_3V PWRCU_LVDS_LV6 + #define PWRCU_LVDS_3V15 PWRCU_LVDS_LV7 + #define PWRCU_LVDS_3V3 PWRCU_LVDS_LV8 +#else + #define PWRCU_LVDS_1V75 PWRCU_LVDS_LV1 + #define PWRCU_LVDS_1V95 PWRCU_LVDS_LV2 + #define PWRCU_LVDS_2V15 PWRCU_LVDS_LV3 + #define PWRCU_LVDS_2V35 PWRCU_LVDS_LV4 + #define PWRCU_LVDS_2V55 PWRCU_LVDS_LV5 + #define PWRCU_LVDS_2V75 PWRCU_LVDS_LV6 + #define PWRCU_LVDS_2V95 PWRCU_LVDS_LV7 + #define PWRCU_LVDS_3V15 PWRCU_LVDS_LV8 +#endif +/** + * @brief BOD reset or interrupt selection + */ +typedef enum +{ + PWRCU_BODRIS_RESET = 0, /*!< Reset the whole chip */ + PWRCU_BODRIS_INT = 1, /*!< Assert interrupt */ +} PWRCU_BODRIS_Enum; +/** + * @brief Sleep entry instruction selection + */ +typedef enum +{ + PWRCU_SLEEP_ENTRY_WFE = 0, /*!< Sleep then wait for event */ + PWRCU_SLEEP_ENTRY_WFI /*!< Sleep then wait for interrupt */ +} PWRCU_SLEEP_ENTRY_Enum; +#if (LIBCFG_BAKREG) +/** + * @brief Backup register selection + */ +typedef enum +{ + PWRCU_BAKREG_0 = 0, + PWRCU_BAKREG_1, + PWRCU_BAKREG_2, + PWRCU_BAKREG_3, + PWRCU_BAKREG_4, + PWRCU_BAKREG_5, + PWRCU_BAKREG_6, + PWRCU_BAKREG_7, + PWRCU_BAKREG_8, + PWRCU_BAKREG_9 +} PWRCU_BAKREG_Enum; +#endif +/** + * @brief Vdd15 power good source selection + */ +typedef enum +{ + PWRCU_V15RDYSC_V33ISO = 0, /*!< Vdd15 power good source come from BK_ISO bit in CKCU unit */ + PWRCU_V15RDYSC_V15POR /*!< Vdd15 power good source come from Vdd15 power on reset */ +} PWRCU_V15RDYSC_Enum; +/** + * @brief LDO operation mode selection + */ +typedef enum +{ + PWRCU_LDO_NORMAL = 0, /*!< The LDO is operated in normal current mode */ + PWRCU_LDO_LOWCURRENT /*!< The LDO is operated in low current mode */ +} PWRCU_LDOMODE_Enum; +#if defined(USE_HT32F52342_52) || defined(USE_HT32F5826) +/** + * @brief HSI ready counter bit length selection + */ +typedef enum +{ + PWRCU_HSIRCBL_4 = 0, /*!< 4 bits */ + PWRCU_HSIRCBL_5, /*!< 5 bits */ + PWRCU_HSIRCBL_6, /*!< 5 bits */ + PWRCU_HSIRCBL_7 /*!< 7 bits (Default) */ +} PWRCU_HSIRCBL_Enum; +#endif +#if (LIBCFG_PWRCU_VREG) +/** + * @brief VREG output voltage selection + */ +typedef enum +{ + #if (LIBCFG_PWRCU_VREG_2V5) + PWRCU_VREG_2V5 = 0x08000000, /*!< VREG output voltage is 2.5 V */ + #else + PWRCU_VREG_4V0 = 0x08000000, /*!< VREG output voltage is 4.0 V */ + #endif + PWRCU_VREG_3V3 = 0x00000000, /*!< VREG output voltage is 3.3 V */ + PWRCU_VREG_3V0 = 0x04000000, /*!< VREG output voltage is 3.0 V */ + PWRCU_VREG_1V8 = 0x0C000000, /*!< VREG output voltage is 1.8 V */ +} PWRCU_VREG_VOLT_Enum; +/** + * @brief VREG operation mode + */ +typedef enum +{ + PWRCU_VREG_DISABLE = 0x00000000, /*!< VREG is disabled */ + PWRCU_VREG_ENABLE = 0x01000000, /*!< VREG is enabled */ + PWRCU_VREG_BYPASS = 0x02000000, /*!< VREG is bypassed */ +} PWRCU_VREG_MODE_Enum; +#endif +/** + * @} + */ + +/* Exported constants --------------------------------------------------------------------------------------*/ +/** @defgroup PWRCU_Exported_Constants PWRCU exported constants + * @{ + */ + +/* Definitions of PWRCU_FLAG */ +#if (!LIBCFG_PWRCU_NO_VDDPORF) +#define PWRCU_FLAG_PWRPOR 0x0001 /*!< VDD power domain power-on reset flag */ +#endif +#if (!LIBCFG_PWRCU_NO_PDF) +#define PWRCU_FLAG_PD 0x0002 /*!< Power-Down flag */ +#endif +#if (LIBCFG_PWRCU_PORF) +#define PWRCU_FLAG_POR 0x0010 /*!< Power-on reset flag */ +#endif +#define PWRCU_FLAG_WUP 0x0100 /*!< External WAKEUP pin flag */ +#define PWRCU_FLAG_WUP0 0x0100 /*!< External WAKEUP0 pin flag */ +#if (LIBCFG_PWRCU_WAKEUP1) +#define PWRCU_FLAG_WUP1 0x0200 /*!< External WAKEUP1 pin flag */ +#endif + +/* check PWRCU_LVDS parameter */ +#define IS_PWRCU_LVDS(x) ((x == PWRCU_LVDS_LV1) || (x == PWRCU_LVDS_LV2) || \ + (x == PWRCU_LVDS_LV3) || (x == PWRCU_LVDS_LV4) || \ + (x == PWRCU_LVDS_LV5) || (x == PWRCU_LVDS_LV6) || \ + (x == PWRCU_LVDS_LV7) || (x == PWRCU_LVDS_LV8)) + +/* check PWRCU_BODRIS parameter */ +#define IS_PWRCU_BODRIS(x) ((x == PWRCU_BODRIS_RESET) || (x == PWRCU_BODRIS_INT)) + +/* check PWRCU_HSIRCBL parameter */ +#define IS_PWRCU_HSIRCBL(x) (x <= 3) + +/* check PWRCU_SLEEP_ENTRY parameter */ +#define IS_PWRCU_SLEEP_ENTRY(x) ((x == PWRCU_SLEEP_ENTRY_WFI) || (x == PWRCU_SLEEP_ENTRY_WFE)) + +/* check PWRCU_BAKREG parameter */ +#define IS_PWRCU_BAKREG(x) (x < 10) + +/* check PWRCU_V15RDY_SRC parameter */ +#define IS_PWRCU_V15RDYSC(x) ((x == PWRCU_V15RDYSC_V33ISO) || (x == PWRCU_V15RDYSC_V15POR)) + +/* check PWRCU_LDOMODE parameter */ +#define IS_PWRCU_LDOMODE(x) ((x == PWRCU_LDO_NORMAL) || (x == PWRCU_LDO_LOWCURRENT)) + +/* check PWRCU_WUP parameter */ +#define IS_PWRCU_WAKEUPPIN(x) (IS_PWRCU_WAKE0(x) || IS_PWRCU_WAKE1(x)) + +#define IS_PWRCU_WAKE0(x) (x == PWRCU_WAKEUP_PIN_0) + +#if (LIBCFG_PWRCU_WAKEUP1) +#define IS_PWRCU_WAKE1(x) (x == PWRCU_WAKEUP_PIN_1) +#else +#define IS_PWRCU_WAKE1(x) (0) +#endif + +/* check PWRCU_WUPTYPE parameter */ +#define IS_PWRCU_TRIGGERTYPE(x) ((x == PWRCU_WUP_POSITIVE_EDGE) || \ + (x == PWRCU_WUP_NEGATIVE_EDGE) || \ + (x == PWRCU_WUP_HIGH_LEVEL) || \ + (x == PWRCU_WUP_LOW_LEVEL)) + +#if (LIBCFG_PWRCU_VREG) +#define IS_PWRCU_VREG_VOLT(x) ((IS_PWRCU_VREG_VOLT_L2(x)) || \ + (x == PWRCU_VREG_3V3) || \ + (x == PWRCU_VREG_3V0) || \ + (x == PWRCU_VREG_1V8)) + +#if (LIBCFG_PWRCU_VREG_2V5) +#define IS_PWRCU_VREG_VOLT_L2(x) (x == PWRCU_VREG_2V5) +#else +#define IS_PWRCU_VREG_VOLT_L2(x) (x == PWRCU_VREG_4V0) +#endif + +#define IS_PWRCU_VREG_MODE(x) ((x == PWRCU_VREG_DISABLE) || \ + (x == PWRCU_VREG_ENABLE) || \ + (x == PWRCU_VREG_BYPASS)) + + +#endif + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------------------------------------*/ +/** @defgroup PWRCU_Exported_Functions PWRCU exported functions + * @{ + */ +void PWRCU_DeInit(void); +#if (!LIBCFG_NO_PWRCU_TEST_REG) +PWRCU_Status PWRCU_CheckReadyAccessed(void); +#endif +u16 PWRCU_GetFlagStatus(void); +#if (LIBCFG_BAKREG) +u32 PWRCU_ReadBackupRegister(PWRCU_BAKREG_Enum BAKREGx); +void PWRCU_WriteBackupRegister(PWRCU_BAKREG_Enum BAKREGx, u32 DATA); +#endif +void PWRCU_Sleep(PWRCU_SLEEP_ENTRY_Enum SleepEntry); +void PWRCU_DeepSleep1(PWRCU_SLEEP_ENTRY_Enum SleepEntry); +void PWRCU_DeepSleep2(PWRCU_SLEEP_ENTRY_Enum SleepEntry); +#if !defined(USE_HT32F52220_30) +void PWRCU_DeepSleep2Ex(PWRCU_SLEEP_ENTRY_Enum SleepEntry); +#endif +#if (!LIBCFG_PWRCU_NO_PD_MODE) +void PWRCU_PowerDown(void); +#endif +void PWRCU_SetLVDS(PWRCU_LVDS_Enum Level); +void PWRCU_LDOConfig(PWRCU_LDOMODE_Enum Sel); +void PWRCU_LVDCmd(ControlStatus NewState); +void PWRCU_BODCmd(ControlStatus NewState); +void PWRCU_BODRISConfig(PWRCU_BODRIS_Enum Selection); +FlagStatus PWRCU_GetLVDFlagStatus(void); +FlagStatus PWRCU_GetBODFlagStatus(void); +PWRCU_DMOSStatus PWRCU_GetDMOSStatus(void); +void PWRCU_DMOSCmd(ControlStatus NewState); +#if (LIBCFG_PWRCU_V15_READY_SOURCE) +void PWRCU_V15RDYSourceConfig(PWRCU_V15RDYSC_Enum Sel); +#endif +void PWRCU_LVDIntWakeupConfig(ControlStatus NewState); +void PWRCU_LVDEventWakeupConfig(ControlStatus NewState); +#if (LIBCFG_PWRCU_VREG) +void PWRCU_SetVREG(PWRCU_VREG_VOLT_Enum Volt); +void PWRCU_VREGConfig(PWRCU_VREG_MODE_Enum Mode); +#endif +void PWRCU_WakeupPinCmd(ControlStatus NewState); +#if (LIBCFG_PWRCU_WAKEUP_V01) +void PWRCU_WakeupMultiPinCmd(PWRCU_WUP_Enum Pin, PWRCU_WUPTYPE_Enum Type, ControlStatus NewState); +#endif +#if defined(USE_HT32F52342_52) || defined(USE_HT32F5826) +void PWRCU_HSIReadyCounterBitLengthConfig(PWRCU_HSIRCBL_Enum BitLength); +#endif +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f5xxxx_rstcu.h b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f5xxxx_rstcu.h new file mode 100644 index 0000000000..60eabde780 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f5xxxx_rstcu.h @@ -0,0 +1,238 @@ +/*********************************************************************************************************//** + * @file ht32f5xxxx_rstcu.h + * @version $Rev:: 7115 $ + * @date $Date:: 2023-08-11 #$ + * @brief The header file of the Reset Control Unit library. + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------------------------------------*/ +#ifndef __HT32F5XXXX_RSTCU_H +#define __HT32F5XXXX_RSTCU_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------------------------------------*/ +#include "ht32.h" + +/** @addtogroup HT32F5xxxx_Peripheral_Driver HT32F5xxxx Peripheral Driver + * @{ + */ + +/** @addtogroup RSTCU + * @{ + */ + + +/* Exported types ------------------------------------------------------------------------------------------*/ +/** @defgroup RSTCU_Exported_Types RSTCU exported types + * @{ + */ + +/** + * @brief Enumeration of Global reset status. + */ +typedef enum +{ + RSTCU_FLAG_SYSRST = 0, + RSTCU_FLAG_EXTRST, + RSTCU_FLAG_WDTRST, + RSTCU_FLAG_PORST +} RSTCU_RSTF_TypeDef; + +/** + * @brief Definition of initial structure of peripheral reset. + */ +typedef union +{ + struct + { + /* Definitions of AHB peripheral reset */ + unsigned long PDMA :1; // Bit 0 + unsigned long :1; // Bit 1 + unsigned long :1; // Bit 2 + unsigned long :1; // Bit 3 + unsigned long :1; // Bit 4 + unsigned long USBD :1; // Bit 5 + unsigned long EBI :1; // Bit 6 + unsigned long CRC :1; // Bit 7 + + unsigned long PA :1; // Bit 8 + unsigned long PB :1; // Bit 9 + unsigned long PC :1; // Bit 10 + unsigned long PD :1; // Bit 11 + unsigned long PE :1; // Bit 12 + unsigned long PF :1; // Bit 13 + unsigned long :1; // Bit 14 + unsigned long AES :1; // Bit 15 + + #ifdef USE_HT32F65230_40 + unsigned long DIV :1; // Bit 16 + #else + unsigned long :1; // Bit 16 + #endif + unsigned long :1; // Bit 17 + unsigned long :1; // Bit 18 + unsigned long :1; // Bit 19 + unsigned long :1; // Bit 20 + unsigned long :1; // Bit 21 + unsigned long :1; // Bit 22 + unsigned long :1; // Bit 23 + + #ifndef USE_HT32F65230_40 + unsigned long DIV :1; // Bit 24 + #else + unsigned long :1; // Bit 24 + #endif + unsigned long QSPI :1; // Bit 25 + unsigned long RF :1; // Bit 26 + unsigned long :1; // Bit 27 + unsigned long :1; // Bit 28 + unsigned long :1; // Bit 29 + unsigned long :1; // Bit 30 + unsigned long :1; // Bit 31 + + /* Definitions of APB peripheral 0 reset */ + unsigned long I2C0 :1; // Bit 0 + unsigned long I2C1 :1; // Bit 1 + unsigned long I2C2 :1; // Bit 2 + unsigned long :1; // Bit 3 + unsigned long SPI0 :1; // Bit 4 + unsigned long SPI1 :1; // Bit 5 + unsigned long :1; // Bit 6 + unsigned long :1; // Bit 7 + + unsigned long USART0 :1; // Bit 8 + unsigned long USART1 :1; // Bit 9 + unsigned long UART0 :1; // Bit 10 + unsigned long UART1 :1; // Bit 11 + unsigned long UART2 :1; // Bit 12 + unsigned long UART3 :1; // Bit 13 + unsigned long AFIO :1; // Bit 14 + unsigned long EXTI :1; // Bit 15 + + unsigned long :1; // Bit 16 + unsigned long :1; // Bit 17 + unsigned long :1; // Bit 18 + unsigned long :1; // Bit 19 + unsigned long :1; // Bit 20 + unsigned long :1; // Bit 21 + unsigned long SLED0 :1; // Bit 22 + unsigned long SLED1 :1; // Bit 23 + + unsigned long SCI0 :1; // Bit 24 + unsigned long I2S :1; // Bit 25 + unsigned long :1; // Bit 26 + unsigned long SCI1 :1; // Bit 27 + unsigned long MIDI :1; // Bit 28 + unsigned long LEDC :1; // Bit 29 + unsigned long CAN0 :1; // Bit 30 + unsigned long :1; // Bit 31 + + /* Definitions of APB peripheral 1 reset */ + unsigned long MCTM0 :1; // Bit 0 + unsigned long :1; // Bit 1 + unsigned long :1; // Bit 2 + unsigned long :1; // Bit 3 + unsigned long WDT :1; // Bit 4 + unsigned long :1; // Bit 5 + unsigned long :1; // Bit 6 + unsigned long DAC1 :1; // Bit 7 + + unsigned long GPTM0 :1; // Bit 8 + unsigned long GPTM1 :1; // Bit 9 + unsigned long :1; // Bit 10 + unsigned long :1; // Bit 11 + unsigned long PWM0 :1; // Bit 12 + unsigned long PWM1 :1; // Bit 13 + unsigned long PWM2 :1; // Bit 14 + unsigned long :1; // Bit 15 + + unsigned long BFTM0 :1; // Bit 16 + unsigned long BFTM1 :1; // Bit 17 + unsigned long TKEY :1; // Bit 18 + unsigned long LCD :1; // Bit 19 + unsigned long :1; // Bit 20 + unsigned long DAC0 :1; // Bit 21 + unsigned long CMP :1; // Bit 22 + unsigned long OPA :1; // Bit 23 + + unsigned long ADC0 :1; // Bit 24 + unsigned long ADC1 :1; // Bit 25 + unsigned long :1; // Bit 26 + unsigned long :1; // Bit 27 + unsigned long SCTM0 :1; // Bit 28 + unsigned long SCTM1 :1; // Bit 29 + unsigned long SCTM2 :1; // Bit 30 + unsigned long SCTM3 :1; // Bit 31 + } Bit; + u32 Reg[3]; +} RSTCU_PeripReset_TypeDef; + +/** + * @} + */ + + +/* Exported constants --------------------------------------------------------------------------------------*/ +/** @defgroup RSTCU_Exported_Constants RSTCU exported constants + * @{ + */ + +/* Other definitions */ +#define IS_RSTCU_FLAG(FLAG) ((FLAG == RSTCU_FLAG_SYSRST) || \ + (FLAG == RSTCU_FLAG_EXTRST) || \ + (FLAG == RSTCU_FLAG_WDTRST) || \ + (FLAG == RSTCU_FLAG_PORST)) +/** + * @} + */ + +/* Exported functions --------------------------------------------------------------------------------------*/ +/** @defgroup RSTCU_Exported_Functions RSTCU exported functions + * @{ + */ +FlagStatus RSTCU_GetResetFlagStatus(RSTCU_RSTF_TypeDef RSTCU_RSTF); +void RSTCU_ClearResetFlag(RSTCU_RSTF_TypeDef RSTCU_RSTF); +void RSTCU_ClearAllResetFlag(void); +void RSTCU_PeripReset(RSTCU_PeripReset_TypeDef Reset, ControlStatus Cmd); + +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f5xxxx_rtc.h b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f5xxxx_rtc.h new file mode 100644 index 0000000000..0677ae6717 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f5xxxx_rtc.h @@ -0,0 +1,255 @@ +/*********************************************************************************************************//** + * @file ht32f5xxxx_rtc.h + * @version $Rev:: 7278 $ + * @date $Date:: 2023-10-04 #$ + * @brief The header file of the RTC library. + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------------------------------------*/ +#ifndef __HT32F5XXXX_RTC_H +#define __HT32F5XXXX_RTC_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------------------------------------*/ +#include "ht32.h" + +/** @addtogroup HT32F5xxxx_Peripheral_Driver HT32F5xxxx Peripheral Driver + * @{ + */ + +/** @addtogroup RTC + * @{ + */ + + +/* Exported types ------------------------------------------------------------------------------------------*/ +/** @defgroup RTC_Exported_Types RTC exported types + * @{ + */ + +/** + * @brief Selection of RTC clock source + */ +typedef enum +{ + RTC_SRC_LSI = 0, /*!< Low speed internal clock, about 32 kHz */ + #if (LIBCFG_LSE) + RTC_SRC_LSE /*!< Low speed external 32768 Hz clock */ + #endif +} RTC_SRC_Enum; +/** + * @brief Selection of RTC LSE startup mode + */ +typedef enum +{ + RTC_LSESM_NORMAL = 0, /*!< Little power consumption but longer startup time. */ + RTC_LSESM_FAST /*!< Shortly startup time but higher power consumption. */ +} RTC_LSESM_Enum; +/** + * @brief Selection of RTC prescaler + */ +typedef enum +{ + RTC_RPRE_1 = 0x0000, /*!< CK_SECOND = CK_RTC */ + RTC_RPRE_2 = 0x0100, /*!< CK_SECOND = CK_RTC / 2 */ + RTC_RPRE_4 = 0x0200, /*!< CK_SECOND = CK_RTC / 4 */ + RTC_RPRE_8 = 0x0300, /*!< CK_SECOND = CK_RTC / 8 */ + RTC_RPRE_16 = 0x0400, /*!< CK_SECOND = CK_RTC / 16 */ + RTC_RPRE_32 = 0x0500, /*!< CK_SECOND = CK_RTC / 32 */ + RTC_RPRE_64 = 0x0600, /*!< CK_SECOND = CK_RTC / 64 */ + RTC_RPRE_128 = 0x0700, /*!< CK_SECOND = CK_RTC / 128 */ + RTC_RPRE_256 = 0x0800, /*!< CK_SECOND = CK_RTC / 256 */ + RTC_RPRE_512 = 0x0900, /*!< CK_SECOND = CK_RTC / 512 */ + RTC_RPRE_1024 = 0x0A00, /*!< CK_SECOND = CK_RTC / 1024 */ + RTC_RPRE_2048 = 0x0B00, /*!< CK_SECOND = CK_RTC / 2048 */ + RTC_RPRE_4096 = 0x0C00, /*!< CK_SECOND = CK_RTC / 4096 */ + RTC_RPRE_8192 = 0x0D00, /*!< CK_SECOND = CK_RTC / 8192 */ + RTC_RPRE_16384 = 0x0E00, /*!< CK_SECOND = CK_RTC / 16384 */ + RTC_RPRE_32768 = 0x0F00 /*!< CK_SECOND = CK_RTC / 32768 */ +} RTC_RPRE_Enum; +/** + * @brief Active polarity of RTC output + */ +typedef enum +{ + RTC_ROAP_HIGH = 0, /*!< Active level is high */ + RTC_ROAP_LOW /*!< Active level is low */ +} RTC_ROAP_Enum; +/** + * @brief Waveform mode of RTC output + */ +typedef enum +{ + RTC_ROWM_PULSE = 0, /*!< Pulse mode. */ + RTC_ROWM_LEVEL /*!< Level mode. */ +} RTC_ROWM_Enum; +/** + * @brief Waveform mode of RTC output + */ +typedef enum +{ + RTC_ROES_MATCH = 0, /*!< Selected RTC compare match. */ + RTC_ROES_SECOND /*!< Selected RTC second clock. */ +} RTC_ROES_Enum; +/** + * @} + */ + +/* Exported constants --------------------------------------------------------------------------------------*/ +/** @defgroup RTC_Exported_Constants RTC exported constants + * @{ + */ + +/** @defgroup RTC_WAKEUP Selection of RTC wakeup source + * @{ + */ +#define RTC_WAKEUP_CSEC 0x00000100 +#define RTC_WAKEUP_CM 0x00000200 +#define RTC_WAKEUP_OV 0x00000400 +/** + * @} + */ + +/** @defgroup RTC_IT RTC Selection of interrupt source + * @{ + */ +#define RTC_INT_CSEC 0x00000001 +#define RTC_INT_CM 0x00000002 +#define RTC_INT_OV 0x00000004 +/** + * @} + */ + +/** @defgroup RTC_FLAG RTC Definitions of flags + * @{ + */ +#define RTC_FLAG_CSEC 0x00000001 +#define RTC_FLAG_CM 0x00000002 +#define RTC_FLAG_OV 0x00000004 +/** + * @} + */ + +/** @defgroup RTC_Check_Parameter Selection of Vdd18 power good + * @{ + */ + +/** + * @brief Used to check RTC_SRC_Enum parameter + */ +#if (LIBCFG_LSE) +#define IS_RTC_SRC_LSE(x) (x == RTC_SRC_LSE) +#else +#define IS_RTC_SRC_LSE(x) (0) +#endif +#define IS_RTC_SRC(x) ((x == RTC_SRC_LSI) || IS_RTC_SRC_LSE(x)) +/** + * @brief Used to check RTC_LSESM_Enum parameter + */ +#define IS_RTC_LSESM(x) ((x == RTC_LSESM_NORMAL) || (x == RTC_LSESM_FAST)) +/** + * @brief Used to check RTC_RPRE_Enum parameter + */ +#define IS_RTC_PSC(x) ((x == RTC_RPRE_1) || (x == RTC_RPRE_2) || (x == RTC_RPRE_4) ||\ + (x == RTC_RPRE_8) || (x == RTC_RPRE_16) || (x == RTC_RPRE_32) ||\ + (x == RTC_RPRE_64) || (x == RTC_RPRE_128) || (x == RTC_RPRE_256) ||\ + (x == RTC_RPRE_512) || (x == RTC_RPRE_1024) || (x == RTC_RPRE_2048) ||\ + (x == RTC_RPRE_4096) || (x == RTC_RPRE_8192) || (x == RTC_RPRE_16384) ||\ + (x == RTC_RPRE_32768)) +/** + * @brief Used to check RTC_ROAP_Enum parameter + */ +#define IS_RTC_ROAP(x) ((x == RTC_ROAP_HIGH) || (x == RTC_ROAP_LOW)) +/** + * @brief Used to check RTC_ROWM_Enum parameter + */ +#define IS_RTC_ROWM(x) ((x == RTC_ROWM_PULSE) || (x == RTC_ROWM_LEVEL)) +/** + * @brief Used to check RTC_ROES_Enum parameter + */ +#define IS_RTC_ROES(x) ((x == RTC_ROES_MATCH) || (x == RTC_ROES_SECOND)) +/** + * @brief Used to check RTC_WAKEUP parameter + */ +#define IS_RTC_WAKEUP(x) ((((x) & (u32)0xFFFFF8FF) == 0x00) && ((x) != 0x00)) +/** + * @brief Used to check RTC_INT parameter + */ +#define IS_RTC_INT(x) ((((x) & (u32)0xFFFFFFF8) == 0x00) && ((x) != 0x00)) +/** + * @brief Used to check RTC_FLAG parameter + */ +#define IS_RTC_FLAG(x) ((((x) & (u32)0xFFFFFFF8) == 0x00) && ((x) != 0x00)) +/** + * @} + */ + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------------------------------------*/ +/** @defgroup RTC_Exported_Functions RTC exported functions + * @{ + */ +void RTC_DeInit(void); +void RTC_ClockSourceConfig(RTC_SRC_Enum Source); +#if (LIBCFG_RTC_LSI_LOAD_TRIM) +void RTC_LSILoadTrimData(void); +#endif +void RTC_LSESMConfig(RTC_LSESM_Enum Mode); +void RTC_LSECmd(ControlStatus NewState); +void RTC_CMPCLRCmd(ControlStatus NewState); +void RTC_SetPrescaler(RTC_RPRE_Enum Psc); +u16 RTC_GetPrescaler(void); +void RTC_Cmd(ControlStatus NewState); +u32 RTC_GetCounter(void); +void RTC_SetCompare(u32 Compare); +u32 RTC_GetCompare(void); +void RTC_WakeupConfig(u32 RTC_WAKEUP, ControlStatus NewState); +void RTC_IntConfig(u32 RTC_INT, ControlStatus NewState); +u8 RTC_GetFlagStatus(void); +void RTC_OutConfig(RTC_ROWM_Enum WMode, RTC_ROES_Enum EventSel, RTC_ROAP_Enum Pol); +void RTC_OutCmd(ControlStatus NewState); +FlagStatus RTC_GetOutStatus(void); +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f5xxxx_sci.h b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f5xxxx_sci.h new file mode 100644 index 0000000000..b95ff72343 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f5xxxx_sci.h @@ -0,0 +1,280 @@ +/*********************************************************************************************************//** + * @file ht32f5xxxx_sci.h + * @version $Rev:: 6386 $ + * @date $Date:: 2022-10-27 #$ + * @brief The header file of the SCI library. + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------------------------------------*/ +#ifndef __HT32F5XXXX_SCI_H +#define __HT32F5XXXX_SCI_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------------------------------------*/ +#include "ht32.h" + +/** @addtogroup HT32F5xxxx_Peripheral_Driver HT32F5xxxx Peripheral Driver + * @{ + */ + +/** @addtogroup SCI + * @{ + */ + + +/* Exported types ------------------------------------------------------------------------------------------*/ +/** @defgroup SCI_Exported_Types SCI exported types + * @{ + */ +typedef struct +{ + u32 SCI_Mode; + u32 SCI_Retry; + u32 SCI_Convention; + u32 SCI_CardPolarity; + u32 SCI_ClockPrescale; +} SCI_InitTypeDef; +/** + * @} + */ + +/* Exported constants --------------------------------------------------------------------------------------*/ +/** @defgroup SCI_Exported_Constants SCI exported constants + * @{ + */ +#define SCI_MODE_MANUAL ((u32)0x00000000) +#define SCI_MODE_SCI ((u32)0x00000008) + +#define IS_SCI_MODE(MODE) ((MODE == SCI_MODE_MANUAL) || \ + (MODE == SCI_MODE_SCI)) + + +#define SCI_RETRY_NO ((u32)0x00000000) +#define SCI_RETRY_4 ((u32)0x00000012) +#define SCI_RETRY_5 ((u32)0x00000002) + +#define IS_SCI_RETRY(RETRY) ((RETRY == SCI_RETRY_NO) || \ + (RETRY == SCI_RETRY_4) || \ + (RETRY == SCI_RETRY_5)) + + +#define SCI_CONVENTION_DIRECT ((u32)0x00000000) +#define SCI_CONVENTION_INVERSE ((u32)0x00000001) + +#define IS_SCI_CONVENTION(CONVENTION) ((CONVENTION == SCI_CONVENTION_DIRECT) || \ + (CONVENTION == SCI_CONVENTION_INVERSE)) + + +#define SCI_CARDPOLARITY_LOW ((u32)0x00000000) +#define SCI_CARDPOLARITY_HIGH ((u32)0x00000040) + +#define IS_SCI_CARD_POLARITY(POLARITY) ((POLARITY == SCI_CARDPOLARITY_LOW) || \ + (POLARITY == SCI_CARDPOLARITY_HIGH)) + + +#define SCI_CLKPRESCALER_1 ((u32)0x00000000) +#define SCI_CLKPRESCALER_2 ((u32)0x00000001) +#define SCI_CLKPRESCALER_4 ((u32)0x00000002) +#define SCI_CLKPRESCALER_6 ((u32)0x00000003) +#define SCI_CLKPRESCALER_8 ((u32)0x00000004) +#define SCI_CLKPRESCALER_10 ((u32)0x00000005) +#define SCI_CLKPRESCALER_12 ((u32)0x00000006) +#define SCI_CLKPRESCALER_14 ((u32)0x00000007) +#define SCI_CLKPRESCALER_16 ((u32)0x00000008) +#define SCI_CLKPRESCALER_18 ((u32)0x00000009) +#define SCI_CLKPRESCALER_20 ((u32)0x0000000A) +#define SCI_CLKPRESCALER_22 ((u32)0x0000000B) +#define SCI_CLKPRESCALER_24 ((u32)0x0000000C) +#define SCI_CLKPRESCALER_26 ((u32)0x0000000D) +#define SCI_CLKPRESCALER_28 ((u32)0x0000000E) +#define SCI_CLKPRESCALER_30 ((u32)0x0000000F) +#define SCI_CLKPRESCALER_32 ((u32)0x00000010) +#define SCI_CLKPRESCALER_34 ((u32)0x00000011) +#define SCI_CLKPRESCALER_36 ((u32)0x00000012) +#define SCI_CLKPRESCALER_38 ((u32)0x00000013) +#define SCI_CLKPRESCALER_40 ((u32)0x00000014) +#define SCI_CLKPRESCALER_42 ((u32)0x00000015) +#define SCI_CLKPRESCALER_44 ((u32)0x00000016) +#define SCI_CLKPRESCALER_46 ((u32)0x00000017) +#define SCI_CLKPRESCALER_48 ((u32)0x00000018) +#define SCI_CLKPRESCALER_50 ((u32)0x00000019) +#define SCI_CLKPRESCALER_52 ((u32)0x0000001A) +#define SCI_CLKPRESCALER_54 ((u32)0x0000001B) +#define SCI_CLKPRESCALER_56 ((u32)0x0000001C) +#define SCI_CLKPRESCALER_58 ((u32)0x0000001D) +#define SCI_CLKPRESCALER_60 ((u32)0x0000001E) +#define SCI_CLKPRESCALER_62 ((u32)0x0000001F) +#define SCI_CLKPRESCALER_64 ((u32)0x00000020) +#define SCI_CLKPRESCALER_66 ((u32)0x00000021) +#define SCI_CLKPRESCALER_68 ((u32)0x00000022) +#define SCI_CLKPRESCALER_70 ((u32)0x00000023) +#define SCI_CLKPRESCALER_72 ((u32)0x00000024) +#define SCI_CLKPRESCALER_74 ((u32)0x00000025) +#define SCI_CLKPRESCALER_76 ((u32)0x00000026) +#define SCI_CLKPRESCALER_78 ((u32)0x00000027) +#define SCI_CLKPRESCALER_80 ((u32)0x00000028) +#define SCI_CLKPRESCALER_82 ((u32)0x00000029) +#define SCI_CLKPRESCALER_84 ((u32)0x0000002A) +#define SCI_CLKPRESCALER_86 ((u32)0x0000002B) +#define SCI_CLKPRESCALER_88 ((u32)0x0000002C) +#define SCI_CLKPRESCALER_90 ((u32)0x0000002D) +#define SCI_CLKPRESCALER_92 ((u32)0x0000002E) +#define SCI_CLKPRESCALER_94 ((u32)0x0000002F) +#define SCI_CLKPRESCALER_96 ((u32)0x00000030) +#define SCI_CLKPRESCALER_98 ((u32)0x00000031) +#define SCI_CLKPRESCALER_100 ((u32)0x00000032) +#define SCI_CLKPRESCALER_102 ((u32)0x00000033) +#define SCI_CLKPRESCALER_104 ((u32)0x00000034) +#define SCI_CLKPRESCALER_106 ((u32)0x00000035) +#define SCI_CLKPRESCALER_108 ((u32)0x00000036) +#define SCI_CLKPRESCALER_110 ((u32)0x00000037) +#define SCI_CLKPRESCALER_112 ((u32)0x00000038) +#define SCI_CLKPRESCALER_114 ((u32)0x00000039) +#define SCI_CLKPRESCALER_116 ((u32)0x0000003A) +#define SCI_CLKPRESCALER_118 ((u32)0x0000003B) +#define SCI_CLKPRESCALER_120 ((u32)0x0000003C) +#define SCI_CLKPRESCALER_122 ((u32)0x0000003D) +#define SCI_CLKPRESCALER_124 ((u32)0x0000003E) +#define SCI_CLKPRESCALER_126 ((u32)0x0000003F) + +#define IS_SCI_CLOCK_PRESCALER(PRESCALER) (PRESCALER <= 0x3F) + + +#define SCI_COMPENSATION_ENABLE ((u32)0x00008000) +#define SCI_COMPENSATION_DISABLE ((u32)0x00000000) + +#define IS_SCI_ETU_COMPENSATION(COMPENSATION) ((COMPENSATION == SCI_COMPENSATION_ENABLE) || \ + (COMPENSATION == SCI_COMPENSATION_DISABLE)) + + +#define SCI_CLK_HARDWARE ((u32)0x00000080) +#define SCI_CLK_SOFTWARE ((u32)0xFFFFFF7F) + +#define IS_SCI_CLK_MODE(MODE) ((MODE == SCI_CLK_HARDWARE) || \ + (MODE == SCI_CLK_SOFTWARE)) + + +#define SCI_CLK_HIGH ((u32)0x00000004) +#define SCI_CLK_LOW ((u32)0xFFFFFFFB) + +#define IS_SCI_CLK(CLK) ((CLK == SCI_CLK_HIGH) || \ + (CLK == SCI_CLK_LOW)) + + +#define SCI_DIO_HIGH ((u32)0x00000008) +#define SCI_DIO_LOW ((u32)0xFFFFFFF7) + +#define IS_SCI_DIO(DIO) ((DIO == SCI_DIO_HIGH) || \ + (DIO == SCI_DIO_LOW)) + + +#define SCI_INT_PAR ((u32)0x00000001) +#define SCI_INT_RXC ((u32)0x00000002) +#define SCI_INT_TXC ((u32)0x00000004) +#define SCI_INT_WT ((u32)0x00000008) +#define SCI_INT_CARD ((u32)0x00000040) +#define SCI_INT_TXBE ((u32)0x00000080) +#define SCI_INT_ALL ((u32)0x000000CF) + +#define IS_SCI_INT(INT) (((INT & 0xFFFFFF30) == 0x0) && (INT != 0)) + + + +#define SCI_FLAG_PAR ((u32)0x00000001) +#define SCI_FLAG_RXC ((u32)0x00000002) +#define SCI_FLAG_TXC ((u32)0x00000004) +#define SCI_FLAG_WT ((u32)0x00000008) +#define SCI_FLAG_CARD ((u32)0x00000040) +#define SCI_FLAG_TXBE ((u32)0x00000080) + +#define IS_SCI_FLAG(FLAG) ((FLAG == SCI_FLAG_PAR) || \ + (FLAG == SCI_FLAG_RXC) || \ + (FLAG == SCI_FLAG_TXC) || \ + (FLAG == SCI_FLAG_WT) || \ + (FLAG == SCI_FLAG_CARD) || \ + (FLAG == SCI_FLAG_TXBE)) + +#define IS_SCI_CLEAR_FLAG(FLAG) ((FLAG == SCI_FLAG_PAR) || \ + (FLAG == SCI_FLAG_TXC) || \ + (FLAG == SCI_FLAG_WT)) + + +#define SCI_PDMAREQ_TX ((u32)0x00000100) +#define SCI_PDMAREQ_RX ((u32)0x00000200) + +#define IS_SCI_PDMA_REQ(REQ) (((REQ & 0xFFFFFCFF) == 0x0) && (REQ != 0)) + + +#define IS_SCI_ETU(ETU) ((ETU >= 12) & (ETU <= 2047)) + +#define IS_SCI_GUARDTIME(GUARDTIME) ((GUARDTIME >= 11) & (GUARDTIME <= 511)) + +#define IS_SCI_WAITING_TIME(TIME) ((TIME >= 372) & (TIME <= 16777215)) +/** + * @} + */ + +/* Exported functions --------------------------------------------------------------------------------------*/ +/** @defgroup SCI_Exported_Functions SCI exported functions + * @{ + */ +void SCI_DeInit(HT_SCI_TypeDef* SCIx); +void SCI_Init(HT_SCI_TypeDef* SCIx, SCI_InitTypeDef* SCI_InitStruct); +void SCI_StructInit(SCI_InitTypeDef* SCI_InitStruct); +void SCI_Cmd(HT_SCI_TypeDef* SCIx, ControlStatus NewState); +void SCI_ETUConfig(HT_SCI_TypeDef* SCIx, u32 SCI_ETU, u32 SCI_Compensation); +void SCI_SetGuardTimeValue(HT_SCI_TypeDef* SCIx, u16 SCI_GuardTime); +void SCI_SetWaitingTimeValue(HT_SCI_TypeDef* SCIx, u32 SCI_WaitingTime); +void SCI_WaitingTimeCounterCmd(HT_SCI_TypeDef* SCIx, ControlStatus NewState); +void SCI_SendData(HT_SCI_TypeDef* SCIx, u8 SCI_Data); +u8 SCI_ReceiveData(HT_SCI_TypeDef* SCIx); +void SCI_ClockModeConfig(HT_SCI_TypeDef* SCIx, u32 SCI_CLKMode); +void SCI_SoftwareClockCmd(HT_SCI_TypeDef* SCIx, u32 SCI_CLK); +void SCI_OutputDIO(HT_SCI_TypeDef* SCIx, u32 SCI_DIO); +void SCI_IntConfig(HT_SCI_TypeDef* SCIx, u32 SCI_Int, ControlStatus NewState); +FlagStatus SCI_GetFlagStatus(HT_SCI_TypeDef* SCIx, u32 SCI_Flag); +void SCI_ClearFlag(HT_SCI_TypeDef* SCIx, u32 SCI_Flag); +#if (LIBCFG_PDMA) +void SCI_PDMACmd(HT_SCI_TypeDef* SCIx, u32 SCI_PDMAREQ, ControlStatus NewState); +#endif +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f5xxxx_sled.h b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f5xxxx_sled.h new file mode 100644 index 0000000000..15a57294ca --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f5xxxx_sled.h @@ -0,0 +1,157 @@ +/*********************************************************************************************************//** + * @file ht32f5xxxx_sled.h + * @version $Rev:: 3875 $ + * @date $Date:: 2019-05-10 #$ + * @brief The header file of the SLED library. + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------------------------------------*/ +#ifndef __HT32F5XXXX_SLED_H +#define __HT32F5XXXX_SLED_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------------------------------------*/ +#include "ht32.h" + +/** @addtogroup HT32F5xxxx_Peripheral_Driver HT32F5xxxx Peripheral Driver + * @{ + */ + +/** @addtogroup SLED + * @{ + */ + + +/* Exported types ------------------------------------------------------------------------------------------*/ +/** @defgroup SLED_Exported_Types SLED exported types + * @{ + */ + +/** + * @brief Enumeration of CK_SLED prescaler. + */ +typedef enum +{ + SLED_CLKPRE_DIV1 = 0, + SLED_CLKPRE_DIV2, + SLED_CLKPRE_DIV4, + SLED_CLKPRE_DIV3 +} SLED_CLKPRE_TypeDef; + +/** + * @brief Definition of SLED Init Structure. + */ +typedef struct +{ + u8 ClockPrescaler; + u8 BaudRate; + u8 T0H; + u8 T1H; + u8 TRST; + u8 SyncState; + u8 IdleState; + u8 ResetState; + u8 SyncMode; + u8 OutputPolarity; +} SLED_InitTypeDef; +/** + * @} + */ + +/* Exported constants --------------------------------------------------------------------------------------*/ +/** @defgroup SLED_Exported_Constants SLED exported constants + * @{ + */ +#define SLED_SYNC_STATE_T0 (0) +#define SLED_SYNC_STATE_T1 (1) + +#define SLED_IDLE_STATE_LOW (0) +#define SLED_IDLE_STATE_HIGH (1) + +#define SLED_RESET_STATE_LOW (0) +#define SLED_RESET_STATE_HIGH (1) + +#define SLED_SYNC_MODE_DISABLE (0) +#define SLED_SYNC_MODE_ENABLE (1) + +#define SLED_OUTPUT_NONINVERTING (0) +#define SLED_OUTPUT_INVERTING (1) + +#define SLED_FIFO_LEVEL_0 (0 << 6) +#define SLED_FIFO_LEVEL_1 (1 << 6) +#define SLED_FIFO_LEVEL_2 (2 << 6) +#define SLED_FIFO_LEVEL_3 (3 << 6) + +#define IS_SLED_FIFO_LEVEL(LEVEL) ((LEVEL == SLED_FIFO_LEVEL_0) || \ + (LEVEL == SLED_FIFO_LEVEL_1) || \ + (LEVEL == SLED_FIFO_LEVEL_2) || \ + (LEVEL == SLED_FIFO_LEVEL_3)) + +#define IS_SLED(SLED) ((SLED == HT_SLED0) || (SLED == HT_SLED1)) +/** + * @} + */ + +/* Exported functions --------------------------------------------------------------------------------------*/ +/** @defgroup SLED_Exported_Functions SLED exported functions + * @{ + */ +void SLED_DeInit(HT_SLED_TypeDef* SLEDx); +void SLED_Init(HT_SLED_TypeDef* SLEDx, SLED_InitTypeDef* SLED_InitStruct); + +void SLED_Cmd(HT_SLED_TypeDef* SLEDx, ControlStatus NewState); +void SLED_OutputCmd(HT_SLED_TypeDef* SLEDx, ControlStatus NewState); +void SLED_PDMACmd(HT_SLED_TypeDef* SLEDx, ControlStatus NewState); + +void SLED_IntCmd(HT_SLED_TypeDef* SLEDx, ControlStatus NewState); +void SLED_ClearIntFlag(HT_SLED_TypeDef* SLEDx); + +void SLED_InsertResetCode(HT_SLED_TypeDef* SLEDx); +FlagStatus SLED_GetResetCodeStatus(HT_SLED_TypeDef* SLEDx); + +FlagStatus SLED_GetBusyStatus(HT_SLED_TypeDef* SLEDx); + +void SLED_FIFOTrigLevelConfig(HT_SLED_TypeDef* SLEDx, u8 FifoLevel); +u8 SLED_GetFIFOStatus(HT_SLED_TypeDef* SLEDx); +void SLED_FIFOReset(HT_SLED_TypeDef* SLEDx); +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f5xxxx_spi.h b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f5xxxx_spi.h new file mode 100644 index 0000000000..b92fb0d006 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f5xxxx_spi.h @@ -0,0 +1,375 @@ +/*********************************************************************************************************//** + * @file ht32f5xxxx_spi.h + * @version $Rev:: 6386 $ + * @date $Date:: 2022-10-27 #$ + * @brief The header file of the SPI library. + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------------------------------------*/ +#ifndef __HT32F5XXXX_SPI_H +#define __HT32F5XXXX_SPI_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------------------------------------*/ +#include "ht32.h" + +/** @addtogroup HT32F5xxxx_Peripheral_Driver HT32F5xxxx Peripheral Driver + * @{ + */ + +/** @addtogroup SPI + * @{ + */ + + +#if (LIBCFG_MIDI) +#include "ht32f5xxxx_spi_midi.h" +#endif + +/* Exported types ------------------------------------------------------------------------------------------*/ +/** @defgroup SPI_Exported_Types SPI exported types + * @{ + */ + +#if (LIBCFG_SPI_DATA_LENGTH_V01) +typedef u8 SPI_DataTypeDef; +#else +typedef u16 SPI_DataTypeDef; +#endif + +#if (LIBCFG_SPI_TIMEOUT_LENGTH_V01) +typedef u8 SPI_TimeoutTypeDef; +#else +typedef u16 SPI_TimeoutTypeDef; +#endif + +typedef struct +{ + u32 SPI_Mode; + u32 SPI_FIFO; + u32 SPI_DataLength; + u32 SPI_SELMode; + u32 SPI_SELPolarity; + u32 SPI_CPOL; + u32 SPI_CPHA; + u32 SPI_FirstBit; + u32 SPI_RxFIFOTriggerLevel; + u32 SPI_TxFIFOTriggerLevel; + u32 SPI_ClockPrescaler; +} SPI_InitTypeDef; + +/** + * @brief Enumeration of SIO direction. + */ +#if (LIBCFG_QSPI) +typedef enum +{ + SIO_DIR_IN = 0, /*!< input mode */ + SIO_DIR_OUT /*!< output mode */ +} SIO_DIR_Enum; +#endif +/** + * @} + */ + +/* Exported constants --------------------------------------------------------------------------------------*/ +/** @defgroup SPI_Exported_Constants SPI exported constants + * @{ + */ +#define SPI_FIFO_ENABLE ((u32)0x00000400) +#define SPI_FIFO_DISABLE ((u32)0x00000000) + +#define IS_SPI_FIFO_SET(FIFO) ((FIFO == SPI_FIFO_ENABLE) || \ + (FIFO == SPI_FIFO_DISABLE)) + +#define SPI_DATALENGTH_1 ((u32)0x00000001) +#define SPI_DATALENGTH_2 ((u32)0x00000002) +#define SPI_DATALENGTH_3 ((u32)0x00000003) +#define SPI_DATALENGTH_4 ((u32)0x00000004) +#define SPI_DATALENGTH_5 ((u32)0x00000005) +#define SPI_DATALENGTH_6 ((u32)0x00000006) +#define SPI_DATALENGTH_7 ((u32)0x00000007) + +#if (LIBCFG_SPI_DATA_LENGTH_V01) +#define SPI_DATALENGTH_8 ((u32)0x00000000) + +#define IS_SPI_DATALENGTH(DATALENGTH) ((DATALENGTH <= 0x07)) +#else +#define SPI_DATALENGTH_8 ((u32)0x00000008) +#define SPI_DATALENGTH_9 ((u32)0x00000009) +#define SPI_DATALENGTH_10 ((u32)0x0000000A) +#define SPI_DATALENGTH_11 ((u32)0x0000000B) +#define SPI_DATALENGTH_12 ((u32)0x0000000C) +#define SPI_DATALENGTH_13 ((u32)0x0000000D) +#define SPI_DATALENGTH_14 ((u32)0x0000000E) +#define SPI_DATALENGTH_15 ((u32)0x0000000F) +#define SPI_DATALENGTH_16 ((u32)0x00000000) + +#define IS_SPI_DATALENGTH(DATALENGTH) ((DATALENGTH <= 0xF)) +#endif + +#define SPI_MASTER ((u32)0x00004000) +#define SPI_SLAVE ((u32)0x00000000) + +#define IS_SPI_MODE(MODE) ((MODE == SPI_MASTER) || \ + (MODE == SPI_SLAVE)) + + +#define SPI_SEL_HARDWARE ((u32)0x00002000) +#define SPI_SEL_SOFTWARE ((u32)0x00000000) + +#define IS_SPI_SEL_MODE(SELMODE) ((SELMODE == SPI_SEL_HARDWARE) || \ + (SELMODE == SPI_SEL_SOFTWARE)) + + +#define SPI_SEL_ACTIVE ((u32)0x00000010) +#define SPI_SEL_INACTIVE ((u32)0xFFFFFFEF) + +#define IS_SPI_SOFTWARE_SEL(SEL) ((SEL == SPI_SEL_ACTIVE) || \ + (SEL == SPI_SEL_INACTIVE)) + + +#define SPI_SELPOLARITY_HIGH ((u32)0x00000800) +#define SPI_SELPOLARITY_LOW ((u32)0x00000000) + +#define IS_SPI_SEL_POLARITY(POLARITY) ((POLARITY == SPI_SELPOLARITY_HIGH) || \ + (POLARITY == SPI_SELPOLARITY_LOW)) + + +#define SPI_CPOL_HIGH ((u32)0x00000400) +#define SPI_CPOL_LOW ((u32)0x00000000) + +#define IS_SPI_CPOL(CPOL) ((CPOL == SPI_CPOL_HIGH) || \ + (CPOL == SPI_CPOL_LOW)) + + +#define SPI_CPHA_FIRST ((u32)0x00000000) +#define SPI_CPHA_SECOND ((u32)0x00000001) + +#define IS_SPI_CPHA(CPHA) ((CPHA == SPI_CPHA_FIRST) || \ + (CPHA == SPI_CPHA_SECOND)) + + +#define SPI_FIRSTBIT_LSB ((u32)0x00001000) +#define SPI_FIRSTBIT_MSB ((u32)0x00000000) + +#define IS_SPI_FIRST_BIT(BIT) ((BIT == SPI_FIRSTBIT_LSB) || \ + (BIT == SPI_FIRSTBIT_MSB)) + + +#define SPI_FLAG_TXBE ((u32)0x00000001) +#define SPI_FLAG_TXE ((u32)0x00000002) +#define SPI_FLAG_RXBNE ((u32)0x00000004) +#define SPI_FLAG_WC ((u32)0x00000008) +#define SPI_FLAG_RO ((u32)0x00000010) +#if (LIBCFG_SPI_NO_MULTI_MASTER) +#define IS_FLAG_MF(x) (0) +#else +#define SPI_FLAG_MF ((u32)0x00000020) +#define IS_FLAG_MF(x) (x == SPI_FLAG_MF) +#endif +#define SPI_FLAG_SA ((u32)0x00000040) +#define SPI_FLAG_TOUT ((u32)0x00000080) +#define SPI_FLAG_BUSY ((u32)0x00000100) + +#define IS_SPI_FLAG(FLAG) ((FLAG == SPI_FLAG_TXBE) || \ + (FLAG == SPI_FLAG_TXE) || \ + (FLAG == SPI_FLAG_RXBNE) || \ + (FLAG == SPI_FLAG_WC) || \ + (FLAG == SPI_FLAG_RO) || \ + IS_FLAG_MF(FLAG) || \ + (FLAG == SPI_FLAG_SA) || \ + (FLAG == SPI_FLAG_TOUT) || \ + (FLAG == SPI_FLAG_BUSY)) + +#define IS_SPI_FLAG_CLEAR(CLEAR) ((CLEAR == SPI_FLAG_WC) || \ + (CLEAR == SPI_FLAG_RO) || \ + IS_FLAG_MF(CLEAR) || \ + (CLEAR == SPI_FLAG_SA) || \ + (CLEAR == SPI_FLAG_TOUT)) + + +#define SPI_INT_TXBE ((u32)0x00000001) +#define SPI_INT_TXE ((u32)0x00000002) +#define SPI_INT_RXBNE ((u32)0x00000004) +#define SPI_INT_WC ((u32)0x00000008) +#define SPI_INT_RO ((u32)0x00000010) +#if (!LIBCFG_SPI_NO_MULTI_MASTER) +#define SPI_INT_MF ((u32)0x00000020) +#endif +#define SPI_INT_SA ((u32)0x00000040) +#define SPI_INT_TOUT ((u32)0x00000080) +#if (LIBCFG_SPI_NO_MULTI_MASTER) +#define SPI_INT_ALL ((u32)0x000000DF) +#else +#define SPI_INT_ALL ((u32)0x000000FF) +#endif + +#define IS_SPI_INT(SPI_INT) (((SPI_INT & 0xFFFFFF00) == 0x0) && (SPI_INT != 0x0)) + + + +#define SPI_FIFO_TX ((u32)0x00000100) +#define SPI_FIFO_RX ((u32)0x00000200) + +#define IS_SPI_FIFO_DIRECTION(DIRECTION) (((DIRECTION & 0xFFFFFCFF) == 0) && (DIRECTION != 0)) + + +#if (LIBCFG_PDMA) +#define SPI_PDMAREQ_TX ((u32)0x00000002) +#define SPI_PDMAREQ_RX ((u32)0x00000004) + +#define IS_SPI_PDMA_REQ(REQ) (((REQ & 0xFFFFFFF9) == 0x0) && (REQ != 0x0)) +#endif + +/* Check parameter of the SIOx input/output direction */ +#if (LIBCFG_QSPI) +#define IS_SIO_DIR(x) (((x) == SIO_DIR_IN) || ((x) == SIO_DIR_OUT)) +#endif + +#define IS_SPI(x) (IS_SPI0(x) || IS_SPI1(x)) +#define IS_SPI0(x) (x == HT_SPI0) +#if (LIBCFG_SPI1) +#define IS_SPI1(x) (x == HT_SPI1) +#else +#define IS_SPI1(x) (0) +#endif +#if (LIBCFG_QSPI) +#define IS_QSPI(x) (x == HT_QSPI) +#else +#define IS_QSPI(x) (0) +#endif + +#if (LIBCFG_SPI_DATA_LENGTH_V01) +#define IS_SPI_DATA(DATA) (DATA <= 0xff) +#else +#define IS_SPI_DATA(DATA) (DATA <= 0xffff) +#endif + +#if (LIBCFG_SPI_FIFO_DEPTH_V01) +#define IS_SPI_FIFO_LEVEL(LEVEL) (LEVEL <= 4) +#else +#define IS_SPI_FIFO_LEVEL(LEVEL) (LEVEL <= 8) +#endif + +#define IS_SPI_CLOCK_PRESCALER(PRESCALER) (PRESCALER >= 2) + +#define SPI_GUADTIME_1_SCK ((u16)0x0000) +#define SPI_GUADTIME_2_SCK ((u16)0x0001) +#define SPI_GUADTIME_3_SCK ((u16)0x0002) +#define SPI_GUADTIME_4_SCK ((u16)0x0003) +#define SPI_GUADTIME_5_SCK ((u16)0x0004) +#define SPI_GUADTIME_6_SCK ((u16)0x0005) +#define SPI_GUADTIME_7_SCK ((u16)0x0006) +#define SPI_GUADTIME_8_SCK ((u16)0x0007) +#define SPI_GUADTIME_9_SCK ((u16)0x0008) +#define SPI_GUADTIME_10_SCK ((u16)0x0009) +#define SPI_GUADTIME_11_SCK ((u16)0x000A) +#define SPI_GUADTIME_12_SCK ((u16)0x000B) +#define SPI_GUADTIME_13_SCK ((u16)0x000C) +#define SPI_GUADTIME_14_SCK ((u16)0x000D) +#define SPI_GUADTIME_15_SCK ((u16)0x000E) +#define SPI_GUADTIME_16_SCK ((u16)0x000F) + +#define IS_SPI_GUADTIME(GUADTIMEPERIOD) ((GUADTIMEPERIOD <= 0x000F)) + + +#define SPI_SELHOLDTIME_HALF_SCK ((u16)0x0000) +#define SPI_SELHOLDTIME_1_SCK ((u16)0x0001) +#define SPI_SELHOLDTIME_1_HALF_SCK ((u16)0x0002) +#define SPI_SELHOLDTIME_2_SCK ((u16)0x0003) +#define SPI_SELHOLDTIME_2_HALF_SCK ((u16)0x0004) +#define SPI_SELHOLDTIME_3_SCK ((u16)0x0005) +#define SPI_SELHOLDTIME_3_HALF_SCK ((u16)0x0006) +#define SPI_SELHOLDTIME_4_SCK ((u16)0x0007) +#define SPI_SELHOLDTIME_4_HALF_SCK ((u16)0x0008) +#define SPI_SELHOLDTIME_5_SCK ((u16)0x0009) +#define SPI_SELHOLDTIME_5_HALF_SCK ((u16)0x000A) +#define SPI_SELHOLDTIME_6_SCK ((u16)0x000B) +#define SPI_SELHOLDTIME_6_HALF_SCK ((u16)0x000C) +#define SPI_SELHOLDTIME_7_SCK ((u16)0x000D) +#define SPI_SELHOLDTIME_7_HALF_SCK ((u16)0x000E) +#define SPI_SELHOLDTIME_8_SCK ((u16)0x000F) + +#define IS_SPI_SELHOLDTIME(SELHOLDTIME) ((SELHOLDTIME <= 0x000F)) +/** + * @} + */ + +/* Exported functions --------------------------------------------------------------------------------------*/ +/** @defgroup SPI_Exported_Functions SPI exported functions + * @{ + */ +void SPI_DeInit(HT_SPI_TypeDef* SPIx); +void SPI_Init(HT_SPI_TypeDef* SPIx, SPI_InitTypeDef* SPI_InitStruct); +void SPI_StructInit(SPI_InitTypeDef* SPI_InitStruct); +void SPI_Cmd(HT_SPI_TypeDef* SPIx, ControlStatus NewState); +#if (!LIBCFG_SPI_NO_MULTI_MASTER) +void SPI_SELOutputCmd(HT_SPI_TypeDef* SPIx, ControlStatus NewState); +#endif +void SPI_FIFOCmd(HT_SPI_TypeDef* SPIx, ControlStatus NewState); +void SPI_SetDataLength(HT_SPI_TypeDef* SPIx, u16 SPI_DataLength); +void SPI_SELModeConfig(HT_SPI_TypeDef* SPIx, u32 SPI_SELMode); +void SPI_SoftwareSELCmd(HT_SPI_TypeDef* SPIx, u32 SPI_SoftwareSEL); +void SPI_SendData(HT_SPI_TypeDef* SPIx, SPI_DataTypeDef SPI_Data); +SPI_DataTypeDef SPI_ReceiveData(HT_SPI_TypeDef* SPIx); +void SPI_SetTimeOutValue(HT_SPI_TypeDef* SPIx, SPI_TimeoutTypeDef SPI_Timeout); +void SPI_IntConfig(HT_SPI_TypeDef* SPIx, u32 SPI_Int, ControlStatus NewState); +FlagStatus SPI_GetFlagStatus(HT_SPI_TypeDef* SPIx, u32 SPI_Flag); +u8 SPI_GetFIFOStatus(HT_SPI_TypeDef* SPIx, u32 SPI_FIFODirection); +void SPI_ClearFlag(HT_SPI_TypeDef* SPIx, u32 SPI_FlagClear); +void SPI_FIFOTriggerLevelConfig(HT_SPI_TypeDef* SPIx, u32 SPI_FIFODirection, u8 SPI_FIFOLevel); +#if (LIBCFG_PDMA) +void SPI_PDMACmd(HT_SPI_TypeDef* SPIx, u32 SPI_PDMAREQ, ControlStatus NewState); +#endif +#if (!LIBCFG_SPI_NO_DUAL) +void SPI_DUALCmd(HT_SPI_TypeDef* SPIx, ControlStatus NewState); +#endif +void SPI_GUARDTCmd(HT_SPI_TypeDef* SPIx, ControlStatus NewState); +void SPI_GUARDTConfig(HT_SPI_TypeDef* SPIx, u32 Guard_Time); +void SPI_SELHTConfig(HT_SPI_TypeDef* SPIx, u32 CS_Hold_Time); +#if (LIBCFG_QSPI) +void QSPI_QuadCmd(HT_SPI_TypeDef* SPIx, ControlStatus NewState); +void QSPI_DirectionConfig(HT_SPI_TypeDef* SPIx, SIO_DIR_Enum SIO_DIR_INorOUT); +#endif +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f5xxxx_spi_midi.h b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f5xxxx_spi_midi.h new file mode 100644 index 0000000000..9494a08e46 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f5xxxx_spi_midi.h @@ -0,0 +1,204 @@ +/*********************************************************************************************************//** + * @file ht32f5xxxx_spi_midi.h + * @version $Rev:: 7075 $ + * @date $Date:: 2023-07-31 #$ + * @brief The header file of SPI library (MIDI Control). + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ +/* Define to prevent recursive inclusion -------------------------------------------------------------------*/ +#ifndef __HT32F5XXXX_SPI_MIDI_H +#define __HT32F5XXXX_SPI_MIDI_H + +#ifdef __cplusplus + extern "C" { +#endif + +/** @addtogroup HT32F5xxxx_Peripheral_Driver HT32F5xxxx Peripheral Driver + * @{ + */ + +/** @addtogroup SPI + * @{ + */ + + +/* Exported typedef ----------------------------------------------------------------------------------------*/ +/** @defgroup SPI_MIDI_Exported_Types QSPI MIDI exported types + * @{ + */ +typedef struct +{ + u32 MIDICTRL_MODE; + u32 MIDICTRL_CommandLength; + u32 MIDICTRL_AddressLength; + u32 MIDICTRL_ModeLength; + u32 MIDICTRL_DummyLength; + u32 MIDICTRL_DataLength; + u32 MIDICTRL_CommandValue; + u32 MIDICTRL_ModeValue; +} MIDICTRL_InitTypeDef; +/** + * @} + */ + +/* Exported constants --------------------------------------------------------------------------------------*/ +/** @defgroup SPI_Exported_Constants SPI exported constants + * @{ + */ +#define QDIOEN_POS (22) +#define SMDEL_POS (6) + +#define DOR_MODE (0UL << QDIOEN_POS | 1UL << SMDEL_POS ) +#define DIOR_MODE (1UL << QDIOEN_POS | 1UL << SMDEL_POS ) +#define QOR_MODE (0UL << QDIOEN_POS | 2UL << SMDEL_POS ) +#define QIOR_MODE (1UL << QDIOEN_POS | 2UL << SMDEL_POS ) +#define QPI_MODE (3UL << SMDEL_POS ) +#define SERIAL_MODE (0UL << SMDEL_POS ) + +/* QSPI Flash Command Field Length -------------------------------------------------------------------------*/ +#define MIDICTRL_CMDLENGTH_0 ((u32)0x00000000) +#define MIDICTRL_CMDLENGTH_1 ((u32)0x01000000) +#define MIDICTRL_CMDLENGTH_2 ((u32)0x02000000) +#define MIDICTRL_CMDLENGTH_3 ((u32)0x03000000) +#define MIDICTRL_CMDLENGTH_4 ((u32)0x04000000) +#define MIDICTRL_CMDLENGTH_5 ((u32)0x05000000) +#define MIDICTRL_CMDLENGTH_6 ((u32)0x06000000) +#define MIDICTRL_CMDLENGTH_7 ((u32)0x07000000) +#define MIDICTRL_CMDLENGTH_8 ((u32)0x08000000) + +/* QSPI FlashAddress Field Length --------------------------------------------------------------------------*/ +#define MIDICTRL_ADLENGTH_0 ((u32)0x00000000) +#define MIDICTRL_ADLENGTH_1 ((u32)0x00010000) +#define MIDICTRL_ADLENGTH_2 ((u32)0x00020000) +#define MIDICTRL_ADLENGTH_3 ((u32)0x00030000) +#define MIDICTRL_ADLENGTH_4 ((u32)0x00040000) +#define MIDICTRL_ADLENGTH_5 ((u32)0x00050000) +#define MIDICTRL_ADLENGTH_6 ((u32)0x00060000) +#define MIDICTRL_ADLENGTH_7 ((u32)0x00070000) +#define MIDICTRL_ADLENGTH_8 ((u32)0x00080000) +#define MIDICTRL_ADLENGTH_9 ((u32)0x00090000) +#define MIDICTRL_ADLENGTH_10 ((u32)0x000A0000) +#define MIDICTRL_ADLENGTH_11 ((u32)0x000B0000) +#define MIDICTRL_ADLENGTH_12 ((u32)0x000C0000) +#define MIDICTRL_ADLENGTH_13 ((u32)0x000D0000) +#define MIDICTRL_ADLENGTH_14 ((u32)0x000E0000) +#define MIDICTRL_ADLENGTH_15 ((u32)0x000F0000) +#define MIDICTRL_ADLENGTH_16 ((u32)0x00100000) +#define MIDICTRL_ADLENGTH_17 ((u32)0x00110000) +#define MIDICTRL_ADLENGTH_18 ((u32)0x00120000) +#define MIDICTRL_ADLENGTH_19 ((u32)0x00130000) +#define MIDICTRL_ADLENGTH_20 ((u32)0x00140000) +#define MIDICTRL_ADLENGTH_21 ((u32)0x00150000) +#define MIDICTRL_ADLENGTH_22 ((u32)0x00160000) +#define MIDICTRL_ADLENGTH_23 ((u32)0x00170000) +#define MIDICTRL_ADLENGTH_24 ((u32)0x00180000) + +/* QSPI Flash Command Field Length -------------------------------------------------------------------------*/ +#define MIDICTRL_MODELENGTH_0 ((u32)0x00000000) +#define MIDICTRL_MODELENGTH_1 ((u32)0x00001000) +#define MIDICTRL_MODELENGTH_2 ((u32)0x00002000) +#define MIDICTRL_MODELENGTH_3 ((u32)0x00003000) +#define MIDICTRL_MODELENGTH_4 ((u32)0x00004000) +#define MIDICTRL_MODELENGTH_5 ((u32)0x00005000) +#define MIDICTRL_MODELENGTH_6 ((u32)0x00006000) +#define MIDICTRL_MODELENGTH_7 ((u32)0x00007000) +#define MIDICTRL_MODELENGTH_8 ((u32)0x00008000) + +/* QSPI Flash Dummy Field Length ---------------------------------------------------------------------------*/ +#define MIDICTRL_DUMMYLENGTH_0 ((u32)0x00000000) +#define MIDICTRL_DUMMYLENGTH_1 ((u32)0x00000100) +#define MIDICTRL_DUMMYLENGTH_2 ((u32)0x00000200) +#define MIDICTRL_DUMMYLENGTH_3 ((u32)0x00000300) +#define MIDICTRL_DUMMYLENGTH_4 ((u32)0x00000400) +#define MIDICTRL_DUMMYLENGTH_5 ((u32)0x00000500) +#define MIDICTRL_DUMMYLENGTH_6 ((u32)0x00000600) +#define MIDICTRL_DUMMYLENGTH_7 ((u32)0x00000700) +#define MIDICTRL_DUMMYLENGTH_8 ((u32)0x00000800) + +/* QSPI Flash Data Field Length ----------------------------------------------------------------------------*/ +#define MIDICTRL_DATALENGTH_0 ((u32)0x00000000) +#define MIDICTRL_DATALENGTH_1 ((u32)0x00000001) +#define MIDICTRL_DATALENGTH_2 ((u32)0x00000002) +#define MIDICTRL_DATALENGTH_3 ((u32)0x00000003) +#define MIDICTRL_DATALENGTH_4 ((u32)0x00000004) +#define MIDICTRL_DATALENGTH_5 ((u32)0x00000005) +#define MIDICTRL_DATALENGTH_6 ((u32)0x00000006) +#define MIDICTRL_DATALENGTH_7 ((u32)0x00000007) +#define MIDICTRL_DATALENGTH_8 ((u32)0x00000008) +#define MIDICTRL_DATALENGTH_9 ((u32)0x00000009) +#define MIDICTRL_DATALENGTH_10 ((u32)0x0000000A) +#define MIDICTRL_DATALENGTH_11 ((u32)0x0000000B) +#define MIDICTRL_DATALENGTH_12 ((u32)0x0000000C) +#define MIDICTRL_DATALENGTH_13 ((u32)0x0000000D) +#define MIDICTRL_DATALENGTH_14 ((u32)0x0000000E) +#define MIDICTRL_DATALENGTH_15 ((u32)0x0000000F) +#define MIDICTRL_DATALENGTH_16 ((u32)0x00000010) +#define MIDICTRL_DATALENGTH_17 ((u32)0x00000011) +#define MIDICTRL_DATALENGTH_18 ((u32)0x00000012) +#define MIDICTRL_DATALENGTH_19 ((u32)0x00000013) +#define MIDICTRL_DATALENGTH_20 ((u32)0x00000014) +#define MIDICTRL_DATALENGTH_21 ((u32)0x00000015) +#define MIDICTRL_DATALENGTH_22 ((u32)0x00000016) +#define MIDICTRL_DATALENGTH_23 ((u32)0x00000017) +#define MIDICTRL_DATALENGTH_24 ((u32)0x00000018) +#define MIDICTRL_DATALENGTH_25 ((u32)0x00000019) +#define MIDICTRL_DATALENGTH_26 ((u32)0x0000001A) +#define MIDICTRL_DATALENGTH_27 ((u32)0x0000001B) +#define MIDICTRL_DATALENGTH_28 ((u32)0x0000001C) +#define MIDICTRL_DATALENGTH_29 ((u32)0x0000001D) +#define MIDICTRL_DATALENGTH_30 ((u32)0x0000001E) +#define MIDICTRL_DATALENGTH_31 ((u32)0x0000001F) +#define MIDICTRL_DATALENGTH_32 ((u32)0x00000020) + +#define MIDICTRL_ON ((u32)0x00800000) +#define MIDICTRL_OFF ((u32)0xFF7FFFFF) + +#define CMDVALUE_POS (8) +#define MDVALUE_POS (0) +/** + * @} + */ + +/* Exported functions --------------------------------------------------------------------------------------*/ +/** @defgroup SPI_Exported_Functions SPI exported functions + * @{ + */ +void MIDICTRL_Cmd(HT_SPI_TypeDef* QSPIx ,ControlStatus NewState); +void MIDICTRL_Init(HT_SPI_TypeDef* QSPIx, MIDICTRL_InitTypeDef* MIDICTRL_InitStruct); +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f5xxxx_tkey.h b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f5xxxx_tkey.h new file mode 100644 index 0000000000..e51f1292b5 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f5xxxx_tkey.h @@ -0,0 +1,311 @@ +/*********************************************************************************************************//** + * @file ht32f5xxxx_tkey.h + * @version $Rev:: 5483 $ + * @date $Date:: 2021-07-19 #$ + * @brief The header file of the TKEY library. + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------------------------------------*/ +#ifndef __HT32F5XXXX_TKEY_H +#define __HT32F5XXXX_TKEY_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------------------------------------*/ +#include "ht32.h" + +/** @addtogroup HT32F5xxxx_Peripheral_Driver HT32F5xxxx Peripheral Driver + * @{ + */ + +/** @addtogroup TKEY + * @{ + */ + + +/* Exported types ------------------------------------------------------------------------------------------*/ +/** @defgroup TKEY_Exported_Types TKEY exported types + * @{ + */ + +typedef enum +{ /*!< Touch key IP clock source */ + TKEY_PCLK = 0 , /*!< PCLK */ + TKEY_LSI /*!< LSI */ +} TKEY_IP_CLK_Enum; + +typedef enum +{ /*!< Periodic auto scan mode time-out selection */ + TKEY_RefOSC_DelayTime_0 = (0 << 13), /*!< 4 RefOSC clock */ + TKEY_RefOSC_DelayTime_1 = (1 << 13), /*!< 2 RefOSC clock */ + TKEY_RefOSC_DelayTime_2 = (2 << 13), /*!< 4 RefOSC clock */ + TKEY_RefOSC_DelayTime_3 = (3 << 13), /*!< 8 RefOSC clock */ + TKEY_RefOSC_DelayTime_4 = (4 << 13), /*!< 16 RefOSC clock */ + TKEY_RefOSC_DelayTime_5 = (5 << 13), /*!< 32 RefOSC clock */ + TKEY_RefOSC_DelayTime_6 = (6 << 13), /*!< 64 RefOSC clock */ + TKEY_RefOSC_DelayTime_7 = (7 << 13), /*!< 4 RefOSC clock */ +} TKEY_RefOSC_DelayTime_Enum; + + +typedef enum +{ /*!< Periodic auto scan mode time-out selection */ + TKEY_PASM_TIMEOUT_0 = (0 << 10), /*!< 2^13/FLIRC */ + TKEY_PASM_TIMEOUT_1 = (1 << 10), /*!< 2^14/FLIRC */ + TKEY_PASM_TIMEOUT_2 = (2 << 10), /*!< 2^15/FLIRC */ + TKEY_PASM_TIMEOUT_3 = (3 << 10), /*!< 2^16/FLIRC */ + TKEY_PASM_TIMEOUT_4 = (4 << 10), /*!< 2^17/FLIRC */ + TKEY_PASM_TIMEOUT_5 = (5 << 10), /*!< 2^18/FLIRC */ +} TKEY_PASM_TIMEOUT_Enum; + +typedef enum +{ /*!< Periodic auto scan mode period selection */ + TKEY_PASM_PERIOD_0 = (0 << 8), /*!< 2^14/FLIRC */ + TKEY_PASM_PERIOD_1 = (1 << 8), /*!< 2^13/FLIRC */ + TKEY_PASM_PERIOD_2 = (2 << 8), /*!< 2^12/FLIRC */ + TKEY_PASM_PERIOD_3 = (3 << 8), /*!< 2^11/FLIRC */ +} TKEY_PASM_PERIOD_Enum; + +typedef enum +{ /*!< 16-bit counter clock source selection */ + TKEY_TK16S_CLK_0 = (0 << 5), /*!< TKCLK/16 */ + TKEY_TK16S_CLK_1 = (1 << 5), /*!< TKCLK/32 */ + TKEY_TK16S_CLK_2 = (2 << 5), /*!< TKCLK/64 */ + TKEY_TK16S_CLK_3 = (3 << 5), /*!< TKCLK/128 */ +} TKEY_TK16S_CLK_Enum; + +typedef enum +{ /*!< OSC frequency selection */ + TKEY_TKFS_FREQ_0 = (0 << 3), /*!< 1MHz */ + TKEY_TKFS_FREQ_1 = (1 << 3), /*!< 3MHz */ + TKEY_TKFS_FREQ_2 = (2 << 3), /*!< 7MHz */ + TKEY_TKFS_FREQ_3 = (3 << 3), /*!< 11MHz */ +} TKEY_TKFS_FREQ_Enum; + +typedef enum +{ /*!< Mode selection */ + TKEY_MODE_AUTOSCAN = (0 << 1), /*!< Auto scan mode */ + TKEY_MODE_MANUAL = (1 << 1), /*!< Manual mode */ + TKEY_MODE_PASM = (2 << 1), /*!< Periodic auto scan mode */ +} TKEY_MODE_Enum; + +typedef enum +{ /*!< TKEY module selection */ + TKM_0 = 0, /*!< TKEY module 0 */ + TKM_1, /*!< TKEY module 1 */ + TKM_2, /*!< TKEY module 2 */ + TKM_3, /*!< TKEY module 3 */ + TKM_4, /*!< TKEY module 4 */ + TKM_5, /*!< TKEY module 5 */ +} TKM_Enum; + +typedef enum +{ /*!< 8-bit time slot counter clock source */ + TKM_TSS_CLK_0 = (0 << 8), /*!< Ref. OSC */ + TKM_TSS_CLK_1 = (1 << 8), /*!< TKCLK/32 */ + TKM_TSS_CLK_2 = (2 << 8), /*!< TKCLK/64 */ + TKM_TSS_CLK_3 = (3 << 8), /*!< TKCLK/128 */ +} TKM_TSS_CLK_Enum; + +typedef enum +{ /*!< C/F OSC frequency hopping selection */ + TKM_SOF_CTRL_SW = (0 << 3), /*!< S/W controlled frequency hopping */ + TKM_SOF_CTRL_HW = (1 << 3), /*!< H/W controlled frequency hopping */ +} TKM_SOF_CTRL_Enum; + +typedef enum +{ /*!< Key OSC and Ref OSC frequency selection */ + TKM_SOF_FREQ_0 = (0 << 0), /*!< 1.020MHz. */ + TKM_SOF_FREQ_1 = (1 << 0), /*!< 1.040MHz. */ + TKM_SOF_FREQ_2 = (2 << 0), /*!< 1.059MHz. */ + TKM_SOF_FREQ_3 = (3 << 0), /*!< 1.074MHz. */ + TKM_SOF_FREQ_4 = (4 << 0), /*!< 1.085MHz. */ + TKM_SOF_FREQ_5 = (5 << 0), /*!< 1.099MHz. */ + TKM_SOF_FREQ_6 = (6 << 0), /*!< 1.111MHz. */ + TKM_SOF_FREQ_7 = (7 << 0) /*!< 1.125MHz. */ +} TKM_SOF_FREQ_Enum; + +typedef enum +{ /*!< Key selection */ + TKM_KEY_0 = 0, /*!< Key 0 */ + TKM_KEY_1, /*!< Key 1 */ + TKM_KEY_2, /*!< Key 2 */ + TKM_KEY_3, /*!< Key 3 */ +} TKM_KEY_Enum; + +typedef enum +{ /*!< Time slot selection */ + TKM_TIME_SLOT_0 = 0, /*!< Time slot 0 */ + TKM_TIME_SLOT_1, /*!< Time slot 1 */ + TKM_TIME_SLOT_2, /*!< Time slot 2 */ + TKM_TIME_SLOT_3, /*!< Time slot 3 */ +} TKM_TIME_SLOT_Enum; + +typedef enum +{ /*!< Key threshold selection */ + TKM_KEY_THR_LOWER = 0, /*!< Lower threshold */ + TKM_KEY_THR_UPPER, /*!< Upper threshold */ +} TKM_KEY_THR_Enum; +/** + * @} + */ + +/* Exported constants --------------------------------------------------------------------------------------*/ +/** @defgroup TKEY_Exported_Constants TKEY exported constants + * @{ + */ +#define IS_TKEY_IP_CLK(x) (((x) == TKEY_PCLK) || ((x) == TKEY_LSI) ) + +#define IS_TKEY_RefOSC_DelayTime(x) (((x) == TKEY_RefOSC_DelayTime_0) || ((x) == TKEY_RefOSC_DelayTime_1) || \ + ((x) == TKEY_RefOSC_DelayTime_2) || ((x) == TKEY_RefOSC_DelayTime_3) || \ + ((x) == TKEY_RefOSC_DelayTime_4) || ((x) == TKEY_RefOSC_DelayTime_5)|| \ + ((x) == TKEY_RefOSC_DelayTime_6) || ((x) == TKEY_RefOSC_DelayTime_7)) + +#define IS_TKEY_PASM_TIMEOUT(x) (((x) == TKEY_PASM_TIMEOUT_0) || ((x) == TKEY_PASM_TIMEOUT_1) || \ + ((x) == TKEY_PASM_TIMEOUT_2) || ((x) == TKEY_PASM_TIMEOUT_3) || \ + ((x) == TKEY_PASM_TIMEOUT_4) || ((x) == TKEY_PASM_TIMEOUT_5)) + +#define IS_TKEY_PASM_PERIOD(x) (((x) == TKEY_PASM_PERIOD_0) || ((x) == TKEY_PASM_PERIOD_1) || \ + ((x) == TKEY_PASM_PERIOD_2) || ((x) == TKEY_PASM_PERIOD_3)) + +#define IS_TKEY_TK16S_CLK(x) (((x) == TKEY_TK16S_CLK_0) || ((x) == TKEY_TK16S_CLK_1) || \ + ((x) == TKEY_TK16S_CLK_2) || ((x) == TKEY_TK16S_CLK_3)) + + +#define IS_TKEY_TKFS_FREQ(x) (((x) == TKEY_TKFS_FREQ_0) || ((x) == TKEY_TKFS_FREQ_1) || \ + ((x) == TKEY_TKFS_FREQ_2) || ((x) == TKEY_TKFS_FREQ_3)) + +#define IS_TKEY_MODE(x) (((x) == TKEY_MODE_AUTOSCAN) || ((x) == TKEY_MODE_MANUAL) || \ + ((x) == TKEY_MODE_PASM)) + +#define TKEY_INT_TKTHE ((u32)0x00000001) +#define TKEY_INT_TKRCOVE ((u32)0x00000002) +#define TKEY_INT_TKTHWUEN ((u32)0x00000004) +#define TKEY_INT_TKRCOVWUEN ((u32)0x00000008) + +#define IS_TKEY_INT(TKEY_INT) (((TKEY_INT & 0xFFFFFFFC) == 0) && (TKEY_INT != 0)) + +#define TKEY_FLAG_TKTHF ((u32)0x00000001) +#define TKEY_FLAG_TKRCOVF ((u32)0x00000002) +#define TKEY_FLAG_TK16OV ((u32)0x00000004) +#define TKEY_FLAG_TKCFOV ((u32)0x00000008) +#define TKEY_FLAG_TKBUSY ((u32)0x00000010) + +#define IS_TKEY_FLAG(FLAG) ((FLAG == TKEY_FLAG_TKTHF) || \ + (FLAG == TKEY_FLAG_TKRCOVF) || \ + (FLAG == TKEY_FLAG_TK16OV) || \ + (FLAG == TKEY_FLAG_TKCFOV) || \ + (FLAG == TKEY_FLAG_TKBUSY)) + + +#define IS_TKEY_FLAG_CLEAR(CLEAR) ((CLEAR == TKEY_FLAG_TKTHF) || \ + (CLEAR == TKEY_FLAG_TKRCOVF) || \ + (CLEAR == TKEY_FLAG_TK16OV) || \ + (CLEAR == TKEY_FLAG_TKCFOV)) + +#define IS_TKM(x) (((x) == TKM_0) || ((x) == TKM_1) || \ + ((x) == TKM_2) || ((x) == TKM_3) || \ + ((x) == TKM_4) || ((x) == TKM_5)) + +#define IS_TKM_TSS_CLK(x) (((x) == TKM_TSS_CLK_0) || ((x) == TKM_TSS_CLK_1) || \ + ((x) == TKM_TSS_CLK_2) || ((x) == TKM_TSS_CLK_3)) + + +#define IS_TKM_SOFC_CTRL(x) (((x) == TKM_SOFC_SW) || ((x) == TKM_SOFC_HW)) + +#define IS_TKM_SOF_FREQ(x) (((x) == TKM_SOF_FREQ_0) || ((x) == TKM_SOF_FREQ_1) || \ + ((x) == TKM_SOF_FREQ_2) || ((x) == TKM_SOF_FREQ_3) || \ + ((x) == TKM_SOF_FREQ_4) || ((x) == TKM_SOF_FREQ_5) || \ + ((x) == TKM_SOF_FREQ_6) || ((x) == TKM_SOF_FREQ_7)) + +#define IS_TKM_KEY(x) (((x) == TKM_KEY_3) || ((x) == TKM_KEY_2) || \ + ((x) == TKM_KEY_1) || ((x) == TKM_KEY_0)) + +#define IS_TKM_SOF_CTRL(x) (((x) == TKM_SOF_CTRL_SW) || ((x) == TKM_SOF_CTRL_HW)) + +#define IS_TKM_TIME_SLOT(x) (((x) == TKM_TIME_SLOT_0) || ((x) == TKM_TIME_SLOT_1) || \ + ((x) == TKM_TIME_SLOT_2) || ((x) == TKM_TIME_SLOT_3)) + +#define IS_TKM_KEY_THR(x) (((x) == TKM_KEY_THR_LOWER) || ((x) == TKM_KEY_THR_UPPER)) +/** + * @} + */ + +/* Exported functions --------------------------------------------------------------------------------------*/ +/** @defgroup TKEY_Exported_Functions TKEY exported functions + * @{ + */ +void TKEY_DeInit(void); +void TKEY_IPClockConfig(TKEY_IP_CLK_Enum Sel); +void TKEY_RefOSCDelayTimeConfig(TKEY_RefOSC_DelayTime_Enum Sel); +void TKEY_PASMTimeoutConfig(TKEY_PASM_TIMEOUT_Enum Sel); +void TKEY_PASMPeriodConfig(TKEY_PASM_PERIOD_Enum Sel); +void TKEY_16BitCounterClockConfig(TKEY_TK16S_CLK_Enum Sel); +void TKEY_OSCFreqConfig(TKEY_TKFS_FREQ_Enum Sel); +void TKEY_ModeConfig(TKEY_MODE_Enum Sel); +void TKEY_StartCmd(ControlStatus NewState); +void TKEY_IntConfig(u32 TKEY_Int, ControlStatus NewState); +FlagStatus TKEY_GetFlagStatus(u32 TKEY_Flag); +void TKEY_ClearFlag(u32 TKEY_Flag); +u32 TKEY_Get16BitCounterValue(void); +void TKEY_Set8BitCounterReload(u32 Reload); +u32 TKEY_Get8BitCounterReload(void); + +void TKM_TimeSlotCounterClockConfig(TKM_Enum TKMn, TKM_TSS_CLK_Enum Sel); +void TKM_RefOSCCmd(TKM_Enum TKMn, ControlStatus NewState); +void TKM_KeyOSCCmd(TKM_Enum TKMn, ControlStatus NewState); +void TKM_MultiFreqCmd(TKM_Enum TKMn, ControlStatus NewState); +void TKM_SOFCtrlConfig(TKM_Enum TKMn, TKM_SOF_CTRL_Enum Sel); +void TKM_SOFFreqConfig(TKM_Enum TKMn, TKM_SOF_FREQ_Enum Sel); +void TKM_KeyCmd(TKM_Enum TKMn, TKM_KEY_Enum Key, ControlStatus NewState); +void TKM_TimeSlotKeyConfig(TKM_Enum TKMn, TKM_TIME_SLOT_Enum Slot, TKM_KEY_Enum Key); +void TKM_KeyThresholdConfig(TKM_Enum TKMn, TKM_KEY_Enum Key, TKM_KEY_THR_Enum Sel); +FlagStatus TKM_GetMatchFlagStatus(TKM_Enum TKMn, TKM_KEY_Enum Key); +void TKM_ClearMatchFlag(TKM_Enum TKMn, TKM_KEY_Enum Key); +void TKM_SetRefOSCCapacitor(TKM_Enum TKMn, u32 Value); +u32 TKM_GetRefOSCCapacitor(TKM_Enum TKMn); +void TKM_SetKeyCapacitor(TKM_Enum TKMn, TKM_KEY_Enum Key, u32 Value); +u32 TKM_GetKeyCapacitor(TKM_Enum TKMn, TKM_KEY_Enum Key); +u32 TKM_Get16BitCFCounterValue(TKM_Enum TKMn); +u32 TKM_GetKeyCounterValue(TKM_Enum TKMn, TKM_KEY_Enum Key); +void TKM_SetKeyThreshold(TKM_Enum TKMn, TKM_KEY_Enum Key, u32 Value); +u32 TKM_GetKeyThreshold(TKM_Enum TKMn, TKM_KEY_Enum Key); +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f5xxxx_tm.h b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f5xxxx_tm.h new file mode 100644 index 0000000000..eb0d814f23 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f5xxxx_tm.h @@ -0,0 +1,942 @@ +/*********************************************************************************************************//** + * @file ht32f5xxxx_tm.h + * @version $Rev:: 7319 $ + * @date $Date:: 2023-10-28 #$ + * @brief The header file of the TM library. + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------------------------------------*/ +#ifndef __HT32F5XXXX_TM_H +#define __HT32F5XXXX_TM_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------------------------------------*/ +#include "ht32.h" + +/** @addtogroup HT32F5xxxx_Peripheral_Driver HT32F5xxxx Peripheral Driver + * @{ + */ + +/** @addtogroup TM + * @{ + */ + + +/* Exported types ------------------------------------------------------------------------------------------*/ +/** @defgroup TM_Exported_Types TM exported types + * @{ + */ +/** + * @brief Enumeration of TM counter mode. + */ +typedef enum +{ + TM_CNT_MODE_UP = 0x00000000, /*!< Edge up-counting mode */ + TM_CNT_MODE_CA1 = 0x00010000, /*!< Center-align mode 1 */ + TM_CNT_MODE_CA2 = 0x00020000, /*!< Center-align mode 2 */ + TM_CNT_MODE_CA3 = 0x00030000, /*!< Center-align mode 3 */ + TM_CNT_MODE_DOWN = 0x01000000 /*!< Edge down-counting mode */ +} TM_CNT_MODE_Enum; +/** + * @brief Enumeration of TM prescaler reload time. + */ +typedef enum +{ + TM_PSC_RLD_UPDATE = 0x0000, /*!< Reload prescaler at next update event */ + TM_PSC_RLD_IMMEDIATE = 0x0100 /*!< Reload prescaler immediately */ +} TM_PSC_RLD_Enum; +/** + * @brief Enumeration of TM channel output mode. + */ +typedef enum +{ + TM_OM_MATCH_NOCHANGE = 0x0000, /*!< TM channel output no change on match */ + TM_OM_MATCH_INACTIVE = 0x0001, /*!< TM channel output inactive level on match */ + TM_OM_MATCH_ACTIVE = 0x0002, /*!< TM channel output active level on match */ + TM_OM_MATCH_TOGGLE = 0x0003, /*!< TM channel output toggle on match */ + TM_OM_FORCED_INACTIVE = 0x0004, /*!< TM channel output forced inactive level */ + TM_OM_FORCED_ACTIVE = 0x0005, /*!< TM channel output forced active level */ + TM_OM_PWM1 = 0x0006, /*!< TM channel pwm1 output mode */ + TM_OM_PWM2 = 0x0007, /*!< TM channel pwm2 output mode */ + TM_OM_ASYMMETRIC_PWM1 = 0x0106, /*!< TM channel asymmetric pwm1 output mode */ + TM_OM_ASYMMETRIC_PWM2 = 0x0107 /*!< TM channel asymmetric pwm2 output mode */ +} TM_OM_Enum; +/** + * @brief Enumeration of TM channel capture source selection. + */ +typedef enum +{ + TM_CHCCS_DIRECT = 0x00010000, /*!< TM channel capture selection direct input */ + TM_CHCCS_INDIRECT = 0x00020000, /*!< TM channel capture selection indirect input */ + TM_CHCCS_TRCED = 0x00030000 /*!< TM channel capture selection TRCED of trigger control block */ +} TM_CHCCS_Enum; +/** + * @brief Enumeration of TM channel capture prescaler. + */ +typedef enum +{ + TM_CHPSC_OFF = 0x00000000, /*!< TM channel capture no prescaler, capture is done each event */ + TM_CHPSC_2 = 0x00040000, /*!< TM channel capture is done once every 2 event */ + TM_CHPSC_4 = 0x00080000, /*!< TM channel capture is done once every 4 event */ + TM_CHPSC_8 = 0x000C0000 /*!< TM channel capture is done once every 8 event */ +} TM_CHPSC_Enum; +#if (LIBCFG_TM_652XX_V1) +/** + * @brief Enumeration of TM channel Filter (Fsampling) Clock Divider. + */ +typedef enum +{ + TM_CHFDIV_1 = 0x00000000, /*!< TM channel Filter Fsampling = Fdts */ + TM_CHFDIV_2 = 0x00000001, /*!< TM channel Filter Fsampling = Fdts/2 */ + TM_CHFDIV_4 = 0x00000002, /*!< TM channel Filter Fsampling = Fdts/4 */ + TM_CHFDIV_8 = 0x00000003, /*!< TM channel Filter Fsampling = Fdts/8 */ + TM_CHFDIV_16 = 0x00000004, /*!< TM channel Filter Fsampling = Fdts/16 */ + TM_CHFDIV_32 = 0x00000005, /*!< TM channel Filter Fsampling = Fdts/32 */ + TM_CHFDIV_64 = 0x00000006 /*!< TM channel Filter Fsampling = Fdts/64 */ +} TM_CHFDIV_Enum; +/** + * @brief Enumeration of TM channel Filter N-event counter + */ +#if (LIBCFG_TM_TIFN_5BIT) +typedef enum +{ + TM_CHFEV_OFF = 0, /*!< TM channel Filter off */ + TM_CHFEV_1, /*!< TM channel Filter n event counter Setting */ + TM_CHFEV_2, + TM_CHFEV_3, + TM_CHFEV_4, + TM_CHFEV_5, + TM_CHFEV_6, + TM_CHFEV_7, + TM_CHFEV_8, + TM_CHFEV_9, + TM_CHFEV_10, + TM_CHFEV_11, + TM_CHFEV_12, + TM_CHFEV_13, + TM_CHFEV_14, + TM_CHFEV_15, + TM_CHFEV_16, + TM_CHFEV_17, + TM_CHFEV_18, + TM_CHFEV_19, + TM_CHFEV_20, + TM_CHFEV_21, + TM_CHFEV_22, + TM_CHFEV_23, + TM_CHFEV_24, + TM_CHFEV_25, + TM_CHFEV_26, + TM_CHFEV_27, + TM_CHFEV_28, + TM_CHFEV_29, + TM_CHFEV_30, + TM_CHFEV_31, +} TM_CHFEV_Enum; +#else +typedef enum +{ + TM_CHFEV_OFF = 0x00000000, /*!< TM channel Filter off */ + TM_CHFEV_2 = 0x00000001, /*!< TM channel Filter 2 event counter Setting */ + TM_CHFEV_4 = 0x00000002, /*!< TM channel Filter 4 event counter Setting */ + TM_CHFEV_8 = 0x00000003, /*!< TM channel Filter 8 event counter Setting */ + TM_CHFEV_12 = 0x00000004, /*!< TM channel Filter 12 event counter Setting */ + TM_CHFEV_16 = 0x00000005 /*!< TM channel Filter 16 event counter Setting */ +} TM_CHFEV_Enum; +#endif +#endif +/** + * @brief Enumeration of TM fDTS clock divider. + */ +typedef enum +{ + TM_CKDIV_OFF = 0x0000, /*!< fDTS = fCLKIN */ + TM_CKDIV_2 = 0x0100, /*!< fDTS = fCLKIN / 2 */ + TM_CKDIV_4 = 0x0200, /*!< fDTS = fCLKIN / 4 */ + #if (LIBCFG_TM_652XX_V1 || LIBCFG_TM_CKDIV_8) + TM_CKDIV_8 = 0x0300, /*!< fDTS = fCLKIN / 8 */ + #endif +} TM_CKDIV_Enum; +#if 0 +/** + * @brief Enumeration of TM ETI input prescaler. + */ +typedef enum +{ + TM_ETIPSC_OFF = 0x00000000, /*!< ETI prescaler off */ + TM_ETIPSC_2 = 0x00001000, /*!< ETIP frequency divided by 2 */ + TM_ETIPSC_4 = 0x00002000, /*!< ETIP frequency divided by 4 */ + TM_ETIPSC_8 = 0x00003000 /*!< ETIP frequency divided by 8 */ +} TM_ETIPSC_Enum; +/** + * @brief Enumeration of TM ETI input polarity. + */ +typedef enum +{ + TM_ETIPOL_NONINVERTED = 0x00000000, /*!< TM ETI polarity is active high or rising edge */ + TM_ETIPOL_INVERTED = 0x00010000 /*!< TM ETI polarity is active low or falling edge */ +} TM_ETIPOL_Enum; +#endif +/** + * @brief Enumeration of TM slave trigger input selection. + */ +typedef enum +{ + TM_TRSEL_UEVG = 0x0, /*!< Software trigger by setting UEVG bit */ + TM_TRSEL_TI0S0 = 0x1, /*!< Filtered channel 0 input */ + TM_TRSEL_TI1S1 = 0x2, /*!< Filtered channel 1 input */ + TM_TRSEL_ETIF = 0x3, /*!< External Trigger input */ + TM_TRSEL_TI0BED = 0x8, /*!< Trigger input 0 both edge detector */ +#if (LIBCFG_TM_NO_ITI == 1) + #define IS_TRSEL_ITI0(x) (0) + #define IS_TRSEL_ITI1(x) (0) + #define IS_TRSEL_ITI2(x) (0) +#else + TM_TRSEL_ITI0 = 0x9, /*!< Internal trigger input 0 */ + TM_TRSEL_ITI1 = 0xA, /*!< Internal trigger input 1 */ + TM_TRSEL_ITI2 = 0xB /*!< Internal trigger input 2 */ + #define IS_TRSEL_ITI0(x) (x == TM_TRSEL_ITI0) + #define IS_TRSEL_ITI1(x) (x == TM_TRSEL_ITI1) + #define IS_TRSEL_ITI2(x) (x == TM_TRSEL_ITI2) +#endif +} TM_TRSEL_Enum; +/** + * @brief Enumeration of TM slave mode selection. + */ +typedef enum +{ + TM_SMSEL_DISABLE = 0x0000, /*!< The prescaler is clocked directly by the internal clock */ + TM_SMSEL_DECODER1 = 0x0100, /*!< Counter counts up/down on CH0 edge depending on CH1 level */ + TM_SMSEL_DECODER2 = 0x0200, /*!< Counter counts up/down on CH1 edge depending on CH0 level */ + TM_SMSEL_DECODER3 = 0x0300, /*!< Counter counts up/down on both CH0 & CH1 edges depending on the + level of the other input */ + TM_SMSEL_RESTART = 0x0400, /*!< Slave restart mode */ + TM_SMSEL_PAUSE = 0x0500, /*!< Slave pause mode */ + TM_SMSEL_TRIGGER = 0x0600, /*!< Slave trigger mode */ + TM_SMSEL_STIED = 0x0700, /*!< Rising edge of the selected trigger(STI) clock the counter */ + #if (LIBCFG_TM_652XX_V1) + TM_SMSEL_DECODER4 = 0x0800, /*!< Pluse/Direction mode(Counter counts on Ch0, Count up/down on Ch1 */ + #endif +} TM_SMSEL_Enum; +/** + * @brief Enumeration of TM master mode selection. + */ +typedef enum +{ + TM_MMSEL_RESET = 0x00000000, /*!< Send trigger signal when S/W setting UEVG or slave restart */ + TM_MMSEL_ENABLE = 0x00010000, /*!< The counter enable signal is used as trigger output. */ + TM_MMSEL_UPDATE = 0x00020000, /*!< The update event is used as trigger output. */ + TM_MMSEL_CH0CC = 0x00030000, /*!< Channel 0 capture or compare match occurred as trigger output. */ + TM_MMSEL_CH0OREF = 0x00040000, /*!< The CH0OREF signal is used as trigger output. */ + TM_MMSEL_CH1OREF = 0x00050000, /*!< The CH1OREF signal is used as trigger output. */ + TM_MMSEL_CH2OREF = 0x00060000, /*!< The CH2OREF signal is used as trigger output. */ + TM_MMSEL_CH3OREF = 0x00070000, /*!< The CH3OREF signal is used as trigger output. */ + #if (LIBCFG_TM_652XX_V1) + TM_MMSEL_VCLK = 0x000C0000 /*!< The VCLK signal is used as trigger output. */ + #endif + #if (LIBCFG_PWM_8_CHANNEL) + TM_MMSEL_CH4OREF = 0x00080000, /*!< The CH4OREF signal is used as trigger output. */ + TM_MMSEL_CH5OREF = 0x00090000, /*!< The CH5OREF signal is used as trigger output. */ + TM_MMSEL_CH6OREF = 0x000A0000, /*!< The CH6OREF signal is used as trigger output. */ + TM_MMSEL_CH7OREF = 0x000B0000 /*!< The CH7OREF signal is used as trigger output. */ + #endif +} TM_MMSEL_Enum; +#if (LIBCFG_PDMA) +/** + * @brief Enumeration of TM channel Capture / Compare PDMA selection. + */ +typedef enum +{ + TM_CHCCDS_CHCCEV = 0, /*!< Send CHx PDMA request when channel capture/compare event occurs */ + TM_CHCCDS_UEV /*!< Send CHx PDMA request when update event occurs */ +} TM_CHCCDS_Enum; +#endif +/** + * @brief Definition of TM timebase init structure. + */ +typedef struct +{ + u16 CounterReload; /*!< Period (Value for CRR register) */ +#if(LIBCFG_TM_PRESCALER_8BIT) + u8 Prescaler; /*!< Prescaler (Value for PSCR register) */ +#else + u16 Prescaler; /*!< Prescaler (Value for PSCR register) */ +#endif + u8 RepetitionCounter; /*!< Repetition counter */ + TM_CNT_MODE_Enum CounterMode; /*!< Counter mode refer to \ref TM_CNT_MODE_Enum */ + TM_PSC_RLD_Enum PSCReloadTime; /*!< Prescaler reload mode refer to \ref TM_PSC_RLD_Enum */ +} TM_TimeBaseInitTypeDef; +/** + * @brief Definition of TM channel output init structure. + */ +typedef struct +{ + TM_CH_Enum Channel; /*!< Channel selection refer to \ref TM_CH_Enum */ + TM_OM_Enum OutputMode; /*!< Channel output mode selection refer to \ref TM_OM_Enum */ + TM_CHCTL_Enum Control; /*!< CHxO output state refer to \ref TM_CHCTL_Enum */ + TM_CHCTL_Enum ControlN; /*!< CHxO output state refer to \ref TM_CHCTL_Enum */ + TM_CHP_Enum Polarity; /*!< CHxO polarity refer to \ref TM_CHP_Enum */ + TM_CHP_Enum PolarityN; /*!< CHxO polarity refer to \ref TM_CHP_Enum */ + MCTM_OIS_Enum IdleState; /*!< CHxO polarity refer to \ref TM_CHP_Enum */ + MCTM_OIS_Enum IdleStateN; /*!< CHxO polarity refer to \ref TM_CHP_Enum */ + u16 Compare; /*!< Value for CHxCCR register */ + u16 AsymmetricCompare; /*!< Value for CHxACR register */ +} TM_OutputInitTypeDef; +/** + * @brief Definition of TM channel input init structure. + */ +typedef struct +{ + TM_CH_Enum Channel; /*!< Channel selection refer to \ref TM_CH_Enum */ + TM_CHP_Enum Polarity; /*!< Channel input polarity refer to \ref TM_CHP_Enum */ + TM_CHCCS_Enum Selection; /*!< Channel capture source selection refer to \ref TM_CHCCS_Enum */ + TM_CHPSC_Enum Prescaler; /*!< Channel Capture prescaler refer to \ref TM_CHPSC_Enum */ + #if (LIBCFG_TM_652XX_V1) + TM_CHFDIV_Enum Fsampling; /*!< Digital filter Fsampling Frequency, it must fDTS/1 ~ fDTS/64 */ + #if (LIBCFG_TM_TIFN_5BIT) + u8 Event; /*!< Digital filter N-event counter Setting, it must be 0 ~ 31 */ + #else + TM_CHFEV_Enum Event; /*!< Digital filter N-event counter Setting, it must be 0, 2, 4, 8, 12, 16 */ + #endif + #else + u8 Filter; /*!< Digital filter Configuration, it must between 0x0 ~ 0xF. */ + #endif +} TM_CaptureInitTypeDef; +/** + * @} + */ + +/* Exported constants --------------------------------------------------------------------------------------*/ +/** @defgroup TM_Exported_Constants TM exported constants + * @{ + */ + +/** @defgroup TM_INT Definitions of TM_INT + * @{ + */ +#define TM_INT_CH0CC 0x0001 /*!< Channel 0 capture/compare interrupt */ +#define TM_INT_CH1CC 0x0002 /*!< Channel 1 capture/compare interrupt */ +#define TM_INT_CH2CC 0x0004 /*!< Channel 2 capture/compare interrupt */ +#define TM_INT_CH3CC 0x0008 /*!< Channel 3 capture/compare interrupt */ +#if (LIBCFG_PWM_8_CHANNEL) +#define TM_INT_CH4CC 0x10000000ul /*!< Channel 4 compare interrupt */ +#define TM_INT_CH5CC 0x20000000ul /*!< Channel 5 compare interrupt */ +#define TM_INT_CH6CC 0x40000000ul /*!< Channel 6 compare interrupt */ +#define TM_INT_CH7CC 0x80000000ul /*!< Channel 7 compare interrupt */ +#endif +#define TM_INT_UEV 0x0100 /*!< Update interrupt */ +#define TM_INT_UEV2 0x0200 /*!< Update interrupt 2 */ +#define TM_INT_TEV 0x0400 /*!< Trigger interrupt */ +#define TM_INT_BRKEV 0x0800 /*!< Break interrupt */ + +#if (LIBCFG_TM_652XX_V1) +#define MCTM_INT_CH0CD 0x100000 /*!< Channel 0 Count-Down compare interrupt */ +#define MCTM_INT_CH1CD 0x200000 /*!< Channel 1 Count-Down compare interrupt */ +#define MCTM_INT_CH2CD 0x400000 /*!< Channel 2 Count-Down compare interrupt */ +#define MCTM_INT_CH3CD 0x800000 /*!< Channel 3 Count-Down compare interrupt */ + +#define TM_INT_VC 0x1000 /*!< Quadrature Decoder VCLK interrupt */ +#define TM_INT_QC 0x2000 /*!< Quadrature Decoder CLKPULSE interrupt */ +#define TM_INT_PE 0x4000 /*!< Quadrature Decoder Phase Error interrupt */ +#define TM_INT_DC 0x8000 /*!< Quadrature Decoder Direction Change interrupt */ + +#define MCTM_INT_OVER 0x2000 /*!< Counter overflow interrupt */ +#define MCTM_INT_UNDER 0x4000 /*!< Counter underflow Interrupt */ +#if (LIBCFG_TM_65232) +#define MCTM_INT_RECCDIF 0x8000 /*!< CCIF or CDIF Interrupt flag control by REPR */ +#endif + +#endif +/** + * @} + */ + +#if (LIBCFG_PDMA) +/** @defgroup TM_PDMA Definitions of TM_PDMA + * @{ + */ +#define TM_PDMA_CH0CC 0x00010000 /*!< Channel 0 capture/compare PDMA request */ +#define TM_PDMA_CH1CC 0x00020000 /*!< Channel 1 capture/compare PDMA request */ +#define TM_PDMA_CH2CC 0x00040000 /*!< Channel 2 capture/compare PDMA request */ +#define TM_PDMA_CH3CC 0x00080000 /*!< Channel 3 capture/compare PDMA request */ +#define TM_PDMA_UEV 0x01000000 /*!< Update PDMA request */ +#define TM_PDMA_UEV2 0x02000000 /*!< Update 2 PDMA request */ +#define TM_PDMA_TEV 0x04000000 /*!< Trigger PDMA request */ +/** + * @} + */ +#endif + +/** @defgroup TM_EVENT Definitions of TM_EVENT + * @{ + */ +#define TM_EVENT_CH0CC 0x0001 /*!< Channel 0 capture/compare event */ +#define TM_EVENT_CH1CC 0x0002 /*!< Channel 1 capture/compare event */ +#define TM_EVENT_CH2CC 0x0004 /*!< Channel 2 capture/compare event */ +#define TM_EVENT_CH3CC 0x0008 /*!< Channel 3 capture/compare event */ +#if (LIBCFG_PWM_8_CHANNEL) +#define TM_EVENT_CH4CC 0x10000000ul /*!< Channel 4 compare event */ +#define TM_EVENT_CH5CC 0x20000000ul /*!< Channel 5 compare event */ +#define TM_EVENT_CH6CC 0x40000000ul /*!< Channel 6 compare event */ +#define TM_EVENT_CH7CC 0x80000000ul /*!< Channel 7 compare event */ +#endif +#define TM_EVENT_UEV 0x0100 /*!< Update event */ +#define TM_EVENT_UEV2 0x0200 /*!< Update event 2 */ +#define TM_EVENT_TEV 0x0400 /*!< Trigger event */ +#define TM_EVENT_BRKEV 0x0800 /*!< Break event */ +/** + * @} + */ + +/** @defgroup TM_FLAG Definitions of TM_FLAG + * @{ + */ +#define TM_FLAG_CH0CC 0x0001 /*!< Channel 0 capture/compare flag */ +#define TM_FLAG_CH1CC 0x0002 /*!< Channel 1 capture/compare flag */ +#define TM_FLAG_CH2CC 0x0004 /*!< Channel 2 capture/compare flag */ +#define TM_FLAG_CH3CC 0x0008 /*!< Channel 3 capture/compare flag */ +#if (LIBCFG_PWM_8_CHANNEL) +#define TM_FLAG_CH4CC 0x10000000ul /*!< Channel 4 compare flag */ +#define TM_FLAG_CH5CC 0x20000000ul /*!< Channel 5 compare flag */ +#define TM_FLAG_CH6CC 0x40000000ul /*!< Channel 6 compare flag */ +#define TM_FLAG_CH7CC 0x80000000ul /*!< Channel 7 compare flag */ +#endif +#define TM_FLAG_CH0OC 0x0010 /*!< Channel 0 over capture flag */ +#define TM_FLAG_CH1OC 0x0020 /*!< Channel 1 over capture flag */ +#define TM_FLAG_CH2OC 0x0040 /*!< Channel 2 over capture flag */ +#define TM_FLAG_CH3OC 0x0080 /*!< Channel 3 over capture flag */ +#define TM_FLAG_UEV 0x0100 /*!< Update flag */ +#define TM_FLAG_UEV2 0x0200 /*!< Update 2 flag */ +#define TM_FLAG_TEV 0x0400 /*!< Trigger flag */ +#define TM_FLAG_BRK0 0x0800 /*!< Break 0 flag */ +#define TM_FLAG_BRK1 0x1000 /*!< Break 1 flag */ +/** + * @} + */ + +/** @defgroup TM_Check_Parameter Check parameter + * @{ + */ + +/** + * @brief Used to check parameter of the TMx. + */ +#define IS_TM(x) (IS_GPTM0(x) || IS_GPTM1(x) || IS_MCTM0(x) || IS_PWM0(x) || IS_PWM1(x) || IS_PWM2(x) || IS_SCTM(x)) +#if (!LIBCFG_NO_GPTM0) +#define IS_GPTM0(x) (x == HT_GPTM0) +#else +#define IS_GPTM0(x) (0) +#endif + +#if (LIBCFG_GPTM1) +#define IS_GPTM1(x) (x == HT_GPTM1) +#else +#define IS_GPTM1(x) (0) +#endif + +#if (LIBCFG_MCTM0) +#define IS_MCTM0(x) (x == HT_MCTM0) +#else +#define IS_MCTM0(x) (0) +#endif + +#if (LIBCFG_PWM0) +#define IS_PWM0(x) (x == HT_PWM0) +#else +#define IS_PWM0(x) (0) +#endif + +#if (LIBCFG_PWM1) +#define IS_PWM1(x) (x == HT_PWM1) +#else +#define IS_PWM1(x) (0) +#endif + +#if (LIBCFG_PWM2) +#define IS_PWM2(x) (x == HT_PWM2) +#else +#define IS_PWM2(x) (0) +#endif + +#define IS_SCTM(x) (IS_SCTM0(x) || IS_SCTM1(x) || IS_SCTM2(x) || IS_SCTM3(x)) + +#define IS_SCTM0(x) (0) +#define IS_SCTM1(x) (0) +#define IS_SCTM2(x) (0) +#define IS_SCTM3(x) (0) + +#if (LIBCFG_SCTM0) +#undef IS_SCTM0 +#define IS_SCTM0(x) (x == HT_SCTM0) +#endif + +#if (LIBCFG_SCTM1) +#undef IS_SCTM1 +#define IS_SCTM1(x) (x == HT_SCTM1) +#endif + +#if (LIBCFG_SCTM2) +#undef IS_SCTM2 +#define IS_SCTM2(x) (x == HT_SCTM2) +#endif + +#if (LIBCFG_SCTM3) +#undef IS_SCTM3 +#define IS_SCTM3(x) (x == HT_SCTM3) +#endif + +/** + * @brief Used to check parameter of the output compare mode. + */ +#define IS_TM_OM_CMP(x) (((x) == TM_OM_MATCH_NOCHANGE) || \ + ((x) == TM_OM_MATCH_INACTIVE) || \ + ((x) == TM_OM_MATCH_ACTIVE) || \ + ((x) == TM_OM_MATCH_TOGGLE) || \ + ((x) == TM_OM_PWM1) || \ + ((x) == TM_OM_PWM2)) +/** + * @brief Used to check parameter of the output mode. + */ +#define IS_TM_OM(x) (((x) == TM_OM_MATCH_NOCHANGE) || \ + ((x) == TM_OM_MATCH_INACTIVE) || \ + ((x) == TM_OM_MATCH_ACTIVE) || \ + ((x) == TM_OM_MATCH_TOGGLE) || \ + ((x) == TM_OM_PWM1) || \ + ((x) == TM_OM_PWM2) || \ + ((x) == TM_OM_FORCED_INACTIVE) || \ + ((x) == TM_OM_FORCED_ACTIVE) || \ + ((x) == TM_OM_ASYMMETRIC_PWM1) || \ + ((x) == TM_OM_ASYMMETRIC_PWM2)) + +#define IS_TM_OM_NOASYM(x) (((x) == TM_OM_MATCH_NOCHANGE) || \ + ((x) == TM_OM_MATCH_INACTIVE) || \ + ((x) == TM_OM_MATCH_ACTIVE) || \ + ((x) == TM_OM_MATCH_TOGGLE) || \ + ((x) == TM_OM_PWM1) || \ + ((x) == TM_OM_PWM2) || \ + ((x) == TM_OM_FORCED_INACTIVE) || \ + ((x) == TM_OM_FORCED_ACTIVE)) +/** + * @brief Used to check parameter of the channel. + */ +#define IS_TM_CH_0(x) (x == TM_CH_0) +#define IS_TM_CH_1(x) (x == TM_CH_1) +#define IS_TM_CH_2(x) (x == TM_CH_2) +#define IS_TM_CH_3(x) (x == TM_CH_3) +#if (LIBCFG_PWM_8_CHANNEL) +#define IS_TM_CH_4(x) (x == TM_CH_4) +#define IS_TM_CH_5(x) (x == TM_CH_5) +#define IS_TM_CH_6(x) (x == TM_CH_6) +#define IS_TM_CH_7(x) (x == TM_CH_7) +#else +#define IS_TM_CH_4(x) (0) +#define IS_TM_CH_5(x) (0) +#define IS_TM_CH_6(x) (0) +#define IS_TM_CH_7(x) (0) +#endif +#define IS_TM_CH(x) (IS_TM_CH_0(x) || IS_TM_CH_1(x) || \ + IS_TM_CH_2(x) || IS_TM_CH_3(x) || \ + IS_TM_CH_4(x) || IS_TM_CH_5(x) || \ + IS_TM_CH_6(x) || IS_TM_CH_7(x) ) + +/** + * @brief Used to check parameter of the channel for PWM input function. + */ +#define IS_TM_CH_PWMI(x) (((x) == TM_CH_0) || ((x) == TM_CH_1)) +/** + * @brief Used to check parameter of the clock divider. + */ +#define IS_TM_CKDIV_OFF(x) (x == TM_CKDIV_OFF) +#define IS_TM_CKDIV_2(x) (x == TM_CKDIV_2) +#define IS_TM_CKDIV_4(x) (x == TM_CKDIV_4) + +#if (LIBCFG_TM_CKDIV_8) +#define IS_TM_CKDIV_8(x) (x == TM_CKDIV_8) +#else +#define IS_TM_CKDIV_8(x) (0) +#endif + +#define IS_TM_CKDIV(x) (IS_TM_CKDIV_OFF(x) || \ + IS_TM_CKDIV_2(x) || \ + IS_TM_CKDIV_4(x) || \ + IS_TM_CKDIV_8(x)) +/** + * @brief Used to check parameter of the counter mode. + */ +#define IS_TM_CNT_MODE(x) ((x == TM_CNT_MODE_UP) || \ + (x == TM_CNT_MODE_CA1) || \ + (x == TM_CNT_MODE_CA2) || \ + (x == TM_CNT_MODE_CA3) || \ + (x == TM_CNT_MODE_DOWN)) +/** + * @brief Used to check parameter of the channel polarity. + */ +#define IS_TM_CHP(x) ((x == TM_CHP_NONINVERTED) || (x == TM_CHP_INVERTED)) +/** + * @brief Used to check parameter of the channel control. + */ +#define IS_TM_CHCTL(x) ((x == TM_CHCTL_DISABLE) || (x == TM_CHCTL_ENABLE)) +/** + * @brief Used to check parameter of the channel capture / compare PDMA selection. + */ +#define IS_TM_CHCCDS(x) ((x == TM_CHCCDS_CHCCEV) || (x == TM_CHCCDS_UEV)) +/** + * @brief Used to check parameter of the channel input selection. + */ +#define IS_TM_CHCCS(x) ((x == TM_CHCCS_DIRECT) || \ + (x == TM_CHCCS_INDIRECT) || \ + (x == TM_CHCCS_TRCED)) +/** + * @brief Used to check parameter of the channel capture prescaler. + */ +#define IS_TM_CHPSC(x) ((x == TM_CHPSC_OFF) || \ + (x == TM_CHPSC_2) || \ + (x == TM_CHPSC_4) || \ + (x == TM_CHPSC_8)) +#if 0 +/** + * @brief Used to check parameter of the ETI prescaler. + */ +#define IS_TM_ETIPSC(x) ((x == TM_ETIPSC_OFF) || \ + (x == TM_ETIPSC_2) || \ + (x == TM_ETIPSC_4) || \ + (x == TM_ETIPSC_8)) +#endif +/** + * @brief Used to check parameter of the TM interrupt. + */ +#define IS_TM_INT(x) (((x & 0xFF0F10F0) == 0x0) && (x != 0)) +/** + * @brief Used to check parameter of the TM PDMA request. + */ +#define IS_TM_PDMA(x) (((x & 0xFAF0FFFF) == 0x0) && (x != 0)) +/** + * @brief Used to check parameter of the TM interrupt for \ref TM_GetIntStatus function. + */ +#define IS_TM_INT_CH0CC(x) (x == TM_INT_CH0CC) +#define IS_TM_INT_CH1CC(x) (x == TM_INT_CH1CC) +#define IS_TM_INT_CH2CC(x) (x == TM_INT_CH2CC) +#define IS_TM_INT_CH3CC(x) (x == TM_INT_CH3CC) +#if (LIBCFG_PWM_8_CHANNEL) +#define IS_TM_INT_CH4CC(x) (x == TM_INT_CH4CC) +#define IS_TM_INT_CH5CC(x) (x == TM_INT_CH5CC) +#define IS_TM_INT_CH6CC(x) (x == TM_INT_CH6CC) +#define IS_TM_INT_CH7CC(x) (x == TM_INT_CH7CC) +#else +#define IS_TM_INT_CH4CC(x) (0) +#define IS_TM_INT_CH5CC(x) (0) +#define IS_TM_INT_CH6CC(x) (0) +#define IS_TM_INT_CH7CC(x) (0) +#endif +#define IS_TM_INT_UEV(x) (x == TM_INT_UEV) +#define IS_TM_INT_UEV2(x) (x == TM_INT_UEV2) +#define IS_TM_INT_TEV(x) (x == TM_INT_TEV) +#define IS_TM_INT_BRKEV(x) (x == TM_INT_BRKEV) +#define IS_TM_GET_INT(x) (IS_TM_INT_CH0CC(x) || \ + IS_TM_INT_CH1CC(x) || \ + IS_TM_INT_CH2CC(x) || \ + IS_TM_INT_CH3CC(x) || \ + IS_TM_INT_CH4CC(x) || \ + IS_TM_INT_CH5CC(x) || \ + IS_TM_INT_CH6CC(x) || \ + IS_TM_INT_CH7CC(x) || \ + IS_TM_INT_UEV(x) || \ + IS_TM_INT_UEV2(x) || \ + IS_TM_INT_TEV(x) || \ + IS_TM_INT_BRKEV(x)) + +/** + * @brief Used to check parameter of the TM STI selection. + */ +#define IS_TM_TRSEL(x) ((x == TM_TRSEL_UEVG) || \ + (x == TM_TRSEL_TI0S0) || \ + (x == TM_TRSEL_TI1S1) || \ + (x == TM_TRSEL_ETIF) || \ + (x == TM_TRSEL_TI0BED) || \ + IS_TRSEL_ITI0(x) || \ + IS_TRSEL_ITI1(x) || \ + IS_TRSEL_ITI2(x)) +/** + * @brief Used to check parameter of the ITI. + */ +#if (LIBCFG_TM_NO_ITI == 1) +#else +#define IS_TM_ITI(x) ((x == TM_TRSEL_ITI0) || (x == TM_TRSEL_ITI1) || (x == TM_TRSEL_ITI2)) +#endif +/** + * @brief Used to check parameter of the TM_TRSEL for \ref TM_ChExternalClockConfig function. + */ +#define IS_TM_TRSEL_CH(x) ((x == TM_TRSEL_TI0S0) || (x == TM_TRSEL_TI1S1) || \ + (x == TM_TRSEL_TI0BED)) +/** + * @brief Used to check parameter of the TM ETI polarity. + */ +#define IS_TM_ETIPOL(x) ((x == TM_ETIPOL_NONINVERTED) || (x == TM_ETIPOL_INVERTED)) +/** + * @brief Used to check parameter of the TM prescaler reload time. + */ +#define IS_TM_PSC_RLD(x) ((x == TM_PSC_RLD_UPDATE) || (x == TM_PSC_RLD_IMMEDIATE)) +/** + * @brief Used to check parameter of the forced action. + */ +#define IS_TM_OM_FORCED(x) ((x == TM_OM_FORCED_ACTIVE) || (x == TM_OM_FORCED_INACTIVE)) +/** + * @brief Used to check parameter of the decoder mode. + */ +#define IS_TM_SMSEL_DECODER(x) ((x == TM_SMSEL_DECODER1) || (x == TM_SMSEL_DECODER2) || \ + (x == TM_SMSEL_DECODER3)) +/** + * @brief Used to check parameter of the event. + */ +#define IS_TM_EVENT(x) (((x & 0xFFFFFAF0) == 0x0000) && (x != 0x0000)) +/** + * @brief Used to check parameter of the TM master mode selection. + */ +#define IS_TM_MMSEL_RESET(x) (x == TM_MMSEL_RESET) +#define IS_TM_MMSEL_ENABLE(x) (x == TM_MMSEL_ENABLE) +#define IS_TM_MMSEL_UPDATE(x) (x == TM_MMSEL_UPDATE) +#define IS_TM_MMSEL_CH0CC(x) (x == TM_MMSEL_CH0CC) +#define IS_TM_MMSEL_CH0OREF(x) (x == TM_MMSEL_CH0OREF) +#define IS_TM_MMSEL_CH1OREF(x) (x == TM_MMSEL_CH1OREF) +#define IS_TM_MMSEL_CH2OREF(x) (x == TM_MMSEL_CH2OREF) +#define IS_TM_MMSEL_CH3OREF(x) (x == TM_MMSEL_CH3OREF) +#if (LIBCFG_PWM_8_CHANNEL) +#define IS_TM_MMSEL_CH4OREF(x) (x == TM_MMSEL_CH4OREF) +#define IS_TM_MMSEL_CH5OREF(x) (x == TM_MMSEL_CH5OREF) +#define IS_TM_MMSEL_CH6OREF(x) (x == TM_MMSEL_CH6OREF) +#define IS_TM_MMSEL_CH7OREF(x) (x == TM_MMSEL_CH7OREF) +#else +#define IS_TM_MMSEL_CH4OREF(x) (0) +#define IS_TM_MMSEL_CH5OREF(x) (0) +#define IS_TM_MMSEL_CH6OREF(x) (0) +#define IS_TM_MMSEL_CH7OREF(x) (0) +#endif +#define IS_TM_MMSEL(x) (IS_TM_MMSEL_RESET(x) || \ + IS_TM_MMSEL_ENABLE(x) || \ + IS_TM_MMSEL_UPDATE(x) || \ + IS_TM_MMSEL_CH0CC(x) || \ + IS_TM_MMSEL_CH0OREF(x) || \ + IS_TM_MMSEL_CH1OREF(x) || \ + IS_TM_MMSEL_CH2OREF(x) || \ + IS_TM_MMSEL_CH3OREF(x) || \ + IS_TM_MMSEL_CH4OREF(x) || \ + IS_TM_MMSEL_CH5OREF(x) || \ + IS_TM_MMSEL_CH6OREF(x) || \ + IS_TM_MMSEL_CH7OREF(x)) + +/** + * @brief Used to check parameter of the TM slave mode. + */ +#define IS_TM_SLAVE_MODE(x) ((x == TM_SMSEL_RESTART) || (x == TM_SMSEL_PAUSE) || \ + (x == TM_SMSEL_TRIGGER) || (x == TM_SMSEL_STIED)) +/** + * @brief Used to check parameter of the TM flag. + */ +#define IS_TM_FLAG_CH0CC(x) (x == TM_FLAG_CH0CC) +#define IS_TM_FLAG_CH1CC(x) (x == TM_FLAG_CH1CC) +#define IS_TM_FLAG_CH2CC(x) (x == TM_FLAG_CH2CC) +#define IS_TM_FLAG_CH3CC(x) (x == TM_FLAG_CH3CC) +#if (LIBCFG_PWM_8_CHANNEL) +#define IS_TM_FLAG_CH4CC(x) (x == TM_FLAG_CH4CC) +#define IS_TM_FLAG_CH5CC(x) (x == TM_FLAG_CH5CC) +#define IS_TM_FLAG_CH6CC(x) (x == TM_FLAG_CH6CC) +#define IS_TM_FLAG_CH7CC(x) (x == TM_FLAG_CH7CC) +#else +#define IS_TM_FLAG_CH4CC(x) (0) +#define IS_TM_FLAG_CH5CC(x) (0) +#define IS_TM_FLAG_CH6CC(x) (0) +#define IS_TM_FLAG_CH7CC(x) (0) +#endif +#define IS_TM_FLAG_CH0OC(x) (x == TM_FLAG_CH0OC) +#define IS_TM_FLAG_CH1OC(x) (x == TM_FLAG_CH1OC) +#define IS_TM_FLAG_CH2OC(x) (x == TM_FLAG_CH2OC) +#define IS_TM_FLAG_CH3OC(x) (x == TM_FLAG_CH3OC) +#define IS_TM_FLAG_UEV(x) (x == TM_FLAG_UEV) +#define IS_TM_FLAG_UEV2(x) (x == TM_FLAG_UEV2) +#define IS_TM_FLAG_TEV(x) (x == TM_FLAG_TEV) +#define IS_TM_FLAG_BRK0(x) (x == TM_FLAG_BRK0) +#define IS_TM_FLAG_BRK1(x) (x == TM_FLAG_BRK1) +#define IS_TM_FLAG(x) (IS_TM_FLAG_CH0CC(x) || \ + IS_TM_FLAG_CH1CC(x) || \ + IS_TM_FLAG_CH2CC(x) || \ + IS_TM_FLAG_CH3CC(x) || \ + IS_TM_FLAG_CH4CC(x) || \ + IS_TM_FLAG_CH5CC(x) || \ + IS_TM_FLAG_CH6CC(x) || \ + IS_TM_FLAG_CH7CC(x) || \ + IS_TM_FLAG_CH0OC(x) || \ + IS_TM_FLAG_CH1OC(x) || \ + IS_TM_FLAG_CH2OC(x) || \ + IS_TM_FLAG_CH3OC(x) || \ + IS_TM_FLAG_UEV(x) || \ + IS_TM_FLAG_UEV2(x) || \ + IS_TM_FLAG_TEV(x) || \ + IS_TM_FLAG_BRK0(x) || \ + IS_TM_FLAG_BRK1(x)) + +/** + * @brief Used to check parameter of the TM flag for \ref TM_ClearFlag function. + */ +#define IS_TM_FLAG_CLR(x) (((x & 0xFFFFFA00) == 0) && (x != 0)) +/** + * @brief Used to check value of TM digital filter. + */ +#if (LIBCFG_TM_652XX_V1) +#define IS_TM_FILTER(x) (x <= 0xFF) +#else +#define IS_TM_FILTER(x) (x <= 0xF) +#endif + +/** + * @} + */ + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------------------------------------*/ +/** @defgroup TM_Exported_Functions TM exported functions + * @{ + */ +#define TM_SetCaptureCompare0(TMx, Cmp) TM_SetCaptureCompare(TMx, TM_CH_0, Cmp) +#define TM_SetCaptureCompare1(TMx, Cmp) TM_SetCaptureCompare(TMx, TM_CH_1, Cmp) +#define TM_SetCaptureCompare2(TMx, Cmp) TM_SetCaptureCompare(TMx, TM_CH_2, Cmp) +#define TM_SetCaptureCompare3(TMx, Cmp) TM_SetCaptureCompare(TMx, TM_CH_3, Cmp) +#if (LIBCFG_PWM_8_CHANNEL) +#define TM_SetCaptureCompare4(TMx, Cmp) TM_SetCaptureCompare(TMx, TM_CH_4, Cmp) +#define TM_SetCaptureCompare5(TMx, Cmp) TM_SetCaptureCompare(TMx, TM_CH_5, Cmp) +#define TM_SetCaptureCompare6(TMx, Cmp) TM_SetCaptureCompare(TMx, TM_CH_6, Cmp) +#define TM_SetCaptureCompare7(TMx, Cmp) TM_SetCaptureCompare(TMx, TM_CH_7, Cmp) +#endif + +#define TM_ForcedOREF0(TMx, ForcedAction) TM_ForcedOREF(TMx, TM_CH_0, ForcedAction) +#define TM_ForcedOREF1(TMx, ForcedAction) TM_ForcedOREF(TMx, TM_CH_1, ForcedAction) +#define TM_ForcedOREF2(TMx, ForcedAction) TM_ForcedOREF(TMx, TM_CH_2, ForcedAction) +#define TM_ForcedOREF3(TMx, ForcedAction) TM_ForcedOREF(TMx, TM_CH_3, ForcedAction) +#if (LIBCFG_PWM_8_CHANNEL) +#define TM_ForcedOREF4(TMx, ForcedAction) TM_ForcedOREF(TMx, TM_CH_4, ForcedAction) +#define TM_ForcedOREF5(TMx, ForcedAction) TM_ForcedOREF(TMx, TM_CH_5, ForcedAction) +#define TM_ForcedOREF6(TMx, ForcedAction) TM_ForcedOREF(TMx, TM_CH_6, ForcedAction) +#define TM_ForcedOREF7(TMx, ForcedAction) TM_ForcedOREF(TMx, TM_CH_7, ForcedAction) +#endif + +#define TM_SetAsymmetricCompare0(TMx, Cmp) TM_SetAsymmetricCompare(TMx, TM_CH_0, Cmp) +#define TM_SetAsymmetricCompare1(TMx, Cmp) TM_SetAsymmetricCompare(TMx, TM_CH_1, Cmp) +#define TM_SetAsymmetricCompare2(TMx, Cmp) TM_SetAsymmetricCompare(TMx, TM_CH_2, Cmp) +#define TM_SetAsymmetricCompare3(TMx, Cmp) TM_SetAsymmetricCompare(TMx, TM_CH_3, Cmp) + +#define TM_GetCaptureCompare0(TMx) TM_GetCaptureCompare(TMx, TM_CH_0) +#define TM_GetCaptureCompare1(TMx) TM_GetCaptureCompare(TMx, TM_CH_1) +#define TM_GetCaptureCompare2(TMx) TM_GetCaptureCompare(TMx, TM_CH_2) +#define TM_GetCaptureCompare3(TMx) TM_GetCaptureCompare(TMx, TM_CH_3) +#if (LIBCFG_PWM_8_CHANNEL) +#define TM_GetCaptureCompare4(TMx) TM_GetCaptureCompare(TMx, TM_CH_4) +#define TM_GetCaptureCompare5(TMx) TM_GetCaptureCompare(TMx, TM_CH_5) +#define TM_GetCaptureCompare6(TMx) TM_GetCaptureCompare(TMx, TM_CH_6) +#define TM_GetCaptureCompare7(TMx) TM_GetCaptureCompare(TMx, TM_CH_7) +#endif + +void TM_DeInit(HT_TM_TypeDef* TMx); +void TM_TimeBaseInit(HT_TM_TypeDef* TMx, TM_TimeBaseInitTypeDef* TimeBaseInit); +void TM_OutputInit(HT_TM_TypeDef* TMx, TM_OutputInitTypeDef* OutInit); +void TM_CaptureInit(HT_TM_TypeDef* TMx, TM_CaptureInitTypeDef* CapInit); +void TM_PwmInputInit(HT_TM_TypeDef* TMx, TM_CaptureInitTypeDef* CapInit); +void TM_TimeBaseStructInit(TM_TimeBaseInitTypeDef* TimeBaseInit); +void TM_OutputStructInit(TM_OutputInitTypeDef* OutInit); +void TM_CaptureStructInit(TM_CaptureInitTypeDef* CapInit); +void TM_Cmd(HT_TM_TypeDef* TMx, ControlStatus NewState); +#if (LIBCFG_TM_NO_ITI == 1) +#else +void TM_ItiExternalClockConfig(HT_TM_TypeDef* TMx, TM_TRSEL_Enum Iti); +#endif +void TM_ChExternalClockConfig(HT_TM_TypeDef* TMx, TM_TRSEL_Enum Sel, TM_CHP_Enum Pol, u8 Filter); +#if 0 // M0+ not supported +void TM_EtiExternalClockConfig(HT_TM_TypeDef* TMx, TM_ETIPSC_Enum Psc, TM_ETIPOL_Enum Pol, u8 Filter); +void TM_EtiConfig(HT_TM_TypeDef* TMx, TM_ETIPSC_Enum Psc, TM_ETIPOL_Enum Pol, u8 Filter); +#endif +void TM_PrescalerConfig(HT_TM_TypeDef* TMx, u16 Psc, TM_PSC_RLD_Enum PscReloadTime); +void TM_CounterModeConfig(HT_TM_TypeDef* TMx, TM_CNT_MODE_Enum Mod); +void TM_StiConfig(HT_TM_TypeDef* TMx, TM_TRSEL_Enum Sel); +void TM_DecoderConfig(HT_TM_TypeDef* TMx, TM_SMSEL_Enum DecoderMod, TM_CHP_Enum CH0P, TM_CHP_Enum CH1P); + +void TM_ForcedOREF(HT_TM_TypeDef* TMx, TM_CH_Enum TM_CH_n, TM_OM_Enum ForcedAction); +void TM_CRRPreloadCmd(HT_TM_TypeDef* TMx, ControlStatus NewState); +void TM_CHCCRPreloadConfig(HT_TM_TypeDef* TMx, TM_CH_Enum Channel, ControlStatus NewState); +void TM_ClearOREFConfig(HT_TM_TypeDef* TMx, TM_CH_Enum Channel, ControlStatus NewState); +void TM_ChPolarityConfig(HT_TM_TypeDef* TMx, TM_CH_Enum Channel, TM_CHP_Enum Pol); + +void TM_ImmActiveConfig(HT_TM_TypeDef* TMx, TM_CH_Enum Channel, ControlStatus NewState); +void TM_ChannelConfig(HT_TM_TypeDef* TMx, TM_CH_Enum Channel, TM_CHCTL_Enum Control); + +void TM_OutputModeConfig(HT_TM_TypeDef* TMx, TM_CH_Enum Channel, TM_OM_Enum Mod); +void TM_UpdateCmd(HT_TM_TypeDef* TMx, ControlStatus NewState); +void TM_UEVG_IntConfig(HT_TM_TypeDef* TMx, ControlStatus NewState); +void TM_HallInterfaceCmd(HT_TM_TypeDef* TMx, ControlStatus NewState); +void TM_SinglePulseModeCmd(HT_TM_TypeDef* TMx, ControlStatus NewState); +void TM_MMSELConfig(HT_TM_TypeDef* TMx, TM_MMSEL_Enum Sel); +void TM_SlaveModeConfig(HT_TM_TypeDef* TMx, TM_SMSEL_Enum Sel); +void TM_TimSyncCmd(HT_TM_TypeDef* TMx, ControlStatus NewState); +void TM_SetCounter(HT_TM_TypeDef* TMx, u16 Counter); +void TM_SetCounterReload(HT_TM_TypeDef* TMx, u16 Reload); +void TM_SetCaptureCompare(HT_TM_TypeDef* TMx, TM_CH_Enum TM_CH_n, u16 Cmp); +void TM_SetAsymmetricCompare(HT_TM_TypeDef* TMx, TM_CH_Enum TM_CH_n, u16 Cmp); + +void TM_CHPSCConfig(HT_TM_TypeDef* TMx, TM_CH_Enum Channel, TM_CHPSC_Enum Psc); +void TM_CKDIVConfig(HT_TM_TypeDef* TMx, TM_CKDIV_Enum Div); +u32 TM_GetCaptureCompare(HT_TM_TypeDef* TMx, TM_CH_Enum TM_CH_n); +u32 TM_GetCounter(HT_TM_TypeDef* TMx); +u32 TM_GetPrescaler(HT_TM_TypeDef* TMx); +void TM_GenerateEvent(HT_TM_TypeDef* TMx, u32 TM_EVENT); +FlagStatus TM_GetFlagStatus(HT_TM_TypeDef* TMx, u32 TM_FLAG); +void TM_ClearFlag(HT_TM_TypeDef* TMx, u32 TM_FLAG); +void TM_IntConfig(HT_TM_TypeDef* TMx, u32 TM_INT, ControlStatus NewState); +FlagStatus TM_GetIntStatus(HT_TM_TypeDef* TMx, u32 TM_INT); +void TM_ClearIntPendingBit(HT_TM_TypeDef* TMx, u32 TM_INT); +void TM_InternalClockConfig(HT_TM_TypeDef* TMx); + +#if (LIBCFG_PDMA) +void TM_CHCCDSConfig(HT_TM_TypeDef* TMx, TM_CHCCDS_Enum Selection); +void TM_PDMAConfig(HT_TM_TypeDef* TMx, u32 TM_PDMA, ControlStatus NewState); +#endif +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f5xxxx_tm_type.h b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f5xxxx_tm_type.h new file mode 100644 index 0000000000..a6ef678b37 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f5xxxx_tm_type.h @@ -0,0 +1,129 @@ +/*********************************************************************************************************//** + * @file ht32f5xxxx_tm_type.h + * @version $Rev:: 7319 $ + * @date $Date:: 2023-10-28 #$ + * @brief The header file of the TM library. + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------------------------------------*/ +#ifndef __HT32F5XXXX_TM_TYPE_H +#define __HT32F5XXXX_TM_TYPE_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------------------------------------*/ +#include "ht32.h" + +/** @addtogroup HT32F5xxxx_Peripheral_Driver HT32F5xxxx Peripheral Driver + * @{ + */ + +/** @addtogroup TM + * @{ + */ + + +/* Exported types ------------------------------------------------------------------------------------------*/ +/** @defgroup TM_Exported_Types TM exported types + * @{ + */ +/** + * @brief Enumeration of TM channel. + */ +typedef enum +{ + TM_CH_0 = 0, /*!< TM channel 0 */ + TM_CH_1, /*!< TM channel 1 */ + TM_CH_2, /*!< TM channel 2 */ + TM_CH_3, /*!< TM channel 3 */ +#if (LIBCFG_PWM_8_CHANNEL) + TM_CH_4, /*!< TM channel 4 */ + TM_CH_5, /*!< TM channel 5 */ + TM_CH_6, /*!< TM channel 6 */ + TM_CH_7, /*!< TM channel 7 */ +#endif +} TM_CH_Enum; +/** + * @brief Enumeration of TM channel control. + */ +typedef enum +{ + TM_CHCTL_DISABLE = 0, /*!< TM channel disable */ + TM_CHCTL_ENABLE /*!< TM channel enable */ +} TM_CHCTL_Enum; +/** + * @brief Enumeration of TM channel polarity. + */ +typedef enum +{ + TM_CHP_NONINVERTED = 0, /*!< TM channel polarity is active high or rising edge */ + TM_CHP_INVERTED /*!< TM channel polarity is active low or falling edge */ +} TM_CHP_Enum; +/** + * @brief Enumeration of MCTM channel output idle state. + */ +typedef enum +{ + MCTM_OIS_LOW = 0, /*!< MCTM channel output low when CHMOE equal to 0 */ + MCTM_OIS_HIGH /*!< MCTM channel output high when CHMOE equal to 0 */ +} MCTM_OIS_Enum; +/** + * @brief Enumeration of MCTM COMUS. + */ +typedef enum +{ + MCTM_COMUS_STIOFF = 0, /*!< MCTM capture/compare control bits are updated by + setting the UEV2G bit only */ + MCTM_COMUS_STION /*!< MCTM capture/compare control bits are updated by both + setting the UEV2G bit or when a rising edge occurs on STI */ +} MCTM_COMUS_Enum; +#if (LIBCFG_MCTM_UEV1DIS) +/** + * @brief Enumeration of MCTM update event1 disasble. + */ +typedef enum +{ + MCTM_UEV1UD = 0x00000004, /*!< MCTM update event 1 rquest by overflow disable control */ + MCTM_UEV1OD = 0x00000008, /*!< MCTM update event 1 rquest by underflow disable control */ +} MCTM_UEV1DIS_Enum; +#endif +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f5xxxx_usart.h b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f5xxxx_usart.h new file mode 100644 index 0000000000..bb0d75fe15 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f5xxxx_usart.h @@ -0,0 +1,499 @@ +/*********************************************************************************************************//** + * @file ht32f5xxxx_usart.h + * @version $Rev:: 7107 $ + * @date $Date:: 2023-08-08 #$ + * @brief The header file of the USART library. + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------------------------------------*/ +#ifndef __HT32F5XXXX_USART_H +#define __HT32F5XXXX_USART_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------------------------------------*/ +#include "ht32.h" + +/** @addtogroup HT32F5xxxx_Peripheral_Driver HT32F5xxxx Peripheral Driver + * @{ + */ + +/** @addtogroup USART + * @{ + */ + + +/* Exported types ------------------------------------------------------------------------------------------*/ +/** @defgroup USART_Exported_Types USART exported types + * @{ + */ +/* Definition of USART Init Structure ---------------------------------------------------------------------*/ +typedef struct +{ + u32 USART_BaudRate; + u16 USART_WordLength; + u16 USART_StopBits; + u16 USART_Parity; + u32 USART_Mode; +} USART_InitTypeDef; + +typedef struct +{ + u16 USART_ClockEnable; + u16 USART_ClockPhase; + u16 USART_ClockPolarity; + u16 USART_TransferSelectMode; +} USART_SynClock_InitTypeDef; +/** + * @} + */ + +/* Exported constants --------------------------------------------------------------------------------------*/ +/** @defgroup USART_Exported_Constants USART exported constants + * @{ + */ + +#define USART_CMD_TX (0) +#define USART_CMD_RX (1) + +#define USART_CMD_OUT (0) +#define USART_CMD_IN (1) + +/* USART Word Length ---------------------------------------------------------------------------------------*/ +/** @defgroup USART_Word_Length Definitions of USART word length + * @{ + */ +#define USART_WORDLENGTH_7B ((u32)0x00000000) +#define USART_WORDLENGTH_8B ((u32)0x00000100) +#define USART_WORDLENGTH_9B ((u32)0x00000200) + +#define IS_USART_WORD_LENGTH(LENGTH) ((LENGTH == USART_WORDLENGTH_9B) || \ + (LENGTH == USART_WORDLENGTH_8B) || \ + (LENGTH == USART_WORDLENGTH_7B)) +/** + * @} + */ + +/* USART Stop Bits -----------------------------------------------------------------------------------------*/ +/** @defgroup USART_Stop_Bit Definitions of USART stop bit + * @{ + */ +#define USART_STOPBITS_1 ((u32)0x00000000) +#define USART_STOPBITS_2 ((u32)0x00000400) + + +#define IS_USART_STOPBITS(STOPBITS) ((STOPBITS == USART_STOPBITS_1) || \ + (STOPBITS == USART_STOPBITS_2)) +/** + * @} + */ + +/* USART Parity --------------------------------------------------------------------------------------------*/ +/** @defgroup USART_Parity Definitions of USART parity + * @{ + */ +#define USART_PARITY_NO ((u32)0x00000000) +#define USART_PARITY_EVEN ((u32)0x00001800) +#define USART_PARITY_ODD ((u32)0x00000800) +#define USART_PARITY_MARK ((u32)0x00002800) +#define USART_PARITY_SPACE ((u32)0x00003800) + +#define IS_USART_PARITY(PARITY) ((PARITY == USART_PARITY_NO) || \ + (PARITY == USART_PARITY_EVEN) || \ + (PARITY == USART_PARITY_ODD)) +/** + * @} + */ + +/* USART Mode ----------------------------------------------------------------------------------------------*/ +/** @defgroup USART_Mode Definitions of USART mode + * @{ + */ +#define USART_MODE_NORMAL ((u32)0x00000000) +#define USART_MODE_IRDA ((u32)0x00000001) +#define USART_MODE_RS485 ((u32)0x00000002) +#define USART_MODE_SYNCHRONOUS ((u32)0x00000003) +#if (LIBCFG_USART_LIN) +#define USART_MODE_LIN ((u32)0x00010000) +#define IS_MODE_LIN(x) (x == USART_MODE_LIN) +#else +#define IS_MODE_LIN(x) (0) +#endif +#if (LIBCFG_USART_SINGLE_WIRE) +#define USART_MODE_SINGLE_WIRE ((u32)0x00010001) +#define IS_MODE_SINGLE_WIRE(x) (x == USART_MODE_SINGLE_WIRE) +#else +#define IS_MODE_SINGLE_WIRE(x) (0) +#endif +#define IS_USART_MODE(MODE) ((MODE == USART_MODE_NORMAL) || \ + (MODE == USART_MODE_IRDA) || \ + (MODE == USART_MODE_RS485) || \ + (MODE == USART_MODE_SYNCHRONOUS) || \ + IS_MODE_LIN(MODE) || \ + IS_MODE_SINGLE_WIRE(MODE)) +/** + * @} + */ + +/* USART Transfer Select Mode ------------------------------------------------------------------------------*/ +/** @defgroup USART_LSB Definitions of USART LSB + * @{ + */ +#define USART_LSB_FIRST ((u32)0x00000000) +#define USART_MSB_FIRST ((u32)0x00000004) + +#define IS_USART_TRANSFER_MODE(TMODE) ((TMODE == USART_LSB_FIRST) || \ + (TMODE == USART_MSB_FIRST)) +/** + * @} + */ + + +/* USART Synchronous Clock ---------------------------------------------------------------------------------*/ +/** @defgroup USART_Synchronous_Clock Definitions of USART synchronous clock + * @{ + */ +#define USART_SYN_CLOCK_DISABLE ((u32)0x00000000) +#define USART_SYN_CLOCK_ENABLE ((u32)0x00000001) + +#define IS_USART_SYNCHRONOUS_CLOCK(SYNCLOCK) ((SYNCLOCK == USART_SYN_CLOCK_DISABLE) || \ + (SYNCLOCK == USART_SYN_CLOCK_ENABLE)) +/** + * @} + */ + +/* USART Synchronous Clock Phase ---------------------------------------------------------------------------*/ +/** @defgroup USART_Synchronous_Clock_Phase Definitions of USART Synchronous clock phase + * @{ + */ +#define USART_SYN_CLOCK_PHASE_FIRST ((u32)0x00000000) +#define USART_SYN_CLOCK_PHASE_SECOND ((u32)0x00000004) + +#define IS_USART_SYNCHRONOUS_PHASE(PHASE) ((PHASE == USART_SYN_CLOCK_PHASE_FIRST) || \ + (PHASE == USART_SYN_CLOCK_PHASE_SECOND)) +/** + * @} + */ + +/* USART Clock Polarity ------------------------------------------------------------------------------------*/ +/** @defgroup USART_Clock_Polarity Definitions of USART clock polarity + * @{ + */ +#define USART_SYN_CLOCK_POLARITY_LOW ((u32)0x00000000) +#define USART_SYN_CLOCK_POLARITY_HIGH ((u32)0x00000008) + +#define IS_USART_SYNCHRONOUS_POLARITY(POLARITY) ((POLARITY == USART_SYN_CLOCK_POLARITY_LOW) || \ + (POLARITY == USART_SYN_CLOCK_POLARITY_HIGH)) +/** + * @} + */ + +/* USART IrDA ---------------------------------------------------------------------------------------------*/ +/** @defgroup USART_IrDA Definitions of USART IrDA + * @{ + */ +#define USART_IRDA_LOWPOWER ((u32)0x00000002) +#define USART_IRDA_NORMAL ((u32)0xFFFFFFFD) + +#define IS_USART_IRDA_MODE(MODE) ((MODE == USART_IRDA_LOWPOWER) || \ + (MODE == USART_IRDA_NORMAL)) + +#define USART_IRDA_TX ((u32)0x00000004) +#define USART_IRDA_RX ((u32)0xFFFFFFFB) + +#define IS_USART_IRDA_DIRECTION(DIRECTION) ((DIRECTION == USART_IRDA_TX) || \ + (DIRECTION == USART_IRDA_RX)) +/** + * @} + */ + +#define IS_USART_TL(x) (IS_USART_RXTL(x) || IS_USART_TXTL(x)) + +/* USART Rx FIFO Interrupt Trigger Level -------------------------------------------------------------------*/ +/** @defgroup USART_RX_FIFO_Trigger_Level Definitions of USART Rx FIFO interrupts + * @{ + */ +#define USART_RXTL_01 ((u32)0x00000000) +#define USART_RXTL_02 ((u32)0x00000010) +#define USART_RXTL_04 ((u32)0x00000020) +#define USART_RXTL_06 ((u32)0x00000030) + +#define IS_USART_RXTL(RXTL) ((RXTL == USART_RXTL_01) || \ + (RXTL == USART_RXTL_02) || \ + (RXTL == USART_RXTL_04) || \ + (RXTL == USART_RXTL_06)) +/** + * @} + */ + +/* USART Tx FIFO Interrupt Trigger Level -------------------------------------------------------------------*/ +/** @defgroup USART_TX_FIFO_Trigger_Level Definitions of USART Tx FIFO interrupts + * @{ + */ +#define USART_TXTL_00 ((u32)0x00000000) +#define USART_TXTL_02 ((u32)0x00000010) +#define USART_TXTL_04 ((u32)0x00000020) +#define USART_TXTL_06 ((u32)0x00000030) + +#define IS_USART_TXTL(TXTL) ((TXTL == USART_TXTL_00) || \ + (TXTL == USART_TXTL_02) || \ + (TXTL == USART_TXTL_04) || \ + (TXTL == USART_TXTL_06)) +/** + * @} + */ + +/* USART Interrupt definition ------------------------------------------------------------------------------*/ +/** @defgroup USART_Interrupt_Enable Definitions of USART interrupt Enable bits + * @{ + */ +#define USART_INT_RXDR ((u32)0x00000001) +#define USART_INT_TXDE ((u32)0x00000002) +#define USART_INT_TXC ((u32)0x00000004) +#define USART_INT_OE ((u32)0x00000008) +#define USART_INT_PE ((u32)0x00000010) +#define USART_INT_FE ((u32)0x00000020) +#define USART_INT_BI ((u32)0x00000040) +#define USART_INT_RSADD ((u32)0x00000080) +#define USART_INT_TOUT ((u32)0x00000100) +#define USART_INT_CTS ((u32)0x00000200) +#if (LIBCFG_USART_LIN) +#define USART_INT_LBD ((u32)0x00000400) +#endif + +#if (LIBCFG_USART_LIN) +#define IS_USART_INT(INT) ((((INT) & 0xFFFFF800) == 0) && ((INT) != 0)) +#else +#define IS_USART_INT(INT) ((((INT) & 0xFFFFFC00) == 0) && ((INT) != 0)) +#endif +/** + * @} + */ + +/* USART Flags ---------------------------------------------------------------------------------------------*/ +/** @defgroup USART_Flag Definitions of USART flags + * @{ + */ +#define USART_FLAG_RXDNE ((u32)0x00000001) +#define USART_FLAG_OE ((u32)0x00000002) +#define USART_FLAG_PE ((u32)0x00000004) +#define USART_FLAG_FE ((u32)0x00000008) +#define USART_FLAG_BI ((u32)0x00000010) +#define USART_FLAG_RXDR ((u32)0x00000020) +#define USART_FLAG_TOUT ((u32)0x00000040) +#define USART_FLAG_TXDE ((u32)0x00000080) +#define USART_FLAG_TXC ((u32)0x00000100) +#define USART_FLAG_RSADD ((u32)0x00000200) +#define USART_FLAG_CTSC ((u32)0x00000400) +#define USART_FLAG_CTSS ((u32)0x00000800) +#if (LIBCFG_USART_LIN) +#define USART_FLAG_LBD ((u32)0x00001000) +#define IS_FLAG_LBD(x) (x == USART_FLAG_LBD) +#else +#define IS_FLAG_LBD(x) (0) +#endif + +#define IS_USART_FLAG(FLAG) ((FLAG == USART_FLAG_RXDNE) || (FLAG == USART_FLAG_OE) || \ + (FLAG == USART_FLAG_PE) || (FLAG == USART_FLAG_FE) || \ + (FLAG == USART_FLAG_BI) || (FLAG == USART_FLAG_RXDR) || \ + (FLAG == USART_FLAG_TOUT) || (FLAG == USART_FLAG_TXDE) || \ + (FLAG == USART_FLAG_TXC) || (FLAG == USART_FLAG_RSADD) || \ + (FLAG == USART_FLAG_CTSC) || (FLAG == USART_FLAG_CTSS) || \ + IS_FLAG_LBD(FLAG)) + +#define IS_USART_CLEAR_FLAG(FLAG) ((FLAG == USART_FLAG_OE) || (FLAG == USART_FLAG_PE) || \ + (FLAG == USART_FLAG_FE) || (FLAG == USART_FLAG_BI) || \ + (FLAG == USART_FLAG_TOUT) || (FLAG == USART_FLAG_RSADD) || \ + (FLAG == USART_FLAG_CTSC) || IS_FLAG_LBD(FLAG)) +/** + * @} + */ + +/* USART RS485 definition ----------------------------------------------------------------------------------*/ +/** @defgroup USART_RS485 Definitions of USART RS485 + * @{ + */ +#define USART_RS485POLARITY_LOW ((u32)0x00000001) +#define USART_RS485POLARITY_HIGH ((u32)0xFFFFFFFE) + +#define IS_USART_RS485_POLARITY(POLARITY) ((POLARITY == USART_RS485POLARITY_LOW) || \ + (POLARITY == USART_RS485POLARITY_HIGH)) +/** + * @} + */ + +/* USART LIN definition -----------------------------------------------------------------------------------*/ +/** @defgroup USART_LIN Definitions of USART LIN + * @{ + */ +#if (LIBCFG_USART_LIN) +#define USART_LINSENDBREAK ((u32)0x00020000) + +#define USART_LINLENGTH_10BIT ((u32)0xFFFBFFFF) +#define USART_LINLENGTH_11BIT ((u32)0x00040000) + +#define IS_USART_LINLENGTH(LENGTH) ((LENGTH == USART_LINLENGTH_10BIT) || \ + (LENGTH == USART_LINLENGTH_11BIT)) +#endif +/** + * @} + */ + +#define USART_FIFO_TX ((u32)0x00000001) +#define USART_FIFO_RX ((u32)0x00000002) + +#define IS_USART_FIFO_DIRECTION(DIRECTION) ((DIRECTION == USART_FIFO_TX) || \ + (DIRECTION == USART_FIFO_RX)) + +#define USART_STICK_LOW ((u32)0x00001000) +#define USART_STICK_HIGH ((u32)0xFFFFEFFF) + +#define IS_USART_STICK_PARITY(PARITY) ((PARITY == USART_STICK_LOW) || (PARITY == USART_STICK_HIGH)) + +#if (LIBCFG_PDMA) +#define USART_PDMAREQ_TX ((u32)0x00000040) +#define USART_PDMAREQ_RX ((u32)0x00000080) + +#define IS_USART_PDMA_REQ(REQ) (((REQ & 0xFFFFFF3F) == 0x0) && (REQ != 0x0)) +#endif + +#define IS_USART(x) (IS_USART0(x) || \ + IS_USART1(x) || \ + IS_UART0(x) || \ + IS_UART1(x) || \ + IS_UART2(x) || \ + IS_UART3(x)) +#if (LIBCFG_NO_USART0) +#define IS_USART0(x) (0) +#else +#define IS_USART0(x) (x == HT_USART0) +#endif +#define IS_UART0(x) (x == HT_UART0) +#if (LIBCFG_USART1) +#define IS_USART1(x) (x == HT_USART1) +#else +#define IS_USART1(x) (0) +#endif +#if (LIBCFG_UART1) +#define IS_UART1(x) (x == HT_UART1) +#else +#define IS_UART1(x) (0) +#endif +#if (LIBCFG_UART2) +#define IS_UART2(x) (x == HT_UART2) +#else +#define IS_UART2(x) (0) +#endif +#if (LIBCFG_UART3) +#define IS_UART3(x) (x == HT_UART3) +#else +#define IS_UART3(x) (0) +#endif +#define IS_USART_BAUDRATE(BAUDRATE) ((BAUDRATE > 0) && (BAUDRATE < 0x0044AA21)) +#define IS_USART_DATA(DATA) (DATA <= 0x1FF) +#define IS_USART_GUARD_TIME(TIME) (TIME <= 0xFF) +#define IS_USART_IRDA_PRESCALER(PRESCALER) (PRESCALER <= 0xFF) +#define IS_USART_TIMEOUT(TIMEOUT) (TIMEOUT <= 0x7F) +#define IS_USART_ADDRESS_MATCH_VALUE(VALUE) (VALUE <= 0xFF) +/** + * @} + */ + +/* Exported functions --------------------------------------------------------------------------------------*/ +/** @defgroup USART_Exported_Functions USART exported functions + * @{ + */ +#define USART_TxCmd(USARTx, NewState) USART_TxRxCmd(USARTx, USART_CMD_TX, NewState) +#define USART_RxCmd(USARTx, NewState) USART_TxRxCmd(USARTx, USART_CMD_RX, NewState) + +#define USART_TxPDMACmd(USARTx, NewState) USART_PDMACmd(USARTx, USART_PDMAREQ_TX, NewState) +#define USART_RxPDMACmd(USARTx, NewState) USART_PDMACmd(USARTx, USART_PDMAREQ_RX, NewState) + +#define USART_RXTLConfig(USARTx, USART_tl) USART_TXRXTLConfig(USARTx, USART_CMD_RX, USART_tl) +#define USART_TXTLConfig(USARTx, USART_tl) USART_TXRXTLConfig(USARTx, USART_CMD_TX, USART_tl) + +#define USART_IrDAInvtOutputCmd(USARTx, NewState) USART_IrDAInvtCmd(USARTx, USART_CMD_OUT, NewState) +#define USART_IrDAInvtInputCmd(USARTx, NewState) USART_IrDAInvtCmd(USARTx, USART_CMD_IN, NewState) + +void USART_DeInit(HT_USART_TypeDef* USARTx); +void USART_Init(HT_USART_TypeDef* USARTx, USART_InitTypeDef* USART_InitStructure); +void USART_StructInit(USART_InitTypeDef* USART_InitStructure); +void USART_SendData(HT_USART_TypeDef* USARTx, u16 Data); +u16 USART_ReceiveData(HT_USART_TypeDef* USARTx); +FlagStatus USART_GetFlagStatus(HT_USART_TypeDef* USARTx, u32 USART_FLAG_x); +FlagStatus USART_GetIntStatus(HT_USART_TypeDef* USARTx, u32 USART_FLAG_x); +void USART_ClearFlag(HT_USART_TypeDef* USARTx, u32 USART_Flag); +void USART_IntConfig(HT_USART_TypeDef* USARTx, u32 USART_INT_x, ControlStatus NewState); +void USART_TxRxCmd(HT_USART_TypeDef* USARTx,u32 TxRx, ControlStatus NewState); +#if (LIBCFG_PDMA) +void USART_PDMACmd(HT_USART_TypeDef* USARTx, u32 USART_PDMAREQ, ControlStatus NewState); +#endif +void USART_ForceBreakCmd(HT_USART_TypeDef* USARTx, ControlStatus NewState); +void USART_StickParityCmd(HT_USART_TypeDef* USARTx, ControlStatus NewState); +void USART_StickParityConfig(HT_USART_TypeDef* USARTx, u32 USART_StickParity); + +void USART_SetGuardTime(HT_USART_TypeDef* USARTx, u32 USART_GuardTime); +void USART_TXRXTLConfig(HT_USART_TypeDef* USARTx, u32 TxRx, u32 USART_tl); +void USART_SetTimeOutValue(HT_USART_TypeDef* USARTx, u32 USART_TimeOut); +void USART_FIFOReset(HT_USART_TypeDef* USARTx, u32 USART_FIFODirection); +u8 USART_GetFIFOStatus(HT_USART_TypeDef* USARTx, u32 USART_FIFODirection); +void USART_HardwareFlowControlCmd(HT_USART_TypeDef* USARTx, ControlStatus NewState); + +void USART_IrDACmd(HT_USART_TypeDef* USARTx, ControlStatus NewState); +void USART_IrDAConfig(HT_USART_TypeDef* USARTx, u32 USART_IrDAMode); +void USART_SetIrDAPrescaler(HT_USART_TypeDef* USARTx, u32 USART_IrDAPrescaler); +void USART_IrDADirectionConfig(HT_USART_TypeDef* USARTx, u32 USART_IrDADirection); +void USART_IrDAInvtCmd(HT_USART_TypeDef* USARTx, u32 inout, ControlStatus NewState); + +void USART_RS485TxEnablePolarityConfig(HT_USART_TypeDef* USARTx, u32 USART_RS485Polarity); +void USART_RS485NMMCmd(HT_USART_TypeDef* USARTx, ControlStatus NewState); +void USART_RS485AADCmd(HT_USART_TypeDef* USARTx, ControlStatus NewState); +void USART_SetAddressMatchValue(HT_USART_TypeDef* USARTx, u32 USART_AddressMatchValue); + +void USART_SynClockInit(HT_USART_TypeDef* USARTx, USART_SynClock_InitTypeDef* USART_SynClock_InitStruct); +void USART_SynClockStructInit(USART_SynClock_InitTypeDef* USART_SynClock_InitStruct); + +#if (LIBCFG_USART_LIN) +void USART_LIN_SendBreak(HT_USART_TypeDef* USARTx); +void USART_LIN_LengthSelect(HT_USART_TypeDef* USARTx, u32 USART_LIN_Length); +#endif +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f5xxxx_usbd.h b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f5xxxx_usbd.h new file mode 100644 index 0000000000..c9ebd0e408 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f5xxxx_usbd.h @@ -0,0 +1,346 @@ +/*********************************************************************************************************//** + * @file ht32f5xxxx_usbd.h + * @version $Rev:: 6559 $ + * @date $Date:: 2022-12-18 #$ + * @brief The header file of the USB Device Driver. + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------------------------------------*/ +#ifndef __HT32F5XXXX_USBD_H +#define __HT32F5XXXX_USBD_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------------------------------------*/ +#include "ht32.h" + +#if (LIBCFG_USBD_V2) +#include "ht32f5xxxx_02_usbdconf.h" +#else +#include "ht32f5xxxx_01_usbdconf.h" +#endif +#include "ht32f5xxxx_usbdinit.h" + +/** @addtogroup HT32F5xxxx_Peripheral_Driver HT32F5xxxx Peripheral Driver + * @{ + */ + +/** @defgroup USBDevice USB Device + * @brief USB Device driver modules + * @{ + */ + + +/* Settings ------------------------------------------------------------------------------------------------*/ +/** @defgroup USBDevice_Settings USB Device settings + * @{ + */ +#if (LIBCFG_USBD_V2) +#define MAX_EP_NUM (10) +#else +#define MAX_EP_NUM (8) +#endif +/** + * @} + */ + +/* Exported types ------------------------------------------------------------------------------------------*/ +/** @defgroup USBDevice_Exported_Types USB Device exported types + * @{ + */ +/* USB Endpoint number */ +typedef enum +{ + USBD_EPT0 = 0, + USBD_EPT1 = 1, + USBD_EPT2 = 2, + USBD_EPT3 = 3, + USBD_EPT4 = 4, + USBD_EPT5 = 5, + USBD_EPT6 = 6, + USBD_EPT7 = 7, + #if (LIBCFG_USBD_V2) + USBD_EPT8 = 8, + USBD_EPT9 = 9, + #endif + USBD_NOEPT = -1, +} USBD_EPTn_Enum; + +typedef enum +{ + USBD_TCR_0 = 0, + USBD_TCR_1 = 16, +} USBD_TCR_Enum; + +typedef enum +{ + USBD_NAK = 0, + USBD_ACK = 1 +} USBD_Handshake_Enum; + +/* Endpoint CFGR Register */ +typedef struct _EPTCFGR_BIT +{ + vu32 EPBUFA: 10; + vu32 EPLEN : 10; + vu32 _RES0 : 3; + vu32 SDBS : 1; + vu32 EPADR : 4; + vu32 EPDIR : 1; + vu32 EPTYPE: 1; + vu32 _RES1 : 1; + vu32 EPEN : 1; +} USBD_EPTCFGR_Bit; + +typedef union _EPTCFGR_TYPEDEF +{ + USBD_EPTCFGR_Bit bits; + u32 word; +} USBD_EPTCFGR_TypeDef; + +/* Endpoint CFGR and IER Register */ +typedef struct +{ + USBD_EPTCFGR_TypeDef CFGR; + u32 IER; +} USBD_EPTInit_TypeDef; + +/* Endpoint 0 ~ MAX_EP_NUM */ +typedef struct +{ + u32 uInterruptMask; + USBD_EPTInit_TypeDef ept[MAX_EP_NUM]; +} USBD_Driver_TypeDef; +/** + * @} + */ + +/* Exported constants --------------------------------------------------------------------------------------*/ +/** @defgroup USBDevice_Exported_Constants USB Device exported constants + * @{ + */ + +/* USB Interrupt Enable Register (USBIER) */ +#define UGIE ((u32)0x00000001) /*!< USB global Interrupt Enable */ +#define SOFIE ((u32)0x00000002) /*!< Start Of Frame Interrupt Enable */ +#define URSTIE ((u32)0x00000004) /*!< USB Reset Interrupt Enable */ +#define RSMIE ((u32)0x00000008) /*!< Resume Interrupt Enable */ +#define SUSPIE ((u32)0x00000010) /*!< Suspend Interrupt Enable */ +#define ESOFIE ((u32)0x00000020) /*!< Expected Start Of Frame Interrupt Enable */ +#define FRESIE ((u32)0x00000040) /*!< Force USB Reset Control Interrupt Enable */ +#define EP0IE ((u32)0x00000100) /*!< Endpoint 0 Interrupt Enable */ +#define EP1IE ((u32)0x00000200) /*!< Endpoint 1 Interrupt Enable */ +#define EP2IE ((u32)0x00000400) /*!< Endpoint 2 Interrupt Enable */ +#define EP3IE ((u32)0x00000800) /*!< Endpoint 3 Interrupt Enable */ +#define EP4IE ((u32)0x00001000) /*!< Endpoint 4 Interrupt Enable */ +#define EP5IE ((u32)0x00002000) /*!< Endpoint 5 Interrupt Enable */ +#define EP6IE ((u32)0x00004000) /*!< Endpoint 6 Interrupt Enable */ +#define EP7IE ((u32)0x00008000) /*!< Endpoint 7 Interrupt Enable */ + +/* USB Interrupt Status Register (USBISR) */ +#define SOFIF ((u32)0x00000002) /*!< Start Of Frame Interrupt Flag */ +#define URSTIF ((u32)0x00000004) /*!< USB Reset Interrupt Flag */ +#define RSMIF ((u32)0x00000008) /*!< Resume Interrupt Flag */ +#define SUSPIF ((u32)0x00000010) /*!< Suspend Interrupt Flag */ +#define ESOFIF ((u32)0x00000020) /*!< Expected Start Of Frame Interrupt Flag */ +#define FRESIF ((u32)0x00000040) /*!< Force USB Reset Control Interrupt Flag */ +#define EP0IF ((u32)0x00000100) /*!< Endpoint 0 Interrupt flag */ +#define EP1IF ((u32)0x00000200) /*!< Endpoint 1 Interrupt flag */ +#define EP2IF ((u32)0x00000400) /*!< Endpoint 2 Interrupt flag */ +#define EP3IF ((u32)0x00000800) /*!< Endpoint 3 Interrupt flag */ +#define EP4IF ((u32)0x00001000) /*!< Endpoint 4 Interrupt flag */ +#define EP5IF ((u32)0x00002000) /*!< Endpoint 5 Interrupt flag */ +#define EP6IF ((u32)0x00004000) /*!< Endpoint 6 Interrupt flag */ +#define EP7IF ((u32)0x00008000) /*!< Endpoint 7 Interrupt flag */ +#if (LIBCFG_USBD_V2) +#define EP8IF ((u32)0x00010000) /*!< Endpoint 8 Interrupt flag */ +#define EP9IF ((u32)0x00020000) /*!< Endpoint 9 Interrupt flag */ +#define EPnIF ((u32)0x0003FF00) /*!< Endpoint n Interrupt flag */ +#else +#define EPnIF ((u32)0x0000FF00) /*!< Endpoint n Interrupt flag */ +#endif + + +/* USB Endpoint n Interrupt Enable Register (USBEPnIER) */ +#define OTRXIE ((u32)0x00000001) /*!< OUT Token Received Interrupt Enable */ +#define ODRXIE ((u32)0x00000002) /*!< OUT Data Received Interrupt Enable */ +#define ODOVIE ((u32)0x00000004) /*!< OUT Data Buffer Overrun Interrupt Enable */ +#define ITRXIE ((u32)0x00000008) /*!< IN Token Received Interrupt Enable */ +#define IDTXIE ((u32)0x00000010) /*!< IN Data Transmitted Interrupt Enable */ +#define NAKIE ((u32)0x00000020) /*!< NAK Transmitted Interrupt Enable */ +#define STLIE ((u32)0x00000040) /*!< STALL Transmitted Interrupt Enable */ +#define UERIE ((u32)0x00000080) /*!< USB Error Interrupt Enable */ +#define STRXIE ((u32)0x00000100) /*!< SETUP Token Received Interrupt Enable */ +#define SDRXIE ((u32)0x00000200) /*!< SETUP Data Received Interrupt Enable */ +#define SDERIE ((u32)0x00000400) /*!< SETUP Data Error Interrupt Enable */ +#define ZLRXIE ((u32)0x00000800) /*!< Zero Length Data Received Interrupt Enable */ + +/* USB Endpoint n Interrupt Status Register (USBEPnISR) */ +#define OTRXIF ((u32)0x00000001) /*!< OUT Token Received Interrupt Flag */ +#define ODRXIF ((u32)0x00000002) /*!< OUT Data Received Interrupt Flag */ +#define ODOVIF ((u32)0x00000004) /*!< OUT Data Buffer Overrun Interrupt Flag */ +#define ITRXIF ((u32)0x00000008) /*!< IN Token Received Interrupt Flag */ +#define IDTXIF ((u32)0x00000010) /*!< IN Data Transmitted Interrupt Flag */ +#define NAKIF ((u32)0x00000020) /*!< NAK Transmitted Interrupt Flag */ +#define STLIF ((u32)0x00000040) /*!< STALL Transmitted Interrupt Flag */ +#define UERIF ((u32)0x00000080) /*!< USB Error Interrupt Flag */ +#define STRXIF ((u32)0x00000100) /*!< SETUP Token Received Interrupt Flag */ +#define SDRXIF ((u32)0x00000200) /*!< SETUP Data Received Interrupt Flag */ +#define SDERIF ((u32)0x00000400) /*!< SETUP Data Error Interrupt Flag */ +#define ZLRXIF ((u32)0x00000800) /*!< Zero Length Data Received Interrupt Flag */ + +/* USB Endpoint n Control and Status Register (USBEPnCSR) */ +#define DTGTX ((u32)0x00000001) /*!< Data Toggle Status, for IN transfer */ +#define NAKTX ((u32)0x00000002) /*!< NAK Status, for IN transfer */ +#define STLTX ((u32)0x00000004) /*!< STALL Status, for IN transfer */ +#define DTGRX ((u32)0x00000008) /*!< Data Toggle Status, for OUT transfer */ +#define NAKRX ((u32)0x00000010) /*!< NAK Status, for OUT transfer */ +#define STLRX ((u32)0x00000020) /*!< STALL Status, for OUT transfer */ + +/* For USBD_EPTGetTranssferCount function */ +#define USBD_CNTB0 (USBD_TCR_0) +#define USBD_CNTB1 (USBD_TCR_1) +#define USBD_CNTIN (USBD_TCR_0) +#define USBD_CNTOUT (USBD_TCR_1) +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------------------------------------*/ +/** @defgroup USBDevice_Exported_Macro USB Device exported macro + * @{ + */ +/* API macro for USB Core - Global event and operation */ +#define API_USB_INIT(driver) (USBD_Init(driver)) +#define API_USB_DEINIT() (USBD_DeInit()) +#define API_USB_POWER_UP(driver, power) (USBD_PowerUp(driver, power)) +#define API_USB_POWER_OFF() (USBD_PowerOff()) +#define API_USB_POWER_ON() (USBD_PowerOn()) +#define API_USB_REMOTE_WAKEUP() (USBD_RemoteWakeup()) +#define API_USB_READ_SETUP(buffer) (USBD_ReadSETUPData((u32 *)(buffer))) +#define API_USB_SET_ADDR(addr) (USBD_SetAddress(addr)) +#define API_USB_GET_CTRL_IN_LEN() (USBD_EPTGetBufferLen(USBD_EPT0)) +#define API_USB_ENABLE_INT(flag) (USBD_EnableINT(flag)) +#define API_USB_GET_INT() (USBD_GetINT()) +#define API_USB_GET_EPT_NUM(flag) (USBD_GetEPTnINTNumber(flag)) +#define API_USB_IS_SETUP_INT(flag) (flag & SDRXIF) +#define API_USB_CLR_SETUP_INT() (USBD_EPTClearINT(USBD_EPT0, SDRXIF)) +#define API_USB_IS_RESET_INT(flag) (flag & URSTIF) +#define API_USB_CLR_RESET_INT() (USBD_ClearINT(URSTIF)) +#define API_USB_IS_SOF_INT(flag) (flag & SOFIF) +#define API_USB_CLR_SOF_INT() (USBD_ClearINT(SOFIF)) +#define API_USB_IS_FRES_INT(flag) (flag & FRESIF) +#define API_USB_CLR_FRES_INT() (USBD_ClearINT(FRESIF)) +#define API_USB_IS_RESUME_INT(flag) (flag & RSMIF) +#define API_USB_CLR_RESUME_INT() (USBD_ClearINT(RSMIF)) +#define API_USB_IS_SUSPEND_INT(flag) (flag & SUSPIF) +#define API_USB_CLR_SUSPEND_INT() (USBD_ClearINT(SUSPIF)) +#define API_USB_IS_EPTn_INT(flag, EPTn) (flag & (EP0IF << EPTn)) +#define API_USB_CLR_EPTn_INT(EPTn) (USBD_ClearINT(EP0IF << EPTn)) + +/* API macro for USB Core - Endpoint event and operation */ +#define API_USB_EPTn_INIT(EPTn, driver) (USBD_EPTInit(EPTn, driver)) +#define API_USB_EPTn_RESET(EPTn) (USBD_EPTReset(EPTn)) +#define API_USB_EPTn_SEND_STALL(EPTn) (USBD_EPTSendSTALL(EPTn)) +#define API_USB_EPTn_GET_INT(EPTn) (USBD_EPTGetINT(EPTn)) +#define API_USB_EPTn_IS_IN_INT(flag) (flag & IDTXIF) +#define API_USB_EPTn_CLR_IN_INT(EPTn) (USBD_EPTClearINT(EPTn, IDTXIF)) +#define API_USB_EPTn_IS_OUT_INT(flag) (flag & ODRXIF) +#define API_USB_EPTn_CLR_OUT_INT(EPTn) (USBD_EPTClearINT(EPTn, ODRXIF)) +#define API_USB_EPTn_IS_INT(flag) (flag & (ODRXIF | IDTXIF)) +#define API_USB_EPTn_CLR_INT(EPTn) (USBD_EPTClearINT(EPTn, (ODRXIF | IDTXIF))) +#define API_USB_EPTn_GET_HALT(EPTn) (USBD_EPTGetHalt(EPTn)) +#define API_USB_EPTn_SET_HALT(EPTn) (USBD_EPTSetHalt(EPTn)) +#define API_USB_EPTn_CLR_HALT(EPTn) (USBD_EPTClearHalt(EPTn)) +#define API_USB_EPTn_WAIT_STALL_SENT(EPTn) (USBD_EPTWaitSTALLSent(EPTn)) +#define API_USB_EPTn_CLR_DTG(EPTn) (USBD_EPTClearDTG(EPTn)) +#define API_USB_EPTn_GET_BUFFLEN(EPTn) (USBD_EPTGetBufferLen(EPTn)) +#define API_USB_EPTn_GET_CNT(EPTn, type) (USBD_EPTGetTransferCount(EPTn, type)) +#define API_USB_EPTn_WRITE_IN(EPTn, from, len) (USBD_EPTWriteINData(EPTn, from, len)) +#define API_USB_EPTn_READ_OUT(EPTn, to, len) (USBD_EPTReadOUTData(EPTn, to, len)) +#define API_USB_EPTn_READ_MEM(EPTn, to, len) (USBD_EPTReadMemory(EPTn, to, len)) +/** + * @} + */ + +/* Exported functions --------------------------------------------------------------------------------------*/ +/** @defgroup USBDevice_Exported_Functions USB Device exported functions + * @{ + */ +void USBD_Init(u32 *pDriver); +void USBD_PreInit(USBD_Driver_TypeDef *pDriver); +void USBD_DPpullupCmd(ControlStatus NewState); +void USBD_DPWakeUpCmd(ControlStatus NewState); +void USBD_DeInit(void); +void USBD_PowerUp(u32 *pDriver, u32 uIsSelfPowered); +void USBD_PowerOff(void); +void USBD_PowerOn(void); +void USBD_SRAMResetConditionCmd(ControlStatus NewState); +void USBD_DisableDefaultPull(void); +void USBD_RemoteWakeup(void); +void USBD_ReadSETUPData(u32 *pBuffer); +void USBD_SetAddress(u32 address); +void USBD_EnableINT(u32 INTFlag); +void USBD_DisableINT(u32 INTFlag); +u32 USBD_GetINT(void); +void USBD_ClearINT(u32 INTFlag); +USBD_EPTn_Enum USBD_GetEPTnINTNumber(u32 INTFlag); + +void USBD_EPTInit(USBD_EPTn_Enum USBD_EPTn, u32 *pDriver); +void USBD_EPTReset(USBD_EPTn_Enum USBD_EPTn); +void USBD_EPTEnableINT(USBD_EPTn_Enum USBD_EPTn, u32 INTFlag); +u32 USBD_EPTGetINT(USBD_EPTn_Enum USBD_EPTn); +void USBD_EPTClearINT(USBD_EPTn_Enum USBD_EPTn, u32 INTFlag); +void USBD_EPTSendSTALL(USBD_EPTn_Enum USBD_EPTn); +u32 USBD_EPTGetHalt(USBD_EPTn_Enum USBD_EPTn); +void USBD_EPTSetHalt(USBD_EPTn_Enum USBD_EPTn); +void USBD_EPTClearHalt(USBD_EPTn_Enum USBD_EPTn); +void USBD_EPTWaitSTALLSent(USBD_EPTn_Enum USBD_EPTn); +void USBD_EPTClearDTG(USBD_EPTn_Enum USBD_EPTn); +u32 USBD_EPTGetBuffer0Addr(USBD_EPTn_Enum USBD_EPTn); +u32 USBD_EPTGetBuffer1Addr(USBD_EPTn_Enum USBD_EPTn); +u32 USBD_EPTGetBufferLen(USBD_EPTn_Enum USBD_EPTn); +u32 USBD_EPTGetTransferCount(USBD_EPTn_Enum USBD_EPTn, USBD_TCR_Enum USBD_TCR_0or1); +u32 USBD_EPTWriteINData(USBD_EPTn_Enum USBD_EPTn, u32 *pFrom, u32 len); +u32 USBD_EPTReadOUTData(USBD_EPTn_Enum USBD_EPTn, u32 *pTo, u32 len); +u32 USBD_EPTReadMemory(USBD_EPTn_Enum USBD_EPTn, u32 *pTo, u32 len); +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f5xxxx_usbdchk.h b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f5xxxx_usbdchk.h new file mode 100644 index 0000000000..d4d1625cef --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f5xxxx_usbdchk.h @@ -0,0 +1,706 @@ +/*********************************************************************************************************//** + * @file ht32f5xxxx_usbdchk.h + * @version $Rev:: 5656 $ + * @date $Date:: 2021-11-24 #$ + * @brief The header file of the USB Device Driver. + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------------------------------------*/ +#ifndef __HT32F5XXXX_USBDCHK_H +#define __HT32F5XXXX_USBDCHK_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------------------------------------*/ + +/** @addtogroup HT32F5xxxx_Peripheral_Driver HT32F5xxxx Peripheral Driver + * @{ + */ + +/** @addtogroup USBDevice + * @{ + */ + + +/*----------------------------------------------------------------------------------------------------------*/ +/* Endpoint 0 ~ 7 and checking */ +/* !!! DO NOT MODIFY !!! */ +/*----------------------------------------------------------------------------------------------------------*/ + +/*----------------------------------------------------------------------------------------------------------*/ +/* Endpoint0 checking */ +/*----------------------------------------------------------------------------------------------------------*/ +#if (_EP0LEN != 8 && _EP0LEN != 16 && _EP0LEN != 32 && _EP0LEN != 64) + #error "USB Buffer Length (EPLEN) of Control Endpoint0 must be 8, 16, 32, or 64 bytes." +#endif + +/*----------------------------------------------------------------------------------------------------------*/ +/* Endpoint1 Configuration and checking */ +/*----------------------------------------------------------------------------------------------------------*/ +#if (_EP1_ENABLE == 1) + #if (_EP1_TYPR == EP_TYPE_BULK) + #if (_EP1LEN != 8 && _EP1LEN != 16 && _EP1LEN != 32 && _EP1LEN != 64) + #error "USB Buffer Length (EPLEN) of Endpoint1 must be 8, 16, 32, or 64 bytes under Bulk transfer." + #endif + #endif + #if (_EP1LEN > 64) + #error "USB Buffer Length (EPLEN) of Endpoint1 must be less than 64 bytes." + #endif + #if (_EP1LEN == 0) + #error "USB Buffer Length (EPLEN) of Endpoint1 cannot be 0 byte." + #endif + #if ((_EP1LEN & 0x3) != 0x0) + #error "USB Buffer Length (EPLEN) of Endpoint1 must be a multiple of 4 (word-aligned)." + #endif +#endif + +/*----------------------------------------------------------------------------------------------------------*/ +/* Endpoint2 checking */ +/*----------------------------------------------------------------------------------------------------------*/ +#if (_EP2_ENABLE == 1) + #if (_EP2_TYPR == EP_TYPE_BULK) + #if (_EP2LEN != 8 && _EP2LEN != 16 && _EP2LEN != 32 && _EP2LEN != 64) + #error "USB Buffer Length (EPLEN) of Endpoint2 must be 8, 16, 32, or 64 bytes under Bulk transfer." + #endif + #endif + #if (_EP2LEN > 64) + #error "USB Buffer Length (EPLEN) of Endpoint2 must be less than 64 bytes." + #endif + #if (_EP2LEN == 0) + #error "USB Buffer Length (EPLEN) of Endpoint2 cannot be 0 byte." + #endif + #if ((_EP2LEN & 0x3) != 0x0) + #error "USB Buffer Length (EPLEN) of Endpoint2 must be a multiple of 4 (word-aligned)." + #endif +#endif + +/*----------------------------------------------------------------------------------------------------------*/ +/* Endpoint3 checking */ +/*----------------------------------------------------------------------------------------------------------*/ +#if (_EP3_ENABLE == 1) + #if (_EP3_TYPR == EP_TYPE_BULK) + #if (_EP3LEN != 8 && _EP3LEN != 16 && _EP3LEN != 32 && _EP3LEN != 64) + #error "USB Buffer Length (EPLEN) of Endpoint3 must be 8, 16, 32, or 64 bytes under Bulk transfer." + #endif + #endif + #if (_EP3LEN > 64) + #error "USB Buffer Length (EPLEN) of Endpoint3 must be less than 64 bytes." + #endif + #if (_EP3LEN == 0) + #error "USB Buffer Length (EPLEN) of Endpoint3 cannot be 0 byte." + #endif + #if ((_EP3LEN & 0x3) != 0x0) + #error "USB Buffer Length (EPLEN) of Endpoint3 must be a multiple of 4 (word-aligned)." + #endif +#endif + +/*----------------------------------------------------------------------------------------------------------*/ +/* Endpoint8 checking */ +/*----------------------------------------------------------------------------------------------------------*/ +#if (_EP8_ENABLE == 1) + #if (_EP8_TYPR == EP_TYPE_BULK) + #if (_EP8LEN != 8 && _EP8LEN != 16 && _EP8LEN != 32 && _EP8LEN != 64) + #error "USB Buffer Length (EPLEN) of Endpoint8 must be 8, 16, 32, or 64 bytes under Bulk transfer." + #endif + #endif + #if (_EP8LEN > 64) + #error "USB Buffer Length (EPLEN) of Endpoint8 must be less than 64 bytes." + #endif + #if (_EP8LEN == 0) + #error "USB Buffer Length (EPLEN) of Endpoint8 cannot be 0 byte." + #endif + #if ((_EP8LEN & 0x3) != 0x0) + #error "USB Buffer Length (EPLEN) of Endpoint8 must be a multiple of 4 (word-aligned)." + #endif +#endif + +/*----------------------------------------------------------------------------------------------------------*/ +/* Endpoint9 checking */ +/*----------------------------------------------------------------------------------------------------------*/ +#if (_EP9_ENABLE == 1) + #if (_EP9_TYPR == EP_TYPE_BULK) + #if (_EP9LEN != 8 && _EP9LEN != 16 && _EP9LEN != 32 && _EP9LEN != 64) + #error "USB Buffer Length (EPLEN) of Endpoint9 must be 8, 16, 32, or 64 bytes under Bulk transfer." + #endif + #endif + #if (_EP9LEN > 64) + #error "USB Buffer Length (EPLEN) of Endpoint9 must be less than 64 bytes." + #endif + #if (_EP9LEN == 0) + #error "USB Buffer Length (EPLEN) of Endpoint9 cannot be 0 byte." + #endif + #if ((_EP9LEN & 0x3) != 0x0) + #error "USB Buffer Length (EPLEN) of Endpoint9 must be a multiple of 4 (word-aligned)." + #endif +#endif + +/*----------------------------------------------------------------------------------------------------------*/ +/* Endpoint4 checking */ +/*----------------------------------------------------------------------------------------------------------*/ +#if (_EP4_ENABLE == 1) + #if (_EP4_TYPR == EP_TYPE_BULK) + #if (_EP4LEN != 8 && _EP4LEN != 16 && _EP4LEN != 32 && _EP4LEN != 64) + #error "USB Buffer Length (EPLEN) of Endpoint4 must be 8, 16, 32, or 64 bytes under Bulk transfer." + #endif + #endif + #if (_EP4_TYPR == EP_TYPE_INT) + #if (_EP4LEN > 64) + #error "USB Buffer Length (EPLEN) of Endpoint4 must be less than 64 bytes under Interrupt transfer." + #endif + #endif + #if (_EP4_TYPR == EP_TYPE_ISO) + #if (_EP4LEN > 1023) + #error "USB Buffer Length (EPLEN) of Endpoint4 must be less than 1023 bytes under Isochronous transfer." + #endif + #endif + #if (_EP4LEN == 0) + #error "USB Buffer Length (EPLEN) of Endpoint4 cannot be 0 byte." + #endif + #if ((_EP4LEN & 0x3) != 0x0) + #error "USB Buffer Length (EPLEN) of Endpoint4 must be a multiple of 4 (word-aligned)." + #endif +#endif + +/*----------------------------------------------------------------------------------------------------------*/ +/* Endpoint5 checking */ +/*----------------------------------------------------------------------------------------------------------*/ +#if (_EP5_ENABLE == 1) + #if (_EP5_TYPR == EP_TYPE_BULK) + #if (_EP5LEN != 8 && _EP5LEN != 16 && _EP5LEN != 32 && _EP5LEN != 64) + #error "USB Buffer Length (EPLEN) of Endpoint5 must be 8, 16, 32, or 64 bytes under Bulk transfer." + #endif + #endif + #if (_EP5_TYPR == EP_TYPE_INT) + #if (_EP5LEN > 64) + #error "USB Buffer Length (EPLEN) of Endpoint5 must be less than 64 bytes under Interrupt transfer." + #endif + #endif + #if (_EP5_TYPR == EP_TYPE_ISO) + #if (_EP5LEN > 1023) + #error "USB Buffer Length (EPLEN) of Endpoint5 must be less than 1023 bytes under Isochronous transfer." + #endif + #endif + #if (_EP5LEN == 0) + #error "USB Buffer Length (EPLEN) of Endpoint5 cannot be 0 byte." + #endif + #if ((_EP5LEN & 0x3) != 0x0) + #error "USB Buffer Length (EPLEN) of Endpoint5 must be a multiple of 4 (word-aligned)." + #endif +#endif + +/*----------------------------------------------------------------------------------------------------------*/ +/* Endpoint6 checking */ +/*----------------------------------------------------------------------------------------------------------*/ +#if (_EP6_ENABLE == 1) + #if (_EP6_TYPR == EP_TYPE_BULK) + #if (_EP6LEN != 8 && _EP6LEN != 16 && _EP6LEN != 32 && _EP6LEN != 64) + #error "USB Buffer Length (EPLEN) of Endpoint6 must be 8, 16, 32, or 64 bytes under Bulk transfer." + #endif + #endif + #if (_EP6_TYPR == EP_TYPE_INT) + #if (_EP6LEN > 64) + #error "USB Buffer Length (EPLEN) of Endpoint6 must be less than 64 bytes under Interrupt transfer." + #endif + #endif + #if (_EP6_TYPR == EP_TYPE_ISO) + #if (_EP6LEN > 1023) + #error "USB Buffer Length (EPLEN) of Endpoint6 must be less than 1023 bytes under Isochronous transfer." + #endif + #endif + #if (_EP6LEN == 0) + #error "USB Buffer Length (EPLEN) of Endpoint6 cannot be 0 byte." + #endif + #if ((_EP6LEN & 0x3) != 0x0) + #error "USB Buffer Length (EPLEN) of Endpoint6 must be a multiple of 4 (word-aligned)." + #endif +#endif + +/*----------------------------------------------------------------------------------------------------------*/ +/* Endpoint7 checking */ +/*----------------------------------------------------------------------------------------------------------*/ +#if (_EP7_ENABLE == 1) + #if (_EP7_TYPR == EP_TYPE_BULK) + #if (_EP7LEN != 8 && _EP7LEN != 16 && _EP7LEN != 32 && _EP7LEN != 64) + #error "USB Buffer Length (EPLEN) of Endpoint7 must be 8, 16, 32, or 64 bytes under Bulk transfer." + #endif + #endif + #if (_EP7_TYPR == EP_TYPE_INT) + #if (_EP7LEN > 64) + #error "USB Buffer Length (EPLEN) of Endpoint7 must be less than 64 bytes under Interrupt transfer." + #endif + #endif + #if (_EP7_TYPR == EP_TYPE_ISO) + #if (_EP7LEN > 1023) + #error "USB Buffer Length (EPLEN) of Endpoint7 must be less than 1023 bytes under Isochronous transfer." + #endif + #endif + #if (_EP7LEN == 0) + #error "USB Buffer Length (EPLEN) of Endpoint7 cannot be 0 byte." + #endif + #if ((_EP7LEN & 0x3) != 0x0) + #error "USB Buffer Length (EPLEN) of Endpoint7 must be a multiple of 4 (word-aligned)." + #endif +#endif + + +/*----------------------------------------------------------------------------------------------------------*/ +/* Check the endpoint address */ +/*----------------------------------------------------------------------------------------------------------*/ +#if (_EP1_ENABLE == 1) + #if (_EP1_CFG_EPADR == 0) + #error "The address of Endpoint1 (EPADR) cannot be 0." + #endif + #if (_EP2_ENABLE == 1) + #if (_EP1_CFG_EPADR == _EP2_CFG_EPADR) + #error "The address of Endpoint1 (EPADR) conflicts with Endpoint2." + #endif + #endif + #if (_EP3_ENABLE == 1) + #if (_EP1_CFG_EPADR == _EP3_CFG_EPADR) + #error "The address of Endpoint1 (EPADR) conflicts with Endpoint3." + #endif + #endif + #if (_EP4_ENABLE == 1) + #if (_EP1_CFG_EPADR == _EP4_CFG_EPADR) + #error "The address of Endpoint1 (EPADR) conflicts with Endpoint4." + #endif + #endif + #if (_EP5_ENABLE == 1) + #if (_EP1_CFG_EPADR == _EP5_CFG_EPADR) + #error "The address of Endpoint1 (EPADR) conflicts with Endpoint5." + #endif + #endif + #if (_EP6_ENABLE == 1) + #if (_EP1_CFG_EPADR == _EP6_CFG_EPADR) + #error "The address of Endpoint1 (EPADR) conflicts with Endpoint6." + #endif + #endif + #if (_EP7_ENABLE == 1) + #if (_EP1_CFG_EPADR == _EP7_CFG_EPADR) + #error "The address of Endpoint1 (EPADR) conflicts with Endpoint7." + #endif + #endif + #if (_EP8_ENABLE == 1) + #if (_EP1_CFG_EPADR == _EP8_CFG_EPADR) + #error "The address of Endpoint1 (EPADR) conflicts with Endpoint8." + #endif + #endif + #if (_EP9_ENABLE == 1) + #if (_EP1_CFG_EPADR == _EP9_CFG_EPADR) + #error "The address of Endpoint1 (EPADR) conflicts with Endpoint9." + #endif + #endif +#endif + +#if (_EP2_ENABLE == 1) + #if (_EP2_CFG_EPADR == 0) + #error "The address of Endpoint2 (EPADR) cannot be 0." + #endif + #if (_EP1_ENABLE == 1) + #if (_EP2_CFG_EPADR == _EP1_CFG_EPADR) + #error "The address of Endpoint2 (EPADR) conflicts with Endpoint1." + #endif + #endif + #if (_EP3_ENABLE == 1) + #if (_EP2_CFG_EPADR == _EP3_CFG_EPADR) + #error "The address of Endpoint2 (EPADR) conflicts with Endpoint3." + #endif + #endif + #if (_EP4_ENABLE == 1) + #if (_EP2_CFG_EPADR == _EP4_CFG_EPADR) + #error "The address of Endpoint2 (EPADR) conflicts with Endpoint4." + #endif + #endif + #if (_EP5_ENABLE == 1) + #if (_EP2_CFG_EPADR == _EP5_CFG_EPADR) + #error "The address of Endpoint2 (EPADR) conflicts with Endpoint5." + #endif + #endif + #if (_EP6_ENABLE == 1) + #if (_EP2_CFG_EPADR == _EP6_CFG_EPADR) + #error "The address of Endpoint2 (EPADR) conflicts with Endpoint6." + #endif + #endif + #if (_EP7_ENABLE == 1) + #if (_EP2_CFG_EPADR == _EP7_CFG_EPADR) + #error "The address of Endpoint2 (EPADR) conflicts with Endpoint7." + #endif + #endif + #if (_EP8_ENABLE == 1) + #if (_EP2_CFG_EPADR == _EP8_CFG_EPADR) + #error "The address of Endpoint2 (EPADR) conflicts with Endpoint8." + #endif + #endif + #if (_EP9_ENABLE == 1) + #if (_EP2_CFG_EPADR == _EP9_CFG_EPADR) + #error "The address of Endpoint2 (EPADR) conflicts with Endpoint9." + #endif + #endif +#endif + +#if (_EP3_ENABLE == 1) + #if (_EP3_CFG_EPADR == 0) + #error "The address of Endpoint3 (EPADR) cannot be 0." + #endif + #if (_EP1_ENABLE == 1) + #if (_EP3_CFG_EPADR == _EP1_CFG_EPADR) + #error "The address of Endpoint3 (EPADR) conflicts with Endpoint1." + #endif + #endif + #if (_EP2_ENABLE == 1) + #if (_EP3_CFG_EPADR == _EP2_CFG_EPADR) + #error "The address of Endpoint3 (EPADR) conflicts with Endpoint2." + #endif + #endif + #if (_EP4_ENABLE == 1) + #if (_EP3_CFG_EPADR == _EP4_CFG_EPADR) + #error "The address of Endpoint3 (EPADR) conflicts with Endpoint4." + #endif + #endif + #if (_EP5_ENABLE == 1) + #if (_EP3_CFG_EPADR == _EP5_CFG_EPADR) + #error "The address of Endpoint3 (EPADR) conflicts with Endpoint5." + #endif + #endif + #if (_EP6_ENABLE == 1) + #if (_EP3_CFG_EPADR == _EP6_CFG_EPADR) + #error "The address of Endpoint3 (EPADR) conflicts with Endpoint6." + #endif + #endif + #if (_EP7_ENABLE == 1) + #if (_EP3_CFG_EPADR == _EP7_CFG_EPADR) + #error "The address of Endpoint3 (EPADR) conflicts with Endpoint7." + #endif + #endif + #if (_EP8_ENABLE == 1) + #if (_EP3_CFG_EPADR == _EP8_CFG_EPADR) + #error "The address of Endpoint3 (EPADR) conflicts with Endpoint8." + #endif + #endif + #if (_EP9_ENABLE == 1) + #if (_EP3_CFG_EPADR == _EP9_CFG_EPADR) + #error "The address of Endpoint3 (EPADR) conflicts with Endpoint9." + #endif + #endif +#endif + +#if (_EP4_ENABLE == 1) + #if (_EP4_CFG_EPADR == 0) + #error "The address of Endpoint4 (EPADR) cannot be 0." + #endif + #if (_EP1_ENABLE == 1) + #if (_EP4_CFG_EPADR == _EP1_CFG_EPADR) + #error "The address of Endpoint4 (EPADR) conflicts with Endpoint1." + #endif + #endif + #if (_EP2_ENABLE == 1) + #if (_EP4_CFG_EPADR == _EP2_CFG_EPADR) + #error "The address of Endpoint4 (EPADR) conflicts with Endpoint2." + #endif + #endif + #if (_EP3_ENABLE == 1) + #if (_EP4_CFG_EPADR == _EP3_CFG_EPADR) + #error "The address of Endpoint4 (EPADR) conflicts with Endpoint3." + #endif + #endif + #if (_EP5_ENABLE == 1) + #if (_EP4_CFG_EPADR == _EP5_CFG_EPADR) + #error "The address of Endpoint4 (EPADR) conflicts with Endpoint5." + #endif + #endif + #if (_EP6_ENABLE == 1) + #if (_EP4_CFG_EPADR == _EP6_CFG_EPADR) + #error "The address of Endpoint4 (EPADR) conflicts with Endpoint6." + #endif + #endif + #if (_EP7_ENABLE == 1) + #if (_EP4_CFG_EPADR == _EP7_CFG_EPADR) + #error "The address of Endpoint4 (EPADR) conflicts with Endpoint7." + #endif + #endif + #if (_EP8_ENABLE == 1) + #if (_EP4_CFG_EPADR == _EP8_CFG_EPADR) + #error "The address of Endpoint4 (EPADR) conflicts with Endpoint8." + #endif + #endif + #if (_EP9_ENABLE == 1) + #if (_EP4_CFG_EPADR == _EP9_CFG_EPADR) + #error "The address of Endpoint4 (EPADR) conflicts with Endpoint9." + #endif + #endif +#endif + +#if (_EP5_ENABLE == 1) + #if (_EP5_CFG_EPADR == 0) + #error "The address of Endpoint5 (EPADR) cannot be 0." + #endif + #if (_EP1_ENABLE == 1) + #if (_EP5_CFG_EPADR == _EP1_CFG_EPADR) + #error "The address of Endpoint5 (EPADR) conflicts with Endpoint1." + #endif + #endif + #if (_EP2_ENABLE == 1) + #if (_EP5_CFG_EPADR == _EP2_CFG_EPADR) + #error "The address of Endpoint5 (EPADR) conflicts with Endpoint2." + #endif + #endif + #if (_EP3_ENABLE == 1) + #if (_EP5_CFG_EPADR == _EP3_CFG_EPADR) + #error "The address of Endpoint5 (EPADR) conflicts with Endpoint3." + #endif + #endif + #if (_EP4_ENABLE == 1) + #if (_EP5_CFG_EPADR == _EP4_CFG_EPADR) + #error "The address of Endpoint5 (EPADR) conflicts with Endpoint4." + #endif + #endif + #if (_EP6_ENABLE == 1) + #if (_EP5_CFG_EPADR == _EP6_CFG_EPADR) + #error "The address of Endpoint5 (EPADR) conflicts with Endpoint6." + #endif + #endif + #if (_EP7_ENABLE == 1) + #if (_EP5_CFG_EPADR == _EP7_CFG_EPADR) + #error "The address of Endpoint5 (EPADR) conflicts with Endpoint7." + #endif + #endif + #if (_EP8_ENABLE == 1) + #if (_EP5_CFG_EPADR == _EP8_CFG_EPADR) + #error "The address of Endpoint5 (EPADR) conflicts with Endpoint8." + #endif + #endif + #if (_EP9_ENABLE == 1) + #if (_EP5_CFG_EPADR == _EP9_CFG_EPADR) + #error "The address of Endpoint5 (EPADR) conflicts with Endpoint9." + #endif + #endif +#endif + +#if (_EP6_ENABLE == 1) + #if (_EP6_CFG_EPADR == 0) + #error "The address of Endpoint6 (EPADR) cannot be 0." + #endif + #if (_EP1_ENABLE == 1) + #if (_EP6_CFG_EPADR == _EP1_CFG_EPADR) + #error "The address of Endpoint6 (EPADR) conflicts with Endpoint1." + #endif + #endif + #if (_EP2_ENABLE == 1) + #if (_EP6_CFG_EPADR == _EP2_CFG_EPADR) + #error "The address of Endpoint6 (EPADR) conflicts with Endpoint2." + #endif + #endif + #if (_EP3_ENABLE == 1) + #if (_EP6_CFG_EPADR == _EP3_CFG_EPADR) + #error "The address of Endpoint6 (EPADR) conflicts with Endpoint3." + #endif + #endif + #if (_EP4_ENABLE == 1) + #if (_EP6_CFG_EPADR == _EP4_CFG_EPADR) + #error "The address of Endpoint6 (EPADR) conflicts with Endpoint4." + #endif + #endif + #if (_EP5_ENABLE == 1) + #if (_EP6_CFG_EPADR == _EP5_CFG_EPADR) + #error "The address of Endpoint6 (EPADR) conflicts with Endpoint5." + #endif + #endif + #if (_EP7_ENABLE == 1) + #if (_EP6_CFG_EPADR == _EP7_CFG_EPADR) + #error "The address of Endpoint6 (EPADR) conflicts with Endpoint7." + #endif + #endif + #if (_EP8_ENABLE == 1) + #if (_EP6_CFG_EPADR == _EP8_CFG_EPADR) + #error "The address of Endpoint6 (EPADR) conflicts with Endpoint8." + #endif + #endif + #if (_EP9_ENABLE == 1) + #if (_EP6_CFG_EPADR == _EP9_CFG_EPADR) + #error "The address of Endpoint6 (EPADR) conflicts with Endpoint9." + #endif + #endif +#endif + +#if (_EP7_ENABLE == 1) + #if (_EP7_CFG_EPADR == 0) + #error "The address of Endpoint1 (EPADR) cannot be 0." + #endif + #if (_EP1_ENABLE == 1) + #if (_EP7_CFG_EPADR == _EP1_CFG_EPADR) + #error "The address of Endpoint7 (EPADR) conflicts with Endpoint1." + #endif + #endif + #if (_EP2_ENABLE == 1) + #if (_EP7_CFG_EPADR == _EP2_CFG_EPADR) + #error "The address of Endpoint7 (EPADR) conflicts with Endpoint2." + #endif + #endif + #if (_EP3_ENABLE == 1) + #if (_EP7_CFG_EPADR == _EP3_CFG_EPADR) + #error "The address of Endpoint7 (EPADR) conflicts with Endpoint3." + #endif + #endif + #if (_EP4_ENABLE == 1) + #if (_EP7_CFG_EPADR == _EP4_CFG_EPADR) + #error "The address of Endpoint7 (EPADR) conflicts with Endpoint4." + #endif + #endif + #if (_EP5_ENABLE == 1) + #if (_EP7_CFG_EPADR == _EP5_CFG_EPADR) + #error "The address of Endpoint7 (EPADR) conflicts with Endpoint5." + #endif + #endif + #if (_EP6_ENABLE == 1) + #if (_EP7_CFG_EPADR == _EP6_CFG_EPADR) + #error "The address of Endpoint7 (EPADR) conflicts with Endpoint6." + #endif + #endif + #if (_EP8_ENABLE == 1) + #if (_EP7_CFG_EPADR == _EP8_CFG_EPADR) + #error "The address of Endpoint7 (EPADR) conflicts with Endpoint8." + #endif + #endif + #if (_EP9_ENABLE == 1) + #if (_EP7_CFG_EPADR == _EP9_CFG_EPADR) + #error "The address of Endpoint7 (EPADR) conflicts with Endpoint9." + #endif + #endif +#endif + +#if (_EP8_ENABLE == 1) + #if (_EP8_CFG_EPADR == 0) + #error "The address of Endpoint8 (EPADR) cannot be 0." + #endif + #if (_EP1_ENABLE == 1) + #if (_EP8_CFG_EPADR == _EP1_CFG_EPADR) + #error "The address of Endpoint8 (EPADR) conflicts with Endpoint1." + #endif + #endif + #if (_EP2_ENABLE == 1) + #if (_EP8_CFG_EPADR == _EP2_CFG_EPADR) + #error "The address of Endpoint8 (EPADR) conflicts with Endpoint2." + #endif + #endif + #if (_EP3_ENABLE == 1) + #if (_EP8_CFG_EPADR == _EP3_CFG_EPADR) + #error "The address of Endpoint8 (EPADR) conflicts with Endpoint3." + #endif + #endif + #if (_EP4_ENABLE == 1) + #if (_EP8_CFG_EPADR == _EP4_CFG_EPADR) + #error "The address of Endpoint8 (EPADR) conflicts with Endpoint4." + #endif + #endif + #if (_EP5_ENABLE == 1) + #if (_EP8_CFG_EPADR == _EP5_CFG_EPADR) + #error "The address of Endpoint8 (EPADR) conflicts with Endpoint5." + #endif + #endif + #if (_EP6_ENABLE == 1) + #if (_EP8_CFG_EPADR == _EP6_CFG_EPADR) + #error "The address of Endpoint8 (EPADR) conflicts with Endpoint6." + #endif + #endif + #if (_EP7_ENABLE == 1) + #if (_EP8_CFG_EPADR == _EP7_CFG_EPADR) + #error "The address of Endpoint8 (EPADR) conflicts with Endpoint7." + #endif + #endif + #if (_EP9_ENABLE == 1) + #if (_EP8_CFG_EPADR == _EP9_CFG_EPADR) + #error "The address of Endpoint8 (EPADR) conflicts with Endpoint9." + #endif + #endif +#endif + +#if (_EP9_ENABLE == 1) + #if (_EP9_CFG_EPADR == 0) + #error "The address of Endpoint9 (EPADR) cannot be 0." + #endif + #if (_EP1_ENABLE == 1) + #if (_EP9_CFG_EPADR == _EP1_CFG_EPADR) + #error "The address of Endpoint9 (EPADR) conflicts with Endpoint1." + #endif + #endif + #if (_EP2_ENABLE == 1) + #if (_EP9_CFG_EPADR == _EP2_CFG_EPADR) + #error "The address of Endpoint9 (EPADR) conflicts with Endpoint2." + #endif + #endif + #if (_EP3_ENABLE == 1) + #if (_EP9_CFG_EPADR == _EP3_CFG_EPADR) + #error "The address of Endpoint9 (EPADR) conflicts with Endpoint3." + #endif + #endif + #if (_EP4_ENABLE == 1) + #if (_EP9_CFG_EPADR == _EP4_CFG_EPADR) + #error "The address of Endpoint9 (EPADR) conflicts with Endpoint4." + #endif + #endif + #if (_EP5_ENABLE == 1) + #if (_EP9_CFG_EPADR == _EP5_CFG_EPADR) + #error "The address of Endpoint9 (EPADR) conflicts with Endpoint5." + #endif + #endif + #if (_EP6_ENABLE == 1) + #if (_EP9_CFG_EPADR == _EP6_CFG_EPADR) + #error "The address of Endpoint9 (EPADR) conflicts with Endpoint6." + #endif + #endif + #if (_EP7_ENABLE == 1) + #if (_EP9_CFG_EPADR == _EP7_CFG_EPADR) + #error "The address of Endpoint9 (EPADR) conflicts with Endpoint7." + #endif + #endif + #if (_EP8_ENABLE == 1) + #if (_EP9_CFG_EPADR == _EP8_CFG_EPADR) + #error "The address of Endpoint9 (EPADR) conflicts with Endpoint8." + #endif + #endif +#endif + + +/*----------------------------------------------------------------------------------------------------------*/ +/* Check Buffer size */ +/*----------------------------------------------------------------------------------------------------------*/ +#if ((_EP0LEN_T + _EP1LEN + _EP2LEN + _EP3LEN + _EP4LEN_T + _EP5LEN_T + _EP6LEN_T + _EP7LEN_T + _EP8LEN + _EP9LEN) > 1024) + #error "Total buffer size of Endpoint 0 ~ 7 (or 0 ~ 9) must be less than 1024 bytes." +#endif + + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f5xxxx_usbdinit.h b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f5xxxx_usbdinit.h new file mode 100644 index 0000000000..97184ef903 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f5xxxx_usbdinit.h @@ -0,0 +1,330 @@ +/*********************************************************************************************************//** + * @file ht32f5xxxx_usbdinit.h + * @version $Rev:: 5656 $ + * @date $Date:: 2021-11-24 #$ + * @brief The header file of the USB Device Driver. + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------------------------------------*/ +#ifndef __HT32F5XXXX_USBDINIT_H +#define __HT32F5XXXX_USBDINIT_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------------------------------------*/ +#include "ht32_retarget_usbdconf.h" + +/** @addtogroup HT32F5xxxx_Peripheral_Driver HT32F5xxxx Peripheral Driver + * @{ + */ + +/** @addtogroup USBDevice + * @{ + */ + + +/*----------------------------------------------------------------------------------------------------------*/ +/* Endpoint 0 ~ 7 Configuration */ +/* !!! DO NOT MODIFY !!! */ +/*----------------------------------------------------------------------------------------------------------*/ + +#define EP_TYPE_ISO (1) +#define EP_TYPE_BULK (2) +#define EP_TYPE_INT (3) + +#ifndef _UIER_ALL + #define _UIER_ALL _UIER +#endif + +/*----------------------------------------------------------------------------------------------------------*/ +/* Endpoint0 Configuration */ +/*----------------------------------------------------------------------------------------------------------*/ +#define _EP0_CFG_EPEN (1UL) +#define _EP0STADR (HT_USB_SRAM_BASE + 0x8) +#define _EP0INTADR (_EP0STADR) +#define _EP0OUTTADR (_EP0STADR + _EP0LEN) +#define _EP0_CFG ((_EP0_CFG_EPEN << 31) | \ + (_EP0LEN << 10) | \ + (_EP0STADR & EPBUFA_MASK)) +#define _EP0LEN_T (_EP0LEN * 2) + +/*----------------------------------------------------------------------------------------------------------*/ +/* Endpoint1 Configuration */ +/*----------------------------------------------------------------------------------------------------------*/ +#define _EP1STADR (_EP0STADR + (_EP0LEN * 2)) + +#if (_EP1_ENABLE == 1) + #define _EP1LEN (_EP1LEN_TMP) +#else + #define _EP1LEN (0) +#endif + +#if (_EP1_CFG_EPEN_TMP == 1) + #define _EP1_CFG_EPEN (1UL) +#else + #define _EP1_CFG_EPEN (0UL) +#endif + +#define _EP1_CFG ((_EP1_CFG_EPEN << 31) | \ + (_EP1_CFG_EPDIR << 28) | \ + (_EP1_CFG_EPADR << 24) | \ + (_EP1LEN << 10) | \ + (_EP1STADR & EPBUFA_MASK)) + +/*----------------------------------------------------------------------------------------------------------*/ +/* Endpoint2 Configuration */ +/*----------------------------------------------------------------------------------------------------------*/ +#define _EP2STADR (_EP1STADR + _EP1LEN) + +#if (_EP2_ENABLE == 1) + #define _EP2LEN (_EP2LEN_TMP) +#else + #define _EP2LEN (0) +#endif + +#if (_EP2_CFG_EPEN_TMP == 1) + #define _EP2_CFG_EPEN (1UL) +#else + #define _EP2_CFG_EPEN (0UL) +#endif + +#define _EP2_CFG ((_EP2_CFG_EPEN << 31) | \ + (_EP2_CFG_EPDIR << 28) | \ + (_EP2_CFG_EPADR << 24) | \ + (_EP2LEN << 10) | \ + (_EP2STADR & EPBUFA_MASK)) + +/*----------------------------------------------------------------------------------------------------------*/ +/* Endpoint3 Configuration */ +/*----------------------------------------------------------------------------------------------------------*/ +#define _EP3STADR (_EP2STADR + _EP2LEN) + +#if (_EP3_ENABLE == 1) + #define _EP3LEN (_EP3LEN_TMP) +#else + #define _EP3LEN (0) +#endif + +#if (_EP3_CFG_EPEN_TMP == 1) + #define _EP3_CFG_EPEN (1UL) +#else + #define _EP3_CFG_EPEN (0UL) +#endif + +#define _EP3_CFG ((_EP3_CFG_EPEN << 31) | \ + (_EP3_CFG_EPDIR << 28) | \ + (_EP3_CFG_EPADR << 24) | \ + (_EP3LEN << 10) | \ + (_EP3STADR & EPBUFA_MASK)) + +/*----------------------------------------------------------------------------------------------------------*/ +/* Endpoint4 Configuration */ +/*----------------------------------------------------------------------------------------------------------*/ +#define _EP4STADR (_EP3STADR + _EP3LEN) + +#if (_EP4_ENABLE == 1) + #define _EP4LEN (_EP4LEN_TMP) + #define _EP4LEN_T (_EP4LEN_TMP * (_EP4_CFG_SDBS + 1)) +#else + #define _EP4LEN (0) + #define _EP4LEN_T (0) +#endif +#if (_EP4_TYPR == EP_TYPE_ISO) + #define _EP4_CFG_EPTYPE (1) +#else + #define _EP4_CFG_EPTYPE (0) +#endif + +#if (_EP4_CFG_EPEN_TMP == 1) + #define _EP4_CFG_EPEN (1UL) +#else + #define _EP4_CFG_EPEN (0UL) +#endif + +#define _EP4_CFG ((_EP4_CFG_EPEN << 31) | \ + (_EP4_CFG_EPTYPE << 29) | \ + (_EP4_CFG_EPDIR << 28) | \ + (_EP4_CFG_EPADR << 24) | \ + (_EP4_CFG_SDBS << 23) | \ + (_EP4LEN << 10) | \ + (_EP4STADR & EPBUFA_MASK)) + +/*----------------------------------------------------------------------------------------------------------*/ +/* Endpoint5 Configuration */ +/*----------------------------------------------------------------------------------------------------------*/ +#define _EP5STADR (_EP4STADR + _EP4LEN_T) + +#if (_EP5_ENABLE == 1) + #define _EP5LEN (_EP5LEN_TMP) + #define _EP5LEN_T (_EP5LEN_TMP * (_EP5_CFG_SDBS + 1)) +#else + #define _EP5LEN (0) + #define _EP5LEN_T (0) +#endif +#if (_EP5_TYPR == EP_TYPE_ISO) + #define _EP5_CFG_EPTYPE (1) +#else + #define _EP5_CFG_EPTYPE (0) +#endif + +#if (_EP5_CFG_EPEN_TMP == 1) + #define _EP5_CFG_EPEN (1UL) +#else + #define _EP5_CFG_EPEN (0UL) +#endif + +#define _EP5_CFG ((_EP5_CFG_EPEN << 31) | \ + (_EP5_CFG_EPTYPE << 29) | \ + (_EP5_CFG_EPDIR << 28) | \ + (_EP5_CFG_EPADR << 24) | \ + (_EP5_CFG_SDBS << 23) | \ + (_EP5LEN << 10) | \ + (_EP5STADR & EPBUFA_MASK)) + +/*----------------------------------------------------------------------------------------------------------*/ +/* Endpoint6 Configuration */ +/*----------------------------------------------------------------------------------------------------------*/ +#define _EP6STADR (_EP5STADR + _EP5LEN_T) + +#if (_EP6_ENABLE == 1) + #define _EP6LEN (_EP6LEN_TMP) + #define _EP6LEN_T (_EP6LEN_TMP * (_EP6_CFG_SDBS + 1)) +#else + #define _EP6LEN (0) + #define _EP6LEN_T (0) +#endif +#if (_EP6_TYPR == EP_TYPE_ISO) + #define _EP6_CFG_EPTYPE (1) +#else + #define _EP6_CFG_EPTYPE (0) +#endif + +#if (_EP6_CFG_EPEN_TMP == 1) + #define _EP6_CFG_EPEN (1UL) +#else + #define _EP6_CFG_EPEN (0UL) +#endif + +#define _EP6_CFG ((_EP6_CFG_EPEN << 31) | \ + (_EP6_CFG_EPTYPE << 29) | \ + (_EP6_CFG_EPDIR << 28) | \ + (_EP6_CFG_EPADR << 24) | \ + (_EP6_CFG_SDBS << 23) | \ + (_EP6LEN << 10) | \ + (_EP6STADR & EPBUFA_MASK)) + +/*----------------------------------------------------------------------------------------------------------*/ +/* Endpoint7 Configuration */ +/*----------------------------------------------------------------------------------------------------------*/ +#define _EP7STADR (_EP6STADR + _EP6LEN_T) + +#if (_EP7_ENABLE == 1) + #define _EP7LEN (_EP7LEN_TMP) + #define _EP7LEN_T (_EP7LEN_TMP * (_EP7_CFG_SDBS + 1)) +#else + #define _EP7LEN (0) + #define _EP7LEN_T (0) +#endif +#if (_EP7_TYPR == EP_TYPE_ISO) + #define _EP7_CFG_EPTYPE (1) +#else + #define _EP7_CFG_EPTYPE (0) +#endif + +#if (_EP7_CFG_EPEN_TMP == 1) + #define _EP7_CFG_EPEN (1UL) +#else + #define _EP7_CFG_EPEN (0UL) +#endif + +#define _EP7_CFG ((_EP7_CFG_EPEN << 31) | \ + (_EP7_CFG_EPTYPE << 29) | \ + (_EP7_CFG_EPDIR << 28) | \ + (_EP7_CFG_EPADR << 24) | \ + (_EP7_CFG_SDBS << 23) | \ + (_EP7LEN << 10) | \ + (_EP7STADR & EPBUFA_MASK)) + +/*----------------------------------------------------------------------------------------------------------*/ +/* Endpoint8 Configuration */ +/*----------------------------------------------------------------------------------------------------------*/ +#define _EP8STADR (_EP7STADR + _EP7LEN_T) + +#if (_EP8_ENABLE == 1) + #define _EP8LEN (_EP8LEN_TMP) +#else + #define _EP8LEN (0) +#endif + +#if (_EP8_CFG_EPEN_TMP == 1) + #define _EP8_CFG_EPEN (1UL) +#else + #define _EP8_CFG_EPEN (0UL) +#endif + +#define _EP8_CFG ((_EP8_CFG_EPEN << 31) | \ + (_EP8_CFG_EPDIR << 28) | \ + (_EP8_CFG_EPADR << 24) | \ + (_EP8LEN << 10) | \ + (_EP8STADR & EPBUFA_MASK)) + + +/*----------------------------------------------------------------------------------------------------------*/ +/* Endpoint9 Configuration */ +/*----------------------------------------------------------------------------------------------------------*/ +#define _EP9STADR (_EP8STADR + _EP8LEN) + +#if (_EP9_ENABLE == 1) + #define _EP9LEN (_EP9LEN_TMP) +#else + #define _EP9LEN (0) +#endif + +#if (_EP9_CFG_EPEN_TMP == 1) + #define _EP9_CFG_EPEN (1UL) +#else + #define _EP9_CFG_EPEN (0UL) +#endif + +#define _EP9_CFG ((_EP9_CFG_EPEN << 31) | \ + (_EP9_CFG_EPDIR << 28) | \ + (_EP9_CFG_EPADR << 24) | \ + (_EP9LEN << 10) | \ + (_EP9STADR & EPBUFA_MASK)) + + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f5xxxx_wdt.h b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f5xxxx_wdt.h new file mode 100644 index 0000000000..ae5fdd1c5e --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f5xxxx_wdt.h @@ -0,0 +1,149 @@ +/*********************************************************************************************************//** + * @file ht32f5xxxx_wdt.h + * @version $Rev:: 1704 $ + * @date $Date:: 2017-08-17 #$ + * @brief The header file of the WDT library. + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------------------------------------*/ +#ifndef __HT32F5XXXX_WDT_H +#define __HT32F5XXXX_WDT_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------------------------------------*/ +#include "ht32.h" + +/** @addtogroup HT32F5xxxx_Peripheral_Driver HT32F5xxxx Peripheral Driver + * @{ + */ + +/** @addtogroup WDT + * @{ + */ + + +/* Exported constants --------------------------------------------------------------------------------------*/ +/** @defgroup WDT_Exported_Constants WDT exported constants + * @{ + */ + +/* WDT prescaler */ +#define WDT_PRESCALER_1 ((u16)0x0000) +#define WDT_PRESCALER_2 ((u16)0x1000) +#define WDT_PRESCALER_4 ((u16)0x2000) +#define WDT_PRESCALER_8 ((u16)0x3000) +#define WDT_PRESCALER_16 ((u16)0x4000) +#define WDT_PRESCALER_32 ((u16)0x5000) +#define WDT_PRESCALER_64 ((u16)0x6000) +#define WDT_PRESCALER_128 ((u16)0x7000) + +#define IS_WDT_PRESCALER(PRESCALER) ((PRESCALER == WDT_PRESCALER_1) || \ + (PRESCALER == WDT_PRESCALER_2) || \ + (PRESCALER == WDT_PRESCALER_4) || \ + (PRESCALER == WDT_PRESCALER_8) || \ + (PRESCALER == WDT_PRESCALER_16) || \ + (PRESCALER == WDT_PRESCALER_32) || \ + (PRESCALER == WDT_PRESCALER_64) || \ + (PRESCALER == WDT_PRESCALER_128)) + + +/* WDT runs or halts in sleep and deep sleep1 mode */ +/* WDT WDTSHLT mask */ +#define MODE0_WDTSHLT_BOTH ((u32)0x00000000) +#define MODE0_WDTSHLT_SLEEP ((u32)0x00004000) +#define MODE0_WDTSHLT_HALT ((u32)0x00008000) + +#define IS_WDT_WDTSHLT_MODE(WDT_Mode) ((WDT_Mode == MODE0_WDTSHLT_BOTH) || \ + (WDT_Mode == MODE0_WDTSHLT_SLEEP) || \ + (WDT_Mode == MODE0_WDTSHLT_HALT)) + + + +/* WDT Flag */ +#define WDT_FLAG_UNDERFLOW ((u32)0x00000001) +#define WDT_FLAG_ERROR ((u32)0x00000002) + + +#define IS_WDT_FLAG(WDT_FLAG) ((WDT_FLAG == WDT_FLAG_UNDERFLOW) || \ + (WDT_FLAG == WDT_FLAG_ERROR)) + + +#define IS_WDT_RELOAD(WDTV) ((WDTV <= 0xFFF)) + +#define IS_WDT_DELTA(WDTD) ((WDTD <= 0xFFF)) + +#if (LIBCFG_LSE) +/* WDT Source Select */ +#define WDT_SOURCE_LSI ((u32)0x00000000) +#define WDT_SOURCE_LSE ((u32)0x00000001) + + +#define IS_WDT_SOURCE_SELECT(WDT_SOURCE) ((WDT_SOURCE == WDT_SOURCE_LSI) || \ + (WDT_SOURCE == WDT_SOURCE_LSE)) +#endif +/** + * @} + */ + +/* Exported functions --------------------------------------------------------------------------------------*/ +/** @defgroup WDT_Exported_Functions WDT exported functions + * @{ + */ +void WDT_DeInit(void); +void WDT_Cmd(ControlStatus NewState); +void WDT_HaltConfig(u32 WDT_Mode); +void WDT_ResetCmd(ControlStatus NewState); +void WDT_ProtectCmd(ControlStatus NewState); +void WDT_SetReloadValue(u16 WDTV); +u16 WDT_GetReloadValue(void); +void WDT_SetDeltaValue(u16 WDTD); +u16 WDT_GetDeltaValue(void); +void WDT_SetPrescaler(u16 WDT_PRESCALER); +u8 WDT_GetPrescaler(void); +void WDT_Restart(void); +FlagStatus WDT_GetFlagStatus (u32 WDT_FLAG); +void WDT_LockCmd(ControlStatus NewState); +#if (LIBCFG_LSE) +void WDT_SourceConfig(u32 WDT_SOURCE); +#endif +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f61141_libcfg.h b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f61141_libcfg.h new file mode 100644 index 0000000000..030674e28b --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f61141_libcfg.h @@ -0,0 +1,76 @@ +/*********************************************************************************************************//** + * @file ht32f61141_libcfg.h + * @version $Rev:: 6386 $ + * @date $Date:: 2022-10-27 #$ + * @brief The library configuration file. + ************************************************************************************************************* +* @attention +* +* Firmware Disclaimer Information +* +* 1. The customer hereby acknowledges and agrees that the program technical documentation, including the +* code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the +* proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and +* other intellectual property laws. +* +* 2. The customer hereby acknowledges and agrees that the program technical documentation, including the +* code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties +* other than HOLTEK and the customer. +* +* 3. The program technical documentation, including the code, is provided "as is" and for customer reference +* only. After delivery by HOLTEK, the customer shall use the program technical documentation, including +* the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including +* the warranties of merchantability, satisfactory quality and fitness for a particular purpose. +* +*

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ +/* Define to prevent recursive inclusion -------------------------------------------------------------------*/ +#ifndef __HT32F61141_LIBCFG_H +#define __HT32F61141_LIBCFG_H + +/* Settings ------------------------------------------------------------------------------------------------*/ + +#if !defined(USE_MEM_HT32F61141) +#define USE_MEM_HT32F61141 +#endif + +#define LIBCFG_MAX_SPEED (48000000) + +#define LIBCFG_FLASH_PAGESIZE (1024) + +#ifdef USE_MEM_HT32F61141 + #define LIBCFG_FLASH_SIZE (LIBCFG_FLASH_PAGESIZE * 63) + #define LIBCFG_RAM_SIZE (1024 * 16) + #define LIBCFG_CHIPNAME (0x61141) +#endif + +#define LIBCFG_NO_ADC (1) +#define LIBCFG_BFTM1 (1) +#define LIBCFG_CKCU_ATM_V01 (1) +#define LIBCFG_CKCU_REFCLK_EXT_PIN (1) +#define LIBCFG_CRC (1) +#define LIBCFG_FMC_PREFETCH (1) +#define LIBCFG_FMC_WAIT_STATE_2 (1) +#define LIBCFG_GPIOC (1) +#define LIBCFG_LSE (1) +#define LIBCFG_PWRCU_NO_PD_MODE (1) +#define LIBCFG_PWRCU_NO_PDF (1) +#define LIBCFG_PWRCU_NO_VDDPORF (1) +#define LIBCFG_NO_PWRCU_TEST_REG (1) +#define LIBCFG_NO_USART0 (1) +#define LIBCFG_PWRCU_WAKEUP_V01 (1) +#define LIBCFG_PWRCU_WAKEUP1 (1) +#define LIBCFG_PWRCU_PORF (1) +#define LIBCFG_PWRCU_VREG (1) +#define LIBCFG_PWRCU_VREG_2V5 (1) +#define LIBCFG_SCI0 (1) +#define LIBCFG_SCI1 (1) +#define LIBCFG_SCTM0 (1) +#define LIBCFG_SCTM1 (1) +#define LIBCFG_PWRCU_VDD_5V (1) +#define LIBCFG_UART1 (1) +#define LIBCFG_USBD (1) +#define LIBCFG_USBD_V2 (1) + + +#endif diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f61244_45_libcfg.h b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f61244_45_libcfg.h new file mode 100644 index 0000000000..b7ed32e296 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f61244_45_libcfg.h @@ -0,0 +1,73 @@ +/*********************************************************************************************************//** + * @file ht32f61244_45_libcfg.h + * @version $Rev:: 6719 $ + * @date $Date:: 2023-02-08 #$ + * @brief The library configuration file. + ************************************************************************************************************* +* @attention +* +* Firmware Disclaimer Information +* +* 1. The customer hereby acknowledges and agrees that the program technical documentation, including the +* code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the +* proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and +* other intellectual property laws. +* +* 2. The customer hereby acknowledges and agrees that the program technical documentation, including the +* code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties +* other than HOLTEK and the customer. +* +* 3. The program technical documentation, including the code, is provided "as is" and for customer reference +* only. After delivery by HOLTEK, the customer shall use the program technical documentation, including +* the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including +* the warranties of merchantability, satisfactory quality and fitness for a particular purpose. +* +*

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ +/* Define to prevent recursive inclusion -------------------------------------------------------------------*/ +#ifndef __HT32F61244_45_LIBCFG_H +#define __HT32F61244_45_LIBCFG_H + +/* Settings ------------------------------------------------------------------------------------------------*/ + +#if !defined(USE_MEM_HT32F61244) && !defined(USE_MEM_HT32F61245) +#define USE_MEM_HT32F61245 +#endif + +#define LIBCFG_MAX_SPEED (48000000) + +#define LIBCFG_FLASH_PAGESIZE (512) + +#ifdef USE_MEM_HT32F61244 + #define LIBCFG_FLASH_SIZE (LIBCFG_FLASH_PAGESIZE * 63) + #define LIBCFG_RAM_SIZE (1024 * 8) + #define LIBCFG_CHIPNAME (0x61244) +#endif + +#ifdef USE_MEM_HT32F61245 + #define LIBCFG_FLASH_SIZE (LIBCFG_FLASH_PAGESIZE * 63) + #define LIBCFG_RAM_SIZE (1024 * 8) + #define LIBCFG_CHIPNAME (0x61245) +#endif + +#define LIBCFG_BFTM1 (1) +#define LIBCFG_DACDUAL16 (1) +#define LIBCFG_GPIOC (1) +#define LIBCFG_GPIOD (1) +#define LIBCFG_MIDI (1) +#define LIBCFG_NO_USART0 (1) +#define LIBCFG_PDMA (1) +#define LIBCFG_QSPI (1) +#define LIBCFG_SCTM0 (1) +#define LIBCFG_SCTM1 (1) + +#define LIBCFG_ADC_CH8_11 (1) +#define LIBCFG_ADC_CH12_15 (1) +#define LIBCFG_CKCU_NO_AUTO_TRIM (1) +#define LIBCFG_FMC_PREFETCH (1) +#define LIBCFG_FMC_WAIT_STATE_2 (1) +#define LIBCFG_PWRCU_VDD_2V0_3V6 (1) +#define LIBCFG_PWRCU_V15_READY_SOURCE (1) +#define LIBCFG_TM_NO_ITI (1) + +#endif diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f65230_40_libcfg.h b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f65230_40_libcfg.h new file mode 100644 index 0000000000..bbf4192d74 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f65230_40_libcfg.h @@ -0,0 +1,92 @@ +/*********************************************************************************************************//** + * @file ht32f65230_40_libcfg.h + * @version $Rev:: 7184 $ + * @date $Date:: 2023-08-31 #$ + * @brief The library configuration file. + ************************************************************************************************************* +* @attention +* +* Firmware Disclaimer Information +* +* 1. The customer hereby acknowledges and agrees that the program technical documentation, including the +* code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the +* proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and +* other intellectual property laws. +* +* 2. The customer hereby acknowledges and agrees that the program technical documentation, including the +* code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties +* other than HOLTEK and the customer. +* +* 3. The program technical documentation, including the code, is provided "as is" and for customer reference +* only. After delivery by HOLTEK, the customer shall use the program technical documentation, including +* the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including +* the warranties of merchantability, satisfactory quality and fitness for a particular purpose. +* +*

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ +/* Define to prevent recursive inclusion -------------------------------------------------------------------*/ +#ifndef __HT32F65230_40_LIBCFG_H +#define __HT32F65230_40_LIBCFG_H + +/* Settings ------------------------------------------------------------------------------------------------*/ + +#if !defined(USE_MEM_HT32F65240) && !defined(USE_MEM_HT32F65230) +#define USE_MEM_HT32F65240 +#endif + +#define LIBCFG_MAX_SPEED (60000000) + +#define LIBCFG_FLASH_PAGESIZE (1024) + +#ifdef USE_MEM_HT32F65230 + #define LIBCFG_FLASH_SIZE (LIBCFG_FLASH_PAGESIZE * 32) + #define LIBCFG_RAM_SIZE (1024 * 4) + #define LIBCFG_CHIPNAME (0x65230) +#endif + +#ifdef USE_MEM_HT32F65240 + #define LIBCFG_FLASH_SIZE (LIBCFG_FLASH_PAGESIZE * 63) + #define LIBCFG_RAM_SIZE (1024 * 8) + #define LIBCFG_CHIPNAME (0x65240) +#endif + +#define LIBCFG_ADC1 (1) +#define LIBCFG_ADC_SAMPLE_TIME_BY_CH (1) +#define LIBCFG_ADC_TRIG_DELAY (1) +#define LIBCFG_BFTM1 (1) +#define LIBCFG_CKCU_ATM_V01 (1) +#define LIBCFG_CKCU_NO_ADCPRE_DIV1 (1) +#define LIBCFG_CKCU_PLLSRCDIV (1) +#define LIBCFG_CKCU_SYS_CK_60M (1) +#define LIBCFG_CMP (1) +#define LIBCFG_CMP2 (1) +#define LIBCFG_CMP_NOSCALER_SRC (1) +#define LIBCFG_CMP_65x_VER (1) +#define LIBCFG_CRC (1) +#define LIBCFG_DIV (1) +#define LIBCFG_EXTI_4_9_GROUP (1) +#define LIBCFG_FMC_BRANCHCACHE (1) +#define LIBCFG_FMC_PREFETCH (1) +#define LIBCFG_FMC_WAIT_STATE_2 (1) +#define LIBCFG_GPIOC (1) +#define LIBCFG_GPTM_GIRQ (1) +#define LIBCFG_LSE (1) +#define LIBCFG_MCTM0 (1) +#define LIBCFG_MCTM_UEV1DIS (1) +#define LIBCFG_PWRCU_NO_PD_MODE (1) +#define LIBCFG_PWRCU_NO_PDF (1) +#define LIBCFG_PWRCU_NO_VDDPORF (1) +#define LIBCFG_NO_PWRCU_TEST_REG (1) +#define LIBCFG_OPA (1) +#define LIBCFG_OPA1 (1) +#define LIBCFG_PDMA (1) +#define LIBCFG_PDMA_CH3FIX (1) +#define LIBCFG_SCTM0 (1) +#define LIBCFG_SCTM1 (1) +#define LIBCFG_SCTM2 (1) +#define LIBCFG_SCTM3 (1) +#define LIBCFG_TM_652XX_V1 (1) +#define LIBCFG_PWRCU_VDD_5V (1) +#define LIBCFG_PWRCU_NO_PORF (1) + +#endif diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f65232_libcfg.h b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f65232_libcfg.h new file mode 100644 index 0000000000..8787c99413 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f65232_libcfg.h @@ -0,0 +1,90 @@ +/*********************************************************************************************************//** + * @file ht32f65232_libcfg.h + * @version $Rev:: 6932 $ + * @date $Date:: 2023-05-11 #$ + * @brief The library configuration file. + ************************************************************************************************************* +* @attention +* +* Firmware Disclaimer Information +* +* 1. The customer hereby acknowledges and agrees that the program technical documentation, including the +* code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the +* proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and +* other intellectual property laws. +* +* 2. The customer hereby acknowledges and agrees that the program technical documentation, including the +* code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties +* other than HOLTEK and the customer. +* +* 3. The program technical documentation, including the code, is provided "as is" and for customer reference +* only. After delivery by HOLTEK, the customer shall use the program technical documentation, including +* the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including +* the warranties of merchantability, satisfactory quality and fitness for a particular purpose. +* +*

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ +/* Define to prevent recursive inclusion -------------------------------------------------------------------*/ +#ifndef __HT32F65232_LIBCFG_H +#define __HT32F65232_LIBCFG_H + +/* Settings ------------------------------------------------------------------------------------------------*/ + +#if !defined(USE_MEM_HT32F65232) +#define USE_MEM_HT32F65232 +#endif + +#define LIBCFG_MAX_SPEED (60000000) + +#define LIBCFG_FLASH_PAGESIZE (1024) + +#ifdef USE_MEM_HT32F65232 + #define LIBCFG_FLASH_SIZE (LIBCFG_FLASH_PAGESIZE * 31) + #define LIBCFG_RAM_SIZE (1024 * 4) + #define LIBCFG_CHIPNAME (0x65232) +#endif + +#define LIBCFG_ADC_SAMPLE_TIME_BY_CH (1) +#define LIBCFG_ADC_TRIG_SRC_V2 (1) +#define LIBCFG_ADC_TRIG_DELAY (1) +#define LIBCFG_ADC_CH_65232 (1) +#define LIBCFG_AFIO_SCTM_MODE9 (1) +#define LIBCFG_BFTM1 (1) +#define LIBCFG_CKCU_ATM_V01 (1) +#define LIBCFG_CKCU_NO_ADCPRE_DIV1 (1) +#define LIBCFG_CKCU_PLLSRCDIV (1) +#define LIBCFG_CKCU_SYS_CK_60M (1) +#define LIBCFG_CMP (1) +#define LIBCFG_CMP_NOSCALER_SRC (1) +#define LIBCFG_CMP_65x_VER (1) +#define LIBCFG_CMP_POS_INPUT_SEL_V2 (1) +#define LIBCFG_CMP_CO (1) +#define LIBCFG_CMP_SCALER_8BIT (1) +#define LIBCFG_CRC (1) +#define LIBCFG_DIV (1) +#define LIBCFG_EXTI_4_9_GROUP (1) +#define LIBCFG_FMC_BRANCHCACHE (1) +#define LIBCFG_FMC_PREFETCH (1) +#define LIBCFG_FMC_WAIT_STATE_2 (1) +#define LIBCFG_GPIOC (1) +#define LIBCFG_GPTM_GIRQ (1) +#define LIBCFG_MCTM0 (1) +#define LIBCFG_MCTM_UEV1DIS (1) +#define LIBCFG_PWRCU_NO_PD_MODE (1) +#define LIBCFG_PWRCU_NO_PDF (1) +#define LIBCFG_PWRCU_NO_VDDPORF (1) +#define LIBCFG_NO_PWRCU_TEST_REG (1) +#define LIBCFG_OPA (1) +#define LIBCFG_OPA_V2 (1) +#define LIBCFG_PDMA (1) +#define LIBCFG_SCTM0 (1) +#define LIBCFG_SCTM1 (1) +#define LIBCFG_SCTM2 (1) +#define LIBCFG_SCTM3 (1) +#define LIBCFG_TM_652XX_V1 (1) +#define LIBCFG_TM_65232 (1) +#define LIBCFG_TM_TIFN_5BIT (1) +#define LIBCFG_PWRCU_VDD_5V (1) +#define LIBCFG_PWRCU_NO_PORF (1) + +#endif diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f65xxx_66xxx_adc.h b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f65xxx_66xxx_adc.h new file mode 100644 index 0000000000..0b0313fc40 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f65xxx_66xxx_adc.h @@ -0,0 +1,417 @@ +/*********************************************************************************************************//** + * @file ht32f65xxx_66xxx_adc.h + * @version $Rev:: 7058 $ + * @date $Date:: 2023-07-27 #$ + * @brief The header file of the ADC library. + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------------------------------------*/ +#ifndef __HT32F65XXX_66XXX_ADC_H +#define __HT32F65XXX_66XXX_ADC_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------------------------------------*/ +#include "ht32.h" + +/** @addtogroup HT32F5xxxx_Peripheral_Driver HT32F5xxxx Peripheral Driver + * @{ + */ + +/** @addtogroup ADC + * @{ + */ + + +/* Exported constants --------------------------------------------------------------------------------------*/ +/** @defgroup ADC_Exported_Constants ADC exported constants + * @{ + */ +#if (LIBCFG_ADC1) +#define IS_ADC(x) ((x == HT_ADC0) || (x == HT_ADC1)) +#else +#define IS_ADC(x) (x == HT_ADC0) +#endif + +#define ONE_SHOT_MODE (0x00000000) +#define CONTINUOUS_MODE (0x00000002) +#define DISCONTINUOUS_MODE (0x00000003) + +#define IS_ADC_CONVERSION_MODE(REGULAR_MODE) (((REGULAR_MODE) == ONE_SHOT_MODE) || \ + ((REGULAR_MODE) == CONTINUOUS_MODE) || \ + ((REGULAR_MODE) == DISCONTINUOUS_MODE)) + +#define IS_ADC_HP_CONVERSION_MODE(HP_MODE) (((HP_MODE) == ONE_SHOT_MODE) || \ + ((HP_MODE) == CONTINUOUS_MODE) || \ + ((HP_MODE) == DISCONTINUOUS_MODE)) + +#define DUAL_INDEPENDENT (0x00000000) +#define DUAL_CASCADE_REGULAR (0x00000001) +#define DUAL_CASCADE_REGULAR_H_PRIORITY (0x00000003) + +#define IS_ADC_DUAL_MODE(DUAL_MODE) (((DUAL_MODE) == DUAL_INDEPENDENT) || \ + ((DUAL_MODE) == DUAL_CASCADE_REGULAR) || \ + ((DUAL_MODE) == DUAL_CASCADE_REGULAR_H_PRIORITY)) + +#if (LIBCFG_ADC_CH_65232) +#define ADC_CH_0 (0) +#define ADC_CH_1 (1) +#define ADC_CH_2 (2) +#define ADC_CH_3 (3) +#define ADC_CH_4 (4) +#define ADC_CH_5 (5) +#define ADC_CH_6 (6) +#define ADC_CH_7 (7) +#define ADC_CH_8 (8) +#define ADC_CH_9 (9) +#define ADC_CH_10 (10) +#define ADC_CH_11 (11) +#define ADC_CH_OPA0 (12) +#define ADC_CH_GND_VREF (13) +#define ADC_CH_VDD_VREF (14) + +#define IS_ADC_CHANNEL(CHANNEL) (((CHANNEL) == ADC_CH_0) || ((CHANNEL) == ADC_CH_1) || \ + ((CHANNEL) == ADC_CH_2) || ((CHANNEL) == ADC_CH_3) || \ + ((CHANNEL) == ADC_CH_4) || ((CHANNEL) == ADC_CH_5) || \ + ((CHANNEL) == ADC_CH_6) || ((CHANNEL) == ADC_CH_7) || \ + ((CHANNEL) == ADC_CH_8) || ((CHANNEL) == ADC_CH_9) || \ + ((CHANNEL) == ADC_CH_10) || ((CHANNEL) == ADC_CH_11) || \ + ((CHANNEL) == ADC_CH_OPA0) || \ + ((CHANNEL) == ADC_CH_GND_VREF) || ((CHANNEL) == ADC_CH_VDD_VREF)) + +#define IS_ADC_INPUT_CHANNEL(CHANNEL) (((CHANNEL) == ADC_CH_0) || ((CHANNEL) == ADC_CH_1) || \ + ((CHANNEL) == ADC_CH_2) || ((CHANNEL) == ADC_CH_3) || \ + ((CHANNEL) == ADC_CH_4) || ((CHANNEL) == ADC_CH_5) || \ + ((CHANNEL) == ADC_CH_6) || ((CHANNEL) == ADC_CH_7) || \ + ((CHANNEL) == ADC_CH_OPA0)) +#else +#define ADC_CH_0 (0) +#define ADC_CH_1 (1) +#define ADC_CH_2 (2) +#define ADC_CH_3 (3) +#define ADC_CH_4 (4) +#define ADC_CH_5 (5) +#define ADC_CH_6 (6) +#define ADC_CH_7 (7) +#define ADC_CH_OPA0 (8) +#define ADC_CH_OPA1 (9) +#define ADC_CH_GND_VREF (12) +#define ADC_CH_VDD_VREF (13) + +#define IS_ADC_CHANNEL(CHANNEL) (((CHANNEL) == ADC_CH_0) || ((CHANNEL) == ADC_CH_1) || \ + ((CHANNEL) == ADC_CH_2) || ((CHANNEL) == ADC_CH_3) || \ + ((CHANNEL) == ADC_CH_4) || ((CHANNEL) == ADC_CH_5) || \ + ((CHANNEL) == ADC_CH_6) || ((CHANNEL) == ADC_CH_7) || \ + ((CHANNEL) == ADC_CH_OPA0) || ((CHANNEL) == ADC_CH_OPA1) || \ + ((CHANNEL) == ADC_CH_GND_VREF) || ((CHANNEL) == ADC_CH_VDD_VREF)) + +#define IS_ADC_INPUT_CHANNEL(CHANNEL) (((CHANNEL) == ADC_CH_0) || ((CHANNEL) == ADC_CH_1) || \ + ((CHANNEL) == ADC_CH_2) || ((CHANNEL) == ADC_CH_3) || \ + ((CHANNEL) == ADC_CH_4) || ((CHANNEL) == ADC_CH_5) || \ + ((CHANNEL) == ADC_CH_6) || ((CHANNEL) == ADC_CH_7) || \ + ((CHANNEL) == ADC_CH_OPA0) || ((CHANNEL) == ADC_CH_OPA1)) +#endif + + +#define ADC_TRIG_SOFTWARE (1UL << 0) + +#define ADC_TRIG_MCTM0_MTO ((1UL << 2) | (0UL << 24) | (0UL << 16)) +#define ADC_TRIG_MCTM0_CH0O ((1UL << 2) | (1UL << 24) | (0UL << 16)) +#define ADC_TRIG_MCTM0_CH1O ((1UL << 2) | (2UL << 24) | (0UL << 16)) +#define ADC_TRIG_MCTM0_CH2O ((1UL << 2) | (3UL << 24) | (0UL << 16)) +#define ADC_TRIG_MCTM0_CH3O ((1UL << 2) | (4UL << 24) | (0UL << 16)) +#define ADC_TRIG_MCTM0_CH0MEV ((1UL << 2) | (0x18UL << 24) | (0UL << 16)) +#define ADC_TRIG_MCTM0_CH0DEV ((1UL << 2) | (0x28UL << 24) | (0UL << 16)) +#define ADC_TRIG_MCTM0_CH0MDEV ((1UL << 2) | (0x38UL << 24) | (0UL << 16)) +#define ADC_TRIG_MCTM0_CH1MEV ((1UL << 2) | (0x19UL << 24) | (0UL << 16)) +#define ADC_TRIG_MCTM0_CH1DEV ((1UL << 2) | (0x29UL << 24) | (0UL << 16)) +#define ADC_TRIG_MCTM0_CH1MDEV ((1UL << 2) | (0x39UL << 24) | (0UL << 16)) +#define ADC_TRIG_MCTM0_CH2MEV ((1UL << 2) | (0x1AUL << 24) | (0UL << 16)) +#define ADC_TRIG_MCTM0_CH2DEV ((1UL << 2) | (0x2AUL << 24) | (0UL << 16)) +#define ADC_TRIG_MCTM0_CH2MDEV ((1UL << 2) | (0x3AUL << 24) | (0UL << 16)) +#define ADC_TRIG_MCTM0_CH3MEV ((1UL << 2) | (0x1BUL << 24) | (0UL << 16)) +#define ADC_TRIG_MCTM0_CH3DEV ((1UL << 2) | (0x2BUL << 24) | (0UL << 16)) +#define ADC_TRIG_MCTM0_CH3MDEV ((1UL << 2) | (0x3BUL << 24) | (0UL << 16)) + +#define IS_ADC_TRIG_MCTM0_CHALL(REGTRIG) (0) + +#if (LIBCFG_ADC_TRIG_SRC_V2) +#define ADC_TRIG_MCTM0_CHALLMEV ((1UL << 2) | (0x1CUL << 24) | (0UL << 16)) +#define ADC_TRIG_MCTM0_CHALLDEV ((1UL << 2) | (0x2CUL << 24) | (0UL << 16)) +#define ADC_TRIG_MCTM0_CHALLMDEV ((1UL << 2) | (0x3CUL << 24) | (0UL << 16)) + +#undef IS_ADC_TRIG_MCTM0_CHALL +#define IS_ADC_TRIG_MCTM0_CHALL(REGTRIG) ((REGTRIG == ADC_TRIG_MCTM0_CHALLMEV) || \ + (REGTRIG == ADC_TRIG_MCTM0_CHALLDEV) || \ + (REGTRIG == ADC_TRIG_MCTM0_CHALLMDEV)) +#endif + +#define ADC_TRIG_CMP0 ((1UL << 4) | (0UL << 20)) +#define ADC_TRIG_CMP1 ((1UL << 4) | (1UL << 20)) +#define ADC_TRIG_CMP2 ((1UL << 4) | (2UL << 20)) + +#define ADC_TRIG_BFTM0 ((1UL << 3) | (0UL << 22) | (0UL << 19)) +#define ADC_TRIG_BFTM1 ((1UL << 3) | (0UL << 22) | (1UL << 19)) + +#define ADC_TRIG_GPTM0_MTO ((1UL << 2) | (0UL << 24) | (1UL << 16)) +#define ADC_TRIG_GPTM0_CH0O ((1UL << 2) | (1UL << 24) | (1UL << 16)) +#define ADC_TRIG_GPTM0_CH1O ((1UL << 2) | (2UL << 24) | (1UL << 16)) +#define ADC_TRIG_GPTM0_CH2O ((1UL << 2) | (3UL << 24) | (1UL << 16)) +#define ADC_TRIG_GPTM0_CH3O ((1UL << 2) | (4UL << 24) | (1UL << 16)) + +#define ADC_TRIG_EXTI_0 ((1UL << 1) | ( 0UL << 8)) +#define ADC_TRIG_EXTI_1 ((1UL << 1) | ( 1UL << 8)) +#define ADC_TRIG_EXTI_2 ((1UL << 1) | ( 2UL << 8)) +#define ADC_TRIG_EXTI_3 ((1UL << 1) | ( 3UL << 8)) +#define ADC_TRIG_EXTI_4 ((1UL << 1) | ( 4UL << 8)) +#define ADC_TRIG_EXTI_5 ((1UL << 1) | ( 5UL << 8)) +#define ADC_TRIG_EXTI_6 ((1UL << 1) | ( 6UL << 8)) +#define ADC_TRIG_EXTI_7 ((1UL << 1) | ( 7UL << 8)) +#define ADC_TRIG_EXTI_8 ((1UL << 1) | ( 8UL << 8)) +#define ADC_TRIG_EXTI_9 ((1UL << 1) | ( 9UL << 8)) +#define ADC_TRIG_EXTI_10 ((1UL << 1) | (10UL << 8)) +#define ADC_TRIG_EXTI_11 ((1UL << 1) | (11UL << 8)) +#define ADC_TRIG_EXTI_12 ((1UL << 1) | (12UL << 8)) +#define ADC_TRIG_EXTI_13 ((1UL << 1) | (13UL << 8)) +#define ADC_TRIG_EXTI_14 ((1UL << 1) | (14UL << 8)) +#define ADC_TRIG_EXTI_15 ((1UL << 1) | (15UL << 8)) + +#define IS_ADC_TRIG(REGTRIG) (((REGTRIG) == ADC_TRIG_GPTM0_MTO) || \ + ((REGTRIG) == ADC_TRIG_GPTM0_CH0O) || \ + ((REGTRIG) == ADC_TRIG_GPTM0_CH1O) || \ + ((REGTRIG) == ADC_TRIG_GPTM0_CH2O) || \ + ((REGTRIG) == ADC_TRIG_GPTM0_CH3O) || \ + ((REGTRIG) == ADC_TRIG_MCTM0_MTO) || \ + ((REGTRIG) == ADC_TRIG_MCTM0_CH0O) || \ + ((REGTRIG) == ADC_TRIG_MCTM0_CH1O) || \ + ((REGTRIG) == ADC_TRIG_MCTM0_CH2O) || \ + ((REGTRIG) == ADC_TRIG_MCTM0_CH3O) || \ + ((REGTRIG) == ADC_TRIG_MCTM0_CH0MEV) || \ + ((REGTRIG) == ADC_TRIG_MCTM0_CH0DEV) || \ + ((REGTRIG) == ADC_TRIG_MCTM0_CH0MDEV) || \ + ((REGTRIG) == ADC_TRIG_MCTM0_CH1MEV) || \ + ((REGTRIG) == ADC_TRIG_MCTM0_CH1DEV) || \ + ((REGTRIG) == ADC_TRIG_MCTM0_CH1MDEV) || \ + ((REGTRIG) == ADC_TRIG_MCTM0_CH2MEV) || \ + ((REGTRIG) == ADC_TRIG_MCTM0_CH2DEV) || \ + ((REGTRIG) == ADC_TRIG_MCTM0_CH2MDEV) || \ + ((REGTRIG) == ADC_TRIG_MCTM0_CH3MEV) || \ + ((REGTRIG) == ADC_TRIG_MCTM0_CH3DEV) || \ + ((REGTRIG) == ADC_TRIG_MCTM0_CH3MDEV) || \ + (IS_ADC_TRIG_MCTM0_CHALL(REGTRIG)) || \ + ((REGTRIG) == ADC_TRIG_BFTM0) || \ + ((REGTRIG) == ADC_TRIG_BFTM1) || \ + ((REGTRIG) == ADC_TRIG_CMP0) || \ + ((REGTRIG) == ADC_TRIG_CMP1) || \ + ((REGTRIG) == ADC_TRIG_CMP2) || \ + ((REGTRIG) == ADC_TRIG_EXTI_0) || \ + ((REGTRIG) == ADC_TRIG_EXTI_1) || \ + ((REGTRIG) == ADC_TRIG_EXTI_2) || \ + ((REGTRIG) == ADC_TRIG_EXTI_3) || \ + ((REGTRIG) == ADC_TRIG_EXTI_4) || \ + ((REGTRIG) == ADC_TRIG_EXTI_5) || \ + ((REGTRIG) == ADC_TRIG_EXTI_6) || \ + ((REGTRIG) == ADC_TRIG_EXTI_7) || \ + ((REGTRIG) == ADC_TRIG_EXTI_8) || \ + ((REGTRIG) == ADC_TRIG_EXTI_9) || \ + ((REGTRIG) == ADC_TRIG_EXTI_10) || \ + ((REGTRIG) == ADC_TRIG_EXTI_11) || \ + ((REGTRIG) == ADC_TRIG_EXTI_12) || \ + ((REGTRIG) == ADC_TRIG_EXTI_13) || \ + ((REGTRIG) == ADC_TRIG_EXTI_14) || \ + ((REGTRIG) == ADC_TRIG_EXTI_15) || \ + ((REGTRIG) == ADC_TRIG_SOFTWARE)) + + +#define ADC_INT_SINGLE_EOC (0x00000001) +#define ADC_INT_SUB_GROUP_EOC (0x00000002) +#define ADC_INT_CYCLE_EOC (0x00000004) +#define ADC_INT_HP_SINGLE_EOC (0x00000100) +#define ADC_INT_HP_SUB_GROUP_EOC (0x00000200) +#define ADC_INT_HP_CYCLE_EOC (0x00000400) +#define ADC_INT_AWD_LOWER (0x00010000) +#define ADC_INT_AWD_UPPER (0x00020000) +#define ADC_INT_DATA_OVERWRITE (0x01000000) +#define ADC_INT_HP_DATA_OVERWRITE (0x02000000) + +#define IS_ADC_INT(INT) ((((INT) & 0xFCFCFF88) == 0) && ((INT) != 0)) + + +#define ADC_FLAG_SINGLE_EOC (0x00000001) +#define ADC_FLAG_SUB_GROUP_EOC (0x00000002) +#define ADC_FLAG_CYCLE_EOC (0x00000004) +#define ADC_FLAG_HP_SINGLE_EOC (0x00000100) +#define ADC_FLAG_HP_SUB_GROUP_EOC (0x00000200) +#define ADC_FLAG_HP_CYCLE_EOC (0x00000400) +#define ADC_FLAG_AWD_LOWER (0x00010000) +#define ADC_FLAG_AWD_UPPER (0x00020000) +#define ADC_FLAG_DATA_OVERWRITE (0x01000000) +#define ADC_FLAG_HP_DATA_OVERWRITE (0x02000000) + +#define IS_ADC_FLAG(FLAG) ((((FLAG) & 0xFCFCFF88) == 0) && ((FLAG) != 0)) + + +#define ADC_REGULAR_DATA0 (0) +#define ADC_REGULAR_DATA1 (1) +#define ADC_REGULAR_DATA2 (2) +#define ADC_REGULAR_DATA3 (3) +#define ADC_REGULAR_DATA4 (4) +#define ADC_REGULAR_DATA5 (5) +#define ADC_REGULAR_DATA6 (6) +#define ADC_REGULAR_DATA7 (7) + +#define IS_ADC_REGULAR_DATA(DATA) ((DATA) < 8) + + +#define ADC_HP_DATA0 (0) +#define ADC_HP_DATA1 (1) +#define ADC_HP_DATA2 (2) +#define ADC_HP_DATA3 (3) + +#define IS_ADC_HP_DATA(DATA) ((DATA) < 4) + + +#define ADC_AWD_DISABLE (u8)0x00 +#define ADC_AWD_ALL_LOWER (u8)0x05 +#define ADC_AWD_ALL_UPPER (u8)0x06 +#define ADC_AWD_ALL_LOWER_UPPER (u8)0x07 +#define ADC_AWD_SINGLE_LOWER (u8)0x01 +#define ADC_AWD_SINGLE_UPPER (u8)0x02 +#define ADC_AWD_SINGLE_LOWER_UPPER (u8)0x03 + +#define IS_ADC_AWD(AWD) (((AWD) == ADC_AWD_DISABLE) || \ + ((AWD) == ADC_AWD_ALL_LOWER) || \ + ((AWD) == ADC_AWD_ALL_UPPER) || \ + ((AWD) == ADC_AWD_ALL_LOWER_UPPER) || \ + ((AWD) == ADC_AWD_SINGLE_LOWER) || \ + ((AWD) == ADC_AWD_SINGLE_UPPER) || \ + ((AWD) == ADC_AWD_SINGLE_LOWER_UPPER)) + +#define IS_ADC_THRESHOLD(THRESHOLD) ((THRESHOLD) < 4096) + +#define ADC_PDMA_REGULAR_SINGLE (0x00000001) +#define ADC_PDMA_REGULAR_SUBGROUP (0x00000002) +#define ADC_PDMA_REGULAR_CYCLE (0x00000004) + +#define ADC_PDMA_HP_SINGLE (0x00000100) +#define ADC_PDMA_HP_SUBGROUP (0x00000200) +#define ADC_PDMA_HP_CYCLE (0x00000400) + +#define IS_ADC_PDMA(PDMA) (((PDMA) == ADC_PDMA_REGULAR_SINGLE) || \ + ((PDMA) == ADC_PDMA_REGULAR_SUBGROUP) || \ + ((PDMA) == ADC_PDMA_REGULAR_CYCLE) || \ + ((PDMA) == ADC_PDMA_HP_SINGLE) || \ + ((PDMA) == ADC_PDMA_HP_SUBGROUP) || \ + ((PDMA) == ADC_PDMA_HP_CYCLE)) + + +#define IS_ADC_INPUT_SAMPLING_TIME(TIME) ((TIME) <= 255) + +#define IS_ADC_OFFSET(OFFSET) ((OFFSET) < 4096) + +#define IS_ADC_REGULAR_RANK(RANK) ((RANK) < 8) + +#define IS_ADC_HP_RANK(RANK) ((RANK) < 4) + +#define IS_ADC_REGULAR_LENGTH(LENGTH) (((LENGTH) >= 1) && ((LENGTH) <= 8)) +#define IS_ADC_REGULAR_SUB_LENGTH(SUB_LENGTH) (((SUB_LENGTH) >= 1) && ((SUB_LENGTH) <= 8)) + +#define IS_ADC_HP_LENGTH(LENGTH) (((LENGTH) >= 1) && ((LENGTH) <= 4)) +#define IS_ADC_HP_SUB_LENGTH(SUB_LENGTH) (((SUB_LENGTH) >= 1) && ((SUB_LENGTH) <= 4)) + +#define IS_ADC_TRIG_DELAY(DELAY) ((DELAY) < 256) + +typedef enum +{ + ADC_ALIGN_RIGHT = (0 << 14), + ADC_ALIGN_LEFT = (1 << 14), +} ADC_ALIGN_Enum; + +#define IS_ADC_ALIGN(ALIGN) (((ALIGN) == ADC_ALIGN_RIGHT) || ((ALIGN) == ADC_ALIGN_LEFT)) +/** + * @} + */ + +/* Exported functions --------------------------------------------------------------------------------------*/ +/** @defgroup ADC_Exported_Functions ADC exported functions + * @{ + */ +void ADC_DeInit(HT_ADC_TypeDef* HT_ADCn); +void ADC_Reset(HT_ADC_TypeDef* HT_ADCn); +void ADC_Cmd(HT_ADC_TypeDef* HT_ADCn, ControlStatus NewState); +#if (LIBCFG_ADC1) +void ADC_DualModeConfig(HT_ADC_TypeDef* HT_ADCn, u32 DUAL_X, u8 HDelayTime, u8 DelayTime); +#endif + +void ADC_RegularChannelConfig(HT_ADC_TypeDef* HT_ADCn, u8 ADC_CH_n, u8 Rank, u8 SampleClock); +void ADC_RegularGroupConfig(HT_ADC_TypeDef* HT_ADCn, u8 ADC_MODE, u8 Length, u8 SubLength); +void ADC_RegularTrigConfig(HT_ADC_TypeDef* HT_ADCn, u32 ADC_TRIG_x); + +void ADC_HPChannelConfig(HT_ADC_TypeDef* HT_ADCn, u8 ADC_CH_n, u8 Rank, u8 SampleClock); +void ADC_HPGroupConfig(HT_ADC_TypeDef* HT_ADCn, u8 ADC_MODE, u8 Length, u8 SubLength); +void ADC_HPTrigConfig(HT_ADC_TypeDef* HT_ADCn, u32 ADC_TRIG_x); + +void ADC_ChannelDataAlign(HT_ADC_TypeDef* HT_ADCn, u8 ADC_CH_n, ADC_ALIGN_Enum ADC_ALIGN_x); +void ADC_ChannelOffsetValue(HT_ADC_TypeDef* HT_ADCn, u8 ADC_CH_n, u16 OffsetValue); +void ADC_ChannelOffsetCmd(HT_ADC_TypeDef* HT_ADCn, u8 ADC_CH_n, ControlStatus NewState); + +#if (LIBCFG_ADC_TRIG_DELAY) +void ADC_TrigDelayConfig(HT_ADC_TypeDef* HT_ADCn, u8 HDelayTime, u8 DelayTime); +#endif + +void ADC_SoftwareStartConvCmd(HT_ADC_TypeDef* HT_ADCn, ControlStatus NewState); +void ADC_HPSoftwareStartConvCmd(HT_ADC_TypeDef* HT_ADCn, ControlStatus NewState); + +u16 ADC_GetConversionData(HT_ADC_TypeDef* HT_ADCn, u8 ADC_REGULAR_DATAn); +u16 ADC_GetHPConversionData(HT_ADC_TypeDef* HT_ADCn, u8 ADC_HP_DATAn); + +void ADC_IntConfig(HT_ADC_TypeDef* HT_ADCn, u32 ADC_INT_x, ControlStatus NewState); +FlagStatus ADC_GetIntStatus(HT_ADC_TypeDef* HT_ADCn, u32 ADC_INT_x); +void ADC_ClearIntPendingBit(HT_ADC_TypeDef* HT_ADCn, u32 ADC_INT_x); +FlagStatus ADC_GetFlagStatus(HT_ADC_TypeDef* HT_ADCn, u32 ADC_FLAG_x); + +void ADC_AWDConfig(HT_ADC_TypeDef* HT_ADCn, u32 ADC_AWD_x); +void ADC_AWDSingleChannelConfig(HT_ADC_TypeDef* HT_ADCn, u8 ADC_CH_n); +void ADC_AWDThresholdsConfig(HT_ADC_TypeDef* HT_ADCn, u16 UPPER, u16 LOWER); + +void ADC_PDMAConfig(HT_ADC_TypeDef* HT_ADCn, u32 ADC_PDMA_x, ControlStatus NewState); +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f65xxx_66xxx_opa.h b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f65xxx_66xxx_opa.h new file mode 100644 index 0000000000..f8cfc6cca8 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f65xxx_66xxx_opa.h @@ -0,0 +1,215 @@ +/*********************************************************************************************************//** + * @file ht32f65xxx_66xxx_opa.h + * @version $Rev:: 6911 $ + * @date $Date:: 2023-05-10 #$ + * @brief The header file of the OPA library. + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------------------------------------*/ +#ifndef __HT32F65XXX_66XXX_OPA_H +#define __HT32F65XXX_66XXX_OPA_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------------------------------------*/ +#include "ht32.h" + +/** @addtogroup HT32F5xxxx_Peripheral_Driver HT32F5xxxx Peripheral Driver + * @{ + */ + +/** @addtogroup OPA + * @{ + */ + + +/* Exported types ------------------------------------------------------------------------------------------*/ +#if (LIBCFG_OPA_V2) +/** @defgroup OPA_Exported_Types OPA exported types + * @{ + */ +/** + * @brief Definition of CMP init structure. + */ +typedef struct +{ + u32 OPA_ScalerEnable; + u32 OPA_ExternalPinEnable; + #if (LIBCFG_OPA_PGA) + u32 OPA_PGAEnable; + u32 OPA_UnitGainEnable; + u32 OPA_PGAGain; + #endif +} OPA_InitTypeDef; +/** + * @brief Enumeration of OPA PGA Gain. + */ +typedef enum +{ + /* OPnPGA = 1, OPnDACEN = 0 */ + PGA_GAIN_6 = 0x0, + PGA_GAIN_8 = 0x1, + PGA_GAIN_12 = 0x2, + PGA_GAIN_16 = 0x3, + PGA_GAIN_24 = 0x4, + PGA_GAIN_32 = 0x5, + PGA_GAIN_48 = 0x6, + PGA_GAIN_64 = 0x7, + + /* OPnPGA = 1, OPnDACEN = 1 */ + PGA_GAIN_5 = 0x0, + PGA_GAIN_7 = 0x1, + PGA_GAIN_11 = 0x2, + PGA_GAIN_15 = 0x3, + PGA_GAIN_23 = 0x4, + PGA_GAIN_31 = 0x5, + PGA_GAIN_47 = 0x6, + PGA_GAIN_63 = 0x7, +} OPA_PGA_Enum; +/** + * @} + */ +#endif + +/* Exported constants --------------------------------------------------------------------------------------*/ +/** @defgroup OPA_Exported_Constants OPA exported constants + * @{ + */ +#define OPA_UNPROTECT_KEY (0x9C3A) + +#if (LIBCFG_OPA1) +#define IS_OPA1(PERIPH) (PERIPH == HT_OPA1) +#else +#define IS_OPA1(PERIPH) (0) +#endif +#define IS_OPA(PERIPH) ((PERIPH == HT_OPA0) || IS_OPA1(PERIPH)) + +#if (LIBCFG_OPA_V2) +/* Definitions of OPA DAC Enable Bit */ +#define OPA_SCALER_ENABLE ((u32)0x00000100) +#define OPA_SCALER_DISABLE ((u32)0x00000000) + +/* Definitions of OPA External Pin Enable Bit */ +#define OPA_ExternalPin_ENABLE ((u32)0x00000008) +#define OPA_ExternalPin_DISABLE ((u32)0x00000000) + +/* Definitions of OPA PGA Enable Bit */ +#define OPA_PGA_ENABLE ((u32)0x00000004) +#define OPA_PGA_DISABLE ((u32)0x00000000) + +/* Definitions of OPA UnitGain Enable Bit */ +#define OPA_UNITGAIN_ENABLE ((u32)0x00000002) +#define OPA_UNITGAIN_DISABLE ((u32)0x00000000) + +/* Definitions of OPA Output Status */ +#define OPA_OUTPUT_HIGH ((u32)0x00000080) +#define OPA_OUTPUT_LOW ((u32)0x00000000) + +#define OPA_NORMAL_MODE (0) +#define OPA_OFFSET_CALIBRATION_MODE (1) + +#define OPA_INPUT_OFFSET_INN (0) +#define OPA_INPUT_OFFSET_INP (1) + +/** + * @brief Used to check parameter of the OPAx. + */ +#define IS_OPA_ScalerEnable(x) ((x == OPA_SCALER_ENABLE) || (x == OPA_SCALER_DISABLE)) + +#define IS_OPA_ExtPinEnable(x) ((x == OPA_ExternalPin_ENABLE) || (x == OPA_ExternalPin_DISABLE)) + +#define IS_OPA_PGAEnable(x) ((x == OPA_PGA_ENABLE) || (x == OPA_PGA_DISABLE)) + +#define IS_OPA_UnitGainEnable(x) ((x == OPA_UNITGAIN_ENABLE) || (x == OPA_UNITGAIN_DISABLE)) + +#define IS_OPA_PGA_SEL(SEL) ((SEL == PGA_GAIN_5) || (SEL == PGA_GAIN_6) || \ + (SEL == PGA_GAIN_7) || (SEL == PGA_GAIN_8) || \ + (SEL == PGA_GAIN_11) || (SEL == PGA_GAIN_12) || \ + (SEL == PGA_GAIN_15) || (SEL == PGA_GAIN_16) || \ + (SEL == PGA_GAIN_23) || (SEL == PGA_GAIN_24) || \ + (SEL == PGA_GAIN_31) || (SEL == PGA_GAIN_32) || \ + (SEL == PGA_GAIN_47) || (SEL == PGA_GAIN_48) || \ + (SEL == PGA_GAIN_63) || (SEL == PGA_GAIN_64)) + +#define IS_OPA_OFMMODE(MODE) ((MODE == OPA_OFFSET_CALIBRATION_MODE) || \ + (MODE == OPA_NORMAL_MODE)) + +#define IS_OPA_INPUTOFFSET_SEL(SEL) ((SEL == OPA_INPUT_OFFSET_INN) || \ + (SEL == OPA_INPUT_OFFSET_INP)) + +/* Check the OPA Scaler Value */ +#define IS_OPA_SCALER_VALUE(x) (x <= 0x3FF) + +/* Check the OPA Input Offset Value */ +#define IS_OPA_INPUTOFFSET_VALUE(x) (x <= 0x1F) +#endif +/** + * @} + */ + +/* Exported functions --------------------------------------------------------------------------------------*/ +/** @defgroup OPA_Exported_Functions OPA exported functions + * @{ + */ +void OPA_DeInit(void); +void OPA_Cmd(HT_OPA_TypeDef* HT_OPAn, ControlStatus NewState); +void OPA_SetUnProtectKey(u32 uUnProtectKey); +void OPA_ProtectConfig(HT_OPA_TypeDef* HT_OPAn); +void OPA_UnprotectConfig(HT_OPA_TypeDef* HT_OPAn); + +#if (LIBCFG_OPA_V2) +void OPA_Init(HT_OPA_TypeDef* HT_OPAn, OPA_InitTypeDef* OPA_InitStruct); +void OPA_StructInit(OPA_InitTypeDef* OPA_InitStruct); +void OPA_ExternalInputCmd(HT_OPA_TypeDef* HT_OPAn, ControlStatus NewState); +#if (LIBCFG_OPA_PGA) +void OPA_UnitGainCmd(HT_OPA_TypeDef* HT_OPAn, ControlStatus NewState); +void OPA_PGACmd(HT_OPA_TypeDef* HT_OPAn, ControlStatus NewState); +void OPA_PGAGain(HT_OPA_TypeDef* HT_OPAn, u8 bGAIN_SEL); +#endif +void OPA_ScalerCmd(HT_OPA_TypeDef* HT_OPAn, ControlStatus NewState); +void OPA_SetScalerValue(HT_OPA_TypeDef* HT_OPAn, u32 Scaler_Value); +FlagStatus OPA_GetOutputStatus(HT_OPA_TypeDef* HT_OPAn); +void OPA_OFMMode(HT_OPA_TypeDef* HT_OPAn, u8 bMODE); +void OPA_OFM_InputOffsetReferenceSelect(HT_OPA_TypeDef* HT_OPAn, u8 bSEL); +void OPA_SetInputOffsetVoltage(HT_OPA_TypeDef* HT_OPAn, u8 bData); +#endif +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f65xxx_66xxx_pga.h b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f65xxx_66xxx_pga.h new file mode 100644 index 0000000000..c72336c2fa --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f65xxx_66xxx_pga.h @@ -0,0 +1,62 @@ +/*********************************************************************************************************//** + * @file ht32f65xxx_66xxx_pga.h + * @version $Rev:: 6915 $ + * @date $Date:: 2023-05-10 #$ + * @brief The header file of the PGA library (temporary file, not finish/support yet). + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------------------------------------*/ +#ifndef __HT32F65XXX_66XXX_PGA_H +#define __HT32F65XXX_66XXX_PGA_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------------------------------------*/ +#include "ht32.h" + +/** @addtogroup HT32F5xxxx_Peripheral_Driver HT32F5xxxx Peripheral Driver + * @{ + */ + +/** @addtogroup PGA + * @{ + */ + + + + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f66242_libcfg.h b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f66242_libcfg.h new file mode 100644 index 0000000000..953106da19 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f66242_libcfg.h @@ -0,0 +1,52 @@ +/*********************************************************************************************************//** + * @file ht32f66242_libcfg.h + * @version $Rev:: 7184 $ + * @date $Date:: 2023-08-31 #$ + * @brief The library configuration file. + ************************************************************************************************************* +* @attention +* +* Firmware Disclaimer Information +* +* 1. The customer hereby acknowledges and agrees that the program technical documentation, including the +* code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the +* proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and +* other intellectual property laws. +* +* 2. The customer hereby acknowledges and agrees that the program technical documentation, including the +* code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties +* other than HOLTEK and the customer. +* +* 3. The program technical documentation, including the code, is provided "as is" and for customer reference +* only. After delivery by HOLTEK, the customer shall use the program technical documentation, including +* the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including +* the warranties of merchantability, satisfactory quality and fitness for a particular purpose. +* +*

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ +/* Define to prevent recursive inclusion -------------------------------------------------------------------*/ +#ifndef __HT32F66242_LIBCFG_H +#define __HT32F66242_LIBCFG_H + +/* Settings ------------------------------------------------------------------------------------------------*/ + +#if !defined(USE_MEM_HT32F66242) +#define USE_MEM_HT32F66242 +#endif + +#define LIBCFG_MAX_SPEED (80000000) + +#define LIBCFG_FLASH_PAGESIZE (1024) + +#ifdef USE_MEM_HT32F66242 + #define LIBCFG_FLASH_SIZE (LIBCFG_FLASH_PAGESIZE * 63) + #define LIBCFG_RAM_SIZE (1024 * 8) + #define LIBCFG_CHIPNAME (0x66242) +#endif + +#define LIBCFG_ADC_NO_OFFSET_REG (1) +#define LIBCFG_GPIOC (1) +#define LIBCFG_NO_PWRCU_TEST_REG (1) +#define LIBCFG_PDMA (1) + +#endif diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f66246_libcfg.h b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f66246_libcfg.h new file mode 100644 index 0000000000..90a37a1703 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f66246_libcfg.h @@ -0,0 +1,52 @@ +/*********************************************************************************************************//** + * @file ht32f66246_libcfg.h + * @version $Rev:: 7184 $ + * @date $Date:: 2023-08-31 #$ + * @brief The library configuration file. + ************************************************************************************************************* +* @attention +* +* Firmware Disclaimer Information +* +* 1. The customer hereby acknowledges and agrees that the program technical documentation, including the +* code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the +* proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and +* other intellectual property laws. +* +* 2. The customer hereby acknowledges and agrees that the program technical documentation, including the +* code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties +* other than HOLTEK and the customer. +* +* 3. The program technical documentation, including the code, is provided "as is" and for customer reference +* only. After delivery by HOLTEK, the customer shall use the program technical documentation, including +* the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including +* the warranties of merchantability, satisfactory quality and fitness for a particular purpose. +* +*

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ +/* Define to prevent recursive inclusion -------------------------------------------------------------------*/ +#ifndef __HT32F66246_LIBCFG_H +#define __HT32F66246_LIBCFG_H + +/* Settings ------------------------------------------------------------------------------------------------*/ + +#if !defined(USE_MEM_HT32F66246) +#define USE_MEM_HT32F66246 +#endif + +#define LIBCFG_MAX_SPEED (80000000) + +#define LIBCFG_FLASH_PAGESIZE (1024) + +#ifdef USE_MEM_HT32F66246 + #define LIBCFG_FLASH_SIZE (LIBCFG_FLASH_PAGESIZE * 63) + #define LIBCFG_RAM_SIZE (1024 * 8) + #define LIBCFG_CHIPNAME (0x66246) +#endif + +#define LIBCFG_ADC_NO_OFFSET_REG (1) +#define LIBCFG_GPIOC (1) +#define LIBCFG_NO_PWRCU_TEST_REG (1) +#define LIBCFG_PDMA (1) + +#endif diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f66xxx_cordic.h b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f66xxx_cordic.h new file mode 100644 index 0000000000..1c25b4c036 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f66xxx_cordic.h @@ -0,0 +1,62 @@ +/*********************************************************************************************************//** + * @file ht32f66xxx_cordic.h + * @version $Rev:: 6915 $ + * @date $Date:: 2023-05-10 #$ + * @brief The header file of the CORDIC library (temporary file, not finish/support yet). + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------------------------------------*/ +#ifndef __HT32F66XXX_CORDIC_H +#define __HT32F66XXX_CORDIC_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------------------------------------*/ +#include "ht32.h" + +/** @addtogroup HT32F5xxxx_Peripheral_Driver HT32F5xxxx Peripheral Driver + * @{ + */ + +/** @addtogroup CORDIC + * @{ + */ + + + + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f66xxx_pid.h b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f66xxx_pid.h new file mode 100644 index 0000000000..c47671643c --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f66xxx_pid.h @@ -0,0 +1,62 @@ +/*********************************************************************************************************//** + * @file ht32f66xxx_pid.h + * @version $Rev:: 6915 $ + * @date $Date:: 2023-05-10 #$ + * @brief The header file of the PID library (temporary file, not finish/support yet). + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------------------------------------*/ +#ifndef __HT32F66XXX_PID_H +#define __HT32F66XXX_PID_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------------------------------------*/ +#include "ht32.h" + +/** @addtogroup HT32F5xxxx_Peripheral_Driver HT32F5xxxx Peripheral Driver + * @{ + */ + +/** @addtogroup PID + * @{ + */ + + + + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f67041_51_libcfg.h b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f67041_51_libcfg.h new file mode 100644 index 0000000000..b72fe2659b --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f67041_51_libcfg.h @@ -0,0 +1,78 @@ +/*********************************************************************************************************//** + * @file ht32f67041_51_libcfg.h + * @version $Rev:: 6923 $ + * @date $Date:: 2023-05-10 #$ + * @brief The library configuration file. + ************************************************************************************************************* +* @attention +* +* Firmware Disclaimer Information +* +* 1. The customer hereby acknowledges and agrees that the program technical documentation, including the +* code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the +* proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and +* other intellectual property laws. +* +* 2. The customer hereby acknowledges and agrees that the program technical documentation, including the +* code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties +* other than HOLTEK and the customer. +* +* 3. The program technical documentation, including the code, is provided "as is" and for customer reference +* only. After delivery by HOLTEK, the customer shall use the program technical documentation, including +* the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including +* the warranties of merchantability, satisfactory quality and fitness for a particular purpose. +* +*

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ +/* Define to prevent recursive inclusion -------------------------------------------------------------------*/ +#ifndef __HT32F67041_51_LIBCFG_H +#define __HT32F67041_51_LIBCFG_H + +/* Settings ------------------------------------------------------------------------------------------------*/ + +#if !defined(USE_MEM_HT32F67041) && !defined(USE_MEM_HT32F67051) +#define USE_MEM_HT32F67051 +#endif + +#define LIBCFG_MAX_SPEED (60000000) + +#define LIBCFG_FLASH_PAGESIZE (1024) + +#ifdef USE_MEM_HT32F67041 + #define LIBCFG_FLASH_SIZE (LIBCFG_FLASH_PAGESIZE * 64) + #define LIBCFG_RAM_SIZE (1024 * 8) + #define LIBCFG_CHIPNAME (0x67041) +#endif + +#ifdef USE_MEM_HT32F67051 + #define LIBCFG_FLASH_SIZE (LIBCFG_FLASH_PAGESIZE * 127) + #define LIBCFG_RAM_SIZE (1024 * 8) + #define LIBCFG_CHIPNAME (0x67051) +#endif + +#define LIBCFG_ADC_CH8_11 (1) +#define LIBCFG_ADC_IVREF (1) +#define LIBCFG_ADC_MVDDA (1) +#define LIBCFG_AES (1) +#define LIBCFG_BFTM1 (1) +#define LIBCFG_CKCU_ATM_V01 (1) +#define LIBCFG_CKCU_PLLSRCDIV (1) +#define LIBCFG_CKCU_REFCLK_EXT_PIN (1) +#define LIBCFG_CKCU_SYS_CK_60M (1) +#define LIBCFG_CRC (1) +#define LIBCFG_DIV (1) +#define LIBCFG_FMC_PREFETCH (1) +#define LIBCFG_FMC_WAIT_STATE_2 (1) +#define LIBCFG_I2C1 (1) +#define LIBCFG_LSE (1) +#define LIBCFG_PDMA (1) +#define LIBCFG_SCTM0 (1) +#define LIBCFG_SCTM1 (1) +#define LIBCFG_SCTM2 (1) +#define LIBCFG_SCTM3 (1) +#define LIBCFG_NO_USART0 (1) +#define LIBCFG_SPI1 (1) +#define LIBCFG_UART1 (1) +#define LIBCFG_PWRCU_VDD_2V0_3V6 (1) + +#endif diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/ht32_cm0plus_misc.c b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/ht32_cm0plus_misc.c new file mode 100644 index 0000000000..91fc97ab99 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/ht32_cm0plus_misc.c @@ -0,0 +1,243 @@ +/*********************************************************************************************************//** + * @file ht32_cm0plus_misc.c + * @version $Rev:: 5377 $ + * @date $Date:: 2021-05-26 #$ + * @brief This file provides all the miscellaneous firmware functions. + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ + +/* Includes ------------------------------------------------------------------------------------------------*/ +#include "ht32_cm0plus_misc.h" +#include "ht32_div.c" +#include "ht32_rand.c" +#ifdef HTCFG_TIME_IPSEL +#include "ht32_time.c" +#endif + +/** @addtogroup HT32_Peripheral_Driver HT32 Peripheral Driver + * @{ + */ + +/** @defgroup MISC MISC + * @brief MISC driver modules + * @{ + */ + + +/* Private definitions -------------------------------------------------------------------------------------*/ +/** @defgroup MISC_Private_Define MISC private definitions + * @{ + */ +#define AIRCR_VECTKEY_MASK ((u32)0x05FA0000) +#define CTRL_TICKINT_SET ((u32)0x00000002) +#define CTRL_TICKINT_RESET ((u32)0xFFFFFFFD) +/** + * @} + */ + +/* Global functions ----------------------------------------------------------------------------------------*/ +/** @defgroup MISC_Exported_Functions MISC exported functions + * @{ + */ +/*********************************************************************************************************//** + * @brief Set the vector table location and Offset. + * @param NVIC_VectTable: Specify if the vector table is in FLASH or RAM. + * This parameter can be one of the following values: + * @arg NVIC_VECTTABLE_RAM + * @arg NVIC_VECTTABLE_FLASH + * @param NVIC_Offset: Vector Table base offset field. + * This value must be a multiple of 0x100. + * @retval None + ***********************************************************************************************************/ +void NVIC_SetVectorTable(u32 NVIC_VectTable, u32 NVIC_Offset) +{ + /* Check the parameters */ + Assert_Param(IS_NVIC_VECTTABLE(NVIC_VectTable)); + Assert_Param(IS_NVIC_OFFSET(NVIC_Offset)); + + SCB->VTOR = NVIC_VectTable | (NVIC_Offset & (u32)0x1FFFFF80); +} + +/*********************************************************************************************************//** + * @brief Select which low power mode to execute to the system. + * @param NVIC_LowPowerMode: Specify the new low power mode to execute to the system. + * This parameter can be one of the following values: + * @arg NVIC_LOWPOWER_SEVONPEND + * @arg NVIC_LOWPOWER_SLEEPDEEP + * @arg NVIC_LOWPOWER_SLEEPONEXIT + * @param NewState: new state of low power condition. + * This parameter can be: ENABLE or DISABLE. + * @retval None + ***********************************************************************************************************/ +void NVIC_LowPowerConfig(u8 NVIC_LowPowerMode, ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_NVIC_LOWPOWER(NVIC_LowPowerMode)); + Assert_Param(IS_CONTROL_STATUS(NewState)); + + if (NewState != DISABLE) + { + SCB->SCR |= NVIC_LowPowerMode; + } + else + { + SCB->SCR &= (u32)(~(u32)NVIC_LowPowerMode); + } +} + +/*********************************************************************************************************//** + * @brief Set the pending bit for a system handler. + * @param SystemHandler: Specify the system handler pending bit to be set. + * This parameter can be one of the following values: + * @arg SYSTEMHANDLER_NMI + * @arg SYSTEMHANDLER_PSV + * @arg SYSTEMHANDLER_SYSTICK + * @retval None + ***********************************************************************************************************/ +void NVIC_SetPendingSystemHandler(u32 SystemHandler) +{ + /* Check the parameters */ + Assert_Param(IS_NVIC_SYSTEMHANDLER(SystemHandler)); + + /* Set the corresponding System Handler pending bit */ + SCB->ICSR |= SystemHandler; +} + +/*********************************************************************************************************//** + * @brief Configure the SysTick clock source. + * @param SysTick_ClockSource: Specify the SysTick clock source. + * This parameter can be one of the following values: + * @arg SYSTICK_SRC_STCLK : External reference clock is selected as SysTick clock source. + * @arg SYSTICK_SRC_FCLK : AHB clock is selected as SysTick clock source. + * @retval None + ***********************************************************************************************************/ +void SYSTICK_ClockSourceConfig(u32 SysTick_ClockSource) +{ + /* Check the parameters */ + Assert_Param(IS_SYSTICK_CLOCK_SOURCE(SysTick_ClockSource)); + + if (SysTick_ClockSource == SYSTICK_SRC_FCLK) + { + SysTick->CTRL |= SYSTICK_SRC_FCLK; + } + else + { + SysTick->CTRL &= SYSTICK_SRC_STCLK; + } +} + +/*********************************************************************************************************//** + * @brief Enable or Disable the SysTick counter. + * @param SysTick_Counter: new state of the SysTick counter. + * This parameter can be one of the following values: + * @arg SYSTICK_COUNTER_DISABLE : Disable counter + * @arg SYSTICK_COUNTER_ENABLE : Enable counter + * @arg SYSTICK_COUNTER_CLEAR : Clear counter value to 0 + * @retval None + ***********************************************************************************************************/ +void SYSTICK_CounterCmd(u32 SysTick_Counter) +{ + /* Check the parameters */ + Assert_Param(IS_SYSTICK_COUNTER(SysTick_Counter)); + + if (SysTick_Counter == SYSTICK_COUNTER_CLEAR) + { + SysTick->VAL = SYSTICK_COUNTER_CLEAR; + } + else + { + if (SysTick_Counter == SYSTICK_COUNTER_ENABLE) + { + SysTick->CTRL |= SYSTICK_COUNTER_ENABLE; + } + else + { + SysTick->CTRL &= SYSTICK_COUNTER_DISABLE; + } + } +} + +/*********************************************************************************************************//** + * @brief Enable or Disable the SysTick Interrupt. + * @param NewState: new state of the SysTick Interrupt. + * This parameter can be: ENABLE or DISABLE. + * @retval None + ***********************************************************************************************************/ +void SYSTICK_IntConfig(ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_CONTROL_STATUS(NewState)); + + if (NewState != DISABLE) + { + SysTick->CTRL |= CTRL_TICKINT_SET; + } + else + { + SysTick->CTRL &= CTRL_TICKINT_RESET; + } +} + +/*********************************************************************************************************//** + * @brief Set SysTick counter reload value. + * @param SysTick_Reload: SysTick reload new value. + * This parameter must be a number between 1 and 0xFFFFFF. + * @retval None + ***********************************************************************************************************/ +void SYSTICK_SetReloadValue(u32 SysTick_Reload) +{ + /* Check the parameters */ + Assert_Param(IS_SYSTICK_RELOAD(SysTick_Reload)); + + SysTick->LOAD = SysTick_Reload; +} + +/*********************************************************************************************************//** + * @brief Reverse bits. + * @param in: Input data + * @retval uRBIT + ***********************************************************************************************************/ +u32 RBIT(u32 in) +{ + u32 uRBIT = 0; + s32 i; + + for(i = 31; i >=0; i--) + { + uRBIT |= ((in & 0x1) << i); + in = in >> 1; + } + + return uRBIT; +} +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/ht32_div.c b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/ht32_div.c new file mode 100644 index 0000000000..37403e1d5e --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/ht32_div.c @@ -0,0 +1,55 @@ +/*********************************************************************************************************//** + * @file ht32_div.c + * @version $Rev:: 220 $ + * @date $Date:: 2016-02-16 #$ + * @brief The division assembly. + ************************************************************************************************************* +* @attention +* +* Firmware Disclaimer Information +* +* 1. The customer hereby acknowledges and agrees that the program technical documentation, including the +* code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the +* proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and +* other intellectual property laws. +* +* 2. The customer hereby acknowledges and agrees that the program technical documentation, including the +* code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties +* other than HOLTEK and the customer. +* +* 3. The program technical documentation, including the code, is provided "as is" and for customer reference +* only. After delivery by HOLTEK, the customer shall use the program technical documentation, including +* the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including +* the warranties of merchantability, satisfactory quality and fitness for a particular purpose. +* +*

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ + +#include "ht32.h" + +/* Global variables ----------------------------------------------------------------------------------------*/ +//__ALIGN4 static uc32 Data[] = +__ALIGN4 static u32 Data[] = +{ +0x09032200, 0xD32C428B, 0x428B0A03, 0x2300D311, 0xE04E469C, 0x430B4603, 0x2200D43C, 0x428B0843, +0x0903D331, 0xD31C428B, 0x428B0A03, 0x4694D301, 0x09C3E03F, 0xD301428B, 0x1AC001CB, 0x09834152, +0xD301428B, 0x1AC0018B, 0x09434152, 0xD301428B, 0x1AC0014B, 0x09034152, 0xD301428B, 0x1AC0010B, +0x08C34152, 0xD301428B, 0x1AC000CB, 0x08834152, 0xD301428B, 0x1AC0008B, 0x08434152, 0xD301428B, +0x1AC0004B, 0x1A414152, 0x4601D200, 0x46104152, 0xE05D4770, 0xD0000FCA, 0x10034249, 0x4240D300, +0x22004053, 0x0903469C, 0xD32D428B, 0x428B0A03, 0x22FCD312, 0xBA120189, 0x428B0A03, 0x0189D30C, +0x428B1192, 0x0189D308, 0x428B1192, 0x0189D304, 0x1192D03A, 0x0989E000, 0x428B09C3, 0x01CBD301, +0x41521AC0, 0x428B0983, 0x018BD301, 0x41521AC0, 0x428B0943, 0x014BD301, 0x41521AC0, 0x428B0903, +0x010BD301, 0x41521AC0, 0x428B08C3, 0x00CBD301, 0x41521AC0, 0x428B0883, 0x008BD301, 0x41521AC0, +0x0843D2D9, 0xD301428B, 0x1AC0004B, 0x1A414152, 0x4601D200, 0x41524663, 0x4610105B, 0x4240D301, +0xD5002B00, 0x47704249, 0x105B4663, 0x4240D300, 0x2000B501, 0x46C046C0, 0x0000BD02 +}; + +u32 (*UDIV32)(u32, u32); +s32 (*SDIV32)(s32, s32); + +void DIV32_Init(void) +{ + u32 fptr = (u32)Data; + UDIV32 = (u32 (*)(u32, u32))(fptr + 0x1); + SDIV32 = (s32 (*)(s32, s32))(fptr + 0x15); +} diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/ht32_rand.c b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/ht32_rand.c new file mode 100644 index 0000000000..435766bb0e --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/ht32_rand.c @@ -0,0 +1,81 @@ +/*********************************************************************************************************//** + * @file ht32_rand.c + * @version $Rev:: 2069 $ + * @date $Date:: 2017-11-07 #$ + * @brief The rundom number function. + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ + +/* Includes ------------------------------------------------------------------------------------------------*/ +#include "ht32.h" +#include + +/* Global variables ----------------------------------------------------------------------------------------*/ +__ALIGN4 static uc32 RandData[] = +{ + 0x4946b5ff, 0x6a4cb087, 0x6b0c9404, 0x6a4c9403, + 0x042d2503, 0x624c432c, 0x4d416b0c, 0x630c432c, + 0x68394f40, 0x2580463c, 0x402926f9, 0x1b890236, + 0x021e6039, 0x04114316, 0x0619430e, 0x607e430e, + 0x43160216, 0x4316041a, 0x60a6430e, 0x62212117, + 0x22014934, 0x630a3140, 0x432b6823, 0x4e326023, + 0x93056873, 0x685c4b31, 0x4c319406, 0x605c6074, + 0x69dd69f4, 0x43136b4b, 0x4a2a634b, 0x68533280, + 0xd5fc075b, 0x463a6b3b, 0x0f1b071b, 0x6b7b9302, + 0x071b6bbf, 0x073f0f1b, 0x97010f3f, 0x07176bd2, + 0x680a0f3f, 0x071746bc, 0x97000f3f, 0x0717684a, + 0x688a0f3f, 0x071246be, 0x0f1268c9, 0x68074e1a, + 0x042d69f6, 0x193419be, 0x4d181964, 0x69ed6004, + 0x011b9e02, 0x431e9f01, 0x023b042d, 0x46671964, + 0x432b033d, 0x431e9f00, 0x431e043b, 0x053b4677, + 0x0612431e, 0x07094316, 0x9a08430e, 0x18891931, + 0x48096001, 0x60419905, 0x99064808, 0x48036041, + 0x62419904, 0x63019903, 0xbdf0b00b, 0x40088000, + 0x01000040, 0x40010000, 0x400b0000, 0x400b2000, + 0x0000ffff +}; + +__ALIGN4 static uc32 RandData2[] = +{ + 0x4604b510, 0x18406800, 0x46216020, 0x68084a03, + 0x4a034350, 0x60081880, 0xbd100840, 0x41c64e6d, + 0x00003039 +}; + +typedef void (*Randinit_TypeDef) (u32 *, u32, u32, u32); +u32 (*Rand_Get)(u32 *, u32); + +/* Global functions ----------------------------------------------------------------------------------------*/ +/*********************************************************************************************************//** + * @brief Rand init. + * @param uSeed + * @param uCount + * @param a + * @param b + * @retval none + ***********************************************************************************************************/ +void Rand_Init(u32 *uSeed, u32 uCount, u32 a, u32 b) +{ + Randinit_TypeDef Randinit = (Randinit_TypeDef)((u32)RandData | 0x1); + Rand_Get = (u32 (*)(u32 *, u32))((u32)RandData2 | 0x1); + Randinit(uSeed, uCount, a, b); +} diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/ht32_retarget.c b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/ht32_retarget.c new file mode 100644 index 0000000000..5ffe762c9d --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/ht32_retarget.c @@ -0,0 +1,413 @@ +/*********************************************************************************************************//** + * @file ht32_retarget.c + * @version $Rev:: 6977 $ + * @date $Date:: 2023-06-07 #$ + * @brief Retarget layer for target-dependent low level functions. + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ + +/* Includes ------------------------------------------------------------------------------------------------*/ +#include "ht32.h" +#include "ht32_board.h" + +#if defined (__CC_ARM) + #pragma import(__use_no_semihosting_swi) +#endif + +#if defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #ifndef __MICROLIB + __asm(".global __use_no_semihosting"); + #endif +#endif + +#if (_RETARGET == 1) +#include + +#if defined (__CC_ARM) + #include +#endif + +/** @addtogroup HT32_Peripheral_Driver HT32 Peripheral Driver + * @{ + */ + +/** @defgroup RETARGET Retarget + * @brief Retarget related functions + * @{ + */ + + +/* Private constants ---------------------------------------------------------------------------------------*/ +/** @defgroup RETARGET_Private_Define Retarget private definitions + * @{ + */ + +#if (RETARGET_PORT == RETARGET_ITM) +#define ITM_PORT8(n) (*((vu8 *)(0xE0000000 + 4 * n))) +#define ITM_PORT16(n) (*((vu16 *)(0xE0000000 + 4 * n))) +#define ITM_PORT32(n) (*((vu32 *)(0xE0000000 + 4 * n))) + +#define DEMCR (*((vu32 *)(0xE000EDFC))) +#define TRCENA (0x01000000) +volatile int32_t ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* For Keil MDK-ARM only */ +#endif +/** + * @} + */ + +/* Global variables ----------------------------------------------------------------------------------------*/ +/** @defgroup RETARGET_Global_Variable Retarget global variables + * @{ + */ +#if defined (__CC_ARM) +struct __FILE { int handle; /* Add whatever you need here */ }; +FILE __stdout; +FILE __stdin; +#endif + +#if defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #ifndef __MICROLIB + FILE __stdout; + FILE __stdin; + FILE __stderr; + #endif +#endif + +#if defined (__SES_ARM) && defined(__SEGGER_RTL_VERSION) +struct __SEGGER_RTL_FILE_impl { // NOTE: Provides implementation for FILE + int stub; // only needed so impl has size != 0. +}; +static FILE __SEGGER_RTL_stdin_file = { 0 }; // stdin reads from UART +static FILE __SEGGER_RTL_stdout_file = { 0 }; // stdout writes to UART +static FILE __SEGGER_RTL_stderr_file = { 0 }; // stderr writes to UART + +FILE *stdin = &__SEGGER_RTL_stdin_file; // NOTE: Provide implementation of stdin for RTL. +FILE *stdout = &__SEGGER_RTL_stdout_file; // NOTE: Provide implementation of stdout for RTL. +FILE *stderr = &__SEGGER_RTL_stderr_file; // NOTE: Provide implementation of stderr for RTL. + +static int _stdin_ungot = EOF; +#endif +/** + * @} + */ + +/* Global functions ----------------------------------------------------------------------------------------*/ +/** @defgroup RETARGET_Exported_Functions Retarget exported functions + * @{ + */ + +void RETARGET_Configuration(void) +{ +#ifdef RETARGET_IS_UART + /* !!! NOTICE !!! + Notice that the local variable (structure) did not have an initial value. + Please confirm that there are no missing members in the parameter settings below in this function. + */ + USART_InitTypeDef USART_InitStructure; + #ifdef RETARGET_UxART_BAUDRATE + USART_InitStructure.USART_BaudRate = RETARGET_UxART_BAUDRATE; + #else + USART_InitStructure.USART_BaudRate = 115200; + #endif + USART_InitStructure.USART_WordLength = USART_WORDLENGTH_8B; + USART_InitStructure.USART_StopBits = USART_STOPBITS_1; + USART_InitStructure.USART_Parity = USART_PARITY_NO; + USART_InitStructure.USART_Mode = USART_MODE_NORMAL; + + #ifdef RETARGET_COM_PORT + HT32F_DVB_COMInit(RETARGET_COM_PORT, &USART_InitStructure); + #else + { /* Enable peripheral clock of UxART */ + CKCU_PeripClockConfig_TypeDef CKCUClock = {{0}}; + CKCUClock.Bit.RETARGET_UxART_IPN = 1; + CKCU_PeripClockConfig(CKCUClock, ENABLE); + } + + USART_Init(RETARGET_USART_PORT, &USART_InitStructure); + USART_TxCmd(RETARGET_USART_PORT, ENABLE); + USART_RxCmd(RETARGET_USART_PORT, ENABLE); + #if (RETARGET_INT_MODE == 1) + NVIC_EnableIRQ(RETARGET_UART_IRQn); + #endif + #endif +#endif + +#if (RETARGET_PORT == RETARGET_ITM) + CKCU_PeripClockConfig_TypeDef CKCUClock = {{ 0 }}; + CKCUClock.Bit.AFIO = 1; + CKCU_PeripClockConfig(CKCUClock, ENABLE); + + CKCU_MCUDBGConfig(CKCU_DBG_TRACE_ON, ENABLE); + AFIO_GPxConfig(TRACESWO_GPIO_ID, TRACESWO_AFIO_PIN, TRACESWO_AFIO_MODE); +#endif + +#ifdef NON_USB_IN_APP + SERIAL_USBDInit(); +#endif +} + +int __backspace(FILE *stream) +{ + if (stream == 0) // Remove the compiler warning + { + } + return 0; +} + +/* + Keil and IAR before 9.20 share fputc() to implement printf +*/ +int fputc (int ch, FILE *f) +{ + #if 0 + if (f == 0) // Remove the compiler warning + { + } + #endif + #if (RETARGET_PORT == RETARGET_ITM) + if (DEMCR & TRCENA) + { + while (ITM_PORT32(0) == 0); + ITM_PORT8(0) = ch; + } + return (ch); + #else + #ifdef AUTO_RETURN + if (ch == '\n') + { + SERIAL_PutChar('\r'); + } + #endif + return (SERIAL_PutChar(ch)); + #endif +} + +#if defined (__ICCARM__) +#if (__VER__ > 9010000) +/* + IAR's version after 9.20 use write to implement printf +*/ +int __write(int Handle, + const unsigned char * Buf, + int Bufsize) +{ + size_t nChars = 0; + if (Handle == -1) + { + return 0; + } + /* Check for stdout and stderr + (only necessary if FILE descriptors are enabled.) */ + if (Handle != 1 && Handle != 2) + { + return -1; + } + for (/*Empty */; Bufsize > 0; --Bufsize) + { + SERIAL_PutChar(*Buf++); + ++nChars; + } + return nChars; +} +#endif +int __read(int Handle, unsigned char *Buf, size_t BufSize) +{ + #if (RETARGET_PORT != RETARGET_ITM) + int nChars = 0; + + if (Handle != 0) + { + return -1; + } + + for (/* Empty */; BufSize > 0; --BufSize) + { + unsigned char c = NULL; + c = SERIAL_GetChar(); + if (c == 0) + break; + *Buf++ = c; + ++nChars; + } + #endif + return nChars; +} + +#elif defined(__SES_ARM) +#if defined(__SEGGER_RTL_VERSION) +/* + SES's version after 6.20 use RTL to implement printf. +*/ +/*********************************************************************************************************//** + * @brief Get character from standard input.. + * @retval Character received. + ************************************************************************************************************/ +static char _stdin_getc(void) { + unsigned char c; + + if (_stdin_ungot != EOF) { + c = _stdin_ungot; + _stdin_ungot = EOF; + } else { + c = SERIAL_GetChar(); + } + return c; +} + +/*********************************************************************************************************//** + * @brief Get file status. + * @param Pointer to file. + * @retval -1: Failure, stream is not a valid file. 0: Success, stream is a valid file. + ***********************************************************************************************************/ +int __SEGGER_RTL_X_file_stat(FILE *stream) { + if (stream == stdin || stream == stdout || stream == stderr) { + return 0; // NOTE: stdin, stdout, and stderr are assumed to be valid. + } else { + return EOF; + } +} + +/*********************************************************************************************************//** + * @brief Get stream buffer size. + * @param stream: Pointer to file. + * @retval Nonzero number of characters to use for buffered I/O; for unbuffered I/O, return 1. + ***********************************************************************************************************/ +int __SEGGER_RTL_X_file_bufsize(FILE *stream) { + (void)stream; + return 1; +} + +/*********************************************************************************************************//** + * @brief Read data from file. + * @param stream: Pointer to file to read from. + * @param s: Pointer to object that receives the input. + * @param len: Number of characters to read from file. + * @retval -1: Failure, stream is not a valid file. >0: Success, stream is a valid file. + ***********************************************************************************************************/ +int __SEGGER_RTL_X_file_read(FILE *stream, char *s, unsigned len) { + int c; + + if (stream == stdin) { + c = 0; + while (len > 0) { + *s = _stdin_getc(); + ++s; + ++c; + --len; + } + } else { + c = EOF; + } + return c; +} + +/*********************************************************************************************************//** + * @brief Write data to file. + * @param stream: Pointer to file to write to. + * @param s:Pointer to object to write to file. + * @param len:Number of characters to write to the file. + * @retval -1: Failure, stream is not a valid file. >0: Success, stream is a valid file. + ***********************************************************************************************************/ +int __SEGGER_RTL_X_file_write(FILE *stream, const char *s, unsigned len) { + if ((stream == stdout) || (stream == stderr)) { + //BSP_UART_WriteBlocking(_UART_Port, (const unsigned char*) s, len); + for (/*Empty */; len > 0; --len) + { + SERIAL_PutChar(*s++); + } + return len; + } else { + return EOF; + } +} + +/*********************************************************************************************************//** + * @brief ush character back to stream. + * @param stream: Pointer to file to push back to. + * @param c: Character to push back. + * @retval -1: Failure, stream is not a valid file. >0: Success, stream is a valid file. + ***********************************************************************************************************/ +int __SEGGER_RTL_X_file_unget(FILE *stream, int c) { + if (stream == stdin) { + if (c != EOF && _stdin_ungot == EOF) { + _stdin_ungot = c; + } else { + c = EOF; + } + } else { + c = EOF; + } + return c; +} +#endif +#else +int fgetc (FILE *f) +{ + #if 0 + if (f == 0) // Remove the compiler warning + { + } + #endif + #if (RETARGET_PORT == RETARGET_ITM) + /* For Keil MDK-ARM only */ + while (ITM_CheckChar() == 0); + return (ITM_ReceiveChar()); + #else + return (SERIAL_GetChar()); + #endif +} +#endif + +void _ttywrch(int ch) +{ + #if (RETARGET_PORT == RETARGET_ITM) + if (DEMCR & TRCENA) + { + while (ITM_PORT32(0) == 0); + ITM_PORT8(0) = ch; + } + #else + SERIAL_PutChar(ch); + #endif +} +#endif + +void _sys_exit(int return_code) +{ + if (return_code == 0) // Remove the compiler warning + { + } + +label: goto label; /* endless loop */ +} +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/ht32_retarget_desc.c b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/ht32_retarget_desc.c new file mode 100644 index 0000000000..b8fec7bee6 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/ht32_retarget_desc.c @@ -0,0 +1,272 @@ +/*********************************************************************************************************//** + * @file ht32_retarget_desc.c + * @version $Rev:: 783 $ + * @date $Date:: 2016-06-10 #$ + * @brief The The USB Descriptor of retarget. + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ +// <<< Use Configuration Wizard in Context Menu >>> + +/* Includes ------------------------------------------------------------------------------------------------*/ + +#define DESC_LEN_CONFN_T (u16)(DESC_LEN_CONFN) + +/*----------------------------------------------------------------------------------------------------------*/ +/* USB Device descriptor setting */ +/*----------------------------------------------------------------------------------------------------------*/ +// USB Device descriptor setting +// USB Specification Release number (bcdUSB) +// <0x0200=> USB 2.0 +// <0x0110=> USB 1.1 +// <0x0100=> USB 1.0 +// USB Class code (assigned by the USB-IF) +// <0x00=> Use class information in the Interface Descriptors (0x00) +// <0x02=> Communications and CDC Control (CDC, 0x02) +// <0xDC=> Diagnostic Device (0xDC) +// <0xEF=> Miscellaneous (0xEF) +// <0xFF=> Vendor Specific (0xFF) +// USB Subclass code (assigned by the USB-IF) <0x0-0xFF:1> +// USB Protocol code (assigned by the USB-IF) <0x0-0xFF:1> +// USB Vendor ID <0x0-0xFFFF:1> +// USB Product ID <0x0-0xFFFF:1> +// USB Device Version <0x0-0xFFFF:1> +// USB String descriptor - Manufacturer +// USB String descriptor - Product +// USB String descriptor - Device serial number +// USB Number of possible configurations <0-255:1> +#define DESC_BCDUSB (0x0110) +#define DESC_BDEVCLASS (0x00) +#define DESC_BDEVSUBCLASS (0x00) +#define DESC_BDEVPROTOCOL (0x00) +#define DESC_IDVENDOR (0x04D9) +#define DESC_IDPRODUCT (0x8008) +#define DESC_BCDDEVICE (0x0100) +#define DESC_IMANUFACTURE (1) +#define DESC_IPRODUCT (1) +#define DESC_ISERIALNUM (1) +#define DESC_INUMCONFN (1) +// + +/*----------------------------------------------------------------------------------------------------------*/ +/* USB Device Descriptor definition. DO NOT MODIFY. */ +/*----------------------------------------------------------------------------------------------------------*/ +#if (DESC_BDEVCLASS == 0x0 & DESC_BDEVSUBCLASS != 0x0) +#error "DESC_BDEVSUBCLASS must be reset to zero when the DESC_BDEVCLASS is equal to zero." +#endif +#define DESC_WMAXPACKETSIZE0 (_EP0LEN) +#define DESC_STR_MAN (1 * DESC_IMANUFACTURE) +#define DESC_STR_PRD (2 * DESC_IPRODUCT) +#define DESC_STR_SER (3 * DESC_ISERIALNUM) +#define DESC_NUM_STRING (1 + 3) + +/*----------------------------------------------------------------------------------------------------------*/ +/* USB Device descriptor */ +/*----------------------------------------------------------------------------------------------------------*/ +__ALIGN4 static uc8 guUSB_DeviceDesc[] = +{ + /*--------------------------------------------------------------------------------------------------------*/ + /* Device descriptor */ + /*--------------------------------------------------------------------------------------------------------*/ + /* Field Size Description */ + /*----------------------------------------------------------------------------*/ + DESC_LEN_DEV, // bLength 1 Size of this descriptor in bytes + DESC_TYPE_01_DEV, // bDescriptorType 1 DEVICE Descriptor Type + DESC_H2B(DESC_BCDUSB), // bcdUSB 2 USB Specification Release Number + DESC_BDEVCLASS, // bDeviceClass 1 Class code (assigned by the USB-IF) + DESC_BDEVSUBCLASS, // bDeviceSubClass 1 Subclass code (assigned by the USB-IF) + DESC_BDEVPROTOCOL, // bDeviceProtocol 1 Protocol code (assigned by the USB-IF) + DESC_WMAXPACKETSIZE0, // wMaxPacketSize0 1 Maximum packet size for endpoint zero + DESC_H2B(DESC_IDVENDOR), // idVendor 2 Vendor ID (assigned by USB-IF) + DESC_H2B(DESC_IDPRODUCT), // idProduct 2 Product ID (assigned by manufacturer) + DESC_H2B(DESC_BCDDEVICE), // bcdDevice 2 Device release number + DESC_STR_MAN, // iManufacturer 1 Index of string descriptor (Manufacturer) + DESC_STR_PRD, // iProduct 1 Index of string descriptor (Product) + DESC_STR_SER, // iSerialNumber 1 Index of string descriptor (Serial Number) + DESC_INUMCONFN, // iNumConfigurations 1 Number of possible configuration +}; + + +/*----------------------------------------------------------------------------------------------------------*/ +/* USB Configuration descriptor setting */ +/*----------------------------------------------------------------------------------------------------------*/ +// USB Configuration descriptor setting +// Self-powered +// Bit 6 of bmAttributes +// Remote Wakeup +// Bit 5 of bmAttributes +// USB Device maximum power (mA) < 2-512:2> +#define DESC_BMATTR_SELF_POWER (0) +#define DESC_BMATTR_REMOTE_WAKEUP (0) +#define DESC_BMAXPOWER (100) +// + +/*----------------------------------------------------------------------------------------------------------*/ +/* USB Configuration Descriptor definition. DO NOT MODIFY. */ +/*----------------------------------------------------------------------------------------------------------*/ +#define DESC_BMATTRIBUTES (0x80 | (DESC_BMATTR_SELF_POWER << 6) | (DESC_BMATTR_REMOTE_WAKEUP << 5)) +#define DESC_TOTAL_LEN DESC_H2B((DESC_LEN_CONFN_T + RETARGET_DLEN)) + +/*----------------------------------------------------------------------------------------------------------*/ +/* USB Configuration Descriptor */ +/*----------------------------------------------------------------------------------------------------------*/ +__ALIGN4 static uc8 guUSB_ConfnDesc[] = +{ + /*--------------------------------------------------------------------------------------------------------*/ + /* Configuration descriptor */ + /*--------------------------------------------------------------------------------------------------------*/ + /* Field Size Description */ + /*----------------------------------------------------------------------------*/ + DESC_LEN_CONFN, // bLength 1 Size of this descriptor in bytes + DESC_TYPE_02_CONFN, // bDescriptorType 1 CONFIGURATION Descriptor Type + DESC_TOTAL_LEN, // wTotalLength 2 Total length of data returned for this configuration + RETARGET_INF, // bNumberInterface 1 Number of interfaces supported by this configuration + 0x01, // bConfigurationValue 1 Value to use as an argument to the SetConfiguration() + 0x00, // iConfiguration 1 Index of string descriptor describing this configuration + DESC_BMATTRIBUTES, // bmAttributes 1 Configuration characteristics + // D6: Self-powered, D5: RemoteWakeup + DESC_POWER(DESC_BMAXPOWER), // bMaxPower 1 Maximum power consumption of the USB device (2 mA units) + + #ifdef RETARGET_IS_USB + #include "ht32_retarget_desc.h" + #endif + +}; + +/*----------------------------------------------------------------------------------------------------------*/ +/* USB String Descriptor */ +/*----------------------------------------------------------------------------------------------------------*/ +__ALIGN4 static uc8 guUSB_StringDescLANGID[] = +{ + /*--------------------------------------------------------------------------------------------------------*/ + /* LANGID (Index = 0) */ + /*--------------------------------------------------------------------------------------------------------*/ + /* Field Size Description */ + /*----------------------------------------------------------------------------*/ + DESC_STRLEN(1), // bLength 1 Size of this descriptor in bytes + DESC_TYPE_03_STR, // bDescriptorType 1 STRING Descriptor Type + DESC_H2B(0x0409), // wLANGID[0] 2 LANGID code zero +}; + +#if (DESC_IMANUFACTURE == 1) +__ALIGN4 static uc8 guUSB_StringDescManufacture[] = +{ + /*--------------------------------------------------------------------------------------------------------*/ + /* Manufacture (Index = 1) */ + /*--------------------------------------------------------------------------------------------------------*/ + /* Field Size Description */ + /*----------------------------------------------------------------------------*/ + DESC_STRLEN(6), // bLength 1 Size of this descriptor in bytes + DESC_TYPE_03_STR, // bDescriptorType 1 STRING Descriptor Type + DESC_CHAR('H'), // bString N UNICODE encoded string + DESC_CHAR('O'), + DESC_CHAR('L'), + DESC_CHAR('T'), + DESC_CHAR('E'), + DESC_CHAR('K'), +}; +#endif + +#if (DESC_IPRODUCT == 1) +__ALIGN4 static uc8 guUSB_StringDescProduct[] = +{ + /*--------------------------------------------------------------------------------------------------------*/ + /* Product (Index = 2) */ + /*--------------------------------------------------------------------------------------------------------*/ + /* Field Size Description */ + /*----------------------------------------------------------------------------*/ + DESC_STRLEN(7), // bLength 1 Size of this descriptor in bytes + DESC_TYPE_03_STR, // bDescriptorType 1 STRING Descriptor Type + DESC_CHAR('U'), // bString N UNICODE encoded string + DESC_CHAR('S'), + DESC_CHAR('B'), + DESC_CHAR('-'), + DESC_CHAR('V'), + DESC_CHAR('C'), + DESC_CHAR('P'), +}; +#endif + + +#if (DESC_ISERIALNUM == 1) +__ALIGN4 static uc8 guUSB_StringDescSerialNum[] = +{ + /*--------------------------------------------------------------------------------------------------------*/ + /* Serial Number (Index = 3) */ + /*--------------------------------------------------------------------------------------------------------*/ + /* Field Size Description */ + /*----------------------------------------------------------------------------*/ + DESC_STRLEN(12), // bLength 1 Size of this descriptor in bytes + DESC_TYPE_03_STR, // bDescriptorType 1 STRING Descriptor Type + DESC_CHAR('S'), // bString N UNICODE encoded string + DESC_CHAR('N'), + DESC_CHAR('0'), + DESC_CHAR('0'), + DESC_CHAR('0'), + DESC_CHAR('0'), + DESC_CHAR('0'), + DESC_CHAR('0'), + DESC_CHAR('1'), + DESC_CHAR('0'), + DESC_CHAR('0'), + DESC_CHAR('0'), +}; +#endif + +uc8 *gpStringDesc[DESC_NUM_STRING] = +{ + + guUSB_StringDescLANGID, + + #if (DESC_IMANUFACTURE == 1) + guUSB_StringDescManufacture, + #else + NULL, + #endif + + #if (DESC_IPRODUCT == 1) + guUSB_StringDescProduct, + #else + NULL, + #endif + + #if (DESC_ISERIALNUM == 1) + guUSB_StringDescSerialNum + #else + NULL, + #endif + +}; + +/*********************************************************************************************************//** + * @brief USB Descriptor pointer initialization. + * @param pDesc: pointer of USBDCore_Desc_TypeDef + * @retval None + ***********************************************************************************************************/ +void USBDDesc_Init(USBDCore_Desc_TypeDef *pDesc) +{ + pDesc->pDeviceDesc = guUSB_DeviceDesc; + pDesc->pConfnDesc = guUSB_ConfnDesc; + pDesc->ppStringDesc = gpStringDesc; + pDesc->uStringDescNumber = DESC_NUM_STRING; + + return; +} diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/ht32_serial.c b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/ht32_serial.c new file mode 100644 index 0000000000..a1f642f393 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/ht32_serial.c @@ -0,0 +1,555 @@ +/*********************************************************************************************************//** + * @file ht32_serial.c + * @version $Rev:: 6490 $ + * @date $Date:: 2022-11-25 #$ + * @brief This file provides all the Low level serial routines for HT32. + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ + +/* Includes ------------------------------------------------------------------------------------------------*/ +#include "ht32.h" +#include "ht32_board.h" + +#if (_RETARGET == 1) + +/** @addtogroup HT32_Peripheral_Driver HT32 Peripheral Driver + * @{ + */ + +/** @defgroup SERIAL SERIAL + * @brief Serial related functions + * @{ + */ + + +/* Global functions ----------------------------------------------------------------------------------------*/ +/** @defgroup SERIAL_Exported_Functions Serial exported functions + * @{ + */ + +#ifdef RETARGET_IS_UART + +#if (RETARGET_INT_MODE == 1) +__ALIGN4 static u8 uSerialBuffer[RETARGET_INT_BUFFER_SIZE]; +static vu32 uReadIndex; +static vu32 uWriteIndex; + +#define IS_BUFFER_FULL(LEN) (((uWriteIndex + LEN) >= RETARGET_INT_BUFFER_SIZE) ? ((uWriteIndex + LEN - RETARGET_INT_BUFFER_SIZE) == uReadIndex) : ((uWriteIndex + LEN) == uReadIndex)) +#define IS_BUFFER_EMPTY() (uReadIndex == uWriteIndex) +#define BUFFER_FREE_LEN() ((uWriteIndex >= uReadIndex) ? (RETARGET_INT_BUFFER_SIZE - uWriteIndex + uReadIndex - 1) : (uReadIndex - uWriteIndex - 1)) + +/*********************************************************************************************************//** + * @brief UART IRQ handler. + * @retval None + ************************************************************************************************************/ +void RETARGET_UART_IRQHandler(void) +{ + if (((RETARGET_USART_PORT->SR) & USART_FLAG_TXDE)) + { + if (IS_BUFFER_EMPTY()) + { + RETARGET_USART_PORT->IER &= ~USART_INT_TXDE; + } + else + { + RETARGET_USART_PORT->DR = uSerialBuffer[uReadIndex++]; + if (uReadIndex == RETARGET_INT_BUFFER_SIZE) + { + uReadIndex = 0; + } + } + } + +} +#endif + +/*********************************************************************************************************//** + * @brief Put char to USART. + * @param ch: The char put to USART. + * @retval The char put to USART. + ************************************************************************************************************/ +u32 SERIAL_PutChar(u32 ch) +{ +#if (RETARGET_INT_MODE == 1) + + while (IS_BUFFER_FULL(1)); + + uSerialBuffer[uWriteIndex++] = ch; + if (uWriteIndex == RETARGET_INT_BUFFER_SIZE) + { + uWriteIndex = 0; + } + RETARGET_USART_PORT->IER |= USART_INT_TXDE; + +#else + + RETARGET_USART_PORT->DR = (u8)ch; + while ((RETARGET_USART_PORT->SR & USART_FLAG_TXC) == RESET) + { + } + +#endif + + return ch; +} + +/*********************************************************************************************************//** + * @brief Get char from USART. + * @retval The char got from USART. + ************************************************************************************************************/ +u32 SERIAL_GetChar(void) +{ + while (USART_GetFlagStatus(RETARGET_USART_PORT, USART_FLAG_RXDR) == RESET) + { + } + return USART_ReceiveData(RETARGET_USART_PORT); +} + +#endif + + +#ifdef RETARGET_IS_USB +/* Private types -------------------------------------------------------------------------------------------*/ +/** @defgroup SERIAL_Private_TypesDefinitions Serial private types definitions + * @{ + */ +typedef struct _VCP_LINE_CODING +{ + u32 dwDTERate; //Bit rate; + u8 bCharFormat; //Stop bits: + //0 = 1 Stop bit + //1 = 1.5 Stop bit + //2 = 2 Stop bit + u8 bParityType; //parity: + //0 = None + //1 = Odd + //2 = Even + //3 = Mark + //4 = Space + u8 bDataBits; //Number of data bits (7, 8, 9) +} USBDClass_VCP_LINE_CODING; +/** + * @} + */ + +/* Private constants ---------------------------------------------------------------------------------------*/ +/** @defgroup SERIAL_Private_Define Serial private definitions + * @{ + */ +#define CLASS_REQ_20_SET_LINE_CODING (0x20) +#define CLASS_REQ_21_GET_LINE_CODING (0x21) +#define CLASS_REQ_22_SET_CONTROL_LINE_STATE (0x22) + +#ifndef RETARGET_TXBUFFER_SIZE + #define RETARGET_TXBUFFER_SIZE (1) +#endif + +#define RETARGET_USB_MODE_BLOCK (0) +#define RETARGET_USB_MODE_NONBLOCK (1) +/** + * @} + */ + +/* Private macro -------------------------------------------------------------------------------------------*/ +/** @defgroup SERIAL_Private_Macro Serial private macros + * @{ + */ +#define IS_BUFFER_FULL(LEN) (((uWriteIndex + LEN) >= RETARGET_BUFFER_SIZE) ? ((uWriteIndex + LEN - RETARGET_BUFFER_SIZE) == uReadIndex) : ((uWriteIndex + LEN) == uReadIndex)) +#define IS_BUFFER_EMPTY() (uReadIndex == uWriteIndex) +#define BUFFER_FREE_LEN() ((uWriteIndex >= uReadIndex) ? (RETARGET_BUFFER_SIZE - uWriteIndex + uReadIndex - 1) : (uReadIndex - uWriteIndex - 1)) +/** + * @} + */ + +/* Private variables ---------------------------------------------------------------------------------------*/ +/** @defgroup SERIAL_Private_Variable Serial private variables + * @{ + */ +static USBDClass_VCP_LINE_CODING USBDClassVCPLineCoding; +__ALIGN4 static u8 uSerialBuffer[RETARGET_BUFFER_SIZE]; +static vu32 uReadIndex; +static vu32 uWriteIndex; +static vu32 uDTRState = 0; +static vu32 gIsINEmpty = TRUE; + +static u32 TxCount = 0; +__ALIGN4 static u8 TxBuffer[RETARGET_TXBUFFER_SIZE]; +/** + * @} + */ + +#if (RETARGET_RX_EPT == RETARGET_TX_EPT) + #error USB Endpoint of retarget Rx and Tx must different. Please check RETARGET_RX_EPT/RETARGET_TX_EPT "ht32_retarget_usbdconf.h". +#endif + +#if (RETARGET_CTRL_EPT == RETARGET_TX_EPT) + #error USB Endpoint of retarget Control and Tx must different. Please check RETARGET_CTRL_EPT/RETARGET_TX_EPT "ht32_retarget_usbdconf.h". +#endif + +#if (RETARGET_CTRL_EPT == RETARGET_RX_EPT) + #error USB Endpoint of retarget Control and Rx must different. Please check RETARGET_CTRL_EPT/RETARGET_RX_EPT "ht32_retarget_usbdconf.h". +#endif + +#ifdef _RERATGET1_ERR + #error Endpoint 1 already used by other USB class. Retarget can not overwrite it. +#endif + +#ifdef _RERATGET2_ERR + #error Endpoint 2 already used by other USB class. Retarget can not overwrite it. +#endif + +#ifdef _RERATGET3_ERR + #error Endpoint 3 already used by other USB class. Retarget can not overwrite it. +#endif + +#ifdef _RERATGET4_ERR + #error Endpoint 4 already used by other USB class. Retarget can not overwrite it. +#endif + +#ifdef _RERATGET5_ERR + #error Endpoint 5 already used by other USB class. Retarget can not overwrite it. +#endif + +#ifdef _RERATGET6_ERR + #error Endpoint 6 already used by other USB class. Retarget can not overwrite it. +#endif + +#ifdef _RERATGET7_ERR + #error Endpoint 7 already used by other USB class. Retarget can not overwrite it. +#endif + +/*********************************************************************************************************//** + * @brief Put char to USB. + * @param ch: The char put to USB. + * @retval The char put to USB. + ************************************************************************************************************/ +u32 SERIAL_PutChar(u32 ch) +{ + #if (RETARGET_TXBUFFER_SIZE > 63) + #error RETARGET_TXBUFFER_SIZE shall less than 63 (define in ht32fxxxxx_conf.h). + #endif + + #if (RETARGET_USB_MODE == RETARGET_USB_MODE_BLOCK) + while (uDTRState == 0); /* Wait until user open the virtual COM port by PC UI such as Hyper Terminal */ + #elif (RETARGET_USB_MODE == RETARGET_USB_MODE_NONBLOCK) + if (uDTRState == 0) /* Drop data if USB or terminal software is not ready */ + { + return ch; + } + #endif + + TxBuffer[TxCount++] = ch; + + if (TxCount == RETARGET_TXBUFFER_SIZE) + { + TxCount = 0; + + while (gIsINEmpty == FALSE) + { + #if (RETARGET_USB_MODE == RETARGET_USB_MODE_NONBLOCK) + if (uDTRState == 0) + { + return ch; + } + #endif + } + + gIsINEmpty = FALSE; + USBDCore_EPTWriteINData((USBD_EPTn_Enum)RETARGET_TX_EPT, (u32 *)&TxBuffer, RETARGET_TXBUFFER_SIZE); + } + + return ch; +} + +/*********************************************************************************************************//** + * @brief Get char from USB. + * @retval The char got from USB. + ************************************************************************************************************/ +u32 SERIAL_GetChar(void) +{ + u32 value = 0; + + while (IS_BUFFER_EMPTY()); + value = uSerialBuffer[uReadIndex++]; + if (uReadIndex == RETARGET_BUFFER_SIZE) + { + uReadIndex = 0; + } + + return value; +} + +/*********************************************************************************************************//** + * @brief Flush the Tx Buffer + * @retval None + ************************************************************************************************************/ +void SERIAL_Flush(void) +{ + do + { + #if (RETARGET_USB_MODE == RETARGET_USB_MODE_NONBLOCK) + if (uDTRState == 0) + { + return; + } + #endif + } while (USBDCore_EPTGetTransferCount((USBD_EPTn_Enum)RETARGET_TX_EPT, USBD_TCR_0)); + + gIsINEmpty = FALSE; + USBDCore_EPTWriteINData((USBD_EPTn_Enum)RETARGET_TX_EPT, (u32 *)&TxBuffer, TxCount); + TxCount = 0; +} + +#ifdef NON_USB_IN_APP +#include "ht32_retarget_desc.c" +__ALIGN4 USBDCore_TypeDef gUSBCore; +USBD_Driver_TypeDef gUSBDriver; + +/*********************************************************************************************************//** + * @brief This function handles USB interrupt. + * @retval None + ************************************************************************************************************/ +void USB_IRQHandler(void) +{ + USBDCore_IRQHandler(&gUSBCore); +} + +/*********************************************************************************************************//** + * @brief USB Class initialization. + * @param pClass: pointer of USBDCore_Class_TypeDef + * @retval None + ************************************************************************************************************/ +void USBDClass_Init(USBDCore_Class_TypeDef *pClass) +{ + pClass->CallBack_ClassRequest = SERIAL_USBDClass_Request; + pClass->CallBack_EPTn[RETARGET_RX_EPT] = SERIAL_USBDClass_RXHandler; + pClass->CallBack_EPTn[RETARGET_TX_EPT] = SERIAL_USBDClass_TXHandler; + return; +} + +#if (LIBCFG_CKCU_USB_PLL) +/*********************************************************************************************************//** + * @brief Configure USB PLL + * @retval None + ************************************************************************************************************/ +void USBPLL_Configuration(void) +{ + if ((HT_CKCU->GCCR & (1 << 11)) == 0) + { + CKCU_HSICmd(ENABLE); + } + + { /* USB PLL configuration */ + + /* !!! NOTICE !!! + Notice that the local variable (structure) did not have an initial value. + Please confirm that there are no missing members in the parameter settings below in this function. + */ + CKCU_PLLInitTypeDef PLLInit; + + PLLInit.ClockSource = CKCU_PLLSRC_HSI; + #if (LIBCFG_CKCU_USB_PLL_96M) + PLLInit.CFG = CKCU_USBPLL_8M_96M; + #else + PLLInit.CFG = CKCU_USBPLL_8M_48M; + #endif + PLLInit.BYPASSCmd = DISABLE; + CKCU_USBPLLInit(&PLLInit); + } + + CKCU_USBPLLCmd(ENABLE); + + while (CKCU_GetClockReadyStatus(CKCU_FLAG_USBPLLRDY) == RESET); + CKCU_USBClockConfig(CKCU_CKUSBPLL); +} +#endif + +#if (LIBCFG_PWRCU_VREG) +/*********************************************************************************************************//** + * @brief Configure USB Voltage + * @retval None + ************************************************************************************************************/ +void USBVRG_Configuration(void) +{ + CKCU_PeripClockConfig_TypeDef CKCUClock = {{ 0 }}; + CKCUClock.Bit.BKP = 1; + CKCU_PeripClockConfig(CKCUClock, ENABLE); + + /* !!! NOTICE !!! + USB LDO should be enabled (PWRCU_VREG_ENABLE) if the MCU VDD > 3.6 V. + */ + PWRCU_VREGConfig(PWRCU_VREG_BYPASS); +} +#endif + +/*********************************************************************************************************//** + * @brief Configure USB for retarget. + * @retval None + ************************************************************************************************************/ +void SERIAL_USBDInit(void) +{ + CKCU_PeripClockConfig_TypeDef CKCUClock = {{0}}; + CKCUClock.Bit.USBD = 1; + CKCU_PeripClockConfig(CKCUClock, ENABLE); + + #if (LIBCFG_CKCU_USB_PLL) + USBPLL_Configuration(); + #endif + + #if (LIBCFG_PWRCU_VREG) + USBVRG_Configuration(); /* Voltage of USB setting */ + #endif + + /* !!! NOTICE !!! + Must turn on if the USB clock source is from HSI (PLL clock Source) + */ + #if (RETARGET_HSI_ATM) + CKCU_HSIAutoTrimClkConfig(CKCU_ATC_USB); + CKCU_HSIAutoTrimCmd(ENABLE); + #endif + + gUSBCore.pDriver = (u32 *)&gUSBDriver; /* Initiate memory pointer of USB driver */ + USBDDesc_Init(&gUSBCore.Device.Desc); /* Initiate memory pointer of descriptor */ + USBDClass_Init(&gUSBCore.Class); /* Initiate USB Class layer */ + USBDCore_Init(&gUSBCore); /* Initiate USB Core layer */ + NVIC_EnableIRQ(USB_IRQn); /* Enable USB device interrupt */ + USBD_DPpullupCmd(ENABLE); + + #if (RETARGET_USB_MODE == RETARGET_USB_MODE_BLOCK) + USBDCore_MainRoutine(&gUSBCore); /* USB core main routine */ + while (USBDCore_GetStatus() != USB_STATE_CONFIGURED); + #else + gUSBCore.Info.CurrentFeature.Bits.bSelfPowered = TRUE; + USBDCore_MainRoutine(&gUSBCore); /* USB core main routine */ + #endif +} +#endif + +/*********************************************************************************************************//** + * @brief USB Device Class Request for USB retarget + * @param pDev: pointer of USB Device + * @retval None + ************************************************************************************************************/ +void SERIAL_USBDClass_Request(USBDCore_Device_TypeDef *pDev) +{ + u8 USBCmd = *((u8 *)(&(pDev->Request.bRequest))); + u16 len = *((u16 *)(&(pDev->Request.wLength))); + u32 inf = pDev->Request.wIndex; + u32 uIsCmdOK = 0; + + if (inf != 11) + { + return; + } + + if (USBCmd == CLASS_REQ_22_SET_CONTROL_LINE_STATE) + { + if (len == 0) + { + uDTRState = pDev->Request.wValueL & 0x1; + pDev->Transfer.pData = 0; + pDev->Transfer.sByteLength = 0; + pDev->Transfer.Action = USB_ACTION_DATAOUT; + } + } + else + { + if (USBCmd == CLASS_REQ_20_SET_LINE_CODING) + { + pDev->Transfer.Action = USB_ACTION_DATAOUT; + uIsCmdOK = 1; + } + else if (USBCmd == CLASS_REQ_21_GET_LINE_CODING) + { + pDev->Transfer.Action = USB_ACTION_DATAIN; + uIsCmdOK = 1; + } + + if (uIsCmdOK == 1) + { + pDev->Transfer.pData = (uc8*)&USBDClassVCPLineCoding; + pDev->Transfer.sByteLength = (sizeof(USBDClassVCPLineCoding) > pDev->Request.wLength) ? (pDev->Request.wLength) : (sizeof(USBDClassVCPLineCoding)); + } + } + + return; +} + +/*********************************************************************************************************//** + * @brief USB Class Received handler + * @param EPTn: USB Endpoint number + * @arg USBD_EPT0 ~ USBD_EPT7 + * @retval None +************************************************************************************************************/ +void SERIAL_USBDClass_RXHandler(USBD_EPTn_Enum EPTn) +{ + u32 uLen; + u32 uFreeLen = BUFFER_FREE_LEN(); + u8 uTempBuffer[64]; + u32 i; + + /* Read Receive data */ + uLen = USBDCore_EPTReadOUTData(EPTn, (u32*)uTempBuffer, 64); + + if (uLen > uFreeLen) + { + uLen = uFreeLen; + } + + for (i = 0; i < uLen; i++) + { + uSerialBuffer[uWriteIndex++] = uTempBuffer[i]; + if (uWriteIndex == RETARGET_BUFFER_SIZE) + { + uWriteIndex = 0; + } + } + + return; +} + +/*********************************************************************************************************//** + * @brief USB Class Tx handler + * @param EPTn: USB Endpoint number + * @arg USBD_EPT0 ~ USBD_EPT7 + * @retval None +************************************************************************************************************/ +void SERIAL_USBDClass_TXHandler(USBD_EPTn_Enum EPTn) +{ + gIsINEmpty = TRUE; + return; +} + +#endif +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ +#endif diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/ht32_time.c b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/ht32_time.c new file mode 100644 index 0000000000..a84bbb61ac --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/ht32_time.c @@ -0,0 +1,185 @@ +/*********************************************************************************************************//** + * @file ht32_time.c + * @version $Rev:: 6461 $ + * @date $Date:: 2022-11-18 #$ + * @brief The time functions. + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ + +/* Includes ------------------------------------------------------------------------------------------------*/ +#include "ht32.h" +#include "ht32_time.h" + +/* + Tick Range: 0 ~ 2^32 / HTCFG_TIME_TICKHZ (maximum tick time) + Interrupt Time: _HTCFG_TIME_OVERFLOW_VALUE / (HTCFG_TIME_TICKHZ * HTCFG_TIME_MULTIPLE) Second (not apply for BFTM) + + Example: 32-bit BFTM with 48 MHz Timer Clock + HTCFG_TIME_TICKHZ = HTCFG_TIME_CLKSRC = 48000000 + Tick Range: 0 ~ 2^32 / 48000000 = 0 ~ 89.478485 Second (maximum tick time, return to 0 every 89.478485 Second) + BFTM do not use interrupt + + Example: 16-bit SCTM with 1 us tick + HTCFG_TIME_TICKHZ = 1000000 (Hz) + HTCFG_TIME_MULTIPLE = 1 (1 Timer Count = 1 Tick) + Tick Range: 0 ~ 2^32 / 1000000 = 0 ~ 4294 Second = 0 ~ 71.58 Minute (maximum tick time, return to 0 every 71.58 Minute) + Interrupt Time: 65536 / (1000000 * 1) = 65.536 ms (Trigger interrupt every 65.536 ms) + + Example: 16-bit SCTM with 10 us tick + HTCFG_TIME_TICKHZ = 100000 (Hz) + HTCFG_TIME_MULTIPLE = 4 (4 Timer Count = 1 Tick) + Tick Range: 0 ~ 2^32 / 100000 = 0 ~ 42949 Second = 0 ~ 715.82 Minute = 11.93 Hour (maximum tick time, return to 0 every 11.93 Hour) + Interrupt Time: 65536 / (100000 * 4) = 163.84 ms (Trigger interrupt every 163.84 ms) + + Example: 16-bit GPTM with 1 ms tick + HTCFG_TIME_TICKHZ = 1000 (Hz) + HTCFG_TIME_MULTIPLE = 4 (4 Timer Count = 1 Tick) + Tick Range: 0 ~ 2^32 / 1000 = 0 ~ 4294967 Second = 0 ~ 49.7 Day (maximum tick time, return to 0 every 49.7 Day) + Interrupt Time: 65536 / (1000 * 4) = 16.384 Second (Trigger interrupt every 16.384 Second) +*/ + +/* Private constants ---------------------------------------------------------------------------------------*/ +#define _HTCFG_TIME_CKCU_PCLK STRCAT2(CKCU_PCLK_, HTCFG_TIME_IPN) + +#if (IS_IPN_TM(HTCFG_TIME_IPN)) +// SCTM/PWM/GPTM/MCTM +#define _HTCFG_TIME_IRQn STRCAT2(HTCFG_TIME_IPN, _IRQn) +#define _HTCFG_TIME_IRQHandler STRCAT2(HTCFG_TIME_IPN, _IRQHandler) +#define _HTCFG_TIME_CLKDIV (HTCFG_TIME_CLKSRC / HTCFG_TIME_TICKHZ / HTCFG_TIME_MULTIPLE) +#define _HTCFG_TIME_OVERFLOW_VALUE (65536) // 16-bit = 2^16 + +#if (_HTCFG_TIME_CLKDIV <= 0) + #error "_HTCFG_TIME_CLKDIV is not correct (must >= 1)!" +#endif + +#if (_HTCFG_TIME_CLKDIV > 65536) + #error "_HTCFG_TIME_CLKDIV is not correct (must <= 65536)!" +#endif + +#if ((_HTCFG_TIME_CLKDIV * HTCFG_TIME_MULTIPLE) != (HTCFG_TIME_CLKSRC / HTCFG_TIME_TICKHZ)) + #error "_HTCFG_TIME_CLKDIV is not correct (must be integer)!" +#endif +#endif + +/* Private variables ---------------------------------------------------------------------------------------*/ +#if (IS_IPN_TM(HTCFG_TIME_IPN)) +u32 gTotalTick = 0x00000000; +u8 gIsTimeInt = FALSE; +#endif + +/* Global functions ----------------------------------------------------------------------------------------*/ +/*********************************************************************************************************//** + * @brief Time Init function. + * @retval None + ***********************************************************************************************************/ +void Time_Init(void) +{ + { /* Enable peripheral clock */ + CKCU_PeripClockConfig_TypeDef CKCUClock = {{ 0 }}; + CKCUClock.Bit.HTCFG_TIME_IPN = 1; + CKCU_PeripClockConfig(CKCUClock, ENABLE); + } + + #if (LIBCFG_CKCU_NO_APB_PRESCALER == 0) + CKCU_SetPeripPrescaler(_HTCFG_TIME_CKCU_PCLK, (CKCU_APBCLKPRE_TypeDef)HTCFG_TIME_PCLK_DIV); + #endif + + #if (IS_IPN_TM(HTCFG_TIME_IPN)) + + { /* Time base configuration */ + /* !!! NOTICE !!! + Notice that the local variable (structure) did not have an initial value. + Please confirm that there are no missing members in the parameter settings below in this function. + */ + TM_TimeBaseInitTypeDef TimeBaseInit; + + TimeBaseInit.Prescaler = _HTCFG_TIME_CLKDIV - 1; + TimeBaseInit.CounterReload = _HTCFG_TIME_OVERFLOW_VALUE -1; + TimeBaseInit.RepetitionCounter = 0; + TimeBaseInit.CounterMode = TM_CNT_MODE_UP; + TimeBaseInit.PSCReloadTime = TM_PSC_RLD_IMMEDIATE; + TM_TimeBaseInit(_HTCFG_TIME_PORT, &TimeBaseInit); + + /* Clear Update Event Interrupt flag since the "TM_TimeBaseInit()" writes the UEV1G bit */ + TM_ClearFlag(_HTCFG_TIME_PORT, TM_FLAG_UEV); + } + + /* Enable Update Event interrupt */ + TM_IntConfig(_HTCFG_TIME_PORT, TM_INT_UEV, ENABLE); + NVIC_EnableIRQ(_HTCFG_TIME_IRQn); + + TM_SetCounter(_HTCFG_TIME_PORT, 0x0000); + TM_Cmd(_HTCFG_TIME_PORT, ENABLE); + + #else + + BFTM_SetCounter(_HTCFG_TIME_PORT, 0x00000000); + BFTM_EnaCmd(_HTCFG_TIME_PORT, ENABLE); + #endif +} + +/*********************************************************************************************************//** + * @brief Time delay function. + * @param uDelayTick: Delay count based on tick. + * @retval None + ***********************************************************************************************************/ +void Time_Delay(u32 uDelayTick) +{ + u32 uCurrent; + u32 uStart = Time_GetTick(); + + do + { + uCurrent = Time_GetTick(); + } while (TIME_TICKDIFF(uStart, uCurrent) < uDelayTick); +} + +#if (IS_IPN_TM(HTCFG_TIME_IPN)) +/*********************************************************************************************************//** + * @brief Gets the current time tick. + * @retval Time Tick + ***********************************************************************************************************/ +u32 Time_GetTick(void) +{ + u32 uCount = GET_CNT(); + + if (gIsTimeInt == TRUE) + { + gIsTimeInt = FALSE; + uCount = GET_CNT(); + gTotalTick += (_HTCFG_TIME_OVERFLOW_VALUE / HTCFG_TIME_MULTIPLE); + } + + return (gTotalTick + (uCount / HTCFG_TIME_MULTIPLE)); +} + +/*********************************************************************************************************//** + * @brief This function handles Timer interrupt. + * @retval None + ************************************************************************************************************/ +void _HTCFG_TIME_IRQHandler(void) +{ + TM_ClearFlag(_HTCFG_TIME_PORT, TM_INT_UEV); + + gIsTimeInt = TRUE; +} +#endif diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/ht32f5xxxx_adc.c b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/ht32f5xxxx_adc.c new file mode 100644 index 0000000000..d244507c11 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/ht32f5xxxx_adc.c @@ -0,0 +1,603 @@ +/*********************************************************************************************************//** + * @file ht32f5xxxx_adc.c + * @version $Rev:: 7366 $ + * @date $Date:: 2023-12-06 #$ + * @brief This file provides all the ADC firmware functions. + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ + +/* Includes ------------------------------------------------------------------------------------------------*/ +#include "ht32f5xxxx_adc.h" + +/** @addtogroup HT32F5xxxx_Peripheral_Driver HT32F5xxxx Peripheral Driver + * @{ + */ + +/** @defgroup ADC ADC + * @brief ADC driver modules + * @{ + */ + + +/* Private constants ---------------------------------------------------------------------------------------*/ +/** @defgroup ADC_Private_Define ADC private definitions + * @{ + */ +#define ADC_ENABLE_BIT (0x00000080) +#define ADC_SOFTWARE_RESET (0x00000040) +#define LST_SEQ_SET (0x0000001F) +#define TCR_SC_SET (0x00000001) + +#define HLST_SEQ_SET (0x0000001F) +#define HTCR_SC_SET (0x00000001) + +#define ADC_VREF_MVDDAEN (0x00000100) +/** + * @} + */ + +/* Global functions ----------------------------------------------------------------------------------------*/ +/** @addtogroup ADC_Exported_Functions ADC exported functions + * @{ + */ +/*********************************************************************************************************//** + * @brief Deinitialize the HT_ADCn peripheral registers to their default reset values. + * @param HT_ADCn: where HT_ADCn is the selected ADC from the ADC peripherals. + * @retval None + ************************************************************************************************************/ +void ADC_DeInit(HT_ADC_TypeDef* HT_ADCn) +{ + RSTCU_PeripReset_TypeDef RSTCUReset = {{0}}; + + /* Check the parameters */ + Assert_Param(IS_ADC(HT_ADCn)); + + if (HT_ADCn == NULL) // Remove the compiler warning + { + } + + RSTCUReset.Bit.ADC0 = 1; + RSTCU_PeripReset(RSTCUReset, ENABLE); +} + +/*********************************************************************************************************//** + * @brief Reset ADC. + * @param HT_ADCn: is the selected ADC from the ADC peripherals. + * @retval None + ************************************************************************************************************/ +void ADC_Reset(HT_ADC_TypeDef* HT_ADCn) +{ + /* Check the parameters */ + Assert_Param(IS_ADC(HT_ADCn)); + + HT_ADCn->CR |= ADC_SOFTWARE_RESET; +} + +/*********************************************************************************************************//** + * @brief Enable or Disable the specified ADC. + * @param HT_ADCn: where HT_ADCn is the selected ADC from the ADC peripherals. + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void ADC_Cmd(HT_ADC_TypeDef* HT_ADCn, ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_ADC(HT_ADCn)); + Assert_Param(IS_CONTROL_STATUS(NewState)); + + if (NewState != DISABLE) + { + HT_ADCn->CR |= ADC_ENABLE_BIT; + } + else + { + HT_ADCn->CR &= ~(ADC_ENABLE_BIT); + } +} + +/*********************************************************************************************************//** + * @brief Configure conversion mode and length of list queue for regular group. + * @param HT_ADCn: where HT_ADCn is the selected ADC from the ADC peripherals. + * @param ADC_MODE: ADC Cyclic Conversion Mode. + * This parameter can be one of the following values: + * @arg ONE_SHOT_MODE : + * @arg CONTINUOUS_MODE : + * @arg DISCONTINUOUS_MODE : + * @param Length: must between 1 ~ 8 + * @param SubLength: must between 1 ~ 8, only valid for DISCONTINUOUS_MODE. + * @retval None + ************************************************************************************************************/ +void ADC_RegularGroupConfig(HT_ADC_TypeDef* HT_ADCn, u8 ADC_MODE, u8 Length, u8 SubLength) +{ + /* Check the parameters */ + Assert_Param(IS_ADC(HT_ADCn)); + Assert_Param(IS_ADC_CONVERSION_MODE(ADC_MODE)); + Assert_Param(IS_ADC_REGULAR_LENGTH(Length)); + #if (LIBCFG_ADC_NO_DISCON_MODE == 0) + if (ADC_MODE == DISCONTINUOUS_MODE) + { + Assert_Param(IS_ADC_REGULAR_SUB_LENGTH(SubLength)); + } + #endif + + #if (LIBCFG_ADC_NO_DISCON_MODE) + /* Config cyclic conversion mode and length of list queue for regular group */ + HT_ADCn->CR = ((u32)(Length - 1) << 8) | ADC_MODE | (HT_ADCn->CR & ADC_ENABLE_BIT); + #else + /* Config cyclic conversion mode and length of list queue and sub length for regular group */ + HT_ADCn->CR = ((u32)(SubLength - 1) << 16) | ((u32)(Length - 1) << 8) | ADC_MODE | (HT_ADCn->CR & ADC_ENABLE_BIT); + #endif +} + +/*********************************************************************************************************//** + * @brief Configure the corresponding rank in the sequencer for the regular channel + * @param HT_ADCn: where HT_ADCn is the selected ADC from the ADC peripherals. + * @param ADC_CH_n: the ADC channel to configure + * This parameter can be one of the following values: + * @arg ADC_CH_n : ADC Channel n selected, n must between 0 ~ m (m represent the maximum external ADC input channel). + * @arg ADC_CH_DAC0_CH0 : ADC DAC0_CH0 selected + * @arg ADC_CH_DAC0_CH1 : ADC DAC0_CH1 selected + * @arg ADC_CH_DAC1_CH0 : ADC DAC1_CH0 selected + * @arg ADC_CH_DAC1_CH1 : ADC DAC1_CH1 selected + * @arg ADC_CH_IVREF : ADC Internal VREF selected + * @arg ADC_CH_GND_VREF : ADC GND VREF selected + * @arg ADC_CH_VDD_VREF : ADC VDD VREF selected + * @arg ADC_CH_MVDDA : ADC MVDDA selected + * @param Rank: The rank in the regular group sequencer. + * This parameter must be between 0 to 7. + * @param ...: Null parameter for API compatibility. + * @retval None + ************************************************************************************************************/ +void ADC_RegularChannelConfig(HT_ADC_TypeDef* HT_ADCn, u8 ADC_CH_n, u8 Rank, ...) +{ + u32 tmpreg1, tmpreg2; + + /* Check the parameters */ + Assert_Param(IS_ADC(HT_ADCn)); + Assert_Param(IS_ADC_CHANNEL(ADC_CH_n)); + Assert_Param(IS_ADC_REGULAR_RANK(Rank)); + + /* Get the old register value */ + tmpreg1 = HT_ADCn->LST[Rank >> 2]; + /* Calculate the mask to clear */ + tmpreg2 = LST_SEQ_SET << (8 * (Rank & 0x3)); + /* Clear the old SEQx bits for the selected rank */ + tmpreg1 &= ~tmpreg2; + /* Calculate the mask to set */ + tmpreg2 = (u32)ADC_CH_n << (8 * (Rank & 0x3)); + /* Set the SEQx bits for the selected rank */ + tmpreg1 |= tmpreg2; + /* Store the new register value */ + HT_ADCn->LST[Rank >> 2] = tmpreg1; +} + +/*********************************************************************************************************//** + * @brief Configure the ADC trigger source for regular channels conversion. + * @param HT_ADCn: where HT_ADCn is the selected ADC from the ADC peripherals. + * @param ADC_TRIG_x: + * This parameter can be one of the following values: + * @arg ADC_TRIG_SOFTWARE : S/W trigger + * @arg ADC_TRIG_EXTI_n : where n can be 0 ~ 15 + * @arg ADC_TRIG_MCTMn_MTO : where n can be 0 + * @arg ADC_TRIG_MCTMn_CH0O : where n can be 0 + * @arg ADC_TRIG_MCTMn_CH1O : where n can be 0 + * @arg ADC_TRIG_MCTMn_CH2O : where n can be 0 + * @arg ADC_TRIG_MCTMn_CH3O : where n can be 0 + * @arg ADC_TRIG_GPTMn_MTO : where n can be 0 ~ 1 + * @arg ADC_TRIG_GPTMn_CH0O : where n can be 0 ~ 1 + * @arg ADC_TRIG_GPTMn_CH1O : where n can be 0 ~ 1 + * @arg ADC_TRIG_GPTMn_CH2O : where n can be 0 ~ 1 + * @arg ADC_TRIG_GPTMn_CH3O : where n can be 0 ~ 1 + * @arg ADC_TRIG_BFTMn : where n can be 0 ~ 1 + * @arg ADC_TRIG_PWMn_MTO : where n can be 0 ~ 1 + * @arg ADC_TRIG_PWMn_CH0O : where n can be 0 ~ 1 + * @arg ADC_TRIG_PWMn_CH1O : where n can be 0 ~ 1 + * @arg ADC_TRIG_PWMn_CH2O : where n can be 0 ~ 1 + * @arg ADC_TRIG_PWMn_CH3O : where n can be 0 ~ 1 + * @arg ADC_TRIG_CMPn : where n can be 0 ~ 1 + * @retval None + ************************************************************************************************************/ +void ADC_RegularTrigConfig(HT_ADC_TypeDef* HT_ADCn, u32 ADC_TRIG_x) +{ + /* Check the parameters */ + Assert_Param(IS_ADC(HT_ADCn)); + Assert_Param(IS_ADC_TRIG(ADC_TRIG_x)); + + /* Config external trigger conversion source of regular group */ + #if (LIBCFG_ADC_SW_TRIGGER_ONLY == 0) + HT_ADCn->TCR = ADC_TRIG_x & 0x0000001F; + #endif + HT_ADCn->TSR = ADC_TRIG_x & (~0x0000001F); +} + +/*********************************************************************************************************//** + * @brief Configure the sampling time for the ADC input channel. + * @param HT_ADCn: where HT_ADCn is the selected ADC from the ADC peripherals. + * @param SampleClock: must between 0 ~ 255. + * @retval None + ************************************************************************************************************/ +void ADC_SamplingTimeConfig(HT_ADC_TypeDef* HT_ADCn, u8 SampleClock) +{ + /* Check the parameters */ + Assert_Param(IS_ADC(HT_ADCn)); + + /* config sampling clock of ADC input channel */ + HT_ADCn->STR = SampleClock; +} + +/*********************************************************************************************************//** + * @brief Enable or Disable software start of the regular channel conversion of the selected ADC. + * @param HT_ADCn: where HT_ADCn is the selected ADC from the ADC peripherals. + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void ADC_SoftwareStartConvCmd(HT_ADC_TypeDef* HT_ADCn, ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_ADC(HT_ADCn)); + Assert_Param(IS_CONTROL_STATUS(NewState)); + + /* Start Conversion */ + if (NewState != DISABLE) + { + HT_ADCn->TSR |= TCR_SC_SET; + } + else + { + HT_ADCn->TSR &= ~TCR_SC_SET; + } +} + +/*********************************************************************************************************//** + * @brief Return the result of ADC regular channel conversion. + * @param HT_ADCn: where HT_ADCn is the selected ADC from the ADC peripherals. + * @param ADC_REGULAR_DATAn: where n can be 0 ~ 7 + * @retval The Value of data conversion. + ************************************************************************************************************/ +u16 ADC_GetConversionData(HT_ADC_TypeDef* HT_ADCn, u8 ADC_REGULAR_DATAn) +{ + /* Check the parameters */ + Assert_Param(IS_ADC(HT_ADCn)); + Assert_Param(IS_ADC_REGULAR_DATA(ADC_REGULAR_DATAn)); + + return ((u16)HT_ADCn->DR[ADC_REGULAR_DATAn]); +} + +/*********************************************************************************************************//** + * @brief Enable or Disable the specified ADC interrupts. + * @param HT_ADCn: where HT_ADCn is the selected ADC from the ADC peripherals. + * @param ADC_INT_x: Specify the ADC interrupt sources that is to be enabled or disabled. + * This parameter can be any combination of the following values: + * @arg ADC_INT_SINGLE_EOC : + * @arg ADC_INT_SUB_GROUP_EOC : + * @arg ADC_INT_CYCLE_EOC : + * @arg ADC_INT_DATA_OVERWRITE : + * @arg ADC_INT_AWD_LOWER : + * @arg ADC_INT_AWD_UPPER : + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void ADC_IntConfig(HT_ADC_TypeDef* HT_ADCn, u32 ADC_INT_x, ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_ADC(HT_ADCn)); + Assert_Param(IS_ADC_INT(ADC_INT_x)); + Assert_Param(IS_CONTROL_STATUS(NewState)); + + if (NewState != DISABLE) + { + HT_ADCn->IER |= ADC_INT_x; + } + else + { + HT_ADCn->IER &= ~ADC_INT_x; + } +} + +/*********************************************************************************************************//** + * @brief Check whether the specified ADC interrupt has occurred. + * @param HT_ADCn: where HT_ADCn is the selected ADC from the ADC peripherals. + * @param ADC_INT_x: Specify the interrupt status to check. + * This parameter can be any combination of the following values: + * @arg ADC_INT_SINGLE_EOC : + * @arg ADC_INT_SUB_GROUP_EOC : + * @arg ADC_INT_CYCLE_EOC : + * @arg ADC_INT_DATA_OVERWRITE : + * @arg ADC_INT_AWD_LOWER : + * @arg ADC_INT_AWD_UPPER : + * @retval SET or RESET + ************************************************************************************************************/ +FlagStatus ADC_GetIntStatus(HT_ADC_TypeDef* HT_ADCn, u32 ADC_INT_x) +{ + FlagStatus Status; + + /* Check the parameters */ + Assert_Param(IS_ADC(HT_ADCn)); + Assert_Param(IS_ADC_INT(ADC_INT_x)); + + if ((HT_ADCn->ISR & ADC_INT_x) != RESET) + { + Status = SET; + } + else + { + Status = RESET; + } + + return Status; +} + +/*********************************************************************************************************//** + * @brief Clear the ADC interrupt pending bits. + * @param HT_ADCn: where HT_ADCn is the selected ADC from the ADC peripherals. + * @param ADC_INT_x: Specify the interrupt pending bits to be cleared. + * This parameter can be any combination of the following values: + * @arg ADC_INT_SINGLE_EOC : + * @arg ADC_INT_SUB_GROUP_EOC : + * @arg ADC_INT_CYCLE_EOC : + * @arg ADC_INT_DATA_OVERWRITE : + * @arg ADC_INT_AWD_LOWER : + * @arg ADC_INT_AWD_UPPER : + * @retval None + ************************************************************************************************************/ +void ADC_ClearIntPendingBit(HT_ADC_TypeDef* HT_ADCn, u32 ADC_INT_x) +{ + /* Check the parameters */ + Assert_Param(IS_ADC(HT_ADCn)); + Assert_Param(IS_ADC_INT(ADC_INT_x)); + + HT_ADCn->ICLR = ADC_INT_x; +} + +/*********************************************************************************************************//** + * @brief Check whether the specified ADC flag has been set. + * @param HT_ADCn: where HT_ADCn is the selected ADC from the ADC peripherals. + * @param ADC_FLAG_x: Specify the flag to check. + * This parameter can be any combination of the following values: + * @arg ADC_FLAG_SINGLE_EOC : + * @arg ADC_FLAG_SUB_GROUP_EOC : + * @arg ADC_FLAG_CYCLE_EOC : + * @arg ADC_FLAG_DATA_OVERWRITE : + * @arg ADC_FLAG_AWD_LOWER : + * @arg ADC_FLAG_AWD_UPPER : + * @retval SET or RESET + ************************************************************************************************************/ +FlagStatus ADC_GetFlagStatus(HT_ADC_TypeDef* HT_ADCn, u32 ADC_FLAG_x) +{ + FlagStatus Status; + + /* Check the parameters */ + Assert_Param(IS_ADC(HT_ADCn)); + Assert_Param(IS_ADC_FLAG(ADC_FLAG_x)); + + if ((HT_ADCn->IRAW & ADC_FLAG_x) != RESET) + { + Status = SET; + } + else + { + Status = RESET; + } + + return Status; +} + +#if (LIBCFG_ADC_NO_WDT == 0) +/*********************************************************************************************************//** + * @brief Enable or Disable Lower/Upper threshold warning of the analog watchdog on single/all channels. + * @param HT_ADCn: where HT_ADCn is the selected ADC from the ADC peripherals. + * @param ADC_AWD_x: + * This parameter can be any combination of the following values: + * @arg ADC_AWD_DISABLE : + * @arg ADC_AWD_ALL_LOWER : + * @arg ADC_AWD_ALL_UPPER : + * @arg ADC_AWD_ALL_LOWER_UPPER : + * @arg ADC_AWD_SINGLE_LOWER : + * @arg ADC_AWD_SINGLE_UPPER : + * @arg ADC_AWD_SINGLE_LOWER_UPPER : + * @retval None + ************************************************************************************************************/ +void ADC_AWDConfig(HT_ADC_TypeDef* HT_ADCn, u32 ADC_AWD_x) +{ + /* Check the parameters */ + Assert_Param(IS_ADC(HT_ADCn)); + Assert_Param(IS_ADC_AWD(ADC_AWD_x)); + + HT_ADCn->WCR = (HT_ADCn->WCR & 0xFFFFFFF8) | ADC_AWD_x; +} + +/*********************************************************************************************************//** + * @brief Configure the analog watchdog that guards single channel. + * @param HT_ADCn: where HT_ADCn is the selected ADC from the ADC peripherals. + * @param ADC_CH_n: where n must between 0 ~ m (m represent the maximum external ADC input channel). + * @retval None + ************************************************************************************************************/ +void ADC_AWDSingleChannelConfig(HT_ADC_TypeDef* HT_ADCn, u8 ADC_CH_n) +{ + /* Check the parameters */ + Assert_Param(IS_ADC(HT_ADCn)); + Assert_Param(IS_ADC_INPUT_CHANNEL(ADC_CH_n)); + + HT_ADCn->WCR = (HT_ADCn->WCR & 0xFFFFF0FF) | ((u32)ADC_CH_n << 8); +} + +/*********************************************************************************************************//** + * @brief Configure the high and low thresholds of the analog watchdog. + * @param HT_ADCn: where HT_ADCn is the selected ADC from the ADC peripherals. + * @param UPPER: must between 0x0000 ~ 0x0FFF + * @param LOWER: must between 0x0000 ~ 0x0FFF + * @retval None + ************************************************************************************************************/ +void ADC_AWDThresholdsConfig(HT_ADC_TypeDef* HT_ADCn, u16 UPPER, u16 LOWER) +{ + /* Check the parameters */ + Assert_Param(IS_ADC(HT_ADCn)); + Assert_Param(IS_ADC_THRESHOLD(UPPER)); + Assert_Param(IS_ADC_THRESHOLD(LOWER)); + + HT_ADCn->WTR = (UPPER << 16) | LOWER; +} +#endif + +#if (LIBCFG_PDMA) +/*********************************************************************************************************//** + * @brief Enable or Disable the specified PDMA request. + * @param HT_ADCn: where HT_ADCn is the selected ADC from the ADC peripherals. + * @param ADC_PDMA_x: Specify the ADC PDMA request that is to be enabled or disabled. + * This parameter can be any combination of the following values: + * @arg ADC_PDMA_REGULAR_SINGLE : + * @arg ADC_PDMA_REGULAR_SUBGROUP : + * @arg ADC_PDMA_REGULAR_CYCLE : + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void ADC_PDMAConfig(HT_ADC_TypeDef* HT_ADCn, u32 ADC_PDMA_x, ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_ADC(HT_ADCn)); + Assert_Param(IS_ADC_PDMA(ADC_PDMA_x)); + Assert_Param(IS_CONTROL_STATUS(NewState)); + + if (NewState != DISABLE) + { + HT_ADCn->PDMAR |= ADC_PDMA_x; + } + else + { + HT_ADCn->PDMAR &= ~ADC_PDMA_x; + } +} +#endif + +#if (LIBCFG_ADC_IVREF) +/*********************************************************************************************************//** + * @brief Enable or Disable the VREF. + * @param HT_ADCn: where HT_ADCn is the selected ADC from the ADC peripherals. + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void ADC_VREFCmd(HT_ADC_TypeDef* HT_ADCn, ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_ADC(HT_ADCn)); + Assert_Param(IS_CONTROL_STATUS(NewState)); + + if (NewState != DISABLE) + { + HT_ADCn->VREFCR |= 0x00000001; + } + else + { + HT_ADCn->VREFCR &= ~(0x00000001); + } +} + +/*********************************************************************************************************//** + * @brief Configure the VREF output voltage. + * @param HT_ADCn: where HT_ADCn is the selected ADC from the ADC peripherals. + * @param ADC_VREF_x: + * This parameter can be one of the following value: + * @arg ADC_VREF_1V215 : + * @arg ADC_VREF_2V0 : + * @arg ADC_VREF_2V5 : + * @arg ADC_VREF_2V7 : + * For the 5 V version (LIBCFG_ADC_IVREF_LEVEL_TYPE2): + * @arg ADC_VREF_2V5 : + * @arg ADC_VREF_3V0 : + * @arg ADC_VREF_4V0 : + * @arg ADC_VREF_4V5 : + * @retval None + ************************************************************************************************************/ +void ADC_VREFConfig(HT_ADC_TypeDef* HT_ADCn, u32 ADC_VREF_x) +{ + /* Check the parameters */ + Assert_Param(IS_ADC(HT_ADCn)); + Assert_Param(IS_ADC_VREF_SEL(ADC_VREF_x)); + + HT_ADCn->VREFCR = (HT_ADCn->VREFCR & ~(3ul << 4)) | (ADC_VREF_x); +} +#endif + +#if (LIBCFG_ADC_VREFBUF) +/*********************************************************************************************************//** + * @brief Enable or Disable the VREF output. When enable, the VREF provides a stable voltage output to the ADVREFP pin (ADC reference positive voltage). + * @param HT_ADCn: where HT_ADCn is the selected ADC from the ADC peripherals. + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void ADC_VREFOutputCmd(HT_ADC_TypeDef* HT_ADCn, ControlStatus NewState) +{ + /* !!! NOTICE !!! + The ADCREFP pin should not be connected to an external voltage when the VREF output is enabled. + */ + + /* Check the parameters */ + Assert_Param(IS_ADC(HT_ADCn)); + Assert_Param(IS_CONTROL_STATUS(NewState)); + + if (NewState != DISABLE) + { + HT_ADCn->VREFCR |= 0x00000002; + } + else + { + HT_ADCn->VREFCR &= ~(0x00000002); + } +} +#endif + +#if (LIBCFG_ADC_MVDDA) +/*********************************************************************************************************//** + * @brief Enable or Disable the power of MVDDA (VDDA/2) + * @param HT_ADCn: where HT_ADCn is the selected ADC from the ADC peripherals. + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void ADC_MVDDACmd(HT_ADC_TypeDef* HT_ADCn, ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_ADC(HT_ADCn)); + Assert_Param(IS_CONTROL_STATUS(NewState)); + + if (NewState != DISABLE) + { + HT_ADCn->VREFCR |= ADC_VREF_MVDDAEN; + } + else + { + HT_ADCn->VREFCR &= ~(ADC_VREF_MVDDAEN); + } +} + +#endif +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/ht32f5xxxx_aes.c b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/ht32f5xxxx_aes.c new file mode 100644 index 0000000000..133889a258 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/ht32f5xxxx_aes.c @@ -0,0 +1,552 @@ +/*********************************************************************************************************//** + * @file ht32f5xxxx_aes.c + * @version $Rev:: 7390 $ + * @date $Date:: 2023-12-12 #$ + * @brief This file provides all the ADC firmware functions. + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ + +/* Includes ------------------------------------------------------------------------------------------------*/ +#include "ht32f5xxxx_aes.h" + +/** @addtogroup HT32F5xxxx_Peripheral_Driver HT32F5xxxx Peripheral Driver + * @{ + */ + +/** @defgroup AES AES + * @brief AES driver modules + * @{ + */ + + +/* Global variables ----------------------------------------------------------------------------------------*/ +u32 *gpu32OutputBuff; +u32 gu32OutputIndex = 0; + +u32 *gpu32InputBuff; +u32 gu32InputSize = 0; +u32 gu32InputIndex = 0; + +/* Private functions ---------------------------------------------------------------------------------------*/ +static void _AES_Init(HT_AES_TypeDef* HT_AESn, AES_InitTypeDef* AES_InitStruct); + +/* Global functions ----------------------------------------------------------------------------------------*/ +/** @defgroup AES_Exported_Functions AES exported functions + * @{ + */ +/*********************************************************************************************************//** + * @brief Deinitialize the AES peripheral registers to their default reset values. + * @param HT_AESn: where HT_AESn is the selected AES from the AES peripherals. + * @retval None + ************************************************************************************************************/ +void AES_DeInit(HT_AES_TypeDef* HT_AESn) +{ + RSTCU_PeripReset_TypeDef RSTCUReset = {{0}}; + + if (HT_AESn == NULL) // Remove the compiler warning + { + } + + RSTCUReset.Bit.AES = 1; + RSTCU_PeripReset(RSTCUReset, ENABLE); +} + +/*********************************************************************************************************//** + * @brief Flush the FIFO. + * @param HT_AESn: where HT_AESn is the selected AES from the AES peripherals. + * @retval None + ************************************************************************************************************/ +void AES_FIFOFlush(HT_AES_TypeDef* HT_AESn) +{ + AES_Cmd(HT_AESn, DISABLE); + HT_AESn->CR |= AES_FLUSH_ENABLE; + AES_Cmd(HT_AESn, ENABLE); +} + +/*********************************************************************************************************//** + * @brief Enable or Disable the specified AES. + * @param HT_AESn: where HT_AESn is the selected AES from the AES peripherals. + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void AES_Cmd(HT_AES_TypeDef* HT_AESn, ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_AES(HT_AESn)); + Assert_Param(IS_CONTROL_STATUS(NewState)); + + if (NewState != DISABLE) + { + HT_AESn->CR |= AES_ENABLE; + } + else + { + HT_AESn->CR &= ~AES_ENABLE; + } +} + +/*********************************************************************************************************//** + * @brief Start the AES key. + * @param HT_AESn: where HT_AESn is the selected AES from the AES peripherals. + * @retval None + ************************************************************************************************************/ +void AES_StartKey(HT_AES_TypeDef* HT_AESn) +{ + HT_AESn->CR |= (1 << 4); +} + +/*********************************************************************************************************//** + * @brief Initialize the AES peripheral according to the specified parameters in the AES_InitStruct. + * @param HT_AESn: where AES is the selected AES peripheral. + * @param AES_InitStruct: pointer to a AES_InitTypeDef structure. + * @retval None + ************************************************************************************************************/ +void _AES_Init(HT_AES_TypeDef* HT_AESn, AES_InitTypeDef* AES_InitStruct) +{ + /* Check the parameters */ + Assert_Param(IS_AES(HT_AESn)); + Assert_Param(IS_AES_KEY_SIZE(AES_InitStruct->AES_KeySize)); + Assert_Param(IS_AES_DIR(AES_InitStruct->AES_Dir)); + Assert_Param(IS_AES_MODE(AES_InitStruct->AES_Mode)); + Assert_Param(IS_AES_SWAP(AES_InitStruct->AES_Swap)); + + HT_AESn->CR = (HT_AESn->CR & 0xFFFFFE81) | AES_InitStruct->AES_KeySize | + AES_InitStruct->AES_Dir | AES_InitStruct->AES_Mode | + AES_InitStruct->AES_Swap; + + AES_Cmd(HT_AESn, ENABLE); +} + +/*********************************************************************************************************//** + * @brief Initialize the AES peripheral on ECB mode according to the specified parameters in the AES_InitStruct. + * @param HT_AESn: where AES is the selected AES peripheral. + * @param AES_InitStruct: pointer to a AES_InitTypeDef structure. + * @retval None + ************************************************************************************************************/ +void AES_ECB_Init(HT_AES_TypeDef* HT_AESn, AES_InitTypeDef* AES_InitStruct) +{ + AES_InitStruct->AES_Mode = AES_MODE_ECB; + _AES_Init(HT_AESn, AES_InitStruct); + + AES_IntConfig(HT_AESn, AES_IER_OFINTEN, ENABLE); + NVIC_EnableIRQ(AES_IRQn); +} + +/*********************************************************************************************************//** + * @brief Initialize the AES peripheral on CBC mode according to the specified parameters in the AES_InitStruct. + * @param HT_AESn: where AES is the selected AES peripheral. + * @param AES_InitStruct: pointer to a AES_InitTypeDef structure. + * @retval None + ************************************************************************************************************/ +void AES_CBC_Init(HT_AES_TypeDef* HT_AESn, AES_InitTypeDef* AES_InitStruct) +{ + AES_InitStruct->AES_Mode = AES_MODE_CBC; + _AES_Init(HT_AESn, AES_InitStruct); + + AES_IntConfig(HT_AESn, AES_IER_OFINTEN, ENABLE); + NVIC_EnableIRQ(AES_IRQn); +} + +/*********************************************************************************************************//** + * @brief Initialize the AES peripheral on CTR mode according to the specified parameters in the AES_InitStruct. + * @param HT_AESn: where HT_AESn is the selected AES peripheral. + * @param AES_InitStruct: pointer to a AES_InitTypeDef structure. + * @retval None + ************************************************************************************************************/ +void AES_CTR_Init(HT_AES_TypeDef* HT_AESn, AES_InitTypeDef* AES_InitStruct) +{ + AES_InitStruct->AES_Mode = AES_MODE_CTR; + _AES_Init(HT_AESn, AES_InitStruct); + + AES_IntConfig(HT_AESn, AES_IER_OFINTEN, ENABLE); + NVIC_EnableIRQ(AES_IRQn); +} + +/*********************************************************************************************************//** + * @brief Check whether the specified AES status has been set. + * @param HT_AESn: where HT_AESn is the selected AES peripheral. + * @param AES_SR_x: specify the flag to be check. + * This parameter can be one of the following values: + * @arg AES_SR_IFEMPTY : AES Input FIFO is Empty + * @arg AES_SR_IFNFULL : AES Input FIFO is not Full + * @arg AES_SR_OFNEMPTY : AES Output FIFO is not Empty + * @arg AES_SR_OFFULL : AES Output FIFO is Full + * @arg AES_SR_BUSY : AES is busy when AES is in encrypt/decrypt action and key expansion + * @retval SET or RESET + ************************************************************************************************************/ +FlagStatus AES_GetStatus(HT_AES_TypeDef* HT_AESn, u32 AES_SR_x) +{ + Assert_Param(IS_AES(HT_AESn)); + Assert_Param(IS_AES_STATUS(AES_SR_x)); + + if ((HT_AESn->SR & AES_SR_x) != (u32)RESET) + { + return (SET); + } + else + { + return (RESET); + } +} + +/*********************************************************************************************************//** + * @brief Enable or Disable the AES PDMA interface. + * @param HT_AESn: where HT_AESn is the selected HT_AESn peripheral. + * @param AES_PDMA_xFDMAEN: specify the AES FIFO DMA to be enabled or disabled. + * This parameter can be any combination of the following values: + * @arg AES_PDMA_IFDMAEN : input FIFO PDMA + * @arg AES_PDMA_OFDMAEN : Output FIFO PDMA + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void AES_PDMACmd(HT_AES_TypeDef* HT_AESn, u32 AES_PDMA_xFDMAEN, ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_AES(HT_AESn)); + Assert_Param(IS_CONTROL_STATUS(NewState)); + + if (NewState != DISABLE) + { + HT_AESn->PDMAR |= AES_PDMA_xFDMAEN; + } + else + { + HT_AESn->PDMAR &= ~AES_PDMA_xFDMAEN; + } +} + +/*********************************************************************************************************//** + * @brief Check whether the specified AES interrupt has occurred. + * @param HT_AESn: where HT_AESn is the selected AES from the AES peripherals. + * @param AES_INTSR_x: Specify the interrupt status to check. + * This parameter can be any combination of the following values: + * @arg AES_INTSR_IFINT : + * @arg AES_INTSR_OFINT : + * @return SET or RESET + ************************************************************************************************************/ +FlagStatus AES_GetIntStatus(HT_AES_TypeDef* HT_AESn, u32 AES_INTSR_x) +{ + FlagStatus Status; + u32 aes_isr = HT_AESn->ISR; + u32 aes_ier = HT_AESn->IER; + + /* Check the parameters */ + Assert_Param(IS_AES(HT_AESn)); + Assert_Param(IS_AES_INTSR(AES_INTSR_x)); + + Status = (FlagStatus)(aes_isr & aes_ier); + if ((Status & AES_INTSR_x) != RESET) + { + Status = SET; + } + else + { + Status = RESET; + } + + return Status; +} + +/*********************************************************************************************************//** + * @brief Enable or Disable the specified AES interrupts. + * @param HT_AESn: where HT_AESn is the selected AES from the AES peripherals. + * @param AES_IER_x: Specify the AES interrupt sources that is to be enabled or disabled. + * This parameter can be any combination of the following values: + * @arg AES_IER_IFINTEN : + * @arg AES_IER_OFINTEN : + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void AES_IntConfig(HT_AES_TypeDef* HT_AESn, u32 AES_IER_x, ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_AES(HT_AESn)); + Assert_Param(IS_AES_IER(AES_IER_x)); + Assert_Param(IS_CONTROL_STATUS(NewState)); + + if (NewState != DISABLE) + { + HT_AESn->IER |= AES_IER_x; + } + else + { + HT_AESn->IER &= ~AES_IER_x; + } +} + +/*********************************************************************************************************//** + * @brief Set the specified AES Input data. + * @param HT_AESn: where HT_AESn is the selected AES from the AES peripherals + * @param AES_Data: Data input + * @retval None + ************************************************************************************************************/ +void AES_SetInputData(HT_AES_TypeDef* HT_AESn, uc32 AES_Data) +{ + Assert_Param(IS_AES(HT_AESn)); + #if (LIBCFG_AES_SWAP) + HT_AESn->DINR = __REV(AES_Data); + #else + HT_AESn->DINR = AES_Data; + #endif +} + +/*********************************************************************************************************//** + * @brief Get the specified AES output data. + * @param HT_AESn: where HT_AESn is the selected AES from the AES peripherals + * @retval Output Data + ************************************************************************************************************/ +u32 AES_GetOutputData(HT_AES_TypeDef* HT_AESn) +{ + Assert_Param(IS_AES(HT_AESn)); + #if (LIBCFG_AES_SWAP) + return __REV(HT_AESn->DOUTR); + #else + return HT_AESn->DOUTR; + #endif +} + +/*********************************************************************************************************//** + * @brief Set the specified AES key table. + * @param HT_AESn: where HT_AESn is the selected AES from the AES peripherals. + * @param Key: Key table + * @param keySize: Key table's size + * @retval None + ************************************************************************************************************/ +void AES_SetKeyTable(HT_AES_TypeDef* HT_AESn, u32 *Key, u32 keySize) +{ + u32 i; + u32 uCRTemp = HT_AESn->CR & (~(0x00000060UL)); + if (keySize == 128/8) + { + uCRTemp |= AES_KEYSIZE_128B; + } + #if (LIBCFG_AES_KEYSIZE_256B) + else if (keySize == 192/8) + { + uCRTemp |= AES_KEYSIZE_192B; + } + else if (keySize == 256/8) + { + uCRTemp |= AES_KEYSIZE_256B; + } + #endif + else + { + return; + } + HT_AESn->CR = uCRTemp; + + for (i = 0; i < keySize; i += 4) + { + #if (LIBCFG_AES_SWAP) + HT_AESn->KEYR[i >> 2] = __REV(*&Key[i]); + #else + HT_AESn->KEYR[i >> 2] = *&Key[i]; + #endif + } + + AES_StartKey(HT_AES); +} + +/*********************************************************************************************************//** + * @brief Set the specified AES Vector table. + * @param HT_AESn: where HT_AESn is the selected AES from the AES peripherals. + * @param Vector: + * @retval None + ************************************************************************************************************/ +void AES_SetVectorTable(HT_AES_TypeDef* HT_AESn, u32 *Vector) +{ + int i; + Assert_Param(IS_AES(HT_AESn)); + + for (i = 0; i < 16; i += 4) + { + #if (LIBCFG_AES_SWAP) + HT_AESn->IVR[i >> 2] = __REV(*&Vector[i]); + #else + HT_AESn->IVR[i >> 2] = *&Vector[i]; + #endif + } +} + +/*********************************************************************************************************//** + * @brief AES Crypt Data + * @param HT_AESn: where HT_AESn is the selected AES from the AES peripherals + * @param dir: Crypt Data's direction + * @param iv: initial vector table + * @param length: data size + * @param inputData: InputData + * @param outputData: Output Data + * @retval SUCCESS or ERROR + ************************************************************************************************************/ +ErrStatus _AES_CryptData(HT_AES_TypeDef* HT_AESn, + AES_DIR_Enum dir, + u32 *iv, + u32 length, + u32 *inputData, + u32 *outputData) +{ + /*AES Data blocks 16 byte */ + if ((length % 16) != 0) + { + /* Data size can not be divisible by 16. */ + return ERROR; + } + + /*Set inital Vector */ + if (iv != NULL) + { + AES_SetVectorTable(HT_AESn, iv); + } + + /*FIFO Flush */ + AES_FIFOFlush(HT_AES); + + /*Set direction */ + HT_AESn->CR = (HT_AESn->CR & 0xFFFFFFFD) | dir; + + /*Create input/output data */ + gpu32InputBuff = inputData; + gpu32OutputBuff = outputData; + + /*Init Index */ + gu32OutputIndex = 0; + gu32InputSize = length/4; + + /*Set input data */ + AES_IntConfig(HT_AES, AES_IER_IFINTEN, ENABLE); + + /*Waitting for conversion */ + while (AES_GetStatus(HT_AES, AES_SR_OFNEMPTY)); + return SUCCESS; +} + +#if 0 +/*********************************************************************************************************//** + * @brief AES Crypt Data on ECB mode + * @param HT_AESn: where HT_AESn is the selected AES from the AES peripherals + * @param dir: Crypt Data's direction + * @param length: data size + * @param inputData: InputData + * @param outputData: Output Data + * @retval SUCCESS or ERROR + ************************************************************************************************************/ +ErrStatus AES_ECB_CryptData(HT_AES_TypeDef* HT_AESn, + AES_DIR_Enum dir, + u32 length, + u32 *inputData, + u32 *outputData) +{ + return _AES_CryptData(HT_AESn, + dir, + NULL, + length, + inputData, + outputData); +} + +/*********************************************************************************************************//** + * @brief AES Crypt Data on CBC mode + * @param HT_AESn: where HT_AESn is the selected AES from the AES peripherals + * @param dir: Crypt Data's direction + * @param iv: initial vector table + * @param length: data size + * @param inputData: InputData + * @param outputData: Output Data + * @retval SUCCESS or ERROR + ************************************************************************************************************/ +ErrStatus AES_CBC_CryptData(HT_AES_TypeDef* HT_AESn, + AES_DIR_Enum dir, + u32 *iv, + u32 length, + u32 *inputData, + u32 *outputData) +{ + return _AES_CryptData(HT_AESn, + dir, + iv, + length, + inputData, + outputData); +} + +/*********************************************************************************************************//** + * @brief AES Crypt Data on CTR mode + * @param HT_AESn: where HT_AESn is the selected AES from the AES peripherals + * @param iv: initial vector table + * @param length: data size + * @param inputData: InputData + * @param outputData: Output Data + * @retval SUCCESS or ERROR + ************************************************************************************************************/ +ErrStatus AES_CTR_CryptData(HT_AES_TypeDef* HT_AESn, + u32 *iv, + u32 length, + u32 *inputData, + u32 *outputData) +{ + return _AES_CryptData(HT_AESn, + AES_DIR_ENCRYPT, + iv, + length, + inputData, + outputData); +} +#endif + +/*********************************************************************************************************//** + * @brief This function handles AES Core interrupt. + * @param HT_AESn: where HT_AESn is the selected AES from the AES peripherals. + * @retval None + ************************************************************************************************************/ +void AESCore_IRQHandler(HT_AES_TypeDef* HT_AESn) +{ + if (AES_GetIntStatus(HT_AES, AES_INTSR_OFINT)) + { + gpu32OutputBuff[gu32OutputIndex++] = AES_GetOutputData(HT_AES); + } + if (AES_GetIntStatus(HT_AES, AES_INTSR_IFINT)) + { + if (gu32InputIndex < gu32InputSize) + { + AES_SetInputData(HT_AES, gpu32InputBuff[gu32InputIndex]); + gu32InputIndex++; + } + else + { + AES_IntConfig(HT_AES, AES_IER_IFINTEN, DISABLE); + gu32InputIndex = 0; + } + } +} +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/ht32f5xxxx_bftm.c b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/ht32f5xxxx_bftm.c new file mode 100644 index 0000000000..db0ad91c0f --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/ht32f5xxxx_bftm.c @@ -0,0 +1,242 @@ +/*********************************************************************************************************//** + * @file ht32f5xxxx_bftm.c + * @version $Rev:: 6393 $ + * @date $Date:: 2022-10-27 #$ + * @brief This file provides all the BFTM firmware functions. + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ + +/* Includes ------------------------------------------------------------------------------------------------*/ +#include "ht32f5xxxx_bftm.h" + +/** @addtogroup HT32F5xxxx_Peripheral_Driver HT32F5xxxx Peripheral Driver + * @{ + */ + +/** @defgroup BFTM BFTM + * @brief BFTM driver modules + * @{ + */ + + +/* Global functions ----------------------------------------------------------------------------------------*/ +/** @defgroup BFTM_Exported_Functions BFTM exported functions + * @{ + */ +/*********************************************************************************************************//** + * @brief Deinitialize the specified BFTM registers to their default values. + * @param HT_BFTMn: where the HT_BFTMn is the selected BFTM from the BFTM peripherals. + * @retval None + ************************************************************************************************************/ +void BFTM_DeInit(HT_BFTM_TypeDef* HT_BFTMn) +{ + RSTCU_PeripReset_TypeDef RSTCUReset = {{0}}; + + /* Check the parameters */ + Assert_Param(IS_BFTM(HT_BFTMn)); + + if (HT_BFTMn == HT_BFTM0) + { + RSTCUReset.Bit.BFTM0 = 1; + } + #if (LIBCFG_BFTM1) + else if (HT_BFTMn == HT_BFTM1) + { + RSTCUReset.Bit.BFTM1 = 1; + } + #endif + RSTCU_PeripReset(RSTCUReset, ENABLE); +} + +/*********************************************************************************************************//** + * @brief Enable or Disable the specified BFTM. + * @param HT_BFTMn: where the HT_BFTMn is the selected BFTM from the BFTM peripherals. + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void BFTM_EnaCmd(HT_BFTM_TypeDef* HT_BFTMn, ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_BFTM(HT_BFTMn)); + Assert_Param(IS_CONTROL_STATUS(NewState)); + + if (NewState != DISABLE) + { + HT_BFTMn->CR |= (1UL << 2); + } + else + { + HT_BFTMn->CR &= ~(1UL << 2); + } +} + +/*********************************************************************************************************//** + * @brief Configure the CMP register value of the specified BFTM. + * @param HT_BFTMn: where the HT_BFTMn is the selected BFTM from the BFTM peripherals. + * @param uCompare: Specify a value to the CMP register. + * @retval None + ************************************************************************************************************/ +void BFTM_SetCompare(HT_BFTM_TypeDef* HT_BFTMn, BFTM_DataTypeDef uCompare) +{ + /* Check the parameters */ + Assert_Param(IS_BFTM(HT_BFTMn)); + + HT_BFTMn->CMP = uCompare; +} + +/*********************************************************************************************************//** + * @brief Get the CMP register value of the specified BFTM. + * @param HT_BFTMn: where the HT_BFTMn is the selected BFTM from the BFTM peripherals. + * @retval The value of the CMP register + ************************************************************************************************************/ +u32 BFTM_GetCompare(HT_BFTM_TypeDef* HT_BFTMn) +{ + /* Check the parameters */ + Assert_Param(IS_BFTM(HT_BFTMn)); + + return HT_BFTMn->CMP; +} + +/*********************************************************************************************************//** + * @brief Set the CNTR register value of the specified BFTM. + * @param HT_BFTMn: where the HT_BFTMn is the selected BFTM from the BFTM peripherals. + * @param uCounter: Specify a new value to the CNTR register. + * @retval None + ************************************************************************************************************/ +void BFTM_SetCounter(HT_BFTM_TypeDef* HT_BFTMn, BFTM_DataTypeDef uCounter) +{ + /* Check the parameters */ + Assert_Param(IS_BFTM(HT_BFTMn)); + + HT_BFTMn->CNTR = uCounter; +} + +/*********************************************************************************************************//** + * @brief Get the CNTR register value of the specified BFTM. + * @param HT_BFTMn: where the HT_BFTMn is the selected BFTM from the BFTM peripherals. + * @retval The value of the CNTR register + ************************************************************************************************************/ +u32 BFTM_GetCounter(HT_BFTM_TypeDef* HT_BFTMn) +{ + /* Check the parameters */ + Assert_Param(IS_BFTM(HT_BFTMn)); + + return HT_BFTMn->CNTR; +} + +/*********************************************************************************************************//** + * @brief Enable or Disable the one shot mode of the specified BFTM. + * @param HT_BFTMn: where the HT_BFTMn is the selected BFTM from the BFTM peripherals. + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void BFTM_OneShotModeCmd(HT_BFTM_TypeDef* HT_BFTMn, ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_BFTM(HT_BFTMn)); + Assert_Param(IS_CONTROL_STATUS(NewState)); + + if (NewState != DISABLE) + { + HT_BFTMn->CR |= (1UL << 1); + } + else + { + HT_BFTMn->CR &= ~(1UL << 1); + } +} + +/*********************************************************************************************************//** + * @brief Enable or Disable the specified BFTM interrupt. + * @param HT_BFTMn: where the HT_BFTMn is the selected BFTM from the BFTM peripherals. + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void BFTM_IntConfig(HT_BFTM_TypeDef* HT_BFTMn, ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_BFTM(HT_BFTMn)); + Assert_Param(IS_CONTROL_STATUS(NewState)); + + if (NewState != DISABLE) + { + HT_BFTMn->CR |= BFTM_INT_MATCH; + } + else + { + HT_BFTMn->CR &= ~BFTM_INT_MATCH; + } +} + +/*********************************************************************************************************//** + * @brief Get the flag status of the specified BFTM. + * @param HT_BFTMn: where the HT_BFTMn is the selected BFTM from the BFTM peripherals. + * @retval SET or RESET + ************************************************************************************************************/ +FlagStatus BFTM_GetFlagStatus(HT_BFTM_TypeDef* HT_BFTMn) +{ + /* Check the parameters */ + Assert_Param(IS_BFTM(HT_BFTMn)); + + if (HT_BFTMn->SR & BFTM_FLAG_MATCH) + { + return SET; + } + else + { + return RESET; + } +} + +/*********************************************************************************************************//** + * @brief Clear the interrupt flag of the specified BFTM. + * @param HT_BFTMn: where the HT_BFTMn is the selected BFTM from the BFTM peripherals. + * @retval None + ************************************************************************************************************/ +void BFTM_ClearFlag(HT_BFTM_TypeDef* HT_BFTMn) +{ + /* Check the parameters */ + Assert_Param(IS_BFTM(HT_BFTMn)); + + HT_BFTMn->SR &= ~BFTM_FLAG_MATCH; + + /*--------------------------------------------------------------------------------------------------------*/ + /* DSB instruction is added in this function to ensure the write operation which is for clearing interrupt*/ + /* flag is actually completed before exiting ISR. It prevents the NVIC from detecting the interrupt again */ + /* since the write register operation may be pended in the internal write buffer of Cortex-Mx when program*/ + /* has exited interrupt routine. This DSB instruction may be masked if this function is called in the */ + /* beginning of ISR and there are still some instructions before exiting ISR. */ + /*--------------------------------------------------------------------------------------------------------*/ + __DSB(); +} +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/ht32f5xxxx_can.c b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/ht32f5xxxx_can.c new file mode 100644 index 0000000000..22fca5ab02 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/ht32f5xxxx_can.c @@ -0,0 +1,1029 @@ +/*********************************************************************************************************//** + * @file ht32f5xxxx_can.c + * @version $Rev:: 7187 $ + * @date $Date:: 2023-08-31 #$ + * @brief This file provides all the CAN firmware functions. + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ + +/* Includes ------------------------------------------------------------------------------------------------*/ +#include "ht32f5xxxx_can.h" + +/** @addtogroup HT32F5xxxx_Peripheral_Driver HT32F5xxxx Peripheral Driver + * @{ + */ + +/** @defgroup CAN CAN + * @brief CAN driver modules + * @{ + */ + +/* Private types -------------------------------------------------------------------------------------------*/ +typedef enum +{ + IF0_NUM = 0, + IF1_NUM, + IF_TOTAL_NUM +} CANIF_NUMBER_Enum; + + +/* Private function prototypes -----------------------------------------------------------------------------*/ +static CANIF_NUMBER_Enum GetFreeIF(HT_CAN_TypeDef *CANx); + +/* Global functions ----------------------------------------------------------------------------------------*/ +/** @defgroup CAN_Exported_Functions CAN exported functions + * @{ + */ +/*********************************************************************************************************//** + * @brief Deinitialize the specified CAN registers to their default values. + * @param CANx: where the CANx is the selected CAN from the CAN peripherals. + * @retval None + ************************************************************************************************************/ +void CAN_DeInit(HT_CAN_TypeDef* CANx) +{ + RSTCU_PeripReset_TypeDef RSTCUReset = {{0}}; + /* Check the parameters */ + Assert_Param(IS_CAN(CANx)); + + if (CANx == HT_CAN0) + { + RSTCUReset.Bit.CAN0 = 1; + } + + RSTCU_PeripReset(RSTCUReset, ENABLE); +} + +/*********************************************************************************************************//** + * @brief This function is used to set CAN to enter initialization mode and enable access bit timing + * register.After bit timing configuration ready, user must call CAN_LeaveInitMode() + * to leave initialization mode and lock bit timing register to let new configuration + * take effect. + * @param CANx: The pointer to CAN module base address. + * @retval None + ***********************************************************************************************************/ +void CAN_EnterInitMode(HT_CAN_TypeDef *CANx) +{ + CANx->CR |= CAN_CR_INIT_Msk; + CANx->CR |= CAN_CR_CCE_Msk; +} + +/*********************************************************************************************************//** + * @brief Leave initialization mode + * @param CANx: The pointer to CAN module base address. + * @retval None + ***********************************************************************************************************/ +void CAN_LeaveInitMode(HT_CAN_TypeDef *CANx) +{ + CANx->CR &= (~(CAN_CR_INIT_Msk | CAN_CR_CCE_Msk)); + + while(CANx->CR & CAN_CR_INIT_Msk); /* Check INIT bit is released */ +} + +/*********************************************************************************************************//** + * @brief This function is used to Wait message into message buffer in basic mode. Please notice the + * function is polling NEWDAT bit of MCR register by while loop and it is used in basic mode. + * @param CANx: The pointer to CAN module base address. + * @retval None + ***********************************************************************************************************/ +void CAN_WaitMsg(HT_CAN_TypeDef *CANx) +{ + CANx->SR = 0x0; /* clr status */ + + while(1) + { + if(CANx->IF1.MCR & CAN_IF_MCR_NEWDAT_Msk) /* check new data */ + { + /*DEBUG_PRINTF("New Data IN\n");*/ + break; + } + if(CANx->SR & CAN_SR_RXOK_Msk) + { + /*DEBUG_PRINTF("Rx OK\n");*/ + } + if(CANx->SR & CAN_SR_LEC_Msk) + { + /*DEBUG_PRINTF("Error\n");*/ + } + } +} + +/*********************************************************************************************************//** + * @brief Get current bit rate + * @param CANx: The pointer to CAN module base address. + * @retval Current Bit-Rate (kilo bit per second) + ***********************************************************************************************************/ +u32 CAN_GetCANBitRate(HT_CAN_TypeDef *CANx) +{ + u32 wTseg1, wTseg2; + u32 wBpr; + + wTseg1 = (CANx->BTR & CAN_BTR_TSEG0_Msk) >> CAN_BTR_TSEG0_Pos; + wTseg2 = (CANx->BTR & CAN_BTR_TSEG1_Msk) >> CAN_BTR_TSEG1_Pos; + wBpr = CANx->BTR & CAN_BTR_BRP_Msk; + wBpr |= CANx->BRPER << 6; + + return (SystemCoreClock / (wBpr + 1) / (wTseg1 + wTseg2 + 3)); +} + +/**********************************************************************************************************//** + * @brief Switch the CAN into test mode. + * @param CANx: The pointer to CAN module base address. + * @param u8TestMask Specifies the configuration in test modes + * @arg CAN_TEST_BASIC_Msk : Enable basic mode of test mode + * @arg CAN_TEST_SILENT_Msk : Enable silent mode of test mode + * @arg CAN_TEST_LBACK_Msk : Enable Loop Back Mode of test mode + * @arg CAN_TEST_TX0_Msk/CAN_TEST_TX1_Msk: Control CAN_TX pin bit field + * @retval None + ***********************************************************************************************************/ +void CAN_EnterTestMode(HT_CAN_TypeDef *CANx, u32 u8TestMask) +{ + CANx->CR |= CAN_CR_TEST_Msk; + CANx->TR = u8TestMask; +} + +/*********************************************************************************************************//** + * @brief Leave the test mode + * @param CANx: The pointer to CAN module base address. + * @retval None + ***********************************************************************************************************/ +void CAN_LeaveTestMode(HT_CAN_TypeDef *CANx) +{ + CANx->CR |= CAN_CR_TEST_Msk; + CANx->TR &= ~(CAN_TEST_LBACK_Msk | CAN_TEST_SILENT_Msk | CAN_TEST_BASIC_Msk); + CANx->CR &= (~CAN_CR_TEST_Msk); +} + +/*********************************************************************************************************//** + * @brief Get the waiting status of a received message. + * @param CANx: The pointer to CAN module base address. + * @param MsgObj: Specifies the Message object number, from 0 to 31. 0 No message object has new data. + ***********************************************************************************************************/ +u32 CAN_IsNewDataReceived(HT_CAN_TypeDef *CANx, u32 MsgObj) +{ + MsgObj--; + return (MsgObj < 16 ? CANx->NDR0 & (1 << MsgObj) : CANx->NDR1 & (1 << (MsgObj - 16))); +} + +/*********************************************************************************************************//** + * @brief The function is used to Send CAN message in BASIC mode of test mode. Before call the API, + * the user should be call CAN_EnterTestMode(CAN_TEST_BASIC) and let CAN controller enter + * basic mode of test mode. Please notice IF0 Registers used as Tx Buffer in basic mode. + * @param CANx: The pointer to CAN module base address. + * @param pCanMsg: Pointer to the message structure containing data to transmit. + * @retval TRUE: Transmission OK, FALSE: Check busy flag of interface 0 is timeout + ***********************************************************************************************************/ +s32 CAN_BasicSendMsg(HT_CAN_TypeDef *CANx, STR_CANMSG_T_TypeDef* pCanMsg) +{ + u32 i = 0; + while(CANx->IF0.CREQ & CAN_IF_CREQ_BUSY_Msk); + + CANx->SR &= (~CAN_SR_TXOK_Msk); + + if(pCanMsg->IdType == CAN_STD_ID) + { + /* standard ID*/ + CANx->IF0.ARB0 = 0; + CANx->IF0.ARB1 = (((pCanMsg->Id) & 0x7FF) << 2) ; + } + else + { + /* extended ID*/ + CANx->IF0.ARB0 = (pCanMsg->Id) & 0xFFFF; + CANx->IF0.ARB1 = ((pCanMsg->Id) & 0x1FFF0000) >> 16 | CAN_IF_ARB1_XTD_Msk; + } + + if(pCanMsg->FrameType) + CANx->IF0.ARB1 |= CAN_IF_ARB1_DIR_Msk; + else + CANx->IF0.ARB1 &= (~CAN_IF_ARB1_DIR_Msk); + + CANx->IF0.MCR = (CANx->IF0.MCR & (~CAN_IF_MCR_DLC_Msk)) | pCanMsg->DLC; + CANx->IF0.DA0R = ((u16)pCanMsg->Data[1] << 8) | pCanMsg->Data[0]; + CANx->IF0.DA1R = ((u16)pCanMsg->Data[3] << 8) | pCanMsg->Data[2]; + CANx->IF0.DB0R = ((u16)pCanMsg->Data[5] << 8) | pCanMsg->Data[4]; + CANx->IF0.DB1R = ((u16)pCanMsg->Data[7] << 8) | pCanMsg->Data[6]; + + /* request transmission*/ + CANx->IF0.CREQ &= (~CAN_IF_CREQ_BUSY_Msk); + if(CANx->IF0.CREQ & CAN_IF_CREQ_BUSY_Msk) + { + return FALSE; + } + + CANx->IF0.CREQ |= CAN_IF_CREQ_BUSY_Msk; /* Sending */ + + for(i = 0; i < 0xFFFFF; i++) + { + if((CANx->IF0.CREQ & CAN_IF_CREQ_BUSY_Msk) == 0) + break; + } + + if(i >= 0xFFFFFFF) + { + return FALSE; + } + return TRUE; +} + +/*********************************************************************************************************//** + * @brief Get a message information in BASIC mode. + * @param CANx: The pointer to CAN module base address. + * @param pCanMsg: Pointer to the message structure where received data is copied. + * @retval FALSE: No any message received, TRUE: Receive a message success. + ***********************************************************************************************************/ +s32 CAN_BasicReceiveMsg(HT_CAN_TypeDef *CANx, STR_CANMSG_T_TypeDef* pCanMsg) +{ + if((CANx->IF1.MCR & CAN_IF_MCR_NEWDAT_Msk) == 0) /* In basic mode, receive data always save in IF1 */ + { + return FALSE; + } + + CANx->SR &= (~CAN_SR_RXOK_Msk); + + CANx->IF1.CMASK = CAN_IF_CMASK_ARB_Msk + | CAN_IF_CMASK_CONTROL_Msk + | CAN_IF_CMASK_DATAA_Msk + | CAN_IF_CMASK_DATAB_Msk; + + if((CANx->IF1.MASK1 & CAN_IF_ARB1_XTD_Msk) == 0) + { + /* standard ID*/ + pCanMsg->IdType = CAN_STD_ID; + pCanMsg->Id = (CANx->IF1.MASK1 >> 2) & 0x07FF; + } + else + { + /* extended ID*/ + pCanMsg->IdType = CAN_EXT_ID; + pCanMsg->Id = (CANx->IF1.ARB1 & 0x1FFF) << 16; + pCanMsg->Id |= (u32)CANx->IF1.ARB0; + } + + pCanMsg->FrameType = !((CANx->IF1.ARB1 & CAN_IF_ARB1_DIR_Msk) >> CAN_IF_ARB1_DIR_Pos); + + pCanMsg->DLC = CANx->IF1.MCR & CAN_IF_MCR_DLC_Msk; + pCanMsg->Data[0] = CANx->IF1.DA0R & CAN_IF_DAT_A0_DATA0_Msk; + pCanMsg->Data[1] = (CANx->IF1.DA0R & CAN_IF_DAT_A0_DATA1_Msk) >> CAN_IF_DAT_A0_DATA1_Pos; + pCanMsg->Data[2] = CANx->IF1.DA1R & CAN_IF_DAT_A1_DATA2_Msk; + pCanMsg->Data[3] = (CANx->IF1.DA1R & CAN_IF_DAT_A1_DATA3_Msk) >> CAN_IF_DAT_A1_DATA3_Pos; + pCanMsg->Data[4] = CANx->IF1.DB0R & CAN_IF_DAT_B0_DATA4_Msk; + pCanMsg->Data[5] = (CANx->IF1.DB0R & CAN_IF_DAT_B0_DATA5_Msk) >> CAN_IF_DAT_B0_DATA5_Pos; + pCanMsg->Data[6] = CANx->IF1.DB1R & CAN_IF_DAT_B1_DATA6_Msk; + pCanMsg->Data[7] = (CANx->IF1.DB1R & CAN_IF_DAT_B1_DATA7_Msk) >> CAN_IF_DAT_B1_DATA7_Pos; + + return TRUE; +} + +/*********************************************************************************************************//** + * @brief Set Rx message object + * @param CANx: The pointer to CAN module base address. + * @param MsgObj: Specifies the Message object number, from 0 to 31. + * @arg CAN_STD_ID (standard ID, 11-bit) + * @arg CAN_EXT_ID (extended ID, 29-bit) + * @param pCanMsg: Pointer to the message structure where received data is copied. + * @retval TRUE: SUCCESS, FALSE: No useful interface. + ***********************************************************************************************************/ +s32 CAN_SetRxMsgObj(HT_CAN_TypeDef *CANx, u32 MsgObj, STR_CANMSG_R_TypeDef* pCanMsg) +{ + u32 u8MsgIfNum = 0; + + if((u8MsgIfNum = GetFreeIF(CANx)) == 2) /* Check Free Interface for configure */ + { + return FALSE; + } + + if (u8MsgIfNum == 1) + { + /* Command Setting */ + CANx->IF1.CMASK = CAN_IF_CMASK_WRRD_Msk | CAN_IF_CMASK_MASK_Msk | CAN_IF_CMASK_ARB_Msk | + CAN_IF_CMASK_CONTROL_Msk | CAN_IF_CMASK_DATAA_Msk | CAN_IF_CMASK_DATAB_Msk; + + if(pCanMsg->IdType == CAN_STD_ID) /* According STD/EXT ID format,Configure Mask and Arbitration register */ + { + CANx->IF1.ARB0 = 0; + CANx->IF1.ARB1 = CAN_IF_ARB1_MSGVAL_Msk | (pCanMsg->Id & 0x7FF) << 2; + CANx->IF1.MASK0 = pCanMsg->MASK0; + CANx->IF1.MASK1 = pCanMsg->MASK1; + } + else + { + CANx->IF1.ARB0 = pCanMsg->Id & 0xFFFF; + CANx->IF1.ARB1 = CAN_IF_ARB1_MSGVAL_Msk | CAN_IF_ARB1_XTD_Msk | (pCanMsg->Id & 0x1FFF0000) >> 16; + } + + CANx->IF1.MCR |= CAN_IF_MCR_RXIE_Msk | pCanMsg->MCR ; + + if(pCanMsg->UMASK) + { + CANx->IF1.MCR |= CAN_IF_MCR_UMASK_Msk; + CANx->IF1.MASK0 = pCanMsg->MASK0; + CANx->IF1.MASK1 = pCanMsg->MASK1; + } + + if(pCanMsg->RMTEN) + CANx->IF1.MCR |= CAN_IF_MCR_RMTEN_Msk; + else + CANx->IF1.MCR &= (~CAN_IF_MCR_RMTEN_Msk); + + if(pCanMsg->EOB) + CANx->IF1.MCR |= CAN_IF_MCR_EOB_Msk; + else + CANx->IF1.MCR &= (~CAN_IF_MCR_EOB_Msk); + + CANx->IF1.MCR &= (~CAN_IF_MCR_INTPND_Msk); + CANx->IF1.MCR &= (~CAN_IF_MCR_NEWDAT_Msk); + CANx->IF1.DA0R = 0; + CANx->IF1.DA1R = 0; + CANx->IF1.DB0R = 0; + CANx->IF1.DB1R = 0; + CANx->IF1.CREQ = MsgObj+1; + } + else + { + /* Command Setting */ + CANx->IF0.CMASK = CAN_IF_CMASK_WRRD_Msk | CAN_IF_CMASK_MASK_Msk | CAN_IF_CMASK_ARB_Msk | + CAN_IF_CMASK_CONTROL_Msk | CAN_IF_CMASK_DATAA_Msk | CAN_IF_CMASK_DATAB_Msk; + + if(pCanMsg->IdType == CAN_STD_ID) /* According STD/EXT ID format,Configure Mask and Arbitration register */ + { + CANx->IF0.ARB0 = 0; + CANx->IF0.ARB1 = CAN_IF_ARB1_MSGVAL_Msk | (pCanMsg->Id & 0x7FF) << 2; + CANx->IF0.MASK0 = pCanMsg->MASK0; + CANx->IF0.MASK1 = pCanMsg->MASK1; + } + else + { + CANx->IF0.ARB0 = pCanMsg->Id & 0xFFFF; + CANx->IF0.ARB1 = CAN_IF_ARB1_MSGVAL_Msk | CAN_IF_ARB1_XTD_Msk | (pCanMsg->Id & 0x1FFF0000) >> 16; + } + + CANx->IF0.MCR |= CAN_IF_MCR_RXIE_Msk | pCanMsg->MCR ; + + if(pCanMsg->UMASK) + { + CANx->IF0.MCR |= CAN_IF_MCR_UMASK_Msk; + CANx->IF0.MASK0 = pCanMsg->MASK0; + CANx->IF0.MASK1 = pCanMsg->MASK1; + } + + if(pCanMsg->RMTEN) + CANx->IF0.MCR |= CAN_IF_MCR_RMTEN_Msk; + else + CANx->IF0.MCR &= (~CAN_IF_MCR_RMTEN_Msk); + + if(pCanMsg->EOB) + CANx->IF0.MCR |= CAN_IF_MCR_EOB_Msk; + else + CANx->IF0.MCR &= (~CAN_IF_MCR_EOB_Msk); + + CANx->IF0.MCR &= (~CAN_IF_MCR_INTPND_Msk); + CANx->IF0.MCR &= (~CAN_IF_MCR_NEWDAT_Msk); + CANx->IF0.DA0R = 0; + CANx->IF0.DA1R = 0; + CANx->IF0.DB0R = 0; + CANx->IF0.DB1R = 0; + CANx->IF0.CREQ = MsgObj+1; + } + return TRUE; +} + +/*********************************************************************************************************//** + * @brief Gets the message + * @param CANx: The pointer to CAN module base address. + * @param MsgObj: Specifies the Message object number, from 0 to 31. + * @param Release: Specifies the message release indicator. + * @arg TRUE : the message object is released when getting the data. + * @arg FALSE: the message object is not released. + * @param pCanMsg: Pointer to the message structure where received data is copied. + * @retval TRUE Success, FALSE No any message received + ***********************************************************************************************************/ +s32 CAN_ReadMsgObj(HT_CAN_TypeDef *CANx, u32 MsgObj, u32 Release, STR_CANMSG_T_TypeDef* pCanMsg) +{ + u32 u8MsgIfNum = 0; + + if(!CAN_IsNewDataReceived(CANx, MsgObj)) + { + return FALSE; + } + + if((u8MsgIfNum = GetFreeIF(CANx)) == 2) /* Check Free Interface for configure */ + { + return FALSE; + } + + CANx->SR &= (~CAN_SR_RXOK_Msk); + + if (u8MsgIfNum == 1) + { + /* read the message contents*/ + CANx->IF1.CMASK = CAN_IF_CMASK_MASK_Msk + | CAN_IF_CMASK_ARB_Msk + | CAN_IF_CMASK_CONTROL_Msk + | CAN_IF_CMASK_CLRINTPND_Msk + | (Release ? CAN_IF_CMASK_TXRQSTNEWDAT_Msk : 0) + | CAN_IF_CMASK_DATAA_Msk + | CAN_IF_CMASK_DATAB_Msk; + + CANx->IF1.CREQ = MsgObj; + + while(CANx->IF1.CREQ & CAN_IF_CREQ_BUSY_Msk) + { + /*Wait*/ + } + + if((CANx->IF1.ARB1 & CAN_IF_ARB1_XTD_Msk) == 0) + { + /* standard ID*/ + pCanMsg->IdType = CAN_STD_ID; + pCanMsg->Id = (CANx->IF1.ARB1 & CAN_IF_ARB1_ID_Msk) >> 2; + } + else + { + /* extended ID*/ + pCanMsg->IdType = CAN_EXT_ID; + pCanMsg->Id = (CANx->IF1.ARB1 & 0x1FFF) << 16 ; + pCanMsg->Id |= CANx->IF1.ARB0; + } + pCanMsg->MCR = CANx->IF1.MCR; + pCanMsg->DLC = CANx->IF1.MCR & CAN_IF_MCR_DLC_Msk; + pCanMsg->EOB = CANx->IF1.MCR & CAN_IF_MCR_EOB_Msk; + pCanMsg->Data[0] = CANx->IF1.DA0R & CAN_IF_DAT_A0_DATA0_Msk; + pCanMsg->Data[1] = (CANx->IF1.DA0R & CAN_IF_DAT_A0_DATA1_Msk) >> CAN_IF_DAT_A0_DATA1_Pos; + pCanMsg->Data[2] = CANx->IF1.DA1R & CAN_IF_DAT_A1_DATA2_Msk; + pCanMsg->Data[3] = (CANx->IF1.DA1R & CAN_IF_DAT_A1_DATA3_Msk) >> CAN_IF_DAT_A1_DATA3_Pos; + pCanMsg->Data[4] = CANx->IF1.DB0R & CAN_IF_DAT_B0_DATA4_Msk; + pCanMsg->Data[5] = (CANx->IF1.DB0R & CAN_IF_DAT_B0_DATA5_Msk) >> CAN_IF_DAT_B0_DATA5_Pos; + pCanMsg->Data[6] = CANx->IF1.DB1R & CAN_IF_DAT_B1_DATA6_Msk; + pCanMsg->Data[7] = (CANx->IF1.DB1R & CAN_IF_DAT_B1_DATA7_Msk) >> CAN_IF_DAT_B1_DATA7_Pos; + } + else + { + /* read the message contents*/ + CANx->IF0.CMASK = CAN_IF_CMASK_MASK_Msk + | CAN_IF_CMASK_ARB_Msk + | CAN_IF_CMASK_CONTROL_Msk + | CAN_IF_CMASK_CLRINTPND_Msk + | (Release ? CAN_IF_CMASK_TXRQSTNEWDAT_Msk : 0) + | CAN_IF_CMASK_DATAA_Msk + | CAN_IF_CMASK_DATAB_Msk; + + CANx->IF0.CREQ = MsgObj; + + while(CANx->IF0.CREQ & CAN_IF_CREQ_BUSY_Msk) + { + /*Wait*/ + } + + if((CANx->IF0.ARB1 & CAN_IF_ARB1_XTD_Msk) == 0) + { + /* standard ID*/ + pCanMsg->IdType = CAN_STD_ID; + pCanMsg->Id = (CANx->IF0.ARB1 & CAN_IF_ARB1_ID_Msk) >> 2; + } + else + { + /* extended ID*/ + pCanMsg->IdType = CAN_EXT_ID; + pCanMsg->Id = (CANx->IF0.ARB1 & 0x1FFF) << 16; + pCanMsg->Id |= CANx->IF0.ARB0; + } + + pCanMsg->MCR = CANx->IF0.MCR; + pCanMsg->DLC = CANx->IF0.MCR & CAN_IF_MCR_DLC_Msk; + pCanMsg->EOB = CANx->IF0.MCR & CAN_IF_MCR_EOB_Msk; + pCanMsg->Data[0] = CANx->IF0.DA0R & CAN_IF_DAT_A0_DATA0_Msk; + pCanMsg->Data[1] = (CANx->IF0.DA0R & CAN_IF_DAT_A0_DATA1_Msk) >> CAN_IF_DAT_A0_DATA1_Pos; + pCanMsg->Data[2] = CANx->IF0.DA1R & CAN_IF_DAT_A1_DATA2_Msk; + pCanMsg->Data[3] = (CANx->IF0.DA1R & CAN_IF_DAT_A1_DATA3_Msk) >> CAN_IF_DAT_A1_DATA3_Pos; + pCanMsg->Data[4] = CANx->IF0.DB0R & CAN_IF_DAT_B0_DATA4_Msk; + pCanMsg->Data[5] = (CANx->IF0.DB0R & CAN_IF_DAT_B0_DATA5_Msk) >> CAN_IF_DAT_B0_DATA5_Pos; + pCanMsg->Data[6] = CANx->IF0.DB1R & CAN_IF_DAT_B1_DATA6_Msk; + pCanMsg->Data[7] = (CANx->IF0.DB1R & CAN_IF_DAT_B1_DATA7_Msk) >> CAN_IF_DAT_B1_DATA7_Pos; + } + return TRUE; +} + +/*********************************************************************************************************//** + * @brief Set bus baud-rate. + * @param CANx: The pointer to CAN module base address. + * @param wBaudRate: The target CAN baud-rate. The range of u32BaudRate is 1~1000KHz. + * @retval CurrentBitRate: Real baud-rate value. + ***********************************************************************************************************/ +u32 CAN_SetBaudRate(HT_CAN_TypeDef *CANx, u32 wBaudRate) +{ + u32 wTseg0, wTseg1; + u32 wBrp; + u32 wValue; + + CAN_EnterInitMode(CANx); + + SystemCoreClockUpdate(); + + wTseg0 = 2; + wTseg1 = 1; + + wValue = SystemCoreClock / wBaudRate; + + while(1) + { + if(((wValue % (wTseg0 + wTseg1 + 3)) == 0)) + break; + if(wTseg1 < 7) + wTseg1++; + + if((wValue % (wTseg0 + wTseg1 + 3)) == 0) + break; + if(wTseg0 < 15) + wTseg0++; + else + { + wTseg0 = 2; + wTseg1 = 1; + break; + } + } + + wBrp = SystemCoreClock / (wBaudRate) / (wTseg0 + wTseg1 + 3) - 1; + + wValue = ((u32)wTseg1 << CAN_BTR_TSEG1_Pos) | ((u32)wTseg0 << CAN_BTR_TSEG0_Pos) | + (wBrp & CAN_BTR_BRP_Msk) | (CANx->BTR & CAN_BTR_SJW_Msk); + CANx->BTR = wValue; + CANx->BRPER = (wBrp >> 6) & 0x0F; + + CAN_LeaveInitMode(CANx); + + return (CAN_GetCANBitRate(CANx)); +} + +/*********************************************************************************************************//** + * @brief The function is used to disable all CAN interrupt. + * @param CANx: The pointer to CAN module base address. + * @retval None + ***********************************************************************************************************/ +void CAN_Close(HT_CAN_TypeDef *CANx) +{ + CAN_DisableInt(CANx, (CAN_CR_IE_Msk | CAN_CR_SIE_Msk | CAN_CR_EIE_Msk)); +} + +/*********************************************************************************************************//** + * @brief Set CAN operation mode and target baud-rate. + * @param CANx: The pointer to CAN module base address. + * @param wBaudRate The target CAN baud-rate. The range of u32BaudRate is 1~1000KHz. + * @param wMode The CAN operation mode. + * @arg CAN_NORMAL_MODE : Normal operation. + * @arg CAN_BASIC_MODE : Basic operation. + * @arg CAN_SILENT_MODE : Silent operation. + * @arg CAN_LBACK_MODE : Loop Back operation. + * @arg CAN_LBS_MODE : Loop Back combined with Silent operation. + * @retval u32CurrentBitRate Real baud-rate value. + ***********************************************************************************************************/ +u32 CAN_Open(HT_CAN_TypeDef *CANx, u32 wBaudRate, u32 wMode) +{ + u32 CurrentBitRate; + + CurrentBitRate = CAN_SetBaudRate(CANx, wBaudRate); + + if(wMode) + CAN_EnterTestMode(CANx, wMode); + + return CurrentBitRate; +} + +/*********************************************************************************************************//** + * @brief The function is used to configure a transmit object. + * @param CANx: The pointer to CAN module base address. + * @param MsgNum: Specifies the Message object number, from 0 to 31. + * @param pCanMsg: Pointer to the message structure where received data is copied. + * @retval FALSE No useful interface, TRUE Config message object success. + ***********************************************************************************************************/ +s32 CAN_SetTxMsg(HT_CAN_TypeDef *CANx, u32 MsgNum , STR_CANMSG_T_TypeDef* pCanMsg) +{ + u32 MsgIfNum = 0; + u32 i = 0; + + while((MsgIfNum = GetFreeIF(CANx)) == 2) + { + i++; + if(i > 0x10000000) + return FALSE; + } + + /* update the contents needed for transmission*/ + if(MsgIfNum ==0) + { + CANx->IF0.CMASK = 0xF3; /* CAN_CMASK_WRRD_Msk | CAN_CMASK_MASK_Msk | CAN_CMASK_ARB_Msk + | CAN_CMASK_CONTROL_Msk | CAN_CMASK_DATAA_Msk | CAN_CMASK_DATAB_Msk ; */ + + if(pCanMsg->IdType == CAN_STD_ID) + { + /* standard ID*/ + CANx->IF0.ARB0 = 0; + CANx->IF0.ARB1 = (((pCanMsg->Id) & 0x7FF) << 2) | CAN_IF_ARB1_DIR_Msk | CAN_IF_ARB1_MSGVAL_Msk; + } + else + { + /* extended ID*/ + CANx->IF0.ARB0 = (pCanMsg->Id) & 0xFFFF; + CANx->IF0.ARB1 = ((pCanMsg->Id) & 0x1FFF0000) >> 16 | CAN_IF_ARB1_DIR_Msk + | CAN_IF_ARB1_XTD_Msk | CAN_IF_ARB1_MSGVAL_Msk; + } + + if(pCanMsg->FrameType) + CANx->IF0.ARB1 |= CAN_IF_ARB1_DIR_Msk; + else + CANx->IF0.ARB1 &= (~CAN_IF_ARB1_DIR_Msk); + + CANx->IF0.DA0R = ((u16)pCanMsg->Data[1] << 8) | pCanMsg->Data[0]; + CANx->IF0.DA1R = ((u16)pCanMsg->Data[3] << 8) | pCanMsg->Data[2]; + CANx->IF0.DB0R = ((u16)pCanMsg->Data[5] << 8) | pCanMsg->Data[4]; + CANx->IF0.DB1R = ((u16)pCanMsg->Data[7] << 8) | pCanMsg->Data[6]; + CANx->IF0.MCR = 0; + if(pCanMsg->RMTEN) + CANx->IF0.MCR |= CAN_IF_MCR_RMTEN_Msk; + else + CANx->IF0.MCR &= (~CAN_IF_MCR_RMTEN_Msk); + if(pCanMsg->EOB) + CANx->IF0.MCR |= CAN_IF_MCR_EOB_Msk; + else + CANx->IF0.MCR &= (~CAN_IF_MCR_EOB_Msk); + + CANx->IF0.MCR |= CAN_IF_MCR_NEWDAT_Msk | pCanMsg->DLC | CAN_IF_MCR_TXIE_Msk ; + CANx->IF0.CREQ = MsgNum +1; + } + else + { + CANx->IF1.CMASK = 0xF3; /* CAN_CMASK_WRRD_Msk | CAN_CMASK_MASK_Msk | CAN_CMASK_ARB_Msk + | CAN_CMASK_CONTROL_Msk | CAN_CMASK_DATAA_Msk | CAN_CMASK_DATAB_Msk ; */ + + if(pCanMsg->IdType == CAN_STD_ID) + { + /* standard ID*/ + CANx->IF1.ARB0 = 0; + CANx->IF1.ARB1 = (((pCanMsg->Id) & 0x7FF) << 2) | CAN_IF_ARB1_DIR_Msk | CAN_IF_ARB1_MSGVAL_Msk; + } + else + { + /* extended ID*/ + CANx->IF1.ARB0 = (pCanMsg->Id) & 0xFFFF; + CANx->IF1.ARB1 = ((pCanMsg->Id) & 0x1FFF0000) >> 16 | CAN_IF_ARB1_DIR_Msk + | CAN_IF_ARB1_XTD_Msk | CAN_IF_ARB1_MSGVAL_Msk; + } + + if(pCanMsg->FrameType) + CANx->IF1.ARB1 |= CAN_IF_ARB1_DIR_Msk; + else + CANx->IF1.ARB1 &= (~CAN_IF_ARB1_DIR_Msk); + + CANx->IF1.DA0R = ((u16)pCanMsg->Data[1] << 8) | pCanMsg->Data[0]; + CANx->IF1.DA1R = ((u16)pCanMsg->Data[3] << 8) | pCanMsg->Data[2]; + CANx->IF1.DB0R = ((u16)pCanMsg->Data[5] << 8) | pCanMsg->Data[4]; + CANx->IF1.DB1R = ((u16)pCanMsg->Data[7] << 8) | pCanMsg->Data[6]; + + CANx->IF1.MCR = 0; + + if(pCanMsg->RMTEN) + CANx->IF1.MCR |= CAN_IF_MCR_RMTEN_Msk; + else + CANx->IF1.MCR &= (~CAN_IF_MCR_RMTEN_Msk); + + if(pCanMsg->EOB) + CANx->IF1.MCR |= CAN_IF_MCR_EOB_Msk; + else + CANx->IF1.MCR &= (~CAN_IF_MCR_EOB_Msk); + + CANx->IF1.MCR |= CAN_IF_MCR_NEWDAT_Msk | pCanMsg->DLC | CAN_IF_MCR_TXIE_Msk ; + CANx->IF1.CREQ = MsgNum +1; + } + return TRUE; +} + +/*********************************************************************************************************//** + * @brief Set transmit request bit. + * If a transmission is requested by programming bit TxRqst/NewDat (IFn_CMASK[2]), the TxRqst + * (IFn_MCON[8]) will be ignored. + * @param CANx: The pointer to CAN module base address. + * @param u32MsgNum: Specifies the Message object number, from 0 to 31. + * @retval TRUE: Start transmit message. + ***********************************************************************************************************/ +s32 CAN_TriggerTxMsg(HT_CAN_TypeDef *CANx, u32 u32MsgNum) +{ + CANx->SR &= (~CAN_SR_TXOK_Msk); + + /* read the message contents*/ + CANx->IF1.CMASK = CAN_IF_CMASK_CLRINTPND_Msk + | CAN_IF_CMASK_TXRQSTNEWDAT_Msk; + + CANx->IF1.CREQ = u32MsgNum+1; + + while(CANx->IF1.CREQ & CAN_IF_CREQ_BUSY_Msk) + { + /*Wait*/ + } + CANx->IF0.CMASK = CAN_IF_CMASK_WRRD_Msk | CAN_IF_CMASK_TXRQSTNEWDAT_Msk; + CANx->IF0.CREQ = u32MsgNum+1; + + return TRUE; +} + +/*********************************************************************************************************//** + * @brief Enable CAN interrupt. + * The application software has two possibilities to follow the source of a message interrupt. + * First, it can follow the IntId in the Interrupt Register and second it can poll the Interrupt Pending Register. + * @param CANx: The pointer to CAN module base address. + * @param u32Mask: Interrupt Mask. + * @arg CAN_CR_IE_Msk : Module interrupt enable. + * @arg CAN_CR_SIE_Msk: Status change interrupt enable. + * @arg CAN_CR_EIE_Msk: Error interrupt enable. + * @retval None + ***********************************************************************************************************/ +void CAN_EnableInt(HT_CAN_TypeDef *CANx, u32 u32Mask) +{ + CAN_EnterInitMode(CANx); + + CANx->CR = (CANx->CR & 0xF1) | ((u32Mask & CAN_CR_IE_Msk) ? CAN_CR_IE_Msk : 0) + | ((u32Mask & CAN_CR_SIE_Msk) ? CAN_CR_SIE_Msk : 0) + | ((u32Mask & CAN_CR_EIE_Msk) ? CAN_CR_EIE_Msk : 0); + + + CAN_LeaveInitMode(CANx); +} + +/*********************************************************************************************************//** + * @brief Disable CAN interrupt. + * @param CANx: The pointer to CAN module base address. + * @param Mask: Interrupt Mask. (CAN_CR_IE_Msk / CAN_CR_SIE_Msk / CAN_CR_EIE_Msk). + * @retval None + ***********************************************************************************************************/ +void CAN_DisableInt(HT_CAN_TypeDef *CANx, u32 Mask) +{ + CAN_EnterInitMode(CANx); + + CANx->CR = CANx->CR & ~(CAN_CR_IE_Msk | ((Mask & CAN_CR_SIE_Msk) ? CAN_CR_SIE_Msk : 0) + | ((Mask & CAN_CR_EIE_Msk) ? CAN_CR_EIE_Msk : 0)); + + CAN_LeaveInitMode(CANx); +} + + +/*********************************************************************************************************//** + * @brief The function is used to configure a receive message object. + * @param CANx: The pointer to CAN module base address. + * @param MsgNum: Specifies the Message object number, from 0 to 31. + * @param pCanMsg: Pointer to the message structure where received data is copied. + * @arg CAN_STD_ID: The 11-bit identifier. + * @arg CAN_EXT_ID: The 29-bit identifier. + * @retval FALSE No useful interface, TRUE Configure a receive message object success. + ***********************************************************************************************************/ +s32 CAN_SetRxMsg(HT_CAN_TypeDef *CANx, u32 MsgNum , STR_CANMSG_R_TypeDef* pCanMsg) +{ + u32 TimeOutCount = 0; + + while(CAN_SetRxMsgObj(CANx, MsgNum, pCanMsg) == FALSE) + { + TimeOutCount++; + + if(TimeOutCount >= 0x10000000) return FALSE; + } + + return TRUE; +} + +/*********************************************************************************************************//** + * @brief The function is used to configure several receive message objects. + * The Interface Registers avoid conflict between the CPU accesses to the Message RAM and CAN message + * reception and transmission by buffering the data to be transferred. + * @param CANx: The pointer to CAN module base address. + * @param MsgNum: The starting MSG RAM number(0 ~ 31). + * @param MsgCount: the number of MSG RAM of the FIFO. + * @param pCanMsg: Pointer to the message structure where received data is copied. + * @arg CAN_STD_ID: The 11-bit identifier. + * @arg CAN_EXT_ID: The 29-bit identifier. + * @retval FALSE No useful interface, TRUE Configure receive message objects success. + ***********************************************************************************************************/ +s32 CAN_SetMultiRxMsg(HT_CAN_TypeDef *CANx, u32 MsgNum , u32 MsgCount, STR_CANMSG_R_TypeDef* pCanMsg) +{ + u32 i = 0; + u32 TimeOutCount; + + for(i = 1; i < MsgCount+1; i++) + { + TimeOutCount = 0; + pCanMsg->EOB = 0; + + if(i == MsgCount) + pCanMsg->EOB=1; + + while(CAN_SetRxMsgObj(CANx, MsgNum, pCanMsg) == FALSE) + { + TimeOutCount++; + + if(TimeOutCount >= 0x10000000) + return FALSE; + } + MsgNum ++; + } + + return TRUE; +} + +/*********************************************************************************************************//** + * @brief Send CAN message. + * @param CANx: The pointer to CAN module base address. + * @param MsgNum: Specifies the Message object number, from 0 to 31. + * @param pCanMsg: Pointer to the message structure where received data is copied. + * @retval FALSE: 1. When operation in basic mode: Transmit message time out. + * 2. When operation in normal mode: No useful interface. + * TRUE: Transmit Message success. + ***********************************************************************************************************/ +s32 CAN_Transmit(HT_CAN_TypeDef *CANx, u32 MsgNum , STR_CANMSG_T_TypeDef* pCanMsg) +{ + if((CANx->CR & CAN_CR_TEST_Msk) && (CANx->TR & CAN_TEST_BASIC_Msk)) + { + return (CAN_BasicSendMsg(CANx, pCanMsg)); + } + else + { + if(CAN_SetTxMsg(CANx, MsgNum, pCanMsg) == FALSE) + return FALSE; + + CANx->SR &= (~CAN_SR_TXOK_Msk); + + /* read the message contents*/ + CANx->IF1.CMASK = CAN_IF_CMASK_CLRINTPND_Msk + | CAN_IF_CMASK_TXRQSTNEWDAT_Msk; + + CANx->IF1.CREQ = MsgNum+1; + + while(CANx->IF1.CREQ & CAN_IF_CREQ_BUSY_Msk) + { + /*Wait*/ + } + CANx->IF0.CMASK = CAN_IF_CMASK_WRRD_Msk | CAN_IF_CMASK_TXRQSTNEWDAT_Msk; + CANx->IF0.CREQ = MsgNum+1; + } + + return TRUE; +} + +/*********************************************************************************************************//** + * @brief Gets the message, if received. + * The Interface Registers avoid conflict between the CPU accesses to the Message RAM and CAN message + * reception and transmission by buffering the data to be transferred. + * @param CANx: The pointer to CAN module base address. + * @param MsgNum: Specifies the Message object number, from 0 to 31. + * @param pCanMsg: Pointer to the message structure where received data is copied. + * @retval FALSE: No any message received, TRUE: Receive Message success. + ***********************************************************************************************************/ +s32 CAN_Receive(HT_CAN_TypeDef *CANx, u32 MsgNum , STR_CANMSG_T_TypeDef* pCanMsg) +{ + if((CANx->CR & CAN_CR_TEST_Msk) && (CANx->TR & CAN_TEST_BASIC_Msk)) + { + return (CAN_BasicReceiveMsg(CANx, pCanMsg)); + } + else + { + return CAN_ReadMsgObj(CANx, MsgNum, TRUE, pCanMsg); + } +} + +/*********************************************************************************************************//** + * @brief Clear interrupt pending bit. + * @param CANx: The pointer to CAN module base address. + * @param MsgNum: Specifies the Message object number, from 0 to 31. + * @retval None + ***********************************************************************************************************/ +void CAN_CLR_INT_PENDING_BIT(HT_CAN_TypeDef *CANx, u32 MsgNum) +{ + u32 u32IFBusyCount = 0; + + while(u32IFBusyCount < 0x10000000) + { + if((CANx->IF0.CREQ & CAN_IF_CREQ_BUSY_Msk) == 0) + { + CANx->IF0.CMASK = CAN_IF_CMASK_CLRINTPND_Msk | CAN_IF_CMASK_TXRQSTNEWDAT_Msk; + CANx->IF0.CREQ = MsgNum+1; + break; + } + else if((CANx->IF1.CREQ & CAN_IF_CREQ_BUSY_Msk) == 0) + { + CANx->IF1.CMASK = CAN_IF_CMASK_CLRINTPND_Msk | CAN_IF_CMASK_TXRQSTNEWDAT_Msk; + CANx->IF1.CREQ = MsgNum+1; + break; + } + + u32IFBusyCount++; + } +} + +/*********************************************************************************************************//** + * @brief The function is used to configure Mask as the message object. + * @param CANx: The pointer to CAN module base address. + * @param MsgObj: Specifies the Message object number, from 0 to 31. + * @param MaskMsg: Pointer to the message structure where received data is copied. + * @arg CAN_STD_ID: The 11-bit identifier. + * @arg CAN_EXT_ID: The 29-bit identifier. + * @retval FALSE No useful interface, TRUE Configure a receive message object success. + ***********************************************************************************************************/ +s32 CAN_MsgObjMaskConfig(HT_CAN_TypeDef *CANx, u32 MsgObj, STR_CANMSG_R_TypeDef* MaskMsg) +{ + if(MaskMsg->IdType == CAN_STD_ID) + { + /* standard ID*/ + CANx->IF0.ARB0 = 0; + CANx->IF0.ARB1 = (((MaskMsg->Id) & 0x7FF) << 2) | CAN_IF_ARB1_MSGVAL_Msk ; + + /* Set the Mask Standard ID(11-bit) for IFn Mask Register is used for acceptance filtering*/ + CANx->IF0.MASK0 = 0; + CANx->IF0.MASK1 = ((MaskMsg->Id & 0x7FF) << 2) ; + } + else + { + /* extended ID*/ + CANx->IF0.ARB0 = (MaskMsg->Id) & 0xFFFF; + CANx->IF0.ARB1 = ((MaskMsg->Id) & 0x1FFF0000) >> 16 | CAN_IF_ARB1_DIR_Msk + | CAN_IF_ARB1_XTD_Msk | CAN_IF_ARB1_MSGVAL_Msk; + /* Set the Mask Extended ID(29-bit) for IFn Mask Register is used for acceptance filtering*/ + CANx->IF0.MASK0 = (MaskMsg->Id) & 0xFFFF; + CANx->IF0.MASK1 = ((MaskMsg->Id) & 0x1FFF0000) >> 16 ; + } + + if(MaskMsg->u8Xtd) + CANx->IF0.MASK1 |= CAN_IF_MASK1_MXTD_Msk; /* The extended identifier bit (IDE) is used for acceptance filtering */ + else + CANx->IF0.MASK1 &= (~CAN_IF_MASK1_MXTD_Msk); /* The extended identifier bit (IDE) has no effect on the acceptance filtering */ + + if(MaskMsg->u8Dir) + CANx->IF0.MASK1 |= CAN_IF_MASK1_MDIR_Msk; /* The message direction bit (Dir) is used for acceptance filtering */ + else + CANx->IF0.MASK1 &= (~CAN_IF_MASK1_MDIR_Msk); /* The message direction bit (Dir) has no effect on the acceptance filtering */ + + CANx->IF0.MCR |= CAN_IF_MCR_UMASK_Msk; /* Use Mask (Msk28-0, MXtd, and MDir) for acceptance filtering */ + + /* Update the contents needed for transmission*/ + CANx->IF0.CMASK = CAN_IF_CMASK_WRRD_Msk /* Transfer data from the selected Message Buffer Registers to the Message Object addressed */ + | CAN_IF_CMASK_MASK_Msk; /* Transfer Identifier Mask + MDir + MXtd to Message Object */ + + CANx->IF0.DA0R = 0; + CANx->IF0.DA1R = 0; + CANx->IF0.DB0R = 0; + CANx->IF0.DB1R = 0; + + /* Set the Message Object in the Message RAM is selected for data transfer */ + CANx->IF0.CREQ = 1 + MsgObj; + + return TRUE; +} + +/* Private functions ----------------------------------------------------------------------------------------*/ +/** @defgroup CAN_Private_Functions CAN private functions + * @{ + */ +/*********************************************************************************************************//** + * @brief Check if SmartCard slot is presented. + * @param CANx: The pointer to CAN module base address. +* @retval Free IF number. IF0_NUM or IF1_NUM or IF_TOTAL_NUM (No IF is free) + ***********************************************************************************************************/ +static CANIF_NUMBER_Enum GetFreeIF(HT_CAN_TypeDef *CANx) +{ + if((CANx->IF0.CREQ & CAN_IF_CREQ_BUSY_Msk) == 0) + return IF0_NUM; + else if((CANx->IF1.CREQ & CAN_IF_CREQ_BUSY_Msk) == 0) + return IF1_NUM; + else + return IF_TOTAL_NUM; +} +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/ht32f5xxxx_ckcu.c b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/ht32f5xxxx_ckcu.c new file mode 100644 index 0000000000..9238830a04 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/ht32f5xxxx_ckcu.c @@ -0,0 +1,1105 @@ +/*********************************************************************************************************//** + * @file ht32f5xxxx_ckcu.c + * @version $Rev:: 7322 $ + * @date $Date:: 2023-10-28 #$ + * @brief This file provides all the Clock Control Unit firmware functions. + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ + +/* Includes ------------------------------------------------------------------------------------------------*/ +#include "ht32f5xxxx_ckcu.h" + +/** @addtogroup HT32F5xxxx_Peripheral_Driver HT32F5xxxx Peripheral Driver + * @{ + */ + +/** @defgroup CKCU CKCU + * @brief CKCU driver modules + * @{ + */ + + +/* Private constants ---------------------------------------------------------------------------------------*/ +/** @defgroup CKCU_Private_Define CKCU private definitions + * @{ + */ + +/* GCFGR bit field definition */ +#define CKCU_POS_CKOUTSRC 0 +#define CKCU_MASK_CKOUTSRC ((u32)0x7 << CKCU_POS_CKOUTSRC) + +#define CKCU_POS_PLLSRC 8 +#define CKCU_MASK_PLLSRC ((u32)0x1 << CKCU_POS_PLLSRC) + +#if (LIBCFG_CKCU_USB_PLL) +#define CKCU_POS_USBPLLSRC 9 +#define CKCU_MASK_USBPLLSRC ((u32)0x1 << CKCU_POS_USBPLLSRC) + +#define CKCU_POS_USBSRC 10 +#define CKCU_MASK_USBSRC ((u32)0x1 << CKCU_POS_USBSRC) +#endif + +#define CKCU_POS_CKREFPRE 11 +#define CKCU_MASK_CKREFPRE ((u32)0x1F << CKCU_POS_CKREFPRE) + +/* GCCR bit field definition */ +#define CKCU_POS_SW 0 +#define CKCU_MASK_SW ((u32)0x7 << CKCU_POS_SW) + +#if (LIBCFG_CKCU_USB_PLL) +#define CKCU_POS_USBPLLEN 3 +#define CKCU_MASK_USBPLLEN ((u32)0x1 << CKCU_POS_USBPLLEN) +#endif + +#define CKCU_POS_PLLEN 9 +#define CKCU_MASK_PLLEN ((u32)0x1 << CKCU_POS_PLLEN) + +#define CKCU_POS_HSEEN 10 +#define CKCU_MASK_HSEEN ((u32)0x1 << CKCU_POS_HSEEN) + +#define CKCU_POS_HSIEN 11 +#define CKCU_MASK_HSIEN ((u32)0x1 << CKCU_POS_HSIEN) + +#define CKCU_POS_CKMEN 16 +#define CKCU_MASK_CKMEN ((u32)0x1 << CKCU_POS_CKMEN) + +#define CKCU_POS_PSRCEN 17 +#define CKCU_MASK_PSRCEN ((u32)0x1 << CKCU_POS_PSRCEN) + +/* PLLCFGR bit field definition */ +#define CKCU_POS_POTD 21 +#define CKCU_MASK_POTD ((u32)0x3 << CKCU_POS_POTD) + +#define CKCU_POS_PFBD 23 +#define CKCU_MASK_PFBD ((u32)0x0F << CKCU_POS_PFBD) + +/* PLLCR bit field definition */ +#define CKCU_POS_PLLBYPASS 31 +#define CKCU_MASK_PLLBYPASS ((u32)0x1 << CKCU_POS_PLLBYPASS) + +/* APBCFGR bit field definition */ +#define CKCU_POS_ADC0DIV 16 +#define CKCU_MASK_ADC0DIV ((u32)0x7 << CKCU_POS_ADC0DIV) + +#if (LIBCFG_ADC1) +#define CKCU_POS_ADC1DIV 20 +#define CKCU_MASK_ADC1DIV ((u32)0x7 << CKCU_POS_ADC1DIV) +#endif + +#if (LIBCFG_CKCU_LCD_SRC) +#define CKCU_POS_LCDSRC 4 +#define CKCU_MASK_LCDSRC ((u32)0x3 << CKCU_POS_LCDSRC) +#endif + +#if (LIBCFG_LCD) +#define CKCU_POS_LCDDIV 8 +#define CKCU_MASK_LCDDIV ((u32)0x7 << CKCU_POS_LCDDIV) +#endif + +#if (LIBCFG_CKCU_MCTM_SRC) +#define CKCU_POS_MCTMCSEL 8 +#define CKCU_MASK_MCTMCSEL ((u32)0x1 << CKCU_POS_MCTMCSEL) +#endif + +#if (LIBCFG_MIDI) +#define CKCU_POS_MIDIDIV 24 +#define CKCU_MASK_MIDIDIV ((u32)0x7 << CKCU_POS_MIDIDIV) +#endif + +/* CKST bit field definition */ +#define CKCU_POS_PLLST 8 +#define CKCU_MASK_PLLST ((u32)0xF << CKCU_POS_PLLST) + +#define CKCU_POS_HSEST 16 +#define CKCU_MASK_HSEST ((u32)0x3 << CKCU_POS_HSEST) + +#define CKCU_POS_HSIST 24 +#define CKCU_MASK_HSIST ((u32)0x7 << CKCU_POS_HSIST) + +#define CKCU_POS_CKSWST 0 +#define CKCU_MASK_CKSWST ((u32)0x7 << CKCU_POS_CKSWST) + +/* LPCR bit field definition */ +#define CKCU_POS_BKISO 0 +#define CKCU_MASK_BKISO ((u32)0x1 << CKCU_POS_BKISO) + +/* HSICR bit field definition */ +#define CKCU_POS_TRIMEN (0) +#define CKCU_MASK_TRIMEN ((u32)0x1 << CKCU_POS_TRIMEN) + +#define CKCU_POS_ATCEN (1) +#define CKCU_MASK_ATCEN ((u32)0x1 << CKCU_POS_ATCEN) + +#define CKCU_POS_REFCLKSEL (5) +#define CKCU_MASK_REFCLKSEL ((u32)0x3 << CKCU_POS_REFCLKSEL) + +/** + * @} + */ + +/* Private macro -------------------------------------------------------------------------------------------*/ +/** @defgroup CKCU_Private_Macro CKCU private macros + * @{ + */ +#define CKCU_BF_WRITE(Reg, Mask, Pos, WriteValue) (Reg = ((Reg & ~((u32)Mask)) | ((u32)WriteValue << Pos))) +#define CKCU_BF_READ(Reg, Mask, Pos) ((Reg & (u32)Mask) >> Pos) +/** + * @} + */ + +/* Global functions ----------------------------------------------------------------------------------------*/ +/** @addtogroup CKCU_Exported_Functions CKCU exported functions + * @{ + */ +/*********************************************************************************************************//** + * @brief Deinitialize the CKCU registers to the reset values. + * @retval None + ************************************************************************************************************/ +void CKCU_DeInit(void) +{ + /* Reset system clock */ + CKCU_HSICmd(ENABLE); + while (CKCU_GetClockReadyStatus(CKCU_FLAG_HSIRDY) == RESET); + CKCU_SysClockConfig(CKCU_SW_HSI); + + #if (LIBCFG_CKCU_USB_PLL) + HT_CKCU->GCFGR = 0x00000302; /* Reset value of GCFGR */ + #else + HT_CKCU->GCFGR = 0x00000102; /* Reset value of GCFGR */ + #endif + HT_CKCU->GCCR = 0x00000803; /* Reset value of GCCR */ + HT_CKCU->GCIR = 0x000000FF; /* Clear all interrupt flags */ + + #if (!LIBCFG_NO_PLL) + HT_CKCU->PLLCR = 0; /* Reset value of PLLCR */ + #endif + HT_CKCU->AHBCFGR = 0; /* Reset value of AHBCFGR */ + HT_CKCU->AHBCCR = 0x00000065; /* Reset value of AHBCCR */ + #if (!LIBCFG_NO_ADC) + HT_CKCU->APBCFGR = 0x00010000; /* Reset value of APBCFGR */ + #endif + HT_CKCU->APBCCR0 = 0; /* Reset value of APBCCR0 */ + HT_CKCU->APBCCR1 = 0; /* Reset value of APBCCR1 */ + #if (!LIBCFG_CKCU_NO_APB_PRESCALER) + HT_CKCU->APBPCSR0 = 0; /* Reset value of APBPCSR0 */ + HT_CKCU->APBPCSR1 = 0; /* Reset value of APBPCSR1 */ + #endif + #if (!LIBCFG_CKCU_NO_AUTO_TRIM) + HT_CKCU->HSICR = 0; /* Reset value of HSICR */ + #endif + #if ((!LIBCFG_CKCU_NO_APB_PRESCALER) && (LIBCFG_PWM0 || LIBCFG_PWM1 || LIBCFG_MIDI || LIBCFG_DAC0 || LIBCFG_DAC1 || LIBCFG_DACDUAL16 || LIBCFG_LCD || LIBCFG_LEDC || LIBCFG_TKEY)) + HT_CKCU->APBPCSR2 = 0; /* Reset value of APBPCSR2 */ + #endif + #if (LIBCFG_CKCU_HSIRDYCR) + HT_CKCU->HSIRDYCR = 0; /* Reset value of HSIRDYCR */ + #endif + #if (!LIBCFG_CKCU_NO_LPCR) + HT_CKCU->LPCR = 0; /* Reset value of LPCR */ + #endif + HT_CKCU->MCUDBGCR = 0; /* Reset value of MCUDBGCR */ +} + +/*********************************************************************************************************//** + * @brief Enable or Disable the external high speed oscillator (HSE). + * @note HSE can not be stopped if it is used by system clock or PLL. + * @param Cmd: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void CKCU_HSECmd(ControlStatus Cmd) +{ + /* Check the parameters */ + Assert_Param(IS_CONTROL_STATUS(Cmd)); + + CKCU_BF_WRITE(HT_CKCU->GCCR, CKCU_MASK_HSEEN, CKCU_POS_HSEEN, Cmd); +} + +/*********************************************************************************************************//** + * @brief Enable or Disable the internal high speed oscillator (HSI). + * @note HSI can not be stopped if it is used by system clock or PLL. + * @param Cmd: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void CKCU_HSICmd(ControlStatus Cmd) +{ + /* Check the parameters */ + Assert_Param(IS_CONTROL_STATUS(Cmd)); + + CKCU_BF_WRITE(HT_CKCU->GCCR, CKCU_MASK_HSIEN, CKCU_POS_HSIEN, Cmd); +} + +#if (!LIBCFG_NO_PLL) +/*********************************************************************************************************//** + * @brief Enable or Disable the PLL clock. + * @note PLL can not be stopped if it is used by system clock or CK_REF. + * @param Cmd: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void CKCU_PLLCmd(ControlStatus Cmd) +{ + /* Check the parameters */ + Assert_Param(IS_CONTROL_STATUS(Cmd)); + + CKCU_BF_WRITE(HT_CKCU->GCCR, CKCU_MASK_PLLEN, CKCU_POS_PLLEN, Cmd); +} +#endif + +#if (LIBCFG_CKCU_USB_PLL) +/*********************************************************************************************************//** + * @brief Enable or Disable the USBPLL clock. + * @param Cmd: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void CKCU_USBPLLCmd(ControlStatus Cmd) +{ + /* Check the parameters */ + Assert_Param(IS_CONTROL_STATUS(Cmd)); + + CKCU_BF_WRITE(HT_CKCU->GCCR, CKCU_MASK_USBPLLEN, CKCU_POS_USBPLLEN, Cmd); +} +#endif + +/*********************************************************************************************************//** + * @brief Wait for HSE is ready to be used. + * @retval SUCCESS or ERROR + ************************************************************************************************************/ +ErrStatus CKCU_WaitHSEReady(void) +{ + u32 ReadyCnt = 0; + + /* Wait until HSE is ready or time-out occurred */ + while (CKCU_GetClockReadyStatus(CKCU_FLAG_HSERDY) != SET) + { + if (++ReadyCnt >= HSE_READY_TIME) + { + return ERROR; + } + } + + return SUCCESS; +} + +/*********************************************************************************************************//** + * @brief Check whether the specific clock ready flag is set or not. + * @param CKCU_FLAG: specify the clock ready flag. + * This parameter can be one of the following values: + * @arg CKCU_FLAG_USBPLLRDY : USB PLL ready flag + * @arg CKCU_FLAG_PLLRDY : PLL ready flag + * @arg CKCU_FLAG_HSERDY : HSE ready flag + * @arg CKCU_FLAG_HSIRDY : HSI ready flag + * @arg CKCU_FLAG_LSERDY : LSE ready flag + * @arg CKCU_FLAG_LSIRDY : LSI ready flag + * @retval SET or RESET + ************************************************************************************************************/ +FlagStatus CKCU_GetClockReadyStatus(u32 CKCU_FLAG) +{ + /* Check the parameters */ + Assert_Param(IS_CKCU_FLAG(CKCU_FLAG)); + + if (HT_CKCU->GCSR & CKCU_FLAG) + { + return SET; + } + else + { + return RESET; + } +} + +#if (!LIBCFG_NO_PLL) +/*********************************************************************************************************//** + * @brief This function is used to configure PLL. + * @param PLL_InitStruct: pointer to CKCU_PLLInitTypeDef structure. + * @retval None + ************************************************************************************************************/ +void CKCU_PLLInit(CKCU_PLLInitTypeDef *PLL_InitStruct) +{ + /* Check the parameters */ + Assert_Param(IS_PLL_CLKSRC(PLL_InitStruct->ClockSource)); + Assert_Param(IS_CONTROL_STATUS(PLL_InitStruct->BYPASSCmd)); + Assert_Param(IS_PLL_CFG(PLL_InitStruct->CFG)); + + CKCU_BF_WRITE(HT_CKCU->GCFGR, CKCU_MASK_PLLSRC, CKCU_POS_PLLSRC, PLL_InitStruct->ClockSource); + CKCU_BF_WRITE(HT_CKCU->PLLCR, CKCU_MASK_PLLBYPASS, CKCU_POS_PLLBYPASS, PLL_InitStruct->BYPASSCmd); + HT_CKCU->PLLCFGR = (HT_CKCU->PLLCFGR & 0x0000FFFF) | PLL_InitStruct->CFG; +} +#endif + +#if (LIBCFG_CKCU_USB_PLL) +/*********************************************************************************************************//** + * @brief This function is used to configure USBPLL. + * @param USBPLL_InitStruct: pointer to CKCU_PLLInitTypeDef structure. + * @retval None + ************************************************************************************************************/ +void CKCU_USBPLLInit(CKCU_PLLInitTypeDef *USBPLL_InitStruct) +{ + /* Check the parameters */ + Assert_Param(IS_PLL_CLKSRC(USBPLL_InitStruct->ClockSource)); + Assert_Param(IS_USBPLL_CFG(USBPLL_InitStruct->CFG)); + + CKCU_BF_WRITE(HT_CKCU->GCFGR, CKCU_MASK_USBPLLSRC, CKCU_POS_USBPLLSRC, USBPLL_InitStruct->ClockSource); + HT_CKCU->PLLCFGR = (HT_CKCU->PLLCFGR & 0xFFFF0000) | USBPLL_InitStruct->CFG; +} + +/*********************************************************************************************************//** + * @brief Configure the CK_USB clock source. + * @param USBSRC: specify the USB clock source. + * This parameter can be one of the following values: + * @arg CKCU_CKPLL : CK_USB = CK_PLL + * @arg CKCU_CKUSBPLL : CK_USB = CK_USBPLL + * @retval None + ************************************************************************************************************/ +void CKCU_USBClockConfig(CKCU_USBSRC_TypeDef USBSRC) +{ + CKCU_BF_WRITE(HT_CKCU->GCFGR, CKCU_MASK_USBSRC, CKCU_POS_USBSRC, USBSRC); +} +#endif + +#if (LIBCFG_CKCU_LCD_SRC) +/*********************************************************************************************************//** + * @brief Configure LCD clock source. + * @param LCDSRC: Specify LCD clock source. + * This parameter can be one of the following values: + * @arg CKCU_LCDSRC_LSI : + * @arg CKCU_LCDSRC_LSE : + * @arg CKCU_LCDSRC_HSI : + * @arg CKCU_LCDSRC_HSE : + * @retval None + ************************************************************************************************************/ +void CKCU_LCDClockConfig(CKCU_LCDSRC_TypeDef LCDSRC) +{ + CKCU_BF_WRITE(HT_CKCU->GCFGR, CKCU_MASK_LCDSRC, CKCU_POS_LCDSRC, LCDSRC); +} +#endif + +#if (LIBCFG_CKCU_MCTM_SRC) +/*********************************************************************************************************//** + * @brief Configure the MCTM clock source. + * @param CKCU_MCTMSRC_x: specify the MCTM clock source. + * This parameter can be one of the following values: + * @arg CKCU_MCTMSRC_AHB : CK_MCTM = CK_AHB + * @arg CKCU_MCTMSRC_USBPLL : CK_MCTM = CK_USBPLL + * @retval None + ************************************************************************************************************/ +void CKCU_MCTMClockConfig(CKCU_MCTMSRC_TypeDef CKCU_MCTMSRC_x) +{ + Assert_Param(IS_MCTM_SRC(CKCU_MCTMSRC_x)); + CKCU_BF_WRITE(HT_CKCU->APBCFGR, CKCU_MASK_MCTMCSEL, CKCU_POS_MCTMCSEL, CKCU_MCTMSRC_x); +} +#endif + +/*********************************************************************************************************//** + * @brief Configure the CK_SYS source. + * @param CLKSRC: specify the system clock source. + * This parameter can be one of the following values: + * @arg CKCU_SW_PLL : PLL is selected as CK_SYS + * @arg CKCU_SW_HSE : HSE is selected as CK_SYS + * @arg CKCU_SW_HSI : HSI is selected as CK_SYS + * @arg CKCU_SW_LSE : LSE is selected as CK_SYS + * @arg CKCU_SW_LSI : LSI is selected as CK_SYS + * @retval None + ************************************************************************************************************/ +ErrStatus CKCU_SysClockConfig(CKCU_SW_TypeDef CLKSRC) +{ + u32 cnt = 0xFF; + + CKCU_BF_WRITE(HT_CKCU->GCCR, CKCU_MASK_SW, CKCU_POS_SW, CLKSRC); + + /* Wait until new system clock source is applied or time-out */ + while (--cnt) + { + if (CKCU_GetSysClockSource() == (u32)CLKSRC) + { + return SUCCESS; + } + } + + return ERROR; +} + +/*********************************************************************************************************//** + * @brief Return the source clock which is used as system clock. + * @retval The source clock used as system clock. + * 0x01: PLL is selected as system clock + * 0x02: HSE is selected as system clock + * 0x03: HSI is selected as system clock + * 0x06: LSE is selected as system clock + * 0x07: LSI is selected as system clock + ************************************************************************************************************/ +u32 CKCU_GetSysClockSource(void) +{ + return ((u32)CKCU_BF_READ(HT_CKCU->CKST, CKCU_MASK_CKSWST, CKCU_POS_CKSWST)); +} + +/*********************************************************************************************************//** + * @brief Configure the CK_AHB prescaler. + * @param HCLKPRE: specify the value of divider. + * This parameter can be one of the following values: + * @arg CKCU_SYSCLK_DIV1 : HCLK = CK_SYS + * @arg CKCU_SYSCLK_DIV2 : HCLK = CK_SYS / 2 + * @arg CKCU_SYSCLK_DIV4 : HCLK = CK_SYS / 4 + * @arg CKCU_SYSCLK_DIV8 : HCLK = CK_SYS / 8 + * @arg CKCU_SYSCLK_DIV16 : HCLK = CK_SYS / 16 + * @arg CKCU_SYSCLK_DIV32 : HCLK = CK_SYS / 32 + * @retval None + ************************************************************************************************************/ +void CKCU_SetHCLKPrescaler(CKCU_SYSCLKDIV_TypeDef HCLKPRE) +{ + HT_CKCU->AHBCFGR = HCLKPRE; +} + +/*********************************************************************************************************//** + * @brief Configure the CK_REF prescaler. + * @param CKREFPRE: specify the value of divider. + * This parameter can be: CKCU_CKREFPRE_DIV2 to CKCU_CKREFPRE_DIV64 (CK_REF = CK_PLL / (2 * (N + 1)), N = 0 ~ 31) + * @retval None + ************************************************************************************************************/ +void CKCU_SetCKREFPrescaler(CKCU_CKREFPRE_TypeDef CKREFPRE) +{ + CKCU_BF_WRITE(HT_CKCU->GCFGR, CKCU_MASK_CKREFPRE, CKCU_POS_CKREFPRE, CKREFPRE); +} + +#if (!LIBCFG_NO_ADC) +/*********************************************************************************************************//** + * @brief Configure the CK_ADCn prescaler. + * @param CKCU_ADCPRE_ADCn: specify the ADCn. + * @param CKCU_ADCPRE_DIVn: specify the prescaler value. + * This parameter can be one of the following values: + * @arg CKCU_ADCPRE_DIV1 : CK_ADC = HCLK / 1 + * @arg CKCU_ADCPRE_DIV2 : CK_ADC = HCLK / 2 + * @arg CKCU_ADCPRE_DIV3 : CK_ADC = HCLK / 3 + * @arg CKCU_ADCPRE_DIV4 : CK_ADC = HCLK / 4 + * @arg CKCU_ADCPRE_DIV8 : CK_ADC = HCLK / 8 + * @arg CKCU_ADCPRE_DIV16 : CK_ADC = HCLK / 16 + * @arg CKCU_ADCPRE_DIV32 : CK_ADC = HCLK / 32 + * @arg CKCU_ADCPRE_DIV64 : CK_ADC = HCLK / 64 + * @retval None + ************************************************************************************************************/ +void CKCU_SetADCnPrescaler(CKCU_ADCPRE_ADCn_TypeDef CKCU_ADCPRE_ADCn, CKCU_ADCPRE_TypeDef CKCU_ADCPRE_DIVn) +{ + HT_CKCU->APBCFGR = (HT_CKCU->APBCFGR & (~(0x07 << CKCU_ADCPRE_ADCn))) | (CKCU_ADCPRE_DIVn << CKCU_ADCPRE_ADCn); +} +#endif + +#if (LIBCFG_LCD) +/*********************************************************************************************************//** + * @brief Configure LCD clock prescaler. + * @param LCDCPS: Specify LCD clock prescaler. + * This parameter can be one of the following values: + * @arg CKCU_LCDPRE_DIV1 : + * @arg CKCU_LCDPRE_DIV2 : + * @arg CKCU_LCDPRE_DIV4 : + * @arg CKCU_LCDPRE_DIV8 : + * @arg CKCU_LCDPRE_DIV16 : + * @retval None + ************************************************************************************************************/ +void CKCU_SetLCDPrescaler(CKCU_LCDPRE_TypeDef LCDPRE) +{ + CKCU_BF_WRITE(HT_CKCU->APBCFGR, CKCU_MASK_LCDDIV, CKCU_POS_LCDDIV, LCDPRE); +} +#endif + +#if (LIBCFG_MIDI) +/*********************************************************************************************************//** + * @brief Configure the CK_MIDI prescaler. + * @param MIDIPRE: specify the value of divider. + * This parameter can be: + * @arg CKCU_MIDIPRE_DIV8 : CK_MIDI = HCLK / 8 + * @arg CKCU_MIDIPRE_DIV9 : CK_MIDI = HCLK / 9 + * @arg CKCU_MIDIPRE_DIV11 : CK_MIDI = HCLK / 11 + * @arg CKCU_MIDIPRE_DIV13 : CK_MIDI = HCLK / 13 + * @arg CKCU_MIDIPRE_DIV16 : CK_MIDI = HCLK / 16 + * @retval None + ************************************************************************************************************/ +void CKCU_SetMIDIPrescaler(CKCU_MIDIPRE_TypeDef MIDIPRE) +{ + CKCU_BF_WRITE(HT_CKCU->APBCFGR, CKCU_MASK_MIDIDIV, CKCU_POS_MIDIDIV, MIDIPRE); +} +#endif + +/*********************************************************************************************************//** + * @brief Return the frequency of the different clocks. + * @param CKCU_Clk: pointer to CKCU_ClocksTypeDef structure to get the clocks frequency. + * @retval None + ************************************************************************************************************/ +void CKCU_GetClocksFrequency(CKCU_ClocksTypeDef* CKCU_Clk) +{ + u32 div; + u32 SystemCoreClockSrc = (HT_CKCU->CKST) & 7UL; +#if (!LIBCFG_NO_PLL) + CKCU_Clk->PLL_Freq = CKCU_GetPLLFrequency(); +#endif + /* Get system frequency */ + switch (SystemCoreClockSrc) + { +#if (!LIBCFG_NO_PLL) + case CKCU_SW_PLL: + CKCU_Clk->SYSCK_Freq = CKCU_Clk->PLL_Freq; + break; +#endif + case CKCU_SW_HSE: + CKCU_Clk->SYSCK_Freq = HSE_VALUE; + break; + case CKCU_SW_HSI: + CKCU_Clk->SYSCK_Freq = HSI_VALUE; + break; + #if (LIBCFG_LSE) + case CKCU_SW_LSE: + CKCU_Clk->SYSCK_Freq = LSE_VALUE; + break; + #endif + case CKCU_SW_LSI: + CKCU_Clk->SYSCK_Freq = LSI_VALUE; + break; + default: + CKCU_Clk->SYSCK_Freq = 0; + break; + } + + /* Get HCLK frequency */ + div = HT_CKCU->AHBCFGR; + CKCU_Clk->HCLK_Freq = (div >= 5) ? ((CKCU_Clk->SYSCK_Freq) >> 5) : ((CKCU_Clk->SYSCK_Freq) >> div); + + /* Get ADC frequency */ + #if (LIBCFG_NO_ADC) + #else + #if (HT32_LIB_ENABLE_GET_CK_ADC) + div = CKCU_BF_READ(HT_CKCU->APBCFGR, CKCU_MASK_ADC0DIV, CKCU_POS_ADC0DIV); + CKCU_Clk->ADC0_Freq = (div == 7) ? ((CKCU_Clk->HCLK_Freq) / 3) : ((CKCU_Clk->HCLK_Freq) >> div); + #if (LIBCFG_ADC1) + div = CKCU_BF_READ(HT_CKCU->APBCFGR, CKCU_MASK_ADC1DIV, CKCU_POS_ADC1DIV); + CKCU_Clk->ADC1_Freq = (div == 7) ? ((CKCU_Clk->HCLK_Freq) / 3) : ((CKCU_Clk->HCLK_Freq) >> div); + #endif + #endif + #endif +} + +#if (!LIBCFG_NO_PLL) +/*********************************************************************************************************//** + * @brief Return the frequency of the PLL. + * @retval PLL Frequency + ************************************************************************************************************/ +u32 CKCU_GetPLLFrequency(void) +{ + u32 pllNO, pllNF, ClockSrc; + u32 CKCU_BB_PLLSRC = CKCU_BF_READ(HT_CKCU->GCFGR, CKCU_MASK_PLLSRC, CKCU_POS_PLLSRC); + u32 CKCU_BB_PLLBYPASS = CKCU_BF_READ(HT_CKCU->PLLCR, CKCU_MASK_PLLBYPASS, CKCU_POS_PLLBYPASS); + u32 CKCU_BB_PLLEN = CKCU_BF_READ(HT_CKCU->GCCR, CKCU_MASK_PLLEN, CKCU_POS_PLLEN); + /* Get PLL frequency */ + if (CKCU_BB_PLLEN == DISABLE) + { + return 0; + } + + ClockSrc = (CKCU_BB_PLLSRC == CKCU_PLLSRC_HSE) ? HSE_VALUE : HSI_VALUE; + + #if (LIBCFG_CKCU_PLLSRCDIV) + { + u32 PllSourceClockDiv = (HT_CKCU->PLLCFGR >> 28) & 1UL; + ClockSrc = ClockSrc >> PllSourceClockDiv; + } + #endif + + if (CKCU_BB_PLLBYPASS == ENABLE) + { + return ClockSrc; + } + + pllNF = CKCU_BF_READ(HT_CKCU->PLLCFGR, CKCU_MASK_PFBD, CKCU_POS_PFBD); + if (pllNF == 0) + pllNF = 16; + + pllNO = CKCU_BF_READ(HT_CKCU->PLLCFGR, CKCU_MASK_POTD, CKCU_POS_POTD); + + return ((ClockSrc * pllNF) >> pllNO); +} +#endif + +#if (!LIBCFG_CKCU_NO_APB_PRESCALER) +/*********************************************************************************************************//** + * @brief Configure the APB peripheral prescaler. + * @param Perip: specify the APB peripheral. + * This parameter can be: + * @arg CKCU_PCLK_I2C0, CKCU_PCLK_I2C1, CKCU_PCLK_I2C2, + * CKCU_PCLK_SPI0, CKCU_PCLK_SPI1, + * CKCU_PCLK_CAN0, + * CKCU_PCLK_BFTM0, CKCU_PCLK_BFTM1, + * CKCU_PCLK_MCTM0, + * CKCU_PCLK_GPTM0, CKCU_PCLK_GPTM1, + * CKCU_PCLK_USART0, CKCU_PCLK_USART1, + * CKCU_PCLK_UART0, CKCU_PCLK_UART1, CKCU_PCLK_UART2, CKCU_PCLK_UART3 + * CKCU_PCLK_AFIO, CKCU_PCLK_EXTI, CKCU_PCLK_ADC, CKCU_PCLK_CMP, CKCU_PCLK_OPA + * CKCU_PCLK_WDTR, CKCU_PCLK_BKPR, + * CKCU_PCLK_SCI0, CKCU_PCLK_SCI1, + * CKCU_PCLK_I2S, + * CKCU_PCLK_SCTM0, CKCU_PCLK_SCTM1, CKCU_PCLK_SCTM2, CKCU_PCLK_SCTM3 + * CKCU_PCLK_PWM0, CKCU_PCLK_PWM1 + * CKCU_PCLK_AFE, CKCU_PCLK_DAC0, CKCU_PCLK_DAC1, CKCU_PCLK_MIDI + * CKCU_PCLK_LEDC, CKCU_PCLK_TKEY + * @param PCLKPrescaler: specify the value of prescaler. + * This parameter can be: + * @arg CKCU_APBCLKPRE_DIV1: specific peripheral clock = PCLK / 1 (inapplicable to BKPRCLK) + * @arg CKCU_APBCLKPRE_DIV2: specific peripheral clock = PCLK / 2 (inapplicable to BKPRCLK) + * @arg CKCU_APBCLKPRE_DIV4: specific peripheral clock = PCLK / 4 + * @arg CKCU_APBCLKPRE_DIV8: specific peripheral clock = PCLK / 8 + * @arg CKCU_APBCLKPRE_DIV16: specific peripheral clock = PCLK / 16 (BKPRCLK only) + * @arg CKCU_APBCLKPRE_DIV32: specific peripheral clock = PCLK / 32 (BKPRCLK only) + * @retval None + ************************************************************************************************************/ +void CKCU_SetPeripPrescaler(CKCU_PeripPrescaler_TypeDef Perip, CKCU_APBCLKPRE_TypeDef PCLKPrescaler) +{ + u32 *PCSR = (u32 *)((&HT_CKCU->APBPCSR0) + (Perip >> CKCU_APBPCSR_OFFSET)); + u32 Prescaler = PCLKPrescaler; + if (Perip == CKCU_PCLK_BKPR) + { + Prescaler -= 2; + } + Perip &= 0x0000001F; + CKCU_BF_WRITE(*PCSR, (3UL << Perip), Perip, Prescaler); +} +#endif + +/*********************************************************************************************************//** + * @brief Return the operating frequency of the specific APB peripheral. + * @param Perip: specify the APB peripheral. + * This parameter can be: + * @arg CKCU_PCLK_I2C0, CKCU_PCLK_I2C1, CKCU_PCLK_I2C2, + * CKCU_PCLK_SPI0, CKCU_PCLK_SPI1, + * CKCU_PCLK_CAN0, + * CKCU_PCLK_BFTM0, CKCU_PCLK_BFTM1, + * CKCU_PCLK_MCTM0, + * CKCU_PCLK_GPTM0, CKCU_PCLK_GPTM1, + * CKCU_PCLK_USART0, CKCU_PCLK_USART1, + * CKCU_PCLK_UART0, CKCU_PCLK_UART1, CKCU_PCLK_UART2, CKCU_PCLK_UART3 + * CKCU_PCLK_AFIO, CKCU_PCLK_EXTI, CKCU_PCLK_ADC0, CKCU_PCLK_ADC1, CKCU_PCLK_CMP, CKCU_PCLK_OPA + * CKCU_PCLK_WDTR, CKCU_PCLK_BKPR, + * CKCU_PCLK_SCI0, CKCU_PCLK_SCI1, + * CKCU_PCLK_I2S, + * CKCU_PCLK_PWM0, CKCU_PCLK_PWM1 + * CKCU_PCLK_AFE, CKCU_PCLK_DAC0, CKCU_PCLK_DAC1, CKCU_PCLK_MIDI + * CKCU_PCLK_LEDC, CKCU_PCLK_TKEY + * @retval Frequency in Hz + ************************************************************************************************************/ +u32 CKCU_GetPeripFrequency(CKCU_PeripPrescaler_TypeDef Perip) +{ + CKCU_ClocksTypeDef Clock; + u32 PCLKPrescaler = 0; + #if (!LIBCFG_CKCU_NO_APB_PRESCALER) + u32 *PCSR = (u32 *)(&HT_CKCU->APBPCSR0 + (Perip >> CKCU_APBPCSR_OFFSET)); + + if (Perip == CKCU_PCLK_BKPR) + { + PCLKPrescaler = 2; + } + + Perip &= 0x0000001F; + PCLKPrescaler += CKCU_BF_READ(*PCSR, (3UL << Perip), Perip); + + #endif + CKCU_GetClocksFrequency(&Clock); + return (Clock.HCLK_Freq >> (PCLKPrescaler)); +} + +/*********************************************************************************************************//** + * @brief Enable or Disable the HSE Clock Monitor function. + * @param Cmd: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void CKCU_CKMCmd(ControlStatus Cmd) +{ + /* Check the parameters */ + Assert_Param(IS_CONTROL_STATUS(Cmd)); + + CKCU_BF_WRITE(HT_CKCU->GCCR, CKCU_MASK_CKMEN, CKCU_POS_CKMEN, Cmd); +} + +/*********************************************************************************************************//** + * @brief Enable or Disable the power saving wakeup RC clock. + * @param Cmd: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void CKCU_PSRCWKUPCmd(ControlStatus Cmd) +{ + /* Check the parameters */ + Assert_Param(IS_CONTROL_STATUS(Cmd)); + + CKCU_BF_WRITE(HT_CKCU->GCCR, CKCU_MASK_PSRCEN, CKCU_POS_PSRCEN, Cmd); +} + +/*********************************************************************************************************//** + * @brief Select the output clock source through the CKOUT pin. + * @param CKOUTInit: pointer to CKCU_CKOUTInitTypeDef structure. + * @retval None + ************************************************************************************************************/ +void CKCU_CKOUTConfig(CKCU_CKOUTInitTypeDef *CKOUTInit) +{ + CKCU_BF_WRITE(HT_CKCU->GCFGR, CKCU_MASK_CKOUTSRC, CKCU_POS_CKOUTSRC, CKOUTInit->CKOUTSRC); +} + +/*********************************************************************************************************//** + * @brief Check whether the specific CKCU interrupt has occurred or not. + * @param CKCU_INT: specify the CKCU interrupt source. + * This parameter can be any combination of the following values: + * @arg CKCU_INT_CKS: HSE clock failure interrupt flag (NMI) + * @retval SET or RESET + ************************************************************************************************************/ +FlagStatus CKCU_GetIntStatus(u32 CKCU_INT) +{ + /* Check the parameters */ + Assert_Param(IS_CKCU_INT_FLAG(CKCU_INT)); + + if (HT_CKCU->GCIR & CKCU_INT) + { + return SET; + } + else + { + return RESET; + } +} + +/*********************************************************************************************************//** + * @brief Clear the CKCU interrupt flag. + * @param CKCU_INT: specify the CKCU interrupt flag to clear. + * This parameter can be any combination of the following values: + * @arg CKCU_INT_CKS : HSE clock failure interrupt flag (NMI) + * @retval None + ************************************************************************************************************/ +void CKCU_ClearIntFlag(u32 CKCU_INT) +{ + /* Check the parameters */ + Assert_Param(IS_CKCU_INT_FLAG(CKCU_INT)); + + HT_CKCU->GCIR |= CKCU_INT; +} + +/*********************************************************************************************************//** + * @brief Enable or Disable the specific CKCU interrupts. + * @param CKCU_INT: specify the CKCU interrupt source which is enabled or disabled. + * This parameter can be any combination of the following values: + * @arg CKCU_INT_CKSIE : HSE clock failure interrupt (NMI) + * @param Cmd: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void CKCU_IntConfig(u32 CKCU_INT, ControlStatus Cmd) +{ + u32 tmp1 = HT_CKCU->GCIR; + + /* Check the parameters */ + Assert_Param(IS_CKCU_INT(CKCU_INT)); + Assert_Param(IS_CONTROL_STATUS(Cmd)); + + if (Cmd != DISABLE) + { + tmp1 |= CKCU_INT; + } + else + { + tmp1 &= ~CKCU_INT; + } + + /* Note: CKCU interrupt flags will be cleared by writing "1" */ + tmp1 &= ~0x00000001; + HT_CKCU->GCIR = tmp1; +} + +/*********************************************************************************************************//** + * @brief Enable or Disable the AHB peripheral clock during SLEEP mode. + * @param CKCU_CLK: specify the clock which is enabled or disabled. + * This parameter can be any combination of the following values: + * @arg CKCU_AHBEN_SLEEP_FMC, CKCU_AHBEN_SLEEP_SRAM, CKCU_AHBEN_SLEEP_BM, CKCU_AHBEN_SLEEP_APB0, + * @param Cmd: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void CKCU_SleepClockConfig(u32 CKCU_CLK, ControlStatus Cmd) +{ + /* Check the parameters */ + Assert_Param(IS_CKCU_SLEEP_AHB(CKCU_CLK)); + Assert_Param(IS_CONTROL_STATUS(Cmd)); + + if (Cmd != DISABLE) + { + HT_CKCU->AHBCCR |= CKCU_CLK; + } + else + { + HT_CKCU->AHBCCR &= ~CKCU_CLK; + } +} + +#if (!LIBCFG_NO_PLL) +/*********************************************************************************************************//** + * @brief Check if PLL clock used by the specific target source or not. + * @param Target: specify the target clock. + * This parameter can be one of the following values: + * @arg CKCU_PLLST_SYSCK : Is PLL used by system clock + * @arg CKCU_PLLST_USB : Is PLL used by USB + * @arg CKCU_PLLST_REFCK : Is PLL used by CK_REF + * @retval TRUE or FALSE + ************************************************************************************************************/ +bool CKCU_IS_PLL_USED(CKCU_PLLST_TypeDef Target) +{ + if ((HT_CKCU->CKST >> CKCU_POS_PLLST) & (u32)Target) + { + return TRUE; + } + else + { + return FALSE; + } +} +#endif + +/*********************************************************************************************************//** + * @brief Check HSI clock used by the specific target source or not. + * @param Target: specify the target clock. + * This parameter can be one of the following values: + * @arg CKCU_HSIST_SYSCK : Is HSI used by system clock + * @arg CKCU_HSIST_PLL : Is HSI used by PLL + * @arg CKCU_HSIST_CKM : Is HSI used by clock monitor + * @retval TRUE or FALSE + ************************************************************************************************************/ +bool CKCU_IS_HSI_USED(CKCU_HSIST_TypeDef Target) +{ + if ((HT_CKCU->CKST >> CKCU_POS_HSIST) & (u32)Target) + { + return TRUE; + } + else + { + return FALSE; + } +} + +/*********************************************************************************************************//** + * @brief Check HSE clock used by the specific target source or not. + * @param Target: specify the target clock. + * This parameter can be one of the following values: + * @arg CKCU_HSEST_SYSCK : Is HSE used by system clock + * @arg CKCU_HSEST_PLL : Is HSE used by PLL + * @retval TRUE or FALSE + ************************************************************************************************************/ +bool CKCU_IS_HSE_USED(CKCU_HSEST_TypeDef Target) +{ + if ((HT_CKCU->CKST >> CKCU_POS_HSEST) & (u32)Target) + { + return TRUE; + } + else + { + return FALSE; + } +} + +/*********************************************************************************************************//** + * @brief Enable or Disable the specific debug function. + * @param CKCU_DBGx: specify the debug functions to be enabled or disabled. + * This parameter can be any combination of the following values: + * @arg CKCU_DBG_SLEEP, CKCU_DBG_DEEPSLEEP1, CKCU_DBG_DEEPSLEEP2, CKCU_DBG_POWERDOWN, + * CKCU_DBG_MCTM0_HALT, + * CKCU_DBG_GPTM0_HALT, CKCU_DBG_GPTM1_HALT, + * CKCU_DBG_SCTM0_HALT, CKCU_DBG_SCTM1_HALT, CKCU_DBG_SCTM2_HALT, CKCU_DBG_SCTM3_HALT, + * CKCU_DBG_BFTM0_HALT, CKCU_DBG_BFTM1_HALT, + * CKCU_DBG_USART0_HALT, CKCU_DBG_USART1_HALT, + * CKCU_DBG_UART0_HALT, CKCU_DBG_UART1_HALT, CKCU_DBG_UART2_HALT, CKCU_DBG_UART3_HALT, + * CKCU_DBG_SPI0_HALT, CKCU_DBG_SPI1_HALT, CKCU_DBG_QSPI_HALT, + * CKCU_DBG_I2C0_HALT, CKCU_DBG_I2C1_HALT, CKCU_DBG_I2C2_HALT, + * CKCU_DBG_CAN0_HALT + * CKCU_DBG_SCI0_HALT, CKCU_DBG_SCI1_HALT, + * CKCU_DBG_WDT_HALT, + * CKCU_DBG_PWM0_HALT, CKCU_DBG_PWM1_HALT, CKCU_DBG_PWM2_HALT, + * @param Cmd: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void CKCU_MCUDBGConfig(u32 CKCU_DBGx, ControlStatus Cmd) +{ + /* Check the parameters */ + Assert_Param(IS_CKCU_DBG(CKCU_DBGx)); + Assert_Param(IS_CONTROL_STATUS(Cmd)); + + if (Cmd != DISABLE) + { + HT_CKCU->MCUDBGCR |= CKCU_DBGx; + } + else + { + HT_CKCU->MCUDBGCR &= ~CKCU_DBGx; + } +} + +#if (!LIBCFG_CKCU_NO_LPCR) +/*********************************************************************************************************//** + * @brief Enable or Disable the Backup domain isolation control. + * @param Cmd: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void CKCU_BKISOCmd(ControlStatus Cmd) +{ + /* Check the parameters */ + Assert_Param(IS_CONTROL_STATUS(Cmd)); + + /* DISABLE: Backup domain is isolated */ + CKCU_BF_WRITE(HT_CKCU->LPCR, CKCU_MASK_BKISO, CKCU_POS_BKISO, !Cmd); +} +#endif + +/*********************************************************************************************************//** + * @brief Enable or Disable the peripheral clock. + * @param Clock: specify the peripheral clock enable bits. + * @param Cmd: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void CKCU_PeripClockConfig(CKCU_PeripClockConfig_TypeDef Clock, ControlStatus Cmd) +{ + u32 uAHBCCR; + u32 uAPBCCR0; + u32 uAPBCCR1; + + uAHBCCR = HT_CKCU->AHBCCR; + uAPBCCR0 = HT_CKCU->APBCCR0; + uAPBCCR1 = HT_CKCU->APBCCR1; + + uAHBCCR &= ~(Clock.Reg[0]); + uAPBCCR0 &= ~(Clock.Reg[1]); + uAPBCCR1 &= ~(Clock.Reg[2]); + + if (Cmd != DISABLE) + { + uAHBCCR |= Clock.Reg[0]; + uAPBCCR0 |= Clock.Reg[1]; + uAPBCCR1 |= Clock.Reg[2]; + } + + HT_CKCU->AHBCCR = uAHBCCR; + HT_CKCU->APBCCR0 = uAPBCCR0; + HT_CKCU->APBCCR1 = uAPBCCR1; +} + +#if (((LIBCFG_LSE) || (LIBCFG_USBD)) && (!LIBCFG_CKCU_NO_AUTO_TRIM)) +/*********************************************************************************************************//** + * @brief Configure the reference clock of HSI auto-trim function. + * @param CLKSRC: specify the clock source. + * This parameter can be: + * @arg CKCU_ATC_LSE: LSE is selected as reference clock + * @arg CKCU_ATC_USB: USB is selected as reference clock + * @arg CKCU_ATC_CKIN: External pin (CKIN) is selected as reference clock + * @retval None + ************************************************************************************************************/ +void CKCU_HSIAutoTrimClkConfig(CKCU_ATC_TypeDef CLKSRC) +{ + CKCU_BF_WRITE(HT_CKCU->HSICR, CKCU_MASK_REFCLKSEL, CKCU_POS_REFCLKSEL, CLKSRC); +} + +#if (LIBCFG_CKCU_ATM_V01) +/*********************************************************************************************************//** + * @brief Initialize the ATC according to the specified parameters in the ATC_InitStruct. + * @param ATC_InitStruct: pointer to a CKCU_ATCInitTypeDef structure. + * @retval None + ************************************************************************************************************/ +void CKCU_ATCInit(CKCU_ATCInitTypeDef* ATC_InitStruct) +{ + HT_CKCU->HSICR &= 0xFFFFFFF3; + HT_CKCU->HSICR |= (u32)ATC_InitStruct->SearchAlgorithm | (u32)ATC_InitStruct->FrqTolerance; +} +#endif + +/*********************************************************************************************************//** + * @brief Enable or Disable the HSI auto-trim function. + * @param Cmd: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void CKCU_HSIAutoTrimCmd(ControlStatus Cmd) +{ + /* Check the parameters */ + Assert_Param(IS_CONTROL_STATUS(Cmd)); + + CKCU_BF_WRITE(HT_CKCU->HSICR, CKCU_MASK_TRIMEN, CKCU_POS_TRIMEN, Cmd); + CKCU_BF_WRITE(HT_CKCU->HSICR, CKCU_MASK_ATCEN, CKCU_POS_ATCEN, Cmd); +} + +/*********************************************************************************************************//** + * @brief Check Auto Trim is ready or not. + * @retval TRUE or FALSE + ************************************************************************************************************/ +bool CKCU_HSIAutoTrimIsReady(void) +{ +#if (LIBCFG_CKCU_AUTO_TRIM_LEGACY) + u32 lower_bound, upper_bound, i; + static u32 ATCR = 0; + + if ((HT_CKCU->HSICR & (3ul << 5)) == 0) + { + lower_bound = 7812 - 19; + upper_bound = 7812 + 19; + } + else + { + lower_bound = 8000 - 20; + upper_bound = 8000 + 20; + } + + SystemCoreClockUpdate(); + for (i = SystemCoreClock / 8000; i > 0; i--){}; + ATCR += HT_CKCU->HSIATCR; + ATCR /= 2; + + if ((ATCR >= lower_bound) && (ATCR <= upper_bound)) + { + ATCR = 0; + return TRUE; + } + else + { + return FALSE; + } + +#else + return (HT_CKCU->HSICR & 0x80) ? TRUE : FALSE; +#endif +} +#endif + +#if (LIBCFG_CKCU_HSIRDYCR) +/*********************************************************************************************************//** + * @brief Set HSI Ready Counter Value. + * @param Value: 0x0~0x1F. + * @retval None + ************************************************************************************************************/ +void CKCU_Set_HSIReadyCounter(u8 Value) +{ + /* Check the parameters */ + Assert_Param(IS_COUNTER_VALUE(Value)); + + HT_CKCU->HSIRDYCR = ((HT_CKCU->HSIRDYCR) & (~(0x1F))) | Value; +} +#endif +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/ht32f5xxxx_cmp.c b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/ht32f5xxxx_cmp.c new file mode 100644 index 0000000000..10f4b9dded --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/ht32f5xxxx_cmp.c @@ -0,0 +1,336 @@ +/*********************************************************************************************************//** + * @file ht32f5xxxx_cmp.c + * @version $Rev:: 6932 $ + * @date $Date:: 2023-05-11 #$ + * @brief This file provides all the CMP firmware functions. + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ + +/* Includes ------------------------------------------------------------------------------------------------*/ +#include "ht32f5xxxx_cmp.h" + +/** @addtogroup HT32F5xxxx_Peripheral_Driver HT32F5xxxx Peripheral Driver + * @{ + */ + +/** @defgroup CMP CMP + * @brief CMP driver modules + * @{ + */ + + +/* Global functions ----------------------------------------------------------------------------------------*/ +/** @defgroup CMP_Exported_Functions CMP exported functions + * @{ + */ +/*********************************************************************************************************//** + * @brief Deinitialize the CMP0 and CMP1 peripheral registers to their default reset values. + * @param HT_CMPn: where HT_CMPn is the selected CMP from the CMP peripherals. + * @retval None + ************************************************************************************************************/ +void CMP_DeInit(HT_CMP_TypeDef* HT_CMPn) +{ + RSTCU_PeripReset_TypeDef RSTCUReset = {{0}}; + + if (HT_CMPn == NULL) // Remove the compiler warning + { + } + + RSTCUReset.Bit.CMP = 1; + RSTCU_PeripReset(RSTCUReset, ENABLE); +} + +/*********************************************************************************************************//** + * @brief Unprotect the selected comparator configuration before setting the Comparator Control Register. + * @param HT_CMPn: where HT_CMPn is the selected CMP from the CMP peripherals. + * @retval None + ************************************************************************************************************/ +void CMP_UnprotectConfig(HT_CMP_TypeDef* HT_CMPn) +{ + /* Check the parameters */ + Assert_Param(IS_CMP(HT_CMPn)); + + /* Set the unlock code corresponding to selected comparator */ + HT_CMPn->CR = CMP_PROTECT_KEY; +} + +/*********************************************************************************************************//** + * @brief Initialize the CMP peripheral according to the specified parameters in the CMP_InitStruct. + * @param HT_CMPn: where HT_CMPn is the selected CMP from the CMP peripherals. + * @param CMP_InitStruct: pointer to a CMP_InitTypeDef structure. + * @retval None + ************************************************************************************************************/ +void CMP_Init(HT_CMP_TypeDef* HT_CMPn, CMP_InitTypeDef* CMP_InitStruct) +{ + /* Check the parameters */ + Assert_Param(IS_CMP(HT_CMPn)); + Assert_Param(IS_CMP_Wakeup_Set(CMP_InitStruct->CMP_Wakeup)); + Assert_Param(IS_CMP_OutputSelection(CMP_InitStruct->CMP_OutputSelection)); + Assert_Param(IS_CMP_ScalerSource(CMP_InitStruct->CMP_ScalerSource)); + Assert_Param(IS_CMP_ScalerOutputBuf(CMP_InitStruct->CMP_ScalerOutputBuf)); + Assert_Param(IS_CMP_ScalerEnable(CMP_InitStruct->CMP_ScalerEnable)); + Assert_Param(IS_CMP_CoutSynchronized(CMP_InitStruct->CMP_CoutSync)); + Assert_Param(IS_CMP_OutputPol_Set(CMP_InitStruct->CMP_OutputPol)); + #if (LIBCFG_CMP_65x_VER) + Assert_Param(IS_CMP_InputSelection(CMP_InitStruct->CMP_InputSelection)); + #endif + Assert_Param(IS_CMP_InvInputSelection(CMP_InitStruct->CMP_InvInputSelection)); + Assert_Param(IS_CMP_Hysteresis_Set(CMP_InitStruct->CMP_Hysteresis)); + Assert_Param(IS_CMP_Speed_Set(CMP_InitStruct->CMP_Speed)); + + HT_CMPn->CR |= CMP_InitStruct->CMP_Wakeup | CMP_InitStruct->CMP_OutputSelection | CMP_InitStruct->CMP_ScalerSource | \ + CMP_InitStruct->CMP_ScalerOutputBuf | CMP_InitStruct->CMP_ScalerEnable | CMP_InitStruct->CMP_CoutSync | \ + CMP_InitStruct->CMP_OutputPol | CMP_InitStruct->CMP_InvInputSelection | CMP_InitStruct->CMP_Hysteresis | \ + CMP_InitStruct->CMP_Speed; + + #if (LIBCFG_CMP_65x_VER) + HT_CMPn->CI = CMP_InitStruct->CMP_InputSelection; + #endif +} + +/*********************************************************************************************************//** + * @brief Fill each CMP_InitStruct member with its default value. + * @param CMP_InitStruct: pointer to an CMP_InitTypeDef structure. + * @retval None + ************************************************************************************************************/ +void CMP_StructInit(CMP_InitTypeDef* CMP_InitStruct) +{ + /* CMP_InitStruct members default value */ + CMP_InitStruct->CMP_Wakeup = CMP_WUP_DISABLE; + CMP_InitStruct->CMP_OutputSelection = CMP_TRIG_NONE; + #if (LIBCFG_CMP_NOSCALER_SRC) + CMP_InitStruct->CMP_ScalerSource = 0; + #else + CMP_InitStruct->CMP_ScalerSource = CMP_SCALER_SRC_VDDA; + #endif + CMP_InitStruct->CMP_ScalerOutputBuf = CMP_SCALER_OBUF_DISABLE; + CMP_InitStruct->CMP_ScalerEnable = CMP_SCALER_DISABLE; + CMP_InitStruct->CMP_CoutSync = CMP_ASYNC_OUTPUT; + CMP_InitStruct->CMP_OutputPol = CMP_NONINV_OUTPUT; + CMP_InitStruct->CMP_InvInputSelection = CMP_EXTERNAL_CN_IN; + CMP_InitStruct->CMP_Hysteresis = CMP_NO_HYSTERESIS; + CMP_InitStruct->CMP_Speed = CMP_LOW_SPEED; +} + +/*********************************************************************************************************//** + * @brief Enable or Disable the specified CMP peripheral. + * @param HT_CMPn: where HT_CMPn is the selected CMP from the CMP peripherals. + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void CMP_Cmd(HT_CMP_TypeDef* HT_CMPn, ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_CMP(HT_CMPn)); + Assert_Param(IS_CONTROL_STATUS(NewState)); + + if (NewState != DISABLE) + { + HT_CMPn->CR |= CMP_ENABLE; + } + else + { + HT_CMPn->CR &= ~(u32)CMP_ENABLE; + } +} + +/*********************************************************************************************************//** + * @brief Enable or Disable the specified CMP interrupts. + * @param HT_CMPn: where HT_CMPn is the selected CMP from the CMP peripherals. + * @param CMP_INT_x: specify the CMP interrupt sources that is to be enabled or disabled. + * This parameter can be any combination of the following values: + * @arg CMP_INT_RE : CMP rising edge interrupt + * @arg CMP_INT_FE : CMP falling edge interrupt + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void CMP_IntConfig(HT_CMP_TypeDef* HT_CMPn, u32 CMP_INT_x, ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_CMP(HT_CMPn)); + Assert_Param(IS_CMP_INT(CMP_INT_x)); + Assert_Param(IS_CONTROL_STATUS(NewState)); + + if (NewState != DISABLE) + { + HT_CMPn->IER |= CMP_INT_x; + } + else + { + HT_CMPn->IER &= ~CMP_INT_x; + } +} + +/*********************************************************************************************************//** + * @brief Enable or Disable the specified CMP edge detection. + * @param HT_CMPn: where HT_CMPn is the selected CMP from the CMP peripherals. + * @param CMP_xE_Detect: specify the CMP edge detection that is to be enabled or disabled. + * This parameter can be any combination of the following values: + * @arg CMP_RE_Detect : CMP rising edge detection + * @arg CMP_FE_Detect : CMP falling edge detection + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void CMP_EdgeDetectConfig(HT_CMP_TypeDef* HT_CMPn, u32 CMP_xE_Detect, ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_CMP(HT_CMPn)); + Assert_Param(IS_CMP_EdgeDetect(CMP_xE_Detect)); + Assert_Param(IS_CONTROL_STATUS(NewState)); + + if (NewState != DISABLE) + { + HT_CMPn->TFR = (HT_CMPn->TFR | CMP_xE_Detect) & 0xfffffffc; + } + else + { + HT_CMPn->TFR = (HT_CMPn->TFR & (~CMP_xE_Detect)) & 0xfffffffc; + } +} + +/*********************************************************************************************************//** + * @brief Check whether the specified CM flag has been set. + * @param HT_CMPn: where HT_CMPn is the selected CMP from the CMP peripherals. + * @param CMP_FLAG_x: specify the flag to be checked. + * This parameter can be any combination of the following values: + * @arg CMP_FLAG_RE : CMP rising edge flag + * @arg CMP_FLAG_FE : CMP falling edge flag + * @retval SET or RESET + ************************************************************************************************************/ +FlagStatus CMP_GetFlagStatus(HT_CMP_TypeDef* HT_CMPn, u32 CMP_FLAG_x) +{ + /* Check the parameters */ + Assert_Param(IS_CMP(HT_CMPn)); + Assert_Param(IS_CMP_FLAG(CMP_FLAG_x)); + + if ((HT_CMPn->TFR & CMP_FLAG_x) != 0) + { + return SET; + } + else + { + return RESET; + } +} + +/*********************************************************************************************************//** + * @brief Clear flags of the specified CMP. + * @param HT_CMPn: where HT_CMPn is the selected CMP from the CMP peripherals. + * @param CMP_FLAG_x: specify the flag to be checked. + * This parameter can be any combination of the following values: + * @arg CMP_FLAG_RE : CMP rising edge flag + * @arg CMP_FLAG_FE : CMP falling edge flag + * @retval None + ************************************************************************************************************/ +void CMP_ClearFlag(HT_CMP_TypeDef* HT_CMPn, u32 CMP_FLAG_x) +{ + /* Check the parameters */ + Assert_Param(IS_CMP(HT_CMPn)); + Assert_Param(IS_CMP_FLAG(CMP_FLAG_x)); + + /* Clear the flags */ + HT_CMPn->TFR = (HT_CMPn->TFR & 0xfffffffc) | CMP_FLAG_x; + + /*--------------------------------------------------------------------------------------------------------*/ + /* DSB instruction is added in this function to ensure the write operation which is for clearing interrupt*/ + /* flag is actually completed before exiting ISR. It prevents the NVIC from detecting the interrupt again */ + /* since the write register operation may be pended in the internal write buffer of Cortex-Mx when program*/ + /* has exited interrupt routine. This DSB instruction may be masked if this function is called in the */ + /* beginning of ISR and there are still some instructions before exiting ISR. */ + /*--------------------------------------------------------------------------------------------------------*/ + __DSB(); +} + +/*********************************************************************************************************//** + * @brief Get the output status of the specified CMP. + * @param HT_CMPn: where HT_CMPn is the selected CMP from the CMP peripherals. + * @retval SET or RESET + ************************************************************************************************************/ +FlagStatus CMP_GetOutputStatus(HT_CMP_TypeDef* HT_CMPn) +{ + /* Check the parameters */ + Assert_Param(IS_CMP(HT_CMPn)); + + if ((HT_CMPn-> CR & CMP_OUTPUT_HIGH) != 0) + { + return SET; + } + else + { + return RESET; + } +} + +/*********************************************************************************************************//** + * @brief Set the specified reference value in the data register of the scaler. + * @param HT_CMPn: where HT_CMPn is the selected CMP from the CMP peripherals. + * @param Scaler_Value: value to be loaded in the selected data register + * @retval None + ************************************************************************************************************/ +void CMP_SetScalerValue(HT_CMP_TypeDef* HT_CMPn, u8 Scaler_Value) +{ + /* Check the parameters */ + Assert_Param(IS_CMP(HT_CMPn)); + Assert_Param(IS_SCALER_VALUE(Scaler_Value)); + + /* Set the scaler reference value register */ + HT_CMPn->VALR = (u32)Scaler_Value; +} + +#if (LIBCFG_CMP_CO) +/*********************************************************************************************************//** + * @brief Select the synchronous source with the CMPnO signal. + * @param HT_CMPn: where HT_CMPn is the selected CMP from the CMP peripherals. + * @param uCOUTSEL: Comparator Sync Output Select. + * This parameter can be one of the following value: + * @arg CMP_SYNCOUT_CMPnO : + * @arg CMP_SYNCOUT_MCTM_CH0O : + * @arg CMP_SYNCOUT_MCTM_CH0NO : + * @arg CMP_SYNCOUT_MCTM_CH1O : + * @arg CMP_SYNCOUT_MCTM_CH1NO : + * @arg CMP_SYNCOUT_MCTM_CH2O : + * @arg CMP_SYNCOUT_MCTM_CH2NO : + * @arg CMP_SYNCOUT_MCTM_CH3O : + * @arg CMP_SYNCOUT_MCTM_CH3OB : + * @retval None + ************************************************************************************************************/ +void CMP_Output_SyncSource_Select(HT_CMP_TypeDef* HT_CMPn, CMP_SYNCOUT_Enum CMP_SYNCOUT_x) +{ + /* Check the parameters */ + Assert_Param(IS_CMP(HT_CMPn)); + Assert_Param(IS_CMP_SYNC_SOURCE(CMP_SYNCOUT_x)); + + HT_CMPn->CO = (HT_CMPn->CO & 0xFFFFFFF0) | CMP_SYNCOUT_x; +} +#endif +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/ht32f5xxxx_crc.c b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/ht32f5xxxx_crc.c new file mode 100644 index 0000000000..04da829194 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/ht32f5xxxx_crc.c @@ -0,0 +1,190 @@ +/*********************************************************************************************************//** + * @file ht32f5xxxx_crc.c + * @version $Rev:: 5483 $ + * @date $Date:: 2021-07-19 #$ + * @brief This file provides all the CRC firmware functions. + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ + +/* Includes ------------------------------------------------------------------------------------------------*/ +#include "ht32f5xxxx_crc.h" + +/** @addtogroup HT32F5xxxx_Peripheral_Driver HT32F5xxxx Peripheral Driver + * @{ + */ + +/** @defgroup CRC CRC + * @brief CRC driver modules + * @{ + */ + + +/* Global functions ----------------------------------------------------------------------------------------*/ +/** @defgroup CRC_Exported_Functions CRC exported functions + * @{ + */ +/*********************************************************************************************************//** + * @brief Deinitialize the CRC peripheral registers to their default reset values. + * @param HT_CRCn: where CRC is the selected CRC peripheral. + * @retval None + ************************************************************************************************************/ +void CRC_DeInit(HT_CRC_TypeDef* HT_CRCn) +{ + RSTCU_PeripReset_TypeDef RSTCUReset = {{0}}; + + if (HT_CRCn == NULL) // Remove the compiler warning + { + } + + RSTCUReset.Bit.CRC = 1; + RSTCU_PeripReset(RSTCUReset, ENABLE); +} + +/*********************************************************************************************************//** + * @brief Initialize the CRC peripheral according to the specified parameters in the CRC_InitStruct. + * @param HT_CRCn: Selected CRC peripheral. + * @param CRC_InitStruct: pointer to a CRC_InitTypeDef structure. + * @retval None + ************************************************************************************************************/ +void CRC_Init(HT_CRC_TypeDef* HT_CRCn, CRC_InitTypeDef* CRC_InitStruct) +{ + u32 uCRValue; + HT_CRCn->SDR = CRC_InitStruct->uSeed; + switch (CRC_InitStruct->Mode) + { + case CRC_CCITT_POLY: + { + uCRValue = CRC_CCITT_POLY | CRC_NORMAL_WR | CRC_NORMAL_SUM; + break; + } + case CRC_16_POLY: + { + uCRValue = CRC_16_POLY | CRC_BIT_RVS_WR | CRC_BIT_RVS_SUM | CRC_BYTE_RVS_SUM; + break; + } + case CRC_32_POLY: + { + uCRValue = CRC_32_POLY | CRC_BIT_RVS_WR | CRC_BIT_RVS_SUM | CRC_BYTE_RVS_SUM | CRC_CMPL_SUM; + break; + } + case CRC_USER_DEFINE: + default: + { + uCRValue = CRC_InitStruct->uCR; + break; + } + } + + HT_CRCn->CR = uCRValue; +} + +/*********************************************************************************************************//** + * @brief Get the CRC checksum from the given data + * @param HT_CRCn: Selected CRC peripheral. + * @param buffer: pointer to the given data to be calculated + * @param length: data length in byte + * @retval The checksum value + ***********************************************************************************************************/ +u32 CRC_Process(HT_CRC_TypeDef* HT_CRCn, u8 *buffer, u32 length) +{ + while (length--) + { + wb(&HT_CRCn->DR, *buffer++); // byte write + } + + return (HT_CRCn->CSR); +} + +/*********************************************************************************************************//** + * @brief Get the CRC-CCITT checksum from the given data + * @param seed: CRC initial data + * @param buffer: pointer to the given data to be calculated + * @param length: data length in byte + * @retval The checksum value + ************************************************************************************************************/ +u16 CRC_CCITT(u16 seed, u8 *buffer, u32 length) +{ + /* CRC-CCITT poly: 0x1021 */ + HT_CRC->SDR = seed; + HT_CRC->CR = CRC_CCITT_POLY | CRC_NORMAL_WR | CRC_NORMAL_SUM; + + while (length--) + { + wb(&HT_CRC->DR, *buffer++); // byte write + } + + return (u16)(HT_CRC->CSR); +} + +/*********************************************************************************************************//** + * @brief Get the CRC-16 checksum from the given data + * @param seed: CRC initial data + * @param buffer: pointer to the given data to be calculated + * @param length: data length in byte + * @retval The checksum value + ************************************************************************************************************/ +u16 CRC_16(u16 seed, u8 *buffer, u32 length) +{ + /* CRC-16 poly: 0x8005 */ + HT_CRC->SDR = seed; + HT_CRC->CR = CRC_16_POLY | CRC_BIT_RVS_WR | CRC_BIT_RVS_SUM | CRC_BYTE_RVS_SUM; + + while (length--) + { + wb(&HT_CRC->DR, *buffer++); // byte write + } + + return (u16)(HT_CRC->CSR); +} + +/*********************************************************************************************************//** + * @brief Get the CRC-32 checksum from the given data + * @param seed: CRC initial data + * @param buffer: pointer to the given data to be calculated + * @param length: data length in byte + * @retval The checksum value + ************************************************************************************************************/ +u32 CRC_32(u32 seed, u8 *buffer, u32 length) +{ + /* CRC-32 poly: 0x04C11DB7 */ + HT_CRC->SDR = seed; + HT_CRC->CR = CRC_32_POLY | CRC_BIT_RVS_WR | CRC_BIT_RVS_SUM | CRC_BYTE_RVS_SUM | CRC_CMPL_SUM; + + while (length--) + { + wb(&HT_CRC->DR, *buffer++); // byte write + } + + return (HT_CRC->CSR); +} +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/ht32f5xxxx_dac.c b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/ht32f5xxxx_dac.c new file mode 100644 index 0000000000..e209d4c1a0 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/ht32f5xxxx_dac.c @@ -0,0 +1,249 @@ +/*********************************************************************************************************//** + * @file ht32f5xxxx_dac.c + * @version $Rev:: 7081 $ + * @date $Date:: 2023-08-01 #$ + * @brief This file provides all the DAC firmware functions. + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ + +/* Includes ------------------------------------------------------------------------------------------------*/ +#include "ht32f5xxxx_dac.h" + +/** @addtogroup HT32F5xxxx_Peripheral_Driver HT32F5xxxx Peripheral Driver + * @{ + */ + +/** @defgroup DAC DAC + * @brief DAC driver modules + * @{ + */ + + +/* Global functions ----------------------------------------------------------------------------------------*/ +/** @defgroup DAC_Exported_Functions DAC exported functions + * @{ + */ +/*********************************************************************************************************//** + * @brief Deinitialize the HT_DACn peripheral registers to their default reset values. + * @param HT_DACn: where HT_DACn is the selected DAC from the DAC peripherals. + * @retval None + ************************************************************************************************************/ +void DAC_DeInit(HT_DAC_TypeDef* HT_DACn) +{ + RSTCU_PeripReset_TypeDef RSTCUReset = {{0}}; + + /* Check the parameters */ + Assert_Param(IS_DAC(HT_DACn)); + + if (HT_DACn == HT_DAC0) + { + RSTCUReset.Bit.DAC0 = 1; + } + #if (LIBCFG_DAC1) + else if (HT_DACn == HT_DAC1) + { + RSTCUReset.Bit.DAC1 = 1; + } + #endif + RSTCU_PeripReset(RSTCUReset, ENABLE); +} + +/*********************************************************************************************************//** + * @brief Configure the DAC conversion mode. + * @param HT_DACn: where HT_DACn is the selected DAC from the DAC peripherals. + * @param ModeSel: specify the conversion mode + * This parameter can be one of the following values: + * @arg ASYNC_MODE : asynchronous conversion mode + * @arg SYNC_MODE : synchronous conversion mode + * @retval None + ************************************************************************************************************/ +void DAC_ModeConfig(HT_DAC_TypeDef* HT_DACn, u8 ModeSel) +{ + /* Check the parameters */ + Assert_Param(IS_DAC(HT_DACn)); + Assert_Param(IS_DAC_CONVERSION_MODE(ModeSel)); + + HT_DACn->CFGR = ModeSel; +} + +/*********************************************************************************************************//** + * @brief Configure the specified DAC channel reference voltage. + * @param HT_DACn: where HT_DACn is the selected DAC from the DAC peripherals. + * @param DAC_Ch: the DAC channel to configure +* This parameter can be one of the following values: +* @arg DAC_CH0 : DAC channel 0 +* @arg DAC_CH1 : DAC channel 1 + * @param RefSel: DAC reference voltage source + * This parameter can be one of the following values: + * @arg DAC_REFERENCE_VDDA : VDDA + * @arg DAC_REFERENCE_VREF : VREF + * @retval None + ************************************************************************************************************/ +void DAC_ReferenceConfig(HT_DAC_TypeDef* HT_DACn, u8 DAC_Ch, u32 RefSel) +{ + HT_DACCH_TypeDef *DACnCH = (HT_DACCH_TypeDef *)((u32)&HT_DACn->DACCH0 + DAC_Ch * 8 * 4); + + /* Check the parameters */ + Assert_Param(IS_DAC(HT_DACn)); + Assert_Param(IS_DAC_CHANNEL(DAC_Ch)); + Assert_Param(IS_DAC_REFERENCE(RefSel)); + + DACnCH->CR = (DACnCH->CR & ~(3UL << 14)) | RefSel; +} + +/*********************************************************************************************************//** + * @brief Configure the specified DAC channel resolution. + * @param HT_DACn: where HT_DACn is the selected DAC from the DAC peripherals. + * @param DAC_Ch: the DAC channel to configure +* This parameter can be one of the following values: +* @arg DAC_CH0 : DAC channel 0 +* @arg DAC_CH1 : DAC channel 1 + * @param ResoSel: DAC Channel Resolution + * This parameter can be one of the following values: + * @arg DAC_RESOLUTION_8BIT : 8-bit resolution + * @arg DAC_RESOLUTION_12BIT : 12-bit resolution + * @retval None + ************************************************************************************************************/ +void DAC_ResolutionConfig(HT_DAC_TypeDef* HT_DACn, u8 DAC_Ch, u32 ResoSel) +{ + HT_DACCH_TypeDef *DACnCH = (HT_DACCH_TypeDef *)((u32)&HT_DACn->DACCH0 + DAC_Ch * 8 * 4); + + /* Check the parameters */ + Assert_Param(IS_DAC(HT_DACn)); + Assert_Param(IS_DAC_CHANNEL(DAC_Ch)); + Assert_Param(IS_DAC_RESOLUTION(ResoSel)); + + DACnCH->CR = (DACnCH->CR & ~(1UL << 2)) | ResoSel; +} + +/*********************************************************************************************************//** + * @brief Enable or Disable the specified DAC Channel output buffer. + * @param HT_DACn: where HT_DACn is the selected DAC from the DAC peripherals. + * @param DAC_Ch: the DAC channel to configure +* This parameter can be one of the following values: +* @arg DAC_CH0 : DAC channel 0 +* @arg DAC_CH1 : DAC channel 1 + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void DAC_OutBufCmd(HT_DAC_TypeDef* HT_DACn, u8 DAC_Ch, ControlStatus NewState) +{ + HT_DACCH_TypeDef *DACnCH = (HT_DACCH_TypeDef *)((u32)&HT_DACn->DACCH0 + DAC_Ch * 8 * 4); + + /* Check the parameters */ + Assert_Param(IS_DAC(HT_DACn)); + Assert_Param(IS_DAC_CHANNEL(DAC_Ch)); + Assert_Param(IS_CONTROL_STATUS(NewState)); + + if (NewState != DISABLE) + { + DACnCH->CR = (DACnCH->CR & ~(3UL << 6)) | (2UL << 6); + } + else + { + DACnCH->CR = (DACnCH->CR & ~(3UL << 6)) | (1UL << 6); + } +} + +/*********************************************************************************************************//** + * @brief Enable or Disable the specified DAC channel. + * @param HT_DACn: where HT_DACn is the selected DAC from the DAC peripherals. + * @param DAC_Ch: the DAC channel to configure +* This parameter can be one of the following values: +* @arg DAC_CH0 : DAC channel 0 +* @arg DAC_CH1 : DAC channel 1 + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void DAC_Cmd(HT_DAC_TypeDef* HT_DACn, u8 DAC_Ch, ControlStatus NewState) +{ + HT_DACCH_TypeDef *DACnCH = (HT_DACCH_TypeDef *)((u32)&HT_DACn->DACCH0 + DAC_Ch * 8 * 4); + + /* Check the parameters */ + Assert_Param(IS_DAC(HT_DACn)); + Assert_Param(IS_DAC_CHANNEL(DAC_Ch)); + Assert_Param(IS_CONTROL_STATUS(NewState)); + + if (NewState != DISABLE) + { + SetBit_BB((u32)&DACnCH->CR, 0); + } + else + { + ResetBit_BB((u32)&DACnCH->CR, 0); + } +} + +/*********************************************************************************************************//** + * @brief Set the data holding register value for the specified DAC channel. + * @param HT_DACn: where HT_DACn is the selected DAC from the DAC peripherals. + * @param DAC_Ch: the DAC channel to configure +* This parameter can be one of the following values: +* @arg DAC_CH0 : DAC channel 0 +* @arg DAC_CH1 : DAC channel 1 + * @param Data: next conversion data. + * @retval None + ************************************************************************************************************/ +void DAC_SetData(HT_DAC_TypeDef* HT_DACn, u8 DAC_Ch, u32 Data) +{ + HT_DACCH_TypeDef *DACnCH = (HT_DACCH_TypeDef *)((u32)&HT_DACn->DACCH0 + DAC_Ch * 8 * 4); + + /* Check the parameters */ + Assert_Param(IS_DAC(HT_DACn)); + Assert_Param(IS_DAC_CHANNEL(DAC_Ch)); + + DACnCH->DHR = Data; +} + +/*********************************************************************************************************//** + * @brief Return the data output register value of the specified DAC channel. + * @param HT_DACn: where HT_DACn is the selected DAC from the DAC peripherals. + * @param DAC_Ch: the DAC channel to configure +* This parameter can be one of the following values: +* @arg DAC_CH0 : DAC channel 0 +* @arg DAC_CH1 : DAC channel 1 + * @return The selected DAC channel data output value. + ************************************************************************************************************/ +u16 DAC_GetOutData(HT_DAC_TypeDef* HT_DACn, u8 DAC_Ch) +{ + HT_DACCH_TypeDef *DACnCH = (HT_DACCH_TypeDef *)((u32)&HT_DACn->DACCH0 + DAC_Ch * 8 * 4); + + /* Check the parameters */ + Assert_Param(IS_DAC(HT_DACn)); + Assert_Param(IS_DAC_CHANNEL(DAC_Ch)); + + return ((u16)DACnCH->DOR); +} + + +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/ht32f5xxxx_dac_dual16.c b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/ht32f5xxxx_dac_dual16.c new file mode 100644 index 0000000000..d08f0e0e78 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/ht32f5xxxx_dac_dual16.c @@ -0,0 +1,191 @@ +/*********************************************************************************************************//** + * @file ht32f5xxxx_dac_dual16.c + * @version $Rev:: 7071 $ + * @date $Date:: 2023-07-28 #$ + * @brief This file provides all the DAC firmware functions. + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ + +/* Includes ------------------------------------------------------------------------------------------------*/ +#include "ht32f5xxxx_dac_dual16.h" + +/** @addtogroup HT32F5xxxx_Peripheral_Driver HT32F5xxxx Peripheral Driver + * @{ + */ + +/** @defgroup DAC_DUAL16 DAC_DUAL16 + * @brief DAC driver modules + * @{ + */ + + +/* Private constants ---------------------------------------------------------------------------------------*/ +/** @defgroup DAC_DUAL16_Private_Define DAC private definitions + * @{ + */ +#define DAC_POS_RCH 0 +#define DAC_POS_LCH 8 + +#define DAC_TRIG_SOFTWARE_RESET (0x00000000) +#define DAC_TRIG_SOFTWARE_SET (0x00000001) + +#define DAC_RCH_RESET (0xFFFFFFFE) +#define DAC_LCH_RESET (0xFFFFFEFF) +/** + * @} + */ + +/* Private macro -------------------------------------------------------------------------------------------*/ +/** @defgroup DAC_DUAL16_Private_Macro DAC private macros + * @{ + */ +#define IS_DAC(x) (x == HT_DACDUAL16) + +#define IS_DAC_CHANNEL(CHANNEL) (((CHANNEL) == DAC_CH_R) || \ + ((CHANNEL) == DAC_CH_L)) + +#define IS_DAC_DATA_SOURCE(SOURCE) (((SOURCE) == DATA_FROM_UC) || \ + ((SOURCE) == DATA_FROM_MIDI)) + +#define IS_DAC_DATA(DATA) ((DATA) <= 0xFFFF) +/** + * @} + */ + + +/* Global functions ----------------------------------------------------------------------------------------*/ +/** @defgroup DAC_DUAL16_Exported_Functions DAC exported functions + * @{ + */ +/*********************************************************************************************************//** + * @brief Deinitialize the DAC peripheral registers to their default reset values. + * @retval None + ************************************************************************************************************/ +void DACD16_DeInit(void) +{ + RSTCU_PeripReset_TypeDef RSTCUReset = {{0}}; + + RSTCUReset.Bit.DAC0 = 1; + + RSTCU_PeripReset(RSTCUReset, ENABLE); +} + +/*********************************************************************************************************//** + * @brief Configure the data source for the DAC channel. + * @param DACx: where DACx is the selected DAC from the DAC peripherals. + * @param DAC_CH_x: the DAC channel to configure + * This parameter can be one of the following values: + * @arg DAC_CH_R : DAC Right Channel selected + * @arg DAC_CH_L : DAC Left Channel selected + * @param DATA_FROM_x: Configure the data source. + * This parameter can be one of the following values: + * @arg DATA_FROM_UC : data and control signal from uC + * @arg DATA_FROM_MIDI : data and control signal from MIDI + * @retval None + ************************************************************************************************************/ +void DACD16_DataSourceConfig(HT_DAC_DUAL16_TypeDef* DACx, DAC_Dual16_Ch DAC_CH_x, DAC_Dual16_Source DATA_FROM_x) +{ + /* Check the parameters */ + Assert_Param(IS_DAC(DACx)); + Assert_Param(IS_DAC_CHANNEL(DAC_CH_x)); + Assert_Param(IS_DAC_DATA_SOURCE(DATA_FROM_x)); + + /* Set the select channel data source */ + if (DAC_CH_x == DAC_CH_R) + { + DACx->CR &= DAC_RCH_RESET; + DACx->CR |= DATA_FROM_x << DAC_POS_RCH; + } + else + { + DACx->CR &= DAC_LCH_RESET; + DACx->CR |= DATA_FROM_x << DAC_POS_LCH; + } +} + +/*********************************************************************************************************//** + * @brief Configure the data source for the DAC channel. + * @param DACx: where DACx is the selected DAC from the DAC peripherals. + * @param DAC_CH_x: the DAC channel to configure + * This parameter can be one of the following values: + * @arg DAC_CH_R : DAC Right Channel selected + * @arg DAC_CH_L : DAC Left Channel selected + * @param Data : Data to be loaded in the selected channel data register. + * @retval None + ************************************************************************************************************/ +void DACD16_SetChannelData(HT_DAC_DUAL16_TypeDef* DACx, DAC_Dual16_Ch DAC_CH_x, u16 Data) +{ + /* Check the parameters */ + Assert_Param(IS_DAC(DACx)); + Assert_Param(IS_DAC_CHANNEL(DAC_CH_x)); + Assert_Param(IS_DAC_DATA(Data)); + + /* Set the select channel data */ + if (DAC_CH_x == DAC_CH_R) + { + DACx->RH = Data; + } + else + { + DACx->LH = Data; + } +} + +/*********************************************************************************************************//** + * @brief Enable or Disable software start of the channel conversion of the selected DAC . + * @param DACx: where DACx is the selected DAC from the DAC peripherals. + * @param DAC_CH_x: the DAC channel to configure + * This parameter can be one of the following values: + * @arg DAC_CH_R : DAC Right Channel selected + * @arg DAC_CH_L : DAC Left Channel selected + * @retval None + ************************************************************************************************************/ +void DACD16_SoftwareStartConvCmd(HT_DAC_DUAL16_TypeDef* DACx, DAC_Dual16_Ch DAC_CH_x) +{ + /* Check the parameters */ + Assert_Param(IS_DAC(DACx)); + Assert_Param(IS_DAC_CHANNEL(DAC_CH_x)); + + /* Start Conversion */ + if (DAC_CH_x == DAC_CH_R) + { + DACx->TG &= DAC_RCH_RESET ; + DACx->TG |= DAC_TRIG_SOFTWARE_SET << DAC_POS_RCH; + } + else + { + DACx->TG &= DAC_LCH_RESET; + DACx->TG |= DAC_TRIG_SOFTWARE_SET << DAC_POS_LCH; + } +} +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/ht32f5xxxx_div.c b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/ht32f5xxxx_div.c new file mode 100644 index 0000000000..6e596480d3 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/ht32f5xxxx_div.c @@ -0,0 +1,211 @@ +/*********************************************************************************************************//** + * @file ht32f5xxxx_div.c + * @version $Rev:: 6656 $ + * @date $Date:: 2023-01-16 #$ + * @brief This file provides all the DIV firmware functions. + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ + +/* Includes ------------------------------------------------------------------------------------------------*/ +#include "ht32f5xxxx_div.h" + +/** @addtogroup HT32F5xxxx_Peripheral_Driver HT32F5xxxx Peripheral Driver + * @{ + */ + +/** @defgroup DIV DIV + * @brief DIV driver modules + * @{ + */ + +/* Private constants ---------------------------------------------------------------------------------------*/ +#define DIVCR_START (0x00000001) +#define DIVCR_ZEF (0x00000004) +#define DIVCR_COM (0x00000008) + +/* Global variables ----------------------------------------------------------------------------------------*/ +u32 guRemainder; + +/* Global functions ----------------------------------------------------------------------------------------*/ +/** @defgroup DIV_Exported_Functions DIV exported functions + * @{ + */ +/*********************************************************************************************************//** + * @brief Deinitialize the DIV peripheral registers to their default reset values. + * @retval None + ************************************************************************************************************/ +void DIV_DeInit(void) +{ + RSTCU_PeripReset_TypeDef RSTCUReset = {{0}}; + + RSTCUReset.Bit.DIV = 1; + RSTCU_PeripReset(RSTCUReset, ENABLE); +} + +/*********************************************************************************************************//** + * @brief Calculate the Quotient of dividend/divisor. + * @param dividend + * @param divisor + * @retval The quotient of dividend/divisor + ************************************************************************************************************/ +s32 DIV_Div32(s32 dividend, s32 divisor) +{ + HT_DIV->DDR = dividend; + HT_DIV->DSR = divisor; + HT_DIV->CR = DIVCR_START; + + while ((HT_DIV->CR & DIVCR_COM) != DIVCR_COM); + + #if (DIV_ENABLE_DIVIDE_BY_ZERO_CHECK == 1) + { + if (DIV_IsDivByZero() == TRUE) + { + while (1); + } + } + #endif + + return (HT_DIV->QTR); +} + +/*********************************************************************************************************//** + * @brief Calculate the 32-bit unsigned of dividend/divisor. + * @param dividend + * @param divisor + * @retval The quotient of dividend/divisor + ************************************************************************************************************/ +u32 DIV_uDiv32(u32 dividend, u32 divisor) +{ + u32 uResult = 0; + guRemainder = 0; + if (dividend < divisor) + { + guRemainder = dividend; + return 0; + } + + if (dividend == divisor) + { + return 1; + } + + if (divisor & 0x80000000) + { + guRemainder = dividend - divisor; + return 1; + } + + if (dividend & 0x80000000) + { + HT_DIV->DDR = 0x7FFFFFFF; + HT_DIV->DSR = divisor; + HT_DIV->CR = DIVCR_START; + + while ((HT_DIV->CR & DIVCR_COM) != DIVCR_COM); + #if (DIV_ENABLE_DIVIDE_BY_ZERO_CHECK == 1) + { + if (DIV_IsDivByZero() == TRUE) + { + while (1); + } + } + #endif + + uResult = HT_DIV->QTR; + guRemainder = HT_DIV->RMR; + dividend -= 0x7FFFFFFF; + } + + HT_DIV->DDR = dividend; + HT_DIV->DSR = divisor; + HT_DIV->CR = DIVCR_START; + + while ((HT_DIV->CR & DIVCR_COM) != DIVCR_COM); + #if (DIV_ENABLE_DIVIDE_BY_ZERO_CHECK == 1) + { + if (DIV_IsDivByZero() == TRUE) + { + while (1); + } + } + #endif + + uResult += HT_DIV->QTR; + guRemainder += HT_DIV->RMR; + + if (guRemainder >= divisor) + { + guRemainder -= divisor; + uResult++; + } + + return uResult; +} + +/*********************************************************************************************************//** + * @brief Retuen the remainder of last unsigned dividend/divisor calculatation. + * @retval guRemainder: The remainder of dividend/divisor + ************************************************************************************************************/ +u32 DIV_uGetLastRemainder(void) +{ + return guRemainder; +} + +/*********************************************************************************************************//** + * @brief Calculate the remainder of dividend/divisor. + * @param dividend + * @param divisor + * @retval The remainder of dividend/divisor + ************************************************************************************************************/ +s32 DIV_Mod(s32 dividend, s32 divisor) +{ + DIV_Div32(dividend, divisor); + + return (HT_DIV->RMR); +} + +/*********************************************************************************************************//** + * @brief Get Divide by Zero Case. + * @retval TRUE or FALSE + ************************************************************************************************************/ +bool DIV_IsDivByZero(void) +{ + if ((HT_DIV->CR & DIVCR_ZEF) == DIVCR_ZEF) + { + return TRUE; + } + + return FALSE; +} + +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/ht32f5xxxx_ebi.c b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/ht32f5xxxx_ebi.c new file mode 100644 index 0000000000..2ea64162cd --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/ht32f5xxxx_ebi.c @@ -0,0 +1,189 @@ +/********************************************************************************************************//** + * @file ht32f5xxxx_ebi.c + * @version $Rev:: 2772 $ + * @date $Date:: 2018-05-15 #$ + * @brief This file provides all the EBI firmware functions. + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ + +/* Includes ------------------------------------------------------------------------------------------------*/ +#include "ht32f5xxxx_ebi.h" + +/** @addtogroup HT32F5xxxx_Peripheral_Driver HT32F5xxxx Peripheral Driver + * @{ + */ + +/** @defgroup EBI EBI + * @brief EBI driver modules + * @{ + */ + + +/* Global functions ----------------------------------------------------------------------------------------*/ +/** @defgroup EBI_Exported_Functions EBI exported functions + * @{ + */ +/*********************************************************************************************************//** + * @brief Deinitializes the EBI peripheral registers to their default reset values. + * @retval None + ************************************************************************************************************/ +void EBI_DeInit(void) +{ + RSTCU_PeripReset_TypeDef RSTCUReset = {{0}}; + + RSTCUReset.Bit.EBI = 1; + RSTCU_PeripReset(RSTCUReset, ENABLE); +} + +/*********************************************************************************************************//** + * @brief Initializes the EBI peripheral according to the specified parameters in the EBI_InitStruct. + * @param EBI_InitStruct: pointer to a EBI_InitTypeDef structure. + * @retval None + ************************************************************************************************************/ +void EBI_Init(EBI_InitTypeDef* EBI_InitStruct) +{ + u32 tmp; + u32 bank = EBI_InitStruct->EBI_Bank; + + /* Check the parameters */ + Assert_Param(IS_EBI_BANK(EBI_InitStruct->EBI_Bank)); + Assert_Param(IS_EBI_MODE(EBI_InitStruct->EBI_Mode)); + Assert_Param(IS_EBI_IDLECYCLE(EBI_InitStruct->EBI_IdleCycle)); + Assert_Param(IS_EBI_CS_POLARITY(EBI_InitStruct->EBI_ChipSelectPolarity)); + Assert_Param(IS_EBI_ALE_POLARITY(EBI_InitStruct->EBI_AddressLatchPolarity)); + Assert_Param(IS_EBI_WE_POLARITY(EBI_InitStruct->EBI_WriteEnablePolarity)); + Assert_Param(IS_EBI_RE_POLARITY(EBI_InitStruct->EBI_ReadEnablePolarity)); + Assert_Param(IS_EBI_IDLE_CYCLE_TIME(EBI_InitStruct->EBI_IdleCycleTime)); + Assert_Param(IS_EBI_ADDRESS_SETUP_TIME(EBI_InitStruct->EBI_AddressSetupTime)); + Assert_Param(IS_EBI_ADDRESS_HOLD_TIME(EBI_InitStruct->EBI_AddressHoldTime)); + Assert_Param(IS_EBI_WRITE_SETUP_TIME(EBI_InitStruct->EBI_WriteSetupTime)); + Assert_Param(IS_EBI_WRITE_STROBE_TIME(EBI_InitStruct->EBI_WriteStrobeTime)); + Assert_Param(IS_EBI_WRITE_HOLD_TIME(EBI_InitStruct->EBI_WriteHoldTime)); + Assert_Param(IS_EBI_READ_SETUP_TIME(EBI_InitStruct->EBI_ReadSetupTime)); + Assert_Param(IS_EBI_READ_STROBE_TIME(EBI_InitStruct->EBI_ReadStrobeTime)); + + HT_EBI->ATR = EBI_InitStruct->EBI_AddressSetupTime | + (EBI_InitStruct->EBI_AddressHoldTime << 8); + HT_EBI->RTR = EBI_InitStruct->EBI_ReadSetupTime | + (EBI_InitStruct->EBI_ReadStrobeTime << 8) | + (EBI_InitStruct->EBI_ReadHoldTime << 16); + + HT_EBI->WTR = EBI_InitStruct->EBI_WriteSetupTime | + (EBI_InitStruct->EBI_WriteStrobeTime << 8) | + (EBI_InitStruct->EBI_WriteHoldTime << 16); + HT_EBI->PR = EBI_InitStruct->EBI_ChipSelectPolarity | + (EBI_InitStruct->EBI_ReadEnablePolarity << 1) | + (EBI_InitStruct->EBI_WriteEnablePolarity << 2) | + (EBI_InitStruct->EBI_AddressLatchPolarity << 3); + + + /*------------------------- EBI Control Register Configuration -------------------------------------------*/ + tmp = (3 << (bank * 2)) | (0x00001000 << bank) | + (0x00010000 << (bank * 2)) | (0x00020000 << (bank * 2)) | + (0x01000000 << bank); + tmp = HT_EBI->CR & (~tmp); + HT_EBI->CR = (EBI_InitStruct->EBI_Mode << (bank * 2)) | + (EBI_InitStruct->EBI_IdleCycle << bank) | + (EBI_InitStruct->EBI_IdleCycleTime << 28) | tmp; +} + +/*********************************************************************************************************//** + * @brief Fills each EBI_InitStruct member with its default value. + * @param EBI_InitStruct: pointer to an EBI_InitTypeDef structure. + * @retval None + ************************************************************************************************************/ +void EBI_StructInit(EBI_InitTypeDef* EBI_InitStruct) +{ + /* Initialize the EBI structure parameters values */ + EBI_InitStruct->EBI_Bank = EBI_BANK_0; + EBI_InitStruct->EBI_Mode = EBI_MODE_D8A8; + EBI_InitStruct->EBI_IdleCycle = EBI_IDLECYCLE_DISABLE; + EBI_InitStruct->EBI_ChipSelectPolarity = EBI_CHIPSELECTPOLARITY_LOW; + EBI_InitStruct->EBI_AddressLatchPolarity = EBI_ADDRESSLATCHPOLARITY_LOW; + EBI_InitStruct->EBI_WriteEnablePolarity = EBI_WRITEENABLEPOLARITY_LOW; + EBI_InitStruct->EBI_ReadEnablePolarity = EBI_READENABLEPOLARITY_LOW; + EBI_InitStruct->EBI_IdleCycleTime = 0xF; + EBI_InitStruct->EBI_AddressSetupTime = 0xF; + EBI_InitStruct->EBI_AddressHoldTime = 0xF; + EBI_InitStruct->EBI_WriteSetupTime = 0xF; + EBI_InitStruct->EBI_WriteStrobeTime = 0x3F; + EBI_InitStruct->EBI_WriteHoldTime = 0xF; + EBI_InitStruct->EBI_ReadSetupTime = 0xF; + EBI_InitStruct->EBI_ReadStrobeTime = 0x3F; + EBI_InitStruct->EBI_ReadHoldTime = 0xF; +} + +/*********************************************************************************************************//** + * @brief Enable or Disable the EBI peripheral. + * @param EBI_Bank: EBI Bank. + * This parameter can be one of the following values: + * @arg EBI_BANK_0 : EBI Bank 0 + * @arg EBI_BANK_1 : EBI Bank 1 + * @arg EBI_BANK_2 : EBI Bank 2 + * @arg EBI_BANK_3 : EBI Bank 3 + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void EBI_Cmd(u32 EBI_Bank, ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_EBI_BANK(EBI_Bank)); + Assert_Param(IS_CONTROL_STATUS(NewState)); + + if (NewState != DISABLE) + { + HT_EBI->CR |= (0x100 << EBI_Bank); + } + else + { + HT_EBI->CR &= ~(0x100 << EBI_Bank); + } +} + +/*********************************************************************************************************//** + * @brief Check whether the specified EBI busy flag has been set. + * @retval SET or RESET + ************************************************************************************************************/ +FlagStatus EBI_GetBusyStatus(void) +{ + if (HT_EBI->SR & 0x1) + { + return SET; + } + else + { + return RESET; + } +} + +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/ht32f5xxxx_exti.c b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/ht32f5xxxx_exti.c new file mode 100644 index 0000000000..5ecc7ef97f --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/ht32f5xxxx_exti.c @@ -0,0 +1,548 @@ +/*********************************************************************************************************//** + * @file ht32f5xxxx_exti.c + * @version $Rev:: 6745 $ + * @date $Date:: 2023-02-23 #$ + * @brief This file provides all the EXTI firmware functions. + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ + +/* Includes ------------------------------------------------------------------------------------------------*/ +#include "ht32f5xxxx_exti.h" + +/** @addtogroup HT32F5xxxx_Peripheral_Driver HT32F5xxxx Peripheral Driver + * @{ + */ + +/** @defgroup EXTI EXTI + * @brief EXTI driver modules + * @{ + */ + + +/* Private constants ---------------------------------------------------------------------------------------*/ +/** @defgroup EXTI_Private_Define EXTI private definitions + * @{ + */ +/* EXTI EVWUPIEN mask */ +#define WAKUPCR_EVWUPIEN_SET ((u32)0x80000000) +#define WAKUPCR_EVWUPIEN_RESET ((u32)0x7FFFFFFF) + +#if (LIBCFG_EXTI_8CH) + const IRQn_Type gEXTIn_IRQn[16] = { + EXTI0_IRQn, EXTI1_IRQn, EXTI2_IRQn, EXTI3_IRQn, + EXTI4_IRQn, EXTI5_IRQn, EXTI6_IRQn, EXTI7_IRQn, + EXTI0_IRQn, EXTI1_IRQn, EXTI2_IRQn, EXTI3_IRQn, + EXTI4_IRQn, EXTI5_IRQn, EXTI6_IRQn, EXTI7_IRQn, + }; +#else + const IRQn_Type gEXTIn_IRQn[16] = { + EXTI0_IRQn, EXTI1_IRQn, EXTI2_IRQn, EXTI3_IRQn, + EXTI4_IRQn, EXTI5_IRQn, EXTI6_IRQn, EXTI7_IRQn, + EXTI8_IRQn, EXTI9_IRQn, EXTI10_IRQn, EXTI11_IRQn, + EXTI12_IRQn, EXTI13_IRQn, EXTI14_IRQn, EXTI15_IRQn, + }; +#endif +/** + * @} + */ + +/* Global functions ----------------------------------------------------------------------------------------*/ +/** @defgroup EXTI_Exported_Functions EXTI exported functions + * @{ + */ +/*********************************************************************************************************//** + * @brief Deinitialize the EXTI peripheral registers. + * @param EXTI_Channel: can be 0, 1 to 15 to select the EXTI Channel. + * This parameter can be one of the following values: + * @arg EXTI_CHANNEL_0 + * @arg EXTI_CHANNEL_1 + * @arg EXTI_CHANNEL_2 + * @arg EXTI_CHANNEL_3 + * @arg EXTI_CHANNEL_4 + * @arg EXTI_CHANNEL_5 + * @arg EXTI_CHANNEL_6 + * @arg EXTI_CHANNEL_7 + * @arg EXTI_CHANNEL_8 + * @arg EXTI_CHANNEL_9 + * @arg EXTI_CHANNEL_10 + * @arg EXTI_CHANNEL_11 + * @arg EXTI_CHANNEL_12 + * @arg EXTI_CHANNEL_13 + * @arg EXTI_CHANNEL_14 + * @arg EXTI_CHANNEL_15 + * @retval None + ************************************************************************************************************/ +void EXTI_DeInit(u32 EXTI_Channel) +{ + u32 tmp; + + /* Check the parameters */ + Assert_Param(IS_EXTI_CHANNEL(EXTI_Channel)); + + tmp = 1 << EXTI_Channel; + + *((u32 *) HT_EXTI + EXTI_Channel) = 0x0; + HT_EXTI->CR &= (~tmp); + HT_EXTI->EDGEFLGR = tmp; + HT_EXTI->EDGESR = tmp; + HT_EXTI->SSCR &= (~tmp); + HT_EXTI->WAKUPCR &= (~tmp); + HT_EXTI->WAKUPPOLR &= (~tmp); + HT_EXTI->WAKUPFLG = tmp; +} + +/*********************************************************************************************************//** + * @brief Initialize the EXTI peripheral. + * @param EXTI_InitStruct: pointer to a EXTI_InitTypeDef structure. + * @retval None + ************************************************************************************************************/ +void EXTI_Init(EXTI_InitTypeDef* EXTI_InitStruct) +{ + u32 regval; + + /* Check the parameters */ + Assert_Param(IS_EXTI_CHANNEL(EXTI_InitStruct->EXTI_Channel)); + Assert_Param(IS_EXTI_DEBOUNCE_TYPE(EXTI_InitStruct->EXTI_Debounce)); + Assert_Param(IS_EXTI_DEBOUNCE_SIZE(EXTI_InitStruct->EXTI_DebounceCnt)); + Assert_Param(IS_EXTI_INT_TYPE(EXTI_InitStruct->EXTI_IntType)); + + /* Set EXTI interrupt configuration */ + regval = (EXTI_InitStruct->EXTI_Debounce << 31) | (EXTI_InitStruct->EXTI_IntType << 28) | (EXTI_InitStruct->EXTI_DebounceCnt); + *((u32 *) HT_EXTI + EXTI_InitStruct->EXTI_Channel) = regval; +} + +/*********************************************************************************************************//** + * @brief Enable or Disable the specified EXTI channelx interrupts. + * @param EXTI_Channel: specify the EXTI channel. + * This parameter can be one of the following values: + * @arg EXTI_CHANNEL_0 + * @arg EXTI_CHANNEL_1 + * @arg EXTI_CHANNEL_2 + * @arg EXTI_CHANNEL_3 + * @arg EXTI_CHANNEL_4 + * @arg EXTI_CHANNEL_5 + * @arg EXTI_CHANNEL_6 + * @arg EXTI_CHANNEL_7 + * @arg EXTI_CHANNEL_8 + * @arg EXTI_CHANNEL_9 + * @arg EXTI_CHANNEL_10 + * @arg EXTI_CHANNEL_11 + * @arg EXTI_CHANNEL_12 + * @arg EXTI_CHANNEL_13 + * @arg EXTI_CHANNEL_14 + * @arg EXTI_CHANNEL_15 + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void EXTI_IntConfig(u32 EXTI_Channel, ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_EXTI_CHANNEL(EXTI_Channel)); + Assert_Param(IS_CONTROL_STATUS(NewState)); + + /* Configure EXTI interrupt */ + if (NewState == ENABLE) + { + HT_EXTI->CR |= (1 << EXTI_Channel); + } + else + { + HT_EXTI->CR &= ~(1 << EXTI_Channel); + } +} + +#if (LIBCFG_EXTI_DEBCNTPRE) +/*********************************************************************************************************//** + * @brief Configure the Debounce Counter prescaler. + * @param EXTI_DebCntPre_DIVn: specify the prescaler value. + * This parameter can be one of the following values: + * @arg EXTI_DBCNTPRE_DIV1 : CK_DBCNT = EXTI_PCLK / 1 + * @arg EXTI_DBCNTPRE_DIV2 : CK_DBCNT = EXTI_PCLK / 2 + * @arg EXTI_DBCNTPRE_DIV4 : CK_DBCNT = EXTI_PCLK / 4 + * @arg EXTI_DBCNTPRE_DIV8 : CK_DBCNT = EXTI_PCLK / 8 + * @arg EXTI_DBCNTPRE_DIV16 : CK_DBCNT = EXTI_PCLK / 16 + * @arg EXTI_DBCNTPRE_DIV32 : CK_DBCNT = EXTI_PCLK / 32 + * @arg EXTI_DBCNTPRE_DIV64 : CK_DBCNT = EXTI_PCLK / 64 + * @arg EXTI_DBCNTPRE_DIV128 : CK_DBCNT = EXTI_PCLK / 128 + * @retval None + ************************************************************************************************************/ +void EXTI_SetDebounceCounterPrescaler(EXTI_DebCntPre_TypeDef EXTI_DBCNTPRE_DIVn) +{ + /* Check the parameters */ + Assert_Param(IS_EXTI_DEBOUNCE_COUNTER_PRESCALER(EXTI_DBCNTPRE_DIVn)); + + HT_EXTI->CFGR0 = ((HT_EXTI->CFGR0 & 0xF8FFFFFF) | (EXTI_DBCNTPRE_DIVn << 24)); +} +#endif + +/*********************************************************************************************************//** + * @brief Configure the EXTI channelx event wakeup function. + * @param EXTI_Channel: specify the EXTI channel. + * This parameter can be one of the following values: + * @arg EXTI_CHANNEL_0 + * @arg EXTI_CHANNEL_1 + * @arg EXTI_CHANNEL_2 + * @arg EXTI_CHANNEL_3 + * @arg EXTI_CHANNEL_4 + * @arg EXTI_CHANNEL_5 + * @arg EXTI_CHANNEL_6 + * @arg EXTI_CHANNEL_7 + * @arg EXTI_CHANNEL_8 + * @arg EXTI_CHANNEL_9 + * @arg EXTI_CHANNEL_10 + * @arg EXTI_CHANNEL_11 + * @arg EXTI_CHANNEL_12 + * @arg EXTI_CHANNEL_13 + * @arg EXTI_CHANNEL_14 + * @arg EXTI_CHANNEL_15 + * @param EXTI_WakeUpType: determines the type of signal to trigger EXTI interrupt. + * This parameter can be one of the following values: + * @arg EXTI_WAKEUP_HIGH_LEVEL + * @arg EXTI_WAKEUP_LOW_LEVEL + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void EXTI_WakeupEventConfig(u32 EXTI_Channel, u8 EXTI_WakeUpType, ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_EXTI_CHANNEL(EXTI_Channel)); + Assert_Param(IS_EXTI_WAKEUP_TYPE(EXTI_WakeUpType)); + Assert_Param(IS_CONTROL_STATUS(NewState)); + + if (NewState == ENABLE) + { + if (EXTI_WakeUpType == EXTI_WAKEUP_HIGH_LEVEL) + { + HT_EXTI->WAKUPPOLR &= ~(1 << EXTI_Channel); + } + else + { + HT_EXTI->WAKUPPOLR |= (1 << EXTI_Channel); + } + + HT_EXTI->WAKUPCR |= (1 << EXTI_Channel); + } + else + { + HT_EXTI->WAKUPCR &= ~(1 << EXTI_Channel); + } +} + +/*********************************************************************************************************//** + * @brief Enable or Disable the EXTI channelx event wakeup interrupt. + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void EXTI_WakeupEventIntConfig(ControlStatus NewState) +{ + if (NewState == ENABLE) + { + /* Set EVWUPIEN bit */ + HT_EXTI->WAKUPCR |= WAKUPCR_EVWUPIEN_SET; + } + else + { + /* Clear EVWUPIEN bit */ + HT_EXTI->WAKUPCR &= WAKUPCR_EVWUPIEN_RESET; + } +} + +/*********************************************************************************************************//** + * @brief Clear the specified EXTI channelx edge flag. + * @param EXTI_Channel: specify the EXTI channel. + * This parameter can be one of the following values: + * @arg EXTI_CHANNEL_0 + * @arg EXTI_CHANNEL_1 + * @arg EXTI_CHANNEL_2 + * @arg EXTI_CHANNEL_3 + * @arg EXTI_CHANNEL_4 + * @arg EXTI_CHANNEL_5 + * @arg EXTI_CHANNEL_6 + * @arg EXTI_CHANNEL_7 + * @arg EXTI_CHANNEL_8 + * @arg EXTI_CHANNEL_9 + * @arg EXTI_CHANNEL_10 + * @arg EXTI_CHANNEL_11 + * @arg EXTI_CHANNEL_12 + * @arg EXTI_CHANNEL_13 + * @arg EXTI_CHANNEL_14 + * @arg EXTI_CHANNEL_15 + * @retval None + ************************************************************************************************************/ +void EXTI_ClearEdgeFlag(u32 EXTI_Channel) +{ + u32 tmp; + + /* Check the parameters */ + Assert_Param(IS_EXTI_CHANNEL(EXTI_Channel)); + + tmp = 1 << EXTI_Channel; + + /* Write 1 to clear both edge detection flag */ + HT_EXTI->EDGEFLGR = tmp; + /* Write 1 to clear positive edge detection flag */ + HT_EXTI->EDGESR = tmp; +} + +/*********************************************************************************************************//** + * @brief Clear the specified EXTI channelx wakeup flag. + * @param EXTI_Channel: specify the EXTI channel. + * This parameter can be one of the following values: + * @arg EXTI_CHANNEL_0 + * @arg EXTI_CHANNEL_1 + * @arg EXTI_CHANNEL_2 + * @arg EXTI_CHANNEL_3 + * @arg EXTI_CHANNEL_4 + * @arg EXTI_CHANNEL_5 + * @arg EXTI_CHANNEL_6 + * @arg EXTI_CHANNEL_7 + * @arg EXTI_CHANNEL_8 + * @arg EXTI_CHANNEL_9 + * @arg EXTI_CHANNEL_10 + * @arg EXTI_CHANNEL_11 + * @arg EXTI_CHANNEL_12 + * @arg EXTI_CHANNEL_13 + * @arg EXTI_CHANNEL_14 + * @arg EXTI_CHANNEL_15 + * @retval None + ************************************************************************************************************/ +void EXTI_ClearWakeupFlag(u32 EXTI_Channel) +{ + /* Check the parameters */ + Assert_Param(IS_EXTI_CHANNEL(EXTI_Channel)); + + /* Write 1 to clear wake up flag */ + HT_EXTI->WAKUPFLG = 1 << EXTI_Channel; + + /*--------------------------------------------------------------------------------------------------------*/ + /* DSB instruction is added in this function to ensure the write operation which is for clearing interrupt*/ + /* flag is actually completed before exiting ISR. It prevents the NVIC from detecting the interrupt again */ + /* since the write register operation may be pended in the internal write buffer of Cortex-Mx when program*/ + /* has exited interrupt routine. This DSB instruction may be masked if this function is called in the */ + /* beginning of ISR and there are still some instructions before exiting ISR. */ + /*--------------------------------------------------------------------------------------------------------*/ + __DSB(); +} + +/*********************************************************************************************************//** + * @brief Get the specified EXTI channelx edge flag. + * @param EXTI_Channel: specify the EXTI channel. + * This parameter can be one of the following values: + * @arg EXTI_CHANNEL_0 + * @arg EXTI_CHANNEL_1 + * @arg EXTI_CHANNEL_2 + * @arg EXTI_CHANNEL_3 + * @arg EXTI_CHANNEL_4 + * @arg EXTI_CHANNEL_5 + * @arg EXTI_CHANNEL_6 + * @arg EXTI_CHANNEL_7 + * @arg EXTI_CHANNEL_8 + * @arg EXTI_CHANNEL_9 + * @arg EXTI_CHANNEL_10 + * @arg EXTI_CHANNEL_11 + * @arg EXTI_CHANNEL_12 + * @arg EXTI_CHANNEL_13 + * @arg EXTI_CHANNEL_14 + * @arg EXTI_CHANNEL_15 + * @retval SET or RESET + ************************************************************************************************************/ +FlagStatus EXTI_GetEdgeFlag(u32 EXTI_Channel) +{ + /* Check the parameters */ + Assert_Param(IS_EXTI_CHANNEL(EXTI_Channel)); + + return ((HT_EXTI->EDGEFLGR & (1UL << EXTI_Channel)) ? SET : RESET); +} + +/*********************************************************************************************************//** + * @brief Get the specified EXTI channelx edge status. + * @param EXTI_Channel: specify the EXTI channel. + * This parameter can be one of the following values: + * @arg EXTI_CHANNEL_0 + * @arg EXTI_CHANNEL_1 + * @arg EXTI_CHANNEL_2 + * @arg EXTI_CHANNEL_3 + * @arg EXTI_CHANNEL_4 + * @arg EXTI_CHANNEL_5 + * @arg EXTI_CHANNEL_6 + * @arg EXTI_CHANNEL_7 + * @arg EXTI_CHANNEL_8 + * @arg EXTI_CHANNEL_9 + * @arg EXTI_CHANNEL_10 + * @arg EXTI_CHANNEL_11 + * @arg EXTI_CHANNEL_12 + * @arg EXTI_CHANNEL_13 + * @arg EXTI_CHANNEL_14 + * @arg EXTI_CHANNEL_15 + * @param EXTI_Edge: can be status of edge that user want to monitor. + * This parameter can be one of the following values: + * @arg EXTI_EDGE_POSITIVE + * @arg EXTI_EDGE_NEGATIVE + * @retval SET or RESET + ************************************************************************************************************/ +FlagStatus EXTI_GetEdgeStatus(u32 EXTI_Channel, u32 EXTI_Edge) +{ + /* Check the parameters */ + Assert_Param(IS_EXTI_CHANNEL(EXTI_Channel)); + Assert_Param(IS_EXTI_EDGE(EXTI_Edge)); + + if (HT_EXTI->EDGEFLGR & (1UL << EXTI_Channel)) + { + if (GetBit_BB((u32)&HT_EXTI->EDGESR, EXTI_Channel) ^ EXTI_Edge) + { + return SET; + } + else + { + return RESET; + } + } + else + { + return RESET; + } +} + +/*********************************************************************************************************//** + * @brief Get the specified EXTI channelx wakeup flag. + * @param EXTI_Channel: specify the EXTI channel. + * This parameter can be one of the following values: + * @arg EXTI_CHANNEL_0 + * @arg EXTI_CHANNEL_1 + * @arg EXTI_CHANNEL_2 + * @arg EXTI_CHANNEL_3 + * @arg EXTI_CHANNEL_4 + * @arg EXTI_CHANNEL_5 + * @arg EXTI_CHANNEL_6 + * @arg EXTI_CHANNEL_7 + * @arg EXTI_CHANNEL_8 + * @arg EXTI_CHANNEL_9 + * @arg EXTI_CHANNEL_10 + * @arg EXTI_CHANNEL_11 + * @arg EXTI_CHANNEL_12 + * @arg EXTI_CHANNEL_13 + * @arg EXTI_CHANNEL_14 + * @arg EXTI_CHANNEL_15 + * @retval SET or RESET + ************************************************************************************************************/ +FlagStatus EXTI_GetWakeupFlagStatus(u32 EXTI_Channel) +{ + /* Check the parameters */ + Assert_Param(IS_EXTI_CHANNEL(EXTI_Channel)); + + if (HT_EXTI->WAKUPFLG & (1 << EXTI_Channel)) + { + return SET; + } + else + { + return RESET; + } +} + +/*********************************************************************************************************//** + * @brief Activate or Deactivate an EXTI channelx interrupt by software. + * @param EXTI_Channel: specify the EXTI channel. + * This parameter can be one of the following values: + * @arg EXTI_CHANNEL_0 + * @arg EXTI_CHANNEL_1 + * @arg EXTI_CHANNEL_2 + * @arg EXTI_CHANNEL_3 + * @arg EXTI_CHANNEL_4 + * @arg EXTI_CHANNEL_5 + * @arg EXTI_CHANNEL_6 + * @arg EXTI_CHANNEL_7 + * @arg EXTI_CHANNEL_8 + * @arg EXTI_CHANNEL_9 + * @arg EXTI_CHANNEL_10 + * @arg EXTI_CHANNEL_11 + * @arg EXTI_CHANNEL_12 + * @arg EXTI_CHANNEL_13 + * @arg EXTI_CHANNEL_14 + * @arg EXTI_CHANNEL_15 + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void EXTI_SWIntCmd(u32 EXTI_Channel, ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_EXTI_CHANNEL(EXTI_Channel)); + Assert_Param(IS_CONTROL_STATUS(NewState)); + + if (NewState == ENABLE) + { + HT_EXTI->SSCR = 1 << EXTI_Channel; + } + else + { + HT_EXTI->SSCR &= ~(1 << EXTI_Channel); + } +} + +/*********************************************************************************************************//** + * @brief Get the specified EXTI channelx software command register bit. + * @param EXTI_Channel: specify the EXTI channel. + * This parameter can be one of the following values: + * @arg EXTI_CHANNEL_0 + * @arg EXTI_CHANNEL_1 + * @arg EXTI_CHANNEL_2 + * @arg EXTI_CHANNEL_3 + * @arg EXTI_CHANNEL_4 + * @arg EXTI_CHANNEL_5 + * @arg EXTI_CHANNEL_6 + * @arg EXTI_CHANNEL_7 + * @arg EXTI_CHANNEL_8 + * @arg EXTI_CHANNEL_9 + * @arg EXTI_CHANNEL_10 + * @arg EXTI_CHANNEL_11 + * @arg EXTI_CHANNEL_12 + * @arg EXTI_CHANNEL_13 + * @arg EXTI_CHANNEL_14 + * @arg EXTI_CHANNEL_15 + * @retval SET or RESET + ************************************************************************************************************/ +FlagStatus EXTI_GetSWCmdStatus(u32 EXTI_Channel) +{ + /* Check the parameters */ + Assert_Param(IS_EXTI_CHANNEL(EXTI_Channel)); + + if (HT_EXTI->SSCR & (1 << EXTI_Channel)) + { + return SET; + } + else + { + return RESET; + } +} +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/ht32f5xxxx_flash.c b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/ht32f5xxxx_flash.c new file mode 100644 index 0000000000..18e04c04fa --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/ht32f5xxxx_flash.c @@ -0,0 +1,471 @@ +/*********************************************************************************************************//** + * @file ht32f5xxxx_flash.c + * @version $Rev:: 6657 $ + * @date $Date:: 2023-01-16 #$ + * @brief This file provides all the FLASH firmware functions. + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ + +/* Includes ------------------------------------------------------------------------------------------------*/ +#include "ht32f5xxxx_flash.h" + +/** @addtogroup HT32F5xxxx_Peripheral_Driver HT32F5xxxx Peripheral Driver + * @{ + */ + +/** @defgroup FLASH FLASH + * @brief FLASH driver modules + * @{ + */ + + +/* Private constants ---------------------------------------------------------------------------------------*/ +/** @defgroup FLASH_Private_Define FLASH private definitions + * @{ + */ + +/* Delay definition */ +#define FLASH_TIMEOUT (0x000FFFFF) + +/* FLASH OCMR */ +#define FLASH_CMD_STADNBY (0x00000000) +#define FLASH_CMD_PROGRAM (0x00000004) +#define FLASH_CMD_PAGEERASE (0x00000008) +#define FLASH_CMD_MASSERASE (0x0000000A) + +/* FLASH OPCR */ +#define FLASH_READY (0x6UL << 1) +#define FLASH_SEND_MAIN (0x00000014) + +/* FLASH CFCR */ +#define CFCR_WAIT_MASK (0xFFFFFFF8) + +#if (LIBCFG_FMC_PREFETCH) +#define FLASH_PREFETCHBUF_ON (0x00000010) +#define FLASH_PREFETCHBUF_OFF (0xFFFFFFEF) +#endif + +#if (LIBCFG_FMC_BRANCHCACHE) +#define FLASH_BRANCHCACHE_ON (0x00001000) +#define FLASH_BRANCHCACHE_OFF (0xFFFFEFFF) +#endif + +#define FLASH_CFCR_MASK (0xFFFFEFE8) +#define FLASH_PREFETCHBUF_AND_BRANCHCACHE_ON (0x00001010) +#define FLASH_PREFETCHBUF_AND_BRANCHCACHE_OFF (0xFFFFEFEF) + +/** + * @} + */ + +/* Private macro -------------------------------------------------------------------------------------------*/ +/** @defgroup FLASH_Private_Macro FLASH private macros + * @{ + */ + +#if (LIBCFG_FMC_PREFETCH) +/** + * @brief Check parameter of the FLASH wait state. + */ +#if (LIBCFG_FMC_WAIT_STATE_2) +#define IS_WAIT_STATE2(x) (x == FLASH_WAITSTATE_2) +#else +#define IS_WAIT_STATE2(x) (0) +#endif + +#define IS_FLASH_WAITSTATE(WAIT) ((WAIT == FLASH_WAITSTATE_0) || \ + (WAIT == FLASH_WAITSTATE_1) || \ + (IS_WAIT_STATE2(WAIT))) +#endif +/** + * @brief Check parameter of the FLASH vector mapping. + */ +#define IS_FLASH_VECTOR_MODE(MODE) ((MODE == FLASH_BOOT_LOADER) || \ + (MODE == FLASH_BOOT_MAIN)) +/** + * @brief Check parameter of the FLASH address. + */ +#define IS_FLASH_ADDRESS(ADDRESS) (ADDRESS < 0x20000000) /* Code 0.5GB Area */ + +/** + * @brief Check parameter of the FLASH interrupt status. + */ +#define IS_FLASH_WC_FLAG(FLAG) ((FLAG & 0x0000001F) != 0) + +/** + * @brief Check parameter of the FLASH interrupt flag. + */ +#define IS_FLASH_FLAG(FLAG) ((FLAG & 0x0003001F) != 0) + +/** + * @brief Check parameter of the FLASH interrupt. + */ +#define IS_FLASH_INT(IT) ((IT & 0x0000001F) != 0) + +/** + * @} + */ + +/* Global functions ----------------------------------------------------------------------------------------*/ +/** @defgroup FLASH_Exported_Functions FLASH exported functions + * @{ + */ +#if (LIBCFG_FMC_PREFETCH) +/*********************************************************************************************************//** + * @brief Configure the FLASH wait state. + * @param FLASH_WAITSTATE_n: Setting of FLASH wait state. + * This parameter can be one of the following values: + * @arg \ref FLASH_WAITSTATE_0 : zero wait state + * @arg \ref FLASH_WAITSTATE_1 : one wait state + * @arg \ref FLASH_WAITSTATE_2 : two wait state + * @retval None + ************************************************************************************************************/ +void FLASH_SetWaitState(u32 FLASH_WAITSTATE_n) +{ + u32 uCFCR; + /* Check the parameters */ + Assert_Param(IS_FLASH_WAITSTATE(FLASH_WAITSTATE_n)); + + /* !!! NOTICE !!! + Before changing wait state, both Pre-fetch function and Branch Cache function must be disabled. + */ + uCFCR = HT_FLASH->CFCR; /* Backup previous settings. */ + + /* Disable Pre-fetch function and Branch Cache. */ + HT_FLASH->CFCR = uCFCR & FLASH_PREFETCHBUF_AND_BRANCHCACHE_OFF; + /* Change wait state. */ + HT_FLASH->CFCR = (uCFCR & FLASH_CFCR_MASK) | FLASH_WAITSTATE_n; + /* Restore previous settings. */ + HT_FLASH->CFCR |= uCFCR & (FLASH_PREFETCHBUF_AND_BRANCHCACHE_ON); +} + +/*********************************************************************************************************//** + * @brief Enable or Disable FLASH pre-fetch buffer. + * @param NewState: This parameter can be ENABLE or DISABLE + * @retval None + ************************************************************************************************************/ +void FLASH_PrefetchBufferCmd(ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_CONTROL_STATUS(NewState)); + + if (NewState != DISABLE) + { + HT_FLASH->CFCR |= FLASH_PREFETCHBUF_ON; + } + else + { + HT_FLASH->CFCR &= FLASH_PREFETCHBUF_OFF; + } +} +#endif + +#if (LIBCFG_FMC_BRANCHCACHE) +/*********************************************************************************************************//** + * @brief Enable or Disable FLASH branch cache. + * @param NewState: This parameter can be ENABLE or DISABLE + * @retval None + ************************************************************************************************************/ +void FLASH_BranchCacheCmd(ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_CONTROL_STATUS(NewState)); + + if (NewState != DISABLE) + { + HT_FLASH->CFCR |= FLASH_BRANCHCACHE_ON; + } + else + { + HT_FLASH->CFCR &= FLASH_BRANCHCACHE_OFF; + } +} +#endif + +/*********************************************************************************************************//** + * @brief Set vector remapping mode. + * @param FLASH_BOOT_x: Booting mode. + * This parameter can be one of the following values: + * @arg \ref FLASH_BOOT_LOADER : Boot loader mode + * @arg \ref FLASH_BOOT_MAIN : Main FLASH mode + * @retval None + ************************************************************************************************************/ +void FLASH_SetRemappingMode(FLASH_Vector FLASH_BOOT_x) +{ + /* Check the parameters */ + Assert_Param(IS_FLASH_VECTOR_MODE(FLASH_BOOT_x)); + + HT_FLASH->VMCR = FLASH_BOOT_x; +} + +/*********************************************************************************************************//** + * @brief Erase a specific FLASH page. + * @param PageAddress: Address of the erased page. + * @retval FLASH_State + * - \ref FLASH_COMPLETE + * - \ref FLASH_TIME_OUT + * - \ref FLASH_ERR_WRITE_PROTECTED + * - \ref FLASH_ERR_ADDR_OUT_OF_RANGE + * @note HSI must keep turn on when doing the Flash operation (Erase/Program). + ************************************************************************************************************/ +FLASH_State FLASH_ErasePage(u32 PageAddress) +{ + /* Check the parameters */ + Assert_Param(IS_FLASH_ADDRESS(PageAddress)); + + HT_FLASH->TADR = PageAddress; + HT_FLASH->OCMR = FLASH_CMD_PAGEERASE; + + return FLASH_WaitForOperationEnd(); +} + +/*********************************************************************************************************//** + * @brief Erase FLASH Option Byte page. + * @retval FLASH_State + * - \ref FLASH_COMPLETE + * - \ref FLASH_TIME_OUT + * - \ref FLASH_ERR_WRITE_PROTECTED + * @note HSI must keep turn on when doing the Flash operation (Erase/Program). + ************************************************************************************************************/ +FLASH_State FLASH_EraseOptionByte(void) +{ + return FLASH_ErasePage(OPTION_BYTE_BASE); +} + +/*********************************************************************************************************//** + * @brief Erase the entire FLASH. + * @retval FLASH_State + * - \ref FLASH_COMPLETE + * - \ref FLASH_TIME_OUT + * @note HSI must keep turn on when doing the Flash operation (Erase/Program). + ************************************************************************************************************/ +FLASH_State FLASH_MassErase(void) +{ + HT_FLASH->OCMR = FLASH_CMD_MASSERASE; + + return FLASH_WaitForOperationEnd(); +} + +/*********************************************************************************************************//** + * @brief Program one word data. + * @param Address: The specific FLASH address to be programmed. + * @param Data: The specific FLASH data to be programmed. + * @retval FLASH_State + * - \ref FLASH_COMPLETE + * - \ref FLASH_TIME_OUT + * - \ref FLASH_ERR_WRITE_PROTECTED + * - \ref FLASH_ERR_ADDR_OUT_OF_RANGE + * @note HSI must keep turn on when doing the Flash operation (Erase/Program). + ************************************************************************************************************/ +FLASH_State FLASH_ProgramWordData(u32 Address, u32 Data) +{ + /* Check the parameters */ + Assert_Param(IS_FLASH_ADDRESS(Address)); + + HT_FLASH->TADR = Address; + HT_FLASH->WRDR = Data; + HT_FLASH->OCMR = FLASH_CMD_PROGRAM; + + return FLASH_WaitForOperationEnd(); +} + +/*********************************************************************************************************//** + * @brief Program FLASH Option Byte page. + * @param Option: Struct pointer of Option Bytes. + * @retval FLASH_State + * - \ref FLASH_COMPLETE + * @note HSI must keep turn on when doing the Flash operation (Erase/Program). + ************************************************************************************************************/ +FLASH_State FLASH_ProgramOptionByte(FLASH_OptionByte *Option) +{ + s32 i; + u32 CP = ~(Option->MainSecurity | Option->OptionProtect << 1); + u32 checksum = 0; + + for (i = 3; i >= 0; i--) + { + FLASH_ProgramWordData(OB_PP0 + i * 4, ~(Option->WriteProtect[i])); + checksum += ~(Option->WriteProtect[i]); + } + + FLASH_ProgramWordData(OB_CP, CP); + checksum += CP; + + FLASH_ProgramWordData(OB_CHECKSUM, checksum); + + return FLASH_COMPLETE; +} + +/*********************************************************************************************************//** + * @brief Return security status of the FLASH. + * @param Option: Struct pointer of Option Bytes. + * @retval None + ************************************************************************************************************/ +void FLASH_GetOptionByteStatus(FLASH_OptionByte *Option) +{ + s32 i; + + for (i = 3; i >= 0; i--) + { + Option->WriteProtect[i] = ~HT_FLASH->PPSR[i]; + } + + Option->MainSecurity = !(HT_FLASH->CPSR & 1); + Option->OptionProtect = !((HT_FLASH->CPSR >> 1) & 1); +} + +/*********************************************************************************************************//** + * @brief Enable or Disable the specific FLASH interrupts. + * @param FLASH_INT_x: The specific FLASH interrupt. + * This parameter can be any combination (|) of the following values: + * @arg \ref FLASH_INT_ORFIEN + * @arg \ref FLASH_INT_ITADIEN + * @arg \ref FLASH_INT_OBEIEN + * @arg \ref FLASH_INT_IOCMIEN + * @arg \ref FLASH_INT_OREIEN + * @arg \ref FLASH_INT_ALL + * @param Cmd: This parameter can be ENABLE or DISABLE + * @retval None + ************************************************************************************************************/ +void FLASH_IntConfig(u32 FLASH_INT_x, ControlStatus Cmd) +{ + /* Check the parameters */ + Assert_Param(IS_FLASH_INT(FLASH_INT_x)); + Assert_Param(IS_CONTROL_STATUS(Cmd)); + + if (Cmd != DISABLE) + { + HT_FLASH->OIER |= FLASH_INT_x; + } + else + { + HT_FLASH->OIER &= ~FLASH_INT_x; + } +} + +/*********************************************************************************************************//** + * @brief Return flag status of the FLASH interrupt. + * @param FLASH_FLAG_x: Flag of the FLASH interrupt. + * This parameter can be any combination (|) of the following values: + * @arg \ref FLASH_FLAG_OREF + * @arg \ref FLASH_FLAG_IOCMF + * @arg \ref FLASH_FLAG_OBEF + * @arg \ref FLASH_FLAG_ITADF + * @arg \ref FLASH_FLAG_ORFF + * @arg \ref FLASH_FLAG_PPEF + * @arg \ref FLASH_FLAG_RORFF + * @retval FlagStatus + * - \ref SET + * - \ref RESET + ************************************************************************************************************/ +FlagStatus FLASH_GetIntStatus(u32 FLASH_FLAG_x) +{ + /* Check the parameters */ + Assert_Param(IS_FLASH_FLAG(FLASH_FLAG_x)); + + if ((HT_FLASH->OISR & FLASH_FLAG_x) != (u32)RESET) + { + return SET; + } + else + { + return RESET; + } +} + +/*********************************************************************************************************//** + * @brief Clear specific interrupt flags of FLASH. + * @param FLASH_FLAG_x: interrupt flag of FLASH. + * This parameter can be any combination (|) of the following values: + * @arg \ref FLASH_FLAG_OREF + * @arg \ref FLASH_FLAG_IOCMF + * @arg \ref FLASH_FLAG_OBEF + * @arg \ref FLASH_FLAG_ITADF + * @arg \ref FLASH_FLAG_ORFF + * @retval None + ************************************************************************************************************/ +void FLASH_ClearIntFlag(u32 FLASH_FLAG_x) +{ + /* Check the parameters */ + Assert_Param(IS_FLASH_WC_FLAG(FLASH_FLAG_x)); + + HT_FLASH->OISR = FLASH_FLAG_x; +} + +/*********************************************************************************************************//** + * @brief Wait untill the FLASH operation has finished or time-out has occurred. + * @retval FLASH_State + * - \ref FLASH_COMPLETE + * - \ref FLASH_TIME_OUT + * - \ref FLASH_ERR_WRITE_PROTECTED + * - \ref FLASH_ERR_ADDR_OUT_OF_RANGE + * @note HSI must keep turn on when doing the Flash operation (Erase/Program). + ************************************************************************************************************/ +FLASH_State FLASH_WaitForOperationEnd(void) +{ + u32 Timeout = FLASH_TIMEOUT; + u32 Status; + + HT_FLASH->OIER |= (FLASH_INT_ITADIEN); + HT_FLASH->OPCR = FLASH_SEND_MAIN; + #if (LIBCFG_FMC_CMD_READY_WAIT) + __NOP();__NOP();__NOP();__NOP(); + #endif + + /* Waits till the FLASH operation has finished or time-out has occurred */ + while (Timeout--) + { + if ((HT_FLASH->OPCR & FLASH_READY) == FLASH_READY) + { + break; + } + } + Status = HT_FLASH->OISR; + HT_FLASH->OISR &= ~(FLASH_INT_ITADIEN); + + if (Status & FLASH_FLAG_PPEF) + { + return FLASH_ERR_WRITE_PROTECTED; + } + if (Status & FLASH_FLAG_ITADF) + { + return FLASH_ERR_ADDR_OUT_OF_RANGE; + } + if (Timeout == 0) + { + return FLASH_TIME_OUT; + } + + return FLASH_COMPLETE; +} +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/ht32f5xxxx_gpio.c b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/ht32f5xxxx_gpio.c new file mode 100644 index 0000000000..4f778467de --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/ht32f5xxxx_gpio.c @@ -0,0 +1,767 @@ +/*********************************************************************************************************//** + * @file ht32f5xxxx_gpio.c + * @version $Rev:: 6398 $ + * @date $Date:: 2022-10-27 #$ + * @brief This file provides all the GPIO and AFIO firmware functions. + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ + +/* Includes ------------------------------------------------------------------------------------------------*/ +#include "ht32f5xxxx_gpio.h" + +/** @addtogroup HT32F5xxxx_Peripheral_Driver HT32F5xxxx Peripheral Driver + * @{ + */ + +/** @defgroup GPIO GPIO + * @brief GPIO driver modules + * @{ + */ + + +/* Private function prototypes -----------------------------------------------------------------------------*/ +u32 _GPIO_ClockControl(HT_GPIO_TypeDef* HT_GPIOx, ControlStatus Cmd); +u32 _AFIO_ClockControl(ControlStatus Cmd); + +/* Private macro -------------------------------------------------------------------------------------------*/ +/** @defgroup GPIO_Private_Macro GPIO private macros + * @{ + */ +#if (AUTO_CK_CONTROL == 1) + #define GPIO_CK_ST u32 isAlreadyOn + #define GPIO_CK_ON() (isAlreadyOn = _GPIO_ClockControl(HT_GPIOx, ENABLE)) + #define GPIO_CK_OFF() if (isAlreadyOn == FALSE) _GPIO_ClockControl(HT_GPIOx, DISABLE) + #define AFIO_CK_ST u32 isAlreadyOn + #define AFIO_CK_ON() (isAlreadyOn = _AFIO_ClockControl(ENABLE)) + #define AFIO_CK_OFF() if (isAlreadyOn == FALSE) _AFIO_ClockControl(DISABLE) +#else + #define GPIO_CK_ST + #define GPIO_CK_ON(...) + #define GPIO_CK_OFF(...) + #define AFIO_CK_ST + #define AFIO_CK_ON(...) + #define AFIO_CK_OFF(...) +#endif +/** + * @} + */ + +/* Global functions ----------------------------------------------------------------------------------------*/ +/** @addtogroup GPIO_Exported_Functions GPIO exported functions + * @{ + */ +/*********************************************************************************************************//** + * @brief Deinitializes the GPIO peripheral registers to their default reset values. + * @param HT_GPIOx: where HT_GPIOx is the selected GPIO from the GPIO peripherals. + * @retval None + ************************************************************************************************************/ +void GPIO_DeInit(HT_GPIO_TypeDef* HT_GPIOx) +{ + RSTCU_PeripReset_TypeDef RSTCUReset = {{0}}; + + /* Check the parameters */ + Assert_Param(IS_GPIO(HT_GPIOx)); + + if (HT_GPIOx == HT_GPIOA) + { + RSTCUReset.Bit.PA = 1; + } + else if (HT_GPIOx == HT_GPIOB) + { + RSTCUReset.Bit.PB = 1; + } + #if (LIBCFG_GPIOC) + else if (HT_GPIOx == HT_GPIOC) + { + RSTCUReset.Bit.PC = 1; + } + #endif + #if (LIBCFG_GPIOD) + else if (HT_GPIOx == HT_GPIOD) + { + RSTCUReset.Bit.PD = 1; + } + #endif + #if (LIBCFG_GPIOE) + else if (HT_GPIOx == HT_GPIOE) + { + RSTCUReset.Bit.PE = 1; + } + #endif + #if (LIBCFG_GPIOF) + else if (HT_GPIOx == HT_GPIOF) + { + RSTCUReset.Bit.PF = 1; + } + #endif + + RSTCU_PeripReset(RSTCUReset, ENABLE); +} + +/*********************************************************************************************************//** + * @brief Configure the direction of specified GPIO pins. + * @param HT_GPIOx: where HT_GPIOx is the selected GPIO from the GPIO peripherals. + * @param GPIO_PIN_nBITMAP: The port pins. + * This parameter can be any combination of GPIO_PIN_x. + * @param GPIO_DIR_INorOUT: + * This parameter can be one of below: + * @arg GPIO_DIR_IN : The pins are input mode + * @arg GPIO_DIR_OUT : The pins are output mode + * @retval None + ************************************************************************************************************/ +void GPIO_DirectionConfig(HT_GPIO_TypeDef* HT_GPIOx, u16 GPIO_PIN_nBITMAP, GPIO_DIR_Enum GPIO_DIR_INorOUT) +{ + GPIO_CK_ST; + + /* Check the parameters */ + Assert_Param(IS_GPIO(HT_GPIOx)); + Assert_Param(IS_GPIO_DIR(GPIO_DIR_INorOUT)); + + GPIO_CK_ON(); + + if (GPIO_DIR_INorOUT != GPIO_DIR_IN) + HT_GPIOx->DIRCR |= GPIO_PIN_nBITMAP; + else + HT_GPIOx->DIRCR &= ~GPIO_PIN_nBITMAP; + + GPIO_CK_OFF(); +} + +/*********************************************************************************************************//** + * @brief Configure the pull resistor of specified GPIO pins. + * @param HT_GPIOx: where HT_GPIOx is the selected GPIO from the GPIO peripherals. + * @param GPIO_PIN_nBITMAP: The port pins. + * This parameter can be any combination of GPIO_PIN_x. + * @param GPIO_PR_x: Selection of Pull resistor. + * This parameter can be one of below: + * @arg GPIO_PR_UP : The pins with internal pull-up resistor + * @arg GPIO_PR_DOWN : The pins with internal pull-down resistor + * @arg GPIO_PR_DISABLE : The pins without pull resistor + * @retval None + ************************************************************************************************************/ +void GPIO_PullResistorConfig(HT_GPIO_TypeDef* HT_GPIOx, u16 GPIO_PIN_nBITMAP, GPIO_PR_Enum GPIO_PR_x) +{ + u32 temp_up, temp_down; + GPIO_CK_ST; + + /* Check the parameters */ + Assert_Param(IS_GPIO(HT_GPIOx)); + Assert_Param(IS_GPIO_PR(GPIO_PR_x)); + + GPIO_CK_ON(); + temp_up = HT_GPIOx->PUR; + temp_down = HT_GPIOx->PDR; + + #if (LIBCFG_GPIO_PR_STRONG_UP) + temp_up &= ~(GPIO_PIN_nBITMAP << 16); + #endif + temp_up &= ~GPIO_PIN_nBITMAP; + temp_down &= ~GPIO_PIN_nBITMAP; + + switch (GPIO_PR_x) + { + case GPIO_PR_UP: + temp_up |= GPIO_PIN_nBITMAP; + break; + case GPIO_PR_DOWN: + temp_down |= GPIO_PIN_nBITMAP; + break; + case GPIO_PR_DISABLE: + break; + #if (LIBCFG_GPIO_PR_STRONG_UP) + case GPIO_PR_STRONG_UP: + temp_up |= (GPIO_PIN_nBITMAP << 16); + break; + case GPIO_PR_STRONGEST_UP: + temp_up |= (GPIO_PIN_nBITMAP << 16); + temp_up |= GPIO_PIN_nBITMAP; + break; + #endif + default: + break; + } + + HT_GPIOx->PUR = temp_up; + HT_GPIOx->PDR = temp_down; + + GPIO_CK_OFF(); +} + +/*********************************************************************************************************//** + * @brief Enable or Disable the input control of specified GPIO pins. + * @param HT_GPIOx: where HT_GPIOx is the selected GPIO from the GPIO peripherals. + * @param GPIO_PIN_nBITMAP: The port pins. + * This parameter can be any combination of GPIO_PIN_x. + * @param Cmd: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void GPIO_InputConfig(HT_GPIO_TypeDef* HT_GPIOx, u16 GPIO_PIN_nBITMAP, ControlStatus Cmd) +{ + GPIO_CK_ST; + + /* Check the parameters */ + Assert_Param(IS_GPIO(HT_GPIOx)); + Assert_Param(IS_CONTROL_STATUS(Cmd)); + + GPIO_CK_ON(); + if (Cmd != DISABLE) + HT_GPIOx->INER |= GPIO_PIN_nBITMAP; + else + HT_GPIOx->INER &= ~GPIO_PIN_nBITMAP; + GPIO_CK_OFF(); +} + +/*********************************************************************************************************//** + * @brief Select the driving current of specified GPIO pins. + * @param HT_GPIOx: where HT_GPIOx is the selected GPIO from the GPIO peripherals. + * @param GPIO_PIN_nBITMAP: The port pins. + * This parameter can be any combination of GPIO_PIN_x. + * @param GPIO_DV_nMA: + * This parameter can be one of below: + * @arg GPIO_DV_4MA : Select output driving current as 4 mA + * @arg GPIO_DV_8MA : Select output driving current as 8 mA + * @arg GPIO_DV_12MA : Select output driving current as 12 mA + * @arg GPIO_DV_16MA : Select output driving current as 16 mA + * @retval None + ************************************************************************************************************/ +void GPIO_DriveConfig(HT_GPIO_TypeDef* HT_GPIOx, u16 GPIO_PIN_nBITMAP, GPIO_DV_Enum GPIO_DV_nMA) +{ + u32 index, temp, CurrentMode = 0, PinPosition = 0; + GPIO_CK_ST; + + /* Check the parameters */ + Assert_Param(IS_GPIO(HT_GPIOx)); + Assert_Param(IS_GPIO_DV(GPIO_DV_nMA)); + + for (index = 0; index < 16; index++) + { + if ((GPIO_PIN_nBITMAP & 0x0001) == 1) + { + temp = index << 1; + CurrentMode |= ((u32) GPIO_DV_nMA << temp); + PinPosition |= ((u32) 0x03 << temp); + } + GPIO_PIN_nBITMAP >>= 1; + } + + GPIO_CK_ON(); + HT_GPIOx->DRVR &= ~PinPosition; + HT_GPIOx->DRVR |= CurrentMode; + GPIO_CK_OFF(); +} + +/*********************************************************************************************************//** + * @brief Enable or Disable the open drain function of specified GPIO pins. + * @param HT_GPIOx: where HT_GPIOx is the selected GPIO from the GPIO peripherals. + * @param GPIO_PIN_nBITMAP: The port pins. + * This parameter can be any combination of GPIO_PIN_x. + * @param Cmd: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void GPIO_OpenDrainConfig(HT_GPIO_TypeDef* HT_GPIOx, u16 GPIO_PIN_nBITMAP, ControlStatus Cmd) +{ + GPIO_CK_ST; + + /* Check the parameters */ + Assert_Param(IS_GPIO(HT_GPIOx)); + Assert_Param(IS_CONTROL_STATUS(Cmd)); + + GPIO_CK_ON(); + if (Cmd != DISABLE) + HT_GPIOx->ODR |= GPIO_PIN_nBITMAP; + else + HT_GPIOx->ODR &= ~GPIO_PIN_nBITMAP; + GPIO_CK_OFF(); +} + +#if LIBCFG_GPIO_SINK_CURRENT_ENHANCED +/*********************************************************************************************************//** + * @brief Select the sink current of specified GPIO pins. + * @param HT_GPIOx: where HT_GPIOx is the selected GPIO from the GPIO peripherals. + * @param GPIO_PIN_n: The port pins. + * This parameter can be any combination of GPIO_PIN_x. + * @param Cmd: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void GPIO_SinkConfig(HT_GPIO_TypeDef* HT_GPIOx, u16 GPIO_PIN_n, ControlStatus Cmd) +{ + /* Check the parameters */ + Assert_Param(IS_GPIO(HT_GPIOx)); + Assert_Param(IS_CONTROL_STATUS(Cmd)); + + if (Cmd != DISABLE) + HT_GPIOx->SCER |= GPIO_PIN_n; + else + HT_GPIOx->SCER &= ~GPIO_PIN_n; +} +#endif + +/*********************************************************************************************************//** + * @brief Get the input data of specified port pin. + * @param HT_GPIOx: where HT_GPIOx is the selected GPIO from the GPIO peripherals. + * @param GPIO_PIN_n: This parameter can be GPIO_PIN_x. + * @retval SET or RESET + ************************************************************************************************************/ +FlagStatus GPIO_ReadInBit(HT_GPIO_TypeDef* HT_GPIOx, u16 GPIO_PIN_n) +{ + FlagStatus result; + GPIO_CK_ST; + + /* Check the parameters */ + Assert_Param(IS_GPIO(HT_GPIOx)); + + GPIO_CK_ON(); + if ((HT_GPIOx->DINR & GPIO_PIN_n) != RESET) + result = SET; + else + result = RESET; + + GPIO_CK_OFF(); + return result; +} + +/*********************************************************************************************************//** + * @brief Get the input data of specified GPIO port. + * @param HT_GPIOx: where HT_GPIOx is the selected GPIO from the GPIO peripherals. + * @retval The value of input data register. + ************************************************************************************************************/ +u16 GPIO_ReadInData(HT_GPIO_TypeDef* HT_GPIOx) +{ + u16 uValue; + GPIO_CK_ST; + + /* Check the parameters */ + Assert_Param(IS_GPIO(HT_GPIOx)); + + GPIO_CK_ON(); + uValue = (u16)HT_GPIOx->DINR; + GPIO_CK_OFF(); + return (uValue); +} + +/*********************************************************************************************************//** + * @brief Get the output data of specified port pin. + * @param HT_GPIOx: where HT_GPIOx is the selected GPIO from the GPIO peripherals. + * @param GPIO_PIN_n: This parameter can be GPIO_PIN_x. + * @retval SET or RESET + ************************************************************************************************************/ +FlagStatus GPIO_ReadOutBit(HT_GPIO_TypeDef* HT_GPIOx, u16 GPIO_PIN_n) +{ + FlagStatus result; + GPIO_CK_ST; + /* Check the parameters */ + Assert_Param(IS_GPIO(HT_GPIOx)); + + GPIO_CK_ON(); + if ((HT_GPIOx->DOUTR & GPIO_PIN_n) != RESET) + result = SET; + else + result = RESET; + + GPIO_CK_OFF(); + return result; +} + +/*********************************************************************************************************//** + * @brief Get the output data of specified GPIO port. + * @param HT_GPIOx: where HT_GPIOx is the selected GPIO from the GPIO peripherals. + * @retval The value of output data register. + ************************************************************************************************************/ +u16 GPIO_ReadOutData(HT_GPIO_TypeDef* HT_GPIOx) +{ + u32 uValue; + GPIO_CK_ST; + + /* Check the parameters */ + Assert_Param(IS_GPIO(HT_GPIOx)); + + GPIO_CK_ON(); + uValue = (u16)HT_GPIOx->DOUTR; + GPIO_CK_OFF(); + return uValue; +} + +/*********************************************************************************************************//** + * @brief Set the selected port bits of output data. + * @param HT_GPIOx: where HT_GPIOx is the selected GPIO from the GPIO peripherals. + * @param GPIO_PIN_nBITMAP: Specify the port bit to be set. + * This parameter can be any combination of GPIO_PIN_x. + * @retval None + ************************************************************************************************************/ +void GPIO_SetOutBits(HT_GPIO_TypeDef* HT_GPIOx, u16 GPIO_PIN_nBITMAP) +{ + GPIO_CK_ST; + + /* Check the parameters */ + Assert_Param(IS_GPIO(HT_GPIOx)); + + GPIO_CK_ON(); + HT_GPIOx->SRR = GPIO_PIN_nBITMAP; + GPIO_CK_OFF(); +} + +/*********************************************************************************************************//** + * @brief Clear the selected port bits of output data. + * @param HT_GPIOx: where HT_GPIOx is the selected GPIO from the GPIO peripherals. + * @param GPIO_PIN_nBITMAP: Specify the port bit to be clear. + * This parameter can be any combination of GPIO_PIN_x. + * @retval None + ************************************************************************************************************/ +void GPIO_ClearOutBits(HT_GPIO_TypeDef* HT_GPIOx, u16 GPIO_PIN_nBITMAP) +{ + GPIO_CK_ST; + + /* Check the parameters */ + Assert_Param(IS_GPIO(HT_GPIOx)); + + GPIO_CK_ON(); + HT_GPIOx->RR = GPIO_PIN_nBITMAP; + GPIO_CK_OFF(); +} + +/*********************************************************************************************************//** + * @brief Set or Clear the selected port bits of data. + * @param HT_GPIOx: where HT_GPIOx is the selected GPIO from the GPIO peripherals. + * @param GPIO_PIN_nBITMAP: Specify the port bits. + * This parameter can be any combination of GPIO_PIN_x. + * @param Status: This parameter can be SET or RESET. + * @retval None + ************************************************************************************************************/ +void GPIO_WriteOutBits(HT_GPIO_TypeDef* HT_GPIOx, u16 GPIO_PIN_nBITMAP, FlagStatus Status) +{ + GPIO_CK_ST; + + /* Check the parameters */ + Assert_Param(IS_GPIO(HT_GPIOx)); + + GPIO_CK_ON(); + if (Status != RESET) + HT_GPIOx->SRR = GPIO_PIN_nBITMAP; + else + HT_GPIOx->RR = GPIO_PIN_nBITMAP; + GPIO_CK_OFF(); +} + +/*********************************************************************************************************//** + * @brief Put data to the specified GPIO data port. + * @param HT_GPIOx: where HT_GPIOx is the selected GPIO from the GPIO peripherals. + * @param Data: Specify the data to be written to the port data register. + * @retval None + ************************************************************************************************************/ +void GPIO_WriteOutData(HT_GPIO_TypeDef* HT_GPIOx, u16 Data) +{ + GPIO_CK_ST; + + /* Check the parameters */ + Assert_Param(IS_GPIO(HT_GPIOx)); + + GPIO_CK_ON(); + HT_GPIOx->DOUTR = Data; + GPIO_CK_OFF(); +} + +/*********************************************************************************************************//** + * @brief Lock configuration of GPIO pins. + * @param HT_GPIOx: where HT_GPIOx is the selected GPIO from the GPIO peripherals. + * @param GPIO_PIN_nBITMAP: Specify the port bits. + * This parameter can be any combination of GPIO_PIN_x. + * @retval None + ************************************************************************************************************/ +void GPIO_PinLock(HT_GPIO_TypeDef* HT_GPIOx, u16 GPIO_PIN_nBITMAP) +{ + GPIO_CK_ST; + + /* Check the parameters */ + Assert_Param(IS_GPIO(HT_GPIOx)); + + GPIO_CK_ON(); + HT_GPIOx->LOCKR = (u32)0x5FA00000 | GPIO_PIN_nBITMAP; + GPIO_CK_OFF(); +} + +/*********************************************************************************************************//** + * @brief Get the lock state of specified GPIO port. + * @param HT_GPIOx: where HT_GPIOx is the selected GPIO from the GPIO peripherals. + * @retval TRUE or FALSE + ************************************************************************************************************/ +bool GPIO_IsPortLocked(HT_GPIO_TypeDef* HT_GPIOx) +{ + bool result; + GPIO_CK_ST; + + /* Check the parameters */ + Assert_Param(IS_GPIO(HT_GPIOx)); + + GPIO_CK_ON(); + if ((HT_GPIOx->LOCKR >> 16) == 0) + result = FALSE; + else + result = TRUE; + GPIO_CK_OFF(); + return result; +} + +/*********************************************************************************************************//** + * @brief Get the lock state of specified GPIO port pin. + * @param HT_GPIOx: where HT_GPIOx is the selected GPIO from the GPIO peripherals. + * @param GPIO_PIN_n: This parameter can be GPIO_PIN_x. + * @retval TRUE or FALSE + ************************************************************************************************************/ +bool GPIO_IsPinLocked(HT_GPIO_TypeDef* HT_GPIOx, u16 GPIO_PIN_n) +{ + bool result; + GPIO_CK_ST; + + /* Check the parameters */ + Assert_Param(IS_GPIO(HT_GPIOx)); + + GPIO_CK_ON(); + if ((HT_GPIOx->LOCKR & GPIO_PIN_n) == 0) + result = FALSE; + else + result = TRUE; + GPIO_CK_OFF(); + return result; +} + +#if (LIBCFG_GPIO_DISABLE_DEBUG_PORT) +/*********************************************************************************************************//** + * @brief Disable DEBUG port to prevent unexpected security lock. + * @retval None + ************************************************************************************************************/ +void GPIO_DisableDebugPort(void) +{ + CKCU_PeripClockConfig_TypeDef CKCUClock = {{ 0 }}; + CKCUClock.Bit.PA = 1; + CKCUClock.Bit.AFIO = 1; + CKCU_PeripClockConfig(CKCUClock, ENABLE); + + AFIO_GPxConfig(GPIO_PA, GPIO_PIN_13, AFIO_FUN_GPIO); + GPIO_PullResistorConfig(HT_GPIOA, GPIO_PIN_13, GPIO_PR_DOWN); + + #if defined(USE_HT32F52342_52) + GPIO_InputConfig(HT_GPIOA, GPIO_PIN_13, DISABLE); + #endif + + #if 0 + GPIO_PullResistorConfig(HT_GPIOA, GPIO_PIN_12, GPIO_PR_DOWN); + GPIO_PullResistorConfig(HT_GPIOA, GPIO_PIN_12, GPIO_PR_UP); + GPIO_PullResistorConfig(HT_GPIOA, GPIO_PIN_12, GPIO_PR_DOWN); + GPIO_PullResistorConfig(HT_GPIOA, GPIO_PIN_12, GPIO_PR_UP); + GPIO_PullResistorConfig(HT_GPIOA, GPIO_PIN_12, GPIO_PR_DOWN); + GPIO_PullResistorConfig(HT_GPIOA, GPIO_PIN_12, GPIO_PR_UP); + GPIO_PullResistorConfig(HT_GPIOA, GPIO_PIN_12, GPIO_PR_DOWN); + GPIO_PullResistorConfig(HT_GPIOA, GPIO_PIN_12, GPIO_PR_UP); + AFIO_GPxConfig(GPIO_PA, GPIO_PIN_12, AFIO_FUN_GPIO); + #endif +} +#endif + +/*********************************************************************************************************//** + * @brief Convert HT_GPIOx to GPIO_Px + * @param HT_GPIOx: where HT_GPIOx is the selected GPIO from the GPIO peripherals. + * @retval GPIO_Px: GPIO ID + ************************************************************************************************************/ +u32 GPIO_GetID(HT_GPIO_TypeDef* HT_GPIOx) +{ + // Convert 0x400B0000 ~ 0x400C6000 to 0 ~ 11 + u32 GPIO_Px = (((u32)HT_GPIOx) >> (12 + 1)) & 0x7F; + GPIO_Px -= 0x58; // 0xB0000 >> 13 = 0x58 + + return GPIO_Px; +} + +/*********************************************************************************************************//** + * @brief Deinitialize the AFIO peripheral registers to their default reset values. + * @retval None + ************************************************************************************************************/ +void AFIO_DeInit(void) +{ + RSTCU_PeripReset_TypeDef RSTCUReset = {{0}}; + + RSTCUReset.Bit.AFIO = 1; + RSTCU_PeripReset(RSTCUReset, ENABLE); +} + +/*********************************************************************************************************//** + * @brief Configure alternated mode of GPIO with specified pins. + * @param GPIO_Px: GPIO_PA ~ GPIO_PD. + * @param AFIO_PIN_n: This parameter can be any combination of AFIO_PIN_x. + * @param AFIO_MODE_n: This parameter can be one of the following values: + * @arg AFIO_MODE_DEFAULT : The default I/O function + * @arg AFIO_MODE_1 : Alternated mode 1 + * @arg AFIO_MODE_2 : Alternated mode 2 + * @arg AFIO_MODE_3 : Alternated mode 3 + * @arg AFIO_MODE_4 : Alternated mode 4 + * @arg AFIO_MODE_5 : Alternated mode 5 + * @arg AFIO_MODE_6 : Alternated mode 6 + * @arg AFIO_MODE_7 : Alternated mode 7 + * @arg AFIO_MODE_8 : Alternated mode 8 + * @arg AFIO_MODE_9 : Alternated mode 9 + * @arg AFIO_MODE_10 : Alternated mode 10 + * @arg AFIO_MODE_11 : Alternated mode 11 + * @arg AFIO_MODE_12 : Alternated mode 12 + * @arg AFIO_MODE_13 : Alternated mode 13 + * @arg AFIO_MODE_14 : Alternated mode 14 + * @arg AFIO_MODE_15 : Alternated mode 15 + * @retval None + ************************************************************************************************************/ +void AFIO_GPxConfig(u32 GPIO_Px, u32 AFIO_PIN_n, AFIO_MODE_Enum AFIO_MODE_n) +{ + vu32* pGPxCFGR = ((vu32*)&HT_AFIO->GPACFGR[0]) + GPIO_Px * 2; + u32 index = 0; + u32 Mask = 0, PinMode = 0; + s32 i; + AFIO_CK_ST; + + Assert_Param(IS_AFIO_MODE(AFIO_MODE_n)); + AFIO_CK_ON(); + + for (i = 0; i <= 8; i += 8) + { + Mask = 0; + PinMode = 0; + if (AFIO_PIN_n & (0x00FF << i)) + { + for (index = 0; index < 8; index++) + { + if ((AFIO_PIN_n >> index) & (0x0001 << i)) + { + Mask |= (0xF << (index * 4)); + PinMode |= (AFIO_MODE_n << (index * 4)); + } + } + *pGPxCFGR = (*pGPxCFGR & (~Mask)) | PinMode; + } + pGPxCFGR++; + } + + AFIO_CK_OFF(); +} + +/*********************************************************************************************************//** + * @brief Select the GPIO pin to be used as EXTI channel. + * @param GPIO_PIN_NUM_n: Specify the GPIO pin number to be configured. + * @param GPIO_Px: GPIO_PA ~ GPIO_PF. + * @retval None + ************************************************************************************************************/ +void AFIO_EXTISourceConfig(u32 GPIO_PIN_NUM_n, u32 GPIO_Px) +{ + u8 index = 0; + u32 tmp = 0; + AFIO_CK_ST; + + /* Check the parameters */ + Assert_Param(IS_GPIO_PORT(GPIO_Px)); + Assert_Param(IS_GPIO_PIN_NUM(GPIO_PIN_NUM_n)); + + AFIO_CK_ON(); + + if (GPIO_PIN_NUM_n > 7) + { + #if (LIBCFG_EXTI_8CH) + GPIO_Px += 8; + #else + index = 1; + #endif + GPIO_PIN_NUM_n -= 8; + } + + tmp = HT_AFIO->ESSR[index]; + tmp &= ~((u32)0x0F << (GPIO_PIN_NUM_n * 4)); + tmp |= (u32)GPIO_Px << (GPIO_PIN_NUM_n * 4); + HT_AFIO->ESSR[index] = tmp; + AFIO_CK_OFF(); +} +/** + * @} + */ + +/* Private functions ---------------------------------------------------------------------------------------*/ +/** @defgroup GPIO_Private_Functions GPIO private functions + * @{ + */ +/*********************************************************************************************************//** + * @brief Turn on/Turn off specify GPIO clock. + * @param HT_GPIOx: where HT_GPIOx is the selected GPIO from the GPIO peripherals. + * @param Cmd: This parameter can be ENABLE or DISABLE. + * @retval TRUE or FALSE (TRUE: already turn on, FALSE, Turn on by this call) + ***********************************************************************************************************/ +u32 _GPIO_ClockControl(HT_GPIO_TypeDef* HT_GPIOx, ControlStatus Cmd) +{ + u32 PxENStatus; + /*--------------------------------------------------------------------------------------------------------*/ + /* ((0x400Bx000 & 0x0000F000) >> 12 ) / 2 + 16 = */ + /* (0x0 ~ 0x4) + 16 = 16 ~ 20 for AHBCCR PAEN ~ PEEN bit offset */ + /*--------------------------------------------------------------------------------------------------------*/ + u32 offset = ((((u32)HT_GPIOx) & 0x0000F000) >> 12) / 2 + 16; + + PxENStatus = HT_CKCU->AHBCCR & (1 << offset); + + if (PxENStatus != 0) + { + if (Cmd == DISABLE) + { + HT_CKCU->AHBCCR &= (~(1 << offset)); + } + return TRUE; + } + + HT_CKCU->AHBCCR |= (1 << offset); + return FALSE; +} + +/*********************************************************************************************************//** + * @brief Turn on/Turn off AFIO clock. + * @param Cmd: This parameter can be ENABLE or DISABLE. + * @retval TRUE or FALSE (TRUE: already turn on, FALSE, Turn on by this call) + ***********************************************************************************************************/ +u32 _AFIO_ClockControl(ControlStatus Cmd) +{ + u32 AFIOENStatus; + + AFIOENStatus = HT_CKCU->APBCCR0 & (1 << 14); + + if (AFIOENStatus != 0) + { + if (Cmd == DISABLE) + { + HT_CKCU->APBCCR0 &= (~(1 << 14)); + } + return TRUE; + } + + HT_CKCU->APBCCR0 |= (1 << 14); + return FALSE; +} +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/ht32f5xxxx_gptm.c b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/ht32f5xxxx_gptm.c new file mode 100644 index 0000000000..b824c72b16 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/ht32f5xxxx_gptm.c @@ -0,0 +1,2 @@ +The SCTM, PWM, GPTM, and MCTM timer have similar architecture. They use the same driver, +"ht32fxxxxx_tm.c/.h" to save the code size. For those timers, please refet to the TM driver/example. diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/ht32f5xxxx_i2c.c b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/ht32f5xxxx_i2c.c new file mode 100644 index 0000000000..1394eb027d --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/ht32f5xxxx_i2c.c @@ -0,0 +1,861 @@ +/*********************************************************************************************************//** + * @file ht32f5xxxx_i2c.c + * @version $Rev:: 6398 $ + * @date $Date:: 2022-10-27 #$ + * @brief This file provides all the I2C firmware functions. + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ + +/* Includes ------------------------------------------------------------------------------------------------*/ +#include "ht32f5xxxx_i2c.h" + +/** @addtogroup HT32F5xxxx_Peripheral_Driver HT32F5xxxx Peripheral Driver + * @{ + */ + +/** @defgroup I2C I2C + * @brief I2C driver modules + * @{ + */ + + +/* Private constants ---------------------------------------------------------------------------------------*/ +/** @defgroup I2C_Private_Define I2C private definitions + * @{ + */ +/* I2C ENI2C mask */ +#define CR_ENI2C_SET ((u32)0x00000008) +#define CR_ENI2C_RESET ((u32)0xFFFFFFF7) + +/* I2C ENGC mask */ +#define CR_ENGC_SET ((u32)0x00000004) +#define CR_ENGC_RESET ((u32)0xFFFFFFFB) + +/* I2C AA mask */ +#define CR_ACK_SET ((u32)0x00000001) +#define CR_ACK_RESET ((u32)0xFFFFFFFE) + +/* I2C PDMANACK mask */ +#define CR_PDMANACK_SET ((u32)0x00000400) +#define CR_PDMANACK_RESET ((u32)0xFFFFFBFF) + +/* I2C ENTOUT mask */ +#define CR_ENTOUT_SET ((u32)0x00001000) +#define CR_ENTOUT_RESET ((u32)0xFFFFEFFF) + +/* I2C COMBFILT mask */ +#define CR_COMBFILTER_SET ((u32)0x00002000) +#define CR_COMBFILTER_RESET ((u32)0xFFFFDFFF) + +/* I2C Device Address 0 and Device Address 1 mask */ +#define ADDR_DEVADDR0_SET ((u32)0x00008000) +#define ADDR_DEVADDR0_RESET ((u32)0xFFFF7FFF) +#define ADDR_DEVADDR1_SET ((u32)0x80000000) +#define ADDR_DEVADDR1_RESET ((u32)0x7FFFFFFF) + +/** + * @} + */ + +/* Global functions ----------------------------------------------------------------------------------------*/ +/** @defgroup I2C_Exported_Functions I2C exported functions + * @{ + */ +/*********************************************************************************************************//** + * @brief Deinitialize the I2C peripheral registers to their default reset values. + * @param I2Cx: where I2Cx is the selected I2C from the I2C peripherals. + * @retval None + ************************************************************************************************************/ +void I2C_DeInit(HT_I2C_TypeDef* I2Cx) +{ + RSTCU_PeripReset_TypeDef RSTCUReset = {{0}}; + + /* Check the parameters */ + Assert_Param(IS_I2C(I2Cx)); + + if (I2Cx == HT_I2C0) + { + RSTCUReset.Bit.I2C0 = 1; + } + #if (LIBCFG_I2C1) + else if (I2Cx == HT_I2C1) + { + RSTCUReset.Bit.I2C1 = 1; + } + #endif + #if (LIBCFG_I2C2) + else if (I2Cx == HT_I2C2) + { + RSTCUReset.Bit.I2C2 = 1; + } + #endif + + RSTCU_PeripReset(RSTCUReset, ENABLE); +} + +/*********************************************************************************************************//** + * @brief Initialize the I2Cx peripheral according to the specified parameters in the I2C_InitStruct. + * @param I2Cx: where I2Cx is the selected I2C from the I2C peripherals. + * @param I2C_InitStruct: pointer to a I2C_InitTypeDef structure. + * @retval None + ************************************************************************************************************/ +void I2C_Init(HT_I2C_TypeDef* I2Cx, I2C_InitTypeDef* I2C_InitStruct) +{ + u32 PCLK_Freq = 0; + s32 sTmp = 0; + s32 SHPGR = 0; + s32 SLPGR = 0; + + /* Check the parameters */ + Assert_Param(IS_I2C(I2Cx)); + Assert_Param(IS_I2C_GENERAL_CALL(I2C_InitStruct->I2C_GeneralCall)); + Assert_Param(IS_I2C_ACKNOWLEDGE_ADDRESS(I2C_InitStruct->I2C_AddressingMode)); + Assert_Param(IS_I2C_ACKNOWLEDGE(I2C_InitStruct->I2C_Acknowledge)); + Assert_Param(IS_I2C_ADDRESS(I2C_InitStruct->I2C_OwnAddress)); + Assert_Param(IS_I2C_SPEED(I2C_InitStruct->I2C_Speed)); + + #if (LIBCFG_I2C_NO_10BIT_MODE) + I2Cx->CR = (I2Cx->CR & 0xFFFFFFFA) | I2C_InitStruct->I2C_GeneralCall | I2C_InitStruct->I2C_Acknowledge; + #else + I2Cx->CR = (I2Cx->CR & 0xFFFFFF7A) | I2C_InitStruct->I2C_GeneralCall | + I2C_InitStruct->I2C_AddressingMode | I2C_InitStruct->I2C_Acknowledge; + #endif + + #if (LIBCFG_I2C_TWO_DEV_ADDR) + I2Cx->ADDR = (I2Cx->ADDR & 0xFFFF0000) | (ADDR_DEVADDR0_SET | (I2C_InitStruct->I2C_OwnAddress)); + #else + I2Cx->ADDR = I2C_InitStruct->I2C_OwnAddress; + #endif + + if (I2Cx == HT_I2C0) + PCLK_Freq = CKCU_GetPeripFrequency(CKCU_PCLK_I2C0); + #if (LIBCFG_I2C1) + else if (I2Cx == HT_I2C1) + PCLK_Freq = CKCU_GetPeripFrequency(CKCU_PCLK_I2C1); + #endif + #if (LIBCFG_I2C2) + else if (I2Cx == HT_I2C2) + PCLK_Freq = CKCU_GetPeripFrequency(CKCU_PCLK_I2C2); + #endif + + switch (I2Cx->CR & 0xC000) + { + case 0: + { + sTmp = 6; + break; + } + case 0x4000: + { + sTmp = 8; + break; + } + case 0x8000: + { + sTmp = 9; + break; + } + } + + SHPGR = (PCLK_Freq * 9)/(I2C_InitStruct->I2C_Speed * 20) - sTmp - I2C_InitStruct->I2C_SpeedOffset; + SLPGR = (PCLK_Freq * 11)/(I2C_InitStruct->I2C_Speed * 20) - sTmp - I2C_InitStruct->I2C_SpeedOffset; + + SHPGR = (SHPGR < 0) ? 0 : SHPGR; + SLPGR = (SLPGR < 0) ? 0 : SLPGR; + + I2Cx->SHPGR = SHPGR; + I2Cx->SLPGR = SLPGR; +} + +/*********************************************************************************************************//** + * @brief Fill each I2C_InitStruct member with its default value. + * @param I2C_InitStruct: pointer to an I2C_InitTypeDef structure. + * @retval None + ************************************************************************************************************/ +void I2C_StructInit(I2C_InitTypeDef* I2C_InitStruct) +{ + I2C_InitStruct->I2C_GeneralCall = I2C_GENERALCALL_DISABLE; + I2C_InitStruct->I2C_AddressingMode = I2C_ADDRESSING_7BIT; + I2C_InitStruct->I2C_Acknowledge = I2C_ACK_DISABLE; + I2C_InitStruct->I2C_OwnAddress = 0; + I2C_InitStruct->I2C_Speed = 1000000; + I2C_InitStruct->I2C_SpeedOffset = 0; +} + +/*********************************************************************************************************//** + * @brief Enable or Disable the specified I2C peripheral. + * @param I2Cx: where I2Cx is the selected I2C from the I2C peripherals. + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void I2C_Cmd(HT_I2C_TypeDef* I2Cx, ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_I2C(I2Cx)); + Assert_Param(IS_CONTROL_STATUS(NewState)); + + if (NewState != DISABLE) + { + I2Cx->CR |= CR_ENI2C_SET; + } + else + { + I2Cx->CR &= CR_ENI2C_RESET; + } +} + +/*********************************************************************************************************//** + * @brief Generate STOP condition of I2C communication. + * @param I2Cx: where I2Cx is the selected I2C from the I2C peripherals. + * @retval None + ************************************************************************************************************/ +void I2C_GenerateSTOP(HT_I2C_TypeDef* I2Cx) +{ + /* Check the parameters */ + Assert_Param(IS_I2C(I2Cx)); + + I2Cx->CR |= 0x2; +} + +/*********************************************************************************************************//** + * @brief Enable or Disable I2C interrupts. + * @param I2Cx: where I2Cx is the selected I2C from the I2C peripherals. + * @param I2C_Int: specify if the I2C interrupt source to be enabled or disabled. + * This parameter can be any combination of the following values: + * @arg I2C_INT_STA + * @arg I2C_INT_STO + * @arg I2C_INT_ADRS + * @arg I2C_INT_GCS + * @arg I2C_INT_ARBLOS + * @arg I2C_INT_RXNACK + * @arg I2C_INT_BUSERR + * @arg I2C_INT_TOUT + * @arg I2C_INT_RXDNE + * @arg I2C_INT_TXDE + * @arg I2C_INT_RXBF + * @arg I2C_INT_ALL + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void I2C_IntConfig(HT_I2C_TypeDef* I2Cx, u32 I2C_Int, ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_I2C(I2Cx)); + Assert_Param(IS_I2C_INT(I2C_Int)); + Assert_Param(IS_CONTROL_STATUS(NewState)); + + if (NewState != DISABLE) + { + I2Cx->IER |= I2C_Int; + } + else + { + I2Cx->IER &= (u32)~I2C_Int; + } +} + +/*********************************************************************************************************//** + * @brief Enable or Disable I2C General Call. + * @param I2Cx: where I2Cx is the selected I2C from the I2C peripherals. + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void I2C_GeneralCallCmd(HT_I2C_TypeDef* I2Cx, ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_I2C(I2Cx)); + Assert_Param(IS_CONTROL_STATUS(NewState)); + + if (NewState != DISABLE) + { + I2Cx->CR |= CR_ENGC_SET; + } + else + { + I2Cx->CR &= CR_ENGC_RESET; + } +} + +/*********************************************************************************************************//** + * @brief Enable or Disable I2C sending acknowledgement. + * @param I2Cx: where I2Cx is the selected I2C from the I2C peripherals. + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void I2C_AckCmd(HT_I2C_TypeDef* I2Cx, ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_I2C(I2Cx)); + Assert_Param(IS_CONTROL_STATUS(NewState)); + + if (NewState != DISABLE) + { + I2Cx->CR |= CR_ACK_SET; + } + else + { + I2Cx->CR &= CR_ACK_RESET; + } +} + +/*********************************************************************************************************//** + * @brief Configure own address of the specified I2C. + * @param I2Cx: where I2Cx is the selected I2C from the I2C peripherals. + * @param I2C_Address: specify own address of I2C. + * @retval None + ************************************************************************************************************/ +void I2C_SetOwnAddress(HT_I2C_TypeDef* I2Cx, I2C_AddressTypeDef I2C_Address) +{ + /* Check the parameters */ + Assert_Param(IS_I2C(I2Cx)); + Assert_Param(IS_I2C_ADDRESS(I2C_Address)); + + #if (LIBCFG_I2C_TWO_DEV_ADDR) + I2Cx->ADDR = (I2Cx->ADDR & 0xFFFFFF80) | (ADDR_DEVADDR0_SET | I2C_Address); + #else + I2Cx->ADDR = I2C_Address; + #endif +} + +#if (LIBCFG_I2C_TWO_DEV_ADDR) +/*********************************************************************************************************//** + * @brief Configure own address 1 of the specified I2C. + * @param I2Cx: where I2Cx is the selected I2C from the I2C peripherals. + * @param I2C_Address: specify own address 1 of I2C. + * @retval None + ************************************************************************************************************/ +void I2C_SetOwnAddress1(HT_I2C_TypeDef* I2Cx, I2C_AddressTypeDef I2C_Address) +{ + /* Check the parameters */ + Assert_Param(IS_I2C(I2Cx)); + Assert_Param(IS_I2C_ADDRESS(I2C_Address)); + + I2Cx->ADDR = (I2Cx->ADDR & 0xFF80FFFF) | (ADDR_DEVADDR1_SET | (I2C_Address << 16)); +} + +/*********************************************************************************************************//** + * @brief Enable or Disable I2C own address. + * @param I2Cx: where I2Cx is the selected I2C from the I2C peripherals. + * @param Address: specify the ADDR number. + * This parameter can be one of the following values: + * @arg I2C_DEV_ADDR_0 : + * @arg I2C_DEV_ADDR_1 : + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void I2C_OwnAddressCmd(HT_I2C_TypeDef* I2Cx, I2C_ADDR_Enum Address, ControlStatus NewState) +{ + u32 value = ADDR_DEVADDR0_SET; + + /* Check the parameters */ + Assert_Param(IS_I2C(I2Cx)); + Assert_Param(IS_I2C_ADDR(Address)); + Assert_Param(IS_CONTROL_STATUS(NewState)); + + if (Address == I2C_DEV_ADDR_1) + { + value = value << 16; + } + + if (NewState != DISABLE) + { + I2Cx->ADDR |= value; + } + else + { + I2Cx->ADDR &= (~value); + } +} +#endif + +/*********************************************************************************************************//** + * @brief Start transmitting to target slave address. + * @param I2Cx: where I2Cx is the selected I2C from the I2C peripherals. + * @param I2C_Address: specify the slave address which will be transmitted. + * @param I2C_Direction: This parameter can be I2C_MASTER_READ or I2C_MASTER_WRITE. + * @retval None + ************************************************************************************************************/ +void I2C_TargetAddressConfig(HT_I2C_TypeDef* I2Cx, I2C_AddressTypeDef I2C_Address, u32 I2C_Direction) +{ + /* Check the parameters */ + Assert_Param(IS_I2C(I2Cx)); + Assert_Param(IS_I2C_ADDRESS(I2C_Address)); + Assert_Param(IS_I2C_DIRECTION(I2C_Direction)); + + /* Make sure the prior stop command has been finished */ + while (I2Cx->CR & 0x2); + + if (I2C_Direction != I2C_MASTER_WRITE) + { + I2Cx->TAR = I2C_Address | I2C_MASTER_READ; + } + else + { + I2Cx->TAR = I2C_Address | I2C_MASTER_WRITE; + } +} + +/*********************************************************************************************************//** + * @brief Send a data word through the I2Cx peripheral. + * @param I2Cx: where I2Cx is the selected I2C from the I2C peripherals. + * @param I2C_Data: Byte to be transmitted. + * @retval None + ************************************************************************************************************/ +void I2C_SendData(HT_I2C_TypeDef* I2Cx, u8 I2C_Data) +{ + /* Check the parameters */ + Assert_Param(IS_I2C(I2Cx)); + + I2Cx->DR = I2C_Data; +} + +/*********************************************************************************************************//** + * @brief Return the received data by the I2Cx peripheral. + * @param I2Cx: where I2Cx is the selected I2C from the I2C peripherals. + * @retval The value of the received data. + ************************************************************************************************************/ +u8 I2C_ReceiveData(HT_I2C_TypeDef* I2Cx) +{ + /* Check the parameters */ + Assert_Param(IS_I2C(I2Cx)); + + return (u8)I2Cx->DR; +} + +/*********************************************************************************************************//** + * @brief Read the specified I2C register and returns its value. + * @param I2Cx: where I2Cx is the selected I2C from the I2C peripherals. + * @param I2C_Register: specify the register to read. + * This parameter can be one of the following values: + * @arg I2C_REGISTER_CR : Control Register + * @arg I2C_REGISTER_IER : Interrupt Enable Register + * @arg I2C_REGISTER_ADDR : Address Register + * @arg I2C_REGISTER_SR : Status Register + * @arg I2C_REGISTER_SHPGR : SCL High Period Generation Register + * @arg I2C_REGISTER_SLPGR : SCL Low Period Generation Register + * @arg I2C_REGISTER_DR : Data Register + * @arg I2C_REGISTER_TAR : Target Register + * @retval None + ************************************************************************************************************/ +u32 I2C_ReadRegister(HT_I2C_TypeDef* I2Cx, u8 I2C_Register) +{ + vu32 tmp = 0; + + /* Check the parameters */ + Assert_Param(IS_I2C(I2Cx)); + Assert_Param(IS_I2C_REGISTER(I2C_Register)); + + tmp = (u32)I2Cx; + tmp += I2C_Register; + return (*(u32 *)tmp); +} + +/*********************************************************************************************************//** + * @brief Check whether the specified I2C flag has been set. + * @param I2Cx: where I2Cx is the selected I2C from the I2C peripherals. + * @param I2C_Flag: specify the flag to be check. + * This parameter can be one of the following values: + * @arg I2C_FLAG_STA : I2C start condition transmitted flag (Master mode) + * @arg I2C_FLAG_STO : I2C stop condition detected flag (Slave flag) + * @arg I2C_FLAG_ADRS : I2C address flag + * @arg I2C_FLAG_GCS : I2C general call flag (Slave mode) + * @arg I2C_FLAG_ARBLOS : I2C arbitration loss flag (Master mode) + * @arg I2C_FLAG_RXNACK : I2C received not acknowledge flag + * @arg I2C_FLAG_BUSERR : I2C bus error flag + * @arg I2C_FLAG_RXDNE : I2C Rx data not empty flag + * @arg I2C_FLAG_TXDE : I2C Tx data empty flag + * @arg I2C_FLAG_RXBF : I2C RX buffer full flag + * @arg I2C_FLAG_BUSBUSY : I2C bus busy flag + * @arg I2C_FLAG_MASTER : I2C master mode flag (Master flag) + * @arg I2C_FLAG_TXNRX : I2C transmitter mode flag + * @retval SET or RESET + ************************************************************************************************************/ +FlagStatus I2C_GetFlagStatus(HT_I2C_TypeDef* I2Cx, u32 I2C_Flag) +{ + /* Check the parameters */ + Assert_Param(IS_I2C(I2Cx)); + Assert_Param(IS_I2C_FLAG(I2C_Flag)); + + if ((I2Cx->SR & I2C_Flag) != (u32)RESET) + { + return (SET); + } + else + { + return (RESET); + } +} + +/*********************************************************************************************************//** + * @brief Check whether the specified I2C status has been active. + * @param I2Cx: where I2Cx is the selected I2C from the I2C peripherals. + * @param I2C_Status: specify the flag that is to be check. + * This parameter can be one of the following values: + * @arg I2C_MASTER_SEND_START + * @arg I2C_MASTER_RECEIVER_MODE + * @arg I2C_MASTER_TRANSMITTER_MODE + * @arg I2C_MASTER_RX_NOT_EMPTY + * @arg I2C_MASTER_RX_NOT_EMPTY_NOBUSY + * @arg I2C_MASTER_TX_EMPTY + * @arg I2C_MASTER_RX_BUFFER_FULL + * @arg I2C_SLAVE_ACK_TRANSMITTER_ADDRESS + * @arg I2C_SLAVE_ACK_RECEIVER_ADDRESS + * @arg I2C_SLAVE_ACK_GCALL_ADDRESS + * @arg I2C_SLAVE_RX_NOT_EMPTY + * @arg I2C_SLAVE_RX_NOT_EMPTY_STOP + * @arg I2C_SLAVE_TX_EMPTY + * @arg I2C_SLAVE_RX_BUFFER_FULL + * @arg I2C_SLAVE_RECEIVED_NACK + * @arg I2C_SLAVE_RECEIVED_NACK_STOP + * @arg I2C_SLAVE_STOP_DETECTED + * @retval SUCCESS or ERROR + ************************************************************************************************************/ +ErrStatus I2C_CheckStatus(HT_I2C_TypeDef* I2Cx, u32 I2C_Status) +{ + /* Check the parameters */ + Assert_Param(IS_I2C(I2Cx)); + Assert_Param(IS_I2C_STATUS(I2C_Status)); + + if (I2Cx->SR == I2C_Status) + { + return (SUCCESS); + } + else + { + return (ERROR); + } +} + +/*********************************************************************************************************//** + * @brief Clear the specified I2C flag. + * @param I2Cx: where I2Cx is the selected I2C from the I2C peripherals. + * @param I2C_Flag: specify the flag that is to be cleared. + * This parameter can be one of the following values: + * @arg I2C_FLAG_ARBLOS : I2C arbitration flag + * @arg I2C_FLAG_RXNACK : I2C receive not acknowledge flag + * @arg I2C_FLAG_BUSERR : I2C Bus error flag + * @retval None + ************************************************************************************************************/ +void I2C_ClearFlag(HT_I2C_TypeDef* I2Cx, u32 I2C_Flag) +{ + /* Check the parameters */ + Assert_Param(IS_I2C(I2Cx)); + Assert_Param(IS_I2C_CLEAR_FLAG(I2C_Flag)); + + I2Cx->SR = I2C_Flag; +} + +/*********************************************************************************************************//** + * @brief Set the interval timing of the high period of the I2C clock. + * @param I2Cx: where I2Cx is the selected I2C from the I2C peripherals. + * @param I2C_HighPeriod: specify the high period that is to be set. + * This parameter must be a number between 0 and 0xFFFF. + * @retval None + ************************************************************************************************************/ +void I2C_SetSCLHighPeriod(HT_I2C_TypeDef* I2Cx, u32 I2C_HighPeriod) +{ + /* Check the parameters */ + Assert_Param(IS_I2C(I2Cx)); + Assert_Param(IS_I2C_SCL_HIGH(I2C_HighPeriod)); + + I2Cx->SHPGR = I2C_HighPeriod; +} + +/*********************************************************************************************************//** + * @brief Set the interval timing of low period of the I2C clock. + * @param I2Cx: where I2Cx is the selected I2C from the I2C peripherals. + * @param I2C_LowPeriod: specify the low period that is to be set. + * This parameter must be a number between 0 and 0xFFFF. + * @retval None + ************************************************************************************************************/ +void I2C_SetSCLLowPeriod(HT_I2C_TypeDef* I2Cx, u32 I2C_LowPeriod) +{ + /* Check the parameters */ + Assert_Param(IS_I2C(I2Cx)); + Assert_Param(IS_I2C_SCL_LOW(I2C_LowPeriod)); + + I2Cx->SLPGR = I2C_LowPeriod; +} + +#if (LIBCFG_PDMA) +/*********************************************************************************************************//** + * @brief Enable or Disable the I2Cx PDMA interface. + * @param I2Cx: where I2Cx is the selected I2C from the I2C peripherals. + * @param I2C_PDMAREQ: specify the I2C PDMA transfer request to be enabled or disabled. + * This parameter can be any combination of the following values: + * @arg I2C_PDMAREQ_TX: Tx PDMA transfer request + * @arg I2C_PDMAREQ_RX: Rx PDMA transfer request + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void I2C_PDMACmd(HT_I2C_TypeDef* I2Cx, u32 I2C_PDMAREQ, ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_I2C(I2Cx)); + Assert_Param(IS_I2C_PDMA_REQ(I2C_PDMAREQ)); + Assert_Param(IS_CONTROL_STATUS(NewState)); + + if (NewState != DISABLE) + { + I2Cx->CR |= I2C_PDMAREQ; + } + else + { + I2Cx->CR &= ~I2C_PDMAREQ; + } +} + +/*********************************************************************************************************//** + * @brief Specify that the next PDMA transfer is the last one. + * @param I2Cx: where I2Cx is the selected I2C from the I2C peripherals. + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void I2C_PDMANACKCmd(HT_I2C_TypeDef* I2Cx, ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_I2C(I2Cx)); + Assert_Param(IS_CONTROL_STATUS(NewState)); + + if (NewState != DISABLE) + { + I2Cx->CR |= CR_PDMANACK_SET; + } + else + { + I2Cx->CR &= CR_PDMANACK_RESET; + } +} +#endif + +/*********************************************************************************************************//** + * @brief Enable or Disable the specified I2C time out function. + * @param I2Cx: where I2Cx is the selected I2C from the I2C peripherals. + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void I2C_TimeOutCmd(HT_I2C_TypeDef* I2Cx, ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_I2C(I2Cx)); + Assert_Param(IS_CONTROL_STATUS(NewState)); + + if (NewState != DISABLE) + { + I2Cx->CR |= CR_ENTOUT_SET; + } + else + { + I2Cx->CR &= CR_ENTOUT_RESET; + } +} + +/*********************************************************************************************************//** + * @brief This function is used to set the I2C timeout value. + * @param I2Cx: where I2Cx is the selected I2C from the I2C peripherals. + * @param I2C_Timeout: specify the timeout value. + * @retval None + ************************************************************************************************************/ +void I2C_SetTimeOutValue(HT_I2C_TypeDef* I2Cx, u32 I2C_Timeout) +{ + /* Check the parameters */ + Assert_Param(IS_I2C(I2Cx)); + Assert_Param(IS_I2C_TIMEOUT(I2C_Timeout)); + + I2Cx->TOUT = (I2C_Timeout | (I2Cx->TOUT & 0xFFFF0000)); +} + +/*********************************************************************************************************//** + * @brief This function is used to set the prescaler of I2C timeout value. + * @param I2Cx: where I2Cx is the selected I2C from the I2C peripherals. + * @param I2C_Prescaler: specify the I2C time out prescaler value. + * This parameter can be one of the following values: + * @arg I2C_PRESCALER_1 : I2C prescaler set to 1 + * @arg I2C_PRESCALER_2 : I2C prescaler set to 2 + * @arg I2C_PRESCALER_4 : I2C prescaler set to 4 + * @arg I2C_PRESCALER_16 : I2C prescaler set to 16 + * @arg I2C_PRESCALER_32 : I2C prescaler set to 32 + * @arg I2C_PRESCALER_64 : I2C prescaler set to 64 + * @arg I2C_PRESCALER_128 : I2C prescaler set to 128 + * @retval None + ************************************************************************************************************/ +void I2C_SetTimeOutPrescaler(HT_I2C_TypeDef* I2Cx, u32 I2C_Prescaler) +{ + /* Check the parameters */ + Assert_Param(IS_I2C(I2Cx)); + Assert_Param(IS_I2C_PRESCALER(I2C_Prescaler)); + + I2Cx->TOUT = (I2C_Prescaler | (I2Cx->TOUT & 0x0000FFFF)); +} + +#if (LIBCFG_I2C_NO_ADDR_MASK == 0) +/*********************************************************************************************************//** + * @brief This function is used to determine the prescaler of I2C timeout value. + * @param I2Cx: where I2Cx is the selected I2C from the I2C peripherals. + * @param I2C_Mask: specify the bit position of I2C slave address to be masked. + * This parameter can be any combination of the following values: + * @arg I2C_MASKBIT_0 : Bit 0 of I2C slave address is masked + * @arg I2C_MASKBIT_1 : Bit 1 of I2C slave address is masked + * @arg I2C_MASKBIT_2 : Bit 2 of I2C slave address is masked + * @arg I2C_MASKBIT_3 : Bit 3 of I2C slave address is masked + * @arg I2C_MASKBIT_4 : Bit 4 of I2C slave address is masked + * @arg I2C_MASKBIT_5 : Bit 5 of I2C slave address is masked + * @arg I2C_MASKBIT_6 : Bit 6 of I2C slave address is masked + * @arg I2C_MASKBIT_7 : Bit 7 of I2C slave address is masked + * @arg I2C_MASKBIT_8 : Bit 8 of I2C slave address is masked + * @arg I2C_MASKBIT_9 : Bit 9 of I2C slave address is masked + * @retval None + ************************************************************************************************************/ +void I2C_AddressMaskConfig(HT_I2C_TypeDef* I2Cx, u32 I2C_Mask) +{ + /* Check the parameters */ + Assert_Param(IS_I2C(I2Cx)); + Assert_Param(IS_I2C_ADDRESS_MASK(I2C_Mask)); + + I2Cx->ADDMR = I2C_Mask; +} +#endif + +/*********************************************************************************************************//** + * @brief Return the received address by the I2Cx peripheral. + * @param I2Cx: where I2Cx is the selected I2C from the I2C peripherals. + * @retval The value of the received address. + ************************************************************************************************************/ +u16 I2C_GetAddressBuffer(HT_I2C_TypeDef* I2Cx) +{ + /* Check the parameters */ + Assert_Param(IS_I2C(I2Cx)); + + return ((u16)I2Cx->ADDSR); +} + +/*********************************************************************************************************//** + * @brief Enable or Disable the combinational filter. + * @param I2Cx: where I2Cx is the selected I2C from the I2C peripherals. + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void I2C_CombFilterCmd(HT_I2C_TypeDef* I2Cx, ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_I2C(I2Cx)); + Assert_Param(IS_CONTROL_STATUS(NewState)); + + if (NewState != DISABLE) + { + I2Cx->CR |= CR_COMBFILTER_SET; + } + else + { + I2Cx->CR &= CR_COMBFILTER_RESET; + } +} + +/*********************************************************************************************************//** + * @brief This function is used to determine the filter glitch width of 0~2 PCLK. + * @param I2Cx: where I2Cx is the selected I2C from the I2C peripherals. + * @param Seq_Filter_Select: specify the glitch width of 0~2 PCLK. + * This parameter can be any combination of the following values: + * @arg SEQ_FILTER_DISABLE : sequential filter is disabled + * @arg SEQ_FILTER_1_PCLK : filter glitch width of 1 PCLK + * @arg SEQ_FILTER_2_PCLK : filter glitch width of 2 PCLK + * @retval None + ************************************************************************************************************/ +void I2C_SequentialFilterConfig(HT_I2C_TypeDef* I2Cx, u32 Seq_Filter_Select) +{ + u32 SHPGR = I2Cx->SHPGR; + u32 SLPGR = I2Cx->SLPGR; + + /* Check the parameters */ + Assert_Param(IS_I2C(I2Cx)); + Assert_Param(IS_I2C_SEQ_FILTER_MASK(Seq_Filter_Select)); + + switch (I2Cx->CR & 0xC000) + { + case 0: + if (Seq_Filter_Select == SEQ_FILTER_1_PCLK) + { + if (SHPGR >= 2) + { + SHPGR -= 2; + SLPGR -= 2; + } + } + else if (Seq_Filter_Select == SEQ_FILTER_2_PCLK) + { + if (SHPGR >= 2) + { + SHPGR -= 3; + SLPGR -= 3; + } + } + break; + + case 0x4000: + if (Seq_Filter_Select == SEQ_FILTER_DISABLE) + { + SHPGR += 2; + SLPGR += 2; + } + else if (Seq_Filter_Select == SEQ_FILTER_2_PCLK) + { + if (SHPGR >= 1) + { + SHPGR -= 1; + SLPGR -= 1; + } + } + break; + + case 0x8000: + if (Seq_Filter_Select == SEQ_FILTER_DISABLE) + { + SHPGR += 3; + SLPGR += 3; + } + else if (Seq_Filter_Select == SEQ_FILTER_1_PCLK) + { + SHPGR += 1; + SLPGR += 1; + } + break; + + default: + break; + } + + I2Cx->SHPGR = SHPGR; + I2Cx->SLPGR = SLPGR; + I2Cx->CR = (I2Cx->CR & 0x3FFF) | Seq_Filter_Select; +} +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/ht32f5xxxx_i2s.c b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/ht32f5xxxx_i2s.c new file mode 100644 index 0000000000..4ca971eed1 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/ht32f5xxxx_i2s.c @@ -0,0 +1,336 @@ +/*********************************************************************************************************//** + * @file ht32f5xxxx_i2s.c + * @version $Rev:: 4829 $ + * @date $Date:: 2020-07-23 #$ + * @brief This file provides all the I2S firmware functions. + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ + +/* Includes ------------------------------------------------------------------------------------------------*/ +#include "ht32f5xxxx_i2s.h" + +/** @addtogroup HT32F5xxxx_Peripheral_Driver HT32F5xxxx Peripheral Driver + * @{ + */ + +/** @defgroup I2S I2S + * @brief I2S driver modules + * @{ + */ + + +/* Private constants ---------------------------------------------------------------------------------------*/ +/** @defgroup I2S_Private_Define I2S private definitions + * @{ + */ +#define I2S_EN (1UL) +#define MCLK_OP_EN (1UL << 9) +#define TX_MUTE_EN (1UL << 12) +#define CLK_DIV_EN (1UL << 15) +#define BCLK_INV_EN (1UL << 18) +#define MCLK_INV_EN (1UL << 19) + +#define I2S_SLAVE (1UL << 3) +/** + * @} + */ + + +/* Global functions ----------------------------------------------------------------------------------------*/ +/** @defgroup I2S_Exported_Functions I2S exported functions + * @{ + */ +/*********************************************************************************************************//** + * @brief Deinitialize the I2S peripheral registers to their default reset values. + * @retval None + ************************************************************************************************************/ +void I2S_DeInit(void) +{ + RSTCU_PeripReset_TypeDef RSTCUReset = {{0}}; + + RSTCUReset.Bit.I2S = 1; + RSTCU_PeripReset(RSTCUReset, ENABLE); +} + +/*********************************************************************************************************//** + * @brief Initialize the I2S peripheral according to the specified parameters in the I2S_InitStruct. + * @param I2S_InitStruct: pointer to a I2S_InitTypeDef structure. + * @retval None + ************************************************************************************************************/ +void I2S_Init(I2S_InitTypeDef* I2S_InitStruct) +{ + /* Check the parameters */ + Assert_Param(IS_I2S_MODE(I2S_InitStruct->I2S_Mode)); + Assert_Param(IS_I2S_FORMAT(I2S_InitStruct->I2S_Format)); + Assert_Param(IS_I2S_WORD_WIDTH(I2S_InitStruct->I2S_WordWidth)); + Assert_Param(IS_I2S_MCLK_DIV(I2S_InitStruct->I2S_X_Div, I2S_InitStruct->I2S_Y_Div)); + Assert_Param(IS_I2S_BCLK_DIV(I2S_InitStruct->I2S_N_Div)); + + HT_I2S->CR = I2S_InitStruct->I2S_Mode | I2S_InitStruct->I2S_Format | I2S_InitStruct->I2S_WordWidth; + + if (I2S_InitStruct->I2S_BclkInv == ENABLE) + { + HT_I2S->CR |= BCLK_INV_EN; + } + + if (I2S_InitStruct->I2S_MclkInv == ENABLE) + { + HT_I2S->CR |= MCLK_INV_EN; + } + + if ((I2S_InitStruct->I2S_Mode & I2S_SLAVE) == RESET) + { + HT_I2S->CDR = (I2S_InitStruct->I2S_N_Div << 16) | (I2S_InitStruct->I2S_X_Div << 8) | + (I2S_InitStruct->I2S_Y_Div); + HT_I2S->CR |= CLK_DIV_EN; + while (I2S_GetFlagStatus(I2S_FLAG_CLK_RDY) == RESET); + + if (I2S_InitStruct->I2S_MclkOut == ENABLE) + { + HT_I2S->CR |= MCLK_OP_EN; + } + } +} + +/*********************************************************************************************************//** + * @brief Enable or Disable the I2S peripheral. + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void I2S_Cmd(ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_CONTROL_STATUS(NewState)); + + if (NewState != DISABLE) + { + HT_I2S->CR |= I2S_EN; + } + else + { + HT_I2S->CR &= ~I2S_EN; + } +} + +/*********************************************************************************************************//** + * @brief Enable or Disable the Tx mute for the I2S peripheral. + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void I2S_TxMuteCmd(ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_CONTROL_STATUS(NewState)); + + if (NewState != DISABLE) + { + HT_I2S->CR |= TX_MUTE_EN; + } + else + { + HT_I2S->CR &= ~TX_MUTE_EN; + } +} + +/*********************************************************************************************************//** + * @brief Enable or Disable the I2S PDMA interface. + * @param I2S_PDMAREQ: specify the I2S PDMA transfer request to be enabled or disabled. + * This parameter can be any combination of the following values: + * @arg I2S_PDMAREQ_TX : Tx PDMA transfer request + * @arg I2S_PDMAREQ_RX : Rx PDMA transfer request + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void I2S_PDMACmd(u32 I2S_PDMAREQ, ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_I2S_PDMA_REQ(I2S_PDMAREQ)); + Assert_Param(IS_CONTROL_STATUS(NewState)); + + if (NewState != DISABLE) + { + HT_I2S->CR |= I2S_PDMAREQ; + } + else + { + HT_I2S->CR &= I2S_PDMAREQ; + } +} + +/*********************************************************************************************************//** + * @brief Reset the specified I2S FIFO. + * @param I2S_FIFO: specify the FIFO that is to be reset. + * This parameter can be any combination of the following values: + * @arg I2S_TX_FIFO : I2S Tx FIFO + * @arg I2S_RX_FIFO : I2S Rx FIFO + * @retval None + ************************************************************************************************************/ +void I2S_FIFOReset(u32 I2S_FIFO) +{ + /* Check the parameters */ + Assert_Param(IS_I2S_TWO_FIFO(I2S_FIFO)); + + HT_I2S->FCR |= I2S_FIFO; +} + +/*********************************************************************************************************//** + * @brief Set the trigger level of specified I2S FIFO. + * @param I2S_FIFO: specify the FIFO that is to be set. + * This parameter can be any combination of the following values: + * @arg I2S_TX_FIFO : I2S Tx FIFO + * @arg I2S_RX_FIFO : I2S Rx FIFO + * @param I2S_FIFOLevel: Specify the FIFO trigger level. + * @retval None + ************************************************************************************************************/ +void I2S_FIFOTrigLevelConfig(u32 I2S_FIFO, u32 I2S_FIFOLevel) +{ + /* Check the parameters */ + Assert_Param(IS_I2S_TWO_FIFO(I2S_FIFO)); + Assert_Param(IS_I2S_FIFO_LEVEL(I2S_FIFOLevel)); + + if (I2S_FIFO == I2S_TX_FIFO) + { + HT_I2S->FCR = ((HT_I2S->FCR & (~0x0000000F)) | I2S_FIFOLevel); + } + else + { + HT_I2S->FCR = ((HT_I2S->FCR & (~0x000000F0)) | (I2S_FIFOLevel << 4)); + } +} + +/*********************************************************************************************************//** + * @brief Return the status of specified I2S FIFO. + * @param I2S_FIFO: specify the FIFO that is to be checked. + * This parameter can be one of the following values: + * @arg I2S_TX_FIFO : I2S Tx FIFO + * @arg I2S_RX_FIFO : I2S Rx FIFO + * @retval The number of data in specified I2S FIFO. + ************************************************************************************************************/ +u8 I2S_GetFIFOStatus(u32 I2S_FIFO) +{ + /* Check the parameters */ + Assert_Param(IS_I2S_ONE_FIFO(I2S_FIFO)); + + if (I2S_FIFO == I2S_TX_FIFO) + { + return (u8)((HT_I2S->SR >> 24) & 0x0F); + } + else + { + return (u8)(HT_I2S->SR >> 28); + } +} + +/*********************************************************************************************************//** + * @brief Enable or Disable the I2S interrupt. + * @param I2S_Int: specify if the I2S interrupt source to be enabled or disabled. + * This parameter can be any combination of the following values: + * @arg I2S_INT_TXFIFO_TRI : I2S Tx FIFO trigger level interrupt + * @arg I2S_INT_TXFIFO_UF : I2S Rx FIFO underflow interrupt + * @arg I2S_INT_TXFIFO_OV : I2S Tx FIFO overflow interrupt + * @arg I2S_INT_RXFIFO_TRI : I2S Rx FIFO trigger level interrupt + * @arg I2S_INT_RXFIFO_UV : I2S Rx FIFO underflow interrupt + * @arg I2S_INT_RXFIFO_OV : I2S Rx FIFO overflow interrupt + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void I2S_IntConfig(u32 I2S_Int, ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_I2S_INT(I2S_Int)); + Assert_Param(IS_CONTROL_STATUS(NewState)); + + if (NewState != DISABLE) + { + HT_I2S->IER |= I2S_Int; + } + else + { + HT_I2S->IER &= ~I2S_Int; + } +} + +/*********************************************************************************************************//** + * @brief Check whether the specified I2S flag has been set or not. + * @param I2S_Flag: specify the flag that is to be check. + * This parameter can be one of the following values: + * @arg I2S_FLAG_TXFIFO_TRI : I2S Tx FIFO trigger level flag + * @arg I2S_FLAG_TXFIFO_UDF : I2S Tx FIFO underflow flag + * @arg I2S_FLAG_TXFIFO_OVF : I2S Tx FIFO overflow flag + * @arg I2S_FLAG_TXFIFO_EMP : I2S Tx FIFO empty flag + * @arg I2S_FLAG_TXFIFO_FUL : I2S Tx FIFO full flag + * @arg I2S_FLAG_RXFIFO_TRI : I2S Rx FIFO trigger level flag + * @arg I2S_FLAG_RXFIFO_UDF : I2S Rx FIFO underflow flag + * @arg I2S_FLAG_RXFIFO_OVF : I2S Rx FIFO overflow flag + * @arg I2S_FLAG_RXFIFO_EMP : I2S Rx FIFO empty flag + * @arg I2S_FLAG_RXFIFO_FUL : I2S Rx FIFO full flag + * @arg I2S_FLAG_RIGHT_CH : I2S right channel flag + * @arg I2S_FLAG_TX_BUSY : I2S Tx busy flag + * @arg I2S_FLAG_CLK_RDY : I2S clock ready flag + * @retval SET or RESET + ************************************************************************************************************/ +FlagStatus I2S_GetFlagStatus(u32 I2S_Flag) +{ + /* Check the parameters */ + Assert_Param(IS_I2S_FLAG(I2S_Flag)); + + if (HT_I2S->SR & I2S_Flag) + { + return SET; + } + else + { + return RESET; + } +} + +/*********************************************************************************************************//** + * @brief Clear the specified I2S flag. + * @param I2S_Flag: specify the flag that is to be cleared. + * This parameter can be any combination of the following values: + * @arg I2S_FLAG_TXFIFO_TRI : I2S Tx FIFO trigger level flag + * @arg I2S_FLAG_TXFIFO_UV : I2S Tx FIFO underflow flag + * @arg I2S_FLAG_TXFIFO_OV : I2S Tx FIFO overflow flag + * @arg I2S_FLAG_RXFIFO_TRI : I2S Rx FIFO trigger level flag + * @arg I2S_FLAG_RXFIFO_UV : I2S Rx FIFO underflow flag + * @arg I2S_FLAG_RXFIFO_OV : I2S Rx FIFO overflow flag + * @retval None + ************************************************************************************************************/ +void I2S_ClearFlag(u32 I2S_Flag) +{ + /* Check the parameters */ + Assert_Param(IS_I2S_FLAG_CLEAR(I2S_Flag)); + + HT_I2S->SR = I2S_Flag; +} +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/ht32f5xxxx_lcd.c b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/ht32f5xxxx_lcd.c new file mode 100644 index 0000000000..eb61db9359 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/ht32f5xxxx_lcd.c @@ -0,0 +1,577 @@ +/*********************************************************************************************************//** + * @file ht32f5xxxx_lcd.c + * @version $Rev:: 1704 $ + * @date $Date:: 2017-08-17 #$ + * @brief This file provides all the LCD firmware functions. + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ + +/* Includes ------------------------------------------------------------------------------------------------*/ +#include "ht32f5xxxx_lcd.h" + +/** @addtogroup HT32F5xxxx_Peripheral_Driver HT32F5xxxx Peripheral Driver + * @{ + */ + +/** @defgroup LCD LCD + * @brief LCD driver modules + * @{ + */ + +/* Global functions ----------------------------------------------------------------------------------------*/ +/** @defgroup LCD_Exported_Functions LCD exported functions + * @{ + */ +/*********************************************************************************************************//** + * @brief Deinitialize the LCD peripheral registers to their default reset values. + * @retval None + ************************************************************************************************************/ +void LCD_DriverDeInit(void) +{ + RSTCU_PeripReset_TypeDef RSTCUReset = {{0}}; + RSTCUReset.Bit.LCD = 1; + RSTCU_PeripReset(RSTCUReset, ENABLE); +} + +/*********************************************************************************************************//** + * @brief Initializes the LCD peripheral according to the specified parameters in the LCD_InitStruct. + * @param LCD_InitStruct: pointer to a LCD_InitTypeDef structure. + * @retval None + ************************************************************************************************************/ +void LCD_DriverInit(LCD_InitTypeDef* LCD_InitStruct) +{ + /* !!! NOTICE !!! + Must wait until the LCDENS = 0 before change the LCD control register. + */ + #if 0 + while (LCD_GetFlagStatus(LCD_FLAG_ENS) == 1); + #endif + + HT_LCD->FCR = (u32)(LCD_InitStruct->LCD_Prescaler) | + (u32)(LCD_InitStruct->LCD_Divider); + + HT_LCD->CR = (u32)(LCD_InitStruct->LCD_Waveform) | + (u32)(LCD_InitStruct->LCD_Bias) | + (u32)(LCD_InitStruct->LCD_Duty) | + (u32)(LCD_InitStruct->LCD_VoltageSource); +} + +/*********************************************************************************************************//** + * @brief Configure the MCONT mask time. + * @param Sel: specify the mask time. + * This parameter can be: + * @arg LCD_MaskTime_25ns : MCONT mask time is 25 ns + * @arg LCD_MaskTime_40ns : MCONT mask time is 40 ns + * @retval None + ************************************************************************************************************/ +void LCD_MaskTimeConfig(LCD_MaskTime_Enum Sel) +{ + /* !!! NOTICE !!! + Must wait until the LCDENS = 0 before change the LCD control register. + */ + #if 0 + while (LCD_GetFlagStatus(LCD_FLAG_ENS) == 1); + #endif + + HT_LCD->CR = (HT_LCD->CR & ~(1ul << 24)) | Sel; +} + +/*********************************************************************************************************//** + * @brief Enable or Disable half of the low value resistor (HRLEN). + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void LCD_HalfRLCmd(ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_CONTROL_STATUS(NewState)); + + if (NewState != DISABLE) + { + HT_LCD->CR |= (1ul << 15); + } + else + { + HT_LCD->CR &= ~(1ul << 15); + } +} + +/*********************************************************************************************************//** + * @brief Configure the STATIC switch. + * @param Sel: specify the STATIC switch status. + * This parameter can be: + * @arg LCD_Static_Switch_Open : STATIC switch is open during dead time. + * @arg LCD_Static_Switch_close : STATIC switch is closed during dead time. + * @retval None + ************************************************************************************************************/ +void LCD_StaticSwitchConfig(LCD_StaticSwitch_Enum Sel) +{ + /* !!! NOTICE !!! + Must wait until the LCDENS = 0 before change the LCD control register. + */ + #if 0 + while (LCD_GetFlagStatus(LCD_FLAG_ENS) == 1); + #endif + + HT_LCD->CR = (HT_LCD->CR & ~(1ul << 14)) | Sel; +} + +/*********************************************************************************************************//** + * @brief Configure MuxCOM7 to be COM7 or SEGx. + * @param Sel: Specify the MuxSEG. + * This parameter can be one of the following values: + * @arg LCD_MUXCOM7_IS_COM7 : + * @arg LCD_MUXCOM7_IS_SEGx :(52341: SEG28, 57352: SEG36) + * @retval None + ************************************************************************************************************/ +void LCD_MuxCOM7Config(LCD_MUXCOM7_Enum Sel) +{ + /* !!! NOTICE !!! + Must wait until the LCDENS = 0 before change the LCD control register. + */ + #if 0 + while (LCD_GetFlagStatus(LCD_FLAG_ENS) == 1); + #endif + + HT_LCD->CR = (HT_LCD->CR & ~(1ul << 11)) | Sel; +} + +/*********************************************************************************************************//** + * @brief Configure MuxCOM6 to be COM6 or SEGx. + * @param Sel: Specify the MuxSEG. + * This parameter can be one of the following values: + * @arg LCD_MUXCOM7_IS_COM6 : + * @arg LCD_MUXCOM7_IS_SEGx :(52341: SEG27, 57352: SEG35) + * @retval None + ************************************************************************************************************/ +void LCD_MuxCOM6Config(LCD_MUXCOM6_Enum Sel) +{ + /* !!! NOTICE !!! + Must wait until the LCDENS = 0 before change the LCD settings. + */ + #if 0 + while (LCD_GetFlagStatus(LCD_FLAG_ENS) == 1); + #endif + + HT_LCD->CR = (HT_LCD->CR & ~(1ul << 10)) | Sel; +} + +/*********************************************************************************************************//** + * @brief Configure MuxCOM5 to be COM5 or SEGx. + * @param Sel: Specify the MuxSEG. + * This parameter can be one of the following values: + * @arg LCD_MUXCOM7_IS_COM5 : + * @arg LCD_MUXCOM7_IS_SEGx :(52341: SEG26, 57352: SEG34) + * @retval None + ************************************************************************************************************/ +void LCD_MuxCOM5Config(LCD_MUXCOM5_Enum Sel) +{ + /* !!! NOTICE !!! + Must wait until the LCDENS = 0 before change the LCD settings. + */ + #if 0 + while (LCD_GetFlagStatus(LCD_FLAG_ENS) == 1); + #endif + + HT_LCD->CR = (HT_LCD->CR & ~(1ul << 9)) | Sel; +} + +/*********************************************************************************************************//** + * @brief Configure MuxCOM4 to be COM4 or SEGx. + * @param Sel: Specify the MuxSEG. + * This parameter can be one of the following values: + * @arg LCD_MUXCOM7_IS_COM4 : + * @arg LCD_MUXCOM7_IS_SEGx :(52341: SEG25, 57352: SEG33) + * @retval None + ************************************************************************************************************/ +void LCD_MuxCOM4Config(LCD_MUXCOM4_Enum Sel) +{ + /* !!! NOTICE !!! + Must wait until the LCDENS = 0 before change the LCD settings. + */ + #if 0 + while (LCD_GetFlagStatus(LCD_FLAG_ENS) == 1); + #endif + + HT_LCD->CR = (HT_LCD->CR & ~(1ul << 8)) | Sel; +} + +/*********************************************************************************************************//** + * @brief Configure the LCD waveform type. + * @param Sel: specify the LCD waveform type. + * This parameter can be one of the following values: + * @arg LCD_Type_A_Waveform : Type A waveform + * @arg LCD_Type_B_Waveform : Type B waveform + * @retval None + ************************************************************************************************************/ +void LCD_WaveformConfig(LCD_Waveform_Enum Sel) +{ + /* !!! NOTICE !!! + Must wait until the LCDENS = 0 before change the LCD settings. + */ + #if 0 + while (LCD_GetFlagStatus(LCD_FLAG_ENS) == 1); + #endif + + HT_LCD->CR = (HT_LCD->CR & ~(1ul << 7)) | Sel; +} + +/*********************************************************************************************************//** + * @brief Configure LCD Bias Selector. + * @param Sel: Specify LCD Bias Selector. + * This parameter can be one of the following values: + * @arg LCD_Bias_1_4 : Bias 1/4 + * @arg LCD_Bias_1_2 : Bias 1/2 + * @arg LCD_Bias_1_3 : Bias 1/3 + * @arg LCD_Bias_Static : STATIC + * @retval None + ************************************************************************************************************/ +void LCD_BiasConfig(LCD_Bias_Enum Sel) +{ + /* !!! NOTICE !!! + Must wait until the LCDENS = 0 before change the LCD settings. + */ + #if 0 + while (LCD_GetFlagStatus(LCD_FLAG_ENS) == 1); + #endif + + HT_LCD->CR = (HT_LCD->CR & ~(3ul << 5)) | Sel; +} + +/*********************************************************************************************************//** + * @brief Configure the LCD Duty Selection. + * @param Sel: Specify LCD Duty select. + * This parameter can be one of the following values: + * @arg LCD_Duty_Static : Static duty + * @arg LCD_Duty_1_2 : 1/2 duty + * @arg LCD_Duty_1_3 : 1/3 duty + * @arg LCD_Duty_1_4 : 1/4 duty + * @arg LCD_Duty_1_6 : 1/6 duty + * @arg LCD_Duty_1_8 : 1/8 duty + ************************************************************************************************************/ +void LCD_DutyConfig(LCD_Duty_Enum Sel) +{ + /* !!! NOTICE !!! + Must wait until the LCDENS = 0 before change the LCD settings. + */ + #if 0 + while (LCD_GetFlagStatus(LCD_FLAG_ENS) == 1); + #endif + + HT_LCD->CR = (HT_LCD->CR & ~(7ul << 2)) | Sel; +} + +/*********************************************************************************************************//** + * @brief Configure the LCD Power Selection. + * @param Sel: Specify LCD Power select. + * This parameter can be one of the following values: + * @arg LCD_VoltageSource_External : External VLCD + * @arg LCD_VoltageSource_Internal : Internal charge pump + * @retval None + ************************************************************************************************************/ +void LCD_VoltageSourceConfig(LCD_VoltageSource_Enum Sel) +{ + /* !!! NOTICE !!! + Must wait until the LCDENS = 0 before change the LCD settings. + */ + #if 0 + while (LCD_GetFlagStatus(LCD_FLAG_ENS) == 1); + #endif + + HT_LCD->CR = (HT_LCD->CR & ~(1ul << 1)) | Sel; +} + +/*********************************************************************************************************//** + * @brief Enable or Disable the LCD peripheral. + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void LCD_Cmd(ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_CONTROL_STATUS(NewState)); + + if (NewState != DISABLE) + { + HT_LCD->CR |= (1ul << 0); + } + else + { + HT_LCD->CR &= ~(1ul << 0); + } +} + +/*********************************************************************************************************//** + * @brief Configure the LCD 16-bit prescaler. + * @param Sel: specify the LCD 16-bit prescaler setting. + * This parameter can be one of the following values: + * @arg LCD_Prescaler_1 : CK_PS = CK_LCD / 1 + * @arg LCD_Prescaler_2 : CK_PS = CK_LCD / 2 + * @arg LCD_Prescaler_4 : CK_PS = CK_LCD / 4 + * @arg LCD_Prescaler_8 : CK_PS = CK_LCD / 8 + * @arg LCD_Prescaler_16 : CK_PS = CK_LCD / 16 + * @arg LCD_Prescaler_32 : CK_PS = CK_LCD / 32 + * @arg LCD_Prescaler_64 : CK_PS = CK_LCD / 64 + * @arg LCD_Prescaler_128 : CK_PS = CK_LCD / 128 + * @arg LCD_Prescaler_256 : CK_PS = CK_LCD / 256 + * @arg LCD_Prescaler_512 : CK_PS = CK_LCD / 512 + * @arg LCD_Prescaler_1024 : CK_PS = CK_LCD / 1024 + * @arg LCD_Prescaler_2048 : CK_PS = CK_LCD / 2048 + * @arg LCD_Prescaler_4096 : CK_PS = CK_LCD / 4096 + * @arg LCD_Prescaler_8192 : CK_PS = CK_LCD / 8192 + * @arg LCD_Prescaler_16384 : CK_PS = CK_LCD / 16384 + * @arg LCD_Prescaler_32768 : CK_PS = CK_LCD / 32768 + * @retval None + ************************************************************************************************************/ +void LCD_PrescalerConfig(LCD_Prescaler_Enum Sel) +{ + while (LCD_GetFlagStatus(LCD_FLAG_FCRSF) == SET); + HT_LCD->FCR = (HT_LCD->FCR & ~(15ul << 22)) | Sel; +} + +/*********************************************************************************************************//** + * @brief Configure the LCD clock divider. + * @param Sel: specify the LCD clock divider setting. + * This parameter can be one of the following values: + * @arg LCD_Divider_16 : CK_DIV = CK_PS / 16 + * @arg LCD_Divider_17 : CK_DIV = CK_PS / 17 + * @arg LCD_Divider_18 : CK_DIV = CK_PS / 18 + * @arg LCD_Divider_19 : CK_DIV = CK_PS / 19 + * @arg LCD_Divider_20 : CK_DIV = CK_PS / 20 + * @arg LCD_Divider_21 : CK_DIV = CK_PS / 21 + * @arg LCD_Divider_22 : CK_DIV = CK_PS / 22 + * @arg LCD_Divider_23 : CK_DIV = CK_PS / 23 + * @arg LCD_Divider_24 : CK_DIV = CK_PS / 24 + * @arg LCD_Divider_25 : CK_DIV = CK_PS / 25 + * @arg LCD_Divider_26 : CK_DIV = CK_PS / 26 + * @arg LCD_Divider_27 : CK_DIV = CK_PS / 27 + * @arg LCD_Divider_28 : CK_DIV = CK_PS / 28 + * @arg LCD_Divider_29 : CK_DIV = CK_PS / 29 + * @arg LCD_Divider_30 : CK_DIV = CK_PS / 30 + * @arg LCD_Divider_31 : CK_DIV = CK_PS / 31 + * @retval None + ************************************************************************************************************/ +void LCD_DividerConfig(LCD_Divider_Enum Sel) +{ + while (LCD_GetFlagStatus(LCD_FLAG_FCRSF) == SET); + HT_LCD->FCR = (HT_LCD->FCR & ~(15ul << 18)) | Sel; +} + +/*********************************************************************************************************//** + * @brief Configure the LCD Blink Mode Selection. + * @param Sel: Specify LCD Blink Mode Selection. + * This parameter can be one of the following values: + * @arg LCD_BlinkMode_Off : Blink inactive + * @arg LCD_BlinkMode_SEG0_COM0 : SEG0 on COM0 blink + * @arg LCD_BlinkMode_SEG0_AllCOM : SEG0 on All COM blink + * @arg LCD_BlinkMode_AllSEG_AllCOM : All SEG on All COM blink + ************************************************************************************************************/ +void LCD_BlinkModeConfig(LCD_BlinkMode_Enum Sel) +{ + while (LCD_GetFlagStatus(LCD_FLAG_FCRSF) == SET); + HT_LCD->FCR = (HT_LCD->FCR & ~(3ul << 16)) | Sel; +} + +/*********************************************************************************************************//** + * @brief Configure the LCD Blink Frequency Selection. + * @param Sel: Specify LCD Blink Frequency Selection. + * This parameter can be one of the following values: + * @arg LCD_BlinkFrequency_Div8 : Blink frequency = frame rate / 8 + * @arg LCD_BlinkFrequency_Div16 : Blink frequency = frame rate / 16 + * @arg LCD_BlinkFrequency_Div32 : Blink frequency = frame rate / 32 + * @arg LCD_BlinkFrequency_Div64 : Blink frequency = frame rate / 64 + * @arg LCD_BlinkFrequency_Div128 : Blink frequency = frame rate / 128 + * @arg LCD_BlinkFrequency_Div256 : Blink frequency = frame rate / 256 + * @arg LCD_BlinkFrequency_Div512 : Blink frequency = frame rate / 512 + * @arg LCD_BlinkFrequency_Div1024 : Blink frequency = frame rate / 1024 + ************************************************************************************************************/ +void LCD_BlinkFrequencyConfig(LCD_BlinkFrequency_Enum Sel) +{ + while (LCD_GetFlagStatus(LCD_FLAG_FCRSF) == SET); + HT_LCD->FCR = (HT_LCD->FCR & ~(7ul << 13)) | Sel; +} + +/*********************************************************************************************************//** + * @brief Configure the LCD Charge Pump Voltage Selection. + * @param Sel: Specify LCD Charge Pump Voltage Selection. + * This parameter can be one of the following values: + * @arg LCD_ChargePump_2V65 : Charge pump voltage = 2.65 V + * @arg LCD_ChargePump_2V75 : Charge pump voltage = 2.75 V + * @arg LCD_ChargePump_2V85 : Charge pump voltage = 2.85 V + * @arg LCD_ChargePump_2V95 : Charge pump voltage = 2.95 V + * @arg LCD_ChargePump_3V10 : Charge pump voltage = 3.10 V + * @arg LCD_ChargePump_3V25 : Charge pump voltage = 3.25 V + * @arg LCD_ChargePump_3V40 : Charge pump voltage = 3.40 V + * @arg LCD_ChargePump_3V55 : Charge pump voltage = 3.55 V + ************************************************************************************************************/ +void LCD_ChargePumpConfig(LCD_ChargePump_Enum Sel) +{ + /* !!! NOTICE !!! + Must wait until the LCDENS = 0 before change the LCD settings. + */ + #if 0 + while (LCD_GetFlagStatus(LCD_FLAG_ENS) == 1); + #endif + + while (LCD_GetFlagStatus(LCD_FLAG_FCRSF)); + HT_LCD->FCR = (HT_LCD->FCR & ~(7ul << 10)) | Sel; +} + +/*********************************************************************************************************//** + * @brief Configure the LCD Dead Time Duration Selection. + * @param Sel: Specify LCD Dead Time Duration Selection. + This parameter can be one of the following values: + * @arg LCD_Deadtime_0 : No dead time + * @arg LCD_Deadtime_1 : Type A: 1/2 phase period; Type B: 1 phase period + * @arg LCD_Deadtime_2 : Type A: 2/2 phase period; Type B: 2 phase period + * @arg LCD_Deadtime_3 : Type A: 3/2 phase period; Type B: 3 phase period + * @arg LCD_Deadtime_4 : Type A: 4/2 phase period; Type B: 4 phase period + * @arg LCD_Deadtime_5 : Type A: 5/2 phase period; Type B: 5 phase period + * @arg LCD_Deadtime_6 : Type A: 6/2 phase period; Type B: 6 phase period + * @arg LCD_Deadtime_7 : Type A: 7/2 phase period; Type B: 7 phase period + ************************************************************************************************************/ +void LCD_DeadTimeConfig(LCD_DeadTime_Enum Sel) +{ + while (LCD_GetFlagStatus(LCD_FLAG_FCRSF) == SET); + HT_LCD->FCR = (HT_LCD->FCR & ~(7ul << 7)) | Sel; +} + +/*********************************************************************************************************//** + * @brief Configure the LCD High Drive Duration Selection. + * @param Sel: Specify LCD High Drive Duration Selection. + * This parameter LCD_DEAD_Enum can be one of the following values: + * @arg LCD_HighDrive_0 : No high drive + * @arg LCD_HighDrive_1 : High drive duration = 1 CK_PS pulses + * @arg LCD_HighDrive_2 : High drive duration = 2 CK_PS pulses + * @arg LCD_HighDrive_3 : High drive duration = 3 CK_PS pulses + * @arg LCD_HighDrive_4 : High drive duration = 4 CK_PS pulses + * @arg LCD_HighDrive_5 : High drive duration = 5 CK_PS pulses + * @arg LCD_HighDrive_6 : High drive duration = 6 CK_PS pulses + * @arg LCD_HighDrive_7 : High drive duration = 7 CK_PS pulses + * @arg LCD_HighDrive_Static : Static high drive + ************************************************************************************************************/ +void LCD_HighDriveConfig(LCD_HighDrive_Enum Sel) +{ + u32 FCR = HT_LCD->FCR; + + if (Sel == LCD_HighDrive_Static) + { + FCR |= (1ul << 0); + } + else + { + FCR &= ~(1ul << 0); + FCR = (FCR & ~(7ul << 4)) | Sel; + } + + while (LCD_GetFlagStatus(LCD_FLAG_FCRSF)); + HT_LCD->FCR = FCR; +} + +/*********************************************************************************************************//** + * @brief Enable or Disable the specified LCD interrupts. + * @param LCD_INT: Specify the LCD interrupt sources that is to be enabled or disabled. + * This parameter can be any combination of the following values: + * @arg LCD_INT_UDDIE : Update Display Done Interrupt Enable + * @arg LCD_INT_SOFIE : Start of Frame Interrupt Enable + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void LCD_IntConfig(u32 LCD_INT, ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_LCD_INT(LCD_INT)); + Assert_Param(IS_CONTROL_STATUS(NewState)); + + if (NewState != DISABLE) + { + HT_LCD->IER |= LCD_INT; + } + else + { + HT_LCD->IER &= ~LCD_INT; + } +} + +/*********************************************************************************************************//** + * @brief Check whether the specified LCD flag has been set. + * @param LCD_FLAG: Specify the interrupt status to check. + * This parameter can be any combination of the following values: + * @arg LCD_FLAG_FCRSF : LCD Frame Control Register Synchronization Flag + * @arg LCD_FLAG_RDY : Ready Flag + * @arg LCD_FLAG_UDD : Update Display Done + * @arg LCD_FLAG_UDR : Update Display Request + * @arg LCD_FLAG_SOF : Start of Frame Flag + * @arg LCD_FLAG_ENS : LCD Enabled Status + * @retval SET or RESET + ************************************************************************************************************/ +FlagStatus LCD_GetFlagStatus(u32 LCD_FLAG) +{ + /* Check the parameters */ + Assert_Param(IS_LCD_FLAG(LCD_FLAG)); + + if ((HT_LCD->SR & LCD_FLAG) != RESET) + { + return SET; + } + else + { + return RESET; + } +} + +/*********************************************************************************************************//** + * @brief SET LCD Update Display Request. + * @retval None + ************************************************************************************************************/ +void LCD_SetUpdateDisplayRequest(void) +{ + HT_LCD->SR |= LCD_FLAG_UDR; +} + +/*********************************************************************************************************//** + * @brief Clear the specified LCD flag. + * @param LCD_Flag: specify the flag that is to be cleared. + * This parameter can be one of the following values: + * @arg LCD_CLR_UDDC : Update display done clear + * @arg LCD_CLR_SOFC : Start of frame flag clear + * @retval None + ************************************************************************************************************/ +void LCD_ClearFlag(u32 LCD_Flag) +{ + /* Check the parameters */ + Assert_Param(IS_LCD_CLEAR(LCD_Flag)); + + HT_LCD->CLR = LCD_Flag; +} +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/ht32f5xxxx_ledc.c b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/ht32f5xxxx_ledc.c new file mode 100644 index 0000000000..37a340dd7f --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/ht32f5xxxx_ledc.c @@ -0,0 +1,309 @@ +/*********************************************************************************************************//** + * @file ht32f5xxxx_ledc.c + * @version $Rev:: 6374 $ + * @date $Date:: 2022-10-25 #$ + * @brief This file provides all the LEDC firmware functions. + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ + +/* Includes ------------------------------------------------------------------------------------------------*/ +#include "ht32f5xxxx_ledc.h" + +/** @addtogroup HT32F5xxxx_Peripheral_Driver HT32F5xxxx Peripheral Driver + * @{ + */ + +/** @defgroup LEDC LEDC + * @brief LEDC driver modules + * @{ + */ + + +/* Private constants ---------------------------------------------------------------------------------------*/ +/** @defgroup LEDC_Private_Define LEDC private definitions + * @{ + */ +#define RPRE_MASK 0xF000FFFF + +/** + * @} + */ + +/* Global functions ----------------------------------------------------------------------------------------*/ +/** @defgroup LEDC_Exported_Functions LEDC exported functions + * @{ + */ +/*********************************************************************************************************//** + * @brief Deinitialize the LEDC peripheral registers to their default reset values. + * @retval None + ************************************************************************************************************/ +void LEDC_DeInit(void) +{ + RSTCU_PeripReset_TypeDef RSTCUReset = {{0}}; + RSTCUReset.Bit.LEDC = 1; + RSTCU_PeripReset(RSTCUReset, ENABLE); +} + +/*********************************************************************************************************//** + * @brief Initialize the LEDC peripheral according to the specified parameters in the LEDC_InitStruct. + * @param LEDC_InitStruct: Pointer to a LEDC_InitTypeDef structure. Please note the following. + 1. When LEDC is started, the LEDC_ClockSource, LEDC_ClockPrescaler and LEDC_DeadTime can't + be changed, so LEDC_Init() will turn off the LED first.You need to restart LEDC by + LEDC_Cmd(ENABEL). + 2. The LEDC_DeadTime number must be less than the LEDC_Prescaler. + Example: + If LEDC_DutyClockNumber selects LEDC_DTYNUM_8, the valid LEDC_DeadTime ranges from 0 to 7. + If LEDC_DutyClockNumber selects LEDC_DTYNUM_16, the valid LEDC_DeadTime ranges from 0 to 15. + If LEDC_DutyClockNumber selects LEDC_DTYNUM_32, the valid LEDC_DeadTime ranges from 0 to 31. + If LEDC_DutyClockNumber selects LEDC_DTYNUM_64, the valid LEDC_DeadTime ranges from 0 to 63. + * @retval None + ************************************************************************************************************/ +void LEDC_Init(LEDC_InitTypeDef* LEDC_InitStruct) +{ + /* Check the parameters */ + Assert_Param(IS_LEDC_SRC(LEDC_InitStruct->LEDC_ClockSource)); + Assert_Param(IS_LEDC_DTYNUM(LEDC_InitStruct->LEDC_DutyClockNumber)); + Assert_Param(IS_LEDC_PSC(LEDC_InitStruct->LEDC_ClockPrescaler)); + Assert_Param(IS_LEDC_COMEN(LEDC_InitStruct->LEDC_COMxEN)); + Assert_Param(IS_LEDC_DTCR(LEDC_InitStruct->LEDC_DeadTime)); + + /* Disable LEDC */ + HT_LEDC->CR = 0; + + /* LEDC Control Register Configuration */ + HT_LEDC->CR = LEDC_InitStruct->LEDC_ClockSource << 8 |\ + LEDC_InitStruct->LEDC_DutyClockNumber << 12 |\ + LEDC_InitStruct->LEDC_ClockPrescaler << 16; + + /* LEDC COM Enable Register Configuration */ + HT_LEDC->CER = LEDC_InitStruct->LEDC_COMxEN; + + /* LEDC Dead Time Control Register Configuration */ + HT_LEDC->DTCR = LEDC_InitStruct->LEDC_DeadTime; +} + +/*********************************************************************************************************//** + * @brief Select the LEDC timer clock source. + * @param Source: specify the clock source of LEDC. + * @arg LEDC_SRC_PCLK + * @arg LEDC_SRC_LSI : Low speed internal clock. + * @arg LEDC_SRC_LSE : Low speed external clock. + * @retval None + ************************************************************************************************************/ +void LEDC_ClockSourceConfig(LEDC_SRC_Enum Source) +{ + Assert_Param(IS_LEDC_SRC(Source)); + + HT_LEDC->CR = (HT_LEDC->CR & ~(3UL << 8)) | ((u32)Source << 8); +} + +/*********************************************************************************************************//** + * @brief Configure the LEDC prescaler. + * @param Psc: Value of LEDC prescaler: 0~4095 + * This parameter can be one of following values: + * @retval None + ************************************************************************************************************/ +void LEDC_SetPrescaler(u32 Psc) +{ + Assert_Param(IS_LEDC_PSC(Psc)); + + HT_LEDC->CR = (HT_LEDC->CR & RPRE_MASK) | (Psc << 16); +} + +/*********************************************************************************************************//** + * @brief Enable or Disable the LEDC. + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void LEDC_Cmd(ControlStatus NewState) +{ + if (NewState != DISABLE) + { + HT_LEDC->CR |= (1UL); + } + else + { + HT_LEDC->CR &= ~(1UL); + } +} + +/*********************************************************************************************************//** + * @brief Enable or Disable Frame interrupt. + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void LEDC_IntConfig(ControlStatus NewState) +{ + if (NewState != DISABLE) + { + HT_LEDC->IER |= LEDC_INT_FRAME; + } + else + { + HT_LEDC->IER &= ~LEDC_INT_FRAME; + } +} + +/*********************************************************************************************************//** + * @brief Get the LEDC flag. + * @retval SET or RESET + ************************************************************************************************************/ +FlagStatus LEDC_GetFlagStatus(void) +{ + if (HT_LEDC->SR & LEDC_FLAG_FRAME) + { + return SET; + } + else + { + return RESET; + } +} + +/*********************************************************************************************************//** + * @brief Clear the LEDC graflag. + * @retval None + ************************************************************************************************************/ +void LEDC_ClearFlagStatus(void) +{ + HT_LEDC->SR |= LEDC_FLAG_FRAME; +} + +/*********************************************************************************************************//** + * @brief Configure COMx's state of LEDC with specified pins. + * @param LEDC_COMxEN: This parameter can be any combination of the following values: + * @arg LEDC_COM0EN : Set LEDC COM0 + * @arg LEDC_COM1EN : Set LEDC COM1 + * @arg LEDC_COM2EN : Set LEDC COM2 + * @arg LEDC_COM3EN : Set LEDC COM3 + * @arg LEDC_COM4EN : Set LEDC COM4 + * @arg LEDC_COM5EN : Set LEDC COM5 + * @arg LEDC_COM6EN : Set LEDC COM6 + * @arg LEDC_COM7EN : Set LEDC COM7 + * @arg LEDC_COM8EN : Set LEDC COM8(Only support 54253 ) + * @arg LEDC_COM9EN : Set LEDC COM9(Only support 54253 ) + * @arg LEDC_COM10EN : Set LEDC COM10(Only support 54253 ) + * @arg LEDC_COM11EN : Set LEDC COM11(Only support 54253 ) + * @param Cmd: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void LEDC_COMxConfig(u32 LEDC_COMxEN, ControlStatus Cmd) +{ + /* Check the parameters */ + Assert_Param(IS_LEDC_COMEN(LEDC_COMxEN)); + + if (Cmd != DISABLE) + HT_LEDC->CER |= LEDC_COMxEN; + else + HT_LEDC->CER &= ~LEDC_COMxEN; +} + +/*********************************************************************************************************//** + * @brief Configure the dead time duty. The LED brightness can be adjusted by adjusting the dead duty. + * @param LEDC_DeadTimeDuty: Deadtime Clock Numbers. The LEDC_DeadTimeDuty number must be less than the + LEDC_DutyClockNumber(DTYNUM). + Example: + If LEDC_DutyClockNumber selects LEDC_DTYNUM_8, the valid LEDC_DeadTime ranges from 0 to 7. + If LEDC_DutyClockNumber selects LEDC_DTYNUM_16, the valid LEDC_DeadTime ranges from 0 to 15. + If LEDC_DutyClockNumber selects LEDC_DTYNUM_32, the valid LEDC_DeadTime ranges from 0 to 31. + If LEDC_DutyClockNumber selects LEDC_DTYNUM_64, the valid LEDC_DeadTime ranges from 0 to 63. + * @retval None + ************************************************************************************************************/ +void LEDC_SetDeadTimeDuty(u32 LEDC_DeadTimeDuty) +{ + /* Check the parameters */ + Assert_Param(IS_LEDC_DTCR(LEDC_DeadTimeDuty)); + + HT_LEDC->DTCR = LEDC_DeadTimeDuty; +} + +/*********************************************************************************************************//** + * @brief Set the output polarity of COM and SEG. + * @param LEDC_COMxPOL: This parameter can be any combination of the following values: + * @arg LEDC_COM0POL : Set COM0 polarity + * @arg LEDC_COM1POL : Set COM1 polarity + * @arg LEDC_COM2POL : Set COM2 polarity + * @arg LEDC_COM3POL : Set COM3 polarity + * @arg LEDC_COM4POL : Set COM4 polarity + * @arg LEDC_COM5POL : Set COM5 polarity + * @arg LEDC_COM6POL : Set COM6 polarity + * @arg LEDC_COM7POL : Set COM7 polarity + * @arg LEDC_COM8POL : Set COM8 polarity(Only support 54253 ) + * @arg LEDC_COM9POL : Set COM9 polarity(Only support 54253 ) + * @arg LEDC_COM10POL : Set COM10 polarity(Only support 54253 ) + * @arg LEDC_COM11POL : Set COM11 polarity(Only support 54253 ) + * @param LEDC_SEGxPOL: This parameter can be any combination of the following values: + * @arg LEDC_SEG0POL : Set SEG0 polarity + * @arg LEDC_SEG1POL : Set SEG1 polarity + * @arg LEDC_SEG2POL : Set SEG2 polarity + * @arg LEDC_SEG3POL : Set SEG3 polarity + * @arg LEDC_SEG4POL : Set SEG4 polarity + * @arg LEDC_SEG5POL : Set SEG5 polarity + * @arg LEDC_SEG6POL : Set SEG6 polarity + * @arg LEDC_SEG7POL : Set SEG7 polarity + * @param mode: LED layout mode. + * SEG polarity COM polarity + * ------------------------------------------------------- + * @arg COMMON_CATHODE : non-inverted non-inverted + * @arg COMMON_CATHODE_WITH_NPN : non-inverted inverted + * @arg COMMON_ANODE_WITH_PNP : inverted non-inverted + * @arg COMMON_ANODE_WITH_NPN : inverted inverted + * @arg @retval None + ************************************************************************************************************/ +void LEDC_SetPolarityMode(u32 LEDC_COMxPOL, u32 LEDC_SEGxPOL , LEDC_Mode mode) +{ + /* Check the parameters */ + Assert_Param(IS_LEDC_DTCR(mode)); + Assert_Param(IS_LEDC_COMPOL(LEDC_COMxPOL)); + Assert_Param(IS_LEDC_SEGPOL(LEDC_SEGxPOL)); + + switch(mode) + { + case COMMON_CATHODE: + HT_LEDC->PCR &= ~(LEDC_COMxPOL|LEDC_SEGxPOL); + break; + case COMMON_CATHODE_WITH_NPN: + HT_LEDC->PCR |= LEDC_COMxPOL; + HT_LEDC->PCR &= ~(LEDC_SEGxPOL); + break; + case COMMON_ANODE_WITH_PNP: + HT_LEDC->PCR &= ~(LEDC_COMxPOL); + HT_LEDC->PCR |= LEDC_SEGxPOL; + break; + case COMMON_ANODE_WITH_NPN: + HT_LEDC->PCR |= LEDC_COMxPOL|LEDC_SEGxPOL; + break; + } +} + +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/ht32f5xxxx_lstm.c b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/ht32f5xxxx_lstm.c new file mode 100644 index 0000000000..02180b2308 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/ht32f5xxxx_lstm.c @@ -0,0 +1,32 @@ +/*********************************************************************************************************//** + * @file ht32f5xxxx_lstm.c + * @version $Rev:: 6594 $ + * @date $Date:: 2022-12-27 #$ + * @brief This file provides all the LSTM firmware functions (alias file of RTC). + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ + +/* Includes ------------------------------------------------------------------------------------------------*/ +#include "ht32f5xxxx_rtc.c" + +// This is an alias file to map LSTM to RTC, since the LSTM is almost the same as RTC +// It reduces the maintenance effort. diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/ht32f5xxxx_mctm.c b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/ht32f5xxxx_mctm.c new file mode 100644 index 0000000000..d30ac8eced --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/ht32f5xxxx_mctm.c @@ -0,0 +1,293 @@ +/*********************************************************************************************************//** + * @file ht32f5xxxx_mctm.c + * @version $Rev:: 6421 $ + * @date $Date:: 2022-11-03 #$ + * @brief This file provides all the MCTM firmware functions. + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ + +/* Includes ------------------------------------------------------------------------------------------------*/ +#include "ht32f5xxxx_mctm.h" + +/** @addtogroup HT32F5xxxx_Peripheral_Driver HT32F5xxxx Peripheral Driver + * @{ + */ + +/** @defgroup MCTM MCTM + * @brief MCTM driver modules + * @{ + */ + + +/* Private constants ---------------------------------------------------------------------------------------*/ +/** @defgroup MCTM_Private_Define MCTM private definitions + * @{ + */ +#define CTR_COMPRE 0x00000100ul +#define CTR_COMUS 0x00000200ul + +#define CHBRKCTR_CHMOE 0x00000010ul +/** + * @} + */ + + +/* Global functions ----------------------------------------------------------------------------------------*/ +/** @defgroup MCTM_Exported_Functions MCTM exported functions + * @{ + */ + +/*********************************************************************************************************//** + * @brief Configure polarity of the MCTMx channel N. + * @param MCTMx: where MCTMx is the selected MCTM from the MCTM peripheral. + * @param Channel: Specify the MCTM channel. + * This parameter can be one of the following values: + * @arg MCTM_CH_0 : MCTM channel 0 + * @arg MCTM_CH_1 : MCTM channel 1 + * @arg MCTM_CH_2 : MCTM channel 2 + * @arg MCTM_CH_3 : MCTM channel 3 + * @param Pol: Specify the polarity of channel N. + * This parameter can be one of the following values: + * @arg MCTM_CHP_NONINVERTED : active high + * @arg MCTM_CHP_INVERTED : active low + * @retval None + ************************************************************************************************************/ +void MCTM_ChNPolarityConfig(HT_TM_TypeDef* MCTMx, TM_CH_Enum Channel, TM_CHP_Enum Pol) +{ + u32 wChpolr; + + /* Check the parameters */ + Assert_Param(IS_MCTM(MCTMx)); + Assert_Param(IS_MCTM_COMPLEMENTARY_CH(Channel)); + Assert_Param(IS_TM_CHP(Pol)); + + /* Set or reset the CHxN polarity */ + wChpolr = MCTMx->CHPOLR & (~(u32)(0x2 << (Channel << 1))); + MCTMx->CHPOLR = wChpolr | ((Pol << 1) << (Channel << 1)); +} + +/*********************************************************************************************************//** + * @brief Enable or Disable the MCTMx channel N. + * @param MCTMx: where MCTMx is the selected MCTM from the MCTM peripheral. + * @param Channel: Specify the MCTM channel. + * This parameter can be one of the following values: + * @arg MCTM_CH_0 : MCTM channel 0 + * @arg MCTM_CH_1 : MCTM channel 1 + * @arg MCTM_CH_2 : MCTM channel 2 + * @arg MCTM_CH_3 : MCTM channel 3 + * @param Control: This parameter can be TM_CHCTL_ENABLE or TM_CHCTL_DISABLE. + * @retval None + ************************************************************************************************************/ +void MCTM_ChannelNConfig(HT_TM_TypeDef* MCTMx, TM_CH_Enum Channel, TM_CHCTL_Enum Control) +{ + /* Check the parameters */ + Assert_Param(IS_MCTM(MCTMx)); + Assert_Param(IS_MCTM_COMPLEMENTARY_CH(Channel)); + Assert_Param(IS_TM_CHCTL(Control)); + + /* Reset the CHxNE Bit */ + MCTMx->CHCTR &= ~(u32)(0x2 << (Channel << 1)); + + /* Set or reset the CHxNE Bit */ + MCTMx->CHCTR |= (u32)(Control << 1) << (Channel << 1); +} + +/*********************************************************************************************************//** + * @brief Enable or Disable the channels main output of the MCTMx. + * @param MCTMx: where MCTMx is the selected MCTM from the MCTM peripherals. + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void MCTM_CHMOECmd(HT_TM_TypeDef* MCTMx, ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_MCTM(MCTMx)); + Assert_Param(IS_CONTROL_STATUS(NewState)); + + if (NewState != DISABLE) + { + /* Enable the MCTM Main Output */ + MCTMx->CHBRKCTR |= CHBRKCTR_CHMOE; + } + else + { + /* Disable the MCTM Main Output */ + MCTMx->CHBRKCTR &= ~CHBRKCTR_CHMOE; + } +} + +/*********************************************************************************************************//** + * @brief Configure the break feature, dead time, Lock level, the OSSI, the OSSR State + * and the CHAOE(automatic output enable). + * @param MCTMx: where MCTMx is the selected MCTM from the MCTM peripherals. + * @param CHBRKCTRInit: Point to a MCTM_CHBRKCTRInitTypeDef structure. + * @retval None + ************************************************************************************************************/ +void MCTM_CHBRKCTRConfig(HT_TM_TypeDef* MCTMx, MCTM_CHBRKCTRInitTypeDef *CHBRKCTRInit) +{ + u32 wTmpReg; + + /* Check the parameters */ + Assert_Param(IS_MCTM(MCTMx)); + Assert_Param(IS_MCTM_OSSR_STATE(CHBRKCTRInit->OSSRState)); + Assert_Param(IS_MCTM_OSSI_STATE(CHBRKCTRInit->OSSIState)); + Assert_Param(IS_MCTM_LOCK_LEVEL(CHBRKCTRInit->LockLevel)); + Assert_Param(IS_MCTM_BREAK_STATE(CHBRKCTRInit->Break0)); + Assert_Param(IS_MCTM_BREAK_POLARITY(CHBRKCTRInit->Break0Polarity)); + Assert_Param(IS_MCTM_CHAOE_STATE(CHBRKCTRInit->AutomaticOutput)); + Assert_Param(IS_TM_FILTER(CHBRKCTRInit->BreakFilter)); + + wTmpReg = MCTMx->CHBRKCTR & 0x00000010; // Keep CHMOE + wTmpReg |= (u32)CHBRKCTRInit->BreakFilter << 8; + wTmpReg |= (u32)CHBRKCTRInit->DeadTime << 24; + wTmpReg |= CHBRKCTRInit->LockLevel | CHBRKCTRInit->OSSRState | CHBRKCTRInit->OSSIState; + wTmpReg |= CHBRKCTRInit->Break0 | CHBRKCTRInit->Break0Polarity | CHBRKCTRInit->AutomaticOutput; + + MCTMx->CHBRKCTR = wTmpReg; +} + +/*********************************************************************************************************//** + * @brief Configure the break feature, dead time, Lock level, the OSSI, the OSSR State + * and the CHAOE(automatic output enable). + * @param MCTMx: where MCTMx is the selected MCTM from the MCTM peripherals. + * @param CHBRKCTRInit: Point to a MCTM_CHBRKCTRTypeDef structure. + * @retval None + ************************************************************************************************************/ +void MCTM_CHBRKCTRConfig2(HT_TM_TypeDef* MCTMx, MCTM_CHBRKCTRTypeDef *CHBRKCTRInit) +{ + u32 wTmpReg; + + wTmpReg = MCTMx->CHBRKCTR & 0x00000010; // Keep CHMOE + + wTmpReg |= CHBRKCTRInit->Reg; + + MCTMx->CHBRKCTR = wTmpReg; +} + +/*********************************************************************************************************//** + * @brief Fill each CHBRKCTRInitStruct member with its default value. + * @param CHBRKCTRInitStruct: Point to a MCTM_CHBRKCTRInitTypeDef structure. + * @retval None + ************************************************************************************************************/ +void MCTM_CHBRKCTRStructInit(MCTM_CHBRKCTRInitTypeDef* CHBRKCTRInitStruct) +{ + /* Set the default configuration */ + CHBRKCTRInitStruct->OSSRState = MCTM_OSSR_STATE_DISABLE; + CHBRKCTRInitStruct->OSSIState = MCTM_OSSI_STATE_DISABLE; + CHBRKCTRInitStruct->LockLevel = MCTM_LOCK_LEVEL_OFF; + CHBRKCTRInitStruct->DeadTime = 0x00; + CHBRKCTRInitStruct->Break0 = MCTM_BREAK_DISABLE; + CHBRKCTRInitStruct->Break0Polarity = MCTM_BREAK_POLARITY_LOW; + CHBRKCTRInitStruct->BreakFilter = 0; + CHBRKCTRInitStruct->AutomaticOutput = MCTM_CHAOE_DISABLE; +} + +/*********************************************************************************************************//** + * @brief Enable or Disable MCTMx COMPRE function. + * @param MCTMx: where MCTMx is the selected MCTM from the MCTM peripherals. + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void MCTM_COMPRECmd(HT_TM_TypeDef* MCTMx, ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_MCTM(MCTMx)); + Assert_Param(IS_CONTROL_STATUS(NewState)); + + if (NewState != DISABLE) + { + /* Enable the MCTM COMPRE */ + MCTMx->CTR |= CTR_COMPRE; + } + else + { + /* Disable the MCTM COMPRE */ + MCTMx->CTR &= ~CTR_COMPRE; + } +} + +/*********************************************************************************************************//** + * @brief Configure the MCTMx COMUS function. + * @param MCTMx: where MCTMx is the selected MCTM from the MCTM peripherals. + * @param Sel: Specify the COMUS value. + * This parameter can be one of the following values: + * @arg MCTM_COMUS_STIOFF : MCTM capture/compare control bits are updated by setting the UEV2G bit only + * @arg MCTM_COMUS_STION : MCTM capture/compare control bits are updated by both setting the UEV2G bit + * or when a rising edge occurs on STI + * @retval None + ************************************************************************************************************/ +void MCTM_COMUSConfig(HT_TM_TypeDef* MCTMx, MCTM_COMUS_Enum Sel) +{ + /* Check the parameters */ + Assert_Param(IS_MCTM(MCTMx)); + Assert_Param(IS_MCTM_COMUS(Sel)); + + if (Sel != MCTM_COMUS_STIOFF) + { + /* Set the MCTM COMUS bit */ + MCTMx->CTR |= CTR_COMUS; + } + else + { + /* Clear the MCTM COMUS bit */ + MCTMx->CTR &= ~CTR_COMUS; + } +} + +#if (LIBCFG_MCTM_UEV1DIS) +/*********************************************************************************************************//** + * @brief Enable or Disable Overflow/Underflow update event(does not contain interrupt) of the MCTMx. + * @param MCTMx: where MCTMx is the selected MCTM from the MCTM peripherals. + * @param MCTM_UEV1x: MCTM_UEV1UD or MCTM_UEV1OD. Overflow/underflow request disable control. + * @param NewState: This parameter can be SET or RESET. + * @retval None + ************************************************************************************************************/ +void MCTM_UpdateEventDisable(HT_TM_TypeDef* MCTMx, MCTM_UEV1DIS_Enum MCTM_UEV1x, FlagStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_MCTM(MCTMx)); + Assert_Param(IS_CONTROL_STATUS(NewState)); + + if (NewState != RESET) + { + /* Set the update disable bit */ + MCTMx->CNTCFR |= MCTM_UEV1x; + } + else + { + /* Reset the update disable bit */ + MCTMx->CNTCFR &= ~MCTM_UEV1x; + } +} +#endif +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/ht32f5xxxx_midi.c b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/ht32f5xxxx_midi.c new file mode 100644 index 0000000000..15369686b3 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/ht32f5xxxx_midi.c @@ -0,0 +1,1176 @@ +/*********************************************************************************************************//** + * @file ht32f5xxxx_midi.c + * @version $Rev:: 6684 $ + * @date $Date:: 2023-01-18 #$ + * @brief This file provides all the MIDI firmware functions. + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ + +/* Includes ------------------------------------------------------------------------------------------------*/ +#include "ht32f5xxxx_midi.h" + +/** @addtogroup HT32F5xxxx_Peripheral_Driver HT32F5xxxx Peripheral Driver + * @{ + */ + +/** @defgroup MIDI MIDI + * @brief MIDI driver modules + * @{ + */ + + +/* Private constants ---------------------------------------------------------------------------------------*/ +/** @defgroup MIDI_Private_Define MIDI private definitions + * @{ + */ +/* MIDI TRIG ST Mask */ +#define TRIG_ST_ENABLE (u32)0x00000400 +#define TRIG_ST_DISABLE (u32)0xFFFFFBFF + +/* MIDI TRIG VM Mask */ +#define TRIG_VM_ENABLE (u32)0x00000200 +#define TRIG_VM_DISABLE (u32)0xFFFFFDFF + +/* MIDI TRIG FR Mask */ +#define TRIG_FR_ENABLE (u32)0x00000100 +#define TRIG_FR_DISABLE (u32)0xFFFFFEFF + +/* MIDI CHAN CHx Mask */ +#define MIDI_CHAN_CHx_MASK (u32)0x0000001F + +/* MIDI FREQ BL Mask */ +#define MIDI_FREQ_BL_MASK (u32)0x0000F000 + +/* MIDI FREQ FR Mask */ +#define MIDI_FREQ_FR_MASK (u32)0x00000FFF + +/* MIDI VOL AR Mask */ +#define MIDI_VOL_AR_MASK (u32)0x80000000 + +/* MIDI VOL ENV Mask */ +#define MIDI_VOL_ENV_MASK (u32)0x60000000 + +/* MIDI VOL VL Mask */ +#define MIDI_VOL_VL_MASK (u32)0x03FF0000 + +/* MIDI VOL VR Mask */ +#define MIDI_VOL_VR_MASK (u32)0x000003FF + +/* MIDI RENUM WBS Mask */ +#define MIDI_RENUM_WBS_MASK (u32)0x00030000 + +/* MIDI RENUM RE Mask */ +#define MIDI_RENUM_RE_MASK (u32)0x00007FFF + +/* MIDI MCUCH0 CH0B Mask */ +#define MIDI_MCUCH0_CH0B_MASK (u32)0xFFFF0000 + +/* MIDI MCUCH0 CH0A Mask */ +#define MIDI_MCUCH0_CH0A_MASK (u32)0x0000FFFF + +/* MIDI MCUCH1 CH1B Mask */ +#define MIDI_MCUCH1_CH1B_MASK (u32)0xFFFF0000 + +/* MIDI MCUCH1 CH1A Mask */ +#define MIDI_MCUCH1_CH1A_MASK (u32)0x0000FFFF + +/* MIDI MCUCH2 CH2B Mask */ +#define MIDI_MCUCH2_CH2B_MASK (u32)0xFFFF0000 + +/* MIDI MCUCH2 CH2A Mask */ +#define MIDI_MCUCH2_CH2A_MASK (u32)0x0000FFFF + +/* MIDI MCUCH3 CH3B Mask */ +#define MIDI_MCUCH3_CH3B_MASK (u32)0xFFFF0000 + +/* MIDI MCUCH3 CH3A Mask */ +#define MIDI_MCUCH3_CH3A_MASK (u32)0x0000FFFF + +/* MIDI CTRL MCUCHEN3 Mask */ +#define MCUCHEN3_ENABLE (u32)0x00008000 +#define MCUCHEN3_DISABLE (u32)0xFFFF7FFF + +/* MIDI CTRL MCUCHEN2 Mask */ +#define MCUCHEN2_ENABLE (u32)0x00004000 +#define MCUCHEN2_DISABLE (u32)0xFFFFBFFF + +/* MIDI CTRL MCUCHEN1 Mask */ +#define MCUCHEN1_ENABLE (u32)0x00002000 +#define MCUCHEN1_DISABLE (u32)0xFFFFDFFF + +/* MIDI CTRL MCUCHEN0 Mask */ +#define MCUCHEN0_ENABLE (u32)0x00001000 +#define MCUCHEN0_DISABLE (u32)0xFFFFEFFF + +/* MIDI CTRL DACDS Mask */ +#define MIDI_CTRL_DACDS_MASK (u32)0x00000700 + +/* MIDI CTRL MUSICEN Mask */ +#define MUSICEN_ENABLE (u32)0x00000080 +#define MUSICEN_DISABLE (u32)0xFFFFFF7F + +/* MIDI CTRL SPIRDEN Mask */ +#define SPIRDEN_ENABLE (u32)0x00000040 +#define SPIRDEN_DISABLE (u32)0xFFFFFFBF + +/* MIDI CTRL SPIDISLOOP Mask */ +#define SPIDISLOOP_ENABLE (u32)0x00000020 +#define SPIDISLOOP_DISABLE (u32)0xFFFFFFDF + +/* MIDI CTRL CHS Mask */ +#define MIDI_CTRL_CHS_MASK (u32)0x00000007 +/** + * @} + */ + +/* Global functions ----------------------------------------------------------------------------------------*/ +/** @defgroup MIDI_Exported_Functions MIDI exported functions + * @{ + */ +/*********************************************************************************************************//** + * @brief Deinitialize the MIDI peripheral registers to their default reset values. + * @retval None + ************************************************************************************************************/ +void MIDI_DeInit(void) +{ + RSTCU_PeripReset_TypeDef RSTCUReset = {{0}}; + + RSTCUReset.Bit.MIDI = 1; + RSTCU_PeripReset(RSTCUReset, ENABLE); +} + +/*********************************************************************************************************//** + * @brief Initialize the MIDIx peripheral according to the specified parameters in the MIDI_InitStruct. + * @param MIDIx: where MIDIx is the selected MIDI from the MIDI peripherals. + * @param MIDI_InitStruct: pointer to a MIDI_InitTypeDef structure that contains the configuration + * information for the specified MIDI peripheral. + * @retval None + ***********************************************************************************************************/ +void MIDI_Init(HT_MIDI_TypeDef* MIDIx, MIDI_InitTypeDef* MIDI_InitStruct) +{ + /* Check the parameters */ + Assert_Param(IS_MIDI(MIDIx)); + Assert_Param(IS_MIDI_CTRL_DACDS(MIDI_InitStruct->MIDI_CTRL_DACDS)); + Assert_Param(IS_MIDI_CTRL_MUSICEN(MIDI_InitStruct->MIDI_CTRL_MUSICEN)); + Assert_Param(IS_MIDI_CTRL_SPIDISLOOP(MIDI_InitStruct->MIDI_CTRL_SPIDISLOOP)); + Assert_Param(IS_MIDI_CTRL_CHS(MIDI_InitStruct->MIDI_CTRL_CHS)); + Assert_Param(IS_MIDI_FREQ_BL(MIDI_InitStruct->MIDI_FREQ_BL)); + Assert_Param(IS_MIDI_FREQ_FR(MIDI_InitStruct->MIDI_FREQ_FR)); + Assert_Param(IS_MIDI_VOL_AR(MIDI_InitStruct->MIDI_VOL_AR)); + Assert_Param(IS_MIDI_VOL_ENV(MIDI_InitStruct->MIDI_VOL_ENV)); + Assert_Param(IS_MIDI_VOL_VL(MIDI_InitStruct->MIDI_VOL_VL)); + Assert_Param(IS_MIDI_VOL_VR(MIDI_InitStruct->MIDI_VOL_VR)); + Assert_Param(IS_MIDI_STADDR(MIDI_InitStruct->MIDI_STADDR)); + Assert_Param(IS_MIDI_RENUM_WBS(MIDI_InitStruct->MIDI_RENUM_WBS)); + Assert_Param(IS_MIDI_RENUM_RE(MIDI_InitStruct->MIDI_RENUM_RE)); + Assert_Param(IS_MIDI_ENDADDR(MIDI_InitStruct->MIDI_ENDADDR)); + Assert_Param(IS_MIDI_CHAN_ST(MIDI_InitStruct->MIDI_CHAN_ST)); + Assert_Param(IS_MIDI_CHAN_VM(MIDI_InitStruct->MIDI_CHAN_VM)); + Assert_Param(IS_MIDI_CHAN_FR(MIDI_InitStruct->MIDI_CHAN_FR)); + Assert_Param(IS_MIDI_CHAN_CHx(MIDI_InitStruct->MIDI_CHAN_CHx)); + + MIDIx->CTRL = ((MIDI_InitStruct->MIDI_CTRL_DACDS) << 8) | + ((MIDI_InitStruct->MIDI_CTRL_MUSICEN) << 7) | + ((MIDI_InitStruct->MIDI_CTRL_SPIDISLOOP) << 6) | + (MIDI_InitStruct->MIDI_CTRL_CHS); + + MIDIx->FREQ = ((MIDI_InitStruct->MIDI_FREQ_BL) << 12) | + (MIDI_InitStruct->MIDI_FREQ_FR); + + MIDIx->VOL = ((MIDI_InitStruct->MIDI_VOL_AR) << 31) | + ((MIDI_InitStruct->MIDI_VOL_ENV) << 29) | + ((MIDI_InitStruct->MIDI_VOL_VL) << 16) | + (MIDI_InitStruct->MIDI_VOL_VR); + + MIDIx->ST_ADDR = MIDI_InitStruct->MIDI_STADDR; + + MIDIx->RE_NUM = ((MIDI_InitStruct->MIDI_RENUM_WBS) << 16) | + (MIDI_InitStruct->MIDI_RENUM_RE); + + MIDIx->END_ADDR = MIDI_InitStruct->MIDI_ENDADDR; + + MIDIx->CHAN = ((MIDI_InitStruct->MIDI_CHAN_ST) << 10) | + ((MIDI_InitStruct->MIDI_CHAN_VM) << 9) | + ((MIDI_InitStruct->MIDI_CHAN_FR) << 8) | + (MIDI_InitStruct->MIDI_CHAN_CHx); +} + +/*********************************************************************************************************//** + * @brief Fill each MIDI_InitStruct member with its default value. + * @param MIDI_InitStruct: pointer to an MIDI_InitTypeDef structure which will be initialized. + * @retval None + ***********************************************************************************************************/ +void MIDI_StructInit(MIDI_InitTypeDef* MIDI_InitStruct) +{ + /* Initialize the MIDI_CTRL_DACDS member */ + MIDI_InitStruct->MIDI_CTRL_DACDS = 0x0; + + /* Initialize the MIDI_CTRL_MUSICEN member */ + MIDI_InitStruct->MIDI_CTRL_MUSICEN = DISABLE; + + /* Initialize the MIDI_CTRL_SPIDISLOOP member */ + MIDI_InitStruct->MIDI_CTRL_SPIDISLOOP = DISABLE; + + /* Initialize the MIDI_CTRL_CHS member */ + MIDI_InitStruct->MIDI_CTRL_CHS = CHS16; + + /* Initialize the MIDI_FREQ_BL member */ + MIDI_InitStruct->MIDI_FREQ_BL = BL0; + + /* Initialize the MIDI_FREQ_FR member */ + MIDI_InitStruct->MIDI_FREQ_FR = 0x0; + + /* Initialize the MIDI_VOL_AR member */ + MIDI_InitStruct->MIDI_VOL_AR = ENV_RELEASE; + + /* Initialize the MIDI_VOL_ENV member */ + MIDI_InitStruct->MIDI_VOL_ENV = ENV_NO; + + /* Initialize the MIDI_VOL_VL member */ + MIDI_InitStruct->MIDI_VOL_VL = 0x3FF; + + /* Initialize the MIDI_VOL_VR member */ + MIDI_InitStruct->MIDI_VOL_VR = 0x3FF; + + /* Initialize the MIDI_STADDR member */ + MIDI_InitStruct->MIDI_STADDR = 0x0; + + /* Initialize the MIDI_RENUM_WBS member */ + MIDI_InitStruct->MIDI_RENUM_WBS = WBS8; + + /* Initialize the MIDI_RENUM_RE member */ + MIDI_InitStruct->MIDI_RENUM_RE = 0x0; + + /* Initialize the MIDI_ENDADDR member */ + MIDI_InitStruct->MIDI_ENDADDR = 0x0; + + /* Initialize the MIDI_CHAN_ST member */ + MIDI_InitStruct->MIDI_CHAN_ST = DISABLE; + + /* Initialize the MIDI_CHAN_VM member */ + MIDI_InitStruct->MIDI_CHAN_VM = DISABLE; + + /* Initialize the MIDI_CHAN_FR member */ + MIDI_InitStruct->MIDI_CHAN_FR = DISABLE; + + /* Initialize the MIDI_CHAN_CHx member */ + MIDI_InitStruct->MIDI_CHAN_CHx = MIDI_CHx0; +} + +/*********************************************************************************************************//** + * @brief Enable or Disable the specified MIDI interrupt. + * @param MIDIx: where MIDIx is the selected MIDI from the MIDI peripherals. + * @param MIDI_Int: specify if the MIDI interrupt source to be enabled or disabled. + * This parameter can be any combination of the following values: + * @arg MIDIO_DMAEN : MIDIO DMAEN + * @arg MIDII_DMAEN : MIDII DMAEN + * @arg MIDI_INTEN : MIDI INTEN + * @param NewState: new state of the MIDI interrupts. + * This parameter can be: ENABLE or DISABLE. + * @retval None + ***********************************************************************************************************/ +void MIDI_IntConfig(HT_MIDI_TypeDef* MIDIx, u32 MIDI_Int, ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_MIDI(MIDIx)); + Assert_Param(IS_MIDI_INT(MIDI_Int)); + Assert_Param(IS_CONTROL_STATUS(NewState)); + + if (NewState != DISABLE) + { + MIDIx->IER |= MIDI_Int; + } + else + { + MIDIx->IER &= (u32)~MIDI_Int; + } +} + +/*********************************************************************************************************//** + * @brief Check whether the specified MIDI flag has been set or not. + * @param MIDIx: where MIDIx is the selected MIDI from the MIDI peripherals. + * @param MIDI_Flag: specify the flag that is to be check. + * This parameter can be one of the following values: + * @arg MIDI_INTF : MIDI int flag + * @retval The new state of MIDI_Flag (SET or RESET). + ***********************************************************************************************************/ +FlagStatus MIDI_GetFlagStatus(HT_MIDI_TypeDef* MIDIx, u32 MIDI_Flag) +{ + FlagStatus bitstatus = RESET; + u32 statusreg = 0; + + /* Check the parameters */ + Assert_Param(IS_MIDI(MIDIx)); + Assert_Param(IS_MIDI_FLAG(MIDI_Flag)); + + statusreg = MIDIx->SR; + + if ((statusreg & MIDI_Flag) != (u32)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + return bitstatus; +} + +/*********************************************************************************************************//** + * @brief Clear the specified MIDI flag. + * @param MIDIx: where MIDIx is the selected MIDI from the MIDI peripherals. + * @param MIDI_Flag: specify the flag that is to be cleared. + * This parameter can be one of the following values: + * @arg MIDI_INTF : MIDI INTF + * @retval None + ***********************************************************************************************************/ +void MIDI_ClearFlag(HT_MIDI_TypeDef* MIDIx, u32 MIDI_Flag) +{ + /* Check the parameters */ + Assert_Param(IS_MIDI(MIDIx)); + Assert_Param(IS_MIDI_FLAG_CLEAR(MIDI_Flag)); + + MIDIx->SR = MIDI_Flag; +} + +/*********************************************************************************************************//** + * @brief Configure the Channel for the selected MIDI. + * @param MIDIx: where MIDIx is the selected MIDI from the MIDI peripherals. + * @param MCUCHEN3: this parameter can be ENABLE or DISABLE. + * @param MCUCHEN2: this parameter can be ENABLE or DISABLE. + * @param MCUCHEN1: this parameter can be ENABLE or DISABLE. + * @param MCUCHEN0: this parameter can be ENABLE or DISABLE. + * @param DACDS: specify the clipping and distorting volume of the MIDI. + * @param MUSICEN: this parameter can be ENABLE or DISABLE. + * @param SPIRDEN: this parameter can be ENABLE or DISABLE. + * @param SPIDISLOOP: this parameter can be ENABLE or DISABLE. + * @param CHS: specify channel selection of the MIDI. + * @retval None + ***********************************************************************************************************/ +void MIDI_CTRL(HT_MIDI_TypeDef* MIDIx, + MIDI_CTRL_MCUCHEN3_Enum MCUCHEN3, MIDI_CTRL_MCUCHEN2_Enum MCUCHEN2, + MIDI_CTRL_MCUCHEN1_Enum MCUCHEN1, MIDI_CTRL_MCUCHEN0_Enum MCUCHEN0, + u8 DACDS, + MIDI_CTRL_MUSICEN_Enum MUSICEN, + MIDI_CTRL_SPIRDEN_Enum SPIRDEN, MIDI_CTRL_SPIDISLOOP_Enum SPIDISLOOP, + MIDI_CTRL_CHS_Enum CHS) +{ + /* Check the parameters */ + Assert_Param(IS_MIDI(MIDIx)); + Assert_Param(IS_MIDI_CTRL_MCUCHEN3(MCUCHEN3)); + Assert_Param(IS_MIDI_CTRL_MCUCHEN2(MCUCHEN2)); + Assert_Param(IS_MIDI_CTRL_MCUCHEN1(MCUCHEN1)); + Assert_Param(IS_MIDI_CTRL_MCUCHEN0(MCUCHEN0)); + Assert_Param(IS_MIDI_CTRL_DACDS(DACDS)); + Assert_Param(IS_MIDI_CTRL_MUSICEN(MUSICEN)); + Assert_Param(IS_MIDI_CTRL_SPIRDEN(SPIRDEN)); + Assert_Param(IS_MIDI_CTRL_SPIDISLOOP(SPIDISLOOP)); + Assert_Param(IS_MIDI_CTRL_CHS(CHS)); + + MIDIx->CTRL = (MCUCHEN3 << 15) | (MCUCHEN2 << 14) | (MCUCHEN1 << 13) | (MCUCHEN0 << 12) | + (DACDS << 8) | + (MUSICEN << 7) | + (SPIRDEN << 6) | (SPIDISLOOP << 5) | + CHS; +} + +/*********************************************************************************************************//** + * @brief Configure the FREQ for the selected MIDI. + * @param MIDIx: where MIDIx is the selected MIDI from the MIDI peripherals. + * @param BL: specify octave of the MIDI. + * @param FR: specify pitch of the MIDI. + * @retval None + ***********************************************************************************************************/ +void MIDI_FREQ(HT_MIDI_TypeDef* MIDIx, MIDI_FREQ_BL_Enum BL, u16 FR) +{ + /* Check the parameters */ + Assert_Param(IS_MIDI(MIDIx)); + Assert_Param(IS_MIDI_FREQ_BL(BL)); + Assert_Param(IS_MIDI_FREQ_FR(FR)); + + MIDIx->FREQ = (BL << 12) | FR; +} + +/*********************************************************************************************************//** + * @brief Configure the VOL for the selected MIDI. + * @param MIDIx: where MIDIx is the selected MIDI from the MIDI peripherals. + * @param A_R: specify attack or release of the MIDI. + * @param ENV: specify envelope of the MIDI. + * @param VL: specify left channel of the MIDI. + * @param VR: specify right channel of the MIDI. + * @retval None + ***********************************************************************************************************/ +void MIDI_VOL(HT_MIDI_TypeDef* MIDIx, MIDI_VOL_AR_Enum A_R, MIDI_VOL_ENV_Enum ENV, u16 VL, u16 VR) +{ + /* Check the parameters */ + Assert_Param(IS_MIDI(MIDIx)); + Assert_Param(IS_MIDI_VOL_AR(A_R)); + Assert_Param(IS_MIDI_VOL_ENV(ENV)); + Assert_Param(IS_MIDI_VOL_VL(VL)); + Assert_Param(IS_MIDI_VOL_VR(VR)); + + MIDIx->VOL = (A_R << 31) | (ENV << 29) | (VL << 16) | VR; +} + +/*********************************************************************************************************//** + * @brief Configure the Start Address for the selected MIDI. + * @param MIDIx: where MIDIx is the selected MIDI from the MIDI peripherals. + * @param ST_ADDR: specify start address of the MIDI. + * @retval None + ***********************************************************************************************************/ +void MIDI_STADDR(HT_MIDI_TypeDef* MIDIx, u32 ST_ADDR) +{ + /* Check the parameters */ + Assert_Param(IS_MIDI(MIDIx)); + Assert_Param(IS_MIDI_STADDR(ST_ADDR)); + + MIDIx->ST_ADDR = ST_ADDR; +} + +/*********************************************************************************************************//** + * @brief Configure the RENUM for the selected MIDI. + * @param MIDIx: where MIDIx is the selected MIDI from the MIDI peripherals. + * @param WBS: specify waveform of the MIDI. + * @param RE: specify repeated code of the MIDI. + * @retval None + ***********************************************************************************************************/ +void MIDI_RENUM(HT_MIDI_TypeDef* MIDIx, MIDI_RENUM_WBS_Enum WBS, u16 RE) +{ + /* Check the parameters */ + Assert_Param(IS_MIDI(MIDIx)); + Assert_Param(IS_MIDI_RENUM_WBS(WBS)); + Assert_Param(IS_MIDI_RENUM_RE(RE)); + + MIDIx->RE_NUM = (WBS << 16) | RE; +} + +/*********************************************************************************************************//** + * @brief Configure the End Address for the selected MIDI. + * @param MIDIx: where MIDIx is the selected MIDI from the MIDI peripherals. + * @param END_ADDR: specify end address of the MIDI. + * @retval None + ***********************************************************************************************************/ +void MIDI_ENDADDR(HT_MIDI_TypeDef* MIDIx, u32 END_ADDR) +{ + /* Check the parameters */ + Assert_Param(IS_MIDI(MIDIx)); + Assert_Param(IS_MIDI_ENDADDR(END_ADDR)); + + MIDIx->END_ADDR = END_ADDR; +} + +/*********************************************************************************************************//** + * @brief Configure the Channel for the selected MIDI. + * @param MIDIx: where MIDIx is the selected MIDI from the MIDI peripherals. + * @param TRIG_ST: this parameter can be ENABLE or DISABLE. + * @param TRIG_VM: this parameter can be ENABLE or DISABLE. + * @param TRIG_FR: this parameter can be ENABLE or DISABLE. + * @param CHx: specify selected channel of the MIDI. + * @retval None + ***********************************************************************************************************/ +void MIDI_CHAN(HT_MIDI_TypeDef* MIDIx, + MIDI_CHAN_ST_Enum TRIG_ST, MIDI_CHAN_VM_Enum TRIG_VM, MIDI_CHAN_FR_Enum TRIG_FR, + u8 CHx) +{ + /* Check the parameters */ + Assert_Param(IS_MIDI(MIDIx)); + Assert_Param(IS_MIDI_CHAN_ST(TRIG_ST)); + Assert_Param(IS_MIDI_CHAN_VM(TRIG_VM)); + Assert_Param(IS_MIDI_CHAN_FR(TRIG_FR)); + Assert_Param(IS_MIDI_CHAN_CHx(CHx)); + + MIDIx->CHAN = (TRIG_ST << 10) | (TRIG_VM << 9) | (TRIG_FR << 8) | CHx; +} + +/*********************************************************************************************************//** + * @brief Configure the MCU CH0 DATA for the selected MIDI. + * @param MIDIx: where MIDIx is the selected MIDI from the MIDI peripherals. + * @param CH0B: specify DATA[31:16] of MCU CH0 of the MIDI. + * @param CH0A: specify DATA[15:0] of MCU CH0 of the MIDI. + * @retval None + ***********************************************************************************************************/ +void MIDI_MCUCH0(HT_MIDI_TypeDef* MIDIx, u16 CH0B, u16 CH0A) +{ + /* Check the parameters */ + Assert_Param(IS_MIDI(MIDIx)); + Assert_Param(IS_MIDI_MCUCHx11_BH(CH0B)); + Assert_Param(IS_MIDI_MCUCHx11_BL(CH0A)); + + MIDIx->MCU_CH0 = (CH0B << 16) | CH0A; +} + +/*********************************************************************************************************//** + * @brief Configure the MCU CH1 DATA for the selected MIDI. + * @param MIDIx: where MIDIx is the selected MIDI from the MIDI peripherals. + * @param CH1B: specify DATA[31:16] of MCU CH1 of the MIDI. + * @param CH1A: specify DATA[15:0] of MCU CH1 of the MIDI. + * @retval None + ***********************************************************************************************************/ +void MIDI_MCUCH1(HT_MIDI_TypeDef* MIDIx, u16 CH1B, u16 CH1A) +{ + /* Check the parameters */ + Assert_Param(IS_MIDI(MIDIx)); + Assert_Param(IS_MIDI_MCUCHx12_CH(CH1B)); + Assert_Param(IS_MIDI_MCUCHx12_CL(CH1A)); + + MIDIx->MCU_CH1 = (CH1B << 16) | CH1A; +} + +/*********************************************************************************************************//** + * @brief Configure the MCU CH2 DATA for the selected MIDI. + * @param MIDIx: where MIDIx is the selected MIDI from the MIDI peripherals. + * @param CH2B: specify DATA[31:16] of MCU CH2 of the MIDI. + * @param CH2A: specify DATA[15:0] of MCU CH2 of the MIDI. + * @retval None + ***********************************************************************************************************/ +void MIDI_MCUCH2(HT_MIDI_TypeDef* MIDIx, u16 CH2B, u16 CH2A) +{ + /* Check the parameters */ + Assert_Param(IS_MIDI(MIDIx)); + Assert_Param(IS_MIDI_MCUCHx13_DH(CH2B)); + Assert_Param(IS_MIDI_MCUCHx13_DL(CH2A)); + + MIDIx->MCU_CH2 = (CH2B << 16) | CH2A; +} + +/*********************************************************************************************************//** + * @brief Configure the MCU CH3 DATA for the selected MIDI. + * @param MIDIx: where MIDIx is the selected MIDI from the MIDI peripherals. + * @param CH3B: specify DATA[31:16] of MCU CH3 of the MIDI. + * @param CH3A: specify DATA[15:0] of MCU CH3 of the MIDI. + * @retval None + ***********************************************************************************************************/ +void MIDI_MCUCH3(HT_MIDI_TypeDef* MIDIx, u16 CH3B, u16 CH3A) +{ + /* Check the parameters */ + Assert_Param(IS_MIDI(MIDIx)); + Assert_Param(IS_MIDI_MCUCHx14_EH(CH3B)); + Assert_Param(IS_MIDI_MCUCHx14_EL(CH3A)); + + MIDIx->MCU_CH3 = (CH3B << 16) | CH3A; +} + +/*********************************************************************************************************//** + * @brief Configure the FREQ BL for the selected MIDI. + * @param MIDIx: where MIDIx is the selected MIDI from the MIDI peripherals. + * @param BL: specify octave of the MIDI. + * @retval None + ***********************************************************************************************************/ +void MIDI_FREQ_BL(HT_MIDI_TypeDef* MIDIx, MIDI_FREQ_BL_Enum BL) +{ + /* Check the parameters */ + Assert_Param(IS_MIDI(MIDIx)); + Assert_Param(IS_MIDI_FREQ_BL(BL)); + + /* Clear BL[3:0] in FREQ */ + MIDIx->FREQ &= (u32)~MIDI_FREQ_BL_MASK; + + /* Set new BL[3:0] in FREQ */ + MIDIx->FREQ |= (BL << 12); +} + +/*********************************************************************************************************//** + * @brief Configure the FREQ FR for the selected MIDI. + * @param MIDIx: where MIDIx is the selected MIDI from the MIDI peripherals. + * @param FR: specify pitch of the MIDI. + * @retval None + ***********************************************************************************************************/ +void MIDI_FREQ_FR(HT_MIDI_TypeDef* MIDIx, u16 FR) +{ + /* Check the parameters */ + Assert_Param(IS_MIDI(MIDIx)); + Assert_Param(IS_MIDI_FREQ_FR(FR)); + + /* Clear FR[11:0] in FREQ */ + MIDIx->FREQ &= (u32)~MIDI_FREQ_FR_MASK; + + /* Set new FR[11:0] in FREQ */ + MIDIx->FREQ |= FR; +} + +/*********************************************************************************************************//** + * @brief Configure the VOL AR for the selected MIDI. + * @param MIDIx: where MIDIx is the selected MIDI from the MIDI peripherals. + * @param A_R: specify attack or release of the MIDI. + * @retval None + ***********************************************************************************************************/ +void MIDI_VOL_AR(HT_MIDI_TypeDef* MIDIx, MIDI_VOL_AR_Enum A_R) +{ + /* Check the parameters */ + Assert_Param(IS_MIDI(MIDIx)); + Assert_Param(IS_MIDI_VOL_AR(A_R)); + + /* Clear A_R in VOL */ + MIDIx->VOL &= (u32)~MIDI_VOL_AR_MASK; + + /* Set new A_R in VOL */ + MIDIx->VOL |= (A_R << 31); +} + +/*********************************************************************************************************//** + * @brief Configure the VOL ENV for the selected MIDI. + * @param MIDIx: where MIDIx is the selected MIDI from the MIDI peripherals. + * @param ENV: specify envelope of the MIDI. + * @retval None + ***********************************************************************************************************/ +void MIDI_VOL_ENV(HT_MIDI_TypeDef* MIDIx, MIDI_VOL_ENV_Enum ENV) +{ + /* Check the parameters */ + Assert_Param(IS_MIDI(MIDIx)); + Assert_Param(IS_MIDI_VOL_ENV(ENV)); + + /* Clear ENV[1:0] in VOL */ + MIDIx->VOL &= (u32)~MIDI_VOL_ENV_MASK; + + /* Set new ENV[1:0] in VOL */ + MIDIx->VOL |= (ENV << 29); +} + +/*********************************************************************************************************//** + * @brief Configure the VOL VL for the selected MIDI. + * @param MIDIx: where MIDIx is the selected MIDI from the MIDI peripherals. + * @param VL: specify left channel of the MIDI. + * @retval None + ***********************************************************************************************************/ +void MIDI_VOL_VL(HT_MIDI_TypeDef* MIDIx, u16 VL) +{ + /* Check the parameters */ + Assert_Param(IS_MIDI(MIDIx)); + Assert_Param(IS_MIDI_VOL_VL(VL)); + + /* Clear VL[9:0] in VOL */ + MIDIx->VOL &= (u32)~MIDI_VOL_VL_MASK; + + /* Set new VL[9:0] in VOL */ + MIDIx->VOL |= (VL << 16); +} + +/*********************************************************************************************************//** + * @brief Configure the VOL VR for the selected MIDI. + * @param MIDIx: where MIDIx is the selected MIDI from the MIDI peripherals. + * @param VR: specify right channel of the MIDI. + * @retval None + ***********************************************************************************************************/ +void MIDI_VOL_VR(HT_MIDI_TypeDef* MIDIx, u16 VR) +{ + /* Check the parameters */ + Assert_Param(IS_MIDI(MIDIx)); + Assert_Param(IS_MIDI_VOL_VR(VR)); + + /* Clear VR[9:0] in VOL */ + MIDIx->VOL &= (u32)~MIDI_VOL_VR_MASK; + + /* Set new VR[9:0] in VOL */ + MIDIx->VOL |= VR; +} + +/*********************************************************************************************************//** + * @brief Configure the RENUM WBS for the selected MIDI. + * @param MIDIx: where MIDIx is the selected MIDI from the MIDI peripherals. + * @param WBS: specify waveform of the MIDI. + * @retval None + ***********************************************************************************************************/ +void MIDI_RENUM_WBS(HT_MIDI_TypeDef* MIDIx, MIDI_RENUM_WBS_Enum WBS) +{ + /* Check the parameters */ + Assert_Param(IS_MIDI(MIDIx)); + Assert_Param(IS_MIDI_RENUM_WBS(WBS)); + + /* Clear WBS[1:0] in RENUM */ + MIDIx->RE_NUM &= (u32)~MIDI_RENUM_WBS_MASK; + + /* Set new WBS[1:0] in RENUM */ + MIDIx->RE_NUM |= (WBS << 16); +} + +/*********************************************************************************************************//** + * @brief Configure the RENUM RE for the selected MIDI. + * @param MIDIx: where MIDIx is the selected MIDI from the MIDI peripherals. + * @param RE: specify repeated code of the MIDI. + * @retval None + ***********************************************************************************************************/ +void MIDI_RENUM_RE(HT_MIDI_TypeDef* MIDIx, u16 RE) +{ + /* Check the parameters */ + Assert_Param(IS_MIDI(MIDIx)); + Assert_Param(IS_MIDI_RENUM_RE(RE)); + + /* Clear RE[14:0] in RENUM */ + MIDIx->RE_NUM &= (u32)~MIDI_RENUM_RE_MASK; + + /* Set new RE[14:0] in RENUM */ + MIDIx->RE_NUM |= RE; +} + +/*********************************************************************************************************//** + * @brief Enable or Disable ST ADDR for the specified MIDI peripheral. + * @param MIDIx: where MIDIx is the selected MIDI from the MIDI peripherals. + * @param NewState: new state of the MIDIx peripheral. + * This parameter can be: ENABLE or DISABLE. + * @retval None + ***********************************************************************************************************/ +void MIDI_CHAN_STCmd(HT_MIDI_TypeDef* MIDIx, ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_MIDI(MIDIx)); + Assert_Param(IS_CONTROL_STATUS(NewState)); + + if (NewState != DISABLE) + { + MIDIx->CHAN |= TRIG_ST_ENABLE; + } + else + { + MIDIx->CHAN &= (TRIG_ST_DISABLE); + } +} + +/*********************************************************************************************************//** + * @brief Enable or Disable VM for the specified MIDI peripheral. + * @param MIDIx: where MIDIx is the selected MIDI from the MIDI peripherals. + * @param NewState: new state of the MIDIx peripheral. + * This parameter can be: ENABLE or DISABLE. + * @retval None + ***********************************************************************************************************/ +void MIDI_CHAN_VMCmd(HT_MIDI_TypeDef* MIDIx, ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_MIDI(MIDIx)); + Assert_Param(IS_CONTROL_STATUS(NewState)); + + if (NewState != DISABLE) + { + MIDIx->CHAN |= TRIG_VM_ENABLE; + } + else + { + MIDIx->CHAN &= (TRIG_VM_DISABLE); + } +} + +/*********************************************************************************************************//** + * @brief Enable or Disable FR for the specified MIDI peripheral. + * @param MIDIx: where MIDIx is the selected MIDI from the MIDI peripherals. + * @param NewState: new state of the MIDIx peripheral. + * This parameter can be: ENABLE or DISABLE. + * @retval None + ***********************************************************************************************************/ +void MIDI_CHAN_FRCmd(HT_MIDI_TypeDef* MIDIx, ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_MIDI(MIDIx)); + Assert_Param(IS_CONTROL_STATUS(NewState)); + + if (NewState != DISABLE) + { + MIDIx->CHAN |= TRIG_FR_ENABLE; + } + else + { + MIDIx->CHAN &= (TRIG_FR_DISABLE); + } +} + +/*********************************************************************************************************//** + * @brief Configure the Selected Channel for the selected MIDI. + * @param MIDIx: where MIDIx is the selected MIDI from the MIDI peripherals. + * @param CHx: specify selected channel of the MIDI. + * @retval None + ***********************************************************************************************************/ +void MIDI_CHAN_CHx(HT_MIDI_TypeDef* MIDIx, u8 CHx) +{ + /* Check the parameters */ + Assert_Param(IS_MIDI(MIDIx)); + Assert_Param(IS_MIDI_CHAN_CHx(CHx)); + + /* Clear CHx[4:0] in CHAN */ + MIDIx->CHAN &= (u32)~MIDI_CHAN_CHx_MASK; + + /* Set new CHx[4:0] in CHAN */ + MIDIx->CHAN |= CHx; +} + +/*********************************************************************************************************//** + * @brief Configure the CH0B of MCU CH0 DATA for the selected MIDI. + * @param MIDIx: where MIDIx is the selected MIDI from the MIDI peripherals. + * @param CH0B: specify DATA[31:16] of MCU CH0 of the MIDI. + * @retval None + ***********************************************************************************************************/ +void MIDI_MCUCH0_CH0B(HT_MIDI_TypeDef* MIDIx, u16 CH0B) +{ + /* Check the parameters */ + Assert_Param(IS_MIDI(MIDIx)); + Assert_Param(IS_MIDI_MCUCHx11_BH(CH0B)); + + /* Clear CH0B[16:0] in MCUCH0 */ + MIDIx->MCU_CH0 &= (u32)~MIDI_MCUCH0_CH0B_MASK; + + /* Set new CH0B[16:0] in MCUCH0 */ + MIDIx->MCU_CH0 |= (CH0B << 16); +} + +/*********************************************************************************************************//** + * @brief Configure the CH0A of MCU CH0 DATA for the selected MIDI. + * @param MIDIx: where MIDIx is the selected MIDI from the MIDI peripherals. + * @param CH0A: specify DATA[15:0] of MCU CH0 of the MIDI. + * @retval None + ***********************************************************************************************************/ +void MIDI_MCUCH0_CH0A(HT_MIDI_TypeDef* MIDIx, u16 CH0A) +{ + /* Check the parameters */ + Assert_Param(IS_MIDI(MIDIx)); + Assert_Param(IS_MIDI_MCUCHx11_BL(CH0A)); + + /* Clear CH0B[16:0] in MCUCH0 */ + MIDIx->MCU_CH0 &= (u32)~MIDI_MCUCH0_CH0A_MASK; + + /* Set new CH0B[16:0] in MCUCH0 */ + MIDIx->MCU_CH0 |= CH0A; +} + +/*********************************************************************************************************//** + * @brief Configure the CH1B of MCU CH1 DATA for the selected MIDI. + * @param MIDIx: where MIDIx is the selected MIDI from the MIDI peripherals. + * @param CH1B: specify DATA[31:16] of MCU CH1 of the MIDI. + * @retval None + ***********************************************************************************************************/ +void MIDI_MCUCH1_CH1B(HT_MIDI_TypeDef* MIDIx, u16 CH1B) +{ + /* Check the parameters */ + Assert_Param(IS_MIDI(MIDIx)); + Assert_Param(IS_MIDI_MCUCHx12_CH(CH1B)); + + /* Clear CH0B[16:0] in MCUCH0 */ + MIDIx->MCU_CH1 &= (u32)~MIDI_MCUCH1_CH1B_MASK; + + /* Set new CH1B[16:0] in MCUCH1 */ + MIDIx->MCU_CH1 |= (CH1B << 16); +} + +/*********************************************************************************************************//** + * @brief Configure the CH1A of MCU CH1 DATA for the selected MIDI. + * @param MIDIx: where MIDIx is the selected MIDI from the MIDI peripherals. + * @param CH1A: specify DATA[15:0] of MCU CH1 of the MIDI. + * @retval None + ***********************************************************************************************************/ +void MIDI_MCUCH1_CH1A(HT_MIDI_TypeDef* MIDIx, u16 CH1A) +{ + /* Check the parameters */ + Assert_Param(IS_MIDI(MIDIx)); + Assert_Param(IS_MIDI_MCUCHx12_CL(CH1A)); + + /* Clear CH1A[16:0] in MCUCH1 */ + MIDIx->MCU_CH1 &= (u32)~MIDI_MCUCH1_CH1A_MASK; + + /* Set new CH1A[16:0] in MCUCH1 */ + MIDIx->MCU_CH1 |= CH1A; +} + +/*********************************************************************************************************//** + * @brief Configure the CH2B of MCU CH2 DATA for the selected MIDI. + * @param MIDIx: where MIDIx is the selected MIDI from the MIDI peripherals. + * @param CH2B: specify DATA[31:16] of MCU CH2 of the MIDI. + * @retval None + ***********************************************************************************************************/ +void MIDI_MCUCH2_CH2B(HT_MIDI_TypeDef* MIDIx, u16 CH2B) +{ + /* Check the parameters */ + Assert_Param(IS_MIDI(MIDIx)); + Assert_Param(IS_MIDI_MCUCHx13_DH(CH2B)); + + /* Clear CH2B[16:0] in MCUCH2 */ + MIDIx->MCU_CH2 &= (u32)~MIDI_MCUCH2_CH2B_MASK; + + /* Set new CH2B[16:0] in MCUCH2 */ + MIDIx->MCU_CH2 |= (CH2B << 16); +} + +/*********************************************************************************************************//** + * @brief Configure the CH2A of MCU CH2 DATA for the selected MIDI. + * @param MIDIx: where MIDIx is the selected MIDI from the MIDI peripherals. + * @param CH2A: specify DATA[15:0] of MCU CH2 of the MIDI. + * @retval None + ***********************************************************************************************************/ +void MIDI_MCUCH2_CH2A(HT_MIDI_TypeDef* MIDIx, u16 CH2A) +{ + /* Check the parameters */ + Assert_Param(IS_MIDI(MIDIx)); + Assert_Param(IS_MIDI_MCUCHx13_DL(CH2A)); + + /* Clear CH2A[16:0] in MCUCH2 */ + MIDIx->MCU_CH2 &= (u32)~MIDI_MCUCH2_CH2A_MASK; + + /* Set new CH2A[16:0] in MCUCH2 */ + MIDIx->MCU_CH2 |= CH2A; +} + +/*********************************************************************************************************//** + * @brief Configure the CH3B of MCU CH3 DATA for the selected MIDI. + * @param MIDIx: where MIDIx is the selected MIDI from the MIDI peripherals. + * @param CH3B: specify DATA[31:16] of MCU CH3 of the MIDI. + * @retval None + ***********************************************************************************************************/ +void MIDI_MCUCH3_CH3B(HT_MIDI_TypeDef* MIDIx, u16 CH3B) +{ + /* Check the parameters */ + Assert_Param(IS_MIDI(MIDIx)); + Assert_Param(IS_MIDI_MCUCHx14_EH(CH3B)); + + /* Clear CH3B[16:0] in MCUCH3 */ + MIDIx->MCU_CH3 &= (u32)~MIDI_MCUCH3_CH3B_MASK; + + /* Set new CH3B[16:0] in MCUCH3 */ + MIDIx->MCU_CH3 |= (CH3B << 16); +} + +/*********************************************************************************************************//** + * @brief Configure the CH3A of MCU CH3 DATA for the selected MIDI. + * @param MIDIx: where MIDIx is the selected MIDI from the MIDI peripherals. + * @param CH3A: specify DATA[15:0] of MCU CH3 of the MIDI. + * @retval None + ***********************************************************************************************************/ +void MIDI_MCUCH3_CH3A(HT_MIDI_TypeDef* MIDIx, u16 CH3A) +{ + /* Check the parameters */ + Assert_Param(IS_MIDI(MIDIx)); + Assert_Param(IS_MIDI_MCUCHx14_EL(CH3A)); + + /* Clear CH3A[16:0] in MCUCH3 */ + MIDIx->MCU_CH3 &= (u32)~MIDI_MCUCH3_CH3A_MASK; + + /* Set new CH3A[16:0] in MCUCH3 */ + MIDIx->MCU_CH3 |= CH3A; +} + +/*********************************************************************************************************//** + * @brief Enable or Disable MCU CHEN3 for the specified MIDI peripheral. + * @param MIDIx: where MIDIx is the selected MIDI from the MIDI peripherals. + * @param NewState: new state of the MIDIx peripheral. + * This parameter can be: ENABLE or DISABLE. + * @retval None + ***********************************************************************************************************/ +void MIDI_CTRL_MCUCHEN3(HT_MIDI_TypeDef* MIDIx, ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_MIDI(MIDIx)); + Assert_Param(IS_CONTROL_STATUS(NewState)); + + if (NewState != DISABLE) + { + MIDIx->CTRL |= MCUCHEN3_ENABLE; + } + else + { + MIDIx->CTRL &= MCUCHEN3_DISABLE; + } +} + +/*********************************************************************************************************//** + * @brief Enable or Disable MCU CHEN2 for the specified MIDI peripheral. + * @param MIDIx: where MIDIx is the selected MIDI from the MIDI peripherals. + * @param NewState: new state of the MIDIx peripheral. + * This parameter can be: ENABLE or DISABLE. + * @retval None + ***********************************************************************************************************/ +void MIDI_CTRL_MCUCHEN2(HT_MIDI_TypeDef* MIDIx, ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_MIDI(MIDIx)); + Assert_Param(IS_CONTROL_STATUS(NewState)); + + if (NewState != DISABLE) + { + MIDIx->CTRL |= MCUCHEN2_ENABLE; + } + else + { + MIDIx->CTRL &= MCUCHEN2_DISABLE; + } +} + +/*********************************************************************************************************//** + * @brief Enable or Disable MCU CHEN1 for the specified MIDI peripheral. + * @param MIDIx: where MIDIx is the selected MIDI from the MIDI peripherals. + * @param NewState: new state of the MIDIx peripheral. + * This parameter can be: ENABLE or DISABLE. + * @retval None + ***********************************************************************************************************/ +void MIDI_CTRL_MCUCHEN1(HT_MIDI_TypeDef* MIDIx, ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_MIDI(MIDIx)); + Assert_Param(IS_CONTROL_STATUS(NewState)); + + if (NewState != DISABLE) + { + MIDIx->CTRL |= MCUCHEN1_ENABLE; + } + else + { + MIDIx->CTRL &= MCUCHEN1_DISABLE; + } +} + +/*********************************************************************************************************//** + * @brief Enable or Disable MCU CHEN0 for the specified MIDI peripheral. + * @param MIDIx: where MIDIx is the selected MIDI from the MIDI peripherals. + * @param NewState: new state of the MIDIx peripheral. + * This parameter can be: ENABLE or DISABLE. + * @retval None + ***********************************************************************************************************/ +void MIDI_CTRL_MCUCHEN0(HT_MIDI_TypeDef* MIDIx, ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_MIDI(MIDIx)); + Assert_Param(IS_CONTROL_STATUS(NewState)); + + if (NewState != DISABLE) + { + MIDIx->CTRL |= MCUCHEN0_ENABLE; + } + else + { + MIDIx->CTRL &= MCUCHEN0_DISABLE; + } +} + + +/*********************************************************************************************************//** + * @brief Configure the DACDS for the selected MIDI. + * @param MIDIx: where MIDIx is the selected MIDI from the MIDI peripherals. + * @param DACDS: specify the clipping and distorting volume of the MIDI. + * @retval None + ***********************************************************************************************************/ +void MIDI_CTRL_DACDS(HT_MIDI_TypeDef* MIDIx, u8 DACDS) +{ + /* Check the parameters */ + Assert_Param(IS_MIDI(MIDIx)); + Assert_Param(IS_MIDI_CTRL_DACDS(DACDS)); + + /* Clear DACDS[2:0] in CTRL */ + MIDIx->CTRL &= (u32)~MIDI_CTRL_DACDS_MASK; + + /* Set new DACDS[2:0] in CTRL */ + MIDIx->CTRL |= (DACDS << 8); +} + +/*********************************************************************************************************//** + * @brief Enable or Disable MUSIC Engine for the specified MIDI peripheral. + * @param MIDIx: where MIDIx is the selected MIDI from the MIDI peripherals. + * @param NewState: new state of the MIDIx peripheral. + * This parameter can be: ENABLE or DISABLE. + * @retval None + ***********************************************************************************************************/ +void MIDI_CTRL_MUSICENCmd(HT_MIDI_TypeDef* MIDIx, ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_MIDI(MIDIx)); + Assert_Param(IS_CONTROL_STATUS(NewState)); + + if (NewState != DISABLE) + { + MIDIx->CTRL |= MUSICEN_ENABLE; + } + else + { + MIDIx->CTRL &= MUSICEN_DISABLE; + } +} + +/*********************************************************************************************************//** + * @brief Enable or Disable SPI RDEN for the specified MIDI peripheral. + * @param MIDIx: where MIDIx is the selected MIDI from the MIDI peripherals. + * @param NewState: new state of the MIDIx peripheral. + * This parameter can be: ENABLE or DISABLE. + * @retval None + ***********************************************************************************************************/ +void MIDI_CTRL_SPIRDENCmd(HT_MIDI_TypeDef* MIDIx, ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_MIDI(MIDIx)); + Assert_Param(IS_CONTROL_STATUS(NewState)); + + if (NewState != DISABLE) + { + MIDIx->CTRL |= SPIRDEN_ENABLE; + } + else + { + MIDIx->CTRL &= SPIRDEN_DISABLE; + } +} + +/*********************************************************************************************************//** + * @brief Enable or Disable SPI DISLOOP for the specified MIDI peripheral. + * @param MIDIx: where MIDIx is the selected MIDI from the MIDI peripherals. + * @param NewState: new state of the MIDIx peripheral. + * This parameter can be: ENABLE or DISABLE. + * @retval None + ***********************************************************************************************************/ +void MIDI_CTRL_SPIDISLOOPCmd(HT_MIDI_TypeDef* MIDIx, ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_MIDI(MIDIx)); + Assert_Param(IS_CONTROL_STATUS(NewState)); + + if (NewState != DISABLE) + { + MIDIx->CTRL |= SPIDISLOOP_ENABLE; + } + else + { + MIDIx->CTRL &= SPIDISLOOP_DISABLE; + } +} + +/*********************************************************************************************************//** + * @brief Configure the Channel Selection for the selected MIDI. + * @param MIDIx: where MIDIx is the selected MIDI from the MIDI peripherals. + * @param CHS: specify channel selection of the MIDI. + * @retval None + ***********************************************************************************************************/ +void MIDI_CTRL_CHS(HT_MIDI_TypeDef* MIDIx, u8 CHS) +{ + /* Check the parameters */ + Assert_Param(IS_MIDI(MIDIx)); + Assert_Param(IS_MIDI_CTRL_CHS(CHS)); + + /* Clear CHS[2:0] in CTRL */ + MIDIx->CTRL &= (u32)~MIDI_CTRL_CHS_MASK; + + /* Set new CHS[2:0] in CTRL */ + MIDIx->CTRL |= CHS; +} + +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/ht32f5xxxx_pdma.c b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/ht32f5xxxx_pdma.c new file mode 100644 index 0000000000..4d7929e5ad --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/ht32f5xxxx_pdma.c @@ -0,0 +1,312 @@ +/*********************************************************************************************************//** + * @file ht32f5xxxx_pdma.c + * @version $Rev:: 6479 $ + * @date $Date:: 2022-11-23 #$ + * @brief This file provides all the PDMA firmware functions. + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ + +/* Includes ------------------------------------------------------------------------------------------------*/ +#include "ht32f5xxxx_pdma.h" + +/** @addtogroup HT32F5xxxx_Peripheral_Driver HT32F5xxxx Peripheral Driver + * @{ + */ + +/** @defgroup PDMA PDMA + * @brief PDMA driver modules + * @{ + */ + + +/* Global functions ----------------------------------------------------------------------------------------*/ +/** @defgroup PDMA_Exported_Functions PDMA exported functions + * @{ + */ +/*********************************************************************************************************//** + * @brief Deinitialize the PDMA peripheral registers to their default reset values. + * @retval None + ************************************************************************************************************/ +void PDMA_DeInit(void) +{ + RSTCU_PeripReset_TypeDef RSTCUReset = {{0}}; + + RSTCUReset.Bit.PDMA = 1; + RSTCU_PeripReset(RSTCUReset, ENABLE); +} + +/*********************************************************************************************************//** + * @brief Configure specific PDMA channel + * @param PDMA_CHn: PDMA_CH0 ~ PDMA_CH5 + * @param PDMACH_InitStruct: pointer to a PDMACH_InitTypeDef structure. + * @retval None + ************************************************************************************************************/ +void PDMA_Config(u32 PDMA_CHn, PDMACH_InitTypeDef *PDMACH_InitStruct) +{ + HT_PDMACH_TypeDef *PDMACHx = (HT_PDMACH_TypeDef *)(HT_PDMA_BASE + PDMA_CHn * 6 * 4); + + /* Check the parameters */ + Assert_Param(IS_PDMA_CH(PDMA_CHn)); + Assert_Param(IS_PDMA_WIDTH(PDMACH_InitStruct->PDMACH_DataSize)); + Assert_Param(IS_PDMA_PRIO(PDMACH_InitStruct->PDMACH_Priority)); + Assert_Param(IS_PDMA_ADR_MOD(PDMACH_InitStruct->PDMACH_AdrMod)); + Assert_Param(IS_PDMA_BLK_CNT(PDMACH_InitStruct->PDMACH_BlkCnt)); + Assert_Param(IS_PDMA_BLK_LEN(PDMACH_InitStruct->PDMACH_BlkLen)); + + /* PDMA channel x configuration */ + PDMACHx->CR = (PDMACH_InitStruct->PDMACH_DataSize | PDMACH_InitStruct->PDMACH_Priority | PDMACH_InitStruct->PDMACH_AdrMod); + + PDMACHx->SADR = PDMACH_InitStruct->PDMACH_SrcAddr; + + PDMACHx->DADR = PDMACH_InitStruct->PDMACH_DstAddr; + + PDMACHx->TSR = (PDMACH_InitStruct->PDMACH_BlkCnt << 16) | PDMACH_InitStruct->PDMACH_BlkLen; +} + +/*********************************************************************************************************//** + * @brief PDMA_AddrConfig + * @param PDMA_CHn: PDMA_CH0 ~ PDMA_CH5 + * @param SrcAddr: Source address + * @param DstAddr: Destination address + * @retval None + ************************************************************************************************************/ +void PDMA_AddrConfig(u32 PDMA_CHn, u32 SrcAddr, u32 DstAddr) +{ + HT_PDMACH_TypeDef *PDMACHx = (HT_PDMACH_TypeDef *)(HT_PDMA_BASE + PDMA_CHn * 6 * 4); + + /* Check the parameters */ + Assert_Param(IS_PDMA_CH(PDMA_CHn)); + + /* transfer address configuration */ + PDMACHx->SADR = SrcAddr; + PDMACHx->DADR = DstAddr; +} + +/*********************************************************************************************************//** + * @brief PDMA_SrcAddrConfig + * @param PDMA_CHn: PDMA_CH0 ~ PDMA_CH5 + * @param SrcAddr: Source address + * @retval None + ************************************************************************************************************/ +void PDMA_SrcAddrConfig(u32 PDMA_CHn, u32 SrcAddr) +{ + HT_PDMACH_TypeDef *PDMACHx = (HT_PDMACH_TypeDef *)(HT_PDMA_BASE + PDMA_CHn * 6 * 4); + + /* Check the parameters */ + Assert_Param(IS_PDMA_CH(PDMA_CHn)); + + /* transfer address configuration */ + PDMACHx->SADR = SrcAddr; +} + +/*********************************************************************************************************//** + * @brief PDMA_DstAddrConfig + * @param PDMA_CHn: PDMA_CH0 ~ PDMA_CH5 + * @param DstAddr: Destination address + * @retval None + ************************************************************************************************************/ +void PDMA_DstAddrConfig(u32 PDMA_CHn, u32 DstAddr) +{ + HT_PDMACH_TypeDef *PDMACHx = (HT_PDMACH_TypeDef *)(HT_PDMA_BASE + PDMA_CHn * 6 * 4); + + /* Check the parameters */ + Assert_Param(IS_PDMA_CH(PDMA_CHn)); + + /* transfer address configuration */ + PDMACHx->DADR = DstAddr; +} + +/*********************************************************************************************************//** + * @brief PDMA_TranSizeConfig + * @param PDMA_CHn: PDMA_CH0 ~ PDMA_CH5 + * @param BlkCnt: Number of blocks for a transfer + * @param BlkLen: Number of data for a block + * @retval None + ************************************************************************************************************/ +void PDMA_TranSizeConfig(u32 PDMA_CHn, u16 BlkCnt, u16 BlkLen) +{ + HT_PDMACH_TypeDef *PDMACHx = (HT_PDMACH_TypeDef *)(HT_PDMA_BASE + PDMA_CHn * 6 * 4); + + /* Check the parameters */ + Assert_Param(IS_PDMA_CH(PDMA_CHn)); + Assert_Param(IS_PDMA_BLK_CNT(BlkCnt)); + Assert_Param(IS_PDMA_BLK_LEN(BlkLen)); + + /* transfer size configuration */ + PDMACHx->TSR = ((BlkCnt << 16) | BlkLen); +} + +/*********************************************************************************************************//** + * @brief Enable the specific PDMA channel interrupts + * @param PDMA_CHn: PDMA_CH0 ~ PDMA_CH5 + * @param PDMA_INT_x: PDMA_INT_GE, PDMA_INT_BE, PDMA_INT_HT, PDMA_INT_TC, PDMA_INT_TE + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void PDMA_IntConfig(u32 PDMA_CHn, u32 PDMA_INT_x, ControlStatus NewState) +{ + u32 uRegTmp = 0; + + /* Check the parameters */ + Assert_Param(IS_PDMA_CH(PDMA_CHn)); + Assert_Param(IS_PDMA_INT(PDMA_INT_x)); + Assert_Param(IS_CONTROL_STATUS(NewState)); + + #if (LIBCFG_PDMA_CH3FIX) + if (PDMA_CHn == PDMA_CH3) + { + if (PDMA_INT_x & PDMA_INT_BE) + { + uRegTmp |= (PDMA_INT_BE << (PDMA_CH2 * 5)); + } + if (PDMA_INT_x & PDMA_INT_HT) + { + uRegTmp |= (PDMA_INT_HT << (PDMA_CH2 * 5)); + } + } + #endif + + if (NewState != DISABLE) + { + HT_PDMA->IER |= ((PDMA_INT_x << (PDMA_CHn * 5)) | uRegTmp); + } + else + { + HT_PDMA->IER &= ~(PDMA_INT_x << (PDMA_CHn * 5)); + } +} + +/*********************************************************************************************************//** + * @brief Enable a specific PDMA channel + * @param PDMA_CHn: PDMA_CH0 ~ PDMA_CH5 + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void PDMA_EnaCmd(u32 PDMA_CHn, ControlStatus NewState) +{ + HT_PDMACH_TypeDef *PDMACHx = (HT_PDMACH_TypeDef *)(HT_PDMA_BASE + PDMA_CHn * 6 * 4); + + /* Check the parameters */ + Assert_Param(IS_PDMA_CH(PDMA_CHn)); + Assert_Param(IS_CONTROL_STATUS(NewState)); + + if (NewState != DISABLE) + { + PDMACHx->CR |= (1UL); + } + else + { + PDMACHx->CR &= ~(1UL); + } +} + +/*********************************************************************************************************//** + * @brief Software trigger a specific PDMA channel + * @param PDMA_CHn: PDMA_CH0 ~ PDMA_CH5 + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void PDMA_SwTrigCmd(u32 PDMA_CHn, ControlStatus NewState) +{ + HT_PDMACH_TypeDef *PDMACHx = (HT_PDMACH_TypeDef *)(HT_PDMA_BASE + PDMA_CHn * 6 * 4); + + /* Check the parameters */ + Assert_Param(IS_PDMA_CH(PDMA_CHn)); + Assert_Param(IS_CONTROL_STATUS(NewState)); + + if (NewState != DISABLE) + { + PDMACHx->CR |= (1UL << 1); + } + else + { + PDMACHx->CR &= ~(1UL << 1); + } +} + +/*********************************************************************************************************//** + * @brief Get the specific PDMA channel interrupt flag + * @param PDMA_CHn: PDMA_CH0 ~ PDMA_CH5 + * @param PDMA_FLAG_x: PDMA_FLAG_GE, PDMA_FLAG_BE, PDMA_FLAG_HT, PDMA_FLAG_TC, PDMA_FLAG_TE + * @retval SET or RESET + ************************************************************************************************************/ +FlagStatus PDMA_GetFlagStatus(u32 PDMA_CHn, u32 PDMA_FLAG_x) +{ + /* !!! NOTICE !!! + Must turn on the PDMA IER to get the ISR flag. + For example: PDMA_GetFlagStatus(PDMA_CH0, PDMA_INT_TC, ENABLE); + */ + + /* Check the parameters */ + Assert_Param(IS_PDMA_CH(PDMA_CHn)); + Assert_Param(IS_PDMA_FLAG(PDMA_FLAG_x)); + + if (HT_PDMA->ISR & (PDMA_FLAG_x << PDMA_CHn * 5)) + { + return SET; + } + else + { + return RESET; + } +} + +/*********************************************************************************************************//** + * @brief Clear the specific PDMA channel interrupt flags + * @param PDMA_CHn: PDMA_CH0 ~ PDMA_CH5 + * @param PDMA_FLAG_x: PDMA_FLAG_GE, PDMA_FLAG_BE, PDMA_FLAG_HT, PDMA_FLAG_TC, PDMA_FLAG_TE + * @retval None + ************************************************************************************************************/ +void PDMA_ClearFlag(u32 PDMA_CHn, u32 PDMA_FLAG_x) +{ + /* Check the parameters */ + Assert_Param(IS_PDMA_CH(PDMA_CHn)); + Assert_Param(IS_PDMA_CLEAR_FLAG(PDMA_FLAG_x)); + + HT_PDMA->ISCR |= (PDMA_FLAG_x << PDMA_CHn * 5); +} + +/*********************************************************************************************************//** + * @brief Get remain block count of the specific PDMA channel + * @retval CBLKCNT + ************************************************************************************************************/ +u16 PDMA_GetRemainBlkCnt(u32 PDMA_CHn) +{ + HT_PDMACH_TypeDef *PDMACHx = (HT_PDMACH_TypeDef *)(HT_PDMA_BASE + PDMA_CHn * 6 * 4); + + /* Check the parameters */ + Assert_Param(IS_PDMA_CH(PDMA_CHn)); + + return ((PDMACHx->CTSR) >> 16); +} +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/ht32f5xxxx_pwm.c b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/ht32f5xxxx_pwm.c new file mode 100644 index 0000000000..b824c72b16 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/ht32f5xxxx_pwm.c @@ -0,0 +1,2 @@ +The SCTM, PWM, GPTM, and MCTM timer have similar architecture. They use the same driver, +"ht32fxxxxx_tm.c/.h" to save the code size. For those timers, please refet to the TM driver/example. diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/ht32f5xxxx_pwrcu.c b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/ht32f5xxxx_pwrcu.c new file mode 100644 index 0000000000..0ab83cf919 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/ht32f5xxxx_pwrcu.c @@ -0,0 +1,846 @@ +/*********************************************************************************************************//** + * @file ht32f5xxxx_pwrcu.c + * @version $Rev:: 6386 $ + * @date $Date:: 2022-10-27 #$ + * @brief This file provides all the Power Control Unit firmware functions. + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ + +/* Includes ------------------------------------------------------------------------------------------------*/ +#include "ht32f5xxxx_pwrcu.h" + +/** @addtogroup HT32F5xxxx_Peripheral_Driver HT32F5xxxx Peripheral Driver + * @{ + */ + +/** @defgroup PWRCU PWRCU + * @brief PWRCU driver modules + * @{ + */ + + +/* Private constants ---------------------------------------------------------------------------------------*/ +/** @defgroup PWRCU_Private_Define PWRCU private definitions + * @{ + */ +#define Set_RTCEN SetBit_BB((u32)&HT_CKCU->APBCCR1, 6); +#define Reset_RTCEN ResetBit_BB((u32)&HT_CKCU->APBCCR1, 6); +#define Get_RTCEN GetBit_BB((u32)&HT_CKCU->APBCCR1, 6) + +#define Set_LDOMODE SetBit_BB((u32)&HT_PWRCU->CR, 2) +#define Reset_LDOMODE ResetBit_BB((u32)&HT_PWRCU->CR, 2) + +#define Set_LDOOFF SetBit_BB((u32)&HT_PWRCU->CR, 3) +#define Reset_LDOOFF ResetBit_BB((u32)&HT_PWRCU->CR, 3) + +#define Set_DMOSON SetBit_BB((u32)&HT_PWRCU->CR, 7) +#define Reset_DMOSON ResetBit_BB((u32)&HT_PWRCU->CR, 7) + +#define Set_WUP0EN SetBit_BB((u32)&HT_PWRCU->CR, 8) +#define Reset_WUP0EN ResetBit_BB((u32)&HT_PWRCU->CR, 8) + +#if (LIBCFG_PWRCU_WAKEUP1) +#define Set_WUP1EN SetBit_BB((u32)&HT_PWRCU->CR, 10) +#define Reset_WUP1EN ResetBit_BB((u32)&HT_PWRCU->CR, 10) +#endif + +#if (LIBCFG_PWRCU_V15_READY_SOURCE) +#define Set_V15RDYSC SetBit_BB((u32)&HT_PWRCU->CR, 12) +#define Reset_V15RDYSC ResetBit_BB((u32)&HT_PWRCU->CR, 12) +#endif + +#define Set_DMOSSTS SetBit_BB((u32)&HT_PWRCU->CR, 15) +#define Reset_DMOSSTS ResetBit_BB((u32)&HT_PWRCU->CR, 15) +#define Get_DMOSSTS GetBit_BB((u32)&HT_PWRCU->CR, 15) + +#define Set_BODEN SetBit_BB((u32)&HT_PWRCU->LVDCSR, 0) +#define Reset_BODEN ResetBit_BB((u32)&HT_PWRCU->LVDCSR, 0) + +#define Set_BODRIS SetBit_BB((u32)&HT_PWRCU->LVDCSR, 1) +#define Reset_BODRIS ResetBit_BB((u32)&HT_PWRCU->LVDCSR, 1) + +#define Set_BODF SetBit_BB((u32)&HT_PWRCU->LVDCSR, 3) +#define Reset_BODF ResetBit_BB((u32)&HT_PWRCU->LVDCSR, 3) +#define Get_BODF GetBit_BB((u32)&HT_PWRCU->LVDCSR, 3) + +#define Set_LVDEN SetBit_BB((u32)&HT_PWRCU->LVDCSR, 16) +#define Reset_LVDEN ResetBit_BB((u32)&HT_PWRCU->LVDCSR, 16) + +#define Set_LVDF SetBit_BB((u32)&HT_PWRCU->LVDCSR, 19) +#define Reset_LVDF ResetBit_BB((u32)&HT_PWRCU->LVDCSR, 19) +#define Get_LVDF GetBit_BB((u32)&HT_PWRCU->LVDCSR, 19) + +#define Set_LVDIWEN SetBit_BB((u32)&HT_PWRCU->LVDCSR, 20) +#define Reset_LVDIWEN ResetBit_BB((u32)&HT_PWRCU->LVDCSR, 20) + +#define Set_LVDEWEN SetBit_BB((u32)&HT_PWRCU->LVDCSR, 21) +#define Reset_LVDEWEN ResetBit_BB((u32)&HT_PWRCU->LVDCSR, 21) + +#define SLEEPDEEP_SET 0x04 /*!< Cortex SLEEPDEEP bit */ + +#define PWRRST_SET 0x1 +#define PWRTEST_READY 0x27 +#define TIME_OUT 24000000 +#define WUP0TYPE_MASK 0xFFFCFFFF +#define WUP1TYPE_MASK 0xFFF3FFFF +#define LVDS_MASK 0xFFB9FFFF +#define VREG_V_MASK 0xF3FFFFFF +#define VREG_M_MASK 0xFCFFFFFF +#define PWRRST_SET 0x1 +/** + * @} + */ + +/* Global functions ----------------------------------------------------------------------------------------*/ +/** @defgroup PWRCU_Exported_Functions PWRCU exported functions + * @{ + */ +/*********************************************************************************************************//** + * @brief Deinitialize backup domain which contains PWRCU and RTC units. + * @retval None + ************************************************************************************************************/ +void PWRCU_DeInit(void) +{ + HT_PWRCU->CR = PWRRST_SET; + while(HT_PWRCU->CR & 0xFFFFEFFF); /* Skip Bit 12 because it isn't of valuable reference. */ + #if (LIBCFG_PWRCU_NO_PORF) + #else + while (HT_PWRCU->SR); /* Waits until the PWRPORF be cleared by read */ + #endif +} + +#if (!LIBCFG_NO_PWRCU_TEST_REG) +/*********************************************************************************************************//** + * @brief Waits, until the PWRCU can be accessed. + * @retval PWRCU_TIMEOUT or PWRCU_OK + ************************************************************************************************************/ +PWRCU_Status PWRCU_CheckReadyAccessed(void) +{ + u32 wTimeOutCnt = TIME_OUT; + + while (--wTimeOutCnt) + { + if (HT_PWRCU->TEST == PWRTEST_READY) + { + return PWRCU_OK; + } + } + return PWRCU_TIMEOUT; +} +#endif + +/*********************************************************************************************************//** + * @brief Return the flags of PWRCU. + * @retval This function will return one of the following: + * - 0x0000 : There is no flag is set. + * - 0x0001 (PWRCU_FLAG_PWRPOR) : VDD power domain power-on reset flag has been set. + * - 0x0002 (PWRCU_FLAG_PD) : Power-Down flag has been set. + * - 0x0010 (PWRCU_FLAG_POR) : Power-on reset flag has been set. + * - 0x0100 (PWRCU_FLAG_WUP0) : External WAKEUP0 pin flag has been set. + * - 0x0200 (PWRCU_FLAG_WUP1) : External WAKEUP1 pin flag has been set. + ************************************************************************************************************/ +u16 PWRCU_GetFlagStatus(void) +{ + return HT_PWRCU->SR; +} + +#if (LIBCFG_BAKREG) +/*********************************************************************************************************//** + * @brief Return the value of specified backup register. + * @param BAKREGx: Number of backup register. Where x can be 0 ~ 9. + * @return Between 0x0 ~ 0xFFFFFFFF. + ************************************************************************************************************/ +u32 PWRCU_ReadBackupRegister(PWRCU_BAKREG_Enum BAKREGx) +{ + /* Check the parameters */ + Assert_Param(IS_PWRCU_BAKREG(BAKREGx)); + + return HT_PWRCU->BAKREG[BAKREGx]; +} + +/*********************************************************************************************************//** + * @brief Write the DATA to specified backup register. + * @param BAKREGx : Number of backup registers. Where x can be 0 ~ 9. + * @param DATA : Must between 0x0 ~ 0xFFFFFFFF. + * @retval None + ************************************************************************************************************/ +void PWRCU_WriteBackupRegister(PWRCU_BAKREG_Enum BAKREGx, u32 DATA) +{ + /* Check the parameters */ + Assert_Param(IS_PWRCU_BAKREG(BAKREGx)); + + HT_PWRCU->BAKREG[BAKREGx] = DATA; +} +#endif + +/*********************************************************************************************************//** + * @brief Enter SLEEP mode. + * @param SleepEntry : Enters sleep mode instruction that is used to WFI or WFE. + * This parameter can be one of the following values: + * @arg PWRCU_SLEEP_ENTRY_WFE : Enters SLEEP mode via WFE instruction + * @arg PWRCU_SLEEP_ENTRY_WFI : Enters SLEEP mode via WFI instruction + * @retval None + ************************************************************************************************************/ +void PWRCU_Sleep(PWRCU_SLEEP_ENTRY_Enum SleepEntry) +{ + /* Check the parameters */ + Assert_Param(IS_PWRCU_SLEEP_ENTRY(SleepEntry)); + + /* Clear SLEEPDEEP bit of Cortex System Control Register */ + SCB->SCR &= ~(u32)SLEEPDEEP_SET; + + if (SleepEntry == PWRCU_SLEEP_ENTRY_WFE) + { + /* Wait for event */ + __SEV(); + __WFE(); + __WFE(); + } + else + { + /* Wait for interrupt */ + __WFI(); + } +} + +/*********************************************************************************************************//** + * @brief Enter DEEP-SLEEP Mode 1. + * @param SleepEntry : Enters sleep mode instruction that is used to WFI or WFE. + * This parameter can be one of the following values: + * @arg PWRCU_SLEEP_ENTRY_WFE : Enters SLEEP mode via WFE instruction + * @arg PWRCU_SLEEP_ENTRY_WFI : Enters SLEEP mode via WFI instruction + * @retval None + ************************************************************************************************************/ +void PWRCU_DeepSleep1(PWRCU_SLEEP_ENTRY_Enum SleepEntry) +{ + u32 uRTCStatus = 0; + /* Check the parameters */ + Assert_Param(IS_PWRCU_SLEEP_ENTRY(SleepEntry)); + + uRTCStatus = Get_RTCEN; + Set_RTCEN; + + Reset_DMOSON; + Reset_LDOOFF; + + /* Sets SLEEPDEEP bit of Cortex System Control Register */ + SCB->SCR |= SLEEPDEEP_SET; + + if (uRTCStatus == 0) + { + Reset_RTCEN; + } + + if (SleepEntry == PWRCU_SLEEP_ENTRY_WFE) + { + /* Wait for event */ + __SEV(); + __WFE(); + __WFE(); + } + else + { + /* Wait for interrupt */ + __WFI(); + } + + SCB->SCR &= ~(u32)SLEEPDEEP_SET; +} + +/*********************************************************************************************************//** + * @brief Enter DEEP-SLEEP Mode 2. + * @param SleepEntry : Enters sleep mode instruction that is used to WFI or WFE. + * This parameter can be one of the following values: + * @arg PWRCU_SLEEP_ENTRY_WFE : Enters SLEEP mode via WFE instruction + * @arg PWRCU_SLEEP_ENTRY_WFI : Enters SLEEP mode via WFI instruction + * @retval None + ************************************************************************************************************/ +void PWRCU_DeepSleep2(PWRCU_SLEEP_ENTRY_Enum SleepEntry) +{ + u32 uRTCStatus = 0; + /* Check the parameters */ + Assert_Param(IS_PWRCU_SLEEP_ENTRY(SleepEntry)); + + uRTCStatus = Get_RTCEN; + Set_RTCEN; + + if (Get_DMOSSTS == 0) + { + Reset_DMOSON; + Set_DMOSON; + } + Reset_LDOOFF; + + if (uRTCStatus == 0) + { + Reset_RTCEN; + } + + /* Sets SLEEPDEEP bit of Cortex System Control Register */ + SCB->SCR |= SLEEPDEEP_SET; + + if (SleepEntry == PWRCU_SLEEP_ENTRY_WFE) + { + /* Wait for event */ + __SEV(); + __WFE(); + __WFE(); + } + else + { + /* Wait for interrupt */ + __WFI(); + } + + SCB->SCR &= ~(u32)SLEEPDEEP_SET; +} + +#if !defined(USE_HT32F52220_30) +/*********************************************************************************************************//** + * @brief Enter DEEP-SLEEP Mode 2. + * @param SleepEntry : Enters sleep mode instruction that is used to WFI or WFE. + * This parameter can be one of the following values: + * @arg PWRCU_SLEEP_ENTRY_WFE : Enters SLEEP mode via WFE instruction + * @arg PWRCU_SLEEP_ENTRY_WFI : Enters SLEEP mode via WFI instruction + * @retval None + ************************************************************************************************************/ +void PWRCU_DeepSleep2Ex(PWRCU_SLEEP_ENTRY_Enum SleepEntry) +{ + u32 uRTCStatus = 0; + u32 uBackUp[4]; + + /* Check the parameters */ + Assert_Param(IS_PWRCU_SLEEP_ENTRY(SleepEntry)); + + uRTCStatus = Get_RTCEN; + Set_RTCEN; + uBackUp[0] = HT_RTC->CMP; + uBackUp[1] = HT_RTC->IWEN; + uBackUp[2] = HT_RTC->CR; + uBackUp[3] = HT_EXTI->WAKUPCR; + + Set_DMOSON; + Reset_LDOOFF; + + /* Sets SLEEPDEEP bit of Cortex System Control Register */ + SCB->SCR |= SLEEPDEEP_SET; + + if (SleepEntry == PWRCU_SLEEP_ENTRY_WFE) + { + /* Wait for event */ + __SEV(); + __WFE(); + __WFE(); + } + else + { + /* Wait for interrupt */ + __WFI(); + } + + if (HT_EXTI->WAKUPFLG) + { + HT_EXTI->WAKUPCR &= ~(0xFFFF); + HT_EXTI->WAKUPFLG = 0xFFFF; + HT_RTC->CR &= (~1UL); + HT_RTC->CMP = 1; + HT_RTC->IWEN = (1 << 9); + HT_RTC->CR = (1 << 4) | (1 << 2) | (1 << 0); + __SEV(); + __WFE(); + __WFE(); + HT_RTC->CR &= (~1UL); + rw((u32)&HT_RTC->SR); + + HT_RTC->CMP = uBackUp[0]; + HT_RTC->IWEN = uBackUp[1]; + HT_RTC->CR = uBackUp[2]; + HT_EXTI->WAKUPCR = uBackUp[3]; + } + + SCB->SCR &= ~(u32)SLEEPDEEP_SET; + + if (uRTCStatus == 0) + { + Reset_RTCEN; + } +} +#endif + +#if (!LIBCFG_PWRCU_NO_PD_MODE) +/*********************************************************************************************************//** + * @brief Enter POWER-DOWN Mode. + * @retval None + ************************************************************************************************************/ +void PWRCU_PowerDown(void) +{ + u32 uRTCStatus = 0; + + uRTCStatus = Get_RTCEN; + Set_RTCEN; + + #if (LIBCFG_RTC_LSI_LOAD_TRIM) + { + static u8 isLSITrimLoaded = FALSE; + if (isLSITrimLoaded == FALSE) + { + u32 i = 4800; + isLSITrimLoaded = TRUE; + HT_RTC->CR &= ~(1UL << 2); + /* Insert a delay must > 1 CK_RTC */ + while (i--); + HT_RTC->CR |= (1UL << 2); + while ((HT_CKCU->GCSR & 0x20) == 0); + } + } + #endif + + Reset_DMOSON; + Set_LDOOFF; + + if (uRTCStatus == 0) + { + Reset_RTCEN; + } + + /* Sets SLEEPDEEP bit of Cortex System Control Register */ + SCB->SCR |= SLEEPDEEP_SET; + + /* Enters power-down mode */ + __SEV(); + __WFE(); + __WFE(); + + { + u32 X = (16 * 250); + while (X--); + } + + NVIC_SystemReset(); +} +#endif + +/*********************************************************************************************************//** + * @brief Configure LVD voltage level. + * @param Level: Low voltage detect level. + * This parameter can be one of the following: + * VDD 2.0 ~ 3.6V version: + * @arg PWRCU_LVDS_2V25 : 2.25 V + * @arg PWRCU_LVDS_2V4 : 2.40 V + * @arg PWRCU_LVDS_2V55 : 2.55 V + * @arg PWRCU_LVDS_2V7 : 2.70 V + * @arg PWRCU_LVDS_2V85 : 2.85 V + * @arg PWRCU_LVDS_3V : 3.00 V + * @arg PWRCU_LVDS_3V15 : 3.15 V + * @arg PWRCU_LVDS_3V3 : 3.30 V + * VDD 1.65 ~ 3.6V version: + * @arg PWRCU_LVDS_1V75 : 1.75 V + * @arg PWRCU_LVDS_1V95 : 1.95 V + * @arg PWRCU_LVDS_2V15 : 2.15 V + * @arg PWRCU_LVDS_2V35 : 2.35 V + * @arg PWRCU_LVDS_2V55 : 2.55 V + * @arg PWRCU_LVDS_2V75 : 2.75 V + * @arg PWRCU_LVDS_2V95 : 2.95 V + * @arg PWRCU_LVDS_3V15 : 3.15 V + * VDD 5.0V version: + * @arg PWRCU_LVDS_2V65 : 2.65 V + * @arg PWRCU_LVDS_2V85 : 2.85 V + * @arg PWRCU_LVDS_3V05 : 3.05 V + * @arg PWRCU_LVDS_3V25 : 3.25 V + * @arg PWRCU_LVDS_3V45 : 3.45 V + * @arg PWRCU_LVDS_4V25 : 4.25 V + * @arg PWRCU_LVDS_4V45 : 4.45 V + * @arg PWRCU_LVDS_4V65 : 4.65 V + * @retval None + ************************************************************************************************************/ +void PWRCU_SetLVDS(PWRCU_LVDS_Enum Level) +{ + /* Check the parameters */ + Assert_Param(IS_PWRCU_LVDS(Level)); + + HT_PWRCU->LVDCSR = (HT_PWRCU->LVDCSR & LVDS_MASK) | Level; +} + +/*********************************************************************************************************//** + * @brief Enable or Disable LVD function. + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void PWRCU_LVDCmd(ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_CONTROL_STATUS(NewState)); + + if (NewState != DISABLE) + { + Set_LVDEN; + } + else + { + Reset_LVDEN; + } +} + +/*********************************************************************************************************//** + * @brief Enable or Disable BOD reset function. + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void PWRCU_BODCmd(ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_CONTROL_STATUS(NewState)); + + if (NewState != DISABLE) + { + Set_BODEN; + } + else + { + Reset_BODEN; + } +} + +/*********************************************************************************************************//** + * @brief Select when the BOD occurs, the action for the cause Reset or Interrupt. + * @param Selection: BOD reset or interrupt selection. + * This parameter can be one of the following values: + * @arg PWRCU_BODRIS_RESET : Reset the whole chip + * @arg PWRCU_BODRIS_INT : Assert interrupt + * @retval None + ************************************************************************************************************/ +void PWRCU_BODRISConfig(PWRCU_BODRIS_Enum Selection) +{ + /* Check the parameters */ + Assert_Param(IS_PWRCU_BODRIS(Selection)); + + if (Selection != PWRCU_BODRIS_RESET) + { + Set_BODRIS; + } + else + { + Reset_BODRIS; + } +} + +/*********************************************************************************************************//** + * @brief Return the flag status of LVD. + * @retval SET or RESET + ************************************************************************************************************/ +FlagStatus PWRCU_GetLVDFlagStatus(void) +{ + return (FlagStatus)Get_LVDF; +} + +/*********************************************************************************************************//** + * @brief Return the flag status of BOD. + * @retval SET or RESET + ************************************************************************************************************/ +FlagStatus PWRCU_GetBODFlagStatus(void) +{ + return (FlagStatus)Get_BODF; +} + +/*********************************************************************************************************//** + * @brief Return the DMOS status. + * @retval This function will return one of the following values: + * - PWRCU_DMOS_STS_ON : DMOS on + * - PWRCU_DMOS_STS_OFF : DMOS off + * - PWRCU_DMOS_STS_OFF_BY_BODRESET : DMOS off caused by brow out reset + ************************************************************************************************************/ +PWRCU_DMOSStatus PWRCU_GetDMOSStatus(void) +{ + u32 wDmosStatus = HT_PWRCU->CR & 0x8080; + + if (wDmosStatus == 0x0) + { + return PWRCU_DMOS_STS_OFF; + } + else if (wDmosStatus == 0x8080) + { + return PWRCU_DMOS_STS_ON; + } + else + { + return PWRCU_DMOS_STS_OFF_BY_BODRESET; + } +} + +/*********************************************************************************************************//** + * @brief Enable or Disable DMOS function. + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void PWRCU_DMOSCmd(ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_CONTROL_STATUS(NewState)); + + if (Get_DMOSSTS == 0) + { + Reset_DMOSON; + } + + if (NewState != DISABLE) + { + Set_DMOSON; + } + else + { + Reset_DMOSON; + } +} + +/*********************************************************************************************************//** + * @brief Configure the LDO operation mode. + * @param Sel: Specify the LDO mode. + * This parameter can be one of the following values: + * @arg PWRCU_LDO_NORMAL : The LDO is operated in normal current mode + * @arg PWRCU_LDO_LOWCURRENT : The LDO is operated in low current mode + * @retval None + ************************************************************************************************************/ +void PWRCU_LDOConfig(PWRCU_LDOMODE_Enum Sel) +{ + u32 uRTCStatus = 0; + + /* Check the parameters */ + Assert_Param(IS_PWRCU_LDOMODE(Sel)); + + uRTCStatus = Get_RTCEN; + Set_RTCEN; + + if (Sel == PWRCU_LDO_NORMAL) + { + Reset_LDOMODE; + } + else + { + Set_LDOMODE; + } + + if (uRTCStatus == 0) + { + Reset_RTCEN; + } +} + +#if (LIBCFG_PWRCU_V15_READY_SOURCE) +/*********************************************************************************************************//** + * @brief Configure VDD15 power good source. + * @param Sel: specifies VDD15 power good source. + * This parameter can be one of the following values: + * @arg PWRCU_V15RDYSC_V33ISO : Vdd15 power good source come from V33_ISO bit in CKCU unit + * @arg PWRCU_V15RDYSC_V15POR : Vdd15 power good source come from Vdd15 power-on reset + * @retval None + ************************************************************************************************************/ +void PWRCU_V15RDYSourceConfig(PWRCU_V15RDYSC_Enum Sel) +{ + /* Check the parameters */ + Assert_Param(IS_PWRCU_V15RDYSC(Sel)); + + if (Sel == PWRCU_V15RDYSC_V33ISO) + { + Reset_V15RDYSC; + } + else + { + Set_V15RDYSC; + } +} +#endif + +/*********************************************************************************************************//** + * @brief Enable or Disable the LVD interrupt wakeup function. + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void PWRCU_LVDIntWakeupConfig(ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_CONTROL_STATUS(NewState)); + + if (NewState != DISABLE) + { + Set_LVDIWEN; + } + else + { + Reset_LVDIWEN; + } +} + +/*********************************************************************************************************//** + * @brief Enable or Disable the LVD event wakeup function. + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void PWRCU_LVDEventWakeupConfig(ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_CONTROL_STATUS(NewState)); + + if (NewState != DISABLE) + { + Set_LVDEWEN; + } + else + { + Reset_LVDEWEN; + } +} + +#if (LIBCFG_PWRCU_VREG) +/*********************************************************************************************************//** + * @brief Configure the VREG output voltage. + * @param Volt: VREG output voltage. + * This parameter can be one of the following: + * @arg PWRCU_VREG_4V0 : 4.0 V + * @arg PWRCU_VREG_3V3 : 3.3 V + * @arg PWRCU_VREG_3V0 : 3.0 V + * @arg PWRCU_VREG_2V5 : 2.5 V + * @arg PWRCU_VREG_1V8 : 1.8 V + * @retval None + ************************************************************************************************************/ +void PWRCU_SetVREG(PWRCU_VREG_VOLT_Enum Volt) +{ + /* Check the parameters */ + Assert_Param(IS_PWRCU_VREG_VOLT(Volt)); + + HT_PWRCU->CR = (HT_PWRCU->CR & VREG_V_MASK) | Volt; +} + +/*********************************************************************************************************//** + * @brief Configure the VREG operation mode. + * @param Mode: VREG operation mode. + * This parameter can be one of the following values: + * @arg PWRCU_VREG_DISABLE : The VREG is disabled + * @arg PWRCU_VREG_ENABLE : The VREG is enabled + * @arg PWRCU_VREG_BYPASS : The VREG is bypassed + * @retval None + ************************************************************************************************************/ +void PWRCU_VREGConfig(PWRCU_VREG_MODE_Enum Mode) +{ + /* Check the parameters */ + Assert_Param(IS_PWRCU_VREG_MODE(Mode)); + + HT_PWRCU->CR = (HT_PWRCU->CR & VREG_M_MASK) | Mode; +} +#endif + +/*********************************************************************************************************//** + * @brief Enable or Disable the external WAKEUP pin function. + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void PWRCU_WakeupPinCmd(ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_CONTROL_STATUS(NewState)); + + if (NewState != DISABLE) + { + Set_WUP0EN; + } + else + { + Reset_WUP0EN; + } +} + +#if (LIBCFG_PWRCU_WAKEUP_V01) +/*********************************************************************************************************//** + * @brief Enable or Disable the external WAKEUP pin function. + * @param Pin: specify the WAKEUP pin number. + * This parameter can be one of the following values: + * @arg PWRCU_WAKEUP_PIN_0 : + * @arg PWRCU_WAKEUP_PIN_1 : + * @param Type: specify the WAKEUP pin type. + * This parameter can be one of the following values: + * @arg PWRCU_WUP_POSITIVE_EDGE : + * @arg PWRCU_WUP_NEGATIVE_EDGE : + * @arg PWRCU_WUP_HIGH_LEVEL : + * @arg PWRCU_WUP_LOW_LEVEL : + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void PWRCU_WakeupMultiPinCmd(PWRCU_WUP_Enum Pin, PWRCU_WUPTYPE_Enum Type, ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_PWRCU_WAKEUPPIN(Pin)); + Assert_Param(IS_PWRCU_TRIGGERTYPE(Type)); + Assert_Param(IS_CONTROL_STATUS(NewState)); + + if (NewState != DISABLE) + { + if (Pin == PWRCU_WAKEUP_PIN_0) + { + HT_PWRCU->CR = (HT_PWRCU->CR & WUP0TYPE_MASK) | (Type << 16); + Set_WUP0EN; + } + else + { + HT_PWRCU->CR = (HT_PWRCU->CR & WUP1TYPE_MASK) | (Type << 18); + Set_WUP1EN; + } + } + else + { + if (Pin == PWRCU_WAKEUP_PIN_0) + Reset_WUP0EN; + else + Reset_WUP1EN; + } +} +#endif + +#if defined(USE_HT32F52342_52) || defined(USE_HT32F5826) +/*********************************************************************************************************//** + * @brief Configure HSI ready counter bit length. + * @param BitLength: HSI ready counter bit length. + * This parameter can be one of following: + * @arg PWRCU_HSIRCBL_4 : 4 bits + * @arg PWRCU_HSIRCBL_5 : 5 bits + * @arg PWRCU_HSIRCBL_6 : 6 bits + * @arg PWRCU_HSIRCBL_7 : 7 bits (Default) + * @retval None + ************************************************************************************************************/ +void PWRCU_HSIReadyCounterBitLengthConfig(PWRCU_HSIRCBL_Enum BitLength) +{ + /* Check the parameters */ + Assert_Param(IS_PWRCU_HSIRCBL(BitLength)); + + HT_PWRCU->HSIRCR = BitLength; +} +#endif +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/ht32f5xxxx_rstcu.c b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/ht32f5xxxx_rstcu.c new file mode 100644 index 0000000000..8c5ced5882 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/ht32f5xxxx_rstcu.c @@ -0,0 +1,142 @@ +/*********************************************************************************************************//** + * @file ht32f5xxxx_rstcu.c + * @version $Rev:: 6479 $ + * @date $Date:: 2022-11-23 #$ + * @brief This file provides all the Reset Control Unit firmware functions. + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ + +/* Includes ------------------------------------------------------------------------------------------------*/ +#include "ht32f5xxxx_rstcu.h" + +/** @addtogroup HT32F5xxxx_Peripheral_Driver HT32F5xxxx Peripheral Driver + * @{ + */ + +/** @defgroup RSTCU RSTCU + * @brief RSTCU driver modules + * @{ + */ + + +/* Global functions ----------------------------------------------------------------------------------------*/ +/** @defgroup RSTCU_Exported_Functions RSTCU exported functions + * @{ + */ +/*********************************************************************************************************//** + * @brief Check whether the specific global reset flag is set or not. + * @param RSTCU_RSTF: specify the reset flag. + * This parameter can be one of the following values: + * @arg RSTCU_FLAG_SYSRST : Get system reset flag + * @arg RSTCU_FLAG_EXTRST : Get external pin reset flag + * @arg RSTCU_FLAG_WDTRST : Get WDT reset flag + * @arg RSTCU_FLAG_PORST : Get power on reset flag + * @retval SET or RESET + ************************************************************************************************************/ +FlagStatus RSTCU_GetResetFlagStatus(RSTCU_RSTF_TypeDef RSTCU_RSTF) +{ + u32 tmp; + + /* Check the parameters */ + Assert_Param(IS_RSTCU_FLAG(RSTCU_RSTF)); + + tmp = (HT_RSTCU->GRSR & ((u32)0x1 << RSTCU_RSTF)); + if (tmp != RESET) + { + return SET; + } + else + { + return RESET; + } +} + +/*********************************************************************************************************//** + * @brief Clear the specific global reset flag. + * @param RSTCU_RSTF: specify the reset flag. + * This parameter can be one of the following values: + * @arg RSTCU_FLAG_SYSRST : Clear system reset flag + * @arg RSTCU_FLAG_EXTRST : Clear external pin reset flag + * @arg RSTCU_FLAG_WDTRST : Clear WDT reset flag + * @arg RSTCU_FLAG_PORST : Clear power on reset flag + * @retval None + ************************************************************************************************************/ +void RSTCU_ClearResetFlag(RSTCU_RSTF_TypeDef RSTCU_RSTF) +{ + /* Check the parameters */ + Assert_Param(IS_RSTCU_FLAG(RSTCU_RSTF)); + + HT_RSTCU->GRSR = (u32)0x1 << RSTCU_RSTF; /* Write 1 to clear */ +} + +/*********************************************************************************************************//** + * @brief Clear all of the global reset flag. + * @retval None + ************************************************************************************************************/ +void RSTCU_ClearAllResetFlag(void) +{ + HT_RSTCU->GRSR = (u32)0xF; /* Write 1 to clear */ +} + +/*********************************************************************************************************//** + * @brief Peripheral reset function. + * @param Reset: specify the peripheral clock enable bits. + * @param Cmd: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void RSTCU_PeripReset(RSTCU_PeripReset_TypeDef Reset, ControlStatus Cmd) +{ + u32 uAHBPRST; + u32 uAPBPRST0; + u32 uAPBPRST1; + + uAHBPRST = HT_RSTCU->AHBPRST; + uAPBPRST0 = HT_RSTCU->APBPRST0; + uAPBPRST1 = HT_RSTCU->APBPRST1; + + uAHBPRST &= ~(Reset.Reg[0]); + uAPBPRST0 &= ~(Reset.Reg[1]); + uAPBPRST1 &= ~(Reset.Reg[2]); + + if (Cmd != DISABLE) + { + uAHBPRST |= Reset.Reg[0]; + uAPBPRST0 |= Reset.Reg[1]; + uAPBPRST1 |= Reset.Reg[2]; + } + + HT_RSTCU->AHBPRST = uAHBPRST; + HT_RSTCU->APBPRST0 = uAPBPRST0; + HT_RSTCU->APBPRST1 = uAPBPRST1; +} +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/ht32f5xxxx_rtc.c b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/ht32f5xxxx_rtc.c new file mode 100644 index 0000000000..b4ae956433 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/ht32f5xxxx_rtc.c @@ -0,0 +1,393 @@ +/*********************************************************************************************************//** + * @file ht32f5xxxx_rtc.c + * @version $Rev:: 7336 $ + * @date $Date:: 2023-11-23 #$ + * @brief This file provides all the RTC firmware functions. + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ + +/* Includes ------------------------------------------------------------------------------------------------*/ +#include "ht32f5xxxx_rtc.h" + +/** @addtogroup HT32F5xxxx_Peripheral_Driver HT32F5xxxx Peripheral Driver + * @{ + */ + +/** @defgroup RTC RTC + * @brief RTC driver modules + * @{ + */ + + +/* Private constants ---------------------------------------------------------------------------------------*/ +/** @defgroup RTC_Private_Define RTC private definitions + * @{ + */ +#define RPRE_MASK (0xFFFFF0FF) + +/** + * @} + */ + +/* Global functions ----------------------------------------------------------------------------------------*/ +/** @defgroup RTC_Exported_Functions RTC exported functions + * @{ + */ +/*********************************************************************************************************//** + * @brief Deinitialize the RTC peripheral registers to their default reset values. + * @retval None + ************************************************************************************************************/ +void RTC_DeInit(void) +{ + HT_RTC->CR = 0x00000004; + HT_RTC->CMP = 0x0; + HT_RTC->IWEN = 0x0; + HT_RTC->CR |= 0x00000005; + while (HT_RTC->CNT); + HT_RTC->CR = 0x00000F04; + /* Read the RTC_SR register to clear it */ + HT_RTC->SR; +} + +/*********************************************************************************************************//** + * @brief Select the RTC timer clock source. + * @param Source: specify the clock source of RTC and backup domain. + * @arg RTC_SRC_LSI : Low speed internal clock. + * @arg RTC_SRC_LSE : Low speed external clock. + * @retval None + ************************************************************************************************************/ +void RTC_ClockSourceConfig(RTC_SRC_Enum Source) +{ + Assert_Param(IS_RTC_SRC(Source)); + + HT_RTC->CR = (HT_RTC->CR & ~(1UL << 1)) | ((u32)Source << 1); +} + +#if (LIBCFG_RTC_LSI_LOAD_TRIM) +/*********************************************************************************************************//** + * @brief Loads the LSI trim data. + * @retval None + ************************************************************************************************************/ +void RTC_LSILoadTrimData(void) +{ + u32 i = 4800; + u32 isRTCEnable = HT_CKCU->APBCCR1 & (1 << 6); + + HT_CKCU->APBCCR1 |= 1 << 6; + HT_RTC->CR &= ~(1UL << 2); + /* Insert a delay must > 1 CK_RTC */ + while (i--); + HT_RTC->CR |= (1UL << 2); + while ((HT_CKCU->GCSR & 0x20) == 0); + + if (isRTCEnable == 0) + HT_CKCU->APBCCR1 &= ~(1 << 6); +} +#endif + +#if (LIBCFG_LSE) +/*********************************************************************************************************//** + * @brief Select the LSE startup mode. + * @param Mode: specify the LSE startup mode. + * This parameter can be one of the following values: + * @arg RTC_LSESM_NORMAL : Little power consumption but longer startup time. + * @arg RTC_LSESM_FAST : Shortly startup time but higher power consumption. + * @retval None + ************************************************************************************************************/ +void RTC_LSESMConfig(RTC_LSESM_Enum Mode) +{ + Assert_Param(IS_RTC_LSESM(Mode)); + + HT_RTC->CR = (HT_RTC->CR & ~(1UL << 5)) | ((u32)Mode << 5); +} + +/*********************************************************************************************************//** + * @brief Enable or Disable the LSE clock. + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void RTC_LSECmd(ControlStatus NewState) +{ + Assert_Param(IS_CONTROL_STATUS(NewState)); + + if (NewState == DISABLE) + { + HT_RTC->CR &= ~(1UL << 3); + } + else + { + HT_RTC->CR |= (1UL << 3); + } +} +#endif + +/*********************************************************************************************************//** + * @brief Enable or Disable the compare match function. + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void RTC_CMPCLRCmd(ControlStatus NewState) +{ + Assert_Param(IS_CONTROL_STATUS(NewState)); + + if (NewState != DISABLE) + { + HT_RTC->CR |= (1UL << 4); + } + else + { + HT_RTC->CR &= ~(1UL << 4); + } +} + +/*********************************************************************************************************//** + * @brief Configure the RTC prescaler. + * @param Psc: Value of RTC prescaler. + * This parameter can be one of following values: + * @arg RTC_RPRE_1 + * @arg RTC_RPRE_2 + * @arg RTC_RPRE_4 + * @arg RTC_RPRE_8 + * @arg RTC_RPRE_16 + * @arg RTC_RPRE_32 + * @arg RTC_RPRE_64 + * @arg RTC_RPRE_128 + * @arg RTC_RPRE_256 + * @arg RTC_RPRE_512 + * @arg RTC_RPRE_1024 + * @arg RTC_RPRE_2048 + * @arg RTC_RPRE_4096 + * @arg RTC_RPRE_8192 + * @arg RTC_RPRE_16384 + * @arg RTC_RPRE_32768 + * @retval None + ************************************************************************************************************/ +void RTC_SetPrescaler(RTC_RPRE_Enum Psc) +{ + Assert_Param(IS_RTC_PSC(Psc)); + + HT_RTC->CR = (HT_RTC->CR & RPRE_MASK) | Psc; +} + +/*********************************************************************************************************//** + * @brief Return the RTC prescaler setting. + * @retval The prescaler value. It is powered by 2 and max.is 32768. + ************************************************************************************************************/ +u16 RTC_GetPrescaler(void) +{ + u32 prescaler; + + prescaler = HT_RTC->CR >> 8; + + return ((u16)0x1 << prescaler); +} + +/*********************************************************************************************************//** + * @brief Enable or Disable the RTC timer. + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void RTC_Cmd(ControlStatus NewState) +{ + if (NewState != DISABLE) + { + HT_RTC->CR |= (1UL); + } + else + { + HT_RTC->CR &= ~(1UL); + } +} + +/*********************************************************************************************************//** + * @brief Return the counter value. + * @retval Between 0x0 ~ 0xFFFFFFFF. + ************************************************************************************************************/ +u32 RTC_GetCounter(void) +{ + /* !!! NOTICE !!! + A 1/CK_RTC delay time is required if you read the RTC CNT count immediately when the RTC compare match + occurred (in the RTC ISR or the system is wakeup from the DeepSleep1/2). + The CK_RTC can be configured from the LSI or LSE. + */ + return (HT_RTC->CNT); +} + +/*********************************************************************************************************//** + * @brief Configure the compare match value. + * @param Compare: Between 0x0 ~ 0xFFFFFFFF + * @retval None + ************************************************************************************************************/ +void RTC_SetCompare(u32 Compare) +{ + HT_RTC->CMP = Compare; +} + +/*********************************************************************************************************//** + * @brief Return the compare match value. + * @retval Between 0x0 ~ 0xFFFFFFFF. + ************************************************************************************************************/ +u32 RTC_GetCompare(void) +{ + return (HT_RTC->CMP); +} + +/*********************************************************************************************************//** + * @brief Enable or Disable the specified wakeup source. + * @param RTC_WAKEUP Selection of Wakeup source. + * This parameter can be any combination of the following values: + * @arg RTC_WAKEUP_CSEC : Waken up by counter counting. + * @arg RTC_WAKEUP_CM : Waken up by counter compare match with CMP register. + * @arg RTC_WAKEUP_OV : Waken up by counter overflow. + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void RTC_WakeupConfig(u32 RTC_WAKEUP, ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_RTC_WAKEUP(RTC_WAKEUP)); + + if (NewState != DISABLE) + { + HT_RTC->IWEN |= RTC_WAKEUP; + } + else + { + HT_RTC->IWEN &= ~RTC_WAKEUP; + } +} + +/*********************************************************************************************************//** + * @brief Enable or Disable the specified interrupt source. + * @param RTC_INT: Selection of Wakeup source. + * This parameter can be any combination of the following values: + * @arg RTC_INT_CSEC : Assert interrupt at counter counting + * @arg RTC_INT_CM : Assert interrupt at counter compare match with CMP register + * @arg RTC_INT_OV : Assert interrupt at counter overflow + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void RTC_IntConfig(u32 RTC_INT, ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_RTC_INT(RTC_INT)); + + if (NewState != DISABLE) + { + HT_RTC->IWEN |= RTC_INT; + } + else + { + HT_RTC->IWEN &= ~RTC_INT; + } +} + +/*********************************************************************************************************//** + * @brief Return the RTC flags. + * @retval RTC_STS register value. + * This parameter can be any combination of following: + * - 0x0 : No flag set + * - 0x1 : Count flag + * - 0x2 : Match flag + * - 0x4 : Overflow flag + * @note RTC_SR is read clear. + ************************************************************************************************************/ +u8 RTC_GetFlagStatus(void) +{ + return ((u8)HT_RTC->SR); +} + +/*********************************************************************************************************//** + * @brief Configure the RTC output function. + * @param WMode: specify the RTC output waveform mode + * This parameter can be one of the following values: + * @arg RTC_ROWM_PULSE : Pulse mode + * @arg RTC_ROWM_LEVEL : Level mode + * @param EventSel: specify the RTC output event selection + * This parameter can be one of the following values: + * @arg RTC_ROES_MATCH : Compare match selected + * @arg RTC_ROES_SECOND : Second clock selected + * @param Pol: specify the RTC output active polarity + * This parameter can be one of the following values: + * @arg RTC_ROAP_HIGH : Active level is high + * @arg RTC_ROAP_LOW : Active level is low + * @note This function will disable RTC output first. + ************************************************************************************************************/ +void RTC_OutConfig(RTC_ROWM_Enum WMode, RTC_ROES_Enum EventSel, RTC_ROAP_Enum Pol) +{ + Assert_Param(IS_RTC_ROWM(WMode)); + Assert_Param(IS_RTC_ROES(EventSel)); + Assert_Param(IS_RTC_ROAP(Pol)); + + HT_RTC->CR &= ~(1UL << 16); + HT_RTC->CR = (HT_RTC->CR & ~(1UL << 18)) | ((u32)WMode << 18); + HT_RTC->CR = (HT_RTC->CR & ~(1UL << 17)) | ((u32)EventSel << 17); + HT_RTC->CR = (HT_RTC->CR & ~(1UL << 19)) | ((u32)Pol << 19); +} + +/*********************************************************************************************************//** + * @brief Enable or Disable the RTC output. + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void RTC_OutCmd(ControlStatus NewState) +{ + Assert_Param(IS_CONTROL_STATUS(NewState)); + + if (NewState != DISABLE) + { + HT_RTC->CR |= (1UL << 16); + } + else + { + HT_RTC->CR &= ~(1UL << 16); + } +} + +/*********************************************************************************************************//** + * @brief Return the RTCOUT level mode flag. + * @retval SET or RESET + * @note Reads RTC_CR action will clear ROLF flag. + ************************************************************************************************************/ +FlagStatus RTC_GetOutStatus(void) +{ + if (HT_RTC->CR & (1UL << 20)) + { + return SET; + } + else + { + return RESET; + } +} +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/ht32f5xxxx_sci.c b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/ht32f5xxxx_sci.c new file mode 100644 index 0000000000..72a4c06067 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/ht32f5xxxx_sci.c @@ -0,0 +1,446 @@ +/*********************************************************************************************************//** + * @file ht32f5xxxx_sci.c + * @version $Rev:: 6386 $ + * @date $Date:: 2022-10-27 #$ + * @brief This file provides all the SCI firmware functions. + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ + +/* Includes ------------------------------------------------------------------------------------------------*/ +#include "ht32f5xxxx_sci.h" + +/** @addtogroup HT32F5xxxx_Peripheral_Driver HT32F5xxxx Peripheral Driver + * @{ + */ + +/** @defgroup SCI SCI + * @brief SCI driver modules + * @{ + */ + + +/* Private constants ---------------------------------------------------------------------------------------*/ +/** @defgroup SCI_Private_Define SCI private definitions + * @{ + */ +/* SCI ENSCI mask */ +#define CR_ENSCI_SET ((u32)0x00000020) +#define CR_ENSCI_RESET ((u32)0xFFFFFFDF) + +/* SCI WTEN mask */ +#define CR_WTEN_SET ((u32)0x00000004) +#define CR_WTEN_RESET ((u32)0xFFFFFFFB) +/** + * @} + */ + +/* Global functions ----------------------------------------------------------------------------------------*/ +/** @defgroup SCI_Exported_Functions SCI exported functions + * @{ + */ +/*********************************************************************************************************//** + * @brief Deinitialize the SCI peripheral registers to their default reset values. + * @param SCIx: where SCIx is the selected SCI from the SCI peripherals. + * @retval None + ************************************************************************************************************/ +void SCI_DeInit(HT_SCI_TypeDef* SCIx) +{ + RSTCU_PeripReset_TypeDef RSTCUReset = {{0}}; + if (SCIx == HT_SCI0) + { + RSTCUReset.Bit.SCI0 = 1; + } + #if (LIBCFG_SCI1) + else + { + RSTCUReset.Bit.SCI1 = 1; + } + #endif + RSTCU_PeripReset(RSTCUReset, ENABLE); +} + +/*********************************************************************************************************//** + * @brief Initialize the SCI peripheral according to the specified parameters in the SCI_InitStruct. + * @param SCIx: where SCIx is the selected SCI from the SCI peripherals. + * @param SCI_InitStruct: pointer to a SCI_InitTypeDef structure. + * @retval None + ************************************************************************************************************/ +void SCI_Init(HT_SCI_TypeDef* SCIx, SCI_InitTypeDef* SCI_InitStruct) +{ + u32 tmpreg; + + /* Check the parameters */ + Assert_Param(IS_SCI_MODE(SCI_InitStruct->SCI_Mode)); + Assert_Param(IS_SCI_RETRY(SCI_InitStruct->SCI_Retry)); + Assert_Param(IS_SCI_CONVENTION(SCI_InitStruct->SCI_Convention)); + Assert_Param(IS_SCI_CARD_POLARITY(SCI_InitStruct->SCI_CardPolarity)); + Assert_Param(IS_SCI_CLOCK_PRESCALER(SCI_InitStruct->SCI_ClockPrescale)); + + + /*------------------------- SCI Control Register Configuration -------------------------------------------*/ + tmpreg = SCIx->CR; + tmpreg &= 0xFFFFFFA4; + + tmpreg |= SCI_InitStruct->SCI_Mode | SCI_InitStruct->SCI_Retry | SCI_InitStruct->SCI_Convention | + SCI_InitStruct->SCI_CardPolarity; + + SCIx->CR = tmpreg; + + /*------------------------- SCI Prescaler Register Configuration -----------------------------------------*/ + SCIx->PSC = SCI_InitStruct->SCI_ClockPrescale; +} + +/*********************************************************************************************************//** + * @brief Initialize the SCI peripheral according to the specified parameters in the SCI_InitStruct. + * @param SCI_InitStruct: pointer to a SCI_InitTypeDef structure. + * @retval None + ************************************************************************************************************/ +void SCI_StructInit(SCI_InitTypeDef* SCI_InitStruct) +{ + /* Initialize the SCI_Mode member */ + SCI_InitStruct->SCI_Mode = SCI_MODE_MANUAL; + + /* Initialize the SCI_Retry member */ + SCI_InitStruct->SCI_Retry = SCI_RETRY_NO; + + /* Initialize the SCI_Convention member */ + SCI_InitStruct->SCI_Convention = SCI_CONVENTION_DIRECT; + + /* Initialize the SCI_CardPolarity member */ + SCI_InitStruct->SCI_CardPolarity = SCI_CARDPOLARITY_LOW; + + /* Initialize the SCI_ClockPrescale member */ + SCI_InitStruct->SCI_ClockPrescale = SCI_CLKPRESCALER_1; +} + +/*********************************************************************************************************//** + * @brief Enable or Disable the specified SCI peripheral. + * @param SCIx: where SCIx is the selected SCI from the SCI peripherals. + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void SCI_Cmd(HT_SCI_TypeDef* SCIx, ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_CONTROL_STATUS(NewState)); + + if (NewState != DISABLE) + { + SCIx->CR |= CR_ENSCI_SET; + } + else + { + SCIx->CR &= CR_ENSCI_RESET; + } +} + +/*********************************************************************************************************//** + * @brief This function is used to configure the Elementary Time Unit. + * @param SCIx: where SCIx is the selected SCI from the SCI peripherals. + * @param SCI_ETU: specify the SCI Elementary Time Unit. + * @param SCI_Compensation: Enable or Disable the Compensation mode. + * This parameter can be one of the following values: + * @arg SCI_COMPENSATION_ENABLE : Compensation mode enabled + * @arg SCI_COMPENSATION_DISABLE : Compensation mode disabled + * @retval None + ************************************************************************************************************/ +void SCI_ETUConfig(HT_SCI_TypeDef* SCIx, u32 SCI_ETU, u32 SCI_Compensation) +{ + /* Check the parameters */ + Assert_Param(IS_SCI_ETU(SCI_ETU)); + Assert_Param(IS_SCI_ETU_COMPENSATION(SCI_Compensation)); + + SCIx->ETU = SCI_ETU | SCI_Compensation; +} + +/*********************************************************************************************************//** + * @brief This function is used to set the value of SCI GuardTime. + * @param SCIx: where SCIx is the selected SCI from the SCI peripherals. + * @param SCI_GuardTime: specify the value of SCI GuardTime value. + * @retval None + ************************************************************************************************************/ +void SCI_SetGuardTimeValue(HT_SCI_TypeDef* SCIx, u16 SCI_GuardTime) +{ + /* Check the parameters */ + Assert_Param(IS_SCI_GUARDTIME(SCI_GuardTime)); + + SCIx->GT = SCI_GuardTime; +} + +/*********************************************************************************************************//** + * @brief This function is used to set the value of SCI Waiting Time. + * @param SCIx: where SCIx is the selected SCI from the SCI peripherals. + * @param SCI_WaitingTime: specify the value of SCI Waiting Time value. + * @retval None + ************************************************************************************************************/ +void SCI_SetWaitingTimeValue(HT_SCI_TypeDef* SCIx, u32 SCI_WaitingTime) +{ + /* Check the parameters */ + Assert_Param(IS_SCI_WAITING_TIME(SCI_WaitingTime)); + + SCIx->WT = SCI_WaitingTime; +} + +/*********************************************************************************************************//** + * @brief Enable or Disable the Waiting Time Counter. + * @param SCIx: where SCIx is the selected SCI from the SCI peripherals. + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void SCI_WaitingTimeCounterCmd(HT_SCI_TypeDef* SCIx, ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_CONTROL_STATUS(NewState)); + + if (NewState != DISABLE) + { + SCIx->CR |= CR_WTEN_SET; + } + else + { + SCIx->CR &= CR_WTEN_RESET; + } +} + +/*********************************************************************************************************//** + * @brief Sends a data byte through the SCI peripheral. + * @param SCIx: where SCIx is the selected SCI from the SCI peripherals. + * @param SCI_Data: byte to be transmitted. + * @retval None + ************************************************************************************************************/ +void SCI_SendData(HT_SCI_TypeDef* SCIx, u8 SCI_Data) +{ + SCIx->TXB = SCI_Data; +} + +/*********************************************************************************************************//** + * @brief Returns the received data through the SCI peripheral. + * @param SCIx: where SCIx is the selected SCI from the SCI peripherals. + * @retval The value of the received data. + ************************************************************************************************************/ +u8 SCI_ReceiveData(HT_SCI_TypeDef* SCIx) +{ + return ((u8)SCIx->RXB); +} + +/*********************************************************************************************************//** + * @brief Determines the SCI output clock signal is driven by hardware or software. + * @param SCIx: where SCIx is the selected SCI from the SCI peripherals. + * @param SCI_CLKMode: specify the SCI clock pin mode. + * This parameter can be one of the following values: + * @arg SCI_CLK_SOFTWARE : SCI output clock is controlled by software + * @arg SCI_CLK_HARDWARE : SCI output clock is controlled by hardware + * @retval None + ************************************************************************************************************/ +void SCI_ClockModeConfig(HT_SCI_TypeDef* SCIx, u32 SCI_CLKMode) +{ + /* Check the parameters */ + Assert_Param(IS_SCI_CLK_MODE(SCI_CLKMode)); + + if (SCI_CLKMode != SCI_CLK_SOFTWARE) + { + SCIx->CCR |= SCI_CLK_HARDWARE; + } + else + { + SCIx->CCR &= SCI_CLK_SOFTWARE; + } +} + +/*********************************************************************************************************//** + * @brief Output the SCI clock pin low or high by software. + * @param SCIx: where SCIx is the selected SCI from the SCI peripherals. + * @param SCI_CLK: specify if the SCI clock pin to be high or low. + * This parameter can be one of the following values: + * @arg SCI_CLK_HIGH : Software drive SCI output clock high + * @arg SCI_CLK_LOW : Software drive SCI output clock low + * @retval None + ************************************************************************************************************/ +void SCI_SoftwareClockCmd(HT_SCI_TypeDef* SCIx, u32 SCI_CLK) +{ + /* Check the parameters */ + Assert_Param(IS_SCI_CLK(SCI_CLK)); + + if (SCI_CLK != SCI_CLK_LOW) + { + SCIx->CCR |= SCI_CLK_HIGH; + } + else + { + SCIx->CCR &= SCI_CLK_LOW; + } +} + +/*********************************************************************************************************//** + * @brief Output the SCI DIO pin low or high by software. + * @param SCIx: where SCIx is the selected SCI from the SCI peripherals. + * @param SCI_DIO: specify if the SCI DIO pin to be high or low. + * This parameter can be one of the following values: + * @arg SCI_DIO_HIGH : Drive SCI DIO signal high + * @arg SCI_DIO_LOW : Drive SCI DIO signal low + * @retval None + ************************************************************************************************************/ +void SCI_OutputDIO(HT_SCI_TypeDef* SCIx, u32 SCI_DIO) +{ + /* Check the parameters */ + Assert_Param(IS_SCI_DIO(SCI_DIO)); + + if (SCI_DIO != SCI_DIO_LOW) + { + SCIx->CCR |= SCI_DIO_HIGH; + } + else + { + SCIx->CCR &= SCI_DIO_LOW; + } +} + +/*********************************************************************************************************//** + * @brief Enable or Disable the specified SCI interrupt. + * @param SCIx: where SCIx is the selected SCI from the SCI peripherals. + * @param SCI_Int: specify the SCI interrupt source to be enabled or disable. + * This parameter can be any combination of the following values: + * @arg SCI_INT_PAR : SCI parity error interrupt + * @arg SCI_INT_RXC : SCI received character interrupt + * @arg SCI_INT_TXC : SCI transmitted character interrupt + * @arg SCI_INT_WT : SCI waiting timer interrupt + * @arg SCI_INT_CARD : SCI card insert/remove interrupt + * @arg SCI_INT_TXBE : SCI transmit buffer empty interrupt + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void SCI_IntConfig(HT_SCI_TypeDef* SCIx, u32 SCI_Int, ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_SCI_INT(SCI_Int)); + Assert_Param(IS_CONTROL_STATUS(NewState)); + + if (NewState != DISABLE) + { + SCIx->IER |= SCI_Int; + } + else + { + SCIx->IER &= ~SCI_Int; + } +} + +/*********************************************************************************************************//** + * @brief Get the status of specified SCI flag. + * @param SCIx: where SCIx is the selected SCI from the SCI peripherals. + * @param SCI_Flag: specify the flag that is to be check. + * This parameter can be one of the following values: + * @arg SCI_FLAG_PAR : SCI parity error flag + * @arg SCI_FLAG_RXC : SCI received character flag + * @arg SCI_FLAG_TXC : SCI transmitted character flag + * @arg SCI_FLAG_WT : SCI waiting timer flag + * @arg SCI_FLAG_CARD : SCI card insert/remove flag + * @arg SCI_FLAG_TXBE : SCI transmit buffer empty flag + * @retval SET or RESET + ************************************************************************************************************/ +FlagStatus SCI_GetFlagStatus(HT_SCI_TypeDef* SCIx, u32 SCI_Flag) +{ + u32 statusreg = 0; + FlagStatus bitstatus = RESET; + + /* Check the parameters */ + Assert_Param(IS_SCI_FLAG(SCI_Flag)); + + statusreg = SCIx->SR; + + if ((statusreg & SCI_Flag) != (u32)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + return bitstatus; +} + +/*********************************************************************************************************//** + * @brief Clears the flag status of specified SCI flag. + * @param SCIx: where SCIx is the selected SCI from the SCI peripherals. + * @param SCI_Flag: specify the flag to be cleared. + * This parameter can be one of the following values: + * @arg SCI_FLAG_PAR : SCI parity error flag + * @arg SCI_FLAG_TXC : SCI transmitted character flag + * @arg SCI_FLAG_WT : SCI waiting timer flag + * @retval None + ************************************************************************************************************/ +void SCI_ClearFlag(HT_SCI_TypeDef* SCIx, u32 SCI_Flag) +{ + /* Check the parameters */ + Assert_Param(IS_SCI_CLEAR_FLAG(SCI_Flag)); + + if (SCI_Flag != SCI_FLAG_WT) + { + SCIx->SR &= ~SCI_Flag; + } + else + { + SCIx->CR &= CR_WTEN_RESET; + SCIx->CR |= CR_WTEN_SET; + } +} + +#if (LIBCFG_PDMA) +/*********************************************************************************************************//** + * @brief Enable or disables the SCI PDMA interface. + * @param SCIx: where SCIx is the selected SCI from the SCI peripherals. + * @param SCI_PDMAREQ: specify the SCI PDMA transfer request to be enabled or disabled. + * This parameter can be any combination of the following values: + * @arg SCI_PDMAREQ_TX : Tx PDMA transfer request + * @arg SCI_PDMAREQ_RX : Rx PDMA transfer request + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void SCI_PDMACmd(HT_SCI_TypeDef* SCIx, u32 SCI_PDMAREQ, ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_SCI_PDMA_REQ(SCI_PDMAREQ)); + Assert_Param(IS_CONTROL_STATUS(NewState)); + + if (NewState != DISABLE) + { + SCIx->CR |= SCI_PDMAREQ; + } + else + { + SCIx->CR &= ~SCI_PDMAREQ; + } +} +#endif +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/ht32f5xxxx_sctm.c b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/ht32f5xxxx_sctm.c new file mode 100644 index 0000000000..b824c72b16 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/ht32f5xxxx_sctm.c @@ -0,0 +1,2 @@ +The SCTM, PWM, GPTM, and MCTM timer have similar architecture. They use the same driver, +"ht32fxxxxx_tm.c/.h" to save the code size. For those timers, please refet to the TM driver/example. diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/ht32f5xxxx_sled.c b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/ht32f5xxxx_sled.c new file mode 100644 index 0000000000..132db84be4 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/ht32f5xxxx_sled.c @@ -0,0 +1,289 @@ +/*********************************************************************************************************//** + * @file ht32f5xxxx_sled.c + * @version $Rev:: 3309 $ + * @date $Date:: 2018-12-12 #$ + * @brief This file provides all the SLED firmware functions. + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ + +/* Includes ------------------------------------------------------------------------------------------------*/ +#include "ht32f5xxxx_sled.h" + +/** @addtogroup HT32F5xxxx_Peripheral_Driver HT32F5xxxx Peripheral Driver + * @{ + */ + +/** @defgroup SLED SLED + * @brief SLED driver modules + * @{ + */ + + +/* Global functions ----------------------------------------------------------------------------------------*/ +/** @defgroup SLED_Exported_Functions SLED exported functions + * @{ + */ +/*********************************************************************************************************//** + * @brief Deinitialize the specified SLED peripheral registers to their default reset values. + * @param SLEDx: where SLEDx is the selected SLED from the SLED peripherals. + * @retval None + ************************************************************************************************************/ +void SLED_DeInit(HT_SLED_TypeDef* SLEDx) +{ + RSTCU_PeripReset_TypeDef RSTCUReset = {{0}}; + + /* Check the parameters */ + Assert_Param(IS_SLED(SLEDx)); + + if (SLEDx == HT_SLED0) + { + RSTCUReset.Bit.SLED0 = 1; + } + #if(LIBCFG_SLED1) + else if (SLEDx == HT_SLED1) + { + RSTCUReset.Bit.SLED1 = 1; + } + #endif + + RSTCU_PeripReset(RSTCUReset, ENABLE); +} + +/*********************************************************************************************************//** + * @brief Initialize the specified SLED peripheral according to the specified parameters in the SLED_InitStruct. + * @param SLEDx: where SLEDx is the selected SLED from the SLED peripherals. + * @param SLED_InitStruct: pointer to a SLED_InitTypeDef structure. + * @retval None + ************************************************************************************************************/ +void SLED_Init(HT_SLED_TypeDef* SLEDx, SLED_InitTypeDef* SLED_InitStruct) +{ + /* Check the parameters */ + Assert_Param(IS_SLED(SLEDx)); + + SLEDx->CDR = (SLED_InitStruct->BaudRate << 8) + | (SLED_InitStruct->ClockPrescaler << 0); + + SLEDx->TCR = (SLED_InitStruct->TRST << 16) + | (SLED_InitStruct->T1H << 8) + | (SLED_InitStruct->T0H << 0); + + SLEDx->CR = (SLED_InitStruct->SyncState << 10) + | (SLED_InitStruct->IdleState << 9) + | (SLED_InitStruct->ResetState << 8) + | (SLED_InitStruct->SyncMode << 3) + | (SLED_InitStruct->OutputPolarity << 2); +} + +/*********************************************************************************************************//** + * @brief Enable or Disable the specified SLED peripheral. + * @param SLEDx: where SLEDx is the selected SLED from the SLED peripherals. + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void SLED_Cmd(HT_SLED_TypeDef* SLEDx, ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_SLED(SLEDx)); + Assert_Param(IS_CONTROL_STATUS(NewState)); + + if (NewState != DISABLE) + { + SLEDx->CR |= (1 << 0); + } + else + { + SLEDx->CR &= ~(1 << 0); + } +} + +/*********************************************************************************************************//** + * @brief Enable or Disable the specified SLED output. + * @param SLEDx: where SLEDx is the selected SLED from the SLED peripherals. + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void SLED_OutputCmd(HT_SLED_TypeDef* SLEDx, ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_SLED(SLEDx)); + Assert_Param(IS_CONTROL_STATUS(NewState)); + + if (NewState != DISABLE) + { + SLEDx->CR |= (1 << 1); + } + else + { + SLEDx->CR &= ~(1 << 1); + } +} + +/*********************************************************************************************************//** + * @brief Enable or Disable the specified SLED PDMA request. + * @param SLEDx: where SLEDx is the selected SLED from the SLED peripherals. + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void SLED_PDMACmd(HT_SLED_TypeDef* SLEDx, ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_SLED(SLEDx)); + Assert_Param(IS_CONTROL_STATUS(NewState)); + + if (NewState != DISABLE) + { + SLEDx->CR |= (1 << 4); + } + else + { + SLEDx->CR &= ~(1 << 4); + } +} + +/*********************************************************************************************************//** + * @brief Enable or Disable the specified SLED interrupt. + * @param SLEDx: where SLEDx is the selected SLED from the SLED peripherals. + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void SLED_IntCmd(HT_SLED_TypeDef* SLEDx, ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_SLED(SLEDx)); + Assert_Param(IS_CONTROL_STATUS(NewState)); + + if (NewState != DISABLE) + { + SLEDx->CR |= (1 << 5); + } + else + { + SLEDx->CR &= ~(1 << 5); + } +} + +/*********************************************************************************************************//** + * @brief Clear the specified SLED interrupt flag. + * @param SLEDx: where SLEDx is the selected SLED from the SLED peripherals. + * @retval None + ************************************************************************************************************/ +void SLED_ClearIntFlag(HT_SLED_TypeDef* SLEDx) +{ + /* Check the parameters */ + Assert_Param(IS_SLED(SLEDx)); + + SLEDx->SR |= (1 << 5); +} + +/*********************************************************************************************************//** + * @brief Insert a Reset Code on the specified SLED. + * @param SLEDx: where SLEDx is the selected SLED from the SLED peripherals. + * @retval None + ************************************************************************************************************/ +void SLED_InsertResetCode(HT_SLED_TypeDef* SLEDx) +{ + /* Check the parameters */ + Assert_Param(IS_SLED(SLEDx)); + + SLEDx->CR |= (1 << 15); +} + +/*********************************************************************************************************//** + * @brief Return the FIFO status of the specified SLED. + * @param SLEDx: where SLEDx is the selected SLED from the SLED peripherals. + * @retval SET or RESET + ************************************************************************************************************/ +FlagStatus SLED_GetResetCodeStatus(HT_SLED_TypeDef* SLEDx) +{ + if ((SLEDx->CR & (1 << 15)) != RESET) + return SET; + else + return RESET; +} + +/*********************************************************************************************************//** + * @brief Return the BUSY status of the specified SLED. + * @param SLEDx: where SLEDx is the selected SLED from the SLED peripherals. + * @retval SET or RESET + ************************************************************************************************************/ +FlagStatus SLED_GetBusyStatus(HT_SLED_TypeDef* SLEDx) +{ + if (SLEDx->SR & 1) + return SET; + else + return RESET; +} + +/*********************************************************************************************************//** + * @brief Set the specified SLED FIFO trigger level. + * @param SLEDx: where SLEDx is the selected SLED from the SLED peripherals. + * @param FifoLevel: specify the FIFO trigger level. + * This parameter can be one of the following values: + * @arg SLED_FIFO_LEVEL_0 : data request will be inserted when FIFO data count is equal to 0 + * @arg SLED_FIFO_LEVEL_1 : data request will be inserted when FIFO data count is less than or equal to 1 + * @arg SLED_FIFO_LEVEL_2 : data request will be inserted when FIFO data count is less than or equal to 2 + * @arg SLED_FIFO_LEVEL_3 : data request will be inserted when FIFO data count is less than or equal to 3 + * @retval None + ************************************************************************************************************/ +void SLED_FIFOTrigLevelConfig(HT_SLED_TypeDef* SLEDx, u8 FifoLevel) +{ + /* Check the parameters */ + Assert_Param(IS_SLED(SLEDx)); + Assert_Param(IS_SLED_FIFO_LEVEL(FifoLevel)); + + SLEDx->FCR = FifoLevel; +} + +/*********************************************************************************************************//** + * @brief Return the FIFO status of the specified SLED. + * @param SLEDx: where SLEDx is the selected SLED from the SLED peripherals. + * @retval The number of data in FIFO. + ************************************************************************************************************/ +u8 SLED_GetFIFOStatus(HT_SLED_TypeDef* SLEDx) +{ + return (SLEDx->FCR >> 24); +} + +/*********************************************************************************************************//** + * @brief Reset the specified SLED FIFO. + * @param SLEDx: where SLEDx is the selected SLED from the SLED peripherals. + * @retval None + ************************************************************************************************************/ +void SLED_FIFOReset(HT_SLED_TypeDef* SLEDx) +{ + /* Check the parameters */ + Assert_Param(IS_SLED(SLEDx)); + + SLEDx->FCR |= (1 << 0); +} +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/ht32f5xxxx_spi.c b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/ht32f5xxxx_spi.c new file mode 100644 index 0000000000..5515859641 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/ht32f5xxxx_spi.c @@ -0,0 +1,712 @@ +/*********************************************************************************************************//** + * @file ht32f5xxxx_spi.c + * @version $Rev:: 7322 $ + * @date $Date:: 2023-10-28 #$ + * @brief This file provides all the SPI firmware functions. + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ + +/* Includes ------------------------------------------------------------------------------------------------*/ +#include "ht32f5xxxx_spi.h" + +/** @addtogroup HT32F5xxxx_Peripheral_Driver HT32F5xxxx Peripheral Driver + * @{ + */ + +/** @defgroup SPI SPI + * @brief SPI driver modules + * @{ + */ + + +#if (LIBCFG_MIDI) +#include "ht32f5xxxx_spi_midi.c" +#endif + +/* Private constants ---------------------------------------------------------------------------------------*/ +/** @defgroup SPI_Private_Define SPI private definitions + * @{ + */ +/* SPI SPIEN Mask */ +#define CR0_SPIEN_SET (u32)0x00000001 +#define CR0_SPIEN_RESET (u32)0xFFFFFFFE + +/* SPI SELOEN Mask */ +#define CR0_SELOEN_SET (u32)0x00000008 +#define CR0_SELOEN_RESET (u32)0xFFFFFFF7 + +/* SPI SPI DUALEN Mask */ +#define CR0_DUALEN_SET (u32)0x00000040 +#define CR0_DUALEN_RESET (u32)0xFFFFFFBF + +#if (LIBCFG_QSPI) +/* QSPI QUADEN Mask */ +#define CR0_QUADEN_SET (u32)0x00020000 +#define CR0_QUADEN_RESET (u32)0xFFFDFFFF +/* QSPI QDIODIR Mask */ +#define CR0_QDIODIR_OUT (u32)0x00010000 +#define CR0_QDIODIR_IN (u32)0xFFFEFFFF +#endif + +/* SPI SPI GUADTEN Mask */ +#define CR0_GUADTEN_SET (u32)0x00000080 +#define CR0_GUADTEN_RESET (u32)0xFFFFFF7F + +/* SPI FIFOEN Mask */ +#define FCR_FIFOEN_SET (u32)0x00000400 +#define FCR_FIFOEN_RESET (u32)0xFFFFFBFF + +/* SPI DFL Mask */ +#if (LIBCFG_SPI_DATA_LENGTH_V01) +#define CR1_DFL_MASK (u32)0x00000007 +#else +#define CR1_DFL_MASK (u32)0x0000000F +#endif + +/* SPI FIFO Mask */ +#if (LIBCFG_SPI_FIFO_DEPTH_V01) +#define FCR_FIFO_MASK (u32)0x00000007 +#else +#define FCR_FIFO_MASK (u32)0x0000000F +#endif + +/** + * @} + */ + + +/* Global functions ----------------------------------------------------------------------------------------*/ +/** @defgroup SPI_Exported_Functions SPI exported functions + * @{ + */ +/*********************************************************************************************************//** + * @brief Deinitialize the SPI peripheral registers to their default reset values. + * @param SPIx: where SPIx is the selected SPI from the SPI peripherals. + * @retval None + ************************************************************************************************************/ +void SPI_DeInit(HT_SPI_TypeDef* SPIx) +{ + RSTCU_PeripReset_TypeDef RSTCUReset = {{0}}; + + /* Check the parameters */ + Assert_Param(IS_SPI(SPIx)); + + if (SPIx == HT_SPI0) + { + RSTCUReset.Bit.SPI0 = 1; + } + #if (LIBCFG_SPI1) + else if (SPIx == HT_SPI1) + { + RSTCUReset.Bit.SPI1 = 1; + } + #endif + #if (LIBCFG_QSPI) + else if (SPIx == HT_QSPI) + { + RSTCUReset.Bit.QSPI = 1; + } + #endif + RSTCU_PeripReset(RSTCUReset, ENABLE); +} + +/*********************************************************************************************************//** + * @brief Initialize the SPIx peripheral according to the specified parameters in the SPI_InitStruct. + * @param SPIx: where SPIx is the selected SPI from the SPI peripherals. + * @param SPI_InitStruct: pointer to a SPI_InitTypeDef structure. + * @retval None + ************************************************************************************************************/ +void SPI_Init(HT_SPI_TypeDef* SPIx, SPI_InitTypeDef* SPI_InitStruct) +{ + u32 tmp; + + /* Check the parameters */ + Assert_Param(IS_SPI(SPIx)); + Assert_Param(IS_SPI_MODE(SPI_InitStruct->SPI_Mode)); + Assert_Param(IS_SPI_FIFO_SET(SPI_InitStruct->SPI_FIFO)); + Assert_Param(IS_SPI_DATALENGTH(SPI_InitStruct->SPI_DataLength)); + Assert_Param(IS_SPI_SEL_MODE(SPI_InitStruct->SPI_SELMode)); + Assert_Param(IS_SPI_SEL_POLARITY(SPI_InitStruct->SPI_SELPolarity)); + Assert_Param(IS_SPI_CPOL(SPI_InitStruct->SPI_CPOL)); + Assert_Param(IS_SPI_CPHA(SPI_InitStruct->SPI_CPHA)); + Assert_Param(IS_SPI_FIRST_BIT(SPI_InitStruct->SPI_FirstBit)); + Assert_Param(IS_SPI_FIFO_LEVEL(SPI_InitStruct->SPI_RxFIFOTriggerLevel)); + Assert_Param(IS_SPI_FIFO_LEVEL(SPI_InitStruct->SPI_TxFIFOTriggerLevel)); + Assert_Param(IS_SPI_CLOCK_PRESCALER(SPI_InitStruct->SPI_ClockPrescaler)); + + /*---------------------------- SPIx Control Register 2 Configuration -------------------------------------*/ + tmp = SPI_InitStruct->SPI_CPOL; + if (tmp == SPI_CPOL_LOW) + { + tmp |= (0x100 << SPI_InitStruct->SPI_CPHA); + } + else + { + tmp |= (0x200 >> SPI_InitStruct->SPI_CPHA); + } + + SPIx->CR1 = SPI_InitStruct->SPI_Mode | SPI_InitStruct->SPI_DataLength | + SPI_InitStruct->SPI_SELMode | SPI_InitStruct->SPI_SELPolarity | + SPI_InitStruct->SPI_FirstBit | tmp; + + /*---------------------------- SPIx FIFO Control Register Configuration ----------------------------------*/ + SPIx->FCR = SPI_InitStruct->SPI_FIFO | SPI_InitStruct->SPI_TxFIFOTriggerLevel | + (SPI_InitStruct->SPI_RxFIFOTriggerLevel << 4); + + /*---------------------------- SPIx Clock Prescaler Register Configuration -------------------------------*/ + #if (LIBCFG_SPI_CLK_PRE_V01) + SPIx->CPR = (SPI_InitStruct->SPI_ClockPrescaler - 1); + #else + SPIx->CPR = (SPI_InitStruct->SPI_ClockPrescaler / 2) - 1; + #endif +} + +/*********************************************************************************************************//** + * @brief Fill each SPI_InitStruct member with its default value. + * @param SPI_InitStruct: pointer to an SPI_InitTypeDef structure. + * @retval None + ************************************************************************************************************/ +void SPI_StructInit(SPI_InitTypeDef* SPI_InitStruct) +{ + /* Initialize the SPI_Mode member */ + SPI_InitStruct->SPI_Mode = SPI_SLAVE; + + /* Initialize the SPI_FIFO member */ + SPI_InitStruct->SPI_FIFO = SPI_FIFO_DISABLE; + + /* Initialize the SPI_DataLength member */ + #if (LIBCFG_SPI_DATA_LENGTH_V01) + SPI_InitStruct->SPI_DataLength = SPI_DATALENGTH_8; + #else + SPI_InitStruct->SPI_DataLength = SPI_DATALENGTH_16; + #endif + + /* Initialize the SPI_SELMode member */ + SPI_InitStruct->SPI_SELMode = SPI_SEL_SOFTWARE; + + /* Initialize the SPI_SELPolarity member */ + SPI_InitStruct->SPI_SELPolarity = SPI_SELPOLARITY_LOW; + + /* Initialize the SPI_CPOL member */ + SPI_InitStruct->SPI_CPOL = SPI_CPOL_LOW; + + /* Initialize the SPI_CPHA member */ + SPI_InitStruct->SPI_CPHA = SPI_CPHA_FIRST; + + /* Initialize the SPI_FirstBit member */ + SPI_InitStruct->SPI_FirstBit = SPI_FIRSTBIT_MSB; + + /* Initialize the SPI_RxFIFOTriggerLevel member */ + SPI_InitStruct->SPI_RxFIFOTriggerLevel = 0; + + /* Initialize the SPI_TxFIFOTriggerLevel member */ + SPI_InitStruct->SPI_TxFIFOTriggerLevel = 0; + + /* Initialize the SPI_ClockPrescaler member */ + SPI_InitStruct->SPI_ClockPrescaler = 2; +} + +/*********************************************************************************************************//** + * @brief Enable or Disable the specified SPI peripheral. + * @param SPIx: where SPIx is the selected SPI from the SPI peripherals. + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void SPI_Cmd(HT_SPI_TypeDef* SPIx, ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_SPI(SPIx)); + Assert_Param(IS_CONTROL_STATUS(NewState)); + + if (NewState != DISABLE) + { + /* Enable the selected SPI peripheral */ + SPIx->CR0 |= CR0_SPIEN_SET; + } + else + { + /* Disable the selected SPI peripheral */ + SPIx->CR0 &= CR0_SPIEN_RESET; + } +} + +#if (!LIBCFG_SPI_NO_MULTI_MASTER) +/*********************************************************************************************************//** + * @brief Enable or Disable the SEL output for the specified SPI peripheral. + * @param SPIx: where SPIx is the selected SPI from the SPI peripherals. + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void SPI_SELOutputCmd(HT_SPI_TypeDef* SPIx, ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_SPI(SPIx)); + Assert_Param(IS_CONTROL_STATUS(NewState)); + + if (NewState != DISABLE) + { + SPIx->CR0 |= CR0_SELOEN_SET; + } + else + { + SPIx->CR0 &= CR0_SELOEN_RESET; + } +} +#endif + +/*********************************************************************************************************//** + * @brief Enable or Disable SPI FIFO. + * @param SPIx: where SPIx is the selected SPI from the SPI peripherals. + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void SPI_FIFOCmd(HT_SPI_TypeDef* SPIx, ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_SPI(SPIx)); + Assert_Param(IS_CONTROL_STATUS(NewState)); + + if (NewState != DISABLE) + { + SPIx->FCR |= FCR_FIFOEN_SET; + } + else + { + SPIx->FCR &= FCR_FIFOEN_RESET; + } +} + +/*********************************************************************************************************//** + * @brief Configure the data length for the selected SPI. + * @param SPIx: where SPIx is the selected SPI from the SPI peripherals. + * @param SPI_DataLength: specify data length of the SPI. + * @retval None + ************************************************************************************************************/ +void SPI_SetDataLength(HT_SPI_TypeDef* SPIx, u16 SPI_DataLength) +{ + /* Check the parameters */ + Assert_Param(IS_SPI(SPIx)); + Assert_Param(IS_SPI_DATALENGTH(SPI_DataLength)); + + /* Clear DFL[x:0] in CR1. + if Datalength is 16-bit mode, then x = 3 + if Datalength is 8-bit mode, then x = 2 */ + SPIx->CR1 &= (u32)~CR1_DFL_MASK; + + /* Set new DFL[x:0] in CR1. + if Datalength is 16-bit mode, then x = 3 + if Datalength is 8-bit mode, then x = 2 */ + SPIx->CR1 |= SPI_DataLength; +} + +/*********************************************************************************************************//** + * @brief SEL pin is configured to be driven by hardware or software. + * @param SPIx: where SPIx is the selected SPI from the SPI peripherals. + * @param SPI_SEL: specify the SPI SEL pin mode. + * This parameter can be one of the following values: + * @arg SPI_SEL_HARDWARE : SEL is driven by hardware + * @arg SPI_SEL_SOFTWARE : SEL is driven by software + * @retval None + ************************************************************************************************************/ +void SPI_SELModeConfig(HT_SPI_TypeDef* SPIx, u32 SPI_SEL) +{ + /* Check the parameters */ + Assert_Param(IS_SPI(SPIx)); + Assert_Param(IS_SPI_SEL_MODE(SPI_SEL)); + + if (SPI_SEL != SPI_SEL_SOFTWARE) + { + SPIx->CR1 |= SPI_SEL_HARDWARE; + } + else + { + SPIx->CR1 &= ~SPI_SEL_HARDWARE; + } +} + +/*********************************************************************************************************//** + * @brief Configure the SEL state by software. + * @param SPIx: where SPIx is the selected SPI from the SPI peripherals. + * @param SPI_SoftwareSEL: specify if the SPI SEL to be active or inactive. + * This parameter can be one of the following values: + * @arg SPI_SEL_ACTIVE : activate SEL signal + * @arg SPI_SEL_INACTIVE : deactivate SEL signal + * @retval None + ************************************************************************************************************/ +void SPI_SoftwareSELCmd(HT_SPI_TypeDef* SPIx, u32 SPI_SoftwareSEL) +{ + /* Check the parameters */ + Assert_Param(IS_SPI(SPIx)); + Assert_Param(IS_SPI_SOFTWARE_SEL(SPI_SoftwareSEL)); + + if (SPI_SoftwareSEL != SPI_SEL_INACTIVE) + { + SPIx->CR0 |= SPI_SEL_ACTIVE; + } + else + { + SPIx->CR0 &= SPI_SEL_INACTIVE; + } +} + +/*********************************************************************************************************//** + * @brief Send a data through the SPIx peripheral. + * @param SPIx: where SPIx is the selected SPI from the SPI peripherals. + * @param SPI_Data: the data to be transmitted. + * @retval None + ************************************************************************************************************/ +void SPI_SendData(HT_SPI_TypeDef* SPIx, SPI_DataTypeDef SPI_Data) +{ + /* Check the parameters */ + Assert_Param(IS_SPI(SPIx)); + Assert_Param(IS_SPI_DATA(SPI_Data)); + + SPIx->DR = SPI_Data; +} + +/*********************************************************************************************************//** + * @brief Return the received data through the SPIx peripheral + * @param SPIx: where SPIx is the selected SPI from the SPI peripherals. + * @retval The value of the received data. + ************************************************************************************************************/ +SPI_DataTypeDef SPI_ReceiveData(HT_SPI_TypeDef* SPIx) +{ + /* Check the parameters */ + Assert_Param(IS_SPI(SPIx)); + + return (SPI_DataTypeDef)SPIx->DR; +} + +/*********************************************************************************************************//** + * @brief Set the value of SPI FIFO Time Out. + * @param SPIx: where SPIx is the selected SPI from the SPI peripherals. + * @param SPI_Timeout: specify the value of Time Out. + * @retval None + ************************************************************************************************************/ +void SPI_SetTimeOutValue(HT_SPI_TypeDef* SPIx, SPI_TimeoutTypeDef SPI_Timeout) +{ + /* Check the parameters */ + Assert_Param(IS_SPI(SPIx)); + + SPIx->FTOCR = SPI_Timeout; +} + +/*********************************************************************************************************//** + * @brief Enable or Disable the specified SPI interrupt. + * @param SPIx: where SPIx is the selected SPI from the SPI peripherals. + * @param SPI_Int: specify if the SPI interrupt source to be enabled or disabled. + * This parameter can be any combination of the following values: + * @arg SPI_INT_TXBE : SPI Tx buffer empty interrupt + * @arg SPI_INT_TXE : SPI Tx empty interrupt + * @arg SPI_INT_RXBNE : SPI Rx buffer not empty interrupt + * @arg SPI_INT_WC : SPI write collision interrupt + * @arg SPI_INT_RO : SPI read overrun interrupt + * @arg SPI_INT_MF : SPI mode fault interrupt + * @arg SPI_INT_SA : SPI slave abort interrupt + * @arg SPI_INT_TO : SPI time out interrupt + * @arg SPI_INT_ALL : All SPI interrupt + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void SPI_IntConfig(HT_SPI_TypeDef* SPIx, u32 SPI_Int, ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_SPI(SPIx)); + Assert_Param(IS_SPI_INT(SPI_Int)); + Assert_Param(IS_CONTROL_STATUS(NewState)); + + if (NewState != DISABLE) + { + SPIx->IER |= SPI_Int; + } + else + { + SPIx->IER &= (u32)~SPI_Int; + } +} + +/*********************************************************************************************************//** + * @brief Check whether the specified SPI flag has been set or not. + * @param SPIx: where SPIx is the selected SPI from the SPI peripherals. + * @param SPI_Flag: specify the flag that is to be check. + * This parameter can be one of the following values: + * @arg SPI_FLAG_TXBE : SPI Tx buffer empty flag + * @arg SPI_FLAG_TXE : SPI Tx empty flag + * @arg SPI_FLAG_RXBNE : SPI Rx buffer not empty flag + * @arg SPI_FLAG_WC : SPI write collision flag + * @arg SPI_FLAG_RO : SPI read overrun flag + * @arg SPI_FLAG_MF : SPI mode fault flag + * @arg SPI_FLAG_SA : SPI slave abort flag + * @arg SPI_FLAG_TOUT : SPI time out flag + * @arg SPI_FLAG_BUSY : SPI busy flag + * @retval SET or RESET + ************************************************************************************************************/ +FlagStatus SPI_GetFlagStatus(HT_SPI_TypeDef* SPIx, u32 SPI_Flag) +{ + FlagStatus bitstatus = RESET; + u32 statusreg = 0; + + /* Check the parameters */ + Assert_Param(IS_SPI(SPIx)); + Assert_Param(IS_SPI_FLAG(SPI_Flag)); + + statusreg = SPIx->SR; + + if ((statusreg & SPI_Flag) != (u32)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + return bitstatus; +} + +/*********************************************************************************************************//** + * @brief Return the status of specified SPI FIFO. + * @param SPIx: where SPIx is the selected SPI from the SPI peripherals. + * @param SPI_FIFODirection: specify the FIFO that is to be checked. + * This parameter can be one of the following values: + * @arg SPI_FIFO_TX : + * @arg SPI_FIFO_RX : + * @retval The number of data in Tx FIFO or Rx FIFO. + ************************************************************************************************************/ +u8 SPI_GetFIFOStatus(HT_SPI_TypeDef* SPIx, u32 SPI_FIFODirection) +{ + u32 tmpreg; + + /* Check the parameters */ + Assert_Param(IS_SPI(SPIx)); + Assert_Param(IS_SPI_FIFO_DIRECTION(SPI_FIFODirection)); + + if (SPI_FIFODirection == SPI_FIFO_TX) + { + tmpreg = SPIx->FSR & FCR_FIFO_MASK; + } + else + { + tmpreg = (SPIx->FSR & (FCR_FIFO_MASK << 4)) >> 4; + } + + return (u8)tmpreg; +} + +/*********************************************************************************************************//** + * @brief Clear the specified SPI flag. + * @param SPIx: where SPIx is the selected SPI from the SPI peripherals. + * @param SPI_Flag: specify the flag that is to be cleared. + * This parameter can be one of the following values: + * @arg SPI_FLAG_WC : SPI write collision flag + * @arg SPI_FLAG_RO : SPI read overrun flag + * @arg SPI_FLAG_MF : SPI mode fault flag + * @arg SPI_FLAG_SA : SPI slave abort flag + * @arg SPI_FLAG_TOUT : SPI time out flag + * @retval None + ************************************************************************************************************/ +void SPI_ClearFlag(HT_SPI_TypeDef* SPIx, u32 SPI_Flag) +{ + /* Check the parameters */ + Assert_Param(IS_SPI(SPIx)); + Assert_Param(IS_SPI_FLAG_CLEAR(SPI_Flag)); + + SPIx->SR = SPI_Flag; +} + +/*********************************************************************************************************//** + * @brief Set the trigger level of SPI FIFO. + * @param SPIx: where SPIx is the selected SPI from the SPI peripherals. + * @param SPI_FIFODirection: specify the FIFO that is to be set. + * This parameter can be one of the following values: + * @arg SPI_FIFO_TX : + * @arg SPI_FIFO_RX : + * @param SPI_FIFOLevel: Specify the FIFO trigger level. + * @retval None + ************************************************************************************************************/ +void SPI_FIFOTriggerLevelConfig(HT_SPI_TypeDef* SPIx, u32 SPI_FIFODirection, u8 SPI_FIFOLevel) +{ + /* Check the parameters */ + Assert_Param(IS_SPI(SPIx)); + Assert_Param(IS_SPI_FIFO_DIRECTION(SPI_FIFODirection)); + Assert_Param(IS_SPI_FIFO_LEVEL(SPI_FIFOLevel)); + + if (SPI_FIFODirection == SPI_FIFO_TX) + { + SPIx->FCR = ((SPIx->FCR & (0x00000400 | (FCR_FIFO_MASK << 4))) | SPI_FIFOLevel); + } + else + { + SPIx->FCR = ((SPIx->FCR & (0x00000400 | FCR_FIFO_MASK)) | (SPI_FIFOLevel << 4)); + } +} + +#if (LIBCFG_PDMA) +/*********************************************************************************************************//** + * @brief Enable or Disable the SPIx PDMA interface. + * @param SPIx: where SPIx is the selected SPI from the SPI peripherals. + * @param SPI_PDMAREQ: specify the SPI PDMA transfer request to be enabled or disabled. + * This parameter can be any combination of the following values: + * @arg SPI_PDMAREQ_TX : Tx PDMA transfer request + * @arg SPI_PDMAREQ_RX : Rx PDMA transfer request + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void SPI_PDMACmd(HT_SPI_TypeDef* SPIx, u32 SPI_PDMAREQ, ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_SPI(SPIx)); + Assert_Param(IS_SPI_PDMA_REQ(SPI_PDMAREQ)); + Assert_Param(IS_CONTROL_STATUS(NewState)); + + if (NewState != DISABLE) + { + SPIx->CR0 |= SPI_PDMAREQ; + } + else + { + SPIx->CR0 &= ~SPI_PDMAREQ; + } +} +#endif + +#if (!LIBCFG_SPI_NO_DUAL) +/*********************************************************************************************************//** + * @brief Enable or Disable the SPIx dual port read interface. + * @param SPIx: where SPIx is the selected SPI from the SPI peripherals. + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void SPI_DUALCmd(HT_SPI_TypeDef* SPIx, ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_SPI(SPIx)); + Assert_Param(IS_CONTROL_STATUS(NewState)); + + (NewState == ENABLE)?(SPIx->CR0 |= CR0_DUALEN_SET):(SPIx->CR0 &= CR0_DUALEN_RESET); +} +#endif + +#if (LIBCFG_QSPI) +/*********************************************************************************************************//** + * @brief Enable or Disable the QSPI quad port interface. + * @param SPIx: where SPIx is the selected QSPI from the QSPI peripherals. + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void QSPI_QuadCmd(HT_SPI_TypeDef* SPIx, ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_QSPI(SPIx)); + Assert_Param(IS_CONTROL_STATUS(NewState)); + + if (NewState == DISABLE) + { + QSPI_DirectionConfig(SPIx, SIO_DIR_IN); + SPIx->CR0 &= CR0_QUADEN_RESET; + } + else + { + SPIx->CR0 |= CR0_QUADEN_SET; + } +} + +/*********************************************************************************************************//** + * @brief Configure the direction of SIO pins in dual or quad mode. + * @param SPIx: where SPIx is the selected QSPI from the QSPI peripherals. + * @param SIO_DIR_INorOUT: + * This parameter can be one of below: + * @arg SIO_DIR_IN : The SIO pins are input mode + * @arg SIO_DIR_OUT : The SIO pins are output mode + * @retval None + ************************************************************************************************************/ +void QSPI_DirectionConfig(HT_SPI_TypeDef* SPIx, SIO_DIR_Enum SIO_DIR_INorOUT) +{ + /* Check the parameters */ + Assert_Param(IS_QSPI(SPIx)); + Assert_Param(IS_SIO_DIR(SIO_DIR_INorOUT)); + + if (SIO_DIR_INorOUT != SIO_DIR_IN) + SPIx->CR0 |= CR0_QDIODIR_OUT; + else + SPIx->CR0 &= CR0_QDIODIR_IN; +} +#endif + +/*********************************************************************************************************//** + * @brief Enable or Disable the SPIx guard time selection function. + * @param SPIx: where SPIx is the selected SPI from the SPI peripherals. + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void SPI_GUARDTCmd(HT_SPI_TypeDef* SPIx, ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_SPI(SPIx)); + Assert_Param(IS_CONTROL_STATUS(NewState)); + + (NewState == ENABLE) ? (SPIx->CR0 |= CR0_GUADTEN_SET) : (SPIx->CR0 &= CR0_GUADTEN_RESET); +} + +/*********************************************************************************************************//** + * @brief Set the SPIx guard time length. + * @param SPIx: where SPIx is the selected SPI from the SPI peripherals. + * @param Guard_Time: number of SCK to be the guard time length. + * This parameter can be: SPI_GUADTIME_1_SCK to SPI_GUADTIME_16_SCK. + * @retval None + ************************************************************************************************************/ +void SPI_GUARDTConfig(HT_SPI_TypeDef* SPIx, u32 Guard_Time) +{ + /* Check the parameters */ + Assert_Param(IS_SPI(SPIx)); + Assert_Param(IS_SPI_GUADTIME(Guard_Time)); + + SPIx->CR0 = (SPIx->CR0 & 0xF0FF) | (Guard_Time << 8); +} + +/*********************************************************************************************************//** + * @brief Set the SPIx chip select hold time. + * @param SPIx: where SPIx is the selected SPI from the SPI peripherals. + * @param CS_Hold_Time: number of SCK to be the hold time length. + * This parameter can be: 0 ~ 15 + * @retval None + ************************************************************************************************************/ +void SPI_SELHTConfig(HT_SPI_TypeDef* SPIx, u32 CS_Hold_Time) +{ + /* Check the parameters */ + Assert_Param(IS_SPI(SPIx)); + Assert_Param(IS_SPI_SELHOLDTIME(CS_Hold_Time)); + + SPIx->CR0 = (SPIx->CR0 & 0x0FFF) | (CS_Hold_Time << 12); +} +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/ht32f5xxxx_spi_midi.c b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/ht32f5xxxx_spi_midi.c new file mode 100644 index 0000000000..69a78217ee --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/ht32f5xxxx_spi_midi.c @@ -0,0 +1,182 @@ +/*********************************************************************************************************//** + * @file ht32f5xxxx_spi_midi.c + * @version $Rev:: 7073 $ + * @date $Date:: 2023-07-28 #$ + * @brief This file provides all the SPI firmware functions (MIDI Control). + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ + +/* Includes ------------------------------------------------------------------------------------------------*/ +#include "ht32f5xxxx_spi_midi.h" + + +/* Private macro -------------------------------------------------------------------------------------------*/ +#define IS_MIDICTRL_MODE(MODE) ((MODE == DOR_MODE) || \ + (MODE == DIOR_MODE) || \ + (MODE == QOR_MODE) || \ + (MODE == QIOR_MODE) || \ + (MODE == QPI_MODE) || \ + (MODE == SERIAL_MODE)) + +#define IS_MIDICTRL_CMD_LENGTH(LENGTH) ((LENGTH == MIDICTRL_CMDLENGTH_0) || \ + (LENGTH == MIDICTRL_CMDLENGTH_1) || \ + (LENGTH == MIDICTRL_CMDLENGTH_2) || \ + (LENGTH == MIDICTRL_CMDLENGTH_3) || \ + (LENGTH == MIDICTRL_CMDLENGTH_4) || \ + (LENGTH == MIDICTRL_CMDLENGTH_5) || \ + (LENGTH == MIDICTRL_CMDLENGTH_6) || \ + (LENGTH == MIDICTRL_CMDLENGTH_7) || \ + (LENGTH == MIDICTRL_CMDLENGTH_8)) + +#define IS_MIDICTRL_AD_LENGTH(LENGTH) ((LENGTH == MIDICTRL_ADLENGTH_0) || \ + (LENGTH == MIDICTRL_ADLENGTH_1) || \ + (LENGTH == MIDICTRL_ADLENGTH_2) || \ + (LENGTH == MIDICTRL_ADLENGTH_3) || \ + (LENGTH == MIDICTRL_ADLENGTH_4) || \ + (LENGTH == MIDICTRL_ADLENGTH_5) || \ + (LENGTH == MIDICTRL_ADLENGTH_6) || \ + (LENGTH == MIDICTRL_ADLENGTH_7) || \ + (LENGTH == MIDICTRL_ADLENGTH_8) || \ + (LENGTH == MIDICTRL_ADLENGTH_9) || \ + (LENGTH == MIDICTRL_ADLENGTH_10) || \ + (LENGTH == MIDICTRL_ADLENGTH_11) || \ + (LENGTH == MIDICTRL_ADLENGTH_12) || \ + (LENGTH == MIDICTRL_ADLENGTH_13) || \ + (LENGTH == MIDICTRL_ADLENGTH_14) || \ + (LENGTH == MIDICTRL_ADLENGTH_15) || \ + (LENGTH == MIDICTRL_ADLENGTH_16) || \ + (LENGTH == MIDICTRL_ADLENGTH_17) || \ + (LENGTH == MIDICTRL_ADLENGTH_18) || \ + (LENGTH == MIDICTRL_ADLENGTH_19) || \ + (LENGTH == MIDICTRL_ADLENGTH_20) || \ + (LENGTH == MIDICTRL_ADLENGTH_21) || \ + (LENGTH == MIDICTRL_ADLENGTH_22) || \ + (LENGTH == MIDICTRL_ADLENGTH_23) || \ + (LENGTH == MIDICTRL_ADLENGTH_24)) + +#define IS_MIDICTRL_MODE_LENGTH(LENGTH) ((LENGTH == MIDICTRL_MODELENGTH_0) || \ + (LENGTH == MIDICTRL_MODELENGTH_1) || \ + (LENGTH == MIDICTRL_MODELENGTH_2) || \ + (LENGTH == MIDICTRL_MODELENGTH_3) || \ + (LENGTH == MIDICTRL_MODELENGTH_4) || \ + (LENGTH == MIDICTRL_MODELENGTH_5) || \ + (LENGTH == MIDICTRL_MODELENGTH_6) || \ + (LENGTH == MIDICTRL_MODELENGTH_7) || \ + (LENGTH == MIDICTRL_MODELENGTH_8)) + +#define IS_MIDICTRL_DUMMY_LENGTH(LENGTH) ((LENGTH == MIDICTRL_DUMMYLENGTH_0) || \ + (LENGTH == MIDICTRL_DUMMYLENGTH_1) || \ + (LENGTH == MIDICTRL_DUMMYLENGTH_2) || \ + (LENGTH == MIDICTRL_DUMMYLENGTH_3) || \ + (LENGTH == MIDICTRL_DUMMYLENGTH_4) || \ + (LENGTH == MIDICTRL_DUMMYLENGTH_5) || \ + (LENGTH == MIDICTRL_DUMMYLENGTH_6) || \ + (LENGTH == MIDICTRL_DUMMYLENGTH_7) || \ + (LENGTH == MIDICTRL_DUMMYLENGTH_8)) + +#define IS_MIDICTRL_DATA_LENGTH(LENGTH) ((LENGTH == MIDICTRL_DATALENGTH_0) || \ + (LENGTH == MIDICTRL_DATALENGTH_1) || \ + (LENGTH == MIDICTRL_DATALENGTH_2) || \ + (LENGTH == MIDICTRL_DATALENGTH_3) || \ + (LENGTH == MIDICTRL_DATALENGTH_4) || \ + (LENGTH == MIDICTRL_DATALENGTH_5) || \ + (LENGTH == MIDICTRL_DATALENGTH_6) || \ + (LENGTH == MIDICTRL_DATALENGTH_7) || \ + (LENGTH == MIDICTRL_DATALENGTH_8) || \ + (LENGTH == MIDICTRL_DATALENGTH_9) || \ + (LENGTH == MIDICTRL_DATALENGTH_10) || \ + (LENGTH == MIDICTRL_DATALENGTH_11) || \ + (LENGTH == MIDICTRL_DATALENGTH_12) || \ + (LENGTH == MIDICTRL_DATALENGTH_13) || \ + (LENGTH == MIDICTRL_DATALENGTH_14) || \ + (LENGTH == MIDICTRL_DATALENGTH_15) || \ + (LENGTH == MIDICTRL_DATALENGTH_16) || \ + (LENGTH == MIDICTRL_DATALENGTH_17) || \ + (LENGTH == MIDICTRL_DATALENGTH_18) || \ + (LENGTH == MIDICTRL_DATALENGTH_19) || \ + (LENGTH == MIDICTRL_DATALENGTH_20) || \ + (LENGTH == MIDICTRL_DATALENGTH_21) || \ + (LENGTH == MIDICTRL_DATALENGTH_22) || \ + (LENGTH == MIDICTRL_DATALENGTH_23) || \ + (LENGTH == MIDICTRL_DATALENGTH_24) || \ + (LENGTH == MIDICTRL_DATALENGTH_25) || \ + (LENGTH == MIDICTRL_DATALENGTH_26) || \ + (LENGTH == MIDICTRL_DATALENGTH_27) || \ + (LENGTH == MIDICTRL_DATALENGTH_28) || \ + (LENGTH == MIDICTRL_DATALENGTH_29) || \ + (LENGTH == MIDICTRL_DATALENGTH_30) || \ + (LENGTH == MIDICTRL_DATALENGTH_31) || \ + (LENGTH == MIDICTRL_DATALENGTH_32)) + +#define IS_MIDICTRL_CMD_VALUE(VALUE) (VALUE <= 0xFF) +#define IS_MIDICTRL_MODE_VALUE(VALUE) (VALUE <= 0xFF) + +/* Global functions ----------------------------------------------------------------------------------------*/ +/*********************************************************************************************************//** + * @brief Enable or Disable QSPI MIDICTRL. + * @param QSPIx: where QSPIx is the selected QSPI from the QSPI peripherals. + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void MIDICTRL_Cmd(HT_SPI_TypeDef* QSPIx ,ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_CONTROL_STATUS(NewState)); + + if (NewState != DISABLE) + { + QSPIx->MIDICR0 |= MIDICTRL_ON; + } + else + { + QSPIx->MIDICR0 &= MIDICTRL_OFF; + } +} + +/*********************************************************************************************************//** + * @brief Initialize the QSPIx peripheral MIDICTRL according to the specified parameters in the MIDICTRL_InitStruct. + * @param QSPIx: This parameter can be HT_QSPI. + * @param MIDICTRL_InitStruct: pointer to a MIDICTRL_InitTypeDef structure that contains the configuration + * information for the specified USART peripheral. + * @retval None + ************************************************************************************************************/ +void MIDICTRL_Init(HT_SPI_TypeDef* QSPIx, MIDICTRL_InitTypeDef* MIDICTRL_InitStruct) +{ + /* Check the parameters */ + Assert_Param(IS_QSPI(QSPIx)); + Assert_Param(IS_MIDICTRL_MODE(MIDICTRL_InitStruct->MIDICTRL_MODE)); + Assert_Param(IS_MIDICTRL_CMD_LENGTH(MIDICTRL_InitStruct->MIDICTRL_CommandLength)); + Assert_Param(IS_MIDICTRL_AD_LENGTH(MIDICTRL_InitStruct->MIDICTRL_AddressLength)); + Assert_Param(IS_MIDICTRL_MODE_LENGTH(MIDICTRL_InitStruct->MIDICTRL_ModeLength)); + Assert_Param(IS_MIDICTRL_DUMMY_LENGTH(MIDICTRL_InitStruct->MIDICTRL_DummyLength)); + Assert_Param(IS_MIDICTRL_DATA_LENGTH(MIDICTRL_InitStruct->MIDICTRL_DataLength)); + Assert_Param(IS_MIDICTRL_CMD_VALUE(MIDICTRL_InitStruct->MIDICTRL_CommandValue)); + Assert_Param(IS_MIDICTRL_MODE_VALUE(MIDICTRL_InitStruct->MIDICTRL_ModeValue)); + + QSPIx->MIDICR0 = (QSPIx->MIDICR0 & 0xF0800000) | MIDICTRL_InitStruct->MIDICTRL_MODE | + MIDICTRL_InitStruct->MIDICTRL_CommandLength | MIDICTRL_InitStruct->MIDICTRL_AddressLength | + MIDICTRL_InitStruct->MIDICTRL_ModeLength | MIDICTRL_InitStruct->MIDICTRL_DummyLength | + MIDICTRL_InitStruct->MIDICTRL_DataLength ; + + QSPIx->MIDICR1 = (QSPIx->MIDICR1 & 0xFFFF0000) | ((MIDICTRL_InitStruct->MIDICTRL_ModeValue) << MDVALUE_POS )| + ((MIDICTRL_InitStruct->MIDICTRL_CommandValue) << CMDVALUE_POS ); +} diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/ht32f5xxxx_tkey.c b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/ht32f5xxxx_tkey.c new file mode 100644 index 0000000000..a6e482d6a0 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/ht32f5xxxx_tkey.c @@ -0,0 +1,703 @@ +/*********************************************************************************************************//** + * @file ht32f5xxxx_tkey.c + * @version $Rev:: 5500 $ + * @date $Date:: 2021-07-20 #$ + * @brief This file provides all the TKEY firmware functions. + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ + +/* Includes ------------------------------------------------------------------------------------------------*/ +#include "ht32f5xxxx_tkey.h" + +/** @addtogroup HT32F5xxxx_Peripheral_Driver HT32F5xxxx Peripheral Driver + * @{ + */ + +/** @defgroup TKEY TKEY + * @brief TKEY driver modules + * @{ + */ + + +/* Private constants ---------------------------------------------------------------------------------------*/ +/** @defgroup TKEY_Private_Define TKEY private definitions + * @{ + */ +#define TKCLKSEL_MASK (0x80000000) +/** + * @} + */ + +/* Global functions ----------------------------------------------------------------------------------------*/ +/** @defgroup TKEY_Exported_Functions TKEY exported functions + * @{ + */ +/*********************************************************************************************************//** + * @brief Deinitialize the TKEY peripheral registers to their default reset values. + * @retval None + ************************************************************************************************************/ +void TKEY_DeInit(void) +{ + RSTCU_PeripReset_TypeDef RSTCUReset = {{0}}; + + RSTCUReset.Bit.TKEY = 1; + RSTCU_PeripReset(RSTCUReset, ENABLE); +} + +/*********************************************************************************************************//** + * @brief Configure Touch key IP clock source. + * @param Sel: Specify the Touch key IP clock source.. + * This parameter can be one of the following values: + * @arg TKEY_PCLK : PCLK. + * @arg TKEY_LSI : LSI. + * @retval None + ************************************************************************************************************/ +void TKEY_IPClockConfig(TKEY_IP_CLK_Enum Sel) +{ + Assert_Param(IS_TKEY_IP_CLK(Sel)); + + HT_TKEY->TKCR = (HT_TKEY->TKCR & TKCLKSEL_MASK) | (Sel << 31); +} + +/*********************************************************************************************************//** + * @brief Configure the RefOSC Delay time. + * @param Sel: Specify the periodic auto scan mode time out. + * This parameter can be one of the following values: + * @arg TKEY_RefOSC_DelayTime_0 : 4 RefOSC clock. + * @arg TKEY_RefOSC_DelayTime_1 : 2 RefOSC clock. + * @arg TKEY_RefOSC_DelayTime_2 : 4 RefOSC clock. + * @arg TKEY_RefOSC_DelayTime_3 : 8 RefOSC clock. + * @arg TKEY_RefOSC_DelayTime_4 : 16 RefOSC clock. + * @arg TKEY_RefOSC_DelayTime_5 : 32 RefOSC clock. + * @arg TKEY_RefOSC_DelayTime_6 : 64 RefOSC clock. + * @arg TKEY_RefOSC_DelayTime_7 : 4 RefOSC clock. + * @retval None + ************************************************************************************************************/ +void TKEY_RefOSCDelayTimeConfig(TKEY_RefOSC_DelayTime_Enum Sel) +{ + /* Check the parameters */ + Assert_Param(IS_TKEY_RefOSC_DelayTime(Sel)); + + HT_TKEY->TKCR = (HT_TKEY->TKCR & ~(7 << 13)) | Sel; +} +/*********************************************************************************************************//** + * @brief Configure the periodic auto scan mode time out. + * @param Sel: Specify the periodic auto scan mode time out. + * This parameter can be one of the following values: + * @arg TKEY_PASM_TIMEOUT_0 : 2^13/FLIRC. + * @arg TKEY_PASM_TIMEOUT_1 : 2^14/FLIRC. + * @arg TKEY_PASM_TIMEOUT_2 : 2^15/FLIRC. + * @arg TKEY_PASM_TIMEOUT_3 : 2^16/FLIRC. + * @arg TKEY_PASM_TIMEOUT_4 : 2^17/FLIRC. + * @arg TKEY_PASM_TIMEOUT_5 : 2^18/FLIRC. + * @retval None + ************************************************************************************************************/ +void TKEY_PASMTimeoutConfig(TKEY_PASM_TIMEOUT_Enum Sel) +{ + /* Check the parameters */ + Assert_Param(IS_TKEY_PASM_TIMEOUT(Sel)); + + HT_TKEY->TKCR = (HT_TKEY->TKCR & ~(7 << 10)) | Sel; +} + +/*********************************************************************************************************//** + * @brief Configure the periodic auto scan mode period. + * @param Sel: Specify the periodic auto scan mode period. + * This parameter can be one of the following values: + * @arg TKEY_PASM_PERIOD_0 : 2^14/FLIRC. + * @arg TKEY_PASM_PERIOD_1 : 2^13/FLIRC. + * @arg TKEY_PASM_PERIOD_2 : 2^12/FLIRC. + * @arg TKEY_PASM_PERIOD_3 : 2^11/FLIRC. + * @retval None + ************************************************************************************************************/ +void TKEY_PASMPeriodConfig(TKEY_PASM_PERIOD_Enum Sel) +{ + /* Check the parameters */ + Assert_Param(IS_TKEY_PASM_PERIOD(Sel)); + + HT_TKEY->TKCR = (HT_TKEY->TKCR & ~(3 << 8)) | Sel; +} + +/*********************************************************************************************************//** + * @brief Configure the touch key 16-bit counter clock source. + * @param Sel: Specify the 16-bit counter clock source. + * This parameter can be one of the following values: + * @arg TKEY_TK16S_CLK_0 : TKCLK/16. + * @arg TKEY_TK16S_CLK_1 : TKCLK/32. + * @arg TKEY_TK16S_CLK_2 : TKCLK/64. + * @arg TKEY_TK16S_CLK_3 : TKCLK/128. + * @retval None + ************************************************************************************************************/ +void TKEY_16BitCounterClockConfig(TKEY_TK16S_CLK_Enum Sel) +{ + /* Check the parameters */ + Assert_Param(IS_TKEY_TK16S_CLK(Sel)); + + HT_TKEY->TKCR = (HT_TKEY->TKCR & ~(3 << 5)) | Sel; +} + +/*********************************************************************************************************//** + * @brief Configure the touch key OSC frequency. + * @param Sel: Specify the Touch Key frequency. + * This parameter can be one of the following values: + * @arg TKEY_TKFS_FREQ_0 : 1MHz. + * @arg TKEY_TKFS_FREQ_1 : 3MHz. + * @arg TKEY_TKFS_FREQ_2 : 7MHz. + * @arg TKEY_TKFS_FREQ_3 : 11MHz. + * @retval None + ************************************************************************************************************/ +void TKEY_OSCFreqConfig(TKEY_TKFS_FREQ_Enum Sel) +{ + /* Check the parameters */ + Assert_Param(IS_TKEY_TKFS_FREQ(Sel)); + + HT_TKEY->TKCR = (HT_TKEY->TKCR & ~(3 << 3)) | Sel; +} + +/*********************************************************************************************************//** + * @brief Configure the touch key operation mode. + * @param Sel: Specify the Touch Key mode. + * This parameter can be one of the following values: + * @arg TKEY_MODE_AUTOSCAN : Auto scan mode. + * @arg TKEY_MODE_MANUAL : Manual mode. + * @arg TKEY_MODE_PASM : Periodic auto scan mode. + * @retval None + ************************************************************************************************************/ +void TKEY_ModeConfig(TKEY_MODE_Enum Sel) +{ + /* Check the parameters */ + Assert_Param(IS_TKEY_MODE(Sel)); + + HT_TKEY->TKCR = (HT_TKEY->TKCR & ~(3 << 1)) | Sel; +} + +/*********************************************************************************************************//** + * @brief Touch Key detection control. + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void TKEY_StartCmd(ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_CONTROL_STATUS(NewState)); + + if (NewState != DISABLE) + { + HT_TKEY->TKCR |= (1 << 0); + } + else + { + HT_TKEY->TKCR &= ~(1 << 0); + } +} + +/*********************************************************************************************************//** + * @brief Enable or Disable the specified TKEY interrupt. + * @param TKEY_Int: specify if the TKEY interrupt source to be enabled or disabled. + * This parameter can be any combination of the following values: + * @arg TKEY_INT_TKRCOVE : 8-bit time slot counter overflow interrupt + * @arg TKEY_INT_TKTHE : Touch Key threshold match interrupt + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void TKEY_IntConfig(u32 TKEY_Int, ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_TKEY_INT(TKEY_Int)); + Assert_Param(IS_CONTROL_STATUS(NewState)); + + if (NewState != DISABLE) + { + HT_TKEY->TKIER |= TKEY_Int; + } + else + { + HT_TKEY->TKIER &= ~TKEY_Int; + } +} + +/*********************************************************************************************************//** + * @brief Check whether the specified TKEY flag has been set or not. + * @param TKEY_Flag: specify the flag that is to be check. + * This parameter can be one of the following values: + * @arg TKEY_FLAG_TKBUSY : Touch Key busy flag + * @arg TKEY_FLAG_TKCFOV : Touch Key 16-bit C/F counter overflow flag + * @arg TKEY_FLAG_TK16OV : Touch Key 16-bit counter overflow flag + * @arg TKEY_FLAG_TKRCOVF : 8-bit time slot counter overflow flag + * @arg TKEY_FLAG_TKTHF : Touch Key threshold match flag + * @retval SET or RESET + ************************************************************************************************************/ +FlagStatus TKEY_GetFlagStatus(u32 TKEY_Flag) +{ + /* Check the parameters */ + Assert_Param(IS_TKEY_FLAG(TKEY_Flag)); + + if ((HT_TKEY->TKSR & TKEY_Flag) != RESET) + { + return SET; + } + else + { + return RESET; + } +} + +/*********************************************************************************************************//** + * @brief Clear the specified TKEY flag. + * @param TKEY_Flag: specify the flag that is to be cleared. + * This parameter can be one of the following values: + * @arg TKEY_FLAG_TKCFOV : Touch Key 16-bit C/F counter overflow flag + * @arg TKEY_FLAG_TK16OV : Touch Key 16-bit counter overflow flag + * @arg TKEY_FLAG_TKRCOVF : 8-bit time slot counter overflow flag + * @arg TKEY_FLAG_TKTHF : Touch Key threshold match flag + * @retval None + ************************************************************************************************************/ +void TKEY_ClearFlag(u32 TKEY_Flag) +{ + /* Check the parameters */ + Assert_Param(IS_TKEY_FLAG_CLEAR(TKEY_Flag)); + + HT_TKEY->TKSR = TKEY_Flag; +} + +/*********************************************************************************************************//** + * @brief Get the touch key 16-bit counter value. + * @retval The counter value + ************************************************************************************************************/ +u32 TKEY_Get16BitCounterValue(void) +{ + return HT_TKEY->TKCNTR; +} + +/*********************************************************************************************************//** + * @brief Set the 8-bit time slot counter reload value. + * @param Reload: Specify the counter reload value. + * @retval None + ************************************************************************************************************/ +void TKEY_Set8BitCounterReload(u32 Reload) +{ + HT_TKEY->TKTSCRR = Reload; +} + +/*********************************************************************************************************//** + * @brief Get the 8-bit time slot counter reload value. + * @retval The counter reload value + ************************************************************************************************************/ +u32 TKEY_Get8BitCounterReload(void) +{ + return HT_TKEY->TKTSCRR; +} + +/*********************************************************************************************************//** + * @brief Configure the 8-bit time slot counter clock source. + * @param TKMn: TKM_0 ~ TKM_5 + * @param Sel: Specify the 8-bit time slot counter clock source. + * This parameter can be one of the following values: + * @arg TKM_TSS_CLK_0 : Ref OSC. + * @arg TKM_TSS_CLK_1 : TKCLK/32. + * @arg TKM_TSS_CLK_2 : TKCLK/64. + * @arg TKM_TSS_CLK_3 : TKCLK/128. + * @retval None + ************************************************************************************************************/ +void TKM_TimeSlotCounterClockConfig(TKM_Enum TKMn, TKM_TSS_CLK_Enum Sel) +{ + HT_TKM_TypeDef *TKMx = (HT_TKM_TypeDef *)((u32)&HT_TKEY->TKM0 + (TKMn * 0x100)); + + /* Check the parameters */ + Assert_Param(IS_TKM(TKMn)); + Assert_Param(IS_TKM_TSS_CLK(Sel)); + + TKMx->CR = (TKMx->CR & ~(3 << 8)) | Sel; +} + +/*********************************************************************************************************//** + * @brief Enable or Disable the Reference OSC. + * @param TKMn: TKM_0 ~ TKM_5 + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void TKM_RefOSCCmd(TKM_Enum TKMn, ControlStatus NewState) +{ + HT_TKM_TypeDef *TKMx = (HT_TKM_TypeDef *)((u32)&HT_TKEY->TKM0 + (TKMn * 0x100)); + + /* Check the parameters */ + Assert_Param(IS_TKM(TKMn)); + Assert_Param(IS_CONTROL_STATUS(NewState)); + + if (NewState != DISABLE) + { + TKMx->CR |= (1 << 7); + } + else + { + TKMx->CR &= ~(1 << 7); + } +} + +/*********************************************************************************************************//** + * @brief Enable or Disable the Key OSC. + * @param TKMn: TKM_0 ~ TKM_5 + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void TKM_KeyOSCCmd(TKM_Enum TKMn, ControlStatus NewState) +{ + HT_TKM_TypeDef *TKMx = (HT_TKM_TypeDef *)((u32)&HT_TKEY->TKM0 + (TKMn * 0x100)); + + /* Check the parameters */ + Assert_Param(IS_TKM(TKMn)); + Assert_Param(IS_CONTROL_STATUS(NewState)); + + if (NewState != DISABLE) + { + TKMx->CR |= (1 << 6); + } + else + { + TKMx->CR &= ~(1 << 6); + } +} + +/*********************************************************************************************************//** + * @brief Enable or Disable the Multi-frequency. + * @param TKMn: TKM_0 ~ TKM_5 + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void TKM_MultiFreqCmd(TKM_Enum TKMn, ControlStatus NewState) +{ + HT_TKM_TypeDef *TKMx = (HT_TKM_TypeDef *)((u32)&HT_TKEY->TKM0 + (TKMn * 0x100)); + + /* Check the parameters */ + Assert_Param(IS_TKM(TKMn)); + Assert_Param(IS_CONTROL_STATUS(NewState)); + + if (NewState != DISABLE) + { + TKMx->CR |= (1 << 5); + } + else + { + TKMx->CR &= ~(1 << 5); + } +} + +/*********************************************************************************************************//** + * @brief Configure the C/F OSC frequency-hopping. + * @param TKMn: TKM_0 ~ TKM_5 + * @param Sel: Specify the C/F OSC frequency-hopping method. + * This paramter can be one of the following values: + * @arg TKM_SOF_CTRL_SW : + * @arg TKM_SOF_CTRL_HW : + * @retval None + ************************************************************************************************************/ +void TKM_SOFCtrlConfig(TKM_Enum TKMn, TKM_SOF_CTRL_Enum Sel) +{ + HT_TKM_TypeDef *TKMx = (HT_TKM_TypeDef *)((u32)&HT_TKEY->TKM0 + (TKMn * 0x100)); + + /* Check the parameters */ + Assert_Param(IS_TKM(TKMn)); + Assert_Param(IS_TKM_SOF_CTRL(Sel)); + + TKMx->CR = (TKMx->CR & ~(1 << 3)) | Sel; +} + +/*********************************************************************************************************//** + * @brief Configure the Key OSC and the Reference OSC frequency. + * @param TKMn: TKM_0 ~ TKM_5 + * @param Sel: Specify the OSC frequency. + * This paramter can be one of the following values: + * @arg TKM_SOF_FREQ_0 : 1.020MHz. + * @arg TKM_SOF_FREQ_1 : 1.040MHz. + * @arg TKM_SOF_FREQ_2 : 1.059MHz. + * @arg TKM_SOF_FREQ_3 : 1.074MHz. + * @arg TKM_SOF_FREQ_4 : 1.085MHz. + * @arg TKM_SOF_FREQ_5 : 1.099MHz. + * @arg TKM_SOF_FREQ_6 : 1.111MHz. + * @arg TKM_SOF_FREQ_7 : 1.125MHz. + * @retval None + ************************************************************************************************************/ +void TKM_SOFFreqConfig(TKM_Enum TKMn, TKM_SOF_FREQ_Enum Sel) +{ + HT_TKM_TypeDef *TKMx = (HT_TKM_TypeDef *)((u32)&HT_TKEY->TKM0 + (TKMn * 0x100)); + + /* Check the parameters */ + Assert_Param(IS_TKM(TKMn)); + Assert_Param(IS_TKM_SOF_FREQ(Sel)); + + TKMx->CR = (TKMx->CR & ~(7 << 0)) | Sel; +} + +/*********************************************************************************************************//** + * @brief Enable or Disable the specified Touch Key. + * @param TKMn: TKM_0 ~ TKM_5 + * @param Key: TKM_KEY_0 ~ TKM_KEY_3 + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void TKM_KeyCmd(TKM_Enum TKMn, TKM_KEY_Enum Key, ControlStatus NewState) +{ + HT_TKM_TypeDef *TKMx = (HT_TKM_TypeDef *)((u32)&HT_TKEY->TKM0 + (TKMn * 0x100)); + + /* Check the parameters */ + Assert_Param(IS_TKM(TKMn)); + Assert_Param(IS_TKM_KEY(Key)); + Assert_Param(IS_CONTROL_STATUS(NewState)); + + if (NewState != DISABLE) + { + TKMx->KCFGR |= (1 << Key); + } + else + { + TKMx->KCFGR &= ~(1 << Key); + } +} + +/*********************************************************************************************************//** + * @brief Configure the Time Slot X key selection (for auto scan mode & Periodic auto scan mode). + * @param TKMn: TKM_0 ~ TKM_5 + * @param Slot: TKM_TIME_SLOT_0 ~ TKM_TIME_SLOT_3 + * @param Key: TKM_KEY_0 ~ TKM_KEY_3 + * @retval None + ************************************************************************************************************/ +void TKM_TimeSlotKeyConfig(TKM_Enum TKMn, TKM_TIME_SLOT_Enum Slot, TKM_KEY_Enum Key) +{ + HT_TKM_TypeDef *TKMx = (HT_TKM_TypeDef *)((u32)&HT_TKEY->TKM0 + (TKMn * 0x100)); + u32 offset = (16 + (Slot * 2)); + + /* Check the parameters */ + Assert_Param(IS_TKM(TKMn)); + Assert_Param(IS_TKM_TIME_SLOT(Slot)); + Assert_Param(IS_TKM_KEY(Key)); + + TKMx->KCFGR = (TKMx->KCFGR & ~(3 << offset)) | (Key << offset); +} + +/*********************************************************************************************************//** + * @brief Configure the Key threshold. + * @param TKMn: TKM_0 ~ TKM_5 + * @param Key: TKM_KEY_0 ~ TKM_KEY_3 + * @param Sel: Specify the Key threshold. + * This parameter can be one of the following values: + * @arg TKM_KEY_THR_LOWER : + * @arg TKM_KEY_THR_UPPER : + * @retval None + ************************************************************************************************************/ +void TKM_KeyThresholdConfig(TKM_Enum TKMn, TKM_KEY_Enum Key, TKM_KEY_THR_Enum Sel) +{ + HT_TKM_TypeDef *TKMx = (HT_TKM_TypeDef *)((u32)&HT_TKEY->TKM0 + (TKMn * 0x100)); + u32 offset = (8 + Key); + + /* Check the parameters */ + Assert_Param(IS_TKM(TKMn)); + Assert_Param(IS_TKM_KEY(Key)); + Assert_Param(IS_TKM_KEY_THR(Sel)); + + TKMx->KCFGR = (TKMx->KCFGR & ~(1 << offset)) | (Sel << offset); +} + +/*********************************************************************************************************//** + * @brief Check whether the specified key threshold match flag has been set or not. + * @param TKMn: TKM_0 ~ TKM_5 + * @param Key: TKM_KEY_0 ~ TKM_KEY_3 + * @retval SET or RESET + ************************************************************************************************************/ +FlagStatus TKM_GetMatchFlagStatus(TKM_Enum TKMn, TKM_KEY_Enum Key) +{ + HT_TKM_TypeDef *TKMx = (HT_TKM_TypeDef *)((u32)&HT_TKEY->TKM0 + (TKMn * 0x100)); + + /* Check the parameters */ + Assert_Param(IS_TKM(TKMn)); + Assert_Param(IS_TKM_KEY(Key)); + + if ((TKMx->SR & (1 << Key)) != RESET) + { + return SET; + } + else + { + return RESET; + } +} + +/*********************************************************************************************************//** + * @brief Clear the specified key threshold match flag. + * @param TKMn: TKM_0 ~ TKM_5 + * @param Key: TKM_KEY_0 ~ TKM_KEY_3 + * @retval None + ************************************************************************************************************/ +void TKM_ClearMatchFlag(TKM_Enum TKMn, TKM_KEY_Enum Key) +{ + HT_TKM_TypeDef *TKMx = (HT_TKM_TypeDef *)((u32)&HT_TKEY->TKM0 + (TKMn * 0x100)); + + /* Check the parameters */ + Assert_Param(IS_TKM(TKMn)); + Assert_Param(IS_TKM_KEY(Key)); + + TKMx->SR = (1 << Key); +} + +/*********************************************************************************************************//** + * @brief Set the reference OSC capacitor value. + * @param TKMn: TKM_0 ~ TKM_5 + * @param Value: Specify the capacitor value between 0x000 ~ 0x3FF. + * @retval None + ************************************************************************************************************/ +void TKM_SetRefOSCCapacitor(TKM_Enum TKMn, u32 Value) +{ + HT_TKM_TypeDef *TKMx = (HT_TKM_TypeDef *)((u32)&HT_TKEY->TKM0 + (TKMn * 0x100)); + + /* Check the parameters */ + Assert_Param(IS_TKM(TKMn)); + + TKMx->ROCPR = Value; +} + +/*********************************************************************************************************//** + * @brief Get the reference OSC capacitor value. + * @param TKMn: TKM_0 ~ TKM_5 + * @retval The capacitor value + ************************************************************************************************************/ +u32 TKM_GetRefOSCCapacitor(TKM_Enum TKMn) +{ + HT_TKM_TypeDef *TKMx = (HT_TKM_TypeDef *)((u32)&HT_TKEY->TKM0 + (TKMn * 0x100)); + + /* Check the parameters */ + Assert_Param(IS_TKM(TKMn)); + + return TKMx->ROCPR; +} + +/*********************************************************************************************************//** + * @brief Set the key capacitor value. + * @param TKMn: TKM_0 ~ TKM_5 + * @param Key: TKM_KEY_0 ~ TKM_KEY_3 + * @param Value: Specify the capacitor value between 0x000 ~ 0x3FF. + * @retval None + ************************************************************************************************************/ +void TKM_SetKeyCapacitor(TKM_Enum TKMn, TKM_KEY_Enum Key, u32 Value) +{ + HT_TKM_TypeDef *TKMx = (HT_TKM_TypeDef *)((u32)&HT_TKEY->TKM0 + (TKMn * 0x100)); + + /* Check the parameters */ + Assert_Param(IS_TKM(TKMn)); + Assert_Param(IS_TKM_KEY(Key)); + + *(vu32*)((u32)&TKMx->K3CPR + ((3 - Key) * 4)) = Value; +} + +/*********************************************************************************************************//** + * @brief Get the key capacitor value. + * @param TKMn: TKM_0 ~ TKM_5 + * @param Key: TKM_KEY_0 ~ TKM_KEY_3 + * @retval The capacitor value + ************************************************************************************************************/ +u32 TKM_GetKeyCapacitor(TKM_Enum TKMn, TKM_KEY_Enum Key) +{ + HT_TKM_TypeDef *TKMx = (HT_TKM_TypeDef *)((u32)&HT_TKEY->TKM0 + (TKMn * 0x100)); + + /* Check the parameters */ + Assert_Param(IS_TKM(TKMn)); + Assert_Param(IS_TKM_KEY(Key)); + + return *(vu32*)((u32)&TKMx->K3CPR + ((3 - Key) * 4)); +} + +/*********************************************************************************************************//** + * @brief Get the 16-bit C/F counter value. + * @param TKMn: TKM_0 ~ TKM_5 + * @retval The counter value + ************************************************************************************************************/ +u32 TKM_Get16BitCFCounterValue(TKM_Enum TKMn) +{ + HT_TKM_TypeDef *TKMx = (HT_TKM_TypeDef *)((u32)&HT_TKEY->TKM0 + (TKMn * 0x100)); + + /* Check the parameters */ + Assert_Param(IS_TKM(TKMn)); + + return TKMx->CFCNTR; +} + +/*********************************************************************************************************//** + * @brief Get the key counter value. + * @param TKMn: TKM_0 ~ TKM_5 + * @param Key: TKM_KEY_0 ~ TKM_KEY_3 + * @retval None + ************************************************************************************************************/ +u32 TKM_GetKeyCounterValue(TKM_Enum TKMn, TKM_KEY_Enum Key) +{ + HT_TKM_TypeDef *TKMx = (HT_TKM_TypeDef *)((u32)&HT_TKEY->TKM0 + (TKMn * 0x100)); + + /* Check the parameters */ + Assert_Param(IS_TKM(TKMn)); + Assert_Param(IS_TKM_KEY(Key)); + + return *(vu32*)((u32)&TKMx->K3CNTR + ((3 - Key) * 4)); +} + +/*********************************************************************************************************//** + * @brief Set the key threshold value. + * @param TKMn: TKM_0 ~ TKM_5 + * @param Key: TKM_KEY_0 ~ TKM_KEY_3 + * @param Value: Specify the key threshold value between 0x0000 ~ 0xFFFF. + * @retval None + ************************************************************************************************************/ +void TKM_SetKeyThreshold(TKM_Enum TKMn, TKM_KEY_Enum Key, u32 Value) +{ + HT_TKM_TypeDef *TKMx = (HT_TKM_TypeDef *)((u32)&HT_TKEY->TKM0 + (TKMn * 0x100)); + + /* Check the parameters */ + Assert_Param(IS_TKM(TKMn)); + Assert_Param(IS_TKM_KEY(Key)); + + *(vu32*)((u32)&TKMx->K3THR + ((3 - Key) * 4)) = Value; +} + +/*********************************************************************************************************//** + * @brief Get the key threshold value. + * @param TKMn: TKM_0 ~ TKM_5 + * @param Key: TKM_KEY_0 ~ TKM_KEY_3 + * @retval The threshold value + ************************************************************************************************************/ +u32 TKEY_GetKeyThreshold(TKM_Enum TKMn, TKM_KEY_Enum Key) +{ + HT_TKM_TypeDef *TKMx = (HT_TKM_TypeDef *)((u32)&HT_TKEY->TKM0 + (TKMn * 0x100)); + + /* Check the parameters */ + Assert_Param(IS_TKM(TKMn)); + Assert_Param(IS_TKM_KEY(Key)); + + return *(vu32*)((u32)&TKMx->K3THR + ((3 - Key) * 4)); +} +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/ht32f5xxxx_tm.c b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/ht32f5xxxx_tm.c new file mode 100644 index 0000000000..1e4a2fe15d --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/ht32f5xxxx_tm.c @@ -0,0 +1,1853 @@ +/*********************************************************************************************************//** + * @file ht32f5xxxx_tm.c + * @version $Rev:: 7059 $ + * @date $Date:: 2023-07-27 #$ + * @brief This file provides all the TM firmware functions. + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ + +/* Includes ------------------------------------------------------------------------------------------------*/ +#include "ht32f5xxxx_tm.h" + +/** @addtogroup HT32F5xxxx_Peripheral_Driver HT32F5xxxx Peripheral Driver + * @{ + */ + +/** @defgroup TM TM + * @brief TM driver modules + * @{ + */ + + +/* Private constants ---------------------------------------------------------------------------------------*/ +/** @defgroup TM_Private_Define TM private definitions + * @{ + */ +#define CNTCFR_UEVDIS 0x00000001ul +#define CNTCFR_UGDIS 0x00000002ul +#define CNTCFR_DIR 0x01000000ul +#define CNTCFR_CMSEL_MASK ~0x00030000ul +#define CNTCFR_CKDIV_MASK ~0x00000300ul + +#define MDCFR_SPMSET 0x01000000ul +#define MDCFR_TSE 0x00000001ul +#define MDCFR_SMSEL_MASK ~0x00000700ul +#define MDCFR_MMSEL_MASK ~0x00070000ul + +#if 0 +#define TRCFR_ECME 0x01000000ul +#define TRCFR_ETI_POL 0x00010000ul +#define TRCFR_ETI_PSC_MASK ~0x00003000ul +#define TRCFR_ETIF_MASK ~0x00000F00ul +#define TRCFR_ETI_CONF_MASK ~0x00013F00ul +#endif +#define TRCFR_TRSEL_MASK ~0x0000000Ful + +#define CTR_TME 0x00000001ul +#define CTR_CRBE 0x00000002ul +#define CTR_CHCCDS 0x00010000ul + +#define CH0ICFR_CH0SRC 0x80000000ul +#define CHICFR_CHF_MASK ~0x000000FFul +#define CHICFR_CHCCS_MASK ~0x00030000ul +#define CHICFR_CHPSC_MASK ~0x000C0000ul + +#define CHOCFR_REFCE 0x00000008ul +#define CHOCFR_CHPRE 0x00000010ul +#define CHOCFR_IMAE 0x00000020ul +#define CHOCFR_CHOM_MASK ~0x00000107ul + +#define CHPOLR_CH0P 0x00000001ul +#define CHPOLR_CH1P 0x00000004ul +/** + * @} + */ + +/* Private function prototypes -----------------------------------------------------------------------------*/ +static void _TM_CHx_Config(HT_TM_TypeDef* TMx, TM_CH_Enum Ch, TM_CHP_Enum Pol, TM_CHCCS_Enum Sel, u8 Filter); + +/* Private macro -------------------------------------------------------------------------------------------*/ +#if (LIBCFG_TM_TIFN_5BIT) +#define FILTER_PROCESS(cap) ((cap->Fsampling << 5) + cap->Event) +#else +#define FILTER_PROCESS(cap) ((cap->Fsampling << 4) + cap->Event) +#endif + +/* Global functions ----------------------------------------------------------------------------------------*/ +/** @defgroup TM_Exported_Functions TM exported functions + * @{ + */ +/*********************************************************************************************************//** + * @brief Deinitialize the TMx peripheral registers to their default reset values. + * @param TMx: where TMx is the selected TM from the TM peripherals. + * @retval None + ************************************************************************************************************/ +void TM_DeInit(HT_TM_TypeDef* TMx) +{ + RSTCU_PeripReset_TypeDef RSTCUReset = {{0}}; + + /* Check the parameters */ + Assert_Param(IS_TM(TMx)); + + #if (!LIBCFG_NO_GPTM0) + if (TMx == HT_GPTM0) + { + RSTCUReset.Bit.GPTM0 = 1; + } + #endif + #if (LIBCFG_GPTM1) + else if (TMx == HT_GPTM1) + { + RSTCUReset.Bit.GPTM1 = 1; + } + #endif + #if (LIBCFG_MCTM0) + else if (TMx == HT_MCTM0) + { + RSTCUReset.Bit.MCTM0 = 1; + } + #endif + #if (LIBCFG_SCTM0) + if (TMx == HT_SCTM0) + { + RSTCUReset.Bit.SCTM0 = 1; + } + #endif + #if (LIBCFG_SCTM1) + else if (TMx == HT_SCTM1) + { + RSTCUReset.Bit.SCTM1 = 1; + } + #endif + #if (LIBCFG_SCTM2) + else if (TMx == HT_SCTM2) + { + RSTCUReset.Bit.SCTM2 = 1; + } + #endif + #if (LIBCFG_SCTM3) + else if (TMx == HT_SCTM3) + { + RSTCUReset.Bit.SCTM3 = 1; + } + #endif + #if (LIBCFG_PWM0) + if (TMx == HT_PWM0) + { + RSTCUReset.Bit.PWM0 = 1; + } + #endif + #if (LIBCFG_PWM1) + else if (TMx == HT_PWM1) + { + RSTCUReset.Bit.PWM1 = 1; + } + #endif + #if (LIBCFG_PWM2) + else if (TMx == HT_PWM2) + { + RSTCUReset.Bit.PWM1 = 1; + } + #endif + + RSTCU_PeripReset(RSTCUReset, ENABLE); +} + +/*********************************************************************************************************//** + * @brief Initialize the TMx counter to reload, prescaler, counter mode and repetition counter. + * @param TMx: where TMx is the selected TM from the TM peripheral. + * @param TimeBaseInit: Point to a \ref TM_TimeBaseInitTypeDef that contains the configuration information. + * @retval None + ************************************************************************************************************/ +void TM_TimeBaseInit(HT_TM_TypeDef* TMx, TM_TimeBaseInitTypeDef* TimeBaseInit) +{ + /* Check the parameters */ + Assert_Param(IS_TM(TMx)); + Assert_Param(IS_TM_CNT_MODE(TimeBaseInit->CounterMode)); + Assert_Param(IS_TM_PSC_RLD(TimeBaseInit->PSCReloadTime)); + + /* Set the counter reload value */ + TMx->CRR = TimeBaseInit->CounterReload; + + /* Set the Prescaler value */ + TMx->PSCR = TimeBaseInit->Prescaler; + + /* Select the Counter Mode */ + TMx->CNTCFR &= CNTCFR_CMSEL_MASK; /* CNTCFR_DIR is read only when the timer configured as */ + TMx->CNTCFR &= ~(u32)CNTCFR_DIR; /* Center-aligned mode. Reset mode first and then reset the */ + /* CNTCFR_DIR bit (separate as two steps). */ + + TMx->CNTCFR |= TimeBaseInit->CounterMode; + + #if (LIBCFG_MCTM0) + if (TMx == HT_MCTM0) + { + /* Set the Repetition value */ + TMx->REPR = TimeBaseInit->RepetitionCounter; + } + #endif + + /* To reload the Prescaler value immediatly or next update event */ + TMx->EVGR = TimeBaseInit->PSCReloadTime; +} + +/*********************************************************************************************************//** + * @brief Initialize the TMx channel N output. + * @param TMx: where TMx is the selected TM from the TM peripherals. + * @param OutInit: Point to a \ref TM_OutputInitTypeDef structure that contains + the configuration information. + * @retval None + ************************************************************************************************************/ +void TM_OutputInit(HT_TM_TypeDef* TMx, TM_OutputInitTypeDef* OutInit) +{ + vu32 *pOcfr = (vu32*)&TMx->CH0OCFR + OutInit->Channel; + vu32 *pCcr = (vu32*)&TMx->CH0CCR + OutInit->Channel; + vu32 *pAcr = (vu32*)&TMx->CH0ACR + OutInit->Channel; + u8 bChPos = OutInit->Channel << 1; + u32 wTmpMask; + u32 wTmpReg; + + #if (LIBCFG_MCTM0) + if (TMx == HT_MCTM0) + { + wTmpMask = ~(0x3ul << bChPos); + } + else + #endif + { + wTmpMask = ~(0x1ul << bChPos); + } + +#if (LIBCFG_PWM_8_CHANNEL) + if ((OutInit->Channel > TM_CH_3) && (OutInit->Channel <= TM_CH_7) ) + { + u8 bOffset = OutInit->Channel - 4; + pOcfr = (vu32*)&TMx->CH4OCFR + bOffset; + pCcr = (vu32*)&TMx->CH4CR + bOffset; + } +#endif + + /* Check the parameters */ + Assert_Param(IS_TM(TMx)); + Assert_Param(IS_TM_CH(OutInit->Channel)); + Assert_Param(IS_TM_OM(OutInit->OutputMode)); +#if (LIBCFG_PWM_8_CHANNEL) + if ((OutInit->Channel > TM_CH_3) && (OutInit->Channel <= TM_CH_7) ) + { + Assert_Param(IS_TM_OM_NOASYM(OutInit->OutputMode)); + } +#endif + Assert_Param(IS_TM_CHCTL(OutInit->Control)); + Assert_Param(IS_TM_CHP(OutInit->Polarity)); + #if (LIBCFG_MCTM0) + if (TMx == HT_MCTM0) + { + Assert_Param(IS_TM_CHCTL(OutInit->ControlN)); + Assert_Param(IS_TM_CHP(OutInit->PolarityN)); + Assert_Param(IS_MCTM_OIS(OutInit->IdleState)); + Assert_Param(IS_MCTM_OIS(OutInit->IdleStateN)); + } + #endif + + /* Disable the Channel */ + TMx->CHCTR &= wTmpMask; + + /* Set the Output Compare Polarity */ + wTmpReg = TMx->CHPOLR & wTmpMask; + #if (LIBCFG_MCTM0) + if (TMx == HT_MCTM0) + { + wTmpReg |= (u32)(OutInit->Polarity | (OutInit->PolarityN << 1)) << bChPos; + } + else + #endif + { + wTmpReg |= (u32)(OutInit->Polarity) << bChPos; + } + + TMx->CHPOLR = wTmpReg; + + /* Set the Output Idle State */ + #if (LIBCFG_MCTM0) + if (TMx == HT_MCTM0) + { + wTmpReg = TMx->CHBRKCFR & wTmpMask; + wTmpReg |= (u32)(OutInit->IdleState | (OutInit->IdleStateN << 1)) << bChPos; + TMx->CHBRKCFR = wTmpReg; + } + #endif + + /* Select the Output Compare Mode */ + *pOcfr &= CHOCFR_CHOM_MASK; + *pOcfr |= OutInit->OutputMode; + + /* Set the Capture Compare Register value */ + *pCcr = OutInit->Compare; + + /* Set the Asymmetric Compare Register value */ + *pAcr = OutInit->AsymmetricCompare; + + /* Set the channel state */ + #if (LIBCFG_MCTM0) + if (TMx == HT_MCTM0) + { + TMx->CHCTR |= (u32)(OutInit->Control | (OutInit->ControlN << 1)) << bChPos; + } + else + #endif + { + TMx->CHCTR |= (u32)(OutInit->Control) << bChPos; + } +} + +/*********************************************************************************************************//** + * @brief Initialize input capture of the TMx channel. + * @param TMx: where TMx is the selected TM from the TM peripherals. + * @param CapInit: Point to a \ref TM_CaptureInitTypeDef structure that contains the configuration + * information. + * @retval None + ************************************************************************************************************/ +void TM_CaptureInit(HT_TM_TypeDef* TMx, TM_CaptureInitTypeDef* CapInit) +{ + u8 Filter; + /* Check the parameters */ + Assert_Param(IS_TM(TMx)); + Assert_Param(IS_TM_CH(CapInit->Channel)); + Assert_Param(IS_TM_CHP(CapInit->Polarity)); + Assert_Param(IS_TM_CHCCS(CapInit->Selection)); + Assert_Param(IS_TM_CHPSC(CapInit->Prescaler)); + #if (LIBCFG_TM_652XX_V1) + #else + Assert_Param(IS_TM_FILTER(CapInit->Filter)); + #endif + + #if (LIBCFG_TM_652XX_V1) + Filter = FILTER_PROCESS(CapInit); + #else + Filter = CapInit->Filter; + #endif + _TM_CHx_Config(TMx, CapInit->Channel, CapInit->Polarity, CapInit->Selection, Filter); + + /* Set the Input Capture Prescaler value */ + TM_CHPSCConfig(TMx, CapInit->Channel, CapInit->Prescaler); +} + +/*********************************************************************************************************//** + * @brief Configure the TMx to measure an external PWM signal. + * @param TMx: where TMx is the selected TM from the TM peripherals. + * @param CapInit: Point to a \ref TM_CaptureInitTypeDef structure that contains the configuration + * information. + * @retval None + * @note The CapInit->Channel can only be TM_CH_0 or TM_CH_1. CH2/CH3 are not supported since it cannot be + * the STI source to reset the counter. + ************************************************************************************************************/ +void TM_PwmInputInit(HT_TM_TypeDef* TMx, TM_CaptureInitTypeDef* CapInit) +{ + u8 Filter; + TM_CHP_Enum OppositePol; + TM_CHCCS_Enum OppositeSel; + TM_CH_Enum OppositeChannel; + + /* Check the parameters */ + Assert_Param(IS_TM(TMx)); + Assert_Param(IS_TM_CH_PWMI(CapInit->Channel)); + Assert_Param(IS_TM_CHP(CapInit->Polarity)); + Assert_Param(IS_TM_CHCCS(CapInit->Selection)); + Assert_Param(IS_TM_CHPSC(CapInit->Prescaler)); + #if (LIBCFG_TM_652XX_V1) + #else + Assert_Param(IS_TM_FILTER(CapInit->Filter)); + #endif + + /* Select the Opposite Input Polarity */ + if (CapInit->Polarity == TM_CHP_NONINVERTED) + { + OppositePol = TM_CHP_INVERTED; + } + else + { + OppositePol = TM_CHP_NONINVERTED; + } + + /* Select the Opposite Input */ + if (CapInit->Selection == TM_CHCCS_DIRECT) + { + OppositeSel = TM_CHCCS_INDIRECT; + } + else + { + OppositeSel = TM_CHCCS_DIRECT; + } + + /* Can only be TM_CH_0 or TM_CH_1. CH2/CH3 are not supported since it cannot be the STI source to */ + /* reset the counter */ + if (CapInit->Channel == TM_CH_0) + { + OppositeChannel = TM_CH_1; + } + else + { + OppositeChannel = TM_CH_0; + } + + #if (LIBCFG_TM_652XX_V1) + Filter = FILTER_PROCESS(CapInit); + #else + Filter = CapInit->Filter; + #endif + + /* Capture Channel Configuration */ + _TM_CHx_Config(TMx, CapInit->Channel, CapInit->Polarity, CapInit->Selection, Filter); + + /* Set the Input Capture Prescaler value */ + TM_CHPSCConfig(TMx, CapInit->Channel, CapInit->Prescaler); + + /* Opposite Channel Configuration */ + _TM_CHx_Config(TMx, OppositeChannel, OppositePol, OppositeSel, Filter); + + /* Set the Input Capture Prescaler value */ + TM_CHPSCConfig(TMx, OppositeChannel, CapInit->Prescaler); +} + +/*********************************************************************************************************//** + * @brief Fill each TimeBaseInit member with its default value. + * @param TimeBaseInit: Point to a \ref TM_TimeBaseInitTypeDef structure. + * @retval None + ************************************************************************************************************/ +void TM_TimeBaseStructInit(TM_TimeBaseInitTypeDef* TimeBaseInit) +{ + /* Set the default configuration */ + TimeBaseInit->CounterMode = TM_CNT_MODE_UP; + TimeBaseInit->CounterReload = 0xFFFF; + TimeBaseInit->Prescaler = 0x0000; + TimeBaseInit->PSCReloadTime = TM_PSC_RLD_IMMEDIATE; + #if (LIBCFG_MCTM0) + TimeBaseInit->RepetitionCounter = 0; + #endif +} + +/*********************************************************************************************************//** + * @brief Fill each OutInit member with its default value. + * @param OutInit: Point to a \ref TM_OutputInitTypeDef structure. + * @retval None + ************************************************************************************************************/ +void TM_OutputStructInit(TM_OutputInitTypeDef* OutInit) +{ + /* Set the default configuration */ + OutInit->Channel = TM_CH_0; + OutInit->OutputMode = TM_OM_MATCH_NOCHANGE; + OutInit->Control = TM_CHCTL_DISABLE; + OutInit->Polarity = TM_CHP_NONINVERTED; + #if (LIBCFG_MCTM0) + OutInit->ControlN = TM_CHCTL_DISABLE; + OutInit->PolarityN = TM_CHP_NONINVERTED; + OutInit->IdleState = MCTM_OIS_LOW; + OutInit->IdleStateN = MCTM_OIS_LOW; + #endif + OutInit->Compare = 0x0000; + OutInit->AsymmetricCompare = 0x0000; +} + +/*********************************************************************************************************//** + * @brief Fill each CapInit member with its default value. + * @param CapInit: Point to a \ref TM_CaptureInitTypeDef structure. + * @retval None + ************************************************************************************************************/ +void TM_CaptureStructInit(TM_CaptureInitTypeDef* CapInit) +{ + /* Set the default configuration */ + CapInit->Channel = TM_CH_0; + CapInit->Polarity = TM_CHP_NONINVERTED; + CapInit->Selection = TM_CHCCS_DIRECT; + CapInit->Prescaler = TM_CHPSC_OFF; + #if (LIBCFG_TM_652XX_V1) + CapInit->Fsampling = TM_CHFDIV_1; + CapInit->Event = TM_CHFEV_OFF; + #else + CapInit->Filter = 0x00; + #endif +} + +/*********************************************************************************************************//** + * @brief Enable or Disable TMx counter. + * @param TMx: where TMx is the selected TM from the TM peripherals. + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void TM_Cmd(HT_TM_TypeDef* TMx, ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_TM(TMx)); + Assert_Param(IS_CONTROL_STATUS(NewState)); + + if (NewState != DISABLE) + { + /* Enable the TM Counter */ + TMx->CTR |= CTR_TME; + } + else + { + /* Disable the TM Counter */ + TMx->CTR &= ~CTR_TME; + } +} + +#if (LIBCFG_TM_NO_ITI == 1) +#else +/*********************************************************************************************************//** + * @brief Configure external clock mode of the TMx. Used ITIx as the clock source. + * @param TMx: where TMx is the selected TM from the TM peripherals. + * @param Iti: Trigger source. + * This parameter can be one of the following values: + * @arg TM_TRSEL_ITI0: Internal trigger 0 + * @arg TM_TRSEL_ITI1: Internal trigger 1 + * @arg TM_TRSEL_ITI2: Internal trigger 2 + * @retval None + ************************************************************************************************************/ +void TM_ItiExternalClockConfig(HT_TM_TypeDef* TMx, TM_TRSEL_Enum Iti) +{ + /* Check the parameters */ + Assert_Param(IS_TM(TMx)); + Assert_Param(IS_TM_ITI(Iti)); + + /* Select the Internal Trigger. Slave mode will be disable in this function */ + TM_StiConfig(TMx, Iti); + + /* Select the STIED as external clock source */ + TMx->MDCFR |= TM_SMSEL_STIED; +} +#endif + +/*********************************************************************************************************//** + * @brief Configure external clock mode of the TMx. Used CHx as the clock source. + * @param TMx: where TMx is the selected TM from the TM peripherals. + * @param Sel: Specify the channel source. + * This parameter can be one of the following values: + * @arg TM_TRSEL_TI0BED : TI0 both edge detector + * @arg TM_TRSEL_TI0S0 : Filtered timer input 0 + * @arg TM_TRSEL_TI1S1 : Filtered timer input 1 + * @param Pol: Specify the CHx Polarity. + * This parameter can be one of the following values: + * @arg TM_CHP_NONINVERTED : active high. + * @arg TM_CHP_INVERTED : active low. + * @param Filter: Specify the filter value. + * This parameter must be a value between 0x0 and 0xF. + * @retval None + ************************************************************************************************************/ +void TM_ChExternalClockConfig(HT_TM_TypeDef* TMx, TM_TRSEL_Enum Sel, TM_CHP_Enum Pol, u8 Filter) +{ + /* Check the parameters */ + Assert_Param(IS_TM(TMx)); + Assert_Param(IS_TM_TRSEL_CH(Sel)); + Assert_Param(IS_TM_CHP(Pol)); + #if (LIBCFG_TM_652XX_V1) + #else + Assert_Param(IS_TM_FILTER(Filter)); + #endif + + /* Configure the Timer Input Clock Source */ + if (Sel == TM_TRSEL_TI1S1) + { + _TM_CHx_Config(TMx, TM_CH_1, Pol, TM_CHCCS_DIRECT, Filter); + } + else + { + _TM_CHx_Config(TMx, TM_CH_0, Pol, TM_CHCCS_DIRECT, Filter); + } + + /* Select the external clock source. Slave mode will be disable in this function */ + TM_StiConfig(TMx, Sel); + + /* Select the STIED as external clock source */ + TMx->MDCFR |= TM_SMSEL_STIED; +} + +#if 0 +/*********************************************************************************************************//** + * @brief Configure external clock mode of the TMx. Used ETI as the clock source. + * @param TMx: where TMx is the selected TM from the TM peripheral. + * @param Psc: The external Trigger Prescaler. + * It can be one of the following values: + * @arg TM_ETIPSC_OFF : ETI prescaler off + * @arg TM_ETIPSC_2 : ETIP frequency divided by 2 + * @arg TM_ETIPSC_4 : ETIP frequency divided by 4 + * @arg TM_ETIPSC_8 : ETIP frequency divided by 8 + * @param Pol: The external trigger input polarity. + * It can be one of the following values: + * @arg TM_ETIPOL_NONINVERTED : Active high level or rising edge + * @arg TM_ETIPOL_INVERTED : Active low level or falling edge + * @param Filter: Filter for ETI input. + * This parameter must be a value between 0x00 and 0x0F + * @retval None + ************************************************************************************************************/ +void TM_EtiExternalClockConfig(HT_TM_TypeDef* TMx, TM_ETIPSC_Enum Psc, TM_ETIPOL_Enum Pol, u8 Filter) +{ + /* Check the parameters */ + Assert_Param(IS_TM(TMx)); + Assert_Param(IS_TM_ETIPSC(Psc)); + Assert_Param(IS_TM_ETIPOL(Pol)); + Assert_Param(IS_TM_FILTER(Filter)); + + /* Configure the ETI Clock source */ + TM_EtiConfig(TMx, Psc, Pol, Filter); + + /* Enable the external clock mode */ + TMx->TRCFR |= TRCFR_ECME; +} + +/*********************************************************************************************************//** + * @brief Configure external trigger input (ETI) of the TMx. + * @param TMx: where TMx is the selected TM from the TM peripheral. + * @param Psc: The external Trigger Prescaler. + * It can be one of the following values: + * @arg TM_ETIPSC_OFF : ETI prescaler off + * @arg TM_ETIPSC_2 : ETIP frequency divided by 2 + * @arg TM_ETIPSC_4 : ETIP frequency divided by 4 + * @arg TM_ETIPSC_8 : ETIP frequency divided by 8 + * @param Pol: The external trigger input polarity. + * It can be one of the following values: + * @arg TM_ETIPOL_NONINVERTED : Active high level or rising edge + * @arg TM_ETIPOL_INVERTED : Active low level or falling edge + * @param Filter: Filter for ETI input. + * This parameter must be a value between 0x00 and 0x0F + * @retval None + ************************************************************************************************************/ +void TM_EtiConfig(HT_TM_TypeDef* TMx, TM_ETIPSC_Enum Psc, TM_ETIPOL_Enum Pol, u8 Filter) +{ + u32 wTrcfr; + + /* Check the parameters */ + Assert_Param(IS_TM(TMx)); + Assert_Param(IS_TM_ETIPSC(Psc)); + Assert_Param(IS_TM_ETIPOL(Pol)); + Assert_Param(IS_TM_FILTER(Filter)); + + /* Get TRCFR value with cleared ETI configuration bits */ + wTrcfr = TMx->TRCFR & TRCFR_ETI_CONF_MASK; + + /* Set the prescaler, filter and polarity for ETI input */ + wTrcfr |= (u32)Psc | Pol | ((u32)Filter << 8); + + /* Write to TMx TRCFR */ + TMx->TRCFR = wTrcfr; +} +#endif + +/*********************************************************************************************************//** + * @brief Configure prescaler of the TMx. + * @param TMx: where TMx is the selected TM from the TM peripherals. + * @param Psc: Specify the prescaler value. + * @param PscReloadTime: Specify the TM prescaler reload time. + * This parameter can be one of the following values: + * @arg TM_PSC_RLD_UPDATE : The prescaler is loaded at the next update event. + * @arg TM_PSC_RLD_IMMEDIATE : The prescaler is loaded immediatly. + * @retval None + ************************************************************************************************************/ +void TM_PrescalerConfig(HT_TM_TypeDef* TMx, u16 Psc, TM_PSC_RLD_Enum PscReloadTime) +{ + /* Check the parameters */ + Assert_Param(IS_TM(TMx)); + Assert_Param(IS_TM_PSC_RLD(PscReloadTime)); + + /* Set the prescaler value */ + TMx->PSCR = Psc; + + /* Set the UEVG bit or not */ + TMx->EVGR = PscReloadTime; +} + +/*********************************************************************************************************//** + * @brief Configure counter mode of the TMx. + * @param TMx: where TMx is the selected TM from the TM peripherals. + * @param Mod: Specify the counter mode to be used. + * This parameter can be one of the following values: + * @arg TM_CNT_MODE_UP : TM up counting mode. + * @arg TM_CNT_MODE_DOWN : TM down counting mode. + * @arg TM_CNT_MODE_CA1 : TM center aligned mode 1. + * @arg TM_CNT_MODE_CA2 : TM center aligned mode 2. + * @arg TM_CNT_MODE_CA3 : TM center aligned mode 3. + * @retval None + ************************************************************************************************************/ +void TM_CounterModeConfig(HT_TM_TypeDef* TMx, TM_CNT_MODE_Enum Mod) +{ + /* Check the parameters */ + Assert_Param(IS_TM(TMx)); + Assert_Param(IS_TM_CNT_MODE(Mod)); + + /* Reset the CMSEL and DIR Bits */ + TMx->CNTCFR &= CNTCFR_CMSEL_MASK; /* CNTCFR_DIR is read only when the timer configured as */ + TMx->CNTCFR &= ~(u32)CNTCFR_DIR; /* Center-aligned mode. Reset mode first and then reset the */ + /* CNTCFR_DIR bit (separate as two steps). */ + + /* Set the Counter Mode */ + TMx->CNTCFR |= Mod; +} + +/*********************************************************************************************************//** + * @brief Select the STI source. + * @param TMx: where TMx is the selected TM from the TM peripherals. + * @param Sel: Specify the STI source. + * This parameter can be one of the following: + * @arg TM_TRSEL_ITI0 : Internal trigger 0. + * @arg TM_TRSEL_ITI1 : Internal trigger 1. + * @arg TM_TRSEL_ITI2 : Internal trigger 2. + * @arg TM_TRSEL_TI0BED : TI0 both edge detector. + * @arg TM_TRSEL_TI0S0 : Filtered channel 0 input. + * @arg TM_TRSEL_TI1S1 : Filtered channel 1 input. + * @arg TM_TRSEL_ETIF : External trigger input. + * @arg TM_TRSEL_UEVG : Trigger by setting UEVG bit. + * @retval None + ************************************************************************************************************/ +void TM_StiConfig(HT_TM_TypeDef* TMx, TM_TRSEL_Enum Sel) +{ + u32 wTrcfr; + + /* Check the parameters */ + Assert_Param(IS_TM(TMx)); + Assert_Param(IS_TM_TRSEL(Sel)); + + /* Disable slave mode */ + TMx->MDCFR &= MDCFR_SMSEL_MASK; + + /* Get the TRCFR value with cleared TRSEL */ + wTrcfr = TMx->TRCFR & TRCFR_TRSEL_MASK; + + /* Set the STI source */ + TMx->TRCFR |= wTrcfr | Sel; +} + +/*********************************************************************************************************//** + * @brief Configure encoder interface of the TMx. + * @param TMx: where TMx is the selected TM from the TM peripherals. + * @param DecoderMod: Specify the TMx decoder mode. + * This parameter can be one of the following values: + * @arg TM_SMSEL_DECODER1 : Counter counts on CH0 edge depending on CH1 level. + * @arg TM_SMSEL_DECODER2 : Counter counts on CH1 edge depending on CH0 level. + * @arg TM_SMSEL_DECODER3 : Counter counts on both CH0 and CH1 edges depending on + * the level of the other input. + * @param CH0P: Specify the CH0 polarity. + * This parameter can be one of the following values: + * @arg TM_CHP_NONINVERTED : Active high level or rising edge + * @arg TM_CHP_INVERTED : Active low level or falling edge + * @param CH1P: Specify the CH1 polarity. + * This parameter can be one of the following values: + * @arg TM_CHP_NONINVERTED : Active high level or rising edge + * @arg TM_CHP_INVERTED : Active low level or falling edge + * @retval None + ************************************************************************************************************/ +void TM_DecoderConfig(HT_TM_TypeDef* TMx, TM_SMSEL_Enum DecoderMod, TM_CHP_Enum CH0P, TM_CHP_Enum CH1P) +{ + u32 wMdcfr, wCh0Icfr, wCh1Icfr, wChpolr; + + /* Check the parameters */ + Assert_Param(IS_TM(TMx)); + Assert_Param(IS_TM_SMSEL_DECODER(DecoderMod)); + Assert_Param(IS_TM_CHP(CH0P)); + Assert_Param(IS_TM_CHP(CH1P)); + + /* Get the TMx MDCFR register value */ + wMdcfr = TMx->MDCFR; + + /* Get the TMx CH0ICFR & CH1ICFR register value */ + wCh0Icfr = TMx->CH0ICFR; + wCh1Icfr = TMx->CH1ICFR; + + /* Get the TMx CHPOLR register value */ + wChpolr = TMx->CHPOLR; + + /* Set the decoder mode */ + wMdcfr &= MDCFR_SMSEL_MASK; + wMdcfr |= DecoderMod; + + /* Select the channel 0 and the channel 1 as input and clear CH0SRC */ + wCh0Icfr &= CHICFR_CHCCS_MASK & (~CH0ICFR_CH0SRC); + wCh1Icfr &= CHICFR_CHCCS_MASK; + wCh0Icfr |= TM_CHCCS_DIRECT; + wCh1Icfr |= TM_CHCCS_DIRECT; + + /* Set the CH0 and the CH1 polarities */ + wChpolr &= ~(CHPOLR_CH0P | CHPOLR_CH1P); + wChpolr |= (CH0P | (CH1P << 2)); + + /* Write to TMx MDCFR */ + TMx->MDCFR = wMdcfr; + + /* Write to TMx CH0ICFR & CH1ICFR */ + TMx->CH0ICFR = wCh0Icfr; + TMx->CH1ICFR = wCh1Icfr; + + /* Write to TMx CHPOLR */ + TMx->CHPOLR = wChpolr; +} + +/*********************************************************************************************************//** + * @brief Force the TMx CHnOREF waveform to active or inactive level. + * @param TMx: where TMx is the selected TM from the TM peripherals. + * @param TM_CH_n: Specify the TM channel. + * This parameter can be one of the following values: + * @arg TM_CH_0 : TM channel 0 + * @arg TM_CH_1 : TM channel 1 + * @arg TM_CH_2 : TM channel 2 + * @arg TM_CH_3 : TM channel 3 + * @arg TM_CH_4 : TM channel 4 + * @arg TM_CH_5 : TM channel 5 + * @arg TM_CH_6 : TM channel 6 + * @arg TM_CH_7 : TM channel 7 + * @param ForcedAction: Specify the forced action to be set to the output waveform. + * This parameter can be one of the following values: + * @arg TM_OM_FORCED_ACTIVE : Forced active level on CH0OREF + * @arg TM_OM_FORCED_INACTIVE : Forced inactive level on CH0OREF. + * @retval None + ************************************************************************************************************/ +void TM_ForcedOREF(HT_TM_TypeDef* TMx, TM_CH_Enum TM_CH_n, TM_OM_Enum ForcedAction) +{ + vu32* pCHnOCFR = ((vu32*)&TMx->CH0OCFR) + (TM_CH_n * 1); +#if (LIBCFG_PWM_8_CHANNEL) + if ((TM_CH_n > TM_CH_3) && (TM_CH_n <= TM_CH_7) ) + { + pCHnOCFR = ((vu32*)&TMx->CH4OCFR) + ((TM_CH_n -4) * 1); + } +#endif + + /* Check the parameters */ + Assert_Param(IS_TM(TMx)); + Assert_Param(IS_TM_CH(TM_CH_n)); + Assert_Param(IS_TM_OM_FORCED(ForcedAction)); + + /* Configure The forced output mode */ + *pCHnOCFR = (*pCHnOCFR & CHOCFR_CHOM_MASK) | ForcedAction; +} + +/*********************************************************************************************************//** + * @brief Enable or Disable the TMx CRR preload function. + * @param TMx: where TMx is the selected TM from the TM peripheral. + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void TM_CRRPreloadCmd(HT_TM_TypeDef* TMx, ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_TM(TMx)); + Assert_Param(IS_CONTROL_STATUS(NewState)); + + if (NewState != DISABLE) + { + /* Set the CRR preload control bit */ + TMx->CTR |= CTR_CRBE; + } + else + { + /* Reset the CRR preload control bit */ + TMx->CTR &= ~CTR_CRBE; + } +} + +/*********************************************************************************************************//** + * @brief Enable or Disable the TMx CHxCCR preload function. + * @param TMx: where TMx is the selected TM from the TM peripherals. + * @param Channel: Specify the TM channel. + * This parameter can be one of the following values: + * @arg TM_CH_0 : TM channel 0 + * @arg TM_CH_1 : TM channel 1 + * @arg TM_CH_2 : TM channel 2 + * @arg TM_CH_3 : TM channel 3 + * @arg TM_CH_4 : TM channel 4 + * @arg TM_CH_5 : TM channel 5 + * @arg TM_CH_6 : TM channel 6 + * @arg TM_CH_7 : TM channel 7 + * @param NewState This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void TM_CHCCRPreloadConfig(HT_TM_TypeDef* TMx, TM_CH_Enum Channel, ControlStatus NewState) +{ + vu32 *pOcfr = (vu32*)&TMx->CH0OCFR + Channel; + + /* Check the parameters */ + Assert_Param(IS_TM(TMx)); + Assert_Param(IS_TM_CH(Channel)); + Assert_Param(IS_CONTROL_STATUS(NewState)); +#if (LIBCFG_PWM_8_CHANNEL) + if ((Channel > TM_CH_3) && (Channel <= TM_CH_7)) + { + u8 bOffset = Channel - 4; + pOcfr = (vu32*)&TMx->CH4OCFR + bOffset; + } +#endif + /* Enable or disable the channel N CCR preload feature */ + if (NewState != DISABLE) + { + *pOcfr |= CHOCFR_CHPRE; + } + else + { + *pOcfr &= ~CHOCFR_CHPRE; + } +} + +/*********************************************************************************************************//** + * @brief Clear or Safeguard the CHxOREF signal when ETI is active. + * @param TMx: where TMx is the selected TM from the TM peripheral. + * @param Channel: Specify the TM channel. + * This parameter can be one of the following values: + * @arg TM_CH_0 : TM channel 0 + * @arg TM_CH_1 : TM channel 1 + * @arg TM_CH_2 : TM channel 2 + * @arg TM_CH_3 : TM channel 3 + * @param NewState This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void TM_ClearOREFConfig(HT_TM_TypeDef* TMx, TM_CH_Enum Channel, ControlStatus NewState) +{ + vu32 *pOcfr = (vu32*)&TMx->CH0OCFR + Channel; + + /* Check the parameters */ + Assert_Param(IS_TM(TMx)); + Assert_Param(IS_TM_CH(Channel)); + Assert_Param(IS_CONTROL_STATUS(NewState)); + + /* Enable or Disable the channel N clear Oref at ETI active function */ + if (NewState != DISABLE) + { + *pOcfr |= CHOCFR_REFCE; + } + else + { + *pOcfr &= ~CHOCFR_REFCE; + } +} + +/*********************************************************************************************************//** + * @brief Configure polarity of the TMx channel N. + * @param TMx: where TMx is the selected TM from the TM peripherals. + * @param Channel: Specify the TM channel. + * This parameter can be one of the following values: + * @arg TM_CH_0 : TM channel 0 + * @arg TM_CH_1 : TM channel 1 + * @arg TM_CH_2 : TM channel 2 + * @arg TM_CH_3 : TM channel 3 + * @arg TM_CH_4 : TM channel 4 + * @arg TM_CH_5 : TM channel 5 + * @arg TM_CH_6 : TM channel 6 + * @arg TM_CH_7 : TM channel 7 + * @param Pol: Specify the polarity of channel N. + * This parameter can be one of the following values: + * @arg TM_CHP_NONINVERTED : active high + * @arg TM_CHP_INVERTED : active low + * @retval None + ************************************************************************************************************/ +void TM_ChPolarityConfig(HT_TM_TypeDef* TMx, TM_CH_Enum Channel, TM_CHP_Enum Pol) +{ + u32 wChpolr; + + /* Check the parameters */ + Assert_Param(IS_TM(TMx)); + Assert_Param(IS_TM_CH(Channel)); + Assert_Param(IS_TM_CHP(Pol)); + + /* Set or reset the CHx polarity */ + wChpolr = TMx->CHPOLR & (~(u32)(0x1 << (Channel << 1))); + TMx->CHPOLR = wChpolr | (Pol << (Channel << 1)); +} + +/*********************************************************************************************************//** + * @brief Enable or Disable the single pulse immediate active function. + * @param TMx: where TMx is the selected TM from the TM peripherals. + * @param Channel: Specify the TM channel. + * This parameter can be one of the following values: + * @arg TM_CH_0 : TM channel 0 + * @arg TM_CH_1 : TM channel 1 + * @arg TM_CH_2 : TM channel 2 + * @arg TM_CH_3 : TM channel 3 + * @arg TM_CH_4 : TM channel 4 + * @arg TM_CH_5 : TM channel 5 + * @arg TM_CH_6 : TM channel 6 + * @arg TM_CH_7 : TM channel 7 + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + * @note Must configure output mode to PWM1 or PWM2 before invoke this function. + ************************************************************************************************************/ +void TM_ImmActiveConfig(HT_TM_TypeDef* TMx, TM_CH_Enum Channel, ControlStatus NewState) +{ + vu32 *pOcfr = (vu32*)&TMx->CH0OCFR + Channel; + +#if (LIBCFG_PWM_8_CHANNEL) + if ((Channel > TM_CH_3) && (Channel <= TM_CH_7) ) + { + u8 bOffset = Channel - 4; + pOcfr = (vu32*)&TMx->CH4OCFR + bOffset; + } +#endif + /* Check the parameters */ + Assert_Param(IS_TM(TMx)); + Assert_Param(IS_TM_CH(Channel)); + Assert_Param(IS_CONTROL_STATUS(NewState)); + + /* Enable or disable the channel N clear CHxOREF at ETI active function */ + if (NewState != DISABLE) + { + *pOcfr |= CHOCFR_IMAE; + } + else + { + *pOcfr &= ~CHOCFR_IMAE; + } +} + +/*********************************************************************************************************//** + * @brief Enable or Disable the TMx channel N. + * @param TMx: where TMx is the selected TM from the TM peripherals. + * @param Channel: Specify the TM channel. + * This parameter can be one of the following values: + * @arg TM_CH_0 : TM channel 0 + * @arg TM_CH_1 : TM channel 1 + * @arg TM_CH_2 : TM channel 2 + * @arg TM_CH_3 : TM channel 3 + * @arg TM_CH_4 : TM channel 4 + * @arg TM_CH_5 : TM channel 5 + * @arg TM_CH_6 : TM channel 6 + * @arg TM_CH_7 : TM channel 7 + * @param Control: This parameter can be TM_CHCTL_ENABLE or TM_CHCTL_DISABLE. + * @retval None + ************************************************************************************************************/ +void TM_ChannelConfig(HT_TM_TypeDef* TMx, TM_CH_Enum Channel, TM_CHCTL_Enum Control) +{ + /* Check the parameters */ + Assert_Param(IS_TM(TMx)); + Assert_Param(IS_TM_CH(Channel)); + Assert_Param(IS_TM_CHCTL(Control)); + + /* Reset the CHxE Bit */ + TMx->CHCTR &= ~(u32)(0x1 << (Channel << 1)); + + /* Set or reset the CHxE Bit */ + TMx->CHCTR |= (u32)Control << (Channel << 1); +} + +/*********************************************************************************************************//** + * @brief Configure output mode of the TMx. + * @param TMx: where TMx is the selected TM from the TM peripherals. + * @param Channel: Specify the TM channel. + * This parameter can be one of the following values: + * @arg TM_CH_0 : TM channel 0 + * @arg TM_CH_1 : TM channel 1 + * @arg TM_CH_2 : TM channel 2 + * @arg TM_CH_3 : TM channel 3 + * @arg TM_CH_4 : TM channel 4 + * @arg TM_CH_5 : TM channel 5 + * @arg TM_CH_6 : TM channel 6 + * @arg TM_CH_7 : TM channel 7 + * @param Mod: Specify the TM output mode. + * This parameter can be one of the following values: + * @arg TM_OM_MATCH_NOCHANGE : Output dont change on match + * @arg TM_OM_MATCH_INACTIVE : Output inactive on compare match + * @arg TM_OM_MATCH_ACTIVE : Output active on compare match + * @arg TM_OM_MATCH_TOGGLE : Output toggle on compare match + * @arg TM_OM_FORCED_INACTIVE : Output forced inactive + * @arg TM_OM_FORCED_ACTIVE : Output forced active + * @arg TM_OM_PWM1 : PWM1 mode + * @arg TM_OM_PWM2 : PWM2 mode + * @arg TM_OM_ASYMMETRIC_PWM1 : Asymmetric PWM1 mode + * @arg TM_OM_ASYMMETRIC_PWM2 : Asymmetric PWM2 mode + * @retval None + * @note This function disables the selected channel before changing the output mode. + ************************************************************************************************************/ +void TM_OutputModeConfig(HT_TM_TypeDef* TMx, TM_CH_Enum Channel, TM_OM_Enum Mod) +{ + vu32 *pOcfr = (vu32*)&TMx->CH0OCFR + Channel; + +#if (LIBCFG_PWM_8_CHANNEL) + if ((Channel > TM_CH_3) && (Channel <= TM_CH_7) ) + { + u8 bOffset = Channel - 4; + pOcfr = (vu32*)&TMx->CH4OCFR + bOffset; + } +#endif + /* Check the parameters */ + Assert_Param(IS_TM(TMx)); + Assert_Param(IS_TM_CH(Channel)); + Assert_Param(IS_TM_OM(Mod)); +#if (LIBCFG_PWM_8_CHANNEL) + if ((Channel > TM_CH_3) && (Channel <= TM_CH_7) ) + { + Assert_Param(IS_TM_OM_NOASYM(Mod)); + } +#endif + + /* Disable the channel: Reset the CHxE Bit */ + TMx->CHCTR &= ~(u32)(0x1 << (Channel << 1)); + + /* Selects the TM output mode */ + *pOcfr = (*pOcfr & CHOCFR_CHOM_MASK) | Mod; +} + +/*********************************************************************************************************//** + * @brief Enable or Disable update event of the TMx. + * @param TMx: where TMx is the selected TM from the TM peripherals. + * @param NewState: This parameter can be ENABLE (default) or DISABLE. + * @retval None + ************************************************************************************************************/ +void TM_UpdateCmd(HT_TM_TypeDef* TMx, ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_TM(TMx)); + Assert_Param(IS_CONTROL_STATUS(NewState)); + + if (NewState == DISABLE) + { + /* Set the update disable bit */ + TMx->CNTCFR |= CNTCFR_UEVDIS; + } + else + { + /* Reset the update disable bit */ + TMx->CNTCFR &= ~CNTCFR_UEVDIS; + } +} + +/*********************************************************************************************************//** + * @brief Configure UEVG interrupt function of the TMx. + * @param TMx: where TMx is the selected TM from the TM peripherals. + * @param NewState: This parameter can be one of the following value: + * @arg ENABLE : Default value. Any of the following events will generate an update event interrupt: + * - Counter overflow/underflow + * - Setting the UEVG bit + * - Update generation through the slave restart mode + * @arg DISABLE : Only counter overflow/underflow generations an update event interrupt. + * @retval None + ************************************************************************************************************/ +void TM_UEVG_IntConfig(HT_TM_TypeDef* TMx, ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_TM(TMx)); + Assert_Param(IS_CONTROL_STATUS(NewState)); + + if (NewState == DISABLE) + { + /* Set the UEVG interrupt disable bit */ + TMx->CNTCFR |= CNTCFR_UGDIS; + } + else + { + /* Reset the UEVG interrupt disable bit */ + TMx->CNTCFR &= ~CNTCFR_UGDIS; + } +} + +/*********************************************************************************************************//** + * @brief Enable or Disable hall sensor interface of the TMx. + * @param TMx: where TMx is the selected TM from the TM peripherals. + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void TM_HallInterfaceCmd(HT_TM_TypeDef* TMx, ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_TM(TMx)); + Assert_Param(IS_CONTROL_STATUS(NewState)); + + if (NewState != DISABLE) + { + /* Set the CH0SRC Bit */ + TMx->CH0ICFR |= CH0ICFR_CH0SRC; + } + else + { + /* Reset the CH0SRC Bit */ + TMx->CH0ICFR &= ~CH0ICFR_CH0SRC; + } +} + +/*********************************************************************************************************//** + * @brief Select single pulse mode of the TMx. + * @param TMx: where TMx is the selected TM from the TM peripherals. + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void TM_SinglePulseModeCmd(HT_TM_TypeDef* TMx, ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_TM(TMx)); + Assert_Param(IS_CONTROL_STATUS(NewState)); + + if (NewState != DISABLE) + { + TMx->MDCFR |= MDCFR_SPMSET; + } + else + { + TMx->MDCFR &= ~MDCFR_SPMSET; + } +} + +/*********************************************************************************************************//** + * @brief Select master trigger output source of the TMx. + * @param TMx: where TMx is the selected TM from the TM peripherals. + * @param Sel: Specify the master trigger output source. + * This parameter can be as follow: + * @arg TM_MMSEL_RESET : Send trigger signal when S/W setting UEVG or slave restart + * @arg TM_MMSEL_ENABLE : The counter enable signal is used as trigger output. + * @arg TM_MMSEL_UPDATE : The update event is used as trigger output. + * @arg TM_MMSEL_CH0CC : Channel 0 capture or compare match occurred as trigger output. + * @arg TM_MMSEL_CH0OREF : The CH0OREF signal is used as trigger output. + * @arg TM_MMSEL_CH1OREF : The CH1OREF signal is used as trigger output. + * @arg TM_MMSEL_CH2OREF : The CH2OREF signal is used as trigger output. + * @arg TM_MMSEL_CH3OREF : The CH3OREF signal is used as trigger output. + * @arg TM_MMSEL_CH4OREF : The CH4OREF signal is used as trigger output. + * @arg TM_MMSEL_CH5OREF : The CH5OREF signal is used as trigger output. + * @arg TM_MMSEL_CH6OREF : The CH6OREF signal is used as trigger output. + * @arg TM_MMSEL_CH7OREF : The CH7OREF signal is used as trigger output. + * @retval None + ************************************************************************************************************/ +void TM_MMSELConfig(HT_TM_TypeDef* TMx, TM_MMSEL_Enum Sel) +{ + /* Check the parameters */ + Assert_Param(IS_TM(TMx)); + Assert_Param(IS_TM_MMSEL(Sel)); + + /* Select the MTO source */ + TMx->MDCFR = (TMx->MDCFR & MDCFR_MMSEL_MASK) | Sel; +} + +/*********************************************************************************************************//** + * @brief Select slave mode of the TMx. + * @param TMx: where TMx is the selected TM from the TM peripherals. + * @param Sel: Specify the timer slave mode. + * This parameter can be one of the following values: + * @arg TM_SMSEL_RESTART : Slave restart counter mode. + * @arg TM_SMSEL_PAUSE : Slave pause counter mode. + * @arg TM_SMSEL_TRIGGER : Slave trigger counter start mode. + * @arg TM_SMSEL_STIED : Used rising edge of STI as prescaler clock source. + * @retval None + ************************************************************************************************************/ +void TM_SlaveModeConfig(HT_TM_TypeDef* TMx, TM_SMSEL_Enum Sel) +{ + /* Check the parameters */ + Assert_Param(IS_TM(TMx)); + Assert_Param(IS_TM_SLAVE_MODE(Sel)); + + /* Select the slave mode */ + TMx->MDCFR = (TMx->MDCFR & MDCFR_SMSEL_MASK) | Sel; +} + +/*********************************************************************************************************//** + * @brief Enable or Disable the master & slave TMx synchronous function. + * @param TMx: where TMx is the selected TM from the TM peripherals. + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void TM_TimSyncCmd(HT_TM_TypeDef* TMx, ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_TM(TMx)); + Assert_Param(IS_CONTROL_STATUS(NewState)); + + if (NewState != DISABLE) + { + /* Set the TSE Bit */ + TMx->MDCFR |= MDCFR_TSE; + } + else + { + /* Reset the TSE Bit */ + TMx->MDCFR &= ~MDCFR_TSE; + } +} + +/*********************************************************************************************************//** + * @brief Set counter register value of the TMx. + * @param TMx: where TMx is the selected TM from the TM peripherals. + * @param Counter: Specify the counter register new value. + * @retval None + ************************************************************************************************************/ +void TM_SetCounter(HT_TM_TypeDef* TMx, u16 Counter) +{ + /* Check the parameters */ + Assert_Param(IS_TM(TMx)); + + /* Set the Counter Register value */ + TMx->CNTR = Counter; +} + +/*********************************************************************************************************//** + * @brief Set counter reload register value of the TMx. + * @param TMx: where TMx is the selected TM from the TM peripherals. + * @param Reload: Specify the counter reload register new value. + * @retval None + ************************************************************************************************************/ +void TM_SetCounterReload(HT_TM_TypeDef* TMx, u16 Reload) +{ + /* Check the parameters */ + Assert_Param(IS_TM(TMx)); + + /* Set the counter reload register value */ + TMx->CRR = Reload; +} + +/*********************************************************************************************************//** + * @brief Set channel n capture/compare register value of the TMx. + * @param TMx: where TMx is the selected TM from the TM peripherals. + * @param TM_CH_n: Specify the TM channel. + * This parameter can be one of the following values: + * @arg TM_CH_0 : TM channel 0 + * @arg TM_CH_1 : TM channel 1 + * @arg TM_CH_2 : TM channel 2 + * @arg TM_CH_3 : TM channel 3 + * @arg TM_CH_4 : TM channel 4 + * @arg TM_CH_5 : TM channel 5 + * @arg TM_CH_6 : TM channel 6 + * @arg TM_CH_7 : TM channel 7 + * @param Cmp: Specify the CH0CCR register new value. + * @retval None + ************************************************************************************************************/ +void TM_SetCaptureCompare(HT_TM_TypeDef* TMx, TM_CH_Enum TM_CH_n, u16 Cmp) +{ + vu32* pCHnCCR = ((vu32*)&TMx->CH0CCR) + (TM_CH_n * 1); + #if (LIBCFG_PWM_8_CHANNEL) + if ((TM_CH_n > TM_CH_3) && (TM_CH_n <= TM_CH_7) ) + { + pCHnCCR = ((vu32*)&TMx->CH4CR) + ((TM_CH_n - 4) * 1); + } + #endif + /* Check the parameters */ + Assert_Param(IS_TM(TMx)); + Assert_Param(IS_TM_CH(TM_CH_n)); + + /* Set the CHnCCR register new value */ + *pCHnCCR = Cmp; +} + +/*********************************************************************************************************//** + * @brief Set channel n asymmetric compare register value of the TMx. + * @param TMx: where TMx is the selected TM from the TM peripherals. + * @param TM_CH_n: Specify the TM channel. + * This parameter can be one of the following values: + * @arg TM_CH_0 : TM channel 0 + * @arg TM_CH_1 : TM channel 1 + * @arg TM_CH_2 : TM channel 2 + * @arg TM_CH_3 : TM channel 3 + * @param Cmp: Specify the CH0ACR register new value. + * @retval None + ************************************************************************************************************/ +void TM_SetAsymmetricCompare(HT_TM_TypeDef* TMx, TM_CH_Enum TM_CH_n, u16 Cmp) +{ + vu32* pCHnACR = ((vu32*)&TMx->CH0ACR) + (TM_CH_n * 1); + + /* Check the parameters */ + Assert_Param(IS_TM(TMx)); + Assert_Param(IS_TM_CH(TM_CH_n)); + + /* Set the CHnACR register new value */ + *pCHnACR = Cmp; +} + +/*********************************************************************************************************//** + * @brief Configure input capture prescaler. + * @param TMx: where TMx is the selected TM from the TM peripherals. + * @param Channel: Specify the TM channel. + * This parameter can be one of the following values: + * @arg TM_CH_0 : TM channel 0 + * @arg TM_CH_1 : TM channel 1 + * @arg TM_CH_2 : TM channel 2 + * @arg TM_CH_3 : TM channel 3 + * @param Psc: Specify the input capture prescaler new value. + * This parameter can be one of the following values: + * @arg TM_CHPSC_OFF : No prescaler + * @arg TM_CHPSC_2 : Capture is done once every 2 events + * @arg TM_CHPSC_4 : Capture is done once every 4 events + * @arg TM_CHPSC_8 : Capture is done once every 8 events + * @retval None + ************************************************************************************************************/ +void TM_CHPSCConfig(HT_TM_TypeDef* TMx, TM_CH_Enum Channel, TM_CHPSC_Enum Psc) +{ + vu32 *pIcfr = (vu32*)&TMx->CH0ICFR + Channel; + + /* Check the parameters */ + Assert_Param(IS_TM(TMx)); + Assert_Param(IS_TM_CH(Channel)); + Assert_Param(IS_TM_CHPSC(Psc)); + + /* Reset the CHxPSC bits */ + *pIcfr &= CHICFR_CHPSC_MASK; + + /* Set the capture input prescaler value */ + *pIcfr |= Psc; +} + +/*********************************************************************************************************//** + * @brief Set clock division value of the TMx. + * @param TMx: where TMx is the selected TM from the TM peripherals. + * @param Div: Specify the clock division value. + * This parameter can be one of the following value: + * @arg TM_CKDIV_OFF : fDTS = fCLKIN + * @arg TM_CKDIV_2 : fDTS = fCLKIN / 2 + * @arg TM_CKDIV_4 : fDTS = fCLKIN / 4 + * @arg TM_CKDIV_8 : fDTS = fCLKIN / 8 + * @retval None + ************************************************************************************************************/ +void TM_CKDIVConfig(HT_TM_TypeDef* TMx, TM_CKDIV_Enum Div) +{ + /* Check the parameters */ + Assert_Param(IS_TM(TMx)); + Assert_Param(IS_TM_CKDIV(Div)); + + /* Reset the CKDIV Bits */ + TMx->CNTCFR &= CNTCFR_CKDIV_MASK; + + /* Set the CKDIV value */ + TMx->CNTCFR |= Div; +} + +/*********************************************************************************************************//** + * @brief Get channel n capture/compare register value of the TMx. + * @param TMx: where TMx is the selected TM from the TM peripherals. + * @param TM_CH_n: Specify the TM channel. + * This parameter can be one of the following values: + * @arg TM_CH_0 : TM channel 0 + * @arg TM_CH_1 : TM channel 1 + * @arg TM_CH_2 : TM channel 2 + * @arg TM_CH_3 : TM channel 3 + * @retval Value of CH0CCR register + ************************************************************************************************************/ +u32 TM_GetCaptureCompare(HT_TM_TypeDef* TMx, TM_CH_Enum TM_CH_n) +{ + vu32* pCHnCCR = ((vu32*)&TMx->CH0CCR) + (TM_CH_n * 1); + + /* Check the parameters */ + Assert_Param(IS_TM(TMx)); + Assert_Param(IS_TM_CH(TM_CH_n)); + + #if (LIBCFG_PWM_8_CHANNEL) + if ((TM_CH_n > TM_CH_3) && (TM_CH_n <= TM_CH_7)) + { + pCHnCCR = ((vu32*)&TMx->CH4CR) + ((TM_CH_n - 4) * 1); + } + #endif + + /* Get the CHnCCR register value */ + return (*pCHnCCR); +} + +/*********************************************************************************************************//** + * @brief Get counter value of the TMx. + * @param TMx: where TMx is the selected TM from the TM peripherals. + * @retval Value of Counter register + ************************************************************************************************************/ +u32 TM_GetCounter(HT_TM_TypeDef* TMx) +{ + /* Check the parameters */ + Assert_Param(IS_TM(TMx)); + + /* Get the Counter Register value */ + return TMx->CNTR; +} + +/*********************************************************************************************************//** + * @brief Get prescaler value of the TMx. + * @param TMx: where TMx is the selected TM from the TM peripherals. + * @retval Value of Prescaler register + ************************************************************************************************************/ +u32 TM_GetPrescaler(HT_TM_TypeDef* TMx) +{ + /* Check the parameters */ + Assert_Param(IS_TM(TMx)); + + /* Get the Prescaler Register value */ + return TMx->PSCR; +} + +/*********************************************************************************************************//** + * @brief Generate TMx events. + * @param TMx: where TMx is the selected TM from the TM peripherals. + * @param TM_EVENT: Stores the event source. + * This parameter can be any combination of following: + * @arg TM_EVENT_CH0CC : Timer Capture/compare 0 event + * @arg TM_EVENT_CH1CC : Timer Capture/compare 1 event + * @arg TM_EVENT_CH2CC : Timer Capture/compare 2 event + * @arg TM_EVENT_CH3CC : Timer Capture/compare 3 event + * @arg TM_EVENT_CH4CC : Timer Compare 4 event + * @arg TM_EVENT_CH5CC : Timer Compare 5 event + * @arg TM_EVENT_CH6CC : Timer Compare 6 event + * @arg TM_EVENT_CH7CC : Timer Compare 7 event + * @arg TM_EVENT_UEV : Timer update event + * @arg TM_EVENT_UEV2 : Timer update event 2 + * @arg TM_EVENT_TEV : Timer trigger event + * @arg TM_EVENT_BRKEV : Timer break event + * @retval None + ************************************************************************************************************/ +void TM_GenerateEvent(HT_TM_TypeDef* TMx, u32 TM_EVENT) +{ + /* Check the parameters */ + Assert_Param(IS_TM(TMx)); + Assert_Param(IS_TM_EVENT(TM_EVENT)); + + /* Set the event sources */ + TMx->EVGR = TM_EVENT; +} + +/*********************************************************************************************************//** + * @brief Check whether the specified TMx flag has been set. + * @param TMx: where TMx is the selected TM from the TM peripherals. + * @param TM_FLAG: Specify the flag to be checked. + * This parameter can be one of the following values: + * @arg TM_FLAG_CH0CC : TM Capture/compare 0 flag + * @arg TM_FLAG_CH1CC : TM Capture/compare 1 flag + * @arg TM_FLAG_CH2CC : TM Capture/compare 2 flag + * @arg TM_FLAG_CH3CC : TM Capture/compare 3 flag + * @arg TM_FLAG_CH4CC : TM Compare 4 flag + * @arg TM_FLAG_CH5CC : TM Compare 5 flag + * @arg TM_FLAG_CH6CC : TM Compare 6 flag + * @arg TM_FLAG_CH7CC : TM Compare 7 flag + * @arg TM_FLAG_CH0OC : TM channel 0 overcapture flag + * @arg TM_FLAG_CH1OC : TM channel 1 overcapture flag + * @arg TM_FLAG_CH2OC : TM channel 2 overcapture flag + * @arg TM_FLAG_CH3OC : TM channel 3 overcapture flag + * @arg TM_FLAG_UEV : TM update flag + * @arg TM_FLAG_UEV2 : TM update 2 flag + * @arg TM_FLAG_TEV : TM trigger flag + * @arg TM_FLAG_BRK0 : TM break 0 flag + * @arg TM_FLAG_BRK1 : TM break 1 flag + * @retval The new state of TM_FLAG (SET or RESET). + ************************************************************************************************************/ +FlagStatus TM_GetFlagStatus(HT_TM_TypeDef* TMx, u32 TM_FLAG) +{ + /* Check the parameters */ + Assert_Param(IS_TM(TMx)); + Assert_Param(IS_TM_FLAG(TM_FLAG)); + + if ((TMx->INTSR & TM_FLAG) != 0) + { + return SET; + } + else + { + return RESET; + } +} + +/*********************************************************************************************************//** + * @brief Clear flags of the TMx. + * @param TMx: where TMx is the selected TM from the TM peripherals. + * @param TM_FLAG: Specify the flag to be cleared. + * This parameter can be any combination of the following values: + * @arg TM_FLAG_CH0CC : TM Capture/compare 0 flag + * @arg TM_FLAG_CH1CC : TM Capture/compare 1 flag + * @arg TM_FLAG_CH2CC : TM Capture/compare 2 flag + * @arg TM_FLAG_CH3CC : TM Capture/compare 3 flag + * @arg TM_FLAG_CH4CC : TM Compare 4 flag + * @arg TM_FLAG_CH5CC : TM Compare 5 flag + * @arg TM_FLAG_CH6CC : TM Compare 6 flag + * @arg TM_FLAG_CH7CC : TM Compare 7 flag + * @arg TM_FLAG_CH0OC : TM channel 0 overcapture flag + * @arg TM_FLAG_CH1OC : TM channel 1 overcapture flag + * @arg TM_FLAG_CH2OC : TM channel 2 overcapture flag + * @arg TM_FLAG_CH3OC : TM channel 3 overcapture flag + * @arg TM_FLAG_UEV : TM update flag + * @arg TM_FLAG_UEV2 : TM update 2 flag + * @arg TM_FLAG_TEV : TM trigger flag + * @arg TM_FLAG_BRK0 : TM break 0 flag + * @arg TM_FLAG_BRK1 : TM break 1 flag + * @retval None + ************************************************************************************************************/ +void TM_ClearFlag(HT_TM_TypeDef* TMx, u32 TM_FLAG) +{ + /* Check the parameters */ + Assert_Param(IS_TM(TMx)); + Assert_Param(IS_TM_FLAG_CLR(TM_FLAG)); + + /* Clear the flags */ + TMx->INTSR = ~TM_FLAG; + + /*--------------------------------------------------------------------------------------------------------*/ + /* DSB instruction is added in this function to ensure the write operation which is for clearing interrupt*/ + /* flag is actually completed before exiting ISR. It prevents the NVIC from detecting the interrupt again */ + /* since the write register operation may be pended in the internal write buffer of Cortex-Mx when program*/ + /* has exited interrupt routine. This DSB instruction may be masked if this function is called in the */ + /* beginning of ISR and there are still some instructions before exiting ISR. */ + /*--------------------------------------------------------------------------------------------------------*/ + __DSB(); +} + +/*********************************************************************************************************//** + * @brief Enable or Disable the specified interrupts of the TMx. + * @param TMx: where TMx is the selected TM from the TM peripherals. + * @param TM_INT: Specify the TM interrupts sources to be enabled or disabled. + * This parameter can be any combination of the following values: + * @arg TM_INT_CH0CC : TM Capture/compare 0 interrupt + * @arg TM_INT_CH1CC : TM Capture/compare 1 interrupt + * @arg TM_INT_CH2CC : TM Capture/compare 2 interrupt + * @arg TM_INT_CH3CC : TM Capture/compare 3 interrupt + * @arg TM_INT_CH4CC : TM Compare 4 interrupt + * @arg TM_INT_CH5CC : TM Compare 5 interrupt + * @arg TM_INT_CH6CC : TM Compare 6 interrupt + * @arg TM_INT_CH7CC : TM Compare 7 interrupt + * @arg TM_INT_UEV : TM update interrupt + * @arg TM_INT_UEV2 : TM update 2 interrupt + * @arg TM_INT_TEV : TM trigger interrupt + * @arg TM_INT_BRKEV : TM break interrupt + * @arg MCTM_INT_CH0CD : MCTM Channel 0 Count-Down compare interrupt + * @arg MCTM_INT_CH1CD : MCTM Channel 1 Count-Down compare interrupt + * @arg MCTM_INT_CH2CD : MCTM Channel 2 Count-Down compare interrupt + * @arg MCTM_INT_CH3CD : MCTM Channel 3 Count-Down compare interrupt + * @arg TM_INT_VC : TM Velocity clock trigger interrupt + * @arg TM_INT_QC : TM Quadrature decoder CLKPULSE interrupt + * @arg TM_INT_PE : TM Phase error interrupt + * @arg TM_INT_DC : TM Counter direction change interrupt + * @arg MCTM_INT_OVER : MCTM CNTR Overflow interrupt + * @arg MCTM_INT_UNDER : MCTM CNTR Underflow interrupt + * @arg MCTM_INT_RECCDIF : MCTM CCIF or CIDF interrupt flag control by REPR + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void TM_IntConfig(HT_TM_TypeDef* TMx, u32 TM_INT, ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_TM(TMx)); + Assert_Param(IS_TM_INT(TM_INT)); + Assert_Param(IS_CONTROL_STATUS(NewState)); + + if (NewState != DISABLE) + { + /* Enable the interrupt sources */ + TMx->DICTR |= TM_INT; + } + else + { + /* Disable the interrupt sources */ + TMx->DICTR &= ~TM_INT; + } +} + +/*********************************************************************************************************//** + * @brief Check whether the TMx interrupt has occurred. + * @param TMx: where TMx is the selected TM from the TM peripherals. + * @param TM_INT: Specify the TM interrupt source to be checked. + * This parameter can be one of the following values: + * @arg TM_INT_CH0CC : TM Capture/compare 0 interrupt + * @arg TM_INT_CH1CC : TM Capture/compare 1 interrupt + * @arg TM_INT_CH2CC : TM Capture/compare 2 interrupt + * @arg TM_INT_CH3CC : TM Capture/compare 3 interrupt + * @arg TM_INT_CH4CC : TM Compare 4 interrupt + * @arg TM_INT_CH5CC : TM Compare 5 interrupt + * @arg TM_INT_CH6CC : TM Compare 6 interrupt + * @arg TM_INT_CH7CC : TM Compare 7 interrupt + * @arg TM_INT_UEV : TM update interrupt + * @arg TM_INT_UEV2 : TM update 2 interrupt + * @arg TM_INT_TEV : TM trigger interrupt + * @arg TM_INT_BRKEV : TM break interrupt + * @retval The new state of the TM_INT(SET or RESET) + ************************************************************************************************************/ +FlagStatus TM_GetIntStatus(HT_TM_TypeDef* TMx, u32 TM_INT) +{ + u32 itstatus, itenable; + + /* Check the parameters */ + Assert_Param(IS_TM(TMx)); + Assert_Param(IS_TM_GET_INT(TM_INT)); + + itstatus = TMx->INTSR & TM_INT; + itenable = TMx->DICTR & TM_INT; + + if ((itstatus != 0) && (itenable != 0)) + { + return SET; + } + else + { + return RESET; + } +} + +/*********************************************************************************************************//** + * @brief Clear interrupt pending bits of the TMx. + * @param TMx: where TMx is the selected TM from the TM peripherals. + * @param TM_INT: Specify the TM interrupt to be cleared. + * This parameter can be any combination of the following values: + * @arg TM_INT_CH0CC : TM Capture/compare 0 interrupt + * @arg TM_INT_CH1CC : TM Capture/compare 1 interrupt + * @arg TM_INT_CH2CC : TM Capture/compare 2 interrupt + * @arg TM_INT_CH3CC : TM Capture/compare 3 interrupt + * @arg TM_INT_CH4CC : TM Compare 4 interrupt + * @arg TM_INT_CH5CC : TM Compare 5 interrupt + * @arg TM_INT_CH6CC : TM Compare 6 interrupt + * @arg TM_INT_CH7CC : TM Compare 7 interrupt + * @arg TM_INT_UEV : TM update interrupt + * @arg TM_INT_UEV2 : TM update 2 interrupt + * @arg TM_INT_TEV : TM trigger interrupt + * @arg TM_INT_BRKEV : TM break interrupt + * @retval None + ************************************************************************************************************/ +void TM_ClearIntPendingBit(HT_TM_TypeDef* TMx, u32 TM_INT) +{ + /* Check the parameters */ + Assert_Param(IS_TM(TMx)); + Assert_Param(IS_TM_INT(TM_INT)); + + /* Clear the interrupt pending Bit */ + TMx->INTSR = ~TM_INT; + + /*--------------------------------------------------------------------------------------------------------*/ + /* DSB instruction is added in this function to ensure the write operation which is for clearing interrupt*/ + /* flag is actually completed before exiting ISR. It prevents the NVIC from detecting the interrupt again */ + /* since the write register operation may be pended in the internal write buffer of Cortex-Mx when program*/ + /* has exited interrupt routine. This DSB instruction may be masked if this function is called in the */ + /* beginning of ISR and there are still some instructions before exiting ISR. */ + /*--------------------------------------------------------------------------------------------------------*/ + __DSB(); +} + +/*********************************************************************************************************//** + * @brief Disable slave mode to clock the prescaler directly with the internal clock. + * @param TMx: where TMx is the selected TM from the TM peripherals. + * @retval None + ************************************************************************************************************/ +void TM_InternalClockConfig(HT_TM_TypeDef* TMx) +{ + /* Check the parameters */ + Assert_Param(IS_TM(TMx)); + + /* Disable slave mode to clock the prescaler directly with the internal clock */ + TMx->MDCFR &= MDCFR_SMSEL_MASK; +} + +#if (LIBCFG_PDMA) +/*********************************************************************************************************//** + * @brief Select Channel Capture/Compare PDMA event of the TMx. + * @param TMx: where TMx is the selected TM from the TM peripherals. + * @param Selection: This parameter can be TM_CHCCDS_CHCCEV or TM_CHCCDS_UEV. + * @retval None + ************************************************************************************************************/ +void TM_CHCCDSConfig(HT_TM_TypeDef* TMx, TM_CHCCDS_Enum Selection) +{ + /* Check the parameters */ + Assert_Param(IS_TM(TMx)); + Assert_Param(IS_TM_CHCCDS(Selection)); + + if (Selection != TM_CHCCDS_CHCCEV) + { + TMx->CTR |= CTR_CHCCDS; + } + else + { + TMx->CTR &= ~CTR_CHCCDS; + } +} + +/*********************************************************************************************************//** + * @brief Enable or Disable the specified PDMA requests of the TMx. + * @param TMx: where TMx is the selected TM from the TM peripherals. + * @param TM_PDMA: Specify the TM PDMA requests to be enabled or disabled. + * This parameter can be any combination of the following values: + * @arg TM_PDMA_CH0CC : TM Capture/compare 0 PDMA request + * @arg TM_PDMA_CH1CC : TM Capture/compare 1 PDMA request + * @arg TM_PDMA_CH2CC : TM Capture/compare 2 PDMA request + * @arg TM_PDMA_CH3CC : TM Capture/compare 3 PDMA request + * @arg TM_PDMA_UEV : TM update PDMA request + * @arg TM_PDMA_UEV2 : TM update 2 PDMA request + * @arg TM_PDMA_TEV : TM trigger PDMA request + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void TM_PDMAConfig(HT_TM_TypeDef* TMx, u32 TM_PDMA, ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_TM(TMx)); + Assert_Param(IS_TM_PDMA(TM_PDMA)); + Assert_Param(IS_CONTROL_STATUS(NewState)); + + if (NewState != DISABLE) + { + /* Enable the PDMA request */ + TMx->DICTR |= TM_PDMA; + } + else + { + /* Disable the PDMA request */ + TMx->DICTR &= ~TM_PDMA; + } +} +#endif +/** + * @} + */ + +/* Private functions ---------------------------------------------------------------------------------------*/ +/** @defgroup TM_Private_Functions TM private functions + * @{ + */ +/*********************************************************************************************************//** + * @brief Configure the CHx as input. + * @param TMx: where TMx is the selected TM from the TM peripherals. + * @param Ch: Specify the TM Channel. + * This parameter can be one of the following values: + * @arg TM_CH_0 : TM channel 0 + * @arg TM_CH_1 : TM channel 1 + * @arg TM_CH_2 : TM channel 2 + * @arg TM_CH_3 : TM channel 3 + * @param Pol: The input polarity. + * This parameter can be one of the following values: + * @arg TM_CHP_NONINVERTED : Active high level or rising edge + * @arg TM_CHP_INVERTED : Active low level or falling edge + * @param Sel: Specify the input to be used. + * This parameter can be one of the following values: + * @arg TM_CHCCS_DIRECT : TM CHxI is mapped on CHx. + * @arg TM_CHCCS_INDIRECT : TM CH1I is mapped on CH0 (or CH0I->CH1 or CH2I->CH3 or CH3I->CH2). + * @arg TM_CHCCS_TRCED : TM CHx is mapped on TRC. + * @param Filter: Specify the input capture filter. + * This parameter must be a value between 0x00 and 0x0F. + * @retval None + ************************************************************************************************************/ +static void _TM_CHx_Config(HT_TM_TypeDef* TMx, TM_CH_Enum Ch, TM_CHP_Enum Pol, TM_CHCCS_Enum Sel, u8 Filter) +{ + vu32* pIcfr = (vu32*)&TMx->CH0ICFR + Ch; + u32 wIcfr, wChpolr; + + /* Disable the channel N: reset the CHxE bit */ + TMx->CHCTR &= ~((u32)0x1 << (Ch << 1)); + + wIcfr = *pIcfr; + wChpolr = TMx->CHPOLR; + + /* Select the input and set the filter */ + wIcfr &= CHICFR_CHCCS_MASK & CHICFR_CHF_MASK; + wIcfr |= Sel | Filter; + *pIcfr = wIcfr; + + /* Select the polarity bit */ + wChpolr &= ~((u32)0x1 << (Ch << 1)); + wChpolr |= (u32)Pol << (Ch << 1); + TMx->CHPOLR = wChpolr; + + /* Set the CHxE Bit */ + TMx->CHCTR |= (u32)0x1 << (Ch << 1); +} +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/ht32f5xxxx_usart.c b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/ht32f5xxxx_usart.c new file mode 100644 index 0000000000..c0dd366f36 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/ht32f5xxxx_usart.c @@ -0,0 +1,911 @@ +/*********************************************************************************************************//** + * @file ht32f5xxxx_usart.c + * @version $Rev:: 7054 $ + * @date $Date:: 2023-07-24 #$ + * @brief This file provides all the USART firmware functions. + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ + +/* Includes ------------------------------------------------------------------------------------------------*/ +#include "ht32f5xxxx_usart.h" + +/** @addtogroup HT32F5xxxx_Peripheral_Driver HT32F5xxxx Peripheral Driver + * @{ + */ + +/** @defgroup USART USART + * @brief USART driver modules + * @{ + */ + + +/* Private constants ---------------------------------------------------------------------------------------*/ +/** @defgroup USART_Private_Define USART private definitions + * @{ + */ +#define CR_CLEAR_Mask ((u32)0xFFFFE0FC) + +#define USART_BREAK_ON ((u32)0x00004000) +#define USART_BREAK_OFF ((u32)0xFFFFBFFF) + +#define USART_PBE_ON ((u32)0x00000800) +#define USART_SPE_ON ((u32)0x00002000) +#define USART_SPE_OFF ((u32)0xFFFFDFFF) + +#define USART_EN_ON ((u32)0x00000010) + +#define USART_HFCEN_ON ((u32)0x00000008) +#define USART_HFCEN_OFF ((u32)0xFFFFFFF7) + +#define USART_RXTOEN_ON ((u32)0x00000080) + +#define FCR_TL_Mask ((u32)0x00000030) + +#define TRSM_CLEAR_Mask ((u32)0xFFFFFFFB) +#define TPR_TG_Mask ((u32)0xFFFF00FF) +#define ICR_IRDAPSC_Mask ((u32)0xFFFF00FF) +#define TPR_RXTOIC_Mask ((u32)0xFFFFFF80) +#define RS485CR_ADDM_Mask ((u32)0xFFFF00FF) + +#define USART_IRDA_ON ((u32)0x00000001) +#define USART_IRDA_OFF ((u32)0xFFFFFFFE) + +#define USART_INV_ON ((u32)0x00000010) + +#define USART_RS485NMM_ON ((u32)0x00000002) +#define USART_RS485NMM_OFF ((u32)0xFFFFFFFD) + +#define USART_RS485AAD_ON ((u32)0x00000004) +#define USART_RS485AAD_OFF ((u32)0xFFFFFFFB) +/** + * @} + */ + +/* Global functions ----------------------------------------------------------------------------------------*/ +/** @defgroup USART_Exported_Functions USART exported functions + * @{ + */ +/*********************************************************************************************************//** + * @brief Deinitialize the USART/UART peripheral registers to their default reset values. + * @param USARTx: Parameter to select the UxART peripheral. + * @retval None + ************************************************************************************************************/ +void USART_DeInit(HT_USART_TypeDef* USARTx) +{ + RSTCU_PeripReset_TypeDef RSTCUReset = {{0}}; + u32 uIPAddr = (u32)USARTx; + + /* Check the parameters */ + Assert_Param(IS_USART(USARTx)); + + switch (uIPAddr) + { + #if (!LIBCFG_NO_USART0) + case HT_USART0_BASE: + { + RSTCUReset.Bit.USART0 = 1; + break; + } + #endif + #if (LIBCFG_USART1) + case HT_USART1_BASE: + { + RSTCUReset.Bit.USART1 = 1; + break; + } + #endif + case HT_UART0_BASE: + { + RSTCUReset.Bit.UART0 = 1; + break; + } + #if (LIBCFG_UART1) + case HT_UART1_BASE: + { + RSTCUReset.Bit.UART1 = 1; + break; + } + #endif + #if (LIBCFG_UART2) + case HT_UART2_BASE: + { + RSTCUReset.Bit.UART2 = 1; + break; + } + #endif + #if (LIBCFG_UART3) + case HT_UART3_BASE: + { + RSTCUReset.Bit.UART3 = 1; + break; + } + #endif + } + + RSTCU_PeripReset(RSTCUReset, ENABLE); +} + +/*********************************************************************************************************//** + * @brief Initialize the USART/UART peripheral according to the specified parameters in the USART_InitStruct. + * @param USARTx: Parameter to select the UxART peripheral. + * @param USART_InitStruct: pointer to a USART_InitTypeDef structure. + * @retval None + ************************************************************************************************************/ +void USART_Init(HT_USART_TypeDef* USARTx, USART_InitTypeDef* USART_InitStruct) +{ + u32 uIPClock = 0; + u32 uIPAddr = (u32)USARTx; + + /* Check the parameters */ + Assert_Param(IS_USART(USARTx)); + Assert_Param(IS_USART_BAUDRATE(USART_InitStruct->USART_BaudRate)); + Assert_Param(IS_USART_WORD_LENGTH(USART_InitStruct->USART_WordLength)); + Assert_Param(IS_USART_STOPBITS(USART_InitStruct->USART_StopBits)); + Assert_Param(IS_USART_PARITY(USART_InitStruct->USART_Parity)); + Assert_Param(IS_USART_MODE(USART_InitStruct->USART_Mode)); + + USARTx->CR = (USARTx->CR & CR_CLEAR_Mask) | USART_InitStruct->USART_StopBits | + USART_InitStruct->USART_WordLength | USART_InitStruct->USART_Parity | + USART_InitStruct->USART_Mode; + + switch (uIPAddr) + { + #if (!LIBCFG_NO_USART0) + case HT_USART0_BASE: + { + uIPClock = CKCU_GetPeripFrequency(CKCU_PCLK_USART0); + break; + } + #endif + #if (LIBCFG_USART1) + case HT_USART1_BASE: + { + uIPClock = CKCU_GetPeripFrequency(CKCU_PCLK_USART1); + break; + } + #endif + case HT_UART0_BASE: + { + uIPClock = CKCU_GetPeripFrequency(CKCU_PCLK_UART0); + break; + } + #if (LIBCFG_UART1) + case HT_UART1_BASE: + { + uIPClock = CKCU_GetPeripFrequency(CKCU_PCLK_UART1); + break; + } + #endif + #if (LIBCFG_UART2) + case HT_UART2_BASE: + { + uIPClock = CKCU_GetPeripFrequency(CKCU_PCLK_UART2); + break; + } + #endif + #if (LIBCFG_UART3) + case HT_UART3_BASE: + { + uIPClock = CKCU_GetPeripFrequency(CKCU_PCLK_UART3); + break; + } + #endif + } + + USARTx->DLR = uIPClock / (u32)USART_InitStruct->USART_BaudRate; +} + +/*********************************************************************************************************//** + * @brief Fill each USART_InitStruct member with its default value. + * @param USART_InitStruct: pointer to a USART_InitTypeDef structure. + * @retval None + ************************************************************************************************************/ +void USART_StructInit(USART_InitTypeDef* USART_InitStruct) +{ + /* USART_InitStruct members default value */ + USART_InitStruct->USART_BaudRate = 9600; + USART_InitStruct->USART_WordLength = USART_WORDLENGTH_8B; + USART_InitStruct->USART_StopBits = USART_STOPBITS_1; + USART_InitStruct->USART_Parity = USART_PARITY_NO; + USART_InitStruct->USART_Mode = USART_MODE_NORMAL; +} + +/*********************************************************************************************************//** + * @brief USART/UART send data to Tx. + * @param USARTx: Parameter to select the UxART peripheral. + * @param Data: the data to be transmitted. + * @retval None + ************************************************************************************************************/ +void USART_SendData(HT_USART_TypeDef* USARTx, u16 Data) +{ + /* Check the parameters */ + Assert_Param(IS_USART(USARTx)); + Assert_Param(IS_USART_DATA(Data)); + + USARTx->DR = Data; +} + +/*********************************************************************************************************//** + * @brief USART/UART receive data from Rx. + * @param USARTx: Parameter to select the UxART peripheral. + * @retval The received data. + ************************************************************************************************************/ +u16 USART_ReceiveData(HT_USART_TypeDef* USARTx) +{ + /* Check the parameters */ + Assert_Param(IS_USART(USARTx)); + + return (u16)(USARTx->DR); +} + +/*********************************************************************************************************//** + * @brief Get the specified USART/UART status flags. + * @param USARTx: Parameter to select the UxART peripheral. + * @param USART_FLAG_x: Specify the flag to be check. + * This parameter can be one of the following values: + * @arg USART_FLAG_RXDNE : + * @arg USART_FLAG_OE : + * @arg USART_FLAG_PE : + * @arg USART_FLAG_FE : + * @arg USART_FLAG_BI : + * @arg USART_FLAG_RXDR : + * @arg USART_FLAG_TOUT : + * @arg USART_FLAG_TXDE : + * @arg USART_FLAG_TXC : + * @arg USART_FLAG_RSADD : + * @arg USART_FLAG_CTSC : + * @arg USART_FLAG_CTSS : + * @arg USART_FLAG_LBD : + * @retval SET or RESET + ************************************************************************************************************/ +FlagStatus USART_GetFlagStatus(HT_USART_TypeDef* USARTx, u32 USART_FLAG_x) +{ + /* Check the parameters */ + Assert_Param(IS_USART(USARTx)); + Assert_Param(IS_USART_FLAG(USART_FLAG_x)); + + if ((USARTx->SR & USART_FLAG_x) != (u32)RESET) + { + return (SET); + } + else + { + return (RESET); + } +} + +/*********************************************************************************************************//** + * @brief Get the specified USART/UART INT status. + * @param USARTx: Parameter to select the UxART peripheral. + * @param USART_INT_x: Specify if the USART/UART interrupt source. + * This parameter can be one of the following values: + * @arg USART_INT_RXDR : + * @arg USART_INT_TXDE : + * @arg USART_INT_TXC : + * @arg USART_INT_OE : + * @arg USART_INT_PE : + * @arg USART_INT_FE : + * @arg USART_INT_BI : + * @arg USART_INT_RSADD : + * @arg USART_INT_TOUT : + * @arg USART_INT_CTS : + * @arg USART_INT_LBD : + * @retval SET or RESET + ************************************************************************************************************/ +FlagStatus USART_GetIntStatus(HT_USART_TypeDef* USARTx, u32 USART_INT_x) +{ + /* Check the parameters */ + Assert_Param(IS_USART(USARTx)); + Assert_Param(IS_USART_INT(USART_INT_x)); + + if ((USARTx->IER & USART_INT_x) != (u32)RESET) + { + return (SET); + } + else + { + return (RESET); + } +} + +/*********************************************************************************************************//** + * @brief Clear the specified USART/UART flags. + * @param USARTx: where USARTx is the selected USART/UART from the USART/UART peripherals. + * @param USART_Flag: Specify the flag to check. + * This parameter can be any combination of the following values: + * @arg USART_FLAG_OE : + * @arg USART_FLAG_PE : + * @arg USART_FLAG_FE : + * @arg USART_FLAG_BI : + * @arg USART_FLAG_TOUT : + * @arg USART_FLAG_RSADD : + * @arg USART_FLAG_CTSC : + * @arg USART_FLAG_LBD : + * @retval SET or RESET + ************************************************************************************************************/ +void USART_ClearFlag(HT_USART_TypeDef* USARTx, u32 USART_Flag) +{ + /* Check the parameters */ + Assert_Param(IS_USART(USARTx)); + Assert_Param(IS_USART_CLEAR_FLAG(USART_Flag)); + + USARTx->SR &= USART_Flag; +} + +/*********************************************************************************************************//** + * @brief Enable or Disable the USART/UART interrupts. + * @param USARTx: Parameter to select the UxART peripheral. + * @param USART_INT_x: Specify if the USART/UART interrupt source to be enabled or disabled. + * This parameter can be one of the following values: + * @arg USART_INT_RXDR : + * @arg USART_INT_TXDE : + * @arg USART_INT_TXC : + * @arg USART_INT_OE : + * @arg USART_INT_PE : + * @arg USART_INT_FE : + * @arg USART_INT_BI : + * @arg USART_INT_RSADD : + * @arg USART_INT_TOUT : + * @arg USART_INT_CTS : +* @arg USART_INT_LBD : + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void USART_IntConfig(HT_USART_TypeDef* USARTx, u32 USART_INT_x, ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_USART(USARTx)); + Assert_Param(IS_USART_INT(USART_INT_x)); + Assert_Param(IS_CONTROL_STATUS(NewState)); + + if (NewState != DISABLE) + { + USARTx->IER |= USART_INT_x; + } + else + { + USARTx->IER &= ~USART_INT_x; + } +} + +/*********************************************************************************************************//** + * @brief Enable or Disable the USART Tx/Rx. + * @param USARTx: Parameter to select the USART peripheral. + * @param TxRx: This parameter can be USART_CMD_TX or USART_CMD_RX. + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void USART_TxRxCmd(HT_USART_TypeDef* USARTx, u32 TxRx, ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_USART(USARTx)); + Assert_Param(IS_CONTROL_STATUS(NewState)); + if (NewState != DISABLE) + { + USARTx->CR |= (USART_EN_ON << TxRx); + } + else + { + USARTx->CR &= ~(USART_EN_ON << TxRx); + } +} + +#if (LIBCFG_PDMA) +/*********************************************************************************************************//** + * @brief Enable or Disable the USART/UART PDMA interface. + * @param USARTx: Parameter to select the UxART peripheral. + * @param USART_PDMAREQ: specify the USART/UART PDMA transfer request to be enabled or disabled. + * This parameter can be any combination of the following values: + * @arg USART_PDMAREQ_TX + * @arg USART_PDMAREQ_RX + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void USART_PDMACmd(HT_USART_TypeDef* USARTx, u32 USART_PDMAREQ, ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_USART(USARTx)); + Assert_Param(IS_USART_PDMA_REQ(USART_PDMAREQ)); + Assert_Param(IS_CONTROL_STATUS(NewState)); + + if (NewState != DISABLE) + { + USARTx->CR |= USART_PDMAREQ; + } + else + { + USARTx->CR &= ~USART_PDMAREQ; + } +} +#endif + +/*********************************************************************************************************//** + * @brief Enable or Disable the USART/UART break control function. + * @param USARTx: Parameter to select the USART peripheral. + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void USART_ForceBreakCmd(HT_USART_TypeDef* USARTx, ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_USART(USARTx)); + Assert_Param(IS_CONTROL_STATUS(NewState)); + + if (NewState != DISABLE) + { + USARTx->CR |= USART_BREAK_ON; + } + else + { + USARTx->CR &= USART_BREAK_OFF; + } +} + +/*********************************************************************************************************//** + * @brief Enable or Disable the USART/UART stick parity function. + * @param USARTx: Parameter to select the UxART peripheral. + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void USART_StickParityCmd(HT_USART_TypeDef* USARTx, ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_USART(USARTx)); + Assert_Param(IS_CONTROL_STATUS(NewState)); + + if (NewState != DISABLE) + { + USARTx->CR |= USART_SPE_ON | USART_PBE_ON; + } + else + { + USARTx->CR &= USART_SPE_OFF; + } +} + +/*********************************************************************************************************//** + * @brief Configure the stick parity value of the USART/UART. + * @param USARTx: Parameter to select the UxART peripheral. + * @param USART_StickParity: Specify the stick parity of the USART/UART. + * This parameter can be one of the following values: + * @arg USART_STICK_LOW + * @arg USART_STICK_HIGH + * @retval None + ************************************************************************************************************/ +void USART_StickParityConfig(HT_USART_TypeDef * USARTx, u32 USART_StickParity) +{ + /* Check the parameters */ + Assert_Param(IS_USART(USARTx)); + Assert_Param(IS_USART_STICK_PARITY(USART_StickParity)); + + if (USART_StickParity != USART_STICK_HIGH) + { + USARTx->CR |= USART_STICK_LOW; + } + else + { + USARTx->CR &= USART_STICK_HIGH; + } +} + +/*********************************************************************************************************//** + * @brief Set the specified USART guard time. + * @param USARTx: Parameter to select the USART peripheral. + * @param USART_GuardTime: Specify the guard time. + * @retval None + ************************************************************************************************************/ +void USART_SetGuardTime(HT_USART_TypeDef* USARTx, u32 USART_GuardTime) +{ + /* Check the parameters */ + Assert_Param(IS_USART(USARTx)); + Assert_Param(IS_USART_GUARD_TIME(USART_GuardTime)); + + USARTx->TPR = (USARTx->TPR & TPR_TG_Mask) | (USART_GuardTime << 0x08); +} + +/*********************************************************************************************************//** + * @brief Configure the Tx/Rx FIFO Interrupt Trigger Level. + * @param USARTx: Parameter to select the USART peripheral. + * @param TxRx: This parameter can be USART_CMD_TX or USART_CMD_RX. + * @param USART_tl: Specify the USART Tx/Rx FIFO interrupt trigger level. + * This parameter can be one of the following values: + * @arg USART_RXTL_01 + * @arg USART_RXTL_02 + * @arg USART_RXTL_04 + * @arg USART_RXTL_06 + * @arg USART_TXTL_00 + * @arg USART_TXTL_02 + * @arg USART_TXTL_04 + * @arg USART_TXTL_06 + * @retval None + ************************************************************************************************************/ +void USART_TXRXTLConfig(HT_USART_TypeDef* USARTx, u32 TxRx, u32 USART_tl) +{ + /* Check the parameters */ + Assert_Param(IS_USART(USARTx)); + Assert_Param(IS_USART_TL(USART_tl)); + + USARTx->FCR = (USARTx->FCR & ~(FCR_TL_Mask << (TxRx * 2))) | (USART_tl << (TxRx * 2)); +} + +/*********************************************************************************************************//** + * @brief Set the USART FIFO time-out value. + * @param USARTx: Parameter to select the USART peripheral. + * @param USART_TimeOut: Specify the time-out value. + * @retval None + ************************************************************************************************************/ +void USART_SetTimeOutValue(HT_USART_TypeDef* USARTx, u32 USART_TimeOut) +{ + /* Check the parameters */ + Assert_Param(IS_USART(USARTx)); + Assert_Param(IS_USART_TIMEOUT(USART_TimeOut)); + + USARTx->TPR = (USARTx->TPR & TPR_RXTOIC_Mask) | USART_TimeOut | USART_RXTOEN_ON; +} + +/*********************************************************************************************************//** + * @brief Clear both the write and read point in USART Tx FIFO or Rx FIFO. + * @param USARTx: Parameter to select the USART peripheral. + * @param USART_FIFODirection: Determine TX FIFO or Rx FIFO that is to be reset. + * This parameter can be any combination of the following values: + * @arg USART_FIFO_TX + * @arg USART_FIFO_RX + * @retval None + ************************************************************************************************************/ +void USART_FIFOReset(HT_USART_TypeDef* USARTx, u32 USART_FIFODirection) +{ + /* Check the parameters */ + Assert_Param(IS_USART(USARTx)); + Assert_Param(IS_USART_FIFO_DIRECTION(USART_FIFODirection)); + + USARTx->FCR |= USART_FIFODirection; +} + +/*********************************************************************************************************//** + * @brief Return the status of specified USART FIFO. + * @param USARTx: Parameter to select the USART peripheral. + * @param USART_FIFODirection: specify the FIFO that is to be check. + * This parameter can be one of the following values: + * @arg USART_FIFO_TX + * @arg USART_FIFO_RX + * @retval The number of data in Tx FIFO or Rx FIFO. + ************************************************************************************************************/ +u8 USART_GetFIFOStatus(HT_USART_TypeDef* USARTx, u32 USART_FIFODirection) +{ + /* Check the parameters */ + Assert_Param(IS_USART(USARTx)); + Assert_Param(IS_USART_FIFO_DIRECTION(USART_FIFODirection)); + + if (USART_FIFODirection == USART_FIFO_TX) + { + return (u8)((USARTx->FCR & 0xF0000) >> 16); + } + else + { + return (u8)((USARTx->FCR & 0xF000000) >> 24); + } +} + +/*********************************************************************************************************//** + * @brief Enable or Disable the USART hardware flow control. + * @param USARTx: Parameter to select the USART peripheral. + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void USART_HardwareFlowControlCmd(HT_USART_TypeDef* USARTx, ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_USART(USARTx)); + Assert_Param(IS_CONTROL_STATUS(NewState)); + + if (NewState != DISABLE) + { + USARTx->CR |= USART_HFCEN_ON; + } + else + { + USARTx->CR &= USART_HFCEN_OFF; + } +} + +/*********************************************************************************************************//** + * @brief Enable or Disable the USART IrDA interface. + * @param USARTx: Parameter to select the USART peripheral. + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void USART_IrDACmd(HT_USART_TypeDef* USARTx, ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_USART(USARTx)); + Assert_Param(IS_CONTROL_STATUS(NewState)); + + if (NewState != DISABLE) + { + USARTx->ICR |= USART_IRDA_ON; + } + else + { + USARTx->ICR &= USART_IRDA_OFF; + } +} + +/*********************************************************************************************************//** + * @brief Configure the USART IrDA interface. + * @param USARTx: Parameter to select the USART peripheral. + * @param USART_IrDAMode: Specify the USART IrDA mode. + * This parameter can be one of the following values: + * @arg USART_IRDA_LOWPOWER + * @arg USART_IRDA_NORMAL + * @retval None + ************************************************************************************************************/ +void USART_IrDAConfig(HT_USART_TypeDef* USARTx, u32 USART_IrDAMode) +{ + /* Check the parameters */ + Assert_Param(IS_USART(USARTx)); + Assert_Param(IS_USART_IRDA_MODE(USART_IrDAMode)); + + if (USART_IrDAMode != USART_IRDA_NORMAL) + { + USARTx->ICR |= USART_IRDA_LOWPOWER; + } + else + { + USARTx->ICR &= USART_IRDA_NORMAL; + } +} + +/*********************************************************************************************************//** + * @brief Set the specified USART IrDA prescaler. + * @param USARTx: Parameter to select the USART peripheral. + * @param USART_IrDAPrescaler: Specify the USART IrDA prescaler. + * @retval None + ************************************************************************************************************/ +void USART_SetIrDAPrescaler(HT_USART_TypeDef* USARTx, u32 USART_IrDAPrescaler) +{ + /* Check the parameters */ + Assert_Param(IS_USART(USARTx)); + Assert_Param(IS_USART_IRDA_PRESCALER(USART_IrDAPrescaler)); + + USARTx->ICR = (USARTx->ICR & ICR_IRDAPSC_Mask) | (USART_IrDAPrescaler << 0x08); +} + +/*********************************************************************************************************//** + * @brief Enable the IrDA transmitter or receiver. + * @param USARTx: Parameter to select the USART peripheral, x can be 0 or 1. + * @param USART_IrDADirection: Specify the USART IrDA direction select. + * This parameter can be one of the following values: + * @arg USART_IRDA_TX + * @arg USART_IRDA_RX + * @retval None + ************************************************************************************************************/ +void USART_IrDADirectionConfig(HT_USART_TypeDef* USARTx, u32 USART_IrDADirection) +{ + /* Check the parameters */ + Assert_Param(IS_USART(USARTx)); + Assert_Param(IS_USART_IRDA_DIRECTION(USART_IrDADirection)); + + if (USART_IrDADirection != USART_IRDA_RX) + { + USARTx->ICR |= USART_IRDA_TX; + } + else + { + USARTx->ICR &= USART_IRDA_RX; + } +} + +/*********************************************************************************************************//** + * @brief Enable or Disable inverting serial output/input function of IrDA on the specified USART. + * @param USARTx: Parameter to select the USART peripheral. + * @param inout: This parameter can be USART_CMD_OUT or USART_CMD_IN. + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void USART_IrDAInvtCmd(HT_USART_TypeDef* USARTx, u32 inout, ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_USART(USARTx)); + Assert_Param(IS_CONTROL_STATUS(NewState)); + + if (NewState != DISABLE) + { + USARTx->ICR |= (USART_INV_ON << inout); + } + else + { + USARTx->ICR &= ~(USART_INV_ON << inout); + } +} + +/*********************************************************************************************************//** + * @brief Configure the polarity of USART RS485 transmitter enable signal. + * @param USARTx: Parameter to select the USART peripheral. + * @param USART_RS485Polarity: Specify the polarity of USART RS485 Tx enable signal. + * This parameter can be one of the following values: + * @arg USART_RS485POL_LOW + * @arg USART_RS485POL_HIGH + * @retval None + ************************************************************************************************************/ +void USART_RS485TxEnablePolarityConfig(HT_USART_TypeDef* USARTx, u32 USART_RS485Polarity) +{ + /* Check the parameters */ + Assert_Param(IS_USART(USARTx)); + Assert_Param(IS_USART_RS485_POLARITY(USART_RS485Polarity)); + + if (USART_RS485Polarity != USART_RS485POLARITY_HIGH) + { + USARTx->RCR |= USART_RS485POLARITY_LOW; + } + else + { + USARTx->RCR &= USART_RS485POLARITY_HIGH; + } +} + +/*********************************************************************************************************//** + * @brief Enable or Disable the USART RS485 normal multi-drop operation mode. + * @param USARTx: Parameter to select the USART peripheral. + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void USART_RS485NMMCmd(HT_USART_TypeDef* USARTx, ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_USART(USARTx)); + Assert_Param(IS_CONTROL_STATUS(NewState)); + + if (NewState != DISABLE) + { + USARTx->RCR |= USART_RS485NMM_ON; + } + else + { + USARTx->RCR &= USART_RS485NMM_OFF; + } +} + +/*********************************************************************************************************//** + * @brief Enable or Disable the USART RS485 normal multi-drop operation mode. + * @param USARTx: Parameter to select the USART peripheral. + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void USART_RS485AADCmd(HT_USART_TypeDef* USARTx, ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_USART(USARTx)); + Assert_Param(IS_CONTROL_STATUS(NewState)); + + if (NewState != DISABLE) + { + USARTx->RCR |= USART_RS485AAD_ON; + } + else + { + USARTx->RCR &= USART_RS485AAD_OFF; + } +} + +/*********************************************************************************************************//** + * @brief Set the specified USART RS485 address match value. + * @param USARTx: Parameter to select the USART peripheral. + * @param USART_AddressMatchValue: specify the USART RS485 address match value. + * @retval None + ************************************************************************************************************/ +void USART_SetAddressMatchValue(HT_USART_TypeDef* USARTx, u32 USART_AddressMatchValue) +{ + /* Check the parameters */ + Assert_Param(IS_USART(USARTx)); + Assert_Param(IS_USART_ADDRESS_MATCH_VALUE(USART_AddressMatchValue)); + + USARTx->RCR = (USARTx->RCR & RS485CR_ADDM_Mask) | (u32)(USART_AddressMatchValue << 0x08); +} + +/*********************************************************************************************************//** + * @brief Initialize the clock of the USART peripheral according to the specified parameters + * in the USART_ClockInitStruct. + * @param USARTx: Parameter to select the USART peripheral. + * @param USART_SynClock_InitStruct: pointer to a USART_SynClock_InitTypeDef structure. + * @retval None + ************************************************************************************************************/ +void USART_SynClockInit(HT_USART_TypeDef* USARTx, USART_SynClock_InitTypeDef* USART_SynClock_InitStruct) +{ + /* Check the parameters */ + Assert_Param(IS_USART(USARTx)); + Assert_Param(IS_USART_SYNCHRONOUS_CLOCK(USART_SynClock_InitStruct->USART_ClockEnable)); + Assert_Param(IS_USART_SYNCHRONOUS_PHASE(USART_SynClock_InitStruct->USART_ClockPhase)); + Assert_Param(IS_USART_SYNCHRONOUS_POLARITY(USART_SynClock_InitStruct->USART_ClockPolarity)); + Assert_Param(IS_USART_TRANSFER_MODE(USART_SynClock_InitStruct->USART_TransferSelectMode)); + + USARTx->SCR = USART_SynClock_InitStruct->USART_ClockEnable | USART_SynClock_InitStruct->USART_ClockPhase | + USART_SynClock_InitStruct->USART_ClockPolarity; + + USARTx->CR = (USARTx->CR & TRSM_CLEAR_Mask) | USART_SynClock_InitStruct->USART_TransferSelectMode; +} + +/*********************************************************************************************************//** + * @brief Fill each USART_SynClockInitStruct member with its default value. + * @param USART_SynClock_InitStruct: pointer to a USART_SynClock_InitTypeDef structure. + * @retval None + ************************************************************************************************************/ +void USART_SynClockStructInit(USART_SynClock_InitTypeDef* USART_SynClock_InitStruct) +{ + /* USART_ClockInitStruct members default value */ + USART_SynClock_InitStruct->USART_ClockEnable = USART_SYN_CLOCK_DISABLE; + USART_SynClock_InitStruct->USART_ClockPhase = USART_SYN_CLOCK_PHASE_FIRST; + USART_SynClock_InitStruct->USART_ClockPolarity = USART_SYN_CLOCK_POLARITY_LOW; + USART_SynClock_InitStruct->USART_TransferSelectMode = USART_LSB_FIRST; +} + +#if (LIBCFG_USART_LIN) +/*********************************************************************************************************//** + * @brief USART/UART LIN Mode send break to Tx. + * @param USARTx: where USARTx is the selected USART/UART from the USART/UART peripherals. + * @retval None + ************************************************************************************************************/ +void USART_LIN_SendBreak(HT_USART_TypeDef* USARTx) +{ + /* Check the parameters */ + Assert_Param(IS_USART(USARTx)); + + USARTx->CR |= USART_LINSENDBREAK; +} + + +/*********************************************************************************************************//** + * @brief Configure the break detection length in LIN mode. + * @param USARTx: where USARTx is the selected USART/UART from the USART/UART peripherals. + * @param length: data length in byte. + * This parameter can be one of the following values: + * @arg USART_LINLENGTH_11BIT + * @arg USART_LINLENGTH_10BIT + * @retval None + ************************************************************************************************************/ +void USART_LIN_LengthSelect(HT_USART_TypeDef* USARTx, u32 USART_LIN_Length) +{ + /* Check the parameters */ + Assert_Param(IS_USART(USARTx)); + Assert_Param(IS_USART_LINLENGTH(USART_LIN_Length)); + + if (USART_LIN_Length != USART_LINLENGTH_10BIT) + { + USARTx->CR |= USART_LINLENGTH_11BIT; + } + else + { + USARTx->CR &= USART_LINLENGTH_10BIT; + } +} +#endif +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/ht32f5xxxx_usbd.c b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/ht32f5xxxx_usbd.c new file mode 100644 index 0000000000..a6597e97b7 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/ht32f5xxxx_usbd.c @@ -0,0 +1,855 @@ +/*********************************************************************************************************//** + * @file ht32f5xxxx_usbd.c + * @version $Rev:: 7335 $ + * @date $Date:: 2023-11-09 #$ + * @brief The USB Device Peripheral Driver. + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ + +/* Includes ------------------------------------------------------------------------------------------------*/ +#include "ht32.h" +#include "ht32f5xxxx_usbdchk.h" + +/** @addtogroup HT32F5xxxx_Peripheral_Driver HT32F5xxxx Peripheral Driver + * @{ + */ + +/** @defgroup USBDevice USB Device + * @brief USB Device driver modules + * @{ + */ + + +/* Private constants ---------------------------------------------------------------------------------------*/ +/** @defgroup USBDevice_Private_Constant USB Device private constants + * @{ + */ +#define TCR_MASK (0x1FF) +#define EPLEN_MASK ((u32)0x000FFC00) +#define EPBUFA_MASK ((u32)0x000003FF) +#define ISR_EPn_OFFSET (8) + +/* USB Control and Status Register (USBCSR) */ +#define FRES ((u32)0x00000002) /* Force USB Reset */ +#define PDWN ((u32)0x00000004) /* Power Down */ +#define LPMODE ((u32)0x00000008) /* Low-power Mode */ +#define GENRSM ((u32)0x00000020) /* Generate Resume */ +#define ADRSET ((u32)0x00000100) /* Device Address Setting */ +#define SRAMRSTC ((u32)0x00000200) /* USB SRAM reset condition */ +#define DPPUEN ((u32)0x00000400) /* DP Pull Up Enable */ +#define DPWKEN ((u32)0x00000800) /* DP Wake Up Enable */ + +#define EPDIR_IN (1) +#define EPDIR_OUT (0) +/** + * @} + */ + +/* Private variables ---------------------------------------------------------------------------------------*/ +/** @defgroup USBDevice_Private_Variable USB Device private variables + * @{ + */ +static u32 gIsFirstPowered = TRUE; +/** + * @} + */ + +/* Private macro -------------------------------------------------------------------------------------------*/ +/** @defgroup USBDevice_Private_Macro USB Device private macros + * @{ + */ +#ifndef USBDCore_LowPower + #define USBDCore_LowPower() PWRCU_DeepSleep1(PWRCU_SLEEP_ENTRY_WFE) +#endif +/** + * @brief Convert Byte length to Word length + */ +#define ByteLen2WordLen(n) ((n + 3) >> 2) +/** + * @} + */ + +/* Private function prototypes -----------------------------------------------------------------------------*/ +static void _USBD_CopyMemory(u32 *pFrom, u32 *pTo, u32 len); +static HT_USBEP_TypeDef * _USBD_GetEPTnAddr(USBD_EPTn_Enum USBD_EPTn); +static void _delay(u32 nCount); + +/* Global functions ----------------------------------------------------------------------------------------*/ +/** @defgroup USBDevice_Exported_Functions USB Device exported functions + * @{ + */ +/*********************************************************************************************************//** + * @brief Pre initialization for USBD_Init function. + * @param pDriver: USB initialization structure + * @retval None + ***********************************************************************************************************/ +void USBD_PreInit(USBD_Driver_TypeDef *pDriver) +{ + pDriver->uInterruptMask = _UIER_ALL; + + pDriver->ept[USBD_EPT0].CFGR.word = _EP0_CFG; + pDriver->ept[USBD_EPT0].IER = _EP0_IER; + + #if (_EP1_ENABLE == 1) + pDriver->ept[USBD_EPT1].CFGR.word = _EP1_CFG; + pDriver->ept[USBD_EPT1].IER = _EP1_IER; + #endif + + #if (_EP2_ENABLE == 1) + pDriver->ept[USBD_EPT2].CFGR.word = _EP2_CFG; + pDriver->ept[USBD_EPT2].IER = _EP2_IER; + #endif + + #if (_EP3_ENABLE == 1) + pDriver->ept[USBD_EPT3].CFGR.word = _EP3_CFG; + pDriver->ept[USBD_EPT3].IER = _EP3_IER; + #endif + + #if (_EP4_ENABLE == 1) + pDriver->ept[USBD_EPT4].CFGR.word = _EP4_CFG; + pDriver->ept[USBD_EPT4].IER = _EP4_IER; + #endif + + #if (_EP5_ENABLE == 1) + pDriver->ept[USBD_EPT5].CFGR.word = _EP5_CFG; + pDriver->ept[USBD_EPT5].IER = _EP5_IER; + #endif + + #if (_EP6_ENABLE == 1) + pDriver->ept[USBD_EPT6].CFGR.word = _EP6_CFG; + pDriver->ept[USBD_EPT6].IER = _EP6_IER; + #endif + + #if (_EP7_ENABLE == 1) + pDriver->ept[USBD_EPT7].CFGR.word = _EP7_CFG; + pDriver->ept[USBD_EPT7].IER = _EP7_IER; + #endif + + #if (LIBCFG_USBD_V2) + #if (_EP8_ENABLE == 1) + pDriver->ept[USBD_EPT8].CFGR.word = _EP8_CFG; + pDriver->ept[USBD_EPT8].IER = _EP8_IER; + #endif + + #if (_EP9_ENABLE == 1) + pDriver->ept[USBD_EPT9].CFGR.word = _EP9_CFG; + pDriver->ept[USBD_EPT9].IER = _EP9_IER; + #endif + #endif + return; +} + +/*********************************************************************************************************//** + * @brief USB Device Peripheral initialization. + * @param pDriver: USB initialization structure + * @retval None + ***********************************************************************************************************/ +void USBD_Init(u32 *pDriver) +{ + USBD_Driver_TypeDef *pDrv = (USBD_Driver_TypeDef *)pDriver; + + /* Init USB Device Driver struct */ + USBD_PreInit(pDrv); + + return; +} + +/*********************************************************************************************************//** + * @brief USB Device Internal DP pull up. + * @param NewState: ENABLE or DISABLE + * @retval None + ***********************************************************************************************************/ +void USBD_DPpullupCmd(ControlStatus NewState) +{ + (NewState == ENABLE)?(HT_USB->CSR |= DPPUEN):(HT_USB->CSR &= ~DPPUEN); +} + +/*********************************************************************************************************//** + * @brief USB Device Wake Up when DP is high level. + * @param NewState: ENABLE or DISABLE + * @retval None + ***********************************************************************************************************/ +void USBD_DPWakeUpCmd(ControlStatus NewState) +{ + (NewState == ENABLE)?(HT_USB->CSR |= DPWKEN):(HT_USB->CSR &= ~DPWKEN); +} + +/*********************************************************************************************************//** + * @brief USB Device Peripheral deinitialization. + * @retval None + ***********************************************************************************************************/ +void USBD_DeInit(void) +{ + RSTCU_PeripReset_TypeDef RSTCUReset = {{0}}; + + RSTCUReset.Bit.USBD = 1; + RSTCU_PeripReset(RSTCUReset, ENABLE); + + return; +} + +/*********************************************************************************************************//** + * @brief USB power up procedure. + * @retval None + ***********************************************************************************************************/ +void USBD_PowerUp(u32 *pDriver, u32 uIsSelfPowered) +{ + USBD_Driver_TypeDef *pDrv = (USBD_Driver_TypeDef *)pDriver; + + if (gIsFirstPowered == TRUE) + { + gIsFirstPowered = FALSE; + + if (HT_USB->CSR & 0x40) + { + HT_USB->CSR = (DPPUEN | LPMODE | PDWN); + while((HT_USB->ISR & URSTIE) == 0); + HT_USB->ISR = 0xFFFFFFFF; + if (uIsSelfPowered == FALSE) + { + USBDCore_LowPower(); + } + USBD_EnableINT(pDrv->uInterruptMask); + } + else + { + HT_USB->CSR = (DPWKEN | DPPUEN | LPMODE | PDWN); + while((HT_USB->ISR & URSTIE) == 0); + HT_USB->ISR = 0xFFFFFFFF; + if (uIsSelfPowered == FALSE) + { + USBDCore_LowPower(); + } + USBD_DPWakeUpCmd(DISABLE); + USBD_EnableINT(pDrv->uInterruptMask); + USBD_DPpullupCmd(DISABLE); + _delay(200); + USBD_DPpullupCmd(ENABLE); + } + } + + return; +} + +/*********************************************************************************************************//** + * @brief Enter USB Device Power Down mode. + * @retval None + ***********************************************************************************************************/ +void USBD_PowerOff(void) +{ + HT_USB->CSR |= (LPMODE | PDWN); + return; +} + +/*********************************************************************************************************//** + * @brief Exit USB Device Power Down mode. + * @retval None + ***********************************************************************************************************/ +void USBD_PowerOn(void) +{ + HT_USB->CSR |= 0x00001000; + HT_USB->CSR &= 0x00001400; + return; +} + +/*********************************************************************************************************//** + * @brief USB SRAM reset condition. + * @param NewState: ENABLE or DISABLE + * @retval None + ***********************************************************************************************************/ +void USBD_SRAMResetConditionCmd(ControlStatus NewState) +{ + (NewState == ENABLE)?(HT_USB->CSR |= SRAMRSTC):(HT_USB->CSR &= ~SRAMRSTC); +} + +/*********************************************************************************************************//** + * @brief Disable Default pull resistance of D+ and D-. + * @retval None + ***********************************************************************************************************/ +void USBD_DisableDefaultPull(void) +{ + HT_USB->CSR = FRES; // Clear PDWN and keep FRES = 1 +} + +/*********************************************************************************************************//** + * @brief Generate a resume request to USB Host for Remote Wakeup function. + * @retval None + ***********************************************************************************************************/ +void USBD_RemoteWakeup(void) +{ + HT_USB->CSR |= GENRSM; + return; +} + +/*********************************************************************************************************//** + * @brief Read Endpoint0 SETUP data from USB Buffer. + * @param pBuffer: Buffer for save SETUP data + * @retval None + ***********************************************************************************************************/ +void USBD_ReadSETUPData(u32 *pBuffer) +{ + u32 *pSrc = (u32 *)HT_USB_SRAM_BASE; + + *pBuffer = *pSrc; + *(pBuffer + 1) = *(pSrc + 1); + return; +} + +/*********************************************************************************************************//** + * @brief Set USB Device address. + * @param address: USB address which specified by Host + * @retval None + ***********************************************************************************************************/ +void USBD_SetAddress(u32 address) +{ + HT_USB->CSR |= ADRSET; + HT_USB->DEVAR = address; + return; +} + +/*********************************************************************************************************//** + * @brief Enable USB Device interrupt. + * @param INTFlag: USB Device global interrupt flag + * @arg UGIE | SOFIE | URSTIE | RSMIE | SUSPIE | ESOFIE + * EP0IE | EP1IE | EP2IE | EP3IE | EP4IE | EP5IE | EP6IE | EP7IE | EP8IE | EP9IE + * @retval None + ***********************************************************************************************************/ +void USBD_EnableINT(u32 INTFlag) +{ + HT_USB->IER |= INTFlag; + return; +} + +/*********************************************************************************************************//** + * @brief Disable USB Device interrupt. + * @param INTFlag: USB Device global interrupt flag + * @arg UGIE | SOFIE | URSTIE | RSMIE | SUSPIE | ESOFIE + * EP0IE | EP1IE | EP2IE | EP3IE | EP4IE | EP5IE | EP6IE | EP7IE | EP8IE | EP9IE + * @retval None + ***********************************************************************************************************/ +void USBD_DisableINT(u32 INTFlag) +{ + HT_USB->IER &= (~INTFlag); + return; +} + +/*********************************************************************************************************//** + * @brief Get active USB Device interrupt flag. + * @retval USB ISR Flag + ***********************************************************************************************************/ +u32 USBD_GetINT(void) +{ + u32 IER = HT_USB->IER | FRESIE; + return (HT_USB->ISR & IER); +} + +/*********************************************************************************************************//** + * @brief Clear USB Device interrupt flag. + * @param INTFlag: USB Device global interrupt flag + * @arg SOFIF | URSTIF | RSMIF | SUSPIF | ESOFIF + * EP0IF | EP1IF | EP2IF | EP3IF | EP4IF | EP5IF | EP6IF | EP7IF | EP8IF | EP9IF + * @retval None + ***********************************************************************************************************/ +void USBD_ClearINT(u32 INTFlag) +{ + HT_USB->ISR = INTFlag; + return; +} + +/*********************************************************************************************************//** + * @brief Get USB Endpoint number by interrupt flag. + * @param INTFlag: USB Device global interrupt flag + * @arg SOFIF | URSTIF | RSMIF | SUSPIF | ESOFIF + * EP0IF | EP1IF | EP2IF | EP3IF | EP4IF | EP5IF | EP6IF | EP7IF | EP8IF | EP9IF + * @retval USB Endpoint number from USBD_EPT1 ~ USBD_EPT9 + ***********************************************************************************************************/ +USBD_EPTn_Enum USBD_GetEPTnINTNumber(u32 INTFlag) +{ + s32 i; + for (i = MAX_EP_NUM - 1; i > 0; i--) + { + if ((INTFlag >> (i + ISR_EPn_OFFSET)) & SET) + { + return (USBD_EPTn_Enum)i; + } + } + + return USBD_NOEPT; +} + +/*********************************************************************************************************//** + * @brief USB Device Peripheral initialization for Endpoint. + * @param USBD_EPTn: USB Endpoint number + * @arg USBD_EPT0 ~ USBD_EPT9 + * @param pDriver: USB initialization structure + * @retval None + ***********************************************************************************************************/ +void USBD_EPTInit(USBD_EPTn_Enum USBD_EPTn, u32 *pDriver) +{ + USBD_Driver_TypeDef *pDrv = (USBD_Driver_TypeDef *)pDriver; + HT_USBEP_TypeDef *USBEPn = _USBD_GetEPTnAddr(USBD_EPTn); + + USBEPn->CFGR = pDrv->ept[USBD_EPTn].CFGR.word; + USBEPn->IER = pDrv->ept[USBD_EPTn].IER; + + USBEPn->ISR = 0xFFFFFFFF; + + USBD_EPTReset(USBD_EPTn); + + return; +} + +/*********************************************************************************************************//** + * @brief Reset Endpoint Status. + * @param USBD_EPTn: USB Endpoint number + * @arg USBD_EPT0 ~ USBD_EPT9 + * @retval None + ***********************************************************************************************************/ +void USBD_EPTReset(USBD_EPTn_Enum USBD_EPTn) +{ + HT_USBEP_TypeDef *USBEPn = _USBD_GetEPTnAddr(USBD_EPTn); + USBEPn->CSR = (USBEPn->CSR) & (DTGTX | DTGRX | NAKRX); + return; +} + +/*********************************************************************************************************//** + * @brief Enable Interrupt for Endpoint. + * @param USBD_EPTn: USB Endpoint number + * @arg USBD_EPT0 ~ USBD_EPT9 + * @param INTFlag: Interrupt flag + * @arg OTRXIE | ODRXIE | ODOVIE | ITRXIE | IDTXIE | NAKIE | STLIE | UERIE | + * STRXIE | SDRXIE | SDERIE | ZLRXIE + * @retval None + ***********************************************************************************************************/ +void USBD_EPTEnableINT(USBD_EPTn_Enum USBD_EPTn, u32 INTFlag) +{ + _USBD_GetEPTnAddr(USBD_EPTn)->IER = INTFlag; + return; +} + +/*********************************************************************************************************//** + * @brief Get active USB Device Endpoint interrupt. + * @param USBD_EPTn: USB Endpoint number + * @arg USBD_EPT0 ~ USBD_EPT9 + * @retval USB Endpoint ISR Flag + ***********************************************************************************************************/ +u32 USBD_EPTGetINT(USBD_EPTn_Enum USBD_EPTn) +{ + HT_USBEP_TypeDef *USBEPn = _USBD_GetEPTnAddr(USBD_EPTn); + u32 IER = USBEPn->IER; + return (USBEPn->ISR & IER); +} + +/*********************************************************************************************************//** + * @brief Clear Interrupt for Endpoint. + * @param USBD_EPTn: USB Endpoint number + * @arg USBD_EPT0 ~ USBD_EPT9 + * @param INTFlag: Interrupt flag + * @arg OTRXIF | ODRXIF | ODOVIF | ITRXIF | IDTXIF | NAKIF | STLIF | UERIF | + * STRXIF | SDRXIF | SDERIF | ZLRXIF + * @retval None + ***********************************************************************************************************/ +void USBD_EPTClearINT(USBD_EPTn_Enum USBD_EPTn, u32 INTFlag) +{ + _USBD_GetEPTnAddr(USBD_EPTn)->ISR = INTFlag; + return; +} + +/*********************************************************************************************************//** + * @brief Get Endpoint n Halt status (STLTX or STLRX). + * @param USBD_EPTn: USB Endpoint number + * @arg USBD_EPT0 ~ USBD_EPT9 + * @retval Endpoint Halt Status (1: Endpoint is Halt, 0: Endpoint is not Halt) + ***********************************************************************************************************/ +u32 USBD_EPTGetHalt(USBD_EPTn_Enum USBD_EPTn) +{ + HT_USBEP_TypeDef *USBEPn = _USBD_GetEPTnAddr(USBD_EPTn); + USBD_EPTCFGR_Bit *CFGR = (USBD_EPTCFGR_Bit *)(&(USBEPn->CFGR)); + if (CFGR->EPDIR == EPDIR_IN) + { + return (((USBEPn->CSR) & STLTX) ? 1 : 0); + } + else + { + return (((USBEPn->CSR) & STLRX) ? 1 : 0); + } +} + +/*********************************************************************************************************//** + * @brief Send STALL on Endpoint n. + * @param USBD_EPTn: USB Endpoint number + * @arg USBD_EPT0 ~ USBD_EPT9 + * @retval None + ***********************************************************************************************************/ +void USBD_EPTSendSTALL(USBD_EPTn_Enum USBD_EPTn) +{ + _USBD_GetEPTnAddr(USBD_EPTn)->CSR = STLTX; + return; +} + +/*********************************************************************************************************//** + * @brief Set Endpoint n Halt status (STLTX or STLRX). + * @param USBD_EPTn: USB Endpoint number + * @arg USBD_EPT0 ~ USBD_EPT9 + * @retval None + ***********************************************************************************************************/ +void USBD_EPTSetHalt(USBD_EPTn_Enum USBD_EPTn) +{ + HT_USBEP_TypeDef *USBEPn = _USBD_GetEPTnAddr(USBD_EPTn); + +#if 1 + /* Clean STLIF flag, for USBD_EPTWaitSTALLSent function */ + USBEPn->ISR = STLIF; + USBEPn->CSR = (~(USBEPn->CSR)) & (STLTX | STLRX); +#else + USBD_EPTCFGR_Bit *CFGR = (USBD_EPTCFGR_Bit *)(&(USBEPn->CFGR)); + if (CFGR->EPDIR == EPDIR_IN) + { + /* Clean STLIF flag, for USBD_EPTWaitSTALLSent function */ + USBEPn->ISR = STLIF; + /* Set only when STLTX = 0 */ + USBEPn->CSR = (~(USBEPn->CSR)) & STLTX; + } + else + { + /* Set only when STLRX = 0 */ + USBEPn->CSR = (~(USBEPn->CSR)) & STLRX; + } +#endif + + return; +} + +/*********************************************************************************************************//** + * @brief Clear Endpoint n Halt status (STLTX or STLRX). + * @param USBD_EPTn: USB Endpoint number + * @arg USBD_EPT0 ~ USBD_EPT9 + * @retval None + ***********************************************************************************************************/ +void USBD_EPTClearHalt(USBD_EPTn_Enum USBD_EPTn) +{ + HT_USBEP_TypeDef *USBEPn = _USBD_GetEPTnAddr(USBD_EPTn); + +#if 1 + USBEPn->CSR = (USBEPn->CSR) & (STLTX | STLRX); +#else + USBD_EPTCFGR_Bit *CFGR = (USBD_EPTCFGR_Bit *)(&(USBEPn->CFGR)); + if (CFGR->EPDIR == EPDIR_IN) + { + /* Clear only when STLTX = 1 */ + USBEPn->CSR = (USBEPn->CSR) & STLTX; + } + else + { + /* Clear only when STLRX = 1 */ + USBEPn->CSR = (USBEPn->CSR) & STLRX; + } +#endif + + return; +} + +/*********************************************************************************************************//** + * @brief Wait until STALL transmission is finished + * @param USBD_EPTn: USB Endpoint number + * @arg USBD_EPT0 ~ USBD_EPT9 + * @retval None + ***********************************************************************************************************/ +void USBD_EPTWaitSTALLSent(USBD_EPTn_Enum USBD_EPTn) +{ + HT_USBEP_TypeDef *USBEPn = _USBD_GetEPTnAddr(USBD_EPTn); + USBD_EPTCFGR_Bit *CFGR = (USBD_EPTCFGR_Bit *)(&(USBEPn->CFGR)); + u32 uSTALLState = (CFGR->EPDIR == EPDIR_IN) ? ((USBEPn->CSR) & STLTX) : ((USBEPn->CSR) & STLRX); + + if (uSTALLState) + { + while ((USBEPn->ISR & STLIF) == 0); + } + + return; +} + +/*********************************************************************************************************//** + * @brief Clear Endpoint n Data toggle bit (DTGTX or DTGRX). + * @param USBD_EPTn: USB Endpoint number + * @arg USBD_EPT0 ~ USBD_EPT9 + * @retval None + ***********************************************************************************************************/ +void USBD_EPTClearDTG(USBD_EPTn_Enum USBD_EPTn) +{ + HT_USBEP_TypeDef *USBEPn = _USBD_GetEPTnAddr(USBD_EPTn); + +#if 1 + USBEPn->CSR = (USBEPn->CSR) & (DTGTX | DTGRX); +#else + USBD_EPTCFGR_Bit *CFGR = (USBD_EPTCFGR_Bit *)(&(USBEPn->CFGR)); + if (CFGR->EPDIR == EPDIR_IN) + { + /* Clear only when DTGTX = 1 */ + USBEPn->CSR = (USBEPn->CSR) & DTGTX; + } + else + { + /* Clear only when DTGRX = 1 */ + USBEPn->CSR = (USBEPn->CSR) & DTGRX; + } +#endif + return; +} + +/*********************************************************************************************************//** + * @brief Get Endpoint n buffer 0 address. + * @param USBD_EPTn: USB Endpoint number + * @arg USBD_EPT0 ~ USBD_EPT9 + * @retval USB Endpoint buffer 0 address + ***********************************************************************************************************/ +u32 USBD_EPTGetBuffer0Addr(USBD_EPTn_Enum USBD_EPTn) +{ + HT_USBEP_TypeDef *USBEPn = _USBD_GetEPTnAddr(USBD_EPTn); + return (HT_USB_SRAM_BASE + (USBEPn->CFGR & EPBUFA_MASK)); +} + +/*********************************************************************************************************//** + * @brief Get Endpoint n buffer 1 address. + * @param USBD_EPTn: USB Endpoint number + * @arg USBD_EPT0 ~ USBD_EPT9 + * @retval USB Endpoint buffer 1 address + ***********************************************************************************************************/ +u32 USBD_EPTGetBuffer1Addr(USBD_EPTn_Enum USBD_EPTn) +{ + HT_USBEP_TypeDef *USBEPn = _USBD_GetEPTnAddr(USBD_EPTn); + return (HT_USB_SRAM_BASE + (USBEPn->CFGR & EPBUFA_MASK) + USBD_EPTGetBufferLen(USBD_EPTn)); +} + +/*********************************************************************************************************//** + * @brief Get Endpoint n buffer length. + * @param USBD_EPTn: USB Endpoint number + * @arg USBD_EPT0 ~ USBD_EPT9 + * @retval USB Endpoint buffer length + ***********************************************************************************************************/ +u32 USBD_EPTGetBufferLen(USBD_EPTn_Enum USBD_EPTn) +{ + return ((_USBD_GetEPTnAddr(USBD_EPTn)->CFGR & EPLEN_MASK) >> 10); +} + +/*********************************************************************************************************//** + * @brief Get Endpoint n Transfer Count. + * @param USBD_EPTn: USB Endpoint number + * @arg USBD_EPT0 ~ USBD_EPT9 + * @param USBD_TCR_n: USBD_TCR_0 or USBD_TCR_1 + * @retval Endpoint Transfer Count + ***********************************************************************************************************/ +u32 USBD_EPTGetTransferCount(USBD_EPTn_Enum USBD_EPTn, USBD_TCR_Enum USBD_TCR_n) +{ + return (((_USBD_GetEPTnAddr(USBD_EPTn)->TCR) >> USBD_TCR_n) & TCR_MASK); +} + +/*********************************************************************************************************//** + * @brief Write IN Data from User buffer to USB buffer. + * @param USBD_EPTn: USB Endpoint number + * @arg USBD_EPT0 ~ USBD_EPT9 + * @param pFrom: Source buffer + * @param len: Length for write IN data + * @retval Total length written by this function + ***********************************************************************************************************/ +u32 USBD_EPTWriteINData(USBD_EPTn_Enum USBD_EPTn, u32 *pFrom, u32 len) +{ + u32 bufferlen = USBD_EPTGetBufferLen(USBD_EPTn); + HT_USBEP_TypeDef *USBEPn = _USBD_GetEPTnAddr(USBD_EPTn); + u32 EPTnLen; + u32 *pTo; + + EPTnLen = (USBD_EPTn == USBD_EPT0) ? USBD_EPTGetTransferCount(USBD_EPTn, USBD_CNTIN):USBD_EPTGetTransferCount(USBD_EPTn, USBD_CNTB0); + + if (len <= bufferlen && EPTnLen == 0) + { + pTo = (u32 *)USBD_EPTGetBuffer0Addr(USBD_EPTn); + _USBD_CopyMemory(pFrom, pTo, ByteLen2WordLen(len)); + USBEPn->TCR = len; + USBEPn->CSR = NAKTX; + return len; + } + else + { + return 0; + } +} + +/*********************************************************************************************************//** + * @brief Read OUT Data from USB buffer to User buffer. + * @param USBD_EPTn: USB Endpoint number + * @arg USBD_EPT0 ~ USBD_EPT9 + * @param pTo: Destination memory + * @param len: Length for read OUT data, set as 0 for discard current OUT data in the USB buffer + * @retval Total length read by this function + ***********************************************************************************************************/ +u32 USBD_EPTReadOUTData(USBD_EPTn_Enum USBD_EPTn, u32 *pTo, u32 len) +{ + HT_USBEP_TypeDef *USBEPn = _USBD_GetEPTnAddr(USBD_EPTn); + u32 EPTnLen = 0; + + if (len != 0) + { + EPTnLen = USBD_EPTReadMemory(USBD_EPTn, pTo, len); + } + + if (EPTnLen != 0 || len == 0) + { + USBEPn->CSR = (USBEPn->CSR & NAKRX); + } + + return EPTnLen; +} + +/*********************************************************************************************************//** + * @brief Read memory from endpoint buffer. + * @param USBD_EPTn: USB Endpoint number + * @arg USBD_EPT0 ~ USBD_EPT9 + * @param pTo: Destination buffer + * @param len: Length for read OUT data + * @retval Total length read by this function + ***********************************************************************************************************/ +u32 USBD_EPTReadMemory(USBD_EPTn_Enum USBD_EPTn, u32 *pTo, u32 len) +{ + u32 EPTnLen = 0; + u32 *pFrom; + + EPTnLen = (USBD_EPTn == USBD_EPT0) ? USBD_EPTGetTransferCount(USBD_EPTn, USBD_CNTOUT):USBD_EPTGetTransferCount(USBD_EPTn, USBD_CNTB0); + + if (EPTnLen <= len) + { + pFrom = (USBD_EPTn == USBD_EPT0) ? (u32 *)USBD_EPTGetBuffer1Addr(USBD_EPTn):(u32 *)USBD_EPTGetBuffer0Addr(USBD_EPTn); + _USBD_CopyMemory(pFrom, pTo, ByteLen2WordLen(EPTnLen)); + } + + return EPTnLen; +} +/** + * @} + */ + +/* Private functions ---------------------------------------------------------------------------------------*/ +/** @defgroup USBDevice_Private_Function USB Device private functions + * @{ + */ +/*********************************************************************************************************//** + * @brief Copy 32 bits memory from pFrom to pTo. + * @param pFrom: Source buffer + * @param pTo: Destination buffer + * @param len: Copy length + * @retval None + ***********************************************************************************************************/ +static void _USBD_CopyMemory(u32 *pFrom, u32 *pTo, u32 len) +{ + s32 i; + u32 uFromAligned = (((u32)pFrom & 0x3) == 0) ? 1 : 0; + u32 uToAligned = (((u32)pTo & 0x3) == 0) ? 1 : 0; + u8 *pFromByte = (u8 *)pFrom; + u8 *pToByte = (u8 *)pTo; + + if (uFromAligned == 0) + { + if (uToAligned == 0) + { + for (i = len - 1; i >= 0; i--) + { + *pToByte++ = *pFromByte++; + *pToByte++ = *pFromByte++; + *pToByte++ = *pFromByte++; + *pToByte++ = *pFromByte++; + } + } + else + { + u32 uTemp = 0; + for (i = 0; i < (s32)len; i++) + { + uTemp = *(pFromByte++) << 0; + uTemp += *(pFromByte++) << 8; + uTemp += *(pFromByte++) << 16; + uTemp += *(pFromByte++) << 24; + pTo[i] = uTemp; + } + } + } + else + { + if (uToAligned == 0) + { + u32 uTemp = 0; + for (i = 0; i < (s32)len; i++) + { + uTemp = pFrom[i]; + *pToByte++ = (uTemp >> 0) & 0xFF; + *pToByte++ = (uTemp >> 8) & 0xFF; + *pToByte++ = (uTemp >> 16) & 0xFF; + *pToByte++ = (uTemp >> 24) & 0xFF; + } + } + else + { + for (i = len - 1; i >= 0; i--) + { + pTo[i] = pFrom[i]; + } + } + } + + return; +} + +/*********************************************************************************************************//** + * @brief Convent USBD_EPTn_Enum to USBEP_TypeDef. + * @param USBD_EPTn: USB Endpoint number + * @arg USBD_EPT0 ~ USBD_EPT9 + * @retval USBEP0 ~ USBEP9 + ***********************************************************************************************************/ +static HT_USBEP_TypeDef * _USBD_GetEPTnAddr(USBD_EPTn_Enum USBD_EPTn) +{ + return ((HT_USBEP_TypeDef *)(HT_USBEP0 + USBD_EPTn)); +} + +/*********************************************************************************************************//** + * @brief Inserts a delay time. + * @param nCount: specifies the delay time length. + * @retval None + ***********************************************************************************************************/ +static void _delay(u32 nCount) +{ + u32 i; + + for (i = 0; i < nCount; i++) + { + } +} +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/ht32f5xxxx_wdt.c b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/ht32f5xxxx_wdt.c new file mode 100644 index 0000000000..b90f5b1fac --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/ht32f5xxxx_wdt.c @@ -0,0 +1,343 @@ +/*********************************************************************************************************//** + * @file ht32f5xxxx_wdt.c + * @version $Rev:: 2772 $ + * @date $Date:: 2018-05-15 #$ + * @brief This file provides all the WDT firmware functions. + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ + +/* Includes ------------------------------------------------------------------------------------------------*/ +#include "ht32f5xxxx_wdt.h" + +/** @addtogroup HT32F5xxxx_Peripheral_Driver HT32F5xxxx Peripheral Driver + * @{ + */ + +/** @defgroup WDT WDT + * @brief WDT driver modules + * @{ + */ + + +/* Private constants ---------------------------------------------------------------------------------------*/ +/** @defgroup WDT_Private_Define WDT private definitions + * @{ + */ + +/* WDT Restart Key */ +#define RESTART_KEY ((u32)0x5FA00000) + +/* WDT Protect mask */ +#define PRCT_SET ((u32)0x0000CA35) +#define PRCT_RESET ((u32)0x000035CA) + +/* WDT WDTFIEN mask */ +#define MODE0_WDTFIEN_SET ((u32)0x00001000) +#define MODE0_WDTFIEN_RESET ((u32)0xFFFFEFFF) + +/* WDT WDTRSTEN mask */ +#define MODE0_WDTRETEN_SET ((u32)0x00002000) +#define MODE0_WDTRETEN_RESET ((u32)0xFFFFDFFF) + +/* WDT WDTEN mask */ +#define MODE0_WDTEN_SET ((u32)0x00010000) +#define MODE0_WDTEN_RESET ((u32)0xFFFEFFFF) + +/* WDT WDTLOCK mask */ +#define MODE0_WDTLOCK_SET ((u32)0x00000010) +#define MODE0_WDTLOCK_RESET ((u32)0x00000000) +/** + * @} + */ + +/* Global functions ----------------------------------------------------------------------------------------*/ +/** @defgroup WDT_Exported_Functions WDT exported functions + * @{ + */ +/*********************************************************************************************************//** + * @brief Deinitialize the WDT peripheral registers to their default reset values. + * @retval None + ************************************************************************************************************/ +void WDT_DeInit(void) +{ + RSTCU_PeripReset_TypeDef RSTCUReset = {{0}}; + + RSTCUReset.Bit.WDT = 1; + RSTCU_PeripReset(RSTCUReset, ENABLE); +} + +/*********************************************************************************************************//** + * @brief Enable or Disable the WDT. + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void WDT_Cmd(ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_CONTROL_STATUS(NewState)); + + if (NewState != DISABLE) + { + HT_WDT->MR0 |= MODE0_WDTEN_SET; + } + else + { + HT_WDT->MR0 &= MODE0_WDTEN_RESET; + } +} + +/*********************************************************************************************************//** + * @brief Configure the WDT to run or halt in sleep and deep sleep1 mode. + * @param WDT_Mode: + * This parameter can be one of the following values: + * @arg MODE0_WDTSHLT_BOTH : WDT runs in sleep and deep sleep1 mode + * @arg MODE0_WDTSHLT_SLEEP : WDT runs in sleep mode + * @arg MODE0_WDTSHLT_HALT : WDT halts in sleep and deep sleep1 mode + * @retval None + ************************************************************************************************************/ +void WDT_HaltConfig(u32 WDT_Mode) +{ + /* Check the parameters */ + Assert_Param(IS_WDT_WDTSHLT_MODE(WDT_Mode)); + + HT_WDT->MR0 = ((WDT_Mode) | (HT_WDT->MR0 & 0x00013FFF)); +} + +/*********************************************************************************************************//** + * @brief Enable or Disable the WDT Reset when WDT meets underflow or error. + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void WDT_ResetCmd(ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_CONTROL_STATUS(NewState)); + + if (NewState != DISABLE) + { + HT_WDT->MR0 |= MODE0_WDTRETEN_SET; + } + else + { + HT_WDT->MR0 &= MODE0_WDTRETEN_RESET; + } +} + +/*********************************************************************************************************//** + * @brief Enable or Disable protection mechanism of the WDT. + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void WDT_ProtectCmd(ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_CONTROL_STATUS(NewState)); + + if (NewState != DISABLE) + { + HT_WDT->PR = PRCT_SET; + } + else + { + HT_WDT->PR = PRCT_RESET; + } +} + +/*********************************************************************************************************//** + * @brief Set reload value of the WDT. + * @param WDT_WDTV : specify the WDT Reload value. + * This parameter must be a number between 0 and 0x0FFF + * @retval None + ************************************************************************************************************/ +void WDT_SetReloadValue(u16 WDT_WDTV) +{ + /* Check the parameters */ + Assert_Param(IS_WDT_RELOAD(WDT_WDTV)); + + HT_WDT->MR0 = WDT_WDTV | (HT_WDT->MR0 & 0x0000F000); +} + +/*********************************************************************************************************//** + * @brief Get the current reload value of the WDT. + * @retval WDT reload value between 0 and 0x0FFF + ************************************************************************************************************/ +u16 WDT_GetReloadValue(void) +{ + return ((u16)(HT_WDT->MR0 & 0xFFF)); +} + +/*********************************************************************************************************//** + * @brief Set delta value of the WDT. + * @param WDT_WDTD : specify the WDT Delta value. + * This parameter must be a number between 0 and 0x0FFF + * @retval None + ************************************************************************************************************/ +void WDT_SetDeltaValue(u16 WDT_WDTD) +{ + /* Check the parameters */ + Assert_Param(IS_WDT_DELTA(WDT_WDTD)); + + HT_WDT->MR1 = (WDT_WDTD | (HT_WDT->MR1 & 0x00007000)); +} + +/*********************************************************************************************************//** + * @brief Get current delta value of the WDT. + * @retval WDT delta value between 0 and 0x0FFF + ************************************************************************************************************/ +u16 WDT_GetDeltaValue(void) +{ + return ((u16)(HT_WDT->MR1 & 0xFFF)); +} + +/*********************************************************************************************************//** + * @brief Set prescaler value of the WDT. + * @param WDT_PRESCALER: specify the WDT Prescaler value. + * This parameter can be one of the following values: + * @arg WDT_PRESCALER_1 : WDT prescaler set to 1 + * @arg WDT_PRESCALER_2 : WDT prescaler set to 2 + * @arg WDT_PRESCALER_4 : WDT prescaler set to 4 + * @arg WDT_PRESCALER_8 : WDT prescaler set to 8 + * @arg WDT_PRESCALER_16 : WDT prescaler set to 16 + * @arg WDT_PRESCALER_32 : WDT prescaler set to 32 + * @arg WDT_PRESCALER_64 : WDT prescaler set to 64 + * @arg WDT_PRESCALER_128 : WDT prescaler set to 128 + * @retval None + ************************************************************************************************************/ +void WDT_SetPrescaler(u16 WDT_PRESCALER) +{ + /* Check the parameters */ + Assert_Param(IS_WDT_PRESCALER(WDT_PRESCALER)); + + HT_WDT->MR1 = (WDT_PRESCALER | (HT_WDT->MR1 & 0x00000FFF)); +} + +/*********************************************************************************************************//** + * @brief Get the current prescaler value of the WDT. + * @retval WDT prescaler value + ************************************************************************************************************/ +u8 WDT_GetPrescaler(void) +{ + u32 tmp; + + tmp = HT_WDT->MR1 & 0x7000; + tmp >>= 12; + return ((u8)0x1 << tmp); +} + +/*********************************************************************************************************//** + * @brief WDT Restart (Reload WDT Counter) + * @retval None + ************************************************************************************************************/ +void WDT_Restart(void) +{ + HT_WDT->CR = RESTART_KEY | 0x1; +} + +/*********************************************************************************************************//** + * @brief Check whether the specified WDT flag has been set. + * @param WDT_FLAG: specify the flag to be check. + * This parameter can be one of the following values: + * @arg WDT_FLAG_UNDERFLOW : WDT underflow active + * @arg WDT_FLAG_ERROR : WDT error active + * @retval SET or RESET + ************************************************************************************************************/ +FlagStatus WDT_GetFlagStatus(u32 WDT_FLAG) +{ + u32 statusreg = 0; + FlagStatus bitstatus = RESET; + + /* Check the parameters */ + Assert_Param(IS_WDT_FLAG(WDT_FLAG)); + + statusreg = HT_WDT->SR; + + if (statusreg != WDT_FLAG) + { + bitstatus = RESET; + } + else + { + bitstatus = SET; + } + + return bitstatus; +} + +/*********************************************************************************************************//** + * @brief Enable or Disable the WDTLOCK. + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void WDT_LockCmd(ControlStatus NewState) +{ + u32 uRegVale; + + /* Check the parameters */ + Assert_Param(IS_CONTROL_STATUS(NewState)); + + uRegVale = HT_WDT->CSR; + if (NewState != DISABLE) + { + HT_WDT->CSR |= (MODE0_WDTLOCK_SET | (uRegVale & 0x00000001)); + } + else + { + HT_WDT->CSR &= (MODE0_WDTLOCK_RESET | (uRegVale & 0x00000001)); + } +} + +#if (LIBCFG_LSE) +/*********************************************************************************************************//** + * @brief WDT source select. + * @param WDT_SOURCE: LSI or LSE of the WDT source. + * This parameter can be one of the following values: + * @arg WDT_SOURCE_LSI : + * @arg WDT_SOURCE_LSE : + * @retval None + ************************************************************************************************************/ +void WDT_SourceConfig(u32 WDT_SOURCE) +{ + /* Check the parameters */ + Assert_Param(IS_WDT_SOURCE_SELECT(WDT_SOURCE)); + + if (WDT_SOURCE != WDT_SOURCE_LSE) + { + HT_WDT->CSR = WDT_SOURCE_LSI; + } + else + { + HT_WDT->CSR = WDT_SOURCE_LSE; + } +} +#endif +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/ht32f652xx_adc.c b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/ht32f652xx_adc.c new file mode 100644 index 0000000000..3071a5ac0a --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/ht32f652xx_adc.c @@ -0,0 +1,32 @@ +/*********************************************************************************************************//** + * @file ht32f652xx_adc.c + * @version $Rev:: 6921 $ + * @date $Date:: 2023-05-10 #$ + * @brief This file provides all the ADC firmware functions (for backward compatible). + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ + +/* Includes ------------------------------------------------------------------------------------------------*/ +#include "ht32f65xxx_66xxx_adc.c" + +// The original file has been renamed to ht32f65xxx_66xxx_adc.c +// This file is added for backward compatibility. diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/ht32f652xx_opa.c b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/ht32f652xx_opa.c new file mode 100644 index 0000000000..dad9694c5f --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/ht32f652xx_opa.c @@ -0,0 +1,32 @@ +/*********************************************************************************************************//** + * @file ht32f652xx_opa.c + * @version $Rev:: 6919 $ + * @date $Date:: 2023-05-10 #$ + * @brief This file provides all the OPA firmware functions (for backward compatible). + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ + +/* Includes ------------------------------------------------------------------------------------------------*/ +#include "ht32f65xxx_66xxx_opa.c" + +// The original file has been renamed to ht32f65xxx_66xxx_opa.c +// This file is added for backward compatibility. diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/ht32f65xxx_66xxx_adc.c b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/ht32f65xxx_66xxx_adc.c new file mode 100644 index 0000000000..88c5d8aced --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/ht32f65xxx_66xxx_adc.c @@ -0,0 +1,784 @@ +/*********************************************************************************************************//** + * @file ht32f65xxx_66xxx_adc.c + * @version $Rev:: 7367 $ + * @date $Date:: 2023-12-06 #$ + * @brief This file provides all the ADC firmware functions. + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ + +/* Includes ------------------------------------------------------------------------------------------------*/ +#include "ht32f65xxx_66xxx_adc.h" + +/** @addtogroup HT32F5xxxx_Peripheral_Driver HT32F5xxxx Peripheral Driver + * @{ + */ + +/** @defgroup ADC ADC + * @brief ADC driver modules + * @{ + */ + + +/* Private constants ---------------------------------------------------------------------------------------*/ +/** @defgroup ADC_Private_Define ADC private definitions + * @{ + */ +#define ADC_ENABLE_BIT (0x00000080) +#define DUAL_MODE_MASK (0x00000003) +#define ADC_SOFTWARE_RESET (0x00000001) +#define LST_SEQ_SET (0x0000001F) +#define TCR_SC_SET (0x00000001) + +#define HLST_SEQ_SET (0x0000001F) +#define HTCR_SC_SET (0x00000001) + +#define OFR_ADOF_MASK (0x00000FFF) +#define OFR_ADAL (1 << 14) +#define OFR_ADOFE (1 << 15) +/** + * @} + */ + +/* Global functions ----------------------------------------------------------------------------------------*/ +/** @addtogroup ADC_Exported_Functions ADC exported functions + * @{ + */ +/*********************************************************************************************************//** + * @brief Deinitialize the HT_ADCn peripheral registers to their default reset values. + * @param HT_ADCn: where HT_ADCn is the selected ADC from the ADC peripherals. + * @retval None + ************************************************************************************************************/ +void ADC_DeInit(HT_ADC_TypeDef* HT_ADCn) +{ + RSTCU_PeripReset_TypeDef RSTCUReset = {{0}}; + + /* Check the parameters */ + Assert_Param(IS_ADC(HT_ADCn)); + + if (HT_ADCn == HT_ADC0) + { + RSTCUReset.Bit.ADC0 = 1; + } + #if (LIBCFG_ADC1) + else if (HT_ADCn == HT_ADC1) + { + RSTCUReset.Bit.ADC1 = 1; + } + #endif + RSTCU_PeripReset(RSTCUReset, ENABLE); +} + +/*********************************************************************************************************//** + * @brief Reset ADC. + * @param HT_ADCn: is the selected ADC from the ADC peripherals. + * @retval None + ************************************************************************************************************/ +void ADC_Reset(HT_ADC_TypeDef* HT_ADCn) +{ + /* Check the parameters */ + Assert_Param(IS_ADC(HT_ADCn)); + + HT_ADCn->RST |= ADC_SOFTWARE_RESET; +} + +/*********************************************************************************************************//** + * @brief Enable or Disable the specified ADC. + * @param HT_ADCn: where HT_ADCn is the selected ADC from the ADC peripherals. + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void ADC_Cmd(HT_ADC_TypeDef* HT_ADCn, ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_ADC(HT_ADCn)); + Assert_Param(IS_CONTROL_STATUS(NewState)); + + if (NewState != DISABLE) + { + HT_ADCn->CONV |= ADC_ENABLE_BIT; + } + else + { + HT_ADCn->CONV &= ~(ADC_ENABLE_BIT); + } +} + +#if (LIBCFG_ADC1) +/*********************************************************************************************************//** + * @brief Configure the ADC dual mode. + * @param HT_ADCn: where HT_ADCn is the selected ADC from the ADC peripherals. (ADC1 only) + * @param DUAL_X: ADC dual mode configuration. + * This parameter can be one of the following values: + * @arg DUAL_INDEPENDENT : Independent mode (dual mode off). + * @arg DUAL_CASCADE_REGULAR : Cascade mode in regular conversion. + * @arg DUAL_CASCADE_REGULAR_H_PRIORITY : Cascade mode in regular/high priority conversion. + * @param HDelayTime: High priority ADC trigger delay. + * This parameter must be between 0x00 to 0xFF. + * @param DelayTime: Regular ADC trigger delay. + * This parameter must be between 0x00 to 0xFF. + * @retval None + ************************************************************************************************************/ +void ADC_DualModeConfig(HT_ADC_TypeDef* HT_ADCn, u32 DUAL_X, u8 HDelayTime, u8 DelayTime) +{ + u32 uTmpReg1, uTmpReg2; + /* Check the parameters */ + Assert_Param(IS_ADC(HT_ADCn)); + Assert_Param(IS_ADC_DUAL_MODE(DUAL_X)); + + uTmpReg1 = HT_ADCn->CFGR; + uTmpReg2 = (DUAL_MODE_MASK | 0x00FFFF00); + uTmpReg1 &= ~uTmpReg2; + uTmpReg2 = (DUAL_X | HDelayTime << 16 | DelayTime << 8); + uTmpReg1 |= uTmpReg2; + + HT_ADCn->CFGR = uTmpReg1; +} +#endif + +/*********************************************************************************************************//** + * @brief Configure conversion mode and length of list queue for regular group. + * @param HT_ADCn: where HT_ADCn is the selected ADC from the ADC peripherals. + * @param ADC_MODE: ADC Cyclic Conversion Mode. + * This parameter can be one of the following values: + * @arg ONE_SHOT_MODE : + * @arg CONTINUOUS_MODE : + * @arg DISCONTINUOUS_MODE : + * @param Length: must between 1 ~ 16 + * @param SubLength: must between 1 ~ 16, only valid for DISCONTINUOUS_MODE. + * @retval None + ************************************************************************************************************/ +void ADC_RegularGroupConfig(HT_ADC_TypeDef* HT_ADCn, u8 ADC_MODE, u8 Length, u8 SubLength) +{ + /* Check the parameters */ + Assert_Param(IS_ADC(HT_ADCn)); + Assert_Param(IS_ADC_CONVERSION_MODE(ADC_MODE)); + Assert_Param(IS_ADC_REGULAR_LENGTH(Length)); + if (ADC_MODE == DISCONTINUOUS_MODE) + { + Assert_Param(IS_ADC_REGULAR_SUB_LENGTH(SubLength)); + } + + /* Config cyclic conversion mode and length of list queue and sub length for regular group */ + HT_ADCn->CONV = ((u32)(SubLength - 1) << 16) | ((u32)(Length - 1) << 8) | ADC_MODE | (HT_ADCn->CONV & ADC_ENABLE_BIT); +} + +/*********************************************************************************************************//** + * @brief Configure conversion mode and length of list queue for high priority group. + * @param HT_ADCn: where HT_ADCn is the selected ADC from the ADC peripherals. + * @param ADC_MODE: ADC Cyclic Conversion Mode. + * This parameter can be one of the following values: + * @arg ONE_SHOT_MODE : + * @arg CONTINUOUS_MODE : + * @arg DISCONTINUOUS_MODE : + * @param Length: must between 1 ~ 4 + * @param SubLength: must between 1 ~ 4 + * @retval None + ************************************************************************************************************/ +void ADC_HPGroupConfig(HT_ADC_TypeDef* HT_ADCn, u8 ADC_MODE, u8 Length, u8 SubLength) +{ + /* Check the parameters */ + Assert_Param(IS_ADC(HT_ADCn)); + Assert_Param(IS_ADC_CONVERSION_MODE(ADC_MODE)); + Assert_Param(IS_ADC_HP_LENGTH(Length)); + Assert_Param(IS_ADC_HP_SUB_LENGTH(SubLength)); + + /* Config cyclic conversion mode and length of list queue and sub length for regular group */ + HT_ADCn->HCONV = ((u32)(SubLength - 1) << 16) | ((u32)(Length - 1) << 8) | ADC_MODE; +} + +/*********************************************************************************************************//** + * @brief Configure the corresponding rank in the sequencer and the sampling time for the regular channel + * @param HT_ADCn: where HT_ADCn is the selected ADC from the ADC peripherals. + * @param ADC_CH_n: the ADC channel to configure + * This parameter can be one of the following values: + * @arg ADC_CH_n : ADC Channel x selected, x must between 0 ~ 7 + * @arg ADC_CH_GND_VREF : ADC GND VREF selected + * @arg ADC_CH_VDD_VREF : ADC VDD VREF selected + * @param Rank: The rank in the regular group sequencer. + * This parameter must be between 0 to 7. + * @param SampleClock: Number of sampling clocks. + * This parameter must be between 0x00 to 0xFF. + * @retval None + ************************************************************************************************************/ +void ADC_RegularChannelConfig(HT_ADC_TypeDef* HT_ADCn, u8 ADC_CH_n, u8 Rank, u8 SampleClock) +{ + u32 tmpreg1, tmpreg2; + + /* Check the parameters */ + Assert_Param(IS_ADC(HT_ADCn)); + Assert_Param(IS_ADC_CHANNEL(ADC_CH_n)); + Assert_Param(IS_ADC_REGULAR_RANK(Rank)); + Assert_Param(IS_ADC_INPUT_SAMPLING_TIME(SampleClock)); + + /* config sampling clock of correspond ADC input channel */ + HT_ADCn->STR[ADC_CH_n] = SampleClock; + + /* Get the old register value */ + tmpreg1 = HT_ADCn->LST[Rank >> 2]; + /* Calculate the mask to clear */ + tmpreg2 = LST_SEQ_SET << (8 * (Rank & 0x3)); + /* Clear the old SEQx bits for the selected rank */ + tmpreg1 &= ~tmpreg2; + /* Calculate the mask to set */ + tmpreg2 = (u32)ADC_CH_n << (8 * (Rank & 0x3)); + /* Set the SEQx bits for the selected rank */ + tmpreg1 |= tmpreg2; + /* Store the new register value */ + HT_ADCn->LST[Rank >> 2] = tmpreg1; +} + +/*********************************************************************************************************//** + * @brief Configure the corresponding rank in the sequencer and the sample time for the High Priority channel + * @param HT_ADCn: where HT_ADCn is the selected ADC from the ADC peripherals. + * @param ADC_CH_n: the ADC channel to configure + * This parameter can be one of the following values: + * @arg ADC_CH_n : ADC Channel x selected, x must between 0 ~ 7 + * @arg ADC_CH_GND_VREF : ADC GND VREF selected + * @arg ADC_CH_VDD_VREF : ADC VDD VREF selected + * @param Rank: The rank in the high priority group sequencer. + * This parameter must be between 0 to 3. + * @param SampleClock: Number of sampling clocks. + * This parameter must be between 0x00 to 0xFF. + * @retval None + ************************************************************************************************************/ +void ADC_HPChannelConfig(HT_ADC_TypeDef* HT_ADCn, u8 ADC_CH_n, u8 Rank, u8 SampleClock) +{ + u32 tmpreg1, tmpreg2; + + /* Check the parameters */ + Assert_Param(IS_ADC(HT_ADCn)); + Assert_Param(IS_ADC_CHANNEL(ADC_CH_n)); + Assert_Param(IS_ADC_HP_RANK(Rank)); + Assert_Param(IS_ADC_INPUT_SAMPLING_TIME(SampleClock)); + + /* config sampling clock of correspond ADC input channel */ + HT_ADCn->STR[ADC_CH_n] = SampleClock; + + /* Get the old register value */ + tmpreg1 = HT_ADCn->HLST; + /* Calculate the mask to clear */ + tmpreg2 = HLST_SEQ_SET << (8 * (Rank & 0x3)); + /* Clear the old SEQx bits for the selected rank */ + tmpreg1 &= ~tmpreg2; + /* Calculate the mask to set */ + tmpreg2 = (u32)ADC_CH_n << (8 * (Rank & 0x3)); + /* Set the SEQx bits for the selected rank */ + tmpreg1 |= tmpreg2; + /* Store the new register value */ + HT_ADCn->HLST = tmpreg1; +} + +/*********************************************************************************************************//** + * @brief Configure the ADC trigger source for regular channels conversion. + * @param HT_ADCn: where HT_ADCn is the selected ADC from the ADC peripherals. + * @param ADC_TRIG_x: + * This parameter can be one of the following values: + * @arg ADC_TRIG_SOFTWARE : S/W trigger + * @arg ADC_TRIG_EXTI_n : where n can be 0 ~ 15 + * @arg ADC_TRIG_MCTMn_MEVx : where n can be 0 + * @arg ADC_TRIG_MCTM0_DMEVx : where n can be 0* + * @arg ADC_TRIG_MCTM0_MEVxDEVz : where n can be 0 + * @arg ADC_TRIG_MCTMn_MTO : where n can be 0 + * @arg ADC_TRIG_MCTMn_CH0O : where n can be 0 + * @arg ADC_TRIG_MCTMn_CH1O : where n can be 0 + * @arg ADC_TRIG_MCTMn_CH2O : where n can be 0 + * @arg ADC_TRIG_MCTMn_CH3O : where n can be 0 + * @arg ADC_TRIG_MCTMn_CHmMEV : where n can be 0, m can be 0 ~ 3 + * @arg ADC_TRIG_MCTMn_CHmDEV : where n can be 0, m can be 0 ~ 3 + * @arg ADC_TRIG_MCTMn_CHmMDEV : where n can be 0, m can be 0 ~ 3 + * @arg ADC_TRIG_MCTMn_CHALLMEV : where n can be 0 + * @arg ADC_TRIG_MCTMn_CHALLDEV : where n can be 0 + * @arg ADC_TRIG_MCTMn_CHALLMDEV : where n can be 0 + * @arg ADC_TRIG_BFTMn : where n can be 0 ~ 1 + * @arg ADC_TRIG_GPTMn_MTO : where n can be 0 + * @arg ADC_TRIG_GPTMn_CH0O : where n can be 0 + * @arg ADC_TRIG_GPTMn_CH1O : where n can be 0 + * @arg ADC_TRIG_GPTMn_CH2O : where n can be 0 + * @arg ADC_TRIG_GPTMn_CH3O : where n can be 0 + * @arg ADC_TRIG_CMPn : where n can be 0 ~ 3 + * @retval None + ************************************************************************************************************/ +void ADC_RegularTrigConfig(HT_ADC_TypeDef* HT_ADCn, u32 ADC_TRIG_x) +{ + /* Check the parameters */ + Assert_Param(IS_ADC(HT_ADCn)); + Assert_Param(IS_ADC_TRIG(ADC_TRIG_x)); + + /* Config external trigger conversion source of regular group */ + HT_ADCn->TCR = ADC_TRIG_x & 0x0000001F; + HT_ADCn->TSR = ADC_TRIG_x & (~0x0000001F); +} + +/*********************************************************************************************************//** + * @brief Configure the ADC trigger source for high priority channels conversion. + * @param HT_ADCn: where HT_ADCn is the selected ADC from the ADC peripherals. + * @param ADC_TRIG_x: + * This parameter can be one of the following values: + * @arg ADC_TRIG_SOFTWARE : S/W trigger + * @arg ADC_TRIG_EXTI_n : where n can be 0 ~ 15 + * @arg ADC_TRIG_MCTMn_MEVx : where n can be 0 + * @arg ADC_TRIG_MCTM0_DMEVx : where n can be 0* + * @arg ADC_TRIG_MCTM0_MEVxDEVz : where n can be 0 + * @arg ADC_TRIG_MCTMn_MTO : where n can be 0 + * @arg ADC_TRIG_MCTMn_CH0O : where n can be 0 + * @arg ADC_TRIG_MCTMn_CH1O : where n can be 0 + * @arg ADC_TRIG_MCTMn_CH2O : where n can be 0 + * @arg ADC_TRIG_MCTMn_CH3O : where n can be 0 + * @arg ADC_TRIG_MCTMn_CHmMEV : where n can be 0, m can be 0 ~ 3 + * @arg ADC_TRIG_MCTMn_CHmDEV : where n can be 0, m can be 0 ~ 3 + * @arg ADC_TRIG_MCTMn_CHmMDEV : where n can be 0, m can be 0 ~ 3 + * @arg ADC_TRIG_MCTMn_CHALLMEV : where n can be 0 + * @arg ADC_TRIG_MCTMn_CHALLDEV : where n can be 0 + * @arg ADC_TRIG_MCTMn_CHALLMDEV : where n can be 0 + * @arg ADC_TRIG_BFTMn : where n can be 0 ~ 1 + * @arg ADC_TRIG_GPTMn_MTO : where n can be 0 + * @arg ADC_TRIG_GPTMn_CH0O : where n can be 0 + * @arg ADC_TRIG_GPTMn_CH1O : where n can be 0 + * @arg ADC_TRIG_GPTMn_CH2O : where n can be 0 + * @arg ADC_TRIG_GPTMn_CH3O : where n can be 0 + * @arg ADC_TRIG_CMPn : where n can be 0 ~ 3 + * @retval None + ************************************************************************************************************/ +void ADC_HPTrigConfig(HT_ADC_TypeDef* HT_ADCn, u32 ADC_TRIG_x) +{ + /* Check the parameters */ + Assert_Param(IS_ADC(HT_ADCn)); + Assert_Param(IS_ADC_TRIG(ADC_TRIG_x)); + + HT_ADCn->HTCR = ADC_TRIG_x & 0x0000001F; + HT_ADCn->HTSR = ADC_TRIG_x & (~0x0000001F); +} + +#if (!LIBCFG_ADC_NO_OFFSET_REG) +/*********************************************************************************************************//** + * @brief Configure the channel data alignment format. + * @param HT_ADCn: where HT_ADCn is the selected ADC from the ADC peripherals. + * @param ADC_CH_n: the ADC channel to configure + * This parameter can be one of the following values: + * @arg ADC_CH_n : ADC Channel x selected + * @arg ADC_CH_OPAn : ADC channel for OPAn + * @arg ADC_CH_GND_VREF : ADC GND VREF selected + * @arg ADC_CH_VDD_VREF : ADC VDD VREF selected + * @param ADC_ALIGN_x: ADC_ALIGN_RIGHT or ADC_ALIGN_LEFT + * @retval None + ************************************************************************************************************/ +void ADC_ChannelDataAlign(HT_ADC_TypeDef* HT_ADCn, u8 ADC_CH_n, ADC_ALIGN_Enum ADC_ALIGN_x) +{ + u32 OFRValue; + + /* Check the parameters */ + Assert_Param(IS_ADC(HT_ADCn)); + Assert_Param(IS_ADC_CHANNEL(ADC_CH_n)); + Assert_Param(IS_ADC_ALIGN(ADC_ALIGN_x)); + + OFRValue = HT_ADCn->OFR[ADC_CH_n] & (~(OFR_ADAL)); + OFRValue |= ADC_ALIGN_x; + + HT_ADCn->OFR[ADC_CH_n] = OFRValue; +} + +/*********************************************************************************************************//** + * @brief Configure the offset value for channel offset cancellation. + * @param HT_ADCn: where HT_ADCn is the selected ADC from the ADC peripherals. + * @param ADC_CH_n: the ADC channel to configure + * This parameter can be one of the following values: + * @arg ADC_CH_n : ADC Channel x selected + * @arg ADC_CH_OPAn : ADC channel for OPAn + * @arg ADC_CH_GND_VREF : ADC GND VREF selected + * @arg ADC_CH_VDD_VREF : ADC VDD VREF selected + * @param OffsetValue: The offset value + * @retval None + ************************************************************************************************************/ +void ADC_ChannelOffsetValue(HT_ADC_TypeDef* HT_ADCn, u8 ADC_CH_n, u16 OffsetValue) +{ + u32 OFRValue; + + /* Check the parameters */ + Assert_Param(IS_ADC(HT_ADCn)); + Assert_Param(IS_ADC_CHANNEL(ADC_CH_n)); + Assert_Param(IS_ADC_OFFSET(OffsetValue)); + + OFRValue = HT_ADCn->OFR[ADC_CH_n] & (~OFR_ADOF_MASK); + OFRValue |= (OffsetValue & 0xFFF); + HT_ADCn->OFR[ADC_CH_n] = OFRValue; +} + +/*********************************************************************************************************//** + * @brief Enable or Disable the channel offset cancellation function. + * @param HT_ADCn: where HT_ADCn is the selected ADC from the ADC peripherals. + * @param ADC_CH_n: the ADC channel to configure + * This parameter can be one of the following values: + * @arg ADC_CH_n : ADC Channel x selected + * @arg ADC_CH_OPAn : ADC channel for OPAn + * @arg ADC_CH_GND_VREF : ADC GND VREF selected + * @arg ADC_CH_VDD_VREF : ADC VDD VREF selected + * @param NewState: ENABLE DISABLE + * @retval None + ************************************************************************************************************/ +void ADC_ChannelOffsetCmd(HT_ADC_TypeDef* HT_ADCn, u8 ADC_CH_n, ControlStatus NewState) +{ + u32 OFRValue; + + /* Check the parameters */ + Assert_Param(IS_ADC(HT_ADCn)); + Assert_Param(IS_ADC_CHANNEL(ADC_CH_n)); + Assert_Param(IS_CONTROL_STATUS(NewState)); + + OFRValue = HT_ADCn->OFR[ADC_CH_n] & (~(OFR_ADOFE)); + + if (NewState == ENABLE) + { + OFRValue |= OFR_ADOFE; + } + + HT_ADCn->OFR[ADC_CH_n] = OFRValue; +} +#endif + +#if (LIBCFG_ADC_TRIG_DELAY) +/*********************************************************************************************************//** + * @brief Configure the ADC Trigger Delay. + * @param HT_ADCn: where HT_ADCn is the selected ADC from the ADC peripherals. (ADC1 only) + * @param HDelayTime: High priority ADC trigger delay. + * This parameter must be between 0x00 to 0xFF. + * @param DelayTime: Regular ADC trigger delay. + * This parameter must be between 0x00 to 0xFF. + * @retval None + ************************************************************************************************************/ +void ADC_TrigDelayConfig(HT_ADC_TypeDef* HT_ADCn, u8 HDelayTime, u8 DelayTime) +{ + /* Check the parameters */ + Assert_Param(IS_ADC(HT_ADCn)); + + HT_ADCn->CFGR = (HDelayTime << 16 | DelayTime << 8); +} +#endif + +/*********************************************************************************************************//** + * @brief Enable or Disable software start of the regular channel conversion of the selected ADC. + * @param HT_ADCn: where HT_ADCn is the selected ADC from the ADC peripherals. + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void ADC_SoftwareStartConvCmd(HT_ADC_TypeDef* HT_ADCn, ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_ADC(HT_ADCn)); + Assert_Param(IS_CONTROL_STATUS(NewState)); + + /* Start Conversion */ + if (NewState != DISABLE) + { + HT_ADCn->TSR |= TCR_SC_SET; + } + else + { + HT_ADCn->TSR &= ~TCR_SC_SET; + } +} + +/*********************************************************************************************************//** + * @brief Enable or Disable software start of the high priority channel conversion of the selected ADC. + * @param HT_ADCn: where HT_ADCn is the selected ADC from the ADC peripherals. + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void ADC_HPSoftwareStartConvCmd(HT_ADC_TypeDef* HT_ADCn, ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_ADC(HT_ADCn)); + Assert_Param(IS_CONTROL_STATUS(NewState)); + + /* Start Conversion */ + if (NewState != DISABLE) + { + HT_ADCn->HTSR |= HTCR_SC_SET; + } + else + { + HT_ADCn->HTSR &= ~HTCR_SC_SET; + } +} + +/*********************************************************************************************************//** + * @brief Return the result of ADC regular channel conversion. + * @param HT_ADCn: where HT_ADCn is the selected ADC from the ADC peripherals. + * @param ADC_REGULAR_DATAn: where n can be 0 ~ 7 + * @retval The Value of data conversion. + ************************************************************************************************************/ +u16 ADC_GetConversionData(HT_ADC_TypeDef* HT_ADCn, u8 ADC_REGULAR_DATAn) +{ + /* Check the parameters */ + Assert_Param(IS_ADC(HT_ADCn)); + Assert_Param(IS_ADC_REGULAR_DATA(ADC_REGULAR_DATAn)); + + return ((u16)HT_ADCn->DR[ADC_REGULAR_DATAn]); +} + +/*********************************************************************************************************//** + * @brief Return the result of ADC high priority channel conversion. + * @param HT_ADCn: where HT_ADCn is the selected ADC from the ADC peripherals. + * @param ADC_HP_DATAn: where x can be 0 ~ 3 + * @retval The Value of data conversion. + ************************************************************************************************************/ +u16 ADC_GetHPConversionData(HT_ADC_TypeDef* HT_ADCn, u8 ADC_HP_DATAn) +{ + /* Check the parameters */ + Assert_Param(IS_ADC(HT_ADCn)); + Assert_Param(IS_ADC_HP_DATA(ADC_HP_DATAn)); + + return ((u16)HT_ADCn->HDR[ADC_HP_DATAn]); +} + +/*********************************************************************************************************//** + * @brief Enable or Disable the specified ADC interrupts. + * @param HT_ADCn: where HT_ADCn is the selected ADC from the ADC peripherals. + * @param ADC_INT_x: Specify the ADC interrupt sources that is to be enabled or disabled. + * This parameter can be any combination of the following values: + * @arg ADC_INT_SINGLE_EOC : + * @arg ADC_INT_SUB_GROUP_EOC : + * @arg ADC_INT_CYCLE_EOC : + * @arg ADC_INT_HP_SINGLE_EOC : + * @arg ADC_INT_HP_SUB_GROUP_EOC : + * @arg ADC_INT_HP_CYCLE_EOC : + * @arg ADC_INT_DATA_OVERWRITE : + * @arg ADC_INT_HP_DATA_OVERWRITE : + * @arg ADC_INT_AWD_LOWER : + * @arg ADC_INT_AWD_UPPER : + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void ADC_IntConfig(HT_ADC_TypeDef* HT_ADCn, u32 ADC_INT_x, ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_ADC(HT_ADCn)); + Assert_Param(IS_ADC_INT(ADC_INT_x)); + Assert_Param(IS_CONTROL_STATUS(NewState)); + + if (NewState != DISABLE) + { + HT_ADCn->IER |= ADC_INT_x; + } + else + { + HT_ADCn->IER &= ~ADC_INT_x; + } +} + +/*********************************************************************************************************//** + * @brief Check whether the specified ADC interrupt has occurred. + * @param HT_ADCn: where HT_ADCn is the selected ADC from the ADC peripherals. + * @param ADC_INT_x: Specify the interrupt status to check. + * This parameter can be any combination of the following values: + * @arg ADC_INT_SINGLE_EOC : + * @arg ADC_INT_SUB_GROUP_EOC : + * @arg ADC_INT_CYCLE_EOC : + * @arg ADC_INT_HP_SINGLE_EOC : + * @arg ADC_INT_HP_SUB_GROUP_EOC : + * @arg ADC_INT_HP_CYCLE_EOC : + * @arg ADC_INT_DATA_OVERWRITE : + * @arg ADC_INT_HP_DATA_OVERWRITE : + * @arg ADC_INT_AWD_LOWER : + * @arg ADC_INT_AWD_UPPER : + * @retval SET or RESET + ************************************************************************************************************/ +FlagStatus ADC_GetIntStatus(HT_ADC_TypeDef* HT_ADCn, u32 ADC_INT_x) +{ + FlagStatus Status; + + /* Check the parameters */ + Assert_Param(IS_ADC(HT_ADCn)); + Assert_Param(IS_ADC_INT(ADC_INT_x)); + + if ((HT_ADCn->ISR & ADC_INT_x) != RESET) + { + Status = SET; + } + else + { + Status = RESET; + } + + return Status; +} + +/*********************************************************************************************************//** + * @brief Clear the ADC interrupt pending bits. + * @param HT_ADCn: where HT_ADCn is the selected ADC from the ADC peripherals. + * @param ADC_INT_x: Specify the interrupt pending bits to be cleared. + * This parameter can be any combination of the following values: + * @arg ADC_INT_SINGLE_EOC : + * @arg ADC_INT_SUB_GROUP_EOC : + * @arg ADC_INT_CYCLE_EOC : + * @arg ADC_INT_HP_SINGLE_EOC : + * @arg ADC_INT_HP_SUB_GROUP_EOC : + * @arg ADC_INT_HP_CYCLE_EOC : + * @arg ADC_INT_DATA_OVERWRITE : + * @arg ADC_INT_HP_DATA_OVERWRITE : + * @arg ADC_INT_AWD_LOWER : + * @arg ADC_INT_AWD_UPPER : + * @retval None + ************************************************************************************************************/ +void ADC_ClearIntPendingBit(HT_ADC_TypeDef* HT_ADCn, u32 ADC_INT_x) +{ + /* Check the parameters */ + Assert_Param(IS_ADC(HT_ADCn)); + Assert_Param(IS_ADC_INT(ADC_INT_x)); + + HT_ADCn->ICLR = ADC_INT_x; +} + +/*********************************************************************************************************//** + * @brief Check whether the specified ADC flag has been set. + * @param HT_ADCn: where HT_ADCn is the selected ADC from the ADC peripherals. + * @param ADC_FLAG_x: Specify the flag to check. + * This parameter can be any combination of the following values: + * @arg ADC_FLAG_SINGLE_EOC : + * @arg ADC_FLAG_SUB_GROUP_EOC : + * @arg ADC_FLAG_CYCLE_EOC : + * @arg ADC_FLAG_HP_SINGLE_EOC : + * @arg ADC_FLAG_HP_SUB_GROUP_EOC : + * @arg ADC_FLAG_HP_CYCLE_EOC : + * @arg ADC_FLAG_DATA_OVERWRITE : + * @arg ADC_FLAG_HP_DATA_OVERWRITE : + * @arg ADC_FLAG_AWD_LOWER : + * @arg ADC_FLAG_AWD_UPPER : + * @retval SET or RESET + ************************************************************************************************************/ +FlagStatus ADC_GetFlagStatus(HT_ADC_TypeDef* HT_ADCn, u32 ADC_FLAG_x) +{ + FlagStatus Status; + + /* Check the parameters */ + Assert_Param(IS_ADC(HT_ADCn)); + Assert_Param(IS_ADC_FLAG(ADC_FLAG_x)); + + if ((HT_ADCn->IRAW & ADC_FLAG_x) != RESET) + { + Status = SET; + } + else + { + Status = RESET; + } + + return Status; +} + +/*********************************************************************************************************//** + * @brief Enable or Disable Lower/Upper threshold warning of the analog watchdog on single/all channels. + * @param HT_ADCn: where HT_ADCn is the selected ADC from the ADC peripherals. + * @param ADC_AWD_x: + * This parameter can be any combination of the following values: + * @arg ADC_AWD_DISABLE : + * @arg ADC_AWD_ALL_LOWER : + * @arg ADC_AWD_ALL_UPPER : + * @arg ADC_AWD_ALL_LOWER_UPPER : + * @arg ADC_AWD_SINGLE_LOWER : + * @arg ADC_AWD_SINGLE_UPPER : + * @arg ADC_AWD_SINGLE_LOWER_UPPER : + * @retval None + ************************************************************************************************************/ +void ADC_AWDConfig(HT_ADC_TypeDef* HT_ADCn, u32 ADC_AWD_x) +{ + /* Check the parameters */ + Assert_Param(IS_ADC(HT_ADCn)); + Assert_Param(IS_ADC_AWD(ADC_AWD_x)); + + HT_ADCn->WCR = (HT_ADCn->WCR & 0xFFFFFFF8) | ADC_AWD_x; +} + +/*********************************************************************************************************//** + * @brief Configure the analog watchdog that guards single channel. + * @param HT_ADCn: where HT_ADCn is the selected ADC from the ADC peripherals. + * @param ADC_CH_n: where n must between 0 ~ 7 + * @retval None + ************************************************************************************************************/ +void ADC_AWDSingleChannelConfig(HT_ADC_TypeDef* HT_ADCn, u8 ADC_CH_n) +{ + /* Check the parameters */ + Assert_Param(IS_ADC(HT_ADCn)); + Assert_Param(IS_ADC_INPUT_CHANNEL(ADC_CH_n)); + + HT_ADCn->WCR = (HT_ADCn->WCR & 0xFFFFF0FF) | ((u32)ADC_CH_n << 8); +} + +/*********************************************************************************************************//** + * @brief Configure the high and low thresholds of the analog watchdog. + * @param HT_ADCn: where HT_ADCn is the selected ADC from the ADC peripherals. + * @param UPPER: must between 0x0000 ~ 0x0FFF + * @param LOWER: must between 0x0000 ~ 0x0FFF + * @retval None + ************************************************************************************************************/ +void ADC_AWDThresholdsConfig(HT_ADC_TypeDef* HT_ADCn, u16 UPPER, u16 LOWER) +{ + /* Check the parameters */ + Assert_Param(IS_ADC(HT_ADCn)); + Assert_Param(IS_ADC_THRESHOLD(UPPER)); + Assert_Param(IS_ADC_THRESHOLD(LOWER)); + + HT_ADCn->LTR = LOWER; + HT_ADCn->UTR = UPPER; +} + +/*********************************************************************************************************//** + * @brief Enable or Disable the specified PDMA request. + * @param HT_ADCn: where HT_ADCn is the selected ADC from the ADC peripherals. + * @param ADC_PDMA_x: Specify the ADC PDMA request that is to be enabled or disabled. + * This parameter can be any combination of the following values: + * @arg ADC_PDMA_REGULAR_SINGLE : + * @arg ADC_PDMA_REGULAR_SUBGROUP : + * @arg ADC_PDMA_REGULAR_CYCLE : + * @arg ADC_PDMA_HP_SINGLE : + * @arg ADC_PDMA_HP_SUBGROUP : + * @arg ADC_PDMA_HP_CYCLE : + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void ADC_PDMAConfig(HT_ADC_TypeDef* HT_ADCn, u32 ADC_PDMA_x, ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_ADC(HT_ADCn)); + Assert_Param(IS_ADC_PDMA(ADC_PDMA_x)); + Assert_Param(IS_CONTROL_STATUS(NewState)); + + if (NewState != DISABLE) + { + HT_ADCn->PDMAR |= ADC_PDMA_x; + } + else + { + HT_ADCn->PDMAR &= ~ADC_PDMA_x; + } +} +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/ht32f65xxx_66xxx_opa.c b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/ht32f65xxx_66xxx_opa.c new file mode 100644 index 0000000000..6df13c0c01 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/ht32f65xxx_66xxx_opa.c @@ -0,0 +1,456 @@ + /*********************************************************************************************************//** + * @file ht32f65xxx_66xxx_opa.c + * @version $Rev:: 6932 $ + * @date $Date:: 2023-05-11 #$ + * @brief This file provides all the OPA firmware functions. + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ + +/* Includes ------------------------------------------------------------------------------------------------*/ +#include "ht32f65xxx_66xxx_opa.h" + +/** @addtogroup HT32F5xxxx_Peripheral_Driver HT32F5xxxx Peripheral Driver + * @{ + */ + +/** @defgroup OPA OPA + * @brief OPA driver modules + * @{ + */ + + +/* Private define ------------------------------------------------------------------------------------------*/ +/** @defgroup OPA_Private_Define OPA private definitions + * @{ + */ +#define OPA_ENABLE (0x00000001ul) +/** + * @} + */ + +/* Private variables ---------------------------------------------------------------------------------------*/ +static u32 gOPAUnProtectKey = 0; + +/* Global functions ----------------------------------------------------------------------------------------*/ +/** @defgroup OPA_Exported_Functions OPA exported functions + * @{ + */ +/*********************************************************************************************************//** + * @brief Deinitialize the OPA peripheral registers to their default reset values. + * @retval None + ************************************************************************************************************/ +void OPA_DeInit(void) +{ + RSTCU_PeripReset_TypeDef RSTCUReset = {{0}}; + + RSTCUReset.Bit.OPA = 1; + RSTCU_PeripReset(RSTCUReset, ENABLE); +} + +/*********************************************************************************************************//** + * @brief Enable or Disable the specified OPA peripheral. + * @param HT_OPAn: where HT_OPAn is the selected OPA from the OPA peripherals, x can be 0 or 1. + * @param NewState: new state of the HT_OPAn peripheral. + * This parameter can be: ENABLE or DISABLE. + * @retval None +************************************************************************************************************/ +void OPA_Cmd(HT_OPA_TypeDef* HT_OPAn, ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_OPA(HT_OPAn)); + Assert_Param(IS_CONTROL_STATUS(NewState)); + + HT_OPAn->CR = gOPAUnProtectKey; + + if (NewState != DISABLE) + { + /* Enable the selected HT_OPAn peripheral */ + HT_OPAn->CR |= OPA_ENABLE; + } + else + { + /* Disable the selected HT_OPAn peripheral */ + HT_OPAn->CR &= ~(u32)OPA_ENABLE; + } +} + +/*********************************************************************************************************//** + * @brief Set the unprotect key. + * @param uUnProtectKey: protect key, shall be OPA_UNPROTECT_KEY + * @retval None + ************************************************************************************************************/ +void OPA_SetUnProtectKey(u32 uUnProtectKey) +{ + gOPAUnProtectKey = uUnProtectKey << 16; +} + +/*********************************************************************************************************//** + * @brief Protect the selected OPA before setting the OPA Control Register. + * @param HT_OPAn: where HT_OPAn is the selected OPA from the OPA peripherals. + * @retval None + ************************************************************************************************************/ +void OPA_ProtectConfig(HT_OPA_TypeDef* HT_OPAn) +{ + /* Check the parameters */ + Assert_Param(IS_OPA(HT_OPAn)); + + /* Write any value to bit 16 ~ 31 (PROTECT) and keep the other control bir */ + HT_OPAn->CR = HT_OPAn->CR; +} + +/*********************************************************************************************************//** + * @brief Unprotect the selected OPA before setting the OPA Control Register. + * @param HT_OPAn: where HT_OPAn is the selected OPA from the OPA peripherals. + * @retval None + ************************************************************************************************************/ +void OPA_UnprotectConfig(HT_OPA_TypeDef* HT_OPAn) +{ + u32 CRValue; + + /* Check the parameters */ + Assert_Param(IS_OPA(HT_OPAn)); + + /* Set the unlock code corresponding to selected OPA */ + CRValue = HT_OPAn->CR & 0x0000FFFF; + HT_OPAn->CR = gOPAUnProtectKey | CRValue; +} + +#if (LIBCFG_OPA_V2) +/*********************************************************************************************************//** + * @brief Initialize the OPA peripheral according to the specified parameters in the OPA_InitStruct. + * @param HT_OPAn: where HT_OPAn is the selected OPA from the OPA peripherals. + * @param OPA_InitStruct: pointer to a OPA_InitTypeDef structure. + * @retval None + ************************************************************************************************************/ +void OPA_Init(HT_OPA_TypeDef* HT_OPAn, OPA_InitTypeDef* OPA_InitStruct) +{ + /* !!! NOTICE !!! + Must call the following functions first. + OPA_SetUnProtectKey(OPA_UNPROTECT_KEY); + OPA_UnprotectConfig(); + */ + + /* Check the parameters */ + Assert_Param(IS_OPA(HT_OPAn)); + Assert_Param(IS_OPA_ScalerEnable(OPA_InitStruct->OPA_ScalerEnable)); + Assert_Param(IS_OPA_ExtPinEnable(OPA_InitStruct->OPA_ExternalPinEnable)); + #if (LIBCFG_OPA_PGA) + Assert_Param(IS_OPA_PGAEnable(OPA_InitStruct->OPA_PGAEnable)); + Assert_Param(IS_OPA_UnitGainEnable(OPA_InitStruct->OPA_UnitGainEnable)); + Assert_Param(IS_OPA_PGA_SEL(OPA_InitStruct->OPA_PGAGain)); + #endif + + #if (LIBCFG_OPA_PGA) + /* avoid both PGA and unit gain active at the same time */ + if (OPA_InitStruct->OPA_UnitGainEnable == OPA_UNITGAIN_ENABLE) + { + OPA_InitStruct->OPA_PGAEnable = OPA_PGA_DISABLE; + } + #endif + + #if (LIBCFG_OPA_PGA) + HT_OPAn->CR = OPA_InitStruct->OPA_ScalerEnable | OPA_InitStruct->OPA_PGAGain | \ + OPA_InitStruct->OPA_ExternalPinEnable | OPA_InitStruct->OPA_PGAEnable | \ + OPA_InitStruct->OPA_UnitGainEnable; + #else + HT_OPAn->CR = OPA_InitStruct->OPA_ScalerEnable | \ + OPA_InitStruct->OPA_ExternalPinEnable; + #endif +} + +/*********************************************************************************************************//** + * @brief Fill each OPA_InitStruct member with its default value. + * @param OPA_InitStruct: pointer to an OPA_InitTypeDef structure. + * @retval None + ************************************************************************************************************/ +void OPA_StructInit(OPA_InitTypeDef* OPA_InitStruct) +{ + /* OPA_InitStruct members default value */ + OPA_InitStruct->OPA_ScalerEnable = OPA_SCALER_DISABLE; + OPA_InitStruct->OPA_ExternalPinEnable = OPA_ExternalPin_DISABLE; + #if (LIBCFG_OPA_PGA) + OPA_InitStruct->OPA_PGAEnable = OPA_PGA_DISABLE; + OPA_InitStruct->OPA_UnitGainEnable = OPA_UNITGAIN_DISABLE; + OPA_InitStruct->OPA_PGAGain = PGA_GAIN_6; + #endif +} + +/*********************************************************************************************************//** + * @brief Enable or Disable the OPA External Input. + * @param HT_OPAn: where HT_OPAn is the selected OPA from the OPA peripherals. + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void OPA_ExternalInputCmd(HT_OPA_TypeDef* HT_OPAn, ControlStatus NewState) +{ + u32 OPA_CR = (u32)(&HT_OPAn->CR); + + /* Check the parameters */ + Assert_Param(IS_OPA(HT_OPAn)); + Assert_Param(IS_CONTROL_STATUS(NewState)); + + HT_OPAn->CR = gOPAUnProtectKey; + + if (NewState != DISABLE) + { + SetBit_BB(OPA_CR, 3); + } + else + { + ResetBit_BB(OPA_CR, 3); + } +} + +#if (LIBCFG_OPA_PGA) +/*********************************************************************************************************//** + * @brief Enable or Disable the Unit Gain. + * @param HT_OPAn: where HT_OPAn is the selected OPA from the OPA peripherals. + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void OPA_UnitGainCmd(HT_OPA_TypeDef* HT_OPAn, ControlStatus NewState) +{ + u32 OPA_CR = (u32)(&HT_OPAn->CR); + u32 CRValue; + + /* Check the parameters */ + Assert_Param(IS_OPA(HT_OPAn)); + Assert_Param(IS_CONTROL_STATUS(NewState)); + + CRValue = HT_OPAn->CR & (~(0x06UL)); // reset unit gain & PGA + + if (NewState == ENABLE) + { + CRValue |= 0x2; + } + + HT_OPAn->CR = gOPAUnProtectKey; + HT_OPAn->CR = CRValue; +} + +/*********************************************************************************************************//** + * @brief Enable or Disable the PGA. + * @param HT_OPAn: where HT_OPAn is the selected OPA from the OPA peripherals. + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void OPA_PGACmd(HT_OPA_TypeDef* HT_OPAn, ControlStatus NewState) +{ + u32 OPA_CR = (u32)(&HT_OPAn->CR); + u32 CRValue; + + /* Check the parameters */ + Assert_Param(IS_OPA(HT_OPAn)); + Assert_Param(IS_CONTROL_STATUS(NewState)); + + CRValue = HT_OPAn->CR & (~(0x06UL)); // reset unit gain & PGA + + if (NewState == ENABLE) + { + CRValue |= 0x4; // set PGA + } + + HT_OPAn->CR = gOPAUnProtectKey; + HT_OPAn->CR = CRValue; +} + +/*********************************************************************************************************//** + * @brief Configure the Gain Selection for the PGA. + * @param HT_OPAn: where HT_OPAn is the selected OPA from the OPA peripherals. + * @param GAIN_SEL : + * This parameter can be one of the following value: + * @arg PGA_GAIN_6 : + * @arg PGA_GAIN_8 : + * @arg PGA_GAIN_12 : + * @arg PGA_GAIN_16 : + * @arg PGA_GAIN_24 : + * @arg PGA_GAIN_32 : + * @arg PGA_GAIN_48 : + * @arg PGA_GAIN_64 : + * @arg PGA_GAIN_5 : + * @arg PGA_GAIN_7 : + * @arg PGA_GAIN_11 : + * @arg PGA_GAIN_15 : + * @arg PGA_GAIN_23 : + * @arg PGA_GAIN_31 : + * @arg PGA_GAIN_47 : + * @arg PGA_GAIN_63 : + * @retval None + ************************************************************************************************************/ +void OPA_PGAGain(HT_OPA_TypeDef* HT_OPAn, u8 bGAIN_SEL) +{ + u32 CRValue; + + /* Check the parameters */ + Assert_Param(IS_OPA(HT_OPAn)); + Assert_Param(IS_OPA_PGA_SEL(bGAIN_SEL)); + + CRValue = HT_OPAn->CR & (~0x70UL); + CRValue |= (u32)bGAIN_SEL << 4; + + HT_OPAn->CR = gOPAUnProtectKey; + HT_OPAn->CR = CRValue; +} +#endif + +/*********************************************************************************************************//** + * @brief Enable or Disable the 10bit Scaler. + * @param HT_OPAn: where HT_OPAn is the selected OPA from the OPA peripherals. + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void OPA_ScalerCmd(HT_OPA_TypeDef* HT_OPAn, ControlStatus NewState) +{ + u32 OPA_CR = (u32)(&HT_OPAn->CR); + + /* Check the parameters */ + Assert_Param(IS_OPA(HT_OPAn)); + Assert_Param(IS_CONTROL_STATUS(NewState)); + + HT_OPAn->CR = gOPAUnProtectKey; + + if (NewState != DISABLE) + { + SetBit_BB(OPA_CR, 8); + } + else + { + ResetBit_BB(OPA_CR, 8); + } +} + +/*********************************************************************************************************//** + * @brief Set the specified reference value in the data register of the scaler. + * @param HT_OPAn: where HT_OPAn is the selected OPA from the OPA peripherals. + * @param Scaler_Value: value to be loaded in the selected data register. + * @retval None + ************************************************************************************************************/ +void OPA_SetScalerValue(HT_OPA_TypeDef* HT_OPAn, u32 Scaler_Value) +{ + /* Check the parameters */ + Assert_Param(IS_OPA(HT_OPAn)); + Assert_Param(IS_OPA_SCALER_VALUE(Scaler_Value)); + + HT_OPAn->DAC = Scaler_Value; +} + +/*********************************************************************************************************//** + * @brief Get the output status of the specified HT_OPAn. + * @param HT_OPAn: where CMPx is the selected OPA from the OPA peripherals. + * @retval SET or RESET + ************************************************************************************************************/ +FlagStatus OPA_GetOutputStatus(HT_OPA_TypeDef* HT_OPAn) +{ + /* Check the parameters */ + Assert_Param(IS_OPA(HT_OPAn)); + + if ((HT_OPAn-> CR & OPA_OUTPUT_HIGH) != 0) + { + return SET; + } + else + { + return RESET; + } +} + +/*********************************************************************************************************//** + * @brief Select OPA Operation Mode. + * @param HT_OPAn: where HT_OPAn is the selected OPA from the OPA peripherals. + * @param MODE: + * This parameter can be one of the following value: + * @arg OPA_OFFSET_CALIBRATION_MODE : + * @arg OPA_NORMAL_MODE : + * @retval None + ************************************************************************************************************/ +void OPA_OFMMode(HT_OPA_TypeDef* HT_OPAn, u8 MODE) +{ + u32 OPA_VOS = (u32)(&HT_OPAn->VOS); + + /* Check the parameters */ + Assert_Param(IS_OPA(HT_OPAn)); + Assert_Param(IS_OPA_OFMMODE(MODE)); + + if (MODE != OPA_NORMAL_MODE) + { + SetBit_BB(OPA_VOS, 7); + } + else + { + ResetBit_BB(OPA_VOS, 7); + } +} + +/*********************************************************************************************************//** + * @brief Select OPA Operation Mode. + * @param HT_OPAn: where HT_OPAn is the selected OPA from the OPA peripherals. + * @param SEL: + * This parameter can be one of the following value: + * @arg OPA_INPUT_OFFSET_INN : + * @arg OPA_INPUT_OFFSET_INP : + * @retval None + ************************************************************************************************************/ +void OPA_OFM_InputOffsetReferenceSelect(HT_OPA_TypeDef* HT_OPAn, u8 SEL) +{ + u32 OPA_VOS = (u32)(&HT_OPAn->VOS); + + /* Check the parameters */ + Assert_Param(IS_OPA(HT_OPAn)); + Assert_Param(IS_OPA_INPUTOFFSET_SEL(SEL)); + + if (SEL != OPA_INPUT_OFFSET_INN) + { + SetBit_BB(OPA_VOS, 6); + } + else + { + ResetBit_BB(OPA_VOS, 6); + } +} + +/*********************************************************************************************************//** + * @brief Configure the input offset calibration voltage for the OPA. + * @param HT_OPAn: where HT_OPAn is the selected OPA from the OPA peripherals. + * @param Data: Set the input offset calibration voltage value. + * @retval None + ************************************************************************************************************/ +void OPA_SetInputOffsetVoltage(HT_OPA_TypeDef* HT_OPAn, u8 Data) +{ + /* Check the parameters */ + Assert_Param(IS_OPA(HT_OPAn)); + Assert_Param(IS_OPA_INPUTOFFSET_VALUE(Data)); + + HT_OPAn->VOS = (HT_OPAn->VOS & 0xFFFFFF70) | (Data & 0x1F); +} +#endif +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/ht32f65xxx_66xxx_pga.c b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/ht32f65xxx_66xxx_pga.c new file mode 100644 index 0000000000..6dacca7f49 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/ht32f65xxx_66xxx_pga.c @@ -0,0 +1,49 @@ +/*********************************************************************************************************//** + * @file ht32f65xxx_66xxx_pga.c + * @version $Rev:: 6914 $ + * @date $Date:: 2023-05-10 #$ + * @brief This file provides all the PGA firmware functions. (temporary file, not finish/support yet). + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ + +/* Includes ------------------------------------------------------------------------------------------------*/ +#include "ht32f65xxx_66xxx_pga.h" + +/** @addtogroup HT32F5xxxx_Peripheral_Driver HT32F5xxxx Peripheral Driver + * @{ + */ + +/** @defgroup PGA PGA + * @brief PGA driver modules + * @{ + */ + + + + +/** + * @} + */ + +/** + * @} + */ diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/ht32f66xxx_cordic.c b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/ht32f66xxx_cordic.c new file mode 100644 index 0000000000..724e166fbe --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/ht32f66xxx_cordic.c @@ -0,0 +1,49 @@ +/*********************************************************************************************************//** + * @file ht32f66xxx_cordic.c + * @version $Rev:: 6914 $ + * @date $Date:: 2023-05-10 #$ + * @brief This file provides all the CORDIC firmware functions. (temporary file, not finish/support yet). + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ + +/* Includes ------------------------------------------------------------------------------------------------*/ +#include "ht32f66xxx_cordic.h" + +/** @addtogroup HT32F5xxxx_Peripheral_Driver HT32F5xxxx Peripheral Driver + * @{ + */ + +/** @defgroup CORDIC CORDIC + * @brief CORDIC driver modules + * @{ + */ + + + + +/** + * @} + */ + +/** + * @} + */ diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/ht32f66xxx_pid.c b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/ht32f66xxx_pid.c new file mode 100644 index 0000000000..d956f5fcf9 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/ht32f66xxx_pid.c @@ -0,0 +1,49 @@ +/*********************************************************************************************************//** + * @file ht32f66xxx_pid.c + * @version $Rev:: 6914 $ + * @date $Date:: 2023-05-10 #$ + * @brief This file provides all the PID firmware functions. (temporary file, not finish/support yet). + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ + +/* Includes ------------------------------------------------------------------------------------------------*/ +#include "ht32f66xxx_pid.h" + +/** @addtogroup HT32F5xxxx_Peripheral_Driver HT32F5xxxx Peripheral Driver + * @{ + */ + +/** @defgroup PID PID + * @brief PID driver modules + * @{ + */ + + + + +/** + * @} + */ + +/** + * @} + */ diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/printf.c b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/printf.c new file mode 100644 index 0000000000..4f3515330c --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/printf.c @@ -0,0 +1,390 @@ +/*********************************************************************************************************//** + * @file printf.c + * @version $Rev:: 93 $ + * @date $Date:: 2015-11-24 #$ + * @brief Print functions. + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ + +/* Includes ------------------------------------------------------------------------------------------------*/ +#include "ht32.h" +#include + +/** @addtogroup HT32_Peripheral_Driver HT32 Peripheral Driver + * @{ + */ + +/** @defgroup PRINTF printf re-implementation + * @brief printf related functions + * @{ + */ + + +/* Private macro -------------------------------------------------------------------------------------------*/ +/** @defgroup PRINTF_Private_Macro printf private macros + * @{ + */ +#define vaStart(list, param) list = (char*)((int)¶m + sizeof(param)) +#define vaArg(list, type) ((type *)(list += sizeof(type)))[-1] +/** + * @} + */ + +/* Private function prototypes -----------------------------------------------------------------------------*/ +static const char *FormatItem(const char *f, int a); +static void PutRepChar(const char c, int count); +static int PutString(const char *pString); +static int PutStringReverse(const char *pString, int index); +static void PutNumber(int value, int radix, int width, char fill); + +/* Global functions ----------------------------------------------------------------------------------------*/ +/** @defgroup PRINTF_Exported_Functions printf exported functions + * @{ + */ +/*********************************************************************************************************//** + * @brief Print function. + * @param f: Format string. + * @retval String length. + ************************************************************************************************************/ +signed int printf(const char *f, ...) +{ + char *argP; + int i = 0; + + vaStart(argP, f); + while (*f) + { + if (*f == '%') + { + f = FormatItem(f + 1, vaArg(argP, int)); + } + else + { + fputc(*f++, (FILE *)1); + } + i++; + } + return i; +} + +/*********************************************************************************************************//** + * @brief Put string. + * @param pString: String. + * @retval String length. + ************************************************************************************************************/ +signed int puts(const char *pString) +{ + int i; + i = PutString(pString); + fputc('\n', (FILE *)1); + return i; +} +/** + * @} + */ + +/* Private functions ---------------------------------------------------------------------------------------*/ +/** @defgroup PRINTF_Private_Function printf private functions + * @{ + */ +/*********************************************************************************************************//** + * @brief Format item for print function. + * @param f: Format string. + * @param a: Length of format string. + * @retval Point of string. + ************************************************************************************************************/ +static const char *FormatItem(const char *f, int a) +{ + char c; + int fieldwidth = 0; + int leftjust = FALSE; + int radix = 0; + char fill = ' '; + int i; + + if (*f == '0') + { + fill = '0'; + } + + while ((c = *f++) != 0) + { + if (c >= '0' && c <= '9') + { + fieldwidth = (fieldwidth * 10) + (c - '0'); + } + else + { + switch (c) + { + case '\000': + { + return (--f); + } + case '%': + { + fputc('%', (FILE *)1); + return (f); + } + case '-': + { + leftjust = TRUE; + break; + } + case 'c': + { + if (leftjust) + { + fputc(a & 0x7f, (FILE *)f); + } + if (fieldwidth > 0) + { + PutRepChar(fill, fieldwidth - 1); + } + if (!leftjust) + { + fputc(a & 0x7f, (FILE *)f); + return (f); + } + } + case 's': + { + i = 0; + while (*((char *)(a + i)) !='\0' ) + { + i++; + } + + if (leftjust) + { + PutString((char *)a); + } + + if (fieldwidth > i ) + { + PutRepChar(fill, fieldwidth - i); + } + + if (!leftjust) + { + PutString((char *)a); + } + return (f); + } + case 'l': + { + radix = -10; + f++; + break; + } + case 'd': + case 'i': + { + radix = -10; + break; + } + case 'u': + { + radix = 10; + break; + } + case 'x': + case 'X': + { + radix = 16; + break; + } + case 'o': + { + radix = 8; + break; + } + default: + { + radix = 3; + break; + } + } + } + if (radix) + { + break; + } + } + + if (leftjust) + { + fieldwidth = -fieldwidth; + } + + PutNumber(a, radix, fieldwidth, fill); + + return (f); +} + +/*********************************************************************************************************//** + * @brief Put repeat character. + * @param c: Character. + * @param count: Repeat count + ************************************************************************************************************/ +static void PutRepChar(const char c, int count) +{ + while (count--) + { + fputc(c, (FILE *)1); + } +} + +/*********************************************************************************************************//** + * @brief Put string. + * @param pString: String. + * @retval String length. + ************************************************************************************************************/ +static int PutString(const char *pString) +{ + int i = 0; + while (*pString != '\0') + { + fputc(*pString, (FILE *)1); + pString++; + i++; + } + + return i; +} + +/*********************************************************************************************************//** + * @brief Put string in reversed order. + * @param pString: String. + * @param index: String length + * @retval String length. + ************************************************************************************************************/ +static int PutStringReverse(const char *pString, int index) +{ + int i = 0; + while ((index--) > 0) + { + fputc(pString[index], (FILE *)1); + i++; + } + return i; +} + +/*********************************************************************************************************//** + * @brief Put number. + * @param value: Value of number. + * @param radix: Radix of number. + * @param width: Width of number. + * @param fill: fill character. + ************************************************************************************************************/ +static void PutNumber(int value, int radix, int width, char fill) +{ + char buffer[8]; + int bi = 0; + unsigned int uvalue; + unsigned short digit; + unsigned short left = FALSE; + unsigned short negative = FALSE; + + if (fill == 0) + { + fill = ' '; + } + + if (width < 0) + { + width = -width; + left = TRUE; + } + + if (width < 0 || width > 80) + { + width = 0; + } + + if (radix < 0) + { + radix = -radix; + if (value < 0) + { + negative = TRUE; + value = -value; + } + } + + uvalue = value; + + do + { + if (radix != 16) + { + digit = uvalue % radix; + uvalue = uvalue / radix; + } + else + { + digit = uvalue & 0xf; + uvalue = uvalue >> 4; + } + buffer[bi] = digit + ((digit <= 9) ? '0' : ('A' - 10)); + bi++; + } + while (uvalue != 0); + + if (negative) + { + buffer[bi] = '-'; + bi += 1; + } + + if (width <= bi) + { + PutStringReverse(buffer, bi); + } + else + { + width -= bi; + if (!left) + { + PutRepChar(fill, width); + } + + PutStringReverse(buffer, bi); + + if (left) + { + PutRepChar(fill, width); + } + } +} +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/syscalls.c b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/syscalls.c new file mode 100644 index 0000000000..566ad8da78 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/syscalls.c @@ -0,0 +1,127 @@ +/*********************************************************************************************************//** + * @file syscalls.c + * @version $Rev:: 6830 $ + * @date $Date:: 2023-03-27 #$ + * @brief Implementation of system call related functions. + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ + +/* Includes ------------------------------------------------------------------------------------------------*/ +#include +#include +#include +#include + +/** @addtogroup HT32_Peripheral_Driver HT32 Peripheral Driver + * @{ + */ + +/** @defgroup SYSCALLS System call functions + * @brief System call functions for GNU toolchain + * @{ + */ + + +/* Global variables ----------------------------------------------------------------------------------------*/ +/** @defgroup SYSCALLS_Global_Variable System call global variables + * @{ + */ +#undef errno +extern int errno; +extern int _end; +/** + * @} + */ + +/* Global functions ----------------------------------------------------------------------------------------*/ +/** @defgroup SYSCALLS_Exported_Functions System call exported functions + * @{ + */ +caddr_t _sbrk(int incr) +{ + static unsigned char *heap = NULL; + unsigned char *prev_heap; + + if (heap == NULL) + { + heap = (unsigned char *)&_end; + } + prev_heap = heap; + + heap += incr; + + return (caddr_t) prev_heap; +} + +int link(char *old, char *new) { +return -1; +} + +int _close(int fd) +{ + return -1; +} + +int _fstat(int fd, struct stat *st) +{ + st->st_mode = S_IFCHR; + return 0; +} + +int _isatty(int fd) +{ + return 1; +} + +int _lseek(int fd, int ptr, int dir) +{ + return 0; +} + +int _read(int fd, char *ptr, int len) +{ + return 0; +} + +int _write(int fd, char *ptr, int len) +{ + return len; +} + +void abort(void) +{ + /* Abort called */ + while (1); +} + +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32_USBD_Library/example/ht32_usbd_class.c b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32_USBD_Library/example/ht32_usbd_class.c new file mode 100644 index 0000000000..928fb2ef33 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32_USBD_Library/example/ht32_usbd_class.c @@ -0,0 +1,426 @@ +/*********************************************************************************************************//** + * @file example/ht32_usbd_class.c + * @version $Rev:: 1234 $ + * @date $Date:: 2016-10-25 #$ + * @brief The USB Device Class. + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ + +/* Includes ------------------------------------------------------------------------------------------------*/ +#include "ht32.h" +#include "ht32_usbd_core.h" +#include "ht32_usbd_class.h" + +/** @addtogroup HT32_USBD_Library HT32 USB Device Library + * @{ + */ + +/** @defgroup USBDClass USB Device Class + * @brief USB Device Class + * @{ + */ + +/* Exported constants --------------------------------------------------------------------------------------*/ +/** @defgroup USBDClass_Private_Define USB Device Class private definitions + * @{ + */ +#define CLASS_REQ_01_CMD1 (u16)(0x1 << 8) +#define CLASS_REQ_02_CMD2 (u16)(0x2 << 8) +/** + * @} + */ + +/* Private function prototypes -----------------------------------------------------------------------------*/ +static void USBDClass_MainRoutine(u32 uPara); +static void USBDClass_ClassProcess(void); +static void USBDClass_EPT1Process(void); +static void USBDClass_EPT2Process(void); + +static void USBDClass_Reset(u32 uPara); +static void USBDClass_StartOfFrame(u32 uPara); + +static void USBDClass_Standard_GetDescriptor(USBDCore_Device_TypeDef *pDev); +static void USBDClass_Standard_SetInterface(USBDCore_Device_TypeDef *pDev); +static void USBDClass_Standard_GetInterface(USBDCore_Device_TypeDef *pDev); + +static void USBDClass_Request(USBDCore_Device_TypeDef *pDev); + +static void USBDClass_CMD1(USBDCore_Device_TypeDef *pDev); +static void USBDClass_CMD2(USBDCore_Device_TypeDef *pDev); + +static void USBDClass_Endpoint1(USBD_EPTn_Enum EPTn); +static void USBDClass_Endpoint2(USBD_EPTn_Enum EPTn); +static void USBDClass_Endpoint3(USBD_EPTn_Enum EPTn); +static void USBDClass_Endpoint4(USBD_EPTn_Enum EPTn); +static void USBDClass_Endpoint5(USBD_EPTn_Enum EPTn); +static void USBDClass_Endpoint6(USBD_EPTn_Enum EPTn); +static void USBDClass_Endpoint7(USBD_EPTn_Enum EPTn); + +/* Global Function -----------------------------------------------------------------------------------------*/ +/** @defgroup USBDClass_Exported_Functions USB Device Class exported functions + * @{ + */ +/*********************************************************************************************************//** + * @brief USB Class initialization. + * @param pClass: pointer of USBDCore_Class_TypeDef + * @retval None + ***********************************************************************************************************/ +void USBDClass_Init(USBDCore_Class_TypeDef *pClass) +{ + pClass->CallBack_MainRoutine.func = USBDClass_MainRoutine; + //pClass->CallBack_MainRoutine.uPara = (u32)NULL; + + pClass->CallBack_Reset.func = USBDClass_Reset; + pClass->CallBack_Reset.uPara = (u32)NULL; + + pClass->CallBack_StartOfFrame.func = USBDClass_StartOfFrame; + pClass->CallBack_StartOfFrame.uPara = (u32)NULL; + + pClass->CallBack_ClassGetDescriptor = USBDClass_Standard_GetDescriptor; + pClass->CallBack_ClassSetInterface = USBDClass_Standard_SetInterface; + pClass->CallBack_ClassGetInterface = USBDClass_Standard_GetInterface; + + pClass->CallBack_ClassRequest = USBDClass_Request; + pClass->CallBack_EPTn[1] = USBDClass_Endpoint1; + pClass->CallBack_EPTn[2] = USBDClass_Endpoint2; + pClass->CallBack_EPTn[3] = USBDClass_Endpoint3; + pClass->CallBack_EPTn[4] = USBDClass_Endpoint4; + pClass->CallBack_EPTn[5] = USBDClass_Endpoint5; + pClass->CallBack_EPTn[6] = USBDClass_Endpoint6; + pClass->CallBack_EPTn[7] = USBDClass_Endpoint7; + + #ifdef RETARGET_IS_USB + pClass->CallBack_EPTn[RETARGET_RX_EPT] = SERIAL_USBDClass_RXHandler; + #endif + + return; +} +/** + * @} + */ + +/* Private functions ---------------------------------------------------------------------------------------*/ +/** @defgroup USBDClass_Private_Functions USB Device Class private functions + * @{ + */ +/*********************************************************************************************************//** + * @brief USB Class main routine. + * @param uPara: Parameter for Class main routine + * @retval None + ***********************************************************************************************************/ +static void USBDClass_MainRoutine(u32 uPara) +{ + USBDClass_ClassProcess(); + USBDClass_EPT1INProcess(); + USBDClass_EPT2OUTProcess(); + + return; +} + +/*********************************************************************************************************//** + * @brief USB Class Process for application. + * @retval None + ***********************************************************************************************************/ +static void USBDClass_ClassProcess(void) +{ + return; +} + +/*********************************************************************************************************//** + * @brief USB Class Endpoint 1 Process for application. + * @retval None + ***********************************************************************************************************/ +static void USBDClass_EPT1Process(void) +{ + if (gIsEP1 == TRUE) + { + gIsEP1 = FALSE; + } + + return; +} + +/*********************************************************************************************************//** + * @brief USB Class Endpoint 2 Process for application. + * @retval None + ***********************************************************************************************************/ +static void USBDClass_EPT2Process(void) +{ + if (gIsEP2 == TRUE) + { + gIsEP2 = FALSE; + } + + return; +} + +/*********************************************************************************************************//** + * @brief USB Class Reset. + * @param uPara: Parameter for Class Reset. + * @retval None + ***********************************************************************************************************/ +static void USBDClass_Reset(u32 uPara) +{ + +} + +/*********************************************************************************************************//** + * @brief USB Class Start of Frame. + * @param uPara: Parameter for Class Start of Frame. + * @retval None + ***********************************************************************************************************/ +static void USBDClass_StartOfFrame(u32 uPara) +{ + +} + +/*********************************************************************************************************//** + * @brief USB Device Class Request + * @param pDev: pointer of USB Device + * @retval None + ***********************************************************************************************************/ +static void USBDClass_Request(USBDCore_Device_TypeDef *pDev) +{ + u16 uUSBCmd = *((u16 *)(&(pDev->Request))); + +#ifdef RETARGET_IS_USB + SERIAL_USBDClass_Request(pDev); +#endif + + switch (uUSBCmd) + { + /*------------------------------------------------------------------------------------------------------*/ + /* | bRequest | Data transfer direction | Type | Recipient | Data */ + /*------------------------------------------------------------------------------------------------------*/ + + /*------------------------------------------------------------------------------------------------------*/ + /* | 01_CMD1 | 80_Device-to-Host | 20_Class Request | 1_Interface | 01A1h */ + /*------------------------------------------------------------------------------------------------------*/ + case (CLASS_REQ_01_CMDID0 | REQ_DIR_01_D2H | REQ_TYPE_01_CLS | REQ_REC_01_INF): + { + __DBG_USBPrintf("%06ld CMD0\t[%02d][%02d]\r\n", __DBG_USBCount, pDev->Request.wValueH, pDev->Request.wLength ); + USBDClass_RequestCMD1(pDev); + break; + } + /*------------------------------------------------------------------------------------------------------*/ + /* | 02_CMD2 | 00_Host-to-Device | 20_Class Request | 1_Interface | 0221h */ + /*------------------------------------------------------------------------------------------------------*/ + case (CLASS_REQ_02_GET_IDLE | REQ_DIR_00_H2D | REQ_TYPE_01_CLS | REQ_REC_01_INF): + { + __DBG_USBPrintf("%06ld CMD1\t[%02d][%02d]\r\n", __DBG_USBCount, pDev->Request.wValueH, pDev->Request.wLength ); + USBDClass_RequestCMD2(pDev); + break; + } + } + + return; +} + +/*********************************************************************************************************//** + * @brief USB Device Class Standard Request - GET_DESCRIPTOR + * @param pDev: pointer of USB Device + * @retval None + ***********************************************************************************************************/ +static void USBDClass_Standard_GetDescriptor(USBDCore_Device_TypeDef *pDev) +{ + u32 type = pDev->Request.wValueH; + + switch (type) + { + case DESC_TYPE_01_XXX + { + pDev->Transfer.pData = (uc8 *)(__BUFFER_POINTER__); + pDev->Transfer.sByteLength = DESC_LEN_XXX; + pDev->Transfer.Action = USB_ACTION_DATAIN; + break; + } + case DESC_TYPE_02_XXX: + { + pDev->Transfer.pData = (uc8 *)(__BUFFER_POINTER__); + pDev->Transfer.sByteLength = DESC_LEN_XXX; + pDev->Transfer.Action = USB_ACTION_DATAIN; + break; + } + } /* switch (type) */ + + return; +} + +/*********************************************************************************************************//** + * @brief USB Device Class Standard Request - SET_INTERFACE + * @param pDev: pointer of USB Device + * @retval None + ***********************************************************************************************************/ +static void USBDClass_Standard_SetInterface(USBDCore_Device_TypeDef *pDev) +{ + +} + +/*********************************************************************************************************//** + * @brief USB Device Class Standard Request - GET_INTERFACE + * @param pDev: pointer of USB Device + * @retval None + ***********************************************************************************************************/ +static void USBDClass_Standard_GetInterface(USBDCore_Device_TypeDef *pDev) +{ + +} + + + +/*********************************************************************************************************//** + * @brief USB Device Class Request - CMD1 + * @param pDev: pointer of USB Device + * @retval None + ***********************************************************************************************************/ +static void USBDClass_CMD1(USBDCore_Device_TypeDef *pDev) +{ + /* Add your own Class request function here.... + For example.... + + u32 uReportID = pDev->Request.wValueL; + u32 uInterface = pDev->Request.wIndex; + + pDev->Transfer.pData = (uc8 *)&(__IDLE_DURATION_BUFFER[uReportID]); + pDev->Transfer.sByteLength = 1; + pDev->Transfer.Action= USB_ACTION_DATAIN; + + */ + return; +} + +/*********************************************************************************************************//** + * @brief USB Device Class Request - CMD2 + * @param pDev: pointer of USB Device + * @retval None + ***********************************************************************************************************/ +static void USBDClass_CMD2(USBDCore_Device_TypeDef *pDev) +{ + /* Add your own Class request function here.... + For example.... + + u32 uReportID = pDev->Request.wValueL; + u32 uInterface = pDev->Request.wIndex; + + pDev->Transfer.pData = (uc8 *)&(__IDLE_DURATION_BUFFER[uReportID]); + pDev->Transfer.sByteLength = 1; + pDev->Transfer.Action= USB_ACTION_DATAIN; + + */ + return; +} + +/*********************************************************************************************************//** + * @brief USB Class Endpoint handler + * @param EPTn: USB Endpoint number + * @arg USBD_EPT0 ~ USBD_EPT7 + * @retval None + ***********************************************************************************************************/ +static void USBDClass_Endpoint1(USBD_EPTn_Enum EPTn) +{ + gIsEP1 = TRUE; + + __DBG_USBPrintf("%06ld EP1\t[%02d]", ++__DBG_USBCount, (int)USBDCore_EPTGetBufferLen(EPTn)); + + return; +} + +/*********************************************************************************************************//** + * @brief USB Class Endpoint handler + * @param EPTn: USB Endpoint number + * @arg USBD_EPT0 ~ USBD_EPT7 + * @retval None + ***********************************************************************************************************/ +static void USBDClass_Endpoint2(USBD_EPTn_Enum EPTn) +{ + gIsEP2 = TRUE; + __DBG_USBPrintf("%06ld EP2\t[%02d]", ++__DBG_USBCount, (int)USBDCore_EPTGetBufferLen(EPTn)); + + return; +} + +/*********************************************************************************************************//** + * @brief USB Class Endpoint handler + * @param EPTn: USB Endpoint number + * @arg USBD_EPT0 ~ USBD_EPT7 + * @retval None + ***********************************************************************************************************/ +static void USBDClass_Endpoint3(USBD_EPTn_Enum EPTn) +{ + return; +} + +/*********************************************************************************************************//** + * @brief USB Class Endpoint handler + * @param EPTn: USB Endpoint number + * @arg USBD_EPT0 ~ USBD_EPT7 + * @retval None + ***********************************************************************************************************/ +static void USBDClass_Endpoint4(USBD_EPTn_Enum EPTn) +{ + return; +} + +/*********************************************************************************************************//** + * @brief USB Class Endpoint handler + * @param EPTn: USB Endpoint number + * @arg USBD_EPT0 ~ USBD_EPT7 + * @retval None + ***********************************************************************************************************/ +static void USBDClass_Endpoint5(USBD_EPTn_Enum EPTn) +{ + return; +} + +/*********************************************************************************************************//** + * @brief USB Class Endpoint handler + * @param EPTn: USB Endpoint number + * @arg USBD_EPT0 ~ USBD_EPT7 + * @retval None + ***********************************************************************************************************/ +static void USBDClass_Endpoint6(USBD_EPTn_Enum EPTn) +{ + return; +} + +/*********************************************************************************************************//** + * @brief USB Class Endpoint handler + * @param EPTn: USB Endpoint number + * @arg USBD_EPT0 ~ USBD_EPT7 + * @retval None + ***********************************************************************************************************/ +static void USBDClass_Endpoint7(USBD_EPTn_Enum EPTn) +{ + return; +} +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32_USBD_Library/example/ht32_usbd_class.h b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32_USBD_Library/example/ht32_usbd_class.h new file mode 100644 index 0000000000..2fe2598bee --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32_USBD_Library/example/ht32_usbd_class.h @@ -0,0 +1,87 @@ +/*********************************************************************************************************//** + * @file example/ht32_usbd_class.h + * @version $Rev:: 47 $ + * @date $Date:: 2015-11-18 #$ + * @brief The header file of USB Device Class. + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------------------------------------*/ +#ifndef __HT32_USBD_CLASS_H +#define __HT32_USBD_CLASS_H + +/* Includes ------------------------------------------------------------------------------------------------*/ + +/** @addtogroup HT32_USBD_Library HT32 USB Device Library + * @{ + */ + +/** @defgroup USBDClass USB Device Class + * @brief USB Device Class + * @{ + */ + + +/* Exported constants --------------------------------------------------------------------------------------*/ +/** @defgroup USBDClass_Private_Define USB Device Class private definitions + * @{ + */ +/* For ht32_usbd_descriptor.c */ +#define CLASS_INF_CLASS (DESC_CLASS_03_XXX) +#define CLASS_INF_SUBCLASS (HID_SUBCLASS_00_NONE) +#define CLASS_INF_PTCO (HID_PROTOCOL_00_NONE) + +/* HID related definition */ +#define DESC_LEN_XXX ((u32)(9)) +#define DESC_LEN_XXX ((u16)(47)) + +#define DESC_TYPE_01_XXX (0x01) +#define DESC_TYPE_02_XXX (0x02) + +#define HID_SUBCLASS_00_NONE (0x00) +#define HID_SUBCLASS_01_BOOT (0x01) + +#define HID_PROTOCOL_00_NONE (0x00) +/** + * @} + */ + + +/* Exported functions --------------------------------------------------------------------------------------*/ +/** @defgroup USBDClass_Exported_Functions USB Device Class exported functions + * @{ + */ +void USBDClass_Init(USBDCore_Class_TypeDef *pClass); +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ + +#endif /* __HT32_USBD_CLASS_H ------------------------------------------------------------------------------*/ diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32_USBD_Library/example/ht32_usbd_descriptor.c b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32_USBD_Library/example/ht32_usbd_descriptor.c new file mode 100644 index 0000000000..c33c0865b9 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32_USBD_Library/example/ht32_usbd_descriptor.c @@ -0,0 +1,368 @@ +/*********************************************************************************************************//** + * @file example/ht32_usbd_descriptor.c + * @version $Rev:: 47 $ + * @date $Date:: 2015-11-18 #$ + * @brief The USB Descriptor. + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ +// <<< Use Configuration Wizard in Context Menu >>> + +/* Includes ------------------------------------------------------------------------------------------------*/ +#include "ht32.h" +#include "ht32_usbd_core.h" +#include "ht32_usbd_class.h" +#include "ht32_usbd_descriptor.h" + +/** @addtogroup HT32_USBD_Library HT32 USB Device Library + * @{ + */ + +/** @defgroup USBDDescriptor USB Descriptor + * @brief USB descriptor + * @{ + */ + + +/*----------------------------------------------------------------------------------------------------------*/ +/* USB Device descriptor setting */ +/*----------------------------------------------------------------------------------------------------------*/ +// USB Device descriptor setting +// USB Specification Release number (bcdUSB) +// <0x0200=> USB 2.0 +// <0x0110=> USB 1.1 +// <0x0100=> USB 1.0 +// USB Class code (assigned by the USB-IF) +// <0x00=> Use class information in the Interface Descriptors (0x00) +// <0x02=> Communications and CDC Control (CDC, 0x02) +// <0xDC=> Diagnostic Device (0xDC) +// <0xEF=> Miscellaneous (0xEF) +// <0xFF=> Vendor Specific (0xFF) +// USB Subclass code (assigned by the USB-IF) <0x0-0xFF:1> +// USB Protocol code (assigned by the USB-IF) <0x0-0xFF:1> +// USB Vendor ID <0x0-0xFFFF:1> +// USB Product ID <0x0-0xFFFF:1> +// USB Device Version <0x0-0xFFFF:1> +// USB String descriptor - Manufacturer +// USB String descriptor - Product +// USB String descriptor - Device serial number +// USB Number of possible configurations <0-255:1> +#define DESC_BCDUSB (0x0110) +#define DESC_BDEVCLASS (0x00) +#define DESC_BDEVSUBCLASS (0x00) +#define DESC_BDEVPROTOCOL (0x00) +#define DESC_IDVENDOR (0x04D9) +#define DESC_IDPRODUCT (0x8008) +#define DESC_BCDDEVICE (0x0100) +#define DESC_IMANUFACTURE (1) +#define DESC_IPRODUCT (1) +#define DESC_ISERIALNUM (1) +#define DESC_INUMCONFN (1) +// + +/*----------------------------------------------------------------------------------------------------------*/ +/* USB Device Descriptor definition. DO NOT MODIFY. */ +/*----------------------------------------------------------------------------------------------------------*/ +#if (DESC_BDEVCLASS == 0x0 & DESC_BDEVSUBCLASS != 0x0) +#error "DESC_BDEVSUBCLASS must be reset to zero when the DESC_BDEVCLASS is equal to zero." +#endif +#define DESC_WMAXPACKETSIZE0 (_EP0LEN) +#define DESC_STR_MAN (1 * DESC_IMANUFACTURE) +#define DESC_STR_PRD (2 * DESC_IPRODUCT) +#define DESC_STR_SER (3 * DESC_ISERIALNUM) +#define DESC_NUM_STRING (1 + 3) + +/*----------------------------------------------------------------------------------------------------------*/ +/* USB Device descriptor */ +/*----------------------------------------------------------------------------------------------------------*/ +__ALIGN4 static uc8 guUSB_DeviceDesc[] = +{ + /*--------------------------------------------------------------------------------------------------------*/ + /* Device descriptor */ + /*--------------------------------------------------------------------------------------------------------*/ + /* Field Size Description */ + /*----------------------------------------------------------------------------*/ + DESC_LEN_DEV, // bLength 1 Size of this descriptor in bytes + DESC_TYPE_01_DEV, // bDescriptorType 1 DEVICE Descriptor Type + DESC_H2B(DESC_BCDUSB), // bcdUSB 2 USB Specification Release Number + DESC_BDEVCLASS, // bDeviceClass 1 Class code (assigned by the USB-IF) + DESC_BDEVSUBCLASS, // bDeviceSubClass 1 Subclass code (assigned by the USB-IF) + DESC_BDEVPROTOCOL, // bDeviceProtocol 1 Protocol code (assigned by the USB-IF) + DESC_WMAXPACKETSIZE0, // wMaxPacketSize0 1 Maximum packet size for endpoint zero + DESC_H2B(DESC_IDVENDOR), // idVendor 2 Vendor ID (assigned by USB-IF) + DESC_H2B(DESC_IDPRODUCT), // idProduct 2 Product ID (assigned by manufacturer) + DESC_H2B(DESC_BCDDEVICE), // bcdDevice 2 Device release number + DESC_STR_MAN, // iManufacturer 1 Index of string descriptor (Manufacturer) + DESC_STR_PRD, // iProduct 1 Index of string descriptor (Product) + DESC_STR_SER, // iSerialNumber 1 Index of string descriptor (Serial Number) + DESC_INUMCONFN, // iNumConfigurations 1 Number of possible configuration +}; + + +/*----------------------------------------------------------------------------------------------------------*/ +/* USB Configuration descriptor setting */ +/*----------------------------------------------------------------------------------------------------------*/ +// USB Configuration descriptor setting +// Self-powered +// Bit 6 of bmAttributes +// Remote Wakeup +// Bit 5 of bmAttributes +// USB Device maximum power (mA) < 2-512:2> +#define DESC_BMATTR_SELF_POWER (0) +#define DESC_BMATTR_REMOTE_WAKEUP (1) +#define DESC_BMAXPOWER (100) +// + +/*----------------------------------------------------------------------------------------------------------*/ +/* USB Configuration Descriptor definition. DO NOT MODIFY. */ +/*----------------------------------------------------------------------------------------------------------*/ +#define DESC_BMATTRIBUTES (0x80 | (DESC_BMATTR_SELF_POWER << 6) | (DESC_BMATTR_REMOTE_WAKEUP << 5)) +#define DESC_TOTAL_LEN DESC_H2B((DESC_LEN_CONFN_T + RETARGET_DLEN)) + +/*----------------------------------------------------------------------------------------------------------*/ +/* USB Configuration Descriptor */ +/*----------------------------------------------------------------------------------------------------------*/ +__ALIGN4 static uc8 guUSB_ConfnDesc[] = +{ + /*--------------------------------------------------------------------------------------------------------*/ + /* Configuration descriptor */ + /*--------------------------------------------------------------------------------------------------------*/ + /* Field Size Description */ + /*----------------------------------------------------------------------------*/ + DESC_LEN_CONFN, // bLength 1 Size of this descriptor in bytes + DESC_TYPE_02_CONFN, // bDescriptorType 1 CONFIGURATION Descriptor Type + DESC_TOTAL_LEN, // wTotalLength 2 Total length of data returned for this configuration + 0x01 + RETARGET_INF, // bNumberInterface 1 Number of interfaces supported by this configuration + 0x01, // bConfigurationValue 1 Value to use as an argument to the SetConfiguration() + 0x00, // iConfiguration 1 Index of string descriptor describing this configuration + DESC_BMATTRIBUTES, // bmAttributes 1 Configuration characteristics + // D6: Self-powered, D5: RemoteWakeup + DESC_POWER(DESC_BMAXPOWER), // bMaxPower 1 Maximum power consumption of the USB device (2 mA units) + + /*--------------------------------------------------------------------------------------------------------*/ + /* Interface descriptor */ + /*--------------------------------------------------------------------------------------------------------*/ + /* Field Size Description */ + /*----------------------------------------------------------------------------*/ + DESC_LEN_INF, // bLength 1 Size of this descriptor in bytes + DESC_TYPE_04_INF, // bDescriptorType 1 INTERFACE Descriptor Type + 0x00, // bInterfaceNumber 1 Number of this interface (Zero-based 0) + 0x00, // bAlternateSetting 1 Value used to select this alternate setting + 2, // bNumEndpoints 1 Number of endpoints used by this interface + CLASS_INF_CLASS, // bInterfaceClass 1 Class code (assigned by USB-IF) + CLASS_INF_SUBCLASS, // bInterfaceSubClass 1 Subclass code (assigned by USB-IF) + CLASS_INF_PTCO, // bInterfaceProtocol 1 Protocol code (assigned by USB) + 0x00, // iInterface 1 Index of string descriptor describing this interface + + /*--------------------------------------------------------------------------------------------------------*/ + /* XXX descriptor */ + /*--------------------------------------------------------------------------------------------------------*/ + /* Field Size Description */ + /*----------------------------------------------------------------------------*/ + DESC_LEN_XXX, // bLength 1 Size of this descriptor in bytes + DESC_TYPE_01_XXX, // bDescriptorType 1 XXX Descriptor type + DESC_H2B(0x0110), // bcdXXX 2 XXX Specification Release Number + 0x21, // bCountryCode 1 Country code of the localized hardware + 0x01, // bNumDescriptors 1 Number of class descriptors (at least 1) + DESC_TYPE_02_XXX, // bDescriptorType 1 REPORT Descriptor Type + DESC_H2B(DESC_LEN_XXXX), // bDescriptorLength 2 Total size of the Report descriptor + + /*--------------------------------------------------------------------------------------------------------*/ + /* Endpoint */ + /*--------------------------------------------------------------------------------------------------------*/ + /* Field Size Description */ + /*----------------------------------------------------------------------------*/ + DESC_LEN_EPT, // bLength 1 Size of this descriptor in bytes + DESC_TYPE_05_EPT, // bDescriptorType 1 ENDPOINT Descriptor Type + 0x81, // bEndpointAddress 1 The address of the endpoint + // Bit 3..0: The endpoint number + // Bit 6..4: Reserved + // Bit 7 : Direction (0 = Out/1 = In) + 0x03, // bmAttribute 1 Endpoint Attribute + // Bit 1..0: Transfer type + // 00 = Control + // 01 = Isochronous + // 10 = Bulk + // 11 = Interrupt + // All other reserved + DESC_H2B(_EP1LEN), // wMaxPacketSize 2 Maximum packet size + 0x01, // bInterval 1 Interval for polling endpoint + + /*--------------------------------------------------------------------------------------------------------*/ + /* Endpoint */ + /*--------------------------------------------------------------------------------------------------------*/ + /* Field Size Description */ + /*----------------------------------------------------------------------------*/ + DESC_LEN_EPT, // bLength 1 Size of this descriptor in bytes + DESC_TYPE_05_EPT, // bDescriptorType 1 ENDPOINT Descriptor Type + 0x02, // bEndpointAddress 1 The address of the endpoint + // Bit 3..0: The endpoint number + // Bit 6..4: Reserved + // Bit 7 : Direction (0 = Out/1 = In) + 0x03, // bmAttribute 1 Endpoint Attribute + // Bit 1..0: Transfer type + // 00 = Control + // 01 = Isochronous + // 10 = Bulk + // 11 = Interrupt + // All other reserved + DESC_H2B(_EP2LEN), // wMaxPacketSize 2 Maximum packet size + 0x01, // bInterval 1 Interval for polling endpoint + + #ifdef RETARGET_IS_USB + #include "ht32_retarget_desc.h" + #endif + +}; + +/*----------------------------------------------------------------------------------------------------------*/ +/* USB String Descriptor */ +/*----------------------------------------------------------------------------------------------------------*/ +__ALIGN4 static uc8 guUSB_StringDescLANGID[] = +{ + /*--------------------------------------------------------------------------------------------------------*/ + /* LANGID (Index = 0) */ + /*--------------------------------------------------------------------------------------------------------*/ + /* Field Size Description */ + /*----------------------------------------------------------------------------*/ + DESC_STRLEN(1), // bLength 1 Size of this descriptor in bytes + DESC_TYPE_03_STR, // bDescriptorType 1 STRING Descriptor Type + DESC_H2B(0x0409), // wLANGID[0] 2 LANGID code zero +}; + +#if (DESC_IMANUFACTURE == 1) +__ALIGN4 static uc8 guUSB_StringDescManufacture[] = +{ + /*--------------------------------------------------------------------------------------------------------*/ + /* Manufacture (Index = 1) */ + /*--------------------------------------------------------------------------------------------------------*/ + /* Field Size Description */ + /*----------------------------------------------------------------------------*/ + DESC_STRLEN(6), // bLength 1 Size of this descriptor in bytes + DESC_TYPE_03_STR, // bDescriptorType 1 STRING Descriptor Type + DESC_CHAR('H'), // bString N UNICODE encoded string + DESC_CHAR('O'), + DESC_CHAR('L'), + DESC_CHAR('T'), + DESC_CHAR('E'), + DESC_CHAR('K'), +}; +#endif + +#if (DESC_IPRODUCT == 1) +__ALIGN4 static uc8 guUSB_StringDescProduct[] = +{ + /*--------------------------------------------------------------------------------------------------------*/ + /* Product (Index = 2) */ + /*--------------------------------------------------------------------------------------------------------*/ + /* Field Size Description */ + /*----------------------------------------------------------------------------*/ + DESC_STRLEN(12), // bLength 1 Size of this descriptor in bytes + DESC_TYPE_03_STR, // bDescriptorType 1 STRING Descriptor Type + DESC_CHAR('U'), // bString N UNICODE encoded string + DESC_CHAR('S'), + DESC_CHAR('B'), + DESC_CHAR('-'), + DESC_CHAR('X'), + DESC_CHAR('X'), + DESC_CHAR('X'), + DESC_CHAR(' '), + DESC_CHAR('D'), + DESC_CHAR('E'), + DESC_CHAR('M'), + DESC_CHAR('O'), +}; +#endif + + +#if (DESC_ISERIALNUM == 1) +__ALIGN4 static u8 guUSB_StringDescSerialNum[] = +{ + /*--------------------------------------------------------------------------------------------------------*/ + /* Serial Number (Index = 3) */ + /*--------------------------------------------------------------------------------------------------------*/ + /* Field Size Description */ + /*----------------------------------------------------------------------------*/ + DESC_STRLEN(12), // bLength 1 Size of this descriptor in bytes + DESC_TYPE_03_STR, // bDescriptorType 1 STRING Descriptor Type + DESC_CHAR('S'), // bString N UNICODE encoded string + DESC_CHAR('N'), + DESC_CHAR('0'), + DESC_CHAR('0'), + DESC_CHAR('0'), + DESC_CHAR('0'), + DESC_CHAR('0'), + DESC_CHAR('0'), + DESC_CHAR('0'), + DESC_CHAR('0'), + DESC_CHAR('0'), + DESC_CHAR('0'), +}; +#endif + +uc8 *gpStringDesc[DESC_NUM_STRING] = +{ + + guUSB_StringDescLANGID, + + #if (DESC_IMANUFACTURE == 1) + guUSB_StringDescManufacture, + #else + NULL, + #endif + + #if (DESC_IPRODUCT == 1) + guUSB_StringDescProduct, + #else + NULL, + #endif + + #if (DESC_ISERIALNUM == 1) + guUSB_StringDescSerialNum + #else + NULL, + #endif + +}; + +/*********************************************************************************************************//** + * @brief USB Descriptor pointer initialization. + * @param pDesc: pointer of USBDCore_Desc_TypeDef + * @retval None + ***********************************************************************************************************/ +void USBDDesc_Init(USBDCore_Desc_TypeDef *pDesc) +{ + pDesc->pDeviceDesc = guUSB_DeviceDesc; + pDesc->pConfnDesc = guUSB_ConfnDesc; + pDesc->ppStringDesc = gpStringDesc; + pDesc->uStringDescNumber = DESC_NUM_STRING; + + return; +} + + +/** + * @} + */ + +/** + * @} + */ diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32_USBD_Library/example/ht32_usbd_descriptor.h b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32_USBD_Library/example/ht32_usbd_descriptor.h new file mode 100644 index 0000000000..eebcf440bf --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32_USBD_Library/example/ht32_usbd_descriptor.h @@ -0,0 +1,59 @@ +/*********************************************************************************************************//** + * @file example/ht32_usbd_descriptor.h + * @version $Rev:: 47 $ + * @date $Date:: 2015-11-18 #$ + * @brief The USB descriptor. + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------------------------------------*/ +#ifndef __HT32_USBD_DESCRIPTOR_H +#define __HT32_USBD_DESCRIPTOR_H + +/* Includes ------------------------------------------------------------------------------------------------*/ + +/** @addtogroup HT32_USBD_Library HT32 USB Device Library + * @{ + */ + +/** @defgroup USBDDescriptor USB Descriptor + * @brief USB descriptor + * @{ + */ + + +/* Exported constants --------------------------------------------------------------------------------------*/ +#define DESC_LEN_CONFN_T (u16)(DESC_LEN_CONFN + DESC_LEN_INF + DESC_LEN_XXX + DESC_LEN_EPT * 2) + +/* Exported functions --------------------------------------------------------------------------------------*/ +void USBDDesc_Init(USBDCore_Desc_TypeDef *pDesc); + + +/** + * @} + */ + +/** + * @} + */ + +#endif /* __HT32_USBD_DESCRIPTOR_H -------------------------------------------------------------------------*/ diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32_USBD_Library/example/ht32fxxxxx_usbdconf.h b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32_USBD_Library/example/ht32fxxxxx_usbdconf.h new file mode 100644 index 0000000000..a5157ea8fa --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32_USBD_Library/example/ht32fxxxxx_usbdconf.h @@ -0,0 +1,453 @@ +/*********************************************************************************************************//** + * @file example/ht32fxxxxx_usbdconf.h + * @version $Rev:: 47 $ + * @date $Date:: 2015-11-18 #$ + * @brief The configuration file of USB Device Driver. + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ +// <<< Use Configuration Wizard in Context Menu >>> + +/* Define to prevent recursive inclusion -------------------------------------------------------------------*/ +#ifndef __HT32FXXXX_USBDCONF_H +#define __HT32FXXXX_USBDCONF_H + +// Enter Low Power mode when Suspended +#define USBDCORE_ENABLE_LOW_POWER (0) +// + +#if (USBDCORE_ENABLE_LOW_POWER == 1) + #define USBDCore_LowPower() PWRCU_DeepSleep1(PWRCU_SLEEP_ENTRY_WFE) +#else + #define USBDCore_LowPower(...) +#endif + +/*----------------------------------------------------------------------------------------------------------*/ +/* USB Interrupt Enable */ +/*----------------------------------------------------------------------------------------------------------*/ +// USB Interrupt Setting (UIER) +// USB Global Interrupt Enable (UGIE) (Default) +// Start Of Frame Interrupt Enable (SOFIE) +// USB Reset Interrupt Enable (URSTIE) (Default) +// Resume Interrupt Enable (RSMIE) (Default) +// Suspend Interrupt Enable (SUSPIE) (Default) +// Expected Start of Frame Interrupt Enable (ESOFE) +// Control Endpoint Interrupt Enable (EP0IE) (Default) +// Endpoint1 Interrupt Enable (EP1IE) +// Endpoint2 Interrupt Enable (EP2IE) +// Endpoint3 Interrupt Enable (EP3IE) +// Endpoint4 Interrupt Enable (EP4IE) +// Endpoint5 Interrupt Enable (EP5IE) +// Endpoint6 Interrupt Enable (EP6IE) +// Endpoint7 Interrupt Enable (EP7IE) +#define _UIER (0x071D) +// + + +/*----------------------------------------------------------------------------------------------------------*/ +/* Endpoint0 Configuration Setting */ +/*----------------------------------------------------------------------------------------------------------*/ +// Control Endpoint0 Configuration +// Endpoint Buffer Length (EPLEN) +// <8=> 8 bytes +// <16=> 16 bytes +// <32=> 32 bytes +// <64=> 64 bytes + /* Maximum: 64 Bytes */ +#define _EP0LEN (64) + + +// Control Endpoint0 Interrupt Enable Settings (EP0IER) +// OUT Token Packet Received Interrupt Enable (OTRXIE) +// OUT Data Packet Received Interrupt Enable (ODRXIE) (Default) +// OUT Data Buffer Overrun Interrupt Enable (ODOVIE) +// IN Token Packet Received Interrupt Enable (ITRXIE) +// IN Data Packet Transmitted Interrupt Enable (IDTXIE) (Default) +// NAK Transmitted Interrupt Enable (NAKIE) +// STALL Transmitted Interrupt Enable (STLIE) +// USB Error Interrupt Enable (UERIE) +// SETUP Token Packet Received Interrupt Enable (STRXIE) +// SETUP Data Packet Received Interrupt Enable (SDRXIE) (Default) +// SETUP Data Error Interrupt Enable (SDERIE) +// Zero Length Data Packet Received Interrupt Enable (ZLRXIE) +#define _EP0_IER (0x212) +// +// + +/*----------------------------------------------------------------------------------------------------------*/ +/* Endpoint1 Configuration Setting */ +/*----------------------------------------------------------------------------------------------------------*/ +// Endpoint1 Configuration +#define _EP1_ENABLE (1) + +// Endpoint Address (EPADR) +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 +#define _EP1_CFG_EPADR (1) + +// Endpoint Enable (EPEN) +#define _EP1_CFG_EPEN_TMP (1) + +// Endpoint Transfer Type +// <2=> Bulk +// <3=> Interrupt +#define _EP1_TYPR (3) + +// Endpoint Direction (EPDIR) +// <1=> IN +// <0=> OUT +#define _EP1_CFG_EPDIR (1) + +// Endpoint Buffer Length (EPLEN) (in byte) <4-64:4> + /* Maximum: 64 Bytes */ +#define _EP1LEN_TMP (64) + +// Endpoint Interrupt Enable Settings (EPIER) +// Endpoint Interrupt Enable Settings (EPIER) <0x0-0xFF:1> +// OUT Token Packet Received Interrupt Enable (OTRXIE) +// OUT Data Packet Received Interrupt Enable (ODRXIE) +// OUT Data Buffer Overrun Interrupt Enable (ODOVIE) +// IN Token Packet Received Interrupt Enable (ITRXIE) +// IN Data Packet Transmitted Interrupt Enable (IDTXIE) +// NAK Transmitted Interrupt Enable (NAKIE) +// STALL Transmitted Interrupt Enable (STLIE) +// USB Error Interrupt Enable (UERIE) +#define _EP1_IER (0x10) +// +// + + +/*----------------------------------------------------------------------------------------------------------*/ +/* Endpoint2 Configuration Setting */ +/*----------------------------------------------------------------------------------------------------------*/ +// Endpoint2 Configuration +#define _EP2_ENABLE (1) + +// Endpoint Address (EPADR) +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 +#define _EP2_CFG_EPADR (2) + +// Endpoint Enable (EPEN) +#define _EP2_CFG_EPEN_TMP (1) + +// Endpoint Transfer Type +// <2=> Bulk +// <3=> Interrupt +#define _EP2_TYPR (3) + +// Endpoint Direction (EPDIR) +// <1=> IN +// <0=> OUT +#define _EP2_CFG_EPDIR (0) + +// Endpoint Buffer Length (EPLEN) (in byte) <4-64:4> + /* Maximum: 64 Bytes */ +#define _EP2LEN_TMP (64) + +// Endpoint Interrupt Enable Settings (EPIER) +// Endpoint Interrupt Enable Settings (EPIER) <0x0-0xFF:1> +// OUT Token Packet Received Interrupt Enable (OTRXIE) +// OUT Data Packet Received Interrupt Enable (ODRXIE) +// OUT Data Buffer Overrun Interrupt Enable (ODOVIE) +// IN Token Packet Received Interrupt Enable (ITRXIE) +// IN Data Packet Transmitted Interrupt Enable (IDTXIE) +// NAK Transmitted Interrupt Enable (NAKIE) +// STALL Transmitted Interrupt Enable (STLIE) +// USB Error Interrupt Enable (UERIE) +#define _EP2_IER (0x002) +// +// + +/*----------------------------------------------------------------------------------------------------------*/ +/* Endpoint3 Configuration Setting */ +/*----------------------------------------------------------------------------------------------------------*/ +// Endpoint3 Configuration +#define _EP3_ENABLE (0) + +// Endpoint Address (EPADR) +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 +#define _EP3_CFG_EPADR (3) + +// Endpoint Enable (EPEN) +#define _EP3_CFG_EPEN_TMP (1) + +// Endpoint Transfer Type +// <2=> Bulk +// <3=> Interrupt +#define _EP3_TYPR (3) + +// Endpoint Direction (EPDIR) +// <1=> IN +// <0=> OUT +#define _EP3_CFG_EPDIR (1) + +// Endpoint Buffer Length (EPLEN) (in byte) <4-64:4> + /* Maximum: 64 Bytes */ +#define _EP3LEN_TMP (8) + +// Endpoint Interrupt Enable Settings (EPIER) +// Endpoint Interrupt Enable Settings (EPIER) <0x0-0xFF:1> +// OUT Token Packet Received Interrupt Enable (OTRXIE) +// OUT Data Packet Received Interrupt Enable (ODRXIE) +// OUT Data Buffer Overrun Interrupt Enable (ODOVIE) +// IN Token Packet Received Interrupt Enable (ITRXIE) +// IN Data Packet Transmitted Interrupt Enable (IDTXIE) +// NAK Transmitted Interrupt Enable (NAKIE) +// STALL Transmitted Interrupt Enable (STLIE) +// USB Error Interrupt Enable (UERIE) +#define _EP3_IER (0x10) +// +// + +/*----------------------------------------------------------------------------------------------------------*/ +/* Endpoint4 Configuration Setting */ +/*----------------------------------------------------------------------------------------------------------*/ +// Endpoint4 Configuration +#define _EP4_ENABLE (0) + +// Endpoint Address (EPADR) +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 +#define _EP4_CFG_EPADR (4) + +// Endpoint Enable (EPEN) +#define _EP4_CFG_EPEN_TMP (1) + +// Endpoint Transfer Type +// <1=> Isochronous +// <2=> Bulk +// <3=> Interrupt +#define _EP4_TYPR (3) + +// Endpoint Direction (EPDIR) +// <1=> IN +// <0=> OUT +#define _EP4_CFG_EPDIR (0) + +// Endpoint Buffer Length (EPLEN) (in byte) <4-1000:4> + /* Maximum: 1000 Bytes */ +#define _EP4LEN_TMP (8) + +// Single/Double Buffer Selection (SDBS) +// <0=> Single Buffer +// <1=> Double Buffer +#define _EP4_CFG_SDBS (0) + +// Endpoint Interrupt Enable Settings (EPIER) +// Endpoint Interrupt Enable Settings (EPIER) <0x0-0xFF:1> +// OUT Token Packet Received Interrupt Enable (OTRXIE) +// OUT Data Packet Received Interrupt Enable (ODRXIE) +// OUT Data Buffer Overrun Interrupt Enable (ODOVIE) +// IN Token Packet Received Interrupt Enable (ITRXIE) +// IN Data Packet Transmitted Interrupt Enable (IDTXIE) +// NAK Transmitted Interrupt Enable (NAKIE) +// STALL Transmitted Interrupt Enable (STLIE) +// USB Error Interrupt Enable (UERIE) +#define _EP4_IER (0x02) +// +// + + +/*----------------------------------------------------------------------------------------------------------*/ +/* Endpoint5 Configuration Setting */ +/*----------------------------------------------------------------------------------------------------------*/ +// Endpoint5 Configuration +#define _EP5_ENABLE (0) + +// Endpoint Address (EPADR) +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 +#define _EP5_CFG_EPADR (5) + +// Endpoint Enable (EPEN) +#define _EP5_CFG_EPEN_TMP (1) + +// Endpoint Transfer Type +// <1=> Isochronous +// <2=> Bulk +// <3=> Interrupt +#define _EP5_TYPR (3) + +// Endpoint Direction (EPDIR) +// <1=> IN +// <0=> OUT +#define _EP5_CFG_EPDIR (1) + +// Endpoint Buffer Length (EPLEN) (in byte) <4-1000:4> + /* Maximum: 1000 Bytes */ +#define _EP5LEN_TMP (8) + + +// Single/Double Buffer Selection (SDBS) +// <0=> Single Buffer +// <1=> Double Buffer +#define _EP5_CFG_SDBS (0) + +// Endpoint Interrupt Enable Settings (EPIER) +// Endpoint Interrupt Enable Settings (EPIER) <0x0-0xFF:1> +// OUT Token Packet Received Interrupt Enable (OTRXIE) +// OUT Data Packet Received Interrupt Enable (ODRXIE) +// OUT Data Buffer Overrun Interrupt Enable (ODOVIE) +// IN Token Packet Received Interrupt Enable (ITRXIE) +// IN Data Packet Transmitted Interrupt Enable (IDTXIE) +// NAK Transmitted Interrupt Enable (NAKIE) +// STALL Transmitted Interrupt Enable (STLIE) +// USB Error Interrupt Enable (UERIE) +#define _EP5_IER (0x10) +// +// + + +/*----------------------------------------------------------------------------------------------------------*/ +/* Endpoint6 Configuration Setting */ +/*----------------------------------------------------------------------------------------------------------*/ +// Endpoint6 Configuration +#define _EP6_ENABLE (0) + +// Endpoint Address (EPADR) +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 +#define _EP6_CFG_EPADR (6) + +// Endpoint Enable (EPEN) +#define _EP6_CFG_EPEN_TMP (1) + +// Endpoint Transfer Type +// <1=> Isochronous +// <2=> Bulk +// <3=> Interrupt +#define _EP6_TYPR (3) + +// Endpoint Direction (EPDIR) +// <1=> IN +// <0=> OUT +#define _EP6_CFG_EPDIR (0) + +// Endpoint Buffer Length (EPLEN) (in byte) <4-1000:4> + /* Maximum: 1000 Bytes */ +#define _EP6LEN_TMP (8) + +// Single/Double Buffer Selection (SDBS) +// <0=> Single Buffer +// <1=> Double Buffer +#define _EP6_CFG_SDBS (0) + +// Endpoint Interrupt Enable Settings (EPIER) +// Endpoint Interrupt Enable Settings (EPIER) <0x0-0xFF:1> +// OUT Token Packet Received Interrupt Enable (OTRXIE) +// OUT Data Packet Received Interrupt Enable (ODRXIE) +// OUT Data Buffer Overrun Interrupt Enable (ODOVIE) +// IN Token Packet Received Interrupt Enable (ITRXIE) +// IN Data Packet Transmitted Interrupt Enable (IDTXIE) +// NAK Transmitted Interrupt Enable (NAKIE) +// STALL Transmitted Interrupt Enable (STLIE) +// USB Error Interrupt Enable (UERIE) +#define _EP6_IER (0x02) +// +// + + +/*----------------------------------------------------------------------------------------------------------*/ +/* Endpoint7 Configuration Setting */ +/*----------------------------------------------------------------------------------------------------------*/ +// Endpoint7 Configuration +#define _EP7_ENABLE (0) + +// Endpoint Address (EPADR) +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 +#define _EP7_CFG_EPADR (7) + +// Endpoint Enable (EPEN) +#define _EP7_CFG_EPEN_TMP (1) + +// Endpoint Transfer Type +// <1=> Isochronous +// <2=> Bulk +// <3=> Interrupt +#define _EP7_TYPR (3) + +// Endpoint Direction (EPDIR) +// <1=> IN +// <0=> OUT +#define _EP7_CFG_EPDIR (1) + +// Endpoint Buffer Length (EPLEN) (in byte) <4-1000:4> + /* Maximum: 1000 Bytes */ +#define _EP7LEN_TMP (8) + +// Single/Double Buffer Selection (SDBS) +// <0=> Single Buffer +// <1=> Double Buffer +#define _EP7_CFG_SDBS (0) + +// Endpoint Interrupt Enable Settings (EPIER) +// Endpoint Interrupt Enable Settings (EPIER) <0x0-0xFF:1> +// OUT Token Packet Received Interrupt Enable (OTRXIE) +// OUT Data Packet Received Interrupt Enable (ODRXIE) +// OUT Data Buffer Overrun Interrupt Enable (ODOVIE) +// IN Token Packet Received Interrupt Enable (ITRXIE) +// IN Data Packet Transmitted Interrupt Enable (IDTXIE) +// NAK Transmitted Interrupt Enable (NAKIE) +// STALL Transmitted Interrupt Enable (STLIE) +// USB Error Interrupt Enable (UERIE) +#define _EP7_IER (0x10) +// +// + +#endif diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32_USBD_Library/inc/ht32_usbd_core.h b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32_USBD_Library/inc/ht32_usbd_core.h new file mode 100644 index 0000000000..00ff7d8e53 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32_USBD_Library/inc/ht32_usbd_core.h @@ -0,0 +1,435 @@ +/*********************************************************************************************************//** + * @file ht32_usbd_core.h + * @version $Rev:: 5656 $ + * @date $Date:: 2021-11-24 #$ + * @brief The header file of standard protocol related function for HT32 USB Device Library. + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ +// <<< Use Configuration Wizard in Context Menu >>> + +/* Define to prevent recursive inclusion -------------------------------------------------------------------*/ +#ifndef __HT32_USBD_CORE_H +#define __HT32_USBD_CORE_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------------------------------------*/ + +/** @addtogroup HT32_USBD_Library + * @{ + */ + +/** @addtogroup USBDCore + * @{ + */ + + +/* Settings ------------------------------------------------------------------------------------------------*/ +/** @defgroup USBDCore_Settings USB Device Core settings + * @{ + */ +/* USBD Debug mode */ +// Enable USB Debug mode +// Dump USB Debug data +#ifndef USBDCORE_DEBUG + #define USBDCORE_DEBUG (0) /*!< Enable USB Debug mode */ + #define USBDCORE_DEBUG_DATA (0) /*!< Dump USB Debug data */ +#endif +/** + * @} + */ + +/* Exported types ------------------------------------------------------------------------------------------*/ +/** @defgroup USBDCore_Exported_Type USB Device Core exported types + * @{ + */ +/** + * @brief USB Device Request. + */ +typedef __PACKED_H struct +{ + uc8 bmRequestType; + uc8 bRequest; + uc8 wValueL; + uc8 wValueH; + uc16 wIndex; + uc16 wLength; +} __PACKED_F USBDCore_Request_TypeDef; + +/** + * @brief USB Descriptor. + */ +typedef struct +{ + uc8 *pDeviceDesc; /*!< Device Descriptor */ + uc8 *pConfnDesc; /*!< Configuration Descriptor */ + uc8 **ppStringDesc; /*!< String Descriptor */ + u32 uStringDescNumber; /*!< Count of String Descriptor */ +} USBDCore_Desc_TypeDef; + +/** + * @brief STALL, control IN or control OUT. + */ +typedef enum +{ + USB_ACTION_STALL = 0, + USB_ACTION_DATAIN = 1, + USB_ACTION_DATAOUT = 2, +} USBDCore_Action_Enum; + +/** + * @brief Call back function. + */ +typedef struct +{ + void (*func) (u32 uPara); /*!< Call back function pointer */ + u32 uPara; /*!< Parameter of call back function */ +} USBDCore_CallBack_TypeDef; + +/** + * @brief Parameter for control IN/OUT Transfer. + */ +typedef struct +{ + u8 uBuffer[2]; /*!< Temporary buffer */ + uc8 *pData; /*!< Pointer of control IN/OUT Data */ + s32 sByteLength; /*!< Total length for control IN/OUT Transfer */ + USBDCore_Action_Enum Action; /*!< STALL, control IN or control OUT */ + USBDCore_CallBack_TypeDef CallBack_OUT; /*!< Call back function pointer for Control OUT */ +} USBDCore_Transfer_TypeDef; + +/** + * @brief USB Device. + */ +typedef struct +{ + USBDCore_Request_TypeDef Request; /*!< USB Device Request */ + USBDCore_Desc_TypeDef Desc; /*!< USB Descriptor */ + USBDCore_Transfer_TypeDef Transfer; /*!< Parameter for control IN/OUT Transfer */ +} USBDCore_Device_TypeDef; + +/** + * @brief Bit access for CurrentFeature. + */ +typedef __PACKED_H struct _FEATURE_TYPEBIT +{ + unsigned bSelfPowered :1; /*!< Remote Wakeup feature */ + unsigned bRemoteWakeup :1; /*!< Self Powered */ +} __PACKED_F USBDCore_Feature_TypeBit; + +/** + * @brief For Set/ClearFeature and GetStatus request. + */ +typedef __PACKED_H union _FEATURE_TYPEDEF +{ + u8 uByte; /*!< Byte access for CurrentFeature */ + USBDCore_Feature_TypeBit Bits; /*!< Bit access for CurrentFeature */ +} __PACKED_F USBDCore_Feature_TypeDef; + +/** + * @brief Device State. + */ +typedef enum +{ + USB_STATE_UNCONNECTED = 0, + USB_STATE_ATTACHED = 1, + USB_STATE_POWERED = 2, + USB_STATE_SUSPENDED = 3, + USB_STATE_DEFAULT = 4, + USB_STATE_ADDRESS = 5, + USB_STATE_CONFIGURED = 6, +} USBDCore_Status_Enum; + +/** + * @brief USB Device information. + */ +typedef struct +{ + u8 uCurrentConfiguration; /*!< For Set/GetConfiguration request */ + u8 uCurrentInterface; /*!< For Set/GetInterface request */ + volatile USBDCore_Status_Enum CurrentStatus; /*!< Device State */ + USBDCore_Status_Enum LastStatus; /*!< Device State before SUSPEND */ + USBDCore_Feature_TypeDef CurrentFeature; /*!< For Set/ClearFeature and GetStatus request */ + u32 uIsDiscardClearFeature; /*!< Discard ClearFeature flag for Mass Storage */ +} USBDCore_Info_TypeDef; + +typedef void (*USBDCore_CallBackClass_Typedef) (USBDCore_Device_TypeDef *pDev); +typedef void (*USBDCore_CallBackVendor_Typedef) (USBDCore_Device_TypeDef *pDev); +typedef void (*USBDCore_CallBackEPTn_Typedef) (USBD_EPTn_Enum EPTn); + +/** + * @brief USB Class call back function. + */ +typedef struct +{ + USBDCore_CallBack_TypeDef CallBack_MainRoutine; /*!< Class main routine call back function */ + USBDCore_CallBack_TypeDef CallBack_Reset; /*!< Class RESET call back function */ + USBDCore_CallBack_TypeDef CallBack_StartOfFrame; /*!< Class SOF call back function */ + USBDCore_CallBackClass_Typedef CallBack_ClassGetDescriptor; /*!< Class Get Descriptor call back function */ + USBDCore_CallBackClass_Typedef CallBack_ClassSetInterface; /*!< Set Interface call back function */ + USBDCore_CallBackClass_Typedef CallBack_ClassGetInterface; /*!< Get Interface call back function */ + USBDCore_CallBackClass_Typedef CallBack_ClassRequest; /*!< Class Request call back function */ + USBDCore_CallBackVendor_Typedef CallBack_VendorRequest; /*!< Vendor Request call back function */ + USBDCore_CallBackEPTn_Typedef CallBack_EPTn[MAX_EP_NUM]; /*!< Endpoint n call back function */ +} USBDCore_Class_TypeDef; + +/** + * @brief USB Device Power related call back function. + */ +typedef struct +{ + USBDCore_CallBack_TypeDef CallBack_Suspend; +} USBDCore_Power_TypeDef; + +/** + * @brief Major structure of USB Library. + */ +typedef struct +{ + USBDCore_Device_TypeDef Device; /*!< USB Device */ + USBDCore_Info_TypeDef Info; /*!< USB Device information */ + USBDCore_Class_TypeDef Class; /*!< USB Class call back function */ + u32 *pDriver; /*!< USB Device Driver initialization structure */ + USBDCore_Power_TypeDef Power; /*!< USB Device Power related call back function */ +} USBDCore_TypeDef; + +/*----------------------------------------------------------------------------------------------------------*/ +/* Variable architecture of USB Library */ +/*----------------------------------------------------------------------------------------------------------*/ +/* USBCore - USBDCore_TypeDef Major structure of USB Library */ +/* USBCore.Device - USBDCore_Device_TypeDef USB Device */ +/* USBCore.Device.Request - USBDCore_Request_TypeDef USB Device Request */ +/* USBCore.Device.Request.bmRequestType */ +/* USBCore.Device.Request.bRequest */ +/* USBCore.Device.Request.wValueL */ +/* USBCore.Device.Request.wValueH */ +/* USBCore.Device.Request.wIndex */ +/* USBCore.Device.Request.wLength */ +/* USBCore.Device.Desc - USBDCore_Desc_TypeDef USB Descriptor */ +/* USBCore.Device.Desc.pDeviceDesc Device Descriptor */ +/* USBCore.Device.Desc.pConfnDesc Configuration Descriptor */ +/* USBCore.Device.Desc.pStringDesc[DESC_NUM_STRING] String Descriptor */ +/* USBCore.Device.Desc.uStringDescNumber Count of String Descriptor */ +/* USBCore.Device.Transfer - USBDCore_Transfer_TypeDef Parameter for control IN/OUT Transfer */ +/* USBCore.Device.Transfer.uBuffer[2] Temporary buffer */ +/* USBCore.Device.Transfer.pData Pointer of control IN/OUT Data */ +/* USBCore.Device.Transfer.sByteLength Total length for control IN/OUT Transfer */ +/* USBCore.Device.Transfer.Action - USBDCore_Action_Enum STALL, control IN or control OUT */ +/* USBCore.Device.Transfer.CallBack_OUT.func(uPara) Call back function pointer for Control OUT */ +/* USBCore.Device.Transfer.CallBack_OUT.uPara Parameter of Control OUT call back function */ +/* */ +/* USBCore.Info - USBDCore_Info_TypeDef USB Device information */ +/* USBCore.Info.uCurrentConfiguration For Set/GetConfiguration request */ +/* USBCore.Info.uCurrentInterface For Set/GetInterface request */ +/* USBCore.Info.CurrentStatus - USBDCore_Status_Enum Device State */ +/* USBCore.Info.LastStatus - USBDCore_Status_Enum Device State before SUSPEND */ +/* USBCore.Info.CurrentFeature - USBDCore_Feature_TypeDef For Set/ClearFeature and GetStatus request */ +/* USBCore.Info.CurrentFeature.uByte Byte access for CurrentFeature */ +/* USBCore.Info.CurrentFeature.Bits.bRemoteWakeup Remote Wakeup feature */ +/* USBCore.Info.CurrentFeature.Bits.bSelfPowered Self Powered */ +/* USBCore.Info.uIsDiscardClearFeature Discard ClearFeature flag for Mass Storage */ +/* */ +/* USBCore.Class - USBDCore_Class_TypeDef USB Class call back function */ +/* USBCore.Class.CallBack_MainRoutine.func(uPara) Class main routine call back function */ +/* USBCore.Class.CallBack_MainRoutine.uPara Parameter of class main routine */ +/* USBCore.Class.CallBack_Reset.func(uPara) Class RESET call back function */ +/* USBCore.Class.CallBack_Reset.uPara Parameter of RESET call back function */ +/* USBCore.Class.CallBack_StartOfFrame.func(uPara) Class SOF call back function */ +/* USBCore.Class.CallBack_StartOfFrame.uPara Parameter of SOF call back function */ +/* USBCore.Class.CallBack_ClassGetDescriptor(pDev) Class Get Descriptor call back function */ +/* USBCore.Class.CallBack_ClassSetInterface(pDev) Set Interface call back function */ +/* USBCore.Class.CallBack_ClassGetInterface(pDev) Get Interface call back function */ +/* USBCore.Class.CallBack_ClassRequest(pDev) Class Request call back function */ +/* USBCore.Class.CallBack_EPTn[MAX_EP_NUM](EPTn) Endpoint n call back function */ +/* */ +/* USBCore.pDriver USB Device Driver initialization structure */ +/* */ +/* USBCore.Power - USBDCore_Power_TypeDef USB Device Power related call back function */ +/* USBCore.Power.CallBack_Suspend.func(uPara) System low power function for SUSPEND */ +/* USBCore.Power.CallBack_Suspend.uPara Parameter of system low power function */ +/*----------------------------------------------------------------------------------------------------------*/ + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------------------------------------*/ +/** @defgroup USBDCore_Exported_Constant USB Device Core exported constants + * @{ + */ + +/** @defgroup USBDCore_Descriptor Definitions for USB descriptor + * @{ + */ +#define DESC_TYPE_01_DEV (0x1) +#define DESC_TYPE_02_CONFN (0x2) +#define DESC_TYPE_03_STR (0x3) +#define DESC_TYPE_04_INF (0x4) +#define DESC_TYPE_05_EPT (0x5) +#define DESC_TYPE_06_DEV_QLF (0x6) +#define DESC_TYPE_08_INF_PWR (0x8) + +#define DESC_CLASS_00_BY_INF (0x00) +#define DESC_CLASS_01_AUDIO (0x01) +#define DESC_CLASS_02_CDC_CTRL (0x02) +#define DESC_CLASS_03_HID (0x03) +#define DESC_CLASS_05_PHY (0x05) +#define DESC_CLASS_06_STILL_IMG (0x06) +#define DESC_CLASS_07_PRINTER (0x07) +#define DESC_CLASS_08_MASS_STORAGE (0x08) +#define DESC_CLASS_09_HUB (0x09) +#define DESC_CLASS_0A_CDC_DATA (0x0A) +#define DESC_CLASS_0B_SMART_CARD (0x0B) +#define DESC_CLASS_0E_VIDEO (0x0E) +#define DESC_CLASS_0F_PHD (0x0F) +#define DESC_CLASS_FF_VENDOR (0xFF) + +#define DESC_LEN_DEV ((u32)(18)) +#define DESC_LEN_CONFN ((u32)(9)) +#define DESC_LEN_INF ((u32)(9)) +#define DESC_LEN_EPT ((u32)(7)) +/** + * @} + */ + +/** @defgroup USBDCore_Request Definitions for USB Request + * @{ + */ +#define REQ_DIR_00_H2D (0 << 7) +#define REQ_DIR_01_D2H (1 << 7) + +#define REQ_TYPE_00_STD (0 << 5) +#define REQ_TYPE_01_CLS (1 << 5) +#define REQ_TYPE_02_VND (2 << 5) + +#define REQ_REC_00_DEV (0) +#define REQ_REC_01_INF (1) +#define REQ_REC_02_EPT (2) +/** + * @} + */ + +/** + * @brief For USBDCore_EPTReadOUTData function. + */ +#define USB_DISCARD_OUT_DATA (0) + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------------------------------------*/ +/** @defgroup USBDCore_Exported_Macro USB Device Core exported macros + * @{ + */ +#define __DBG_USBPrintf(...) +#define __DBG_USBDump(a, b) + +#if (USBDCORE_DEBUG == 1) + #ifndef RETARGET_IS_USB + extern u32 __DBG_USBCount; + #undef __DBG_USBPrintf + #define __DBG_USBPrintf printf + #if (USBDCORE_DEBUG_DATA == 1) + #undef __DBG_USBDump + void __DBG_USBDump(uc8 *memory, u32 len); + #endif + #endif +#endif + +/** + * @brief Convert Half-Word to Byte for descriptor. + */ +#define DESC_H2B(Val) ((u8)(Val & 0x00FF)), ((u8)((Val & 0xFF00) >> 8)) + +/** + * @brief Padding 0 automatically for String descriptor. + */ +#define DESC_CHAR(c) (c), (0) + +/** + * @brief Calculate String length for String descriptor. + */ +#define DESC_STRLEN(n) (n * 2 + 2) + +/** + * @brief Calculate power for Configuration descriptor. + */ +#define DESC_POWER(mA) (mA / 2) +/** + * @} + */ + +/* Exported functions --------------------------------------------------------------------------------------*/ +/** @defgroup USBDCore_Exported_Functions USB Device Core exported functions + * @{ + */ +#define USBDCore_DeInit API_USB_DEINIT +#define USBDCore_EPTReset API_USB_EPTn_RESET +#define USBDCore_EPTGetBufferLen API_USB_EPTn_GET_BUFFLEN +#define USBDCore_EPTGetTransferCount API_USB_EPTn_GET_CNT +#define USBDCore_EPTSetSTALL API_USB_EPTn_SET_HALT +#define USBDCore_EPTWaitSTALLSent API_USB_EPTn_WAIT_STALL_SENT +#define USBDCore_EPTClearDataToggle API_USB_EPTn_CLR_DTG + +#define USBDCore_EPTWriteINData API_USB_EPTn_WRITE_IN +#define USBDCore_EPTReadOUTData API_USB_EPTn_READ_OUT +#define USBDCore_EPTReadMemory API_USB_EPTn_READ_MEM + +void USBDCore_Init(USBDCore_TypeDef *pCore); +void USBDCore_IRQHandler(USBDCore_TypeDef *pCore); +void USBDCore_MainRoutine(USBDCore_TypeDef *pCore); +u32 USBDCore_IsSuspend(USBDCore_TypeDef *pCore); +u32 USBDCore_GetRemoteWakeUpFeature(USBDCore_TypeDef *pCore); +void USBDCore_TriggerRemoteWakeup(void); +USBDCore_Status_Enum USBDCore_GetStatus(void); + +void USBDCore_EPTReset(USBD_EPTn_Enum USBD_EPTn); +u32 USBDCore_EPTGetBufferLen(USBD_EPTn_Enum USBD_EPTn); +u32 USBDCore_EPTGetTransferCount(USBD_EPTn_Enum USBD_EPTn, USBD_TCR_Enum type); +void USBDCore_EPTSetSTALL(USBD_EPTn_Enum USBD_EPTn); +void USBDCore_EPTWaitSTALLSent(USBD_EPTn_Enum USBD_EPTn); +void USBDCore_EPTClearDataToggle(USBD_EPTn_Enum USBD_EPTn); + +u32 USBDCore_EPTWriteINData(USBD_EPTn_Enum USBD_EPTn, u32 *pFrom, u32 len); +u32 USBDCore_EPTReadOUTData(USBD_EPTn_Enum USBD_EPTn, u32 *pTo, u32 len); +u32 USBDCore_EPTReadMemory(USBD_EPTn_Enum USBD_EPTn, u32 *pTo, u32 len); +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __HT32_USBD_CORE_H -------------------------------------------------------------------------------*/ diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32_USBD_Library/src/ht32_usbd_core.c b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32_USBD_Library/src/ht32_usbd_core.c new file mode 100644 index 0000000000..bfc1abbb9c --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32_USBD_Library/src/ht32_usbd_core.c @@ -0,0 +1,1037 @@ +/*********************************************************************************************************//** + * @file ht32_usbd_core.c + * @version $Rev:: 3813 $ + * @date $Date:: 2019-05-07 #$ + * @brief The standard protocol related function of HT32 USB Device Library. + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ + +/* Includes ------------------------------------------------------------------------------------------------*/ +#include "ht32.h" +#include "ht32_usbd_core.h" + +#ifdef USBD_VENDOR_SUPPORT +#include "ht32_usbd_vendor.c" +#endif + +/** @addtogroup HT32_USBD_Library HT32 USB Device Library + * @{ + */ + +/** @defgroup USBDCore USB Device Core + * @brief USB Device Core standard protocol related function + * @{ + */ + + +/* Private types -------------------------------------------------------------------------------------------*/ +/** @defgroup USBDCore_Private_TypesDefinitions USB Device Core private types definitions + * @{ + */ +typedef enum +{ + Device = 0, + Interface = 1, + Endpoint = 2, + Other = 3, +} USBDCore_Recipient_Enum; + +typedef enum +{ + ClearFeature = 0, + SetFeature = 1, +} USBDCore_SetClearFeature_Enum; +/** + * @} + */ + +/* Private constants ---------------------------------------------------------------------------------------*/ +/** @defgroup USBDCore_Private_Define USB Device Core private definitions + * @{ + */ +/* USBD Debug mode */ +#if (USBDCORE_DEBUG == 1) + #ifdef RETARGET_IS_USB + #warning "USB debug mode can not work when retaget to USB Virtual COM. Turn off automatically." + #undef USBDCORE_DEBUG + #define USBDCORE_DEBUG 0 + #else + u32 __DBG_USBCount; + #warning "USB debug mode has been enabled which degrade the performance." + #warning "After the debug operation, please remember to turn off USB debug mode." + #endif +#endif + +/** @defgroup USBDCore_STD Definition for standard request + * @{ + */ +#define REQ_00_GET_STAT ((u16)(0 << 8)) +#define REQ_01_CLR_FETU ((u16)(1 << 8)) +#define REQ_03_SET_FETU ((u16)(3 << 8)) +#define REQ_05_SET_ADDR ((u16)(5 << 8)) +#define REQ_06_GET_DESC ((u16)(6 << 8)) +#define REQ_07_SET_DESC ((u16)(7 << 8)) +#define REQ_08_GET_CONF ((u16)(8 << 8)) +#define REQ_09_SET_CONF ((u16)(9 << 8)) +#define REQ_10_GET_INF ((u16)(10 << 8)) +#define REQ_11_SET_INF ((u16)(11 << 8)) +#define REQ_12_SYN_FRME ((u16)(12 << 8)) +/** + * @} + */ + +#define DESC_TYPE_01_DEV (0x1) +#define DESC_TYPE_02_CONFN (0x2) +#define DESC_TYPE_03_STR (0x3) +#define USB_NO_DATA (-1) /*!< For Device.Transfer.sByteLength */ +#define BMREQUEST_TYPE_MASK (0x6 << 4) /*!< bmRequestType[6:5] */ +#define USB_FEATURE_REMOTE_WAKEUP (1) + +#define MAX_CONTROL_OUT_SIZE (64) +/** + * @} + */ + +/* Private function prototypes -----------------------------------------------------------------------------*/ +static void _USBDCore_PowerHandler(USBDCore_TypeDef *pCore); +static void _USBDCore_Reset(USBDCore_TypeDef *pCore); +static void _USBDCore_Resume(USBDCore_TypeDef *pCore); +static void _USBDCore_Suspend(USBDCore_TypeDef *pCore); +static void _USBDCore_Setup(USBDCore_TypeDef *pCore); +static void _USBDCore_Standard_Request(USBDCore_TypeDef *pCore); +static void _USBDCore_Standard_GetStatus(USBDCore_TypeDef *pCore, USBDCore_Recipient_Enum recipient); +static void _USBDCore_Standard_SetClearFeature(USBDCore_TypeDef *pCore, USBDCore_Recipient_Enum recipient, USBDCore_SetClearFeature_Enum type); +static void _USBDCore_Standard_SetAddress(USBDCore_TypeDef *pCore); +static void _USBDCore_Standard_GetDescriptor(USBDCore_TypeDef *pCore); +static void _USBDCore_Standard_GetConfiguration(USBDCore_TypeDef *pCore); +static void _USBDCore_Standard_SetConfiguration(USBDCore_TypeDef *pCore); +static void _USBDCore_ControlIN(USBDCore_TypeDef *pCore); +static void _USBDCore_ControlOUT(USBDCore_TypeDef *pCore); + +/* Private macro -------------------------------------------------------------------------------------------*/ +/** @defgroup USBDCore_Private_Macro USB Device Core private macros + * @{ + */ +/** + * @brief Get self powered bit from Device descriptor + */ +#define _GET_SELFPOWERED_FROM_DESC() (((pCore->Device.Desc.pConfnDesc[7]) >> 6) & 0x01) +/** + * @} + */ + +/* Private variables ---------------------------------------------------------------------------------------*/ +/** @defgroup USBDCore_Private_Variable USB Device Core private variables + * @{ + */ +USBDCore_TypeDef *pUSBCore; +/** + * @} + */ + + +/* Global Function -----------------------------------------------------------------------------------------*/ +/** @defgroup USBDCore_Exported_Functions USB Device Core exported functions + * @{ + */ +/*********************************************************************************************************//** + * @brief USB Core initialization. + * @param pCore: pointer of USB Device + * @retval None + ***********************************************************************************************************/ +void USBDCore_Init(USBDCore_TypeDef *pCore) +{ + pUSBCore = pCore; + pCore->Info.CurrentStatus = USB_STATE_POWERED; + API_USB_INIT(pCore->pDriver); + __DBG_USBPrintf("\r\n%06ld \r\n", ++__DBG_USBCount); + return; +} + +/*********************************************************************************************************//** + * @brief USB Interrupt Service Routine. + * @param pCore: pointer of USB Device + * @retval None + ***********************************************************************************************************/ +void USBDCore_IRQHandler(USBDCore_TypeDef *pCore) +{ + u32 USBISRFlag = API_USB_GET_INT(); + u32 USBEPTISRFlag; + USBD_EPTn_Enum EPTn; + + #if (USBDCORE_DEBUG == 1) + u32 USBAddr = HT_USB->DEVAR; + #endif + + /*--------------------------------------------------------------------------------------------------------*/ + /* USB SOF Interrupt */ + /*--------------------------------------------------------------------------------------------------------*/ + if (API_USB_IS_SOF_INT(USBISRFlag)) + { + __DBG_USBPrintf("%06ld SOF[%02d][%02lX]\r\n", ++__DBG_USBCount, pCore->Info.CurrentStatus, USBAddr); + if (pCore->Class.CallBack_StartOfFrame.func != NULL) + { + pCore->Class.CallBack_StartOfFrame.func(pCore->Class.CallBack_StartOfFrame.uPara); + } + API_USB_CLR_SOF_INT(); + } + + /*--------------------------------------------------------------------------------------------------------*/ + /* USB SUSPEND Interrupt */ + /*--------------------------------------------------------------------------------------------------------*/ + if (API_USB_IS_SUSPEND_INT(USBISRFlag)) + { + __DBG_USBPrintf("%06ld SUSPEND[%02d]\r\n", ++__DBG_USBCount, pCore->Info.CurrentStatus); + API_USB_CLR_SUSPEND_INT(); + _USBDCore_Suspend(pCore); + } + + /*--------------------------------------------------------------------------------------------------------*/ + /* USB RESET Interrupt */ + /*--------------------------------------------------------------------------------------------------------*/ + if (API_USB_IS_RESET_INT(USBISRFlag)) + { + if (API_USB_IS_FRES_INT(USBISRFlag)) + { + API_USB_CLR_FRES_INT(); + } + else + { + __DBG_USBPrintf("%06ld RESET[%02d][%02lX]\r\n", ++__DBG_USBCount, pCore->Info.CurrentStatus, USBAddr); + _USBDCore_Reset(pCore); + if (pCore->Class.CallBack_Reset.func != NULL) + { + pCore->Class.CallBack_Reset.func(pCore->Class.CallBack_Reset.uPara); + } + } + API_USB_CLR_RESET_INT(); + } + + /*--------------------------------------------------------------------------------------------------------*/ + /* USB RESUME Interrupt */ + /*--------------------------------------------------------------------------------------------------------*/ + if (API_USB_IS_RESUME_INT(USBISRFlag)) + { + __DBG_USBPrintf("%06ld RESUME\r\n", ++__DBG_USBCount); + _USBDCore_Resume(pCore); + API_USB_CLR_RESUME_INT(); + } + + /*--------------------------------------------------------------------------------------------------------*/ + /* USB Endpoint 0 interrupt */ + /*--------------------------------------------------------------------------------------------------------*/ + if (API_USB_IS_EPTn_INT(USBISRFlag, USBD_EPT0)) + { + USBEPTISRFlag = API_USB_EPTn_GET_INT(USBD_EPT0); + + /*------------------------------------------------------------------------------------------------------*/ + /* Control SETUP Stage */ + /*------------------------------------------------------------------------------------------------------*/ + if (API_USB_IS_SETUP_INT(USBEPTISRFlag)) + { + API_USB_READ_SETUP(&(pCore->Device.Request)); /* Read SETUP Command data from USB Buffer*/ + + __DBG_USBPrintf("%06ld SETUP\t[08]\r\n", ++__DBG_USBCount); + __DBG_USBDump((uc8 *)&(pCore->Device.Request), 8); + + _USBDCore_Setup(pCore); + API_USB_CLR_SETUP_INT(); /* Clear SETUP Interrupt */ + } + + /*------------------------------------------------------------------------------------------------------*/ + /* Control Endpoint 0 IN */ + /*------------------------------------------------------------------------------------------------------*/ + if (API_USB_EPTn_IS_IN_INT(USBEPTISRFlag)) + { + __DBG_USBPrintf("%06ld EP0IN\t[%02ld]", ++__DBG_USBCount, pCore->Device.Transfer.sByteLength); + + _USBDCore_ControlIN(pCore); + API_USB_EPTn_CLR_IN_INT(USBD_EPT0); + } + + /*------------------------------------------------------------------------------------------------------*/ + /* Control Endpoint 0 OUT */ + /*------------------------------------------------------------------------------------------------------*/ + if (API_USB_EPTn_IS_OUT_INT(USBEPTISRFlag)) + { + __DBG_USBPrintf("%06ld EP0OUT\t[%02ld]", ++__DBG_USBCount, pCore->Device.Transfer.sByteLength); + + /*----------------------------------------------------------------------------------------------------*/ + /* Clear interrupt flag before USBDCore_ControlOUT is meaning since USBDCore_ControlOUT clear NAKRX */ + /* bit which will cause another interrupt occur. */ + /*----------------------------------------------------------------------------------------------------*/ + API_USB_EPTn_CLR_OUT_INT(USBD_EPT0); + _USBDCore_ControlOUT(pCore); + } + + /*------------------------------------------------------------------------------------------------------*/ + /* Clear Control Endpoint 0 global interrupt */ + /*------------------------------------------------------------------------------------------------------*/ + API_USB_CLR_EPTn_INT(USBD_EPT0); + + } /* if (API_USB_IS_EP_INT(USBISRFlag, USBD_EPT0)) */ + + + /*--------------------------------------------------------------------------------------------------------*/ + /* USB Endpoint n call back function */ + /*--------------------------------------------------------------------------------------------------------*/ + while ((EPTn = API_USB_GET_EPT_NUM(API_USB_GET_INT())) != USBD_NOEPT) + { + USBEPTISRFlag = API_USB_EPTn_GET_INT((USBD_EPTn_Enum)EPTn); + + if (API_USB_EPTn_IS_INT(USBEPTISRFlag)) + { + API_USB_EPTn_CLR_INT(EPTn); + API_USB_CLR_EPTn_INT(EPTn); + + if (pCore->Class.CallBack_EPTn[EPTn] != NULL) + { + pCore->Class.CallBack_EPTn[EPTn](EPTn); + } + } + } /* while ((EPTn = API_USB_GET_EPTn_NUM(API_USB_GET_INT())) != USBD_NOEPT) */ + + return; +} + +/*********************************************************************************************************//** + * @brief USB Core Main Routine for application. + * @param pCore: pointer of USB Device + * @retval None + ***********************************************************************************************************/ +void USBDCore_MainRoutine(USBDCore_TypeDef *pCore) +{ + _USBDCore_PowerHandler(pCore); + + /*--------------------------------------------------------------------------------------------------------*/ + /* Class main routine call back function */ + /*--------------------------------------------------------------------------------------------------------*/ + if ((pCore->Class.CallBack_MainRoutine.func != NULL) && (pCore->Info.CurrentStatus == USB_STATE_CONFIGURED)) + { + pCore->Class.CallBack_MainRoutine.func(pCore->Class.CallBack_MainRoutine.uPara); + } + + return; +} + +/*********************************************************************************************************//** + * @brief Return Suspend status + * @param pCore: pointer of USB Device + * @retval TRUE or FALSE + ***********************************************************************************************************/ +u32 USBDCore_IsSuspend(USBDCore_TypeDef *pCore) +{ + return ((pCore->Info.CurrentStatus == USB_STATE_SUSPENDED) ? TRUE : FALSE); +} + +/*********************************************************************************************************//** + * @brief Return remote wake status which set by SET FEATURE standard command + * @param pCore: pointer of USB Device + * @retval TRUE or FALSE + ***********************************************************************************************************/ +u32 USBDCore_GetRemoteWakeUpFeature(USBDCore_TypeDef *pCore) +{ + return (pCore->Info.CurrentFeature.Bits.bRemoteWakeup); +} + +/*********************************************************************************************************//** + * @brief Turn on USB power and remote wakeup the Host + * @retval None + ***********************************************************************************************************/ +void USBDCore_TriggerRemoteWakeup(void) +{ + API_USB_POWER_ON(); /* Turn on USB Power */ + API_USB_REMOTE_WAKEUP(); /* Generate Remote Wakeup request to Host (RESUME) */ + return; +} + +/*********************************************************************************************************//** + * @brief Get USB Device status + * @retval USBDCore_Status_Enum + ***********************************************************************************************************/ +USBDCore_Status_Enum USBDCore_GetStatus(void) +{ + return pUSBCore->Info.CurrentStatus; +} + +/*********************************************************************************************************//** + * @brief Dump memory data for debug purpose. + * @param memory: buffer pointer to dump + * @param len: dump length + * @retval None + ***********************************************************************************************************/ +#if (USBDCORE_DEBUG == 1 && USBDCORE_DEBUG_DATA == 1) +void __DBG_USBDump(uc8 *memory, u32 len) +{ + u32 i; + for (i = 0; i < len; i++) + { + if (i % 8 == 0) + { + if (i != 0) + { + __DBG_USBPrintf("\r\n"); + } + __DBG_USBPrintf("\t\t"); + } + __DBG_USBPrintf("%02X ", *((u8 *)(memory + i))); + } + __DBG_USBPrintf("\r\n"); + + return; +} +#endif +/** + * @} + */ + +/* Private functions ---------------------------------------------------------------------------------------*/ +/** @defgroup USBDCore_Private_Function USB Device Core private functions + * @{ + */ +/*********************************************************************************************************//** + * @brief USB Core Power handler for application. + * @param pCore: pointer of USB Device + * @retval None + ***********************************************************************************************************/ +static void _USBDCore_PowerHandler(USBDCore_TypeDef *pCore) +{ + API_USB_POWER_UP(pCore->pDriver, pCore->Info.CurrentFeature.Bits.bSelfPowered); + + if (pCore->Info.CurrentStatus == USB_STATE_SUSPENDED) + { + /*------------------------------------------------------------------------------------------------------*/ + /* System Low Power call back function */ + /*------------------------------------------------------------------------------------------------------*/ + if (pCore->Power.CallBack_Suspend.func != NULL) + { + __DBG_USBPrintf("%06ld >LOWPOWER\r\n", ++__DBG_USBCount); + + pCore->Power.CallBack_Suspend.func(pCore->Power.CallBack_Suspend.uPara); + + __DBG_USBPrintf("%06ld pDriver; + + pCore->Device.Transfer.sByteLength = USB_NO_DATA; + pCore->Info.uCurrentConfiguration = 0; + pCore->Info.uCurrentInterface = 0; + pCore->Info.CurrentFeature.Bits.bRemoteWakeup = 0; + pCore->Info.CurrentStatus = USB_STATE_DEFAULT; + pCore->Info.uIsDiscardClearFeature = FALSE; + + API_USB_DEINIT(); + + API_USB_POWER_ON(); + + /* Endpoint 0 initialization */ + API_USB_EPTn_INIT(USBD_EPT0, pCore->pDriver); // To be modify, init from desc + + /* Enable USB interrupt */ + API_USB_ENABLE_INT(pDrv->uInterruptMask); + + return; +} + +/*********************************************************************************************************//** + * @brief USB Resume + * @param pCore: pointer of USB Device + * @retval None + ***********************************************************************************************************/ +static void _USBDCore_Resume(USBDCore_TypeDef *pCore) +{ + API_USB_POWER_ON(); + pCore->Info.CurrentStatus = pCore->Info.LastStatus; + return; +} + +/*********************************************************************************************************//** + * @brief USB Suspend + * @param pCore: pointer of USB Device + * @retval None + ***********************************************************************************************************/ +static void _USBDCore_Suspend(USBDCore_TypeDef *pCore) +{ + /*--------------------------------------------------------------------------------------------------------*/ + /* When Device has been suspended, Change CurrentStatus as SUSPEND and then USBDCore_PowerHandler will */ + /* turn off chip power. */ + /*--------------------------------------------------------------------------------------------------------*/ + if (pCore->Info.CurrentStatus >= USB_STATE_POWERED) + { + API_USB_POWER_OFF(); + pCore->Info.LastStatus = pCore->Info.CurrentStatus; + pCore->Info.CurrentStatus = USB_STATE_SUSPENDED; + } + + return; +} + +/*********************************************************************************************************//** + * @brief USB Setup Stage + * @param pCore: pointer of USB Device + * @retval None + ***********************************************************************************************************/ +static void _USBDCore_Setup(USBDCore_TypeDef *pCore) +{ + pCore->Device.Transfer.Action = USB_ACTION_STALL; + pCore->Device.Transfer.sByteLength = 0; + + switch (pCore->Device.Request.bmRequestType & BMREQUEST_TYPE_MASK) + { + /*------------------------------------------------------------------------------------------------------*/ + /* Standard requests */ + /*------------------------------------------------------------------------------------------------------*/ + case REQ_TYPE_00_STD: + { + _USBDCore_Standard_Request(pCore); + break; + } + /*------------------------------------------------------------------------------------------------------*/ + /* Class requests */ + /*------------------------------------------------------------------------------------------------------*/ + case REQ_TYPE_01_CLS: + { + if (pCore->Class.CallBack_ClassRequest != NULL) + { + pCore->Class.CallBack_ClassRequest(&(pCore->Device)); + } + break; + } + /*------------------------------------------------------------------------------------------------------*/ + /* Vendor requests */ + /*------------------------------------------------------------------------------------------------------*/ + case REQ_TYPE_02_VND: + { + if (pCore->Class.CallBack_VendorRequest != NULL) + { + pCore->Class.CallBack_VendorRequest(&(pCore->Device)); + } + /* Add Vendor requests handler here.... */ + #ifdef USBD_VENDOR_SUPPORT + USBDVendor_Request(pCore); + #endif + break; + } + } /* switch (gUSBReq.bmRequestType.byte) */ + + switch (pCore->Device.Transfer.Action) + { + /*------------------------------------------------------------------------------------------------------*/ + /* Control IN */ + /*------------------------------------------------------------------------------------------------------*/ + case USB_ACTION_DATAIN: + { + /*----------------------------------------------------------------------------------------------------*/ + /* When the Control IN length is large than the Host required, transfer the length which specified */ + /* by SETUP Data Packet. */ + /*----------------------------------------------------------------------------------------------------*/ + if (pCore->Device.Transfer.sByteLength > pCore->Device.Request.wLength) + { + pCore->Device.Transfer.sByteLength = pCore->Device.Request.wLength; + } + __DBG_USBPrintf("%06ld EP0IN\t[%02ld]", __DBG_USBCount, pCore->Device.Transfer.sByteLength); + + _USBDCore_ControlIN(pCore); + break; + } + /*------------------------------------------------------------------------------------------------------*/ + /* Control OUT */ + /*------------------------------------------------------------------------------------------------------*/ + case USB_ACTION_DATAOUT: + { + if (pCore->Device.Transfer.sByteLength == 0) + { + API_USB_EPTn_WRITE_IN(USBD_EPT0, (u32 *)0, 0); /* Prepare ZLP ack for Control OUT */ + } + break; + } + /*------------------------------------------------------------------------------------------------------*/ + /* STALL */ + /*------------------------------------------------------------------------------------------------------*/ + default: + { + __DBG_USBPrintf("%06ld EP0 STALL\r\n", __DBG_USBCount); + + API_USB_EPTn_SEND_STALL(USBD_EPT0); + break; + } + } + + return; +} + +/*********************************************************************************************************//** + * @brief USB Stand Request. + * @param pCore: pointer of USB Device + * @retval None + ***********************************************************************************************************/ +static void _USBDCore_Standard_Request(USBDCore_TypeDef *pCore) +{ + u16 USBCmd = *((u16 *)(&(pCore->Device.Request))); + + switch (USBCmd) + { + /*------------------------------------------------------------------------------------------------------*/ + /* | bRequest | Data transfer direction | Type | Recipient | Data */ + /*------------------------------------------------------------------------------------------------------*/ + + /*------------------------------------------------------------------------------------------------------*/ + /* | 00_Get Status | 80_Device-to-Host | 00_Standard Request | 0_Device | 0080h */ + /*------------------------------------------------------------------------------------------------------*/ + case (REQ_00_GET_STAT | REQ_DIR_01_D2H | REQ_TYPE_00_STD | REQ_REC_00_DEV): + { + __DBG_USBPrintf("%06ld GET DST\t[%02d]\r\n", __DBG_USBCount, pCore->Info.CurrentFeature.uByte); + _USBDCore_Standard_GetStatus(pCore, Device); + break; + } + /*------------------------------------------------------------------------------------------------------*/ + /* | 00_Get Status | 80_Device-to-Host | 00_Standard Request | 1_Interface | 0081h */ + /*------------------------------------------------------------------------------------------------------*/ + case (REQ_00_GET_STAT | REQ_DIR_01_D2H | REQ_TYPE_00_STD | REQ_REC_01_INF): + { + __DBG_USBPrintf("%06ld GET IST\t[%02d]\r\n", __DBG_USBCount, 0); + _USBDCore_Standard_GetStatus(pCore, Interface); + break; + } + /*------------------------------------------------------------------------------------------------------*/ + /* | 00_Get Status | 80_Device-to-Host | 00_Standard Request | 2_Endpoint | 0082h */ + /*------------------------------------------------------------------------------------------------------*/ + case (REQ_00_GET_STAT | REQ_DIR_01_D2H | REQ_TYPE_00_STD | REQ_REC_02_EPT): + { + __DBG_USBPrintf("%06ld GET EST\t[%02d]\r\n", __DBG_USBCount, pCore->Device.Request.wIndex); + _USBDCore_Standard_GetStatus(pCore, Endpoint); + break; + } + /*------------------------------------------------------------------------------------------------------*/ + /* | 01_Clear Feature | 00_Host-to-Device | 00_Standard Request | 0_Device | 0100h */ + /*------------------------------------------------------------------------------------------------------*/ + case (REQ_01_CLR_FETU | REQ_DIR_00_H2D | REQ_TYPE_00_STD | REQ_REC_00_DEV): + { + __DBG_USBPrintf("%06ld CLR DFEA\t[%02d]\r\n", __DBG_USBCount, pCore->Device.Request.wValueL); + _USBDCore_Standard_SetClearFeature(pCore, Device, ClearFeature); + break; + } + /*------------------------------------------------------------------------------------------------------*/ + /* | 01_Clear Feature | 00_Host-to-Device | 00_Standard Request | 2_Endpoint | 0102h */ + /*------------------------------------------------------------------------------------------------------*/ + case (REQ_01_CLR_FETU | REQ_DIR_00_H2D | REQ_TYPE_00_STD | REQ_REC_02_EPT): + { + __DBG_USBPrintf("%06ld CLR EFEA\t[0x%02x]\r\n", __DBG_USBCount, pCore->Device.Request.wIndex); + _USBDCore_Standard_SetClearFeature(pCore, Endpoint, ClearFeature); + break; + } + /*------------------------------------------------------------------------------------------------------*/ + /* | 03_Set Feature | 00_Host-to-Device | 00_Standard Request | 0_Device | 0300h */ + /*------------------------------------------------------------------------------------------------------*/ + case (REQ_03_SET_FETU | REQ_DIR_00_H2D | REQ_TYPE_00_STD | REQ_REC_00_DEV): + { + __DBG_USBPrintf("%06ld SET DFEA\t[%02d]\r\n", __DBG_USBCount, pCore->Device.Request.wValueL); + _USBDCore_Standard_SetClearFeature(pCore, Device, SetFeature); + break; + } + /*------------------------------------------------------------------------------------------------------*/ + /* | 03_Set Feature | 00_Host-to-Device | 00_Standard Request | 2_Endpoint | 0302h */ + /*------------------------------------------------------------------------------------------------------*/ + case (REQ_03_SET_FETU | REQ_DIR_00_H2D | REQ_TYPE_00_STD | REQ_REC_02_EPT): + { + __DBG_USBPrintf("%06ld SET EFEA\t[%02d]\r\n", __DBG_USBCount, pCore->Device.Request.wIndex); + _USBDCore_Standard_SetClearFeature(pCore, Endpoint, SetFeature); + break; + } + /*------------------------------------------------------------------------------------------------------*/ + /* | 05_Set Address | 00_Host-to-Device | 00_Standard Request | 0_Device | 0500h */ + /*------------------------------------------------------------------------------------------------------*/ + case (REQ_05_SET_ADDR | REQ_DIR_00_H2D | REQ_TYPE_00_STD | REQ_REC_00_DEV): + { + __DBG_USBPrintf("%06ld SET ADDR\t[%02d]\r\n", __DBG_USBCount, pCore->Device.Request.wValueL); + _USBDCore_Standard_SetAddress(pCore); + break; + } + /*------------------------------------------------------------------------------------------------------*/ + /* | 06_Get Descriptor | 80_Device-to-Host | 00_Standard Request | 0_Device | 0680h */ + /*------------------------------------------------------------------------------------------------------*/ + case (REQ_06_GET_DESC | REQ_DIR_01_D2H | REQ_TYPE_00_STD | REQ_REC_00_DEV): + { + __DBG_USBPrintf("%06ld GET DDESC\t[%02X]\r\n", __DBG_USBCount, pCore->Device.Request.wValueH); + _USBDCore_Standard_GetDescriptor(pCore); + break; + } + /*------------------------------------------------------------------------------------------------------*/ + /* | 06_Get Descriptor | 80_Device-to-Host | 00_Standard Request | 1_Interface | 0681h */ + /*------------------------------------------------------------------------------------------------------*/ + case (REQ_06_GET_DESC | REQ_DIR_01_D2H | REQ_TYPE_00_STD | REQ_REC_01_INF): + { + __DBG_USBPrintf("%06ld GET IDESC\t[%02X]\r\n", __DBG_USBCount, pCore->Device.Request.wValueH); + if (pCore->Class.CallBack_ClassGetDescriptor != NULL) + { + pCore->Class.CallBack_ClassGetDescriptor((USBDCore_Device_TypeDef *)&(pCore->Device)); + } + break; + } + /*------------------------------------------------------------------------------------------------------*/ + /* | 08_Get Configuration | 80_Host-to-Device | 00_Standard Request | 0_Device | 0880h */ + /*------------------------------------------------------------------------------------------------------*/ + case (REQ_08_GET_CONF | REQ_DIR_01_D2H | REQ_TYPE_00_STD | REQ_REC_00_DEV): + { + __DBG_USBPrintf("%06ld GET CONF\t[%02X]\r\n", __DBG_USBCount, pCore->Info.uCurrentConfiguration); + _USBDCore_Standard_GetConfiguration(pCore); + break; + } + /*------------------------------------------------------------------------------------------------------*/ + /* | 09_Set Configuration | 00_Host-to-Device | 00_Standard Request | 0_Device | 0900h */ + /*------------------------------------------------------------------------------------------------------*/ + case (REQ_09_SET_CONF | REQ_DIR_00_H2D | REQ_TYPE_00_STD | REQ_REC_00_DEV): + { + __DBG_USBPrintf("%06ld SET CONF\t[%02X]\r\n", __DBG_USBCount, pCore->Device.Request.wValueL); + _USBDCore_Standard_SetConfiguration(pCore); + break; + } + /*------------------------------------------------------------------------------------------------------*/ + /* | 11_Set Interface | 00_Host-to-Device | 00_Standard Request | 1_Interface | 0B01h */ + /*------------------------------------------------------------------------------------------------------*/ + case (REQ_11_SET_INF | REQ_DIR_00_H2D | REQ_TYPE_00_STD | REQ_REC_01_INF): + { + __DBG_USBPrintf("%06ld SET INF\t[%02X]\r\n", __DBG_USBCount, pCore->Device.Request.wValueL); + if (pCore->Class.CallBack_ClassSetInterface != NULL) + { + pCore->Class.CallBack_ClassSetInterface((USBDCore_Device_TypeDef *)&(pCore->Device)); + } + break; + } + /*------------------------------------------------------------------------------------------------------*/ + /* | 10_Get Interface | 80_Device-to-Host | 00_Standard Request | 1_Interface | 0A81h */ + /*------------------------------------------------------------------------------------------------------*/ + case (REQ_10_GET_INF | REQ_DIR_01_D2H | REQ_TYPE_00_STD | REQ_REC_01_INF): + { + __DBG_USBPrintf("%06ld GET INF\t[%02X]\r\n", __DBG_USBCount, pCore->Device.Request.wValueL); + if (pCore->Class.CallBack_ClassGetInterface != NULL) + { + pCore->Class.CallBack_ClassGetInterface((USBDCore_Device_TypeDef *)&(pCore->Device)); + } + break; + } + } + + return; +} + +/*********************************************************************************************************//** + * @brief USB Standard Request - GET_STATUS. + * @param pCore: pointer of USB Device + * @param recipient: Recipient + * @arg Device: 0 + * @arg Interface: 1 + * @arg Endpoint: 2 + * @retval None + ***********************************************************************************************************/ +static void _USBDCore_Standard_GetStatus(USBDCore_TypeDef *pCore, USBDCore_Recipient_Enum recipient) +{ + pCore->Device.Transfer.uBuffer[1] = 0; + switch (recipient) + { + case Device: + { + pCore->Device.Transfer.uBuffer[0] = pCore->Info.CurrentFeature.uByte; + break; + } + case Interface: + { + pCore->Device.Transfer.uBuffer[0] = 0; + break; + } + case Endpoint: + { + pCore->Device.Transfer.uBuffer[0] = API_USB_EPTn_GET_HALT((USBD_EPTn_Enum)(pCore->Device.Request.wIndex & 0xF)); + break; + } + default: + { + return; + } + } + + pCore->Device.Transfer.pData = (uc8 *)&(pCore->Device.Transfer.uBuffer); + pCore->Device.Transfer.sByteLength = 2; + pCore->Device.Transfer.Action = USB_ACTION_DATAIN; + + return; +} + +/*********************************************************************************************************//** + * @brief USB Standard Request - SET_FEATURE / CLEAR_FEATURE. + * @param pCore: pointer of USB Device + * @param recipient: Recipient + * @arg Device: 0 + * @arg Interface: 1 + * @arg Endpoint: 2 + * @param type: + * @arg ClearFeature: 0 + @arg SerFeature: 1 + * @retval None + ***********************************************************************************************************/ +static void _USBDCore_Standard_SetClearFeature(USBDCore_TypeDef *pCore, + USBDCore_Recipient_Enum recipient, + USBDCore_SetClearFeature_Enum type) +{ + u32 i; + switch (recipient) + { + case Device: + { + if (pCore->Device.Request.wValueL == USB_FEATURE_REMOTE_WAKEUP) + { + pCore->Info.CurrentFeature.Bits.bRemoteWakeup = type; + pCore->Device.Transfer.Action = USB_ACTION_DATAIN; + } + break; + } + case Endpoint: + { + i = pCore->Device.Request.wIndex & 0xF; + if (i != 0) + { + if (type == ClearFeature) + { + if (pCore->Info.uIsDiscardClearFeature == FALSE) + { + API_USB_EPTn_CLR_HALT((USBD_EPTn_Enum)i); + API_USB_EPTn_CLR_DTG((USBD_EPTn_Enum)i); + } + } + else + { + API_USB_EPTn_SET_HALT((USBD_EPTn_Enum)i); + } + } + pCore->Device.Transfer.Action = USB_ACTION_DATAIN; + break; + } + default: + { + break; + } + } + + return; +} + +/*********************************************************************************************************//** + * @brief USB Standard Request - SET_ADDRESS. + * @param pCore: pointer of USB Device + * @retval None + ***********************************************************************************************************/ +static void _USBDCore_Standard_SetAddress(USBDCore_TypeDef *pCore) +{ + API_USB_SET_ADDR(pCore->Device.Request.wValueL); + pCore->Device.Transfer.Action = USB_ACTION_DATAIN; + pCore->Info.CurrentStatus = USB_STATE_ADDRESS; + + return; +} + +/*********************************************************************************************************//** + * @brief USB Standard Request - GET_DESCRIPTOR. + * @param pCore: pointer of USB Device + * @retval None + ***********************************************************************************************************/ +static void _USBDCore_Standard_GetDescriptor(USBDCore_TypeDef *pCore) +{ + u32 value = pCore->Device.Request.wValueH; + uc8 *pTemp; + + switch (value) + { + case DESC_TYPE_01_DEV: + { + pCore->Device.Transfer.pData = pCore->Device.Desc.pDeviceDesc; + pCore->Device.Transfer.sByteLength = *(pCore->Device.Desc.pDeviceDesc); + pCore->Device.Transfer.Action= USB_ACTION_DATAIN; + break; + } + case DESC_TYPE_02_CONFN: + { + pCore->Device.Transfer.pData = pCore->Device.Desc.pConfnDesc; + pCore->Device.Transfer.sByteLength = *(u16 *)((pCore->Device.Desc.pConfnDesc) + 2); + pCore->Device.Transfer.Action = USB_ACTION_DATAIN; + break; + } + case DESC_TYPE_03_STR: + { + value = pCore->Device.Request.wValueL; + if (value < pCore->Device.Desc.uStringDescNumber) + { + if (*(pCore->Device.Desc.ppStringDesc + value) != NULL) + { + pTemp = *(pCore->Device.Desc.ppStringDesc + value); + pCore->Device.Transfer.pData = (uc8 *)(pTemp); + pCore->Device.Transfer.sByteLength = *(pTemp); + pCore->Device.Transfer.Action = USB_ACTION_DATAIN; + } + } + break; + } + } + + #ifdef USBD_VENDOR_SUPPORT + USBDVendor_StandardGetDescriptor(pCore); + #endif + + return; +} + +/*********************************************************************************************************//** + * @brief USB Standard Request - GET_CONFIGURATION. + * @param pCore: pointer of USB Device + * @retval None + ***********************************************************************************************************/ +static void _USBDCore_Standard_GetConfiguration(USBDCore_TypeDef *pCore) +{ + pCore->Device.Transfer.pData = &(pCore->Info.uCurrentConfiguration); + pCore->Device.Transfer.sByteLength = 1; + pCore->Device.Transfer.Action= USB_ACTION_DATAIN; + + return; +} + +/*********************************************************************************************************//** + * @brief USB Standard Request - SET_CONFIGURATION. + * @param pCore: pointer of USB Device + * @retval None + ***********************************************************************************************************/ +static void _USBDCore_Standard_SetConfiguration(USBDCore_TypeDef *pCore) +{ + u32 i; + + pCore->Info.uCurrentConfiguration = pCore->Device.Request.wValueL; + pCore->Device.Transfer.Action= USB_ACTION_DATAIN; + + /* Endpoint n settings */ + for (i = 1; i < MAX_EP_NUM; i++) + { + API_USB_EPTn_INIT((USBD_EPTn_Enum)i, pCore->pDriver); // To be modify, init from desc + } + + pCore->Info.CurrentStatus = USB_STATE_CONFIGURED; + + return; +} + +/*********************************************************************************************************//** + * @brief USB Control IN transfer. + * @param pCore: pointer of USB Device + * @retval None + ***********************************************************************************************************/ +static void _USBDCore_ControlIN(USBDCore_TypeDef *pCore) +{ + s32 EP0INLen = API_USB_GET_CTRL_IN_LEN(); + u32 len; + + if (pCore->Device.Transfer.sByteLength != USB_NO_DATA && pCore->Device.Transfer.Action == USB_ACTION_DATAIN) + { + if (pCore->Device.Transfer.sByteLength >= EP0INLen) + { + len = EP0INLen; + pCore->Device.Transfer.sByteLength -= len; + } + else + { + len = pCore->Device.Transfer.sByteLength; + pCore->Device.Transfer.sByteLength = USB_NO_DATA; + pCore->Device.Transfer.Action = USB_ACTION_DATAOUT; + } + + __DBG_USBPrintf("[%02ld]\r\n", len); + __DBG_USBDump((uc8 *)pCore->Device.Transfer.pData, len); + + API_USB_EPTn_WRITE_IN(USBD_EPT0, (u32 *)pCore->Device.Transfer.pData, len); + pCore->Device.Transfer.pData = pCore->Device.Transfer.pData + len; + } + else + { + __DBG_USBPrintf("[-1]\r\n"); + } + + return; +} + +/*********************************************************************************************************//** + * @brief USB Control OUT transfer. + * @param pCore: pointer of USB Device + * @retval None + ***********************************************************************************************************/ +static void _USBDCore_ControlOUT(USBDCore_TypeDef *pCore) +{ + u32 len; + + if (pCore->Device.Transfer.sByteLength != USB_NO_DATA && pCore->Device.Transfer.Action == USB_ACTION_DATAOUT) + { + len = API_USB_EPTn_READ_OUT(USBD_EPT0, (u32 *)pCore->Device.Transfer.pData, MAX_CONTROL_OUT_SIZE); + + __DBG_USBPrintf("[%02ld]\r\n", len); + __DBG_USBDump((uc8 *)pCore->Device.Transfer.pData, len); + + pCore->Device.Transfer.pData = pCore->Device.Transfer.pData + len; + pCore->Device.Transfer.sByteLength -= len; + + if (pCore->Device.Transfer.sByteLength == 0) + { + pCore->Device.Transfer.Action = USB_ACTION_DATAIN; + if (pCore->Device.Transfer.CallBack_OUT.func != NULL) + { + pCore->Device.Transfer.CallBack_OUT.func(pCore->Device.Transfer.CallBack_OUT.uPara); + pCore->Device.Transfer.CallBack_OUT.func = NULL; + } + pCore->Device.Transfer.sByteLength = USB_NO_DATA; + API_USB_EPTn_WRITE_IN(USBD_EPT0, (u32 *)0, 0); + } + } + else + { + __DBG_USBPrintf("[-1]\r\n"); + } + + return; +} +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ diff --git a/bsp/ht32/libraries/Kconfig b/bsp/ht32/libraries/Kconfig new file mode 100644 index 0000000000..80395cb727 --- /dev/null +++ b/bsp/ht32/libraries/Kconfig @@ -0,0 +1,12 @@ +config SOC_FAMILY_HT32 + bool + +config SOC_SERIES_HT32F5 + bool + select ARCH_ARM_CORTEX_M0 + select SOC_FAMILY_HT32 + +config SOC_SERIES_HT32F1 + bool + select ARCH_ARM_CORTEX_M3 + select SOC_FAMILY_HT32 diff --git a/bsp/ht32/libraries/ht32_drivers/SConscript b/bsp/ht32/libraries/ht32_drivers/SConscript new file mode 100644 index 0000000000..10c92e8492 --- /dev/null +++ b/bsp/ht32/libraries/ht32_drivers/SConscript @@ -0,0 +1,37 @@ +#导入其他模块中的变量 +Import('RTT_ROOT') +Import('rtconfig') + +#导入使用到的模块 +from building import * + +#获取当前目录的路径 +cwd = GetCurrentDir() + +#创建一个列表，用于保存需要使用到的C文件路径 +src = Split(""" +drv_common.c +""") +#drv_common.c +#根据宏定义来对需要用到的C文件进行裁剪 +if GetDepend(['BSP_USING_GPIO']): + src += ['drv_gpio.c'] + +if GetDepend(['BSP_USING_UART']): + src += ['drv_usart.c'] + +if GetDepend(['BSP_USING_SPI']): + src += ['drv_spi.c'] + +if GetDepend(['BSP_USING_I2C']): + src += ['drv_i2c.c'] + +#创建一个列表，用于保存需要包含的H文件路径 +path = [cwd] + +#创建一个组别 +group = DefineGroup('Drivers', src ,depend = [''], CPPPATH = path) + +#返回创建好的组别 +Return('group') + diff --git a/bsp/ht32/libraries/ht32_drivers/drv_common.c b/bsp/ht32/libraries/ht32_drivers/drv_common.c new file mode 100644 index 0000000000..1bdb6a36e1 --- /dev/null +++ b/bsp/ht32/libraries/ht32_drivers/drv_common.c @@ -0,0 +1,82 @@ +/* + * Copyright (c) 2006-2024, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2024-04-08 QT-one first version + */ + +#include +#include "drv_common.h" +#ifdef RT_USING_SERIAL + #include "drv_usart.h" +#endif + +#ifdef RT_USING_FINSH +#include +static void reboot(uint8_t argc, char **argv) +{ + rt_hw_cpu_reset(); +} +MSH_CMD_EXPORT(reboot, Reboot System); +#endif /* RT_USING_FINSH */ + +/* SysTick configuration */ +void rt_hw_systick_init(void) +{ + SYSTICK_ClockSourceConfig(SYSTICK_SRC_STCLK); + SYSTICK_SetReloadValue(SystemCoreClock / 8 / RT_TICK_PER_SECOND); + SYSTICK_IntConfig(ENABLE); + SYSTICK_CounterCmd(SYSTICK_COUNTER_CLEAR); + SYSTICK_CounterCmd(SYSTICK_COUNTER_ENABLE); +} + +/* This is the timer interrupt service routine */ +void SysTick_Handler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + rt_tick_increase(); + + /* leave interrupt */ + rt_interrupt_leave(); +} + +/* This function is executed in case of error occurrence */ +void _Error_Handler(char *s, int num) +{ + /* User can add his own implementation to report the error return state */ + LOG_E("Error_Handler at file:%s num:%d", s, num); + while (1) + { + } +} + +/* This function will initial HT32 board */ +void rt_hw_board_init(void) +{ + /* Configure the System clock */ + rt_hw_board_clock_init(); + + /* Configure the SysTick */ + rt_hw_systick_init(); + + /* heap initialization */ +#ifdef RT_USING_HEAP + rt_system_heap_init((void *)HEAP_BEGIN, (void *)HEAP_END); +#endif + + /* board underlying hardware initialization */ +#ifdef RT_USING_COMPONENTS_INIT + rt_components_board_init(); +#endif + + /* set the shell console output device */ +#ifdef RT_USING_CONSOLE + rt_console_set_device(RT_CONSOLE_DEVICE_NAME); +#endif + +} diff --git a/bsp/ht32/libraries/ht32_drivers/drv_common.h b/bsp/ht32/libraries/ht32_drivers/drv_common.h new file mode 100644 index 0000000000..f35cb885a6 --- /dev/null +++ b/bsp/ht32/libraries/ht32_drivers/drv_common.h @@ -0,0 +1,37 @@ +/* + * Copyright (c) 2006-2024, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2024-04-08 QT-one first version + */ + +#ifndef __DRV_COMMON_H__ +#define __DRV_COMMON_H__ + +#include +#include +#ifdef RT_USING_DEVICE + #include +#endif +#include "board.h" + +#ifdef __cplusplus +extern "C" { +#endif + +void _Error_Handler(char *s, int num); + +#ifndef Error_Handler +#define Error_Handler() _Error_Handler(__FILE__, __LINE__) +#endif + +#define DMA_NOT_AVAILABLE ((DMA_INSTANCE_TYPE *)0xFFFFFFFFU) + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsp/ht32/libraries/ht32_drivers/drv_gpio.c b/bsp/ht32/libraries/ht32_drivers/drv_gpio.c new file mode 100644 index 0000000000..5df27aad7b --- /dev/null +++ b/bsp/ht32/libraries/ht32_drivers/drv_gpio.c @@ -0,0 +1,910 @@ +/* + * Copyright (c) 2006-2024, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2024-04-08 QT-one first version + */ + +#include "drv_gpio.h" + +#ifdef RT_USING_PIN + +#define __HT32_PIN(index, gpio, pin) \ + { \ + index, HT_GPIO##gpio, GPIO_PIN_##pin \ + } + +struct pin_index +{ + int index; + HT_GPIO_TypeDef *gpio; + uint32_t pin; +}; + +struct pin_irq_map +{ + rt_uint16_t pinbit; + IRQn_Type irqno; +}; + +static const struct pin_index pins[] = +{ +#if defined(HT_GPIOA) + __HT32_PIN(0, A, 0), + __HT32_PIN(1, A, 1), + __HT32_PIN(2, A, 2), + __HT32_PIN(3, A, 3), + __HT32_PIN(4, A, 4), + __HT32_PIN(5, A, 5), + __HT32_PIN(6, A, 6), + __HT32_PIN(7, A, 7), + __HT32_PIN(8, A, 8), + __HT32_PIN(9, A, 9), + __HT32_PIN(10, A, 10), + __HT32_PIN(11, A, 11), + __HT32_PIN(12, A, 12), + __HT32_PIN(13, A, 13), + __HT32_PIN(14, A, 14), + __HT32_PIN(15, A, 15), +#if defined(HT_GPIOB) + __HT32_PIN(16, B, 0), + __HT32_PIN(17, B, 1), + __HT32_PIN(18, B, 2), + __HT32_PIN(19, B, 3), + __HT32_PIN(20, B, 4), + __HT32_PIN(21, B, 5), + __HT32_PIN(22, B, 6), + __HT32_PIN(23, B, 7), + __HT32_PIN(24, B, 8), + __HT32_PIN(25, B, 9), + __HT32_PIN(26, B, 10), + __HT32_PIN(27, B, 11), + __HT32_PIN(28, B, 12), + __HT32_PIN(29, B, 13), + __HT32_PIN(30, B, 14), + __HT32_PIN(31, B, 15), +#if defined(HT_GPIOC) + __HT32_PIN(32, C, 0), + __HT32_PIN(33, C, 1), + __HT32_PIN(34, C, 2), + __HT32_PIN(35, C, 3), + __HT32_PIN(36, C, 4), + __HT32_PIN(37, C, 5), + __HT32_PIN(38, C, 6), + __HT32_PIN(39, C, 7), + __HT32_PIN(40, C, 8), + __HT32_PIN(41, C, 9), + __HT32_PIN(42, C, 10), + __HT32_PIN(43, C, 11), + __HT32_PIN(44, C, 12), + __HT32_PIN(45, C, 13), + __HT32_PIN(46, C, 14), + __HT32_PIN(47, C, 15), +#if defined(HT_GPIOD) + __HT32_PIN(48, D, 0), + __HT32_PIN(49, D, 1), + __HT32_PIN(50, D, 2), + __HT32_PIN(51, D, 3), + __HT32_PIN(52, D, 4), + __HT32_PIN(53, D, 5), + __HT32_PIN(54, D, 6), + __HT32_PIN(55, D, 7), + __HT32_PIN(56, D, 8), + __HT32_PIN(57, D, 9), + __HT32_PIN(58, D, 10), + __HT32_PIN(59, D, 11), + __HT32_PIN(60, D, 12), + __HT32_PIN(61, D, 13), + __HT32_PIN(62, D, 14), + __HT32_PIN(63, D, 15), +#if defined(HT_GPIOE) + __HT32_PIN(64, E, 0), + __HT32_PIN(65, E, 1), + __HT32_PIN(66, E, 2), + __HT32_PIN(67, E, 3), + __HT32_PIN(68, E, 4), + __HT32_PIN(69, E, 5), + __HT32_PIN(70, E, 6), + __HT32_PIN(71, E, 7), + __HT32_PIN(72, E, 8), + __HT32_PIN(73, E, 9), + __HT32_PIN(74, E, 10), + __HT32_PIN(75, E, 11), + __HT32_PIN(76, E, 12), + __HT32_PIN(77, E, 13), + __HT32_PIN(78, E, 14), + __HT32_PIN(79, E, 15), +#if defined(HT_GPIOF) + __HT32_PIN(80, F, 0), + __HT32_PIN(81, F, 1), + __HT32_PIN(82, F, 2), + __HT32_PIN(83, F, 3), + __HT32_PIN(84, F, 4), + __HT32_PIN(85, F, 5), + __HT32_PIN(86, F, 6), + __HT32_PIN(87, F, 7), + __HT32_PIN(88, F, 8), + __HT32_PIN(89, F, 9), + __HT32_PIN(90, F, 10), + __HT32_PIN(91, F, 11), + __HT32_PIN(92, F, 12), + __HT32_PIN(93, F, 13), + __HT32_PIN(94, F, 14), + __HT32_PIN(95, F, 15), +#endif /* defined(HT_GPIOF) */ +#endif /* defined(HT_GPIOE) */ +#endif /* defined(HT_GPIOD) */ +#endif /* defined(HT_GPIOC) */ +#endif /* defined(HT_GPIOB) */ +#endif /* defined(HT_GPIOA) */ +}; + +static const struct pin_irq_map pin_irq_map[] = +{ + {GPIO_PIN_0, EXTI0_IRQn}, + {GPIO_PIN_1, EXTI1_IRQn}, + {GPIO_PIN_2, EXTI2_IRQn}, + {GPIO_PIN_3, EXTI3_IRQn}, + {GPIO_PIN_4, EXTI4_IRQn}, + {GPIO_PIN_5, EXTI5_IRQn}, + {GPIO_PIN_6, EXTI6_IRQn}, + {GPIO_PIN_7, EXTI7_IRQn}, + {GPIO_PIN_8, EXTI8_IRQn}, + {GPIO_PIN_9, EXTI9_IRQn}, + {GPIO_PIN_10, EXTI10_IRQn}, + {GPIO_PIN_11, EXTI11_IRQn}, + {GPIO_PIN_12, EXTI12_IRQn}, + {GPIO_PIN_13, EXTI13_IRQn}, + {GPIO_PIN_14, EXTI14_IRQn}, + {GPIO_PIN_15, EXTI15_IRQn}, +}; + +static struct rt_pin_irq_hdr pin_irq_hdr_tab[] = +{ + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, +}; + +#define ITEM_NUM(items) sizeof(items) / sizeof(items[0]) + +static const struct pin_index *get_pin(rt_uint8_t pin) +{ + const struct pin_index *index; + + if (pin < ITEM_NUM(pins)) + { + index = &pins[pin]; + if (index->index == -1) + index = RT_NULL; + } + else + { + index = RT_NULL; + } + return index; +} + +static void ht32_pin_mode(rt_device_t dev, rt_base_t pin, rt_uint8_t mode) +{ + const struct pin_index *index; + index = get_pin(pin); + if (index == RT_NULL) + { + return; + } + + CKCU_PeripClockConfig_TypeDef CKCUClock = {{0}}; + if ((index->gpio) == HT_GPIOA) + CKCUClock.Bit.PA = 1; + else if ((index->gpio) == HT_GPIOB) + CKCUClock.Bit.PB = 1; +#if defined(HT_GPIOC) + else if ((index->gpio) == HT_GPIOC) + CKCUClock.Bit.PC = 1; +#endif +#if defined(HT_GPIOD) + else if ((index->gpio) == HT_GPIOD) + CKCUClock.Bit.PD = 1; +#endif +#if defined(HT_GPIOE) + else if ((index->gpio) == HT_GPIOE) + CKCUClock.Bit.PE = 1; +#endif +#if defined(HT_GPIOF) + else if ((index->gpio) == HT_GPIOF) + CKCUClock.Bit.PF = 1; +#endif + CKCUClock.Bit.AFIO = 1; + CKCUClock.Bit.BKP = 1; + CKCU_PeripClockConfig(CKCUClock, ENABLE); + + if ((index->gpio) == HT_GPIOA) + AFIO_GPxConfig(GPIO_PA, index->pin, AFIO_MODE_1); + else if ((index->gpio) == HT_GPIOB) + AFIO_GPxConfig(GPIO_PB, index->pin, AFIO_MODE_1); +#if defined(HT_GPIOC) + else if ((index->gpio) == HT_GPIOC) + AFIO_GPxConfig(GPIO_PC, index->pin, AFIO_MODE_1); +#endif +#if defined(HT_GPIOD) + else if ((index->gpio) == HT_GPIOD) + AFIO_GPxConfig(GPIO_PD, index->pin, AFIO_MODE_1); +#endif +#if defined(HT_GPIOE) + else if ((index->gpio) == HT_GPIOE) + AFIO_GPxConfig(GPIO_PE, index->pin, AFIO_MODE_1); +#endif +#if defined(HT_GPIOF) + else if ((index->gpio) == HT_GPIOF) + AFIO_GPxConfig(GPIO_PF, index->pin, AFIO_MODE_1); +#endif + + switch (mode) + { + case PIN_MODE_OUTPUT: + /* output setting */ + GPIO_DirectionConfig(index->gpio, index->pin, GPIO_DIR_OUT); + GPIO_PullResistorConfig(index->gpio, index->pin, GPIO_PR_DISABLE); + break; + case PIN_MODE_OUTPUT_OD: + /* output setting: od. */ + GPIO_DirectionConfig(index->gpio, index->pin, GPIO_DIR_OUT); + GPIO_PullResistorConfig(index->gpio, index->pin, GPIO_PR_DISABLE); + break; + case PIN_MODE_INPUT: + /* input setting: not pull. */ + GPIO_DirectionConfig(index->gpio, index->pin, GPIO_DIR_IN); + GPIO_PullResistorConfig(index->gpio, index->pin, GPIO_PR_DISABLE); + GPIO_InputConfig(index->gpio, index->pin, ENABLE); + break; + case PIN_MODE_INPUT_PULLUP: + /* input setting: pull up. */ + GPIO_DirectionConfig(index->gpio, index->pin, GPIO_DIR_IN); + GPIO_PullResistorConfig(index->gpio, index->pin, GPIO_PR_UP); + GPIO_InputConfig(index->gpio, index->pin, ENABLE); + break; + case PIN_MODE_INPUT_PULLDOWN: + /* input setting: pull down. */ + GPIO_DirectionConfig(index->gpio, index->pin, GPIO_DIR_IN); + GPIO_PullResistorConfig(index->gpio, index->pin, GPIO_PR_DOWN); + GPIO_InputConfig(index->gpio, index->pin, ENABLE); + break; + default: + break; + } +} + +static void ht32_pin_write(rt_device_t dev, rt_base_t pin, rt_uint8_t value) +{ + const struct pin_index *index; + + index = get_pin(pin); + if (index == RT_NULL) + { + return; + } + if (value == PIN_LOW) + { + GPIO_ClearOutBits(index->gpio, index->pin); + } + else + { + GPIO_SetOutBits(index->gpio, index->pin); + } +} + +static rt_ssize_t ht32_pin_read(rt_device_t dev, rt_base_t pin) +{ + int value; + const struct pin_index *index; + value = PIN_LOW; + + index = get_pin(pin); + if (index == RT_NULL) + { + return value; + } + value = GPIO_ReadInBit(index->gpio, index->pin); + return value; +} + +rt_inline rt_int32_t bit2bitno(rt_uint32_t bit) +{ + rt_uint8_t i; + for (i = 0; i < 32; i++) + { + if ((0x01 << i) == bit) + { + return i; + } + } + return -1; +} + +rt_inline const struct pin_irq_map *get_pin_irq_map(rt_uint32_t pinbit) +{ + rt_int32_t mapindex = bit2bitno(pinbit); + if (mapindex < 0 || mapindex >= ITEM_NUM(pin_irq_map)) + { + return RT_NULL; + } + return &pin_irq_map[mapindex]; +} + +static rt_err_t ht32_pin_attach_irq(struct rt_device *device, + rt_base_t pin, + rt_uint8_t mode, + void (*hdr)(void *args), + void *args) +{ + const struct pin_index *index; + rt_base_t level; + rt_int32_t hdr_index = -1; + + index = get_pin(pin); + if (index == RT_NULL) + { + return RT_ERROR; + } + + hdr_index = bit2bitno(index->pin); + + if (hdr_index < 0 || hdr_index >= ITEM_NUM(pin_irq_map)) + { + return RT_ERROR; + } + + level = rt_hw_interrupt_disable(); + if (pin_irq_hdr_tab[hdr_index].pin == pin && + pin_irq_hdr_tab[hdr_index].hdr == hdr && + pin_irq_hdr_tab[hdr_index].mode == mode && + pin_irq_hdr_tab[hdr_index].args == args) + { + rt_hw_interrupt_enable(level); + return RT_EOK; + } + if (pin_irq_hdr_tab[hdr_index].pin != -1) + { + rt_hw_interrupt_enable(level); + return RT_ERROR; + } + pin_irq_hdr_tab[hdr_index].pin = pin; + pin_irq_hdr_tab[hdr_index].hdr = hdr; + pin_irq_hdr_tab[hdr_index].mode = mode; + pin_irq_hdr_tab[hdr_index].args = args; + rt_hw_interrupt_enable(level); + + return RT_EOK; +} + +static rt_err_t ht32_pin_detach_irq(struct rt_device *device, rt_base_t pin) +{ + const struct pin_index *index; + rt_base_t level; + rt_int32_t hdr_index = -1; + + index = get_pin(pin); + if (index == RT_NULL) + { + return RT_ERROR; + } + + hdr_index = bit2bitno(index->pin); + if (hdr_index < 0 || hdr_index >= ITEM_NUM(pin_irq_map)) + { + return RT_ERROR; + } + + level = rt_hw_interrupt_disable(); + if (pin_irq_hdr_tab[hdr_index].pin == -1) + { + rt_hw_interrupt_enable(level); + return RT_EOK; + } + pin_irq_hdr_tab[hdr_index].pin = -1; + pin_irq_hdr_tab[hdr_index].hdr = RT_NULL; + pin_irq_hdr_tab[hdr_index].mode = 0; + pin_irq_hdr_tab[hdr_index].args = RT_NULL; + rt_hw_interrupt_enable(level); + + return RT_EOK; +} + +static rt_err_t ht32_pin_irq_enable(struct rt_device *device, rt_base_t pin, rt_uint8_t enabled) +{ + const struct pin_index *index; + const struct pin_irq_map *irqmap; + rt_base_t level; + rt_int32_t hdr_index = -1; + EXTI_InitTypeDef EXTI_InitStruct; + + index = get_pin(pin); + if (index == RT_NULL) + { + return RT_ERROR; + } + if (enabled == PIN_IRQ_ENABLE) + { + hdr_index = bit2bitno(index->pin); + if (hdr_index < 0 || hdr_index >= ITEM_NUM(pin_irq_map)) + { + return RT_ERROR; + } + + level = rt_hw_interrupt_disable(); + + if (pin_irq_hdr_tab[hdr_index].pin == -1) + { + rt_hw_interrupt_enable(level); + return RT_ERROR; + } + + irqmap = &pin_irq_map[hdr_index]; + + CKCU_PeripClockConfig_TypeDef CKCUClock = {{0}}; + CKCUClock.Bit.AFIO = 1; + CKCUClock.Bit.EXTI = 1; + + if ((index->gpio) == HT_GPIOA) + CKCUClock.Bit.PA = 1; + else if ((index->gpio) == HT_GPIOB) + CKCUClock.Bit.PB = 1; +#if defined(HT_GPIOC) + else if ((index->gpio) == HT_GPIOC) + CKCUClock.Bit.PC = 1; +#endif +#if defined(HT_GPIOD) + else if ((index->gpio) == HT_GPIOD) + CKCUClock.Bit.PD = 1; +#endif +#if defined(HT_GPIOE) + else if ((index->gpio) == HT_GPIOE) + CKCUClock.Bit.PE = 1; +#endif +#if defined(HT_GPIOF) + else if ((index->gpio) == HT_GPIOF) + CKCUClock.Bit.PF = 1; +#endif + + CKCU_PeripClockConfig(CKCUClock, ENABLE); + + if ((index->gpio) == HT_GPIOA) + { + AFIO_GPxConfig(GPIO_PA, index->pin, AFIO_MODE_1); + GPIO_InputConfig(HT_GPIOA, index->pin, ENABLE); + AFIO_EXTISourceConfig(hdr_index, AFIO_ESS_PA); + } + else if ((index->gpio) == HT_GPIOB) + { + AFIO_GPxConfig(GPIO_PB, index->pin, AFIO_MODE_1); + GPIO_InputConfig(HT_GPIOB, index->pin, ENABLE); + AFIO_EXTISourceConfig(hdr_index, AFIO_ESS_PB); + } +#if defined(HT_GPIOC) + else if ((index->gpio) == HT_GPIOC) + { + AFIO_GPxConfig(GPIO_PC, index->pin, AFIO_MODE_1); + GPIO_InputConfig(HT_GPIOC, index->pin, ENABLE); + AFIO_EXTISourceConfig(hdr_index, AFIO_ESS_PC); + } +#endif +#if defined(HT_GPIOD) + else if ((index->gpio) == HT_GPIOD) + { + AFIO_GPxConfig(GPIO_PD, index->pin, AFIO_MODE_1); + GPIO_InputConfig(HT_GPIOD, index->pin, ENABLE); + AFIO_EXTISourceConfig(hdr_index, AFIO_ESS_PD); + } +#endif +#if defined(HT_GPIOE) + else if ((index->gpio) == HT_GPIOE) + { + AFIO_GPxConfig(GPIO_PE, index->pin, AFIO_MODE_1); + GPIO_InputConfig(HT_GPIOE, index->pin, ENABLE); + AFIO_EXTISourceConfig(hdr_index, AFIO_ESS_PE); + } +#endif +#if defined(HT_GPIOF) + else if ((index->gpio) == HT_GPIOF) + { + AFIO_GPxConfig(GPIO_PF, index->pin, AFIO_MODE_1); + GPIO_InputConfig(HT_GPIOF, index->pin, ENABLE); + AFIO_EXTISourceConfig(hdr_index, AFIO_ESS_PF); + } +#endif + + switch (pin_irq_hdr_tab[hdr_index].mode) + { + case PIN_IRQ_MODE_RISING: + GPIO_PullResistorConfig(index->gpio, index->pin, GPIO_PR_DOWN); + EXTI_InitStruct.EXTI_IntType = EXTI_POSITIVE_EDGE; + break; + case PIN_IRQ_MODE_FALLING: + GPIO_PullResistorConfig(index->gpio, index->pin, GPIO_PR_UP); + EXTI_InitStruct.EXTI_IntType = EXTI_NEGATIVE_EDGE; + break; + case PIN_IRQ_MODE_RISING_FALLING: + GPIO_PullResistorConfig(index->gpio, index->pin, GPIO_PR_DISABLE); + EXTI_InitStruct.EXTI_IntType = EXTI_BOTH_EDGE; + break; + case PIN_IRQ_MODE_HIGH_LEVEL: + GPIO_PullResistorConfig(index->gpio, index->pin, GPIO_PR_DOWN); + EXTI_InitStruct.EXTI_IntType = EXTI_HIGH_LEVEL; + break; + case PIN_IRQ_MODE_LOW_LEVEL: + GPIO_PullResistorConfig(index->gpio, index->pin, GPIO_PR_UP); + EXTI_InitStruct.EXTI_IntType = EXTI_LOW_LEVEL; + break; + default: + rt_hw_interrupt_enable(level); + return RT_ERROR; + } + + EXTI_InitStruct.EXTI_Channel = hdr_index; + + EXTI_InitStruct.EXTI_Debounce = EXTI_DEBOUNCE_DISABLE; + EXTI_InitStruct.EXTI_DebounceCnt = 0; + EXTI_Init(&EXTI_InitStruct); + + EXTI_IntConfig(hdr_index, ENABLE); + + NVIC_EnableIRQ((irqmap->irqno)); + rt_hw_interrupt_enable(level); + } + + else if (enabled == PIN_IRQ_DISABLE) + { + irqmap = get_pin_irq_map(index->pin); + if (irqmap == RT_NULL) + { + return RT_ERROR; + } + if ((irqmap->irqno) == EXTI0_IRQn) + EXTI_IntConfig(EXTI_CHANNEL_0, DISABLE); + else if ((irqmap->irqno) == EXTI1_IRQn) + EXTI_IntConfig(EXTI_CHANNEL_1, DISABLE); + else if ((irqmap->irqno) == EXTI2_IRQn) + EXTI_IntConfig(EXTI_CHANNEL_2, DISABLE); + else if ((irqmap->irqno) == EXTI3_IRQn) + EXTI_IntConfig(EXTI_CHANNEL_3, DISABLE); + else if ((irqmap->irqno) == EXTI4_IRQn) + EXTI_IntConfig(EXTI_CHANNEL_4, DISABLE); + else if ((irqmap->irqno) == EXTI5_IRQn) + EXTI_IntConfig(EXTI_CHANNEL_5, DISABLE); + else if ((irqmap->irqno) == EXTI6_IRQn) + EXTI_IntConfig(EXTI_CHANNEL_6, DISABLE); + else if ((irqmap->irqno) == EXTI7_IRQn) + EXTI_IntConfig(EXTI_CHANNEL_7, DISABLE); + else if ((irqmap->irqno) == EXTI8_IRQn) + EXTI_IntConfig(EXTI_CHANNEL_8, DISABLE); + else if ((irqmap->irqno) == EXTI9_IRQn) + EXTI_IntConfig(EXTI_CHANNEL_9, DISABLE); + else if ((irqmap->irqno) == EXTI10_IRQn) + EXTI_IntConfig(EXTI_CHANNEL_10, DISABLE); + else if ((irqmap->irqno) == EXTI11_IRQn) + EXTI_IntConfig(EXTI_CHANNEL_11, DISABLE); + else if ((irqmap->irqno) == EXTI12_IRQn) + EXTI_IntConfig(EXTI_CHANNEL_12, DISABLE); + else if ((irqmap->irqno) == EXTI13_IRQn) + EXTI_IntConfig(EXTI_CHANNEL_13, DISABLE); + else if ((irqmap->irqno) == EXTI14_IRQn) + EXTI_IntConfig(EXTI_CHANNEL_14, DISABLE); + else if ((irqmap->irqno) == EXTI15_IRQn) + EXTI_IntConfig(EXTI_CHANNEL_15, DISABLE); + } + else + { + return RT_ERROR; + } + return RT_EOK; +} + +const static struct rt_pin_ops _ht32_pin_ops = +{ + .pin_mode = ht32_pin_mode, + .pin_write = ht32_pin_write, + .pin_read = ht32_pin_read, + .pin_attach_irq = ht32_pin_attach_irq, + .pin_detach_irq = ht32_pin_detach_irq, + .pin_irq_enable = ht32_pin_irq_enable, + .pin_get = NULL, +}; + +int rt_hw_pin_init(void) +{ + int result; + + result = rt_device_pin_register("pin", &_ht32_pin_ops, RT_NULL); + + return result; +} +INIT_BOARD_EXPORT(rt_hw_pin_init); + +rt_inline void pin_irq_hdr(int irqno) +{ + if (pin_irq_hdr_tab[irqno].hdr) + { + pin_irq_hdr_tab[irqno].hdr(pin_irq_hdr_tab[irqno].args); + } +} +#ifdef SOC_SERIES_HT32F5 +void EXTI0_1_IRQHandler(void) +{ + rt_interrupt_enter(); + if (EXTI_GetEdgeStatus(EXTI_CHANNEL_0, EXTI_EDGE_POSITIVE)) + { + EXTI_ClearEdgeFlag(EXTI_CHANNEL_0); + pin_irq_hdr(0); + } + else if (EXTI_GetEdgeStatus(EXTI_CHANNEL_1, EXTI_EDGE_POSITIVE)) + { + EXTI_ClearEdgeFlag(EXTI_CHANNEL_1); + pin_irq_hdr(1); + } + rt_interrupt_leave(); +} + +void EXTI2_3_IRQHandler(void) +{ + rt_interrupt_enter(); + if (EXTI_GetEdgeStatus(EXTI_CHANNEL_2, EXTI_EDGE_POSITIVE)) + { + EXTI_ClearEdgeFlag(EXTI_CHANNEL_2); + pin_irq_hdr(2); + } + else if (EXTI_GetEdgeStatus(EXTI_CHANNEL_3, EXTI_EDGE_POSITIVE)) + { + EXTI_ClearEdgeFlag(EXTI_CHANNEL_3); + pin_irq_hdr(3); + } + rt_interrupt_leave(); +} + +void EXTI4_15_IRQHandler(void) +{ + rt_interrupt_enter(); + if (EXTI_GetEdgeStatus(EXTI_CHANNEL_4, EXTI_EDGE_POSITIVE)) + { + EXTI_ClearEdgeFlag(EXTI_CHANNEL_4); + pin_irq_hdr(4); + } + else if (EXTI_GetEdgeStatus(EXTI_CHANNEL_5, EXTI_EDGE_POSITIVE)) + { + EXTI_ClearEdgeFlag(EXTI_CHANNEL_5); + pin_irq_hdr(5); + } + else if (EXTI_GetEdgeStatus(EXTI_CHANNEL_6, EXTI_EDGE_POSITIVE)) + { + EXTI_ClearEdgeFlag(EXTI_CHANNEL_6); + pin_irq_hdr(6); + } + else if (EXTI_GetEdgeStatus(EXTI_CHANNEL_7, EXTI_EDGE_POSITIVE)) + { + EXTI_ClearEdgeFlag(EXTI_CHANNEL_7); + pin_irq_hdr(7); + } + else if (EXTI_GetEdgeStatus(EXTI_CHANNEL_8, EXTI_EDGE_POSITIVE)) + { + EXTI_ClearEdgeFlag(EXTI_CHANNEL_8); + pin_irq_hdr(8); + } + else if (EXTI_GetEdgeStatus(EXTI_CHANNEL_9, EXTI_EDGE_POSITIVE)) + { + EXTI_ClearEdgeFlag(EXTI_CHANNEL_9); + pin_irq_hdr(9); + } + else if (EXTI_GetEdgeStatus(EXTI_CHANNEL_10, EXTI_EDGE_POSITIVE)) + { + EXTI_ClearEdgeFlag(EXTI_CHANNEL_10); + pin_irq_hdr(10); + } + else if (EXTI_GetEdgeStatus(EXTI_CHANNEL_11, EXTI_EDGE_POSITIVE)) + { + EXTI_ClearEdgeFlag(EXTI_CHANNEL_11); + pin_irq_hdr(11); + } + else if (EXTI_GetEdgeStatus(EXTI_CHANNEL_12, EXTI_EDGE_POSITIVE)) + { + EXTI_ClearEdgeFlag(EXTI_CHANNEL_12); + pin_irq_hdr(12); + } + else if (EXTI_GetEdgeStatus(EXTI_CHANNEL_13, EXTI_EDGE_POSITIVE)) + { + EXTI_ClearEdgeFlag(EXTI_CHANNEL_13); + pin_irq_hdr(13); + } + else if (EXTI_GetEdgeStatus(EXTI_CHANNEL_14, EXTI_EDGE_POSITIVE)) + { + EXTI_ClearEdgeFlag(EXTI_CHANNEL_14); + pin_irq_hdr(14); + } + else if (EXTI_GetEdgeStatus(EXTI_CHANNEL_15, EXTI_EDGE_POSITIVE)) + { + EXTI_ClearEdgeFlag(EXTI_CHANNEL_15); + pin_irq_hdr(15); + } + rt_interrupt_leave(); +} +#endif + +#ifdef SOC_SERIES_HT32F1 +void EXTI0_IRQHandler(void) +{ + rt_interrupt_enter(); + if (EXTI_GetEdgeStatus(EXTI_CHANNEL_0, EXTI_EDGE_POSITIVE)) + { + EXTI_ClearEdgeFlag(EXTI_CHANNEL_0); + pin_irq_hdr(0); + } + rt_interrupt_leave(); +} +void EXTI1_IRQHandler(void) +{ + rt_interrupt_enter(); + if (EXTI_GetEdgeStatus(EXTI_CHANNEL_1, EXTI_EDGE_POSITIVE)) + { + EXTI_ClearEdgeFlag(EXTI_CHANNEL_1); + pin_irq_hdr(1); + } + rt_interrupt_leave(); +} +void EXTI2_IRQHandler(void) +{ + rt_interrupt_enter(); + if (EXTI_GetEdgeStatus(EXTI_CHANNEL_2, EXTI_EDGE_POSITIVE)) + { + EXTI_ClearEdgeFlag(EXTI_CHANNEL_2); + pin_irq_hdr(2); + } + rt_interrupt_leave(); +} +void EXTI3_IRQHandler(void) +{ + rt_interrupt_enter(); + if (EXTI_GetEdgeStatus(EXTI_CHANNEL_3, EXTI_EDGE_POSITIVE)) + { + EXTI_ClearEdgeFlag(EXTI_CHANNEL_3); + pin_irq_hdr(3); + } + rt_interrupt_leave(); +} +void EXTI4_IRQHandler(void) +{ + rt_interrupt_enter(); + if (EXTI_GetEdgeStatus(EXTI_CHANNEL_4, EXTI_EDGE_POSITIVE)) + { + EXTI_ClearEdgeFlag(EXTI_CHANNEL_4); + pin_irq_hdr(4); + } + rt_interrupt_leave(); +} +void EXTI5_IRQHandler(void) +{ + rt_interrupt_enter(); + if (EXTI_GetEdgeStatus(EXTI_CHANNEL_5, EXTI_EDGE_POSITIVE)) + { + EXTI_ClearEdgeFlag(EXTI_CHANNEL_5); + pin_irq_hdr(5); + } + rt_interrupt_leave(); +} +void EXTI6_IRQHandler(void) +{ + rt_interrupt_enter(); + if (EXTI_GetEdgeStatus(EXTI_CHANNEL_6, EXTI_EDGE_POSITIVE)) + { + EXTI_ClearEdgeFlag(EXTI_CHANNEL_6); + pin_irq_hdr(6); + } + rt_interrupt_leave(); +} +void EXTI7_IRQHandler(void) +{ + rt_interrupt_enter(); + if (EXTI_GetEdgeStatus(EXTI_CHANNEL_7, EXTI_EDGE_POSITIVE)) + { + EXTI_ClearEdgeFlag(EXTI_CHANNEL_7); + pin_irq_hdr(7); + } + rt_interrupt_leave(); +} +void EXTI8_IRQHandler(void) +{ + rt_interrupt_enter(); + if (EXTI_GetEdgeStatus(EXTI_CHANNEL_8, EXTI_EDGE_POSITIVE)) + { + EXTI_ClearEdgeFlag(EXTI_CHANNEL_8); + pin_irq_hdr(8); + } + rt_interrupt_leave(); +} +void EXTI9_IRQHandler(void) +{ + rt_interrupt_enter(); + if (EXTI_GetEdgeStatus(EXTI_CHANNEL_9, EXTI_EDGE_POSITIVE)) + { + EXTI_ClearEdgeFlag(EXTI_CHANNEL_9); + pin_irq_hdr(9); + } + rt_interrupt_leave(); +} +void EXTI10_IRQHandler(void) +{ + rt_interrupt_enter(); + if (EXTI_GetEdgeStatus(EXTI_CHANNEL_10, EXTI_EDGE_POSITIVE)) + { + EXTI_ClearEdgeFlag(EXTI_CHANNEL_10); + pin_irq_hdr(10); + } + rt_interrupt_leave(); +} +void EXTI11_IRQHandler(void) +{ + rt_interrupt_enter(); + if (EXTI_GetEdgeStatus(EXTI_CHANNEL_11, EXTI_EDGE_POSITIVE)) + { + EXTI_ClearEdgeFlag(EXTI_CHANNEL_11); + pin_irq_hdr(11); + } + rt_interrupt_leave(); +} +void EXTI12_IRQHandler(void) +{ + rt_interrupt_enter(); + if (EXTI_GetEdgeStatus(EXTI_CHANNEL_12, EXTI_EDGE_POSITIVE)) + { + EXTI_ClearEdgeFlag(EXTI_CHANNEL_12); + pin_irq_hdr(12); + } + rt_interrupt_leave(); +} +void EXTI13_IRQHandler(void) +{ + rt_interrupt_enter(); + if (EXTI_GetEdgeStatus(EXTI_CHANNEL_13, EXTI_EDGE_POSITIVE)) + { + EXTI_ClearEdgeFlag(EXTI_CHANNEL_13); + pin_irq_hdr(13); + } + rt_interrupt_leave(); +} +void EXTI14_IRQHandler(void) +{ + rt_interrupt_enter(); + if (EXTI_GetEdgeStatus(EXTI_CHANNEL_14, EXTI_EDGE_POSITIVE)) + { + EXTI_ClearEdgeFlag(EXTI_CHANNEL_14); + pin_irq_hdr(14); + } + rt_interrupt_leave(); +} +void EXTI15_IRQHandler(void) +{ + rt_interrupt_enter(); + if (EXTI_GetEdgeStatus(EXTI_CHANNEL_15, EXTI_EDGE_POSITIVE)) + { + EXTI_ClearEdgeFlag(EXTI_CHANNEL_15); + pin_irq_hdr(15); + } + rt_interrupt_leave(); +} +#endif + +#endif diff --git a/bsp/ht32/libraries/ht32_drivers/drv_gpio.h b/bsp/ht32/libraries/ht32_drivers/drv_gpio.h new file mode 100644 index 0000000000..01ec12fc24 --- /dev/null +++ b/bsp/ht32/libraries/ht32_drivers/drv_gpio.h @@ -0,0 +1,30 @@ +/* + * Copyright (c) 2006-2024, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2024-04-08 QT-one first version + */ + +#ifndef __DRV_GPIO_H__ +#define __DRV_GPIO_H__ + +#include +#include +#include "drv_common.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#define __HT32_PORT(port) HT_GPIO##port##_BASE + +#define GET_PIN(PORTx,PIN) (rt_base_t)((16 * ( ((rt_base_t)__HT32_PORT(PORTx) - (rt_base_t)HT_GPIOA_BASE)/(0x2000UL) )) + PIN) + +#ifdef __cplusplus +} +#endif + +#endif /* __DRV_GPIO_H__ */ diff --git a/bsp/ht32/libraries/ht32_drivers/drv_i2c.c b/bsp/ht32/libraries/ht32_drivers/drv_i2c.c new file mode 100644 index 0000000000..edf98127c5 --- /dev/null +++ b/bsp/ht32/libraries/ht32_drivers/drv_i2c.c @@ -0,0 +1,208 @@ +/* + * Copyright (c) 2006-2024, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2024-04-08 QT-one first version + */ + +#include "drv_i2c.h" + +#ifdef RT_USING_I2C +#if !defined(BSP_USING_I2C0) && !defined(BSP_USING_I2C1) + #error "Please define at least one BSP_USING_I2Cx" + /* this driver can be disabled at menuconfig RT-Thread Components Device Drivers */ +#endif + +struct ht32_i2c_config +{ + HT_I2C_TypeDef *i2c_x; + const char *i2c_name; + IRQn_Type irq; +}; + +struct ht32_i2c +{ + struct ht32_i2c_config *config; + struct rt_i2c_bus_device i2c_bus; +}; + +enum +{ +#ifdef BSP_USING_I2C0 + I2C0_INDEX, +#endif +#ifdef BSP_USING_I2C1 + I2C1_INDEX, +#endif +}; + +static struct ht32_i2c_config i2c_config[] = +{ +#ifdef BSP_USING_I2C0 + {HT_I2C0, "i2c0", I2C0_IRQn}, +#endif +#ifdef BSP_USING_I2C1 + {HT_I2C1, "i2c1", I2C1_IRQn}, +#endif +}; + +static struct ht32_i2c i2cs[sizeof(i2c_config) / sizeof(i2c_config[0])] = {0}; + +static rt_size_t ht32_i2c_init(struct ht32_i2c *i2c_drv) +{ + struct ht32_i2c_config *i2c_config = i2c_drv->config; + + CKCU_PeripClockConfig_TypeDef CKCUClock = {{0}}; +#ifdef BSP_USING_I2C0 + if (HT_I2C0 == i2c_config->i2c_x) + { + CKCUClock.Bit.I2C0 = 1; + } +#endif +#ifdef BSP_USING_I2C1 + if (HT_I2C1 == i2c_config->i2c_x) + { + CKCUClock.Bit.I2C1 = 1; + } +#endif + CKCUClock.Bit.AFIO = 1; + CKCU_PeripClockConfig(CKCUClock, ENABLE); + + ht32_i2c_gpio_init(i2c_config->i2c_x); + + I2C_InitTypeDef I2C_InitStructure; + I2C_InitStructure.I2C_GeneralCall = DISABLE; + I2C_InitStructure.I2C_AddressingMode = I2C_ADDRESSING_7BIT; + I2C_InitStructure.I2C_Acknowledge = DISABLE; + I2C_InitStructure.I2C_OwnAddress = 0x00; + I2C_InitStructure.I2C_Speed = 400000; + I2C_InitStructure.I2C_SpeedOffset = 0; + + I2C_Init(i2c_config->i2c_x, &I2C_InitStructure); + I2C_Cmd(i2c_config->i2c_x, ENABLE); + + return RT_EOK; +} + +static int ht32_i2c_read(struct ht32_i2c_config *hi2c, + rt_uint16_t slave_address, + rt_uint8_t *p_buffer, + rt_uint16_t data_byte) +{ + uint16_t date_num = 0; + uint8_t data = 0xFF; + + I2C_TargetAddressConfig(hi2c->i2c_x, slave_address, I2C_MASTER_READ); + while (!I2C_CheckStatus(hi2c->i2c_x, I2C_MASTER_SEND_START)); + while (!I2C_CheckStatus(hi2c->i2c_x, I2C_MASTER_RECEIVER_MODE)); + I2C_AckCmd(hi2c->i2c_x, ENABLE); + while (date_num < data_byte) + { + date_num++; + + while (!I2C_CheckStatus(hi2c->i2c_x, I2C_MASTER_RX_NOT_EMPTY)); + data = I2C_ReceiveData(hi2c->i2c_x); + + if (date_num == (data_byte - 1)) + { + I2C_AckCmd(hi2c->i2c_x, DISABLE); + } + if (p_buffer != RT_NULL) + { + *p_buffer++ = data; + } + } + I2C_GenerateSTOP(hi2c->i2c_x); + while (I2C_ReadRegister(hi2c->i2c_x, I2C_REGISTER_SR) & 0x80000); + + return 0; +} + +static int ht32_i2c_write(struct ht32_i2c_config *hi2c, + uint16_t slave_address, + uint8_t *p_buffer, + uint16_t data_byte) +{ + uint16_t date_num = data_byte; + + I2C_TargetAddressConfig(hi2c->i2c_x, slave_address, I2C_MASTER_WRITE); + + while (!I2C_CheckStatus(hi2c->i2c_x, I2C_MASTER_SEND_START)); + + while (!I2C_CheckStatus(hi2c->i2c_x, I2C_MASTER_TRANSMITTER_MODE)); + while (date_num--) + { + while (!I2C_CheckStatus(hi2c->i2c_x, I2C_MASTER_TX_EMPTY)); + I2C_SendData(hi2c->i2c_x, *p_buffer++); + } + + while (!I2C_CheckStatus(hi2c->i2c_x, I2C_MASTER_TX_EMPTY)); + I2C_GenerateSTOP(hi2c->i2c_x); + while (I2C_ReadRegister(hi2c->i2c_x, I2C_REGISTER_SR) & 0x80000); + return 0; +} + +static rt_ssize_t ht32_master_xfer(struct rt_i2c_bus_device *bus, + struct rt_i2c_msg msgs[], + rt_uint32_t num) +{ + struct ht32_i2c *i2c_instance; + struct rt_i2c_msg *msg; + rt_uint32_t i; + + i2c_instance = rt_container_of(bus, struct ht32_i2c, i2c_bus); + RT_ASSERT(bus != RT_NULL); + RT_ASSERT(msgs != RT_NULL); + + for (i = 0; i < num; i++) + { + msg = &msgs[i]; + + if (msg->flags & RT_I2C_RD) + { + if (ht32_i2c_read(i2c_instance->config, msg->addr, msg->buf, msg->len) != 0) + { + return i; + } + } + else + { + if (ht32_i2c_write(i2c_instance->config, msg->addr, msg->buf, msg->len) != 0) + { + return i; + } + } + } + return i; +} + +static struct rt_i2c_bus_device_ops ht32_i2c_ops = +{ + .master_xfer = ht32_master_xfer, + .slave_xfer = RT_NULL, + .i2c_bus_control = RT_NULL +}; + +int rt_hw_i2c_init(void) +{ + int i; + rt_err_t result; + rt_size_t obj_num = sizeof(i2cs) / sizeof(struct ht32_i2c); + + for (i = 0; i < obj_num; i++) + { + i2cs[i].config = &i2c_config[i]; + i2cs[i].i2c_bus.parent.user_data = (void *)&i2cs[i]; + i2cs[i].i2c_bus.ops = &ht32_i2c_ops; + + ht32_i2c_init(&i2cs[i]); + result = rt_i2c_bus_device_register(&i2cs[i].i2c_bus, i2cs[i].config->i2c_name); + } + return result; +} +INIT_BOARD_EXPORT(rt_hw_i2c_init); + +#endif /* RT_USING_I2C */ diff --git a/bsp/ht32/libraries/ht32_drivers/drv_i2c.h b/bsp/ht32/libraries/ht32_drivers/drv_i2c.h new file mode 100644 index 0000000000..186aa12b53 --- /dev/null +++ b/bsp/ht32/libraries/ht32_drivers/drv_i2c.h @@ -0,0 +1,30 @@ +/* + * Copyright (c) 2006-2024, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2024-04-08 QT-one first version + */ + +#ifndef __DRV_I2C_H__ +#define __DRV_I2C_H__ + +#include +#include +#ifdef RT_USING_DEVICE + #include +#endif +#include "drv_common.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#ifdef __cplusplus +} +#endif + +#endif /* __DRV_I2C_H__ */ + diff --git a/bsp/ht32/libraries/ht32_drivers/drv_spi.c b/bsp/ht32/libraries/ht32_drivers/drv_spi.c new file mode 100644 index 0000000000..c01867c909 --- /dev/null +++ b/bsp/ht32/libraries/ht32_drivers/drv_spi.c @@ -0,0 +1,352 @@ +/* + * Copyright (c) 2006-2024, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2024-04-08 QT-one first version + */ + +#include +#include "drv_spi.h" + +#ifdef RT_USING_SPI +#if !defined(BSP_USING_SPI0) && !defined(BSP_USING_SPI1) + #error "Please define at least one BSP_USING_SPIx" +#endif + +struct ht32_spi_config +{ + HT_SPI_TypeDef *spi_x; + const char *spi_name; + IRQn_Type irq; +}; + +struct ht32_spi +{ + struct ht32_spi_config *config; + struct rt_spi_bus spi_bus; +}; + +struct ht32_spi_cs +{ + HT_GPIO_TypeDef *gpio_x; + uint32_t gpio_pin; +}; + +enum +{ +#ifdef BSP_USING_SPI0 + SPI0_INDEX, +#endif +#ifdef BSP_USING_SPI1 + SPI1_INDEX, +#endif +}; + +static struct ht32_spi_config spi_config[] = +{ +#ifdef BSP_USING_SPI0 + {HT_SPI0, "spi0", SPI0_IRQn}, +#endif +#ifdef BSP_USING_SPI1 + {HT_SPI1, "spi1", SPI1_IRQn}, +#endif +}; + +static struct ht32_spi spis[sizeof(spi_config) / sizeof(spi_config[0])] = {0}; + +/* attach the spi device to spi bus, this function must be used after initialization */ +rt_err_t rt_hw_spi_device_attach(const char *bus_name, const char *device_name, HT_GPIO_TypeDef *cs_gpiox, uint16_t cs_gpio_pin) +{ + CKCU_PeripClockConfig_TypeDef CKCUClock = {{0}}; + + RT_ASSERT(bus_name != RT_NULL); + RT_ASSERT(device_name != RT_NULL); + + rt_err_t result; + struct rt_spi_device *spi_device; + struct ht32_spi_cs *cs_pin; + + if ((cs_gpiox) == HT_GPIOA) + { + CKCUClock.Bit.PA = 1; + CKCU_PeripClockConfig(CKCUClock, ENABLE); + AFIO_GPxConfig(GPIO_PA, cs_gpio_pin, AFIO_FUN_GPIO); + } + else if ((cs_gpiox) == HT_GPIOB) + { + CKCUClock.Bit.PB = 1; + CKCU_PeripClockConfig(CKCUClock, ENABLE); + AFIO_GPxConfig(GPIO_PB, cs_gpio_pin, AFIO_FUN_GPIO); + } +#if defined(HT_GPIOC) + else if ((cs_gpiox) == HT_GPIOC) + { + CKCUClock.Bit.PC = 1; + CKCU_PeripClockConfig(CKCUClock, ENABLE); + AFIO_GPxConfig(GPIO_PC, cs_gpio_pin, AFIO_FUN_GPIO); + } +#endif +#if defined(HT_GPIOD) + else if ((cs_gpiox) == HT_GPIOD) + { + CKCUClock.Bit.PD = 1; + CKCU_PeripClockConfig(CKCUClock, ENABLE); + AFIO_GPxConfig(GPIO_PD, cs_gpio_pin, AFIO_FUN_GPIO); + } +#endif +#if defined(HT_GPIOE) + else if ((cs_gpiox) == HT_GPIOE) + { + CKCUClock.Bit.PE = 1; + CKCU_PeripClockConfig(CKCUClock, ENABLE); + AFIO_GPxConfig(GPIO_PE, cs_gpio_pin, AFIO_FUN_GPIO); + } +#endif +#if defined(HT_GPIOF) + else if ((cs_gpiox) == HT_GPIOF) + { + CKCUClock.Bit.PF = 1; + CKCU_PeripClockConfig(CKCUClock, ENABLE); + AFIO_GPxConfig(GPIO_PF, cs_gpio_pin, AFIO_FUN_GPIO); + } +#endif + GPIO_PullResistorConfig(cs_gpiox, cs_gpio_pin, GPIO_PR_DISABLE); + GPIO_WriteOutBits(cs_gpiox, cs_gpio_pin, SET); + GPIO_DirectionConfig(cs_gpiox, cs_gpio_pin, GPIO_DIR_OUT); + + /* attach the device to spi bus */ + spi_device = (struct rt_spi_device *)rt_malloc(sizeof(struct rt_spi_device)); + RT_ASSERT(spi_device != RT_NULL); + cs_pin = (struct ht32_spi_cs *)rt_malloc(sizeof(struct ht32_spi_cs)); + RT_ASSERT(cs_pin != RT_NULL); + cs_pin->gpio_x = cs_gpiox; + cs_pin->gpio_pin = cs_gpio_pin; + result = rt_spi_bus_attach_device(spi_device, device_name, bus_name, (void *)cs_pin); + + if (result != RT_EOK) + { + LOG_D("%s attach to %s faild, %d\n", device_name, bus_name, result); + } + + RT_ASSERT(result == RT_EOK); + + LOG_D("%s attach to %s done", device_name, bus_name); + + return result; +} + +static rt_err_t ht32_configure(struct rt_spi_device *device, struct rt_spi_configuration *configuration) +{ + struct rt_spi_bus *spi_bus = (struct rt_spi_bus *)device->bus; + struct ht32_spi *spi_instance = (struct ht32_spi *)spi_bus->parent.user_data; + + SPI_InitTypeDef SPI_InitStructure; + CKCU_PeripClockConfig_TypeDef CKCUClock = {{0}}; + + RT_ASSERT(device != RT_NULL); + RT_ASSERT(configuration != RT_NULL); +#ifdef BSP_USING_SPI0 + if (HT_SPI0 == spi_instance->config->spi_x) + { + CKCUClock.Bit.SPI0 = 1; + } +#endif +#ifdef BSP_USING_SPI1 + if (HT_SPI1 == spi_instance->config->spi_x) + { + CKCUClock.Bit.SPI1 = 1; + } +#endif + CKCUClock.Bit.AFIO = 1; + CKCU_PeripClockConfig(CKCUClock, ENABLE); + + ht32_spi_gpio_init(spi_instance->config->spi_x); + + /* data_width */ + if (configuration->data_width <= 8) + { + SPI_InitStructure.SPI_DataLength = SPI_DATALENGTH_8; + } + else if (configuration->data_width <= 16) + { + SPI_InitStructure.SPI_DataLength = SPI_DATALENGTH_16; + } + else + { + return RT_ERROR; + } + + /* Set the polarity and phase of the SPI */ + switch (configuration->mode & RT_SPI_MODE_3) + { + case RT_SPI_MODE_0: + SPI_InitStructure.SPI_CPOL = SPI_CPOL_LOW; + SPI_InitStructure.SPI_CPHA = SPI_CPHA_FIRST; + break; + case RT_SPI_MODE_1: + SPI_InitStructure.SPI_CPOL = SPI_CPOL_LOW; + SPI_InitStructure.SPI_CPHA = SPI_CPHA_SECOND; + break; + case RT_SPI_MODE_2: + SPI_InitStructure.SPI_CPOL = SPI_CPOL_HIGH; + SPI_InitStructure.SPI_CPHA = SPI_CPHA_FIRST; + break; + case RT_SPI_MODE_3: + SPI_InitStructure.SPI_CPOL = SPI_CPOL_HIGH; + SPI_InitStructure.SPI_CPHA = SPI_CPHA_SECOND; + break; + } + + /* Set the SPI as a master or slave */ + SPI_InitStructure.SPI_Mode = (configuration->mode & RT_SPI_SLAVE) ? (SPI_SLAVE) : (SPI_MASTER); + + /* Set the data high or low first */ + SPI_InitStructure.SPI_FirstBit = (configuration->mode & RT_SPI_MSB) ? (SPI_FIRSTBIT_MSB) : (SPI_FIRSTBIT_LSB); + + /* SEL uses software by default */ + SPI_InitStructure.SPI_SELMode = SPI_SEL_SOFTWARE; + + /* SEL effective level */ + SPI_InitStructure.SPI_SELPolarity = (configuration->mode & RT_SPI_CS_HIGH) ? (SPI_SELPOLARITY_HIGH) : (SPI_SELPOLARITY_LOW); + + /* Configure the SCK clock frequency of the SPI */ + if (configuration->max_hz < 0xFFFF) + { + SPI_InitStructure.SPI_ClockPrescaler = ((configuration->max_hz) & 0xFFFF); + } + else + { + return RT_ERROR; + } + + SPI_InitStructure.SPI_FIFO = SPI_FIFO_DISABLE; + SPI_InitStructure.SPI_RxFIFOTriggerLevel = 0; + SPI_InitStructure.SPI_TxFIFOTriggerLevel = 0; + SPI_Init(spi_instance->config->spi_x, &SPI_InitStructure); +#if (!LIBCFG_SPI_NO_MULTI_MASTER) + SPI_SELOutputCmd(spi_instance->config->spi_x, ENABLE); +#endif + + SPI_Cmd(spi_instance->config->spi_x, ENABLE); + return RT_EOK; +} + +static rt_ssize_t ht32_xfer(struct rt_spi_device *device, struct rt_spi_message *message) +{ + struct rt_spi_bus *ht32_spi_bus = (struct rt_spi_bus *)device->bus; + struct ht32_spi *spi_instance = (struct ht32_spi *)ht32_spi_bus->parent.user_data; + struct rt_spi_configuration *config = &device->config; + struct ht32_spi_cs *ht32_spi_cs = device->parent.user_data; + + RT_ASSERT(device != NULL); + RT_ASSERT(message != NULL); + + /* take cs */ + if (message->cs_take) + { + GPIO_ClearOutBits(ht32_spi_cs->gpio_x, ht32_spi_cs->gpio_pin); + LOG_D("spi take cs\n"); + } + + if (config->data_width <= 8) + { + const rt_uint8_t *send_ptr = message->send_buf; + rt_uint8_t *recv_ptr = message->recv_buf; + rt_uint32_t size = message->length; + + LOG_D("spi poll transfer start: %d\n", size); + + while (size--) + { + rt_uint8_t data = 0xFF; + + if (send_ptr != RT_NULL) + { + data = *send_ptr++; + } + + /* wait until the transmit buffer is empty */ + while (SPI_GetFlagStatus(spi_instance->config->spi_x, SPI_FLAG_TXE) == RESET); + /* send the byte */ + SPI_SendData(spi_instance->config->spi_x, data); + + /* wait until a data is received */ + while (SPI_GetFlagStatus(spi_instance->config->spi_x, SPI_INT_RXBNE) == RESET); + /* get the received data */ + data = SPI_ReceiveData(spi_instance->config->spi_x); + + if (recv_ptr != RT_NULL) + { + *recv_ptr++ = data; + } + } + LOG_D("spi poll transfer finsh\n"); + } + else if (config->data_width <= 16) + { + const rt_uint16_t *send_ptr = message->send_buf; + rt_uint16_t *recv_ptr = message->recv_buf; + rt_uint32_t size = message->length; + + while (size--) + { + rt_uint16_t data = 0xFF; + + if (send_ptr != RT_NULL) + { + data = *send_ptr++; + } + + /* wait until the transmit buffer is empty */ + while (SPI_GetFlagStatus(spi_instance->config->spi_x, SPI_FLAG_TXE) == RESET); + /* send the byte */ + SPI_SendData(spi_instance->config->spi_x, data); + + /* wait until a data is received */ + while (SPI_GetFlagStatus(spi_instance->config->spi_x, SPI_INT_RXBNE) == RESET); + /* get the received data */ + data = SPI_ReceiveData(spi_instance->config->spi_x); + + if (recv_ptr != RT_NULL) + { + *recv_ptr++ = data; + } + } + } + + /* release cs */ + if (message->cs_release) + { + GPIO_SetOutBits(ht32_spi_cs->gpio_x, ht32_spi_cs->gpio_pin); + LOG_D("spi release cs\n"); + } + + return message->length; +} + +static struct rt_spi_ops ht32_spi_ops = +{ + .configure = ht32_configure, + .xfer = ht32_xfer +}; + +int rt_hw_spi_init(void) +{ + int i; + rt_err_t result; + rt_size_t obj_num = sizeof(spis) / sizeof(struct ht32_spi); + + for (i = 0; i < obj_num; i++) + { + spis[i].config = &spi_config[i]; + spis[i].spi_bus.parent.user_data = (void *)&spis[i]; + result = rt_spi_bus_register(&spis[i].spi_bus, spis[i].config->spi_name, &ht32_spi_ops); + } + return result; +} +INIT_BOARD_EXPORT(rt_hw_spi_init); + +#endif /* RT_USING_SPI */ diff --git a/bsp/ht32/libraries/ht32_drivers/drv_spi.h b/bsp/ht32/libraries/ht32_drivers/drv_spi.h new file mode 100644 index 0000000000..65e63a5d3a --- /dev/null +++ b/bsp/ht32/libraries/ht32_drivers/drv_spi.h @@ -0,0 +1,29 @@ +/* + * Copyright (c) 2006-2024, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2024-04-08 QT-one first version + */ + +#ifndef __DRV_SPI_H__ +#define __DRV_SPI_H__ + +#include +#include +#include "drv_common.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* public function */ +rt_err_t rt_hw_spi_device_attach(const char *bus_name, const char *device_name, HT_GPIO_TypeDef *cs_gpiox, uint16_t cs_gpio_pin); + +#ifdef __cplusplus +} +#endif + +#endif /* __DRV_SPI_H__ */ diff --git a/bsp/ht32/libraries/ht32_drivers/drv_usart.c b/bsp/ht32/libraries/ht32_drivers/drv_usart.c new file mode 100644 index 0000000000..7e108e5f1a --- /dev/null +++ b/bsp/ht32/libraries/ht32_drivers/drv_usart.c @@ -0,0 +1,372 @@ +/* + * Copyright (c) 2006-2024, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2024-04-08 QT-one first version + */ + +#include "drv_usart.h" + +#ifdef RT_USING_SERIAL +#if !defined(BSP_USING_USART0) && !defined(BSP_USING_USART1) && \ + !defined(BSP_USING_UART0) && !defined(BSP_USING_UART1) && \ + !defined(BSP_USING_UART2) && !defined(BSP_USING_UART3) + #error "Please define at least one BSP_USING_UARTx" +#endif + +struct ht32_usart +{ + char *name; + HT_USART_TypeDef *usart_x; + IRQn_Type irq; + struct rt_serial_device serial; +}; + +enum +{ +#ifdef BSP_USING_USART0 + USART0_INDEX, +#endif +#ifdef BSP_USING_USART1 + USART1_INDEX, +#endif +#ifdef BSP_USING_UART0 + UART0_INDEX, +#endif +#ifdef BSP_USING_UART1 + UART1_INDEX, +#endif +#ifdef BSP_USING_UART2 + UART2_INDEX, +#endif +#ifdef BSP_USING_UART3 + UART3_INDEX, +#endif + +}; + +static struct ht32_usart usart_config[] = +{ +#ifdef BSP_USING_USART0 + { + "usart0", + HT_USART0, + USART0_IRQn, + RT_NULL + }, +#endif +#ifdef BSP_USING_USART1 + { + "usart1", + HT_USART1, + USART1_IRQn, + RT_NULL + }, +#endif +#ifdef BSP_USING_UART0 + { + "uart0", + HT_UART0, + UART0_IRQn, + RT_NULL + }, +#endif +#ifdef BSP_USING_UART1 + { + "uart1", + HT_UART1, + UART1_IRQn, + RT_NULL + }, +#endif +#ifdef BSP_USING_UART2 + { + "uart2", + HT_UART2, + UART0_UART2_IRQn, + RT_NULL + }, +#endif +#ifdef BSP_USING_UART3 + { + "uart3", + HT_UART3, + UART1_UART3_IRQn, + RT_NULL + }, +#endif +}; + +static rt_err_t ht32_configure(struct rt_serial_device *serial, struct serial_configure *cfg) +{ + + CKCU_PeripClockConfig_TypeDef CKCUClock = {{0}}; + USART_InitTypeDef USART_InitStructure = {0}; + + struct ht32_usart *usart_instance = (struct ht32_usart *)serial->parent.user_data; + + RT_ASSERT(serial != RT_NULL); + RT_ASSERT(cfg != RT_NULL); + + CKCUClock.Bit.AFIO = 1; + + if ((usart_instance->usart_x) == HT_UART0) + CKCUClock.Bit.UART0 = 1; +#if defined(HT_USART0) + else if ((usart_instance->usart_x) == HT_USART0) + CKCUClock.Bit.USART0 = 1; +#endif +#if defined(HT_USART1) + else if ((usart_instance->usart_x) == HT_USART1) + CKCUClock.Bit.USART1 = 1; +#endif +#if defined(HT_UART1) + else if ((usart_instance->usart_x) == HT_UART1) + CKCUClock.Bit.UART1 = 1; +#endif +#if defined(HT_UART2) + else if ((usart_instance->usart_x) == HT_UART2) + CKCUClock.Bit.UART2 = 1; +#endif +#if defined(HT_UART3) + else if ((usart_instance->usart_x) == HT_UART3) + CKCUClock.Bit.UART3 = 1; +#endif + CKCU_PeripClockConfig(CKCUClock, ENABLE); + + /* UART gpio init */ + ht32_usart_gpio_init((void *)usart_instance->usart_x); + + /* baud rate */ + USART_InitStructure.USART_BaudRate = (cfg->baud_rate); + + /* data width */ + switch (cfg->data_bits) + { + case DATA_BITS_7: + USART_InitStructure.USART_WordLength = USART_WORDLENGTH_7B; + break; + case DATA_BITS_8: + USART_InitStructure.USART_WordLength = USART_WORDLENGTH_8B; + break; + case DATA_BITS_9: + USART_InitStructure.USART_WordLength = USART_WORDLENGTH_9B; + break; + default: + USART_InitStructure.USART_WordLength = USART_WORDLENGTH_8B; + break; + } + + /* stop bit */ + switch (cfg->stop_bits) + { + case STOP_BITS_1: + USART_InitStructure.USART_StopBits = USART_STOPBITS_1; + break; + case STOP_BITS_2: + USART_InitStructure.USART_StopBits = USART_STOPBITS_2; + break; + default: + USART_InitStructure.USART_StopBits = USART_STOPBITS_1; + break; + } + + switch (cfg->parity) + { + case PARITY_NONE: + USART_InitStructure.USART_Parity = USART_PARITY_NO; + break; + case PARITY_ODD: + USART_InitStructure.USART_Parity = USART_PARITY_ODD; + break; + case PARITY_EVEN: + USART_InitStructure.USART_Parity = USART_PARITY_EVEN; + break; + default: + USART_InitStructure.USART_Parity = USART_PARITY_NO; + break; + } + + /* UART mode */ + USART_InitStructure.USART_Mode = USART_MODE_NORMAL; + /* UART init */ + USART_Init((usart_instance->usart_x), &USART_InitStructure); + /*UART enable */ + USART_TxCmd((usart_instance->usart_x), ENABLE); + USART_RxCmd((usart_instance->usart_x), ENABLE); + + return RT_EOK; +} + +static rt_err_t ht32_control(struct rt_serial_device *serial, int cmd, void *arg) +{ + struct ht32_usart *usart; + + RT_ASSERT(serial != RT_NULL); + usart = (struct ht32_usart *) serial->parent.user_data; + RT_ASSERT(usart != RT_NULL); + + switch (cmd) + { + case RT_DEVICE_CTRL_CLR_INT: + NVIC_DisableIRQ(usart->irq); + USART_IntConfig(usart->usart_x, USART_INT_RXDR, DISABLE); + break; + case RT_DEVICE_CTRL_SET_INT: + NVIC_EnableIRQ(usart->irq); + USART_IntConfig(usart->usart_x, USART_INT_RXDR, ENABLE); + break; + } + return RT_EOK; +} + +static int ht32_putc(struct rt_serial_device *serial, char c) +{ + struct ht32_usart *usart; + + RT_ASSERT(serial != RT_NULL); + usart = (struct ht32_usart *) serial->parent.user_data; + RT_ASSERT(usart != RT_NULL); + + while ((usart->usart_x->SR & USART_FLAG_TXC) == 0); + usart->usart_x->DR = (u8)c; + + return 1; +} + +static int ht32_getc(struct rt_serial_device *serial) +{ + int ch; + struct ht32_usart *usart; + + RT_ASSERT(serial != RT_NULL); + usart = (struct ht32_usart *) serial->parent.user_data; + RT_ASSERT(usart != RT_NULL); + + ch = -1; + if (USART_GetFlagStatus(usart->usart_x, USART_FLAG_RXDR) != RESET) + { + ch = USART_ReceiveData(usart->usart_x); + } + return ch; +} + +static rt_ssize_t ht32_dma_transmit(struct rt_serial_device *serial, rt_uint8_t *buf, rt_size_t size, int direction) +{ + return RT_ERROR; +} + +static const struct rt_uart_ops ht32_usart_ops = +{ + .configure = ht32_configure, + .control = ht32_control, + .putc = ht32_putc, + .getc = ht32_getc, + .dma_transmit = ht32_dma_transmit, +}; + +int rt_hw_usart_init(void) +{ + rt_size_t obj_num; + int index; + + obj_num = sizeof(usart_config) / sizeof(struct ht32_usart); + struct serial_configure config = RT_SERIAL_CONFIG_DEFAULT; + rt_err_t result = 0; + + for (index = 0; index < obj_num; index++) + { + usart_config[index].serial.ops = &ht32_usart_ops; + usart_config[index].serial.config = config; + + /* register uart device */ + result = rt_hw_serial_register(&usart_config[index].serial, + usart_config[index].name, + RT_DEVICE_FLAG_RDWR | + RT_DEVICE_FLAG_INT_RX | + RT_DEVICE_FLAG_INT_TX, + &usart_config[index]); + RT_ASSERT(result == RT_EOK); + } + + return result; +} +INIT_BOARD_EXPORT(rt_hw_usart_init); + +static void usart_isr(struct rt_serial_device *serial) +{ + + struct ht32_usart *usart = (struct ht32_usart *)serial->parent.user_data; + RT_ASSERT(usart != RT_NULL); + + if ((USART_GetFlagStatus(usart->usart_x, USART_FLAG_RXDR) != RESET) && ((usart->usart_x->IER & USART_INT_RXDR) != RESET)) + { + rt_hw_serial_isr(serial, RT_SERIAL_EVENT_RX_IND); + } +} + +#ifdef BSP_USING_USART0 +void USART0_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + usart_isr(&usart_config[USART0_INDEX].serial); + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif +#ifdef BSP_USING_USART1 +void USART1_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + usart_isr(&usart_config[USART1_INDEX].serial); + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif +#ifdef BSP_USING_UART0 +void UART0_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + usart_isr(&usart_config[UART0_INDEX].serial); + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif +#ifdef BSP_USING_UART1 +void UART1_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + usart_isr(&usart_config[UART1_INDEX].serial); + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif +#ifdef BSP_USING_UART2 +void UART2_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + usart_isr(&usart_config[UART2_INDEX].serial); + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif +#ifdef BSP_USING_UART3 +void UART3_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + usart_isr(&usart_config[UART3_INDEX].serial); + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif + +#endif /* RT_USING_SERIAL */ diff --git a/bsp/ht32/libraries/ht32_drivers/drv_usart.h b/bsp/ht32/libraries/ht32_drivers/drv_usart.h new file mode 100644 index 0000000000..19fdaf68df --- /dev/null +++ b/bsp/ht32/libraries/ht32_drivers/drv_usart.h @@ -0,0 +1,26 @@ +/* + * Copyright (c) 2006-2024, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2024-04-08 QT-one first version + */ + +#ifndef __DRV_UART_H__ +#define __DRV_UART_H__ + +#include +#include +#include "drv_common.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#ifdef __cplusplus +} +#endif + +#endif /* __DRV_USART_H__ */ diff --git a/bsp/ht32/tools/sdk_dist.py b/bsp/ht32/tools/sdk_dist.py new file mode 100644 index 0000000000..2383b82a90 --- /dev/null +++ b/bsp/ht32/tools/sdk_dist.py @@ -0,0 +1,40 @@ +import os +import sys +import shutil +cwd_path = os.getcwd() +sys.path.append(os.path.join(os.path.dirname(cwd_path), 'rt-thread', 'tools')) + +def bsp_update_kconfig_library(dist_dir): + # change RTT_ROOT in Kconfig + if not os.path.isfile(os.path.join(dist_dir, 'Kconfig')): + return + + with open(os.path.join(dist_dir, 'Kconfig'), 'r') as f: + data = f.readlines() + with open(os.path.join(dist_dir, 'Kconfig'), 'w') as f: + found = 0 + for line in data: + if line.find('RTT_ROOT') != -1: + found = 1 + if line.find('../libraries') != -1 and found: + position = line.find('../libraries') + line = line[0:position] + 'libraries/Kconfig"\n' + found = 0 + f.write(line) + +# BSP dist function +def dist_do_building(BSP_ROOT, dist_dir): + from mkdist import bsp_copy_files + import rtconfig + + print("=> copy ht32 bsp library") + library_dir = os.path.join(dist_dir, 'libraries') + library_path = os.path.join(os.path.dirname(BSP_ROOT), 'libraries') + bsp_copy_files(os.path.join(library_path, rtconfig.BSP_LIBRARY_TYPE), + os.path.join(library_dir, rtconfig.BSP_LIBRARY_TYPE)) + + print("=> copy bsp drivers") + bsp_copy_files(os.path.join(library_path, 'ht32_drivers'), os.path.join(library_dir, 'ht32_drivers')) + shutil.copyfile(os.path.join(library_path, 'Kconfig'), os.path.join(library_dir, 'Kconfig')) + bsp_update_kconfig_library(dist_dir) +